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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_context *rctx,
64 struct r600_pipe_shader *pipeshader,
65 union r600_shader_key key);
66
67
68 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
69 int size, unsigned comp_mask) {
70
71 if (!size)
72 return;
73
74 if (ps->num_arrays == ps->max_arrays) {
75 ps->max_arrays += 64;
76 ps->arrays = realloc(ps->arrays, ps->max_arrays *
77 sizeof(struct r600_shader_array));
78 }
79
80 int n = ps->num_arrays;
81 ++ps->num_arrays;
82
83 ps->arrays[n].comp_mask = comp_mask;
84 ps->arrays[n].gpr_start = start_gpr;
85 ps->arrays[n].gpr_count = size;
86 }
87
88 static void r600_dump_streamout(struct pipe_stream_output_info *so)
89 {
90 unsigned i;
91
92 fprintf(stderr, "STREAMOUT\n");
93 for (i = 0; i < so->num_outputs; i++) {
94 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
95 so->output[i].start_component;
96 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
97 i, so->output[i].output_buffer,
98 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
99 so->output[i].register_index,
100 mask & 1 ? "x" : "",
101 mask & 2 ? "y" : "",
102 mask & 4 ? "z" : "",
103 mask & 8 ? "w" : "",
104 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
105 }
106 }
107
108 static int store_shader(struct pipe_context *ctx,
109 struct r600_pipe_shader *shader)
110 {
111 struct r600_context *rctx = (struct r600_context *)ctx;
112 uint32_t *ptr, i;
113
114 if (shader->bo == NULL) {
115 shader->bo = (struct r600_resource*)
116 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
117 if (shader->bo == NULL) {
118 return -ENOMEM;
119 }
120 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
121 if (R600_BIG_ENDIAN) {
122 for (i = 0; i < shader->shader.bc.ndw; ++i) {
123 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
124 }
125 } else {
126 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
127 }
128 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
129 }
130
131 return 0;
132 }
133
134 int r600_pipe_shader_create(struct pipe_context *ctx,
135 struct r600_pipe_shader *shader,
136 union r600_shader_key key)
137 {
138 struct r600_context *rctx = (struct r600_context *)ctx;
139 struct r600_pipe_shader_selector *sel = shader->selector;
140 int r;
141 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
142 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
143 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
144 unsigned export_shader = key.vs.as_es;
145
146 shader->shader.bc.isa = rctx->isa;
147
148 if (dump) {
149 fprintf(stderr, "--------------------------------------------------------------\n");
150 tgsi_dump(sel->tokens, 0);
151
152 if (sel->so.num_outputs) {
153 r600_dump_streamout(&sel->so);
154 }
155 }
156 r = r600_shader_from_tgsi(rctx, shader, key);
157 if (r) {
158 R600_ERR("translation from TGSI failed !\n");
159 goto error;
160 }
161
162 /* disable SB for geom shaders on R6xx/R7xx due to some mysterious gs piglit regressions with it enabled. */
163 if (rctx->b.chip_class <= R700) {
164 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_GEOMETRY);
165 }
166 /* disable SB for shaders using CF_INDEX_0/1 (sampler/ubo array indexing) as it doesn't handle those currently */
167 use_sb &= !shader->shader.uses_index_registers;
168
169 /* Check if the bytecode has already been built. When using the llvm
170 * backend, r600_shader_from_tgsi() will take care of building the
171 * bytecode.
172 */
173 if (!shader->shader.bc.bytecode) {
174 r = r600_bytecode_build(&shader->shader.bc);
175 if (r) {
176 R600_ERR("building bytecode failed !\n");
177 goto error;
178 }
179 }
180
181 if (dump && !sb_disasm) {
182 fprintf(stderr, "--------------------------------------------------------------\n");
183 r600_bytecode_disasm(&shader->shader.bc);
184 fprintf(stderr, "______________________________________________________________\n");
185 } else if ((dump && sb_disasm) || use_sb) {
186 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
187 dump, use_sb);
188 if (r) {
189 R600_ERR("r600_sb_bytecode_process failed !\n");
190 goto error;
191 }
192 }
193
194 if (shader->gs_copy_shader) {
195 if (dump) {
196 // dump copy shader
197 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
198 &shader->gs_copy_shader->shader, dump, 0);
199 if (r)
200 goto error;
201 }
202
203 if ((r = store_shader(ctx, shader->gs_copy_shader)))
204 goto error;
205 }
206
207 /* Store the shader in a buffer. */
208 if ((r = store_shader(ctx, shader)))
209 goto error;
210
211 /* Build state. */
212 switch (shader->shader.processor_type) {
213 case TGSI_PROCESSOR_GEOMETRY:
214 if (rctx->b.chip_class >= EVERGREEN) {
215 evergreen_update_gs_state(ctx, shader);
216 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
217 } else {
218 r600_update_gs_state(ctx, shader);
219 r600_update_vs_state(ctx, shader->gs_copy_shader);
220 }
221 break;
222 case TGSI_PROCESSOR_VERTEX:
223 if (rctx->b.chip_class >= EVERGREEN) {
224 if (export_shader)
225 evergreen_update_es_state(ctx, shader);
226 else
227 evergreen_update_vs_state(ctx, shader);
228 } else {
229 if (export_shader)
230 r600_update_es_state(ctx, shader);
231 else
232 r600_update_vs_state(ctx, shader);
233 }
234 break;
235 case TGSI_PROCESSOR_FRAGMENT:
236 if (rctx->b.chip_class >= EVERGREEN) {
237 evergreen_update_ps_state(ctx, shader);
238 } else {
239 r600_update_ps_state(ctx, shader);
240 }
241 break;
242 default:
243 r = -EINVAL;
244 goto error;
245 }
246 return 0;
247
248 error:
249 r600_pipe_shader_destroy(ctx, shader);
250 return r;
251 }
252
253 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
254 {
255 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
256 r600_bytecode_clear(&shader->shader.bc);
257 r600_release_command_buffer(&shader->command_buffer);
258 }
259
260 /*
261 * tgsi -> r600 shader
262 */
263 struct r600_shader_tgsi_instruction;
264
265 struct r600_shader_src {
266 unsigned sel;
267 unsigned swizzle[4];
268 unsigned neg;
269 unsigned abs;
270 unsigned rel;
271 unsigned kc_bank;
272 boolean kc_rel; /* true if cache bank is indexed */
273 uint32_t value[4];
274 };
275
276 struct eg_interp {
277 boolean enabled;
278 unsigned ij_index;
279 };
280
281 struct r600_shader_ctx {
282 struct tgsi_shader_info info;
283 struct tgsi_parse_context parse;
284 const struct tgsi_token *tokens;
285 unsigned type;
286 unsigned file_offset[TGSI_FILE_COUNT];
287 unsigned temp_reg;
288 const struct r600_shader_tgsi_instruction *inst_info;
289 struct r600_bytecode *bc;
290 struct r600_shader *shader;
291 struct r600_shader_src src[4];
292 uint32_t *literals;
293 uint32_t nliterals;
294 uint32_t max_driver_temp_used;
295 boolean use_llvm;
296 /* needed for evergreen interpolation */
297 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
298 /* evergreen/cayman also store sample mask in face register */
299 int face_gpr;
300 /* sample id is .w component stored in fixed point position register */
301 int fixed_pt_position_gpr;
302 int colors_used;
303 boolean clip_vertex_write;
304 unsigned cv_output;
305 unsigned edgeflag_output;
306 int fragcoord_input;
307 int native_integers;
308 int next_ring_offset;
309 int gs_out_ring_offset;
310 int gs_next_vertex;
311 struct r600_shader *gs_for_vs;
312 int gs_export_gpr_treg;
313 unsigned enabled_stream_buffers_mask;
314 };
315
316 struct r600_shader_tgsi_instruction {
317 unsigned op;
318 int (*process)(struct r600_shader_ctx *ctx);
319 };
320
321 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, bool ind);
322 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
323 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
324 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
325 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
326 static int tgsi_else(struct r600_shader_ctx *ctx);
327 static int tgsi_endif(struct r600_shader_ctx *ctx);
328 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
329 static int tgsi_endloop(struct r600_shader_ctx *ctx);
330 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
331 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
332 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
333 unsigned int dst_reg);
334 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
335 const struct r600_shader_src *shader_src,
336 unsigned chan);
337
338 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
339 {
340 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
341 int j;
342
343 if (i->Instruction.NumDstRegs > 1) {
344 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
345 return -EINVAL;
346 }
347 if (i->Instruction.Predicate) {
348 R600_ERR("predicate unsupported\n");
349 return -EINVAL;
350 }
351 #if 0
352 if (i->Instruction.Label) {
353 R600_ERR("label unsupported\n");
354 return -EINVAL;
355 }
356 #endif
357 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
358 if (i->Src[j].Register.Dimension) {
359 switch (i->Src[j].Register.File) {
360 case TGSI_FILE_CONSTANT:
361 break;
362 case TGSI_FILE_INPUT:
363 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
364 break;
365 default:
366 R600_ERR("unsupported src %d (dimension %d)\n", j,
367 i->Src[j].Register.Dimension);
368 return -EINVAL;
369 }
370 }
371 }
372 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
373 if (i->Dst[j].Register.Dimension) {
374 R600_ERR("unsupported dst (dimension)\n");
375 return -EINVAL;
376 }
377 }
378 return 0;
379 }
380
381 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
382 {
383 if (interpolate == TGSI_INTERPOLATE_COLOR ||
384 interpolate == TGSI_INTERPOLATE_LINEAR ||
385 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
386 {
387 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
388 int loc;
389
390 switch(location) {
391 case TGSI_INTERPOLATE_LOC_CENTER:
392 loc = 1;
393 break;
394 case TGSI_INTERPOLATE_LOC_CENTROID:
395 loc = 2;
396 break;
397 case TGSI_INTERPOLATE_LOC_SAMPLE:
398 default:
399 loc = 0; break;
400 }
401
402 return is_linear * 3 + loc;
403 }
404
405 return -1;
406 }
407
408 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
409 int input)
410 {
411 int i = eg_get_interpolator_index(
412 ctx->shader->input[input].interpolate,
413 ctx->shader->input[input].interpolate_location);
414 assert(i >= 0);
415 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
416 }
417
418 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
419 {
420 int i, r;
421 struct r600_bytecode_alu alu;
422 int gpr = 0, base_chan = 0;
423 int ij_index = ctx->shader->input[input].ij_index;
424
425 /* work out gpr and base_chan from index */
426 gpr = ij_index / 2;
427 base_chan = (2 * (ij_index % 2)) + 1;
428
429 for (i = 0; i < 8; i++) {
430 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
431
432 if (i < 4)
433 alu.op = ALU_OP2_INTERP_ZW;
434 else
435 alu.op = ALU_OP2_INTERP_XY;
436
437 if ((i > 1) && (i < 6)) {
438 alu.dst.sel = ctx->shader->input[input].gpr;
439 alu.dst.write = 1;
440 }
441
442 alu.dst.chan = i % 4;
443
444 alu.src[0].sel = gpr;
445 alu.src[0].chan = (base_chan - (i % 2));
446
447 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
448
449 alu.bank_swizzle_force = SQ_ALU_VEC_210;
450 if ((i % 4) == 3)
451 alu.last = 1;
452 r = r600_bytecode_add_alu(ctx->bc, &alu);
453 if (r)
454 return r;
455 }
456 return 0;
457 }
458
459 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
460 {
461 int i, r;
462 struct r600_bytecode_alu alu;
463
464 for (i = 0; i < 4; i++) {
465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
466
467 alu.op = ALU_OP1_INTERP_LOAD_P0;
468
469 alu.dst.sel = ctx->shader->input[input].gpr;
470 alu.dst.write = 1;
471
472 alu.dst.chan = i;
473
474 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
475 alu.src[0].chan = i;
476
477 if (i == 3)
478 alu.last = 1;
479 r = r600_bytecode_add_alu(ctx->bc, &alu);
480 if (r)
481 return r;
482 }
483 return 0;
484 }
485
486 /*
487 * Special export handling in shaders
488 *
489 * shader export ARRAY_BASE for EXPORT_POS:
490 * 60 is position
491 * 61 is misc vector
492 * 62, 63 are clip distance vectors
493 *
494 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
495 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
496 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
497 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
498 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
499 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
500 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
501 * exclusive from render target index)
502 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
503 *
504 *
505 * shader export ARRAY_BASE for EXPORT_PIXEL:
506 * 0-7 CB targets
507 * 61 computed Z vector
508 *
509 * The use of the values exported in the computed Z vector are controlled
510 * by DB_SHADER_CONTROL:
511 * Z_EXPORT_ENABLE - Z as a float in RED
512 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
513 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
514 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
515 * DB_SOURCE_FORMAT - export control restrictions
516 *
517 */
518
519
520 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
521 static int r600_spi_sid(struct r600_shader_io * io)
522 {
523 int index, name = io->name;
524
525 /* These params are handled differently, they don't need
526 * semantic indices, so we'll use 0 for them.
527 */
528 if (name == TGSI_SEMANTIC_POSITION ||
529 name == TGSI_SEMANTIC_PSIZE ||
530 name == TGSI_SEMANTIC_EDGEFLAG ||
531 name == TGSI_SEMANTIC_FACE ||
532 name == TGSI_SEMANTIC_SAMPLEMASK)
533 index = 0;
534 else {
535 if (name == TGSI_SEMANTIC_GENERIC) {
536 /* For generic params simply use sid from tgsi */
537 index = io->sid;
538 } else {
539 /* For non-generic params - pack name and sid into 8 bits */
540 index = 0x80 | (name<<3) | (io->sid);
541 }
542
543 /* Make sure that all really used indices have nonzero value, so
544 * we can just compare it to 0 later instead of comparing the name
545 * with different values to detect special cases. */
546 index++;
547 }
548
549 return index;
550 };
551
552 /* turn input into interpolate on EG */
553 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
554 {
555 int r = 0;
556
557 if (ctx->shader->input[index].spi_sid) {
558 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
559 if (ctx->shader->input[index].interpolate > 0) {
560 evergreen_interp_assign_ij_index(ctx, index);
561 if (!ctx->use_llvm)
562 r = evergreen_interp_alu(ctx, index);
563 } else {
564 if (!ctx->use_llvm)
565 r = evergreen_interp_flat(ctx, index);
566 }
567 }
568 return r;
569 }
570
571 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
572 {
573 struct r600_bytecode_alu alu;
574 int i, r;
575 int gpr_front = ctx->shader->input[front].gpr;
576 int gpr_back = ctx->shader->input[back].gpr;
577
578 for (i = 0; i < 4; i++) {
579 memset(&alu, 0, sizeof(alu));
580 alu.op = ALU_OP3_CNDGT;
581 alu.is_op3 = 1;
582 alu.dst.write = 1;
583 alu.dst.sel = gpr_front;
584 alu.src[0].sel = ctx->face_gpr;
585 alu.src[1].sel = gpr_front;
586 alu.src[2].sel = gpr_back;
587
588 alu.dst.chan = i;
589 alu.src[1].chan = i;
590 alu.src[2].chan = i;
591 alu.last = (i==3);
592
593 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
594 return r;
595 }
596
597 return 0;
598 }
599
600 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
601 {
602 int i;
603 i = ctx->shader->noutput++;
604 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
605 ctx->shader->output[i].sid = 0;
606 ctx->shader->output[i].gpr = 0;
607 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
608 ctx->shader->output[i].write_mask = 0x4;
609 ctx->shader->output[i].spi_sid = prim_id_sid;
610
611 return 0;
612 }
613
614 static int tgsi_declaration(struct r600_shader_ctx *ctx)
615 {
616 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
617 int r, i, j, count = d->Range.Last - d->Range.First + 1;
618
619 switch (d->Declaration.File) {
620 case TGSI_FILE_INPUT:
621 for (j = 0; j < count; j++) {
622 i = ctx->shader->ninput + j;
623 assert(i < Elements(ctx->shader->input));
624 ctx->shader->input[i].name = d->Semantic.Name;
625 ctx->shader->input[i].sid = d->Semantic.Index + j;
626 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
627 ctx->shader->input[i].interpolate_location = d->Interp.Location;
628 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
629 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
630 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
631 switch (ctx->shader->input[i].name) {
632 case TGSI_SEMANTIC_FACE:
633 if (ctx->face_gpr != -1)
634 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
635 else
636 ctx->face_gpr = ctx->shader->input[i].gpr;
637 break;
638 case TGSI_SEMANTIC_COLOR:
639 ctx->colors_used++;
640 break;
641 case TGSI_SEMANTIC_POSITION:
642 ctx->fragcoord_input = i;
643 break;
644 case TGSI_SEMANTIC_PRIMID:
645 /* set this for now */
646 ctx->shader->gs_prim_id_input = true;
647 ctx->shader->ps_prim_id_input = i;
648 break;
649 }
650 if (ctx->bc->chip_class >= EVERGREEN) {
651 if ((r = evergreen_interp_input(ctx, i)))
652 return r;
653 }
654 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
655 /* FIXME probably skip inputs if they aren't passed in the ring */
656 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
657 ctx->next_ring_offset += 16;
658 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
659 ctx->shader->gs_prim_id_input = true;
660 }
661 }
662 ctx->shader->ninput += count;
663 break;
664 case TGSI_FILE_OUTPUT:
665 for (j = 0; j < count; j++) {
666 i = ctx->shader->noutput + j;
667 assert(i < Elements(ctx->shader->output));
668 ctx->shader->output[i].name = d->Semantic.Name;
669 ctx->shader->output[i].sid = d->Semantic.Index + j;
670 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
671 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
672 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
673 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
674 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
675 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
676 switch (d->Semantic.Name) {
677 case TGSI_SEMANTIC_CLIPDIST:
678 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
679 ((d->Semantic.Index + j) << 2);
680 break;
681 case TGSI_SEMANTIC_PSIZE:
682 ctx->shader->vs_out_misc_write = 1;
683 ctx->shader->vs_out_point_size = 1;
684 break;
685 case TGSI_SEMANTIC_EDGEFLAG:
686 ctx->shader->vs_out_misc_write = 1;
687 ctx->shader->vs_out_edgeflag = 1;
688 ctx->edgeflag_output = i;
689 break;
690 case TGSI_SEMANTIC_VIEWPORT_INDEX:
691 ctx->shader->vs_out_misc_write = 1;
692 ctx->shader->vs_out_viewport = 1;
693 break;
694 case TGSI_SEMANTIC_LAYER:
695 ctx->shader->vs_out_misc_write = 1;
696 ctx->shader->vs_out_layer = 1;
697 break;
698 case TGSI_SEMANTIC_CLIPVERTEX:
699 ctx->clip_vertex_write = TRUE;
700 ctx->cv_output = i;
701 break;
702 }
703 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
704 ctx->gs_out_ring_offset += 16;
705 }
706 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
707 switch (d->Semantic.Name) {
708 case TGSI_SEMANTIC_COLOR:
709 ctx->shader->nr_ps_max_color_exports++;
710 break;
711 }
712 }
713 }
714 ctx->shader->noutput += count;
715 break;
716 case TGSI_FILE_TEMPORARY:
717 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
718 if (d->Array.ArrayID) {
719 r600_add_gpr_array(ctx->shader,
720 ctx->file_offset[TGSI_FILE_TEMPORARY] +
721 d->Range.First,
722 d->Range.Last - d->Range.First + 1, 0x0F);
723 }
724 }
725 break;
726
727 case TGSI_FILE_CONSTANT:
728 case TGSI_FILE_SAMPLER:
729 case TGSI_FILE_SAMPLER_VIEW:
730 case TGSI_FILE_ADDRESS:
731 break;
732
733 case TGSI_FILE_SYSTEM_VALUE:
734 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
735 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
736 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
737 break; /* Already handled from allocate_system_value_inputs */
738 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
739 if (!ctx->native_integers) {
740 struct r600_bytecode_alu alu;
741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
742
743 alu.op = ALU_OP1_INT_TO_FLT;
744 alu.src[0].sel = 0;
745 alu.src[0].chan = 3;
746
747 alu.dst.sel = 0;
748 alu.dst.chan = 3;
749 alu.dst.write = 1;
750 alu.last = 1;
751
752 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
753 return r;
754 }
755 break;
756 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
757 break;
758 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
759 break;
760 default:
761 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
762 return -EINVAL;
763 }
764 return 0;
765 }
766
767 static int r600_get_temp(struct r600_shader_ctx *ctx)
768 {
769 return ctx->temp_reg + ctx->max_driver_temp_used++;
770 }
771
772 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
773 {
774 struct tgsi_parse_context parse;
775 struct {
776 boolean enabled;
777 int *reg;
778 unsigned name, alternate_name;
779 } inputs[2] = {
780 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
781
782 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
783 };
784 int i, k, num_regs = 0;
785
786 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
787 return 0;
788 }
789
790 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
791 while (!tgsi_parse_end_of_tokens(&parse)) {
792 tgsi_parse_token(&parse);
793
794 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
795 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
796 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
797 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
798 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
799 {
800 int interpolate, location, k;
801
802 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
803 location = TGSI_INTERPOLATE_LOC_CENTER;
804 inputs[1].enabled = true; /* needs SAMPLEID */
805 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
806 location = TGSI_INTERPOLATE_LOC_CENTER;
807 /* Needs sample positions, currently those are always available */
808 } else {
809 location = TGSI_INTERPOLATE_LOC_CENTROID;
810 }
811
812 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
813 k = eg_get_interpolator_index(interpolate, location);
814 ctx->eg_interpolators[k].enabled = true;
815 }
816 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
817 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
818 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
819 for (k = 0; k < Elements(inputs); k++) {
820 if (d->Semantic.Name == inputs[k].name ||
821 d->Semantic.Name == inputs[k].alternate_name) {
822 inputs[k].enabled = true;
823 }
824 }
825 }
826 }
827 }
828
829 tgsi_parse_free(&parse);
830
831 for (i = 0; i < Elements(inputs); i++) {
832 boolean enabled = inputs[i].enabled;
833 int *reg = inputs[i].reg;
834 unsigned name = inputs[i].name;
835
836 if (enabled) {
837 int gpr = gpr_offset + num_regs++;
838
839 // add to inputs, allocate a gpr
840 k = ctx->shader->ninput ++;
841 ctx->shader->input[k].name = name;
842 ctx->shader->input[k].sid = 0;
843 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
844 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
845 *reg = ctx->shader->input[k].gpr = gpr;
846 }
847 }
848
849 return gpr_offset + num_regs;
850 }
851
852 /*
853 * for evergreen we need to scan the shader to find the number of GPRs we need to
854 * reserve for interpolation and system values
855 *
856 * we need to know if we are going to emit
857 * any sample or centroid inputs
858 * if perspective and linear are required
859 */
860 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
861 {
862 int i;
863 int num_baryc;
864 struct tgsi_parse_context parse;
865
866 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
867
868 for (i = 0; i < ctx->info.num_inputs; i++) {
869 int k;
870 /* skip position/face/mask/sampleid */
871 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
872 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
873 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
874 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
875 continue;
876
877 k = eg_get_interpolator_index(
878 ctx->info.input_interpolate[i],
879 ctx->info.input_interpolate_loc[i]);
880 if (k >= 0)
881 ctx->eg_interpolators[k].enabled = TRUE;
882 }
883
884 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
885 return 0;
886 }
887
888 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
889 while (!tgsi_parse_end_of_tokens(&parse)) {
890 tgsi_parse_token(&parse);
891
892 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
893 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
894 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
895 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
896 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
897 {
898 int interpolate, location, k;
899
900 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
901 location = TGSI_INTERPOLATE_LOC_CENTER;
902 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
903 location = TGSI_INTERPOLATE_LOC_CENTER;
904 } else {
905 location = TGSI_INTERPOLATE_LOC_CENTROID;
906 }
907
908 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
909 k = eg_get_interpolator_index(interpolate, location);
910 ctx->eg_interpolators[k].enabled = true;
911 }
912 }
913 }
914
915 tgsi_parse_free(&parse);
916
917 /* assign gpr to each interpolator according to priority */
918 num_baryc = 0;
919 for (i = 0; i < Elements(ctx->eg_interpolators); i++) {
920 if (ctx->eg_interpolators[i].enabled) {
921 ctx->eg_interpolators[i].ij_index = num_baryc;
922 num_baryc ++;
923 }
924 }
925
926 /* XXX PULL MODEL and LINE STIPPLE */
927
928 num_baryc = (num_baryc + 1) >> 1;
929 return allocate_system_value_inputs(ctx, num_baryc);
930 }
931
932 /* sample_id_sel == NULL means fetch for current sample */
933 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
934 {
935 struct r600_bytecode_vtx vtx;
936 int r, t1;
937
938 assert(ctx->fixed_pt_position_gpr != -1);
939
940 t1 = r600_get_temp(ctx);
941
942 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
943 vtx.op = FETCH_OP_VFETCH;
944 vtx.buffer_id = R600_SAMPLE_POSITIONS_CONST_BUFFER;
945 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
946 if (sample_id == NULL) {
947 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
948 vtx.src_sel_x = 3;
949 }
950 else {
951 struct r600_bytecode_alu alu;
952
953 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
954 alu.op = ALU_OP1_MOV;
955 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
956 alu.dst.sel = t1;
957 alu.dst.write = 1;
958 alu.last = 1;
959 r = r600_bytecode_add_alu(ctx->bc, &alu);
960 if (r)
961 return r;
962
963 vtx.src_gpr = t1;
964 vtx.src_sel_x = 0;
965 }
966 vtx.mega_fetch_count = 16;
967 vtx.dst_gpr = t1;
968 vtx.dst_sel_x = 0;
969 vtx.dst_sel_y = 1;
970 vtx.dst_sel_z = 2;
971 vtx.dst_sel_w = 3;
972 vtx.data_format = FMT_32_32_32_32_FLOAT;
973 vtx.num_format_all = 2;
974 vtx.format_comp_all = 1;
975 vtx.use_const_fields = 0;
976 vtx.offset = 1; // first element is size of buffer
977 vtx.endian = r600_endian_swap(32);
978 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
979
980 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
981 if (r)
982 return r;
983
984 return t1;
985 }
986
987 static void tgsi_src(struct r600_shader_ctx *ctx,
988 const struct tgsi_full_src_register *tgsi_src,
989 struct r600_shader_src *r600_src)
990 {
991 memset(r600_src, 0, sizeof(*r600_src));
992 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
993 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
994 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
995 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
996 r600_src->neg = tgsi_src->Register.Negate;
997 r600_src->abs = tgsi_src->Register.Absolute;
998
999 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1000 int index;
1001 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1002 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1003 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1004
1005 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1006 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
1007 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1008 return;
1009 }
1010 index = tgsi_src->Register.Index;
1011 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1012 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1013 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1014 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1015 r600_src->swizzle[0] = 2; // Z value
1016 r600_src->swizzle[1] = 2;
1017 r600_src->swizzle[2] = 2;
1018 r600_src->swizzle[3] = 2;
1019 r600_src->sel = ctx->face_gpr;
1020 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1021 r600_src->swizzle[0] = 3; // W value
1022 r600_src->swizzle[1] = 3;
1023 r600_src->swizzle[2] = 3;
1024 r600_src->swizzle[3] = 3;
1025 r600_src->sel = ctx->fixed_pt_position_gpr;
1026 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1027 r600_src->swizzle[0] = 0;
1028 r600_src->swizzle[1] = 1;
1029 r600_src->swizzle[2] = 4;
1030 r600_src->swizzle[3] = 4;
1031 r600_src->sel = load_sample_position(ctx, NULL, -1);
1032 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1033 r600_src->swizzle[0] = 3;
1034 r600_src->swizzle[1] = 3;
1035 r600_src->swizzle[2] = 3;
1036 r600_src->swizzle[3] = 3;
1037 r600_src->sel = 0;
1038 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1039 r600_src->swizzle[0] = 0;
1040 r600_src->swizzle[1] = 0;
1041 r600_src->swizzle[2] = 0;
1042 r600_src->swizzle[3] = 0;
1043 r600_src->sel = 0;
1044 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1045 r600_src->swizzle[0] = 3;
1046 r600_src->swizzle[1] = 3;
1047 r600_src->swizzle[2] = 3;
1048 r600_src->swizzle[3] = 3;
1049 r600_src->sel = 1;
1050 }
1051 } else {
1052 if (tgsi_src->Register.Indirect)
1053 r600_src->rel = V_SQ_REL_RELATIVE;
1054 r600_src->sel = tgsi_src->Register.Index;
1055 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1056 }
1057 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1058 if (tgsi_src->Register.Dimension) {
1059 r600_src->kc_bank = tgsi_src->Dimension.Index;
1060 if (tgsi_src->Dimension.Indirect) {
1061 r600_src->kc_rel = 1;
1062 }
1063 }
1064 }
1065 }
1066
1067 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1068 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1069 unsigned int dst_reg)
1070 {
1071 struct r600_bytecode_vtx vtx;
1072 unsigned int ar_reg;
1073 int r;
1074
1075 if (offset) {
1076 struct r600_bytecode_alu alu;
1077
1078 memset(&alu, 0, sizeof(alu));
1079
1080 alu.op = ALU_OP2_ADD_INT;
1081 alu.src[0].sel = ctx->bc->ar_reg;
1082 alu.src[0].chan = ar_chan;
1083
1084 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1085 alu.src[1].value = offset;
1086
1087 alu.dst.sel = dst_reg;
1088 alu.dst.chan = ar_chan;
1089 alu.dst.write = 1;
1090 alu.last = 1;
1091
1092 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1093 return r;
1094
1095 ar_reg = dst_reg;
1096 } else {
1097 ar_reg = ctx->bc->ar_reg;
1098 }
1099
1100 memset(&vtx, 0, sizeof(vtx));
1101 vtx.buffer_id = cb_idx;
1102 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1103 vtx.src_gpr = ar_reg;
1104 vtx.src_sel_x = ar_chan;
1105 vtx.mega_fetch_count = 16;
1106 vtx.dst_gpr = dst_reg;
1107 vtx.dst_sel_x = 0; /* SEL_X */
1108 vtx.dst_sel_y = 1; /* SEL_Y */
1109 vtx.dst_sel_z = 2; /* SEL_Z */
1110 vtx.dst_sel_w = 3; /* SEL_W */
1111 vtx.data_format = FMT_32_32_32_32_FLOAT;
1112 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1113 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1114 vtx.endian = r600_endian_swap(32);
1115 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1116
1117 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1118 return r;
1119
1120 return 0;
1121 }
1122
1123 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1124 {
1125 struct r600_bytecode_vtx vtx;
1126 int r;
1127 unsigned index = src->Register.Index;
1128 unsigned vtx_id = src->Dimension.Index;
1129 int offset_reg = vtx_id / 3;
1130 int offset_chan = vtx_id % 3;
1131
1132 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1133 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1134
1135 if (offset_reg == 0 && offset_chan == 2)
1136 offset_chan = 3;
1137
1138 if (src->Dimension.Indirect) {
1139 int treg[3];
1140 int t2;
1141 struct r600_bytecode_alu alu;
1142 int r, i;
1143
1144 /* you have got to be shitting me -
1145 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1146 at least this is what fglrx seems to do. */
1147 for (i = 0; i < 3; i++) {
1148 treg[i] = r600_get_temp(ctx);
1149 }
1150 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1151
1152 t2 = r600_get_temp(ctx);
1153 for (i = 0; i < 3; i++) {
1154 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1155 alu.op = ALU_OP1_MOV;
1156 alu.src[0].sel = 0;
1157 alu.src[0].chan = i == 2 ? 3 : i;
1158 alu.dst.sel = treg[i];
1159 alu.dst.chan = 0;
1160 alu.dst.write = 1;
1161 alu.last = 1;
1162 r = r600_bytecode_add_alu(ctx->bc, &alu);
1163 if (r)
1164 return r;
1165 }
1166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1167 alu.op = ALU_OP1_MOV;
1168 alu.src[0].sel = treg[0];
1169 alu.src[0].rel = 1;
1170 alu.dst.sel = t2;
1171 alu.dst.write = 1;
1172 alu.last = 1;
1173 r = r600_bytecode_add_alu(ctx->bc, &alu);
1174 if (r)
1175 return r;
1176 offset_reg = t2;
1177 }
1178
1179
1180 memset(&vtx, 0, sizeof(vtx));
1181 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1182 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1183 vtx.src_gpr = offset_reg;
1184 vtx.src_sel_x = offset_chan;
1185 vtx.offset = index * 16; /*bytes*/
1186 vtx.mega_fetch_count = 16;
1187 vtx.dst_gpr = dst_reg;
1188 vtx.dst_sel_x = 0; /* SEL_X */
1189 vtx.dst_sel_y = 1; /* SEL_Y */
1190 vtx.dst_sel_z = 2; /* SEL_Z */
1191 vtx.dst_sel_w = 3; /* SEL_W */
1192 if (ctx->bc->chip_class >= EVERGREEN) {
1193 vtx.use_const_fields = 1;
1194 } else {
1195 vtx.data_format = FMT_32_32_32_32_FLOAT;
1196 }
1197
1198 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1199 return r;
1200
1201 return 0;
1202 }
1203
1204 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1205 {
1206 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1207 int i;
1208
1209 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1210 struct tgsi_full_src_register *src = &inst->Src[i];
1211
1212 if (src->Register.File == TGSI_FILE_INPUT) {
1213 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1214 /* primitive id is in R0.z */
1215 ctx->src[i].sel = 0;
1216 ctx->src[i].swizzle[0] = 2;
1217 }
1218 }
1219 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1220 int treg = r600_get_temp(ctx);
1221
1222 fetch_gs_input(ctx, src, treg);
1223 ctx->src[i].sel = treg;
1224 }
1225 }
1226 return 0;
1227 }
1228
1229 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1230 {
1231 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1232 struct r600_bytecode_alu alu;
1233 int i, j, k, nconst, r;
1234
1235 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1236 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1237 nconst++;
1238 }
1239 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1240 }
1241 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1242 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1243 continue;
1244 }
1245
1246 if (ctx->src[i].kc_rel)
1247 ctx->shader->uses_index_registers = true;
1248
1249 if (ctx->src[i].rel) {
1250 int chan = inst->Src[i].Indirect.Swizzle;
1251 int treg = r600_get_temp(ctx);
1252 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1253 return r;
1254
1255 ctx->src[i].kc_bank = 0;
1256 ctx->src[i].kc_rel = 0;
1257 ctx->src[i].sel = treg;
1258 ctx->src[i].rel = 0;
1259 j--;
1260 } else if (j > 0) {
1261 int treg = r600_get_temp(ctx);
1262 for (k = 0; k < 4; k++) {
1263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1264 alu.op = ALU_OP1_MOV;
1265 alu.src[0].sel = ctx->src[i].sel;
1266 alu.src[0].chan = k;
1267 alu.src[0].rel = ctx->src[i].rel;
1268 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1269 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1270 alu.dst.sel = treg;
1271 alu.dst.chan = k;
1272 alu.dst.write = 1;
1273 if (k == 3)
1274 alu.last = 1;
1275 r = r600_bytecode_add_alu(ctx->bc, &alu);
1276 if (r)
1277 return r;
1278 }
1279 ctx->src[i].sel = treg;
1280 ctx->src[i].rel =0;
1281 j--;
1282 }
1283 }
1284 return 0;
1285 }
1286
1287 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1288 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1289 {
1290 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1291 struct r600_bytecode_alu alu;
1292 int i, j, k, nliteral, r;
1293
1294 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1295 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1296 nliteral++;
1297 }
1298 }
1299 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1300 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1301 int treg = r600_get_temp(ctx);
1302 for (k = 0; k < 4; k++) {
1303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1304 alu.op = ALU_OP1_MOV;
1305 alu.src[0].sel = ctx->src[i].sel;
1306 alu.src[0].chan = k;
1307 alu.src[0].value = ctx->src[i].value[k];
1308 alu.dst.sel = treg;
1309 alu.dst.chan = k;
1310 alu.dst.write = 1;
1311 if (k == 3)
1312 alu.last = 1;
1313 r = r600_bytecode_add_alu(ctx->bc, &alu);
1314 if (r)
1315 return r;
1316 }
1317 ctx->src[i].sel = treg;
1318 j--;
1319 }
1320 }
1321 return 0;
1322 }
1323
1324 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1325 {
1326 int i, r, count = ctx->shader->ninput;
1327
1328 for (i = 0; i < count; i++) {
1329 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1330 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1331 if (r)
1332 return r;
1333 }
1334 }
1335 return 0;
1336 }
1337
1338 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so)
1339 {
1340 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1341 int i, j, r;
1342
1343 /* Sanity checking. */
1344 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1345 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1346 r = -EINVAL;
1347 goto out_err;
1348 }
1349 for (i = 0; i < so->num_outputs; i++) {
1350 if (so->output[i].output_buffer >= 4) {
1351 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1352 so->output[i].output_buffer);
1353 r = -EINVAL;
1354 goto out_err;
1355 }
1356 }
1357
1358 /* Initialize locations where the outputs are stored. */
1359 for (i = 0; i < so->num_outputs; i++) {
1360 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1361
1362 /* Lower outputs with dst_offset < start_component.
1363 *
1364 * We can only output 4D vectors with a write mask, e.g. we can
1365 * only output the W component at offset 3, etc. If we want
1366 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1367 * to move it to X and output X. */
1368 if (so->output[i].dst_offset < so->output[i].start_component) {
1369 unsigned tmp = r600_get_temp(ctx);
1370
1371 for (j = 0; j < so->output[i].num_components; j++) {
1372 struct r600_bytecode_alu alu;
1373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1374 alu.op = ALU_OP1_MOV;
1375 alu.src[0].sel = so_gpr[i];
1376 alu.src[0].chan = so->output[i].start_component + j;
1377
1378 alu.dst.sel = tmp;
1379 alu.dst.chan = j;
1380 alu.dst.write = 1;
1381 if (j == so->output[i].num_components - 1)
1382 alu.last = 1;
1383 r = r600_bytecode_add_alu(ctx->bc, &alu);
1384 if (r)
1385 return r;
1386 }
1387 so->output[i].start_component = 0;
1388 so_gpr[i] = tmp;
1389 }
1390 }
1391
1392 /* Write outputs to buffers. */
1393 for (i = 0; i < so->num_outputs; i++) {
1394 struct r600_bytecode_output output;
1395
1396 memset(&output, 0, sizeof(struct r600_bytecode_output));
1397 output.gpr = so_gpr[i];
1398 output.elem_size = so->output[i].num_components;
1399 output.array_base = so->output[i].dst_offset - so->output[i].start_component;
1400 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1401 output.burst_count = 1;
1402 /* array_size is an upper limit for the burst_count
1403 * with MEM_STREAM instructions */
1404 output.array_size = 0xFFF;
1405 output.comp_mask = ((1 << so->output[i].num_components) - 1) << so->output[i].start_component;
1406
1407 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer);
1408
1409 if (ctx->bc->chip_class >= EVERGREEN) {
1410 switch (so->output[i].output_buffer) {
1411 case 0:
1412 output.op = CF_OP_MEM_STREAM0_BUF0;
1413 break;
1414 case 1:
1415 output.op = CF_OP_MEM_STREAM0_BUF1;
1416 break;
1417 case 2:
1418 output.op = CF_OP_MEM_STREAM0_BUF2;
1419 break;
1420 case 3:
1421 output.op = CF_OP_MEM_STREAM0_BUF3;
1422 break;
1423 }
1424 } else {
1425 switch (so->output[i].output_buffer) {
1426 case 0:
1427 output.op = CF_OP_MEM_STREAM0;
1428 break;
1429 case 1:
1430 output.op = CF_OP_MEM_STREAM1;
1431 break;
1432 case 2:
1433 output.op = CF_OP_MEM_STREAM2;
1434 break;
1435 case 3:
1436 output.op = CF_OP_MEM_STREAM3;
1437 break;
1438 }
1439 }
1440 r = r600_bytecode_add_output(ctx->bc, &output);
1441 if (r)
1442 goto out_err;
1443 }
1444 return 0;
1445 out_err:
1446 return r;
1447 }
1448
1449 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
1450 {
1451 struct r600_bytecode_alu alu;
1452 unsigned reg;
1453
1454 if (!ctx->shader->vs_out_edgeflag)
1455 return;
1456
1457 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
1458
1459 /* clamp(x, 0, 1) */
1460 memset(&alu, 0, sizeof(alu));
1461 alu.op = ALU_OP1_MOV;
1462 alu.src[0].sel = reg;
1463 alu.dst.sel = reg;
1464 alu.dst.write = 1;
1465 alu.dst.clamp = 1;
1466 alu.last = 1;
1467 r600_bytecode_add_alu(ctx->bc, &alu);
1468
1469 memset(&alu, 0, sizeof(alu));
1470 alu.op = ALU_OP1_FLT_TO_INT;
1471 alu.src[0].sel = reg;
1472 alu.dst.sel = reg;
1473 alu.dst.write = 1;
1474 alu.last = 1;
1475 r600_bytecode_add_alu(ctx->bc, &alu);
1476 }
1477
1478 static int generate_gs_copy_shader(struct r600_context *rctx,
1479 struct r600_pipe_shader *gs,
1480 struct pipe_stream_output_info *so)
1481 {
1482 struct r600_shader_ctx ctx = {};
1483 struct r600_shader *gs_shader = &gs->shader;
1484 struct r600_pipe_shader *cshader;
1485 int ocnt = gs_shader->noutput;
1486 struct r600_bytecode_alu alu;
1487 struct r600_bytecode_vtx vtx;
1488 struct r600_bytecode_output output;
1489 struct r600_bytecode_cf *cf_jump, *cf_pop,
1490 *last_exp_pos = NULL, *last_exp_param = NULL;
1491 int i, next_clip_pos = 61, next_param = 0;
1492
1493 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1494 if (!cshader)
1495 return 0;
1496
1497 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1498 sizeof(struct r600_shader_io));
1499
1500 cshader->shader.noutput = ocnt;
1501
1502 ctx.shader = &cshader->shader;
1503 ctx.bc = &ctx.shader->bc;
1504 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1505
1506 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1507 rctx->screen->has_compressed_msaa_texturing);
1508
1509 ctx.bc->isa = rctx->isa;
1510
1511 /* R0.x = R0.x & 0x3fffffff */
1512 memset(&alu, 0, sizeof(alu));
1513 alu.op = ALU_OP2_AND_INT;
1514 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1515 alu.src[1].value = 0x3fffffff;
1516 alu.dst.write = 1;
1517 r600_bytecode_add_alu(ctx.bc, &alu);
1518
1519 /* R0.y = R0.x >> 30 */
1520 memset(&alu, 0, sizeof(alu));
1521 alu.op = ALU_OP2_LSHR_INT;
1522 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1523 alu.src[1].value = 0x1e;
1524 alu.dst.chan = 1;
1525 alu.dst.write = 1;
1526 alu.last = 1;
1527 r600_bytecode_add_alu(ctx.bc, &alu);
1528
1529 /* PRED_SETE_INT __, R0.y, 0 */
1530 memset(&alu, 0, sizeof(alu));
1531 alu.op = ALU_OP2_PRED_SETE_INT;
1532 alu.src[0].chan = 1;
1533 alu.src[1].sel = V_SQ_ALU_SRC_0;
1534 alu.execute_mask = 1;
1535 alu.update_pred = 1;
1536 alu.last = 1;
1537 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1538
1539 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1540 cf_jump = ctx.bc->cf_last;
1541
1542 /* fetch vertex data from GSVS ring */
1543 for (i = 0; i < ocnt; ++i) {
1544 struct r600_shader_io *out = &ctx.shader->output[i];
1545 out->gpr = i + 1;
1546 out->ring_offset = i * 16;
1547
1548 memset(&vtx, 0, sizeof(vtx));
1549 vtx.op = FETCH_OP_VFETCH;
1550 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1551 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1552 vtx.offset = out->ring_offset;
1553 vtx.dst_gpr = out->gpr;
1554 vtx.dst_sel_x = 0;
1555 vtx.dst_sel_y = 1;
1556 vtx.dst_sel_z = 2;
1557 vtx.dst_sel_w = 3;
1558 if (rctx->b.chip_class >= EVERGREEN) {
1559 vtx.use_const_fields = 1;
1560 } else {
1561 vtx.data_format = FMT_32_32_32_32_FLOAT;
1562 }
1563
1564 r600_bytecode_add_vtx(ctx.bc, &vtx);
1565 }
1566
1567 /* XXX handle clipvertex, streamout? */
1568 emit_streamout(&ctx, so);
1569
1570 /* export vertex data */
1571 /* XXX factor out common code with r600_shader_from_tgsi ? */
1572 for (i = 0; i < ocnt; ++i) {
1573 struct r600_shader_io *out = &ctx.shader->output[i];
1574
1575 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1576 continue;
1577
1578 memset(&output, 0, sizeof(output));
1579 output.gpr = out->gpr;
1580 output.elem_size = 3;
1581 output.swizzle_x = 0;
1582 output.swizzle_y = 1;
1583 output.swizzle_z = 2;
1584 output.swizzle_w = 3;
1585 output.burst_count = 1;
1586 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1587 output.op = CF_OP_EXPORT;
1588 switch (out->name) {
1589 case TGSI_SEMANTIC_POSITION:
1590 output.array_base = 60;
1591 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1592 break;
1593
1594 case TGSI_SEMANTIC_PSIZE:
1595 output.array_base = 61;
1596 if (next_clip_pos == 61)
1597 next_clip_pos = 62;
1598 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1599 output.swizzle_y = 7;
1600 output.swizzle_z = 7;
1601 output.swizzle_w = 7;
1602 ctx.shader->vs_out_misc_write = 1;
1603 ctx.shader->vs_out_point_size = 1;
1604 break;
1605 case TGSI_SEMANTIC_LAYER:
1606 if (out->spi_sid) {
1607 /* duplicate it as PARAM to pass to the pixel shader */
1608 output.array_base = next_param++;
1609 r600_bytecode_add_output(ctx.bc, &output);
1610 last_exp_param = ctx.bc->cf_last;
1611 }
1612 output.array_base = 61;
1613 if (next_clip_pos == 61)
1614 next_clip_pos = 62;
1615 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1616 output.swizzle_x = 7;
1617 output.swizzle_y = 7;
1618 output.swizzle_z = 0;
1619 output.swizzle_w = 7;
1620 ctx.shader->vs_out_misc_write = 1;
1621 ctx.shader->vs_out_layer = 1;
1622 break;
1623 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1624 if (out->spi_sid) {
1625 /* duplicate it as PARAM to pass to the pixel shader */
1626 output.array_base = next_param++;
1627 r600_bytecode_add_output(ctx.bc, &output);
1628 last_exp_param = ctx.bc->cf_last;
1629 }
1630 output.array_base = 61;
1631 if (next_clip_pos == 61)
1632 next_clip_pos = 62;
1633 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1634 ctx.shader->vs_out_misc_write = 1;
1635 ctx.shader->vs_out_viewport = 1;
1636 output.swizzle_x = 7;
1637 output.swizzle_y = 7;
1638 output.swizzle_z = 7;
1639 output.swizzle_w = 0;
1640 break;
1641 case TGSI_SEMANTIC_CLIPDIST:
1642 /* spi_sid is 0 for clipdistance outputs that were generated
1643 * for clipvertex - we don't need to pass them to PS */
1644 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
1645 if (out->spi_sid) {
1646 /* duplicate it as PARAM to pass to the pixel shader */
1647 output.array_base = next_param++;
1648 r600_bytecode_add_output(ctx.bc, &output);
1649 last_exp_param = ctx.bc->cf_last;
1650 }
1651 output.array_base = next_clip_pos++;
1652 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1653 break;
1654 case TGSI_SEMANTIC_FOG:
1655 output.swizzle_y = 4; /* 0 */
1656 output.swizzle_z = 4; /* 0 */
1657 output.swizzle_w = 5; /* 1 */
1658 break;
1659 default:
1660 output.array_base = next_param++;
1661 break;
1662 }
1663 r600_bytecode_add_output(ctx.bc, &output);
1664 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1665 last_exp_param = ctx.bc->cf_last;
1666 else
1667 last_exp_pos = ctx.bc->cf_last;
1668 }
1669
1670 if (!last_exp_pos) {
1671 memset(&output, 0, sizeof(output));
1672 output.gpr = 0;
1673 output.elem_size = 3;
1674 output.swizzle_x = 7;
1675 output.swizzle_y = 7;
1676 output.swizzle_z = 7;
1677 output.swizzle_w = 7;
1678 output.burst_count = 1;
1679 output.type = 2;
1680 output.op = CF_OP_EXPORT;
1681 output.array_base = 60;
1682 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1683 r600_bytecode_add_output(ctx.bc, &output);
1684 last_exp_pos = ctx.bc->cf_last;
1685 }
1686
1687 if (!last_exp_param) {
1688 memset(&output, 0, sizeof(output));
1689 output.gpr = 0;
1690 output.elem_size = 3;
1691 output.swizzle_x = 7;
1692 output.swizzle_y = 7;
1693 output.swizzle_z = 7;
1694 output.swizzle_w = 7;
1695 output.burst_count = 1;
1696 output.type = 2;
1697 output.op = CF_OP_EXPORT;
1698 output.array_base = next_param++;
1699 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1700 r600_bytecode_add_output(ctx.bc, &output);
1701 last_exp_param = ctx.bc->cf_last;
1702 }
1703
1704 last_exp_pos->op = CF_OP_EXPORT_DONE;
1705 last_exp_param->op = CF_OP_EXPORT_DONE;
1706
1707 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1708 cf_pop = ctx.bc->cf_last;
1709
1710 cf_jump->cf_addr = cf_pop->id + 2;
1711 cf_jump->pop_count = 1;
1712 cf_pop->cf_addr = cf_pop->id + 2;
1713 cf_pop->pop_count = 1;
1714
1715 if (ctx.bc->chip_class == CAYMAN)
1716 cm_bytecode_add_cf_end(ctx.bc);
1717 else {
1718 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1719 ctx.bc->cf_last->end_of_program = 1;
1720 }
1721
1722 gs->gs_copy_shader = cshader;
1723
1724 ctx.bc->nstack = 1;
1725
1726 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
1727 cshader->shader.ring_item_size = ocnt * 16;
1728
1729 return r600_bytecode_build(ctx.bc);
1730 }
1731
1732 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, bool ind)
1733 {
1734 struct r600_bytecode_output output;
1735 int i, k, ring_offset;
1736
1737 for (i = 0; i < ctx->shader->noutput; i++) {
1738 if (ctx->gs_for_vs) {
1739 /* for ES we need to lookup corresponding ring offset expected by GS
1740 * (map this output to GS input by name and sid) */
1741 /* FIXME precompute offsets */
1742 ring_offset = -1;
1743 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1744 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1745 struct r600_shader_io *out = &ctx->shader->output[i];
1746 if (in->name == out->name && in->sid == out->sid)
1747 ring_offset = in->ring_offset;
1748 }
1749
1750 if (ring_offset == -1)
1751 continue;
1752 } else
1753 ring_offset = i * 16;
1754
1755 /* next_ring_offset after parsing input decls contains total size of
1756 * single vertex data, gs_next_vertex - current vertex index */
1757 if (!ind)
1758 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
1759
1760 /* get a temp and add the ring offset to the next vertex base in the shader */
1761 memset(&output, 0, sizeof(struct r600_bytecode_output));
1762 output.gpr = ctx->shader->output[i].gpr;
1763 output.elem_size = 3;
1764 output.comp_mask = 0xF;
1765 output.burst_count = 1;
1766
1767 if (ind)
1768 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
1769 else
1770 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1771 output.op = CF_OP_MEM_RING;
1772
1773
1774 if (ind) {
1775 output.array_base = ring_offset >> 2; /* in dwords */
1776 output.array_size = 0xfff;
1777 output.index_gpr = ctx->gs_export_gpr_treg;
1778 } else
1779 output.array_base = ring_offset >> 2; /* in dwords */
1780 r600_bytecode_add_output(ctx->bc, &output);
1781 }
1782
1783 if (ind) {
1784 struct r600_bytecode_alu alu;
1785 int r;
1786
1787 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1788 alu.op = ALU_OP2_ADD_INT;
1789 alu.src[0].sel = ctx->gs_export_gpr_treg;
1790 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1791 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
1792 alu.dst.sel = ctx->gs_export_gpr_treg;
1793 alu.dst.write = 1;
1794 alu.last = 1;
1795 r = r600_bytecode_add_alu(ctx->bc, &alu);
1796 if (r)
1797 return r;
1798 }
1799 ++ctx->gs_next_vertex;
1800 return 0;
1801 }
1802
1803 static int r600_shader_from_tgsi(struct r600_context *rctx,
1804 struct r600_pipe_shader *pipeshader,
1805 union r600_shader_key key)
1806 {
1807 struct r600_screen *rscreen = rctx->screen;
1808 struct r600_shader *shader = &pipeshader->shader;
1809 struct tgsi_token *tokens = pipeshader->selector->tokens;
1810 struct pipe_stream_output_info so = pipeshader->selector->so;
1811 struct tgsi_full_immediate *immediate;
1812 struct r600_shader_ctx ctx;
1813 struct r600_bytecode_output output[32];
1814 unsigned output_done, noutput;
1815 unsigned opcode;
1816 int i, j, k, r = 0;
1817 int next_param_base = 0, next_clip_base;
1818 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
1819 /* Declarations used by llvm code */
1820 bool use_llvm = false;
1821 bool indirect_gprs;
1822 bool ring_outputs = false;
1823 bool pos_emitted = false;
1824
1825 #ifdef R600_USE_LLVM
1826 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
1827 #endif
1828 ctx.bc = &shader->bc;
1829 ctx.shader = shader;
1830 ctx.native_integers = true;
1831
1832 shader->vs_as_gs_a = key.vs.as_gs_a;
1833 shader->vs_as_es = key.vs.as_es;
1834
1835 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
1836 rscreen->has_compressed_msaa_texturing);
1837 ctx.tokens = tokens;
1838 tgsi_scan_shader(tokens, &ctx.info);
1839 shader->indirect_files = ctx.info.indirect_files;
1840 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
1841 tgsi_parse_init(&ctx.parse, tokens);
1842 ctx.type = ctx.info.processor;
1843 shader->processor_type = ctx.type;
1844 ctx.bc->type = shader->processor_type;
1845
1846 ring_outputs = key.vs.as_es || (ctx.type == TGSI_PROCESSOR_GEOMETRY);
1847
1848 if (key.vs.as_es) {
1849 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
1850 } else {
1851 ctx.gs_for_vs = NULL;
1852 }
1853
1854 ctx.next_ring_offset = 0;
1855 ctx.gs_out_ring_offset = 0;
1856 ctx.gs_next_vertex = 0;
1857
1858 shader->uses_index_registers = false;
1859 ctx.face_gpr = -1;
1860 ctx.fixed_pt_position_gpr = -1;
1861 ctx.fragcoord_input = -1;
1862 ctx.colors_used = 0;
1863 ctx.clip_vertex_write = 0;
1864
1865 shader->nr_ps_color_exports = 0;
1866 shader->nr_ps_max_color_exports = 0;
1867
1868 shader->two_side = key.ps.color_two_side;
1869
1870 /* register allocations */
1871 /* Values [0,127] correspond to GPR[0..127].
1872 * Values [128,159] correspond to constant buffer bank 0
1873 * Values [160,191] correspond to constant buffer bank 1
1874 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1875 * Values [256,287] correspond to constant buffer bank 2 (EG)
1876 * Values [288,319] correspond to constant buffer bank 3 (EG)
1877 * Other special values are shown in the list below.
1878 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1879 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1880 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1881 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1882 * 248 SQ_ALU_SRC_0: special constant 0.0.
1883 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1884 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1885 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1886 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1887 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1888 * 254 SQ_ALU_SRC_PV: previous vector result.
1889 * 255 SQ_ALU_SRC_PS: previous scalar result.
1890 */
1891 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1892 ctx.file_offset[i] = 0;
1893 }
1894
1895 #ifdef R600_USE_LLVM
1896 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1897 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1898 "indirect adressing. Falling back to TGSI "
1899 "backend.\n");
1900 use_llvm = 0;
1901 }
1902 #endif
1903 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1904 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1905 if (!use_llvm) {
1906 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1907 }
1908 }
1909 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
1910 if (ctx.bc->chip_class >= EVERGREEN)
1911 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1912 else
1913 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
1914 }
1915 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1916 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
1917 ctx.file_offset[TGSI_FILE_INPUT] = 2;
1918 }
1919 ctx.use_llvm = use_llvm;
1920
1921 if (use_llvm) {
1922 ctx.file_offset[TGSI_FILE_OUTPUT] =
1923 ctx.file_offset[TGSI_FILE_INPUT];
1924 } else {
1925 ctx.file_offset[TGSI_FILE_OUTPUT] =
1926 ctx.file_offset[TGSI_FILE_INPUT] +
1927 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1928 }
1929 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1930 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1931
1932 /* Outside the GPR range. This will be translated to one of the
1933 * kcache banks later. */
1934 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1935
1936 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1937 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1938 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1939 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
1940 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
1941
1942 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1943 ctx.gs_export_gpr_treg = ctx.bc->ar_reg + 3;
1944 ctx.temp_reg = ctx.bc->ar_reg + 4;
1945 } else {
1946 ctx.temp_reg = ctx.bc->ar_reg + 3;
1947 }
1948
1949 shader->max_arrays = 0;
1950 shader->num_arrays = 0;
1951 if (indirect_gprs) {
1952
1953 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1954 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1955 ctx.file_offset[TGSI_FILE_OUTPUT] -
1956 ctx.file_offset[TGSI_FILE_INPUT],
1957 0x0F);
1958 }
1959 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1960 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1961 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1962 ctx.file_offset[TGSI_FILE_OUTPUT],
1963 0x0F);
1964 }
1965 }
1966
1967 ctx.nliterals = 0;
1968 ctx.literals = NULL;
1969 shader->fs_write_all = FALSE;
1970 if (ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1971 shader->fs_write_all = TRUE;
1972
1973 shader->vs_position_window_space = FALSE;
1974 if (ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION])
1975 shader->vs_position_window_space = TRUE;
1976
1977 if (shader->vs_as_gs_a)
1978 vs_add_primid_output(&ctx, key.vs.prim_id_out);
1979
1980 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1981 tgsi_parse_token(&ctx.parse);
1982 switch (ctx.parse.FullToken.Token.Type) {
1983 case TGSI_TOKEN_TYPE_IMMEDIATE:
1984 immediate = &ctx.parse.FullToken.FullImmediate;
1985 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1986 if(ctx.literals == NULL) {
1987 r = -ENOMEM;
1988 goto out_err;
1989 }
1990 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1991 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1992 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1993 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1994 ctx.nliterals++;
1995 break;
1996 case TGSI_TOKEN_TYPE_DECLARATION:
1997 r = tgsi_declaration(&ctx);
1998 if (r)
1999 goto out_err;
2000 break;
2001 case TGSI_TOKEN_TYPE_INSTRUCTION:
2002 case TGSI_TOKEN_TYPE_PROPERTY:
2003 break;
2004 default:
2005 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
2006 r = -EINVAL;
2007 goto out_err;
2008 }
2009 }
2010
2011 shader->ring_item_size = ctx.next_ring_offset;
2012
2013 /* Process two side if needed */
2014 if (shader->two_side && ctx.colors_used) {
2015 int i, count = ctx.shader->ninput;
2016 unsigned next_lds_loc = ctx.shader->nlds;
2017
2018 /* additional inputs will be allocated right after the existing inputs,
2019 * we won't need them after the color selection, so we don't need to
2020 * reserve these gprs for the rest of the shader code and to adjust
2021 * output offsets etc. */
2022 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
2023 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2024
2025 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
2026 if (ctx.face_gpr == -1) {
2027 i = ctx.shader->ninput++;
2028 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
2029 ctx.shader->input[i].spi_sid = 0;
2030 ctx.shader->input[i].gpr = gpr++;
2031 ctx.face_gpr = ctx.shader->input[i].gpr;
2032 }
2033
2034 for (i = 0; i < count; i++) {
2035 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2036 int ni = ctx.shader->ninput++;
2037 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
2038 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
2039 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
2040 ctx.shader->input[ni].gpr = gpr++;
2041 // TGSI to LLVM needs to know the lds position of inputs.
2042 // Non LLVM path computes it later (in process_twoside_color)
2043 ctx.shader->input[ni].lds_pos = next_lds_loc++;
2044 ctx.shader->input[i].back_color_input = ni;
2045 if (ctx.bc->chip_class >= EVERGREEN) {
2046 if ((r = evergreen_interp_input(&ctx, ni)))
2047 return r;
2048 }
2049 }
2050 }
2051 }
2052
2053 /* LLVM backend setup */
2054 #ifdef R600_USE_LLVM
2055 if (use_llvm) {
2056 struct radeon_llvm_context radeon_llvm_ctx;
2057 LLVMModuleRef mod;
2058 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
2059 boolean use_kill = false;
2060
2061 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
2062 radeon_llvm_ctx.type = ctx.type;
2063 radeon_llvm_ctx.two_side = shader->two_side;
2064 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
2065 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
2066 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
2067 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
2068 radeon_llvm_ctx.color_buffer_count = max_color_exports;
2069 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
2070 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
2071 radeon_llvm_ctx.stream_outputs = &so;
2072 radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
2073 radeon_llvm_ctx.has_compressed_msaa_texturing =
2074 ctx.bc->has_compressed_msaa_texturing;
2075 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
2076 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
2077 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
2078
2079 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
2080 radeon_llvm_dispose(&radeon_llvm_ctx);
2081 use_llvm = 0;
2082 fprintf(stderr, "R600 LLVM backend failed to compile "
2083 "shader. Falling back to TGSI\n");
2084 } else {
2085 ctx.file_offset[TGSI_FILE_OUTPUT] =
2086 ctx.file_offset[TGSI_FILE_INPUT];
2087 }
2088 if (use_kill)
2089 ctx.shader->uses_kill = use_kill;
2090 radeon_llvm_dispose(&radeon_llvm_ctx);
2091 }
2092 #endif
2093 /* End of LLVM backend setup */
2094
2095 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
2096 shader->nr_ps_max_color_exports = 8;
2097
2098 if (!use_llvm) {
2099 if (ctx.fragcoord_input >= 0) {
2100 if (ctx.bc->chip_class == CAYMAN) {
2101 for (j = 0 ; j < 4; j++) {
2102 struct r600_bytecode_alu alu;
2103 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2104 alu.op = ALU_OP1_RECIP_IEEE;
2105 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2106 alu.src[0].chan = 3;
2107
2108 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2109 alu.dst.chan = j;
2110 alu.dst.write = (j == 3);
2111 alu.last = 1;
2112 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2113 return r;
2114 }
2115 } else {
2116 struct r600_bytecode_alu alu;
2117 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2118 alu.op = ALU_OP1_RECIP_IEEE;
2119 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2120 alu.src[0].chan = 3;
2121
2122 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2123 alu.dst.chan = 3;
2124 alu.dst.write = 1;
2125 alu.last = 1;
2126 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2127 return r;
2128 }
2129 }
2130
2131 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2132 struct r600_bytecode_alu alu;
2133 int r;
2134
2135 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2136 alu.op = ALU_OP1_MOV;
2137 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2138 alu.src[0].value = 0;
2139 alu.dst.sel = ctx.gs_export_gpr_treg;
2140 alu.dst.write = 1;
2141 alu.last = 1;
2142 r = r600_bytecode_add_alu(ctx.bc, &alu);
2143 if (r)
2144 return r;
2145 }
2146 if (shader->two_side && ctx.colors_used) {
2147 if ((r = process_twoside_color_inputs(&ctx)))
2148 return r;
2149 }
2150
2151 tgsi_parse_init(&ctx.parse, tokens);
2152 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2153 tgsi_parse_token(&ctx.parse);
2154 switch (ctx.parse.FullToken.Token.Type) {
2155 case TGSI_TOKEN_TYPE_INSTRUCTION:
2156 r = tgsi_is_supported(&ctx);
2157 if (r)
2158 goto out_err;
2159 ctx.max_driver_temp_used = 0;
2160 /* reserve first tmp for everyone */
2161 r600_get_temp(&ctx);
2162
2163 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
2164 if ((r = tgsi_split_constant(&ctx)))
2165 goto out_err;
2166 if ((r = tgsi_split_literal_constant(&ctx)))
2167 goto out_err;
2168 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
2169 if ((r = tgsi_split_gs_inputs(&ctx)))
2170 goto out_err;
2171 if (ctx.bc->chip_class == CAYMAN)
2172 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
2173 else if (ctx.bc->chip_class >= EVERGREEN)
2174 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
2175 else
2176 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
2177 r = ctx.inst_info->process(&ctx);
2178 if (r)
2179 goto out_err;
2180 break;
2181 default:
2182 break;
2183 }
2184 }
2185 }
2186
2187 /* Reset the temporary register counter. */
2188 ctx.max_driver_temp_used = 0;
2189
2190 noutput = shader->noutput;
2191
2192 if (!ring_outputs && ctx.clip_vertex_write) {
2193 unsigned clipdist_temp[2];
2194
2195 clipdist_temp[0] = r600_get_temp(&ctx);
2196 clipdist_temp[1] = r600_get_temp(&ctx);
2197
2198 /* need to convert a clipvertex write into clipdistance writes and not export
2199 the clip vertex anymore */
2200
2201 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
2202 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2203 shader->output[noutput].gpr = clipdist_temp[0];
2204 noutput++;
2205 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2206 shader->output[noutput].gpr = clipdist_temp[1];
2207 noutput++;
2208
2209 /* reset spi_sid for clipvertex output to avoid confusing spi */
2210 shader->output[ctx.cv_output].spi_sid = 0;
2211
2212 shader->clip_dist_write = 0xFF;
2213
2214 for (i = 0; i < 8; i++) {
2215 int oreg = i >> 2;
2216 int ochan = i & 3;
2217
2218 for (j = 0; j < 4; j++) {
2219 struct r600_bytecode_alu alu;
2220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2221 alu.op = ALU_OP2_DOT4;
2222 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
2223 alu.src[0].chan = j;
2224
2225 alu.src[1].sel = 512 + i;
2226 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
2227 alu.src[1].chan = j;
2228
2229 alu.dst.sel = clipdist_temp[oreg];
2230 alu.dst.chan = j;
2231 alu.dst.write = (j == ochan);
2232 if (j == 3)
2233 alu.last = 1;
2234 if (!use_llvm)
2235 r = r600_bytecode_add_alu(ctx.bc, &alu);
2236 if (r)
2237 return r;
2238 }
2239 }
2240 }
2241
2242 /* Add stream outputs. */
2243 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
2244 so.num_outputs && !use_llvm)
2245 emit_streamout(&ctx, &so);
2246
2247 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2248 convert_edgeflag_to_int(&ctx);
2249
2250 if (ring_outputs) {
2251 if (key.vs.as_es)
2252 emit_gs_ring_writes(&ctx, FALSE);
2253 } else {
2254 /* Export output */
2255 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
2256
2257 for (i = 0, j = 0; i < noutput; i++, j++) {
2258 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2259 output[j].gpr = shader->output[i].gpr;
2260 output[j].elem_size = 3;
2261 output[j].swizzle_x = 0;
2262 output[j].swizzle_y = 1;
2263 output[j].swizzle_z = 2;
2264 output[j].swizzle_w = 3;
2265 output[j].burst_count = 1;
2266 output[j].type = -1;
2267 output[j].op = CF_OP_EXPORT;
2268 switch (ctx.type) {
2269 case TGSI_PROCESSOR_VERTEX:
2270 switch (shader->output[i].name) {
2271 case TGSI_SEMANTIC_POSITION:
2272 output[j].array_base = 60;
2273 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2274 pos_emitted = true;
2275 break;
2276
2277 case TGSI_SEMANTIC_PSIZE:
2278 output[j].array_base = 61;
2279 output[j].swizzle_y = 7;
2280 output[j].swizzle_z = 7;
2281 output[j].swizzle_w = 7;
2282 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2283 pos_emitted = true;
2284 break;
2285 case TGSI_SEMANTIC_EDGEFLAG:
2286 output[j].array_base = 61;
2287 output[j].swizzle_x = 7;
2288 output[j].swizzle_y = 0;
2289 output[j].swizzle_z = 7;
2290 output[j].swizzle_w = 7;
2291 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2292 pos_emitted = true;
2293 break;
2294 case TGSI_SEMANTIC_LAYER:
2295 /* spi_sid is 0 for outputs that are
2296 * not consumed by PS */
2297 if (shader->output[i].spi_sid) {
2298 output[j].array_base = next_param_base++;
2299 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2300 j++;
2301 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2302 }
2303 output[j].array_base = 61;
2304 output[j].swizzle_x = 7;
2305 output[j].swizzle_y = 7;
2306 output[j].swizzle_z = 0;
2307 output[j].swizzle_w = 7;
2308 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2309 pos_emitted = true;
2310 break;
2311 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2312 /* spi_sid is 0 for outputs that are
2313 * not consumed by PS */
2314 if (shader->output[i].spi_sid) {
2315 output[j].array_base = next_param_base++;
2316 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2317 j++;
2318 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2319 }
2320 output[j].array_base = 61;
2321 output[j].swizzle_x = 7;
2322 output[j].swizzle_y = 7;
2323 output[j].swizzle_z = 7;
2324 output[j].swizzle_w = 0;
2325 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2326 pos_emitted = true;
2327 break;
2328 case TGSI_SEMANTIC_CLIPVERTEX:
2329 j--;
2330 break;
2331 case TGSI_SEMANTIC_CLIPDIST:
2332 output[j].array_base = next_clip_base++;
2333 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2334 pos_emitted = true;
2335 /* spi_sid is 0 for clipdistance outputs that were generated
2336 * for clipvertex - we don't need to pass them to PS */
2337 if (shader->output[i].spi_sid) {
2338 j++;
2339 /* duplicate it as PARAM to pass to the pixel shader */
2340 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2341 output[j].array_base = next_param_base++;
2342 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2343 }
2344 break;
2345 case TGSI_SEMANTIC_FOG:
2346 output[j].swizzle_y = 4; /* 0 */
2347 output[j].swizzle_z = 4; /* 0 */
2348 output[j].swizzle_w = 5; /* 1 */
2349 break;
2350 case TGSI_SEMANTIC_PRIMID:
2351 output[j].swizzle_x = 2;
2352 output[j].swizzle_y = 4; /* 0 */
2353 output[j].swizzle_z = 4; /* 0 */
2354 output[j].swizzle_w = 4; /* 0 */
2355 break;
2356 }
2357
2358 break;
2359 case TGSI_PROCESSOR_FRAGMENT:
2360 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
2361 /* never export more colors than the number of CBs */
2362 if (shader->output[i].sid >= max_color_exports) {
2363 /* skip export */
2364 j--;
2365 continue;
2366 }
2367 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2368 output[j].array_base = shader->output[i].sid;
2369 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2370 shader->nr_ps_color_exports++;
2371 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
2372 for (k = 1; k < max_color_exports; k++) {
2373 j++;
2374 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2375 output[j].gpr = shader->output[i].gpr;
2376 output[j].elem_size = 3;
2377 output[j].swizzle_x = 0;
2378 output[j].swizzle_y = 1;
2379 output[j].swizzle_z = 2;
2380 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2381 output[j].burst_count = 1;
2382 output[j].array_base = k;
2383 output[j].op = CF_OP_EXPORT;
2384 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2385 shader->nr_ps_color_exports++;
2386 }
2387 }
2388 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
2389 output[j].array_base = 61;
2390 output[j].swizzle_x = 2;
2391 output[j].swizzle_y = 7;
2392 output[j].swizzle_z = output[j].swizzle_w = 7;
2393 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2394 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2395 output[j].array_base = 61;
2396 output[j].swizzle_x = 7;
2397 output[j].swizzle_y = 1;
2398 output[j].swizzle_z = output[j].swizzle_w = 7;
2399 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2400 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2401 output[j].array_base = 61;
2402 output[j].swizzle_x = 7;
2403 output[j].swizzle_y = 7;
2404 output[j].swizzle_z = 0;
2405 output[j].swizzle_w = 7;
2406 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2407 } else {
2408 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
2409 r = -EINVAL;
2410 goto out_err;
2411 }
2412 break;
2413 default:
2414 R600_ERR("unsupported processor type %d\n", ctx.type);
2415 r = -EINVAL;
2416 goto out_err;
2417 }
2418
2419 if (output[j].type==-1) {
2420 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2421 output[j].array_base = next_param_base++;
2422 }
2423 }
2424
2425 /* add fake position export */
2426 if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
2427 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2428 output[j].gpr = 0;
2429 output[j].elem_size = 3;
2430 output[j].swizzle_x = 7;
2431 output[j].swizzle_y = 7;
2432 output[j].swizzle_z = 7;
2433 output[j].swizzle_w = 7;
2434 output[j].burst_count = 1;
2435 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2436 output[j].array_base = 60;
2437 output[j].op = CF_OP_EXPORT;
2438 j++;
2439 }
2440
2441 /* add fake param output for vertex shader if no param is exported */
2442 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
2443 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2444 output[j].gpr = 0;
2445 output[j].elem_size = 3;
2446 output[j].swizzle_x = 7;
2447 output[j].swizzle_y = 7;
2448 output[j].swizzle_z = 7;
2449 output[j].swizzle_w = 7;
2450 output[j].burst_count = 1;
2451 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2452 output[j].array_base = 0;
2453 output[j].op = CF_OP_EXPORT;
2454 j++;
2455 }
2456
2457 /* add fake pixel export */
2458 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
2459 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2460 output[j].gpr = 0;
2461 output[j].elem_size = 3;
2462 output[j].swizzle_x = 7;
2463 output[j].swizzle_y = 7;
2464 output[j].swizzle_z = 7;
2465 output[j].swizzle_w = 7;
2466 output[j].burst_count = 1;
2467 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2468 output[j].array_base = 0;
2469 output[j].op = CF_OP_EXPORT;
2470 j++;
2471 shader->nr_ps_color_exports++;
2472 }
2473
2474 noutput = j;
2475
2476 /* set export done on last export of each type */
2477 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
2478 if (!(output_done & (1 << output[i].type))) {
2479 output_done |= (1 << output[i].type);
2480 output[i].op = CF_OP_EXPORT_DONE;
2481 }
2482 }
2483 /* add output to bytecode */
2484 if (!use_llvm) {
2485 for (i = 0; i < noutput; i++) {
2486 r = r600_bytecode_add_output(ctx.bc, &output[i]);
2487 if (r)
2488 goto out_err;
2489 }
2490 }
2491 }
2492
2493 /* add program end */
2494 if (!use_llvm) {
2495 if (ctx.bc->chip_class == CAYMAN)
2496 cm_bytecode_add_cf_end(ctx.bc);
2497 else {
2498 const struct cf_op_info *last = NULL;
2499
2500 if (ctx.bc->cf_last)
2501 last = r600_isa_cf(ctx.bc->cf_last->op);
2502
2503 /* alu clause instructions don't have EOP bit, so add NOP */
2504 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
2505 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2506
2507 ctx.bc->cf_last->end_of_program = 1;
2508 }
2509 }
2510
2511 /* check GPR limit - we have 124 = 128 - 4
2512 * (4 are reserved as alu clause temporary registers) */
2513 if (ctx.bc->ngpr > 124) {
2514 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
2515 r = -ENOMEM;
2516 goto out_err;
2517 }
2518
2519 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2520 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
2521 return r;
2522 }
2523
2524 free(ctx.literals);
2525 tgsi_parse_free(&ctx.parse);
2526 return 0;
2527 out_err:
2528 free(ctx.literals);
2529 tgsi_parse_free(&ctx.parse);
2530 return r;
2531 }
2532
2533 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
2534 {
2535 const unsigned tgsi_opcode =
2536 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
2537 R600_ERR("%s tgsi opcode unsupported\n",
2538 tgsi_get_opcode_name(tgsi_opcode));
2539 return -EINVAL;
2540 }
2541
2542 static int tgsi_end(struct r600_shader_ctx *ctx)
2543 {
2544 return 0;
2545 }
2546
2547 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
2548 const struct r600_shader_src *shader_src,
2549 unsigned chan)
2550 {
2551 bc_src->sel = shader_src->sel;
2552 bc_src->chan = shader_src->swizzle[chan];
2553 bc_src->neg = shader_src->neg;
2554 bc_src->abs = shader_src->abs;
2555 bc_src->rel = shader_src->rel;
2556 bc_src->value = shader_src->value[bc_src->chan];
2557 bc_src->kc_bank = shader_src->kc_bank;
2558 bc_src->kc_rel = shader_src->kc_rel;
2559 }
2560
2561 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
2562 {
2563 bc_src->abs = 1;
2564 bc_src->neg = 0;
2565 }
2566
2567 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2568 {
2569 bc_src->neg = !bc_src->neg;
2570 }
2571
2572 static void tgsi_dst(struct r600_shader_ctx *ctx,
2573 const struct tgsi_full_dst_register *tgsi_dst,
2574 unsigned swizzle,
2575 struct r600_bytecode_alu_dst *r600_dst)
2576 {
2577 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2578
2579 r600_dst->sel = tgsi_dst->Register.Index;
2580 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2581 r600_dst->chan = swizzle;
2582 r600_dst->write = 1;
2583 if (tgsi_dst->Register.Indirect)
2584 r600_dst->rel = V_SQ_REL_RELATIVE;
2585 if (inst->Instruction.Saturate) {
2586 r600_dst->clamp = 1;
2587 }
2588 }
2589
2590 static int tgsi_last_instruction(unsigned writemask)
2591 {
2592 int i, lasti = 0;
2593
2594 for (i = 0; i < 4; i++) {
2595 if (writemask & (1 << i)) {
2596 lasti = i;
2597 }
2598 }
2599 return lasti;
2600 }
2601
2602 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
2603 {
2604 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2605 struct r600_bytecode_alu alu;
2606 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2607 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2608 /* use temp register if trans_only and more than one dst component */
2609 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
2610
2611 for (i = 0; i <= lasti; i++) {
2612 if (!(write_mask & (1 << i)))
2613 continue;
2614
2615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2616 if (use_tmp) {
2617 alu.dst.sel = ctx->temp_reg;
2618 alu.dst.chan = i;
2619 alu.dst.write = 1;
2620 } else
2621 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2622
2623 alu.op = ctx->inst_info->op;
2624 if (!swap) {
2625 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2626 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2627 }
2628 } else {
2629 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2630 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2631 }
2632 /* handle some special cases */
2633 switch (inst->Instruction.Opcode) {
2634 case TGSI_OPCODE_SUB:
2635 r600_bytecode_src_toggle_neg(&alu.src[1]);
2636 break;
2637 case TGSI_OPCODE_ABS:
2638 r600_bytecode_src_set_abs(&alu.src[0]);
2639 break;
2640 default:
2641 break;
2642 }
2643 if (i == lasti || trans_only) {
2644 alu.last = 1;
2645 }
2646 r = r600_bytecode_add_alu(ctx->bc, &alu);
2647 if (r)
2648 return r;
2649 }
2650
2651 if (use_tmp) {
2652 /* move result from temp to dst */
2653 for (i = 0; i <= lasti; i++) {
2654 if (!(write_mask & (1 << i)))
2655 continue;
2656
2657 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2658 alu.op = ALU_OP1_MOV;
2659 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2660 alu.src[0].sel = ctx->temp_reg;
2661 alu.src[0].chan = i;
2662 alu.last = (i == lasti);
2663
2664 r = r600_bytecode_add_alu(ctx->bc, &alu);
2665 if (r)
2666 return r;
2667 }
2668 }
2669 return 0;
2670 }
2671
2672 static int tgsi_op2(struct r600_shader_ctx *ctx)
2673 {
2674 return tgsi_op2_s(ctx, 0, 0);
2675 }
2676
2677 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2678 {
2679 return tgsi_op2_s(ctx, 1, 0);
2680 }
2681
2682 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2683 {
2684 return tgsi_op2_s(ctx, 0, 1);
2685 }
2686
2687 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2688 {
2689 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2690 struct r600_bytecode_alu alu;
2691 int i, r;
2692 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2693
2694 for (i = 0; i < lasti + 1; i++) {
2695
2696 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2697 continue;
2698 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2699 alu.op = ctx->inst_info->op;
2700
2701 alu.src[0].sel = V_SQ_ALU_SRC_0;
2702
2703 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2704
2705 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2706
2707 if (i == lasti) {
2708 alu.last = 1;
2709 }
2710 r = r600_bytecode_add_alu(ctx->bc, &alu);
2711 if (r)
2712 return r;
2713 }
2714 return 0;
2715
2716 }
2717
2718 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
2719 {
2720 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2721 int i, j, r;
2722 struct r600_bytecode_alu alu;
2723 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2724
2725 for (i = 0 ; i < last_slot; i++) {
2726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2727 alu.op = ctx->inst_info->op;
2728 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2729 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
2730
2731 /* RSQ should take the absolute value of src */
2732 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
2733 r600_bytecode_src_set_abs(&alu.src[j]);
2734 }
2735 }
2736 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2737 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2738
2739 if (i == last_slot - 1)
2740 alu.last = 1;
2741 r = r600_bytecode_add_alu(ctx->bc, &alu);
2742 if (r)
2743 return r;
2744 }
2745 return 0;
2746 }
2747
2748 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
2749 {
2750 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2751 int i, j, k, r;
2752 struct r600_bytecode_alu alu;
2753 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2754 int t1 = ctx->temp_reg;
2755
2756 for (k = 0; k <= lasti; k++) {
2757 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
2758 continue;
2759
2760 for (i = 0 ; i < 4; i++) {
2761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2762 alu.op = ctx->inst_info->op;
2763 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2764 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
2765 }
2766 alu.dst.sel = t1;
2767 alu.dst.chan = i;
2768 alu.dst.write = (i == k);
2769 if (i == 3)
2770 alu.last = 1;
2771 r = r600_bytecode_add_alu(ctx->bc, &alu);
2772 if (r)
2773 return r;
2774 }
2775 }
2776
2777 for (i = 0 ; i <= lasti; i++) {
2778 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2779 continue;
2780 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2781 alu.op = ALU_OP1_MOV;
2782 alu.src[0].sel = t1;
2783 alu.src[0].chan = i;
2784 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2785 alu.dst.write = 1;
2786 if (i == lasti)
2787 alu.last = 1;
2788 r = r600_bytecode_add_alu(ctx->bc, &alu);
2789 if (r)
2790 return r;
2791 }
2792
2793 return 0;
2794 }
2795
2796 /*
2797 * r600 - trunc to -PI..PI range
2798 * r700 - normalize by dividing by 2PI
2799 * see fdo bug 27901
2800 */
2801 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
2802 {
2803 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
2804 static float double_pi = 3.1415926535 * 2;
2805 static float neg_pi = -3.1415926535;
2806
2807 int r;
2808 struct r600_bytecode_alu alu;
2809
2810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2811 alu.op = ALU_OP3_MULADD;
2812 alu.is_op3 = 1;
2813
2814 alu.dst.chan = 0;
2815 alu.dst.sel = ctx->temp_reg;
2816 alu.dst.write = 1;
2817
2818 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2819
2820 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2821 alu.src[1].chan = 0;
2822 alu.src[1].value = *(uint32_t *)&half_inv_pi;
2823 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2824 alu.src[2].chan = 0;
2825 alu.last = 1;
2826 r = r600_bytecode_add_alu(ctx->bc, &alu);
2827 if (r)
2828 return r;
2829
2830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2831 alu.op = ALU_OP1_FRACT;
2832
2833 alu.dst.chan = 0;
2834 alu.dst.sel = ctx->temp_reg;
2835 alu.dst.write = 1;
2836
2837 alu.src[0].sel = ctx->temp_reg;
2838 alu.src[0].chan = 0;
2839 alu.last = 1;
2840 r = r600_bytecode_add_alu(ctx->bc, &alu);
2841 if (r)
2842 return r;
2843
2844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2845 alu.op = ALU_OP3_MULADD;
2846 alu.is_op3 = 1;
2847
2848 alu.dst.chan = 0;
2849 alu.dst.sel = ctx->temp_reg;
2850 alu.dst.write = 1;
2851
2852 alu.src[0].sel = ctx->temp_reg;
2853 alu.src[0].chan = 0;
2854
2855 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2856 alu.src[1].chan = 0;
2857 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2858 alu.src[2].chan = 0;
2859
2860 if (ctx->bc->chip_class == R600) {
2861 alu.src[1].value = *(uint32_t *)&double_pi;
2862 alu.src[2].value = *(uint32_t *)&neg_pi;
2863 } else {
2864 alu.src[1].sel = V_SQ_ALU_SRC_1;
2865 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2866 alu.src[2].neg = 1;
2867 }
2868
2869 alu.last = 1;
2870 r = r600_bytecode_add_alu(ctx->bc, &alu);
2871 if (r)
2872 return r;
2873 return 0;
2874 }
2875
2876 static int cayman_trig(struct r600_shader_ctx *ctx)
2877 {
2878 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2879 struct r600_bytecode_alu alu;
2880 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2881 int i, r;
2882
2883 r = tgsi_setup_trig(ctx);
2884 if (r)
2885 return r;
2886
2887
2888 for (i = 0; i < last_slot; i++) {
2889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2890 alu.op = ctx->inst_info->op;
2891 alu.dst.chan = i;
2892
2893 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2894 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2895
2896 alu.src[0].sel = ctx->temp_reg;
2897 alu.src[0].chan = 0;
2898 if (i == last_slot - 1)
2899 alu.last = 1;
2900 r = r600_bytecode_add_alu(ctx->bc, &alu);
2901 if (r)
2902 return r;
2903 }
2904 return 0;
2905 }
2906
2907 static int tgsi_trig(struct r600_shader_ctx *ctx)
2908 {
2909 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2910 struct r600_bytecode_alu alu;
2911 int i, r;
2912 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2913
2914 r = tgsi_setup_trig(ctx);
2915 if (r)
2916 return r;
2917
2918 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2919 alu.op = ctx->inst_info->op;
2920 alu.dst.chan = 0;
2921 alu.dst.sel = ctx->temp_reg;
2922 alu.dst.write = 1;
2923
2924 alu.src[0].sel = ctx->temp_reg;
2925 alu.src[0].chan = 0;
2926 alu.last = 1;
2927 r = r600_bytecode_add_alu(ctx->bc, &alu);
2928 if (r)
2929 return r;
2930
2931 /* replicate result */
2932 for (i = 0; i < lasti + 1; i++) {
2933 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2934 continue;
2935
2936 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2937 alu.op = ALU_OP1_MOV;
2938
2939 alu.src[0].sel = ctx->temp_reg;
2940 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2941 if (i == lasti)
2942 alu.last = 1;
2943 r = r600_bytecode_add_alu(ctx->bc, &alu);
2944 if (r)
2945 return r;
2946 }
2947 return 0;
2948 }
2949
2950 static int tgsi_scs(struct r600_shader_ctx *ctx)
2951 {
2952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2953 struct r600_bytecode_alu alu;
2954 int i, r;
2955
2956 /* We'll only need the trig stuff if we are going to write to the
2957 * X or Y components of the destination vector.
2958 */
2959 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2960 r = tgsi_setup_trig(ctx);
2961 if (r)
2962 return r;
2963 }
2964
2965 /* dst.x = COS */
2966 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2967 if (ctx->bc->chip_class == CAYMAN) {
2968 for (i = 0 ; i < 3; i++) {
2969 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2970 alu.op = ALU_OP1_COS;
2971 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2972
2973 if (i == 0)
2974 alu.dst.write = 1;
2975 else
2976 alu.dst.write = 0;
2977 alu.src[0].sel = ctx->temp_reg;
2978 alu.src[0].chan = 0;
2979 if (i == 2)
2980 alu.last = 1;
2981 r = r600_bytecode_add_alu(ctx->bc, &alu);
2982 if (r)
2983 return r;
2984 }
2985 } else {
2986 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2987 alu.op = ALU_OP1_COS;
2988 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2989
2990 alu.src[0].sel = ctx->temp_reg;
2991 alu.src[0].chan = 0;
2992 alu.last = 1;
2993 r = r600_bytecode_add_alu(ctx->bc, &alu);
2994 if (r)
2995 return r;
2996 }
2997 }
2998
2999 /* dst.y = SIN */
3000 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3001 if (ctx->bc->chip_class == CAYMAN) {
3002 for (i = 0 ; i < 3; i++) {
3003 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3004 alu.op = ALU_OP1_SIN;
3005 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3006 if (i == 1)
3007 alu.dst.write = 1;
3008 else
3009 alu.dst.write = 0;
3010 alu.src[0].sel = ctx->temp_reg;
3011 alu.src[0].chan = 0;
3012 if (i == 2)
3013 alu.last = 1;
3014 r = r600_bytecode_add_alu(ctx->bc, &alu);
3015 if (r)
3016 return r;
3017 }
3018 } else {
3019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3020 alu.op = ALU_OP1_SIN;
3021 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3022
3023 alu.src[0].sel = ctx->temp_reg;
3024 alu.src[0].chan = 0;
3025 alu.last = 1;
3026 r = r600_bytecode_add_alu(ctx->bc, &alu);
3027 if (r)
3028 return r;
3029 }
3030 }
3031
3032 /* dst.z = 0.0; */
3033 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3034 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3035
3036 alu.op = ALU_OP1_MOV;
3037
3038 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3039
3040 alu.src[0].sel = V_SQ_ALU_SRC_0;
3041 alu.src[0].chan = 0;
3042
3043 alu.last = 1;
3044
3045 r = r600_bytecode_add_alu(ctx->bc, &alu);
3046 if (r)
3047 return r;
3048 }
3049
3050 /* dst.w = 1.0; */
3051 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3052 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3053
3054 alu.op = ALU_OP1_MOV;
3055
3056 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3057
3058 alu.src[0].sel = V_SQ_ALU_SRC_1;
3059 alu.src[0].chan = 0;
3060
3061 alu.last = 1;
3062
3063 r = r600_bytecode_add_alu(ctx->bc, &alu);
3064 if (r)
3065 return r;
3066 }
3067
3068 return 0;
3069 }
3070
3071 static int tgsi_kill(struct r600_shader_ctx *ctx)
3072 {
3073 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3074 struct r600_bytecode_alu alu;
3075 int i, r;
3076
3077 for (i = 0; i < 4; i++) {
3078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3079 alu.op = ctx->inst_info->op;
3080
3081 alu.dst.chan = i;
3082
3083 alu.src[0].sel = V_SQ_ALU_SRC_0;
3084
3085 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
3086 alu.src[1].sel = V_SQ_ALU_SRC_1;
3087 alu.src[1].neg = 1;
3088 } else {
3089 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3090 }
3091 if (i == 3) {
3092 alu.last = 1;
3093 }
3094 r = r600_bytecode_add_alu(ctx->bc, &alu);
3095 if (r)
3096 return r;
3097 }
3098
3099 /* kill must be last in ALU */
3100 ctx->bc->force_add_cf = 1;
3101 ctx->shader->uses_kill = TRUE;
3102 return 0;
3103 }
3104
3105 static int tgsi_lit(struct r600_shader_ctx *ctx)
3106 {
3107 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3108 struct r600_bytecode_alu alu;
3109 int r;
3110
3111 /* tmp.x = max(src.y, 0.0) */
3112 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3113 alu.op = ALU_OP2_MAX;
3114 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3115 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3116 alu.src[1].chan = 1;
3117
3118 alu.dst.sel = ctx->temp_reg;
3119 alu.dst.chan = 0;
3120 alu.dst.write = 1;
3121
3122 alu.last = 1;
3123 r = r600_bytecode_add_alu(ctx->bc, &alu);
3124 if (r)
3125 return r;
3126
3127 if (inst->Dst[0].Register.WriteMask & (1 << 2))
3128 {
3129 int chan;
3130 int sel;
3131 int i;
3132
3133 if (ctx->bc->chip_class == CAYMAN) {
3134 for (i = 0; i < 3; i++) {
3135 /* tmp.z = log(tmp.x) */
3136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3137 alu.op = ALU_OP1_LOG_CLAMPED;
3138 alu.src[0].sel = ctx->temp_reg;
3139 alu.src[0].chan = 0;
3140 alu.dst.sel = ctx->temp_reg;
3141 alu.dst.chan = i;
3142 if (i == 2) {
3143 alu.dst.write = 1;
3144 alu.last = 1;
3145 } else
3146 alu.dst.write = 0;
3147
3148 r = r600_bytecode_add_alu(ctx->bc, &alu);
3149 if (r)
3150 return r;
3151 }
3152 } else {
3153 /* tmp.z = log(tmp.x) */
3154 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3155 alu.op = ALU_OP1_LOG_CLAMPED;
3156 alu.src[0].sel = ctx->temp_reg;
3157 alu.src[0].chan = 0;
3158 alu.dst.sel = ctx->temp_reg;
3159 alu.dst.chan = 2;
3160 alu.dst.write = 1;
3161 alu.last = 1;
3162 r = r600_bytecode_add_alu(ctx->bc, &alu);
3163 if (r)
3164 return r;
3165 }
3166
3167 chan = alu.dst.chan;
3168 sel = alu.dst.sel;
3169
3170 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
3171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3172 alu.op = ALU_OP3_MUL_LIT;
3173 alu.src[0].sel = sel;
3174 alu.src[0].chan = chan;
3175 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
3176 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
3177 alu.dst.sel = ctx->temp_reg;
3178 alu.dst.chan = 0;
3179 alu.dst.write = 1;
3180 alu.is_op3 = 1;
3181 alu.last = 1;
3182 r = r600_bytecode_add_alu(ctx->bc, &alu);
3183 if (r)
3184 return r;
3185
3186 if (ctx->bc->chip_class == CAYMAN) {
3187 for (i = 0; i < 3; i++) {
3188 /* dst.z = exp(tmp.x) */
3189 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3190 alu.op = ALU_OP1_EXP_IEEE;
3191 alu.src[0].sel = ctx->temp_reg;
3192 alu.src[0].chan = 0;
3193 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3194 if (i == 2) {
3195 alu.dst.write = 1;
3196 alu.last = 1;
3197 } else
3198 alu.dst.write = 0;
3199 r = r600_bytecode_add_alu(ctx->bc, &alu);
3200 if (r)
3201 return r;
3202 }
3203 } else {
3204 /* dst.z = exp(tmp.x) */
3205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3206 alu.op = ALU_OP1_EXP_IEEE;
3207 alu.src[0].sel = ctx->temp_reg;
3208 alu.src[0].chan = 0;
3209 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3210 alu.last = 1;
3211 r = r600_bytecode_add_alu(ctx->bc, &alu);
3212 if (r)
3213 return r;
3214 }
3215 }
3216
3217 /* dst.x, <- 1.0 */
3218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3219 alu.op = ALU_OP1_MOV;
3220 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
3221 alu.src[0].chan = 0;
3222 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3223 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
3224 r = r600_bytecode_add_alu(ctx->bc, &alu);
3225 if (r)
3226 return r;
3227
3228 /* dst.y = max(src.x, 0.0) */
3229 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3230 alu.op = ALU_OP2_MAX;
3231 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3232 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3233 alu.src[1].chan = 0;
3234 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3235 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
3236 r = r600_bytecode_add_alu(ctx->bc, &alu);
3237 if (r)
3238 return r;
3239
3240 /* dst.w, <- 1.0 */
3241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3242 alu.op = ALU_OP1_MOV;
3243 alu.src[0].sel = V_SQ_ALU_SRC_1;
3244 alu.src[0].chan = 0;
3245 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3246 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
3247 alu.last = 1;
3248 r = r600_bytecode_add_alu(ctx->bc, &alu);
3249 if (r)
3250 return r;
3251
3252 return 0;
3253 }
3254
3255 static int tgsi_rsq(struct r600_shader_ctx *ctx)
3256 {
3257 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3258 struct r600_bytecode_alu alu;
3259 int i, r;
3260
3261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3262
3263 /* XXX:
3264 * For state trackers other than OpenGL, we'll want to use
3265 * _RECIPSQRT_IEEE instead.
3266 */
3267 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
3268
3269 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3270 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3271 r600_bytecode_src_set_abs(&alu.src[i]);
3272 }
3273 alu.dst.sel = ctx->temp_reg;
3274 alu.dst.write = 1;
3275 alu.last = 1;
3276 r = r600_bytecode_add_alu(ctx->bc, &alu);
3277 if (r)
3278 return r;
3279 /* replicate result */
3280 return tgsi_helper_tempx_replicate(ctx);
3281 }
3282
3283 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
3284 {
3285 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3286 struct r600_bytecode_alu alu;
3287 int i, r;
3288
3289 for (i = 0; i < 4; i++) {
3290 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3291 alu.src[0].sel = ctx->temp_reg;
3292 alu.op = ALU_OP1_MOV;
3293 alu.dst.chan = i;
3294 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3295 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3296 if (i == 3)
3297 alu.last = 1;
3298 r = r600_bytecode_add_alu(ctx->bc, &alu);
3299 if (r)
3300 return r;
3301 }
3302 return 0;
3303 }
3304
3305 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
3306 {
3307 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3308 struct r600_bytecode_alu alu;
3309 int i, r;
3310
3311 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3312 alu.op = ctx->inst_info->op;
3313 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3314 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3315 }
3316 alu.dst.sel = ctx->temp_reg;
3317 alu.dst.write = 1;
3318 alu.last = 1;
3319 r = r600_bytecode_add_alu(ctx->bc, &alu);
3320 if (r)
3321 return r;
3322 /* replicate result */
3323 return tgsi_helper_tempx_replicate(ctx);
3324 }
3325
3326 static int cayman_pow(struct r600_shader_ctx *ctx)
3327 {
3328 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3329 int i, r;
3330 struct r600_bytecode_alu alu;
3331 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3332
3333 for (i = 0; i < 3; i++) {
3334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3335 alu.op = ALU_OP1_LOG_IEEE;
3336 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3337 alu.dst.sel = ctx->temp_reg;
3338 alu.dst.chan = i;
3339 alu.dst.write = 1;
3340 if (i == 2)
3341 alu.last = 1;
3342 r = r600_bytecode_add_alu(ctx->bc, &alu);
3343 if (r)
3344 return r;
3345 }
3346
3347 /* b * LOG2(a) */
3348 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3349 alu.op = ALU_OP2_MUL;
3350 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3351 alu.src[1].sel = ctx->temp_reg;
3352 alu.dst.sel = ctx->temp_reg;
3353 alu.dst.write = 1;
3354 alu.last = 1;
3355 r = r600_bytecode_add_alu(ctx->bc, &alu);
3356 if (r)
3357 return r;
3358
3359 for (i = 0; i < last_slot; i++) {
3360 /* POW(a,b) = EXP2(b * LOG2(a))*/
3361 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3362 alu.op = ALU_OP1_EXP_IEEE;
3363 alu.src[0].sel = ctx->temp_reg;
3364
3365 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3366 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3367 if (i == last_slot - 1)
3368 alu.last = 1;
3369 r = r600_bytecode_add_alu(ctx->bc, &alu);
3370 if (r)
3371 return r;
3372 }
3373 return 0;
3374 }
3375
3376 static int tgsi_pow(struct r600_shader_ctx *ctx)
3377 {
3378 struct r600_bytecode_alu alu;
3379 int r;
3380
3381 /* LOG2(a) */
3382 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3383 alu.op = ALU_OP1_LOG_IEEE;
3384 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3385 alu.dst.sel = ctx->temp_reg;
3386 alu.dst.write = 1;
3387 alu.last = 1;
3388 r = r600_bytecode_add_alu(ctx->bc, &alu);
3389 if (r)
3390 return r;
3391 /* b * LOG2(a) */
3392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3393 alu.op = ALU_OP2_MUL;
3394 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3395 alu.src[1].sel = ctx->temp_reg;
3396 alu.dst.sel = ctx->temp_reg;
3397 alu.dst.write = 1;
3398 alu.last = 1;
3399 r = r600_bytecode_add_alu(ctx->bc, &alu);
3400 if (r)
3401 return r;
3402 /* POW(a,b) = EXP2(b * LOG2(a))*/
3403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3404 alu.op = ALU_OP1_EXP_IEEE;
3405 alu.src[0].sel = ctx->temp_reg;
3406 alu.dst.sel = ctx->temp_reg;
3407 alu.dst.write = 1;
3408 alu.last = 1;
3409 r = r600_bytecode_add_alu(ctx->bc, &alu);
3410 if (r)
3411 return r;
3412 return tgsi_helper_tempx_replicate(ctx);
3413 }
3414
3415 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
3416 {
3417 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3418 struct r600_bytecode_alu alu;
3419 int i, r, j;
3420 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3421 int tmp0 = ctx->temp_reg;
3422 int tmp1 = r600_get_temp(ctx);
3423 int tmp2 = r600_get_temp(ctx);
3424 int tmp3 = r600_get_temp(ctx);
3425 /* Unsigned path:
3426 *
3427 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
3428 *
3429 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
3430 * 2. tmp0.z = lo (tmp0.x * src2)
3431 * 3. tmp0.w = -tmp0.z
3432 * 4. tmp0.y = hi (tmp0.x * src2)
3433 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
3434 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
3435 * 7. tmp1.x = tmp0.x - tmp0.w
3436 * 8. tmp1.y = tmp0.x + tmp0.w
3437 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
3438 * 10. tmp0.z = hi(tmp0.x * src1) = q
3439 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
3440 *
3441 * 12. tmp0.w = src1 - tmp0.y = r
3442 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
3443 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
3444 *
3445 * if DIV
3446 *
3447 * 15. tmp1.z = tmp0.z + 1 = q + 1
3448 * 16. tmp1.w = tmp0.z - 1 = q - 1
3449 *
3450 * else MOD
3451 *
3452 * 15. tmp1.z = tmp0.w - src2 = r - src2
3453 * 16. tmp1.w = tmp0.w + src2 = r + src2
3454 *
3455 * endif
3456 *
3457 * 17. tmp1.x = tmp1.x & tmp1.y
3458 *
3459 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
3460 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
3461 *
3462 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
3463 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
3464 *
3465 * Signed path:
3466 *
3467 * Same as unsigned, using abs values of the operands,
3468 * and fixing the sign of the result in the end.
3469 */
3470
3471 for (i = 0; i < 4; i++) {
3472 if (!(write_mask & (1<<i)))
3473 continue;
3474
3475 if (signed_op) {
3476
3477 /* tmp2.x = -src0 */
3478 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3479 alu.op = ALU_OP2_SUB_INT;
3480
3481 alu.dst.sel = tmp2;
3482 alu.dst.chan = 0;
3483 alu.dst.write = 1;
3484
3485 alu.src[0].sel = V_SQ_ALU_SRC_0;
3486
3487 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3488
3489 alu.last = 1;
3490 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3491 return r;
3492
3493 /* tmp2.y = -src1 */
3494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3495 alu.op = ALU_OP2_SUB_INT;
3496
3497 alu.dst.sel = tmp2;
3498 alu.dst.chan = 1;
3499 alu.dst.write = 1;
3500
3501 alu.src[0].sel = V_SQ_ALU_SRC_0;
3502
3503 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3504
3505 alu.last = 1;
3506 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3507 return r;
3508
3509 /* tmp2.z sign bit is set if src0 and src2 signs are different */
3510 /* it will be a sign of the quotient */
3511 if (!mod) {
3512
3513 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3514 alu.op = ALU_OP2_XOR_INT;
3515
3516 alu.dst.sel = tmp2;
3517 alu.dst.chan = 2;
3518 alu.dst.write = 1;
3519
3520 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3521 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3522
3523 alu.last = 1;
3524 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3525 return r;
3526 }
3527
3528 /* tmp2.x = |src0| */
3529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3530 alu.op = ALU_OP3_CNDGE_INT;
3531 alu.is_op3 = 1;
3532
3533 alu.dst.sel = tmp2;
3534 alu.dst.chan = 0;
3535 alu.dst.write = 1;
3536
3537 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3538 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3539 alu.src[2].sel = tmp2;
3540 alu.src[2].chan = 0;
3541
3542 alu.last = 1;
3543 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3544 return r;
3545
3546 /* tmp2.y = |src1| */
3547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3548 alu.op = ALU_OP3_CNDGE_INT;
3549 alu.is_op3 = 1;
3550
3551 alu.dst.sel = tmp2;
3552 alu.dst.chan = 1;
3553 alu.dst.write = 1;
3554
3555 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3556 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3557 alu.src[2].sel = tmp2;
3558 alu.src[2].chan = 1;
3559
3560 alu.last = 1;
3561 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3562 return r;
3563
3564 }
3565
3566 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
3567 if (ctx->bc->chip_class == CAYMAN) {
3568 /* tmp3.x = u2f(src2) */
3569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3570 alu.op = ALU_OP1_UINT_TO_FLT;
3571
3572 alu.dst.sel = tmp3;
3573 alu.dst.chan = 0;
3574 alu.dst.write = 1;
3575
3576 if (signed_op) {
3577 alu.src[0].sel = tmp2;
3578 alu.src[0].chan = 1;
3579 } else {
3580 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3581 }
3582
3583 alu.last = 1;
3584 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3585 return r;
3586
3587 /* tmp0.x = recip(tmp3.x) */
3588 for (j = 0 ; j < 3; j++) {
3589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3590 alu.op = ALU_OP1_RECIP_IEEE;
3591
3592 alu.dst.sel = tmp0;
3593 alu.dst.chan = j;
3594 alu.dst.write = (j == 0);
3595
3596 alu.src[0].sel = tmp3;
3597 alu.src[0].chan = 0;
3598
3599 if (j == 2)
3600 alu.last = 1;
3601 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3602 return r;
3603 }
3604
3605 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3606 alu.op = ALU_OP2_MUL;
3607
3608 alu.src[0].sel = tmp0;
3609 alu.src[0].chan = 0;
3610
3611 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3612 alu.src[1].value = 0x4f800000;
3613
3614 alu.dst.sel = tmp3;
3615 alu.dst.write = 1;
3616 alu.last = 1;
3617 r = r600_bytecode_add_alu(ctx->bc, &alu);
3618 if (r)
3619 return r;
3620
3621 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3622 alu.op = ALU_OP1_FLT_TO_UINT;
3623
3624 alu.dst.sel = tmp0;
3625 alu.dst.chan = 0;
3626 alu.dst.write = 1;
3627
3628 alu.src[0].sel = tmp3;
3629 alu.src[0].chan = 0;
3630
3631 alu.last = 1;
3632 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3633 return r;
3634
3635 } else {
3636 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3637 alu.op = ALU_OP1_RECIP_UINT;
3638
3639 alu.dst.sel = tmp0;
3640 alu.dst.chan = 0;
3641 alu.dst.write = 1;
3642
3643 if (signed_op) {
3644 alu.src[0].sel = tmp2;
3645 alu.src[0].chan = 1;
3646 } else {
3647 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3648 }
3649
3650 alu.last = 1;
3651 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3652 return r;
3653 }
3654
3655 /* 2. tmp0.z = lo (tmp0.x * src2) */
3656 if (ctx->bc->chip_class == CAYMAN) {
3657 for (j = 0 ; j < 4; j++) {
3658 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3659 alu.op = ALU_OP2_MULLO_UINT;
3660
3661 alu.dst.sel = tmp0;
3662 alu.dst.chan = j;
3663 alu.dst.write = (j == 2);
3664
3665 alu.src[0].sel = tmp0;
3666 alu.src[0].chan = 0;
3667 if (signed_op) {
3668 alu.src[1].sel = tmp2;
3669 alu.src[1].chan = 1;
3670 } else {
3671 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3672 }
3673
3674 alu.last = (j == 3);
3675 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3676 return r;
3677 }
3678 } else {
3679 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3680 alu.op = ALU_OP2_MULLO_UINT;
3681
3682 alu.dst.sel = tmp0;
3683 alu.dst.chan = 2;
3684 alu.dst.write = 1;
3685
3686 alu.src[0].sel = tmp0;
3687 alu.src[0].chan = 0;
3688 if (signed_op) {
3689 alu.src[1].sel = tmp2;
3690 alu.src[1].chan = 1;
3691 } else {
3692 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3693 }
3694
3695 alu.last = 1;
3696 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3697 return r;
3698 }
3699
3700 /* 3. tmp0.w = -tmp0.z */
3701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3702 alu.op = ALU_OP2_SUB_INT;
3703
3704 alu.dst.sel = tmp0;
3705 alu.dst.chan = 3;
3706 alu.dst.write = 1;
3707
3708 alu.src[0].sel = V_SQ_ALU_SRC_0;
3709 alu.src[1].sel = tmp0;
3710 alu.src[1].chan = 2;
3711
3712 alu.last = 1;
3713 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3714 return r;
3715
3716 /* 4. tmp0.y = hi (tmp0.x * src2) */
3717 if (ctx->bc->chip_class == CAYMAN) {
3718 for (j = 0 ; j < 4; j++) {
3719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3720 alu.op = ALU_OP2_MULHI_UINT;
3721
3722 alu.dst.sel = tmp0;
3723 alu.dst.chan = j;
3724 alu.dst.write = (j == 1);
3725
3726 alu.src[0].sel = tmp0;
3727 alu.src[0].chan = 0;
3728
3729 if (signed_op) {
3730 alu.src[1].sel = tmp2;
3731 alu.src[1].chan = 1;
3732 } else {
3733 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3734 }
3735 alu.last = (j == 3);
3736 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3737 return r;
3738 }
3739 } else {
3740 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3741 alu.op = ALU_OP2_MULHI_UINT;
3742
3743 alu.dst.sel = tmp0;
3744 alu.dst.chan = 1;
3745 alu.dst.write = 1;
3746
3747 alu.src[0].sel = tmp0;
3748 alu.src[0].chan = 0;
3749
3750 if (signed_op) {
3751 alu.src[1].sel = tmp2;
3752 alu.src[1].chan = 1;
3753 } else {
3754 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3755 }
3756
3757 alu.last = 1;
3758 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3759 return r;
3760 }
3761
3762 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
3763 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3764 alu.op = ALU_OP3_CNDE_INT;
3765 alu.is_op3 = 1;
3766
3767 alu.dst.sel = tmp0;
3768 alu.dst.chan = 2;
3769 alu.dst.write = 1;
3770
3771 alu.src[0].sel = tmp0;
3772 alu.src[0].chan = 1;
3773 alu.src[1].sel = tmp0;
3774 alu.src[1].chan = 3;
3775 alu.src[2].sel = tmp0;
3776 alu.src[2].chan = 2;
3777
3778 alu.last = 1;
3779 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3780 return r;
3781
3782 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
3783 if (ctx->bc->chip_class == CAYMAN) {
3784 for (j = 0 ; j < 4; j++) {
3785 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3786 alu.op = ALU_OP2_MULHI_UINT;
3787
3788 alu.dst.sel = tmp0;
3789 alu.dst.chan = j;
3790 alu.dst.write = (j == 3);
3791
3792 alu.src[0].sel = tmp0;
3793 alu.src[0].chan = 2;
3794
3795 alu.src[1].sel = tmp0;
3796 alu.src[1].chan = 0;
3797
3798 alu.last = (j == 3);
3799 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3800 return r;
3801 }
3802 } else {
3803 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3804 alu.op = ALU_OP2_MULHI_UINT;
3805
3806 alu.dst.sel = tmp0;
3807 alu.dst.chan = 3;
3808 alu.dst.write = 1;
3809
3810 alu.src[0].sel = tmp0;
3811 alu.src[0].chan = 2;
3812
3813 alu.src[1].sel = tmp0;
3814 alu.src[1].chan = 0;
3815
3816 alu.last = 1;
3817 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3818 return r;
3819 }
3820
3821 /* 7. tmp1.x = tmp0.x - tmp0.w */
3822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3823 alu.op = ALU_OP2_SUB_INT;
3824
3825 alu.dst.sel = tmp1;
3826 alu.dst.chan = 0;
3827 alu.dst.write = 1;
3828
3829 alu.src[0].sel = tmp0;
3830 alu.src[0].chan = 0;
3831 alu.src[1].sel = tmp0;
3832 alu.src[1].chan = 3;
3833
3834 alu.last = 1;
3835 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3836 return r;
3837
3838 /* 8. tmp1.y = tmp0.x + tmp0.w */
3839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3840 alu.op = ALU_OP2_ADD_INT;
3841
3842 alu.dst.sel = tmp1;
3843 alu.dst.chan = 1;
3844 alu.dst.write = 1;
3845
3846 alu.src[0].sel = tmp0;
3847 alu.src[0].chan = 0;
3848 alu.src[1].sel = tmp0;
3849 alu.src[1].chan = 3;
3850
3851 alu.last = 1;
3852 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3853 return r;
3854
3855 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3857 alu.op = ALU_OP3_CNDE_INT;
3858 alu.is_op3 = 1;
3859
3860 alu.dst.sel = tmp0;
3861 alu.dst.chan = 0;
3862 alu.dst.write = 1;
3863
3864 alu.src[0].sel = tmp0;
3865 alu.src[0].chan = 1;
3866 alu.src[1].sel = tmp1;
3867 alu.src[1].chan = 1;
3868 alu.src[2].sel = tmp1;
3869 alu.src[2].chan = 0;
3870
3871 alu.last = 1;
3872 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3873 return r;
3874
3875 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3876 if (ctx->bc->chip_class == CAYMAN) {
3877 for (j = 0 ; j < 4; j++) {
3878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3879 alu.op = ALU_OP2_MULHI_UINT;
3880
3881 alu.dst.sel = tmp0;
3882 alu.dst.chan = j;
3883 alu.dst.write = (j == 2);
3884
3885 alu.src[0].sel = tmp0;
3886 alu.src[0].chan = 0;
3887
3888 if (signed_op) {
3889 alu.src[1].sel = tmp2;
3890 alu.src[1].chan = 0;
3891 } else {
3892 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3893 }
3894
3895 alu.last = (j == 3);
3896 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3897 return r;
3898 }
3899 } else {
3900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3901 alu.op = ALU_OP2_MULHI_UINT;
3902
3903 alu.dst.sel = tmp0;
3904 alu.dst.chan = 2;
3905 alu.dst.write = 1;
3906
3907 alu.src[0].sel = tmp0;
3908 alu.src[0].chan = 0;
3909
3910 if (signed_op) {
3911 alu.src[1].sel = tmp2;
3912 alu.src[1].chan = 0;
3913 } else {
3914 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3915 }
3916
3917 alu.last = 1;
3918 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3919 return r;
3920 }
3921
3922 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3923 if (ctx->bc->chip_class == CAYMAN) {
3924 for (j = 0 ; j < 4; j++) {
3925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3926 alu.op = ALU_OP2_MULLO_UINT;
3927
3928 alu.dst.sel = tmp0;
3929 alu.dst.chan = j;
3930 alu.dst.write = (j == 1);
3931
3932 if (signed_op) {
3933 alu.src[0].sel = tmp2;
3934 alu.src[0].chan = 1;
3935 } else {
3936 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3937 }
3938
3939 alu.src[1].sel = tmp0;
3940 alu.src[1].chan = 2;
3941
3942 alu.last = (j == 3);
3943 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3944 return r;
3945 }
3946 } else {
3947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3948 alu.op = ALU_OP2_MULLO_UINT;
3949
3950 alu.dst.sel = tmp0;
3951 alu.dst.chan = 1;
3952 alu.dst.write = 1;
3953
3954 if (signed_op) {
3955 alu.src[0].sel = tmp2;
3956 alu.src[0].chan = 1;
3957 } else {
3958 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3959 }
3960
3961 alu.src[1].sel = tmp0;
3962 alu.src[1].chan = 2;
3963
3964 alu.last = 1;
3965 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3966 return r;
3967 }
3968
3969 /* 12. tmp0.w = src1 - tmp0.y = r */
3970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3971 alu.op = ALU_OP2_SUB_INT;
3972
3973 alu.dst.sel = tmp0;
3974 alu.dst.chan = 3;
3975 alu.dst.write = 1;
3976
3977 if (signed_op) {
3978 alu.src[0].sel = tmp2;
3979 alu.src[0].chan = 0;
3980 } else {
3981 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3982 }
3983
3984 alu.src[1].sel = tmp0;
3985 alu.src[1].chan = 1;
3986
3987 alu.last = 1;
3988 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3989 return r;
3990
3991 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3993 alu.op = ALU_OP2_SETGE_UINT;
3994
3995 alu.dst.sel = tmp1;
3996 alu.dst.chan = 0;
3997 alu.dst.write = 1;
3998
3999 alu.src[0].sel = tmp0;
4000 alu.src[0].chan = 3;
4001 if (signed_op) {
4002 alu.src[1].sel = tmp2;
4003 alu.src[1].chan = 1;
4004 } else {
4005 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4006 }
4007
4008 alu.last = 1;
4009 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4010 return r;
4011
4012 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
4013 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4014 alu.op = ALU_OP2_SETGE_UINT;
4015
4016 alu.dst.sel = tmp1;
4017 alu.dst.chan = 1;
4018 alu.dst.write = 1;
4019
4020 if (signed_op) {
4021 alu.src[0].sel = tmp2;
4022 alu.src[0].chan = 0;
4023 } else {
4024 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4025 }
4026
4027 alu.src[1].sel = tmp0;
4028 alu.src[1].chan = 1;
4029
4030 alu.last = 1;
4031 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4032 return r;
4033
4034 if (mod) { /* UMOD */
4035
4036 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
4037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4038 alu.op = ALU_OP2_SUB_INT;
4039
4040 alu.dst.sel = tmp1;
4041 alu.dst.chan = 2;
4042 alu.dst.write = 1;
4043
4044 alu.src[0].sel = tmp0;
4045 alu.src[0].chan = 3;
4046
4047 if (signed_op) {
4048 alu.src[1].sel = tmp2;
4049 alu.src[1].chan = 1;
4050 } else {
4051 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4052 }
4053
4054 alu.last = 1;
4055 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4056 return r;
4057
4058 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
4059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4060 alu.op = ALU_OP2_ADD_INT;
4061
4062 alu.dst.sel = tmp1;
4063 alu.dst.chan = 3;
4064 alu.dst.write = 1;
4065
4066 alu.src[0].sel = tmp0;
4067 alu.src[0].chan = 3;
4068 if (signed_op) {
4069 alu.src[1].sel = tmp2;
4070 alu.src[1].chan = 1;
4071 } else {
4072 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4073 }
4074
4075 alu.last = 1;
4076 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4077 return r;
4078
4079 } else { /* UDIV */
4080
4081 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
4082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4083 alu.op = ALU_OP2_ADD_INT;
4084
4085 alu.dst.sel = tmp1;
4086 alu.dst.chan = 2;
4087 alu.dst.write = 1;
4088
4089 alu.src[0].sel = tmp0;
4090 alu.src[0].chan = 2;
4091 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4092
4093 alu.last = 1;
4094 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4095 return r;
4096
4097 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
4098 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4099 alu.op = ALU_OP2_ADD_INT;
4100
4101 alu.dst.sel = tmp1;
4102 alu.dst.chan = 3;
4103 alu.dst.write = 1;
4104
4105 alu.src[0].sel = tmp0;
4106 alu.src[0].chan = 2;
4107 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
4108
4109 alu.last = 1;
4110 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4111 return r;
4112
4113 }
4114
4115 /* 17. tmp1.x = tmp1.x & tmp1.y */
4116 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4117 alu.op = ALU_OP2_AND_INT;
4118
4119 alu.dst.sel = tmp1;
4120 alu.dst.chan = 0;
4121 alu.dst.write = 1;
4122
4123 alu.src[0].sel = tmp1;
4124 alu.src[0].chan = 0;
4125 alu.src[1].sel = tmp1;
4126 alu.src[1].chan = 1;
4127
4128 alu.last = 1;
4129 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4130 return r;
4131
4132 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
4133 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
4134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4135 alu.op = ALU_OP3_CNDE_INT;
4136 alu.is_op3 = 1;
4137
4138 alu.dst.sel = tmp0;
4139 alu.dst.chan = 2;
4140 alu.dst.write = 1;
4141
4142 alu.src[0].sel = tmp1;
4143 alu.src[0].chan = 0;
4144 alu.src[1].sel = tmp0;
4145 alu.src[1].chan = mod ? 3 : 2;
4146 alu.src[2].sel = tmp1;
4147 alu.src[2].chan = 2;
4148
4149 alu.last = 1;
4150 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4151 return r;
4152
4153 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
4154 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4155 alu.op = ALU_OP3_CNDE_INT;
4156 alu.is_op3 = 1;
4157
4158 if (signed_op) {
4159 alu.dst.sel = tmp0;
4160 alu.dst.chan = 2;
4161 alu.dst.write = 1;
4162 } else {
4163 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4164 }
4165
4166 alu.src[0].sel = tmp1;
4167 alu.src[0].chan = 1;
4168 alu.src[1].sel = tmp1;
4169 alu.src[1].chan = 3;
4170 alu.src[2].sel = tmp0;
4171 alu.src[2].chan = 2;
4172
4173 alu.last = 1;
4174 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4175 return r;
4176
4177 if (signed_op) {
4178
4179 /* fix the sign of the result */
4180
4181 if (mod) {
4182
4183 /* tmp0.x = -tmp0.z */
4184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4185 alu.op = ALU_OP2_SUB_INT;
4186
4187 alu.dst.sel = tmp0;
4188 alu.dst.chan = 0;
4189 alu.dst.write = 1;
4190
4191 alu.src[0].sel = V_SQ_ALU_SRC_0;
4192 alu.src[1].sel = tmp0;
4193 alu.src[1].chan = 2;
4194
4195 alu.last = 1;
4196 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4197 return r;
4198
4199 /* sign of the remainder is the same as the sign of src0 */
4200 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
4201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4202 alu.op = ALU_OP3_CNDGE_INT;
4203 alu.is_op3 = 1;
4204
4205 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4206
4207 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4208 alu.src[1].sel = tmp0;
4209 alu.src[1].chan = 2;
4210 alu.src[2].sel = tmp0;
4211 alu.src[2].chan = 0;
4212
4213 alu.last = 1;
4214 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4215 return r;
4216
4217 } else {
4218
4219 /* tmp0.x = -tmp0.z */
4220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4221 alu.op = ALU_OP2_SUB_INT;
4222
4223 alu.dst.sel = tmp0;
4224 alu.dst.chan = 0;
4225 alu.dst.write = 1;
4226
4227 alu.src[0].sel = V_SQ_ALU_SRC_0;
4228 alu.src[1].sel = tmp0;
4229 alu.src[1].chan = 2;
4230
4231 alu.last = 1;
4232 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4233 return r;
4234
4235 /* fix the quotient sign (same as the sign of src0*src1) */
4236 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
4237 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4238 alu.op = ALU_OP3_CNDGE_INT;
4239 alu.is_op3 = 1;
4240
4241 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4242
4243 alu.src[0].sel = tmp2;
4244 alu.src[0].chan = 2;
4245 alu.src[1].sel = tmp0;
4246 alu.src[1].chan = 2;
4247 alu.src[2].sel = tmp0;
4248 alu.src[2].chan = 0;
4249
4250 alu.last = 1;
4251 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4252 return r;
4253 }
4254 }
4255 }
4256 return 0;
4257 }
4258
4259 static int tgsi_udiv(struct r600_shader_ctx *ctx)
4260 {
4261 return tgsi_divmod(ctx, 0, 0);
4262 }
4263
4264 static int tgsi_umod(struct r600_shader_ctx *ctx)
4265 {
4266 return tgsi_divmod(ctx, 1, 0);
4267 }
4268
4269 static int tgsi_idiv(struct r600_shader_ctx *ctx)
4270 {
4271 return tgsi_divmod(ctx, 0, 1);
4272 }
4273
4274 static int tgsi_imod(struct r600_shader_ctx *ctx)
4275 {
4276 return tgsi_divmod(ctx, 1, 1);
4277 }
4278
4279
4280 static int tgsi_f2i(struct r600_shader_ctx *ctx)
4281 {
4282 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4283 struct r600_bytecode_alu alu;
4284 int i, r;
4285 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4286 int last_inst = tgsi_last_instruction(write_mask);
4287
4288 for (i = 0; i < 4; i++) {
4289 if (!(write_mask & (1<<i)))
4290 continue;
4291
4292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4293 alu.op = ALU_OP1_TRUNC;
4294
4295 alu.dst.sel = ctx->temp_reg;
4296 alu.dst.chan = i;
4297 alu.dst.write = 1;
4298
4299 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4300 if (i == last_inst)
4301 alu.last = 1;
4302 r = r600_bytecode_add_alu(ctx->bc, &alu);
4303 if (r)
4304 return r;
4305 }
4306
4307 for (i = 0; i < 4; i++) {
4308 if (!(write_mask & (1<<i)))
4309 continue;
4310
4311 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4312 alu.op = ctx->inst_info->op;
4313
4314 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4315
4316 alu.src[0].sel = ctx->temp_reg;
4317 alu.src[0].chan = i;
4318
4319 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
4320 alu.last = 1;
4321 r = r600_bytecode_add_alu(ctx->bc, &alu);
4322 if (r)
4323 return r;
4324 }
4325
4326 return 0;
4327 }
4328
4329 static int tgsi_iabs(struct r600_shader_ctx *ctx)
4330 {
4331 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4332 struct r600_bytecode_alu alu;
4333 int i, r;
4334 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4335 int last_inst = tgsi_last_instruction(write_mask);
4336
4337 /* tmp = -src */
4338 for (i = 0; i < 4; i++) {
4339 if (!(write_mask & (1<<i)))
4340 continue;
4341
4342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4343 alu.op = ALU_OP2_SUB_INT;
4344
4345 alu.dst.sel = ctx->temp_reg;
4346 alu.dst.chan = i;
4347 alu.dst.write = 1;
4348
4349 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4350 alu.src[0].sel = V_SQ_ALU_SRC_0;
4351
4352 if (i == last_inst)
4353 alu.last = 1;
4354 r = r600_bytecode_add_alu(ctx->bc, &alu);
4355 if (r)
4356 return r;
4357 }
4358
4359 /* dst = (src >= 0 ? src : tmp) */
4360 for (i = 0; i < 4; i++) {
4361 if (!(write_mask & (1<<i)))
4362 continue;
4363
4364 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4365 alu.op = ALU_OP3_CNDGE_INT;
4366 alu.is_op3 = 1;
4367 alu.dst.write = 1;
4368
4369 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4370
4371 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4372 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4373 alu.src[2].sel = ctx->temp_reg;
4374 alu.src[2].chan = i;
4375
4376 if (i == last_inst)
4377 alu.last = 1;
4378 r = r600_bytecode_add_alu(ctx->bc, &alu);
4379 if (r)
4380 return r;
4381 }
4382 return 0;
4383 }
4384
4385 static int tgsi_issg(struct r600_shader_ctx *ctx)
4386 {
4387 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4388 struct r600_bytecode_alu alu;
4389 int i, r;
4390 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4391 int last_inst = tgsi_last_instruction(write_mask);
4392
4393 /* tmp = (src >= 0 ? src : -1) */
4394 for (i = 0; i < 4; i++) {
4395 if (!(write_mask & (1<<i)))
4396 continue;
4397
4398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4399 alu.op = ALU_OP3_CNDGE_INT;
4400 alu.is_op3 = 1;
4401
4402 alu.dst.sel = ctx->temp_reg;
4403 alu.dst.chan = i;
4404 alu.dst.write = 1;
4405
4406 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4407 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4408 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
4409
4410 if (i == last_inst)
4411 alu.last = 1;
4412 r = r600_bytecode_add_alu(ctx->bc, &alu);
4413 if (r)
4414 return r;
4415 }
4416
4417 /* dst = (tmp > 0 ? 1 : tmp) */
4418 for (i = 0; i < 4; i++) {
4419 if (!(write_mask & (1<<i)))
4420 continue;
4421
4422 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4423 alu.op = ALU_OP3_CNDGT_INT;
4424 alu.is_op3 = 1;
4425 alu.dst.write = 1;
4426
4427 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4428
4429 alu.src[0].sel = ctx->temp_reg;
4430 alu.src[0].chan = i;
4431
4432 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4433
4434 alu.src[2].sel = ctx->temp_reg;
4435 alu.src[2].chan = i;
4436
4437 if (i == last_inst)
4438 alu.last = 1;
4439 r = r600_bytecode_add_alu(ctx->bc, &alu);
4440 if (r)
4441 return r;
4442 }
4443 return 0;
4444 }
4445
4446
4447
4448 static int tgsi_ssg(struct r600_shader_ctx *ctx)
4449 {
4450 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4451 struct r600_bytecode_alu alu;
4452 int i, r;
4453
4454 /* tmp = (src > 0 ? 1 : src) */
4455 for (i = 0; i < 4; i++) {
4456 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4457 alu.op = ALU_OP3_CNDGT;
4458 alu.is_op3 = 1;
4459
4460 alu.dst.sel = ctx->temp_reg;
4461 alu.dst.chan = i;
4462
4463 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4464 alu.src[1].sel = V_SQ_ALU_SRC_1;
4465 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
4466
4467 if (i == 3)
4468 alu.last = 1;
4469 r = r600_bytecode_add_alu(ctx->bc, &alu);
4470 if (r)
4471 return r;
4472 }
4473
4474 /* dst = (-tmp > 0 ? -1 : tmp) */
4475 for (i = 0; i < 4; i++) {
4476 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4477 alu.op = ALU_OP3_CNDGT;
4478 alu.is_op3 = 1;
4479 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4480
4481 alu.src[0].sel = ctx->temp_reg;
4482 alu.src[0].chan = i;
4483 alu.src[0].neg = 1;
4484
4485 alu.src[1].sel = V_SQ_ALU_SRC_1;
4486 alu.src[1].neg = 1;
4487
4488 alu.src[2].sel = ctx->temp_reg;
4489 alu.src[2].chan = i;
4490
4491 if (i == 3)
4492 alu.last = 1;
4493 r = r600_bytecode_add_alu(ctx->bc, &alu);
4494 if (r)
4495 return r;
4496 }
4497 return 0;
4498 }
4499
4500 static int tgsi_bfi(struct r600_shader_ctx *ctx)
4501 {
4502 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4503 struct r600_bytecode_alu alu;
4504 int i, r, t1, t2;
4505
4506 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4507 int last_inst = tgsi_last_instruction(write_mask);
4508
4509 t1 = ctx->temp_reg;
4510
4511 for (i = 0; i < 4; i++) {
4512 if (!(write_mask & (1<<i)))
4513 continue;
4514
4515 /* create mask tmp */
4516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4517 alu.op = ALU_OP2_BFM_INT;
4518 alu.dst.sel = t1;
4519 alu.dst.chan = i;
4520 alu.dst.write = 1;
4521 alu.last = i == last_inst;
4522
4523 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
4524 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4525
4526 r = r600_bytecode_add_alu(ctx->bc, &alu);
4527 if (r)
4528 return r;
4529 }
4530
4531 t2 = r600_get_temp(ctx);
4532
4533 for (i = 0; i < 4; i++) {
4534 if (!(write_mask & (1<<i)))
4535 continue;
4536
4537 /* shift insert left */
4538 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4539 alu.op = ALU_OP2_LSHL_INT;
4540 alu.dst.sel = t2;
4541 alu.dst.chan = i;
4542 alu.dst.write = 1;
4543 alu.last = i == last_inst;
4544
4545 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4546 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4547
4548 r = r600_bytecode_add_alu(ctx->bc, &alu);
4549 if (r)
4550 return r;
4551 }
4552
4553 for (i = 0; i < 4; i++) {
4554 if (!(write_mask & (1<<i)))
4555 continue;
4556
4557 /* actual bitfield insert */
4558 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4559 alu.op = ALU_OP3_BFI_INT;
4560 alu.is_op3 = 1;
4561 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4562 alu.dst.chan = i;
4563 alu.dst.write = 1;
4564 alu.last = i == last_inst;
4565
4566 alu.src[0].sel = t1;
4567 alu.src[0].chan = i;
4568 alu.src[1].sel = t2;
4569 alu.src[1].chan = i;
4570 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
4571
4572 r = r600_bytecode_add_alu(ctx->bc, &alu);
4573 if (r)
4574 return r;
4575 }
4576
4577 return 0;
4578 }
4579
4580 static int tgsi_msb(struct r600_shader_ctx *ctx)
4581 {
4582 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4583 struct r600_bytecode_alu alu;
4584 int i, r, t1, t2;
4585
4586 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4587 int last_inst = tgsi_last_instruction(write_mask);
4588
4589 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
4590 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
4591
4592 t1 = ctx->temp_reg;
4593
4594 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
4595 for (i = 0; i < 4; i++) {
4596 if (!(write_mask & (1<<i)))
4597 continue;
4598
4599 /* t1 = FFBH_INT / FFBH_UINT */
4600 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4601 alu.op = ctx->inst_info->op;
4602 alu.dst.sel = t1;
4603 alu.dst.chan = i;
4604 alu.dst.write = 1;
4605 alu.last = i == last_inst;
4606
4607 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4608
4609 r = r600_bytecode_add_alu(ctx->bc, &alu);
4610 if (r)
4611 return r;
4612 }
4613
4614 t2 = r600_get_temp(ctx);
4615
4616 for (i = 0; i < 4; i++) {
4617 if (!(write_mask & (1<<i)))
4618 continue;
4619
4620 /* t2 = 31 - t1 */
4621 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4622 alu.op = ALU_OP2_SUB_INT;
4623 alu.dst.sel = t2;
4624 alu.dst.chan = i;
4625 alu.dst.write = 1;
4626 alu.last = i == last_inst;
4627
4628 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4629 alu.src[0].value = 31;
4630 alu.src[1].sel = t1;
4631 alu.src[1].chan = i;
4632
4633 r = r600_bytecode_add_alu(ctx->bc, &alu);
4634 if (r)
4635 return r;
4636 }
4637
4638 for (i = 0; i < 4; i++) {
4639 if (!(write_mask & (1<<i)))
4640 continue;
4641
4642 /* result = t1 >= 0 ? t2 : t1 */
4643 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4644 alu.op = ALU_OP3_CNDGE_INT;
4645 alu.is_op3 = 1;
4646 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4647 alu.dst.chan = i;
4648 alu.dst.write = 1;
4649 alu.last = i == last_inst;
4650
4651 alu.src[0].sel = t1;
4652 alu.src[0].chan = i;
4653 alu.src[1].sel = t2;
4654 alu.src[1].chan = i;
4655 alu.src[2].sel = t1;
4656 alu.src[2].chan = i;
4657
4658 r = r600_bytecode_add_alu(ctx->bc, &alu);
4659 if (r)
4660 return r;
4661 }
4662
4663 return 0;
4664 }
4665
4666 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
4667 {
4668 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4669 struct r600_bytecode_alu alu;
4670 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
4671 unsigned location;
4672 int input;
4673
4674 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
4675
4676 input = inst->Src[0].Register.Index;
4677
4678 /* Interpolators have been marked for use already by allocate_system_value_inputs */
4679 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4680 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4681 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
4682 }
4683 else {
4684 location = TGSI_INTERPOLATE_LOC_CENTROID;
4685 }
4686
4687 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
4688 if (k < 0)
4689 k = 0;
4690 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
4691 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
4692
4693 /* NOTE: currently offset is not perspective correct */
4694 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4695 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4696 int sample_gpr = -1;
4697 int gradientsH, gradientsV;
4698 struct r600_bytecode_tex tex;
4699
4700 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4701 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
4702 }
4703
4704 gradientsH = r600_get_temp(ctx);
4705 gradientsV = r600_get_temp(ctx);
4706 for (i = 0; i < 2; i++) {
4707 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4708 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
4709 tex.src_gpr = interp_gpr;
4710 tex.src_sel_x = interp_base_chan + 0;
4711 tex.src_sel_y = interp_base_chan + 1;
4712 tex.src_sel_z = 0;
4713 tex.src_sel_w = 0;
4714 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
4715 tex.dst_sel_x = 0;
4716 tex.dst_sel_y = 1;
4717 tex.dst_sel_z = 7;
4718 tex.dst_sel_w = 7;
4719 tex.inst_mod = 1; // Use per pixel gradient calculation
4720 tex.sampler_id = 0;
4721 tex.resource_id = tex.sampler_id;
4722 r = r600_bytecode_add_tex(ctx->bc, &tex);
4723 if (r)
4724 return r;
4725 }
4726
4727 for (i = 0; i < 2; i++) {
4728 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4729 alu.op = ALU_OP3_MULADD;
4730 alu.is_op3 = 1;
4731 alu.src[0].sel = gradientsH;
4732 alu.src[0].chan = i;
4733 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4734 alu.src[1].sel = sample_gpr;
4735 alu.src[1].chan = 2;
4736 }
4737 else {
4738 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
4739 }
4740 alu.src[2].sel = interp_gpr;
4741 alu.src[2].chan = interp_base_chan + i;
4742 alu.dst.sel = ctx->temp_reg;
4743 alu.dst.chan = i;
4744 alu.last = i == 1;
4745
4746 r = r600_bytecode_add_alu(ctx->bc, &alu);
4747 if (r)
4748 return r;
4749 }
4750
4751 for (i = 0; i < 2; i++) {
4752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4753 alu.op = ALU_OP3_MULADD;
4754 alu.is_op3 = 1;
4755 alu.src[0].sel = gradientsV;
4756 alu.src[0].chan = i;
4757 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4758 alu.src[1].sel = sample_gpr;
4759 alu.src[1].chan = 3;
4760 }
4761 else {
4762 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
4763 }
4764 alu.src[2].sel = ctx->temp_reg;
4765 alu.src[2].chan = i;
4766 alu.dst.sel = ctx->temp_reg;
4767 alu.dst.chan = i;
4768 alu.last = i == 1;
4769
4770 r = r600_bytecode_add_alu(ctx->bc, &alu);
4771 if (r)
4772 return r;
4773 }
4774 }
4775
4776 tmp = r600_get_temp(ctx);
4777 for (i = 0; i < 8; i++) {
4778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4779 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
4780
4781 alu.dst.sel = tmp;
4782 if ((i > 1 && i < 6)) {
4783 alu.dst.write = 1;
4784 }
4785 else {
4786 alu.dst.write = 0;
4787 }
4788 alu.dst.chan = i % 4;
4789
4790 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4791 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4792 alu.src[0].sel = ctx->temp_reg;
4793 alu.src[0].chan = 1 - (i % 2);
4794 } else {
4795 alu.src[0].sel = interp_gpr;
4796 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
4797 }
4798 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
4799 alu.src[1].chan = 0;
4800
4801 alu.last = i % 4 == 3;
4802 alu.bank_swizzle_force = SQ_ALU_VEC_210;
4803
4804 r = r600_bytecode_add_alu(ctx->bc, &alu);
4805 if (r)
4806 return r;
4807 }
4808
4809 // INTERP can't swizzle dst
4810 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4811 for (i = 0; i <= lasti; i++) {
4812 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4813 continue;
4814
4815 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4816 alu.op = ALU_OP1_MOV;
4817 alu.src[0].sel = tmp;
4818 alu.src[0].chan = ctx->src[0].swizzle[i];
4819 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4820 alu.dst.write = 1;
4821 alu.last = i == lasti;
4822 r = r600_bytecode_add_alu(ctx->bc, &alu);
4823 if (r)
4824 return r;
4825 }
4826
4827 return 0;
4828 }
4829
4830
4831 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
4832 {
4833 struct r600_bytecode_alu alu;
4834 int i, r;
4835
4836 for (i = 0; i < 4; i++) {
4837 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4838 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
4839 alu.op = ALU_OP0_NOP;
4840 alu.dst.chan = i;
4841 } else {
4842 alu.op = ALU_OP1_MOV;
4843 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4844 alu.src[0].sel = ctx->temp_reg;
4845 alu.src[0].chan = i;
4846 }
4847 if (i == 3) {
4848 alu.last = 1;
4849 }
4850 r = r600_bytecode_add_alu(ctx->bc, &alu);
4851 if (r)
4852 return r;
4853 }
4854 return 0;
4855 }
4856
4857 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
4858 unsigned temp, int chan,
4859 struct r600_bytecode_alu_src *bc_src,
4860 const struct r600_shader_src *shader_src)
4861 {
4862 struct r600_bytecode_alu alu;
4863 int r;
4864
4865 r600_bytecode_src(bc_src, shader_src, chan);
4866
4867 /* op3 operands don't support abs modifier */
4868 if (bc_src->abs) {
4869 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
4870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4871 alu.op = ALU_OP1_MOV;
4872 alu.dst.sel = temp;
4873 alu.dst.chan = chan;
4874 alu.dst.write = 1;
4875
4876 alu.src[0] = *bc_src;
4877 alu.last = true; // sufficient?
4878 r = r600_bytecode_add_alu(ctx->bc, &alu);
4879 if (r)
4880 return r;
4881
4882 memset(bc_src, 0, sizeof(*bc_src));
4883 bc_src->sel = temp;
4884 bc_src->chan = chan;
4885 }
4886 return 0;
4887 }
4888
4889 static int tgsi_op3(struct r600_shader_ctx *ctx)
4890 {
4891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4892 struct r600_bytecode_alu alu;
4893 int i, j, r;
4894 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4895 int temp_regs[4];
4896
4897 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4898 temp_regs[j] = 0;
4899 if (ctx->src[j].abs)
4900 temp_regs[j] = r600_get_temp(ctx);
4901 }
4902 for (i = 0; i < lasti + 1; i++) {
4903 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4904 continue;
4905
4906 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4907 alu.op = ctx->inst_info->op;
4908 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4909 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
4910 if (r)
4911 return r;
4912 }
4913
4914 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4915 alu.dst.chan = i;
4916 alu.dst.write = 1;
4917 alu.is_op3 = 1;
4918 if (i == lasti) {
4919 alu.last = 1;
4920 }
4921 r = r600_bytecode_add_alu(ctx->bc, &alu);
4922 if (r)
4923 return r;
4924 }
4925 return 0;
4926 }
4927
4928 static int tgsi_dp(struct r600_shader_ctx *ctx)
4929 {
4930 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4931 struct r600_bytecode_alu alu;
4932 int i, j, r;
4933
4934 for (i = 0; i < 4; i++) {
4935 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4936 alu.op = ctx->inst_info->op;
4937 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4938 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4939 }
4940
4941 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4942 alu.dst.chan = i;
4943 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4944 /* handle some special cases */
4945 switch (inst->Instruction.Opcode) {
4946 case TGSI_OPCODE_DP2:
4947 if (i > 1) {
4948 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
4949 alu.src[0].chan = alu.src[1].chan = 0;
4950 }
4951 break;
4952 case TGSI_OPCODE_DP3:
4953 if (i > 2) {
4954 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
4955 alu.src[0].chan = alu.src[1].chan = 0;
4956 }
4957 break;
4958 case TGSI_OPCODE_DPH:
4959 if (i == 3) {
4960 alu.src[0].sel = V_SQ_ALU_SRC_1;
4961 alu.src[0].chan = 0;
4962 alu.src[0].neg = 0;
4963 }
4964 break;
4965 default:
4966 break;
4967 }
4968 if (i == 3) {
4969 alu.last = 1;
4970 }
4971 r = r600_bytecode_add_alu(ctx->bc, &alu);
4972 if (r)
4973 return r;
4974 }
4975 return 0;
4976 }
4977
4978 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
4979 unsigned index)
4980 {
4981 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4982 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
4983 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
4984 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
4985 ctx->src[index].neg || ctx->src[index].abs ||
4986 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
4987 }
4988
4989 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
4990 unsigned index)
4991 {
4992 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4993 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
4994 }
4995
4996 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
4997 {
4998 struct r600_bytecode_vtx vtx;
4999 struct r600_bytecode_alu alu;
5000 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5001 int src_gpr, r, i;
5002 int id = tgsi_tex_get_src_gpr(ctx, 1);
5003
5004 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5005 if (src_requires_loading) {
5006 for (i = 0; i < 4; i++) {
5007 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5008 alu.op = ALU_OP1_MOV;
5009 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5010 alu.dst.sel = ctx->temp_reg;
5011 alu.dst.chan = i;
5012 if (i == 3)
5013 alu.last = 1;
5014 alu.dst.write = 1;
5015 r = r600_bytecode_add_alu(ctx->bc, &alu);
5016 if (r)
5017 return r;
5018 }
5019 src_gpr = ctx->temp_reg;
5020 }
5021
5022 memset(&vtx, 0, sizeof(vtx));
5023 vtx.op = FETCH_OP_VFETCH;
5024 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
5025 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
5026 vtx.src_gpr = src_gpr;
5027 vtx.mega_fetch_count = 16;
5028 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5029 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
5030 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
5031 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
5032 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
5033 vtx.use_const_fields = 1;
5034
5035 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
5036 return r;
5037
5038 if (ctx->bc->chip_class >= EVERGREEN)
5039 return 0;
5040
5041 for (i = 0; i < 4; i++) {
5042 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5043 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5044 continue;
5045
5046 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5047 alu.op = ALU_OP2_AND_INT;
5048
5049 alu.dst.chan = i;
5050 alu.dst.sel = vtx.dst_gpr;
5051 alu.dst.write = 1;
5052
5053 alu.src[0].sel = vtx.dst_gpr;
5054 alu.src[0].chan = i;
5055
5056 alu.src[1].sel = 512 + (id * 2);
5057 alu.src[1].chan = i % 4;
5058 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5059
5060 if (i == lasti)
5061 alu.last = 1;
5062 r = r600_bytecode_add_alu(ctx->bc, &alu);
5063 if (r)
5064 return r;
5065 }
5066
5067 if (inst->Dst[0].Register.WriteMask & 3) {
5068 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5069 alu.op = ALU_OP2_OR_INT;
5070
5071 alu.dst.chan = 3;
5072 alu.dst.sel = vtx.dst_gpr;
5073 alu.dst.write = 1;
5074
5075 alu.src[0].sel = vtx.dst_gpr;
5076 alu.src[0].chan = 3;
5077
5078 alu.src[1].sel = 512 + (id * 2) + 1;
5079 alu.src[1].chan = 0;
5080 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5081
5082 alu.last = 1;
5083 r = r600_bytecode_add_alu(ctx->bc, &alu);
5084 if (r)
5085 return r;
5086 }
5087 return 0;
5088 }
5089
5090 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
5091 {
5092 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5093 struct r600_bytecode_alu alu;
5094 int r;
5095 int id = tgsi_tex_get_src_gpr(ctx, 1);
5096
5097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5098 alu.op = ALU_OP1_MOV;
5099
5100 if (ctx->bc->chip_class >= EVERGREEN) {
5101 /* channel 0 or 2 of each word */
5102 alu.src[0].sel = 512 + (id / 2);
5103 alu.src[0].chan = (id % 2) * 2;
5104 } else {
5105 /* r600 we have them at channel 2 of the second dword */
5106 alu.src[0].sel = 512 + (id * 2) + 1;
5107 alu.src[0].chan = 1;
5108 }
5109 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5110 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5111 alu.last = 1;
5112 r = r600_bytecode_add_alu(ctx->bc, &alu);
5113 if (r)
5114 return r;
5115 return 0;
5116 }
5117
5118 static int tgsi_tex(struct r600_shader_ctx *ctx)
5119 {
5120 static float one_point_five = 1.5f;
5121 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5122 struct r600_bytecode_tex tex;
5123 struct r600_bytecode_alu alu;
5124 unsigned src_gpr;
5125 int r, i, j;
5126 int opcode;
5127 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
5128 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5129 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
5130 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
5131
5132 bool txf_add_offsets = inst->Texture.NumOffsets &&
5133 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5134 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
5135
5136 /* Texture fetch instructions can only use gprs as source.
5137 * Also they cannot negate the source or take the absolute value */
5138 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
5139 tgsi_tex_src_requires_loading(ctx, 0)) ||
5140 read_compressed_msaa || txf_add_offsets;
5141
5142 boolean src_loaded = FALSE;
5143 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
5144 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
5145 boolean has_txq_cube_array_z = false;
5146 unsigned sampler_index_mode;
5147
5148 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
5149 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5150 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
5151 if (inst->Dst[0].Register.WriteMask & 4) {
5152 ctx->shader->has_txq_cube_array_z_comp = true;
5153 has_txq_cube_array_z = true;
5154 }
5155
5156 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
5157 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5158 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
5159 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
5160 sampler_src_reg = 2;
5161
5162 /* TGSI moves the sampler to src reg 3 for TXD */
5163 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
5164 sampler_src_reg = 3;
5165
5166 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
5167 if (sampler_index_mode)
5168 ctx->shader->uses_index_registers = true;
5169
5170 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5171
5172 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
5173 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
5174 ctx->shader->uses_tex_buffers = true;
5175 return r600_do_buffer_txq(ctx);
5176 }
5177 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
5178 if (ctx->bc->chip_class < EVERGREEN)
5179 ctx->shader->uses_tex_buffers = true;
5180 return do_vtx_fetch_inst(ctx, src_requires_loading);
5181 }
5182 }
5183
5184 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
5185 int out_chan;
5186 /* Add perspective divide */
5187 if (ctx->bc->chip_class == CAYMAN) {
5188 out_chan = 2;
5189 for (i = 0; i < 3; i++) {
5190 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5191 alu.op = ALU_OP1_RECIP_IEEE;
5192 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5193
5194 alu.dst.sel = ctx->temp_reg;
5195 alu.dst.chan = i;
5196 if (i == 2)
5197 alu.last = 1;
5198 if (out_chan == i)
5199 alu.dst.write = 1;
5200 r = r600_bytecode_add_alu(ctx->bc, &alu);
5201 if (r)
5202 return r;
5203 }
5204
5205 } else {
5206 out_chan = 3;
5207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5208 alu.op = ALU_OP1_RECIP_IEEE;
5209 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5210
5211 alu.dst.sel = ctx->temp_reg;
5212 alu.dst.chan = out_chan;
5213 alu.last = 1;
5214 alu.dst.write = 1;
5215 r = r600_bytecode_add_alu(ctx->bc, &alu);
5216 if (r)
5217 return r;
5218 }
5219
5220 for (i = 0; i < 3; i++) {
5221 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5222 alu.op = ALU_OP2_MUL;
5223 alu.src[0].sel = ctx->temp_reg;
5224 alu.src[0].chan = out_chan;
5225 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5226 alu.dst.sel = ctx->temp_reg;
5227 alu.dst.chan = i;
5228 alu.dst.write = 1;
5229 r = r600_bytecode_add_alu(ctx->bc, &alu);
5230 if (r)
5231 return r;
5232 }
5233 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5234 alu.op = ALU_OP1_MOV;
5235 alu.src[0].sel = V_SQ_ALU_SRC_1;
5236 alu.src[0].chan = 0;
5237 alu.dst.sel = ctx->temp_reg;
5238 alu.dst.chan = 3;
5239 alu.last = 1;
5240 alu.dst.write = 1;
5241 r = r600_bytecode_add_alu(ctx->bc, &alu);
5242 if (r)
5243 return r;
5244 src_loaded = TRUE;
5245 src_gpr = ctx->temp_reg;
5246 }
5247
5248
5249 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
5250 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5251 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5252 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
5253 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
5254 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
5255
5256 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
5257 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
5258
5259 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
5260 for (i = 0; i < 4; i++) {
5261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5262 alu.op = ALU_OP2_CUBE;
5263 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5264 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
5265 alu.dst.sel = ctx->temp_reg;
5266 alu.dst.chan = i;
5267 if (i == 3)
5268 alu.last = 1;
5269 alu.dst.write = 1;
5270 r = r600_bytecode_add_alu(ctx->bc, &alu);
5271 if (r)
5272 return r;
5273 }
5274
5275 /* tmp1.z = RCP_e(|tmp1.z|) */
5276 if (ctx->bc->chip_class == CAYMAN) {
5277 for (i = 0; i < 3; i++) {
5278 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5279 alu.op = ALU_OP1_RECIP_IEEE;
5280 alu.src[0].sel = ctx->temp_reg;
5281 alu.src[0].chan = 2;
5282 alu.src[0].abs = 1;
5283 alu.dst.sel = ctx->temp_reg;
5284 alu.dst.chan = i;
5285 if (i == 2)
5286 alu.dst.write = 1;
5287 if (i == 2)
5288 alu.last = 1;
5289 r = r600_bytecode_add_alu(ctx->bc, &alu);
5290 if (r)
5291 return r;
5292 }
5293 } else {
5294 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5295 alu.op = ALU_OP1_RECIP_IEEE;
5296 alu.src[0].sel = ctx->temp_reg;
5297 alu.src[0].chan = 2;
5298 alu.src[0].abs = 1;
5299 alu.dst.sel = ctx->temp_reg;
5300 alu.dst.chan = 2;
5301 alu.dst.write = 1;
5302 alu.last = 1;
5303 r = r600_bytecode_add_alu(ctx->bc, &alu);
5304 if (r)
5305 return r;
5306 }
5307
5308 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
5309 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
5310 * muladd has no writemask, have to use another temp
5311 */
5312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5313 alu.op = ALU_OP3_MULADD;
5314 alu.is_op3 = 1;
5315
5316 alu.src[0].sel = ctx->temp_reg;
5317 alu.src[0].chan = 0;
5318 alu.src[1].sel = ctx->temp_reg;
5319 alu.src[1].chan = 2;
5320
5321 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5322 alu.src[2].chan = 0;
5323 alu.src[2].value = *(uint32_t *)&one_point_five;
5324
5325 alu.dst.sel = ctx->temp_reg;
5326 alu.dst.chan = 0;
5327 alu.dst.write = 1;
5328
5329 r = r600_bytecode_add_alu(ctx->bc, &alu);
5330 if (r)
5331 return r;
5332
5333 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5334 alu.op = ALU_OP3_MULADD;
5335 alu.is_op3 = 1;
5336
5337 alu.src[0].sel = ctx->temp_reg;
5338 alu.src[0].chan = 1;
5339 alu.src[1].sel = ctx->temp_reg;
5340 alu.src[1].chan = 2;
5341
5342 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5343 alu.src[2].chan = 0;
5344 alu.src[2].value = *(uint32_t *)&one_point_five;
5345
5346 alu.dst.sel = ctx->temp_reg;
5347 alu.dst.chan = 1;
5348 alu.dst.write = 1;
5349
5350 alu.last = 1;
5351 r = r600_bytecode_add_alu(ctx->bc, &alu);
5352 if (r)
5353 return r;
5354 /* write initial compare value into Z component
5355 - W src 0 for shadow cube
5356 - X src 1 for shadow cube array */
5357 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5358 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5360 alu.op = ALU_OP1_MOV;
5361 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
5362 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5363 else
5364 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5365 alu.dst.sel = ctx->temp_reg;
5366 alu.dst.chan = 2;
5367 alu.dst.write = 1;
5368 alu.last = 1;
5369 r = r600_bytecode_add_alu(ctx->bc, &alu);
5370 if (r)
5371 return r;
5372 }
5373
5374 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5375 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5376 if (ctx->bc->chip_class >= EVERGREEN) {
5377 int mytmp = r600_get_temp(ctx);
5378 static const float eight = 8.0f;
5379 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5380 alu.op = ALU_OP1_MOV;
5381 alu.src[0].sel = ctx->temp_reg;
5382 alu.src[0].chan = 3;
5383 alu.dst.sel = mytmp;
5384 alu.dst.chan = 0;
5385 alu.dst.write = 1;
5386 alu.last = 1;
5387 r = r600_bytecode_add_alu(ctx->bc, &alu);
5388 if (r)
5389 return r;
5390
5391 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
5392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5393 alu.op = ALU_OP3_MULADD;
5394 alu.is_op3 = 1;
5395 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5396 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5397 alu.src[1].chan = 0;
5398 alu.src[1].value = *(uint32_t *)&eight;
5399 alu.src[2].sel = mytmp;
5400 alu.src[2].chan = 0;
5401 alu.dst.sel = ctx->temp_reg;
5402 alu.dst.chan = 3;
5403 alu.dst.write = 1;
5404 alu.last = 1;
5405 r = r600_bytecode_add_alu(ctx->bc, &alu);
5406 if (r)
5407 return r;
5408 } else if (ctx->bc->chip_class < EVERGREEN) {
5409 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5410 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
5411 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5412 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5413 tex.src_gpr = r600_get_temp(ctx);
5414 tex.src_sel_x = 0;
5415 tex.src_sel_y = 0;
5416 tex.src_sel_z = 0;
5417 tex.src_sel_w = 0;
5418 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
5419 tex.coord_type_x = 1;
5420 tex.coord_type_y = 1;
5421 tex.coord_type_z = 1;
5422 tex.coord_type_w = 1;
5423 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5424 alu.op = ALU_OP1_MOV;
5425 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5426 alu.dst.sel = tex.src_gpr;
5427 alu.dst.chan = 0;
5428 alu.last = 1;
5429 alu.dst.write = 1;
5430 r = r600_bytecode_add_alu(ctx->bc, &alu);
5431 if (r)
5432 return r;
5433
5434 r = r600_bytecode_add_tex(ctx->bc, &tex);
5435 if (r)
5436 return r;
5437 }
5438
5439 }
5440
5441 /* for cube forms of lod and bias we need to route things */
5442 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
5443 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
5444 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5445 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
5446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5447 alu.op = ALU_OP1_MOV;
5448 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5449 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
5450 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5451 else
5452 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5453 alu.dst.sel = ctx->temp_reg;
5454 alu.dst.chan = 2;
5455 alu.last = 1;
5456 alu.dst.write = 1;
5457 r = r600_bytecode_add_alu(ctx->bc, &alu);
5458 if (r)
5459 return r;
5460 }
5461
5462 src_loaded = TRUE;
5463 src_gpr = ctx->temp_reg;
5464 }
5465
5466 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
5467 int temp_h = 0, temp_v = 0;
5468 int start_val = 0;
5469
5470 /* if we've already loaded the src (i.e. CUBE don't reload it). */
5471 if (src_loaded == TRUE)
5472 start_val = 1;
5473 else
5474 src_loaded = TRUE;
5475 for (i = start_val; i < 3; i++) {
5476 int treg = r600_get_temp(ctx);
5477
5478 if (i == 0)
5479 src_gpr = treg;
5480 else if (i == 1)
5481 temp_h = treg;
5482 else
5483 temp_v = treg;
5484
5485 for (j = 0; j < 4; j++) {
5486 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5487 alu.op = ALU_OP1_MOV;
5488 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
5489 alu.dst.sel = treg;
5490 alu.dst.chan = j;
5491 if (j == 3)
5492 alu.last = 1;
5493 alu.dst.write = 1;
5494 r = r600_bytecode_add_alu(ctx->bc, &alu);
5495 if (r)
5496 return r;
5497 }
5498 }
5499 for (i = 1; i < 3; i++) {
5500 /* set gradients h/v */
5501 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5502 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
5503 FETCH_OP_SET_GRADIENTS_V;
5504 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5505 tex.sampler_index_mode = sampler_index_mode;
5506 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5507 tex.resource_index_mode = sampler_index_mode;
5508
5509 tex.src_gpr = (i == 1) ? temp_h : temp_v;
5510 tex.src_sel_x = 0;
5511 tex.src_sel_y = 1;
5512 tex.src_sel_z = 2;
5513 tex.src_sel_w = 3;
5514
5515 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
5516 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
5517 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
5518 tex.coord_type_x = 1;
5519 tex.coord_type_y = 1;
5520 tex.coord_type_z = 1;
5521 tex.coord_type_w = 1;
5522 }
5523 r = r600_bytecode_add_tex(ctx->bc, &tex);
5524 if (r)
5525 return r;
5526 }
5527 }
5528
5529 if (src_requires_loading && !src_loaded) {
5530 for (i = 0; i < 4; i++) {
5531 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5532 alu.op = ALU_OP1_MOV;
5533 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5534 alu.dst.sel = ctx->temp_reg;
5535 alu.dst.chan = i;
5536 if (i == 3)
5537 alu.last = 1;
5538 alu.dst.write = 1;
5539 r = r600_bytecode_add_alu(ctx->bc, &alu);
5540 if (r)
5541 return r;
5542 }
5543 src_loaded = TRUE;
5544 src_gpr = ctx->temp_reg;
5545 }
5546
5547 /* get offset values */
5548 if (inst->Texture.NumOffsets) {
5549 assert(inst->Texture.NumOffsets == 1);
5550
5551 /* The texture offset feature doesn't work with the TXF instruction
5552 * and must be emulated by adding the offset to the texture coordinates. */
5553 if (txf_add_offsets) {
5554 const struct tgsi_texture_offset *off = inst->TexOffsets;
5555
5556 switch (inst->Texture.Texture) {
5557 case TGSI_TEXTURE_3D:
5558 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5559 alu.op = ALU_OP2_ADD_INT;
5560 alu.src[0].sel = src_gpr;
5561 alu.src[0].chan = 2;
5562 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5563 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
5564 alu.dst.sel = src_gpr;
5565 alu.dst.chan = 2;
5566 alu.dst.write = 1;
5567 alu.last = 1;
5568 r = r600_bytecode_add_alu(ctx->bc, &alu);
5569 if (r)
5570 return r;
5571 /* fall through */
5572
5573 case TGSI_TEXTURE_2D:
5574 case TGSI_TEXTURE_SHADOW2D:
5575 case TGSI_TEXTURE_RECT:
5576 case TGSI_TEXTURE_SHADOWRECT:
5577 case TGSI_TEXTURE_2D_ARRAY:
5578 case TGSI_TEXTURE_SHADOW2D_ARRAY:
5579 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5580 alu.op = ALU_OP2_ADD_INT;
5581 alu.src[0].sel = src_gpr;
5582 alu.src[0].chan = 1;
5583 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5584 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
5585 alu.dst.sel = src_gpr;
5586 alu.dst.chan = 1;
5587 alu.dst.write = 1;
5588 alu.last = 1;
5589 r = r600_bytecode_add_alu(ctx->bc, &alu);
5590 if (r)
5591 return r;
5592 /* fall through */
5593
5594 case TGSI_TEXTURE_1D:
5595 case TGSI_TEXTURE_SHADOW1D:
5596 case TGSI_TEXTURE_1D_ARRAY:
5597 case TGSI_TEXTURE_SHADOW1D_ARRAY:
5598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5599 alu.op = ALU_OP2_ADD_INT;
5600 alu.src[0].sel = src_gpr;
5601 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5602 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
5603 alu.dst.sel = src_gpr;
5604 alu.dst.write = 1;
5605 alu.last = 1;
5606 r = r600_bytecode_add_alu(ctx->bc, &alu);
5607 if (r)
5608 return r;
5609 break;
5610 /* texture offsets do not apply to other texture targets */
5611 }
5612 } else {
5613 switch (inst->Texture.Texture) {
5614 case TGSI_TEXTURE_3D:
5615 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
5616 /* fallthrough */
5617 case TGSI_TEXTURE_2D:
5618 case TGSI_TEXTURE_SHADOW2D:
5619 case TGSI_TEXTURE_RECT:
5620 case TGSI_TEXTURE_SHADOWRECT:
5621 case TGSI_TEXTURE_2D_ARRAY:
5622 case TGSI_TEXTURE_SHADOW2D_ARRAY:
5623 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
5624 /* fallthrough */
5625 case TGSI_TEXTURE_1D:
5626 case TGSI_TEXTURE_SHADOW1D:
5627 case TGSI_TEXTURE_1D_ARRAY:
5628 case TGSI_TEXTURE_SHADOW1D_ARRAY:
5629 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
5630 }
5631 }
5632 }
5633
5634 /* Obtain the sample index for reading a compressed MSAA color texture.
5635 * To read the FMASK, we use the ldfptr instruction, which tells us
5636 * where the samples are stored.
5637 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
5638 * which is the identity mapping. Each nibble says which physical sample
5639 * should be fetched to get that sample.
5640 *
5641 * Assume src.z contains the sample index. It should be modified like this:
5642 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
5643 * Then fetch the texel with src.
5644 */
5645 if (read_compressed_msaa) {
5646 unsigned sample_chan = 3;
5647 unsigned temp = r600_get_temp(ctx);
5648 assert(src_loaded);
5649
5650 /* temp.w = ldfptr() */
5651 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5652 tex.op = FETCH_OP_LD;
5653 tex.inst_mod = 1; /* to indicate this is ldfptr */
5654 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5655 tex.sampler_index_mode = sampler_index_mode;
5656 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5657 tex.resource_index_mode = sampler_index_mode;
5658 tex.src_gpr = src_gpr;
5659 tex.dst_gpr = temp;
5660 tex.dst_sel_x = 7; /* mask out these components */
5661 tex.dst_sel_y = 7;
5662 tex.dst_sel_z = 7;
5663 tex.dst_sel_w = 0; /* store X */
5664 tex.src_sel_x = 0;
5665 tex.src_sel_y = 1;
5666 tex.src_sel_z = 2;
5667 tex.src_sel_w = 3;
5668 tex.offset_x = offset_x;
5669 tex.offset_y = offset_y;
5670 tex.offset_z = offset_z;
5671 r = r600_bytecode_add_tex(ctx->bc, &tex);
5672 if (r)
5673 return r;
5674
5675 /* temp.x = sample_index*4 */
5676 if (ctx->bc->chip_class == CAYMAN) {
5677 for (i = 0 ; i < 4; i++) {
5678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5679 alu.op = ALU_OP2_MULLO_INT;
5680 alu.src[0].sel = src_gpr;
5681 alu.src[0].chan = sample_chan;
5682 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5683 alu.src[1].value = 4;
5684 alu.dst.sel = temp;
5685 alu.dst.chan = i;
5686 alu.dst.write = i == 0;
5687 if (i == 3)
5688 alu.last = 1;
5689 r = r600_bytecode_add_alu(ctx->bc, &alu);
5690 if (r)
5691 return r;
5692 }
5693 } else {
5694 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5695 alu.op = ALU_OP2_MULLO_INT;
5696 alu.src[0].sel = src_gpr;
5697 alu.src[0].chan = sample_chan;
5698 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5699 alu.src[1].value = 4;
5700 alu.dst.sel = temp;
5701 alu.dst.chan = 0;
5702 alu.dst.write = 1;
5703 alu.last = 1;
5704 r = r600_bytecode_add_alu(ctx->bc, &alu);
5705 if (r)
5706 return r;
5707 }
5708
5709 /* sample_index = temp.w >> temp.x */
5710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5711 alu.op = ALU_OP2_LSHR_INT;
5712 alu.src[0].sel = temp;
5713 alu.src[0].chan = 3;
5714 alu.src[1].sel = temp;
5715 alu.src[1].chan = 0;
5716 alu.dst.sel = src_gpr;
5717 alu.dst.chan = sample_chan;
5718 alu.dst.write = 1;
5719 alu.last = 1;
5720 r = r600_bytecode_add_alu(ctx->bc, &alu);
5721 if (r)
5722 return r;
5723
5724 /* sample_index & 0xF */
5725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5726 alu.op = ALU_OP2_AND_INT;
5727 alu.src[0].sel = src_gpr;
5728 alu.src[0].chan = sample_chan;
5729 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5730 alu.src[1].value = 0xF;
5731 alu.dst.sel = src_gpr;
5732 alu.dst.chan = sample_chan;
5733 alu.dst.write = 1;
5734 alu.last = 1;
5735 r = r600_bytecode_add_alu(ctx->bc, &alu);
5736 if (r)
5737 return r;
5738 #if 0
5739 /* visualize the FMASK */
5740 for (i = 0; i < 4; i++) {
5741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5742 alu.op = ALU_OP1_INT_TO_FLT;
5743 alu.src[0].sel = src_gpr;
5744 alu.src[0].chan = sample_chan;
5745 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5746 alu.dst.chan = i;
5747 alu.dst.write = 1;
5748 alu.last = 1;
5749 r = r600_bytecode_add_alu(ctx->bc, &alu);
5750 if (r)
5751 return r;
5752 }
5753 return 0;
5754 #endif
5755 }
5756
5757 /* does this shader want a num layers from TXQ for a cube array? */
5758 if (has_txq_cube_array_z) {
5759 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5760
5761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5762 alu.op = ALU_OP1_MOV;
5763
5764 if (ctx->bc->chip_class >= EVERGREEN) {
5765 /* channel 1 or 3 of each word */
5766 alu.src[0].sel = 512 + (id / 2);
5767 alu.src[0].chan = ((id % 2) * 2) + 1;
5768 } else {
5769 /* r600 we have them at channel 2 of the second dword */
5770 alu.src[0].sel = 512 + (id * 2) + 1;
5771 alu.src[0].chan = 2;
5772 }
5773 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5774 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5775 alu.last = 1;
5776 r = r600_bytecode_add_alu(ctx->bc, &alu);
5777 if (r)
5778 return r;
5779 /* disable writemask from texture instruction */
5780 inst->Dst[0].Register.WriteMask &= ~4;
5781 }
5782
5783 opcode = ctx->inst_info->op;
5784 if (opcode == FETCH_OP_GATHER4 &&
5785 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
5786 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
5787 opcode = FETCH_OP_GATHER4_O;
5788
5789 /* GATHER4_O/GATHER4_C_O use offset values loaded by
5790 SET_TEXTURE_OFFSETS instruction. The immediate offset values
5791 encoded in the instruction are ignored. */
5792 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5793 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
5794 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5795 tex.sampler_index_mode = sampler_index_mode;
5796 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5797 tex.resource_index_mode = sampler_index_mode;
5798
5799 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
5800 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
5801 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
5802 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
5803 tex.src_sel_w = 4;
5804
5805 tex.dst_sel_x = 7;
5806 tex.dst_sel_y = 7;
5807 tex.dst_sel_z = 7;
5808 tex.dst_sel_w = 7;
5809
5810 r = r600_bytecode_add_tex(ctx->bc, &tex);
5811 if (r)
5812 return r;
5813 }
5814
5815 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
5816 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
5817 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
5818 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5819 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
5820 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
5821 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5822 switch (opcode) {
5823 case FETCH_OP_SAMPLE:
5824 opcode = FETCH_OP_SAMPLE_C;
5825 break;
5826 case FETCH_OP_SAMPLE_L:
5827 opcode = FETCH_OP_SAMPLE_C_L;
5828 break;
5829 case FETCH_OP_SAMPLE_LB:
5830 opcode = FETCH_OP_SAMPLE_C_LB;
5831 break;
5832 case FETCH_OP_SAMPLE_G:
5833 opcode = FETCH_OP_SAMPLE_C_G;
5834 break;
5835 /* Texture gather variants */
5836 case FETCH_OP_GATHER4:
5837 opcode = FETCH_OP_GATHER4_C;
5838 break;
5839 case FETCH_OP_GATHER4_O:
5840 opcode = FETCH_OP_GATHER4_C_O;
5841 break;
5842 }
5843 }
5844
5845 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5846 tex.op = opcode;
5847
5848 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5849 tex.sampler_index_mode = sampler_index_mode;
5850 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5851 tex.resource_index_mode = sampler_index_mode;
5852 tex.src_gpr = src_gpr;
5853 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5854
5855 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
5856 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
5857 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
5858 }
5859
5860 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
5861 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
5862 tex.inst_mod = texture_component_select;
5863
5864 if (ctx->bc->chip_class == CAYMAN) {
5865 /* GATHER4 result order is different from TGSI TG4 */
5866 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
5867 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
5868 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
5869 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
5870 } else {
5871 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
5872 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
5873 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
5874 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
5875 }
5876 }
5877 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
5878 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
5879 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
5880 tex.dst_sel_z = 7;
5881 tex.dst_sel_w = 7;
5882 }
5883 else {
5884 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
5885 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
5886 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
5887 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
5888 }
5889
5890
5891 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
5892 tex.src_sel_x = 4;
5893 tex.src_sel_y = 4;
5894 tex.src_sel_z = 4;
5895 tex.src_sel_w = 4;
5896 } else if (src_loaded) {
5897 tex.src_sel_x = 0;
5898 tex.src_sel_y = 1;
5899 tex.src_sel_z = 2;
5900 tex.src_sel_w = 3;
5901 } else {
5902 tex.src_sel_x = ctx->src[0].swizzle[0];
5903 tex.src_sel_y = ctx->src[0].swizzle[1];
5904 tex.src_sel_z = ctx->src[0].swizzle[2];
5905 tex.src_sel_w = ctx->src[0].swizzle[3];
5906 tex.src_rel = ctx->src[0].rel;
5907 }
5908
5909 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
5910 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5911 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5912 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5913 tex.src_sel_x = 1;
5914 tex.src_sel_y = 0;
5915 tex.src_sel_z = 3;
5916 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
5917 }
5918
5919 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
5920 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
5921 tex.coord_type_x = 1;
5922 tex.coord_type_y = 1;
5923 }
5924 tex.coord_type_z = 1;
5925 tex.coord_type_w = 1;
5926
5927 tex.offset_x = offset_x;
5928 tex.offset_y = offset_y;
5929 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
5930 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
5931 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
5932 tex.offset_z = 0;
5933 }
5934 else {
5935 tex.offset_z = offset_z;
5936 }
5937
5938 /* Put the depth for comparison in W.
5939 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
5940 * Some instructions expect the depth in Z. */
5941 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
5942 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
5943 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
5944 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
5945 opcode != FETCH_OP_SAMPLE_C_L &&
5946 opcode != FETCH_OP_SAMPLE_C_LB) {
5947 tex.src_sel_w = tex.src_sel_z;
5948 }
5949
5950 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
5951 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
5952 if (opcode == FETCH_OP_SAMPLE_C_L ||
5953 opcode == FETCH_OP_SAMPLE_C_LB) {
5954 /* the array index is read from Y */
5955 tex.coord_type_y = 0;
5956 } else {
5957 /* the array index is read from Z */
5958 tex.coord_type_z = 0;
5959 tex.src_sel_z = tex.src_sel_y;
5960 }
5961 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
5962 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
5963 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5964 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
5965 (ctx->bc->chip_class >= EVERGREEN)))
5966 /* the array index is read from Z */
5967 tex.coord_type_z = 0;
5968
5969 /* mask unused source components */
5970 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
5971 switch (inst->Texture.Texture) {
5972 case TGSI_TEXTURE_2D:
5973 case TGSI_TEXTURE_RECT:
5974 tex.src_sel_z = 7;
5975 tex.src_sel_w = 7;
5976 break;
5977 case TGSI_TEXTURE_1D_ARRAY:
5978 tex.src_sel_y = 7;
5979 tex.src_sel_w = 7;
5980 break;
5981 case TGSI_TEXTURE_1D:
5982 tex.src_sel_y = 7;
5983 tex.src_sel_z = 7;
5984 tex.src_sel_w = 7;
5985 break;
5986 }
5987 }
5988
5989 r = r600_bytecode_add_tex(ctx->bc, &tex);
5990 if (r)
5991 return r;
5992
5993 /* add shadow ambient support - gallium doesn't do it yet */
5994 return 0;
5995 }
5996
5997 static int tgsi_lrp(struct r600_shader_ctx *ctx)
5998 {
5999 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6000 struct r600_bytecode_alu alu;
6001 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6002 unsigned i, temp_regs[2];
6003 int r;
6004
6005 /* optimize if it's just an equal balance */
6006 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
6007 for (i = 0; i < lasti + 1; i++) {
6008 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6009 continue;
6010
6011 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6012 alu.op = ALU_OP2_ADD;
6013 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6014 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6015 alu.omod = 3;
6016 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6017 alu.dst.chan = i;
6018 if (i == lasti) {
6019 alu.last = 1;
6020 }
6021 r = r600_bytecode_add_alu(ctx->bc, &alu);
6022 if (r)
6023 return r;
6024 }
6025 return 0;
6026 }
6027
6028 /* 1 - src0 */
6029 for (i = 0; i < lasti + 1; i++) {
6030 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6031 continue;
6032
6033 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6034 alu.op = ALU_OP2_ADD;
6035 alu.src[0].sel = V_SQ_ALU_SRC_1;
6036 alu.src[0].chan = 0;
6037 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6038 r600_bytecode_src_toggle_neg(&alu.src[1]);
6039 alu.dst.sel = ctx->temp_reg;
6040 alu.dst.chan = i;
6041 if (i == lasti) {
6042 alu.last = 1;
6043 }
6044 alu.dst.write = 1;
6045 r = r600_bytecode_add_alu(ctx->bc, &alu);
6046 if (r)
6047 return r;
6048 }
6049
6050 /* (1 - src0) * src2 */
6051 for (i = 0; i < lasti + 1; i++) {
6052 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6053 continue;
6054
6055 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6056 alu.op = ALU_OP2_MUL;
6057 alu.src[0].sel = ctx->temp_reg;
6058 alu.src[0].chan = i;
6059 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6060 alu.dst.sel = ctx->temp_reg;
6061 alu.dst.chan = i;
6062 if (i == lasti) {
6063 alu.last = 1;
6064 }
6065 alu.dst.write = 1;
6066 r = r600_bytecode_add_alu(ctx->bc, &alu);
6067 if (r)
6068 return r;
6069 }
6070
6071 /* src0 * src1 + (1 - src0) * src2 */
6072 if (ctx->src[0].abs)
6073 temp_regs[0] = r600_get_temp(ctx);
6074 else
6075 temp_regs[0] = 0;
6076 if (ctx->src[1].abs)
6077 temp_regs[1] = r600_get_temp(ctx);
6078 else
6079 temp_regs[1] = 0;
6080
6081 for (i = 0; i < lasti + 1; i++) {
6082 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6083 continue;
6084
6085 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6086 alu.op = ALU_OP3_MULADD;
6087 alu.is_op3 = 1;
6088 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6089 if (r)
6090 return r;
6091 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
6092 if (r)
6093 return r;
6094 alu.src[2].sel = ctx->temp_reg;
6095 alu.src[2].chan = i;
6096
6097 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6098 alu.dst.chan = i;
6099 if (i == lasti) {
6100 alu.last = 1;
6101 }
6102 r = r600_bytecode_add_alu(ctx->bc, &alu);
6103 if (r)
6104 return r;
6105 }
6106 return 0;
6107 }
6108
6109 static int tgsi_cmp(struct r600_shader_ctx *ctx)
6110 {
6111 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6112 struct r600_bytecode_alu alu;
6113 int i, r, j;
6114 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6115 int temp_regs[3];
6116
6117 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6118 temp_regs[j] = 0;
6119 if (ctx->src[j].abs)
6120 temp_regs[j] = r600_get_temp(ctx);
6121 }
6122
6123 for (i = 0; i < lasti + 1; i++) {
6124 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6125 continue;
6126
6127 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6128 alu.op = ALU_OP3_CNDGE;
6129 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6130 if (r)
6131 return r;
6132 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
6133 if (r)
6134 return r;
6135 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
6136 if (r)
6137 return r;
6138 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6139 alu.dst.chan = i;
6140 alu.dst.write = 1;
6141 alu.is_op3 = 1;
6142 if (i == lasti)
6143 alu.last = 1;
6144 r = r600_bytecode_add_alu(ctx->bc, &alu);
6145 if (r)
6146 return r;
6147 }
6148 return 0;
6149 }
6150
6151 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
6152 {
6153 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6154 struct r600_bytecode_alu alu;
6155 int i, r;
6156 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6157
6158 for (i = 0; i < lasti + 1; i++) {
6159 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6160 continue;
6161
6162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6163 alu.op = ALU_OP3_CNDE_INT;
6164 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6165 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6166 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6167 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6168 alu.dst.chan = i;
6169 alu.dst.write = 1;
6170 alu.is_op3 = 1;
6171 if (i == lasti)
6172 alu.last = 1;
6173 r = r600_bytecode_add_alu(ctx->bc, &alu);
6174 if (r)
6175 return r;
6176 }
6177 return 0;
6178 }
6179
6180 static int tgsi_xpd(struct r600_shader_ctx *ctx)
6181 {
6182 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6183 static const unsigned int src0_swizzle[] = {2, 0, 1};
6184 static const unsigned int src1_swizzle[] = {1, 2, 0};
6185 struct r600_bytecode_alu alu;
6186 uint32_t use_temp = 0;
6187 int i, r;
6188
6189 if (inst->Dst[0].Register.WriteMask != 0xf)
6190 use_temp = 1;
6191
6192 for (i = 0; i < 4; i++) {
6193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6194 alu.op = ALU_OP2_MUL;
6195 if (i < 3) {
6196 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6197 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
6198 } else {
6199 alu.src[0].sel = V_SQ_ALU_SRC_0;
6200 alu.src[0].chan = i;
6201 alu.src[1].sel = V_SQ_ALU_SRC_0;
6202 alu.src[1].chan = i;
6203 }
6204
6205 alu.dst.sel = ctx->temp_reg;
6206 alu.dst.chan = i;
6207 alu.dst.write = 1;
6208
6209 if (i == 3)
6210 alu.last = 1;
6211 r = r600_bytecode_add_alu(ctx->bc, &alu);
6212 if (r)
6213 return r;
6214 }
6215
6216 for (i = 0; i < 4; i++) {
6217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6218 alu.op = ALU_OP3_MULADD;
6219
6220 if (i < 3) {
6221 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
6222 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
6223 } else {
6224 alu.src[0].sel = V_SQ_ALU_SRC_0;
6225 alu.src[0].chan = i;
6226 alu.src[1].sel = V_SQ_ALU_SRC_0;
6227 alu.src[1].chan = i;
6228 }
6229
6230 alu.src[2].sel = ctx->temp_reg;
6231 alu.src[2].neg = 1;
6232 alu.src[2].chan = i;
6233
6234 if (use_temp)
6235 alu.dst.sel = ctx->temp_reg;
6236 else
6237 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6238 alu.dst.chan = i;
6239 alu.dst.write = 1;
6240 alu.is_op3 = 1;
6241 if (i == 3)
6242 alu.last = 1;
6243 r = r600_bytecode_add_alu(ctx->bc, &alu);
6244 if (r)
6245 return r;
6246 }
6247 if (use_temp)
6248 return tgsi_helper_copy(ctx, inst);
6249 return 0;
6250 }
6251
6252 static int tgsi_exp(struct r600_shader_ctx *ctx)
6253 {
6254 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6255 struct r600_bytecode_alu alu;
6256 int r;
6257 int i;
6258
6259 /* result.x = 2^floor(src); */
6260 if (inst->Dst[0].Register.WriteMask & 1) {
6261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6262
6263 alu.op = ALU_OP1_FLOOR;
6264 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6265
6266 alu.dst.sel = ctx->temp_reg;
6267 alu.dst.chan = 0;
6268 alu.dst.write = 1;
6269 alu.last = 1;
6270 r = r600_bytecode_add_alu(ctx->bc, &alu);
6271 if (r)
6272 return r;
6273
6274 if (ctx->bc->chip_class == CAYMAN) {
6275 for (i = 0; i < 3; i++) {
6276 alu.op = ALU_OP1_EXP_IEEE;
6277 alu.src[0].sel = ctx->temp_reg;
6278 alu.src[0].chan = 0;
6279
6280 alu.dst.sel = ctx->temp_reg;
6281 alu.dst.chan = i;
6282 alu.dst.write = i == 0;
6283 alu.last = i == 2;
6284 r = r600_bytecode_add_alu(ctx->bc, &alu);
6285 if (r)
6286 return r;
6287 }
6288 } else {
6289 alu.op = ALU_OP1_EXP_IEEE;
6290 alu.src[0].sel = ctx->temp_reg;
6291 alu.src[0].chan = 0;
6292
6293 alu.dst.sel = ctx->temp_reg;
6294 alu.dst.chan = 0;
6295 alu.dst.write = 1;
6296 alu.last = 1;
6297 r = r600_bytecode_add_alu(ctx->bc, &alu);
6298 if (r)
6299 return r;
6300 }
6301 }
6302
6303 /* result.y = tmp - floor(tmp); */
6304 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
6305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6306
6307 alu.op = ALU_OP1_FRACT;
6308 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6309
6310 alu.dst.sel = ctx->temp_reg;
6311 #if 0
6312 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6313 if (r)
6314 return r;
6315 #endif
6316 alu.dst.write = 1;
6317 alu.dst.chan = 1;
6318
6319 alu.last = 1;
6320
6321 r = r600_bytecode_add_alu(ctx->bc, &alu);
6322 if (r)
6323 return r;
6324 }
6325
6326 /* result.z = RoughApprox2ToX(tmp);*/
6327 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
6328 if (ctx->bc->chip_class == CAYMAN) {
6329 for (i = 0; i < 3; i++) {
6330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6331 alu.op = ALU_OP1_EXP_IEEE;
6332 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6333
6334 alu.dst.sel = ctx->temp_reg;
6335 alu.dst.chan = i;
6336 if (i == 2) {
6337 alu.dst.write = 1;
6338 alu.last = 1;
6339 }
6340
6341 r = r600_bytecode_add_alu(ctx->bc, &alu);
6342 if (r)
6343 return r;
6344 }
6345 } else {
6346 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6347 alu.op = ALU_OP1_EXP_IEEE;
6348 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6349
6350 alu.dst.sel = ctx->temp_reg;
6351 alu.dst.write = 1;
6352 alu.dst.chan = 2;
6353
6354 alu.last = 1;
6355
6356 r = r600_bytecode_add_alu(ctx->bc, &alu);
6357 if (r)
6358 return r;
6359 }
6360 }
6361
6362 /* result.w = 1.0;*/
6363 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
6364 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6365
6366 alu.op = ALU_OP1_MOV;
6367 alu.src[0].sel = V_SQ_ALU_SRC_1;
6368 alu.src[0].chan = 0;
6369
6370 alu.dst.sel = ctx->temp_reg;
6371 alu.dst.chan = 3;
6372 alu.dst.write = 1;
6373 alu.last = 1;
6374 r = r600_bytecode_add_alu(ctx->bc, &alu);
6375 if (r)
6376 return r;
6377 }
6378 return tgsi_helper_copy(ctx, inst);
6379 }
6380
6381 static int tgsi_log(struct r600_shader_ctx *ctx)
6382 {
6383 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6384 struct r600_bytecode_alu alu;
6385 int r;
6386 int i;
6387
6388 /* result.x = floor(log2(|src|)); */
6389 if (inst->Dst[0].Register.WriteMask & 1) {
6390 if (ctx->bc->chip_class == CAYMAN) {
6391 for (i = 0; i < 3; i++) {
6392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6393
6394 alu.op = ALU_OP1_LOG_IEEE;
6395 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6396 r600_bytecode_src_set_abs(&alu.src[0]);
6397
6398 alu.dst.sel = ctx->temp_reg;
6399 alu.dst.chan = i;
6400 if (i == 0)
6401 alu.dst.write = 1;
6402 if (i == 2)
6403 alu.last = 1;
6404 r = r600_bytecode_add_alu(ctx->bc, &alu);
6405 if (r)
6406 return r;
6407 }
6408
6409 } else {
6410 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6411
6412 alu.op = ALU_OP1_LOG_IEEE;
6413 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6414 r600_bytecode_src_set_abs(&alu.src[0]);
6415
6416 alu.dst.sel = ctx->temp_reg;
6417 alu.dst.chan = 0;
6418 alu.dst.write = 1;
6419 alu.last = 1;
6420 r = r600_bytecode_add_alu(ctx->bc, &alu);
6421 if (r)
6422 return r;
6423 }
6424
6425 alu.op = ALU_OP1_FLOOR;
6426 alu.src[0].sel = ctx->temp_reg;
6427 alu.src[0].chan = 0;
6428
6429 alu.dst.sel = ctx->temp_reg;
6430 alu.dst.chan = 0;
6431 alu.dst.write = 1;
6432 alu.last = 1;
6433
6434 r = r600_bytecode_add_alu(ctx->bc, &alu);
6435 if (r)
6436 return r;
6437 }
6438
6439 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
6440 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
6441
6442 if (ctx->bc->chip_class == CAYMAN) {
6443 for (i = 0; i < 3; i++) {
6444 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6445
6446 alu.op = ALU_OP1_LOG_IEEE;
6447 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6448 r600_bytecode_src_set_abs(&alu.src[0]);
6449
6450 alu.dst.sel = ctx->temp_reg;
6451 alu.dst.chan = i;
6452 if (i == 1)
6453 alu.dst.write = 1;
6454 if (i == 2)
6455 alu.last = 1;
6456
6457 r = r600_bytecode_add_alu(ctx->bc, &alu);
6458 if (r)
6459 return r;
6460 }
6461 } else {
6462 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6463
6464 alu.op = ALU_OP1_LOG_IEEE;
6465 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6466 r600_bytecode_src_set_abs(&alu.src[0]);
6467
6468 alu.dst.sel = ctx->temp_reg;
6469 alu.dst.chan = 1;
6470 alu.dst.write = 1;
6471 alu.last = 1;
6472
6473 r = r600_bytecode_add_alu(ctx->bc, &alu);
6474 if (r)
6475 return r;
6476 }
6477
6478 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6479
6480 alu.op = ALU_OP1_FLOOR;
6481 alu.src[0].sel = ctx->temp_reg;
6482 alu.src[0].chan = 1;
6483
6484 alu.dst.sel = ctx->temp_reg;
6485 alu.dst.chan = 1;
6486 alu.dst.write = 1;
6487 alu.last = 1;
6488
6489 r = r600_bytecode_add_alu(ctx->bc, &alu);
6490 if (r)
6491 return r;
6492
6493 if (ctx->bc->chip_class == CAYMAN) {
6494 for (i = 0; i < 3; i++) {
6495 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6496 alu.op = ALU_OP1_EXP_IEEE;
6497 alu.src[0].sel = ctx->temp_reg;
6498 alu.src[0].chan = 1;
6499
6500 alu.dst.sel = ctx->temp_reg;
6501 alu.dst.chan = i;
6502 if (i == 1)
6503 alu.dst.write = 1;
6504 if (i == 2)
6505 alu.last = 1;
6506
6507 r = r600_bytecode_add_alu(ctx->bc, &alu);
6508 if (r)
6509 return r;
6510 }
6511 } else {
6512 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6513 alu.op = ALU_OP1_EXP_IEEE;
6514 alu.src[0].sel = ctx->temp_reg;
6515 alu.src[0].chan = 1;
6516
6517 alu.dst.sel = ctx->temp_reg;
6518 alu.dst.chan = 1;
6519 alu.dst.write = 1;
6520 alu.last = 1;
6521
6522 r = r600_bytecode_add_alu(ctx->bc, &alu);
6523 if (r)
6524 return r;
6525 }
6526
6527 if (ctx->bc->chip_class == CAYMAN) {
6528 for (i = 0; i < 3; i++) {
6529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6530 alu.op = ALU_OP1_RECIP_IEEE;
6531 alu.src[0].sel = ctx->temp_reg;
6532 alu.src[0].chan = 1;
6533
6534 alu.dst.sel = ctx->temp_reg;
6535 alu.dst.chan = i;
6536 if (i == 1)
6537 alu.dst.write = 1;
6538 if (i == 2)
6539 alu.last = 1;
6540
6541 r = r600_bytecode_add_alu(ctx->bc, &alu);
6542 if (r)
6543 return r;
6544 }
6545 } else {
6546 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6547 alu.op = ALU_OP1_RECIP_IEEE;
6548 alu.src[0].sel = ctx->temp_reg;
6549 alu.src[0].chan = 1;
6550
6551 alu.dst.sel = ctx->temp_reg;
6552 alu.dst.chan = 1;
6553 alu.dst.write = 1;
6554 alu.last = 1;
6555
6556 r = r600_bytecode_add_alu(ctx->bc, &alu);
6557 if (r)
6558 return r;
6559 }
6560
6561 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6562
6563 alu.op = ALU_OP2_MUL;
6564
6565 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6566 r600_bytecode_src_set_abs(&alu.src[0]);
6567
6568 alu.src[1].sel = ctx->temp_reg;
6569 alu.src[1].chan = 1;
6570
6571 alu.dst.sel = ctx->temp_reg;
6572 alu.dst.chan = 1;
6573 alu.dst.write = 1;
6574 alu.last = 1;
6575
6576 r = r600_bytecode_add_alu(ctx->bc, &alu);
6577 if (r)
6578 return r;
6579 }
6580
6581 /* result.z = log2(|src|);*/
6582 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
6583 if (ctx->bc->chip_class == CAYMAN) {
6584 for (i = 0; i < 3; i++) {
6585 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6586
6587 alu.op = ALU_OP1_LOG_IEEE;
6588 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6589 r600_bytecode_src_set_abs(&alu.src[0]);
6590
6591 alu.dst.sel = ctx->temp_reg;
6592 if (i == 2)
6593 alu.dst.write = 1;
6594 alu.dst.chan = i;
6595 if (i == 2)
6596 alu.last = 1;
6597
6598 r = r600_bytecode_add_alu(ctx->bc, &alu);
6599 if (r)
6600 return r;
6601 }
6602 } else {
6603 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6604
6605 alu.op = ALU_OP1_LOG_IEEE;
6606 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6607 r600_bytecode_src_set_abs(&alu.src[0]);
6608
6609 alu.dst.sel = ctx->temp_reg;
6610 alu.dst.write = 1;
6611 alu.dst.chan = 2;
6612 alu.last = 1;
6613
6614 r = r600_bytecode_add_alu(ctx->bc, &alu);
6615 if (r)
6616 return r;
6617 }
6618 }
6619
6620 /* result.w = 1.0; */
6621 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
6622 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6623
6624 alu.op = ALU_OP1_MOV;
6625 alu.src[0].sel = V_SQ_ALU_SRC_1;
6626 alu.src[0].chan = 0;
6627
6628 alu.dst.sel = ctx->temp_reg;
6629 alu.dst.chan = 3;
6630 alu.dst.write = 1;
6631 alu.last = 1;
6632
6633 r = r600_bytecode_add_alu(ctx->bc, &alu);
6634 if (r)
6635 return r;
6636 }
6637
6638 return tgsi_helper_copy(ctx, inst);
6639 }
6640
6641 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
6642 {
6643 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6644 struct r600_bytecode_alu alu;
6645 int r;
6646 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6647 unsigned reg = inst->Dst[0].Register.Index > 0 ? ctx->bc->index_reg[inst->Dst[0].Register.Index - 1] : ctx->bc->ar_reg;
6648
6649 assert(inst->Dst[0].Register.Index < 3);
6650 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6651
6652 switch (inst->Instruction.Opcode) {
6653 case TGSI_OPCODE_ARL:
6654 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
6655 break;
6656 case TGSI_OPCODE_ARR:
6657 alu.op = ALU_OP1_FLT_TO_INT;
6658 break;
6659 case TGSI_OPCODE_UARL:
6660 alu.op = ALU_OP1_MOV;
6661 break;
6662 default:
6663 assert(0);
6664 return -1;
6665 }
6666
6667 for (i = 0; i <= lasti; ++i) {
6668 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6669 continue;
6670 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6671 alu.last = i == lasti;
6672 alu.dst.sel = reg;
6673 alu.dst.chan = i;
6674 alu.dst.write = 1;
6675 r = r600_bytecode_add_alu(ctx->bc, &alu);
6676 if (r)
6677 return r;
6678 }
6679
6680 if (inst->Dst[0].Register.Index > 0)
6681 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
6682 else
6683 ctx->bc->ar_loaded = 0;
6684
6685 return 0;
6686 }
6687 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
6688 {
6689 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6690 struct r600_bytecode_alu alu;
6691 int r;
6692 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6693
6694 switch (inst->Instruction.Opcode) {
6695 case TGSI_OPCODE_ARL:
6696 memset(&alu, 0, sizeof(alu));
6697 alu.op = ALU_OP1_FLOOR;
6698 alu.dst.sel = ctx->bc->ar_reg;
6699 alu.dst.write = 1;
6700 for (i = 0; i <= lasti; ++i) {
6701 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
6702 alu.dst.chan = i;
6703 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6704 alu.last = i == lasti;
6705 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6706 return r;
6707 }
6708 }
6709
6710 memset(&alu, 0, sizeof(alu));
6711 alu.op = ALU_OP1_FLT_TO_INT;
6712 alu.src[0].sel = ctx->bc->ar_reg;
6713 alu.dst.sel = ctx->bc->ar_reg;
6714 alu.dst.write = 1;
6715 /* FLT_TO_INT is trans-only on r600/r700 */
6716 alu.last = TRUE;
6717 for (i = 0; i <= lasti; ++i) {
6718 alu.dst.chan = i;
6719 alu.src[0].chan = i;
6720 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6721 return r;
6722 }
6723 break;
6724 case TGSI_OPCODE_ARR:
6725 memset(&alu, 0, sizeof(alu));
6726 alu.op = ALU_OP1_FLT_TO_INT;
6727 alu.dst.sel = ctx->bc->ar_reg;
6728 alu.dst.write = 1;
6729 /* FLT_TO_INT is trans-only on r600/r700 */
6730 alu.last = TRUE;
6731 for (i = 0; i <= lasti; ++i) {
6732 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
6733 alu.dst.chan = i;
6734 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6735 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6736 return r;
6737 }
6738 }
6739 break;
6740 case TGSI_OPCODE_UARL:
6741 memset(&alu, 0, sizeof(alu));
6742 alu.op = ALU_OP1_MOV;
6743 alu.dst.sel = ctx->bc->ar_reg;
6744 alu.dst.write = 1;
6745 for (i = 0; i <= lasti; ++i) {
6746 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
6747 alu.dst.chan = i;
6748 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6749 alu.last = i == lasti;
6750 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6751 return r;
6752 }
6753 }
6754 break;
6755 default:
6756 assert(0);
6757 return -1;
6758 }
6759
6760 ctx->bc->ar_loaded = 0;
6761 return 0;
6762 }
6763
6764 static int tgsi_opdst(struct r600_shader_ctx *ctx)
6765 {
6766 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6767 struct r600_bytecode_alu alu;
6768 int i, r = 0;
6769
6770 for (i = 0; i < 4; i++) {
6771 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6772
6773 alu.op = ALU_OP2_MUL;
6774 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6775
6776 if (i == 0 || i == 3) {
6777 alu.src[0].sel = V_SQ_ALU_SRC_1;
6778 } else {
6779 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6780 }
6781
6782 if (i == 0 || i == 2) {
6783 alu.src[1].sel = V_SQ_ALU_SRC_1;
6784 } else {
6785 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6786 }
6787 if (i == 3)
6788 alu.last = 1;
6789 r = r600_bytecode_add_alu(ctx->bc, &alu);
6790 if (r)
6791 return r;
6792 }
6793 return 0;
6794 }
6795
6796 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
6797 {
6798 struct r600_bytecode_alu alu;
6799 int r;
6800
6801 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6802 alu.op = opcode;
6803 alu.execute_mask = 1;
6804 alu.update_pred = 1;
6805
6806 alu.dst.sel = ctx->temp_reg;
6807 alu.dst.write = 1;
6808 alu.dst.chan = 0;
6809
6810 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6811 alu.src[1].sel = V_SQ_ALU_SRC_0;
6812 alu.src[1].chan = 0;
6813
6814 alu.last = 1;
6815
6816 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
6817 if (r)
6818 return r;
6819 return 0;
6820 }
6821
6822 static int pops(struct r600_shader_ctx *ctx, int pops)
6823 {
6824 unsigned force_pop = ctx->bc->force_add_cf;
6825
6826 if (!force_pop) {
6827 int alu_pop = 3;
6828 if (ctx->bc->cf_last) {
6829 if (ctx->bc->cf_last->op == CF_OP_ALU)
6830 alu_pop = 0;
6831 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
6832 alu_pop = 1;
6833 }
6834 alu_pop += pops;
6835 if (alu_pop == 1) {
6836 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
6837 ctx->bc->force_add_cf = 1;
6838 } else if (alu_pop == 2) {
6839 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
6840 ctx->bc->force_add_cf = 1;
6841 } else {
6842 force_pop = 1;
6843 }
6844 }
6845
6846 if (force_pop) {
6847 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
6848 ctx->bc->cf_last->pop_count = pops;
6849 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
6850 }
6851
6852 return 0;
6853 }
6854
6855 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
6856 unsigned reason)
6857 {
6858 struct r600_stack_info *stack = &ctx->bc->stack;
6859 unsigned elements, entries;
6860
6861 unsigned entry_size = stack->entry_size;
6862
6863 elements = (stack->loop + stack->push_wqm ) * entry_size;
6864 elements += stack->push;
6865
6866 switch (ctx->bc->chip_class) {
6867 case R600:
6868 case R700:
6869 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
6870 * the stack must be reserved to hold the current active/continue
6871 * masks */
6872 if (reason == FC_PUSH_VPM) {
6873 elements += 2;
6874 }
6875 break;
6876
6877 case CAYMAN:
6878 /* r9xx: any stack operation on empty stack consumes 2 additional
6879 * elements */
6880 elements += 2;
6881
6882 /* fallthrough */
6883 /* FIXME: do the two elements added above cover the cases for the
6884 * r8xx+ below? */
6885
6886 case EVERGREEN:
6887 /* r8xx+: 2 extra elements are not always required, but one extra
6888 * element must be added for each of the following cases:
6889 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
6890 * stack usage.
6891 * (Currently we don't use ALU_ELSE_AFTER.)
6892 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
6893 * PUSH instruction executed.
6894 *
6895 * NOTE: it seems we also need to reserve additional element in some
6896 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
6897 * then STACK_SIZE should be 2 instead of 1 */
6898 if (reason == FC_PUSH_VPM) {
6899 elements += 1;
6900 }
6901 break;
6902
6903 default:
6904 assert(0);
6905 break;
6906 }
6907
6908 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
6909 * for all chips, so we use 4 in the final formula, not the real entry_size
6910 * for the chip */
6911 entry_size = 4;
6912
6913 entries = (elements + (entry_size - 1)) / entry_size;
6914
6915 if (entries > stack->max_entries)
6916 stack->max_entries = entries;
6917 }
6918
6919 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
6920 {
6921 switch(reason) {
6922 case FC_PUSH_VPM:
6923 --ctx->bc->stack.push;
6924 assert(ctx->bc->stack.push >= 0);
6925 break;
6926 case FC_PUSH_WQM:
6927 --ctx->bc->stack.push_wqm;
6928 assert(ctx->bc->stack.push_wqm >= 0);
6929 break;
6930 case FC_LOOP:
6931 --ctx->bc->stack.loop;
6932 assert(ctx->bc->stack.loop >= 0);
6933 break;
6934 default:
6935 assert(0);
6936 break;
6937 }
6938 }
6939
6940 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
6941 {
6942 switch (reason) {
6943 case FC_PUSH_VPM:
6944 ++ctx->bc->stack.push;
6945 break;
6946 case FC_PUSH_WQM:
6947 ++ctx->bc->stack.push_wqm;
6948 case FC_LOOP:
6949 ++ctx->bc->stack.loop;
6950 break;
6951 default:
6952 assert(0);
6953 }
6954
6955 callstack_update_max_depth(ctx, reason);
6956 }
6957
6958 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
6959 {
6960 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
6961
6962 sp->mid = realloc((void *)sp->mid,
6963 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
6964 sp->mid[sp->num_mid] = ctx->bc->cf_last;
6965 sp->num_mid++;
6966 }
6967
6968 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
6969 {
6970 ctx->bc->fc_sp++;
6971 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
6972 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
6973 }
6974
6975 static void fc_poplevel(struct r600_shader_ctx *ctx)
6976 {
6977 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
6978 free(sp->mid);
6979 sp->mid = NULL;
6980 sp->num_mid = 0;
6981 sp->start = NULL;
6982 sp->type = 0;
6983 ctx->bc->fc_sp--;
6984 }
6985
6986 #if 0
6987 static int emit_return(struct r600_shader_ctx *ctx)
6988 {
6989 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
6990 return 0;
6991 }
6992
6993 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
6994 {
6995
6996 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
6997 ctx->bc->cf_last->pop_count = pops;
6998 /* XXX work out offset */
6999 return 0;
7000 }
7001
7002 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
7003 {
7004 return 0;
7005 }
7006
7007 static void emit_testflag(struct r600_shader_ctx *ctx)
7008 {
7009
7010 }
7011
7012 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
7013 {
7014 emit_testflag(ctx);
7015 emit_jump_to_offset(ctx, 1, 4);
7016 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
7017 pops(ctx, ifidx + 1);
7018 emit_return(ctx);
7019 }
7020
7021 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
7022 {
7023 emit_testflag(ctx);
7024
7025 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7026 ctx->bc->cf_last->pop_count = 1;
7027
7028 fc_set_mid(ctx, fc_sp);
7029
7030 pops(ctx, 1);
7031 }
7032 #endif
7033
7034 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
7035 {
7036 int alu_type = CF_OP_ALU_PUSH_BEFORE;
7037
7038 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
7039 * LOOP_STARTxxx for nested loops may put the branch stack into a state
7040 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
7041 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
7042 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
7043 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
7044 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7045 alu_type = CF_OP_ALU;
7046 }
7047
7048 emit_logic_pred(ctx, opcode, alu_type);
7049
7050 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
7051
7052 fc_pushlevel(ctx, FC_IF);
7053
7054 callstack_push(ctx, FC_PUSH_VPM);
7055 return 0;
7056 }
7057
7058 static int tgsi_if(struct r600_shader_ctx *ctx)
7059 {
7060 return emit_if(ctx, ALU_OP2_PRED_SETNE);
7061 }
7062
7063 static int tgsi_uif(struct r600_shader_ctx *ctx)
7064 {
7065 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
7066 }
7067
7068 static int tgsi_else(struct r600_shader_ctx *ctx)
7069 {
7070 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
7071 ctx->bc->cf_last->pop_count = 1;
7072
7073 fc_set_mid(ctx, ctx->bc->fc_sp);
7074 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
7075 return 0;
7076 }
7077
7078 static int tgsi_endif(struct r600_shader_ctx *ctx)
7079 {
7080 pops(ctx, 1);
7081 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
7082 R600_ERR("if/endif unbalanced in shader\n");
7083 return -1;
7084 }
7085
7086 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
7087 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7088 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
7089 } else {
7090 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
7091 }
7092 fc_poplevel(ctx);
7093
7094 callstack_pop(ctx, FC_PUSH_VPM);
7095 return 0;
7096 }
7097
7098 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
7099 {
7100 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
7101 * limited to 4096 iterations, like the other LOOP_* instructions. */
7102 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
7103
7104 fc_pushlevel(ctx, FC_LOOP);
7105
7106 /* check stack depth */
7107 callstack_push(ctx, FC_LOOP);
7108 return 0;
7109 }
7110
7111 static int tgsi_endloop(struct r600_shader_ctx *ctx)
7112 {
7113 int i;
7114
7115 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
7116
7117 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
7118 R600_ERR("loop/endloop in shader code are not paired.\n");
7119 return -EINVAL;
7120 }
7121
7122 /* fixup loop pointers - from r600isa
7123 LOOP END points to CF after LOOP START,
7124 LOOP START point to CF after LOOP END
7125 BRK/CONT point to LOOP END CF
7126 */
7127 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
7128
7129 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7130
7131 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
7132 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
7133 }
7134 /* XXX add LOOPRET support */
7135 fc_poplevel(ctx);
7136 callstack_pop(ctx, FC_LOOP);
7137 return 0;
7138 }
7139
7140 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
7141 {
7142 int r;
7143 unsigned int fscp;
7144
7145 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7146 {
7147 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7148 break;
7149 }
7150 if (fscp == 0) {
7151 R600_ERR("BREAKC not inside loop/endloop pair\n");
7152 return -EINVAL;
7153 }
7154
7155 if (ctx->bc->chip_class == EVERGREEN &&
7156 ctx->bc->family != CHIP_CYPRESS &&
7157 ctx->bc->family != CHIP_JUNIPER) {
7158 /* HW bug: ALU_BREAK does not save the active mask correctly */
7159 r = tgsi_uif(ctx);
7160 if (r)
7161 return r;
7162
7163 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
7164 if (r)
7165 return r;
7166 fc_set_mid(ctx, fscp);
7167
7168 return tgsi_endif(ctx);
7169 } else {
7170 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
7171 if (r)
7172 return r;
7173 fc_set_mid(ctx, fscp);
7174 }
7175
7176 return 0;
7177 }
7178
7179 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
7180 {
7181 unsigned int fscp;
7182
7183 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7184 {
7185 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7186 break;
7187 }
7188
7189 if (fscp == 0) {
7190 R600_ERR("Break not inside loop/endloop pair\n");
7191 return -EINVAL;
7192 }
7193
7194 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7195
7196 fc_set_mid(ctx, fscp);
7197
7198 return 0;
7199 }
7200
7201 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
7202 {
7203 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
7204 emit_gs_ring_writes(ctx, TRUE);
7205
7206 return r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7207 }
7208
7209 static int tgsi_umad(struct r600_shader_ctx *ctx)
7210 {
7211 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7212 struct r600_bytecode_alu alu;
7213 int i, j, k, r;
7214 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7215
7216 /* src0 * src1 */
7217 for (i = 0; i < lasti + 1; i++) {
7218 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7219 continue;
7220
7221 if (ctx->bc->chip_class == CAYMAN) {
7222 for (j = 0 ; j < 4; j++) {
7223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7224
7225 alu.op = ALU_OP2_MULLO_UINT;
7226 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
7227 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
7228 }
7229 alu.dst.chan = j;
7230 alu.dst.sel = ctx->temp_reg;
7231 alu.dst.write = (j == i);
7232 if (j == 3)
7233 alu.last = 1;
7234 r = r600_bytecode_add_alu(ctx->bc, &alu);
7235 if (r)
7236 return r;
7237 }
7238 } else {
7239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7240
7241 alu.dst.chan = i;
7242 alu.dst.sel = ctx->temp_reg;
7243 alu.dst.write = 1;
7244
7245 alu.op = ALU_OP2_MULLO_UINT;
7246 for (j = 0; j < 2; j++) {
7247 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
7248 }
7249
7250 alu.last = 1;
7251 r = r600_bytecode_add_alu(ctx->bc, &alu);
7252 if (r)
7253 return r;
7254 }
7255 }
7256
7257
7258 for (i = 0; i < lasti + 1; i++) {
7259 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7260 continue;
7261
7262 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7263 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7264
7265 alu.op = ALU_OP2_ADD_INT;
7266
7267 alu.src[0].sel = ctx->temp_reg;
7268 alu.src[0].chan = i;
7269
7270 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7271 if (i == lasti) {
7272 alu.last = 1;
7273 }
7274 r = r600_bytecode_add_alu(ctx->bc, &alu);
7275 if (r)
7276 return r;
7277 }
7278 return 0;
7279 }
7280
7281 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
7282 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
7283 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
7284 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
7285
7286 /* XXX:
7287 * For state trackers other than OpenGL, we'll want to use
7288 * _RECIP_IEEE instead.
7289 */
7290 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
7291
7292 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
7293 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
7294 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
7295 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
7296 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
7297 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
7298 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
7299 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
7300 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
7301 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
7302 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
7303 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
7304 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
7305 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
7306 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
7307 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
7308 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
7309 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
7310 [22] = { ALU_OP0_NOP, tgsi_unsupported},
7311 [23] = { ALU_OP0_NOP, tgsi_unsupported},
7312 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
7313 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
7314 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
7315 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
7316 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
7317 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
7318 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
7319 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
7320 [32] = { ALU_OP0_NOP, tgsi_unsupported},
7321 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
7322 [34] = { ALU_OP0_NOP, tgsi_unsupported},
7323 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
7324 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
7325 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7326 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7327 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
7328 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
7329 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
7330 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
7331 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7332 [44] = { ALU_OP0_NOP, tgsi_unsupported},
7333 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
7334 [46] = { ALU_OP0_NOP, tgsi_unsupported},
7335 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
7336 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
7337 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
7338 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
7339 [51] = { ALU_OP0_NOP, tgsi_unsupported},
7340 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
7341 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
7342 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
7343 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
7344 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
7345 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
7346 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7347 [59] = { ALU_OP0_NOP, tgsi_unsupported},
7348 [60] = { ALU_OP0_NOP, tgsi_unsupported},
7349 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
7350 [62] = { ALU_OP0_NOP, tgsi_unsupported},
7351 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
7352 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
7353 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
7354 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
7355 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
7356 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7357 [69] = { ALU_OP0_NOP, tgsi_unsupported},
7358 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
7359 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
7360 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7361 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
7362 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
7363 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
7364 [76] = { ALU_OP0_NOP, tgsi_unsupported},
7365 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
7366 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
7367 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
7368 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
7369 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
7370 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
7371 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
7372 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
7373 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
7374 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
7375 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
7376 [88] = { ALU_OP0_NOP, tgsi_unsupported},
7377 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
7378 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
7379 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
7380 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
7381 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
7382 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
7383 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7384 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
7385 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
7386 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
7387 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
7388 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7389 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
7390 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7391 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7392 [104] = { ALU_OP0_NOP, tgsi_unsupported},
7393 [105] = { ALU_OP0_NOP, tgsi_unsupported},
7394 [106] = { ALU_OP0_NOP, tgsi_unsupported},
7395 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
7396 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
7397 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
7398 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
7399 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
7400 [112] = { ALU_OP0_NOP, tgsi_unsupported},
7401 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
7402 [114] = { ALU_OP0_NOP, tgsi_unsupported},
7403 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
7404 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
7405 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
7406 [118] = { ALU_OP0_NOP, tgsi_unsupported},
7407 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
7408 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
7409 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
7410 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
7411 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
7412 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
7413 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
7414 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
7415 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
7416 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
7417 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
7418 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
7419 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
7420 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
7421 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
7422 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
7423 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
7424 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
7425 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
7426 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
7427 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
7428 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
7429 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7430 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
7431 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
7432 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7433 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
7434 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
7435 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
7436 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
7437 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
7438 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
7439 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
7440 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
7441 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
7442 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
7443 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
7444 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
7445 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
7446 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
7447 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
7448 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
7449 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
7450 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
7451 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7452 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7453 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7454 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
7455 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
7456 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
7457 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
7458 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
7459 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
7460 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
7461 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
7462 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
7463 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
7464 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
7465 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
7466 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7467 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7468 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
7469 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
7470 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
7471 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
7472 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
7473 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
7474 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
7475 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
7476 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
7477 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
7478 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
7479 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
7480 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
7481 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
7482 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
7483 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
7484 };
7485
7486 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
7487 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
7488 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
7489 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
7490 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
7491 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
7492 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
7493 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
7494 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
7495 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
7496 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
7497 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
7498 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
7499 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
7500 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
7501 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
7502 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
7503 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
7504 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
7505 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
7506 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
7507 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
7508 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
7509 [22] = { ALU_OP0_NOP, tgsi_unsupported},
7510 [23] = { ALU_OP0_NOP, tgsi_unsupported},
7511 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
7512 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
7513 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
7514 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
7515 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
7516 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
7517 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
7518 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
7519 [32] = { ALU_OP0_NOP, tgsi_unsupported},
7520 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
7521 [34] = { ALU_OP0_NOP, tgsi_unsupported},
7522 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
7523 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
7524 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7525 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7526 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
7527 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
7528 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
7529 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
7530 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7531 [44] = { ALU_OP0_NOP, tgsi_unsupported},
7532 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
7533 [46] = { ALU_OP0_NOP, tgsi_unsupported},
7534 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
7535 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
7536 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
7537 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
7538 [51] = { ALU_OP0_NOP, tgsi_unsupported},
7539 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
7540 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
7541 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
7542 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
7543 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
7544 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
7545 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7546 [59] = { ALU_OP0_NOP, tgsi_unsupported},
7547 [60] = { ALU_OP0_NOP, tgsi_unsupported},
7548 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
7549 [62] = { ALU_OP0_NOP, tgsi_unsupported},
7550 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
7551 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
7552 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
7553 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
7554 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
7555 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7556 [69] = { ALU_OP0_NOP, tgsi_unsupported},
7557 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
7558 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
7559 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7560 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
7561 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
7562 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
7563 [76] = { ALU_OP0_NOP, tgsi_unsupported},
7564 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
7565 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
7566 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7567 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7568 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
7569 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
7570 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
7571 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
7572 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
7573 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
7574 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
7575 [88] = { ALU_OP0_NOP, tgsi_unsupported},
7576 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
7577 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
7578 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
7579 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
7580 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
7581 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
7582 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7583 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
7584 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
7585 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
7586 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
7587 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7588 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
7589 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7590 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7591 [104] = { ALU_OP0_NOP, tgsi_unsupported},
7592 [105] = { ALU_OP0_NOP, tgsi_unsupported},
7593 [106] = { ALU_OP0_NOP, tgsi_unsupported},
7594 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
7595 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
7596 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
7597 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
7598 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
7599 [112] = { ALU_OP0_NOP, tgsi_unsupported},
7600 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
7601 [114] = { ALU_OP0_NOP, tgsi_unsupported},
7602 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
7603 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
7604 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
7605 [118] = { ALU_OP0_NOP, tgsi_unsupported},
7606 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
7607 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
7608 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
7609 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
7610 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
7611 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
7612 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
7613 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
7614 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
7615 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
7616 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
7617 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
7618 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
7619 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
7620 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
7621 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
7622 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
7623 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
7624 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
7625 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
7626 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
7627 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
7628 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7629 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
7630 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
7631 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7632 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
7633 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
7634 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
7635 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
7636 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
7637 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
7638 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
7639 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
7640 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
7641 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
7642 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
7643 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
7644 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
7645 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
7646 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
7647 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
7648 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
7649 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
7650 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7651 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7652 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7653 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
7654 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
7655 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
7656 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
7657 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
7658 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
7659 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
7660 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
7661 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
7662 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
7663 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
7664 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
7665 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7666 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7667 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
7668 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
7669 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
7670 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
7671 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
7672 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
7673 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
7674 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
7675 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
7676 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
7677 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
7678 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
7679 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
7680 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
7681 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
7682 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
7683 };
7684
7685 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
7686 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
7687 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
7688 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
7689 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
7690 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
7691 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
7692 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
7693 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
7694 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
7695 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
7696 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
7697 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
7698 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
7699 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
7700 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
7701 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
7702 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
7703 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
7704 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
7705 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
7706 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
7707 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
7708 [22] = { ALU_OP0_NOP, tgsi_unsupported},
7709 [23] = { ALU_OP0_NOP, tgsi_unsupported},
7710 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
7711 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
7712 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
7713 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
7714 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
7715 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
7716 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
7717 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
7718 [32] = { ALU_OP0_NOP, tgsi_unsupported},
7719 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
7720 [34] = { ALU_OP0_NOP, tgsi_unsupported},
7721 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
7722 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
7723 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7724 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7725 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
7726 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
7727 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
7728 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
7729 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7730 [44] = { ALU_OP0_NOP, tgsi_unsupported},
7731 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
7732 [46] = { ALU_OP0_NOP, tgsi_unsupported},
7733 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
7734 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
7735 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
7736 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
7737 [51] = { ALU_OP0_NOP, tgsi_unsupported},
7738 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
7739 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
7740 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
7741 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
7742 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
7743 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
7744 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7745 [59] = { ALU_OP0_NOP, tgsi_unsupported},
7746 [60] = { ALU_OP0_NOP, tgsi_unsupported},
7747 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
7748 [62] = { ALU_OP0_NOP, tgsi_unsupported},
7749 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
7750 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
7751 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
7752 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
7753 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
7754 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7755 [69] = { ALU_OP0_NOP, tgsi_unsupported},
7756 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
7757 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
7758 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7759 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
7760 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
7761 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
7762 [76] = { ALU_OP0_NOP, tgsi_unsupported},
7763 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
7764 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
7765 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7766 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7767 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
7768 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
7769 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
7770 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
7771 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
7772 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
7773 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
7774 [88] = { ALU_OP0_NOP, tgsi_unsupported},
7775 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
7776 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
7777 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
7778 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
7779 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
7780 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
7781 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7782 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
7783 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
7784 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
7785 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
7786 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7787 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
7788 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7789 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7790 [104] = { ALU_OP0_NOP, tgsi_unsupported},
7791 [105] = { ALU_OP0_NOP, tgsi_unsupported},
7792 [106] = { ALU_OP0_NOP, tgsi_unsupported},
7793 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
7794 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
7795 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
7796 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
7797 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
7798 [112] = { ALU_OP0_NOP, tgsi_unsupported},
7799 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
7800 [114] = { ALU_OP0_NOP, tgsi_unsupported},
7801 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
7802 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
7803 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
7804 [118] = { ALU_OP0_NOP, tgsi_unsupported},
7805 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
7806 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
7807 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
7808 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
7809 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
7810 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
7811 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
7812 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
7813 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
7814 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
7815 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
7816 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
7817 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
7818 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
7819 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
7820 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
7821 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
7822 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
7823 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
7824 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
7825 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
7826 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
7827 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7828 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
7829 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
7830 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7831 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
7832 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
7833 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
7834 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
7835 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
7836 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
7837 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
7838 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
7839 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
7840 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
7841 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
7842 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
7843 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
7844 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
7845 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
7846 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
7847 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
7848 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
7849 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7850 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7851 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7852 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
7853 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
7854 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
7855 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
7856 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
7857 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
7858 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
7859 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
7860 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
7861 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
7862 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
7863 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
7864 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7865 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7866 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
7867 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
7868 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
7869 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
7870 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
7871 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
7872 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
7873 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
7874 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
7875 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
7876 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
7877 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
7878 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
7879 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
7880 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
7881 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
7882 };