2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
29 #include "sb/sb_public.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
43 Why CAYMAN got loops for lots of instructions is explained here.
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
63 /* Contents of r0 on entry to various shaders
69 GS - r0.xyw, r1.xyz = per-vertex offsets
75 .w = tess factor base.
77 TES - .x = TessCoord.x
79 - .z = RelPatchID (??)
82 PS - face_gpr.z = SampleMask
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
87 struct r600_pipe_shader
*pipeshader
,
88 union r600_shader_key key
);
90 static void r600_add_gpr_array(struct r600_shader
*ps
, int start_gpr
,
91 int size
, unsigned comp_mask
) {
96 if (ps
->num_arrays
== ps
->max_arrays
) {
98 ps
->arrays
= realloc(ps
->arrays
, ps
->max_arrays
*
99 sizeof(struct r600_shader_array
));
102 int n
= ps
->num_arrays
;
105 ps
->arrays
[n
].comp_mask
= comp_mask
;
106 ps
->arrays
[n
].gpr_start
= start_gpr
;
107 ps
->arrays
[n
].gpr_count
= size
;
110 static void r600_dump_streamout(struct pipe_stream_output_info
*so
)
114 fprintf(stderr
, "STREAMOUT\n");
115 for (i
= 0; i
< so
->num_outputs
; i
++) {
116 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
117 so
->output
[i
].start_component
;
118 fprintf(stderr
, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
120 so
->output
[i
].stream
,
121 so
->output
[i
].output_buffer
,
122 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
123 so
->output
[i
].register_index
,
128 so
->output
[i
].dst_offset
< so
->output
[i
].start_component
? " (will lower)" : "");
132 static int store_shader(struct pipe_context
*ctx
,
133 struct r600_pipe_shader
*shader
)
135 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
138 if (shader
->bo
== NULL
) {
139 shader
->bo
= (struct r600_resource
*)
140 pipe_buffer_create(ctx
->screen
, 0, PIPE_USAGE_IMMUTABLE
, shader
->shader
.bc
.ndw
* 4);
141 if (shader
->bo
== NULL
) {
144 ptr
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->bo
, PIPE_TRANSFER_WRITE
);
145 if (R600_BIG_ENDIAN
) {
146 for (i
= 0; i
< shader
->shader
.bc
.ndw
; ++i
) {
147 ptr
[i
] = util_cpu_to_le32(shader
->shader
.bc
.bytecode
[i
]);
150 memcpy(ptr
, shader
->shader
.bc
.bytecode
, shader
->shader
.bc
.ndw
* sizeof(*ptr
));
152 rctx
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
158 int r600_pipe_shader_create(struct pipe_context
*ctx
,
159 struct r600_pipe_shader
*shader
,
160 union r600_shader_key key
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_shader_selector
*sel
= shader
->selector
;
165 bool dump
= r600_can_dump_shader(&rctx
->screen
->b
,
166 tgsi_get_processor_type(sel
->tokens
));
167 unsigned use_sb
= !(rctx
->screen
->b
.debug_flags
& DBG_NO_SB
);
168 unsigned sb_disasm
= use_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
169 unsigned export_shader
;
171 shader
->shader
.bc
.isa
= rctx
->isa
;
174 fprintf(stderr
, "--------------------------------------------------------------\n");
175 tgsi_dump(sel
->tokens
, 0);
177 if (sel
->so
.num_outputs
) {
178 r600_dump_streamout(&sel
->so
);
181 r
= r600_shader_from_tgsi(rctx
, shader
, key
);
183 R600_ERR("translation from TGSI failed !\n");
186 if (shader
->shader
.processor_type
== PIPE_SHADER_VERTEX
) {
187 /* only disable for vertex shaders in tess paths */
191 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_CTRL
);
192 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_EVAL
);
194 /* disable SB for shaders using doubles */
195 use_sb
&= !shader
->shader
.uses_doubles
;
197 use_sb
&= !shader
->shader
.uses_atomics
;
198 use_sb
&= !shader
->shader
.uses_images
;
200 /* Check if the bytecode has already been built. */
201 if (!shader
->shader
.bc
.bytecode
) {
202 r
= r600_bytecode_build(&shader
->shader
.bc
);
204 R600_ERR("building bytecode failed !\n");
209 if (dump
&& !sb_disasm
) {
210 fprintf(stderr
, "--------------------------------------------------------------\n");
211 r600_bytecode_disasm(&shader
->shader
.bc
);
212 fprintf(stderr
, "______________________________________________________________\n");
213 } else if ((dump
&& sb_disasm
) || use_sb
) {
214 r
= r600_sb_bytecode_process(rctx
, &shader
->shader
.bc
, &shader
->shader
,
217 R600_ERR("r600_sb_bytecode_process failed !\n");
222 if (shader
->gs_copy_shader
) {
225 r
= r600_sb_bytecode_process(rctx
, &shader
->gs_copy_shader
->shader
.bc
,
226 &shader
->gs_copy_shader
->shader
, dump
, 0);
231 if ((r
= store_shader(ctx
, shader
->gs_copy_shader
)))
235 /* Store the shader in a buffer. */
236 if ((r
= store_shader(ctx
, shader
)))
240 switch (shader
->shader
.processor_type
) {
241 case PIPE_SHADER_TESS_CTRL
:
242 evergreen_update_hs_state(ctx
, shader
);
244 case PIPE_SHADER_TESS_EVAL
:
246 evergreen_update_es_state(ctx
, shader
);
248 evergreen_update_vs_state(ctx
, shader
);
250 case PIPE_SHADER_GEOMETRY
:
251 if (rctx
->b
.chip_class
>= EVERGREEN
) {
252 evergreen_update_gs_state(ctx
, shader
);
253 evergreen_update_vs_state(ctx
, shader
->gs_copy_shader
);
255 r600_update_gs_state(ctx
, shader
);
256 r600_update_vs_state(ctx
, shader
->gs_copy_shader
);
259 case PIPE_SHADER_VERTEX
:
260 export_shader
= key
.vs
.as_es
;
261 if (rctx
->b
.chip_class
>= EVERGREEN
) {
263 evergreen_update_ls_state(ctx
, shader
);
264 else if (key
.vs
.as_es
)
265 evergreen_update_es_state(ctx
, shader
);
267 evergreen_update_vs_state(ctx
, shader
);
270 r600_update_es_state(ctx
, shader
);
272 r600_update_vs_state(ctx
, shader
);
275 case PIPE_SHADER_FRAGMENT
:
276 if (rctx
->b
.chip_class
>= EVERGREEN
) {
277 evergreen_update_ps_state(ctx
, shader
);
279 r600_update_ps_state(ctx
, shader
);
289 r600_pipe_shader_destroy(ctx
, shader
);
293 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
295 r600_resource_reference(&shader
->bo
, NULL
);
296 r600_bytecode_clear(&shader
->shader
.bc
);
297 r600_release_command_buffer(&shader
->command_buffer
);
301 * tgsi -> r600 shader
303 struct r600_shader_tgsi_instruction
;
305 struct r600_shader_src
{
312 boolean kc_rel
; /* true if cache bank is indexed */
321 struct r600_shader_ctx
{
322 struct tgsi_shader_info info
;
323 struct tgsi_parse_context parse
;
324 const struct tgsi_token
*tokens
;
326 unsigned file_offset
[TGSI_FILE_COUNT
];
328 const struct r600_shader_tgsi_instruction
*inst_info
;
329 struct r600_bytecode
*bc
;
330 struct r600_shader
*shader
;
331 struct r600_shader_src src
[4];
334 uint32_t max_driver_temp_used
;
335 /* needed for evergreen interpolation */
336 struct eg_interp eg_interpolators
[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
337 /* evergreen/cayman also store sample mask in face register */
339 /* sample id is .w component stored in fixed point position register */
340 int fixed_pt_position_gpr
;
342 boolean clip_vertex_write
;
344 unsigned edgeflag_output
;
347 int next_ring_offset
;
348 int gs_out_ring_offset
;
350 struct r600_shader
*gs_for_vs
;
351 int gs_export_gpr_tregs
[4];
352 int gs_rotated_input
[2];
353 const struct pipe_stream_output_info
*gs_stream_output_info
;
354 unsigned enabled_stream_buffers_mask
;
355 unsigned tess_input_info
; /* temp with tess input offsets */
356 unsigned tess_output_info
; /* temp with tess input offsets */
357 unsigned thread_id_gpr
; /* temp with thread id calculated for images */
360 struct r600_shader_tgsi_instruction
{
362 int (*process
)(struct r600_shader_ctx
*ctx
);
365 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
);
366 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
367 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
368 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
);
369 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
);
370 static int tgsi_else(struct r600_shader_ctx
*ctx
);
371 static int tgsi_endif(struct r600_shader_ctx
*ctx
);
372 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
);
373 static int tgsi_endloop(struct r600_shader_ctx
*ctx
);
374 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
);
375 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
376 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
377 unsigned int dst_reg
);
378 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
379 const struct r600_shader_src
*shader_src
,
381 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
384 static int tgsi_last_instruction(unsigned writemask
)
388 for (i
= 0; i
< 4; i
++) {
389 if (writemask
& (1 << i
)) {
396 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
398 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
401 if (i
->Instruction
.NumDstRegs
> 1 && i
->Instruction
.Opcode
!= TGSI_OPCODE_DFRACEXP
) {
402 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
406 if (i
->Instruction
.Label
) {
407 R600_ERR("label unsupported\n");
411 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
412 if (i
->Src
[j
].Register
.Dimension
) {
413 switch (i
->Src
[j
].Register
.File
) {
414 case TGSI_FILE_CONSTANT
:
415 case TGSI_FILE_HW_ATOMIC
:
417 case TGSI_FILE_INPUT
:
418 if (ctx
->type
== PIPE_SHADER_GEOMETRY
||
419 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
420 ctx
->type
== PIPE_SHADER_TESS_EVAL
)
422 case TGSI_FILE_OUTPUT
:
423 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
426 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j
,
427 i
->Src
[j
].Register
.File
,
428 i
->Src
[j
].Register
.Dimension
);
433 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
434 if (i
->Dst
[j
].Register
.Dimension
) {
435 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
437 R600_ERR("unsupported dst (dimension)\n");
444 int eg_get_interpolator_index(unsigned interpolate
, unsigned location
)
446 if (interpolate
== TGSI_INTERPOLATE_COLOR
||
447 interpolate
== TGSI_INTERPOLATE_LINEAR
||
448 interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
450 int is_linear
= interpolate
== TGSI_INTERPOLATE_LINEAR
;
454 case TGSI_INTERPOLATE_LOC_CENTER
:
457 case TGSI_INTERPOLATE_LOC_CENTROID
:
460 case TGSI_INTERPOLATE_LOC_SAMPLE
:
465 return is_linear
* 3 + loc
;
471 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx
*ctx
,
474 int i
= eg_get_interpolator_index(
475 ctx
->shader
->input
[input
].interpolate
,
476 ctx
->shader
->input
[input
].interpolate_location
);
478 ctx
->shader
->input
[input
].ij_index
= ctx
->eg_interpolators
[i
].ij_index
;
481 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
484 struct r600_bytecode_alu alu
;
485 int gpr
= 0, base_chan
= 0;
486 int ij_index
= ctx
->shader
->input
[input
].ij_index
;
488 /* work out gpr and base_chan from index */
490 base_chan
= (2 * (ij_index
% 2)) + 1;
492 for (i
= 0; i
< 8; i
++) {
493 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
496 alu
.op
= ALU_OP2_INTERP_ZW
;
498 alu
.op
= ALU_OP2_INTERP_XY
;
500 if ((i
> 1) && (i
< 6)) {
501 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
505 alu
.dst
.chan
= i
% 4;
507 alu
.src
[0].sel
= gpr
;
508 alu
.src
[0].chan
= (base_chan
- (i
% 2));
510 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
512 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
515 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
522 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
525 struct r600_bytecode_alu alu
;
527 for (i
= 0; i
< 4; i
++) {
528 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
530 alu
.op
= ALU_OP1_INTERP_LOAD_P0
;
532 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
537 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
542 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
550 * Special export handling in shaders
552 * shader export ARRAY_BASE for EXPORT_POS:
555 * 62, 63 are clip distance vectors
557 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
558 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
559 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
560 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
561 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
562 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
563 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
564 * exclusive from render target index)
565 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
568 * shader export ARRAY_BASE for EXPORT_PIXEL:
570 * 61 computed Z vector
572 * The use of the values exported in the computed Z vector are controlled
573 * by DB_SHADER_CONTROL:
574 * Z_EXPORT_ENABLE - Z as a float in RED
575 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
576 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
577 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
578 * DB_SOURCE_FORMAT - export control restrictions
583 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
584 static int r600_spi_sid(struct r600_shader_io
* io
)
586 int index
, name
= io
->name
;
588 /* These params are handled differently, they don't need
589 * semantic indices, so we'll use 0 for them.
591 if (name
== TGSI_SEMANTIC_POSITION
||
592 name
== TGSI_SEMANTIC_PSIZE
||
593 name
== TGSI_SEMANTIC_EDGEFLAG
||
594 name
== TGSI_SEMANTIC_FACE
||
595 name
== TGSI_SEMANTIC_SAMPLEMASK
)
598 if (name
== TGSI_SEMANTIC_GENERIC
) {
599 /* For generic params simply use sid from tgsi */
602 /* For non-generic params - pack name and sid into 8 bits */
603 index
= 0x80 | (name
<<3) | (io
->sid
);
606 /* Make sure that all really used indices have nonzero value, so
607 * we can just compare it to 0 later instead of comparing the name
608 * with different values to detect special cases. */
615 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
616 int r600_get_lds_unique_index(unsigned semantic_name
, unsigned index
)
618 switch (semantic_name
) {
619 case TGSI_SEMANTIC_POSITION
:
621 case TGSI_SEMANTIC_PSIZE
:
623 case TGSI_SEMANTIC_CLIPDIST
:
626 case TGSI_SEMANTIC_GENERIC
:
628 return 4 + index
- 9;
630 /* same explanation as in the default statement,
631 * the only user hitting this is st/nine.
635 /* patch indices are completely separate and thus start from 0 */
636 case TGSI_SEMANTIC_TESSOUTER
:
638 case TGSI_SEMANTIC_TESSINNER
:
640 case TGSI_SEMANTIC_PATCH
:
644 /* Don't fail here. The result of this function is only used
645 * for LS, TCS, TES, and GS, where legacy GL semantics can't
646 * occur, but this function is called for all vertex shaders
647 * before it's known whether LS will be compiled or not.
653 /* turn input into interpolate on EG */
654 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
658 if (ctx
->shader
->input
[index
].spi_sid
) {
659 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
660 if (ctx
->shader
->input
[index
].interpolate
> 0) {
661 evergreen_interp_assign_ij_index(ctx
, index
);
662 r
= evergreen_interp_alu(ctx
, index
);
664 r
= evergreen_interp_flat(ctx
, index
);
670 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
672 struct r600_bytecode_alu alu
;
674 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
675 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
677 for (i
= 0; i
< 4; i
++) {
678 memset(&alu
, 0, sizeof(alu
));
679 alu
.op
= ALU_OP3_CNDGT
;
682 alu
.dst
.sel
= gpr_front
;
683 alu
.src
[0].sel
= ctx
->face_gpr
;
684 alu
.src
[1].sel
= gpr_front
;
685 alu
.src
[2].sel
= gpr_back
;
692 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
699 /* execute a single slot ALU calculation */
700 static int single_alu_op2(struct r600_shader_ctx
*ctx
, int op
,
701 int dst_sel
, int dst_chan
,
702 int src0_sel
, unsigned src0_chan_val
,
703 int src1_sel
, unsigned src1_chan_val
)
705 struct r600_bytecode_alu alu
;
708 if (ctx
->bc
->chip_class
== CAYMAN
&& op
== ALU_OP2_MULLO_INT
) {
709 for (i
= 0; i
< 4; i
++) {
710 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
712 alu
.src
[0].sel
= src0_sel
;
713 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
714 alu
.src
[0].value
= src0_chan_val
;
716 alu
.src
[0].chan
= src0_chan_val
;
717 alu
.src
[1].sel
= src1_sel
;
718 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
719 alu
.src
[1].value
= src1_chan_val
;
721 alu
.src
[1].chan
= src1_chan_val
;
722 alu
.dst
.sel
= dst_sel
;
724 alu
.dst
.write
= i
== dst_chan
;
726 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
733 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
735 alu
.src
[0].sel
= src0_sel
;
736 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
737 alu
.src
[0].value
= src0_chan_val
;
739 alu
.src
[0].chan
= src0_chan_val
;
740 alu
.src
[1].sel
= src1_sel
;
741 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
742 alu
.src
[1].value
= src1_chan_val
;
744 alu
.src
[1].chan
= src1_chan_val
;
745 alu
.dst
.sel
= dst_sel
;
746 alu
.dst
.chan
= dst_chan
;
749 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
755 /* execute a single slot ALU calculation */
756 static int single_alu_op3(struct r600_shader_ctx
*ctx
, int op
,
757 int dst_sel
, int dst_chan
,
758 int src0_sel
, unsigned src0_chan_val
,
759 int src1_sel
, unsigned src1_chan_val
,
760 int src2_sel
, unsigned src2_chan_val
)
762 struct r600_bytecode_alu alu
;
765 /* validate this for other ops */
766 assert(op
== ALU_OP3_MULADD_UINT24
|| op
== ALU_OP3_CNDE_INT
);
767 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
769 alu
.src
[0].sel
= src0_sel
;
770 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
771 alu
.src
[0].value
= src0_chan_val
;
773 alu
.src
[0].chan
= src0_chan_val
;
774 alu
.src
[1].sel
= src1_sel
;
775 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
776 alu
.src
[1].value
= src1_chan_val
;
778 alu
.src
[1].chan
= src1_chan_val
;
779 alu
.src
[2].sel
= src2_sel
;
780 if (src2_sel
== V_SQ_ALU_SRC_LITERAL
)
781 alu
.src
[2].value
= src2_chan_val
;
783 alu
.src
[2].chan
= src2_chan_val
;
784 alu
.dst
.sel
= dst_sel
;
785 alu
.dst
.chan
= dst_chan
;
788 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
794 /* put it in temp_reg.x */
795 static int get_lds_offset0(struct r600_shader_ctx
*ctx
,
797 int temp_reg
, bool is_patch_var
)
801 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
803 Dimension - patch0_offset (input_vals.z),
804 Non-dim - patch0_data_offset (input_vals.w)
806 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
808 ctx
->tess_output_info
, 0,
810 ctx
->tess_output_info
, is_patch_var
? 3 : 2);
816 static inline int get_address_file_reg(struct r600_shader_ctx
*ctx
, int index
)
818 return index
> 0 ? ctx
->bc
->index_reg
[index
- 1] : ctx
->bc
->ar_reg
;
821 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
823 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
826 static int vs_add_primid_output(struct r600_shader_ctx
*ctx
, int prim_id_sid
)
829 i
= ctx
->shader
->noutput
++;
830 ctx
->shader
->output
[i
].name
= TGSI_SEMANTIC_PRIMID
;
831 ctx
->shader
->output
[i
].sid
= 0;
832 ctx
->shader
->output
[i
].gpr
= 0;
833 ctx
->shader
->output
[i
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
834 ctx
->shader
->output
[i
].write_mask
= 0x4;
835 ctx
->shader
->output
[i
].spi_sid
= prim_id_sid
;
840 static int tgsi_barrier(struct r600_shader_ctx
*ctx
)
842 struct r600_bytecode_alu alu
;
845 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
846 alu
.op
= ctx
->inst_info
->op
;
849 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
855 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
857 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
858 int r
, i
, j
, count
= d
->Range
.Last
- d
->Range
.First
+ 1;
860 switch (d
->Declaration
.File
) {
861 case TGSI_FILE_INPUT
:
862 for (j
= 0; j
< count
; j
++) {
863 i
= ctx
->shader
->ninput
+ j
;
864 assert(i
< ARRAY_SIZE(ctx
->shader
->input
));
865 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
866 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
+ j
;
867 ctx
->shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
868 ctx
->shader
->input
[i
].interpolate_location
= d
->Interp
.Location
;
869 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
+ j
;
870 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
871 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
872 switch (ctx
->shader
->input
[i
].name
) {
873 case TGSI_SEMANTIC_FACE
:
874 if (ctx
->face_gpr
!= -1)
875 ctx
->shader
->input
[i
].gpr
= ctx
->face_gpr
; /* already allocated by allocate_system_value_inputs */
877 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
879 case TGSI_SEMANTIC_COLOR
:
882 case TGSI_SEMANTIC_POSITION
:
883 ctx
->fragcoord_input
= i
;
885 case TGSI_SEMANTIC_PRIMID
:
886 /* set this for now */
887 ctx
->shader
->gs_prim_id_input
= true;
888 ctx
->shader
->ps_prim_id_input
= i
;
891 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
892 if ((r
= evergreen_interp_input(ctx
, i
)))
895 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
896 /* FIXME probably skip inputs if they aren't passed in the ring */
897 ctx
->shader
->input
[i
].ring_offset
= ctx
->next_ring_offset
;
898 ctx
->next_ring_offset
+= 16;
899 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_PRIMID
)
900 ctx
->shader
->gs_prim_id_input
= true;
903 ctx
->shader
->ninput
+= count
;
905 case TGSI_FILE_OUTPUT
:
906 for (j
= 0; j
< count
; j
++) {
907 i
= ctx
->shader
->noutput
+ j
;
908 assert(i
< ARRAY_SIZE(ctx
->shader
->output
));
909 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
910 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
+ j
;
911 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
+ j
;
912 ctx
->shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
913 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
914 if (ctx
->type
== PIPE_SHADER_VERTEX
||
915 ctx
->type
== PIPE_SHADER_GEOMETRY
||
916 ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
917 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
918 switch (d
->Semantic
.Name
) {
919 case TGSI_SEMANTIC_CLIPDIST
:
920 ctx
->shader
->clip_dist_write
|= d
->Declaration
.UsageMask
<<
921 ((d
->Semantic
.Index
+ j
) << 2);
923 case TGSI_SEMANTIC_PSIZE
:
924 ctx
->shader
->vs_out_misc_write
= 1;
925 ctx
->shader
->vs_out_point_size
= 1;
927 case TGSI_SEMANTIC_EDGEFLAG
:
928 ctx
->shader
->vs_out_misc_write
= 1;
929 ctx
->shader
->vs_out_edgeflag
= 1;
930 ctx
->edgeflag_output
= i
;
932 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
933 ctx
->shader
->vs_out_misc_write
= 1;
934 ctx
->shader
->vs_out_viewport
= 1;
936 case TGSI_SEMANTIC_LAYER
:
937 ctx
->shader
->vs_out_misc_write
= 1;
938 ctx
->shader
->vs_out_layer
= 1;
940 case TGSI_SEMANTIC_CLIPVERTEX
:
941 ctx
->clip_vertex_write
= TRUE
;
945 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
946 ctx
->gs_out_ring_offset
+= 16;
948 } else if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
949 switch (d
->Semantic
.Name
) {
950 case TGSI_SEMANTIC_COLOR
:
951 ctx
->shader
->nr_ps_max_color_exports
++;
956 ctx
->shader
->noutput
+= count
;
958 case TGSI_FILE_TEMPORARY
:
959 if (ctx
->info
.indirect_files
& (1 << TGSI_FILE_TEMPORARY
)) {
960 if (d
->Array
.ArrayID
) {
961 r600_add_gpr_array(ctx
->shader
,
962 ctx
->file_offset
[TGSI_FILE_TEMPORARY
] +
964 d
->Range
.Last
- d
->Range
.First
+ 1, 0x0F);
969 case TGSI_FILE_CONSTANT
:
970 case TGSI_FILE_SAMPLER
:
971 case TGSI_FILE_SAMPLER_VIEW
:
972 case TGSI_FILE_ADDRESS
:
973 case TGSI_FILE_IMAGE
:
976 case TGSI_FILE_HW_ATOMIC
:
977 i
= ctx
->shader
->nhwatomic_ranges
;
978 ctx
->shader
->atomics
[i
].start
= d
->Range
.First
;
979 ctx
->shader
->atomics
[i
].end
= d
->Range
.Last
;
980 ctx
->shader
->atomics
[i
].hw_idx
= ctx
->shader
->atomic_base
+ ctx
->shader
->nhwatomic
;
981 ctx
->shader
->atomics
[i
].array_id
= d
->Array
.ArrayID
;
982 ctx
->shader
->atomics
[i
].buffer_id
= d
->Dim
.Index2D
;
983 ctx
->shader
->nhwatomic_ranges
++;
984 ctx
->shader
->nhwatomic
+= count
;
987 case TGSI_FILE_SYSTEM_VALUE
:
988 if (d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEMASK
||
989 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEID
||
990 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEPOS
) {
991 break; /* Already handled from allocate_system_value_inputs */
992 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
993 if (!ctx
->native_integers
) {
994 struct r600_bytecode_alu alu
;
995 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
997 alu
.op
= ALU_OP1_INT_TO_FLT
;
1006 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1010 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
1012 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INVOCATIONID
)
1014 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
||
1015 d
->Semantic
.Name
== TGSI_SEMANTIC_TESSOUTER
) {
1016 int param
= r600_get_lds_unique_index(d
->Semantic
.Name
, 0);
1017 int dreg
= d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
? 3 : 2;
1018 unsigned temp_reg
= r600_get_temp(ctx
);
1020 r
= get_lds_offset0(ctx
, 2, temp_reg
, true);
1024 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1027 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1031 do_lds_fetch_values(ctx
, temp_reg
, dreg
);
1033 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSCOORD
) {
1037 for (i
= 0; i
< 2; i
++) {
1038 struct r600_bytecode_alu alu
;
1039 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1040 alu
.op
= ALU_OP1_MOV
;
1042 alu
.src
[0].chan
= 0 + i
;
1044 alu
.dst
.chan
= 0 + i
;
1046 alu
.last
= (i
== 1) ? 1 : 0;
1047 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1050 /* ADD r1.z, 1.0f, -r0.x */
1051 struct r600_bytecode_alu alu
;
1052 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1053 alu
.op
= ALU_OP2_ADD
;
1054 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1056 alu
.src
[1].chan
= 0;
1062 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1065 /* ADD r1.z, r1.z, -r1.y */
1066 alu
.op
= ALU_OP2_ADD
;
1068 alu
.src
[0].chan
= 2;
1070 alu
.src
[1].chan
= 1;
1076 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1082 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
1088 static int allocate_system_value_inputs(struct r600_shader_ctx
*ctx
, int gpr_offset
)
1090 struct tgsi_parse_context parse
;
1094 unsigned name
, alternate_name
;
1096 { false, &ctx
->face_gpr
, TGSI_SEMANTIC_SAMPLEMASK
, ~0u }, /* lives in Front Face GPR.z */
1098 { false, &ctx
->fixed_pt_position_gpr
, TGSI_SEMANTIC_SAMPLEID
, TGSI_SEMANTIC_SAMPLEPOS
} /* SAMPLEID is in Fixed Point Position GPR.w */
1100 int i
, k
, num_regs
= 0;
1102 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1106 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1107 while (!tgsi_parse_end_of_tokens(&parse
)) {
1108 tgsi_parse_token(&parse
);
1110 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1111 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1112 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1113 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1114 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1116 int interpolate
, location
, k
;
1118 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1119 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1120 inputs
[1].enabled
= true; /* needs SAMPLEID */
1121 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1122 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1123 /* Needs sample positions, currently those are always available */
1125 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1128 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1129 k
= eg_get_interpolator_index(interpolate
, location
);
1131 ctx
->eg_interpolators
[k
].enabled
= true;
1133 } else if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_DECLARATION
) {
1134 struct tgsi_full_declaration
*d
= &parse
.FullToken
.FullDeclaration
;
1135 if (d
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1136 for (k
= 0; k
< ARRAY_SIZE(inputs
); k
++) {
1137 if (d
->Semantic
.Name
== inputs
[k
].name
||
1138 d
->Semantic
.Name
== inputs
[k
].alternate_name
) {
1139 inputs
[k
].enabled
= true;
1146 tgsi_parse_free(&parse
);
1148 for (i
= 0; i
< ARRAY_SIZE(inputs
); i
++) {
1149 boolean enabled
= inputs
[i
].enabled
;
1150 int *reg
= inputs
[i
].reg
;
1151 unsigned name
= inputs
[i
].name
;
1154 int gpr
= gpr_offset
+ num_regs
++;
1155 ctx
->shader
->nsys_inputs
++;
1157 // add to inputs, allocate a gpr
1158 k
= ctx
->shader
->ninput
++;
1159 ctx
->shader
->input
[k
].name
= name
;
1160 ctx
->shader
->input
[k
].sid
= 0;
1161 ctx
->shader
->input
[k
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1162 ctx
->shader
->input
[k
].interpolate_location
= TGSI_INTERPOLATE_LOC_CENTER
;
1163 *reg
= ctx
->shader
->input
[k
].gpr
= gpr
;
1167 return gpr_offset
+ num_regs
;
1171 * for evergreen we need to scan the shader to find the number of GPRs we need to
1172 * reserve for interpolation and system values
1174 * we need to know if we are going to emit
1175 * any sample or centroid inputs
1176 * if perspective and linear are required
1178 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
1182 struct tgsi_parse_context parse
;
1184 memset(&ctx
->eg_interpolators
, 0, sizeof(ctx
->eg_interpolators
));
1186 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
1188 /* skip position/face/mask/sampleid */
1189 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
1190 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
||
1191 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEMASK
||
1192 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEID
)
1195 k
= eg_get_interpolator_index(
1196 ctx
->info
.input_interpolate
[i
],
1197 ctx
->info
.input_interpolate_loc
[i
]);
1199 ctx
->eg_interpolators
[k
].enabled
= TRUE
;
1202 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1206 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1207 while (!tgsi_parse_end_of_tokens(&parse
)) {
1208 tgsi_parse_token(&parse
);
1210 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1211 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1212 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1213 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1214 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1216 int interpolate
, location
, k
;
1218 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1219 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1220 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1221 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1223 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1226 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1227 k
= eg_get_interpolator_index(interpolate
, location
);
1229 ctx
->eg_interpolators
[k
].enabled
= true;
1234 tgsi_parse_free(&parse
);
1236 /* assign gpr to each interpolator according to priority */
1238 for (i
= 0; i
< ARRAY_SIZE(ctx
->eg_interpolators
); i
++) {
1239 if (ctx
->eg_interpolators
[i
].enabled
) {
1240 ctx
->eg_interpolators
[i
].ij_index
= num_baryc
;
1245 /* XXX PULL MODEL and LINE STIPPLE */
1247 num_baryc
= (num_baryc
+ 1) >> 1;
1248 return allocate_system_value_inputs(ctx
, num_baryc
);
1251 /* sample_id_sel == NULL means fetch for current sample */
1252 static int load_sample_position(struct r600_shader_ctx
*ctx
, struct r600_shader_src
*sample_id
, int chan_sel
)
1254 struct r600_bytecode_vtx vtx
;
1257 assert(ctx
->fixed_pt_position_gpr
!= -1);
1259 t1
= r600_get_temp(ctx
);
1261 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
1262 vtx
.op
= FETCH_OP_VFETCH
;
1263 vtx
.buffer_id
= R600_BUFFER_INFO_CONST_BUFFER
;
1264 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1265 if (sample_id
== NULL
) {
1266 vtx
.src_gpr
= ctx
->fixed_pt_position_gpr
; // SAMPLEID is in .w;
1270 struct r600_bytecode_alu alu
;
1272 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1273 alu
.op
= ALU_OP1_MOV
;
1274 r600_bytecode_src(&alu
.src
[0], sample_id
, chan_sel
);
1278 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1285 vtx
.mega_fetch_count
= 16;
1291 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1292 vtx
.num_format_all
= 2;
1293 vtx
.format_comp_all
= 1;
1294 vtx
.use_const_fields
= 0;
1295 vtx
.offset
= 1; // first element is size of buffer
1296 vtx
.endian
= r600_endian_swap(32);
1297 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
1299 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
1306 static void tgsi_src(struct r600_shader_ctx
*ctx
,
1307 const struct tgsi_full_src_register
*tgsi_src
,
1308 struct r600_shader_src
*r600_src
)
1310 memset(r600_src
, 0, sizeof(*r600_src
));
1311 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
1312 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
1313 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
1314 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
1315 r600_src
->neg
= tgsi_src
->Register
.Negate
;
1316 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
1318 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
1320 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
1321 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
1322 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
1324 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
1325 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
, r600_src
->abs
);
1326 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
1329 index
= tgsi_src
->Register
.Index
;
1330 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
1331 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
1332 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1333 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEMASK
) {
1334 r600_src
->swizzle
[0] = 2; // Z value
1335 r600_src
->swizzle
[1] = 2;
1336 r600_src
->swizzle
[2] = 2;
1337 r600_src
->swizzle
[3] = 2;
1338 r600_src
->sel
= ctx
->face_gpr
;
1339 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEID
) {
1340 r600_src
->swizzle
[0] = 3; // W value
1341 r600_src
->swizzle
[1] = 3;
1342 r600_src
->swizzle
[2] = 3;
1343 r600_src
->swizzle
[3] = 3;
1344 r600_src
->sel
= ctx
->fixed_pt_position_gpr
;
1345 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEPOS
) {
1346 r600_src
->swizzle
[0] = 0;
1347 r600_src
->swizzle
[1] = 1;
1348 r600_src
->swizzle
[2] = 4;
1349 r600_src
->swizzle
[3] = 4;
1350 r600_src
->sel
= load_sample_position(ctx
, NULL
, -1);
1351 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
1352 r600_src
->swizzle
[0] = 3;
1353 r600_src
->swizzle
[1] = 3;
1354 r600_src
->swizzle
[2] = 3;
1355 r600_src
->swizzle
[3] = 3;
1357 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
1358 r600_src
->swizzle
[0] = 0;
1359 r600_src
->swizzle
[1] = 0;
1360 r600_src
->swizzle
[2] = 0;
1361 r600_src
->swizzle
[3] = 0;
1363 } else if (ctx
->type
!= PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1364 r600_src
->swizzle
[0] = 3;
1365 r600_src
->swizzle
[1] = 3;
1366 r600_src
->swizzle
[2] = 3;
1367 r600_src
->swizzle
[3] = 3;
1369 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1370 r600_src
->swizzle
[0] = 2;
1371 r600_src
->swizzle
[1] = 2;
1372 r600_src
->swizzle
[2] = 2;
1373 r600_src
->swizzle
[3] = 2;
1375 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSCOORD
) {
1377 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSINNER
) {
1379 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSOUTER
) {
1381 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTICESIN
) {
1382 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
1383 r600_src
->sel
= ctx
->tess_input_info
;
1384 r600_src
->swizzle
[0] = 2;
1385 r600_src
->swizzle
[1] = 2;
1386 r600_src
->swizzle
[2] = 2;
1387 r600_src
->swizzle
[3] = 2;
1389 r600_src
->sel
= ctx
->tess_input_info
;
1390 r600_src
->swizzle
[0] = 3;
1391 r600_src
->swizzle
[1] = 3;
1392 r600_src
->swizzle
[2] = 3;
1393 r600_src
->swizzle
[3] = 3;
1395 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1397 r600_src
->swizzle
[0] = 0;
1398 r600_src
->swizzle
[1] = 0;
1399 r600_src
->swizzle
[2] = 0;
1400 r600_src
->swizzle
[3] = 0;
1401 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1403 r600_src
->swizzle
[0] = 3;
1404 r600_src
->swizzle
[1] = 3;
1405 r600_src
->swizzle
[2] = 3;
1406 r600_src
->swizzle
[3] = 3;
1409 if (tgsi_src
->Register
.Indirect
)
1410 r600_src
->rel
= V_SQ_REL_RELATIVE
;
1411 r600_src
->sel
= tgsi_src
->Register
.Index
;
1412 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
1414 if (tgsi_src
->Register
.File
== TGSI_FILE_CONSTANT
) {
1415 if (tgsi_src
->Register
.Dimension
) {
1416 r600_src
->kc_bank
= tgsi_src
->Dimension
.Index
;
1417 if (tgsi_src
->Dimension
.Indirect
) {
1418 r600_src
->kc_rel
= 1;
1424 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
1425 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
1426 unsigned int dst_reg
)
1428 struct r600_bytecode_vtx vtx
;
1429 unsigned int ar_reg
;
1433 struct r600_bytecode_alu alu
;
1435 memset(&alu
, 0, sizeof(alu
));
1437 alu
.op
= ALU_OP2_ADD_INT
;
1438 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
1439 alu
.src
[0].chan
= ar_chan
;
1441 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1442 alu
.src
[1].value
= offset
;
1444 alu
.dst
.sel
= dst_reg
;
1445 alu
.dst
.chan
= ar_chan
;
1449 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1454 ar_reg
= ctx
->bc
->ar_reg
;
1457 memset(&vtx
, 0, sizeof(vtx
));
1458 vtx
.buffer_id
= cb_idx
;
1459 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1460 vtx
.src_gpr
= ar_reg
;
1461 vtx
.src_sel_x
= ar_chan
;
1462 vtx
.mega_fetch_count
= 16;
1463 vtx
.dst_gpr
= dst_reg
;
1464 vtx
.dst_sel_x
= 0; /* SEL_X */
1465 vtx
.dst_sel_y
= 1; /* SEL_Y */
1466 vtx
.dst_sel_z
= 2; /* SEL_Z */
1467 vtx
.dst_sel_w
= 3; /* SEL_W */
1468 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1469 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
1470 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
1471 vtx
.endian
= r600_endian_swap(32);
1472 vtx
.buffer_index_mode
= cb_rel
; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1474 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1480 static int fetch_gs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1482 struct r600_bytecode_vtx vtx
;
1484 unsigned index
= src
->Register
.Index
;
1485 unsigned vtx_id
= src
->Dimension
.Index
;
1486 int offset_reg
= ctx
->gs_rotated_input
[vtx_id
/ 3];
1487 int offset_chan
= vtx_id
% 3;
1490 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1491 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1493 if (offset_reg
== ctx
->gs_rotated_input
[0] && offset_chan
== 2)
1496 if (src
->Dimension
.Indirect
|| src
->Register
.Indirect
)
1497 t2
= r600_get_temp(ctx
);
1499 if (src
->Dimension
.Indirect
) {
1501 struct r600_bytecode_alu alu
;
1504 addr_reg
= get_address_file_reg(ctx
, src
->DimIndirect
.Index
);
1505 if (src
->DimIndirect
.Index
> 0) {
1506 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
1514 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1515 at least this is what fglrx seems to do. */
1516 for (i
= 0; i
< 3; i
++) {
1517 treg
[i
] = r600_get_temp(ctx
);
1519 r600_add_gpr_array(ctx
->shader
, treg
[0], 3, 0x0F);
1521 for (i
= 0; i
< 3; i
++) {
1522 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1523 alu
.op
= ALU_OP1_MOV
;
1524 alu
.src
[0].sel
= ctx
->gs_rotated_input
[0];
1525 alu
.src
[0].chan
= i
== 2 ? 3 : i
;
1526 alu
.dst
.sel
= treg
[i
];
1530 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1534 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1535 alu
.op
= ALU_OP1_MOV
;
1536 alu
.src
[0].sel
= treg
[0];
1541 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1548 if (src
->Register
.Indirect
) {
1550 unsigned first
= ctx
->info
.input_array_first
[src
->Indirect
.ArrayID
];
1552 addr_reg
= get_address_file_reg(ctx
, src
->Indirect
.Index
);
1554 /* pull the value from index_reg */
1555 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1558 V_SQ_ALU_SRC_LITERAL
, first
);
1561 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1564 V_SQ_ALU_SRC_LITERAL
, 4,
1565 offset_reg
, offset_chan
);
1570 index
= src
->Register
.Index
- first
;
1573 memset(&vtx
, 0, sizeof(vtx
));
1574 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
1575 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1576 vtx
.src_gpr
= offset_reg
;
1577 vtx
.src_sel_x
= offset_chan
;
1578 vtx
.offset
= index
* 16; /*bytes*/
1579 vtx
.mega_fetch_count
= 16;
1580 vtx
.dst_gpr
= dst_reg
;
1581 vtx
.dst_sel_x
= 0; /* SEL_X */
1582 vtx
.dst_sel_y
= 1; /* SEL_Y */
1583 vtx
.dst_sel_z
= 2; /* SEL_Z */
1584 vtx
.dst_sel_w
= 3; /* SEL_W */
1585 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1586 vtx
.use_const_fields
= 1;
1588 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1591 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1597 static int tgsi_split_gs_inputs(struct r600_shader_ctx
*ctx
)
1599 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1602 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1603 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1605 if (src
->Register
.File
== TGSI_FILE_INPUT
) {
1606 if (ctx
->shader
->input
[src
->Register
.Index
].name
== TGSI_SEMANTIC_PRIMID
) {
1607 /* primitive id is in R0.z */
1608 ctx
->src
[i
].sel
= 0;
1609 ctx
->src
[i
].swizzle
[0] = 2;
1612 if (src
->Register
.File
== TGSI_FILE_INPUT
&& src
->Register
.Dimension
) {
1613 int treg
= r600_get_temp(ctx
);
1615 fetch_gs_input(ctx
, src
, treg
);
1616 ctx
->src
[i
].sel
= treg
;
1617 ctx
->src
[i
].rel
= 0;
1624 /* Tessellation shaders pass outputs to the next shader using LDS.
1626 * LS outputs = TCS(HS) inputs
1627 * TCS(HS) outputs = TES(DS) inputs
1629 * The LDS layout is:
1630 * - TCS inputs for patch 0
1631 * - TCS inputs for patch 1
1632 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1634 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1635 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1636 * - TCS outputs for patch 1
1637 * - Per-patch TCS outputs for patch 1
1638 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1639 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1642 * All three shaders VS(LS), TCS, TES share the same LDS space.
1644 /* this will return with the dw address in temp_reg.x */
1645 static int r600_get_byte_address(struct r600_shader_ctx
*ctx
, int temp_reg
,
1646 const struct tgsi_full_dst_register
*dst
,
1647 const struct tgsi_full_src_register
*src
,
1648 int stride_bytes_reg
, int stride_bytes_chan
)
1650 struct tgsi_full_dst_register reg
;
1651 ubyte
*name
, *index
, *array_first
;
1654 struct tgsi_shader_info
*info
= &ctx
->info
;
1655 /* Set the register description. The address computation is the same
1656 * for sources and destinations. */
1658 reg
.Register
.File
= src
->Register
.File
;
1659 reg
.Register
.Index
= src
->Register
.Index
;
1660 reg
.Register
.Indirect
= src
->Register
.Indirect
;
1661 reg
.Register
.Dimension
= src
->Register
.Dimension
;
1662 reg
.Indirect
= src
->Indirect
;
1663 reg
.Dimension
= src
->Dimension
;
1664 reg
.DimIndirect
= src
->DimIndirect
;
1668 /* If the register is 2-dimensional (e.g. an array of vertices
1669 * in a primitive), calculate the base address of the vertex. */
1670 if (reg
.Register
.Dimension
) {
1672 if (reg
.Dimension
.Indirect
) {
1674 assert (reg
.DimIndirect
.File
== TGSI_FILE_ADDRESS
);
1676 addr_reg
= get_address_file_reg(ctx
, reg
.DimIndirect
.Index
);
1677 /* pull the value from index_reg */
1681 sel
= V_SQ_ALU_SRC_LITERAL
;
1682 chan
= reg
.Dimension
.Index
;
1685 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1687 stride_bytes_reg
, stride_bytes_chan
,
1694 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1695 name
= info
->input_semantic_name
;
1696 index
= info
->input_semantic_index
;
1697 array_first
= info
->input_array_first
;
1698 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1699 name
= info
->output_semantic_name
;
1700 index
= info
->output_semantic_index
;
1701 array_first
= info
->output_array_first
;
1706 if (reg
.Register
.Indirect
) {
1709 /* Add the relative address of the element. */
1710 if (reg
.Indirect
.ArrayID
)
1711 first
= array_first
[reg
.Indirect
.ArrayID
];
1713 first
= reg
.Register
.Index
;
1715 addr_reg
= get_address_file_reg(ctx
, reg
.Indirect
.Index
);
1717 /* pull the value from index_reg */
1718 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1720 V_SQ_ALU_SRC_LITERAL
, 16,
1726 param
= r600_get_lds_unique_index(name
[first
],
1730 param
= r600_get_lds_unique_index(name
[reg
.Register
.Index
],
1731 index
[reg
.Register
.Index
]);
1734 /* add to base_addr - passed in temp_reg.x */
1736 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1739 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1747 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
1750 struct r600_bytecode_alu alu
;
1753 if ((ctx
->bc
->cf_last
->ndw
>>1) >= 0x60)
1754 ctx
->bc
->force_add_cf
= 1;
1755 for (i
= 1; i
< 4; i
++) {
1756 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1759 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
1763 for (i
= 0; i
< 4; i
++) {
1764 /* emit an LDS_READ_RET */
1765 memset(&alu
, 0, sizeof(alu
));
1766 alu
.op
= LDS_OP1_LDS_READ_RET
;
1767 alu
.src
[0].sel
= temp_reg
;
1768 alu
.src
[0].chan
= i
;
1769 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1770 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
1772 alu
.is_lds_idx_op
= true;
1774 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1778 for (i
= 0; i
< 4; i
++) {
1779 /* then read from LDS_OQ_A_POP */
1780 memset(&alu
, 0, sizeof(alu
));
1782 alu
.op
= ALU_OP1_MOV
;
1783 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
;
1784 alu
.src
[0].chan
= 0;
1785 alu
.dst
.sel
= dst_reg
;
1789 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1796 static int fetch_tes_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1799 unsigned temp_reg
= r600_get_temp(ctx
);
1801 r
= get_lds_offset0(ctx
, 2, temp_reg
,
1802 src
->Register
.Dimension
? false : true);
1806 /* the base address is now in temp.x */
1807 r
= r600_get_byte_address(ctx
, temp_reg
,
1808 NULL
, src
, ctx
->tess_output_info
, 1);
1812 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1818 static int fetch_tcs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1821 unsigned temp_reg
= r600_get_temp(ctx
);
1823 /* t.x = ips * r0.y */
1824 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
1826 ctx
->tess_input_info
, 0,
1832 /* the base address is now in temp.x */
1833 r
= r600_get_byte_address(ctx
, temp_reg
,
1834 NULL
, src
, ctx
->tess_input_info
, 1);
1838 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1844 static int fetch_tcs_output(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1847 unsigned temp_reg
= r600_get_temp(ctx
);
1849 r
= get_lds_offset0(ctx
, 1, temp_reg
,
1850 src
->Register
.Dimension
? false : true);
1853 /* the base address is now in temp.x */
1854 r
= r600_get_byte_address(ctx
, temp_reg
,
1856 ctx
->tess_output_info
, 1);
1860 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1866 static int tgsi_split_lds_inputs(struct r600_shader_ctx
*ctx
)
1868 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1871 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1872 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1874 if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1875 int treg
= r600_get_temp(ctx
);
1876 fetch_tes_input(ctx
, src
, treg
);
1877 ctx
->src
[i
].sel
= treg
;
1878 ctx
->src
[i
].rel
= 0;
1880 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1881 int treg
= r600_get_temp(ctx
);
1882 fetch_tcs_input(ctx
, src
, treg
);
1883 ctx
->src
[i
].sel
= treg
;
1884 ctx
->src
[i
].rel
= 0;
1886 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_OUTPUT
) {
1887 int treg
= r600_get_temp(ctx
);
1888 fetch_tcs_output(ctx
, src
, treg
);
1889 ctx
->src
[i
].sel
= treg
;
1890 ctx
->src
[i
].rel
= 0;
1896 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
1898 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1899 struct r600_bytecode_alu alu
;
1900 int i
, j
, k
, nconst
, r
;
1902 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1903 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
1906 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
1908 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1909 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
1913 if (ctx
->src
[i
].rel
) {
1914 int chan
= inst
->Src
[i
].Indirect
.Swizzle
;
1915 int treg
= r600_get_temp(ctx
);
1916 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].kc_bank
, ctx
->src
[i
].kc_rel
, ctx
->src
[i
].sel
- 512, chan
, treg
)))
1919 ctx
->src
[i
].kc_bank
= 0;
1920 ctx
->src
[i
].kc_rel
= 0;
1921 ctx
->src
[i
].sel
= treg
;
1922 ctx
->src
[i
].rel
= 0;
1925 int treg
= r600_get_temp(ctx
);
1926 for (k
= 0; k
< 4; k
++) {
1927 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1928 alu
.op
= ALU_OP1_MOV
;
1929 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1930 alu
.src
[0].chan
= k
;
1931 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
1932 alu
.src
[0].kc_bank
= ctx
->src
[i
].kc_bank
;
1933 alu
.src
[0].kc_rel
= ctx
->src
[i
].kc_rel
;
1939 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1943 ctx
->src
[i
].sel
= treg
;
1951 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1952 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
1954 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1955 struct r600_bytecode_alu alu
;
1956 int i
, j
, k
, nliteral
, r
;
1958 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1959 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1963 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1964 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1965 int treg
= r600_get_temp(ctx
);
1966 for (k
= 0; k
< 4; k
++) {
1967 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1968 alu
.op
= ALU_OP1_MOV
;
1969 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1970 alu
.src
[0].chan
= k
;
1971 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
1977 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1981 ctx
->src
[i
].sel
= treg
;
1988 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
1990 int i
, r
, count
= ctx
->shader
->ninput
;
1992 for (i
= 0; i
< count
; i
++) {
1993 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1994 r
= select_twoside_color(ctx
, i
, ctx
->shader
->input
[i
].back_color_input
);
2002 static int emit_streamout(struct r600_shader_ctx
*ctx
, struct pipe_stream_output_info
*so
,
2003 int stream
, unsigned *stream_item_size
)
2005 unsigned so_gpr
[PIPE_MAX_SHADER_OUTPUTS
];
2006 unsigned start_comp
[PIPE_MAX_SHADER_OUTPUTS
];
2009 /* Sanity checking. */
2010 if (so
->num_outputs
> PIPE_MAX_SO_OUTPUTS
) {
2011 R600_ERR("Too many stream outputs: %d\n", so
->num_outputs
);
2015 for (i
= 0; i
< so
->num_outputs
; i
++) {
2016 if (so
->output
[i
].output_buffer
>= 4) {
2017 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2018 so
->output
[i
].output_buffer
);
2024 /* Initialize locations where the outputs are stored. */
2025 for (i
= 0; i
< so
->num_outputs
; i
++) {
2027 so_gpr
[i
] = ctx
->shader
->output
[so
->output
[i
].register_index
].gpr
;
2028 start_comp
[i
] = so
->output
[i
].start_component
;
2029 /* Lower outputs with dst_offset < start_component.
2031 * We can only output 4D vectors with a write mask, e.g. we can
2032 * only output the W component at offset 3, etc. If we want
2033 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2034 * to move it to X and output X. */
2035 if (so
->output
[i
].dst_offset
< so
->output
[i
].start_component
) {
2036 unsigned tmp
= r600_get_temp(ctx
);
2038 for (j
= 0; j
< so
->output
[i
].num_components
; j
++) {
2039 struct r600_bytecode_alu alu
;
2040 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2041 alu
.op
= ALU_OP1_MOV
;
2042 alu
.src
[0].sel
= so_gpr
[i
];
2043 alu
.src
[0].chan
= so
->output
[i
].start_component
+ j
;
2048 if (j
== so
->output
[i
].num_components
- 1)
2050 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2059 /* Write outputs to buffers. */
2060 for (i
= 0; i
< so
->num_outputs
; i
++) {
2061 struct r600_bytecode_output output
;
2063 if (stream
!= -1 && stream
!= so
->output
[i
].output_buffer
)
2066 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2067 output
.gpr
= so_gpr
[i
];
2068 output
.elem_size
= so
->output
[i
].num_components
- 1;
2069 if (output
.elem_size
== 2)
2070 output
.elem_size
= 3; // 3 not supported, write 4 with junk at end
2071 output
.array_base
= so
->output
[i
].dst_offset
- start_comp
[i
];
2072 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2073 output
.burst_count
= 1;
2074 /* array_size is an upper limit for the burst_count
2075 * with MEM_STREAM instructions */
2076 output
.array_size
= 0xFFF;
2077 output
.comp_mask
= ((1 << so
->output
[i
].num_components
) - 1) << start_comp
[i
];
2079 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
2080 switch (so
->output
[i
].output_buffer
) {
2082 output
.op
= CF_OP_MEM_STREAM0_BUF0
;
2085 output
.op
= CF_OP_MEM_STREAM0_BUF1
;
2088 output
.op
= CF_OP_MEM_STREAM0_BUF2
;
2091 output
.op
= CF_OP_MEM_STREAM0_BUF3
;
2094 output
.op
+= so
->output
[i
].stream
* 4;
2095 assert(output
.op
>= CF_OP_MEM_STREAM0_BUF0
&& output
.op
<= CF_OP_MEM_STREAM3_BUF3
);
2096 ctx
->enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << so
->output
[i
].stream
* 4;
2098 switch (so
->output
[i
].output_buffer
) {
2100 output
.op
= CF_OP_MEM_STREAM0
;
2103 output
.op
= CF_OP_MEM_STREAM1
;
2106 output
.op
= CF_OP_MEM_STREAM2
;
2109 output
.op
= CF_OP_MEM_STREAM3
;
2112 ctx
->enabled_stream_buffers_mask
|= 1 << so
->output
[i
].output_buffer
;
2114 r
= r600_bytecode_add_output(ctx
->bc
, &output
);
2123 static void convert_edgeflag_to_int(struct r600_shader_ctx
*ctx
)
2125 struct r600_bytecode_alu alu
;
2128 if (!ctx
->shader
->vs_out_edgeflag
)
2131 reg
= ctx
->shader
->output
[ctx
->edgeflag_output
].gpr
;
2133 /* clamp(x, 0, 1) */
2134 memset(&alu
, 0, sizeof(alu
));
2135 alu
.op
= ALU_OP1_MOV
;
2136 alu
.src
[0].sel
= reg
;
2141 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2143 memset(&alu
, 0, sizeof(alu
));
2144 alu
.op
= ALU_OP1_FLT_TO_INT
;
2145 alu
.src
[0].sel
= reg
;
2149 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2152 static int generate_gs_copy_shader(struct r600_context
*rctx
,
2153 struct r600_pipe_shader
*gs
,
2154 struct pipe_stream_output_info
*so
)
2156 struct r600_shader_ctx ctx
= {};
2157 struct r600_shader
*gs_shader
= &gs
->shader
;
2158 struct r600_pipe_shader
*cshader
;
2159 int ocnt
= gs_shader
->noutput
;
2160 struct r600_bytecode_alu alu
;
2161 struct r600_bytecode_vtx vtx
;
2162 struct r600_bytecode_output output
;
2163 struct r600_bytecode_cf
*cf_jump
, *cf_pop
,
2164 *last_exp_pos
= NULL
, *last_exp_param
= NULL
;
2165 int i
, j
, next_clip_pos
= 61, next_param
= 0;
2167 bool only_ring_0
= true;
2168 cshader
= calloc(1, sizeof(struct r600_pipe_shader
));
2172 memcpy(cshader
->shader
.output
, gs_shader
->output
, ocnt
*
2173 sizeof(struct r600_shader_io
));
2175 cshader
->shader
.noutput
= ocnt
;
2177 ctx
.shader
= &cshader
->shader
;
2178 ctx
.bc
= &ctx
.shader
->bc
;
2179 ctx
.type
= ctx
.bc
->type
= PIPE_SHADER_VERTEX
;
2181 r600_bytecode_init(ctx
.bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2182 rctx
->screen
->has_compressed_msaa_texturing
);
2184 ctx
.bc
->isa
= rctx
->isa
;
2187 memset(cshader
->shader
.ring_item_sizes
, 0, sizeof(cshader
->shader
.ring_item_sizes
));
2189 /* R0.x = R0.x & 0x3fffffff */
2190 memset(&alu
, 0, sizeof(alu
));
2191 alu
.op
= ALU_OP2_AND_INT
;
2192 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2193 alu
.src
[1].value
= 0x3fffffff;
2195 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2197 /* R0.y = R0.x >> 30 */
2198 memset(&alu
, 0, sizeof(alu
));
2199 alu
.op
= ALU_OP2_LSHR_INT
;
2200 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2201 alu
.src
[1].value
= 0x1e;
2205 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2207 /* fetch vertex data from GSVS ring */
2208 for (i
= 0; i
< ocnt
; ++i
) {
2209 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2212 out
->ring_offset
= i
* 16;
2214 memset(&vtx
, 0, sizeof(vtx
));
2215 vtx
.op
= FETCH_OP_VFETCH
;
2216 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
2217 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2218 vtx
.mega_fetch_count
= 16;
2219 vtx
.offset
= out
->ring_offset
;
2220 vtx
.dst_gpr
= out
->gpr
;
2226 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2227 vtx
.use_const_fields
= 1;
2229 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
2232 r600_bytecode_add_vtx(ctx
.bc
, &vtx
);
2234 ctx
.temp_reg
= i
+ 1;
2235 for (ring
= 3; ring
>= 0; --ring
) {
2236 bool enabled
= false;
2237 for (i
= 0; i
< so
->num_outputs
; i
++) {
2238 if (so
->output
[i
].stream
== ring
) {
2241 only_ring_0
= false;
2245 if (ring
!= 0 && !enabled
) {
2246 cshader
->shader
.ring_item_sizes
[ring
] = 0;
2251 // Patch up jump label
2252 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2253 cf_pop
= ctx
.bc
->cf_last
;
2255 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2256 cf_jump
->pop_count
= 1;
2257 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2258 cf_pop
->pop_count
= 1;
2261 /* PRED_SETE_INT __, R0.y, ring */
2262 memset(&alu
, 0, sizeof(alu
));
2263 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2264 alu
.src
[0].chan
= 1;
2265 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2266 alu
.src
[1].value
= ring
;
2267 alu
.execute_mask
= 1;
2268 alu
.update_pred
= 1;
2270 r600_bytecode_add_alu_type(ctx
.bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2272 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_JUMP
);
2273 cf_jump
= ctx
.bc
->cf_last
;
2276 emit_streamout(&ctx
, so
, only_ring_0
? -1 : ring
, &cshader
->shader
.ring_item_sizes
[ring
]);
2277 cshader
->shader
.ring_item_sizes
[ring
] = ocnt
* 16;
2280 /* bc adds nops - copy it */
2281 if (ctx
.bc
->chip_class
== R600
) {
2282 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2283 alu
.op
= ALU_OP0_NOP
;
2285 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2287 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2290 /* export vertex data */
2291 /* XXX factor out common code with r600_shader_from_tgsi ? */
2292 for (i
= 0; i
< ocnt
; ++i
) {
2293 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2294 bool instream0
= true;
2295 if (out
->name
== TGSI_SEMANTIC_CLIPVERTEX
)
2298 for (j
= 0; j
< so
->num_outputs
; j
++) {
2299 if (so
->output
[j
].register_index
== i
) {
2300 if (so
->output
[j
].stream
== 0)
2302 if (so
->output
[j
].stream
> 0)
2308 memset(&output
, 0, sizeof(output
));
2309 output
.gpr
= out
->gpr
;
2310 output
.elem_size
= 3;
2311 output
.swizzle_x
= 0;
2312 output
.swizzle_y
= 1;
2313 output
.swizzle_z
= 2;
2314 output
.swizzle_w
= 3;
2315 output
.burst_count
= 1;
2316 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2317 output
.op
= CF_OP_EXPORT
;
2318 switch (out
->name
) {
2319 case TGSI_SEMANTIC_POSITION
:
2320 output
.array_base
= 60;
2321 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2324 case TGSI_SEMANTIC_PSIZE
:
2325 output
.array_base
= 61;
2326 if (next_clip_pos
== 61)
2328 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2329 output
.swizzle_y
= 7;
2330 output
.swizzle_z
= 7;
2331 output
.swizzle_w
= 7;
2332 ctx
.shader
->vs_out_misc_write
= 1;
2333 ctx
.shader
->vs_out_point_size
= 1;
2335 case TGSI_SEMANTIC_LAYER
:
2337 /* duplicate it as PARAM to pass to the pixel shader */
2338 output
.array_base
= next_param
++;
2339 r600_bytecode_add_output(ctx
.bc
, &output
);
2340 last_exp_param
= ctx
.bc
->cf_last
;
2342 output
.array_base
= 61;
2343 if (next_clip_pos
== 61)
2345 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2346 output
.swizzle_x
= 7;
2347 output
.swizzle_y
= 7;
2348 output
.swizzle_z
= 0;
2349 output
.swizzle_w
= 7;
2350 ctx
.shader
->vs_out_misc_write
= 1;
2351 ctx
.shader
->vs_out_layer
= 1;
2353 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2355 /* duplicate it as PARAM to pass to the pixel shader */
2356 output
.array_base
= next_param
++;
2357 r600_bytecode_add_output(ctx
.bc
, &output
);
2358 last_exp_param
= ctx
.bc
->cf_last
;
2360 output
.array_base
= 61;
2361 if (next_clip_pos
== 61)
2363 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2364 ctx
.shader
->vs_out_misc_write
= 1;
2365 ctx
.shader
->vs_out_viewport
= 1;
2366 output
.swizzle_x
= 7;
2367 output
.swizzle_y
= 7;
2368 output
.swizzle_z
= 7;
2369 output
.swizzle_w
= 0;
2371 case TGSI_SEMANTIC_CLIPDIST
:
2372 /* spi_sid is 0 for clipdistance outputs that were generated
2373 * for clipvertex - we don't need to pass them to PS */
2374 ctx
.shader
->clip_dist_write
= gs
->shader
.clip_dist_write
;
2376 /* duplicate it as PARAM to pass to the pixel shader */
2377 output
.array_base
= next_param
++;
2378 r600_bytecode_add_output(ctx
.bc
, &output
);
2379 last_exp_param
= ctx
.bc
->cf_last
;
2381 output
.array_base
= next_clip_pos
++;
2382 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2384 case TGSI_SEMANTIC_FOG
:
2385 output
.swizzle_y
= 4; /* 0 */
2386 output
.swizzle_z
= 4; /* 0 */
2387 output
.swizzle_w
= 5; /* 1 */
2390 output
.array_base
= next_param
++;
2393 r600_bytecode_add_output(ctx
.bc
, &output
);
2394 if (output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
)
2395 last_exp_param
= ctx
.bc
->cf_last
;
2397 last_exp_pos
= ctx
.bc
->cf_last
;
2400 if (!last_exp_pos
) {
2401 memset(&output
, 0, sizeof(output
));
2403 output
.elem_size
= 3;
2404 output
.swizzle_x
= 7;
2405 output
.swizzle_y
= 7;
2406 output
.swizzle_z
= 7;
2407 output
.swizzle_w
= 7;
2408 output
.burst_count
= 1;
2410 output
.op
= CF_OP_EXPORT
;
2411 output
.array_base
= 60;
2412 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2413 r600_bytecode_add_output(ctx
.bc
, &output
);
2414 last_exp_pos
= ctx
.bc
->cf_last
;
2417 if (!last_exp_param
) {
2418 memset(&output
, 0, sizeof(output
));
2420 output
.elem_size
= 3;
2421 output
.swizzle_x
= 7;
2422 output
.swizzle_y
= 7;
2423 output
.swizzle_z
= 7;
2424 output
.swizzle_w
= 7;
2425 output
.burst_count
= 1;
2427 output
.op
= CF_OP_EXPORT
;
2428 output
.array_base
= next_param
++;
2429 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2430 r600_bytecode_add_output(ctx
.bc
, &output
);
2431 last_exp_param
= ctx
.bc
->cf_last
;
2434 last_exp_pos
->op
= CF_OP_EXPORT_DONE
;
2435 last_exp_param
->op
= CF_OP_EXPORT_DONE
;
2437 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2438 cf_pop
= ctx
.bc
->cf_last
;
2440 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2441 cf_jump
->pop_count
= 1;
2442 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2443 cf_pop
->pop_count
= 1;
2445 if (ctx
.bc
->chip_class
== CAYMAN
)
2446 cm_bytecode_add_cf_end(ctx
.bc
);
2448 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2449 ctx
.bc
->cf_last
->end_of_program
= 1;
2452 gs
->gs_copy_shader
= cshader
;
2453 cshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
2457 return r600_bytecode_build(ctx
.bc
);
2460 static int emit_inc_ring_offset(struct r600_shader_ctx
*ctx
, int idx
, bool ind
)
2463 struct r600_bytecode_alu alu
;
2466 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2467 alu
.op
= ALU_OP2_ADD_INT
;
2468 alu
.src
[0].sel
= ctx
->gs_export_gpr_tregs
[idx
];
2469 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2470 alu
.src
[1].value
= ctx
->gs_out_ring_offset
>> 4;
2471 alu
.dst
.sel
= ctx
->gs_export_gpr_tregs
[idx
];
2474 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2481 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
)
2483 struct r600_bytecode_output output
;
2484 int i
, k
, ring_offset
;
2485 int effective_stream
= stream
== -1 ? 0 : stream
;
2488 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2489 if (ctx
->gs_for_vs
) {
2490 /* for ES we need to lookup corresponding ring offset expected by GS
2491 * (map this output to GS input by name and sid) */
2492 /* FIXME precompute offsets */
2494 for(k
= 0; k
< ctx
->gs_for_vs
->ninput
; ++k
) {
2495 struct r600_shader_io
*in
= &ctx
->gs_for_vs
->input
[k
];
2496 struct r600_shader_io
*out
= &ctx
->shader
->output
[i
];
2497 if (in
->name
== out
->name
&& in
->sid
== out
->sid
)
2498 ring_offset
= in
->ring_offset
;
2501 if (ring_offset
== -1)
2504 ring_offset
= idx
* 16;
2508 if (stream
> 0 && ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2510 /* next_ring_offset after parsing input decls contains total size of
2511 * single vertex data, gs_next_vertex - current vertex index */
2513 ring_offset
+= ctx
->gs_out_ring_offset
* ctx
->gs_next_vertex
;
2515 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2516 output
.gpr
= ctx
->shader
->output
[i
].gpr
;
2517 output
.elem_size
= 3;
2518 output
.comp_mask
= 0xF;
2519 output
.burst_count
= 1;
2522 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
2524 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2529 output
.op
= CF_OP_MEM_RING
; break;
2531 output
.op
= CF_OP_MEM_RING1
; break;
2533 output
.op
= CF_OP_MEM_RING2
; break;
2535 output
.op
= CF_OP_MEM_RING3
; break;
2539 output
.array_base
= ring_offset
>> 2; /* in dwords */
2540 output
.array_size
= 0xfff;
2541 output
.index_gpr
= ctx
->gs_export_gpr_tregs
[effective_stream
];
2543 output
.array_base
= ring_offset
>> 2; /* in dwords */
2544 r600_bytecode_add_output(ctx
->bc
, &output
);
2547 ++ctx
->gs_next_vertex
;
2552 static int r600_fetch_tess_io_info(struct r600_shader_ctx
*ctx
)
2555 struct r600_bytecode_vtx vtx
;
2556 int temp_val
= ctx
->temp_reg
;
2557 /* need to store the TCS output somewhere */
2558 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2560 V_SQ_ALU_SRC_LITERAL
, 0,
2565 /* used by VS/TCS */
2566 if (ctx
->tess_input_info
) {
2567 /* fetch tcs input values into resv space */
2568 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2569 vtx
.op
= FETCH_OP_VFETCH
;
2570 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2571 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2572 vtx
.mega_fetch_count
= 16;
2573 vtx
.data_format
= FMT_32_32_32_32
;
2574 vtx
.num_format_all
= 2;
2575 vtx
.format_comp_all
= 1;
2576 vtx
.use_const_fields
= 0;
2577 vtx
.endian
= r600_endian_swap(32);
2578 vtx
.srf_mode_all
= 1;
2580 vtx
.dst_gpr
= ctx
->tess_input_info
;
2585 vtx
.src_gpr
= temp_val
;
2588 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2593 /* used by TCS/TES */
2594 if (ctx
->tess_output_info
) {
2595 /* fetch tcs output values into resv space */
2596 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2597 vtx
.op
= FETCH_OP_VFETCH
;
2598 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2599 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2600 vtx
.mega_fetch_count
= 16;
2601 vtx
.data_format
= FMT_32_32_32_32
;
2602 vtx
.num_format_all
= 2;
2603 vtx
.format_comp_all
= 1;
2604 vtx
.use_const_fields
= 0;
2605 vtx
.endian
= r600_endian_swap(32);
2606 vtx
.srf_mode_all
= 1;
2608 vtx
.dst_gpr
= ctx
->tess_output_info
;
2613 vtx
.src_gpr
= temp_val
;
2616 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2623 static int emit_lds_vs_writes(struct r600_shader_ctx
*ctx
)
2628 /* fetch tcs input values into input_vals */
2629 ctx
->tess_input_info
= r600_get_temp(ctx
);
2630 ctx
->tess_output_info
= 0;
2631 r
= r600_fetch_tess_io_info(ctx
);
2635 temp_reg
= r600_get_temp(ctx
);
2636 /* dst reg contains LDS address stride * idx */
2637 /* MUL vertexID, vertex_dw_stride */
2638 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
2640 ctx
->tess_input_info
, 1,
2641 0, 1); /* rel id in r0.y? */
2645 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2646 struct r600_bytecode_alu alu
;
2647 int param
= r600_get_lds_unique_index(ctx
->shader
->output
[i
].name
, ctx
->shader
->output
[i
].sid
);
2650 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2653 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2658 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2660 temp_reg
, param
? 1 : 0,
2661 V_SQ_ALU_SRC_LITERAL
, 8);
2666 for (j
= 0; j
< 2; j
++) {
2667 int chan
= (j
== 1) ? 2 : (param
? 1 : 0);
2668 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2669 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2670 alu
.src
[0].sel
= temp_reg
;
2671 alu
.src
[0].chan
= chan
;
2672 alu
.src
[1].sel
= ctx
->shader
->output
[i
].gpr
;
2673 alu
.src
[1].chan
= j
* 2;
2674 alu
.src
[2].sel
= ctx
->shader
->output
[i
].gpr
;
2675 alu
.src
[2].chan
= (j
* 2) + 1;
2679 alu
.is_lds_idx_op
= true;
2680 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2688 static int r600_store_tcs_output(struct r600_shader_ctx
*ctx
)
2690 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2691 const struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
2693 int temp_reg
= r600_get_temp(ctx
);
2694 struct r600_bytecode_alu alu
;
2695 unsigned write_mask
= dst
->Register
.WriteMask
;
2697 if (inst
->Dst
[0].Register
.File
!= TGSI_FILE_OUTPUT
)
2700 r
= get_lds_offset0(ctx
, 1, temp_reg
, dst
->Register
.Dimension
? false : true);
2704 /* the base address is now in temp.x */
2705 r
= r600_get_byte_address(ctx
, temp_reg
,
2706 &inst
->Dst
[0], NULL
, ctx
->tess_output_info
, 1);
2711 lasti
= tgsi_last_instruction(write_mask
);
2712 for (i
= 1; i
<= lasti
; i
++) {
2714 if (!(write_mask
& (1 << i
)))
2716 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2719 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2724 for (i
= 0; i
<= lasti
; i
++) {
2725 if (!(write_mask
& (1 << i
)))
2728 if ((i
== 0 && ((write_mask
& 3) == 3)) ||
2729 (i
== 2 && ((write_mask
& 0xc) == 0xc))) {
2730 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2731 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2732 alu
.src
[0].sel
= temp_reg
;
2733 alu
.src
[0].chan
= i
;
2735 alu
.src
[1].sel
= dst
->Register
.Index
;
2736 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2737 alu
.src
[1].chan
= i
;
2739 alu
.src
[2].sel
= dst
->Register
.Index
;
2740 alu
.src
[2].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2741 alu
.src
[2].chan
= i
+ 1;
2745 alu
.is_lds_idx_op
= true;
2746 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2752 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2753 alu
.op
= LDS_OP2_LDS_WRITE
;
2754 alu
.src
[0].sel
= temp_reg
;
2755 alu
.src
[0].chan
= i
;
2757 alu
.src
[1].sel
= dst
->Register
.Index
;
2758 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2759 alu
.src
[1].chan
= i
;
2761 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
2764 alu
.is_lds_idx_op
= true;
2765 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2772 static int r600_tess_factor_read(struct r600_shader_ctx
*ctx
,
2776 unsigned temp_reg
= r600_get_temp(ctx
);
2777 unsigned name
= ctx
->shader
->output
[output_idx
].name
;
2778 int dreg
= ctx
->shader
->output
[output_idx
].gpr
;
2781 param
= r600_get_lds_unique_index(name
, 0);
2782 r
= get_lds_offset0(ctx
, 1, temp_reg
, true);
2786 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2789 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2793 do_lds_fetch_values(ctx
, temp_reg
, dreg
);
2797 static int r600_emit_tess_factor(struct r600_shader_ctx
*ctx
)
2800 int stride
, outer_comps
, inner_comps
;
2801 int tessinner_idx
= -1, tessouter_idx
= -1;
2803 int temp_reg
= r600_get_temp(ctx
);
2804 int treg
[3] = {-1, -1, -1};
2805 struct r600_bytecode_alu alu
;
2806 struct r600_bytecode_cf
*cf_jump
, *cf_pop
;
2808 /* only execute factor emission for invocation 0 */
2809 /* PRED_SETE_INT __, R0.x, 0 */
2810 memset(&alu
, 0, sizeof(alu
));
2811 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2812 alu
.src
[0].chan
= 2;
2813 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2814 alu
.execute_mask
= 1;
2815 alu
.update_pred
= 1;
2817 r600_bytecode_add_alu_type(ctx
->bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2819 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
2820 cf_jump
= ctx
->bc
->cf_last
;
2822 treg
[0] = r600_get_temp(ctx
);
2823 switch (ctx
->shader
->tcs_prim_mode
) {
2824 case PIPE_PRIM_LINES
:
2825 stride
= 8; /* 2 dwords, 1 vec2 store */
2829 case PIPE_PRIM_TRIANGLES
:
2830 stride
= 16; /* 4 dwords, 1 vec4 store */
2833 treg
[1] = r600_get_temp(ctx
);
2835 case PIPE_PRIM_QUADS
:
2836 stride
= 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2839 treg
[1] = r600_get_temp(ctx
);
2840 treg
[2] = r600_get_temp(ctx
);
2847 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2848 /* TF_WRITE takes index in R.x, value in R.y */
2849 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2850 if (ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_TESSINNER
)
2852 if (ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_TESSOUTER
)
2856 if (tessouter_idx
== -1)
2859 if (tessinner_idx
== -1 && inner_comps
)
2862 if (tessouter_idx
!= -1) {
2863 r
= r600_tess_factor_read(ctx
, tessouter_idx
);
2868 if (tessinner_idx
!= -1) {
2869 r
= r600_tess_factor_read(ctx
, tessinner_idx
);
2874 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2875 /* r.x = relpatchid(r0.y) * tf_stride */
2877 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2878 /* add incoming r0.w to it: t.x = t.x + r0.w */
2879 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
2882 V_SQ_ALU_SRC_LITERAL
, stride
,
2887 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2888 int out_idx
= i
>= outer_comps
? tessinner_idx
: tessouter_idx
;
2889 int out_comp
= i
>= outer_comps
? i
- outer_comps
: i
;
2891 if (ctx
->shader
->tcs_prim_mode
== PIPE_PRIM_LINES
) {
2894 else if (out_comp
== 0)
2898 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2899 treg
[i
/ 2], (2 * (i
% 2)),
2901 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2904 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2905 treg
[i
/ 2], 1 + (2 * (i
%2)),
2906 ctx
->shader
->output
[out_idx
].gpr
, out_comp
,
2911 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2912 struct r600_bytecode_gds gds
;
2914 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
2915 gds
.src_gpr
= treg
[i
/ 2];
2916 gds
.src_sel_x
= 2 * (i
% 2);
2917 gds
.src_sel_y
= 1 + (2 * (i
% 2));
2923 gds
.op
= FETCH_OP_TF_WRITE
;
2924 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
2929 // Patch up jump label
2930 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
2931 cf_pop
= ctx
->bc
->cf_last
;
2933 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2934 cf_jump
->pop_count
= 1;
2935 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2936 cf_pop
->pop_count
= 1;
2942 * We have to work out the thread ID for load and atomic
2943 * operations, which store the returned value to an index
2944 * in an intermediate buffer.
2945 * The index is calculated by taking the thread id,
2946 * calculated from the MBCNT instructions.
2947 * Then the shader engine ID is multiplied by 256,
2948 * and the wave id is added.
2949 * Then the result is multipled by 64 and thread id is
2952 static int load_thread_id_gpr(struct r600_shader_ctx
*ctx
)
2954 struct r600_bytecode_alu alu
;
2957 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2958 alu
.op
= ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT
;
2959 alu
.dst
.sel
= ctx
->temp_reg
;
2961 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
2962 alu
.src
[0].value
= 0xffffffff;
2964 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2968 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2969 alu
.op
= ALU_OP1_MBCNT_32HI_INT
;
2970 alu
.dst
.sel
= ctx
->temp_reg
;
2972 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
2973 alu
.src
[0].value
= 0xffffffff;
2975 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2979 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2980 alu
.op
= ALU_OP3_MULADD_UINT24
;
2981 alu
.dst
.sel
= ctx
->temp_reg
;
2983 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_SE_ID
;
2984 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2985 alu
.src
[1].value
= 256;
2986 alu
.src
[2].sel
= EG_V_SQ_ALU_SRC_HW_WAVE_ID
;
2990 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2994 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
2995 ctx
->thread_id_gpr
, 1,
2997 V_SQ_ALU_SRC_LITERAL
, 0x40,
3004 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
3005 struct r600_pipe_shader
*pipeshader
,
3006 union r600_shader_key key
)
3008 struct r600_screen
*rscreen
= rctx
->screen
;
3009 struct r600_shader
*shader
= &pipeshader
->shader
;
3010 struct tgsi_token
*tokens
= pipeshader
->selector
->tokens
;
3011 struct pipe_stream_output_info so
= pipeshader
->selector
->so
;
3012 struct tgsi_full_immediate
*immediate
;
3013 struct r600_shader_ctx ctx
;
3014 struct r600_bytecode_output output
[ARRAY_SIZE(shader
->output
)];
3015 unsigned output_done
, noutput
;
3018 int next_param_base
= 0, next_clip_base
;
3019 int max_color_exports
= MAX2(key
.ps
.nr_cbufs
, 1);
3021 bool ring_outputs
= false;
3022 bool lds_outputs
= false;
3023 bool lds_inputs
= false;
3024 bool pos_emitted
= false;
3026 ctx
.bc
= &shader
->bc
;
3027 ctx
.shader
= shader
;
3028 ctx
.native_integers
= true;
3030 r600_bytecode_init(ctx
.bc
, rscreen
->b
.chip_class
, rscreen
->b
.family
,
3031 rscreen
->has_compressed_msaa_texturing
);
3032 ctx
.tokens
= tokens
;
3033 tgsi_scan_shader(tokens
, &ctx
.info
);
3034 shader
->indirect_files
= ctx
.info
.indirect_files
;
3036 shader
->uses_doubles
= ctx
.info
.uses_doubles
;
3037 shader
->uses_atomics
= ctx
.info
.file_mask
[TGSI_FILE_HW_ATOMIC
];
3038 shader
->nsys_inputs
= 0;
3040 shader
->uses_images
= ctx
.info
.file_count
[TGSI_FILE_IMAGE
] > 0;
3041 indirect_gprs
= ctx
.info
.indirect_files
& ~((1 << TGSI_FILE_CONSTANT
) | (1 << TGSI_FILE_SAMPLER
));
3042 tgsi_parse_init(&ctx
.parse
, tokens
);
3043 ctx
.type
= ctx
.info
.processor
;
3044 shader
->processor_type
= ctx
.type
;
3045 ctx
.bc
->type
= shader
->processor_type
;
3048 case PIPE_SHADER_VERTEX
:
3049 shader
->vs_as_gs_a
= key
.vs
.as_gs_a
;
3050 shader
->vs_as_es
= key
.vs
.as_es
;
3051 shader
->vs_as_ls
= key
.vs
.as_ls
;
3052 shader
->atomic_base
= key
.vs
.first_atomic_counter
;
3053 if (shader
->vs_as_es
)
3054 ring_outputs
= true;
3055 if (shader
->vs_as_ls
)
3058 case PIPE_SHADER_GEOMETRY
:
3059 ring_outputs
= true;
3060 shader
->atomic_base
= key
.gs
.first_atomic_counter
;
3061 shader
->gs_tri_strip_adj_fix
= key
.gs
.tri_strip_adj_fix
;
3063 case PIPE_SHADER_TESS_CTRL
:
3064 shader
->tcs_prim_mode
= key
.tcs
.prim_mode
;
3065 shader
->atomic_base
= key
.tcs
.first_atomic_counter
;
3069 case PIPE_SHADER_TESS_EVAL
:
3070 shader
->tes_as_es
= key
.tes
.as_es
;
3071 shader
->atomic_base
= key
.tes
.first_atomic_counter
;
3073 if (shader
->tes_as_es
)
3074 ring_outputs
= true;
3076 case PIPE_SHADER_FRAGMENT
:
3077 shader
->two_side
= key
.ps
.color_two_side
;
3078 shader
->atomic_base
= key
.ps
.first_atomic_counter
;
3079 shader
->rat_base
= key
.ps
.nr_cbufs
;
3085 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3086 ctx
.gs_for_vs
= &rctx
->gs_shader
->current
->shader
;
3088 ctx
.gs_for_vs
= NULL
;
3091 ctx
.next_ring_offset
= 0;
3092 ctx
.gs_out_ring_offset
= 0;
3093 ctx
.gs_next_vertex
= 0;
3094 ctx
.gs_stream_output_info
= &so
;
3097 ctx
.fixed_pt_position_gpr
= -1;
3098 ctx
.fragcoord_input
= -1;
3099 ctx
.colors_used
= 0;
3100 ctx
.clip_vertex_write
= 0;
3102 shader
->nr_ps_color_exports
= 0;
3103 shader
->nr_ps_max_color_exports
= 0;
3106 /* register allocations */
3107 /* Values [0,127] correspond to GPR[0..127].
3108 * Values [128,159] correspond to constant buffer bank 0
3109 * Values [160,191] correspond to constant buffer bank 1
3110 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3111 * Values [256,287] correspond to constant buffer bank 2 (EG)
3112 * Values [288,319] correspond to constant buffer bank 3 (EG)
3113 * Other special values are shown in the list below.
3114 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3115 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3116 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3117 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3118 * 248 SQ_ALU_SRC_0: special constant 0.0.
3119 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3120 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3121 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3122 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3123 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3124 * 254 SQ_ALU_SRC_PV: previous vector result.
3125 * 255 SQ_ALU_SRC_PS: previous scalar result.
3127 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
3128 ctx
.file_offset
[i
] = 0;
3131 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3133 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3134 if (ctx
.info
.num_inputs
)
3135 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CALL_FS
);
3137 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
3138 if (ctx
.bc
->chip_class
>= EVERGREEN
)
3139 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
3141 ctx
.file_offset
[TGSI_FILE_INPUT
] = allocate_system_value_inputs(&ctx
, ctx
.file_offset
[TGSI_FILE_INPUT
]);
3143 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3144 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3145 ctx
.file_offset
[TGSI_FILE_INPUT
] = 2;
3147 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3148 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3149 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3150 bool add_tesscoord
= false, add_tess_inout
= false;
3151 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3152 for (i
= 0; i
< PIPE_MAX_SHADER_INPUTS
; i
++) {
3153 /* if we have tesscoord save one reg */
3154 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSCOORD
)
3155 add_tesscoord
= true;
3156 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSINNER
||
3157 ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSOUTER
)
3158 add_tess_inout
= true;
3160 if (add_tesscoord
|| add_tess_inout
)
3161 ctx
.file_offset
[TGSI_FILE_INPUT
]++;
3163 ctx
.file_offset
[TGSI_FILE_INPUT
]+=2;
3166 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
3167 ctx
.file_offset
[TGSI_FILE_INPUT
] +
3168 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3169 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
3170 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
3172 /* Outside the GPR range. This will be translated to one of the
3173 * kcache banks later. */
3174 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
3176 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
3177 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
3178 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
3179 ctx
.bc
->index_reg
[0] = ctx
.bc
->ar_reg
+ 1;
3180 ctx
.bc
->index_reg
[1] = ctx
.bc
->ar_reg
+ 2;
3182 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3183 ctx
.tess_input_info
= ctx
.bc
->ar_reg
+ 3;
3184 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 4;
3185 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 5;
3186 } else if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3187 ctx
.tess_input_info
= 0;
3188 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 3;
3189 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 4;
3190 } else if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3191 ctx
.gs_export_gpr_tregs
[0] = ctx
.bc
->ar_reg
+ 3;
3192 ctx
.gs_export_gpr_tregs
[1] = ctx
.bc
->ar_reg
+ 4;
3193 ctx
.gs_export_gpr_tregs
[2] = ctx
.bc
->ar_reg
+ 5;
3194 ctx
.gs_export_gpr_tregs
[3] = ctx
.bc
->ar_reg
+ 6;
3195 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 7;
3196 if (ctx
.shader
->gs_tri_strip_adj_fix
) {
3197 ctx
.gs_rotated_input
[0] = ctx
.bc
->ar_reg
+ 7;
3198 ctx
.gs_rotated_input
[1] = ctx
.bc
->ar_reg
+ 8;
3201 ctx
.gs_rotated_input
[0] = 0;
3202 ctx
.gs_rotated_input
[1] = 1;
3205 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 3;
3208 if (shader
->uses_images
&& ctx
.type
== PIPE_SHADER_FRAGMENT
) {
3209 ctx
.thread_id_gpr
= ctx
.temp_reg
;
3212 ctx
.thread_id_gpr
= 0;
3214 shader
->max_arrays
= 0;
3215 shader
->num_arrays
= 0;
3216 if (indirect_gprs
) {
3218 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_INPUT
)) {
3219 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_INPUT
],
3220 ctx
.file_offset
[TGSI_FILE_OUTPUT
] -
3221 ctx
.file_offset
[TGSI_FILE_INPUT
],
3224 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_OUTPUT
)) {
3225 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3226 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] -
3227 ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3233 ctx
.literals
= NULL
;
3235 shader
->fs_write_all
= ctx
.info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
3236 ctx
.info
.colors_written
== 1;
3237 shader
->vs_position_window_space
= ctx
.info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
3238 shader
->ps_conservative_z
= (uint8_t)ctx
.info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
];
3240 if (shader
->vs_as_gs_a
)
3241 vs_add_primid_output(&ctx
, key
.vs
.prim_id_out
);
3243 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3244 r600_fetch_tess_io_info(&ctx
);
3246 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3247 tgsi_parse_token(&ctx
.parse
);
3248 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3249 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3250 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
3251 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
3252 if(ctx
.literals
== NULL
) {
3256 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
3257 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
3258 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
3259 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
3262 case TGSI_TOKEN_TYPE_DECLARATION
:
3263 r
= tgsi_declaration(&ctx
);
3267 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3268 case TGSI_TOKEN_TYPE_PROPERTY
:
3271 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
3277 shader
->ring_item_sizes
[0] = ctx
.next_ring_offset
;
3278 shader
->ring_item_sizes
[1] = 0;
3279 shader
->ring_item_sizes
[2] = 0;
3280 shader
->ring_item_sizes
[3] = 0;
3282 /* Process two side if needed */
3283 if (shader
->two_side
&& ctx
.colors_used
) {
3284 int i
, count
= ctx
.shader
->ninput
;
3285 unsigned next_lds_loc
= ctx
.shader
->nlds
;
3287 /* additional inputs will be allocated right after the existing inputs,
3288 * we won't need them after the color selection, so we don't need to
3289 * reserve these gprs for the rest of the shader code and to adjust
3290 * output offsets etc. */
3291 int gpr
= ctx
.file_offset
[TGSI_FILE_INPUT
] +
3292 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3294 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3295 if (ctx
.face_gpr
== -1) {
3296 i
= ctx
.shader
->ninput
++;
3297 ctx
.shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
3298 ctx
.shader
->input
[i
].spi_sid
= 0;
3299 ctx
.shader
->input
[i
].gpr
= gpr
++;
3300 ctx
.face_gpr
= ctx
.shader
->input
[i
].gpr
;
3303 for (i
= 0; i
< count
; i
++) {
3304 if (ctx
.shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3305 int ni
= ctx
.shader
->ninput
++;
3306 memcpy(&ctx
.shader
->input
[ni
],&ctx
.shader
->input
[i
], sizeof(struct r600_shader_io
));
3307 ctx
.shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
3308 ctx
.shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
.shader
->input
[ni
]);
3309 ctx
.shader
->input
[ni
].gpr
= gpr
++;
3310 // TGSI to LLVM needs to know the lds position of inputs.
3311 // Non LLVM path computes it later (in process_twoside_color)
3312 ctx
.shader
->input
[ni
].lds_pos
= next_lds_loc
++;
3313 ctx
.shader
->input
[i
].back_color_input
= ni
;
3314 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
3315 if ((r
= evergreen_interp_input(&ctx
, ni
)))
3322 if (shader
->fs_write_all
&& rscreen
->b
.chip_class
>= EVERGREEN
)
3323 shader
->nr_ps_max_color_exports
= 8;
3325 if (ctx
.fragcoord_input
>= 0) {
3326 if (ctx
.bc
->chip_class
== CAYMAN
) {
3327 for (j
= 0 ; j
< 4; j
++) {
3328 struct r600_bytecode_alu alu
;
3329 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3330 alu
.op
= ALU_OP1_RECIP_IEEE
;
3331 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3332 alu
.src
[0].chan
= 3;
3334 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3336 alu
.dst
.write
= (j
== 3);
3338 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3342 struct r600_bytecode_alu alu
;
3343 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3344 alu
.op
= ALU_OP1_RECIP_IEEE
;
3345 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3346 alu
.src
[0].chan
= 3;
3348 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3352 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3357 if (ctx
.thread_id_gpr
) {
3358 load_thread_id_gpr(&ctx
);
3361 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3362 struct r600_bytecode_alu alu
;
3365 /* GS thread with no output workaround - emit a cut at start of GS */
3366 if (ctx
.bc
->chip_class
== R600
)
3367 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CUT_VERTEX
);
3369 for (j
= 0; j
< 4; j
++) {
3370 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3371 alu
.op
= ALU_OP1_MOV
;
3372 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
3373 alu
.src
[0].value
= 0;
3374 alu
.dst
.sel
= ctx
.gs_export_gpr_tregs
[j
];
3377 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3382 if (ctx
.shader
->gs_tri_strip_adj_fix
) {
3383 r
= single_alu_op2(&ctx
, ALU_OP2_AND_INT
,
3384 ctx
.gs_rotated_input
[0], 2,
3386 V_SQ_ALU_SRC_LITERAL
, 1);
3390 for (i
= 0; i
< 6; i
++) {
3391 int rotated
= (i
+ 4) % 6;
3392 int offset_reg
= i
/ 3;
3393 int offset_chan
= i
% 3;
3394 int rotated_offset_reg
= rotated
/ 3;
3395 int rotated_offset_chan
= rotated
% 3;
3397 if (offset_reg
== 0 && offset_chan
== 2)
3399 if (rotated_offset_reg
== 0 && rotated_offset_chan
== 2)
3400 rotated_offset_chan
= 3;
3402 r
= single_alu_op3(&ctx
, ALU_OP3_CNDE_INT
,
3403 ctx
.gs_rotated_input
[offset_reg
], offset_chan
,
3404 ctx
.gs_rotated_input
[0], 2,
3405 offset_reg
, offset_chan
,
3406 rotated_offset_reg
, rotated_offset_chan
);
3413 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3414 r600_fetch_tess_io_info(&ctx
);
3416 if (shader
->two_side
&& ctx
.colors_used
) {
3417 if ((r
= process_twoside_color_inputs(&ctx
)))
3421 tgsi_parse_init(&ctx
.parse
, tokens
);
3422 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3423 tgsi_parse_token(&ctx
.parse
);
3424 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3425 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3426 r
= tgsi_is_supported(&ctx
);
3429 ctx
.max_driver_temp_used
= 0;
3430 /* reserve first tmp for everyone */
3431 r600_get_temp(&ctx
);
3433 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3434 if ((r
= tgsi_split_constant(&ctx
)))
3436 if ((r
= tgsi_split_literal_constant(&ctx
)))
3438 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3439 if ((r
= tgsi_split_gs_inputs(&ctx
)))
3441 } else if (lds_inputs
) {
3442 if ((r
= tgsi_split_lds_inputs(&ctx
)))
3445 if (ctx
.bc
->chip_class
== CAYMAN
)
3446 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
3447 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
3448 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
3450 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
3451 r
= ctx
.inst_info
->process(&ctx
);
3455 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3456 r
= r600_store_tcs_output(&ctx
);
3466 /* Reset the temporary register counter. */
3467 ctx
.max_driver_temp_used
= 0;
3469 noutput
= shader
->noutput
;
3471 if (!ring_outputs
&& ctx
.clip_vertex_write
) {
3472 unsigned clipdist_temp
[2];
3474 clipdist_temp
[0] = r600_get_temp(&ctx
);
3475 clipdist_temp
[1] = r600_get_temp(&ctx
);
3477 /* need to convert a clipvertex write into clipdistance writes and not export
3478 the clip vertex anymore */
3480 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
3481 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3482 shader
->output
[noutput
].gpr
= clipdist_temp
[0];
3484 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3485 shader
->output
[noutput
].gpr
= clipdist_temp
[1];
3488 /* reset spi_sid for clipvertex output to avoid confusing spi */
3489 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
3491 shader
->clip_dist_write
= 0xFF;
3493 for (i
= 0; i
< 8; i
++) {
3497 for (j
= 0; j
< 4; j
++) {
3498 struct r600_bytecode_alu alu
;
3499 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3500 alu
.op
= ALU_OP2_DOT4
;
3501 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
3502 alu
.src
[0].chan
= j
;
3504 alu
.src
[1].sel
= 512 + i
;
3505 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
3506 alu
.src
[1].chan
= j
;
3508 alu
.dst
.sel
= clipdist_temp
[oreg
];
3510 alu
.dst
.write
= (j
== ochan
);
3513 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3520 /* Add stream outputs. */
3521 if (so
.num_outputs
) {
3523 if (!lds_outputs
&& !ring_outputs
&& ctx
.type
== PIPE_SHADER_VERTEX
)
3525 if (!ring_outputs
&& ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3528 emit_streamout(&ctx
, &so
, -1, NULL
);
3530 pipeshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
3531 convert_edgeflag_to_int(&ctx
);
3533 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3534 r600_emit_tess_factor(&ctx
);
3537 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3538 if (ctx
.shader
->noutput
)
3539 emit_lds_vs_writes(&ctx
);
3541 } else if (ring_outputs
) {
3542 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3543 ctx
.gs_export_gpr_tregs
[0] = r600_get_temp(&ctx
);
3544 ctx
.gs_export_gpr_tregs
[1] = -1;
3545 ctx
.gs_export_gpr_tregs
[2] = -1;
3546 ctx
.gs_export_gpr_tregs
[3] = -1;
3548 emit_gs_ring_writes(&ctx
, &so
, -1, FALSE
);
3552 next_clip_base
= shader
->vs_out_misc_write
? 62 : 61;
3554 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
3555 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3556 output
[j
].gpr
= shader
->output
[i
].gpr
;
3557 output
[j
].elem_size
= 3;
3558 output
[j
].swizzle_x
= 0;
3559 output
[j
].swizzle_y
= 1;
3560 output
[j
].swizzle_z
= 2;
3561 output
[j
].swizzle_w
= 3;
3562 output
[j
].burst_count
= 1;
3563 output
[j
].type
= -1;
3564 output
[j
].op
= CF_OP_EXPORT
;
3566 case PIPE_SHADER_VERTEX
:
3567 case PIPE_SHADER_TESS_EVAL
:
3568 switch (shader
->output
[i
].name
) {
3569 case TGSI_SEMANTIC_POSITION
:
3570 output
[j
].array_base
= 60;
3571 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3575 case TGSI_SEMANTIC_PSIZE
:
3576 output
[j
].array_base
= 61;
3577 output
[j
].swizzle_y
= 7;
3578 output
[j
].swizzle_z
= 7;
3579 output
[j
].swizzle_w
= 7;
3580 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3583 case TGSI_SEMANTIC_EDGEFLAG
:
3584 output
[j
].array_base
= 61;
3585 output
[j
].swizzle_x
= 7;
3586 output
[j
].swizzle_y
= 0;
3587 output
[j
].swizzle_z
= 7;
3588 output
[j
].swizzle_w
= 7;
3589 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3592 case TGSI_SEMANTIC_LAYER
:
3593 /* spi_sid is 0 for outputs that are
3594 * not consumed by PS */
3595 if (shader
->output
[i
].spi_sid
) {
3596 output
[j
].array_base
= next_param_base
++;
3597 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3599 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3601 output
[j
].array_base
= 61;
3602 output
[j
].swizzle_x
= 7;
3603 output
[j
].swizzle_y
= 7;
3604 output
[j
].swizzle_z
= 0;
3605 output
[j
].swizzle_w
= 7;
3606 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3609 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
3610 /* spi_sid is 0 for outputs that are
3611 * not consumed by PS */
3612 if (shader
->output
[i
].spi_sid
) {
3613 output
[j
].array_base
= next_param_base
++;
3614 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3616 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3618 output
[j
].array_base
= 61;
3619 output
[j
].swizzle_x
= 7;
3620 output
[j
].swizzle_y
= 7;
3621 output
[j
].swizzle_z
= 7;
3622 output
[j
].swizzle_w
= 0;
3623 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3626 case TGSI_SEMANTIC_CLIPVERTEX
:
3629 case TGSI_SEMANTIC_CLIPDIST
:
3630 output
[j
].array_base
= next_clip_base
++;
3631 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3633 /* spi_sid is 0 for clipdistance outputs that were generated
3634 * for clipvertex - we don't need to pass them to PS */
3635 if (shader
->output
[i
].spi_sid
) {
3637 /* duplicate it as PARAM to pass to the pixel shader */
3638 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3639 output
[j
].array_base
= next_param_base
++;
3640 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3643 case TGSI_SEMANTIC_FOG
:
3644 output
[j
].swizzle_y
= 4; /* 0 */
3645 output
[j
].swizzle_z
= 4; /* 0 */
3646 output
[j
].swizzle_w
= 5; /* 1 */
3648 case TGSI_SEMANTIC_PRIMID
:
3649 output
[j
].swizzle_x
= 2;
3650 output
[j
].swizzle_y
= 4; /* 0 */
3651 output
[j
].swizzle_z
= 4; /* 0 */
3652 output
[j
].swizzle_w
= 4; /* 0 */
3657 case PIPE_SHADER_FRAGMENT
:
3658 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3659 /* never export more colors than the number of CBs */
3660 if (shader
->output
[i
].sid
>= max_color_exports
) {
3665 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3666 output
[j
].array_base
= shader
->output
[i
].sid
;
3667 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3668 shader
->nr_ps_color_exports
++;
3669 if (shader
->fs_write_all
&& (rscreen
->b
.chip_class
>= EVERGREEN
)) {
3670 for (k
= 1; k
< max_color_exports
; k
++) {
3672 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3673 output
[j
].gpr
= shader
->output
[i
].gpr
;
3674 output
[j
].elem_size
= 3;
3675 output
[j
].swizzle_x
= 0;
3676 output
[j
].swizzle_y
= 1;
3677 output
[j
].swizzle_z
= 2;
3678 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3679 output
[j
].burst_count
= 1;
3680 output
[j
].array_base
= k
;
3681 output
[j
].op
= CF_OP_EXPORT
;
3682 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3683 shader
->nr_ps_color_exports
++;
3686 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
3687 output
[j
].array_base
= 61;
3688 output
[j
].swizzle_x
= 2;
3689 output
[j
].swizzle_y
= 7;
3690 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3691 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3692 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
3693 output
[j
].array_base
= 61;
3694 output
[j
].swizzle_x
= 7;
3695 output
[j
].swizzle_y
= 1;
3696 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3697 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3698 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
3699 output
[j
].array_base
= 61;
3700 output
[j
].swizzle_x
= 7;
3701 output
[j
].swizzle_y
= 7;
3702 output
[j
].swizzle_z
= 0;
3703 output
[j
].swizzle_w
= 7;
3704 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3706 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
3711 case PIPE_SHADER_TESS_CTRL
:
3714 R600_ERR("unsupported processor type %d\n", ctx
.type
);
3719 if (output
[j
].type
==-1) {
3720 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3721 output
[j
].array_base
= next_param_base
++;
3725 /* add fake position export */
3726 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && pos_emitted
== false) {
3727 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3729 output
[j
].elem_size
= 3;
3730 output
[j
].swizzle_x
= 7;
3731 output
[j
].swizzle_y
= 7;
3732 output
[j
].swizzle_z
= 7;
3733 output
[j
].swizzle_w
= 7;
3734 output
[j
].burst_count
= 1;
3735 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3736 output
[j
].array_base
= 60;
3737 output
[j
].op
= CF_OP_EXPORT
;
3741 /* add fake param output for vertex shader if no param is exported */
3742 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && next_param_base
== 0) {
3743 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3745 output
[j
].elem_size
= 3;
3746 output
[j
].swizzle_x
= 7;
3747 output
[j
].swizzle_y
= 7;
3748 output
[j
].swizzle_z
= 7;
3749 output
[j
].swizzle_w
= 7;
3750 output
[j
].burst_count
= 1;
3751 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3752 output
[j
].array_base
= 0;
3753 output
[j
].op
= CF_OP_EXPORT
;
3757 /* add fake pixel export */
3758 if (ctx
.type
== PIPE_SHADER_FRAGMENT
&& shader
->nr_ps_color_exports
== 0) {
3759 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3761 output
[j
].elem_size
= 3;
3762 output
[j
].swizzle_x
= 7;
3763 output
[j
].swizzle_y
= 7;
3764 output
[j
].swizzle_z
= 7;
3765 output
[j
].swizzle_w
= 7;
3766 output
[j
].burst_count
= 1;
3767 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3768 output
[j
].array_base
= 0;
3769 output
[j
].op
= CF_OP_EXPORT
;
3771 shader
->nr_ps_color_exports
++;
3776 /* set export done on last export of each type */
3777 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
3778 if (!(output_done
& (1 << output
[i
].type
))) {
3779 output_done
|= (1 << output
[i
].type
);
3780 output
[i
].op
= CF_OP_EXPORT_DONE
;
3783 /* add output to bytecode */
3784 for (i
= 0; i
< noutput
; i
++) {
3785 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
3791 /* add program end */
3792 if (ctx
.bc
->chip_class
== CAYMAN
)
3793 cm_bytecode_add_cf_end(ctx
.bc
);
3795 const struct cf_op_info
*last
= NULL
;
3797 if (ctx
.bc
->cf_last
)
3798 last
= r600_isa_cf(ctx
.bc
->cf_last
->op
);
3800 /* alu clause instructions don't have EOP bit, so add NOP */
3801 if (!last
|| last
->flags
& CF_ALU
|| ctx
.bc
->cf_last
->op
== CF_OP_LOOP_END
|| ctx
.bc
->cf_last
->op
== CF_OP_CALL_FS
|| ctx
.bc
->cf_last
->op
== CF_OP_POP
|| ctx
.bc
->cf_last
->op
== CF_OP_GDS
)
3802 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
3804 ctx
.bc
->cf_last
->end_of_program
= 1;
3807 /* check GPR limit - we have 124 = 128 - 4
3808 * (4 are reserved as alu clause temporary registers) */
3809 if (ctx
.bc
->ngpr
> 124) {
3810 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx
.bc
->ngpr
);
3815 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3816 if ((r
= generate_gs_copy_shader(rctx
, pipeshader
, &so
)))
3821 tgsi_parse_free(&ctx
.parse
);
3825 tgsi_parse_free(&ctx
.parse
);
3829 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
3831 const unsigned tgsi_opcode
=
3832 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3833 R600_ERR("%s tgsi opcode unsupported\n",
3834 tgsi_get_opcode_name(tgsi_opcode
));
3838 static int tgsi_end(struct r600_shader_ctx
*ctx
)
3843 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
3844 const struct r600_shader_src
*shader_src
,
3847 bc_src
->sel
= shader_src
->sel
;
3848 bc_src
->chan
= shader_src
->swizzle
[chan
];
3849 bc_src
->neg
= shader_src
->neg
;
3850 bc_src
->abs
= shader_src
->abs
;
3851 bc_src
->rel
= shader_src
->rel
;
3852 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
3853 bc_src
->kc_bank
= shader_src
->kc_bank
;
3854 bc_src
->kc_rel
= shader_src
->kc_rel
;
3857 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
3863 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
3865 bc_src
->neg
= !bc_src
->neg
;
3868 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
3869 const struct tgsi_full_dst_register
*tgsi_dst
,
3871 struct r600_bytecode_alu_dst
*r600_dst
)
3873 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3875 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
3876 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
3877 r600_dst
->chan
= swizzle
;
3878 r600_dst
->write
= 1;
3879 if (inst
->Instruction
.Saturate
) {
3880 r600_dst
->clamp
= 1;
3882 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
3883 if (tgsi_dst
->Register
.File
== TGSI_FILE_OUTPUT
) {
3887 if (tgsi_dst
->Register
.Indirect
)
3888 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
3892 static int tgsi_op2_64_params(struct r600_shader_ctx
*ctx
, bool singledest
, bool swap
)
3894 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3895 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3896 struct r600_bytecode_alu alu
;
3897 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
3901 switch (write_mask
) {
3919 lasti
= tgsi_last_instruction(write_mask
);
3920 for (i
= 0; i
<= lasti
; i
++) {
3922 if (!(write_mask
& (1 << i
)))
3925 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3928 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3930 alu
.dst
.sel
= ctx
->temp_reg
;
3934 if (i
== 1 || i
== 3)
3937 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3939 alu
.op
= ctx
->inst_info
->op
;
3940 if (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DABS
) {
3941 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3943 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3944 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
3947 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], fp64_switch(i
));
3948 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], fp64_switch(i
));
3951 /* handle some special cases */
3952 if (i
== 1 || i
== 3) {
3953 switch (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
) {
3954 case TGSI_OPCODE_DABS
:
3955 r600_bytecode_src_set_abs(&alu
.src
[0]);
3964 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3970 write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3972 /* move result from temp to dst */
3973 for (i
= 0; i
<= lasti
; i
++) {
3974 if (!(write_mask
& (1 << i
)))
3977 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3978 alu
.op
= ALU_OP1_MOV
;
3979 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3980 alu
.src
[0].sel
= ctx
->temp_reg
;
3981 alu
.src
[0].chan
= use_tmp
- 1;
3982 alu
.last
= (i
== lasti
);
3984 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3992 static int tgsi_op2_64(struct r600_shader_ctx
*ctx
)
3994 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3995 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3996 /* confirm writemasking */
3997 if ((write_mask
& 0x3) != 0x3 &&
3998 (write_mask
& 0xc) != 0xc) {
3999 fprintf(stderr
, "illegal writemask for 64-bit: 0x%x\n", write_mask
);
4002 return tgsi_op2_64_params(ctx
, false, false);
4005 static int tgsi_op2_64_single_dest(struct r600_shader_ctx
*ctx
)
4007 return tgsi_op2_64_params(ctx
, true, false);
4010 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx
*ctx
)
4012 return tgsi_op2_64_params(ctx
, true, true);
4015 static int tgsi_op3_64(struct r600_shader_ctx
*ctx
)
4017 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4018 struct r600_bytecode_alu alu
;
4021 int tmp
= r600_get_temp(ctx
);
4023 for (i
= 0; i
< lasti
+ 1; i
++) {
4025 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4026 alu
.op
= ctx
->inst_info
->op
;
4027 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4028 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
== 3 ? 0 : 1);
4031 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
))
4032 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4041 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4048 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
4050 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4051 struct r600_bytecode_alu alu
;
4052 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4053 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
4054 /* use temp register if trans_only and more than one dst component */
4055 int use_tmp
= trans_only
&& (write_mask
^ (1 << lasti
));
4056 unsigned op
= ctx
->inst_info
->op
;
4058 if (op
== ALU_OP2_MUL_IEEE
&&
4059 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
4062 for (i
= 0; i
<= lasti
; i
++) {
4063 if (!(write_mask
& (1 << i
)))
4066 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4068 alu
.dst
.sel
= ctx
->temp_reg
;
4072 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4076 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4077 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
4080 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
4081 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4083 if (i
== lasti
|| trans_only
) {
4086 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4092 /* move result from temp to dst */
4093 for (i
= 0; i
<= lasti
; i
++) {
4094 if (!(write_mask
& (1 << i
)))
4097 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4098 alu
.op
= ALU_OP1_MOV
;
4099 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4100 alu
.src
[0].sel
= ctx
->temp_reg
;
4101 alu
.src
[0].chan
= i
;
4102 alu
.last
= (i
== lasti
);
4104 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4112 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
4114 return tgsi_op2_s(ctx
, 0, 0);
4117 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
4119 return tgsi_op2_s(ctx
, 1, 0);
4122 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
4124 return tgsi_op2_s(ctx
, 0, 1);
4127 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
4129 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4130 struct r600_bytecode_alu alu
;
4132 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4134 for (i
= 0; i
< lasti
+ 1; i
++) {
4136 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4138 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4139 alu
.op
= ctx
->inst_info
->op
;
4141 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4143 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4145 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4150 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4158 static int tgsi_dneg(struct r600_shader_ctx
*ctx
)
4160 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4161 struct r600_bytecode_alu alu
;
4163 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4165 for (i
= 0; i
< lasti
+ 1; i
++) {
4167 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4169 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4170 alu
.op
= ALU_OP1_MOV
;
4172 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4174 if (i
== 1 || i
== 3)
4175 r600_bytecode_src_toggle_neg(&alu
.src
[0]);
4176 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4181 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4189 static int tgsi_dfracexp(struct r600_shader_ctx
*ctx
)
4191 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4192 struct r600_bytecode_alu alu
;
4193 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4196 for (i
= 0; i
<= 3; i
++) {
4197 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4198 alu
.op
= ctx
->inst_info
->op
;
4200 alu
.dst
.sel
= ctx
->temp_reg
;
4203 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4204 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
4210 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4215 /* Replicate significand result across channels. */
4216 for (i
= 0; i
<= 3; i
++) {
4217 if (!(write_mask
& (1 << i
)))
4220 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4221 alu
.op
= ALU_OP1_MOV
;
4222 alu
.src
[0].chan
= (i
& 1) + 2;
4223 alu
.src
[0].sel
= ctx
->temp_reg
;
4225 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4228 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4233 for (i
= 0; i
<= 3; i
++) {
4234 if (inst
->Dst
[1].Register
.WriteMask
& (1 << i
)) {
4235 /* MOV third channels to writemask dst1 */
4236 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4237 alu
.op
= ALU_OP1_MOV
;
4238 alu
.src
[0].chan
= 1;
4239 alu
.src
[0].sel
= ctx
->temp_reg
;
4241 tgsi_dst(ctx
, &inst
->Dst
[1], i
, &alu
.dst
);
4243 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4253 static int egcm_int_to_double(struct r600_shader_ctx
*ctx
)
4255 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4256 struct r600_bytecode_alu alu
;
4258 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4260 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_I2D
||
4261 inst
->Instruction
.Opcode
== TGSI_OPCODE_U2D
);
4263 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4264 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4265 alu
.op
= ctx
->inst_info
->op
;
4267 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4268 alu
.dst
.sel
= ctx
->temp_reg
;
4273 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4278 for (i
= 0; i
<= lasti
; i
++) {
4279 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4280 alu
.op
= ALU_OP1_FLT32_TO_FLT64
;
4282 alu
.src
[0].chan
= i
/2;
4284 alu
.src
[0].sel
= ctx
->temp_reg
;
4286 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
4287 alu
.src
[0].value
= 0x0;
4289 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4290 alu
.last
= i
== lasti
;
4292 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4300 static int egcm_double_to_int(struct r600_shader_ctx
*ctx
)
4302 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4303 struct r600_bytecode_alu alu
;
4305 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4307 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_D2I
||
4308 inst
->Instruction
.Opcode
== TGSI_OPCODE_D2U
);
4310 for (i
= 0; i
<= lasti
; i
++) {
4311 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4312 alu
.op
= ALU_OP1_FLT64_TO_FLT32
;
4314 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], fp64_switch(i
));
4316 alu
.dst
.sel
= ctx
->temp_reg
;
4317 alu
.dst
.write
= i
%2 == 0;
4318 alu
.last
= i
== lasti
;
4320 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4325 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4326 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4327 alu
.op
= ctx
->inst_info
->op
;
4329 alu
.src
[0].chan
= i
*2;
4330 alu
.src
[0].sel
= ctx
->temp_reg
;
4331 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4334 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4342 static int cayman_emit_unary_double_raw(struct r600_bytecode
*bc
,
4345 struct r600_shader_src
*src
,
4348 struct r600_bytecode_alu alu
;
4349 const int last_slot
= 3;
4352 /* these have to write the result to X/Y by the looks of it */
4353 for (int i
= 0 ; i
< last_slot
; i
++) {
4354 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4357 r600_bytecode_src(&alu
.src
[0], src
, 1);
4358 r600_bytecode_src(&alu
.src
[1], src
, 0);
4361 r600_bytecode_src_set_abs(&alu
.src
[1]);
4363 alu
.dst
.sel
= dst_reg
;
4365 alu
.dst
.write
= (i
== 0 || i
== 1);
4367 if (bc
->chip_class
!= CAYMAN
|| i
== last_slot
- 1)
4369 r
= r600_bytecode_add_alu(bc
, &alu
);
4377 static int cayman_emit_double_instr(struct r600_shader_ctx
*ctx
)
4379 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4381 struct r600_bytecode_alu alu
;
4382 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4383 int t1
= ctx
->temp_reg
;
4385 /* should only be one src regs */
4386 assert(inst
->Instruction
.NumSrcRegs
== 1);
4388 /* only support one double at a time */
4389 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4390 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4392 r
= cayman_emit_unary_double_raw(
4393 ctx
->bc
, ctx
->inst_info
->op
, t1
,
4395 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DRSQ
||
4396 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DSQRT
);
4400 for (i
= 0 ; i
<= lasti
; i
++) {
4401 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4403 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4404 alu
.op
= ALU_OP1_MOV
;
4405 alu
.src
[0].sel
= t1
;
4406 alu
.src
[0].chan
= (i
== 0 || i
== 2) ? 0 : 1;
4407 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4411 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4418 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
4420 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4422 struct r600_bytecode_alu alu
;
4423 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4425 for (i
= 0 ; i
< last_slot
; i
++) {
4426 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4427 alu
.op
= ctx
->inst_info
->op
;
4428 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4429 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
4431 /* RSQ should take the absolute value of src */
4432 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_RSQ
) {
4433 r600_bytecode_src_set_abs(&alu
.src
[j
]);
4436 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4437 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4439 if (i
== last_slot
- 1)
4441 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4448 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
4450 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4452 struct r600_bytecode_alu alu
;
4453 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4454 int t1
= ctx
->temp_reg
;
4456 for (k
= 0; k
<= lasti
; k
++) {
4457 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
4460 for (i
= 0 ; i
< 4; i
++) {
4461 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4462 alu
.op
= ctx
->inst_info
->op
;
4463 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4464 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
4468 alu
.dst
.write
= (i
== k
);
4471 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4477 for (i
= 0 ; i
<= lasti
; i
++) {
4478 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4480 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4481 alu
.op
= ALU_OP1_MOV
;
4482 alu
.src
[0].sel
= t1
;
4483 alu
.src
[0].chan
= i
;
4484 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4488 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4497 static int cayman_mul_double_instr(struct r600_shader_ctx
*ctx
)
4499 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4501 struct r600_bytecode_alu alu
;
4502 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4503 int t1
= ctx
->temp_reg
;
4505 /* t1 would get overwritten below if we actually tried to
4506 * multiply two pairs of doubles at a time. */
4507 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4508 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4510 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4512 for (i
= 0; i
< 4; i
++) {
4513 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4514 alu
.op
= ctx
->inst_info
->op
;
4515 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4516 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
* 2 + ((i
== 3) ? 0 : 1));
4523 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4528 for (i
= 0; i
<= lasti
; i
++) {
4529 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4531 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4532 alu
.op
= ALU_OP1_MOV
;
4533 alu
.src
[0].sel
= t1
;
4534 alu
.src
[0].chan
= i
;
4535 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4539 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4548 * Emit RECIP_64 + MUL_64 to implement division.
4550 static int cayman_ddiv_instr(struct r600_shader_ctx
*ctx
)
4552 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4554 struct r600_bytecode_alu alu
;
4555 int t1
= ctx
->temp_reg
;
4558 /* Only support one double at a time. This is the same constraint as
4559 * in DMUL lowering. */
4560 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4561 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4563 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4565 r
= cayman_emit_unary_double_raw(ctx
->bc
, ALU_OP2_RECIP_64
, t1
, &ctx
->src
[1], false);
4569 for (int i
= 0; i
< 4; i
++) {
4570 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4571 alu
.op
= ALU_OP2_MUL_64
;
4573 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], k
* 2 + ((i
== 3) ? 0 : 1));
4575 alu
.src
[1].sel
= t1
;
4576 alu
.src
[1].chan
= (i
== 3) ? 0 : 1;
4583 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4588 for (int i
= 0; i
< 2; i
++) {
4589 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4590 alu
.op
= ALU_OP1_MOV
;
4591 alu
.src
[0].sel
= t1
;
4592 alu
.src
[0].chan
= i
;
4593 tgsi_dst(ctx
, &inst
->Dst
[0], k
* 2 + i
, &alu
.dst
);
4597 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4605 * r600 - trunc to -PI..PI range
4606 * r700 - normalize by dividing by 2PI
4609 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
4612 struct r600_bytecode_alu alu
;
4614 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4615 alu
.op
= ALU_OP3_MULADD
;
4619 alu
.dst
.sel
= ctx
->temp_reg
;
4622 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4624 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4625 alu
.src
[1].chan
= 0;
4626 alu
.src
[1].value
= u_bitcast_f2u(0.5f
* M_1_PI
);
4627 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4628 alu
.src
[2].chan
= 0;
4630 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4634 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4635 alu
.op
= ALU_OP1_FRACT
;
4638 alu
.dst
.sel
= ctx
->temp_reg
;
4641 alu
.src
[0].sel
= ctx
->temp_reg
;
4642 alu
.src
[0].chan
= 0;
4644 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4648 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4649 alu
.op
= ALU_OP3_MULADD
;
4653 alu
.dst
.sel
= ctx
->temp_reg
;
4656 alu
.src
[0].sel
= ctx
->temp_reg
;
4657 alu
.src
[0].chan
= 0;
4659 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4660 alu
.src
[1].chan
= 0;
4661 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
4662 alu
.src
[2].chan
= 0;
4664 if (ctx
->bc
->chip_class
== R600
) {
4665 alu
.src
[1].value
= u_bitcast_f2u(2.0f
* M_PI
);
4666 alu
.src
[2].value
= u_bitcast_f2u(-M_PI
);
4668 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4669 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4674 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4680 static int cayman_trig(struct r600_shader_ctx
*ctx
)
4682 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4683 struct r600_bytecode_alu alu
;
4684 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4687 r
= tgsi_setup_trig(ctx
);
4692 for (i
= 0; i
< last_slot
; i
++) {
4693 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4694 alu
.op
= ctx
->inst_info
->op
;
4697 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4698 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4700 alu
.src
[0].sel
= ctx
->temp_reg
;
4701 alu
.src
[0].chan
= 0;
4702 if (i
== last_slot
- 1)
4704 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4711 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
4713 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4714 struct r600_bytecode_alu alu
;
4716 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4718 r
= tgsi_setup_trig(ctx
);
4722 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4723 alu
.op
= ctx
->inst_info
->op
;
4725 alu
.dst
.sel
= ctx
->temp_reg
;
4728 alu
.src
[0].sel
= ctx
->temp_reg
;
4729 alu
.src
[0].chan
= 0;
4731 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4735 /* replicate result */
4736 for (i
= 0; i
< lasti
+ 1; i
++) {
4737 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4740 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4741 alu
.op
= ALU_OP1_MOV
;
4743 alu
.src
[0].sel
= ctx
->temp_reg
;
4744 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4747 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4754 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
4756 const struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4757 struct r600_bytecode_alu alu
;
4760 for (i
= 0; i
< 4; i
++) {
4761 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4762 alu
.op
= ctx
->inst_info
->op
;
4766 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4768 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_KILL
) {
4769 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4772 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4777 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4782 /* kill must be last in ALU */
4783 ctx
->bc
->force_add_cf
= 1;
4784 ctx
->shader
->uses_kill
= TRUE
;
4788 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
4790 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4791 struct r600_bytecode_alu alu
;
4794 /* tmp.x = max(src.y, 0.0) */
4795 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4796 alu
.op
= ALU_OP2_MAX
;
4797 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
4798 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4799 alu
.src
[1].chan
= 1;
4801 alu
.dst
.sel
= ctx
->temp_reg
;
4806 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4810 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
4816 if (ctx
->bc
->chip_class
== CAYMAN
) {
4817 for (i
= 0; i
< 3; i
++) {
4818 /* tmp.z = log(tmp.x) */
4819 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4820 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4821 alu
.src
[0].sel
= ctx
->temp_reg
;
4822 alu
.src
[0].chan
= 0;
4823 alu
.dst
.sel
= ctx
->temp_reg
;
4831 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4836 /* tmp.z = log(tmp.x) */
4837 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4838 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4839 alu
.src
[0].sel
= ctx
->temp_reg
;
4840 alu
.src
[0].chan
= 0;
4841 alu
.dst
.sel
= ctx
->temp_reg
;
4845 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4850 chan
= alu
.dst
.chan
;
4853 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4854 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4855 alu
.op
= ALU_OP3_MUL_LIT
;
4856 alu
.src
[0].sel
= sel
;
4857 alu
.src
[0].chan
= chan
;
4858 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
4859 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
4860 alu
.dst
.sel
= ctx
->temp_reg
;
4865 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4869 if (ctx
->bc
->chip_class
== CAYMAN
) {
4870 for (i
= 0; i
< 3; i
++) {
4871 /* dst.z = exp(tmp.x) */
4872 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4873 alu
.op
= ALU_OP1_EXP_IEEE
;
4874 alu
.src
[0].sel
= ctx
->temp_reg
;
4875 alu
.src
[0].chan
= 0;
4876 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4882 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4887 /* dst.z = exp(tmp.x) */
4888 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4889 alu
.op
= ALU_OP1_EXP_IEEE
;
4890 alu
.src
[0].sel
= ctx
->temp_reg
;
4891 alu
.src
[0].chan
= 0;
4892 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
4894 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4901 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4902 alu
.op
= ALU_OP1_MOV
;
4903 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
4904 alu
.src
[0].chan
= 0;
4905 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4906 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
4907 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4911 /* dst.y = max(src.x, 0.0) */
4912 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4913 alu
.op
= ALU_OP2_MAX
;
4914 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4915 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4916 alu
.src
[1].chan
= 0;
4917 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
4918 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
4919 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4924 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4925 alu
.op
= ALU_OP1_MOV
;
4926 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4927 alu
.src
[0].chan
= 0;
4928 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
4929 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
4931 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4938 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
4940 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4941 struct r600_bytecode_alu alu
;
4944 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4946 alu
.op
= ALU_OP1_RECIPSQRT_IEEE
;
4948 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
4949 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
4950 r600_bytecode_src_set_abs(&alu
.src
[i
]);
4952 alu
.dst
.sel
= ctx
->temp_reg
;
4955 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4958 /* replicate result */
4959 return tgsi_helper_tempx_replicate(ctx
);
4962 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
4964 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4965 struct r600_bytecode_alu alu
;
4968 for (i
= 0; i
< 4; i
++) {
4969 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4970 alu
.src
[0].sel
= ctx
->temp_reg
;
4971 alu
.op
= ALU_OP1_MOV
;
4973 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4974 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4977 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4984 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
4986 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4987 struct r600_bytecode_alu alu
;
4990 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4991 alu
.op
= ctx
->inst_info
->op
;
4992 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
4993 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
4995 alu
.dst
.sel
= ctx
->temp_reg
;
4998 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5001 /* replicate result */
5002 return tgsi_helper_tempx_replicate(ctx
);
5005 static int cayman_pow(struct r600_shader_ctx
*ctx
)
5007 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5009 struct r600_bytecode_alu alu
;
5010 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
5012 for (i
= 0; i
< 3; i
++) {
5013 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5014 alu
.op
= ALU_OP1_LOG_IEEE
;
5015 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5016 alu
.dst
.sel
= ctx
->temp_reg
;
5021 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5027 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5028 alu
.op
= ALU_OP2_MUL
;
5029 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5030 alu
.src
[1].sel
= ctx
->temp_reg
;
5031 alu
.dst
.sel
= ctx
->temp_reg
;
5034 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5038 for (i
= 0; i
< last_slot
; i
++) {
5039 /* POW(a,b) = EXP2(b * LOG2(a))*/
5040 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5041 alu
.op
= ALU_OP1_EXP_IEEE
;
5042 alu
.src
[0].sel
= ctx
->temp_reg
;
5044 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5045 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
5046 if (i
== last_slot
- 1)
5048 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5055 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
5057 struct r600_bytecode_alu alu
;
5061 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5062 alu
.op
= ALU_OP1_LOG_IEEE
;
5063 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5064 alu
.dst
.sel
= ctx
->temp_reg
;
5067 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5071 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5072 alu
.op
= ALU_OP2_MUL
;
5073 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5074 alu
.src
[1].sel
= ctx
->temp_reg
;
5075 alu
.dst
.sel
= ctx
->temp_reg
;
5078 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5081 /* POW(a,b) = EXP2(b * LOG2(a))*/
5082 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5083 alu
.op
= ALU_OP1_EXP_IEEE
;
5084 alu
.src
[0].sel
= ctx
->temp_reg
;
5085 alu
.dst
.sel
= ctx
->temp_reg
;
5088 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5091 return tgsi_helper_tempx_replicate(ctx
);
5094 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
5096 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5097 struct r600_bytecode_alu alu
;
5099 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5100 int tmp0
= ctx
->temp_reg
;
5101 int tmp1
= r600_get_temp(ctx
);
5102 int tmp2
= r600_get_temp(ctx
);
5103 int tmp3
= r600_get_temp(ctx
);
5106 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5108 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5109 * 2. tmp0.z = lo (tmp0.x * src2)
5110 * 3. tmp0.w = -tmp0.z
5111 * 4. tmp0.y = hi (tmp0.x * src2)
5112 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5113 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5114 * 7. tmp1.x = tmp0.x - tmp0.w
5115 * 8. tmp1.y = tmp0.x + tmp0.w
5116 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5117 * 10. tmp0.z = hi(tmp0.x * src1) = q
5118 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5120 * 12. tmp0.w = src1 - tmp0.y = r
5121 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5122 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5126 * 15. tmp1.z = tmp0.z + 1 = q + 1
5127 * 16. tmp1.w = tmp0.z - 1 = q - 1
5131 * 15. tmp1.z = tmp0.w - src2 = r - src2
5132 * 16. tmp1.w = tmp0.w + src2 = r + src2
5136 * 17. tmp1.x = tmp1.x & tmp1.y
5138 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5139 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5141 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5142 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5146 * Same as unsigned, using abs values of the operands,
5147 * and fixing the sign of the result in the end.
5150 for (i
= 0; i
< 4; i
++) {
5151 if (!(write_mask
& (1<<i
)))
5156 /* tmp2.x = -src0 */
5157 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5158 alu
.op
= ALU_OP2_SUB_INT
;
5164 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5166 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5169 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5172 /* tmp2.y = -src1 */
5173 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5174 alu
.op
= ALU_OP2_SUB_INT
;
5180 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5182 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5185 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5188 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5189 /* it will be a sign of the quotient */
5192 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5193 alu
.op
= ALU_OP2_XOR_INT
;
5199 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5200 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5203 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5207 /* tmp2.x = |src0| */
5208 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5209 alu
.op
= ALU_OP3_CNDGE_INT
;
5216 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5217 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5218 alu
.src
[2].sel
= tmp2
;
5219 alu
.src
[2].chan
= 0;
5222 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5225 /* tmp2.y = |src1| */
5226 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5227 alu
.op
= ALU_OP3_CNDGE_INT
;
5234 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5235 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5236 alu
.src
[2].sel
= tmp2
;
5237 alu
.src
[2].chan
= 1;
5240 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5245 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5246 if (ctx
->bc
->chip_class
== CAYMAN
) {
5247 /* tmp3.x = u2f(src2) */
5248 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5249 alu
.op
= ALU_OP1_UINT_TO_FLT
;
5256 alu
.src
[0].sel
= tmp2
;
5257 alu
.src
[0].chan
= 1;
5259 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5263 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5266 /* tmp0.x = recip(tmp3.x) */
5267 for (j
= 0 ; j
< 3; j
++) {
5268 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5269 alu
.op
= ALU_OP1_RECIP_IEEE
;
5273 alu
.dst
.write
= (j
== 0);
5275 alu
.src
[0].sel
= tmp3
;
5276 alu
.src
[0].chan
= 0;
5280 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5284 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5285 alu
.op
= ALU_OP2_MUL
;
5287 alu
.src
[0].sel
= tmp0
;
5288 alu
.src
[0].chan
= 0;
5290 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5291 alu
.src
[1].value
= 0x4f800000;
5296 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5300 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5301 alu
.op
= ALU_OP1_FLT_TO_UINT
;
5307 alu
.src
[0].sel
= tmp3
;
5308 alu
.src
[0].chan
= 0;
5311 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5315 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5316 alu
.op
= ALU_OP1_RECIP_UINT
;
5323 alu
.src
[0].sel
= tmp2
;
5324 alu
.src
[0].chan
= 1;
5326 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5330 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5334 /* 2. tmp0.z = lo (tmp0.x * src2) */
5335 if (ctx
->bc
->chip_class
== CAYMAN
) {
5336 for (j
= 0 ; j
< 4; j
++) {
5337 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5338 alu
.op
= ALU_OP2_MULLO_UINT
;
5342 alu
.dst
.write
= (j
== 2);
5344 alu
.src
[0].sel
= tmp0
;
5345 alu
.src
[0].chan
= 0;
5347 alu
.src
[1].sel
= tmp2
;
5348 alu
.src
[1].chan
= 1;
5350 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5353 alu
.last
= (j
== 3);
5354 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5358 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5359 alu
.op
= ALU_OP2_MULLO_UINT
;
5365 alu
.src
[0].sel
= tmp0
;
5366 alu
.src
[0].chan
= 0;
5368 alu
.src
[1].sel
= tmp2
;
5369 alu
.src
[1].chan
= 1;
5371 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5375 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5379 /* 3. tmp0.w = -tmp0.z */
5380 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5381 alu
.op
= ALU_OP2_SUB_INT
;
5387 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5388 alu
.src
[1].sel
= tmp0
;
5389 alu
.src
[1].chan
= 2;
5392 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5395 /* 4. tmp0.y = hi (tmp0.x * src2) */
5396 if (ctx
->bc
->chip_class
== CAYMAN
) {
5397 for (j
= 0 ; j
< 4; j
++) {
5398 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5399 alu
.op
= ALU_OP2_MULHI_UINT
;
5403 alu
.dst
.write
= (j
== 1);
5405 alu
.src
[0].sel
= tmp0
;
5406 alu
.src
[0].chan
= 0;
5409 alu
.src
[1].sel
= tmp2
;
5410 alu
.src
[1].chan
= 1;
5412 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5414 alu
.last
= (j
== 3);
5415 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5419 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5420 alu
.op
= ALU_OP2_MULHI_UINT
;
5426 alu
.src
[0].sel
= tmp0
;
5427 alu
.src
[0].chan
= 0;
5430 alu
.src
[1].sel
= tmp2
;
5431 alu
.src
[1].chan
= 1;
5433 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5437 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5441 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5442 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5443 alu
.op
= ALU_OP3_CNDE_INT
;
5450 alu
.src
[0].sel
= tmp0
;
5451 alu
.src
[0].chan
= 1;
5452 alu
.src
[1].sel
= tmp0
;
5453 alu
.src
[1].chan
= 3;
5454 alu
.src
[2].sel
= tmp0
;
5455 alu
.src
[2].chan
= 2;
5458 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5461 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5462 if (ctx
->bc
->chip_class
== CAYMAN
) {
5463 for (j
= 0 ; j
< 4; j
++) {
5464 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5465 alu
.op
= ALU_OP2_MULHI_UINT
;
5469 alu
.dst
.write
= (j
== 3);
5471 alu
.src
[0].sel
= tmp0
;
5472 alu
.src
[0].chan
= 2;
5474 alu
.src
[1].sel
= tmp0
;
5475 alu
.src
[1].chan
= 0;
5477 alu
.last
= (j
== 3);
5478 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5482 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5483 alu
.op
= ALU_OP2_MULHI_UINT
;
5489 alu
.src
[0].sel
= tmp0
;
5490 alu
.src
[0].chan
= 2;
5492 alu
.src
[1].sel
= tmp0
;
5493 alu
.src
[1].chan
= 0;
5496 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5500 /* 7. tmp1.x = tmp0.x - tmp0.w */
5501 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5502 alu
.op
= ALU_OP2_SUB_INT
;
5508 alu
.src
[0].sel
= tmp0
;
5509 alu
.src
[0].chan
= 0;
5510 alu
.src
[1].sel
= tmp0
;
5511 alu
.src
[1].chan
= 3;
5514 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5517 /* 8. tmp1.y = tmp0.x + tmp0.w */
5518 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5519 alu
.op
= ALU_OP2_ADD_INT
;
5525 alu
.src
[0].sel
= tmp0
;
5526 alu
.src
[0].chan
= 0;
5527 alu
.src
[1].sel
= tmp0
;
5528 alu
.src
[1].chan
= 3;
5531 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5534 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5535 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5536 alu
.op
= ALU_OP3_CNDE_INT
;
5543 alu
.src
[0].sel
= tmp0
;
5544 alu
.src
[0].chan
= 1;
5545 alu
.src
[1].sel
= tmp1
;
5546 alu
.src
[1].chan
= 1;
5547 alu
.src
[2].sel
= tmp1
;
5548 alu
.src
[2].chan
= 0;
5551 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5554 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5555 if (ctx
->bc
->chip_class
== CAYMAN
) {
5556 for (j
= 0 ; j
< 4; j
++) {
5557 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5558 alu
.op
= ALU_OP2_MULHI_UINT
;
5562 alu
.dst
.write
= (j
== 2);
5564 alu
.src
[0].sel
= tmp0
;
5565 alu
.src
[0].chan
= 0;
5568 alu
.src
[1].sel
= tmp2
;
5569 alu
.src
[1].chan
= 0;
5571 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5574 alu
.last
= (j
== 3);
5575 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5579 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5580 alu
.op
= ALU_OP2_MULHI_UINT
;
5586 alu
.src
[0].sel
= tmp0
;
5587 alu
.src
[0].chan
= 0;
5590 alu
.src
[1].sel
= tmp2
;
5591 alu
.src
[1].chan
= 0;
5593 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5597 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5601 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5602 if (ctx
->bc
->chip_class
== CAYMAN
) {
5603 for (j
= 0 ; j
< 4; j
++) {
5604 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5605 alu
.op
= ALU_OP2_MULLO_UINT
;
5609 alu
.dst
.write
= (j
== 1);
5612 alu
.src
[0].sel
= tmp2
;
5613 alu
.src
[0].chan
= 1;
5615 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5618 alu
.src
[1].sel
= tmp0
;
5619 alu
.src
[1].chan
= 2;
5621 alu
.last
= (j
== 3);
5622 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5626 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5627 alu
.op
= ALU_OP2_MULLO_UINT
;
5634 alu
.src
[0].sel
= tmp2
;
5635 alu
.src
[0].chan
= 1;
5637 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5640 alu
.src
[1].sel
= tmp0
;
5641 alu
.src
[1].chan
= 2;
5644 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5648 /* 12. tmp0.w = src1 - tmp0.y = r */
5649 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5650 alu
.op
= ALU_OP2_SUB_INT
;
5657 alu
.src
[0].sel
= tmp2
;
5658 alu
.src
[0].chan
= 0;
5660 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5663 alu
.src
[1].sel
= tmp0
;
5664 alu
.src
[1].chan
= 1;
5667 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5670 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5671 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5672 alu
.op
= ALU_OP2_SETGE_UINT
;
5678 alu
.src
[0].sel
= tmp0
;
5679 alu
.src
[0].chan
= 3;
5681 alu
.src
[1].sel
= tmp2
;
5682 alu
.src
[1].chan
= 1;
5684 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5688 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5691 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5692 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5693 alu
.op
= ALU_OP2_SETGE_UINT
;
5700 alu
.src
[0].sel
= tmp2
;
5701 alu
.src
[0].chan
= 0;
5703 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5706 alu
.src
[1].sel
= tmp0
;
5707 alu
.src
[1].chan
= 1;
5710 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5713 if (mod
) { /* UMOD */
5715 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5716 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5717 alu
.op
= ALU_OP2_SUB_INT
;
5723 alu
.src
[0].sel
= tmp0
;
5724 alu
.src
[0].chan
= 3;
5727 alu
.src
[1].sel
= tmp2
;
5728 alu
.src
[1].chan
= 1;
5730 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5734 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5737 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5738 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5739 alu
.op
= ALU_OP2_ADD_INT
;
5745 alu
.src
[0].sel
= tmp0
;
5746 alu
.src
[0].chan
= 3;
5748 alu
.src
[1].sel
= tmp2
;
5749 alu
.src
[1].chan
= 1;
5751 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5755 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5760 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5761 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5762 alu
.op
= ALU_OP2_ADD_INT
;
5768 alu
.src
[0].sel
= tmp0
;
5769 alu
.src
[0].chan
= 2;
5770 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
5773 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5776 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5777 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5778 alu
.op
= ALU_OP2_ADD_INT
;
5784 alu
.src
[0].sel
= tmp0
;
5785 alu
.src
[0].chan
= 2;
5786 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
5789 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5794 /* 17. tmp1.x = tmp1.x & tmp1.y */
5795 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5796 alu
.op
= ALU_OP2_AND_INT
;
5802 alu
.src
[0].sel
= tmp1
;
5803 alu
.src
[0].chan
= 0;
5804 alu
.src
[1].sel
= tmp1
;
5805 alu
.src
[1].chan
= 1;
5808 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5811 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5812 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5813 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5814 alu
.op
= ALU_OP3_CNDE_INT
;
5821 alu
.src
[0].sel
= tmp1
;
5822 alu
.src
[0].chan
= 0;
5823 alu
.src
[1].sel
= tmp0
;
5824 alu
.src
[1].chan
= mod
? 3 : 2;
5825 alu
.src
[2].sel
= tmp1
;
5826 alu
.src
[2].chan
= 2;
5829 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5832 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5833 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5834 alu
.op
= ALU_OP3_CNDE_INT
;
5842 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5845 alu
.src
[0].sel
= tmp1
;
5846 alu
.src
[0].chan
= 1;
5847 alu
.src
[1].sel
= tmp1
;
5848 alu
.src
[1].chan
= 3;
5849 alu
.src
[2].sel
= tmp0
;
5850 alu
.src
[2].chan
= 2;
5853 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5858 /* fix the sign of the result */
5862 /* tmp0.x = -tmp0.z */
5863 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5864 alu
.op
= ALU_OP2_SUB_INT
;
5870 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5871 alu
.src
[1].sel
= tmp0
;
5872 alu
.src
[1].chan
= 2;
5875 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5878 /* sign of the remainder is the same as the sign of src0 */
5879 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5880 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5881 alu
.op
= ALU_OP3_CNDGE_INT
;
5884 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5886 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5887 alu
.src
[1].sel
= tmp0
;
5888 alu
.src
[1].chan
= 2;
5889 alu
.src
[2].sel
= tmp0
;
5890 alu
.src
[2].chan
= 0;
5893 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5898 /* tmp0.x = -tmp0.z */
5899 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5900 alu
.op
= ALU_OP2_SUB_INT
;
5906 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5907 alu
.src
[1].sel
= tmp0
;
5908 alu
.src
[1].chan
= 2;
5911 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5914 /* fix the quotient sign (same as the sign of src0*src1) */
5915 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5916 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5917 alu
.op
= ALU_OP3_CNDGE_INT
;
5920 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5922 alu
.src
[0].sel
= tmp2
;
5923 alu
.src
[0].chan
= 2;
5924 alu
.src
[1].sel
= tmp0
;
5925 alu
.src
[1].chan
= 2;
5926 alu
.src
[2].sel
= tmp0
;
5927 alu
.src
[2].chan
= 0;
5930 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5938 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
5940 return tgsi_divmod(ctx
, 0, 0);
5943 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
5945 return tgsi_divmod(ctx
, 1, 0);
5948 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
5950 return tgsi_divmod(ctx
, 0, 1);
5953 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
5955 return tgsi_divmod(ctx
, 1, 1);
5959 static int tgsi_f2i(struct r600_shader_ctx
*ctx
)
5961 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5962 struct r600_bytecode_alu alu
;
5964 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5965 int last_inst
= tgsi_last_instruction(write_mask
);
5967 for (i
= 0; i
< 4; i
++) {
5968 if (!(write_mask
& (1<<i
)))
5971 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5972 alu
.op
= ALU_OP1_TRUNC
;
5974 alu
.dst
.sel
= ctx
->temp_reg
;
5978 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5981 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5986 for (i
= 0; i
< 4; i
++) {
5987 if (!(write_mask
& (1<<i
)))
5990 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5991 alu
.op
= ctx
->inst_info
->op
;
5993 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5995 alu
.src
[0].sel
= ctx
->temp_reg
;
5996 alu
.src
[0].chan
= i
;
5998 if (i
== last_inst
|| alu
.op
== ALU_OP1_FLT_TO_UINT
)
6000 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6008 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
6010 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6011 struct r600_bytecode_alu alu
;
6013 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6014 int last_inst
= tgsi_last_instruction(write_mask
);
6017 for (i
= 0; i
< 4; i
++) {
6018 if (!(write_mask
& (1<<i
)))
6021 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6022 alu
.op
= ALU_OP2_SUB_INT
;
6024 alu
.dst
.sel
= ctx
->temp_reg
;
6028 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6029 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
6033 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6038 /* dst = (src >= 0 ? src : tmp) */
6039 for (i
= 0; i
< 4; i
++) {
6040 if (!(write_mask
& (1<<i
)))
6043 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6044 alu
.op
= ALU_OP3_CNDGE_INT
;
6048 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6050 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6051 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6052 alu
.src
[2].sel
= ctx
->temp_reg
;
6053 alu
.src
[2].chan
= i
;
6057 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6064 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
6066 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6067 struct r600_bytecode_alu alu
;
6069 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6070 int last_inst
= tgsi_last_instruction(write_mask
);
6072 /* tmp = (src >= 0 ? src : -1) */
6073 for (i
= 0; i
< 4; i
++) {
6074 if (!(write_mask
& (1<<i
)))
6077 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6078 alu
.op
= ALU_OP3_CNDGE_INT
;
6081 alu
.dst
.sel
= ctx
->temp_reg
;
6085 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6086 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6087 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
6091 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6096 /* dst = (tmp > 0 ? 1 : tmp) */
6097 for (i
= 0; i
< 4; i
++) {
6098 if (!(write_mask
& (1<<i
)))
6101 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6102 alu
.op
= ALU_OP3_CNDGT_INT
;
6106 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6108 alu
.src
[0].sel
= ctx
->temp_reg
;
6109 alu
.src
[0].chan
= i
;
6111 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
6113 alu
.src
[2].sel
= ctx
->temp_reg
;
6114 alu
.src
[2].chan
= i
;
6118 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6127 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
6129 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6130 struct r600_bytecode_alu alu
;
6133 /* tmp = (src > 0 ? 1 : src) */
6134 for (i
= 0; i
< 4; i
++) {
6135 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6136 alu
.op
= ALU_OP3_CNDGT
;
6139 alu
.dst
.sel
= ctx
->temp_reg
;
6142 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6143 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6144 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6148 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6153 /* dst = (-tmp > 0 ? -1 : tmp) */
6154 for (i
= 0; i
< 4; i
++) {
6155 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6156 alu
.op
= ALU_OP3_CNDGT
;
6158 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6160 alu
.src
[0].sel
= ctx
->temp_reg
;
6161 alu
.src
[0].chan
= i
;
6164 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6167 alu
.src
[2].sel
= ctx
->temp_reg
;
6168 alu
.src
[2].chan
= i
;
6172 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6179 static int tgsi_bfi(struct r600_shader_ctx
*ctx
)
6181 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6182 struct r600_bytecode_alu alu
;
6185 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6186 int last_inst
= tgsi_last_instruction(write_mask
);
6188 t1
= r600_get_temp(ctx
);
6190 for (i
= 0; i
< 4; i
++) {
6191 if (!(write_mask
& (1<<i
)))
6194 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6195 alu
.op
= ALU_OP2_SETGE_INT
;
6196 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6197 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
6198 alu
.src
[1].value
= 32;
6199 alu
.dst
.sel
= ctx
->temp_reg
;
6202 alu
.last
= i
== last_inst
;
6203 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6208 for (i
= 0; i
< 4; i
++) {
6209 if (!(write_mask
& (1<<i
)))
6212 /* create mask tmp */
6213 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6214 alu
.op
= ALU_OP2_BFM_INT
;
6218 alu
.last
= i
== last_inst
;
6220 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6221 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6223 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6228 t2
= r600_get_temp(ctx
);
6230 for (i
= 0; i
< 4; i
++) {
6231 if (!(write_mask
& (1<<i
)))
6234 /* shift insert left */
6235 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6236 alu
.op
= ALU_OP2_LSHL_INT
;
6240 alu
.last
= i
== last_inst
;
6242 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
6243 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6245 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6250 for (i
= 0; i
< 4; i
++) {
6251 if (!(write_mask
& (1<<i
)))
6254 /* actual bitfield insert */
6255 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6256 alu
.op
= ALU_OP3_BFI_INT
;
6258 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6261 alu
.last
= i
== last_inst
;
6263 alu
.src
[0].sel
= t1
;
6264 alu
.src
[0].chan
= i
;
6265 alu
.src
[1].sel
= t2
;
6266 alu
.src
[1].chan
= i
;
6267 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6269 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6274 for (i
= 0; i
< 4; i
++) {
6275 if (!(write_mask
& (1<<i
)))
6277 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6278 alu
.op
= ALU_OP3_CNDE_INT
;
6280 alu
.src
[0].sel
= ctx
->temp_reg
;
6281 alu
.src
[0].chan
= i
;
6282 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
6284 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6286 alu
.src
[1].sel
= alu
.dst
.sel
;
6287 alu
.src
[1].chan
= i
;
6289 alu
.last
= i
== last_inst
;
6290 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6297 static int tgsi_msb(struct r600_shader_ctx
*ctx
)
6299 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6300 struct r600_bytecode_alu alu
;
6303 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6304 int last_inst
= tgsi_last_instruction(write_mask
);
6306 assert(ctx
->inst_info
->op
== ALU_OP1_FFBH_INT
||
6307 ctx
->inst_info
->op
== ALU_OP1_FFBH_UINT
);
6311 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6312 for (i
= 0; i
< 4; i
++) {
6313 if (!(write_mask
& (1<<i
)))
6316 /* t1 = FFBH_INT / FFBH_UINT */
6317 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6318 alu
.op
= ctx
->inst_info
->op
;
6322 alu
.last
= i
== last_inst
;
6324 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6326 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6331 t2
= r600_get_temp(ctx
);
6333 for (i
= 0; i
< 4; i
++) {
6334 if (!(write_mask
& (1<<i
)))
6338 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6339 alu
.op
= ALU_OP2_SUB_INT
;
6343 alu
.last
= i
== last_inst
;
6345 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
6346 alu
.src
[0].value
= 31;
6347 alu
.src
[1].sel
= t1
;
6348 alu
.src
[1].chan
= i
;
6350 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6355 for (i
= 0; i
< 4; i
++) {
6356 if (!(write_mask
& (1<<i
)))
6359 /* result = t1 >= 0 ? t2 : t1 */
6360 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6361 alu
.op
= ALU_OP3_CNDGE_INT
;
6363 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6366 alu
.last
= i
== last_inst
;
6368 alu
.src
[0].sel
= t1
;
6369 alu
.src
[0].chan
= i
;
6370 alu
.src
[1].sel
= t2
;
6371 alu
.src
[1].chan
= i
;
6372 alu
.src
[2].sel
= t1
;
6373 alu
.src
[2].chan
= i
;
6375 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6383 static int tgsi_interp_egcm(struct r600_shader_ctx
*ctx
)
6385 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6386 struct r600_bytecode_alu alu
;
6387 int r
, i
= 0, k
, interp_gpr
, interp_base_chan
, tmp
, lasti
;
6389 const int input
= inst
->Src
[0].Register
.Index
+ ctx
->shader
->nsys_inputs
;
6391 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
6393 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6394 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6395 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6396 location
= TGSI_INTERPOLATE_LOC_CENTER
; /* sample offset will be added explicitly */
6399 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
6402 k
= eg_get_interpolator_index(ctx
->shader
->input
[input
].interpolate
, location
);
6405 interp_gpr
= ctx
->eg_interpolators
[k
].ij_index
/ 2;
6406 interp_base_chan
= 2 * (ctx
->eg_interpolators
[k
].ij_index
% 2);
6408 /* NOTE: currently offset is not perspective correct */
6409 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6410 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6411 int sample_gpr
= -1;
6412 int gradientsH
, gradientsV
;
6413 struct r600_bytecode_tex tex
;
6415 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6416 sample_gpr
= load_sample_position(ctx
, &ctx
->src
[1], ctx
->src
[1].swizzle
[0]);
6419 gradientsH
= r600_get_temp(ctx
);
6420 gradientsV
= r600_get_temp(ctx
);
6421 for (i
= 0; i
< 2; i
++) {
6422 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
6423 tex
.op
= i
== 0 ? FETCH_OP_GET_GRADIENTS_H
: FETCH_OP_GET_GRADIENTS_V
;
6424 tex
.src_gpr
= interp_gpr
;
6425 tex
.src_sel_x
= interp_base_chan
+ 0;
6426 tex
.src_sel_y
= interp_base_chan
+ 1;
6429 tex
.dst_gpr
= i
== 0 ? gradientsH
: gradientsV
;
6434 tex
.inst_mod
= 1; // Use per pixel gradient calculation
6436 tex
.resource_id
= tex
.sampler_id
;
6437 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
6442 for (i
= 0; i
< 2; i
++) {
6443 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6444 alu
.op
= ALU_OP3_MULADD
;
6446 alu
.src
[0].sel
= gradientsH
;
6447 alu
.src
[0].chan
= i
;
6448 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6449 alu
.src
[1].sel
= sample_gpr
;
6450 alu
.src
[1].chan
= 2;
6453 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 0);
6455 alu
.src
[2].sel
= interp_gpr
;
6456 alu
.src
[2].chan
= interp_base_chan
+ i
;
6457 alu
.dst
.sel
= ctx
->temp_reg
;
6461 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6466 for (i
= 0; i
< 2; i
++) {
6467 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6468 alu
.op
= ALU_OP3_MULADD
;
6470 alu
.src
[0].sel
= gradientsV
;
6471 alu
.src
[0].chan
= i
;
6472 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6473 alu
.src
[1].sel
= sample_gpr
;
6474 alu
.src
[1].chan
= 3;
6477 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 1);
6479 alu
.src
[2].sel
= ctx
->temp_reg
;
6480 alu
.src
[2].chan
= i
;
6481 alu
.dst
.sel
= ctx
->temp_reg
;
6485 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6491 tmp
= r600_get_temp(ctx
);
6492 for (i
= 0; i
< 8; i
++) {
6493 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6494 alu
.op
= i
< 4 ? ALU_OP2_INTERP_ZW
: ALU_OP2_INTERP_XY
;
6497 if ((i
> 1 && i
< 6)) {
6503 alu
.dst
.chan
= i
% 4;
6505 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6506 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6507 alu
.src
[0].sel
= ctx
->temp_reg
;
6508 alu
.src
[0].chan
= 1 - (i
% 2);
6510 alu
.src
[0].sel
= interp_gpr
;
6511 alu
.src
[0].chan
= interp_base_chan
+ 1 - (i
% 2);
6513 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
6514 alu
.src
[1].chan
= 0;
6516 alu
.last
= i
% 4 == 3;
6517 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
6519 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6524 // INTERP can't swizzle dst
6525 lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6526 for (i
= 0; i
<= lasti
; i
++) {
6527 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6530 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6531 alu
.op
= ALU_OP1_MOV
;
6532 alu
.src
[0].sel
= tmp
;
6533 alu
.src
[0].chan
= ctx
->src
[0].swizzle
[i
];
6534 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6536 alu
.last
= i
== lasti
;
6537 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6546 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
6548 struct r600_bytecode_alu alu
;
6551 for (i
= 0; i
< 4; i
++) {
6552 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6553 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
6554 alu
.op
= ALU_OP0_NOP
;
6557 alu
.op
= ALU_OP1_MOV
;
6558 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6559 alu
.src
[0].sel
= ctx
->temp_reg
;
6560 alu
.src
[0].chan
= i
;
6565 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6572 static int tgsi_make_src_for_op3(struct r600_shader_ctx
*ctx
,
6573 unsigned temp
, int chan
,
6574 struct r600_bytecode_alu_src
*bc_src
,
6575 const struct r600_shader_src
*shader_src
)
6577 struct r600_bytecode_alu alu
;
6580 r600_bytecode_src(bc_src
, shader_src
, chan
);
6582 /* op3 operands don't support abs modifier */
6584 assert(temp
!=0); /* we actually need the extra register, make sure it is allocated. */
6585 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6586 alu
.op
= ALU_OP1_MOV
;
6588 alu
.dst
.chan
= chan
;
6591 alu
.src
[0] = *bc_src
;
6592 alu
.last
= true; // sufficient?
6593 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6597 memset(bc_src
, 0, sizeof(*bc_src
));
6599 bc_src
->chan
= chan
;
6604 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
6606 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6607 struct r600_bytecode_alu alu
;
6609 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6611 unsigned op
= ctx
->inst_info
->op
;
6613 if (op
== ALU_OP3_MULADD_IEEE
&&
6614 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6615 op
= ALU_OP3_MULADD
;
6617 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6619 if (ctx
->src
[j
].abs
)
6620 temp_regs
[j
] = r600_get_temp(ctx
);
6622 for (i
= 0; i
< lasti
+ 1; i
++) {
6623 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6626 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6628 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6629 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[j
], i
, &alu
.src
[j
], &ctx
->src
[j
]);
6634 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6641 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6648 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
6650 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6651 struct r600_bytecode_alu alu
;
6653 unsigned op
= ctx
->inst_info
->op
;
6654 if (op
== ALU_OP2_DOT4_IEEE
&&
6655 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6658 for (i
= 0; i
< 4; i
++) {
6659 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6661 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6662 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
6665 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6667 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
6668 /* handle some special cases */
6669 switch (inst
->Instruction
.Opcode
) {
6670 case TGSI_OPCODE_DP2
:
6672 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6673 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6676 case TGSI_OPCODE_DP3
:
6678 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6679 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6688 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6695 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
6698 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6699 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
6700 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
&&
6701 inst
->Src
[index
].Register
.File
!= TGSI_FILE_OUTPUT
) ||
6702 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
||
6703 (inst
->Src
[index
].Register
.File
== TGSI_FILE_INPUT
&& ctx
->type
== PIPE_SHADER_GEOMETRY
);
6706 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
6709 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6710 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
6713 static int do_vtx_fetch_inst(struct r600_shader_ctx
*ctx
, boolean src_requires_loading
)
6715 struct r600_bytecode_vtx vtx
;
6716 struct r600_bytecode_alu alu
;
6717 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6719 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6721 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6722 if (src_requires_loading
) {
6723 for (i
= 0; i
< 4; i
++) {
6724 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6725 alu
.op
= ALU_OP1_MOV
;
6726 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6727 alu
.dst
.sel
= ctx
->temp_reg
;
6732 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6736 src_gpr
= ctx
->temp_reg
;
6739 memset(&vtx
, 0, sizeof(vtx
));
6740 vtx
.op
= FETCH_OP_VFETCH
;
6741 vtx
.buffer_id
= id
+ R600_MAX_CONST_BUFFERS
;
6742 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
6743 vtx
.src_gpr
= src_gpr
;
6744 vtx
.mega_fetch_count
= 16;
6745 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
6746 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
6747 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7; /* SEL_Y */
6748 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7; /* SEL_Z */
6749 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7; /* SEL_W */
6750 vtx
.use_const_fields
= 1;
6752 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
6755 if (ctx
->bc
->chip_class
>= EVERGREEN
)
6758 for (i
= 0; i
< 4; i
++) {
6759 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6760 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6763 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6764 alu
.op
= ALU_OP2_AND_INT
;
6767 alu
.dst
.sel
= vtx
.dst_gpr
;
6770 alu
.src
[0].sel
= vtx
.dst_gpr
;
6771 alu
.src
[0].chan
= i
;
6773 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6774 alu
.src
[1].sel
+= (id
* 2);
6775 alu
.src
[1].chan
= i
% 4;
6776 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6780 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6785 if (inst
->Dst
[0].Register
.WriteMask
& 3) {
6786 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6787 alu
.op
= ALU_OP2_OR_INT
;
6790 alu
.dst
.sel
= vtx
.dst_gpr
;
6793 alu
.src
[0].sel
= vtx
.dst_gpr
;
6794 alu
.src
[0].chan
= 3;
6796 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
+ (id
* 2) + 1;
6797 alu
.src
[1].chan
= 0;
6798 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6801 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6808 static int r600_do_buffer_txq(struct r600_shader_ctx
*ctx
)
6810 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6811 struct r600_bytecode_alu alu
;
6813 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6815 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6816 alu
.op
= ALU_OP1_MOV
;
6817 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6818 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
6819 /* channel 0 or 2 of each word */
6820 alu
.src
[0].sel
+= (id
/ 2);
6821 alu
.src
[0].chan
= (id
% 2) * 2;
6823 /* r600 we have them at channel 2 of the second dword */
6824 alu
.src
[0].sel
+= (id
* 2) + 1;
6825 alu
.src
[0].chan
= 1;
6827 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6828 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
6830 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6836 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
6838 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6839 struct r600_bytecode_tex tex
;
6840 struct r600_bytecode_alu alu
;
6844 bool read_compressed_msaa
= ctx
->bc
->has_compressed_msaa_texturing
&&
6845 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6846 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
6847 inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
6849 bool txf_add_offsets
= inst
->Texture
.NumOffsets
&&
6850 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6851 inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
;
6853 /* Texture fetch instructions can only use gprs as source.
6854 * Also they cannot negate the source or take the absolute value */
6855 const boolean src_requires_loading
= (inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQS
&&
6856 tgsi_tex_src_requires_loading(ctx
, 0)) ||
6857 read_compressed_msaa
|| txf_add_offsets
;
6859 boolean src_loaded
= FALSE
;
6860 unsigned sampler_src_reg
= 1;
6861 int8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
6862 boolean has_txq_cube_array_z
= false;
6863 unsigned sampler_index_mode
;
6865 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
6866 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
6867 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)))
6868 if (inst
->Dst
[0].Register
.WriteMask
& 4) {
6869 ctx
->shader
->has_txq_cube_array_z_comp
= true;
6870 has_txq_cube_array_z
= true;
6873 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
6874 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
6875 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
||
6876 inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
)
6877 sampler_src_reg
= 2;
6879 /* TGSI moves the sampler to src reg 3 for TXD */
6880 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
)
6881 sampler_src_reg
= 3;
6883 sampler_index_mode
= inst
->Src
[sampler_src_reg
].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6885 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6887 if (inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
6888 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
6889 ctx
->shader
->uses_tex_buffers
= true;
6890 return r600_do_buffer_txq(ctx
);
6892 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
6893 if (ctx
->bc
->chip_class
< EVERGREEN
)
6894 ctx
->shader
->uses_tex_buffers
= true;
6895 return do_vtx_fetch_inst(ctx
, src_requires_loading
);
6899 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
6901 /* Add perspective divide */
6902 if (ctx
->bc
->chip_class
== CAYMAN
) {
6904 for (i
= 0; i
< 3; i
++) {
6905 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6906 alu
.op
= ALU_OP1_RECIP_IEEE
;
6907 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6909 alu
.dst
.sel
= ctx
->temp_reg
;
6915 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6922 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6923 alu
.op
= ALU_OP1_RECIP_IEEE
;
6924 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6926 alu
.dst
.sel
= ctx
->temp_reg
;
6927 alu
.dst
.chan
= out_chan
;
6930 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6935 for (i
= 0; i
< 3; i
++) {
6936 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6937 alu
.op
= ALU_OP2_MUL
;
6938 alu
.src
[0].sel
= ctx
->temp_reg
;
6939 alu
.src
[0].chan
= out_chan
;
6940 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6941 alu
.dst
.sel
= ctx
->temp_reg
;
6944 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6948 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6949 alu
.op
= ALU_OP1_MOV
;
6950 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
6951 alu
.src
[0].chan
= 0;
6952 alu
.dst
.sel
= ctx
->temp_reg
;
6956 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6960 src_gpr
= ctx
->temp_reg
;
6964 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
6965 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
6966 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
6967 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
6968 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
) {
6970 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
6971 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
6973 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6974 for (i
= 0; i
< 4; i
++) {
6975 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6976 alu
.op
= ALU_OP2_CUBE
;
6977 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
6978 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
6979 alu
.dst
.sel
= ctx
->temp_reg
;
6984 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6989 /* tmp1.z = RCP_e(|tmp1.z|) */
6990 if (ctx
->bc
->chip_class
== CAYMAN
) {
6991 for (i
= 0; i
< 3; i
++) {
6992 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6993 alu
.op
= ALU_OP1_RECIP_IEEE
;
6994 alu
.src
[0].sel
= ctx
->temp_reg
;
6995 alu
.src
[0].chan
= 2;
6997 alu
.dst
.sel
= ctx
->temp_reg
;
7003 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7008 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7009 alu
.op
= ALU_OP1_RECIP_IEEE
;
7010 alu
.src
[0].sel
= ctx
->temp_reg
;
7011 alu
.src
[0].chan
= 2;
7013 alu
.dst
.sel
= ctx
->temp_reg
;
7017 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7022 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7023 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7024 * muladd has no writemask, have to use another temp
7026 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7027 alu
.op
= ALU_OP3_MULADD
;
7030 alu
.src
[0].sel
= ctx
->temp_reg
;
7031 alu
.src
[0].chan
= 0;
7032 alu
.src
[1].sel
= ctx
->temp_reg
;
7033 alu
.src
[1].chan
= 2;
7035 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
7036 alu
.src
[2].chan
= 0;
7037 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
7039 alu
.dst
.sel
= ctx
->temp_reg
;
7043 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7047 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7048 alu
.op
= ALU_OP3_MULADD
;
7051 alu
.src
[0].sel
= ctx
->temp_reg
;
7052 alu
.src
[0].chan
= 1;
7053 alu
.src
[1].sel
= ctx
->temp_reg
;
7054 alu
.src
[1].chan
= 2;
7056 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
7057 alu
.src
[2].chan
= 0;
7058 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
7060 alu
.dst
.sel
= ctx
->temp_reg
;
7065 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7068 /* write initial compare value into Z component
7069 - W src 0 for shadow cube
7070 - X src 1 for shadow cube array */
7071 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7072 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7073 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7074 alu
.op
= ALU_OP1_MOV
;
7075 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
7076 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7078 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7079 alu
.dst
.sel
= ctx
->temp_reg
;
7083 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7088 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7089 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7090 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7091 int mytmp
= r600_get_temp(ctx
);
7092 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7093 alu
.op
= ALU_OP1_MOV
;
7094 alu
.src
[0].sel
= ctx
->temp_reg
;
7095 alu
.src
[0].chan
= 3;
7096 alu
.dst
.sel
= mytmp
;
7100 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7104 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7105 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7106 alu
.op
= ALU_OP3_MULADD
;
7108 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7109 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7110 alu
.src
[1].chan
= 0;
7111 alu
.src
[1].value
= u_bitcast_f2u(8.0f
);
7112 alu
.src
[2].sel
= mytmp
;
7113 alu
.src
[2].chan
= 0;
7114 alu
.dst
.sel
= ctx
->temp_reg
;
7118 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7121 } else if (ctx
->bc
->chip_class
< EVERGREEN
) {
7122 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7123 tex
.op
= FETCH_OP_SET_CUBEMAP_INDEX
;
7124 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7125 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7126 tex
.src_gpr
= r600_get_temp(ctx
);
7131 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7132 tex
.coord_type_x
= 1;
7133 tex
.coord_type_y
= 1;
7134 tex
.coord_type_z
= 1;
7135 tex
.coord_type_w
= 1;
7136 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7137 alu
.op
= ALU_OP1_MOV
;
7138 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7139 alu
.dst
.sel
= tex
.src_gpr
;
7143 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7147 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7154 /* for cube forms of lod and bias we need to route things */
7155 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
||
7156 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
||
7157 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7158 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
7159 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7160 alu
.op
= ALU_OP1_MOV
;
7161 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7162 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
)
7163 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7165 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7166 alu
.dst
.sel
= ctx
->temp_reg
;
7170 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7176 src_gpr
= ctx
->temp_reg
;
7179 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
7180 int temp_h
= 0, temp_v
= 0;
7183 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7184 if (src_loaded
== TRUE
)
7188 for (i
= start_val
; i
< 3; i
++) {
7189 int treg
= r600_get_temp(ctx
);
7198 for (j
= 0; j
< 4; j
++) {
7199 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7200 alu
.op
= ALU_OP1_MOV
;
7201 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
7207 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7212 for (i
= 1; i
< 3; i
++) {
7213 /* set gradients h/v */
7214 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7215 tex
.op
= (i
== 1) ? FETCH_OP_SET_GRADIENTS_H
:
7216 FETCH_OP_SET_GRADIENTS_V
;
7217 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7218 tex
.sampler_index_mode
= sampler_index_mode
;
7219 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7220 tex
.resource_index_mode
= sampler_index_mode
;
7222 tex
.src_gpr
= (i
== 1) ? temp_h
: temp_v
;
7228 tex
.dst_gpr
= r600_get_temp(ctx
); /* just to avoid confusing the asm scheduler */
7229 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7230 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
7231 tex
.coord_type_x
= 1;
7232 tex
.coord_type_y
= 1;
7233 tex
.coord_type_z
= 1;
7234 tex
.coord_type_w
= 1;
7236 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7242 if (src_requires_loading
&& !src_loaded
) {
7243 for (i
= 0; i
< 4; i
++) {
7244 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7245 alu
.op
= ALU_OP1_MOV
;
7246 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
7247 alu
.dst
.sel
= ctx
->temp_reg
;
7252 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7257 src_gpr
= ctx
->temp_reg
;
7260 /* get offset values */
7261 if (inst
->Texture
.NumOffsets
) {
7262 assert(inst
->Texture
.NumOffsets
== 1);
7264 /* The texture offset feature doesn't work with the TXF instruction
7265 * and must be emulated by adding the offset to the texture coordinates. */
7266 if (txf_add_offsets
) {
7267 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
7269 switch (inst
->Texture
.Texture
) {
7270 case TGSI_TEXTURE_3D
:
7271 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7272 alu
.op
= ALU_OP2_ADD_INT
;
7273 alu
.src
[0].sel
= src_gpr
;
7274 alu
.src
[0].chan
= 2;
7275 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7276 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleZ
];
7277 alu
.dst
.sel
= src_gpr
;
7281 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7286 case TGSI_TEXTURE_2D
:
7287 case TGSI_TEXTURE_SHADOW2D
:
7288 case TGSI_TEXTURE_RECT
:
7289 case TGSI_TEXTURE_SHADOWRECT
:
7290 case TGSI_TEXTURE_2D_ARRAY
:
7291 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7292 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7293 alu
.op
= ALU_OP2_ADD_INT
;
7294 alu
.src
[0].sel
= src_gpr
;
7295 alu
.src
[0].chan
= 1;
7296 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7297 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleY
];
7298 alu
.dst
.sel
= src_gpr
;
7302 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7307 case TGSI_TEXTURE_1D
:
7308 case TGSI_TEXTURE_SHADOW1D
:
7309 case TGSI_TEXTURE_1D_ARRAY
:
7310 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7311 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7312 alu
.op
= ALU_OP2_ADD_INT
;
7313 alu
.src
[0].sel
= src_gpr
;
7314 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7315 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleX
];
7316 alu
.dst
.sel
= src_gpr
;
7319 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7323 /* texture offsets do not apply to other texture targets */
7326 switch (inst
->Texture
.Texture
) {
7327 case TGSI_TEXTURE_3D
:
7328 offset_z
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
7330 case TGSI_TEXTURE_2D
:
7331 case TGSI_TEXTURE_SHADOW2D
:
7332 case TGSI_TEXTURE_RECT
:
7333 case TGSI_TEXTURE_SHADOWRECT
:
7334 case TGSI_TEXTURE_2D_ARRAY
:
7335 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7336 offset_y
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
7338 case TGSI_TEXTURE_1D
:
7339 case TGSI_TEXTURE_SHADOW1D
:
7340 case TGSI_TEXTURE_1D_ARRAY
:
7341 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7342 offset_x
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
7347 /* Obtain the sample index for reading a compressed MSAA color texture.
7348 * To read the FMASK, we use the ldfptr instruction, which tells us
7349 * where the samples are stored.
7350 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7351 * which is the identity mapping. Each nibble says which physical sample
7352 * should be fetched to get that sample.
7354 * Assume src.z contains the sample index. It should be modified like this:
7355 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7356 * Then fetch the texel with src.
7358 if (read_compressed_msaa
) {
7359 unsigned sample_chan
= 3;
7360 unsigned temp
= r600_get_temp(ctx
);
7363 /* temp.w = ldfptr() */
7364 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7365 tex
.op
= FETCH_OP_LD
;
7366 tex
.inst_mod
= 1; /* to indicate this is ldfptr */
7367 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7368 tex
.sampler_index_mode
= sampler_index_mode
;
7369 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7370 tex
.resource_index_mode
= sampler_index_mode
;
7371 tex
.src_gpr
= src_gpr
;
7373 tex
.dst_sel_x
= 7; /* mask out these components */
7376 tex
.dst_sel_w
= 0; /* store X */
7381 tex
.offset_x
= offset_x
;
7382 tex
.offset_y
= offset_y
;
7383 tex
.offset_z
= offset_z
;
7384 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7388 /* temp.x = sample_index*4 */
7389 if (ctx
->bc
->chip_class
== CAYMAN
) {
7390 for (i
= 0 ; i
< 4; i
++) {
7391 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7392 alu
.op
= ALU_OP2_MULLO_INT
;
7393 alu
.src
[0].sel
= src_gpr
;
7394 alu
.src
[0].chan
= sample_chan
;
7395 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7396 alu
.src
[1].value
= 4;
7399 alu
.dst
.write
= i
== 0;
7402 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7407 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7408 alu
.op
= ALU_OP2_MULLO_INT
;
7409 alu
.src
[0].sel
= src_gpr
;
7410 alu
.src
[0].chan
= sample_chan
;
7411 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7412 alu
.src
[1].value
= 4;
7417 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7422 /* sample_index = temp.w >> temp.x */
7423 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7424 alu
.op
= ALU_OP2_LSHR_INT
;
7425 alu
.src
[0].sel
= temp
;
7426 alu
.src
[0].chan
= 3;
7427 alu
.src
[1].sel
= temp
;
7428 alu
.src
[1].chan
= 0;
7429 alu
.dst
.sel
= src_gpr
;
7430 alu
.dst
.chan
= sample_chan
;
7433 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7437 /* sample_index & 0xF */
7438 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7439 alu
.op
= ALU_OP2_AND_INT
;
7440 alu
.src
[0].sel
= src_gpr
;
7441 alu
.src
[0].chan
= sample_chan
;
7442 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7443 alu
.src
[1].value
= 0xF;
7444 alu
.dst
.sel
= src_gpr
;
7445 alu
.dst
.chan
= sample_chan
;
7448 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7452 /* visualize the FMASK */
7453 for (i
= 0; i
< 4; i
++) {
7454 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7455 alu
.op
= ALU_OP1_INT_TO_FLT
;
7456 alu
.src
[0].sel
= src_gpr
;
7457 alu
.src
[0].chan
= sample_chan
;
7458 alu
.dst
.sel
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7462 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7470 /* does this shader want a num layers from TXQ for a cube array? */
7471 if (has_txq_cube_array_z
) {
7472 int id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7474 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7475 alu
.op
= ALU_OP1_MOV
;
7477 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
7478 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7479 /* channel 1 or 3 of each word */
7480 alu
.src
[0].sel
+= (id
/ 2);
7481 alu
.src
[0].chan
= ((id
% 2) * 2) + 1;
7483 /* r600 we have them at channel 2 of the second dword */
7484 alu
.src
[0].sel
+= (id
* 2) + 1;
7485 alu
.src
[0].chan
= 2;
7487 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
7488 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
7490 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7493 /* disable writemask from texture instruction */
7494 inst
->Dst
[0].Register
.WriteMask
&= ~4;
7497 opcode
= ctx
->inst_info
->op
;
7498 if (opcode
== FETCH_OP_GATHER4
&&
7499 inst
->TexOffsets
[0].File
!= TGSI_FILE_NULL
&&
7500 inst
->TexOffsets
[0].File
!= TGSI_FILE_IMMEDIATE
) {
7501 opcode
= FETCH_OP_GATHER4_O
;
7503 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7504 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7505 encoded in the instruction are ignored. */
7506 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7507 tex
.op
= FETCH_OP_SET_TEXTURE_OFFSETS
;
7508 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7509 tex
.sampler_index_mode
= sampler_index_mode
;
7510 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7511 tex
.resource_index_mode
= sampler_index_mode
;
7513 tex
.src_gpr
= ctx
->file_offset
[inst
->TexOffsets
[0].File
] + inst
->TexOffsets
[0].Index
;
7514 tex
.src_sel_x
= inst
->TexOffsets
[0].SwizzleX
;
7515 tex
.src_sel_y
= inst
->TexOffsets
[0].SwizzleY
;
7516 tex
.src_sel_z
= inst
->TexOffsets
[0].SwizzleZ
;
7524 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7529 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7530 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7531 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7532 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7533 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
7534 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7535 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7537 case FETCH_OP_SAMPLE
:
7538 opcode
= FETCH_OP_SAMPLE_C
;
7540 case FETCH_OP_SAMPLE_L
:
7541 opcode
= FETCH_OP_SAMPLE_C_L
;
7543 case FETCH_OP_SAMPLE_LB
:
7544 opcode
= FETCH_OP_SAMPLE_C_LB
;
7546 case FETCH_OP_SAMPLE_G
:
7547 opcode
= FETCH_OP_SAMPLE_C_G
;
7549 /* Texture gather variants */
7550 case FETCH_OP_GATHER4
:
7551 opcode
= FETCH_OP_GATHER4_C
;
7553 case FETCH_OP_GATHER4_O
:
7554 opcode
= FETCH_OP_GATHER4_C_O
;
7559 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7562 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7563 tex
.sampler_index_mode
= sampler_index_mode
;
7564 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7565 tex
.resource_index_mode
= sampler_index_mode
;
7566 tex
.src_gpr
= src_gpr
;
7567 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7569 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_DDX_FINE
||
7570 inst
->Instruction
.Opcode
== TGSI_OPCODE_DDY_FINE
) {
7571 tex
.inst_mod
= 1; /* per pixel gradient calculation instead of per 2x2 quad */
7574 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
) {
7575 int8_t texture_component_select
= ctx
->literals
[4 * inst
->Src
[1].Register
.Index
+ inst
->Src
[1].Register
.SwizzleX
];
7576 tex
.inst_mod
= texture_component_select
;
7578 if (ctx
->bc
->chip_class
== CAYMAN
) {
7579 /* GATHER4 result order is different from TGSI TG4 */
7580 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 0 : 7;
7581 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 1 : 7;
7582 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 2 : 7;
7583 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7585 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7586 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7587 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7588 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7591 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LODQ
) {
7592 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7593 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7597 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7604 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7605 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7606 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7607 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7611 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7616 } else if (src_loaded
) {
7622 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
7623 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
7624 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
7625 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
7626 tex
.src_rel
= ctx
->src
[0].rel
;
7629 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
7630 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7631 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7632 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7636 tex
.src_sel_w
= 2; /* route Z compare or Lod value into W */
7639 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
7640 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
7641 tex
.coord_type_x
= 1;
7642 tex
.coord_type_y
= 1;
7644 tex
.coord_type_z
= 1;
7645 tex
.coord_type_w
= 1;
7647 tex
.offset_x
= offset_x
;
7648 tex
.offset_y
= offset_y
;
7649 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
&&
7650 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7651 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)) {
7655 tex
.offset_z
= offset_z
;
7658 /* Put the depth for comparison in W.
7659 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7660 * Some instructions expect the depth in Z. */
7661 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7662 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7663 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7664 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
7665 opcode
!= FETCH_OP_SAMPLE_C_L
&&
7666 opcode
!= FETCH_OP_SAMPLE_C_LB
) {
7667 tex
.src_sel_w
= tex
.src_sel_z
;
7670 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
7671 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
7672 if (opcode
== FETCH_OP_SAMPLE_C_L
||
7673 opcode
== FETCH_OP_SAMPLE_C_LB
) {
7674 /* the array index is read from Y */
7675 tex
.coord_type_y
= 0;
7677 /* the array index is read from Z */
7678 tex
.coord_type_z
= 0;
7679 tex
.src_sel_z
= tex
.src_sel_y
;
7681 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7682 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7683 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7684 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
7685 (ctx
->bc
->chip_class
>= EVERGREEN
)))
7686 /* the array index is read from Z */
7687 tex
.coord_type_z
= 0;
7689 /* mask unused source components */
7690 if (opcode
== FETCH_OP_SAMPLE
|| opcode
== FETCH_OP_GATHER4
) {
7691 switch (inst
->Texture
.Texture
) {
7692 case TGSI_TEXTURE_2D
:
7693 case TGSI_TEXTURE_RECT
:
7697 case TGSI_TEXTURE_1D_ARRAY
:
7701 case TGSI_TEXTURE_1D
:
7709 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7713 /* add shadow ambient support - gallium doesn't do it yet */
7717 static int find_hw_atomic_counter(struct r600_shader_ctx
*ctx
,
7718 struct tgsi_full_src_register
*src
)
7722 if (src
->Register
.Indirect
) {
7723 for (i
= 0; i
< ctx
->shader
->nhwatomic_ranges
; i
++) {
7724 if (src
->Indirect
.ArrayID
== ctx
->shader
->atomics
[i
].array_id
)
7725 return ctx
->shader
->atomics
[i
].hw_idx
;
7728 uint32_t index
= src
->Register
.Index
;
7729 for (i
= 0; i
< ctx
->shader
->nhwatomic_ranges
; i
++) {
7730 if (ctx
->shader
->atomics
[i
].buffer_id
!= src
->Dimension
.Index
)
7732 if (index
> ctx
->shader
->atomics
[i
].end
)
7734 if (index
< ctx
->shader
->atomics
[i
].start
)
7736 uint32_t offset
= (index
- ctx
->shader
->atomics
[i
].start
);
7737 return ctx
->shader
->atomics
[i
].hw_idx
+ offset
;
7745 static int tgsi_load_gds(struct r600_shader_ctx
*ctx
)
7747 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7749 struct r600_bytecode_gds gds
;
7751 int uav_index_mode
= 0;
7753 uav_id
= find_hw_atomic_counter(ctx
, &inst
->Src
[0]);
7755 if (inst
->Src
[0].Register
.Indirect
)
7758 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
7759 gds
.op
= FETCH_OP_GDS_READ_RET
;
7760 gds
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7761 gds
.uav_id
= uav_id
;
7762 gds
.uav_index_mode
= uav_index_mode
;
7763 gds
.src_gpr
= ctx
->temp_reg
;
7771 gds
.src_gpr2
= ctx
->temp_reg
;
7772 gds
.alloc_consume
= 1;
7773 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
7777 ctx
->bc
->cf_last
->vpm
= 1;
7781 /* this fixes up 1D arrays properly */
7782 static int load_index_src(struct r600_shader_ctx
*ctx
, int src_index
, int *idx_gpr
)
7784 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7786 struct r600_bytecode_alu alu
;
7787 int temp_reg
= r600_get_temp(ctx
);
7789 for (i
= 0; i
< 4; i
++) {
7790 bool def_val
= true, write_zero
= false;
7791 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7792 alu
.op
= ALU_OP1_MOV
;
7793 alu
.dst
.sel
= temp_reg
;
7796 switch (inst
->Memory
.Texture
) {
7797 case TGSI_TEXTURE_BUFFER
:
7798 case TGSI_TEXTURE_1D
:
7799 if (i
== 1 || i
== 2 || i
== 3) {
7803 case TGSI_TEXTURE_1D_ARRAY
:
7804 if (i
== 1 || i
== 3)
7807 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[src_index
], 1);
7811 case TGSI_TEXTURE_2D
:
7812 if (i
== 2 || i
== 3)
7822 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
7823 alu
.src
[0].value
= 0;
7824 } else if (def_val
) {
7825 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[src_index
], i
);
7831 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7835 *idx_gpr
= temp_reg
;
7839 static int tgsi_load_rat(struct r600_shader_ctx
*ctx
)
7841 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7842 /* have to work out the offset into the RAT immediate return buffer */
7843 struct r600_bytecode_vtx vtx
;
7844 struct r600_bytecode_cf
*cf
;
7847 unsigned format
, num_format
, format_comp
, endian
;
7848 const struct util_format_description
*desc
;
7849 unsigned rat_index_mode
;
7850 unsigned immed_base
;
7852 rat_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7854 immed_base
= R600_IMAGE_IMMED_RESOURCE_OFFSET
;
7855 r
= load_index_src(ctx
, 1, &idx_gpr
);
7860 egcm_load_index_reg(ctx
->bc
, 1, false);
7862 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
7863 cf
= ctx
->bc
->cf_last
;
7865 cf
->rat
.id
= ctx
->shader
->rat_base
+ inst
->Src
[0].Register
.Index
;
7866 cf
->rat
.inst
= V_RAT_INST_NOP_RTN
;
7867 cf
->rat
.index_mode
= rat_index_mode
;
7868 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND
;
7869 cf
->output
.gpr
= ctx
->thread_id_gpr
;
7870 cf
->output
.index_gpr
= idx_gpr
;
7871 cf
->output
.comp_mask
= 0xf;
7872 cf
->output
.burst_count
= 1;
7876 cf
->output
.elem_size
= 0;
7878 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_WAIT_ACK
);
7879 cf
= ctx
->bc
->cf_last
;
7882 desc
= util_format_description(inst
->Memory
.Format
);
7883 r600_vertex_data_type(inst
->Memory
.Format
,
7884 &format
, &num_format
, &format_comp
, &endian
);
7885 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
7886 vtx
.op
= FETCH_OP_VFETCH
;
7887 vtx
.buffer_id
= immed_base
+ inst
->Src
[0].Register
.Index
;
7888 vtx
.buffer_index_mode
= rat_index_mode
;
7889 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
7890 vtx
.src_gpr
= ctx
->thread_id_gpr
;
7892 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7893 vtx
.dst_sel_x
= desc
->swizzle
[0];
7894 vtx
.dst_sel_y
= desc
->swizzle
[1];
7895 vtx
.dst_sel_z
= desc
->swizzle
[2];
7896 vtx
.dst_sel_w
= desc
->swizzle
[3];
7897 vtx
.srf_mode_all
= 1;
7898 vtx
.data_format
= format
;
7899 vtx
.num_format_all
= num_format
;
7900 vtx
.format_comp_all
= format_comp
;
7901 vtx
.endian
= endian
;
7903 vtx
.mega_fetch_count
= 3;
7904 r
= r600_bytecode_add_vtx_tc(ctx
->bc
, &vtx
);
7907 cf
= ctx
->bc
->cf_last
;
7912 static int tgsi_load(struct r600_shader_ctx
*ctx
)
7914 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7915 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
7916 return tgsi_load_rat(ctx
);
7917 if (inst
->Src
[0].Register
.File
== TGSI_FILE_HW_ATOMIC
)
7918 return tgsi_load_gds(ctx
);
7922 static int tgsi_store_rat(struct r600_shader_ctx
*ctx
)
7924 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7925 struct r600_bytecode_cf
*cf
;
7926 bool src_requires_loading
= false;
7927 int val_gpr
, idx_gpr
;
7929 unsigned rat_index_mode
;
7931 rat_index_mode
= inst
->Dst
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7933 r
= load_index_src(ctx
, 0, &idx_gpr
);
7937 if (inst
->Src
[1].Register
.File
!= TGSI_FILE_TEMPORARY
)
7938 src_requires_loading
= true;
7940 if (src_requires_loading
) {
7941 struct r600_bytecode_alu alu
;
7942 for (i
= 0; i
< 4; i
++) {
7943 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7944 alu
.op
= ALU_OP1_MOV
;
7945 alu
.dst
.sel
= ctx
->temp_reg
;
7948 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
7952 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7956 val_gpr
= ctx
->temp_reg
;
7958 val_gpr
= tgsi_tex_get_src_gpr(ctx
, 1);
7960 egcm_load_index_reg(ctx
->bc
, 1, false);
7962 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
7963 cf
= ctx
->bc
->cf_last
;
7965 cf
->rat
.id
= ctx
->shader
->rat_base
+ inst
->Dst
[0].Register
.Index
;
7966 cf
->rat
.inst
= V_RAT_INST_STORE_TYPED
;
7967 cf
->rat
.index_mode
= rat_index_mode
;
7968 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
7969 cf
->output
.gpr
= val_gpr
;
7970 cf
->output
.index_gpr
= idx_gpr
;
7971 cf
->output
.comp_mask
= 0xf;
7972 cf
->output
.burst_count
= 1;
7975 cf
->output
.elem_size
= 0;
7979 static int tgsi_store(struct r600_shader_ctx
*ctx
)
7981 return tgsi_store_rat(ctx
);
7984 static int tgsi_atomic_op_rat(struct r600_shader_ctx
*ctx
)
7986 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7987 /* have to work out the offset into the RAT immediate return buffer */
7988 struct r600_bytecode_alu alu
;
7989 struct r600_bytecode_vtx vtx
;
7990 struct r600_bytecode_cf
*cf
;
7993 unsigned format
, num_format
, format_comp
, endian
;
7994 const struct util_format_description
*desc
;
7995 unsigned rat_index_mode
;
7996 unsigned immed_base
;
7998 immed_base
= R600_IMAGE_IMMED_RESOURCE_OFFSET
;
8000 assert (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
);
8001 rat_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8003 r
= load_index_src(ctx
, 1, &idx_gpr
);
8007 if (ctx
->inst_info
->op
== V_RAT_INST_CMPXCHG_INT_RTN
) {
8008 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8009 alu
.op
= ALU_OP1_MOV
;
8010 alu
.dst
.sel
= ctx
->thread_id_gpr
;
8013 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], 0);
8015 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8019 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8020 alu
.op
= ALU_OP1_MOV
;
8021 alu
.dst
.sel
= ctx
->thread_id_gpr
;
8024 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
8026 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8030 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8031 alu
.op
= ALU_OP1_MOV
;
8032 alu
.dst
.sel
= ctx
->thread_id_gpr
;
8035 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
8037 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8043 egcm_load_index_reg(ctx
->bc
, 1, false);
8044 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
8045 cf
= ctx
->bc
->cf_last
;
8047 cf
->rat
.id
= ctx
->shader
->rat_base
+ inst
->Src
[0].Register
.Index
;
8048 cf
->rat
.inst
= ctx
->inst_info
->op
;
8049 cf
->rat
.index_mode
= rat_index_mode
;
8050 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND
;
8051 cf
->output
.gpr
= ctx
->thread_id_gpr
;
8052 cf
->output
.index_gpr
= idx_gpr
;
8053 cf
->output
.comp_mask
= 0xf;
8054 cf
->output
.burst_count
= 1;
8058 cf
->output
.elem_size
= 0;
8059 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_WAIT_ACK
);
8060 cf
= ctx
->bc
->cf_last
;
8064 desc
= util_format_description(inst
->Memory
.Format
);
8065 r600_vertex_data_type(inst
->Memory
.Format
,
8066 &format
, &num_format
, &format_comp
, &endian
);
8067 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
8068 vtx
.op
= FETCH_OP_VFETCH
;
8069 vtx
.buffer_id
= immed_base
+ inst
->Src
[0].Register
.Index
;
8070 vtx
.buffer_index_mode
= rat_index_mode
;
8071 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
8072 vtx
.src_gpr
= ctx
->thread_id_gpr
;
8074 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8075 vtx
.dst_sel_x
= desc
->swizzle
[0];
8079 vtx
.use_const_fields
= 0;
8080 vtx
.srf_mode_all
= 1;
8081 vtx
.data_format
= format
;
8082 vtx
.num_format_all
= num_format
;
8083 vtx
.format_comp_all
= format_comp
;
8084 vtx
.endian
= endian
;
8086 vtx
.mega_fetch_count
= 0xf;
8087 r
= r600_bytecode_add_vtx_tc(ctx
->bc
, &vtx
);
8090 cf
= ctx
->bc
->cf_last
;
8096 static int get_gds_op(int opcode
)
8099 case TGSI_OPCODE_ATOMUADD
:
8100 return FETCH_OP_GDS_ADD_RET
;
8101 case TGSI_OPCODE_ATOMAND
:
8102 return FETCH_OP_GDS_AND_RET
;
8103 case TGSI_OPCODE_ATOMOR
:
8104 return FETCH_OP_GDS_OR_RET
;
8105 case TGSI_OPCODE_ATOMXOR
:
8106 return FETCH_OP_GDS_XOR_RET
;
8107 case TGSI_OPCODE_ATOMUMIN
:
8108 return FETCH_OP_GDS_MIN_UINT_RET
;
8109 case TGSI_OPCODE_ATOMUMAX
:
8110 return FETCH_OP_GDS_MAX_UINT_RET
;
8111 case TGSI_OPCODE_ATOMXCHG
:
8112 return FETCH_OP_GDS_XCHG_RET
;
8113 case TGSI_OPCODE_ATOMCAS
:
8114 return FETCH_OP_GDS_CMP_XCHG_RET
;
8120 static int tgsi_atomic_op_gds(struct r600_shader_ctx
*ctx
)
8122 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8123 struct r600_bytecode_gds gds
;
8124 struct r600_bytecode_alu alu
;
8125 int gds_op
= get_gds_op(inst
->Instruction
.Opcode
);
8128 int uav_index_mode
= 0;
8131 fprintf(stderr
, "unknown GDS op for opcode %d\n", inst
->Instruction
.Opcode
);
8135 uav_id
= find_hw_atomic_counter(ctx
, &inst
->Src
[0]);
8137 if (inst
->Src
[0].Register
.Indirect
)
8140 if (inst
->Src
[2].Register
.File
== TGSI_FILE_IMMEDIATE
) {
8141 int value
= (ctx
->literals
[4 * inst
->Src
[2].Register
.Index
+ inst
->Src
[2].Register
.SwizzleX
]);
8142 int abs_value
= abs(value
);
8143 if (abs_value
!= value
&& gds_op
== FETCH_OP_GDS_ADD_RET
)
8144 gds_op
= FETCH_OP_GDS_SUB_RET
;
8145 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8146 alu
.op
= ALU_OP1_MOV
;
8147 alu
.dst
.sel
= ctx
->temp_reg
;
8149 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
8150 alu
.src
[0].value
= abs_value
;
8153 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8157 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8158 alu
.op
= ALU_OP1_MOV
;
8159 alu
.dst
.sel
= ctx
->temp_reg
;
8161 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
8164 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8169 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
8171 gds
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8172 gds
.uav_id
= uav_id
;
8173 gds
.uav_index_mode
= uav_index_mode
;
8174 gds
.src_gpr
= ctx
->temp_reg
;
8175 gds
.src_gpr2
= ctx
->temp_reg
;
8183 gds
.alloc_consume
= 1;
8184 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
8187 ctx
->bc
->cf_last
->vpm
= 1;
8191 static int tgsi_atomic_op(struct r600_shader_ctx
*ctx
)
8193 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8194 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
8195 return tgsi_atomic_op_rat(ctx
);
8196 if (inst
->Src
[0].Register
.File
== TGSI_FILE_HW_ATOMIC
)
8197 return tgsi_atomic_op_gds(ctx
);
8201 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
8203 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8204 struct r600_bytecode_alu alu
;
8205 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8206 unsigned i
, temp_regs
[2];
8209 /* optimize if it's just an equal balance */
8210 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
8211 for (i
= 0; i
< lasti
+ 1; i
++) {
8212 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8215 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8216 alu
.op
= ALU_OP2_ADD
;
8217 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
8218 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8220 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8225 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8233 for (i
= 0; i
< lasti
+ 1; i
++) {
8234 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8237 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8238 alu
.op
= ALU_OP2_ADD
;
8239 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8240 alu
.src
[0].chan
= 0;
8241 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
8242 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
8243 alu
.dst
.sel
= ctx
->temp_reg
;
8249 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8254 /* (1 - src0) * src2 */
8255 for (i
= 0; i
< lasti
+ 1; i
++) {
8256 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8259 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8260 alu
.op
= ALU_OP2_MUL
;
8261 alu
.src
[0].sel
= ctx
->temp_reg
;
8262 alu
.src
[0].chan
= i
;
8263 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8264 alu
.dst
.sel
= ctx
->temp_reg
;
8270 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8275 /* src0 * src1 + (1 - src0) * src2 */
8276 if (ctx
->src
[0].abs
)
8277 temp_regs
[0] = r600_get_temp(ctx
);
8280 if (ctx
->src
[1].abs
)
8281 temp_regs
[1] = r600_get_temp(ctx
);
8285 for (i
= 0; i
< lasti
+ 1; i
++) {
8286 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8289 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8290 alu
.op
= ALU_OP3_MULADD
;
8292 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
8295 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[1], &ctx
->src
[1]);
8298 alu
.src
[2].sel
= ctx
->temp_reg
;
8299 alu
.src
[2].chan
= i
;
8301 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8306 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8313 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
8315 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8316 struct r600_bytecode_alu alu
;
8318 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8322 if (ctx
->src
[0].abs
&& ctx
->src
[0].neg
) {
8324 ctx
->src
[0].abs
= 0;
8325 ctx
->src
[0].neg
= 0;
8330 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
8332 if (ctx
->src
[j
].abs
)
8333 temp_regs
[j
] = r600_get_temp(ctx
);
8336 for (i
= 0; i
< lasti
+ 1; i
++) {
8337 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8340 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8342 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
8345 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[2], i
, &alu
.src
[1], &ctx
->src
[2]);
8348 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[2], &ctx
->src
[1]);
8351 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8357 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8364 static int tgsi_ucmp(struct r600_shader_ctx
*ctx
)
8366 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8367 struct r600_bytecode_alu alu
;
8369 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8371 for (i
= 0; i
< lasti
+ 1; i
++) {
8372 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8375 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8376 alu
.op
= ALU_OP3_CNDE_INT
;
8377 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8378 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8379 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
8380 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8386 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8393 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
8395 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8396 struct r600_bytecode_alu alu
;
8400 /* result.x = 2^floor(src); */
8401 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
8402 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8404 alu
.op
= ALU_OP1_FLOOR
;
8405 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8407 alu
.dst
.sel
= ctx
->temp_reg
;
8411 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8415 if (ctx
->bc
->chip_class
== CAYMAN
) {
8416 for (i
= 0; i
< 3; i
++) {
8417 alu
.op
= ALU_OP1_EXP_IEEE
;
8418 alu
.src
[0].sel
= ctx
->temp_reg
;
8419 alu
.src
[0].chan
= 0;
8421 alu
.dst
.sel
= ctx
->temp_reg
;
8423 alu
.dst
.write
= i
== 0;
8425 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8430 alu
.op
= ALU_OP1_EXP_IEEE
;
8431 alu
.src
[0].sel
= ctx
->temp_reg
;
8432 alu
.src
[0].chan
= 0;
8434 alu
.dst
.sel
= ctx
->temp_reg
;
8438 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8444 /* result.y = tmp - floor(tmp); */
8445 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
8446 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8448 alu
.op
= ALU_OP1_FRACT
;
8449 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8451 alu
.dst
.sel
= ctx
->temp_reg
;
8453 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8462 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8467 /* result.z = RoughApprox2ToX(tmp);*/
8468 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
8469 if (ctx
->bc
->chip_class
== CAYMAN
) {
8470 for (i
= 0; i
< 3; i
++) {
8471 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8472 alu
.op
= ALU_OP1_EXP_IEEE
;
8473 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8475 alu
.dst
.sel
= ctx
->temp_reg
;
8482 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8487 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8488 alu
.op
= ALU_OP1_EXP_IEEE
;
8489 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8491 alu
.dst
.sel
= ctx
->temp_reg
;
8497 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8503 /* result.w = 1.0;*/
8504 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
8505 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8507 alu
.op
= ALU_OP1_MOV
;
8508 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8509 alu
.src
[0].chan
= 0;
8511 alu
.dst
.sel
= ctx
->temp_reg
;
8515 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8519 return tgsi_helper_copy(ctx
, inst
);
8522 static int tgsi_log(struct r600_shader_ctx
*ctx
)
8524 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8525 struct r600_bytecode_alu alu
;
8529 /* result.x = floor(log2(|src|)); */
8530 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
8531 if (ctx
->bc
->chip_class
== CAYMAN
) {
8532 for (i
= 0; i
< 3; i
++) {
8533 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8535 alu
.op
= ALU_OP1_LOG_IEEE
;
8536 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8537 r600_bytecode_src_set_abs(&alu
.src
[0]);
8539 alu
.dst
.sel
= ctx
->temp_reg
;
8545 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8551 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8553 alu
.op
= ALU_OP1_LOG_IEEE
;
8554 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8555 r600_bytecode_src_set_abs(&alu
.src
[0]);
8557 alu
.dst
.sel
= ctx
->temp_reg
;
8561 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8566 alu
.op
= ALU_OP1_FLOOR
;
8567 alu
.src
[0].sel
= ctx
->temp_reg
;
8568 alu
.src
[0].chan
= 0;
8570 alu
.dst
.sel
= ctx
->temp_reg
;
8575 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8580 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8581 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
8583 if (ctx
->bc
->chip_class
== CAYMAN
) {
8584 for (i
= 0; i
< 3; i
++) {
8585 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8587 alu
.op
= ALU_OP1_LOG_IEEE
;
8588 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8589 r600_bytecode_src_set_abs(&alu
.src
[0]);
8591 alu
.dst
.sel
= ctx
->temp_reg
;
8598 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8603 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8605 alu
.op
= ALU_OP1_LOG_IEEE
;
8606 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8607 r600_bytecode_src_set_abs(&alu
.src
[0]);
8609 alu
.dst
.sel
= ctx
->temp_reg
;
8614 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8619 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8621 alu
.op
= ALU_OP1_FLOOR
;
8622 alu
.src
[0].sel
= ctx
->temp_reg
;
8623 alu
.src
[0].chan
= 1;
8625 alu
.dst
.sel
= ctx
->temp_reg
;
8630 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8634 if (ctx
->bc
->chip_class
== CAYMAN
) {
8635 for (i
= 0; i
< 3; i
++) {
8636 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8637 alu
.op
= ALU_OP1_EXP_IEEE
;
8638 alu
.src
[0].sel
= ctx
->temp_reg
;
8639 alu
.src
[0].chan
= 1;
8641 alu
.dst
.sel
= ctx
->temp_reg
;
8648 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8653 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8654 alu
.op
= ALU_OP1_EXP_IEEE
;
8655 alu
.src
[0].sel
= ctx
->temp_reg
;
8656 alu
.src
[0].chan
= 1;
8658 alu
.dst
.sel
= ctx
->temp_reg
;
8663 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8668 if (ctx
->bc
->chip_class
== CAYMAN
) {
8669 for (i
= 0; i
< 3; i
++) {
8670 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8671 alu
.op
= ALU_OP1_RECIP_IEEE
;
8672 alu
.src
[0].sel
= ctx
->temp_reg
;
8673 alu
.src
[0].chan
= 1;
8675 alu
.dst
.sel
= ctx
->temp_reg
;
8682 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8687 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8688 alu
.op
= ALU_OP1_RECIP_IEEE
;
8689 alu
.src
[0].sel
= ctx
->temp_reg
;
8690 alu
.src
[0].chan
= 1;
8692 alu
.dst
.sel
= ctx
->temp_reg
;
8697 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8702 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8704 alu
.op
= ALU_OP2_MUL
;
8706 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8707 r600_bytecode_src_set_abs(&alu
.src
[0]);
8709 alu
.src
[1].sel
= ctx
->temp_reg
;
8710 alu
.src
[1].chan
= 1;
8712 alu
.dst
.sel
= ctx
->temp_reg
;
8717 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8722 /* result.z = log2(|src|);*/
8723 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
8724 if (ctx
->bc
->chip_class
== CAYMAN
) {
8725 for (i
= 0; i
< 3; i
++) {
8726 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8728 alu
.op
= ALU_OP1_LOG_IEEE
;
8729 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8730 r600_bytecode_src_set_abs(&alu
.src
[0]);
8732 alu
.dst
.sel
= ctx
->temp_reg
;
8739 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8744 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8746 alu
.op
= ALU_OP1_LOG_IEEE
;
8747 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8748 r600_bytecode_src_set_abs(&alu
.src
[0]);
8750 alu
.dst
.sel
= ctx
->temp_reg
;
8755 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8761 /* result.w = 1.0; */
8762 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
8763 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8765 alu
.op
= ALU_OP1_MOV
;
8766 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8767 alu
.src
[0].chan
= 0;
8769 alu
.dst
.sel
= ctx
->temp_reg
;
8774 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8779 return tgsi_helper_copy(ctx
, inst
);
8782 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
8784 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8785 struct r600_bytecode_alu alu
;
8787 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8788 unsigned reg
= get_address_file_reg(ctx
, inst
->Dst
[0].Register
.Index
);
8790 assert(inst
->Dst
[0].Register
.Index
< 3);
8791 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8793 switch (inst
->Instruction
.Opcode
) {
8794 case TGSI_OPCODE_ARL
:
8795 alu
.op
= ALU_OP1_FLT_TO_INT_FLOOR
;
8797 case TGSI_OPCODE_ARR
:
8798 alu
.op
= ALU_OP1_FLT_TO_INT
;
8800 case TGSI_OPCODE_UARL
:
8801 alu
.op
= ALU_OP1_MOV
;
8808 for (i
= 0; i
<= lasti
; ++i
) {
8809 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8811 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8812 alu
.last
= i
== lasti
;
8816 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8821 if (inst
->Dst
[0].Register
.Index
> 0)
8822 ctx
->bc
->index_loaded
[inst
->Dst
[0].Register
.Index
- 1] = 0;
8824 ctx
->bc
->ar_loaded
= 0;
8828 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
8830 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8831 struct r600_bytecode_alu alu
;
8833 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8835 switch (inst
->Instruction
.Opcode
) {
8836 case TGSI_OPCODE_ARL
:
8837 memset(&alu
, 0, sizeof(alu
));
8838 alu
.op
= ALU_OP1_FLOOR
;
8839 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8841 for (i
= 0; i
<= lasti
; ++i
) {
8842 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8844 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8845 alu
.last
= i
== lasti
;
8846 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8851 memset(&alu
, 0, sizeof(alu
));
8852 alu
.op
= ALU_OP1_FLT_TO_INT
;
8853 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
8854 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8856 /* FLT_TO_INT is trans-only on r600/r700 */
8858 for (i
= 0; i
<= lasti
; ++i
) {
8860 alu
.src
[0].chan
= i
;
8861 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8865 case TGSI_OPCODE_ARR
:
8866 memset(&alu
, 0, sizeof(alu
));
8867 alu
.op
= ALU_OP1_FLT_TO_INT
;
8868 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8870 /* FLT_TO_INT is trans-only on r600/r700 */
8872 for (i
= 0; i
<= lasti
; ++i
) {
8873 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8875 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8876 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8881 case TGSI_OPCODE_UARL
:
8882 memset(&alu
, 0, sizeof(alu
));
8883 alu
.op
= ALU_OP1_MOV
;
8884 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8886 for (i
= 0; i
<= lasti
; ++i
) {
8887 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8889 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8890 alu
.last
= i
== lasti
;
8891 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8901 ctx
->bc
->ar_loaded
= 0;
8905 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
8907 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8908 struct r600_bytecode_alu alu
;
8911 for (i
= 0; i
< 4; i
++) {
8912 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8914 alu
.op
= ALU_OP2_MUL
;
8915 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8917 if (i
== 0 || i
== 3) {
8918 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8920 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8923 if (i
== 0 || i
== 2) {
8924 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
8926 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
8930 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8937 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
, int alu_type
)
8939 struct r600_bytecode_alu alu
;
8942 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8944 alu
.execute_mask
= 1;
8945 alu
.update_pred
= 1;
8947 alu
.dst
.sel
= ctx
->temp_reg
;
8951 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8952 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
8953 alu
.src
[1].chan
= 0;
8957 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, alu_type
);
8963 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
8965 unsigned force_pop
= ctx
->bc
->force_add_cf
;
8969 if (ctx
->bc
->cf_last
) {
8970 if (ctx
->bc
->cf_last
->op
== CF_OP_ALU
)
8972 else if (ctx
->bc
->cf_last
->op
== CF_OP_ALU_POP_AFTER
)
8977 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP_AFTER
;
8978 ctx
->bc
->force_add_cf
= 1;
8979 } else if (alu_pop
== 2) {
8980 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP2_AFTER
;
8981 ctx
->bc
->force_add_cf
= 1;
8988 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
8989 ctx
->bc
->cf_last
->pop_count
= pops
;
8990 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8996 static inline void callstack_update_max_depth(struct r600_shader_ctx
*ctx
,
8999 struct r600_stack_info
*stack
= &ctx
->bc
->stack
;
9000 unsigned elements
, entries
;
9002 unsigned entry_size
= stack
->entry_size
;
9004 elements
= (stack
->loop
+ stack
->push_wqm
) * entry_size
;
9005 elements
+= stack
->push
;
9007 switch (ctx
->bc
->chip_class
) {
9010 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9011 * the stack must be reserved to hold the current active/continue
9013 if (reason
== FC_PUSH_VPM
) {
9019 /* r9xx: any stack operation on empty stack consumes 2 additional
9024 /* FIXME: do the two elements added above cover the cases for the
9028 /* r8xx+: 2 extra elements are not always required, but one extra
9029 * element must be added for each of the following cases:
9030 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9032 * (Currently we don't use ALU_ELSE_AFTER.)
9033 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9034 * PUSH instruction executed.
9036 * NOTE: it seems we also need to reserve additional element in some
9037 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9038 * then STACK_SIZE should be 2 instead of 1 */
9039 if (reason
== FC_PUSH_VPM
) {
9049 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9050 * for all chips, so we use 4 in the final formula, not the real entry_size
9054 entries
= (elements
+ (entry_size
- 1)) / entry_size
;
9056 if (entries
> stack
->max_entries
)
9057 stack
->max_entries
= entries
;
9060 static inline void callstack_pop(struct r600_shader_ctx
*ctx
, unsigned reason
)
9064 --ctx
->bc
->stack
.push
;
9065 assert(ctx
->bc
->stack
.push
>= 0);
9068 --ctx
->bc
->stack
.push_wqm
;
9069 assert(ctx
->bc
->stack
.push_wqm
>= 0);
9072 --ctx
->bc
->stack
.loop
;
9073 assert(ctx
->bc
->stack
.loop
>= 0);
9081 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
)
9085 ++ctx
->bc
->stack
.push
;
9088 ++ctx
->bc
->stack
.push_wqm
;
9090 ++ctx
->bc
->stack
.loop
;
9096 callstack_update_max_depth(ctx
, reason
);
9099 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
9101 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
9103 sp
->mid
= realloc((void *)sp
->mid
,
9104 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
9105 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
9109 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
9111 assert(ctx
->bc
->fc_sp
< ARRAY_SIZE(ctx
->bc
->fc_stack
));
9112 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
9113 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
9117 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
9119 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1];
9129 static int emit_return(struct r600_shader_ctx
*ctx
)
9131 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_RETURN
));
9135 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
9138 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
));
9139 ctx
->bc
->cf_last
->pop_count
= pops
;
9140 /* XXX work out offset */
9144 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
9149 static void emit_testflag(struct r600_shader_ctx
*ctx
)
9154 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
9157 emit_jump_to_offset(ctx
, 1, 4);
9158 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
9159 pops(ctx
, ifidx
+ 1);
9163 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
9167 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
9168 ctx
->bc
->cf_last
->pop_count
= 1;
9170 fc_set_mid(ctx
, fc_sp
);
9176 static int emit_if(struct r600_shader_ctx
*ctx
, int opcode
)
9178 int alu_type
= CF_OP_ALU_PUSH_BEFORE
;
9180 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9181 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9182 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9183 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9184 if (ctx
->bc
->chip_class
== CAYMAN
&& ctx
->bc
->stack
.loop
> 1) {
9185 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_PUSH
);
9186 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9187 alu_type
= CF_OP_ALU
;
9190 emit_logic_pred(ctx
, opcode
, alu_type
);
9192 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
9194 fc_pushlevel(ctx
, FC_IF
);
9196 callstack_push(ctx
, FC_PUSH_VPM
);
9200 static int tgsi_if(struct r600_shader_ctx
*ctx
)
9202 return emit_if(ctx
, ALU_OP2_PRED_SETNE
);
9205 static int tgsi_uif(struct r600_shader_ctx
*ctx
)
9207 return emit_if(ctx
, ALU_OP2_PRED_SETNE_INT
);
9210 static int tgsi_else(struct r600_shader_ctx
*ctx
)
9212 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_ELSE
);
9213 ctx
->bc
->cf_last
->pop_count
= 1;
9215 fc_set_mid(ctx
, ctx
->bc
->fc_sp
- 1);
9216 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
9220 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
9223 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_IF
) {
9224 R600_ERR("if/endif unbalanced in shader\n");
9228 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
== NULL
) {
9229 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9230 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->pop_count
= 1;
9232 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9236 callstack_pop(ctx
, FC_PUSH_VPM
);
9240 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
9242 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9243 * limited to 4096 iterations, like the other LOOP_* instructions. */
9244 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_START_DX10
);
9246 fc_pushlevel(ctx
, FC_LOOP
);
9248 /* check stack depth */
9249 callstack_push(ctx
, FC_LOOP
);
9253 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
9257 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_END
);
9259 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_LOOP
) {
9260 R600_ERR("loop/endloop in shader code are not paired.\n");
9264 /* fixup loop pointers - from r600isa
9265 LOOP END points to CF after LOOP START,
9266 LOOP START point to CF after LOOP END
9267 BRK/CONT point to LOOP END CF
9269 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->id
+ 2;
9271 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9273 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].num_mid
; i
++) {
9274 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
9276 /* XXX add LOOPRET support */
9278 callstack_pop(ctx
, FC_LOOP
);
9282 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
9286 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
9288 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
- 1].type
)
9293 R600_ERR("Break not inside loop/endloop pair\n");
9297 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
9299 fc_set_mid(ctx
, fscp
- 1);
9304 static int tgsi_gs_emit(struct r600_shader_ctx
*ctx
)
9306 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9307 int stream
= ctx
->literals
[inst
->Src
[0].Register
.Index
* 4 + inst
->Src
[0].Register
.SwizzleX
];
9310 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
9311 emit_gs_ring_writes(ctx
, ctx
->gs_stream_output_info
, stream
, TRUE
);
9313 r
= r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
9315 ctx
->bc
->cf_last
->count
= stream
; // Count field for CUT/EMIT_VERTEX indicates which stream
9316 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
9317 return emit_inc_ring_offset(ctx
, stream
, TRUE
);
9322 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
9324 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9325 struct r600_bytecode_alu alu
;
9327 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9330 for (i
= 0; i
< lasti
+ 1; i
++) {
9331 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9334 if (ctx
->bc
->chip_class
== CAYMAN
) {
9335 for (j
= 0 ; j
< 4; j
++) {
9336 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9338 alu
.op
= ALU_OP2_MULLO_UINT
;
9339 for (k
= 0; k
< inst
->Instruction
.NumSrcRegs
; k
++) {
9340 r600_bytecode_src(&alu
.src
[k
], &ctx
->src
[k
], i
);
9343 alu
.dst
.sel
= ctx
->temp_reg
;
9344 alu
.dst
.write
= (j
== i
);
9347 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9352 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9355 alu
.dst
.sel
= ctx
->temp_reg
;
9358 alu
.op
= ALU_OP2_MULLO_UINT
;
9359 for (j
= 0; j
< 2; j
++) {
9360 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
9364 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9371 for (i
= 0; i
< lasti
+ 1; i
++) {
9372 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9375 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9376 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9378 alu
.op
= ALU_OP2_ADD_INT
;
9380 alu
.src
[0].sel
= ctx
->temp_reg
;
9381 alu
.src
[0].chan
= i
;
9383 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
9387 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9394 static int tgsi_pk2h(struct r600_shader_ctx
*ctx
)
9396 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9397 struct r600_bytecode_alu alu
;
9399 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9401 /* temp.xy = f32_to_f16(src) */
9402 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9403 alu
.op
= ALU_OP1_FLT32_TO_FLT16
;
9405 alu
.dst
.sel
= ctx
->temp_reg
;
9407 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9408 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9412 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
9414 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9418 /* dst.x = temp.y * 0x10000 + temp.x */
9419 for (i
= 0; i
< lasti
+ 1; i
++) {
9420 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9423 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9424 alu
.op
= ALU_OP3_MULADD_UINT24
;
9426 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9427 alu
.last
= i
== lasti
;
9428 alu
.src
[0].sel
= ctx
->temp_reg
;
9429 alu
.src
[0].chan
= 1;
9430 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9431 alu
.src
[1].value
= 0x10000;
9432 alu
.src
[2].sel
= ctx
->temp_reg
;
9433 alu
.src
[2].chan
= 0;
9434 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9442 static int tgsi_up2h(struct r600_shader_ctx
*ctx
)
9444 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9445 struct r600_bytecode_alu alu
;
9447 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9449 /* temp.x = src.x */
9450 /* note: no need to mask out the high bits */
9451 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9452 alu
.op
= ALU_OP1_MOV
;
9454 alu
.dst
.sel
= ctx
->temp_reg
;
9456 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9457 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9461 /* temp.y = src.x >> 16 */
9462 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9463 alu
.op
= ALU_OP2_LSHR_INT
;
9465 alu
.dst
.sel
= ctx
->temp_reg
;
9467 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9468 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9469 alu
.src
[1].value
= 16;
9471 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9475 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9476 for (i
= 0; i
< lasti
+ 1; i
++) {
9477 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9479 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9480 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9481 alu
.op
= ALU_OP1_FLT16_TO_FLT32
;
9482 alu
.src
[0].sel
= ctx
->temp_reg
;
9483 alu
.src
[0].chan
= i
% 2;
9484 alu
.last
= i
== lasti
;
9485 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9493 static int tgsi_bfe(struct r600_shader_ctx
*ctx
)
9495 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9496 struct r600_bytecode_alu alu
;
9497 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9504 for (i
= 0; i
< lasti
+ 1; i
++) {
9505 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9506 alu
.op
= ALU_OP2_SETGE_INT
;
9507 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], i
);
9508 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9509 alu
.src
[1].value
= 32;
9510 alu
.dst
.sel
= ctx
->temp_reg
;
9515 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9520 for (i
= 0; i
< lasti
+ 1; i
++) {
9521 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9522 alu
.op
= ALU_OP3_CNDE_INT
;
9524 alu
.src
[0].sel
= ctx
->temp_reg
;
9525 alu
.src
[1].chan
= i
;
9527 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9528 alu
.src
[1].sel
= alu
.dst
.sel
;
9529 alu
.src
[1].chan
= i
;
9530 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
9534 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9542 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
9543 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
9544 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9545 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9547 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
9549 [TGSI_OPCODE_RSQ
] = { ALU_OP0_NOP
, tgsi_rsq
},
9550 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9551 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9552 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9553 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9554 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9555 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9556 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9557 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
9558 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN_DX10
, tgsi_op2
},
9559 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX_DX10
, tgsi_op2
},
9560 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9561 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9562 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9563 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9564 [TGSI_OPCODE_FMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9565 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
9566 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
9567 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9568 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9569 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9570 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9571 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9572 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9573 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
9574 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
9575 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
9576 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
9577 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9578 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
9579 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9580 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
9581 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
9582 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9583 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9584 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9585 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9586 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9587 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9588 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9589 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9590 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9591 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9592 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9593 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
9594 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9595 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9596 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9597 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9598 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9599 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9600 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9601 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9602 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9603 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9604 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9605 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9606 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
9607 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9608 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9609 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9610 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9611 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9612 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
9613 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9614 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9615 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9616 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9617 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9618 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9619 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9620 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9621 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9622 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9623 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9624 [TGSI_OPCODE_DDX_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9625 [TGSI_OPCODE_DDY_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9626 [81] = { ALU_OP0_NOP
, tgsi_unsupported
},
9627 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
9628 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9629 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
9630 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9631 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9632 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2_trans
},
9633 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9634 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9635 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9636 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9637 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9638 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
9639 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9640 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9641 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9642 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9643 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9644 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9645 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9646 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9647 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9648 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9649 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9650 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9651 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9652 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9653 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9654 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9655 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9656 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9657 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9658 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
9659 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9660 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
9661 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9662 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9663 [TGSI_OPCODE_DFMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9664 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2_trans
},
9665 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9666 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9667 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9668 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9669 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9670 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2_trans
},
9671 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9672 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2_trans
},
9673 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
9674 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9675 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9676 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9677 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9678 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9679 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9680 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
9681 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9682 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9683 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2_trans
},
9684 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9685 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2_swap
},
9686 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9687 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9688 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9689 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9690 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9691 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9692 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9693 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9694 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9695 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9696 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9697 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9698 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9699 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9700 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9701 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9702 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_r600_arl
},
9703 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9704 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9705 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9706 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9707 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9708 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
9709 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
9710 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
9711 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9712 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9713 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9714 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9715 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9716 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9717 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9718 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9719 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9720 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9721 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9722 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9723 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9724 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9725 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
9726 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
9727 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_unsupported
},
9728 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_unsupported
},
9729 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_unsupported
},
9730 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_unsupported
},
9731 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9732 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_unsupported
},
9733 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_unsupported
},
9734 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_unsupported
},
9735 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_unsupported
},
9736 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_unsupported
},
9737 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9738 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9739 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9740 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9743 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
9744 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9745 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9746 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9747 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
9748 [TGSI_OPCODE_RSQ
] = { ALU_OP0_NOP
, tgsi_rsq
},
9749 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9750 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9751 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9752 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9753 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9754 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9755 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9756 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN_DX10
, tgsi_op2
},
9757 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX_DX10
, tgsi_op2
},
9758 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9759 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9760 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9761 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9762 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
9763 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
9764 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
9765 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9766 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9767 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9768 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9769 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9770 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9771 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
9772 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
9773 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
9774 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
9775 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9776 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
9777 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9778 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
9779 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
9780 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9781 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9782 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9783 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
9784 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9785 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9786 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9787 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9788 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9789 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9790 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9791 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
9792 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9793 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9794 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9795 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9796 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9797 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9798 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
9799 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9800 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9801 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9802 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9803 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9804 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9805 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9806 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9807 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9808 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9809 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9810 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
9811 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9812 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9813 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9814 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9815 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9816 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9817 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9818 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9819 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9820 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9821 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9822 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9823 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9824 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
9825 [83] = { ALU_OP0_NOP
, tgsi_unsupported
},
9826 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9827 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
9828 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9829 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9830 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
9831 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9832 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9833 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9834 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9835 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9836 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
9837 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9838 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9839 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9840 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9841 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9842 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9843 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9844 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9845 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9846 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9847 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9848 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9849 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9850 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9851 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9852 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9853 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9854 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9855 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
9856 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
9857 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9858 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
9859 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9860 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9861 /* Refer below for TGSI_OPCODE_DFMA */
9862 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_f2i
},
9863 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9864 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9865 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9866 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9867 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9868 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
9869 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9870 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_f2i
},
9871 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
9872 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9873 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9874 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9875 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9876 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9877 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9878 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
9879 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9880 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9881 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
9882 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9883 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
9884 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9885 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9886 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9887 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9888 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9889 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9890 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9891 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9892 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9893 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9894 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9895 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9896 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9897 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9898 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9899 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9900 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
9901 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9902 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9903 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9904 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_load
},
9905 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_store
},
9906 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
9907 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
9908 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
9909 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
9910 [TGSI_OPCODE_ATOMUADD
] = { V_RAT_INST_ADD_RTN
, tgsi_atomic_op
},
9911 [TGSI_OPCODE_ATOMXCHG
] = { V_RAT_INST_XCHG_RTN
, tgsi_atomic_op
},
9912 [TGSI_OPCODE_ATOMCAS
] = { V_RAT_INST_CMPXCHG_INT_RTN
, tgsi_atomic_op
},
9913 [TGSI_OPCODE_ATOMAND
] = { V_RAT_INST_AND_RTN
, tgsi_atomic_op
},
9914 [TGSI_OPCODE_ATOMOR
] = { V_RAT_INST_OR_RTN
, tgsi_atomic_op
},
9915 [TGSI_OPCODE_ATOMXOR
] = { V_RAT_INST_XOR_RTN
, tgsi_atomic_op
},
9916 [TGSI_OPCODE_ATOMUMIN
] = { V_RAT_INST_MIN_UINT_RTN
, tgsi_atomic_op
},
9917 [TGSI_OPCODE_ATOMUMAX
] = { V_RAT_INST_MAX_UINT_RTN
, tgsi_atomic_op
},
9918 [TGSI_OPCODE_ATOMIMIN
] = { V_RAT_INST_MIN_INT_RTN
, tgsi_atomic_op
},
9919 [TGSI_OPCODE_ATOMIMAX
] = { V_RAT_INST_MAX_INT_RTN
, tgsi_atomic_op
},
9920 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9921 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9922 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9923 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
9924 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
9925 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
9926 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
9927 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_bfe
},
9928 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_bfe
},
9929 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
9930 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
9931 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
9932 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
9933 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
9934 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
9935 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9936 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9937 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9938 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
9939 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
9940 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
9941 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
9942 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
9943 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
9944 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
9945 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
9946 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
9947 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
9948 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
9949 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
9950 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
9951 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
9952 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
9953 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9954 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9955 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
9956 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
9957 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
9958 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
9959 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
9960 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
9961 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
9962 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
9963 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9966 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
9967 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9968 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9969 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9970 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, cayman_emit_float_instr
},
9971 [TGSI_OPCODE_RSQ
] = { ALU_OP1_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
9972 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9973 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9974 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9975 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9976 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9977 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9978 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9979 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN_DX10
, tgsi_op2
},
9980 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX_DX10
, tgsi_op2
},
9981 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9982 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9983 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9984 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9985 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
9986 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, cayman_emit_float_instr
},
9987 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
9988 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9989 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9990 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9991 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9992 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9993 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9994 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, cayman_emit_float_instr
},
9995 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, cayman_emit_float_instr
},
9996 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, cayman_pow
},
9997 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
9998 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9999 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
10000 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
10001 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
10002 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, cayman_trig
},
10003 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10004 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10005 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
10006 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
10007 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10008 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10009 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10010 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
10011 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
10012 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
10013 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
10014 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, cayman_trig
},
10015 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
10016 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
10017 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
10018 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10019 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
10020 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10021 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
10022 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10023 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10024 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10025 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
10026 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
10027 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
10028 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
10029 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10030 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10031 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
10032 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
10033 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
10034 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10035 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
10036 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10037 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10038 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10039 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
10040 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
10041 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
10042 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
10043 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
10044 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
10045 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10046 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10047 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
10048 [83] = { ALU_OP0_NOP
, tgsi_unsupported
},
10049 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
10050 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2
},
10051 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
10052 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
10053 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
10054 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
10055 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
10056 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
10057 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
10058 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
10059 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
10060 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
10061 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10062 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
10063 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
10064 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
10065 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
10066 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10067 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
10068 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10069 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10070 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
10071 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10072 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
10073 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10074 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
10075 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
10076 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
10077 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
10078 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10079 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
10080 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
10081 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
10082 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
10083 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
10084 /* Refer below for TGSI_OPCODE_DFMA */
10085 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2
},
10086 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
10087 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
10088 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
10089 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
10090 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
10091 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
10092 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
10093 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2
},
10094 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2
},
10095 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
10096 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
10097 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
10098 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
10099 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
10100 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
10101 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_INT
, cayman_mul_int_instr
},
10102 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
10103 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
10104 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
10105 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
10106 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
10107 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10108 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10109 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10110 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10111 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
10112 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
10113 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
10114 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
10115 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
10116 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
10117 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
10118 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
10119 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
10120 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
10121 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
10122 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
10123 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
10124 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
10125 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
10126 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
10127 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_load
},
10128 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_store
},
10129 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
10130 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
10131 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
10132 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10133 [TGSI_OPCODE_ATOMUADD
] = { V_RAT_INST_ADD_RTN
, tgsi_atomic_op
},
10134 [TGSI_OPCODE_ATOMXCHG
] = { V_RAT_INST_XCHG_RTN
, tgsi_atomic_op
},
10135 [TGSI_OPCODE_ATOMCAS
] = { V_RAT_INST_CMPXCHG_INT_RTN
, tgsi_atomic_op
},
10136 [TGSI_OPCODE_ATOMAND
] = { V_RAT_INST_AND_RTN
, tgsi_atomic_op
},
10137 [TGSI_OPCODE_ATOMOR
] = { V_RAT_INST_OR_RTN
, tgsi_atomic_op
},
10138 [TGSI_OPCODE_ATOMXOR
] = { V_RAT_INST_XOR_RTN
, tgsi_atomic_op
},
10139 [TGSI_OPCODE_ATOMUMIN
] = { V_RAT_INST_MIN_UINT_RTN
, tgsi_atomic_op
},
10140 [TGSI_OPCODE_ATOMUMAX
] = { V_RAT_INST_MAX_UINT_RTN
, tgsi_atomic_op
},
10141 [TGSI_OPCODE_ATOMIMIN
] = { V_RAT_INST_MIN_INT_RTN
, tgsi_atomic_op
},
10142 [TGSI_OPCODE_ATOMIMAX
] = { V_RAT_INST_MAX_INT_RTN
, tgsi_atomic_op
},
10143 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10144 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10145 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10146 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, cayman_mul_int_instr
},
10147 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, cayman_mul_int_instr
},
10148 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
10149 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
10150 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_bfe
},
10151 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_bfe
},
10152 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
10153 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
10154 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
10155 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
10156 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
10157 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
10158 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10159 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10160 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10161 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
10162 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
10163 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
10164 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
10165 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
10166 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
10167 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
10168 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
10169 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
10170 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
10171 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
10172 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
10173 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
10174 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
10175 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
10176 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10177 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10178 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
10179 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
10180 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
10181 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
10182 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
10183 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
10184 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
10185 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
10186 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},