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r600g: hack around property unknown issues.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
49 */
50 for (i = 0; i < 10; i++) {
51 spi_vs_out_id[i] = 0;
52 }
53 for (i = 0; i < 32; i++) {
54 tmp = i << ((i & 3) * 8);
55 spi_vs_out_id[i / 4] |= tmp;
56 }
57 for (i = 0; i < 10; i++) {
58 r600_pipe_state_add_reg(rstate,
59 R_028614_SPI_VS_OUT_ID_0 + i * 4,
60 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
61 }
62
63 r600_pipe_state_add_reg(rstate,
64 R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
66 0xFFFFFFFF, NULL);
67 r600_pipe_state_add_reg(rstate,
68 R_028868_SQ_PGM_RESOURCES_VS,
69 S_028868_NUM_GPRS(rshader->bc.ngpr) |
70 S_028868_STACK_SIZE(rshader->bc.nstack),
71 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_028858_SQ_PGM_START_VS,
77 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
78
79 r600_pipe_state_add_reg(rstate,
80 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
81 0xFFFFFFFF, NULL);
82
83 }
84
85 int r600_find_vs_semantic_index(struct r600_shader *vs,
86 struct r600_shader *ps, int id)
87 {
88 struct r600_shader_io *input = &ps->input[id];
89
90 for (int i = 0; i < vs->noutput; i++) {
91 if (input->name == vs->output[i].name &&
92 input->sid == vs->output[i].sid) {
93 return i - 1;
94 }
95 }
96 return 0;
97 }
98
99 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
100 {
101 struct r600_pipe_state *rstate = &shader->rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
104 int pos_index = -1, face_index = -1;
105
106 rstate->nregs = 0;
107
108 for (i = 0; i < rshader->ninput; i++) {
109 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
110 pos_index = i;
111 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
112 face_index = i;
113 }
114
115 for (i = 0; i < rshader->noutput; i++) {
116 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
117 r600_pipe_state_add_reg(rstate,
118 R_02880C_DB_SHADER_CONTROL,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL);
121 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
122 r600_pipe_state_add_reg(rstate,
123 R_02880C_DB_SHADER_CONTROL,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
126 }
127
128 exports_ps = 0;
129 num_cout = 0;
130 for (i = 0; i < rshader->noutput; i++) {
131 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
132 exports_ps |= 1;
133 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
134 num_cout++;
135 }
136 }
137 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
138 if (!exports_ps) {
139 /* always at least export 1 component per pixel */
140 exports_ps = 2;
141 }
142
143 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
145 spi_input_z = 0;
146 if (pos_index != -1) {
147 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
149 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
151 spi_input_z |= 1;
152 }
153
154 spi_ps_in_control_1 = 0;
155 if (face_index != -1) {
156 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
158 }
159
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->uses_kill) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate,
181 R_02880C_DB_SHADER_CONTROL,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL);
184 }
185 r600_pipe_state_add_reg(rstate,
186 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
187 0xFFFFFFFF, NULL);
188 }
189
190 int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
191 {
192 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
193 struct r600_shader *rshader = &shader->shader;
194 void *ptr;
195
196 /* copy new shader */
197 if (shader->bo == NULL) {
198 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
199 if (shader->bo == NULL) {
200 return -ENOMEM;
201 }
202 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
203 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
204 r600_bo_unmap(rctx->radeon, shader->bo);
205 }
206 /* build state */
207 switch (rshader->processor_type) {
208 case TGSI_PROCESSOR_VERTEX:
209 if (rshader->family >= CHIP_CEDAR) {
210 evergreen_pipe_shader_vs(ctx, shader);
211 } else {
212 r600_pipe_shader_vs(ctx, shader);
213 }
214 break;
215 case TGSI_PROCESSOR_FRAGMENT:
216 if (rshader->family >= CHIP_CEDAR) {
217 evergreen_pipe_shader_ps(ctx, shader);
218 } else {
219 r600_pipe_shader_ps(ctx, shader);
220 }
221 break;
222 default:
223 return -EINVAL;
224 }
225 return 0;
226 }
227
228 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
229 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
230 {
231 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
232 int r;
233
234 //fprintf(stderr, "--------------------------------------------------------------\n");
235 //tgsi_dump(tokens, 0);
236 shader->shader.family = r600_get_family(rctx->radeon);
237 r = r600_shader_from_tgsi(tokens, &shader->shader);
238 if (r) {
239 R600_ERR("translation from TGSI failed !\n");
240 return r;
241 }
242 r = r600_bc_build(&shader->shader.bc);
243 if (r) {
244 R600_ERR("building bytecode failed !\n");
245 return r;
246 }
247 //r600_bc_dump(&shader->shader.bc);
248 //fprintf(stderr, "______________________________________________________________\n");
249 return r600_pipe_shader(ctx, shader);
250 }
251
252 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
253 {
254 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
255
256 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
257 r600_bc_clear(&shader->shader.bc);
258 }
259
260 /*
261 * tgsi -> r600 shader
262 */
263 struct r600_shader_tgsi_instruction;
264
265 struct r600_shader_ctx {
266 struct tgsi_shader_info info;
267 struct tgsi_parse_context parse;
268 const struct tgsi_token *tokens;
269 unsigned type;
270 unsigned file_offset[TGSI_FILE_COUNT];
271 unsigned temp_reg;
272 struct r600_shader_tgsi_instruction *inst_info;
273 struct r600_bc *bc;
274 struct r600_shader *shader;
275 u32 value[4];
276 u32 *literals;
277 u32 nliterals;
278 u32 max_driver_temp_used;
279 /* needed for evergreen interpolation */
280 boolean input_centroid;
281 boolean input_linear;
282 boolean input_perspective;
283 int num_interp_gpr;
284 };
285
286 struct r600_shader_tgsi_instruction {
287 unsigned tgsi_opcode;
288 unsigned is_op3;
289 unsigned r600_opcode;
290 int (*process)(struct r600_shader_ctx *ctx);
291 };
292
293 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
294 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
295
296 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
297 {
298 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
299 int j;
300
301 if (i->Instruction.NumDstRegs > 1) {
302 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
303 return -EINVAL;
304 }
305 if (i->Instruction.Predicate) {
306 R600_ERR("predicate unsupported\n");
307 return -EINVAL;
308 }
309 #if 0
310 if (i->Instruction.Label) {
311 R600_ERR("label unsupported\n");
312 return -EINVAL;
313 }
314 #endif
315 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
316 if (i->Src[j].Register.Dimension) {
317 R600_ERR("unsupported src %d (dimension %d)\n", j,
318 i->Src[j].Register.Dimension);
319 return -EINVAL;
320 }
321 }
322 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
323 if (i->Dst[j].Register.Dimension) {
324 R600_ERR("unsupported dst (dimension)\n");
325 return -EINVAL;
326 }
327 }
328 return 0;
329 }
330
331 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
332 {
333 int i, r;
334 struct r600_bc_alu alu;
335 int gpr = 0, base_chan = 0;
336 int ij_index = 0;
337
338 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
339 ij_index = 0;
340 if (ctx->shader->input[input].centroid)
341 ij_index++;
342 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
343 ij_index = 0;
344 /* if we have perspective add one */
345 if (ctx->input_perspective) {
346 ij_index++;
347 /* if we have perspective centroid */
348 if (ctx->input_centroid)
349 ij_index++;
350 }
351 if (ctx->shader->input[input].centroid)
352 ij_index++;
353 }
354
355 /* work out gpr and base_chan from index */
356 gpr = ij_index / 2;
357 base_chan = (2 * (ij_index % 2)) + 1;
358
359 for (i = 0; i < 8; i++) {
360 memset(&alu, 0, sizeof(struct r600_bc_alu));
361
362 if (i < 4)
363 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
364 else
365 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
366
367 if ((i > 1) && (i < 6)) {
368 alu.dst.sel = ctx->shader->input[input].gpr;
369 alu.dst.write = 1;
370 }
371
372 alu.dst.chan = i % 4;
373
374 alu.src[0].sel = gpr;
375 alu.src[0].chan = (base_chan - (i % 2));
376
377 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
378
379 alu.bank_swizzle_force = SQ_ALU_VEC_210;
380 if ((i % 4) == 3)
381 alu.last = 1;
382 r = r600_bc_add_alu(ctx->bc, &alu);
383 if (r)
384 return r;
385 }
386 return 0;
387 }
388
389
390 static int tgsi_declaration(struct r600_shader_ctx *ctx)
391 {
392 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
393 unsigned i;
394
395 switch (d->Declaration.File) {
396 case TGSI_FILE_INPUT:
397 i = ctx->shader->ninput++;
398 ctx->shader->input[i].name = d->Semantic.Name;
399 ctx->shader->input[i].sid = d->Semantic.Index;
400 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
401 ctx->shader->input[i].centroid = d->Declaration.Centroid;
402 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
403 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
404 /* turn input into interpolate on EG */
405 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
406 if (ctx->shader->input[i].interpolate > 0) {
407 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
408 evergreen_interp_alu(ctx, i);
409 }
410 }
411 }
412 break;
413 case TGSI_FILE_OUTPUT:
414 i = ctx->shader->noutput++;
415 ctx->shader->output[i].name = d->Semantic.Name;
416 ctx->shader->output[i].sid = d->Semantic.Index;
417 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
418 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
419 break;
420 case TGSI_FILE_CONSTANT:
421 case TGSI_FILE_TEMPORARY:
422 case TGSI_FILE_SAMPLER:
423 case TGSI_FILE_ADDRESS:
424 break;
425 default:
426 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
427 return -EINVAL;
428 }
429 return 0;
430 }
431
432 static int r600_get_temp(struct r600_shader_ctx *ctx)
433 {
434 return ctx->temp_reg + ctx->max_driver_temp_used++;
435 }
436
437 /*
438 * for evergreen we need to scan the shader to find the number of GPRs we need to
439 * reserve for interpolation.
440 *
441 * we need to know if we are going to emit
442 * any centroid inputs
443 * if perspective and linear are required
444 */
445 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
446 {
447 int i;
448 int num_baryc;
449
450 ctx->input_linear = FALSE;
451 ctx->input_perspective = FALSE;
452 ctx->input_centroid = FALSE;
453 ctx->num_interp_gpr = 1;
454
455 /* any centroid inputs */
456 for (i = 0; i < ctx->info.num_inputs; i++) {
457 /* skip position/face */
458 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
459 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
460 continue;
461 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
462 ctx->input_linear = TRUE;
463 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
464 ctx->input_perspective = TRUE;
465 if (ctx->info.input_centroid[i])
466 ctx->input_centroid = TRUE;
467 }
468
469 num_baryc = 0;
470 /* ignoring sample for now */
471 if (ctx->input_perspective)
472 num_baryc++;
473 if (ctx->input_linear)
474 num_baryc++;
475 if (ctx->input_centroid)
476 num_baryc *= 2;
477
478 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
479
480 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
481 return ctx->num_interp_gpr;
482 }
483
484 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
485 {
486 struct tgsi_full_immediate *immediate;
487 struct r600_shader_ctx ctx;
488 struct r600_bc_output output[32];
489 unsigned output_done, noutput;
490 unsigned opcode;
491 int i, r = 0, pos0;
492
493 ctx.bc = &shader->bc;
494 ctx.shader = shader;
495 r = r600_bc_init(ctx.bc, shader->family);
496 if (r)
497 return r;
498 ctx.tokens = tokens;
499 tgsi_scan_shader(tokens, &ctx.info);
500 tgsi_parse_init(&ctx.parse, tokens);
501 ctx.type = ctx.parse.FullHeader.Processor.Processor;
502 shader->processor_type = ctx.type;
503 ctx.bc->type = shader->processor_type;
504
505 /* register allocations */
506 /* Values [0,127] correspond to GPR[0..127].
507 * Values [128,159] correspond to constant buffer bank 0
508 * Values [160,191] correspond to constant buffer bank 1
509 * Values [256,511] correspond to cfile constants c[0..255].
510 * Other special values are shown in the list below.
511 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
512 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
513 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
514 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
515 * 248 SQ_ALU_SRC_0: special constant 0.0.
516 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
517 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
518 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
519 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
520 * 253 SQ_ALU_SRC_LITERAL: literal constant.
521 * 254 SQ_ALU_SRC_PV: previous vector result.
522 * 255 SQ_ALU_SRC_PS: previous scalar result.
523 */
524 for (i = 0; i < TGSI_FILE_COUNT; i++) {
525 ctx.file_offset[i] = 0;
526 }
527 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
528 ctx.file_offset[TGSI_FILE_INPUT] = 1;
529 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
530 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
531 } else {
532 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
533 }
534 }
535 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
536 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
537 }
538 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
539 ctx.info.file_count[TGSI_FILE_INPUT];
540 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
541 ctx.info.file_count[TGSI_FILE_OUTPUT];
542
543 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
544
545 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
546 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
547 ctx.info.file_count[TGSI_FILE_TEMPORARY];
548
549 ctx.nliterals = 0;
550 ctx.literals = NULL;
551
552 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
553 tgsi_parse_token(&ctx.parse);
554 switch (ctx.parse.FullToken.Token.Type) {
555 case TGSI_TOKEN_TYPE_IMMEDIATE:
556 immediate = &ctx.parse.FullToken.FullImmediate;
557 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
558 if(ctx.literals == NULL) {
559 r = -ENOMEM;
560 goto out_err;
561 }
562 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
563 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
564 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
565 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
566 ctx.nliterals++;
567 break;
568 case TGSI_TOKEN_TYPE_DECLARATION:
569 r = tgsi_declaration(&ctx);
570 if (r)
571 goto out_err;
572 break;
573 case TGSI_TOKEN_TYPE_INSTRUCTION:
574 r = tgsi_is_supported(&ctx);
575 if (r)
576 goto out_err;
577 ctx.max_driver_temp_used = 0;
578 /* reserve first tmp for everyone */
579 r600_get_temp(&ctx);
580 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
581 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
582 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
583 else
584 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
585 r = ctx.inst_info->process(&ctx);
586 if (r)
587 goto out_err;
588 r = r600_bc_add_literal(ctx.bc, ctx.value);
589 if (r)
590 goto out_err;
591 break;
592 case TGSI_TOKEN_TYPE_PROPERTY:
593 break;
594 default:
595 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
596 r = -EINVAL;
597 goto out_err;
598 }
599 }
600 /* export output */
601 noutput = shader->noutput;
602 for (i = 0, pos0 = 0; i < noutput; i++) {
603 memset(&output[i], 0, sizeof(struct r600_bc_output));
604 output[i].gpr = shader->output[i].gpr;
605 output[i].elem_size = 3;
606 output[i].swizzle_x = 0;
607 output[i].swizzle_y = 1;
608 output[i].swizzle_z = 2;
609 output[i].swizzle_w = 3;
610 output[i].barrier = 1;
611 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
612 output[i].array_base = i - pos0;
613 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
614 switch (ctx.type) {
615 case TGSI_PROCESSOR_VERTEX:
616 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
617 output[i].array_base = 60;
618 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
619 /* position doesn't count in array_base */
620 pos0++;
621 }
622 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
623 output[i].array_base = 61;
624 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
625 /* position doesn't count in array_base */
626 pos0++;
627 }
628 break;
629 case TGSI_PROCESSOR_FRAGMENT:
630 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
631 output[i].array_base = shader->output[i].sid;
632 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
633 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
634 output[i].array_base = 61;
635 output[i].swizzle_x = 2;
636 output[i].swizzle_y = 7;
637 output[i].swizzle_z = output[i].swizzle_w = 7;
638 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
639 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
640 output[i].array_base = 61;
641 output[i].swizzle_x = 7;
642 output[i].swizzle_y = 1;
643 output[i].swizzle_z = output[i].swizzle_w = 7;
644 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
645 } else {
646 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
647 r = -EINVAL;
648 goto out_err;
649 }
650 break;
651 default:
652 R600_ERR("unsupported processor type %d\n", ctx.type);
653 r = -EINVAL;
654 goto out_err;
655 }
656 }
657 /* add fake param output for vertex shader if no param is exported */
658 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
659 for (i = 0, pos0 = 0; i < noutput; i++) {
660 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
661 pos0 = 1;
662 break;
663 }
664 }
665 if (!pos0) {
666 memset(&output[i], 0, sizeof(struct r600_bc_output));
667 output[i].gpr = 0;
668 output[i].elem_size = 3;
669 output[i].swizzle_x = 0;
670 output[i].swizzle_y = 1;
671 output[i].swizzle_z = 2;
672 output[i].swizzle_w = 3;
673 output[i].barrier = 1;
674 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
675 output[i].array_base = 0;
676 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
677 noutput++;
678 }
679 }
680 /* add fake pixel export */
681 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
682 memset(&output[0], 0, sizeof(struct r600_bc_output));
683 output[0].gpr = 0;
684 output[0].elem_size = 3;
685 output[0].swizzle_x = 7;
686 output[0].swizzle_y = 7;
687 output[0].swizzle_z = 7;
688 output[0].swizzle_w = 7;
689 output[0].barrier = 1;
690 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
691 output[0].array_base = 0;
692 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
693 noutput++;
694 }
695 /* set export done on last export of each type */
696 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
697 if (i == (noutput - 1)) {
698 output[i].end_of_program = 1;
699 }
700 if (!(output_done & (1 << output[i].type))) {
701 output_done |= (1 << output[i].type);
702 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
703 }
704 }
705 /* add output to bytecode */
706 for (i = 0; i < noutput; i++) {
707 r = r600_bc_add_output(ctx.bc, &output[i]);
708 if (r)
709 goto out_err;
710 }
711 free(ctx.literals);
712 tgsi_parse_free(&ctx.parse);
713 return 0;
714 out_err:
715 free(ctx.literals);
716 tgsi_parse_free(&ctx.parse);
717 return r;
718 }
719
720 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
721 {
722 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
723 return -EINVAL;
724 }
725
726 static int tgsi_end(struct r600_shader_ctx *ctx)
727 {
728 return 0;
729 }
730
731 static int tgsi_src(struct r600_shader_ctx *ctx,
732 const struct tgsi_full_src_register *tgsi_src,
733 struct r600_bc_alu_src *r600_src)
734 {
735 int index;
736 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
737 r600_src->sel = tgsi_src->Register.Index;
738 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
739 r600_src->sel = 0;
740 index = tgsi_src->Register.Index;
741 ctx->value[0] = ctx->literals[index * 4 + 0];
742 ctx->value[1] = ctx->literals[index * 4 + 1];
743 ctx->value[2] = ctx->literals[index * 4 + 2];
744 ctx->value[3] = ctx->literals[index * 4 + 3];
745 }
746 if (tgsi_src->Register.Indirect)
747 r600_src->rel = V_SQ_REL_RELATIVE;
748 r600_src->neg = tgsi_src->Register.Negate;
749 r600_src->abs = tgsi_src->Register.Absolute;
750 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
751 return 0;
752 }
753
754 static int tgsi_dst(struct r600_shader_ctx *ctx,
755 const struct tgsi_full_dst_register *tgsi_dst,
756 unsigned swizzle,
757 struct r600_bc_alu_dst *r600_dst)
758 {
759 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
760
761 r600_dst->sel = tgsi_dst->Register.Index;
762 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
763 r600_dst->chan = swizzle;
764 r600_dst->write = 1;
765 if (tgsi_dst->Register.Indirect)
766 r600_dst->rel = V_SQ_REL_RELATIVE;
767 if (inst->Instruction.Saturate) {
768 r600_dst->clamp = 1;
769 }
770 return 0;
771 }
772
773 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
774 {
775 switch (swizzle) {
776 case 0:
777 return tgsi_src->Register.SwizzleX;
778 case 1:
779 return tgsi_src->Register.SwizzleY;
780 case 2:
781 return tgsi_src->Register.SwizzleZ;
782 case 3:
783 return tgsi_src->Register.SwizzleW;
784 default:
785 return 0;
786 }
787 }
788
789 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
790 {
791 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
792 struct r600_bc_alu alu;
793 int i, j, k, nconst, r;
794
795 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
796 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
797 nconst++;
798 }
799 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
800 if (r) {
801 return r;
802 }
803 }
804 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
805 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
806 int treg = r600_get_temp(ctx);
807 for (k = 0; k < 4; k++) {
808 memset(&alu, 0, sizeof(struct r600_bc_alu));
809 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
810 alu.src[0].sel = r600_src[i].sel;
811 alu.src[0].chan = k;
812 alu.src[0].rel = r600_src[i].rel;
813 alu.dst.sel = treg;
814 alu.dst.chan = k;
815 alu.dst.write = 1;
816 if (k == 3)
817 alu.last = 1;
818 r = r600_bc_add_alu(ctx->bc, &alu);
819 if (r)
820 return r;
821 }
822 r600_src[i].sel = treg;
823 r600_src[i].rel =0;
824 j--;
825 }
826 }
827 return 0;
828 }
829
830 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
831 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
832 {
833 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
834 struct r600_bc_alu alu;
835 int i, j, k, nliteral, r;
836
837 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
838 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
839 nliteral++;
840 }
841 }
842 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
843 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
844 int treg = r600_get_temp(ctx);
845 for (k = 0; k < 4; k++) {
846 memset(&alu, 0, sizeof(struct r600_bc_alu));
847 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
848 alu.src[0].sel = r600_src[i].sel;
849 alu.src[0].chan = k;
850 alu.dst.sel = treg;
851 alu.dst.chan = k;
852 alu.dst.write = 1;
853 if (k == 3)
854 alu.last = 1;
855 r = r600_bc_add_alu(ctx->bc, &alu);
856 if (r)
857 return r;
858 }
859 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
860 if (r)
861 return r;
862 r600_src[i].sel = treg;
863 j--;
864 }
865 }
866 return 0;
867 }
868
869 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
870 {
871 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
872 struct r600_bc_alu_src r600_src[3];
873 struct r600_bc_alu alu;
874 int i, j, r;
875 int lasti = 0;
876
877 for (i = 0; i < 4; i++) {
878 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
879 lasti = i;
880 }
881 }
882
883 r = tgsi_split_constant(ctx, r600_src);
884 if (r)
885 return r;
886 r = tgsi_split_literal_constant(ctx, r600_src);
887 if (r)
888 return r;
889 for (i = 0; i < lasti + 1; i++) {
890 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
891 continue;
892
893 memset(&alu, 0, sizeof(struct r600_bc_alu));
894 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
895 if (r)
896 return r;
897
898 alu.inst = ctx->inst_info->r600_opcode;
899 if (!swap) {
900 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
901 alu.src[j] = r600_src[j];
902 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
903 }
904 } else {
905 alu.src[0] = r600_src[1];
906 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
907
908 alu.src[1] = r600_src[0];
909 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
910 }
911 /* handle some special cases */
912 switch (ctx->inst_info->tgsi_opcode) {
913 case TGSI_OPCODE_SUB:
914 alu.src[1].neg = 1;
915 break;
916 case TGSI_OPCODE_ABS:
917 alu.src[0].abs = 1;
918 break;
919 default:
920 break;
921 }
922 if (i == lasti) {
923 alu.last = 1;
924 }
925 r = r600_bc_add_alu(ctx->bc, &alu);
926 if (r)
927 return r;
928 }
929 return 0;
930 }
931
932 static int tgsi_op2(struct r600_shader_ctx *ctx)
933 {
934 return tgsi_op2_s(ctx, 0);
935 }
936
937 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
938 {
939 return tgsi_op2_s(ctx, 1);
940 }
941
942 /*
943 * r600 - trunc to -PI..PI range
944 * r700 - normalize by dividing by 2PI
945 * see fdo bug 27901
946 */
947 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
948 struct r600_bc_alu_src r600_src[3])
949 {
950 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
951 int r;
952 uint32_t lit_vals[4];
953 struct r600_bc_alu alu;
954
955 memset(lit_vals, 0, 4*4);
956 r = tgsi_split_constant(ctx, r600_src);
957 if (r)
958 return r;
959 r = tgsi_split_literal_constant(ctx, r600_src);
960 if (r)
961 return r;
962
963 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
964 lit_vals[1] = fui(0.5f);
965
966 memset(&alu, 0, sizeof(struct r600_bc_alu));
967 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
968 alu.is_op3 = 1;
969
970 alu.dst.chan = 0;
971 alu.dst.sel = ctx->temp_reg;
972 alu.dst.write = 1;
973
974 alu.src[0] = r600_src[0];
975 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
976
977 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
978 alu.src[1].chan = 0;
979 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
980 alu.src[2].chan = 1;
981 alu.last = 1;
982 r = r600_bc_add_alu(ctx->bc, &alu);
983 if (r)
984 return r;
985 r = r600_bc_add_literal(ctx->bc, lit_vals);
986 if (r)
987 return r;
988
989 memset(&alu, 0, sizeof(struct r600_bc_alu));
990 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
991
992 alu.dst.chan = 0;
993 alu.dst.sel = ctx->temp_reg;
994 alu.dst.write = 1;
995
996 alu.src[0].sel = ctx->temp_reg;
997 alu.src[0].chan = 0;
998 alu.last = 1;
999 r = r600_bc_add_alu(ctx->bc, &alu);
1000 if (r)
1001 return r;
1002
1003 if (ctx->bc->chiprev == CHIPREV_R600) {
1004 lit_vals[0] = fui(3.1415926535897f * 2.0f);
1005 lit_vals[1] = fui(-3.1415926535897f);
1006 } else {
1007 lit_vals[0] = fui(1.0f);
1008 lit_vals[1] = fui(-0.5f);
1009 }
1010
1011 memset(&alu, 0, sizeof(struct r600_bc_alu));
1012 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1013 alu.is_op3 = 1;
1014
1015 alu.dst.chan = 0;
1016 alu.dst.sel = ctx->temp_reg;
1017 alu.dst.write = 1;
1018
1019 alu.src[0].sel = ctx->temp_reg;
1020 alu.src[0].chan = 0;
1021
1022 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1023 alu.src[1].chan = 0;
1024 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1025 alu.src[2].chan = 1;
1026 alu.last = 1;
1027 r = r600_bc_add_alu(ctx->bc, &alu);
1028 if (r)
1029 return r;
1030 r = r600_bc_add_literal(ctx->bc, lit_vals);
1031 if (r)
1032 return r;
1033 return 0;
1034 }
1035
1036 static int tgsi_trig(struct r600_shader_ctx *ctx)
1037 {
1038 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1039 struct r600_bc_alu_src r600_src[3];
1040 struct r600_bc_alu alu;
1041 int i, r;
1042 int lasti = 0;
1043
1044 r = tgsi_setup_trig(ctx, r600_src);
1045 if (r)
1046 return r;
1047
1048 memset(&alu, 0, sizeof(struct r600_bc_alu));
1049 alu.inst = ctx->inst_info->r600_opcode;
1050 alu.dst.chan = 0;
1051 alu.dst.sel = ctx->temp_reg;
1052 alu.dst.write = 1;
1053
1054 alu.src[0].sel = ctx->temp_reg;
1055 alu.src[0].chan = 0;
1056 alu.last = 1;
1057 r = r600_bc_add_alu(ctx->bc, &alu);
1058 if (r)
1059 return r;
1060
1061 /* replicate result */
1062 for (i = 0; i < 4; i++) {
1063 if (inst->Dst[0].Register.WriteMask & (1 << i))
1064 lasti = i;
1065 }
1066 for (i = 0; i < lasti + 1; i++) {
1067 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1068 continue;
1069
1070 memset(&alu, 0, sizeof(struct r600_bc_alu));
1071 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1072
1073 alu.src[0].sel = ctx->temp_reg;
1074 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1075 if (r)
1076 return r;
1077 if (i == lasti)
1078 alu.last = 1;
1079 r = r600_bc_add_alu(ctx->bc, &alu);
1080 if (r)
1081 return r;
1082 }
1083 return 0;
1084 }
1085
1086 static int tgsi_scs(struct r600_shader_ctx *ctx)
1087 {
1088 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1089 struct r600_bc_alu_src r600_src[3];
1090 struct r600_bc_alu alu;
1091 int r;
1092
1093 /* We'll only need the trig stuff if we are going to write to the
1094 * X or Y components of the destination vector.
1095 */
1096 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1097 r = tgsi_setup_trig(ctx, r600_src);
1098 if (r)
1099 return r;
1100 }
1101
1102 /* dst.x = COS */
1103 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1104 memset(&alu, 0, sizeof(struct r600_bc_alu));
1105 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1106 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1107 if (r)
1108 return r;
1109
1110 alu.src[0].sel = ctx->temp_reg;
1111 alu.src[0].chan = 0;
1112 alu.last = 1;
1113 r = r600_bc_add_alu(ctx->bc, &alu);
1114 if (r)
1115 return r;
1116 }
1117
1118 /* dst.y = SIN */
1119 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1120 memset(&alu, 0, sizeof(struct r600_bc_alu));
1121 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1122 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1123 if (r)
1124 return r;
1125
1126 alu.src[0].sel = ctx->temp_reg;
1127 alu.src[0].chan = 0;
1128 alu.last = 1;
1129 r = r600_bc_add_alu(ctx->bc, &alu);
1130 if (r)
1131 return r;
1132 }
1133
1134 /* dst.z = 0.0; */
1135 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1136 memset(&alu, 0, sizeof(struct r600_bc_alu));
1137
1138 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1139
1140 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1141 if (r)
1142 return r;
1143
1144 alu.src[0].sel = V_SQ_ALU_SRC_0;
1145 alu.src[0].chan = 0;
1146
1147 alu.last = 1;
1148
1149 r = r600_bc_add_alu(ctx->bc, &alu);
1150 if (r)
1151 return r;
1152
1153 r = r600_bc_add_literal(ctx->bc, ctx->value);
1154 if (r)
1155 return r;
1156 }
1157
1158 /* dst.w = 1.0; */
1159 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1160 memset(&alu, 0, sizeof(struct r600_bc_alu));
1161
1162 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1163
1164 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1165 if (r)
1166 return r;
1167
1168 alu.src[0].sel = V_SQ_ALU_SRC_1;
1169 alu.src[0].chan = 0;
1170
1171 alu.last = 1;
1172
1173 r = r600_bc_add_alu(ctx->bc, &alu);
1174 if (r)
1175 return r;
1176
1177 r = r600_bc_add_literal(ctx->bc, ctx->value);
1178 if (r)
1179 return r;
1180 }
1181
1182 return 0;
1183 }
1184
1185 static int tgsi_kill(struct r600_shader_ctx *ctx)
1186 {
1187 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1188 struct r600_bc_alu alu;
1189 int i, r;
1190
1191 for (i = 0; i < 4; i++) {
1192 memset(&alu, 0, sizeof(struct r600_bc_alu));
1193 alu.inst = ctx->inst_info->r600_opcode;
1194
1195 alu.dst.chan = i;
1196
1197 alu.src[0].sel = V_SQ_ALU_SRC_0;
1198
1199 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1200 alu.src[1].sel = V_SQ_ALU_SRC_1;
1201 alu.src[1].neg = 1;
1202 } else {
1203 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1204 if (r)
1205 return r;
1206 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1207 }
1208 if (i == 3) {
1209 alu.last = 1;
1210 }
1211 r = r600_bc_add_alu(ctx->bc, &alu);
1212 if (r)
1213 return r;
1214 }
1215 r = r600_bc_add_literal(ctx->bc, ctx->value);
1216 if (r)
1217 return r;
1218
1219 /* kill must be last in ALU */
1220 ctx->bc->force_add_cf = 1;
1221 ctx->shader->uses_kill = TRUE;
1222 return 0;
1223 }
1224
1225 static int tgsi_lit(struct r600_shader_ctx *ctx)
1226 {
1227 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1228 struct r600_bc_alu alu;
1229 struct r600_bc_alu_src r600_src[3];
1230 int r;
1231
1232 r = tgsi_split_constant(ctx, r600_src);
1233 if (r)
1234 return r;
1235 r = tgsi_split_literal_constant(ctx, r600_src);
1236 if (r)
1237 return r;
1238
1239 /* dst.x, <- 1.0 */
1240 memset(&alu, 0, sizeof(struct r600_bc_alu));
1241 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1242 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1243 alu.src[0].chan = 0;
1244 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1245 if (r)
1246 return r;
1247 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1248 r = r600_bc_add_alu(ctx->bc, &alu);
1249 if (r)
1250 return r;
1251
1252 /* dst.y = max(src.x, 0.0) */
1253 memset(&alu, 0, sizeof(struct r600_bc_alu));
1254 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1255 alu.src[0] = r600_src[0];
1256 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1257 alu.src[1].chan = 0;
1258 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1259 if (r)
1260 return r;
1261 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1262 r = r600_bc_add_alu(ctx->bc, &alu);
1263 if (r)
1264 return r;
1265
1266 /* dst.w, <- 1.0 */
1267 memset(&alu, 0, sizeof(struct r600_bc_alu));
1268 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1269 alu.src[0].sel = V_SQ_ALU_SRC_1;
1270 alu.src[0].chan = 0;
1271 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1272 if (r)
1273 return r;
1274 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1275 alu.last = 1;
1276 r = r600_bc_add_alu(ctx->bc, &alu);
1277 if (r)
1278 return r;
1279
1280 r = r600_bc_add_literal(ctx->bc, ctx->value);
1281 if (r)
1282 return r;
1283
1284 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1285 {
1286 int chan;
1287 int sel;
1288
1289 /* dst.z = log(src.y) */
1290 memset(&alu, 0, sizeof(struct r600_bc_alu));
1291 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1292 alu.src[0] = r600_src[0];
1293 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1294 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1295 if (r)
1296 return r;
1297 alu.last = 1;
1298 r = r600_bc_add_alu(ctx->bc, &alu);
1299 if (r)
1300 return r;
1301
1302 r = r600_bc_add_literal(ctx->bc, ctx->value);
1303 if (r)
1304 return r;
1305
1306 chan = alu.dst.chan;
1307 sel = alu.dst.sel;
1308
1309 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1310 memset(&alu, 0, sizeof(struct r600_bc_alu));
1311 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1312 alu.src[0] = r600_src[0];
1313 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1314 alu.src[1].sel = sel;
1315 alu.src[1].chan = chan;
1316
1317 alu.src[2] = r600_src[0];
1318 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1319 alu.dst.sel = ctx->temp_reg;
1320 alu.dst.chan = 0;
1321 alu.dst.write = 1;
1322 alu.is_op3 = 1;
1323 alu.last = 1;
1324 r = r600_bc_add_alu(ctx->bc, &alu);
1325 if (r)
1326 return r;
1327
1328 r = r600_bc_add_literal(ctx->bc, ctx->value);
1329 if (r)
1330 return r;
1331 /* dst.z = exp(tmp.x) */
1332 memset(&alu, 0, sizeof(struct r600_bc_alu));
1333 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1334 alu.src[0].sel = ctx->temp_reg;
1335 alu.src[0].chan = 0;
1336 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1337 if (r)
1338 return r;
1339 alu.last = 1;
1340 r = r600_bc_add_alu(ctx->bc, &alu);
1341 if (r)
1342 return r;
1343 }
1344 return 0;
1345 }
1346
1347 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1348 {
1349 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1350 struct r600_bc_alu alu;
1351 int i, r;
1352
1353 memset(&alu, 0, sizeof(struct r600_bc_alu));
1354
1355 /* FIXME:
1356 * For state trackers other than OpenGL, we'll want to use
1357 * _RECIPSQRT_IEEE instead.
1358 */
1359 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1360
1361 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1362 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1363 if (r)
1364 return r;
1365 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1366 alu.src[i].abs = 1;
1367 }
1368 alu.dst.sel = ctx->temp_reg;
1369 alu.dst.write = 1;
1370 alu.last = 1;
1371 r = r600_bc_add_alu(ctx->bc, &alu);
1372 if (r)
1373 return r;
1374 r = r600_bc_add_literal(ctx->bc, ctx->value);
1375 if (r)
1376 return r;
1377 /* replicate result */
1378 return tgsi_helper_tempx_replicate(ctx);
1379 }
1380
1381 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1382 {
1383 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1384 struct r600_bc_alu alu;
1385 int i, r;
1386
1387 for (i = 0; i < 4; i++) {
1388 memset(&alu, 0, sizeof(struct r600_bc_alu));
1389 alu.src[0].sel = ctx->temp_reg;
1390 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1391 alu.dst.chan = i;
1392 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1393 if (r)
1394 return r;
1395 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1396 if (i == 3)
1397 alu.last = 1;
1398 r = r600_bc_add_alu(ctx->bc, &alu);
1399 if (r)
1400 return r;
1401 }
1402 return 0;
1403 }
1404
1405 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1406 {
1407 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1408 struct r600_bc_alu alu;
1409 int i, r;
1410
1411 memset(&alu, 0, sizeof(struct r600_bc_alu));
1412 alu.inst = ctx->inst_info->r600_opcode;
1413 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1414 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1415 if (r)
1416 return r;
1417 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1418 }
1419 alu.dst.sel = ctx->temp_reg;
1420 alu.dst.write = 1;
1421 alu.last = 1;
1422 r = r600_bc_add_alu(ctx->bc, &alu);
1423 if (r)
1424 return r;
1425 r = r600_bc_add_literal(ctx->bc, ctx->value);
1426 if (r)
1427 return r;
1428 /* replicate result */
1429 return tgsi_helper_tempx_replicate(ctx);
1430 }
1431
1432 static int tgsi_pow(struct r600_shader_ctx *ctx)
1433 {
1434 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1435 struct r600_bc_alu alu;
1436 int r;
1437
1438 /* LOG2(a) */
1439 memset(&alu, 0, sizeof(struct r600_bc_alu));
1440 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1441 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1442 if (r)
1443 return r;
1444 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1445 alu.dst.sel = ctx->temp_reg;
1446 alu.dst.write = 1;
1447 alu.last = 1;
1448 r = r600_bc_add_alu(ctx->bc, &alu);
1449 if (r)
1450 return r;
1451 r = r600_bc_add_literal(ctx->bc,ctx->value);
1452 if (r)
1453 return r;
1454 /* b * LOG2(a) */
1455 memset(&alu, 0, sizeof(struct r600_bc_alu));
1456 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1457 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1458 if (r)
1459 return r;
1460 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1461 alu.src[1].sel = ctx->temp_reg;
1462 alu.dst.sel = ctx->temp_reg;
1463 alu.dst.write = 1;
1464 alu.last = 1;
1465 r = r600_bc_add_alu(ctx->bc, &alu);
1466 if (r)
1467 return r;
1468 r = r600_bc_add_literal(ctx->bc,ctx->value);
1469 if (r)
1470 return r;
1471 /* POW(a,b) = EXP2(b * LOG2(a))*/
1472 memset(&alu, 0, sizeof(struct r600_bc_alu));
1473 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1474 alu.src[0].sel = ctx->temp_reg;
1475 alu.dst.sel = ctx->temp_reg;
1476 alu.dst.write = 1;
1477 alu.last = 1;
1478 r = r600_bc_add_alu(ctx->bc, &alu);
1479 if (r)
1480 return r;
1481 r = r600_bc_add_literal(ctx->bc,ctx->value);
1482 if (r)
1483 return r;
1484 return tgsi_helper_tempx_replicate(ctx);
1485 }
1486
1487 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1488 {
1489 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1490 struct r600_bc_alu alu;
1491 struct r600_bc_alu_src r600_src[3];
1492 int i, r;
1493
1494 r = tgsi_split_constant(ctx, r600_src);
1495 if (r)
1496 return r;
1497 r = tgsi_split_literal_constant(ctx, r600_src);
1498 if (r)
1499 return r;
1500
1501 /* tmp = (src > 0 ? 1 : src) */
1502 for (i = 0; i < 4; i++) {
1503 memset(&alu, 0, sizeof(struct r600_bc_alu));
1504 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1505 alu.is_op3 = 1;
1506
1507 alu.dst.sel = ctx->temp_reg;
1508 alu.dst.chan = i;
1509
1510 alu.src[0] = r600_src[0];
1511 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1512
1513 alu.src[1].sel = V_SQ_ALU_SRC_1;
1514
1515 alu.src[2] = r600_src[0];
1516 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1517 if (i == 3)
1518 alu.last = 1;
1519 r = r600_bc_add_alu(ctx->bc, &alu);
1520 if (r)
1521 return r;
1522 }
1523 r = r600_bc_add_literal(ctx->bc, ctx->value);
1524 if (r)
1525 return r;
1526
1527 /* dst = (-tmp > 0 ? -1 : tmp) */
1528 for (i = 0; i < 4; i++) {
1529 memset(&alu, 0, sizeof(struct r600_bc_alu));
1530 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1531 alu.is_op3 = 1;
1532 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1533 if (r)
1534 return r;
1535
1536 alu.src[0].sel = ctx->temp_reg;
1537 alu.src[0].chan = i;
1538 alu.src[0].neg = 1;
1539
1540 alu.src[1].sel = V_SQ_ALU_SRC_1;
1541 alu.src[1].neg = 1;
1542
1543 alu.src[2].sel = ctx->temp_reg;
1544 alu.src[2].chan = i;
1545
1546 if (i == 3)
1547 alu.last = 1;
1548 r = r600_bc_add_alu(ctx->bc, &alu);
1549 if (r)
1550 return r;
1551 }
1552 return 0;
1553 }
1554
1555 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1556 {
1557 struct r600_bc_alu alu;
1558 int i, r;
1559
1560 r = r600_bc_add_literal(ctx->bc, ctx->value);
1561 if (r)
1562 return r;
1563 for (i = 0; i < 4; i++) {
1564 memset(&alu, 0, sizeof(struct r600_bc_alu));
1565 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1566 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1567 alu.dst.chan = i;
1568 } else {
1569 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1570 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1571 if (r)
1572 return r;
1573 alu.src[0].sel = ctx->temp_reg;
1574 alu.src[0].chan = i;
1575 }
1576 if (i == 3) {
1577 alu.last = 1;
1578 }
1579 r = r600_bc_add_alu(ctx->bc, &alu);
1580 if (r)
1581 return r;
1582 }
1583 return 0;
1584 }
1585
1586 static int tgsi_op3(struct r600_shader_ctx *ctx)
1587 {
1588 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1589 struct r600_bc_alu_src r600_src[3];
1590 struct r600_bc_alu alu;
1591 int i, j, r;
1592
1593 r = tgsi_split_constant(ctx, r600_src);
1594 if (r)
1595 return r;
1596 r = tgsi_split_literal_constant(ctx, r600_src);
1597 if (r)
1598 return r;
1599 /* do it in 2 step as op3 doesn't support writemask */
1600 for (i = 0; i < 4; i++) {
1601 memset(&alu, 0, sizeof(struct r600_bc_alu));
1602 alu.inst = ctx->inst_info->r600_opcode;
1603 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1604 alu.src[j] = r600_src[j];
1605 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1606 }
1607 alu.dst.sel = ctx->temp_reg;
1608 alu.dst.chan = i;
1609 alu.dst.write = 1;
1610 alu.is_op3 = 1;
1611 if (i == 3) {
1612 alu.last = 1;
1613 }
1614 r = r600_bc_add_alu(ctx->bc, &alu);
1615 if (r)
1616 return r;
1617 }
1618 return tgsi_helper_copy(ctx, inst);
1619 }
1620
1621 static int tgsi_dp(struct r600_shader_ctx *ctx)
1622 {
1623 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1624 struct r600_bc_alu_src r600_src[3];
1625 struct r600_bc_alu alu;
1626 int i, j, r;
1627
1628 r = tgsi_split_constant(ctx, r600_src);
1629 if (r)
1630 return r;
1631 r = tgsi_split_literal_constant(ctx, r600_src);
1632 if (r)
1633 return r;
1634 for (i = 0; i < 4; i++) {
1635 memset(&alu, 0, sizeof(struct r600_bc_alu));
1636 alu.inst = ctx->inst_info->r600_opcode;
1637 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1638 alu.src[j] = r600_src[j];
1639 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1640 }
1641 alu.dst.sel = ctx->temp_reg;
1642 alu.dst.chan = i;
1643 alu.dst.write = 1;
1644 /* handle some special cases */
1645 switch (ctx->inst_info->tgsi_opcode) {
1646 case TGSI_OPCODE_DP2:
1647 if (i > 1) {
1648 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1649 alu.src[0].chan = alu.src[1].chan = 0;
1650 }
1651 break;
1652 case TGSI_OPCODE_DP3:
1653 if (i > 2) {
1654 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1655 alu.src[0].chan = alu.src[1].chan = 0;
1656 }
1657 break;
1658 case TGSI_OPCODE_DPH:
1659 if (i == 3) {
1660 alu.src[0].sel = V_SQ_ALU_SRC_1;
1661 alu.src[0].chan = 0;
1662 alu.src[0].neg = 0;
1663 }
1664 break;
1665 default:
1666 break;
1667 }
1668 if (i == 3) {
1669 alu.last = 1;
1670 }
1671 r = r600_bc_add_alu(ctx->bc, &alu);
1672 if (r)
1673 return r;
1674 }
1675 return tgsi_helper_copy(ctx, inst);
1676 }
1677
1678 static int tgsi_tex(struct r600_shader_ctx *ctx)
1679 {
1680 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1681 struct r600_bc_tex tex;
1682 struct r600_bc_alu alu;
1683 unsigned src_gpr;
1684 int r, i;
1685 int opcode;
1686 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1687 uint32_t lit_vals[4];
1688
1689 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1690
1691 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1692 /* Add perspective divide */
1693 memset(&alu, 0, sizeof(struct r600_bc_alu));
1694 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1695 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1696 if (r)
1697 return r;
1698
1699 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1700 alu.dst.sel = ctx->temp_reg;
1701 alu.dst.chan = 3;
1702 alu.last = 1;
1703 alu.dst.write = 1;
1704 r = r600_bc_add_alu(ctx->bc, &alu);
1705 if (r)
1706 return r;
1707
1708 for (i = 0; i < 3; i++) {
1709 memset(&alu, 0, sizeof(struct r600_bc_alu));
1710 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1711 alu.src[0].sel = ctx->temp_reg;
1712 alu.src[0].chan = 3;
1713 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1714 if (r)
1715 return r;
1716 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1717 alu.dst.sel = ctx->temp_reg;
1718 alu.dst.chan = i;
1719 alu.dst.write = 1;
1720 r = r600_bc_add_alu(ctx->bc, &alu);
1721 if (r)
1722 return r;
1723 }
1724 memset(&alu, 0, sizeof(struct r600_bc_alu));
1725 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1726 alu.src[0].sel = V_SQ_ALU_SRC_1;
1727 alu.src[0].chan = 0;
1728 alu.dst.sel = ctx->temp_reg;
1729 alu.dst.chan = 3;
1730 alu.last = 1;
1731 alu.dst.write = 1;
1732 r = r600_bc_add_alu(ctx->bc, &alu);
1733 if (r)
1734 return r;
1735 src_not_temp = FALSE;
1736 src_gpr = ctx->temp_reg;
1737 }
1738
1739 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1740 int src_chan, src2_chan;
1741
1742 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1743 for (i = 0; i < 4; i++) {
1744 memset(&alu, 0, sizeof(struct r600_bc_alu));
1745 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1746 switch (i) {
1747 case 0:
1748 src_chan = 2;
1749 src2_chan = 1;
1750 break;
1751 case 1:
1752 src_chan = 2;
1753 src2_chan = 0;
1754 break;
1755 case 2:
1756 src_chan = 0;
1757 src2_chan = 2;
1758 break;
1759 case 3:
1760 src_chan = 1;
1761 src2_chan = 2;
1762 break;
1763 default:
1764 assert(0);
1765 src_chan = 0;
1766 src2_chan = 0;
1767 break;
1768 }
1769 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1770 if (r)
1771 return r;
1772 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1773 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1774 if (r)
1775 return r;
1776 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1777 alu.dst.sel = ctx->temp_reg;
1778 alu.dst.chan = i;
1779 if (i == 3)
1780 alu.last = 1;
1781 alu.dst.write = 1;
1782 r = r600_bc_add_alu(ctx->bc, &alu);
1783 if (r)
1784 return r;
1785 }
1786
1787 /* tmp1.z = RCP_e(|tmp1.z|) */
1788 memset(&alu, 0, sizeof(struct r600_bc_alu));
1789 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1790 alu.src[0].sel = ctx->temp_reg;
1791 alu.src[0].chan = 2;
1792 alu.src[0].abs = 1;
1793 alu.dst.sel = ctx->temp_reg;
1794 alu.dst.chan = 2;
1795 alu.dst.write = 1;
1796 alu.last = 1;
1797 r = r600_bc_add_alu(ctx->bc, &alu);
1798 if (r)
1799 return r;
1800
1801 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1802 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1803 * muladd has no writemask, have to use another temp
1804 */
1805 memset(&alu, 0, sizeof(struct r600_bc_alu));
1806 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1807 alu.is_op3 = 1;
1808
1809 alu.src[0].sel = ctx->temp_reg;
1810 alu.src[0].chan = 0;
1811 alu.src[1].sel = ctx->temp_reg;
1812 alu.src[1].chan = 2;
1813
1814 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1815 alu.src[2].chan = 0;
1816
1817 alu.dst.sel = ctx->temp_reg;
1818 alu.dst.chan = 0;
1819 alu.dst.write = 1;
1820
1821 r = r600_bc_add_alu(ctx->bc, &alu);
1822 if (r)
1823 return r;
1824
1825 memset(&alu, 0, sizeof(struct r600_bc_alu));
1826 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1827 alu.is_op3 = 1;
1828
1829 alu.src[0].sel = ctx->temp_reg;
1830 alu.src[0].chan = 1;
1831 alu.src[1].sel = ctx->temp_reg;
1832 alu.src[1].chan = 2;
1833
1834 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1835 alu.src[2].chan = 0;
1836
1837 alu.dst.sel = ctx->temp_reg;
1838 alu.dst.chan = 1;
1839 alu.dst.write = 1;
1840
1841 alu.last = 1;
1842 r = r600_bc_add_alu(ctx->bc, &alu);
1843 if (r)
1844 return r;
1845
1846 lit_vals[0] = fui(1.5f);
1847
1848 r = r600_bc_add_literal(ctx->bc, lit_vals);
1849 if (r)
1850 return r;
1851 src_not_temp = FALSE;
1852 src_gpr = ctx->temp_reg;
1853 }
1854
1855 if (src_not_temp) {
1856 for (i = 0; i < 4; i++) {
1857 memset(&alu, 0, sizeof(struct r600_bc_alu));
1858 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1859 alu.src[0].sel = src_gpr;
1860 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1861 alu.dst.sel = ctx->temp_reg;
1862 alu.dst.chan = i;
1863 if (i == 3)
1864 alu.last = 1;
1865 alu.dst.write = 1;
1866 r = r600_bc_add_alu(ctx->bc, &alu);
1867 if (r)
1868 return r;
1869 }
1870 src_gpr = ctx->temp_reg;
1871 }
1872
1873 opcode = ctx->inst_info->r600_opcode;
1874 if (opcode == SQ_TEX_INST_SAMPLE &&
1875 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1876 opcode = SQ_TEX_INST_SAMPLE_C;
1877
1878 memset(&tex, 0, sizeof(struct r600_bc_tex));
1879 tex.inst = opcode;
1880 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1881 tex.resource_id = tex.sampler_id;
1882 tex.src_gpr = src_gpr;
1883 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1884 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1885 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1886 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1887 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1888 tex.src_sel_x = 0;
1889 tex.src_sel_y = 1;
1890 tex.src_sel_z = 2;
1891 tex.src_sel_w = 3;
1892
1893 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1894 tex.src_sel_x = 1;
1895 tex.src_sel_y = 0;
1896 tex.src_sel_z = 3;
1897 tex.src_sel_w = 1;
1898 }
1899
1900 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1901 tex.coord_type_x = 1;
1902 tex.coord_type_y = 1;
1903 tex.coord_type_z = 1;
1904 tex.coord_type_w = 1;
1905 }
1906
1907 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1908 tex.src_sel_w = 2;
1909
1910 r = r600_bc_add_tex(ctx->bc, &tex);
1911 if (r)
1912 return r;
1913
1914 /* add shadow ambient support - gallium doesn't do it yet */
1915 return 0;
1916 }
1917
1918 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1919 {
1920 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1921 struct r600_bc_alu_src r600_src[3];
1922 struct r600_bc_alu alu;
1923 unsigned i;
1924 int r;
1925
1926 r = tgsi_split_constant(ctx, r600_src);
1927 if (r)
1928 return r;
1929 r = tgsi_split_literal_constant(ctx, r600_src);
1930 if (r)
1931 return r;
1932 /* 1 - src0 */
1933 for (i = 0; i < 4; i++) {
1934 memset(&alu, 0, sizeof(struct r600_bc_alu));
1935 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1936 alu.src[0].sel = V_SQ_ALU_SRC_1;
1937 alu.src[0].chan = 0;
1938 alu.src[1] = r600_src[0];
1939 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1940 alu.src[1].neg = 1;
1941 alu.dst.sel = ctx->temp_reg;
1942 alu.dst.chan = i;
1943 if (i == 3) {
1944 alu.last = 1;
1945 }
1946 alu.dst.write = 1;
1947 r = r600_bc_add_alu(ctx->bc, &alu);
1948 if (r)
1949 return r;
1950 }
1951 r = r600_bc_add_literal(ctx->bc, ctx->value);
1952 if (r)
1953 return r;
1954
1955 /* (1 - src0) * src2 */
1956 for (i = 0; i < 4; i++) {
1957 memset(&alu, 0, sizeof(struct r600_bc_alu));
1958 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1959 alu.src[0].sel = ctx->temp_reg;
1960 alu.src[0].chan = i;
1961 alu.src[1] = r600_src[2];
1962 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1963 alu.dst.sel = ctx->temp_reg;
1964 alu.dst.chan = i;
1965 if (i == 3) {
1966 alu.last = 1;
1967 }
1968 alu.dst.write = 1;
1969 r = r600_bc_add_alu(ctx->bc, &alu);
1970 if (r)
1971 return r;
1972 }
1973 r = r600_bc_add_literal(ctx->bc, ctx->value);
1974 if (r)
1975 return r;
1976
1977 /* src0 * src1 + (1 - src0) * src2 */
1978 for (i = 0; i < 4; i++) {
1979 memset(&alu, 0, sizeof(struct r600_bc_alu));
1980 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1981 alu.is_op3 = 1;
1982 alu.src[0] = r600_src[0];
1983 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1984 alu.src[1] = r600_src[1];
1985 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1986 alu.src[2].sel = ctx->temp_reg;
1987 alu.src[2].chan = i;
1988 alu.dst.sel = ctx->temp_reg;
1989 alu.dst.chan = i;
1990 if (i == 3) {
1991 alu.last = 1;
1992 }
1993 r = r600_bc_add_alu(ctx->bc, &alu);
1994 if (r)
1995 return r;
1996 }
1997 return tgsi_helper_copy(ctx, inst);
1998 }
1999
2000 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2001 {
2002 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2003 struct r600_bc_alu_src r600_src[3];
2004 struct r600_bc_alu alu;
2005 int use_temp = 0;
2006 int i, r;
2007
2008 r = tgsi_split_constant(ctx, r600_src);
2009 if (r)
2010 return r;
2011 r = tgsi_split_literal_constant(ctx, r600_src);
2012 if (r)
2013 return r;
2014
2015 if (inst->Dst[0].Register.WriteMask != 0xf)
2016 use_temp = 1;
2017
2018 for (i = 0; i < 4; i++) {
2019 memset(&alu, 0, sizeof(struct r600_bc_alu));
2020 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2021 alu.src[0] = r600_src[0];
2022 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2023
2024 alu.src[1] = r600_src[2];
2025 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2026
2027 alu.src[2] = r600_src[1];
2028 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2029
2030 if (use_temp)
2031 alu.dst.sel = ctx->temp_reg;
2032 else {
2033 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2034 if (r)
2035 return r;
2036 }
2037 alu.dst.chan = i;
2038 alu.dst.write = 1;
2039 alu.is_op3 = 1;
2040 if (i == 3)
2041 alu.last = 1;
2042 r = r600_bc_add_alu(ctx->bc, &alu);
2043 if (r)
2044 return r;
2045 }
2046 if (use_temp)
2047 return tgsi_helper_copy(ctx, inst);
2048 return 0;
2049 }
2050
2051 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2052 {
2053 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2054 struct r600_bc_alu_src r600_src[3];
2055 struct r600_bc_alu alu;
2056 uint32_t use_temp = 0;
2057 int i, r;
2058
2059 if (inst->Dst[0].Register.WriteMask != 0xf)
2060 use_temp = 1;
2061
2062 r = tgsi_split_constant(ctx, r600_src);
2063 if (r)
2064 return r;
2065 r = tgsi_split_literal_constant(ctx, r600_src);
2066 if (r)
2067 return r;
2068
2069 for (i = 0; i < 4; i++) {
2070 memset(&alu, 0, sizeof(struct r600_bc_alu));
2071 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2072
2073 alu.src[0] = r600_src[0];
2074 switch (i) {
2075 case 0:
2076 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2077 break;
2078 case 1:
2079 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2080 break;
2081 case 2:
2082 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2083 break;
2084 case 3:
2085 alu.src[0].sel = V_SQ_ALU_SRC_0;
2086 alu.src[0].chan = i;
2087 }
2088
2089 alu.src[1] = r600_src[1];
2090 switch (i) {
2091 case 0:
2092 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2093 break;
2094 case 1:
2095 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2096 break;
2097 case 2:
2098 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2099 break;
2100 case 3:
2101 alu.src[1].sel = V_SQ_ALU_SRC_0;
2102 alu.src[1].chan = i;
2103 }
2104
2105 alu.dst.sel = ctx->temp_reg;
2106 alu.dst.chan = i;
2107 alu.dst.write = 1;
2108
2109 if (i == 3)
2110 alu.last = 1;
2111 r = r600_bc_add_alu(ctx->bc, &alu);
2112 if (r)
2113 return r;
2114
2115 r = r600_bc_add_literal(ctx->bc, ctx->value);
2116 if (r)
2117 return r;
2118 }
2119
2120 for (i = 0; i < 4; i++) {
2121 memset(&alu, 0, sizeof(struct r600_bc_alu));
2122 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2123
2124 alu.src[0] = r600_src[0];
2125 switch (i) {
2126 case 0:
2127 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2128 break;
2129 case 1:
2130 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2131 break;
2132 case 2:
2133 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2134 break;
2135 case 3:
2136 alu.src[0].sel = V_SQ_ALU_SRC_0;
2137 alu.src[0].chan = i;
2138 }
2139
2140 alu.src[1] = r600_src[1];
2141 switch (i) {
2142 case 0:
2143 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2144 break;
2145 case 1:
2146 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2147 break;
2148 case 2:
2149 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2150 break;
2151 case 3:
2152 alu.src[1].sel = V_SQ_ALU_SRC_0;
2153 alu.src[1].chan = i;
2154 }
2155
2156 alu.src[2].sel = ctx->temp_reg;
2157 alu.src[2].neg = 1;
2158 alu.src[2].chan = i;
2159
2160 if (use_temp)
2161 alu.dst.sel = ctx->temp_reg;
2162 else {
2163 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2164 if (r)
2165 return r;
2166 }
2167 alu.dst.chan = i;
2168 alu.dst.write = 1;
2169 alu.is_op3 = 1;
2170 if (i == 3)
2171 alu.last = 1;
2172 r = r600_bc_add_alu(ctx->bc, &alu);
2173 if (r)
2174 return r;
2175
2176 r = r600_bc_add_literal(ctx->bc, ctx->value);
2177 if (r)
2178 return r;
2179 }
2180 if (use_temp)
2181 return tgsi_helper_copy(ctx, inst);
2182 return 0;
2183 }
2184
2185 static int tgsi_exp(struct r600_shader_ctx *ctx)
2186 {
2187 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2188 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2189 struct r600_bc_alu alu;
2190 int r;
2191
2192 /* result.x = 2^floor(src); */
2193 if (inst->Dst[0].Register.WriteMask & 1) {
2194 memset(&alu, 0, sizeof(struct r600_bc_alu));
2195
2196 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2197 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2198 if (r)
2199 return r;
2200
2201 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2202
2203 alu.dst.sel = ctx->temp_reg;
2204 alu.dst.chan = 0;
2205 alu.dst.write = 1;
2206 alu.last = 1;
2207 r = r600_bc_add_alu(ctx->bc, &alu);
2208 if (r)
2209 return r;
2210
2211 r = r600_bc_add_literal(ctx->bc, ctx->value);
2212 if (r)
2213 return r;
2214
2215 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2216 alu.src[0].sel = ctx->temp_reg;
2217 alu.src[0].chan = 0;
2218
2219 alu.dst.sel = ctx->temp_reg;
2220 alu.dst.chan = 0;
2221 alu.dst.write = 1;
2222 alu.last = 1;
2223 r = r600_bc_add_alu(ctx->bc, &alu);
2224 if (r)
2225 return r;
2226
2227 r = r600_bc_add_literal(ctx->bc, ctx->value);
2228 if (r)
2229 return r;
2230 }
2231
2232 /* result.y = tmp - floor(tmp); */
2233 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2234 memset(&alu, 0, sizeof(struct r600_bc_alu));
2235
2236 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2237 alu.src[0] = r600_src[0];
2238 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2239 if (r)
2240 return r;
2241 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2242
2243 alu.dst.sel = ctx->temp_reg;
2244 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2245 // if (r)
2246 // return r;
2247 alu.dst.write = 1;
2248 alu.dst.chan = 1;
2249
2250 alu.last = 1;
2251
2252 r = r600_bc_add_alu(ctx->bc, &alu);
2253 if (r)
2254 return r;
2255 r = r600_bc_add_literal(ctx->bc, ctx->value);
2256 if (r)
2257 return r;
2258 }
2259
2260 /* result.z = RoughApprox2ToX(tmp);*/
2261 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2262 memset(&alu, 0, sizeof(struct r600_bc_alu));
2263 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2264 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2265 if (r)
2266 return r;
2267 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2268
2269 alu.dst.sel = ctx->temp_reg;
2270 alu.dst.write = 1;
2271 alu.dst.chan = 2;
2272
2273 alu.last = 1;
2274
2275 r = r600_bc_add_alu(ctx->bc, &alu);
2276 if (r)
2277 return r;
2278 r = r600_bc_add_literal(ctx->bc, ctx->value);
2279 if (r)
2280 return r;
2281 }
2282
2283 /* result.w = 1.0;*/
2284 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2285 memset(&alu, 0, sizeof(struct r600_bc_alu));
2286
2287 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2288 alu.src[0].sel = V_SQ_ALU_SRC_1;
2289 alu.src[0].chan = 0;
2290
2291 alu.dst.sel = ctx->temp_reg;
2292 alu.dst.chan = 3;
2293 alu.dst.write = 1;
2294 alu.last = 1;
2295 r = r600_bc_add_alu(ctx->bc, &alu);
2296 if (r)
2297 return r;
2298 r = r600_bc_add_literal(ctx->bc, ctx->value);
2299 if (r)
2300 return r;
2301 }
2302 return tgsi_helper_copy(ctx, inst);
2303 }
2304
2305 static int tgsi_log(struct r600_shader_ctx *ctx)
2306 {
2307 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2308 struct r600_bc_alu alu;
2309 int r;
2310
2311 /* result.x = floor(log2(src)); */
2312 if (inst->Dst[0].Register.WriteMask & 1) {
2313 memset(&alu, 0, sizeof(struct r600_bc_alu));
2314
2315 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2316 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2317 if (r)
2318 return r;
2319
2320 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2321
2322 alu.dst.sel = ctx->temp_reg;
2323 alu.dst.chan = 0;
2324 alu.dst.write = 1;
2325 alu.last = 1;
2326 r = r600_bc_add_alu(ctx->bc, &alu);
2327 if (r)
2328 return r;
2329
2330 r = r600_bc_add_literal(ctx->bc, ctx->value);
2331 if (r)
2332 return r;
2333
2334 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2335 alu.src[0].sel = ctx->temp_reg;
2336 alu.src[0].chan = 0;
2337
2338 alu.dst.sel = ctx->temp_reg;
2339 alu.dst.chan = 0;
2340 alu.dst.write = 1;
2341 alu.last = 1;
2342
2343 r = r600_bc_add_alu(ctx->bc, &alu);
2344 if (r)
2345 return r;
2346
2347 r = r600_bc_add_literal(ctx->bc, ctx->value);
2348 if (r)
2349 return r;
2350 }
2351
2352 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2353 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2354 memset(&alu, 0, sizeof(struct r600_bc_alu));
2355
2356 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2357 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2358 if (r)
2359 return r;
2360
2361 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2362
2363 alu.dst.sel = ctx->temp_reg;
2364 alu.dst.chan = 1;
2365 alu.dst.write = 1;
2366 alu.last = 1;
2367
2368 r = r600_bc_add_alu(ctx->bc, &alu);
2369 if (r)
2370 return r;
2371
2372 r = r600_bc_add_literal(ctx->bc, ctx->value);
2373 if (r)
2374 return r;
2375
2376 memset(&alu, 0, sizeof(struct r600_bc_alu));
2377
2378 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2379 alu.src[0].sel = ctx->temp_reg;
2380 alu.src[0].chan = 1;
2381
2382 alu.dst.sel = ctx->temp_reg;
2383 alu.dst.chan = 1;
2384 alu.dst.write = 1;
2385 alu.last = 1;
2386
2387 r = r600_bc_add_alu(ctx->bc, &alu);
2388 if (r)
2389 return r;
2390
2391 r = r600_bc_add_literal(ctx->bc, ctx->value);
2392 if (r)
2393 return r;
2394
2395 memset(&alu, 0, sizeof(struct r600_bc_alu));
2396
2397 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2398 alu.src[0].sel = ctx->temp_reg;
2399 alu.src[0].chan = 1;
2400
2401 alu.dst.sel = ctx->temp_reg;
2402 alu.dst.chan = 1;
2403 alu.dst.write = 1;
2404 alu.last = 1;
2405
2406 r = r600_bc_add_alu(ctx->bc, &alu);
2407 if (r)
2408 return r;
2409
2410 r = r600_bc_add_literal(ctx->bc, ctx->value);
2411 if (r)
2412 return r;
2413
2414 memset(&alu, 0, sizeof(struct r600_bc_alu));
2415
2416 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2417 alu.src[0].sel = ctx->temp_reg;
2418 alu.src[0].chan = 1;
2419
2420 alu.dst.sel = ctx->temp_reg;
2421 alu.dst.chan = 1;
2422 alu.dst.write = 1;
2423 alu.last = 1;
2424
2425 r = r600_bc_add_alu(ctx->bc, &alu);
2426 if (r)
2427 return r;
2428
2429 r = r600_bc_add_literal(ctx->bc, ctx->value);
2430 if (r)
2431 return r;
2432
2433 memset(&alu, 0, sizeof(struct r600_bc_alu));
2434
2435 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2436
2437 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2438 if (r)
2439 return r;
2440
2441 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2442
2443 alu.src[1].sel = ctx->temp_reg;
2444 alu.src[1].chan = 1;
2445
2446 alu.dst.sel = ctx->temp_reg;
2447 alu.dst.chan = 1;
2448 alu.dst.write = 1;
2449 alu.last = 1;
2450
2451 r = r600_bc_add_alu(ctx->bc, &alu);
2452 if (r)
2453 return r;
2454
2455 r = r600_bc_add_literal(ctx->bc, ctx->value);
2456 if (r)
2457 return r;
2458 }
2459
2460 /* result.z = log2(src);*/
2461 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2462 memset(&alu, 0, sizeof(struct r600_bc_alu));
2463
2464 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2465 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2466 if (r)
2467 return r;
2468
2469 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2470
2471 alu.dst.sel = ctx->temp_reg;
2472 alu.dst.write = 1;
2473 alu.dst.chan = 2;
2474 alu.last = 1;
2475
2476 r = r600_bc_add_alu(ctx->bc, &alu);
2477 if (r)
2478 return r;
2479
2480 r = r600_bc_add_literal(ctx->bc, ctx->value);
2481 if (r)
2482 return r;
2483 }
2484
2485 /* result.w = 1.0; */
2486 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2487 memset(&alu, 0, sizeof(struct r600_bc_alu));
2488
2489 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2490 alu.src[0].sel = V_SQ_ALU_SRC_1;
2491 alu.src[0].chan = 0;
2492
2493 alu.dst.sel = ctx->temp_reg;
2494 alu.dst.chan = 3;
2495 alu.dst.write = 1;
2496 alu.last = 1;
2497
2498 r = r600_bc_add_alu(ctx->bc, &alu);
2499 if (r)
2500 return r;
2501
2502 r = r600_bc_add_literal(ctx->bc, ctx->value);
2503 if (r)
2504 return r;
2505 }
2506
2507 return tgsi_helper_copy(ctx, inst);
2508 }
2509
2510 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2511 {
2512 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2513 struct r600_bc_alu alu;
2514 int r;
2515 memset(&alu, 0, sizeof(struct r600_bc_alu));
2516
2517 switch (inst->Instruction.Opcode) {
2518 case TGSI_OPCODE_ARL:
2519 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2520 break;
2521 case TGSI_OPCODE_ARR:
2522 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2523 break;
2524 default:
2525 assert(0);
2526 return -1;
2527 }
2528
2529 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2530 if (r)
2531 return r;
2532 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2533 alu.last = 1;
2534 alu.dst.chan = 0;
2535 alu.dst.sel = ctx->temp_reg;
2536 alu.dst.write = 1;
2537 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2538 if (r)
2539 return r;
2540 memset(&alu, 0, sizeof(struct r600_bc_alu));
2541 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2542 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2543 if (r)
2544 return r;
2545 alu.src[0].sel = ctx->temp_reg;
2546 alu.src[0].chan = 0;
2547 alu.last = 1;
2548 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2549 if (r)
2550 return r;
2551 return 0;
2552 }
2553 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2554 {
2555 /* TODO from r600c, ar values don't persist between clauses */
2556 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2557 struct r600_bc_alu alu;
2558 int r;
2559 memset(&alu, 0, sizeof(struct r600_bc_alu));
2560
2561 switch (inst->Instruction.Opcode) {
2562 case TGSI_OPCODE_ARL:
2563 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2564 break;
2565 case TGSI_OPCODE_ARR:
2566 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2567 break;
2568 default:
2569 assert(0);
2570 return -1;
2571 }
2572
2573
2574 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2575 if (r)
2576 return r;
2577 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2578
2579 alu.last = 1;
2580
2581 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2582 if (r)
2583 return r;
2584 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2585 return 0;
2586 }
2587
2588 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2589 {
2590 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2591 struct r600_bc_alu alu;
2592 int i, r = 0;
2593
2594 for (i = 0; i < 4; i++) {
2595 memset(&alu, 0, sizeof(struct r600_bc_alu));
2596
2597 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2598 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2599 if (r)
2600 return r;
2601
2602 if (i == 0 || i == 3) {
2603 alu.src[0].sel = V_SQ_ALU_SRC_1;
2604 } else {
2605 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2606 if (r)
2607 return r;
2608 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2609 }
2610
2611 if (i == 0 || i == 2) {
2612 alu.src[1].sel = V_SQ_ALU_SRC_1;
2613 } else {
2614 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2615 if (r)
2616 return r;
2617 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2618 }
2619 if (i == 3)
2620 alu.last = 1;
2621 r = r600_bc_add_alu(ctx->bc, &alu);
2622 if (r)
2623 return r;
2624 }
2625 return 0;
2626 }
2627
2628 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2629 {
2630 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2631 struct r600_bc_alu alu;
2632 int r;
2633
2634 memset(&alu, 0, sizeof(struct r600_bc_alu));
2635 alu.inst = opcode;
2636 alu.predicate = 1;
2637
2638 alu.dst.sel = ctx->temp_reg;
2639 alu.dst.write = 1;
2640 alu.dst.chan = 0;
2641
2642 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2643 if (r)
2644 return r;
2645 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2646 alu.src[1].sel = V_SQ_ALU_SRC_0;
2647 alu.src[1].chan = 0;
2648
2649 alu.last = 1;
2650
2651 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2652 if (r)
2653 return r;
2654 return 0;
2655 }
2656
2657 static int pops(struct r600_shader_ctx *ctx, int pops)
2658 {
2659 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2660 ctx->bc->cf_last->pop_count = pops;
2661 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2662 return 0;
2663 }
2664
2665 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2666 {
2667 switch(reason) {
2668 case FC_PUSH_VPM:
2669 ctx->bc->callstack[ctx->bc->call_sp].current--;
2670 break;
2671 case FC_PUSH_WQM:
2672 case FC_LOOP:
2673 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2674 break;
2675 case FC_REP:
2676 /* TOODO : for 16 vp asic should -= 2; */
2677 ctx->bc->callstack[ctx->bc->call_sp].current --;
2678 break;
2679 }
2680 }
2681
2682 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2683 {
2684 if (check_max_only) {
2685 int diff;
2686 switch (reason) {
2687 case FC_PUSH_VPM:
2688 diff = 1;
2689 break;
2690 case FC_PUSH_WQM:
2691 diff = 4;
2692 break;
2693 default:
2694 assert(0);
2695 diff = 0;
2696 }
2697 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2698 ctx->bc->callstack[ctx->bc->call_sp].max) {
2699 ctx->bc->callstack[ctx->bc->call_sp].max =
2700 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2701 }
2702 return;
2703 }
2704 switch (reason) {
2705 case FC_PUSH_VPM:
2706 ctx->bc->callstack[ctx->bc->call_sp].current++;
2707 break;
2708 case FC_PUSH_WQM:
2709 case FC_LOOP:
2710 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2711 break;
2712 case FC_REP:
2713 ctx->bc->callstack[ctx->bc->call_sp].current++;
2714 break;
2715 }
2716
2717 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2718 ctx->bc->callstack[ctx->bc->call_sp].max) {
2719 ctx->bc->callstack[ctx->bc->call_sp].max =
2720 ctx->bc->callstack[ctx->bc->call_sp].current;
2721 }
2722 }
2723
2724 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2725 {
2726 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2727
2728 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2729 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2730 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2731 sp->num_mid++;
2732 }
2733
2734 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2735 {
2736 ctx->bc->fc_sp++;
2737 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2738 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2739 }
2740
2741 static void fc_poplevel(struct r600_shader_ctx *ctx)
2742 {
2743 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2744 if (sp->mid) {
2745 free(sp->mid);
2746 sp->mid = NULL;
2747 }
2748 sp->num_mid = 0;
2749 sp->start = NULL;
2750 sp->type = 0;
2751 ctx->bc->fc_sp--;
2752 }
2753
2754 #if 0
2755 static int emit_return(struct r600_shader_ctx *ctx)
2756 {
2757 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2758 return 0;
2759 }
2760
2761 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2762 {
2763
2764 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2765 ctx->bc->cf_last->pop_count = pops;
2766 /* TODO work out offset */
2767 return 0;
2768 }
2769
2770 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2771 {
2772 return 0;
2773 }
2774
2775 static void emit_testflag(struct r600_shader_ctx *ctx)
2776 {
2777
2778 }
2779
2780 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2781 {
2782 emit_testflag(ctx);
2783 emit_jump_to_offset(ctx, 1, 4);
2784 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2785 pops(ctx, ifidx + 1);
2786 emit_return(ctx);
2787 }
2788
2789 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2790 {
2791 emit_testflag(ctx);
2792
2793 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2794 ctx->bc->cf_last->pop_count = 1;
2795
2796 fc_set_mid(ctx, fc_sp);
2797
2798 pops(ctx, 1);
2799 }
2800 #endif
2801
2802 static int tgsi_if(struct r600_shader_ctx *ctx)
2803 {
2804 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2805
2806 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2807
2808 fc_pushlevel(ctx, FC_IF);
2809
2810 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2811 return 0;
2812 }
2813
2814 static int tgsi_else(struct r600_shader_ctx *ctx)
2815 {
2816 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2817 ctx->bc->cf_last->pop_count = 1;
2818
2819 fc_set_mid(ctx, ctx->bc->fc_sp);
2820 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2821 return 0;
2822 }
2823
2824 static int tgsi_endif(struct r600_shader_ctx *ctx)
2825 {
2826 pops(ctx, 1);
2827 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2828 R600_ERR("if/endif unbalanced in shader\n");
2829 return -1;
2830 }
2831
2832 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2833 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2834 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2835 } else {
2836 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2837 }
2838 fc_poplevel(ctx);
2839
2840 callstack_decrease_current(ctx, FC_PUSH_VPM);
2841 return 0;
2842 }
2843
2844 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2845 {
2846 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2847
2848 fc_pushlevel(ctx, FC_LOOP);
2849
2850 /* check stack depth */
2851 callstack_check_depth(ctx, FC_LOOP, 0);
2852 return 0;
2853 }
2854
2855 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2856 {
2857 int i;
2858
2859 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2860
2861 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2862 R600_ERR("loop/endloop in shader code are not paired.\n");
2863 return -EINVAL;
2864 }
2865
2866 /* fixup loop pointers - from r600isa
2867 LOOP END points to CF after LOOP START,
2868 LOOP START point to CF after LOOP END
2869 BRK/CONT point to LOOP END CF
2870 */
2871 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2872
2873 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2874
2875 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2876 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2877 }
2878 /* TODO add LOOPRET support */
2879 fc_poplevel(ctx);
2880 callstack_decrease_current(ctx, FC_LOOP);
2881 return 0;
2882 }
2883
2884 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2885 {
2886 unsigned int fscp;
2887
2888 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2889 {
2890 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2891 break;
2892 }
2893
2894 if (fscp == 0) {
2895 R600_ERR("Break not inside loop/endloop pair\n");
2896 return -EINVAL;
2897 }
2898
2899 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2900 ctx->bc->cf_last->pop_count = 1;
2901
2902 fc_set_mid(ctx, fscp);
2903
2904 pops(ctx, 1);
2905 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2906 return 0;
2907 }
2908
2909 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2910 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2911 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2912 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2913
2914 /* FIXME:
2915 * For state trackers other than OpenGL, we'll want to use
2916 * _RECIP_IEEE instead.
2917 */
2918 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2919
2920 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2921 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2922 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2923 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2924 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2925 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2926 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2927 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2928 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2929 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2930 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2931 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2932 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2933 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2934 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2935 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 /* gap */
2937 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 /* gap */
2940 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2943 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2945 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2947 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2948 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2949 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2950 /* gap */
2951 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2953 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2955 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2956 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2957 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2958 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2959 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2960 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2961 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2965 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2967 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2968 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2969 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2970 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2972 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2974 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2981 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2985 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2986 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2987 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2988 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2991 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2992 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2993 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2994 /* gap */
2995 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2998 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2999 /* gap */
3000 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3008 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 /* gap */
3010 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3015 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3019 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3022 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3024 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 /* gap */
3026 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3027 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3028 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3029 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 /* gap */
3032 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3037 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3039 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3040 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3041 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3042 /* gap */
3043 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3044 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3045 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3049 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3051 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3053 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3056 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3058 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3069 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 };
3072
3073 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3074 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3075 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3076 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3077 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3078 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3079 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3080 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3082 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3083 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3084 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3085 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3086 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3087 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3088 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3089 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3090 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3091 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3092 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3093 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 /* gap */
3095 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 /* gap */
3098 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3101 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3103 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3105 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3106 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3107 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3108 /* gap */
3109 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3111 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3113 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3114 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3115 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3116 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3117 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3118 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3123 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3125 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3126 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3127 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3128 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3130 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3132 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3139 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3143 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3144 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3145 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3146 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3147 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3149 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3150 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3151 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3152 /* gap */
3153 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3154 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3156 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3157 /* gap */
3158 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3159 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3160 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3161 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3162 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3163 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3164 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3166 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3167 /* gap */
3168 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3169 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3170 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3171 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3172 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3173 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3174 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3176 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3177 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3178 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3179 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3180 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3181 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3182 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3183 /* gap */
3184 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3185 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3186 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3187 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3188 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3189 /* gap */
3190 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3191 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3192 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3193 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3194 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3195 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3196 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3197 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3198 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3199 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3200 /* gap */
3201 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3202 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3203 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3204 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3205 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3206 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3207 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3208 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3209 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3210 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3211 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3212 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3213 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3214 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3215 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3216 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3217 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3218 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3219 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3220 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3221 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3222 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3223 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3224 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3225 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3226 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3227 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3228 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3229 };