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eg/compute: Drop reference on code_bo in destructor.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm;
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193 use_sb &= (shader->shader.processor_type != PIPE_SHADER_COMPUTE);
194
195 /* disable SB for shaders using doubles */
196 use_sb &= !shader->shader.uses_doubles;
197
198 use_sb &= !shader->shader.uses_atomics;
199 use_sb &= !shader->shader.uses_images;
200 use_sb &= !shader->shader.uses_helper_invocation;
201
202 /* Check if the bytecode has already been built. */
203 if (!shader->shader.bc.bytecode) {
204 r = r600_bytecode_build(&shader->shader.bc);
205 if (r) {
206 R600_ERR("building bytecode failed !\n");
207 goto error;
208 }
209 }
210
211 sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
212 if (dump && !sb_disasm) {
213 fprintf(stderr, "--------------------------------------------------------------\n");
214 r600_bytecode_disasm(&shader->shader.bc);
215 fprintf(stderr, "______________________________________________________________\n");
216 } else if ((dump && sb_disasm) || use_sb) {
217 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
218 dump, use_sb);
219 if (r) {
220 R600_ERR("r600_sb_bytecode_process failed !\n");
221 goto error;
222 }
223 }
224
225 if (shader->gs_copy_shader) {
226 if (dump) {
227 // dump copy shader
228 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
229 &shader->gs_copy_shader->shader, dump, 0);
230 if (r)
231 goto error;
232 }
233
234 if ((r = store_shader(ctx, shader->gs_copy_shader)))
235 goto error;
236 }
237
238 /* Store the shader in a buffer. */
239 if ((r = store_shader(ctx, shader)))
240 goto error;
241
242 /* Build state. */
243 switch (shader->shader.processor_type) {
244 case PIPE_SHADER_TESS_CTRL:
245 evergreen_update_hs_state(ctx, shader);
246 break;
247 case PIPE_SHADER_TESS_EVAL:
248 if (key.tes.as_es)
249 evergreen_update_es_state(ctx, shader);
250 else
251 evergreen_update_vs_state(ctx, shader);
252 break;
253 case PIPE_SHADER_GEOMETRY:
254 if (rctx->b.chip_class >= EVERGREEN) {
255 evergreen_update_gs_state(ctx, shader);
256 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
257 } else {
258 r600_update_gs_state(ctx, shader);
259 r600_update_vs_state(ctx, shader->gs_copy_shader);
260 }
261 break;
262 case PIPE_SHADER_VERTEX:
263 export_shader = key.vs.as_es;
264 if (rctx->b.chip_class >= EVERGREEN) {
265 if (key.vs.as_ls)
266 evergreen_update_ls_state(ctx, shader);
267 else if (key.vs.as_es)
268 evergreen_update_es_state(ctx, shader);
269 else
270 evergreen_update_vs_state(ctx, shader);
271 } else {
272 if (export_shader)
273 r600_update_es_state(ctx, shader);
274 else
275 r600_update_vs_state(ctx, shader);
276 }
277 break;
278 case PIPE_SHADER_FRAGMENT:
279 if (rctx->b.chip_class >= EVERGREEN) {
280 evergreen_update_ps_state(ctx, shader);
281 } else {
282 r600_update_ps_state(ctx, shader);
283 }
284 break;
285 case PIPE_SHADER_COMPUTE:
286 evergreen_update_ls_state(ctx, shader);
287 break;
288 default:
289 r = -EINVAL;
290 goto error;
291 }
292 return 0;
293
294 error:
295 r600_pipe_shader_destroy(ctx, shader);
296 return r;
297 }
298
299 void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
300 {
301 r600_resource_reference(&shader->bo, NULL);
302 r600_bytecode_clear(&shader->shader.bc);
303 r600_release_command_buffer(&shader->command_buffer);
304 }
305
306 /*
307 * tgsi -> r600 shader
308 */
309 struct r600_shader_tgsi_instruction;
310
311 struct r600_shader_src {
312 unsigned sel;
313 unsigned swizzle[4];
314 unsigned neg;
315 unsigned abs;
316 unsigned rel;
317 unsigned kc_bank;
318 boolean kc_rel; /* true if cache bank is indexed */
319 uint32_t value[4];
320 };
321
322 struct eg_interp {
323 boolean enabled;
324 unsigned ij_index;
325 };
326
327 struct r600_shader_ctx {
328 struct tgsi_shader_info info;
329 struct tgsi_array_info *array_infos;
330 /* flag for each tgsi temp array if its been spilled or not */
331 bool *spilled_arrays;
332 struct tgsi_parse_context parse;
333 const struct tgsi_token *tokens;
334 unsigned type;
335 unsigned file_offset[TGSI_FILE_COUNT];
336 unsigned temp_reg;
337 const struct r600_shader_tgsi_instruction *inst_info;
338 struct r600_bytecode *bc;
339 struct r600_shader *shader;
340 struct r600_shader_src src[4];
341 uint32_t *literals;
342 uint32_t nliterals;
343 uint32_t max_driver_temp_used;
344 /* needed for evergreen interpolation */
345 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
346 /* evergreen/cayman also store sample mask in face register */
347 int face_gpr;
348 /* sample id is .w component stored in fixed point position register */
349 int fixed_pt_position_gpr;
350 int colors_used;
351 boolean clip_vertex_write;
352 unsigned cv_output;
353 unsigned edgeflag_output;
354 int helper_invoc_reg;
355 int cs_block_size_reg;
356 int cs_grid_size_reg;
357 bool cs_block_size_loaded, cs_grid_size_loaded;
358 int fragcoord_input;
359 int next_ring_offset;
360 int gs_out_ring_offset;
361 int gs_next_vertex;
362 struct r600_shader *gs_for_vs;
363 int gs_export_gpr_tregs[4];
364 int gs_rotated_input[2];
365 const struct pipe_stream_output_info *gs_stream_output_info;
366 unsigned enabled_stream_buffers_mask;
367 unsigned tess_input_info; /* temp with tess input offsets */
368 unsigned tess_output_info; /* temp with tess input offsets */
369 unsigned thread_id_gpr; /* temp with thread id calculated for images */
370 };
371
372 struct r600_shader_tgsi_instruction {
373 unsigned op;
374 int (*process)(struct r600_shader_ctx *ctx);
375 };
376
377 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
378 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
379 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
380 static inline int callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
381 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
382 static int tgsi_else(struct r600_shader_ctx *ctx);
383 static int tgsi_endif(struct r600_shader_ctx *ctx);
384 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
385 static int tgsi_endloop(struct r600_shader_ctx *ctx);
386 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
387 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
388 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
389 unsigned int dst_reg);
390 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
391 const struct r600_shader_src *shader_src,
392 unsigned chan);
393 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
394 unsigned dst_reg, unsigned mask);
395
396 static bool ctx_needs_stack_workaround_8xx(struct r600_shader_ctx *ctx)
397 {
398 if (ctx->bc->family == CHIP_HEMLOCK ||
399 ctx->bc->family == CHIP_CYPRESS ||
400 ctx->bc->family == CHIP_JUNIPER)
401 return false;
402 return true;
403 }
404
405 static int tgsi_last_instruction(unsigned writemask)
406 {
407 int i, lasti = 0;
408
409 for (i = 0; i < 4; i++) {
410 if (writemask & (1 << i)) {
411 lasti = i;
412 }
413 }
414 return lasti;
415 }
416
417 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
418 {
419 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
420 unsigned j;
421
422 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
423 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
424 return -EINVAL;
425 }
426 #if 0
427 if (i->Instruction.Label) {
428 R600_ERR("label unsupported\n");
429 return -EINVAL;
430 }
431 #endif
432 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
433 if (i->Src[j].Register.Dimension) {
434 switch (i->Src[j].Register.File) {
435 case TGSI_FILE_CONSTANT:
436 case TGSI_FILE_HW_ATOMIC:
437 break;
438 case TGSI_FILE_INPUT:
439 if (ctx->type == PIPE_SHADER_GEOMETRY ||
440 ctx->type == PIPE_SHADER_TESS_CTRL ||
441 ctx->type == PIPE_SHADER_TESS_EVAL)
442 break;
443 case TGSI_FILE_OUTPUT:
444 if (ctx->type == PIPE_SHADER_TESS_CTRL)
445 break;
446 default:
447 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
448 i->Src[j].Register.File,
449 i->Src[j].Register.Dimension);
450 return -EINVAL;
451 }
452 }
453 }
454 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
455 if (i->Dst[j].Register.Dimension) {
456 if (ctx->type == PIPE_SHADER_TESS_CTRL)
457 continue;
458 R600_ERR("unsupported dst (dimension)\n");
459 return -EINVAL;
460 }
461 }
462 return 0;
463 }
464
465 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
466 {
467 if (interpolate == TGSI_INTERPOLATE_COLOR ||
468 interpolate == TGSI_INTERPOLATE_LINEAR ||
469 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
470 {
471 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
472 int loc;
473
474 switch(location) {
475 case TGSI_INTERPOLATE_LOC_CENTER:
476 loc = 1;
477 break;
478 case TGSI_INTERPOLATE_LOC_CENTROID:
479 loc = 2;
480 break;
481 case TGSI_INTERPOLATE_LOC_SAMPLE:
482 default:
483 loc = 0; break;
484 }
485
486 return is_linear * 3 + loc;
487 }
488
489 return -1;
490 }
491
492 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
493 int input)
494 {
495 int i = eg_get_interpolator_index(
496 ctx->shader->input[input].interpolate,
497 ctx->shader->input[input].interpolate_location);
498 assert(i >= 0);
499 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
500 }
501
502 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
503 {
504 int i, r;
505 struct r600_bytecode_alu alu;
506 int gpr = 0, base_chan = 0;
507 int ij_index = ctx->shader->input[input].ij_index;
508
509 /* work out gpr and base_chan from index */
510 gpr = ij_index / 2;
511 base_chan = (2 * (ij_index % 2)) + 1;
512
513 for (i = 0; i < 8; i++) {
514 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
515
516 if (i < 4)
517 alu.op = ALU_OP2_INTERP_ZW;
518 else
519 alu.op = ALU_OP2_INTERP_XY;
520
521 if ((i > 1) && (i < 6)) {
522 alu.dst.sel = ctx->shader->input[input].gpr;
523 alu.dst.write = 1;
524 }
525
526 alu.dst.chan = i % 4;
527
528 alu.src[0].sel = gpr;
529 alu.src[0].chan = (base_chan - (i % 2));
530
531 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
532
533 alu.bank_swizzle_force = SQ_ALU_VEC_210;
534 if ((i % 4) == 3)
535 alu.last = 1;
536 r = r600_bytecode_add_alu(ctx->bc, &alu);
537 if (r)
538 return r;
539 }
540 return 0;
541 }
542
543 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
544 {
545 int i, r;
546 struct r600_bytecode_alu alu;
547
548 for (i = 0; i < 4; i++) {
549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
550
551 alu.op = ALU_OP1_INTERP_LOAD_P0;
552
553 alu.dst.sel = ctx->shader->input[input].gpr;
554 alu.dst.write = 1;
555
556 alu.dst.chan = i;
557
558 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
559 alu.src[0].chan = i;
560
561 if (i == 3)
562 alu.last = 1;
563 r = r600_bytecode_add_alu(ctx->bc, &alu);
564 if (r)
565 return r;
566 }
567 return 0;
568 }
569
570 /*
571 * Special export handling in shaders
572 *
573 * shader export ARRAY_BASE for EXPORT_POS:
574 * 60 is position
575 * 61 is misc vector
576 * 62, 63 are clip distance vectors
577 *
578 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
579 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
580 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
581 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
582 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
583 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
584 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
585 * exclusive from render target index)
586 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
587 *
588 *
589 * shader export ARRAY_BASE for EXPORT_PIXEL:
590 * 0-7 CB targets
591 * 61 computed Z vector
592 *
593 * The use of the values exported in the computed Z vector are controlled
594 * by DB_SHADER_CONTROL:
595 * Z_EXPORT_ENABLE - Z as a float in RED
596 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
597 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
598 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
599 * DB_SOURCE_FORMAT - export control restrictions
600 *
601 */
602
603
604 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
605 static int r600_spi_sid(struct r600_shader_io * io)
606 {
607 int index, name = io->name;
608
609 /* These params are handled differently, they don't need
610 * semantic indices, so we'll use 0 for them.
611 */
612 if (name == TGSI_SEMANTIC_POSITION ||
613 name == TGSI_SEMANTIC_PSIZE ||
614 name == TGSI_SEMANTIC_EDGEFLAG ||
615 name == TGSI_SEMANTIC_FACE ||
616 name == TGSI_SEMANTIC_SAMPLEMASK)
617 index = 0;
618 else {
619 if (name == TGSI_SEMANTIC_GENERIC) {
620 /* For generic params simply use sid from tgsi */
621 index = io->sid;
622 } else {
623 /* For non-generic params - pack name and sid into 8 bits */
624 index = 0x80 | (name<<3) | (io->sid);
625 }
626
627 /* Make sure that all really used indices have nonzero value, so
628 * we can just compare it to 0 later instead of comparing the name
629 * with different values to detect special cases. */
630 index++;
631 }
632
633 return index;
634 };
635
636 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
637 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
638 {
639 switch (semantic_name) {
640 case TGSI_SEMANTIC_POSITION:
641 return 0;
642 case TGSI_SEMANTIC_PSIZE:
643 return 1;
644 case TGSI_SEMANTIC_CLIPDIST:
645 assert(index <= 1);
646 return 2 + index;
647 case TGSI_SEMANTIC_GENERIC:
648 if (index <= 63-4)
649 return 4 + index - 9;
650 else
651 /* same explanation as in the default statement,
652 * the only user hitting this is st/nine.
653 */
654 return 0;
655
656 /* patch indices are completely separate and thus start from 0 */
657 case TGSI_SEMANTIC_TESSOUTER:
658 return 0;
659 case TGSI_SEMANTIC_TESSINNER:
660 return 1;
661 case TGSI_SEMANTIC_PATCH:
662 return 2 + index;
663
664 default:
665 /* Don't fail here. The result of this function is only used
666 * for LS, TCS, TES, and GS, where legacy GL semantics can't
667 * occur, but this function is called for all vertex shaders
668 * before it's known whether LS will be compiled or not.
669 */
670 return 0;
671 }
672 }
673
674 /* turn input into interpolate on EG */
675 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
676 {
677 int r = 0;
678
679 if (ctx->shader->input[index].spi_sid) {
680 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
681 if (ctx->shader->input[index].interpolate > 0) {
682 evergreen_interp_assign_ij_index(ctx, index);
683 r = evergreen_interp_alu(ctx, index);
684 } else {
685 r = evergreen_interp_flat(ctx, index);
686 }
687 }
688 return r;
689 }
690
691 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
692 {
693 struct r600_bytecode_alu alu;
694 int i, r;
695 int gpr_front = ctx->shader->input[front].gpr;
696 int gpr_back = ctx->shader->input[back].gpr;
697
698 for (i = 0; i < 4; i++) {
699 memset(&alu, 0, sizeof(alu));
700 alu.op = ALU_OP3_CNDGT;
701 alu.is_op3 = 1;
702 alu.dst.write = 1;
703 alu.dst.sel = gpr_front;
704 alu.src[0].sel = ctx->face_gpr;
705 alu.src[1].sel = gpr_front;
706 alu.src[2].sel = gpr_back;
707
708 alu.dst.chan = i;
709 alu.src[1].chan = i;
710 alu.src[2].chan = i;
711 alu.last = (i==3);
712
713 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
714 return r;
715 }
716
717 return 0;
718 }
719
720 /* execute a single slot ALU calculation */
721 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
722 int dst_sel, int dst_chan,
723 int src0_sel, unsigned src0_chan_val,
724 int src1_sel, unsigned src1_chan_val)
725 {
726 struct r600_bytecode_alu alu;
727 int r, i;
728
729 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
730 for (i = 0; i < 4; i++) {
731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
732 alu.op = op;
733 alu.src[0].sel = src0_sel;
734 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
735 alu.src[0].value = src0_chan_val;
736 else
737 alu.src[0].chan = src0_chan_val;
738 alu.src[1].sel = src1_sel;
739 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
740 alu.src[1].value = src1_chan_val;
741 else
742 alu.src[1].chan = src1_chan_val;
743 alu.dst.sel = dst_sel;
744 alu.dst.chan = i;
745 alu.dst.write = i == dst_chan;
746 alu.last = (i == 3);
747 r = r600_bytecode_add_alu(ctx->bc, &alu);
748 if (r)
749 return r;
750 }
751 return 0;
752 }
753
754 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
755 alu.op = op;
756 alu.src[0].sel = src0_sel;
757 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
758 alu.src[0].value = src0_chan_val;
759 else
760 alu.src[0].chan = src0_chan_val;
761 alu.src[1].sel = src1_sel;
762 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
763 alu.src[1].value = src1_chan_val;
764 else
765 alu.src[1].chan = src1_chan_val;
766 alu.dst.sel = dst_sel;
767 alu.dst.chan = dst_chan;
768 alu.dst.write = 1;
769 alu.last = 1;
770 r = r600_bytecode_add_alu(ctx->bc, &alu);
771 if (r)
772 return r;
773 return 0;
774 }
775
776 /* execute a single slot ALU calculation */
777 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
778 int dst_sel, int dst_chan,
779 int src0_sel, unsigned src0_chan_val,
780 int src1_sel, unsigned src1_chan_val,
781 int src2_sel, unsigned src2_chan_val)
782 {
783 struct r600_bytecode_alu alu;
784 int r;
785
786 /* validate this for other ops */
787 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT || op == ALU_OP3_BFE_UINT);
788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
789 alu.op = op;
790 alu.src[0].sel = src0_sel;
791 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
792 alu.src[0].value = src0_chan_val;
793 else
794 alu.src[0].chan = src0_chan_val;
795 alu.src[1].sel = src1_sel;
796 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
797 alu.src[1].value = src1_chan_val;
798 else
799 alu.src[1].chan = src1_chan_val;
800 alu.src[2].sel = src2_sel;
801 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
802 alu.src[2].value = src2_chan_val;
803 else
804 alu.src[2].chan = src2_chan_val;
805 alu.dst.sel = dst_sel;
806 alu.dst.chan = dst_chan;
807 alu.is_op3 = 1;
808 alu.last = 1;
809 r = r600_bytecode_add_alu(ctx->bc, &alu);
810 if (r)
811 return r;
812 return 0;
813 }
814
815 /* put it in temp_reg.x */
816 static int get_lds_offset0(struct r600_shader_ctx *ctx,
817 int rel_patch_chan,
818 int temp_reg, bool is_patch_var)
819 {
820 int r;
821
822 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
823 /* ADD
824 Dimension - patch0_offset (input_vals.z),
825 Non-dim - patch0_data_offset (input_vals.w)
826 */
827 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
828 temp_reg, 0,
829 ctx->tess_output_info, 0,
830 0, rel_patch_chan,
831 ctx->tess_output_info, is_patch_var ? 3 : 2);
832 if (r)
833 return r;
834 return 0;
835 }
836
837 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
838 {
839 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
840 }
841
842 static int r600_get_temp(struct r600_shader_ctx *ctx)
843 {
844 return ctx->temp_reg + ctx->max_driver_temp_used++;
845 }
846
847 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
848 {
849 int i;
850 i = ctx->shader->noutput++;
851 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
852 ctx->shader->output[i].sid = 0;
853 ctx->shader->output[i].gpr = 0;
854 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
855 ctx->shader->output[i].write_mask = 0x4;
856 ctx->shader->output[i].spi_sid = prim_id_sid;
857
858 return 0;
859 }
860
861 static int tgsi_barrier(struct r600_shader_ctx *ctx)
862 {
863 struct r600_bytecode_alu alu;
864 int r;
865
866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
867 alu.op = ctx->inst_info->op;
868 alu.last = 1;
869
870 r = r600_bytecode_add_alu(ctx->bc, &alu);
871 if (r)
872 return r;
873 return 0;
874 }
875
876 static void choose_spill_arrays(struct r600_shader_ctx *ctx, int *regno, unsigned *scratch_space_needed)
877 {
878 // pick largest array and spill it, repeat until the number of temps is under limit or we run out of arrays
879 unsigned n = ctx->info.array_max[TGSI_FILE_TEMPORARY];
880 unsigned narrays_left = n;
881 bool *spilled = ctx->spilled_arrays; // assumed calloc:ed
882
883 *scratch_space_needed = 0;
884 while (*regno > 124 && narrays_left) {
885 unsigned i;
886 unsigned largest = 0;
887 unsigned largest_index = 0;
888
889 for (i = 0; i < n; i++) {
890 unsigned size = ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
891 if (!spilled[i] && size > largest) {
892 largest = size;
893 largest_index = i;
894 }
895 }
896
897 spilled[largest_index] = true;
898 *regno -= largest;
899 *scratch_space_needed += largest;
900
901 narrays_left --;
902 }
903
904 if (narrays_left == 0) {
905 ctx->info.indirect_files &= ~(1 << TGSI_FILE_TEMPORARY);
906 }
907 }
908
909 /* Take spilled temp arrays into account when translating tgsi register
910 * indexes into r600 gprs if spilled is false, or scratch array offset if
911 * spilled is true */
912 static int map_tgsi_reg_index_to_r600_gpr(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index, bool *spilled)
913 {
914 unsigned i;
915 unsigned spilled_size = 0;
916
917 for (i = 0; i < ctx->info.array_max[TGSI_FILE_TEMPORARY]; i++) {
918 if (tgsi_reg_index >= ctx->array_infos[i].range.First && tgsi_reg_index <= ctx->array_infos[i].range.Last) {
919 if (ctx->spilled_arrays[i]) {
920 /* vec4 index into spilled scratch memory */
921 *spilled = true;
922 return tgsi_reg_index - ctx->array_infos[i].range.First + spilled_size;
923 }
924 else {
925 /* regular GPR array */
926 *spilled = false;
927 return tgsi_reg_index - spilled_size + ctx->file_offset[TGSI_FILE_TEMPORARY];
928 }
929 }
930
931 if (tgsi_reg_index < ctx->array_infos[i].range.First)
932 break;
933 if (ctx->spilled_arrays[i]) {
934 spilled_size += ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
935 }
936 }
937
938 /* regular GPR index, minus the holes from spilled arrays */
939 *spilled = false;
940
941 return tgsi_reg_index - spilled_size + ctx->file_offset[TGSI_FILE_TEMPORARY];
942 }
943
944 /* look up spill area base offset and array size for a spilled temp array */
945 static void get_spilled_array_base_and_size(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index,
946 unsigned *array_base, unsigned *array_size)
947 {
948 unsigned i;
949 unsigned offset = 0;
950
951 for (i = 0; i < ctx->info.array_max[TGSI_FILE_TEMPORARY]; i++) {
952 if (ctx->spilled_arrays[i]) {
953 unsigned size = ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
954
955 if (tgsi_reg_index >= ctx->array_infos[i].range.First && tgsi_reg_index <= ctx->array_infos[i].range.Last) {
956 *array_base = offset;
957 *array_size = size - 1; /* hw counts from 1 */
958
959 return;
960 }
961
962 offset += size;
963 }
964 }
965 }
966
967 static int tgsi_declaration(struct r600_shader_ctx *ctx)
968 {
969 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
970 int r, i, j, count = d->Range.Last - d->Range.First + 1;
971
972 switch (d->Declaration.File) {
973 case TGSI_FILE_INPUT:
974 for (j = 0; j < count; j++) {
975 i = ctx->shader->ninput + j;
976 assert(i < ARRAY_SIZE(ctx->shader->input));
977 ctx->shader->input[i].name = d->Semantic.Name;
978 ctx->shader->input[i].sid = d->Semantic.Index + j;
979 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
980 ctx->shader->input[i].interpolate_location = d->Interp.Location;
981 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
982 if (ctx->type == PIPE_SHADER_FRAGMENT) {
983 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
984 switch (ctx->shader->input[i].name) {
985 case TGSI_SEMANTIC_FACE:
986 if (ctx->face_gpr != -1)
987 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
988 else
989 ctx->face_gpr = ctx->shader->input[i].gpr;
990 break;
991 case TGSI_SEMANTIC_COLOR:
992 ctx->colors_used++;
993 break;
994 case TGSI_SEMANTIC_POSITION:
995 ctx->fragcoord_input = i;
996 break;
997 case TGSI_SEMANTIC_PRIMID:
998 /* set this for now */
999 ctx->shader->gs_prim_id_input = true;
1000 ctx->shader->ps_prim_id_input = i;
1001 break;
1002 }
1003 if (ctx->bc->chip_class >= EVERGREEN) {
1004 if ((r = evergreen_interp_input(ctx, i)))
1005 return r;
1006 }
1007 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
1008 /* FIXME probably skip inputs if they aren't passed in the ring */
1009 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
1010 ctx->next_ring_offset += 16;
1011 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
1012 ctx->shader->gs_prim_id_input = true;
1013 }
1014 }
1015 ctx->shader->ninput += count;
1016 break;
1017 case TGSI_FILE_OUTPUT:
1018 for (j = 0; j < count; j++) {
1019 i = ctx->shader->noutput + j;
1020 assert(i < ARRAY_SIZE(ctx->shader->output));
1021 ctx->shader->output[i].name = d->Semantic.Name;
1022 ctx->shader->output[i].sid = d->Semantic.Index + j;
1023 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
1024 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
1025 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
1026 if (ctx->type == PIPE_SHADER_VERTEX ||
1027 ctx->type == PIPE_SHADER_GEOMETRY ||
1028 ctx->type == PIPE_SHADER_TESS_EVAL) {
1029 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
1030 switch (d->Semantic.Name) {
1031 case TGSI_SEMANTIC_CLIPDIST:
1032 break;
1033 case TGSI_SEMANTIC_PSIZE:
1034 ctx->shader->vs_out_misc_write = 1;
1035 ctx->shader->vs_out_point_size = 1;
1036 break;
1037 case TGSI_SEMANTIC_EDGEFLAG:
1038 ctx->shader->vs_out_misc_write = 1;
1039 ctx->shader->vs_out_edgeflag = 1;
1040 ctx->edgeflag_output = i;
1041 break;
1042 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1043 ctx->shader->vs_out_misc_write = 1;
1044 ctx->shader->vs_out_viewport = 1;
1045 break;
1046 case TGSI_SEMANTIC_LAYER:
1047 ctx->shader->vs_out_misc_write = 1;
1048 ctx->shader->vs_out_layer = 1;
1049 break;
1050 case TGSI_SEMANTIC_CLIPVERTEX:
1051 ctx->clip_vertex_write = TRUE;
1052 ctx->cv_output = i;
1053 break;
1054 }
1055 if (ctx->type == PIPE_SHADER_GEOMETRY) {
1056 ctx->gs_out_ring_offset += 16;
1057 }
1058 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
1059 switch (d->Semantic.Name) {
1060 case TGSI_SEMANTIC_COLOR:
1061 ctx->shader->nr_ps_max_color_exports++;
1062 break;
1063 }
1064 }
1065 }
1066 ctx->shader->noutput += count;
1067 break;
1068 case TGSI_FILE_TEMPORARY:
1069 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
1070 if (d->Array.ArrayID) {
1071 bool spilled;
1072 unsigned idx = map_tgsi_reg_index_to_r600_gpr(ctx,
1073 d->Range.First,
1074 &spilled);
1075
1076 if (!spilled) {
1077 r600_add_gpr_array(ctx->shader, idx,
1078 d->Range.Last - d->Range.First + 1, 0x0F);
1079 }
1080 }
1081 }
1082 break;
1083
1084 case TGSI_FILE_CONSTANT:
1085 case TGSI_FILE_SAMPLER:
1086 case TGSI_FILE_SAMPLER_VIEW:
1087 case TGSI_FILE_ADDRESS:
1088 case TGSI_FILE_BUFFER:
1089 case TGSI_FILE_IMAGE:
1090 case TGSI_FILE_MEMORY:
1091 break;
1092
1093 case TGSI_FILE_HW_ATOMIC:
1094 i = ctx->shader->nhwatomic_ranges;
1095 ctx->shader->atomics[i].start = d->Range.First;
1096 ctx->shader->atomics[i].end = d->Range.Last;
1097 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
1098 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
1099 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
1100 ctx->shader->nhwatomic_ranges++;
1101 ctx->shader->nhwatomic += count;
1102 break;
1103
1104 case TGSI_FILE_SYSTEM_VALUE:
1105 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
1106 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
1107 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
1108 break; /* Already handled from allocate_system_value_inputs */
1109 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
1110 break;
1111 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1112 break;
1113 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1114 break;
1115 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1116 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1117 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1118 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1119 unsigned temp_reg = r600_get_temp(ctx);
1120
1121 r = get_lds_offset0(ctx, 2, temp_reg, true);
1122 if (r)
1123 return r;
1124
1125 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1126 temp_reg, 0,
1127 temp_reg, 0,
1128 V_SQ_ALU_SRC_LITERAL, param * 16);
1129 if (r)
1130 return r;
1131
1132 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
1133 }
1134 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1135 /* MOV r1.x, r0.x;
1136 MOV r1.y, r0.y;
1137 */
1138 for (i = 0; i < 2; i++) {
1139 struct r600_bytecode_alu alu;
1140 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1141 alu.op = ALU_OP1_MOV;
1142 alu.src[0].sel = 0;
1143 alu.src[0].chan = 0 + i;
1144 alu.dst.sel = 1;
1145 alu.dst.chan = 0 + i;
1146 alu.dst.write = 1;
1147 alu.last = (i == 1) ? 1 : 0;
1148 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1149 return r;
1150 }
1151 /* ADD r1.z, 1.0f, -r0.x */
1152 struct r600_bytecode_alu alu;
1153 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1154 alu.op = ALU_OP2_ADD;
1155 alu.src[0].sel = V_SQ_ALU_SRC_1;
1156 alu.src[1].sel = 1;
1157 alu.src[1].chan = 0;
1158 alu.src[1].neg = 1;
1159 alu.dst.sel = 1;
1160 alu.dst.chan = 2;
1161 alu.dst.write = 1;
1162 alu.last = 1;
1163 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1164 return r;
1165
1166 /* ADD r1.z, r1.z, -r1.y */
1167 alu.op = ALU_OP2_ADD;
1168 alu.src[0].sel = 1;
1169 alu.src[0].chan = 2;
1170 alu.src[1].sel = 1;
1171 alu.src[1].chan = 1;
1172 alu.src[1].neg = 1;
1173 alu.dst.sel = 1;
1174 alu.dst.chan = 2;
1175 alu.dst.write = 1;
1176 alu.last = 1;
1177 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1178 return r;
1179 break;
1180 }
1181 break;
1182 default:
1183 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1184 return -EINVAL;
1185 }
1186 return 0;
1187 }
1188
1189 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1190 {
1191 struct tgsi_parse_context parse;
1192 struct {
1193 boolean enabled;
1194 int *reg;
1195 unsigned name, alternate_name;
1196 } inputs[2] = {
1197 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1198
1199 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1200 };
1201 int num_regs = 0;
1202 unsigned k, i;
1203
1204 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1205 return 0;
1206 }
1207
1208 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1209 while (!tgsi_parse_end_of_tokens(&parse)) {
1210 tgsi_parse_token(&parse);
1211
1212 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1213 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1214 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1215 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1216 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1217 {
1218 int interpolate, location, k;
1219
1220 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1221 location = TGSI_INTERPOLATE_LOC_CENTER;
1222 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1223 location = TGSI_INTERPOLATE_LOC_CENTER;
1224 /* Needs sample positions, currently those are always available */
1225 } else {
1226 location = TGSI_INTERPOLATE_LOC_CENTROID;
1227 }
1228
1229 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1230 k = eg_get_interpolator_index(interpolate, location);
1231 if (k >= 0)
1232 ctx->eg_interpolators[k].enabled = true;
1233 }
1234 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1235 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1236 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1237 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1238 if (d->Semantic.Name == inputs[k].name ||
1239 d->Semantic.Name == inputs[k].alternate_name) {
1240 inputs[k].enabled = true;
1241 }
1242 }
1243 }
1244 }
1245 }
1246
1247 tgsi_parse_free(&parse);
1248
1249 if (ctx->info.reads_samplemask &&
1250 (ctx->info.uses_linear_sample || ctx->info.uses_linear_sample)) {
1251 inputs[1].enabled = true;
1252 }
1253
1254 if (ctx->bc->chip_class >= EVERGREEN) {
1255 int num_baryc = 0;
1256 /* assign gpr to each interpolator according to priority */
1257 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1258 if (ctx->eg_interpolators[i].enabled) {
1259 ctx->eg_interpolators[i].ij_index = num_baryc;
1260 num_baryc++;
1261 }
1262 }
1263 num_baryc = (num_baryc + 1) >> 1;
1264 gpr_offset += num_baryc;
1265 }
1266
1267 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1268 boolean enabled = inputs[i].enabled;
1269 int *reg = inputs[i].reg;
1270 unsigned name = inputs[i].name;
1271
1272 if (enabled) {
1273 int gpr = gpr_offset + num_regs++;
1274 ctx->shader->nsys_inputs++;
1275
1276 // add to inputs, allocate a gpr
1277 k = ctx->shader->ninput++;
1278 ctx->shader->input[k].name = name;
1279 ctx->shader->input[k].sid = 0;
1280 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1281 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1282 *reg = ctx->shader->input[k].gpr = gpr;
1283 }
1284 }
1285
1286 return gpr_offset + num_regs;
1287 }
1288
1289 /*
1290 * for evergreen we need to scan the shader to find the number of GPRs we need to
1291 * reserve for interpolation and system values
1292 *
1293 * we need to know if we are going to emit any sample or centroid inputs
1294 * if perspective and linear are required
1295 */
1296 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1297 {
1298 unsigned i;
1299
1300 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1301
1302 /*
1303 * Could get this information from the shader info. But right now
1304 * we interpolate all declared inputs, whereas the shader info will
1305 * only contain the bits if the inputs are actually used, so it might
1306 * not be safe...
1307 */
1308 for (i = 0; i < ctx->info.num_inputs; i++) {
1309 int k;
1310 /* skip position/face/mask/sampleid */
1311 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1312 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1313 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1314 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1315 continue;
1316
1317 k = eg_get_interpolator_index(
1318 ctx->info.input_interpolate[i],
1319 ctx->info.input_interpolate_loc[i]);
1320 if (k >= 0)
1321 ctx->eg_interpolators[k].enabled = TRUE;
1322 }
1323
1324 /* XXX PULL MODEL and LINE STIPPLE */
1325
1326 return allocate_system_value_inputs(ctx, 0);
1327 }
1328
1329 /* sample_id_sel == NULL means fetch for current sample */
1330 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1331 {
1332 struct r600_bytecode_vtx vtx;
1333 int r, t1;
1334
1335 t1 = r600_get_temp(ctx);
1336
1337 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1338 vtx.op = FETCH_OP_VFETCH;
1339 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1340 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1341 if (sample_id == NULL) {
1342 assert(ctx->fixed_pt_position_gpr != -1);
1343
1344 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1345 vtx.src_sel_x = 3;
1346 }
1347 else {
1348 struct r600_bytecode_alu alu;
1349
1350 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1351 alu.op = ALU_OP1_MOV;
1352 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1353 alu.dst.sel = t1;
1354 alu.dst.write = 1;
1355 alu.last = 1;
1356 r = r600_bytecode_add_alu(ctx->bc, &alu);
1357 if (r)
1358 return r;
1359
1360 vtx.src_gpr = t1;
1361 vtx.src_sel_x = 0;
1362 }
1363 vtx.mega_fetch_count = 16;
1364 vtx.dst_gpr = t1;
1365 vtx.dst_sel_x = 0;
1366 vtx.dst_sel_y = 1;
1367 vtx.dst_sel_z = 2;
1368 vtx.dst_sel_w = 3;
1369 vtx.data_format = FMT_32_32_32_32_FLOAT;
1370 vtx.num_format_all = 2;
1371 vtx.format_comp_all = 1;
1372 vtx.use_const_fields = 0;
1373 vtx.offset = 0;
1374 vtx.endian = r600_endian_swap(32);
1375 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1376
1377 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1378 if (r)
1379 return r;
1380
1381 return t1;
1382 }
1383
1384 static int eg_load_helper_invocation(struct r600_shader_ctx *ctx)
1385 {
1386 int r;
1387 struct r600_bytecode_alu alu;
1388
1389 /* do a vtx fetch with wqm set on the vtx fetch */
1390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1391 alu.op = ALU_OP1_MOV;
1392 alu.dst.sel = ctx->helper_invoc_reg;
1393 alu.dst.chan = 0;
1394 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1395 alu.src[0].value = 0xffffffff;
1396 alu.dst.write = 1;
1397 alu.last = 1;
1398 r = r600_bytecode_add_alu(ctx->bc, &alu);
1399 if (r)
1400 return r;
1401
1402 /* do a vtx fetch in VPM mode */
1403 struct r600_bytecode_vtx vtx;
1404 memset(&vtx, 0, sizeof(vtx));
1405 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
1406 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1407 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1408 vtx.src_gpr = 0;
1409 vtx.mega_fetch_count = 16; /* no idea here really... */
1410 vtx.dst_gpr = ctx->helper_invoc_reg;
1411 vtx.dst_sel_x = 4;
1412 vtx.dst_sel_y = 7; /* SEL_Y */
1413 vtx.dst_sel_z = 7; /* SEL_Z */
1414 vtx.dst_sel_w = 7; /* SEL_W */
1415 vtx.data_format = FMT_32;
1416 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
1417 return r;
1418 ctx->bc->cf_last->vpm = 1;
1419 return 0;
1420 }
1421
1422 static int cm_load_helper_invocation(struct r600_shader_ctx *ctx)
1423 {
1424 int r;
1425 struct r600_bytecode_alu alu;
1426
1427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1428 alu.op = ALU_OP1_MOV;
1429 alu.dst.sel = ctx->helper_invoc_reg;
1430 alu.dst.chan = 0;
1431 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1432 alu.src[0].value = 0xffffffff;
1433 alu.dst.write = 1;
1434 alu.last = 1;
1435 r = r600_bytecode_add_alu(ctx->bc, &alu);
1436 if (r)
1437 return r;
1438
1439 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1440 alu.op = ALU_OP1_MOV;
1441 alu.dst.sel = ctx->helper_invoc_reg;
1442 alu.dst.chan = 0;
1443 alu.src[0].sel = V_SQ_ALU_SRC_0;
1444 alu.dst.write = 1;
1445 alu.last = 1;
1446 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_VALID_PIXEL_MODE);
1447 if (r)
1448 return r;
1449
1450 return ctx->helper_invoc_reg;
1451 }
1452
1453 static int load_block_grid_size(struct r600_shader_ctx *ctx, bool load_block)
1454 {
1455 struct r600_bytecode_vtx vtx;
1456 int r, t1;
1457
1458 if (ctx->cs_block_size_loaded)
1459 return ctx->cs_block_size_reg;
1460 if (ctx->cs_grid_size_loaded)
1461 return ctx->cs_grid_size_reg;
1462
1463 t1 = load_block ? ctx->cs_block_size_reg : ctx->cs_grid_size_reg;
1464 struct r600_bytecode_alu alu;
1465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1466 alu.op = ALU_OP1_MOV;
1467 alu.src[0].sel = V_SQ_ALU_SRC_0;
1468 alu.dst.sel = t1;
1469 alu.dst.write = 1;
1470 alu.last = 1;
1471 r = r600_bytecode_add_alu(ctx->bc, &alu);
1472 if (r)
1473 return r;
1474
1475 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1476 vtx.op = FETCH_OP_VFETCH;
1477 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1478 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1479 vtx.src_gpr = t1;
1480 vtx.src_sel_x = 0;
1481
1482 vtx.mega_fetch_count = 16;
1483 vtx.dst_gpr = t1;
1484 vtx.dst_sel_x = 0;
1485 vtx.dst_sel_y = 1;
1486 vtx.dst_sel_z = 2;
1487 vtx.dst_sel_w = 7;
1488 vtx.data_format = FMT_32_32_32_32;
1489 vtx.num_format_all = 1;
1490 vtx.format_comp_all = 0;
1491 vtx.use_const_fields = 0;
1492 vtx.offset = load_block ? 0 : 16; // first element is size of buffer
1493 vtx.endian = r600_endian_swap(32);
1494 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1495
1496 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1497 if (r)
1498 return r;
1499
1500 if (load_block)
1501 ctx->cs_block_size_loaded = true;
1502 else
1503 ctx->cs_grid_size_loaded = true;
1504 return t1;
1505 }
1506
1507 static void tgsi_src(struct r600_shader_ctx *ctx,
1508 const struct tgsi_full_src_register *tgsi_src,
1509 struct r600_shader_src *r600_src)
1510 {
1511 memset(r600_src, 0, sizeof(*r600_src));
1512 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1513 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1514 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1515 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1516 r600_src->neg = tgsi_src->Register.Negate;
1517 r600_src->abs = tgsi_src->Register.Absolute;
1518
1519 if (tgsi_src->Register.File == TGSI_FILE_TEMPORARY) {
1520 bool spilled;
1521 unsigned idx;
1522
1523 idx = map_tgsi_reg_index_to_r600_gpr(ctx, tgsi_src->Register.Index, &spilled);
1524
1525 if (spilled) {
1526 int reg = r600_get_temp(ctx);
1527 int r;
1528
1529 r600_src->sel = reg;
1530
1531 if (ctx->bc->chip_class < R700) {
1532 struct r600_bytecode_output cf;
1533
1534 memset(&cf, 0, sizeof(struct r600_bytecode_output));
1535 cf.op = CF_OP_MEM_SCRATCH;
1536 cf.elem_size = 3;
1537 cf.gpr = reg;
1538 cf.comp_mask = 0xF;
1539 cf.swizzle_x = 0;
1540 cf.swizzle_y = 1;
1541 cf.swizzle_z = 2;
1542 cf.swizzle_w = 3;
1543 cf.burst_count = 1;
1544
1545 get_spilled_array_base_and_size(ctx, tgsi_src->Register.Index,
1546 &cf.array_base, &cf.array_size);
1547
1548 if (tgsi_src->Register.Indirect) {
1549 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
1550 cf.index_gpr = ctx->bc->ar_reg;
1551 }
1552 else {
1553 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ;
1554 cf.array_base += idx;
1555 cf.array_size = 0;
1556 }
1557
1558 r = r600_bytecode_add_output(ctx->bc, &cf);
1559 }
1560 else {
1561 struct r600_bytecode_vtx vtx;
1562
1563 if (r600_bytecode_get_need_wait_ack(ctx->bc)) {
1564 r600_bytecode_need_wait_ack(ctx->bc, false);
1565 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
1566 }
1567
1568 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1569 vtx.op = FETCH_OP_READ_SCRATCH;
1570 vtx.dst_gpr = reg;
1571 vtx.uncached = 1; // Must bypass cache since prior spill written in same invocation
1572 vtx.elem_size = 3;
1573 vtx.data_format = FMT_32_32_32_32;
1574 vtx.num_format_all = V_038010_SQ_NUM_FORMAT_INT;
1575 vtx.dst_sel_x = tgsi_src->Register.SwizzleX;
1576 vtx.dst_sel_y = tgsi_src->Register.SwizzleY;
1577 vtx.dst_sel_z = tgsi_src->Register.SwizzleZ;
1578 vtx.dst_sel_w = tgsi_src->Register.SwizzleW;
1579
1580 get_spilled_array_base_and_size(ctx, tgsi_src->Register.Index,
1581 &vtx.array_base, &vtx.array_size);
1582
1583 if (tgsi_src->Register.Indirect) {
1584 vtx.indexed = 1;
1585 vtx.src_gpr = ctx->bc->ar_reg;
1586 }
1587 else {
1588 vtx.array_base += idx;
1589 vtx.array_size = 0;
1590 }
1591
1592 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1593 }
1594
1595 if (r)
1596 return;
1597 }
1598 else {
1599 if (tgsi_src->Register.Indirect)
1600 r600_src->rel = V_SQ_REL_RELATIVE;
1601
1602 r600_src->sel = idx;
1603 }
1604
1605 return;
1606 }
1607
1608 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1609 int index;
1610 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1611 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1612 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1613
1614 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1615 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1616 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1617 return;
1618 }
1619 index = tgsi_src->Register.Index;
1620 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1621 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1622 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1623 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1624 r600_src->swizzle[0] = 2; // Z value
1625 r600_src->swizzle[1] = 2;
1626 r600_src->swizzle[2] = 2;
1627 r600_src->swizzle[3] = 2;
1628 r600_src->sel = ctx->face_gpr;
1629 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1630 r600_src->swizzle[0] = 3; // W value
1631 r600_src->swizzle[1] = 3;
1632 r600_src->swizzle[2] = 3;
1633 r600_src->swizzle[3] = 3;
1634 r600_src->sel = ctx->fixed_pt_position_gpr;
1635 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1636 r600_src->swizzle[0] = 0;
1637 r600_src->swizzle[1] = 1;
1638 r600_src->swizzle[2] = 4;
1639 r600_src->swizzle[3] = 4;
1640 r600_src->sel = load_sample_position(ctx, NULL, -1);
1641 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1642 r600_src->swizzle[0] = 3;
1643 r600_src->swizzle[1] = 3;
1644 r600_src->swizzle[2] = 3;
1645 r600_src->swizzle[3] = 3;
1646 r600_src->sel = 0;
1647 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1648 r600_src->swizzle[0] = 0;
1649 r600_src->swizzle[1] = 0;
1650 r600_src->swizzle[2] = 0;
1651 r600_src->swizzle[3] = 0;
1652 r600_src->sel = 0;
1653 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_THREAD_ID) {
1654 r600_src->sel = 0;
1655 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_ID) {
1656 r600_src->sel = 1;
1657 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1658 r600_src->swizzle[0] = 3;
1659 r600_src->swizzle[1] = 3;
1660 r600_src->swizzle[2] = 3;
1661 r600_src->swizzle[3] = 3;
1662 r600_src->sel = 1;
1663 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1664 r600_src->swizzle[0] = 2;
1665 r600_src->swizzle[1] = 2;
1666 r600_src->swizzle[2] = 2;
1667 r600_src->swizzle[3] = 2;
1668 r600_src->sel = 0;
1669 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1670 r600_src->sel = 1;
1671 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1672 r600_src->sel = 3;
1673 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1674 r600_src->sel = 2;
1675 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1676 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1677 r600_src->sel = ctx->tess_input_info;
1678 r600_src->swizzle[0] = 2;
1679 r600_src->swizzle[1] = 2;
1680 r600_src->swizzle[2] = 2;
1681 r600_src->swizzle[3] = 2;
1682 } else {
1683 r600_src->sel = ctx->tess_input_info;
1684 r600_src->swizzle[0] = 3;
1685 r600_src->swizzle[1] = 3;
1686 r600_src->swizzle[2] = 3;
1687 r600_src->swizzle[3] = 3;
1688 }
1689 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1690 r600_src->sel = 0;
1691 r600_src->swizzle[0] = 0;
1692 r600_src->swizzle[1] = 0;
1693 r600_src->swizzle[2] = 0;
1694 r600_src->swizzle[3] = 0;
1695 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1696 r600_src->sel = 0;
1697 r600_src->swizzle[0] = 3;
1698 r600_src->swizzle[1] = 3;
1699 r600_src->swizzle[2] = 3;
1700 r600_src->swizzle[3] = 3;
1701 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_GRID_SIZE) {
1702 r600_src->sel = load_block_grid_size(ctx, false);
1703 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_SIZE) {
1704 r600_src->sel = load_block_grid_size(ctx, true);
1705 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_HELPER_INVOCATION) {
1706 r600_src->sel = ctx->helper_invoc_reg;
1707 r600_src->swizzle[0] = 0;
1708 r600_src->swizzle[1] = 0;
1709 r600_src->swizzle[2] = 0;
1710 r600_src->swizzle[3] = 0;
1711 }
1712 } else {
1713 if (tgsi_src->Register.Indirect)
1714 r600_src->rel = V_SQ_REL_RELATIVE;
1715 r600_src->sel = tgsi_src->Register.Index;
1716 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1717 }
1718 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1719 if (tgsi_src->Register.Dimension) {
1720 r600_src->kc_bank = tgsi_src->Dimension.Index;
1721 if (tgsi_src->Dimension.Indirect) {
1722 r600_src->kc_rel = 1;
1723 }
1724 }
1725 }
1726 }
1727
1728 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1729 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1730 unsigned int dst_reg)
1731 {
1732 struct r600_bytecode_vtx vtx;
1733 unsigned int ar_reg;
1734 int r;
1735
1736 if (offset) {
1737 struct r600_bytecode_alu alu;
1738
1739 memset(&alu, 0, sizeof(alu));
1740
1741 alu.op = ALU_OP2_ADD_INT;
1742 alu.src[0].sel = ctx->bc->ar_reg;
1743 alu.src[0].chan = ar_chan;
1744
1745 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1746 alu.src[1].value = offset;
1747
1748 alu.dst.sel = dst_reg;
1749 alu.dst.chan = ar_chan;
1750 alu.dst.write = 1;
1751 alu.last = 1;
1752
1753 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1754 return r;
1755
1756 ar_reg = dst_reg;
1757 } else {
1758 ar_reg = ctx->bc->ar_reg;
1759 }
1760
1761 memset(&vtx, 0, sizeof(vtx));
1762 vtx.buffer_id = cb_idx;
1763 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1764 vtx.src_gpr = ar_reg;
1765 vtx.src_sel_x = ar_chan;
1766 vtx.mega_fetch_count = 16;
1767 vtx.dst_gpr = dst_reg;
1768 vtx.dst_sel_x = 0; /* SEL_X */
1769 vtx.dst_sel_y = 1; /* SEL_Y */
1770 vtx.dst_sel_z = 2; /* SEL_Z */
1771 vtx.dst_sel_w = 3; /* SEL_W */
1772 vtx.data_format = FMT_32_32_32_32_FLOAT;
1773 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1774 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1775 vtx.endian = r600_endian_swap(32);
1776 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1777
1778 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1779 return r;
1780
1781 return 0;
1782 }
1783
1784 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1785 {
1786 struct r600_bytecode_vtx vtx;
1787 int r;
1788 unsigned index = src->Register.Index;
1789 unsigned vtx_id = src->Dimension.Index;
1790 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1791 int offset_chan = vtx_id % 3;
1792 int t2 = 0;
1793
1794 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1795 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1796
1797 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1798 offset_chan = 3;
1799
1800 if (src->Dimension.Indirect || src->Register.Indirect)
1801 t2 = r600_get_temp(ctx);
1802
1803 if (src->Dimension.Indirect) {
1804 int treg[3];
1805 struct r600_bytecode_alu alu;
1806 int r, i;
1807 unsigned addr_reg;
1808 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1809 if (src->DimIndirect.Index > 0) {
1810 r = single_alu_op2(ctx, ALU_OP1_MOV,
1811 ctx->bc->ar_reg, 0,
1812 addr_reg, 0,
1813 0, 0);
1814 if (r)
1815 return r;
1816 }
1817 /*
1818 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1819 at least this is what fglrx seems to do. */
1820 for (i = 0; i < 3; i++) {
1821 treg[i] = r600_get_temp(ctx);
1822 }
1823 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1824
1825 for (i = 0; i < 3; i++) {
1826 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1827 alu.op = ALU_OP1_MOV;
1828 alu.src[0].sel = ctx->gs_rotated_input[0];
1829 alu.src[0].chan = i == 2 ? 3 : i;
1830 alu.dst.sel = treg[i];
1831 alu.dst.chan = 0;
1832 alu.dst.write = 1;
1833 alu.last = 1;
1834 r = r600_bytecode_add_alu(ctx->bc, &alu);
1835 if (r)
1836 return r;
1837 }
1838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1839 alu.op = ALU_OP1_MOV;
1840 alu.src[0].sel = treg[0];
1841 alu.src[0].rel = 1;
1842 alu.dst.sel = t2;
1843 alu.dst.write = 1;
1844 alu.last = 1;
1845 r = r600_bytecode_add_alu(ctx->bc, &alu);
1846 if (r)
1847 return r;
1848 offset_reg = t2;
1849 offset_chan = 0;
1850 }
1851
1852 if (src->Register.Indirect) {
1853 int addr_reg;
1854 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1855
1856 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1857
1858 /* pull the value from index_reg */
1859 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1860 t2, 1,
1861 addr_reg, 0,
1862 V_SQ_ALU_SRC_LITERAL, first);
1863 if (r)
1864 return r;
1865 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1866 t2, 0,
1867 t2, 1,
1868 V_SQ_ALU_SRC_LITERAL, 4,
1869 offset_reg, offset_chan);
1870 if (r)
1871 return r;
1872 offset_reg = t2;
1873 offset_chan = 0;
1874 index = src->Register.Index - first;
1875 }
1876
1877 memset(&vtx, 0, sizeof(vtx));
1878 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1879 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1880 vtx.src_gpr = offset_reg;
1881 vtx.src_sel_x = offset_chan;
1882 vtx.offset = index * 16; /*bytes*/
1883 vtx.mega_fetch_count = 16;
1884 vtx.dst_gpr = dst_reg;
1885 vtx.dst_sel_x = 0; /* SEL_X */
1886 vtx.dst_sel_y = 1; /* SEL_Y */
1887 vtx.dst_sel_z = 2; /* SEL_Z */
1888 vtx.dst_sel_w = 3; /* SEL_W */
1889 if (ctx->bc->chip_class >= EVERGREEN) {
1890 vtx.use_const_fields = 1;
1891 } else {
1892 vtx.data_format = FMT_32_32_32_32_FLOAT;
1893 }
1894
1895 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1896 return r;
1897
1898 return 0;
1899 }
1900
1901 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1902 {
1903 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1904 unsigned i;
1905
1906 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1907 struct tgsi_full_src_register *src = &inst->Src[i];
1908
1909 if (src->Register.File == TGSI_FILE_INPUT) {
1910 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1911 /* primitive id is in R0.z */
1912 ctx->src[i].sel = 0;
1913 ctx->src[i].swizzle[0] = 2;
1914 }
1915 }
1916 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1917 int treg = r600_get_temp(ctx);
1918
1919 fetch_gs_input(ctx, src, treg);
1920 ctx->src[i].sel = treg;
1921 ctx->src[i].rel = 0;
1922 }
1923 }
1924 return 0;
1925 }
1926
1927
1928 /* Tessellation shaders pass outputs to the next shader using LDS.
1929 *
1930 * LS outputs = TCS(HS) inputs
1931 * TCS(HS) outputs = TES(DS) inputs
1932 *
1933 * The LDS layout is:
1934 * - TCS inputs for patch 0
1935 * - TCS inputs for patch 1
1936 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1937 * - ...
1938 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1939 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1940 * - TCS outputs for patch 1
1941 * - Per-patch TCS outputs for patch 1
1942 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1943 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1944 * - ...
1945 *
1946 * All three shaders VS(LS), TCS, TES share the same LDS space.
1947 */
1948 /* this will return with the dw address in temp_reg.x */
1949 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1950 const struct tgsi_full_dst_register *dst,
1951 const struct tgsi_full_src_register *src,
1952 int stride_bytes_reg, int stride_bytes_chan)
1953 {
1954 struct tgsi_full_dst_register reg;
1955 ubyte *name, *index, *array_first;
1956 int r;
1957 int param;
1958 struct tgsi_shader_info *info = &ctx->info;
1959 /* Set the register description. The address computation is the same
1960 * for sources and destinations. */
1961 if (src) {
1962 reg.Register.File = src->Register.File;
1963 reg.Register.Index = src->Register.Index;
1964 reg.Register.Indirect = src->Register.Indirect;
1965 reg.Register.Dimension = src->Register.Dimension;
1966 reg.Indirect = src->Indirect;
1967 reg.Dimension = src->Dimension;
1968 reg.DimIndirect = src->DimIndirect;
1969 } else
1970 reg = *dst;
1971
1972 /* If the register is 2-dimensional (e.g. an array of vertices
1973 * in a primitive), calculate the base address of the vertex. */
1974 if (reg.Register.Dimension) {
1975 int sel, chan;
1976 if (reg.Dimension.Indirect) {
1977 unsigned addr_reg;
1978 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1979
1980 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1981 /* pull the value from index_reg */
1982 sel = addr_reg;
1983 chan = 0;
1984 } else {
1985 sel = V_SQ_ALU_SRC_LITERAL;
1986 chan = reg.Dimension.Index;
1987 }
1988
1989 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1990 temp_reg, 0,
1991 stride_bytes_reg, stride_bytes_chan,
1992 sel, chan,
1993 temp_reg, 0);
1994 if (r)
1995 return r;
1996 }
1997
1998 if (reg.Register.File == TGSI_FILE_INPUT) {
1999 name = info->input_semantic_name;
2000 index = info->input_semantic_index;
2001 array_first = info->input_array_first;
2002 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
2003 name = info->output_semantic_name;
2004 index = info->output_semantic_index;
2005 array_first = info->output_array_first;
2006 } else {
2007 assert(0);
2008 return -1;
2009 }
2010 if (reg.Register.Indirect) {
2011 int addr_reg;
2012 int first;
2013 /* Add the relative address of the element. */
2014 if (reg.Indirect.ArrayID)
2015 first = array_first[reg.Indirect.ArrayID];
2016 else
2017 first = reg.Register.Index;
2018
2019 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
2020
2021 /* pull the value from index_reg */
2022 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2023 temp_reg, 0,
2024 V_SQ_ALU_SRC_LITERAL, 16,
2025 addr_reg, 0,
2026 temp_reg, 0);
2027 if (r)
2028 return r;
2029
2030 param = r600_get_lds_unique_index(name[first],
2031 index[first]);
2032
2033 } else {
2034 param = r600_get_lds_unique_index(name[reg.Register.Index],
2035 index[reg.Register.Index]);
2036 }
2037
2038 /* add to base_addr - passed in temp_reg.x */
2039 if (param) {
2040 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2041 temp_reg, 0,
2042 temp_reg, 0,
2043 V_SQ_ALU_SRC_LITERAL, param * 16);
2044 if (r)
2045 return r;
2046
2047 }
2048 return 0;
2049 }
2050
2051 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
2052 unsigned dst_reg, unsigned mask)
2053 {
2054 struct r600_bytecode_alu alu;
2055 int r, i, lasti;
2056
2057 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
2058 ctx->bc->force_add_cf = 1;
2059
2060 lasti = tgsi_last_instruction(mask);
2061 for (i = 1; i <= lasti; i++) {
2062 if (!(mask & (1 << i)))
2063 continue;
2064
2065 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2066 temp_reg, i,
2067 temp_reg, 0,
2068 V_SQ_ALU_SRC_LITERAL, 4 * i);
2069 if (r)
2070 return r;
2071 }
2072 for (i = 0; i <= lasti; i++) {
2073 if (!(mask & (1 << i)))
2074 continue;
2075
2076 /* emit an LDS_READ_RET */
2077 memset(&alu, 0, sizeof(alu));
2078 alu.op = LDS_OP1_LDS_READ_RET;
2079 alu.src[0].sel = temp_reg;
2080 alu.src[0].chan = i;
2081 alu.src[1].sel = V_SQ_ALU_SRC_0;
2082 alu.src[2].sel = V_SQ_ALU_SRC_0;
2083 alu.dst.chan = 0;
2084 alu.is_lds_idx_op = true;
2085 alu.last = 1;
2086 r = r600_bytecode_add_alu(ctx->bc, &alu);
2087 if (r)
2088 return r;
2089 }
2090 for (i = 0; i <= lasti; i++) {
2091 if (!(mask & (1 << i)))
2092 continue;
2093
2094 /* then read from LDS_OQ_A_POP */
2095 memset(&alu, 0, sizeof(alu));
2096
2097 alu.op = ALU_OP1_MOV;
2098 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
2099 alu.src[0].chan = 0;
2100 alu.dst.sel = dst_reg;
2101 alu.dst.chan = i;
2102 alu.dst.write = 1;
2103 alu.last = 1;
2104 r = r600_bytecode_add_alu(ctx->bc, &alu);
2105 if (r)
2106 return r;
2107 }
2108 return 0;
2109 }
2110
2111 static int fetch_mask(struct tgsi_src_register *reg)
2112 {
2113 int mask = 0;
2114 mask |= 1 << reg->SwizzleX;
2115 mask |= 1 << reg->SwizzleY;
2116 mask |= 1 << reg->SwizzleZ;
2117 mask |= 1 << reg->SwizzleW;
2118 return mask;
2119 }
2120
2121 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
2122 {
2123 int r;
2124 unsigned temp_reg = r600_get_temp(ctx);
2125
2126 r = get_lds_offset0(ctx, 2, temp_reg,
2127 src->Register.Dimension ? false : true);
2128 if (r)
2129 return r;
2130
2131 /* the base address is now in temp.x */
2132 r = r600_get_byte_address(ctx, temp_reg,
2133 NULL, src, ctx->tess_output_info, 1);
2134 if (r)
2135 return r;
2136
2137 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2138 if (r)
2139 return r;
2140 return 0;
2141 }
2142
2143 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
2144 {
2145 int r;
2146 unsigned temp_reg = r600_get_temp(ctx);
2147
2148 /* t.x = ips * r0.y */
2149 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2150 temp_reg, 0,
2151 ctx->tess_input_info, 0,
2152 0, 1);
2153
2154 if (r)
2155 return r;
2156
2157 /* the base address is now in temp.x */
2158 r = r600_get_byte_address(ctx, temp_reg,
2159 NULL, src, ctx->tess_input_info, 1);
2160 if (r)
2161 return r;
2162
2163 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2164 if (r)
2165 return r;
2166 return 0;
2167 }
2168
2169 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
2170 {
2171 int r;
2172 unsigned temp_reg = r600_get_temp(ctx);
2173
2174 r = get_lds_offset0(ctx, 1, temp_reg,
2175 src->Register.Dimension ? false : true);
2176 if (r)
2177 return r;
2178 /* the base address is now in temp.x */
2179 r = r600_get_byte_address(ctx, temp_reg,
2180 NULL, src,
2181 ctx->tess_output_info, 1);
2182 if (r)
2183 return r;
2184
2185 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2186 if (r)
2187 return r;
2188 return 0;
2189 }
2190
2191 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
2192 {
2193 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2194 unsigned i;
2195
2196 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2197 struct tgsi_full_src_register *src = &inst->Src[i];
2198
2199 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
2200 int treg = r600_get_temp(ctx);
2201 fetch_tes_input(ctx, src, treg);
2202 ctx->src[i].sel = treg;
2203 ctx->src[i].rel = 0;
2204 }
2205 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
2206 int treg = r600_get_temp(ctx);
2207 fetch_tcs_input(ctx, src, treg);
2208 ctx->src[i].sel = treg;
2209 ctx->src[i].rel = 0;
2210 }
2211 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
2212 int treg = r600_get_temp(ctx);
2213 fetch_tcs_output(ctx, src, treg);
2214 ctx->src[i].sel = treg;
2215 ctx->src[i].rel = 0;
2216 }
2217 }
2218 return 0;
2219 }
2220
2221 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
2222 {
2223 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2224 struct r600_bytecode_alu alu;
2225 int i, j, k, nconst, r;
2226
2227 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
2228 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
2229 nconst++;
2230 }
2231 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
2232 }
2233 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
2234 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
2235 continue;
2236 }
2237
2238 if (ctx->src[i].rel) {
2239 int chan = inst->Src[i].Indirect.Swizzle;
2240 int treg = r600_get_temp(ctx);
2241 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
2242 return r;
2243
2244 ctx->src[i].kc_bank = 0;
2245 ctx->src[i].kc_rel = 0;
2246 ctx->src[i].sel = treg;
2247 ctx->src[i].rel = 0;
2248 j--;
2249 } else if (j > 0) {
2250 int treg = r600_get_temp(ctx);
2251 for (k = 0; k < 4; k++) {
2252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2253 alu.op = ALU_OP1_MOV;
2254 alu.src[0].sel = ctx->src[i].sel;
2255 alu.src[0].chan = k;
2256 alu.src[0].rel = ctx->src[i].rel;
2257 alu.src[0].kc_bank = ctx->src[i].kc_bank;
2258 alu.src[0].kc_rel = ctx->src[i].kc_rel;
2259 alu.dst.sel = treg;
2260 alu.dst.chan = k;
2261 alu.dst.write = 1;
2262 if (k == 3)
2263 alu.last = 1;
2264 r = r600_bytecode_add_alu(ctx->bc, &alu);
2265 if (r)
2266 return r;
2267 }
2268 ctx->src[i].sel = treg;
2269 ctx->src[i].rel =0;
2270 j--;
2271 }
2272 }
2273 return 0;
2274 }
2275
2276 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
2277 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
2278 {
2279 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2280 struct r600_bytecode_alu alu;
2281 int i, j, k, nliteral, r;
2282
2283 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
2284 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2285 nliteral++;
2286 }
2287 }
2288 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
2289 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2290 int treg = r600_get_temp(ctx);
2291 for (k = 0; k < 4; k++) {
2292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2293 alu.op = ALU_OP1_MOV;
2294 alu.src[0].sel = ctx->src[i].sel;
2295 alu.src[0].chan = k;
2296 alu.src[0].value = ctx->src[i].value[k];
2297 alu.dst.sel = treg;
2298 alu.dst.chan = k;
2299 alu.dst.write = 1;
2300 if (k == 3)
2301 alu.last = 1;
2302 r = r600_bytecode_add_alu(ctx->bc, &alu);
2303 if (r)
2304 return r;
2305 }
2306 ctx->src[i].sel = treg;
2307 j--;
2308 }
2309 }
2310 return 0;
2311 }
2312
2313 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
2314 {
2315 int i, r, count = ctx->shader->ninput;
2316
2317 for (i = 0; i < count; i++) {
2318 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2319 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
2320 if (r)
2321 return r;
2322 }
2323 }
2324 return 0;
2325 }
2326
2327 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2328 int stream, unsigned *stream_item_size UNUSED)
2329 {
2330 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2331 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2332 int j, r;
2333 unsigned i;
2334
2335 /* Sanity checking. */
2336 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2337 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2338 r = -EINVAL;
2339 goto out_err;
2340 }
2341 for (i = 0; i < so->num_outputs; i++) {
2342 if (so->output[i].output_buffer >= 4) {
2343 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2344 so->output[i].output_buffer);
2345 r = -EINVAL;
2346 goto out_err;
2347 }
2348 }
2349
2350 /* Initialize locations where the outputs are stored. */
2351 for (i = 0; i < so->num_outputs; i++) {
2352
2353 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2354 start_comp[i] = so->output[i].start_component;
2355 /* Lower outputs with dst_offset < start_component.
2356 *
2357 * We can only output 4D vectors with a write mask, e.g. we can
2358 * only output the W component at offset 3, etc. If we want
2359 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2360 * to move it to X and output X. */
2361 if (so->output[i].dst_offset < so->output[i].start_component) {
2362 unsigned tmp = r600_get_temp(ctx);
2363
2364 for (j = 0; j < so->output[i].num_components; j++) {
2365 struct r600_bytecode_alu alu;
2366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2367 alu.op = ALU_OP1_MOV;
2368 alu.src[0].sel = so_gpr[i];
2369 alu.src[0].chan = so->output[i].start_component + j;
2370
2371 alu.dst.sel = tmp;
2372 alu.dst.chan = j;
2373 alu.dst.write = 1;
2374 if (j == so->output[i].num_components - 1)
2375 alu.last = 1;
2376 r = r600_bytecode_add_alu(ctx->bc, &alu);
2377 if (r)
2378 return r;
2379 }
2380 start_comp[i] = 0;
2381 so_gpr[i] = tmp;
2382 }
2383 }
2384
2385 /* Write outputs to buffers. */
2386 for (i = 0; i < so->num_outputs; i++) {
2387 struct r600_bytecode_output output;
2388
2389 if (stream != -1 && stream != so->output[i].stream)
2390 continue;
2391
2392 memset(&output, 0, sizeof(struct r600_bytecode_output));
2393 output.gpr = so_gpr[i];
2394 output.elem_size = so->output[i].num_components - 1;
2395 if (output.elem_size == 2)
2396 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2397 output.array_base = so->output[i].dst_offset - start_comp[i];
2398 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2399 output.burst_count = 1;
2400 /* array_size is an upper limit for the burst_count
2401 * with MEM_STREAM instructions */
2402 output.array_size = 0xFFF;
2403 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2404
2405 if (ctx->bc->chip_class >= EVERGREEN) {
2406 switch (so->output[i].output_buffer) {
2407 case 0:
2408 output.op = CF_OP_MEM_STREAM0_BUF0;
2409 break;
2410 case 1:
2411 output.op = CF_OP_MEM_STREAM0_BUF1;
2412 break;
2413 case 2:
2414 output.op = CF_OP_MEM_STREAM0_BUF2;
2415 break;
2416 case 3:
2417 output.op = CF_OP_MEM_STREAM0_BUF3;
2418 break;
2419 }
2420 output.op += so->output[i].stream * 4;
2421 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2422 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2423 } else {
2424 switch (so->output[i].output_buffer) {
2425 case 0:
2426 output.op = CF_OP_MEM_STREAM0;
2427 break;
2428 case 1:
2429 output.op = CF_OP_MEM_STREAM1;
2430 break;
2431 case 2:
2432 output.op = CF_OP_MEM_STREAM2;
2433 break;
2434 case 3:
2435 output.op = CF_OP_MEM_STREAM3;
2436 break;
2437 }
2438 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2439 }
2440 r = r600_bytecode_add_output(ctx->bc, &output);
2441 if (r)
2442 goto out_err;
2443 }
2444 return 0;
2445 out_err:
2446 return r;
2447 }
2448
2449 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2450 {
2451 struct r600_bytecode_alu alu;
2452 unsigned reg;
2453
2454 if (!ctx->shader->vs_out_edgeflag)
2455 return;
2456
2457 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2458
2459 /* clamp(x, 0, 1) */
2460 memset(&alu, 0, sizeof(alu));
2461 alu.op = ALU_OP1_MOV;
2462 alu.src[0].sel = reg;
2463 alu.dst.sel = reg;
2464 alu.dst.write = 1;
2465 alu.dst.clamp = 1;
2466 alu.last = 1;
2467 r600_bytecode_add_alu(ctx->bc, &alu);
2468
2469 memset(&alu, 0, sizeof(alu));
2470 alu.op = ALU_OP1_FLT_TO_INT;
2471 alu.src[0].sel = reg;
2472 alu.dst.sel = reg;
2473 alu.dst.write = 1;
2474 alu.last = 1;
2475 r600_bytecode_add_alu(ctx->bc, &alu);
2476 }
2477
2478 static int generate_gs_copy_shader(struct r600_context *rctx,
2479 struct r600_pipe_shader *gs,
2480 struct pipe_stream_output_info *so)
2481 {
2482 struct r600_shader_ctx ctx = {};
2483 struct r600_shader *gs_shader = &gs->shader;
2484 struct r600_pipe_shader *cshader;
2485 unsigned ocnt = gs_shader->noutput;
2486 struct r600_bytecode_alu alu;
2487 struct r600_bytecode_vtx vtx;
2488 struct r600_bytecode_output output;
2489 struct r600_bytecode_cf *cf_jump, *cf_pop,
2490 *last_exp_pos = NULL, *last_exp_param = NULL;
2491 int next_clip_pos = 61, next_param = 0;
2492 unsigned i, j;
2493 int ring;
2494 bool only_ring_0 = true;
2495 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2496 if (!cshader)
2497 return 0;
2498
2499 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2500 sizeof(struct r600_shader_io));
2501
2502 cshader->shader.noutput = ocnt;
2503
2504 ctx.shader = &cshader->shader;
2505 ctx.bc = &ctx.shader->bc;
2506 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2507
2508 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2509 rctx->screen->has_compressed_msaa_texturing);
2510
2511 ctx.bc->isa = rctx->isa;
2512
2513 cf_jump = NULL;
2514 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2515
2516 /* R0.x = R0.x & 0x3fffffff */
2517 memset(&alu, 0, sizeof(alu));
2518 alu.op = ALU_OP2_AND_INT;
2519 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2520 alu.src[1].value = 0x3fffffff;
2521 alu.dst.write = 1;
2522 r600_bytecode_add_alu(ctx.bc, &alu);
2523
2524 /* R0.y = R0.x >> 30 */
2525 memset(&alu, 0, sizeof(alu));
2526 alu.op = ALU_OP2_LSHR_INT;
2527 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2528 alu.src[1].value = 0x1e;
2529 alu.dst.chan = 1;
2530 alu.dst.write = 1;
2531 alu.last = 1;
2532 r600_bytecode_add_alu(ctx.bc, &alu);
2533
2534 /* fetch vertex data from GSVS ring */
2535 for (i = 0; i < ocnt; ++i) {
2536 struct r600_shader_io *out = &ctx.shader->output[i];
2537
2538 out->gpr = i + 1;
2539 out->ring_offset = i * 16;
2540
2541 memset(&vtx, 0, sizeof(vtx));
2542 vtx.op = FETCH_OP_VFETCH;
2543 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2544 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2545 vtx.mega_fetch_count = 16;
2546 vtx.offset = out->ring_offset;
2547 vtx.dst_gpr = out->gpr;
2548 vtx.src_gpr = 0;
2549 vtx.dst_sel_x = 0;
2550 vtx.dst_sel_y = 1;
2551 vtx.dst_sel_z = 2;
2552 vtx.dst_sel_w = 3;
2553 if (rctx->b.chip_class >= EVERGREEN) {
2554 vtx.use_const_fields = 1;
2555 } else {
2556 vtx.data_format = FMT_32_32_32_32_FLOAT;
2557 }
2558
2559 r600_bytecode_add_vtx(ctx.bc, &vtx);
2560 }
2561 ctx.temp_reg = i + 1;
2562 for (ring = 3; ring >= 0; --ring) {
2563 bool enabled = false;
2564 for (i = 0; i < so->num_outputs; i++) {
2565 if (so->output[i].stream == ring) {
2566 enabled = true;
2567 if (ring > 0)
2568 only_ring_0 = false;
2569 break;
2570 }
2571 }
2572 if (ring != 0 && !enabled) {
2573 cshader->shader.ring_item_sizes[ring] = 0;
2574 continue;
2575 }
2576
2577 if (cf_jump) {
2578 // Patch up jump label
2579 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2580 cf_pop = ctx.bc->cf_last;
2581
2582 cf_jump->cf_addr = cf_pop->id + 2;
2583 cf_jump->pop_count = 1;
2584 cf_pop->cf_addr = cf_pop->id + 2;
2585 cf_pop->pop_count = 1;
2586 }
2587
2588 /* PRED_SETE_INT __, R0.y, ring */
2589 memset(&alu, 0, sizeof(alu));
2590 alu.op = ALU_OP2_PRED_SETE_INT;
2591 alu.src[0].chan = 1;
2592 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2593 alu.src[1].value = ring;
2594 alu.execute_mask = 1;
2595 alu.update_pred = 1;
2596 alu.last = 1;
2597 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2598
2599 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2600 cf_jump = ctx.bc->cf_last;
2601
2602 if (enabled)
2603 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2604 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2605 }
2606
2607 /* bc adds nops - copy it */
2608 if (ctx.bc->chip_class == R600) {
2609 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2610 alu.op = ALU_OP0_NOP;
2611 alu.last = 1;
2612 r600_bytecode_add_alu(ctx.bc, &alu);
2613
2614 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2615 }
2616
2617 /* export vertex data */
2618 /* XXX factor out common code with r600_shader_from_tgsi ? */
2619 for (i = 0; i < ocnt; ++i) {
2620 struct r600_shader_io *out = &ctx.shader->output[i];
2621 bool instream0 = true;
2622 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2623 continue;
2624
2625 for (j = 0; j < so->num_outputs; j++) {
2626 if (so->output[j].register_index == i) {
2627 if (so->output[j].stream == 0)
2628 break;
2629 if (so->output[j].stream > 0)
2630 instream0 = false;
2631 }
2632 }
2633 if (!instream0)
2634 continue;
2635 memset(&output, 0, sizeof(output));
2636 output.gpr = out->gpr;
2637 output.elem_size = 3;
2638 output.swizzle_x = 0;
2639 output.swizzle_y = 1;
2640 output.swizzle_z = 2;
2641 output.swizzle_w = 3;
2642 output.burst_count = 1;
2643 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2644 output.op = CF_OP_EXPORT;
2645 switch (out->name) {
2646 case TGSI_SEMANTIC_POSITION:
2647 output.array_base = 60;
2648 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2649 break;
2650
2651 case TGSI_SEMANTIC_PSIZE:
2652 output.array_base = 61;
2653 if (next_clip_pos == 61)
2654 next_clip_pos = 62;
2655 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2656 output.swizzle_y = 7;
2657 output.swizzle_z = 7;
2658 output.swizzle_w = 7;
2659 ctx.shader->vs_out_misc_write = 1;
2660 ctx.shader->vs_out_point_size = 1;
2661 break;
2662 case TGSI_SEMANTIC_LAYER:
2663 if (out->spi_sid) {
2664 /* duplicate it as PARAM to pass to the pixel shader */
2665 output.array_base = next_param++;
2666 r600_bytecode_add_output(ctx.bc, &output);
2667 last_exp_param = ctx.bc->cf_last;
2668 }
2669 output.array_base = 61;
2670 if (next_clip_pos == 61)
2671 next_clip_pos = 62;
2672 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2673 output.swizzle_x = 7;
2674 output.swizzle_y = 7;
2675 output.swizzle_z = 0;
2676 output.swizzle_w = 7;
2677 ctx.shader->vs_out_misc_write = 1;
2678 ctx.shader->vs_out_layer = 1;
2679 break;
2680 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2681 if (out->spi_sid) {
2682 /* duplicate it as PARAM to pass to the pixel shader */
2683 output.array_base = next_param++;
2684 r600_bytecode_add_output(ctx.bc, &output);
2685 last_exp_param = ctx.bc->cf_last;
2686 }
2687 output.array_base = 61;
2688 if (next_clip_pos == 61)
2689 next_clip_pos = 62;
2690 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2691 ctx.shader->vs_out_misc_write = 1;
2692 ctx.shader->vs_out_viewport = 1;
2693 output.swizzle_x = 7;
2694 output.swizzle_y = 7;
2695 output.swizzle_z = 7;
2696 output.swizzle_w = 0;
2697 break;
2698 case TGSI_SEMANTIC_CLIPDIST:
2699 /* spi_sid is 0 for clipdistance outputs that were generated
2700 * for clipvertex - we don't need to pass them to PS */
2701 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2702 ctx.shader->cull_dist_write = gs->shader.cull_dist_write;
2703 ctx.shader->cc_dist_mask = gs->shader.cc_dist_mask;
2704 if (out->spi_sid) {
2705 /* duplicate it as PARAM to pass to the pixel shader */
2706 output.array_base = next_param++;
2707 r600_bytecode_add_output(ctx.bc, &output);
2708 last_exp_param = ctx.bc->cf_last;
2709 }
2710 output.array_base = next_clip_pos++;
2711 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2712 break;
2713 case TGSI_SEMANTIC_FOG:
2714 output.swizzle_y = 4; /* 0 */
2715 output.swizzle_z = 4; /* 0 */
2716 output.swizzle_w = 5; /* 1 */
2717 break;
2718 default:
2719 output.array_base = next_param++;
2720 break;
2721 }
2722 r600_bytecode_add_output(ctx.bc, &output);
2723 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2724 last_exp_param = ctx.bc->cf_last;
2725 else
2726 last_exp_pos = ctx.bc->cf_last;
2727 }
2728
2729 if (!last_exp_pos) {
2730 memset(&output, 0, sizeof(output));
2731 output.gpr = 0;
2732 output.elem_size = 3;
2733 output.swizzle_x = 7;
2734 output.swizzle_y = 7;
2735 output.swizzle_z = 7;
2736 output.swizzle_w = 7;
2737 output.burst_count = 1;
2738 output.type = 2;
2739 output.op = CF_OP_EXPORT;
2740 output.array_base = 60;
2741 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2742 r600_bytecode_add_output(ctx.bc, &output);
2743 last_exp_pos = ctx.bc->cf_last;
2744 }
2745
2746 if (!last_exp_param) {
2747 memset(&output, 0, sizeof(output));
2748 output.gpr = 0;
2749 output.elem_size = 3;
2750 output.swizzle_x = 7;
2751 output.swizzle_y = 7;
2752 output.swizzle_z = 7;
2753 output.swizzle_w = 7;
2754 output.burst_count = 1;
2755 output.type = 2;
2756 output.op = CF_OP_EXPORT;
2757 output.array_base = next_param++;
2758 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2759 r600_bytecode_add_output(ctx.bc, &output);
2760 last_exp_param = ctx.bc->cf_last;
2761 }
2762
2763 last_exp_pos->op = CF_OP_EXPORT_DONE;
2764 last_exp_param->op = CF_OP_EXPORT_DONE;
2765
2766 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2767 cf_pop = ctx.bc->cf_last;
2768
2769 cf_jump->cf_addr = cf_pop->id + 2;
2770 cf_jump->pop_count = 1;
2771 cf_pop->cf_addr = cf_pop->id + 2;
2772 cf_pop->pop_count = 1;
2773
2774 if (ctx.bc->chip_class == CAYMAN)
2775 cm_bytecode_add_cf_end(ctx.bc);
2776 else {
2777 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2778 ctx.bc->cf_last->end_of_program = 1;
2779 }
2780
2781 gs->gs_copy_shader = cshader;
2782 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2783
2784 ctx.bc->nstack = 1;
2785
2786 return r600_bytecode_build(ctx.bc);
2787 }
2788
2789 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2790 {
2791 if (ind) {
2792 struct r600_bytecode_alu alu;
2793 int r;
2794
2795 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2796 alu.op = ALU_OP2_ADD_INT;
2797 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2798 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2799 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2800 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2801 alu.dst.write = 1;
2802 alu.last = 1;
2803 r = r600_bytecode_add_alu(ctx->bc, &alu);
2804 if (r)
2805 return r;
2806 }
2807 return 0;
2808 }
2809
2810 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so UNUSED, int stream, bool ind)
2811 {
2812 struct r600_bytecode_output output;
2813 int ring_offset;
2814 unsigned i, k;
2815 int effective_stream = stream == -1 ? 0 : stream;
2816 int idx = 0;
2817
2818 for (i = 0; i < ctx->shader->noutput; i++) {
2819 if (ctx->gs_for_vs) {
2820 /* for ES we need to lookup corresponding ring offset expected by GS
2821 * (map this output to GS input by name and sid) */
2822 /* FIXME precompute offsets */
2823 ring_offset = -1;
2824 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2825 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2826 struct r600_shader_io *out = &ctx->shader->output[i];
2827 if (in->name == out->name && in->sid == out->sid)
2828 ring_offset = in->ring_offset;
2829 }
2830
2831 if (ring_offset == -1)
2832 continue;
2833 } else {
2834 ring_offset = idx * 16;
2835 idx++;
2836 }
2837
2838 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2839 continue;
2840 /* next_ring_offset after parsing input decls contains total size of
2841 * single vertex data, gs_next_vertex - current vertex index */
2842 if (!ind)
2843 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2844
2845 memset(&output, 0, sizeof(struct r600_bytecode_output));
2846 output.gpr = ctx->shader->output[i].gpr;
2847 output.elem_size = 3;
2848 output.comp_mask = 0xF;
2849 output.burst_count = 1;
2850
2851 if (ind)
2852 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2853 else
2854 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2855
2856 switch (stream) {
2857 default:
2858 case 0:
2859 output.op = CF_OP_MEM_RING; break;
2860 case 1:
2861 output.op = CF_OP_MEM_RING1; break;
2862 case 2:
2863 output.op = CF_OP_MEM_RING2; break;
2864 case 3:
2865 output.op = CF_OP_MEM_RING3; break;
2866 }
2867
2868 if (ind) {
2869 output.array_base = ring_offset >> 2; /* in dwords */
2870 output.array_size = 0xfff;
2871 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2872 } else
2873 output.array_base = ring_offset >> 2; /* in dwords */
2874 r600_bytecode_add_output(ctx->bc, &output);
2875 }
2876
2877 ++ctx->gs_next_vertex;
2878 return 0;
2879 }
2880
2881
2882 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2883 {
2884 int r;
2885 struct r600_bytecode_vtx vtx;
2886 int temp_val = ctx->temp_reg;
2887 /* need to store the TCS output somewhere */
2888 r = single_alu_op2(ctx, ALU_OP1_MOV,
2889 temp_val, 0,
2890 V_SQ_ALU_SRC_LITERAL, 0,
2891 0, 0);
2892 if (r)
2893 return r;
2894
2895 /* used by VS/TCS */
2896 if (ctx->tess_input_info) {
2897 /* fetch tcs input values into resv space */
2898 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2899 vtx.op = FETCH_OP_VFETCH;
2900 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2901 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2902 vtx.mega_fetch_count = 16;
2903 vtx.data_format = FMT_32_32_32_32;
2904 vtx.num_format_all = 2;
2905 vtx.format_comp_all = 1;
2906 vtx.use_const_fields = 0;
2907 vtx.endian = r600_endian_swap(32);
2908 vtx.srf_mode_all = 1;
2909 vtx.offset = 0;
2910 vtx.dst_gpr = ctx->tess_input_info;
2911 vtx.dst_sel_x = 0;
2912 vtx.dst_sel_y = 1;
2913 vtx.dst_sel_z = 2;
2914 vtx.dst_sel_w = 3;
2915 vtx.src_gpr = temp_val;
2916 vtx.src_sel_x = 0;
2917
2918 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2919 if (r)
2920 return r;
2921 }
2922
2923 /* used by TCS/TES */
2924 if (ctx->tess_output_info) {
2925 /* fetch tcs output values into resv space */
2926 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2927 vtx.op = FETCH_OP_VFETCH;
2928 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2929 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2930 vtx.mega_fetch_count = 16;
2931 vtx.data_format = FMT_32_32_32_32;
2932 vtx.num_format_all = 2;
2933 vtx.format_comp_all = 1;
2934 vtx.use_const_fields = 0;
2935 vtx.endian = r600_endian_swap(32);
2936 vtx.srf_mode_all = 1;
2937 vtx.offset = 16;
2938 vtx.dst_gpr = ctx->tess_output_info;
2939 vtx.dst_sel_x = 0;
2940 vtx.dst_sel_y = 1;
2941 vtx.dst_sel_z = 2;
2942 vtx.dst_sel_w = 3;
2943 vtx.src_gpr = temp_val;
2944 vtx.src_sel_x = 0;
2945
2946 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2947 if (r)
2948 return r;
2949 }
2950 return 0;
2951 }
2952
2953 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2954 {
2955 int j, r;
2956 int temp_reg;
2957 unsigned i;
2958
2959 /* fetch tcs input values into input_vals */
2960 ctx->tess_input_info = r600_get_temp(ctx);
2961 ctx->tess_output_info = 0;
2962 r = r600_fetch_tess_io_info(ctx);
2963 if (r)
2964 return r;
2965
2966 temp_reg = r600_get_temp(ctx);
2967 /* dst reg contains LDS address stride * idx */
2968 /* MUL vertexID, vertex_dw_stride */
2969 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2970 temp_reg, 0,
2971 ctx->tess_input_info, 1,
2972 0, 1); /* rel id in r0.y? */
2973 if (r)
2974 return r;
2975
2976 for (i = 0; i < ctx->shader->noutput; i++) {
2977 struct r600_bytecode_alu alu;
2978 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2979
2980 if (param) {
2981 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2982 temp_reg, 1,
2983 temp_reg, 0,
2984 V_SQ_ALU_SRC_LITERAL, param * 16);
2985 if (r)
2986 return r;
2987 }
2988
2989 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2990 temp_reg, 2,
2991 temp_reg, param ? 1 : 0,
2992 V_SQ_ALU_SRC_LITERAL, 8);
2993 if (r)
2994 return r;
2995
2996
2997 for (j = 0; j < 2; j++) {
2998 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3000 alu.op = LDS_OP3_LDS_WRITE_REL;
3001 alu.src[0].sel = temp_reg;
3002 alu.src[0].chan = chan;
3003 alu.src[1].sel = ctx->shader->output[i].gpr;
3004 alu.src[1].chan = j * 2;
3005 alu.src[2].sel = ctx->shader->output[i].gpr;
3006 alu.src[2].chan = (j * 2) + 1;
3007 alu.last = 1;
3008 alu.dst.chan = 0;
3009 alu.lds_idx = 1;
3010 alu.is_lds_idx_op = true;
3011 r = r600_bytecode_add_alu(ctx->bc, &alu);
3012 if (r)
3013 return r;
3014 }
3015 }
3016 return 0;
3017 }
3018
3019 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
3020 {
3021 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3022 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
3023 int i, r, lasti;
3024 int temp_reg = r600_get_temp(ctx);
3025 struct r600_bytecode_alu alu;
3026 unsigned write_mask = dst->Register.WriteMask;
3027
3028 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
3029 return 0;
3030
3031 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
3032 if (r)
3033 return r;
3034
3035 /* the base address is now in temp.x */
3036 r = r600_get_byte_address(ctx, temp_reg,
3037 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
3038 if (r)
3039 return r;
3040
3041 /* LDS write */
3042 lasti = tgsi_last_instruction(write_mask);
3043 for (i = 1; i <= lasti; i++) {
3044
3045 if (!(write_mask & (1 << i)))
3046 continue;
3047 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3048 temp_reg, i,
3049 temp_reg, 0,
3050 V_SQ_ALU_SRC_LITERAL, 4 * i);
3051 if (r)
3052 return r;
3053 }
3054
3055 for (i = 0; i <= lasti; i++) {
3056 if (!(write_mask & (1 << i)))
3057 continue;
3058
3059 if ((i == 0 && ((write_mask & 3) == 3)) ||
3060 (i == 2 && ((write_mask & 0xc) == 0xc))) {
3061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3062 alu.op = LDS_OP3_LDS_WRITE_REL;
3063 alu.src[0].sel = temp_reg;
3064 alu.src[0].chan = i;
3065
3066 alu.src[1].sel = dst->Register.Index;
3067 alu.src[1].sel += ctx->file_offset[dst->Register.File];
3068 alu.src[1].chan = i;
3069
3070 alu.src[2].sel = dst->Register.Index;
3071 alu.src[2].sel += ctx->file_offset[dst->Register.File];
3072 alu.src[2].chan = i + 1;
3073 alu.lds_idx = 1;
3074 alu.dst.chan = 0;
3075 alu.last = 1;
3076 alu.is_lds_idx_op = true;
3077 r = r600_bytecode_add_alu(ctx->bc, &alu);
3078 if (r)
3079 return r;
3080 i += 1;
3081 continue;
3082 }
3083 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3084 alu.op = LDS_OP2_LDS_WRITE;
3085 alu.src[0].sel = temp_reg;
3086 alu.src[0].chan = i;
3087
3088 alu.src[1].sel = dst->Register.Index;
3089 alu.src[1].sel += ctx->file_offset[dst->Register.File];
3090 alu.src[1].chan = i;
3091
3092 alu.src[2].sel = V_SQ_ALU_SRC_0;
3093 alu.dst.chan = 0;
3094 alu.last = 1;
3095 alu.is_lds_idx_op = true;
3096 r = r600_bytecode_add_alu(ctx->bc, &alu);
3097 if (r)
3098 return r;
3099 }
3100 return 0;
3101 }
3102
3103 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
3104 int output_idx, int nc)
3105 {
3106 int param;
3107 unsigned temp_reg = r600_get_temp(ctx);
3108 unsigned name = ctx->shader->output[output_idx].name;
3109 int dreg = ctx->shader->output[output_idx].gpr;
3110 int r;
3111
3112 param = r600_get_lds_unique_index(name, 0);
3113 r = get_lds_offset0(ctx, 1, temp_reg, true);
3114 if (r)
3115 return r;
3116
3117 if (param) {
3118 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3119 temp_reg, 0,
3120 temp_reg, 0,
3121 V_SQ_ALU_SRC_LITERAL, param * 16);
3122 if (r)
3123 return r;
3124 }
3125
3126 do_lds_fetch_values(ctx, temp_reg, dreg, ((1u << nc) - 1));
3127 return 0;
3128 }
3129
3130 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
3131 {
3132 int stride, outer_comps, inner_comps;
3133 int tessinner_idx = -1, tessouter_idx = -1;
3134 int i, r;
3135 unsigned j;
3136 int temp_reg = r600_get_temp(ctx);
3137 int treg[3] = {-1, -1, -1};
3138 struct r600_bytecode_alu alu;
3139 struct r600_bytecode_cf *cf_jump, *cf_pop;
3140
3141 /* only execute factor emission for invocation 0 */
3142 /* PRED_SETE_INT __, R0.x, 0 */
3143 memset(&alu, 0, sizeof(alu));
3144 alu.op = ALU_OP2_PRED_SETE_INT;
3145 alu.src[0].chan = 2;
3146 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3147 alu.execute_mask = 1;
3148 alu.update_pred = 1;
3149 alu.last = 1;
3150 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
3151
3152 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
3153 cf_jump = ctx->bc->cf_last;
3154
3155 treg[0] = r600_get_temp(ctx);
3156 switch (ctx->shader->tcs_prim_mode) {
3157 case PIPE_PRIM_LINES:
3158 stride = 8; /* 2 dwords, 1 vec2 store */
3159 outer_comps = 2;
3160 inner_comps = 0;
3161 break;
3162 case PIPE_PRIM_TRIANGLES:
3163 stride = 16; /* 4 dwords, 1 vec4 store */
3164 outer_comps = 3;
3165 inner_comps = 1;
3166 treg[1] = r600_get_temp(ctx);
3167 break;
3168 case PIPE_PRIM_QUADS:
3169 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
3170 outer_comps = 4;
3171 inner_comps = 2;
3172 treg[1] = r600_get_temp(ctx);
3173 treg[2] = r600_get_temp(ctx);
3174 break;
3175 default:
3176 assert(0);
3177 return -1;
3178 }
3179
3180 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
3181 /* TF_WRITE takes index in R.x, value in R.y */
3182 for (j = 0; j < ctx->shader->noutput; j++) {
3183 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSINNER)
3184 tessinner_idx = j;
3185 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSOUTER)
3186 tessouter_idx = j;
3187 }
3188
3189 if (tessouter_idx == -1)
3190 return -1;
3191
3192 if (tessinner_idx == -1 && inner_comps)
3193 return -1;
3194
3195 if (tessouter_idx != -1) {
3196 r = r600_tess_factor_read(ctx, tessouter_idx, outer_comps);
3197 if (r)
3198 return r;
3199 }
3200
3201 if (tessinner_idx != -1) {
3202 r = r600_tess_factor_read(ctx, tessinner_idx, inner_comps);
3203 if (r)
3204 return r;
3205 }
3206
3207 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
3208 /* r.x = relpatchid(r0.y) * tf_stride */
3209
3210 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
3211 /* add incoming r0.w to it: t.x = t.x + r0.w */
3212 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3213 temp_reg, 0,
3214 0, 1,
3215 V_SQ_ALU_SRC_LITERAL, stride,
3216 0, 3);
3217 if (r)
3218 return r;
3219
3220 for (i = 0; i < outer_comps + inner_comps; i++) {
3221 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
3222 int out_comp = i >= outer_comps ? i - outer_comps : i;
3223
3224 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
3225 if (out_comp == 1)
3226 out_comp = 0;
3227 else if (out_comp == 0)
3228 out_comp = 1;
3229 }
3230
3231 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3232 treg[i / 2], (2 * (i % 2)),
3233 temp_reg, 0,
3234 V_SQ_ALU_SRC_LITERAL, 4 * i);
3235 if (r)
3236 return r;
3237 r = single_alu_op2(ctx, ALU_OP1_MOV,
3238 treg[i / 2], 1 + (2 * (i%2)),
3239 ctx->shader->output[out_idx].gpr, out_comp,
3240 0, 0);
3241 if (r)
3242 return r;
3243 }
3244 for (i = 0; i < outer_comps + inner_comps; i++) {
3245 struct r600_bytecode_gds gds;
3246
3247 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
3248 gds.src_gpr = treg[i / 2];
3249 gds.src_sel_x = 2 * (i % 2);
3250 gds.src_sel_y = 1 + (2 * (i % 2));
3251 gds.src_sel_z = 4;
3252 gds.dst_sel_x = 7;
3253 gds.dst_sel_y = 7;
3254 gds.dst_sel_z = 7;
3255 gds.dst_sel_w = 7;
3256 gds.op = FETCH_OP_TF_WRITE;
3257 r = r600_bytecode_add_gds(ctx->bc, &gds);
3258 if (r)
3259 return r;
3260 }
3261
3262 // Patch up jump label
3263 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
3264 cf_pop = ctx->bc->cf_last;
3265
3266 cf_jump->cf_addr = cf_pop->id + 2;
3267 cf_jump->pop_count = 1;
3268 cf_pop->cf_addr = cf_pop->id + 2;
3269 cf_pop->pop_count = 1;
3270
3271 return 0;
3272 }
3273
3274 /*
3275 * We have to work out the thread ID for load and atomic
3276 * operations, which store the returned value to an index
3277 * in an intermediate buffer.
3278 * The index is calculated by taking the thread id,
3279 * calculated from the MBCNT instructions.
3280 * Then the shader engine ID is multiplied by 256,
3281 * and the wave id is added.
3282 * Then the result is multipled by 64 and thread id is
3283 * added.
3284 */
3285 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
3286 {
3287 struct r600_bytecode_alu alu;
3288 int r;
3289
3290 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3291 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
3292 alu.dst.sel = ctx->temp_reg;
3293 alu.dst.chan = 0;
3294 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3295 alu.src[0].value = 0xffffffff;
3296 alu.dst.write = 1;
3297 r = r600_bytecode_add_alu(ctx->bc, &alu);
3298 if (r)
3299 return r;
3300
3301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3302 alu.op = ALU_OP1_MBCNT_32HI_INT;
3303 alu.dst.sel = ctx->temp_reg;
3304 alu.dst.chan = 1;
3305 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3306 alu.src[0].value = 0xffffffff;
3307 alu.dst.write = 1;
3308 r = r600_bytecode_add_alu(ctx->bc, &alu);
3309 if (r)
3310 return r;
3311
3312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3313 alu.op = ALU_OP3_MULADD_UINT24;
3314 alu.dst.sel = ctx->temp_reg;
3315 alu.dst.chan = 2;
3316 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
3317 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3318 alu.src[1].value = 256;
3319 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
3320 alu.dst.write = 1;
3321 alu.is_op3 = 1;
3322 alu.last = 1;
3323 r = r600_bytecode_add_alu(ctx->bc, &alu);
3324 if (r)
3325 return r;
3326
3327 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3328 ctx->thread_id_gpr, 1,
3329 ctx->temp_reg, 2,
3330 V_SQ_ALU_SRC_LITERAL, 0x40,
3331 ctx->temp_reg, 0);
3332 if (r)
3333 return r;
3334 return 0;
3335 }
3336
3337 static int r600_shader_from_tgsi(struct r600_context *rctx,
3338 struct r600_pipe_shader *pipeshader,
3339 union r600_shader_key key)
3340 {
3341 struct r600_screen *rscreen = rctx->screen;
3342 struct r600_shader *shader = &pipeshader->shader;
3343 struct tgsi_token *tokens = pipeshader->selector->tokens;
3344 struct pipe_stream_output_info so = pipeshader->selector->so;
3345 struct tgsi_full_immediate *immediate;
3346 struct r600_shader_ctx ctx;
3347 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3348 unsigned output_done, noutput;
3349 unsigned opcode;
3350 int j, k, r = 0;
3351 unsigned i;
3352 int next_param_base = 0, next_clip_base;
3353 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3354 bool indirect_gprs;
3355 bool ring_outputs = false;
3356 bool lds_outputs = false;
3357 bool lds_inputs = false;
3358 bool pos_emitted = false;
3359
3360 ctx.bc = &shader->bc;
3361 ctx.shader = shader;
3362
3363 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3364 rscreen->has_compressed_msaa_texturing);
3365 ctx.tokens = tokens;
3366 tgsi_scan_shader(tokens, &ctx.info);
3367 shader->indirect_files = ctx.info.indirect_files;
3368
3369 int narrays = ctx.info.array_max[TGSI_FILE_TEMPORARY];
3370 ctx.array_infos = calloc(narrays, sizeof(*ctx.array_infos));
3371 ctx.spilled_arrays = calloc(narrays, sizeof(bool));
3372 tgsi_scan_arrays(tokens, TGSI_FILE_TEMPORARY, narrays, ctx.array_infos);
3373
3374 shader->uses_helper_invocation = false;
3375 shader->uses_doubles = ctx.info.uses_doubles;
3376 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3377 shader->nsys_inputs = 0;
3378
3379 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0 ||
3380 ctx.info.file_count[TGSI_FILE_BUFFER] > 0;
3381 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3382 tgsi_parse_init(&ctx.parse, tokens);
3383 ctx.type = ctx.info.processor;
3384 shader->processor_type = ctx.type;
3385 ctx.bc->type = shader->processor_type;
3386
3387 switch (ctx.type) {
3388 case PIPE_SHADER_VERTEX:
3389 shader->vs_as_gs_a = key.vs.as_gs_a;
3390 shader->vs_as_es = key.vs.as_es;
3391 shader->vs_as_ls = key.vs.as_ls;
3392 shader->atomic_base = key.vs.first_atomic_counter;
3393 if (shader->vs_as_es)
3394 ring_outputs = true;
3395 if (shader->vs_as_ls)
3396 lds_outputs = true;
3397 break;
3398 case PIPE_SHADER_GEOMETRY:
3399 ring_outputs = true;
3400 shader->atomic_base = key.gs.first_atomic_counter;
3401 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3402 break;
3403 case PIPE_SHADER_TESS_CTRL:
3404 shader->tcs_prim_mode = key.tcs.prim_mode;
3405 shader->atomic_base = key.tcs.first_atomic_counter;
3406 lds_outputs = true;
3407 lds_inputs = true;
3408 break;
3409 case PIPE_SHADER_TESS_EVAL:
3410 shader->tes_as_es = key.tes.as_es;
3411 shader->atomic_base = key.tes.first_atomic_counter;
3412 lds_inputs = true;
3413 if (shader->tes_as_es)
3414 ring_outputs = true;
3415 break;
3416 case PIPE_SHADER_FRAGMENT:
3417 shader->two_side = key.ps.color_two_side;
3418 shader->atomic_base = key.ps.first_atomic_counter;
3419 shader->rat_base = key.ps.nr_cbufs;
3420 shader->image_size_const_offset = key.ps.image_size_const_offset;
3421 break;
3422 case PIPE_SHADER_COMPUTE:
3423 shader->rat_base = 0;
3424 shader->image_size_const_offset = ctx.info.file_count[TGSI_FILE_SAMPLER];
3425 break;
3426 default:
3427 break;
3428 }
3429
3430 if (shader->vs_as_es || shader->tes_as_es) {
3431 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3432 } else {
3433 ctx.gs_for_vs = NULL;
3434 }
3435
3436 ctx.next_ring_offset = 0;
3437 ctx.gs_out_ring_offset = 0;
3438 ctx.gs_next_vertex = 0;
3439 ctx.gs_stream_output_info = &so;
3440
3441 ctx.thread_id_gpr = -1;
3442 ctx.face_gpr = -1;
3443 ctx.fixed_pt_position_gpr = -1;
3444 ctx.fragcoord_input = -1;
3445 ctx.colors_used = 0;
3446 ctx.clip_vertex_write = 0;
3447
3448 ctx.helper_invoc_reg = -1;
3449 ctx.cs_block_size_reg = -1;
3450 ctx.cs_grid_size_reg = -1;
3451 ctx.cs_block_size_loaded = false;
3452 ctx.cs_grid_size_loaded = false;
3453
3454 shader->nr_ps_color_exports = 0;
3455 shader->nr_ps_max_color_exports = 0;
3456
3457
3458 /* register allocations */
3459 /* Values [0,127] correspond to GPR[0..127].
3460 * Values [128,159] correspond to constant buffer bank 0
3461 * Values [160,191] correspond to constant buffer bank 1
3462 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3463 * Values [256,287] correspond to constant buffer bank 2 (EG)
3464 * Values [288,319] correspond to constant buffer bank 3 (EG)
3465 * Other special values are shown in the list below.
3466 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3467 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3468 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3469 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3470 * 248 SQ_ALU_SRC_0: special constant 0.0.
3471 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3472 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3473 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3474 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3475 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3476 * 254 SQ_ALU_SRC_PV: previous vector result.
3477 * 255 SQ_ALU_SRC_PS: previous scalar result.
3478 */
3479 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3480 ctx.file_offset[i] = 0;
3481 }
3482
3483 if (ctx.type == PIPE_SHADER_VERTEX) {
3484
3485 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3486 if (ctx.info.num_inputs)
3487 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3488 }
3489 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3490 if (ctx.bc->chip_class >= EVERGREEN)
3491 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3492 else
3493 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3494
3495 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3496 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_HELPER_INVOCATION) {
3497 ctx.helper_invoc_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3498 shader->uses_helper_invocation = true;
3499 }
3500 }
3501 }
3502 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3503 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3504 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3505 }
3506 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3507 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3508 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3509 bool add_tesscoord = false, add_tess_inout = false;
3510 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3511 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3512 /* if we have tesscoord save one reg */
3513 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3514 add_tesscoord = true;
3515 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3516 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3517 add_tess_inout = true;
3518 }
3519 if (add_tesscoord || add_tess_inout)
3520 ctx.file_offset[TGSI_FILE_INPUT]++;
3521 if (add_tess_inout)
3522 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3523 }
3524 if (ctx.type == PIPE_SHADER_COMPUTE) {
3525 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3526 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3527 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_GRID_SIZE)
3528 ctx.cs_grid_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3529 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_BLOCK_SIZE)
3530 ctx.cs_block_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3531 }
3532 }
3533
3534 ctx.file_offset[TGSI_FILE_OUTPUT] =
3535 ctx.file_offset[TGSI_FILE_INPUT] +
3536 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3537 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3538 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3539
3540 /* Outside the GPR range. This will be translated to one of the
3541 * kcache banks later. */
3542 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3543 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3544
3545 pipeshader->scratch_space_needed = 0;
3546 int regno = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3547 ctx.info.file_max[TGSI_FILE_TEMPORARY];
3548 if (regno > 124) {
3549 choose_spill_arrays(&ctx, &regno, &pipeshader->scratch_space_needed);
3550 shader->indirect_files = ctx.info.indirect_files;
3551 }
3552 shader->needs_scratch_space = pipeshader->scratch_space_needed != 0;
3553
3554 ctx.bc->ar_reg = ++regno;
3555 ctx.bc->index_reg[0] = ++regno;
3556 ctx.bc->index_reg[1] = ++regno;
3557
3558 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3559 ctx.tess_input_info = ++regno;
3560 ctx.tess_output_info = ++regno;
3561 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3562 ctx.tess_input_info = 0;
3563 ctx.tess_output_info = ++regno;
3564 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3565 ctx.gs_export_gpr_tregs[0] = ++regno;
3566 ctx.gs_export_gpr_tregs[1] = ++regno;
3567 ctx.gs_export_gpr_tregs[2] = ++regno;
3568 ctx.gs_export_gpr_tregs[3] = ++regno;
3569 if (ctx.shader->gs_tri_strip_adj_fix) {
3570 ctx.gs_rotated_input[0] = ++regno;
3571 ctx.gs_rotated_input[1] = ++regno;
3572 } else {
3573 ctx.gs_rotated_input[0] = 0;
3574 ctx.gs_rotated_input[1] = 1;
3575 }
3576 }
3577
3578 if (shader->uses_images) {
3579 ctx.thread_id_gpr = ++regno;
3580 }
3581 ctx.temp_reg = ++regno;
3582
3583 shader->max_arrays = 0;
3584 shader->num_arrays = 0;
3585 if (indirect_gprs) {
3586
3587 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3588 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3589 ctx.file_offset[TGSI_FILE_OUTPUT] -
3590 ctx.file_offset[TGSI_FILE_INPUT],
3591 0x0F);
3592 }
3593 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3594 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3595 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3596 ctx.file_offset[TGSI_FILE_OUTPUT],
3597 0x0F);
3598 }
3599 }
3600
3601 ctx.nliterals = 0;
3602 ctx.literals = NULL;
3603 ctx.max_driver_temp_used = 0;
3604
3605 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3606 ctx.info.colors_written == 1;
3607 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3608 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3609
3610 if (ctx.type == PIPE_SHADER_VERTEX ||
3611 ctx.type == PIPE_SHADER_GEOMETRY ||
3612 ctx.type == PIPE_SHADER_TESS_EVAL) {
3613 shader->cc_dist_mask = (1 << (ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED] +
3614 ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED])) - 1;
3615 shader->clip_dist_write = (1 << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED]) - 1;
3616 shader->cull_dist_write = ((1 << ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED]) - 1) << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED];
3617 }
3618
3619 if (shader->vs_as_gs_a)
3620 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3621
3622 if (ctx.thread_id_gpr != -1) {
3623 r = load_thread_id_gpr(&ctx);
3624 if (r)
3625 return r;
3626 }
3627
3628 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3629 r600_fetch_tess_io_info(&ctx);
3630
3631 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3632 tgsi_parse_token(&ctx.parse);
3633 switch (ctx.parse.FullToken.Token.Type) {
3634 case TGSI_TOKEN_TYPE_IMMEDIATE:
3635 immediate = &ctx.parse.FullToken.FullImmediate;
3636 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3637 if(ctx.literals == NULL) {
3638 r = -ENOMEM;
3639 goto out_err;
3640 }
3641 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3642 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3643 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3644 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3645 ctx.nliterals++;
3646 break;
3647 case TGSI_TOKEN_TYPE_DECLARATION:
3648 r = tgsi_declaration(&ctx);
3649 if (r)
3650 goto out_err;
3651 break;
3652 case TGSI_TOKEN_TYPE_INSTRUCTION:
3653 case TGSI_TOKEN_TYPE_PROPERTY:
3654 break;
3655 default:
3656 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3657 r = -EINVAL;
3658 goto out_err;
3659 }
3660 }
3661
3662 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3663 shader->ring_item_sizes[1] = 0;
3664 shader->ring_item_sizes[2] = 0;
3665 shader->ring_item_sizes[3] = 0;
3666
3667 /* Process two side if needed */
3668 if (shader->two_side && ctx.colors_used) {
3669 int i, count = ctx.shader->ninput;
3670 unsigned next_lds_loc = ctx.shader->nlds;
3671
3672 /* additional inputs will be allocated right after the existing inputs,
3673 * we won't need them after the color selection, so we don't need to
3674 * reserve these gprs for the rest of the shader code and to adjust
3675 * output offsets etc. */
3676 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3677 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3678
3679 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3680 if (ctx.face_gpr == -1) {
3681 i = ctx.shader->ninput++;
3682 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3683 ctx.shader->input[i].spi_sid = 0;
3684 ctx.shader->input[i].gpr = gpr++;
3685 ctx.face_gpr = ctx.shader->input[i].gpr;
3686 }
3687
3688 for (i = 0; i < count; i++) {
3689 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3690 int ni = ctx.shader->ninput++;
3691 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3692 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3693 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3694 ctx.shader->input[ni].gpr = gpr++;
3695 // TGSI to LLVM needs to know the lds position of inputs.
3696 // Non LLVM path computes it later (in process_twoside_color)
3697 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3698 ctx.shader->input[i].back_color_input = ni;
3699 if (ctx.bc->chip_class >= EVERGREEN) {
3700 if ((r = evergreen_interp_input(&ctx, ni)))
3701 return r;
3702 }
3703 }
3704 }
3705 }
3706
3707 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3708 shader->nr_ps_max_color_exports = 8;
3709
3710 if (ctx.shader->uses_helper_invocation) {
3711 if (ctx.bc->chip_class == CAYMAN)
3712 r = cm_load_helper_invocation(&ctx);
3713 else
3714 r = eg_load_helper_invocation(&ctx);
3715 if (r)
3716 return r;
3717 }
3718
3719 /*
3720 * XXX this relies on fixed_pt_position_gpr only being present when
3721 * this shader should be executed per sample. Should be the case for now...
3722 */
3723 if (ctx.fixed_pt_position_gpr != -1 && ctx.info.reads_samplemask) {
3724 /*
3725 * Fix up sample mask. The hw always gives us coverage mask for
3726 * the pixel. However, for per-sample shading, we need the
3727 * coverage for the shader invocation only.
3728 * Also, with disabled msaa, only the first bit should be set
3729 * (luckily the same fixup works for both problems).
3730 * For now, we can only do it if we know this shader is always
3731 * executed per sample (due to usage of bits in the shader
3732 * forcing per-sample execution).
3733 * If the fb is not multisampled, we'd do unnecessary work but
3734 * it should still be correct.
3735 * It will however do nothing for sample shading according
3736 * to MinSampleShading.
3737 */
3738 struct r600_bytecode_alu alu;
3739 int tmp = r600_get_temp(&ctx);
3740 assert(ctx.face_gpr != -1);
3741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3742
3743 alu.op = ALU_OP2_LSHL_INT;
3744 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3745 alu.src[0].value = 0x1;
3746 alu.src[1].sel = ctx.fixed_pt_position_gpr;
3747 alu.src[1].chan = 3;
3748 alu.dst.sel = tmp;
3749 alu.dst.chan = 0;
3750 alu.dst.write = 1;
3751 alu.last = 1;
3752 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3753 return r;
3754
3755 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3756 alu.op = ALU_OP2_AND_INT;
3757 alu.src[0].sel = tmp;
3758 alu.src[1].sel = ctx.face_gpr;
3759 alu.src[1].chan = 2;
3760 alu.dst.sel = ctx.face_gpr;
3761 alu.dst.chan = 2;
3762 alu.dst.write = 1;
3763 alu.last = 1;
3764 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3765 return r;
3766 }
3767
3768 if (ctx.fragcoord_input >= 0) {
3769 if (ctx.bc->chip_class == CAYMAN) {
3770 for (j = 0 ; j < 4; j++) {
3771 struct r600_bytecode_alu alu;
3772 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3773 alu.op = ALU_OP1_RECIP_IEEE;
3774 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3775 alu.src[0].chan = 3;
3776
3777 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3778 alu.dst.chan = j;
3779 alu.dst.write = (j == 3);
3780 alu.last = (j == 3);
3781 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3782 return r;
3783 }
3784 } else {
3785 struct r600_bytecode_alu alu;
3786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3787 alu.op = ALU_OP1_RECIP_IEEE;
3788 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3789 alu.src[0].chan = 3;
3790
3791 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3792 alu.dst.chan = 3;
3793 alu.dst.write = 1;
3794 alu.last = 1;
3795 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3796 return r;
3797 }
3798 }
3799
3800 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3801 struct r600_bytecode_alu alu;
3802 int r;
3803
3804 /* GS thread with no output workaround - emit a cut at start of GS */
3805 if (ctx.bc->chip_class == R600)
3806 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3807
3808 for (j = 0; j < 4; j++) {
3809 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3810 alu.op = ALU_OP1_MOV;
3811 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3812 alu.src[0].value = 0;
3813 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3814 alu.dst.write = 1;
3815 alu.last = 1;
3816 r = r600_bytecode_add_alu(ctx.bc, &alu);
3817 if (r)
3818 return r;
3819 }
3820
3821 if (ctx.shader->gs_tri_strip_adj_fix) {
3822 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3823 ctx.gs_rotated_input[0], 2,
3824 0, 2,
3825 V_SQ_ALU_SRC_LITERAL, 1);
3826 if (r)
3827 return r;
3828
3829 for (i = 0; i < 6; i++) {
3830 int rotated = (i + 4) % 6;
3831 int offset_reg = i / 3;
3832 int offset_chan = i % 3;
3833 int rotated_offset_reg = rotated / 3;
3834 int rotated_offset_chan = rotated % 3;
3835
3836 if (offset_reg == 0 && offset_chan == 2)
3837 offset_chan = 3;
3838 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3839 rotated_offset_chan = 3;
3840
3841 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3842 ctx.gs_rotated_input[offset_reg], offset_chan,
3843 ctx.gs_rotated_input[0], 2,
3844 offset_reg, offset_chan,
3845 rotated_offset_reg, rotated_offset_chan);
3846 if (r)
3847 return r;
3848 }
3849 }
3850 }
3851
3852 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3853 r600_fetch_tess_io_info(&ctx);
3854
3855 if (shader->two_side && ctx.colors_used) {
3856 if ((r = process_twoside_color_inputs(&ctx)))
3857 return r;
3858 }
3859
3860 tgsi_parse_init(&ctx.parse, tokens);
3861 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3862 tgsi_parse_token(&ctx.parse);
3863 switch (ctx.parse.FullToken.Token.Type) {
3864 case TGSI_TOKEN_TYPE_INSTRUCTION:
3865 r = tgsi_is_supported(&ctx);
3866 if (r)
3867 goto out_err;
3868 ctx.max_driver_temp_used = 0;
3869 /* reserve first tmp for everyone */
3870 r600_get_temp(&ctx);
3871
3872 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3873 if ((r = tgsi_split_constant(&ctx)))
3874 goto out_err;
3875 if ((r = tgsi_split_literal_constant(&ctx)))
3876 goto out_err;
3877 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3878 if ((r = tgsi_split_gs_inputs(&ctx)))
3879 goto out_err;
3880 } else if (lds_inputs) {
3881 if ((r = tgsi_split_lds_inputs(&ctx)))
3882 goto out_err;
3883 }
3884 if (ctx.bc->chip_class == CAYMAN)
3885 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3886 else if (ctx.bc->chip_class >= EVERGREEN)
3887 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3888 else
3889 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3890 r = ctx.inst_info->process(&ctx);
3891 if (r)
3892 goto out_err;
3893
3894 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3895 r = r600_store_tcs_output(&ctx);
3896 if (r)
3897 goto out_err;
3898 }
3899 break;
3900 default:
3901 break;
3902 }
3903 }
3904
3905 /* Reset the temporary register counter. */
3906 ctx.max_driver_temp_used = 0;
3907
3908 noutput = shader->noutput;
3909
3910 if (!ring_outputs && ctx.clip_vertex_write) {
3911 unsigned clipdist_temp[2];
3912
3913 clipdist_temp[0] = r600_get_temp(&ctx);
3914 clipdist_temp[1] = r600_get_temp(&ctx);
3915
3916 /* need to convert a clipvertex write into clipdistance writes and not export
3917 the clip vertex anymore */
3918
3919 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3920 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3921 shader->output[noutput].gpr = clipdist_temp[0];
3922 noutput++;
3923 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3924 shader->output[noutput].gpr = clipdist_temp[1];
3925 noutput++;
3926
3927 /* reset spi_sid for clipvertex output to avoid confusing spi */
3928 shader->output[ctx.cv_output].spi_sid = 0;
3929
3930 shader->clip_dist_write = 0xFF;
3931 shader->cc_dist_mask = 0xFF;
3932
3933 for (i = 0; i < 8; i++) {
3934 int oreg = i >> 2;
3935 int ochan = i & 3;
3936
3937 for (j = 0; j < 4; j++) {
3938 struct r600_bytecode_alu alu;
3939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3940 alu.op = ALU_OP2_DOT4;
3941 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3942 alu.src[0].chan = j;
3943
3944 alu.src[1].sel = 512 + i;
3945 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3946 alu.src[1].chan = j;
3947
3948 alu.dst.sel = clipdist_temp[oreg];
3949 alu.dst.chan = j;
3950 alu.dst.write = (j == ochan);
3951 if (j == 3)
3952 alu.last = 1;
3953 r = r600_bytecode_add_alu(ctx.bc, &alu);
3954 if (r)
3955 return r;
3956 }
3957 }
3958 }
3959
3960 /* Add stream outputs. */
3961 if (so.num_outputs) {
3962 bool emit = false;
3963 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3964 emit = true;
3965 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3966 emit = true;
3967 if (emit)
3968 emit_streamout(&ctx, &so, -1, NULL);
3969 }
3970 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3971 convert_edgeflag_to_int(&ctx);
3972
3973 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3974 r600_emit_tess_factor(&ctx);
3975
3976 if (lds_outputs) {
3977 if (ctx.type == PIPE_SHADER_VERTEX) {
3978 if (ctx.shader->noutput)
3979 emit_lds_vs_writes(&ctx);
3980 }
3981 } else if (ring_outputs) {
3982 if (shader->vs_as_es || shader->tes_as_es) {
3983 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3984 ctx.gs_export_gpr_tregs[1] = -1;
3985 ctx.gs_export_gpr_tregs[2] = -1;
3986 ctx.gs_export_gpr_tregs[3] = -1;
3987
3988 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3989 }
3990 } else {
3991 /* Export output */
3992 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3993
3994 for (i = 0, j = 0; i < noutput; i++, j++) {
3995 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3996 output[j].gpr = shader->output[i].gpr;
3997 output[j].elem_size = 3;
3998 output[j].swizzle_x = 0;
3999 output[j].swizzle_y = 1;
4000 output[j].swizzle_z = 2;
4001 output[j].swizzle_w = 3;
4002 output[j].burst_count = 1;
4003 output[j].type = 0xffffffff;
4004 output[j].op = CF_OP_EXPORT;
4005 switch (ctx.type) {
4006 case PIPE_SHADER_VERTEX:
4007 case PIPE_SHADER_TESS_EVAL:
4008 switch (shader->output[i].name) {
4009 case TGSI_SEMANTIC_POSITION:
4010 output[j].array_base = 60;
4011 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4012 pos_emitted = true;
4013 break;
4014
4015 case TGSI_SEMANTIC_PSIZE:
4016 output[j].array_base = 61;
4017 output[j].swizzle_y = 7;
4018 output[j].swizzle_z = 7;
4019 output[j].swizzle_w = 7;
4020 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4021 pos_emitted = true;
4022 break;
4023 case TGSI_SEMANTIC_EDGEFLAG:
4024 output[j].array_base = 61;
4025 output[j].swizzle_x = 7;
4026 output[j].swizzle_y = 0;
4027 output[j].swizzle_z = 7;
4028 output[j].swizzle_w = 7;
4029 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4030 pos_emitted = true;
4031 break;
4032 case TGSI_SEMANTIC_LAYER:
4033 /* spi_sid is 0 for outputs that are
4034 * not consumed by PS */
4035 if (shader->output[i].spi_sid) {
4036 output[j].array_base = next_param_base++;
4037 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4038 j++;
4039 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
4040 }
4041 output[j].array_base = 61;
4042 output[j].swizzle_x = 7;
4043 output[j].swizzle_y = 7;
4044 output[j].swizzle_z = 0;
4045 output[j].swizzle_w = 7;
4046 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4047 pos_emitted = true;
4048 break;
4049 case TGSI_SEMANTIC_VIEWPORT_INDEX:
4050 /* spi_sid is 0 for outputs that are
4051 * not consumed by PS */
4052 if (shader->output[i].spi_sid) {
4053 output[j].array_base = next_param_base++;
4054 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4055 j++;
4056 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
4057 }
4058 output[j].array_base = 61;
4059 output[j].swizzle_x = 7;
4060 output[j].swizzle_y = 7;
4061 output[j].swizzle_z = 7;
4062 output[j].swizzle_w = 0;
4063 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4064 pos_emitted = true;
4065 break;
4066 case TGSI_SEMANTIC_CLIPVERTEX:
4067 j--;
4068 break;
4069 case TGSI_SEMANTIC_CLIPDIST:
4070 output[j].array_base = next_clip_base++;
4071 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4072 pos_emitted = true;
4073 /* spi_sid is 0 for clipdistance outputs that were generated
4074 * for clipvertex - we don't need to pass them to PS */
4075 if (shader->output[i].spi_sid) {
4076 j++;
4077 /* duplicate it as PARAM to pass to the pixel shader */
4078 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
4079 output[j].array_base = next_param_base++;
4080 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4081 }
4082 break;
4083 case TGSI_SEMANTIC_FOG:
4084 output[j].swizzle_y = 4; /* 0 */
4085 output[j].swizzle_z = 4; /* 0 */
4086 output[j].swizzle_w = 5; /* 1 */
4087 break;
4088 case TGSI_SEMANTIC_PRIMID:
4089 output[j].swizzle_x = 2;
4090 output[j].swizzle_y = 4; /* 0 */
4091 output[j].swizzle_z = 4; /* 0 */
4092 output[j].swizzle_w = 4; /* 0 */
4093 break;
4094 }
4095
4096 break;
4097 case PIPE_SHADER_FRAGMENT:
4098 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
4099 /* never export more colors than the number of CBs */
4100 if (shader->output[i].sid >= max_color_exports) {
4101 /* skip export */
4102 j--;
4103 continue;
4104 }
4105 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
4106 output[j].array_base = shader->output[i].sid;
4107 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4108 shader->nr_ps_color_exports++;
4109 shader->ps_color_export_mask |= (0xf << (shader->output[i].sid * 4));
4110
4111 /* If the i-th target format is set, all previous target formats must
4112 * be non-zero to avoid hangs. - from radeonsi, seems to apply to eg as well.
4113 */
4114 if (shader->output[i].sid > 0)
4115 for (unsigned x = 0; x < shader->output[i].sid; x++)
4116 shader->ps_color_export_mask |= (1 << (x*4));
4117
4118 if (shader->output[i].sid > shader->ps_export_highest)
4119 shader->ps_export_highest = shader->output[i].sid;
4120 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
4121 for (k = 1; k < max_color_exports; k++) {
4122 j++;
4123 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4124 output[j].gpr = shader->output[i].gpr;
4125 output[j].elem_size = 3;
4126 output[j].swizzle_x = 0;
4127 output[j].swizzle_y = 1;
4128 output[j].swizzle_z = 2;
4129 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
4130 output[j].burst_count = 1;
4131 output[j].array_base = k;
4132 output[j].op = CF_OP_EXPORT;
4133 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4134 shader->nr_ps_color_exports++;
4135 if (k > shader->ps_export_highest)
4136 shader->ps_export_highest = k;
4137 shader->ps_color_export_mask |= (0xf << (j * 4));
4138 }
4139 }
4140 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
4141 output[j].array_base = 61;
4142 output[j].swizzle_x = 2;
4143 output[j].swizzle_y = 7;
4144 output[j].swizzle_z = output[j].swizzle_w = 7;
4145 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4146 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
4147 output[j].array_base = 61;
4148 output[j].swizzle_x = 7;
4149 output[j].swizzle_y = 1;
4150 output[j].swizzle_z = output[j].swizzle_w = 7;
4151 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4152 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
4153 output[j].array_base = 61;
4154 output[j].swizzle_x = 7;
4155 output[j].swizzle_y = 7;
4156 output[j].swizzle_z = 0;
4157 output[j].swizzle_w = 7;
4158 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4159 } else {
4160 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
4161 r = -EINVAL;
4162 goto out_err;
4163 }
4164 break;
4165 case PIPE_SHADER_TESS_CTRL:
4166 break;
4167 default:
4168 R600_ERR("unsupported processor type %d\n", ctx.type);
4169 r = -EINVAL;
4170 goto out_err;
4171 }
4172
4173 if (output[j].type == 0xffffffff) {
4174 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4175 output[j].array_base = next_param_base++;
4176 }
4177 }
4178
4179 /* add fake position export */
4180 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
4181 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4182 output[j].gpr = 0;
4183 output[j].elem_size = 3;
4184 output[j].swizzle_x = 7;
4185 output[j].swizzle_y = 7;
4186 output[j].swizzle_z = 7;
4187 output[j].swizzle_w = 7;
4188 output[j].burst_count = 1;
4189 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4190 output[j].array_base = 60;
4191 output[j].op = CF_OP_EXPORT;
4192 j++;
4193 }
4194
4195 /* add fake param output for vertex shader if no param is exported */
4196 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
4197 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4198 output[j].gpr = 0;
4199 output[j].elem_size = 3;
4200 output[j].swizzle_x = 7;
4201 output[j].swizzle_y = 7;
4202 output[j].swizzle_z = 7;
4203 output[j].swizzle_w = 7;
4204 output[j].burst_count = 1;
4205 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4206 output[j].array_base = 0;
4207 output[j].op = CF_OP_EXPORT;
4208 j++;
4209 }
4210
4211 /* add fake pixel export */
4212 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
4213 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4214 output[j].gpr = 0;
4215 output[j].elem_size = 3;
4216 output[j].swizzle_x = 7;
4217 output[j].swizzle_y = 7;
4218 output[j].swizzle_z = 7;
4219 output[j].swizzle_w = 7;
4220 output[j].burst_count = 1;
4221 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4222 output[j].array_base = 0;
4223 output[j].op = CF_OP_EXPORT;
4224 j++;
4225 shader->nr_ps_color_exports++;
4226 shader->ps_color_export_mask = 0xf;
4227 }
4228
4229 noutput = j;
4230
4231 /* set export done on last export of each type */
4232 for (k = noutput - 1, output_done = 0; k >= 0; k--) {
4233 if (!(output_done & (1 << output[k].type))) {
4234 output_done |= (1 << output[k].type);
4235 output[k].op = CF_OP_EXPORT_DONE;
4236 }
4237 }
4238 /* add output to bytecode */
4239 for (i = 0; i < noutput; i++) {
4240 r = r600_bytecode_add_output(ctx.bc, &output[i]);
4241 if (r)
4242 goto out_err;
4243 }
4244 }
4245
4246 /* add program end */
4247 if (ctx.bc->chip_class == CAYMAN)
4248 cm_bytecode_add_cf_end(ctx.bc);
4249 else {
4250 const struct cf_op_info *last = NULL;
4251
4252 if (ctx.bc->cf_last)
4253 last = r600_isa_cf(ctx.bc->cf_last->op);
4254
4255 /* alu clause instructions don't have EOP bit, so add NOP */
4256 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_POP)
4257 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
4258
4259 ctx.bc->cf_last->end_of_program = 1;
4260 }
4261
4262 /* check GPR limit - we have 124 = 128 - 4
4263 * (4 are reserved as alu clause temporary registers) */
4264 if (ctx.bc->ngpr > 124) {
4265 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
4266 r = -ENOMEM;
4267 goto out_err;
4268 }
4269
4270 if (ctx.type == PIPE_SHADER_GEOMETRY) {
4271 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
4272 return r;
4273 }
4274
4275 free(ctx.spilled_arrays);
4276 free(ctx.array_infos);
4277 free(ctx.literals);
4278 tgsi_parse_free(&ctx.parse);
4279 return 0;
4280 out_err:
4281 free(ctx.spilled_arrays);
4282 free(ctx.array_infos);
4283 free(ctx.literals);
4284 tgsi_parse_free(&ctx.parse);
4285 return r;
4286 }
4287
4288 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
4289 {
4290 const unsigned tgsi_opcode =
4291 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
4292 R600_ERR("%s tgsi opcode unsupported\n",
4293 tgsi_get_opcode_name(tgsi_opcode));
4294 return -EINVAL;
4295 }
4296
4297 static int tgsi_end(struct r600_shader_ctx *ctx UNUSED)
4298 {
4299 return 0;
4300 }
4301
4302 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
4303 const struct r600_shader_src *shader_src,
4304 unsigned chan)
4305 {
4306 bc_src->sel = shader_src->sel;
4307 bc_src->chan = shader_src->swizzle[chan];
4308 bc_src->neg = shader_src->neg;
4309 bc_src->abs = shader_src->abs;
4310 bc_src->rel = shader_src->rel;
4311 bc_src->value = shader_src->value[bc_src->chan];
4312 bc_src->kc_bank = shader_src->kc_bank;
4313 bc_src->kc_rel = shader_src->kc_rel;
4314 }
4315
4316 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
4317 {
4318 bc_src->abs = 1;
4319 bc_src->neg = 0;
4320 }
4321
4322 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
4323 {
4324 bc_src->neg = !bc_src->neg;
4325 }
4326
4327 static void tgsi_dst(struct r600_shader_ctx *ctx,
4328 const struct tgsi_full_dst_register *tgsi_dst,
4329 unsigned swizzle,
4330 struct r600_bytecode_alu_dst *r600_dst)
4331 {
4332 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4333
4334 if (tgsi_dst->Register.File == TGSI_FILE_TEMPORARY) {
4335 bool spilled;
4336 unsigned idx;
4337
4338 idx = map_tgsi_reg_index_to_r600_gpr(ctx, tgsi_dst->Register.Index, &spilled);
4339
4340 if (spilled) {
4341 struct r600_bytecode_output cf;
4342 int reg = r600_get_temp(ctx);
4343 int r;
4344
4345 r600_dst->sel = reg;
4346 r600_dst->chan = swizzle;
4347 r600_dst->write = 1;
4348 if (inst->Instruction.Saturate) {
4349 r600_dst->clamp = 1;
4350 }
4351
4352 // needs to be added after op using tgsi_dst
4353 memset(&cf, 0, sizeof(struct r600_bytecode_output));
4354 cf.op = CF_OP_MEM_SCRATCH;
4355 cf.elem_size = 3;
4356 cf.gpr = reg;
4357 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
4358 cf.mark = 1;
4359 cf.comp_mask = inst->Dst[0].Register.WriteMask;
4360 cf.swizzle_x = 0;
4361 cf.swizzle_y = 1;
4362 cf.swizzle_z = 2;
4363 cf.swizzle_w = 3;
4364 cf.burst_count = 1;
4365
4366 get_spilled_array_base_and_size(ctx, tgsi_dst->Register.Index,
4367 &cf.array_base, &cf.array_size);
4368
4369 if (tgsi_dst->Register.Indirect) {
4370 if (ctx->bc->chip_class < R700)
4371 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
4372 else
4373 cf.type = 3; // V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK;
4374 cf.index_gpr = ctx->bc->ar_reg;
4375 }
4376 else {
4377 cf.array_base += idx;
4378 cf.array_size = 0;
4379 }
4380
4381 r = r600_bytecode_add_pending_output(ctx->bc, &cf);
4382 if (r)
4383 return;
4384
4385 if (ctx->bc->chip_class >= R700)
4386 r600_bytecode_need_wait_ack(ctx->bc, true);
4387
4388 return;
4389 }
4390 else {
4391 r600_dst->sel = idx;
4392 }
4393 }
4394 else {
4395 r600_dst->sel = tgsi_dst->Register.Index;
4396 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
4397 }
4398 r600_dst->chan = swizzle;
4399 r600_dst->write = 1;
4400 if (inst->Instruction.Saturate) {
4401 r600_dst->clamp = 1;
4402 }
4403 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
4404 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
4405 return;
4406 }
4407 }
4408 if (tgsi_dst->Register.Indirect)
4409 r600_dst->rel = V_SQ_REL_RELATIVE;
4410
4411 }
4412
4413 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap, int dest_temp, int op_override)
4414 {
4415 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4416 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4417 struct r600_bytecode_alu alu;
4418 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4419 int use_tmp = 0;
4420 int swizzle_x = inst->Src[0].Register.SwizzleX;
4421
4422 if (singledest) {
4423 switch (write_mask) {
4424 case 0x1:
4425 if (swizzle_x == 2) {
4426 write_mask = 0xc;
4427 use_tmp = 3;
4428 } else
4429 write_mask = 0x3;
4430 break;
4431 case 0x2:
4432 if (swizzle_x == 2) {
4433 write_mask = 0xc;
4434 use_tmp = 3;
4435 } else {
4436 write_mask = 0x3;
4437 use_tmp = 1;
4438 }
4439 break;
4440 case 0x4:
4441 if (swizzle_x == 0) {
4442 write_mask = 0x3;
4443 use_tmp = 1;
4444 } else
4445 write_mask = 0xc;
4446 break;
4447 case 0x8:
4448 if (swizzle_x == 0) {
4449 write_mask = 0x3;
4450 use_tmp = 1;
4451 } else {
4452 write_mask = 0xc;
4453 use_tmp = 3;
4454 }
4455 break;
4456 }
4457 }
4458
4459 lasti = tgsi_last_instruction(write_mask);
4460 for (i = 0; i <= lasti; i++) {
4461
4462 if (!(write_mask & (1 << i)))
4463 continue;
4464
4465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4466
4467 if (singledest) {
4468 if (use_tmp || dest_temp) {
4469 alu.dst.sel = use_tmp ? ctx->temp_reg : dest_temp;
4470 alu.dst.chan = i;
4471 alu.dst.write = 1;
4472 } else {
4473 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4474 }
4475 if (i == 1 || i == 3)
4476 alu.dst.write = 0;
4477 } else
4478 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4479
4480 alu.op = op_override ? op_override : ctx->inst_info->op;
4481 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
4482 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4483 } else if (!swap) {
4484 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4485 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4486 }
4487 } else {
4488 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
4489 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
4490 }
4491
4492 /* handle some special cases */
4493 if (i == 1 || i == 3) {
4494 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
4495 case TGSI_OPCODE_DABS:
4496 r600_bytecode_src_set_abs(&alu.src[0]);
4497 break;
4498 default:
4499 break;
4500 }
4501 }
4502 if (i == lasti) {
4503 alu.last = 1;
4504 }
4505 r = r600_bytecode_add_alu(ctx->bc, &alu);
4506 if (r)
4507 return r;
4508 }
4509
4510 if (use_tmp) {
4511 write_mask = inst->Dst[0].Register.WriteMask;
4512
4513 lasti = tgsi_last_instruction(write_mask);
4514 /* move result from temp to dst */
4515 for (i = 0; i <= lasti; i++) {
4516 if (!(write_mask & (1 << i)))
4517 continue;
4518
4519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4520 alu.op = ALU_OP1_MOV;
4521
4522 if (dest_temp) {
4523 alu.dst.sel = dest_temp;
4524 alu.dst.chan = i;
4525 alu.dst.write = 1;
4526 } else
4527 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4528 alu.src[0].sel = ctx->temp_reg;
4529 alu.src[0].chan = use_tmp - 1;
4530 alu.last = (i == lasti);
4531
4532 r = r600_bytecode_add_alu(ctx->bc, &alu);
4533 if (r)
4534 return r;
4535 }
4536 }
4537 return 0;
4538 }
4539
4540 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
4541 {
4542 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4543 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4544 /* confirm writemasking */
4545 if ((write_mask & 0x3) != 0x3 &&
4546 (write_mask & 0xc) != 0xc) {
4547 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4548 return -1;
4549 }
4550 return tgsi_op2_64_params(ctx, false, false, 0, 0);
4551 }
4552
4553 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4554 {
4555 return tgsi_op2_64_params(ctx, true, false, 0, 0);
4556 }
4557
4558 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4559 {
4560 return tgsi_op2_64_params(ctx, true, true, 0, 0);
4561 }
4562
4563 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4564 {
4565 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4566 struct r600_bytecode_alu alu;
4567 int i, j, r;
4568 int lasti = 3;
4569 int tmp = r600_get_temp(ctx);
4570
4571 for (i = 0; i < lasti + 1; i++) {
4572
4573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4574 alu.op = ctx->inst_info->op;
4575 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4576 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4577 }
4578
4579 if (inst->Dst[0].Register.WriteMask & (1 << i))
4580 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4581 else
4582 alu.dst.sel = tmp;
4583
4584 alu.dst.chan = i;
4585 alu.is_op3 = 1;
4586 if (i == lasti) {
4587 alu.last = 1;
4588 }
4589 r = r600_bytecode_add_alu(ctx->bc, &alu);
4590 if (r)
4591 return r;
4592 }
4593 return 0;
4594 }
4595
4596 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4597 {
4598 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4599 struct r600_bytecode_alu alu;
4600 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4601 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4602 /* use temp register if trans_only and more than one dst component */
4603 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4604 unsigned op = ctx->inst_info->op;
4605
4606 if (op == ALU_OP2_MUL_IEEE &&
4607 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4608 op = ALU_OP2_MUL;
4609
4610 for (i = 0; i <= lasti; i++) {
4611 if (!(write_mask & (1 << i)))
4612 continue;
4613
4614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4615 if (use_tmp) {
4616 alu.dst.sel = ctx->temp_reg;
4617 alu.dst.chan = i;
4618 alu.dst.write = 1;
4619 } else
4620 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4621
4622 alu.op = op;
4623 if (!swap) {
4624 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4625 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4626 }
4627 } else {
4628 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4629 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4630 }
4631 if (i == lasti || trans_only) {
4632 alu.last = 1;
4633 }
4634 r = r600_bytecode_add_alu(ctx->bc, &alu);
4635 if (r)
4636 return r;
4637 }
4638
4639 if (use_tmp) {
4640 /* move result from temp to dst */
4641 for (i = 0; i <= lasti; i++) {
4642 if (!(write_mask & (1 << i)))
4643 continue;
4644
4645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4646 alu.op = ALU_OP1_MOV;
4647 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4648 alu.src[0].sel = ctx->temp_reg;
4649 alu.src[0].chan = i;
4650 alu.last = (i == lasti);
4651
4652 r = r600_bytecode_add_alu(ctx->bc, &alu);
4653 if (r)
4654 return r;
4655 }
4656 }
4657 return 0;
4658 }
4659
4660 static int tgsi_op2(struct r600_shader_ctx *ctx)
4661 {
4662 return tgsi_op2_s(ctx, 0, 0);
4663 }
4664
4665 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4666 {
4667 return tgsi_op2_s(ctx, 1, 0);
4668 }
4669
4670 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4671 {
4672 return tgsi_op2_s(ctx, 0, 1);
4673 }
4674
4675 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4676 {
4677 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4678 struct r600_bytecode_alu alu;
4679 int i, r;
4680 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4681
4682 for (i = 0; i < lasti + 1; i++) {
4683
4684 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4685 continue;
4686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4687 alu.op = ctx->inst_info->op;
4688
4689 alu.src[0].sel = V_SQ_ALU_SRC_0;
4690
4691 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4692
4693 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4694
4695 if (i == lasti) {
4696 alu.last = 1;
4697 }
4698 r = r600_bytecode_add_alu(ctx->bc, &alu);
4699 if (r)
4700 return r;
4701 }
4702 return 0;
4703
4704 }
4705
4706 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4707 {
4708 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4709 struct r600_bytecode_alu alu;
4710 int i, r;
4711 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4712
4713 for (i = 0; i < lasti + 1; i++) {
4714
4715 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4716 continue;
4717 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4718 alu.op = ALU_OP1_MOV;
4719
4720 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4721
4722 if (i == 1 || i == 3)
4723 r600_bytecode_src_toggle_neg(&alu.src[0]);
4724 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4725
4726 if (i == lasti) {
4727 alu.last = 1;
4728 }
4729 r = r600_bytecode_add_alu(ctx->bc, &alu);
4730 if (r)
4731 return r;
4732 }
4733 return 0;
4734
4735 }
4736
4737 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4738 {
4739 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4740 struct r600_bytecode_alu alu;
4741 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4742 int i, j, r;
4743
4744 for (i = 0; i <= 3; i++) {
4745 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4746 alu.op = ctx->inst_info->op;
4747
4748 alu.dst.sel = ctx->temp_reg;
4749 alu.dst.chan = i;
4750 alu.dst.write = 1;
4751 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4752 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4753 }
4754
4755 if (i == 3)
4756 alu.last = 1;
4757
4758 r = r600_bytecode_add_alu(ctx->bc, &alu);
4759 if (r)
4760 return r;
4761 }
4762
4763 /* Replicate significand result across channels. */
4764 for (i = 0; i <= 3; i++) {
4765 if (!(write_mask & (1 << i)))
4766 continue;
4767
4768 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4769 alu.op = ALU_OP1_MOV;
4770 alu.src[0].chan = (i & 1) + 2;
4771 alu.src[0].sel = ctx->temp_reg;
4772
4773 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4774 alu.dst.write = 1;
4775 alu.last = 1;
4776 r = r600_bytecode_add_alu(ctx->bc, &alu);
4777 if (r)
4778 return r;
4779 }
4780
4781 for (i = 0; i <= 3; i++) {
4782 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4783 /* MOV third channels to writemask dst1 */
4784 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4785 alu.op = ALU_OP1_MOV;
4786 alu.src[0].chan = 1;
4787 alu.src[0].sel = ctx->temp_reg;
4788
4789 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4790 alu.last = 1;
4791 r = r600_bytecode_add_alu(ctx->bc, &alu);
4792 if (r)
4793 return r;
4794 break;
4795 }
4796 }
4797 return 0;
4798 }
4799
4800
4801 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4802 {
4803 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4804 struct r600_bytecode_alu alu;
4805 int i, c, r;
4806 int write_mask = inst->Dst[0].Register.WriteMask;
4807 int temp_reg = r600_get_temp(ctx);
4808
4809 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4810 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4811
4812 for (c = 0; c < 2; c++) {
4813 int dchan = c * 2;
4814 if (write_mask & (0x3 << dchan)) {
4815 /* split into 24-bit int and 8-bit int */
4816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4817 alu.op = ALU_OP2_AND_INT;
4818 alu.dst.sel = temp_reg;
4819 alu.dst.chan = dchan;
4820 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4821 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4822 alu.src[1].value = 0xffffff00;
4823 alu.dst.write = 1;
4824 r = r600_bytecode_add_alu(ctx->bc, &alu);
4825 if (r)
4826 return r;
4827
4828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4829 alu.op = ALU_OP2_AND_INT;
4830 alu.dst.sel = temp_reg;
4831 alu.dst.chan = dchan + 1;
4832 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4833 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4834 alu.src[1].value = 0xff;
4835 alu.dst.write = 1;
4836 alu.last = 1;
4837 r = r600_bytecode_add_alu(ctx->bc, &alu);
4838 if (r)
4839 return r;
4840 }
4841 }
4842
4843 for (c = 0; c < 2; c++) {
4844 int dchan = c * 2;
4845 if (write_mask & (0x3 << dchan)) {
4846 for (i = dchan; i <= dchan + 1; i++) {
4847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4848 alu.op = i == dchan ? ctx->inst_info->op : ALU_OP1_UINT_TO_FLT;
4849
4850 alu.src[0].sel = temp_reg;
4851 alu.src[0].chan = i;
4852 alu.dst.sel = temp_reg;
4853 alu.dst.chan = i;
4854 alu.dst.write = 1;
4855 if (ctx->bc->chip_class == CAYMAN)
4856 alu.last = i == dchan + 1;
4857 else
4858 alu.last = 1; /* trans only ops on evergreen */
4859
4860 r = r600_bytecode_add_alu(ctx->bc, &alu);
4861 if (r)
4862 return r;
4863 }
4864 }
4865 }
4866
4867 for (c = 0; c < 2; c++) {
4868 int dchan = c * 2;
4869 if (write_mask & (0x3 << dchan)) {
4870 for (i = 0; i < 4; i++) {
4871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4872 alu.op = ALU_OP1_FLT32_TO_FLT64;
4873
4874 alu.src[0].chan = dchan + (i / 2);
4875 if (i == 0 || i == 2)
4876 alu.src[0].sel = temp_reg;
4877 else {
4878 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4879 alu.src[0].value = 0x0;
4880 }
4881 alu.dst.sel = ctx->temp_reg;
4882 alu.dst.chan = i;
4883 alu.last = i == 3;
4884 alu.dst.write = 1;
4885
4886 r = r600_bytecode_add_alu(ctx->bc, &alu);
4887 if (r)
4888 return r;
4889 }
4890
4891 for (i = 0; i <= 1; i++) {
4892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4893 alu.op = ALU_OP2_ADD_64;
4894
4895 alu.src[0].chan = fp64_switch(i);
4896 alu.src[0].sel = ctx->temp_reg;
4897
4898 alu.src[1].chan = fp64_switch(i + 2);
4899 alu.src[1].sel = ctx->temp_reg;
4900 tgsi_dst(ctx, &inst->Dst[0], dchan + i, &alu.dst);
4901 alu.last = i == 1;
4902
4903 r = r600_bytecode_add_alu(ctx->bc, &alu);
4904 if (r)
4905 return r;
4906 }
4907 }
4908 }
4909
4910 return 0;
4911 }
4912
4913 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4914 {
4915 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4916 struct r600_bytecode_alu alu;
4917 int i, r;
4918 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4919 int treg = r600_get_temp(ctx);
4920 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4921 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4922
4923 /* do a 64->32 into a temp register */
4924 r = tgsi_op2_64_params(ctx, true, false, treg, ALU_OP1_FLT64_TO_FLT32);
4925 if (r)
4926 return r;
4927
4928 for (i = 0; i <= lasti; i++) {
4929 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4930 continue;
4931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4932 alu.op = ctx->inst_info->op;
4933
4934 alu.src[0].chan = i;
4935 alu.src[0].sel = treg;
4936 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4937 alu.last = (i == lasti);
4938
4939 r = r600_bytecode_add_alu(ctx->bc, &alu);
4940 if (r)
4941 return r;
4942 }
4943
4944 return 0;
4945 }
4946
4947 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4948 unsigned op,
4949 int dst_reg,
4950 struct r600_shader_src *src,
4951 bool abs)
4952 {
4953 struct r600_bytecode_alu alu;
4954 const int last_slot = 3;
4955 int r;
4956
4957 /* these have to write the result to X/Y by the looks of it */
4958 for (int i = 0 ; i < last_slot; i++) {
4959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4960 alu.op = op;
4961
4962 r600_bytecode_src(&alu.src[0], src, 1);
4963 r600_bytecode_src(&alu.src[1], src, 0);
4964
4965 if (abs)
4966 r600_bytecode_src_set_abs(&alu.src[1]);
4967
4968 alu.dst.sel = dst_reg;
4969 alu.dst.chan = i;
4970 alu.dst.write = (i == 0 || i == 1);
4971
4972 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4973 alu.last = 1;
4974 r = r600_bytecode_add_alu(bc, &alu);
4975 if (r)
4976 return r;
4977 }
4978
4979 return 0;
4980 }
4981
4982 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4983 {
4984 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4985 int i, r;
4986 struct r600_bytecode_alu alu;
4987 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4988 int t1 = ctx->temp_reg;
4989
4990 /* should only be one src regs */
4991 assert(inst->Instruction.NumSrcRegs == 1);
4992
4993 /* only support one double at a time */
4994 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4995 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4996
4997 r = cayman_emit_unary_double_raw(
4998 ctx->bc, ctx->inst_info->op, t1,
4999 &ctx->src[0],
5000 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
5001 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
5002 if (r)
5003 return r;
5004
5005 for (i = 0 ; i <= lasti; i++) {
5006 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5007 continue;
5008 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5009 alu.op = ALU_OP1_MOV;
5010 alu.src[0].sel = t1;
5011 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
5012 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5013 alu.dst.write = 1;
5014 if (i == lasti)
5015 alu.last = 1;
5016 r = r600_bytecode_add_alu(ctx->bc, &alu);
5017 if (r)
5018 return r;
5019 }
5020 return 0;
5021 }
5022
5023 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
5024 {
5025 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5026 int i, j, r;
5027 struct r600_bytecode_alu alu;
5028 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5029
5030 for (i = 0 ; i < last_slot; i++) {
5031 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5032 alu.op = ctx->inst_info->op;
5033 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5034 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
5035
5036 /* RSQ should take the absolute value of src */
5037 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
5038 r600_bytecode_src_set_abs(&alu.src[j]);
5039 }
5040 }
5041 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5042 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5043
5044 if (i == last_slot - 1)
5045 alu.last = 1;
5046 r = r600_bytecode_add_alu(ctx->bc, &alu);
5047 if (r)
5048 return r;
5049 }
5050 return 0;
5051 }
5052
5053 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
5054 {
5055 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5056 int i, j, k, r;
5057 struct r600_bytecode_alu alu;
5058 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5059 int t1 = ctx->temp_reg;
5060
5061 for (k = 0; k <= lasti; k++) {
5062 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
5063 continue;
5064
5065 for (i = 0 ; i < 4; i++) {
5066 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5067 alu.op = ctx->inst_info->op;
5068 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5069 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
5070 }
5071 alu.dst.sel = t1;
5072 alu.dst.chan = i;
5073 alu.dst.write = (i == k);
5074 if (i == 3)
5075 alu.last = 1;
5076 r = r600_bytecode_add_alu(ctx->bc, &alu);
5077 if (r)
5078 return r;
5079 }
5080 }
5081
5082 for (i = 0 ; i <= lasti; i++) {
5083 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5084 continue;
5085 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5086 alu.op = ALU_OP1_MOV;
5087 alu.src[0].sel = t1;
5088 alu.src[0].chan = i;
5089 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5090 alu.dst.write = 1;
5091 if (i == lasti)
5092 alu.last = 1;
5093 r = r600_bytecode_add_alu(ctx->bc, &alu);
5094 if (r)
5095 return r;
5096 }
5097
5098 return 0;
5099 }
5100
5101
5102 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
5103 {
5104 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5105 int i, j, k, r;
5106 struct r600_bytecode_alu alu;
5107 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5108 int t1 = ctx->temp_reg;
5109
5110 /* t1 would get overwritten below if we actually tried to
5111 * multiply two pairs of doubles at a time. */
5112 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
5113 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
5114
5115 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
5116
5117 for (i = 0; i < 4; i++) {
5118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5119 alu.op = ctx->inst_info->op;
5120 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5121 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
5122 }
5123 alu.dst.sel = t1;
5124 alu.dst.chan = i;
5125 alu.dst.write = 1;
5126 if (i == 3)
5127 alu.last = 1;
5128 r = r600_bytecode_add_alu(ctx->bc, &alu);
5129 if (r)
5130 return r;
5131 }
5132
5133 for (i = 0; i <= lasti; i++) {
5134 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5135 continue;
5136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5137 alu.op = ALU_OP1_MOV;
5138 alu.src[0].sel = t1;
5139 alu.src[0].chan = i;
5140 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5141 alu.dst.write = 1;
5142 if (i == lasti)
5143 alu.last = 1;
5144 r = r600_bytecode_add_alu(ctx->bc, &alu);
5145 if (r)
5146 return r;
5147 }
5148
5149 return 0;
5150 }
5151
5152 /*
5153 * Emit RECIP_64 + MUL_64 to implement division.
5154 */
5155 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
5156 {
5157 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5158 int r;
5159 struct r600_bytecode_alu alu;
5160 int t1 = ctx->temp_reg;
5161 int k;
5162
5163 /* Only support one double at a time. This is the same constraint as
5164 * in DMUL lowering. */
5165 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
5166 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
5167
5168 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
5169
5170 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
5171 if (r)
5172 return r;
5173
5174 for (int i = 0; i < 4; i++) {
5175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5176 alu.op = ALU_OP2_MUL_64;
5177
5178 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
5179
5180 alu.src[1].sel = t1;
5181 alu.src[1].chan = (i == 3) ? 0 : 1;
5182
5183 alu.dst.sel = t1;
5184 alu.dst.chan = i;
5185 alu.dst.write = 1;
5186 if (i == 3)
5187 alu.last = 1;
5188 r = r600_bytecode_add_alu(ctx->bc, &alu);
5189 if (r)
5190 return r;
5191 }
5192
5193 for (int i = 0; i < 2; i++) {
5194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5195 alu.op = ALU_OP1_MOV;
5196 alu.src[0].sel = t1;
5197 alu.src[0].chan = i;
5198 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
5199 alu.dst.write = 1;
5200 if (i == 1)
5201 alu.last = 1;
5202 r = r600_bytecode_add_alu(ctx->bc, &alu);
5203 if (r)
5204 return r;
5205 }
5206 return 0;
5207 }
5208
5209 /*
5210 * r600 - trunc to -PI..PI range
5211 * r700 - normalize by dividing by 2PI
5212 * see fdo bug 27901
5213 */
5214 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
5215 {
5216 int r;
5217 struct r600_bytecode_alu alu;
5218
5219 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5220 alu.op = ALU_OP3_MULADD;
5221 alu.is_op3 = 1;
5222
5223 alu.dst.chan = 0;
5224 alu.dst.sel = ctx->temp_reg;
5225 alu.dst.write = 1;
5226
5227 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5228
5229 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5230 alu.src[1].chan = 0;
5231 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
5232 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
5233 alu.src[2].chan = 0;
5234 alu.last = 1;
5235 r = r600_bytecode_add_alu(ctx->bc, &alu);
5236 if (r)
5237 return r;
5238
5239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5240 alu.op = ALU_OP1_FRACT;
5241
5242 alu.dst.chan = 0;
5243 alu.dst.sel = ctx->temp_reg;
5244 alu.dst.write = 1;
5245
5246 alu.src[0].sel = ctx->temp_reg;
5247 alu.src[0].chan = 0;
5248 alu.last = 1;
5249 r = r600_bytecode_add_alu(ctx->bc, &alu);
5250 if (r)
5251 return r;
5252
5253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5254 alu.op = ALU_OP3_MULADD;
5255 alu.is_op3 = 1;
5256
5257 alu.dst.chan = 0;
5258 alu.dst.sel = ctx->temp_reg;
5259 alu.dst.write = 1;
5260
5261 alu.src[0].sel = ctx->temp_reg;
5262 alu.src[0].chan = 0;
5263
5264 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5265 alu.src[1].chan = 0;
5266 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5267 alu.src[2].chan = 0;
5268
5269 if (ctx->bc->chip_class == R600) {
5270 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
5271 alu.src[2].value = u_bitcast_f2u(-M_PI);
5272 } else {
5273 alu.src[1].sel = V_SQ_ALU_SRC_1;
5274 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
5275 alu.src[2].neg = 1;
5276 }
5277
5278 alu.last = 1;
5279 r = r600_bytecode_add_alu(ctx->bc, &alu);
5280 if (r)
5281 return r;
5282 return 0;
5283 }
5284
5285 static int cayman_trig(struct r600_shader_ctx *ctx)
5286 {
5287 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5288 struct r600_bytecode_alu alu;
5289 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5290 int i, r;
5291
5292 r = tgsi_setup_trig(ctx);
5293 if (r)
5294 return r;
5295
5296
5297 for (i = 0; i < last_slot; i++) {
5298 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5299 alu.op = ctx->inst_info->op;
5300 alu.dst.chan = i;
5301
5302 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5303 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5304
5305 alu.src[0].sel = ctx->temp_reg;
5306 alu.src[0].chan = 0;
5307 if (i == last_slot - 1)
5308 alu.last = 1;
5309 r = r600_bytecode_add_alu(ctx->bc, &alu);
5310 if (r)
5311 return r;
5312 }
5313 return 0;
5314 }
5315
5316 static int tgsi_trig(struct r600_shader_ctx *ctx)
5317 {
5318 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5319 struct r600_bytecode_alu alu;
5320 int i, r;
5321 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5322
5323 r = tgsi_setup_trig(ctx);
5324 if (r)
5325 return r;
5326
5327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5328 alu.op = ctx->inst_info->op;
5329 alu.dst.chan = 0;
5330 alu.dst.sel = ctx->temp_reg;
5331 alu.dst.write = 1;
5332
5333 alu.src[0].sel = ctx->temp_reg;
5334 alu.src[0].chan = 0;
5335 alu.last = 1;
5336 r = r600_bytecode_add_alu(ctx->bc, &alu);
5337 if (r)
5338 return r;
5339
5340 /* replicate result */
5341 for (i = 0; i < lasti + 1; i++) {
5342 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5343 continue;
5344
5345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5346 alu.op = ALU_OP1_MOV;
5347
5348 alu.src[0].sel = ctx->temp_reg;
5349 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5350 if (i == lasti)
5351 alu.last = 1;
5352 r = r600_bytecode_add_alu(ctx->bc, &alu);
5353 if (r)
5354 return r;
5355 }
5356 return 0;
5357 }
5358
5359 static int tgsi_kill(struct r600_shader_ctx *ctx)
5360 {
5361 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5362 struct r600_bytecode_alu alu;
5363 int i, r;
5364
5365 for (i = 0; i < 4; i++) {
5366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5367 alu.op = ctx->inst_info->op;
5368
5369 alu.dst.chan = i;
5370
5371 alu.src[0].sel = V_SQ_ALU_SRC_0;
5372
5373 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
5374 alu.src[1].sel = V_SQ_ALU_SRC_1;
5375 alu.src[1].neg = 1;
5376 } else {
5377 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5378 }
5379 if (i == 3) {
5380 alu.last = 1;
5381 }
5382 r = r600_bytecode_add_alu(ctx->bc, &alu);
5383 if (r)
5384 return r;
5385 }
5386
5387 /* kill must be last in ALU */
5388 ctx->bc->force_add_cf = 1;
5389 ctx->shader->uses_kill = TRUE;
5390 return 0;
5391 }
5392
5393 static int tgsi_lit(struct r600_shader_ctx *ctx)
5394 {
5395 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5396 struct r600_bytecode_alu alu;
5397 int r;
5398
5399 /* tmp.x = max(src.y, 0.0) */
5400 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5401 alu.op = ALU_OP2_MAX;
5402 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
5403 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5404 alu.src[1].chan = 1;
5405
5406 alu.dst.sel = ctx->temp_reg;
5407 alu.dst.chan = 0;
5408 alu.dst.write = 1;
5409
5410 alu.last = 1;
5411 r = r600_bytecode_add_alu(ctx->bc, &alu);
5412 if (r)
5413 return r;
5414
5415 if (inst->Dst[0].Register.WriteMask & (1 << 2))
5416 {
5417 int chan;
5418 int sel;
5419 unsigned i;
5420
5421 if (ctx->bc->chip_class == CAYMAN) {
5422 for (i = 0; i < 3; i++) {
5423 /* tmp.z = log(tmp.x) */
5424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5425 alu.op = ALU_OP1_LOG_CLAMPED;
5426 alu.src[0].sel = ctx->temp_reg;
5427 alu.src[0].chan = 0;
5428 alu.dst.sel = ctx->temp_reg;
5429 alu.dst.chan = i;
5430 if (i == 2) {
5431 alu.dst.write = 1;
5432 alu.last = 1;
5433 } else
5434 alu.dst.write = 0;
5435
5436 r = r600_bytecode_add_alu(ctx->bc, &alu);
5437 if (r)
5438 return r;
5439 }
5440 } else {
5441 /* tmp.z = log(tmp.x) */
5442 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5443 alu.op = ALU_OP1_LOG_CLAMPED;
5444 alu.src[0].sel = ctx->temp_reg;
5445 alu.src[0].chan = 0;
5446 alu.dst.sel = ctx->temp_reg;
5447 alu.dst.chan = 2;
5448 alu.dst.write = 1;
5449 alu.last = 1;
5450 r = r600_bytecode_add_alu(ctx->bc, &alu);
5451 if (r)
5452 return r;
5453 }
5454
5455 chan = alu.dst.chan;
5456 sel = alu.dst.sel;
5457
5458 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
5459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5460 alu.op = ALU_OP3_MUL_LIT;
5461 alu.src[0].sel = sel;
5462 alu.src[0].chan = chan;
5463 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
5464 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
5465 alu.dst.sel = ctx->temp_reg;
5466 alu.dst.chan = 0;
5467 alu.dst.write = 1;
5468 alu.is_op3 = 1;
5469 alu.last = 1;
5470 r = r600_bytecode_add_alu(ctx->bc, &alu);
5471 if (r)
5472 return r;
5473
5474 if (ctx->bc->chip_class == CAYMAN) {
5475 for (i = 0; i < 3; i++) {
5476 /* dst.z = exp(tmp.x) */
5477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5478 alu.op = ALU_OP1_EXP_IEEE;
5479 alu.src[0].sel = ctx->temp_reg;
5480 alu.src[0].chan = 0;
5481 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5482 if (i == 2) {
5483 alu.dst.write = 1;
5484 alu.last = 1;
5485 } else
5486 alu.dst.write = 0;
5487 r = r600_bytecode_add_alu(ctx->bc, &alu);
5488 if (r)
5489 return r;
5490 }
5491 } else {
5492 /* dst.z = exp(tmp.x) */
5493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5494 alu.op = ALU_OP1_EXP_IEEE;
5495 alu.src[0].sel = ctx->temp_reg;
5496 alu.src[0].chan = 0;
5497 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5498 alu.last = 1;
5499 r = r600_bytecode_add_alu(ctx->bc, &alu);
5500 if (r)
5501 return r;
5502 }
5503 }
5504
5505 /* dst.x, <- 1.0 */
5506 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5507 alu.op = ALU_OP1_MOV;
5508 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
5509 alu.src[0].chan = 0;
5510 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5511 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
5512 r = r600_bytecode_add_alu(ctx->bc, &alu);
5513 if (r)
5514 return r;
5515
5516 /* dst.y = max(src.x, 0.0) */
5517 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5518 alu.op = ALU_OP2_MAX;
5519 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5520 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5521 alu.src[1].chan = 0;
5522 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
5523 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
5524 r = r600_bytecode_add_alu(ctx->bc, &alu);
5525 if (r)
5526 return r;
5527
5528 /* dst.w, <- 1.0 */
5529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5530 alu.op = ALU_OP1_MOV;
5531 alu.src[0].sel = V_SQ_ALU_SRC_1;
5532 alu.src[0].chan = 0;
5533 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
5534 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
5535 alu.last = 1;
5536 r = r600_bytecode_add_alu(ctx->bc, &alu);
5537 if (r)
5538 return r;
5539
5540 return 0;
5541 }
5542
5543 static int tgsi_rsq(struct r600_shader_ctx *ctx)
5544 {
5545 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5546 struct r600_bytecode_alu alu;
5547 int i, r;
5548
5549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5550
5551 alu.op = ALU_OP1_RECIPSQRT_IEEE;
5552
5553 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5554 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5555 r600_bytecode_src_set_abs(&alu.src[i]);
5556 }
5557 alu.dst.sel = ctx->temp_reg;
5558 alu.dst.write = 1;
5559 alu.last = 1;
5560 r = r600_bytecode_add_alu(ctx->bc, &alu);
5561 if (r)
5562 return r;
5563 /* replicate result */
5564 return tgsi_helper_tempx_replicate(ctx);
5565 }
5566
5567 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
5568 {
5569 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5570 struct r600_bytecode_alu alu;
5571 int i, r;
5572
5573 for (i = 0; i < 4; i++) {
5574 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5575 alu.src[0].sel = ctx->temp_reg;
5576 alu.op = ALU_OP1_MOV;
5577 alu.dst.chan = i;
5578 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5579 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5580 if (i == 3)
5581 alu.last = 1;
5582 r = r600_bytecode_add_alu(ctx->bc, &alu);
5583 if (r)
5584 return r;
5585 }
5586 return 0;
5587 }
5588
5589 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
5590 {
5591 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5592 struct r600_bytecode_alu alu;
5593 int i, r;
5594
5595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5596 alu.op = ctx->inst_info->op;
5597 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5598 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5599 }
5600 alu.dst.sel = ctx->temp_reg;
5601 alu.dst.write = 1;
5602 alu.last = 1;
5603 r = r600_bytecode_add_alu(ctx->bc, &alu);
5604 if (r)
5605 return r;
5606 /* replicate result */
5607 return tgsi_helper_tempx_replicate(ctx);
5608 }
5609
5610 static int cayman_pow(struct r600_shader_ctx *ctx)
5611 {
5612 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5613 int i, r;
5614 struct r600_bytecode_alu alu;
5615 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5616
5617 for (i = 0; i < 3; i++) {
5618 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5619 alu.op = ALU_OP1_LOG_IEEE;
5620 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5621 alu.dst.sel = ctx->temp_reg;
5622 alu.dst.chan = i;
5623 alu.dst.write = 1;
5624 if (i == 2)
5625 alu.last = 1;
5626 r = r600_bytecode_add_alu(ctx->bc, &alu);
5627 if (r)
5628 return r;
5629 }
5630
5631 /* b * LOG2(a) */
5632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5633 alu.op = ALU_OP2_MUL;
5634 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5635 alu.src[1].sel = ctx->temp_reg;
5636 alu.dst.sel = ctx->temp_reg;
5637 alu.dst.write = 1;
5638 alu.last = 1;
5639 r = r600_bytecode_add_alu(ctx->bc, &alu);
5640 if (r)
5641 return r;
5642
5643 for (i = 0; i < last_slot; i++) {
5644 /* POW(a,b) = EXP2(b * LOG2(a))*/
5645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5646 alu.op = ALU_OP1_EXP_IEEE;
5647 alu.src[0].sel = ctx->temp_reg;
5648
5649 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5650 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5651 if (i == last_slot - 1)
5652 alu.last = 1;
5653 r = r600_bytecode_add_alu(ctx->bc, &alu);
5654 if (r)
5655 return r;
5656 }
5657 return 0;
5658 }
5659
5660 static int tgsi_pow(struct r600_shader_ctx *ctx)
5661 {
5662 struct r600_bytecode_alu alu;
5663 int r;
5664
5665 /* LOG2(a) */
5666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5667 alu.op = ALU_OP1_LOG_IEEE;
5668 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5669 alu.dst.sel = ctx->temp_reg;
5670 alu.dst.write = 1;
5671 alu.last = 1;
5672 r = r600_bytecode_add_alu(ctx->bc, &alu);
5673 if (r)
5674 return r;
5675 /* b * LOG2(a) */
5676 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5677 alu.op = ALU_OP2_MUL;
5678 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5679 alu.src[1].sel = ctx->temp_reg;
5680 alu.dst.sel = ctx->temp_reg;
5681 alu.dst.write = 1;
5682 alu.last = 1;
5683 r = r600_bytecode_add_alu(ctx->bc, &alu);
5684 if (r)
5685 return r;
5686 /* POW(a,b) = EXP2(b * LOG2(a))*/
5687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5688 alu.op = ALU_OP1_EXP_IEEE;
5689 alu.src[0].sel = ctx->temp_reg;
5690 alu.dst.sel = ctx->temp_reg;
5691 alu.dst.write = 1;
5692 alu.last = 1;
5693 r = r600_bytecode_add_alu(ctx->bc, &alu);
5694 if (r)
5695 return r;
5696 return tgsi_helper_tempx_replicate(ctx);
5697 }
5698
5699 static int emit_mul_int_op(struct r600_bytecode *bc,
5700 struct r600_bytecode_alu *alu_src)
5701 {
5702 struct r600_bytecode_alu alu;
5703 int i, r;
5704 alu = *alu_src;
5705 if (bc->chip_class == CAYMAN) {
5706 for (i = 0; i < 4; i++) {
5707 alu.dst.chan = i;
5708 alu.dst.write = (i == alu_src->dst.chan);
5709 alu.last = (i == 3);
5710
5711 r = r600_bytecode_add_alu(bc, &alu);
5712 if (r)
5713 return r;
5714 }
5715 } else {
5716 alu.last = 1;
5717 r = r600_bytecode_add_alu(bc, &alu);
5718 if (r)
5719 return r;
5720 }
5721 return 0;
5722 }
5723
5724 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5725 {
5726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5727 struct r600_bytecode_alu alu;
5728 int i, r, j;
5729 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5730 int tmp0 = ctx->temp_reg;
5731 int tmp1 = r600_get_temp(ctx);
5732 int tmp2 = r600_get_temp(ctx);
5733 int tmp3 = r600_get_temp(ctx);
5734 /* Unsigned path:
5735 *
5736 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5737 *
5738 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5739 * 2. tmp0.z = lo (tmp0.x * src2)
5740 * 3. tmp0.w = -tmp0.z
5741 * 4. tmp0.y = hi (tmp0.x * src2)
5742 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5743 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5744 * 7. tmp1.x = tmp0.x - tmp0.w
5745 * 8. tmp1.y = tmp0.x + tmp0.w
5746 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5747 * 10. tmp0.z = hi(tmp0.x * src1) = q
5748 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5749 *
5750 * 12. tmp0.w = src1 - tmp0.y = r
5751 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5752 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5753 *
5754 * if DIV
5755 *
5756 * 15. tmp1.z = tmp0.z + 1 = q + 1
5757 * 16. tmp1.w = tmp0.z - 1 = q - 1
5758 *
5759 * else MOD
5760 *
5761 * 15. tmp1.z = tmp0.w - src2 = r - src2
5762 * 16. tmp1.w = tmp0.w + src2 = r + src2
5763 *
5764 * endif
5765 *
5766 * 17. tmp1.x = tmp1.x & tmp1.y
5767 *
5768 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5769 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5770 *
5771 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5772 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5773 *
5774 * Signed path:
5775 *
5776 * Same as unsigned, using abs values of the operands,
5777 * and fixing the sign of the result in the end.
5778 */
5779
5780 for (i = 0; i < 4; i++) {
5781 if (!(write_mask & (1<<i)))
5782 continue;
5783
5784 if (signed_op) {
5785
5786 /* tmp2.x = -src0 */
5787 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5788 alu.op = ALU_OP2_SUB_INT;
5789
5790 alu.dst.sel = tmp2;
5791 alu.dst.chan = 0;
5792 alu.dst.write = 1;
5793
5794 alu.src[0].sel = V_SQ_ALU_SRC_0;
5795
5796 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5797
5798 alu.last = 1;
5799 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5800 return r;
5801
5802 /* tmp2.y = -src1 */
5803 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5804 alu.op = ALU_OP2_SUB_INT;
5805
5806 alu.dst.sel = tmp2;
5807 alu.dst.chan = 1;
5808 alu.dst.write = 1;
5809
5810 alu.src[0].sel = V_SQ_ALU_SRC_0;
5811
5812 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5813
5814 alu.last = 1;
5815 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5816 return r;
5817
5818 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5819 /* it will be a sign of the quotient */
5820 if (!mod) {
5821
5822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5823 alu.op = ALU_OP2_XOR_INT;
5824
5825 alu.dst.sel = tmp2;
5826 alu.dst.chan = 2;
5827 alu.dst.write = 1;
5828
5829 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5830 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5831
5832 alu.last = 1;
5833 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5834 return r;
5835 }
5836
5837 /* tmp2.x = |src0| */
5838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5839 alu.op = ALU_OP3_CNDGE_INT;
5840 alu.is_op3 = 1;
5841
5842 alu.dst.sel = tmp2;
5843 alu.dst.chan = 0;
5844 alu.dst.write = 1;
5845
5846 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5847 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5848 alu.src[2].sel = tmp2;
5849 alu.src[2].chan = 0;
5850
5851 alu.last = 1;
5852 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5853 return r;
5854
5855 /* tmp2.y = |src1| */
5856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5857 alu.op = ALU_OP3_CNDGE_INT;
5858 alu.is_op3 = 1;
5859
5860 alu.dst.sel = tmp2;
5861 alu.dst.chan = 1;
5862 alu.dst.write = 1;
5863
5864 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5865 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5866 alu.src[2].sel = tmp2;
5867 alu.src[2].chan = 1;
5868
5869 alu.last = 1;
5870 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5871 return r;
5872
5873 }
5874
5875 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5876 if (ctx->bc->chip_class == CAYMAN) {
5877 /* tmp3.x = u2f(src2) */
5878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5879 alu.op = ALU_OP1_UINT_TO_FLT;
5880
5881 alu.dst.sel = tmp3;
5882 alu.dst.chan = 0;
5883 alu.dst.write = 1;
5884
5885 if (signed_op) {
5886 alu.src[0].sel = tmp2;
5887 alu.src[0].chan = 1;
5888 } else {
5889 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5890 }
5891
5892 alu.last = 1;
5893 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5894 return r;
5895
5896 /* tmp0.x = recip(tmp3.x) */
5897 for (j = 0 ; j < 3; j++) {
5898 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5899 alu.op = ALU_OP1_RECIP_IEEE;
5900
5901 alu.dst.sel = tmp0;
5902 alu.dst.chan = j;
5903 alu.dst.write = (j == 0);
5904
5905 alu.src[0].sel = tmp3;
5906 alu.src[0].chan = 0;
5907
5908 if (j == 2)
5909 alu.last = 1;
5910 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5911 return r;
5912 }
5913
5914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5915 alu.op = ALU_OP2_MUL;
5916
5917 alu.src[0].sel = tmp0;
5918 alu.src[0].chan = 0;
5919
5920 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5921 alu.src[1].value = 0x4f800000;
5922
5923 alu.dst.sel = tmp3;
5924 alu.dst.write = 1;
5925 alu.last = 1;
5926 r = r600_bytecode_add_alu(ctx->bc, &alu);
5927 if (r)
5928 return r;
5929
5930 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5931 alu.op = ALU_OP1_FLT_TO_UINT;
5932
5933 alu.dst.sel = tmp0;
5934 alu.dst.chan = 0;
5935 alu.dst.write = 1;
5936
5937 alu.src[0].sel = tmp3;
5938 alu.src[0].chan = 0;
5939
5940 alu.last = 1;
5941 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5942 return r;
5943
5944 } else {
5945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5946 alu.op = ALU_OP1_RECIP_UINT;
5947
5948 alu.dst.sel = tmp0;
5949 alu.dst.chan = 0;
5950 alu.dst.write = 1;
5951
5952 if (signed_op) {
5953 alu.src[0].sel = tmp2;
5954 alu.src[0].chan = 1;
5955 } else {
5956 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5957 }
5958
5959 alu.last = 1;
5960 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5961 return r;
5962 }
5963
5964 /* 2. tmp0.z = lo (tmp0.x * src2) */
5965 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5966 alu.op = ALU_OP2_MULLO_UINT;
5967
5968 alu.dst.sel = tmp0;
5969 alu.dst.chan = 2;
5970 alu.dst.write = 1;
5971
5972 alu.src[0].sel = tmp0;
5973 alu.src[0].chan = 0;
5974 if (signed_op) {
5975 alu.src[1].sel = tmp2;
5976 alu.src[1].chan = 1;
5977 } else {
5978 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5979 }
5980
5981 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5982 return r;
5983
5984 /* 3. tmp0.w = -tmp0.z */
5985 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5986 alu.op = ALU_OP2_SUB_INT;
5987
5988 alu.dst.sel = tmp0;
5989 alu.dst.chan = 3;
5990 alu.dst.write = 1;
5991
5992 alu.src[0].sel = V_SQ_ALU_SRC_0;
5993 alu.src[1].sel = tmp0;
5994 alu.src[1].chan = 2;
5995
5996 alu.last = 1;
5997 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5998 return r;
5999
6000 /* 4. tmp0.y = hi (tmp0.x * src2) */
6001 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6002 alu.op = ALU_OP2_MULHI_UINT;
6003
6004 alu.dst.sel = tmp0;
6005 alu.dst.chan = 1;
6006 alu.dst.write = 1;
6007
6008 alu.src[0].sel = tmp0;
6009 alu.src[0].chan = 0;
6010
6011 if (signed_op) {
6012 alu.src[1].sel = tmp2;
6013 alu.src[1].chan = 1;
6014 } else {
6015 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6016 }
6017
6018 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6019 return r;
6020
6021 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
6022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6023 alu.op = ALU_OP3_CNDE_INT;
6024 alu.is_op3 = 1;
6025
6026 alu.dst.sel = tmp0;
6027 alu.dst.chan = 2;
6028 alu.dst.write = 1;
6029
6030 alu.src[0].sel = tmp0;
6031 alu.src[0].chan = 1;
6032 alu.src[1].sel = tmp0;
6033 alu.src[1].chan = 3;
6034 alu.src[2].sel = tmp0;
6035 alu.src[2].chan = 2;
6036
6037 alu.last = 1;
6038 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6039 return r;
6040
6041 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
6042 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6043 alu.op = ALU_OP2_MULHI_UINT;
6044
6045 alu.dst.sel = tmp0;
6046 alu.dst.chan = 3;
6047 alu.dst.write = 1;
6048
6049 alu.src[0].sel = tmp0;
6050 alu.src[0].chan = 2;
6051
6052 alu.src[1].sel = tmp0;
6053 alu.src[1].chan = 0;
6054
6055 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6056 return r;
6057
6058 /* 7. tmp1.x = tmp0.x - tmp0.w */
6059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6060 alu.op = ALU_OP2_SUB_INT;
6061
6062 alu.dst.sel = tmp1;
6063 alu.dst.chan = 0;
6064 alu.dst.write = 1;
6065
6066 alu.src[0].sel = tmp0;
6067 alu.src[0].chan = 0;
6068 alu.src[1].sel = tmp0;
6069 alu.src[1].chan = 3;
6070
6071 alu.last = 1;
6072 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6073 return r;
6074
6075 /* 8. tmp1.y = tmp0.x + tmp0.w */
6076 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6077 alu.op = ALU_OP2_ADD_INT;
6078
6079 alu.dst.sel = tmp1;
6080 alu.dst.chan = 1;
6081 alu.dst.write = 1;
6082
6083 alu.src[0].sel = tmp0;
6084 alu.src[0].chan = 0;
6085 alu.src[1].sel = tmp0;
6086 alu.src[1].chan = 3;
6087
6088 alu.last = 1;
6089 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6090 return r;
6091
6092 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
6093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6094 alu.op = ALU_OP3_CNDE_INT;
6095 alu.is_op3 = 1;
6096
6097 alu.dst.sel = tmp0;
6098 alu.dst.chan = 0;
6099 alu.dst.write = 1;
6100
6101 alu.src[0].sel = tmp0;
6102 alu.src[0].chan = 1;
6103 alu.src[1].sel = tmp1;
6104 alu.src[1].chan = 1;
6105 alu.src[2].sel = tmp1;
6106 alu.src[2].chan = 0;
6107
6108 alu.last = 1;
6109 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6110 return r;
6111
6112 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
6113 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6114 alu.op = ALU_OP2_MULHI_UINT;
6115
6116 alu.dst.sel = tmp0;
6117 alu.dst.chan = 2;
6118 alu.dst.write = 1;
6119
6120 alu.src[0].sel = tmp0;
6121 alu.src[0].chan = 0;
6122
6123 if (signed_op) {
6124 alu.src[1].sel = tmp2;
6125 alu.src[1].chan = 0;
6126 } else {
6127 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6128 }
6129
6130 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6131 return r;
6132
6133 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
6134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6135 alu.op = ALU_OP2_MULLO_UINT;
6136
6137 alu.dst.sel = tmp0;
6138 alu.dst.chan = 1;
6139 alu.dst.write = 1;
6140
6141 if (signed_op) {
6142 alu.src[0].sel = tmp2;
6143 alu.src[0].chan = 1;
6144 } else {
6145 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6146 }
6147
6148 alu.src[1].sel = tmp0;
6149 alu.src[1].chan = 2;
6150
6151 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6152 return r;
6153
6154 /* 12. tmp0.w = src1 - tmp0.y = r */
6155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6156 alu.op = ALU_OP2_SUB_INT;
6157
6158 alu.dst.sel = tmp0;
6159 alu.dst.chan = 3;
6160 alu.dst.write = 1;
6161
6162 if (signed_op) {
6163 alu.src[0].sel = tmp2;
6164 alu.src[0].chan = 0;
6165 } else {
6166 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6167 }
6168
6169 alu.src[1].sel = tmp0;
6170 alu.src[1].chan = 1;
6171
6172 alu.last = 1;
6173 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6174 return r;
6175
6176 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
6177 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6178 alu.op = ALU_OP2_SETGE_UINT;
6179
6180 alu.dst.sel = tmp1;
6181 alu.dst.chan = 0;
6182 alu.dst.write = 1;
6183
6184 alu.src[0].sel = tmp0;
6185 alu.src[0].chan = 3;
6186 if (signed_op) {
6187 alu.src[1].sel = tmp2;
6188 alu.src[1].chan = 1;
6189 } else {
6190 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6191 }
6192
6193 alu.last = 1;
6194 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6195 return r;
6196
6197 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
6198 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6199 alu.op = ALU_OP2_SETGE_UINT;
6200
6201 alu.dst.sel = tmp1;
6202 alu.dst.chan = 1;
6203 alu.dst.write = 1;
6204
6205 if (signed_op) {
6206 alu.src[0].sel = tmp2;
6207 alu.src[0].chan = 0;
6208 } else {
6209 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6210 }
6211
6212 alu.src[1].sel = tmp0;
6213 alu.src[1].chan = 1;
6214
6215 alu.last = 1;
6216 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6217 return r;
6218
6219 if (mod) { /* UMOD */
6220
6221 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
6222 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6223 alu.op = ALU_OP2_SUB_INT;
6224
6225 alu.dst.sel = tmp1;
6226 alu.dst.chan = 2;
6227 alu.dst.write = 1;
6228
6229 alu.src[0].sel = tmp0;
6230 alu.src[0].chan = 3;
6231
6232 if (signed_op) {
6233 alu.src[1].sel = tmp2;
6234 alu.src[1].chan = 1;
6235 } else {
6236 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6237 }
6238
6239 alu.last = 1;
6240 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6241 return r;
6242
6243 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
6244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6245 alu.op = ALU_OP2_ADD_INT;
6246
6247 alu.dst.sel = tmp1;
6248 alu.dst.chan = 3;
6249 alu.dst.write = 1;
6250
6251 alu.src[0].sel = tmp0;
6252 alu.src[0].chan = 3;
6253 if (signed_op) {
6254 alu.src[1].sel = tmp2;
6255 alu.src[1].chan = 1;
6256 } else {
6257 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6258 }
6259
6260 alu.last = 1;
6261 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6262 return r;
6263
6264 } else { /* UDIV */
6265
6266 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
6267 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6268 alu.op = ALU_OP2_ADD_INT;
6269
6270 alu.dst.sel = tmp1;
6271 alu.dst.chan = 2;
6272 alu.dst.write = 1;
6273
6274 alu.src[0].sel = tmp0;
6275 alu.src[0].chan = 2;
6276 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6277
6278 alu.last = 1;
6279 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6280 return r;
6281
6282 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
6283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6284 alu.op = ALU_OP2_ADD_INT;
6285
6286 alu.dst.sel = tmp1;
6287 alu.dst.chan = 3;
6288 alu.dst.write = 1;
6289
6290 alu.src[0].sel = tmp0;
6291 alu.src[0].chan = 2;
6292 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
6293
6294 alu.last = 1;
6295 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6296 return r;
6297
6298 }
6299
6300 /* 17. tmp1.x = tmp1.x & tmp1.y */
6301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6302 alu.op = ALU_OP2_AND_INT;
6303
6304 alu.dst.sel = tmp1;
6305 alu.dst.chan = 0;
6306 alu.dst.write = 1;
6307
6308 alu.src[0].sel = tmp1;
6309 alu.src[0].chan = 0;
6310 alu.src[1].sel = tmp1;
6311 alu.src[1].chan = 1;
6312
6313 alu.last = 1;
6314 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6315 return r;
6316
6317 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
6318 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
6319 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6320 alu.op = ALU_OP3_CNDE_INT;
6321 alu.is_op3 = 1;
6322
6323 alu.dst.sel = tmp0;
6324 alu.dst.chan = 2;
6325 alu.dst.write = 1;
6326
6327 alu.src[0].sel = tmp1;
6328 alu.src[0].chan = 0;
6329 alu.src[1].sel = tmp0;
6330 alu.src[1].chan = mod ? 3 : 2;
6331 alu.src[2].sel = tmp1;
6332 alu.src[2].chan = 2;
6333
6334 alu.last = 1;
6335 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6336 return r;
6337
6338 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
6339 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6340 alu.op = ALU_OP3_CNDE_INT;
6341 alu.is_op3 = 1;
6342
6343 if (signed_op) {
6344 alu.dst.sel = tmp0;
6345 alu.dst.chan = 2;
6346 alu.dst.write = 1;
6347 } else {
6348 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6349 }
6350
6351 alu.src[0].sel = tmp1;
6352 alu.src[0].chan = 1;
6353 alu.src[1].sel = tmp1;
6354 alu.src[1].chan = 3;
6355 alu.src[2].sel = tmp0;
6356 alu.src[2].chan = 2;
6357
6358 alu.last = 1;
6359 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6360 return r;
6361
6362 if (signed_op) {
6363
6364 /* fix the sign of the result */
6365
6366 if (mod) {
6367
6368 /* tmp0.x = -tmp0.z */
6369 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6370 alu.op = ALU_OP2_SUB_INT;
6371
6372 alu.dst.sel = tmp0;
6373 alu.dst.chan = 0;
6374 alu.dst.write = 1;
6375
6376 alu.src[0].sel = V_SQ_ALU_SRC_0;
6377 alu.src[1].sel = tmp0;
6378 alu.src[1].chan = 2;
6379
6380 alu.last = 1;
6381 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6382 return r;
6383
6384 /* sign of the remainder is the same as the sign of src0 */
6385 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
6386 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6387 alu.op = ALU_OP3_CNDGE_INT;
6388 alu.is_op3 = 1;
6389
6390 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6391
6392 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6393 alu.src[1].sel = tmp0;
6394 alu.src[1].chan = 2;
6395 alu.src[2].sel = tmp0;
6396 alu.src[2].chan = 0;
6397
6398 alu.last = 1;
6399 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6400 return r;
6401
6402 } else {
6403
6404 /* tmp0.x = -tmp0.z */
6405 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6406 alu.op = ALU_OP2_SUB_INT;
6407
6408 alu.dst.sel = tmp0;
6409 alu.dst.chan = 0;
6410 alu.dst.write = 1;
6411
6412 alu.src[0].sel = V_SQ_ALU_SRC_0;
6413 alu.src[1].sel = tmp0;
6414 alu.src[1].chan = 2;
6415
6416 alu.last = 1;
6417 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6418 return r;
6419
6420 /* fix the quotient sign (same as the sign of src0*src1) */
6421 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
6422 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6423 alu.op = ALU_OP3_CNDGE_INT;
6424 alu.is_op3 = 1;
6425
6426 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6427
6428 alu.src[0].sel = tmp2;
6429 alu.src[0].chan = 2;
6430 alu.src[1].sel = tmp0;
6431 alu.src[1].chan = 2;
6432 alu.src[2].sel = tmp0;
6433 alu.src[2].chan = 0;
6434
6435 alu.last = 1;
6436 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6437 return r;
6438 }
6439 }
6440 }
6441 return 0;
6442 }
6443
6444 static int tgsi_udiv(struct r600_shader_ctx *ctx)
6445 {
6446 return tgsi_divmod(ctx, 0, 0);
6447 }
6448
6449 static int tgsi_umod(struct r600_shader_ctx *ctx)
6450 {
6451 return tgsi_divmod(ctx, 1, 0);
6452 }
6453
6454 static int tgsi_idiv(struct r600_shader_ctx *ctx)
6455 {
6456 return tgsi_divmod(ctx, 0, 1);
6457 }
6458
6459 static int tgsi_imod(struct r600_shader_ctx *ctx)
6460 {
6461 return tgsi_divmod(ctx, 1, 1);
6462 }
6463
6464
6465 static int tgsi_f2i(struct r600_shader_ctx *ctx)
6466 {
6467 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6468 struct r600_bytecode_alu alu;
6469 int i, r;
6470 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6471 int last_inst = tgsi_last_instruction(write_mask);
6472
6473 for (i = 0; i < 4; i++) {
6474 if (!(write_mask & (1<<i)))
6475 continue;
6476
6477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6478 alu.op = ALU_OP1_TRUNC;
6479
6480 alu.dst.sel = ctx->temp_reg;
6481 alu.dst.chan = i;
6482 alu.dst.write = 1;
6483
6484 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6485 if (i == last_inst)
6486 alu.last = 1;
6487 r = r600_bytecode_add_alu(ctx->bc, &alu);
6488 if (r)
6489 return r;
6490 }
6491
6492 for (i = 0; i < 4; i++) {
6493 if (!(write_mask & (1<<i)))
6494 continue;
6495
6496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6497 alu.op = ctx->inst_info->op;
6498
6499 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6500
6501 alu.src[0].sel = ctx->temp_reg;
6502 alu.src[0].chan = i;
6503
6504 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6505 alu.last = 1;
6506 r = r600_bytecode_add_alu(ctx->bc, &alu);
6507 if (r)
6508 return r;
6509 }
6510
6511 return 0;
6512 }
6513
6514 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6515 {
6516 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6517 struct r600_bytecode_alu alu;
6518 int i, r;
6519 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6520 int last_inst = tgsi_last_instruction(write_mask);
6521
6522 /* tmp = -src */
6523 for (i = 0; i < 4; i++) {
6524 if (!(write_mask & (1<<i)))
6525 continue;
6526
6527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6528 alu.op = ALU_OP2_SUB_INT;
6529
6530 alu.dst.sel = ctx->temp_reg;
6531 alu.dst.chan = i;
6532 alu.dst.write = 1;
6533
6534 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6535 alu.src[0].sel = V_SQ_ALU_SRC_0;
6536
6537 if (i == last_inst)
6538 alu.last = 1;
6539 r = r600_bytecode_add_alu(ctx->bc, &alu);
6540 if (r)
6541 return r;
6542 }
6543
6544 /* dst = (src >= 0 ? src : tmp) */
6545 for (i = 0; i < 4; i++) {
6546 if (!(write_mask & (1<<i)))
6547 continue;
6548
6549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6550 alu.op = ALU_OP3_CNDGE_INT;
6551 alu.is_op3 = 1;
6552 alu.dst.write = 1;
6553
6554 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6555
6556 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6557 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6558 alu.src[2].sel = ctx->temp_reg;
6559 alu.src[2].chan = i;
6560
6561 if (i == last_inst)
6562 alu.last = 1;
6563 r = r600_bytecode_add_alu(ctx->bc, &alu);
6564 if (r)
6565 return r;
6566 }
6567 return 0;
6568 }
6569
6570 static int tgsi_issg(struct r600_shader_ctx *ctx)
6571 {
6572 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6573 struct r600_bytecode_alu alu;
6574 int i, r;
6575 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6576 int last_inst = tgsi_last_instruction(write_mask);
6577
6578 /* tmp = (src >= 0 ? src : -1) */
6579 for (i = 0; i < 4; i++) {
6580 if (!(write_mask & (1<<i)))
6581 continue;
6582
6583 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6584 alu.op = ALU_OP3_CNDGE_INT;
6585 alu.is_op3 = 1;
6586
6587 alu.dst.sel = ctx->temp_reg;
6588 alu.dst.chan = i;
6589 alu.dst.write = 1;
6590
6591 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6592 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6593 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6594
6595 if (i == last_inst)
6596 alu.last = 1;
6597 r = r600_bytecode_add_alu(ctx->bc, &alu);
6598 if (r)
6599 return r;
6600 }
6601
6602 /* dst = (tmp > 0 ? 1 : tmp) */
6603 for (i = 0; i < 4; i++) {
6604 if (!(write_mask & (1<<i)))
6605 continue;
6606
6607 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6608 alu.op = ALU_OP3_CNDGT_INT;
6609 alu.is_op3 = 1;
6610 alu.dst.write = 1;
6611
6612 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6613
6614 alu.src[0].sel = ctx->temp_reg;
6615 alu.src[0].chan = i;
6616
6617 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6618
6619 alu.src[2].sel = ctx->temp_reg;
6620 alu.src[2].chan = i;
6621
6622 if (i == last_inst)
6623 alu.last = 1;
6624 r = r600_bytecode_add_alu(ctx->bc, &alu);
6625 if (r)
6626 return r;
6627 }
6628 return 0;
6629 }
6630
6631
6632
6633 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6634 {
6635 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6636 struct r600_bytecode_alu alu;
6637 int i, r;
6638
6639 /* tmp = (src > 0 ? 1 : src) */
6640 for (i = 0; i < 4; i++) {
6641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6642 alu.op = ALU_OP3_CNDGT;
6643 alu.is_op3 = 1;
6644
6645 alu.dst.sel = ctx->temp_reg;
6646 alu.dst.chan = i;
6647
6648 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6649 alu.src[1].sel = V_SQ_ALU_SRC_1;
6650 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6651
6652 if (i == 3)
6653 alu.last = 1;
6654 r = r600_bytecode_add_alu(ctx->bc, &alu);
6655 if (r)
6656 return r;
6657 }
6658
6659 /* dst = (-tmp > 0 ? -1 : tmp) */
6660 for (i = 0; i < 4; i++) {
6661 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6662 alu.op = ALU_OP3_CNDGT;
6663 alu.is_op3 = 1;
6664 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6665
6666 alu.src[0].sel = ctx->temp_reg;
6667 alu.src[0].chan = i;
6668 alu.src[0].neg = 1;
6669
6670 alu.src[1].sel = V_SQ_ALU_SRC_1;
6671 alu.src[1].neg = 1;
6672
6673 alu.src[2].sel = ctx->temp_reg;
6674 alu.src[2].chan = i;
6675
6676 if (i == 3)
6677 alu.last = 1;
6678 r = r600_bytecode_add_alu(ctx->bc, &alu);
6679 if (r)
6680 return r;
6681 }
6682 return 0;
6683 }
6684
6685 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6686 {
6687 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6688 struct r600_bytecode_alu alu;
6689 int i, r, t1, t2;
6690
6691 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6692 int last_inst = tgsi_last_instruction(write_mask);
6693
6694 t1 = r600_get_temp(ctx);
6695
6696 for (i = 0; i < 4; i++) {
6697 if (!(write_mask & (1<<i)))
6698 continue;
6699
6700 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6701 alu.op = ALU_OP2_SETGE_INT;
6702 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6703 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6704 alu.src[1].value = 32;
6705 alu.dst.sel = ctx->temp_reg;
6706 alu.dst.chan = i;
6707 alu.dst.write = 1;
6708 alu.last = i == last_inst;
6709 r = r600_bytecode_add_alu(ctx->bc, &alu);
6710 if (r)
6711 return r;
6712 }
6713
6714 for (i = 0; i < 4; i++) {
6715 if (!(write_mask & (1<<i)))
6716 continue;
6717
6718 /* create mask tmp */
6719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6720 alu.op = ALU_OP2_BFM_INT;
6721 alu.dst.sel = t1;
6722 alu.dst.chan = i;
6723 alu.dst.write = 1;
6724 alu.last = i == last_inst;
6725
6726 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6727 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6728
6729 r = r600_bytecode_add_alu(ctx->bc, &alu);
6730 if (r)
6731 return r;
6732 }
6733
6734 t2 = r600_get_temp(ctx);
6735
6736 for (i = 0; i < 4; i++) {
6737 if (!(write_mask & (1<<i)))
6738 continue;
6739
6740 /* shift insert left */
6741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6742 alu.op = ALU_OP2_LSHL_INT;
6743 alu.dst.sel = t2;
6744 alu.dst.chan = i;
6745 alu.dst.write = 1;
6746 alu.last = i == last_inst;
6747
6748 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6749 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6750
6751 r = r600_bytecode_add_alu(ctx->bc, &alu);
6752 if (r)
6753 return r;
6754 }
6755
6756 for (i = 0; i < 4; i++) {
6757 if (!(write_mask & (1<<i)))
6758 continue;
6759
6760 /* actual bitfield insert */
6761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6762 alu.op = ALU_OP3_BFI_INT;
6763 alu.is_op3 = 1;
6764 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6765 alu.dst.chan = i;
6766 alu.dst.write = 1;
6767 alu.last = i == last_inst;
6768
6769 alu.src[0].sel = t1;
6770 alu.src[0].chan = i;
6771 alu.src[1].sel = t2;
6772 alu.src[1].chan = i;
6773 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6774
6775 r = r600_bytecode_add_alu(ctx->bc, &alu);
6776 if (r)
6777 return r;
6778 }
6779
6780 for (i = 0; i < 4; i++) {
6781 if (!(write_mask & (1<<i)))
6782 continue;
6783 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6784 alu.op = ALU_OP3_CNDE_INT;
6785 alu.is_op3 = 1;
6786 alu.src[0].sel = ctx->temp_reg;
6787 alu.src[0].chan = i;
6788 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6789
6790 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6791
6792 alu.src[1].sel = alu.dst.sel;
6793 alu.src[1].chan = i;
6794
6795 alu.last = i == last_inst;
6796 r = r600_bytecode_add_alu(ctx->bc, &alu);
6797 if (r)
6798 return r;
6799 }
6800 return 0;
6801 }
6802
6803 static int tgsi_msb(struct r600_shader_ctx *ctx)
6804 {
6805 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6806 struct r600_bytecode_alu alu;
6807 int i, r, t1, t2;
6808
6809 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6810 int last_inst = tgsi_last_instruction(write_mask);
6811
6812 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6813 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6814
6815 t1 = ctx->temp_reg;
6816
6817 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6818 for (i = 0; i < 4; i++) {
6819 if (!(write_mask & (1<<i)))
6820 continue;
6821
6822 /* t1 = FFBH_INT / FFBH_UINT */
6823 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6824 alu.op = ctx->inst_info->op;
6825 alu.dst.sel = t1;
6826 alu.dst.chan = i;
6827 alu.dst.write = 1;
6828 alu.last = i == last_inst;
6829
6830 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6831
6832 r = r600_bytecode_add_alu(ctx->bc, &alu);
6833 if (r)
6834 return r;
6835 }
6836
6837 t2 = r600_get_temp(ctx);
6838
6839 for (i = 0; i < 4; i++) {
6840 if (!(write_mask & (1<<i)))
6841 continue;
6842
6843 /* t2 = 31 - t1 */
6844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6845 alu.op = ALU_OP2_SUB_INT;
6846 alu.dst.sel = t2;
6847 alu.dst.chan = i;
6848 alu.dst.write = 1;
6849 alu.last = i == last_inst;
6850
6851 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6852 alu.src[0].value = 31;
6853 alu.src[1].sel = t1;
6854 alu.src[1].chan = i;
6855
6856 r = r600_bytecode_add_alu(ctx->bc, &alu);
6857 if (r)
6858 return r;
6859 }
6860
6861 for (i = 0; i < 4; i++) {
6862 if (!(write_mask & (1<<i)))
6863 continue;
6864
6865 /* result = t1 >= 0 ? t2 : t1 */
6866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6867 alu.op = ALU_OP3_CNDGE_INT;
6868 alu.is_op3 = 1;
6869 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6870 alu.dst.chan = i;
6871 alu.dst.write = 1;
6872 alu.last = i == last_inst;
6873
6874 alu.src[0].sel = t1;
6875 alu.src[0].chan = i;
6876 alu.src[1].sel = t2;
6877 alu.src[1].chan = i;
6878 alu.src[2].sel = t1;
6879 alu.src[2].chan = i;
6880
6881 r = r600_bytecode_add_alu(ctx->bc, &alu);
6882 if (r)
6883 return r;
6884 }
6885
6886 return 0;
6887 }
6888
6889 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6890 {
6891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6892 struct r600_bytecode_alu alu;
6893 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6894 unsigned location;
6895 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6896
6897 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6898
6899 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6900 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6901 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6902 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6903 }
6904 else {
6905 location = TGSI_INTERPOLATE_LOC_CENTROID;
6906 }
6907
6908 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6909 if (k < 0)
6910 k = 0;
6911 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6912 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6913
6914 /* NOTE: currently offset is not perspective correct */
6915 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6916 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6917 int sample_gpr = -1;
6918 int gradientsH, gradientsV;
6919 struct r600_bytecode_tex tex;
6920
6921 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6922 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6923 }
6924
6925 gradientsH = r600_get_temp(ctx);
6926 gradientsV = r600_get_temp(ctx);
6927 for (i = 0; i < 2; i++) {
6928 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6929 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6930 tex.src_gpr = interp_gpr;
6931 tex.src_sel_x = interp_base_chan + 0;
6932 tex.src_sel_y = interp_base_chan + 1;
6933 tex.src_sel_z = 0;
6934 tex.src_sel_w = 0;
6935 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6936 tex.dst_sel_x = 0;
6937 tex.dst_sel_y = 1;
6938 tex.dst_sel_z = 7;
6939 tex.dst_sel_w = 7;
6940 tex.inst_mod = 1; // Use per pixel gradient calculation
6941 tex.sampler_id = 0;
6942 tex.resource_id = tex.sampler_id;
6943 r = r600_bytecode_add_tex(ctx->bc, &tex);
6944 if (r)
6945 return r;
6946 }
6947
6948 for (i = 0; i < 2; i++) {
6949 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6950 alu.op = ALU_OP3_MULADD;
6951 alu.is_op3 = 1;
6952 alu.src[0].sel = gradientsH;
6953 alu.src[0].chan = i;
6954 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6955 alu.src[1].sel = sample_gpr;
6956 alu.src[1].chan = 2;
6957 }
6958 else {
6959 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6960 }
6961 alu.src[2].sel = interp_gpr;
6962 alu.src[2].chan = interp_base_chan + i;
6963 alu.dst.sel = ctx->temp_reg;
6964 alu.dst.chan = i;
6965 alu.last = i == 1;
6966
6967 r = r600_bytecode_add_alu(ctx->bc, &alu);
6968 if (r)
6969 return r;
6970 }
6971
6972 for (i = 0; i < 2; i++) {
6973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6974 alu.op = ALU_OP3_MULADD;
6975 alu.is_op3 = 1;
6976 alu.src[0].sel = gradientsV;
6977 alu.src[0].chan = i;
6978 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6979 alu.src[1].sel = sample_gpr;
6980 alu.src[1].chan = 3;
6981 }
6982 else {
6983 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6984 }
6985 alu.src[2].sel = ctx->temp_reg;
6986 alu.src[2].chan = i;
6987 alu.dst.sel = ctx->temp_reg;
6988 alu.dst.chan = i;
6989 alu.last = i == 1;
6990
6991 r = r600_bytecode_add_alu(ctx->bc, &alu);
6992 if (r)
6993 return r;
6994 }
6995 }
6996
6997 tmp = r600_get_temp(ctx);
6998 for (i = 0; i < 8; i++) {
6999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7000 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
7001
7002 alu.dst.sel = tmp;
7003 if ((i > 1 && i < 6)) {
7004 alu.dst.write = 1;
7005 }
7006 else {
7007 alu.dst.write = 0;
7008 }
7009 alu.dst.chan = i % 4;
7010
7011 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
7012 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7013 alu.src[0].sel = ctx->temp_reg;
7014 alu.src[0].chan = 1 - (i % 2);
7015 } else {
7016 alu.src[0].sel = interp_gpr;
7017 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
7018 }
7019 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
7020 alu.src[1].chan = 0;
7021
7022 alu.last = i % 4 == 3;
7023 alu.bank_swizzle_force = SQ_ALU_VEC_210;
7024
7025 r = r600_bytecode_add_alu(ctx->bc, &alu);
7026 if (r)
7027 return r;
7028 }
7029
7030 // INTERP can't swizzle dst
7031 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7032 for (i = 0; i <= lasti; i++) {
7033 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7034 continue;
7035
7036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7037 alu.op = ALU_OP1_MOV;
7038 alu.src[0].sel = tmp;
7039 alu.src[0].chan = ctx->src[0].swizzle[i];
7040 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7041 alu.dst.write = 1;
7042 alu.last = i == lasti;
7043 r = r600_bytecode_add_alu(ctx->bc, &alu);
7044 if (r)
7045 return r;
7046 }
7047
7048 return 0;
7049 }
7050
7051
7052 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
7053 {
7054 struct r600_bytecode_alu alu;
7055 int i, r;
7056
7057 for (i = 0; i < 4; i++) {
7058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7059 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
7060 alu.op = ALU_OP0_NOP;
7061 alu.dst.chan = i;
7062 } else {
7063 alu.op = ALU_OP1_MOV;
7064 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7065 alu.src[0].sel = ctx->temp_reg;
7066 alu.src[0].chan = i;
7067 }
7068 if (i == 3) {
7069 alu.last = 1;
7070 }
7071 r = r600_bytecode_add_alu(ctx->bc, &alu);
7072 if (r)
7073 return r;
7074 }
7075 return 0;
7076 }
7077
7078 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
7079 unsigned writemask,
7080 struct r600_bytecode_alu_src *bc_src,
7081 const struct r600_shader_src *shader_src)
7082 {
7083 struct r600_bytecode_alu alu;
7084 int i, r;
7085 int lasti = tgsi_last_instruction(writemask);
7086 int temp_reg = 0;
7087
7088 r600_bytecode_src(&bc_src[0], shader_src, 0);
7089 r600_bytecode_src(&bc_src[1], shader_src, 1);
7090 r600_bytecode_src(&bc_src[2], shader_src, 2);
7091 r600_bytecode_src(&bc_src[3], shader_src, 3);
7092
7093 if (bc_src->abs) {
7094 temp_reg = r600_get_temp(ctx);
7095
7096 for (i = 0; i < lasti + 1; i++) {
7097 if (!(writemask & (1 << i)))
7098 continue;
7099 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7100 alu.op = ALU_OP1_MOV;
7101 alu.dst.sel = temp_reg;
7102 alu.dst.chan = i;
7103 alu.dst.write = 1;
7104 alu.src[0] = bc_src[i];
7105 if (i == lasti) {
7106 alu.last = 1;
7107 }
7108 r = r600_bytecode_add_alu(ctx->bc, &alu);
7109 if (r)
7110 return r;
7111 memset(&bc_src[i], 0, sizeof(*bc_src));
7112 bc_src[i].sel = temp_reg;
7113 bc_src[i].chan = i;
7114 }
7115 }
7116 return 0;
7117 }
7118
7119 static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
7120 {
7121 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7122 struct r600_bytecode_alu alu;
7123 struct r600_bytecode_alu_src srcs[4][4];
7124 int i, j, r;
7125 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7126 unsigned op = ctx->inst_info->op;
7127
7128 if (op == ALU_OP3_MULADD_IEEE &&
7129 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
7130 op = ALU_OP3_MULADD;
7131
7132 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7133 r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
7134 srcs[j], &ctx->src[j]);
7135 if (r)
7136 return r;
7137 }
7138
7139 for (i = 0; i < lasti + 1; i++) {
7140 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7141 continue;
7142
7143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7144 alu.op = op;
7145 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7146 alu.src[j] = srcs[j][i];
7147 }
7148
7149 if (dst == -1) {
7150 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7151 } else {
7152 alu.dst.sel = dst;
7153 }
7154 alu.dst.chan = i;
7155 alu.dst.write = 1;
7156 alu.is_op3 = 1;
7157 if (i == lasti) {
7158 alu.last = 1;
7159 }
7160 r = r600_bytecode_add_alu(ctx->bc, &alu);
7161 if (r)
7162 return r;
7163 }
7164 return 0;
7165 }
7166
7167 static int tgsi_op3(struct r600_shader_ctx *ctx)
7168 {
7169 return tgsi_op3_dst(ctx, -1);
7170 }
7171
7172 static int tgsi_dp(struct r600_shader_ctx *ctx)
7173 {
7174 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7175 struct r600_bytecode_alu alu;
7176 int i, j, r;
7177 unsigned op = ctx->inst_info->op;
7178 if (op == ALU_OP2_DOT4_IEEE &&
7179 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
7180 op = ALU_OP2_DOT4;
7181
7182 for (i = 0; i < 4; i++) {
7183 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7184 alu.op = op;
7185 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7186 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
7187 }
7188
7189 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7190 alu.dst.chan = i;
7191 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
7192 /* handle some special cases */
7193 switch (inst->Instruction.Opcode) {
7194 case TGSI_OPCODE_DP2:
7195 if (i > 1) {
7196 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
7197 alu.src[0].chan = alu.src[1].chan = 0;
7198 }
7199 break;
7200 case TGSI_OPCODE_DP3:
7201 if (i > 2) {
7202 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
7203 alu.src[0].chan = alu.src[1].chan = 0;
7204 }
7205 break;
7206 default:
7207 break;
7208 }
7209 if (i == 3) {
7210 alu.last = 1;
7211 }
7212 r = r600_bytecode_add_alu(ctx->bc, &alu);
7213 if (r)
7214 return r;
7215 }
7216 return 0;
7217 }
7218
7219 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
7220 unsigned index)
7221 {
7222 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7223 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
7224 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
7225 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
7226 ctx->src[index].neg || ctx->src[index].abs ||
7227 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
7228 }
7229
7230 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
7231 unsigned index)
7232 {
7233 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7234 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
7235 }
7236
7237 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
7238 {
7239 struct r600_bytecode_vtx vtx;
7240 struct r600_bytecode_alu alu;
7241 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7242 int src_gpr, r, i;
7243 int id = tgsi_tex_get_src_gpr(ctx, 1);
7244 int sampler_index_mode = inst->Src[1].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7245
7246 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7247 if (src_requires_loading) {
7248 for (i = 0; i < 4; i++) {
7249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7250 alu.op = ALU_OP1_MOV;
7251 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7252 alu.dst.sel = ctx->temp_reg;
7253 alu.dst.chan = i;
7254 if (i == 3)
7255 alu.last = 1;
7256 alu.dst.write = 1;
7257 r = r600_bytecode_add_alu(ctx->bc, &alu);
7258 if (r)
7259 return r;
7260 }
7261 src_gpr = ctx->temp_reg;
7262 }
7263
7264 memset(&vtx, 0, sizeof(vtx));
7265 vtx.op = FETCH_OP_VFETCH;
7266 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
7267 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7268 vtx.src_gpr = src_gpr;
7269 vtx.mega_fetch_count = 16;
7270 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7271 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7272 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
7273 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
7274 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
7275 vtx.use_const_fields = 1;
7276 vtx.buffer_index_mode = sampler_index_mode;
7277
7278 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
7279 return r;
7280
7281 if (ctx->bc->chip_class >= EVERGREEN)
7282 return 0;
7283
7284 for (i = 0; i < 4; i++) {
7285 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7286 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7287 continue;
7288
7289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7290 alu.op = ALU_OP2_AND_INT;
7291
7292 alu.dst.chan = i;
7293 alu.dst.sel = vtx.dst_gpr;
7294 alu.dst.write = 1;
7295
7296 alu.src[0].sel = vtx.dst_gpr;
7297 alu.src[0].chan = i;
7298
7299 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
7300 alu.src[1].sel += (id * 2);
7301 alu.src[1].chan = i % 4;
7302 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7303
7304 if (i == lasti)
7305 alu.last = 1;
7306 r = r600_bytecode_add_alu(ctx->bc, &alu);
7307 if (r)
7308 return r;
7309 }
7310
7311 if (inst->Dst[0].Register.WriteMask & 3) {
7312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7313 alu.op = ALU_OP2_OR_INT;
7314
7315 alu.dst.chan = 3;
7316 alu.dst.sel = vtx.dst_gpr;
7317 alu.dst.write = 1;
7318
7319 alu.src[0].sel = vtx.dst_gpr;
7320 alu.src[0].chan = 3;
7321
7322 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
7323 alu.src[1].chan = 0;
7324 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7325
7326 alu.last = 1;
7327 r = r600_bytecode_add_alu(ctx->bc, &alu);
7328 if (r)
7329 return r;
7330 }
7331 return 0;
7332 }
7333
7334 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset, int eg_buffer_base)
7335 {
7336 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7337 int r;
7338 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
7339 int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7340
7341 if (ctx->bc->chip_class < EVERGREEN) {
7342 struct r600_bytecode_alu alu;
7343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7344 alu.op = ALU_OP1_MOV;
7345 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7346 /* r600 we have them at channel 2 of the second dword */
7347 alu.src[0].sel += (id * 2) + 1;
7348 alu.src[0].chan = 1;
7349 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7350 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
7351 alu.last = 1;
7352 r = r600_bytecode_add_alu(ctx->bc, &alu);
7353 if (r)
7354 return r;
7355 return 0;
7356 } else {
7357 struct r600_bytecode_vtx vtx;
7358 memset(&vtx, 0, sizeof(vtx));
7359 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
7360 vtx.buffer_id = id + eg_buffer_base;
7361 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7362 vtx.src_gpr = 0;
7363 vtx.mega_fetch_count = 16; /* no idea here really... */
7364 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7365 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7366 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 4 : 7; /* SEL_Y */
7367 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 4 : 7; /* SEL_Z */
7368 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 4 : 7; /* SEL_W */
7369 vtx.data_format = FMT_32_32_32_32;
7370 vtx.buffer_index_mode = sampler_index_mode;
7371
7372 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
7373 return r;
7374 return 0;
7375 }
7376 }
7377
7378
7379 static int tgsi_tex(struct r600_shader_ctx *ctx)
7380 {
7381 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7382 struct r600_bytecode_tex tex;
7383 struct r600_bytecode_alu alu;
7384 unsigned src_gpr;
7385 int r, i, j;
7386 int opcode;
7387 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
7388 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7389 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
7390 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
7391
7392 bool txf_add_offsets = inst->Texture.NumOffsets &&
7393 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7394 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
7395
7396 /* Texture fetch instructions can only use gprs as source.
7397 * Also they cannot negate the source or take the absolute value */
7398 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
7399 tgsi_tex_src_requires_loading(ctx, 0)) ||
7400 read_compressed_msaa || txf_add_offsets;
7401
7402 boolean src_loaded = FALSE;
7403 unsigned sampler_src_reg = 1;
7404 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
7405 boolean has_txq_cube_array_z = false;
7406 unsigned sampler_index_mode;
7407
7408 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
7409 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7410 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
7411 if (inst->Dst[0].Register.WriteMask & 4) {
7412 ctx->shader->has_txq_cube_array_z_comp = true;
7413 has_txq_cube_array_z = true;
7414 }
7415
7416 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
7417 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7418 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
7419 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
7420 sampler_src_reg = 2;
7421
7422 /* TGSI moves the sampler to src reg 3 for TXD */
7423 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
7424 sampler_src_reg = 3;
7425
7426 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7427
7428 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7429
7430 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
7431 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
7432 if (ctx->bc->chip_class < EVERGREEN)
7433 ctx->shader->uses_tex_buffers = true;
7434 return r600_do_buffer_txq(ctx, 1, 0, R600_MAX_CONST_BUFFERS);
7435 }
7436 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
7437 if (ctx->bc->chip_class < EVERGREEN)
7438 ctx->shader->uses_tex_buffers = true;
7439 return do_vtx_fetch_inst(ctx, src_requires_loading);
7440 }
7441 }
7442
7443 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
7444 int out_chan;
7445 /* Add perspective divide */
7446 if (ctx->bc->chip_class == CAYMAN) {
7447 out_chan = 2;
7448 for (i = 0; i < 3; i++) {
7449 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7450 alu.op = ALU_OP1_RECIP_IEEE;
7451 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7452
7453 alu.dst.sel = ctx->temp_reg;
7454 alu.dst.chan = i;
7455 if (i == 2)
7456 alu.last = 1;
7457 if (out_chan == i)
7458 alu.dst.write = 1;
7459 r = r600_bytecode_add_alu(ctx->bc, &alu);
7460 if (r)
7461 return r;
7462 }
7463
7464 } else {
7465 out_chan = 3;
7466 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7467 alu.op = ALU_OP1_RECIP_IEEE;
7468 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7469
7470 alu.dst.sel = ctx->temp_reg;
7471 alu.dst.chan = out_chan;
7472 alu.last = 1;
7473 alu.dst.write = 1;
7474 r = r600_bytecode_add_alu(ctx->bc, &alu);
7475 if (r)
7476 return r;
7477 }
7478
7479 for (i = 0; i < 3; i++) {
7480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7481 alu.op = ALU_OP2_MUL;
7482 alu.src[0].sel = ctx->temp_reg;
7483 alu.src[0].chan = out_chan;
7484 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7485 alu.dst.sel = ctx->temp_reg;
7486 alu.dst.chan = i;
7487 alu.dst.write = 1;
7488 r = r600_bytecode_add_alu(ctx->bc, &alu);
7489 if (r)
7490 return r;
7491 }
7492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7493 alu.op = ALU_OP1_MOV;
7494 alu.src[0].sel = V_SQ_ALU_SRC_1;
7495 alu.src[0].chan = 0;
7496 alu.dst.sel = ctx->temp_reg;
7497 alu.dst.chan = 3;
7498 alu.last = 1;
7499 alu.dst.write = 1;
7500 r = r600_bytecode_add_alu(ctx->bc, &alu);
7501 if (r)
7502 return r;
7503 src_loaded = TRUE;
7504 src_gpr = ctx->temp_reg;
7505 }
7506
7507
7508 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7509 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7510 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7511 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7512 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
7513
7514 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
7515 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
7516
7517 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7518 for (i = 0; i < 4; i++) {
7519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7520 alu.op = ALU_OP2_CUBE;
7521 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7522 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
7523 alu.dst.sel = ctx->temp_reg;
7524 alu.dst.chan = i;
7525 if (i == 3)
7526 alu.last = 1;
7527 alu.dst.write = 1;
7528 r = r600_bytecode_add_alu(ctx->bc, &alu);
7529 if (r)
7530 return r;
7531 }
7532
7533 /* tmp1.z = RCP_e(|tmp1.z|) */
7534 if (ctx->bc->chip_class == CAYMAN) {
7535 for (i = 0; i < 3; i++) {
7536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7537 alu.op = ALU_OP1_RECIP_IEEE;
7538 alu.src[0].sel = ctx->temp_reg;
7539 alu.src[0].chan = 2;
7540 alu.src[0].abs = 1;
7541 alu.dst.sel = ctx->temp_reg;
7542 alu.dst.chan = i;
7543 if (i == 2)
7544 alu.dst.write = 1;
7545 if (i == 2)
7546 alu.last = 1;
7547 r = r600_bytecode_add_alu(ctx->bc, &alu);
7548 if (r)
7549 return r;
7550 }
7551 } else {
7552 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7553 alu.op = ALU_OP1_RECIP_IEEE;
7554 alu.src[0].sel = ctx->temp_reg;
7555 alu.src[0].chan = 2;
7556 alu.src[0].abs = 1;
7557 alu.dst.sel = ctx->temp_reg;
7558 alu.dst.chan = 2;
7559 alu.dst.write = 1;
7560 alu.last = 1;
7561 r = r600_bytecode_add_alu(ctx->bc, &alu);
7562 if (r)
7563 return r;
7564 }
7565
7566 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7567 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7568 * muladd has no writemask, have to use another temp
7569 */
7570 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7571 alu.op = ALU_OP3_MULADD;
7572 alu.is_op3 = 1;
7573
7574 alu.src[0].sel = ctx->temp_reg;
7575 alu.src[0].chan = 0;
7576 alu.src[1].sel = ctx->temp_reg;
7577 alu.src[1].chan = 2;
7578
7579 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7580 alu.src[2].chan = 0;
7581 alu.src[2].value = u_bitcast_f2u(1.5f);
7582
7583 alu.dst.sel = ctx->temp_reg;
7584 alu.dst.chan = 0;
7585 alu.dst.write = 1;
7586
7587 r = r600_bytecode_add_alu(ctx->bc, &alu);
7588 if (r)
7589 return r;
7590
7591 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7592 alu.op = ALU_OP3_MULADD;
7593 alu.is_op3 = 1;
7594
7595 alu.src[0].sel = ctx->temp_reg;
7596 alu.src[0].chan = 1;
7597 alu.src[1].sel = ctx->temp_reg;
7598 alu.src[1].chan = 2;
7599
7600 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7601 alu.src[2].chan = 0;
7602 alu.src[2].value = u_bitcast_f2u(1.5f);
7603
7604 alu.dst.sel = ctx->temp_reg;
7605 alu.dst.chan = 1;
7606 alu.dst.write = 1;
7607
7608 alu.last = 1;
7609 r = r600_bytecode_add_alu(ctx->bc, &alu);
7610 if (r)
7611 return r;
7612 /* write initial compare value into Z component
7613 - W src 0 for shadow cube
7614 - X src 1 for shadow cube array */
7615 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7616 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7617 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7618 alu.op = ALU_OP1_MOV;
7619 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7620 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7621 else
7622 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7623 alu.dst.sel = ctx->temp_reg;
7624 alu.dst.chan = 2;
7625 alu.dst.write = 1;
7626 alu.last = 1;
7627 r = r600_bytecode_add_alu(ctx->bc, &alu);
7628 if (r)
7629 return r;
7630 }
7631
7632 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7633 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7634 if (ctx->bc->chip_class >= EVERGREEN) {
7635 int mytmp = r600_get_temp(ctx);
7636 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7637 alu.op = ALU_OP1_MOV;
7638 alu.src[0].sel = ctx->temp_reg;
7639 alu.src[0].chan = 3;
7640 alu.dst.sel = mytmp;
7641 alu.dst.chan = 0;
7642 alu.dst.write = 1;
7643 alu.last = 1;
7644 r = r600_bytecode_add_alu(ctx->bc, &alu);
7645 if (r)
7646 return r;
7647
7648 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7649 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7650 alu.op = ALU_OP3_MULADD;
7651 alu.is_op3 = 1;
7652 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7653 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7654 alu.src[1].chan = 0;
7655 alu.src[1].value = u_bitcast_f2u(8.0f);
7656 alu.src[2].sel = mytmp;
7657 alu.src[2].chan = 0;
7658 alu.dst.sel = ctx->temp_reg;
7659 alu.dst.chan = 3;
7660 alu.dst.write = 1;
7661 alu.last = 1;
7662 r = r600_bytecode_add_alu(ctx->bc, &alu);
7663 if (r)
7664 return r;
7665 } else if (ctx->bc->chip_class < EVERGREEN) {
7666 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7667 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7668 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7669 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7670 tex.src_gpr = r600_get_temp(ctx);
7671 tex.src_sel_x = 0;
7672 tex.src_sel_y = 0;
7673 tex.src_sel_z = 0;
7674 tex.src_sel_w = 0;
7675 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7676 tex.coord_type_x = 1;
7677 tex.coord_type_y = 1;
7678 tex.coord_type_z = 1;
7679 tex.coord_type_w = 1;
7680 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7681 alu.op = ALU_OP1_MOV;
7682 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7683 alu.dst.sel = tex.src_gpr;
7684 alu.dst.chan = 0;
7685 alu.last = 1;
7686 alu.dst.write = 1;
7687 r = r600_bytecode_add_alu(ctx->bc, &alu);
7688 if (r)
7689 return r;
7690
7691 r = r600_bytecode_add_tex(ctx->bc, &tex);
7692 if (r)
7693 return r;
7694 }
7695
7696 }
7697
7698 /* for cube forms of lod and bias we need to route things */
7699 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7700 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7701 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7702 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7704 alu.op = ALU_OP1_MOV;
7705 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7706 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7707 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7708 else
7709 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7710 alu.dst.sel = ctx->temp_reg;
7711 alu.dst.chan = 2;
7712 alu.last = 1;
7713 alu.dst.write = 1;
7714 r = r600_bytecode_add_alu(ctx->bc, &alu);
7715 if (r)
7716 return r;
7717 }
7718
7719 src_loaded = TRUE;
7720 src_gpr = ctx->temp_reg;
7721 }
7722
7723 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7724 int temp_h = 0, temp_v = 0;
7725 int start_val = 0;
7726
7727 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7728 if (src_loaded == TRUE)
7729 start_val = 1;
7730 else
7731 src_loaded = TRUE;
7732 for (i = start_val; i < 3; i++) {
7733 int treg = r600_get_temp(ctx);
7734
7735 if (i == 0)
7736 src_gpr = treg;
7737 else if (i == 1)
7738 temp_h = treg;
7739 else
7740 temp_v = treg;
7741
7742 for (j = 0; j < 4; j++) {
7743 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7744 alu.op = ALU_OP1_MOV;
7745 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7746 alu.dst.sel = treg;
7747 alu.dst.chan = j;
7748 if (j == 3)
7749 alu.last = 1;
7750 alu.dst.write = 1;
7751 r = r600_bytecode_add_alu(ctx->bc, &alu);
7752 if (r)
7753 return r;
7754 }
7755 }
7756 for (i = 1; i < 3; i++) {
7757 /* set gradients h/v */
7758 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7759 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7760 FETCH_OP_SET_GRADIENTS_V;
7761 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7762 tex.sampler_index_mode = sampler_index_mode;
7763 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7764 tex.resource_index_mode = sampler_index_mode;
7765
7766 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7767 tex.src_sel_x = 0;
7768 tex.src_sel_y = 1;
7769 tex.src_sel_z = 2;
7770 tex.src_sel_w = 3;
7771
7772 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7773 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7774 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7775 tex.coord_type_x = 1;
7776 tex.coord_type_y = 1;
7777 tex.coord_type_z = 1;
7778 tex.coord_type_w = 1;
7779 }
7780 r = r600_bytecode_add_tex(ctx->bc, &tex);
7781 if (r)
7782 return r;
7783 }
7784 }
7785
7786 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7787 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
7788 * incorrectly forces nearest filtering if the texture format is integer.
7789 * The only effect it has on Gather4, which always returns 4 texels for
7790 * bilinear filtering, is that the final coordinates are off by 0.5 of
7791 * the texel size.
7792 *
7793 * The workaround is to subtract 0.5 from the unnormalized coordinates,
7794 * or (0.5 / size) from the normalized coordinates.
7795 */
7796 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
7797 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
7798 int treg = r600_get_temp(ctx);
7799
7800 /* mov array and comparison oordinate to temp_reg if needed */
7801 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7802 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7803 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) && !src_loaded) {
7804 int end = inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ? 3 : 2;
7805 for (i = 2; i <= end; i++) {
7806 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7807 alu.op = ALU_OP1_MOV;
7808 alu.dst.sel = ctx->temp_reg;
7809 alu.dst.chan = i;
7810 alu.dst.write = 1;
7811 alu.last = (i == end);
7812 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7813 r = r600_bytecode_add_alu(ctx->bc, &alu);
7814 if (r)
7815 return r;
7816 }
7817 }
7818
7819 if (inst->Texture.Texture == TGSI_TEXTURE_RECT ||
7820 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
7821 for (i = 0; i < 2; i++) {
7822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7823 alu.op = ALU_OP2_ADD;
7824 alu.dst.sel = ctx->temp_reg;
7825 alu.dst.chan = i;
7826 alu.dst.write = 1;
7827 alu.last = i == 1;
7828 if (src_loaded) {
7829 alu.src[0].sel = ctx->temp_reg;
7830 alu.src[0].chan = i;
7831 } else
7832 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7833 alu.src[1].sel = V_SQ_ALU_SRC_0_5;
7834 alu.src[1].neg = 1;
7835 r = r600_bytecode_add_alu(ctx->bc, &alu);
7836 if (r)
7837 return r;
7838 }
7839 } else {
7840 /* execute a TXQ */
7841 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7842 tex.op = FETCH_OP_GET_TEXTURE_RESINFO;
7843 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7844 tex.sampler_index_mode = sampler_index_mode;
7845 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7846 tex.resource_index_mode = sampler_index_mode;
7847 tex.dst_gpr = treg;
7848 tex.src_sel_x = 4;
7849 tex.src_sel_y = 4;
7850 tex.src_sel_z = 4;
7851 tex.src_sel_w = 4;
7852 tex.dst_sel_x = 0;
7853 tex.dst_sel_y = 1;
7854 tex.dst_sel_z = 7;
7855 tex.dst_sel_w = 7;
7856 r = r600_bytecode_add_tex(ctx->bc, &tex);
7857 if (r)
7858 return r;
7859
7860 /* coord.xy = -0.5 * (1.0/int_to_flt(size)) + coord.xy */
7861 if (ctx->bc->chip_class == CAYMAN) {
7862 /* */
7863 for (i = 0; i < 2; i++) {
7864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7865 alu.op = ALU_OP1_INT_TO_FLT;
7866 alu.dst.sel = treg;
7867 alu.dst.chan = i;
7868 alu.dst.write = 1;
7869 alu.src[0].sel = treg;
7870 alu.src[0].chan = i;
7871 alu.last = (i == 1) ? 1 : 0;
7872 r = r600_bytecode_add_alu(ctx->bc, &alu);
7873 if (r)
7874 return r;
7875 }
7876 for (j = 0; j < 2; j++) {
7877 for (i = 0; i < 3; i++) {
7878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7879 alu.op = ALU_OP1_RECIP_IEEE;
7880 alu.src[0].sel = treg;
7881 alu.src[0].chan = j;
7882 alu.dst.sel = treg;
7883 alu.dst.chan = i;
7884 if (i == 2)
7885 alu.last = 1;
7886 if (i == j)
7887 alu.dst.write = 1;
7888 r = r600_bytecode_add_alu(ctx->bc, &alu);
7889 if (r)
7890 return r;
7891 }
7892 }
7893 } else {
7894 for (i = 0; i < 2; i++) {
7895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7896 alu.op = ALU_OP1_INT_TO_FLT;
7897 alu.dst.sel = treg;
7898 alu.dst.chan = i;
7899 alu.dst.write = 1;
7900 alu.src[0].sel = treg;
7901 alu.src[0].chan = i;
7902 alu.last = 1;
7903 r = r600_bytecode_add_alu(ctx->bc, &alu);
7904 if (r)
7905 return r;
7906 }
7907 for (i = 0; i < 2; i++) {
7908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7909 alu.op = ALU_OP1_RECIP_IEEE;
7910 alu.src[0].sel = treg;
7911 alu.src[0].chan = i;
7912 alu.dst.sel = treg;
7913 alu.dst.chan = i;
7914 alu.last = 1;
7915 alu.dst.write = 1;
7916 r = r600_bytecode_add_alu(ctx->bc, &alu);
7917 if (r)
7918 return r;
7919 }
7920 }
7921 for (i = 0; i < 2; i++) {
7922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7923 alu.op = ALU_OP3_MULADD;
7924 alu.is_op3 = 1;
7925 alu.dst.sel = ctx->temp_reg;
7926 alu.dst.chan = i;
7927 alu.dst.write = 1;
7928 alu.last = i == 1;
7929 alu.src[0].sel = treg;
7930 alu.src[0].chan = i;
7931 alu.src[1].sel = V_SQ_ALU_SRC_0_5;
7932 alu.src[1].neg = 1;
7933 if (src_loaded) {
7934 alu.src[2].sel = ctx->temp_reg;
7935 alu.src[2].chan = i;
7936 } else
7937 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
7938 r = r600_bytecode_add_alu(ctx->bc, &alu);
7939 if (r)
7940 return r;
7941 }
7942 }
7943 src_loaded = TRUE;
7944 src_gpr = ctx->temp_reg;
7945 }
7946 }
7947
7948 if (src_requires_loading && !src_loaded) {
7949 for (i = 0; i < 4; i++) {
7950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7951 alu.op = ALU_OP1_MOV;
7952 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7953 alu.dst.sel = ctx->temp_reg;
7954 alu.dst.chan = i;
7955 if (i == 3)
7956 alu.last = 1;
7957 alu.dst.write = 1;
7958 r = r600_bytecode_add_alu(ctx->bc, &alu);
7959 if (r)
7960 return r;
7961 }
7962 src_loaded = TRUE;
7963 src_gpr = ctx->temp_reg;
7964 }
7965
7966 /* get offset values */
7967 if (inst->Texture.NumOffsets) {
7968 assert(inst->Texture.NumOffsets == 1);
7969
7970 /* The texture offset feature doesn't work with the TXF instruction
7971 * and must be emulated by adding the offset to the texture coordinates. */
7972 if (txf_add_offsets) {
7973 const struct tgsi_texture_offset *off = inst->TexOffsets;
7974
7975 switch (inst->Texture.Texture) {
7976 case TGSI_TEXTURE_3D:
7977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7978 alu.op = ALU_OP2_ADD_INT;
7979 alu.src[0].sel = src_gpr;
7980 alu.src[0].chan = 2;
7981 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7982 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7983 alu.dst.sel = src_gpr;
7984 alu.dst.chan = 2;
7985 alu.dst.write = 1;
7986 alu.last = 1;
7987 r = r600_bytecode_add_alu(ctx->bc, &alu);
7988 if (r)
7989 return r;
7990 /* fall through */
7991
7992 case TGSI_TEXTURE_2D:
7993 case TGSI_TEXTURE_SHADOW2D:
7994 case TGSI_TEXTURE_RECT:
7995 case TGSI_TEXTURE_SHADOWRECT:
7996 case TGSI_TEXTURE_2D_ARRAY:
7997 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7999 alu.op = ALU_OP2_ADD_INT;
8000 alu.src[0].sel = src_gpr;
8001 alu.src[0].chan = 1;
8002 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8003 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
8004 alu.dst.sel = src_gpr;
8005 alu.dst.chan = 1;
8006 alu.dst.write = 1;
8007 alu.last = 1;
8008 r = r600_bytecode_add_alu(ctx->bc, &alu);
8009 if (r)
8010 return r;
8011 /* fall through */
8012
8013 case TGSI_TEXTURE_1D:
8014 case TGSI_TEXTURE_SHADOW1D:
8015 case TGSI_TEXTURE_1D_ARRAY:
8016 case TGSI_TEXTURE_SHADOW1D_ARRAY:
8017 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8018 alu.op = ALU_OP2_ADD_INT;
8019 alu.src[0].sel = src_gpr;
8020 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8021 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
8022 alu.dst.sel = src_gpr;
8023 alu.dst.write = 1;
8024 alu.last = 1;
8025 r = r600_bytecode_add_alu(ctx->bc, &alu);
8026 if (r)
8027 return r;
8028 break;
8029 /* texture offsets do not apply to other texture targets */
8030 }
8031 } else {
8032 switch (inst->Texture.Texture) {
8033 case TGSI_TEXTURE_3D:
8034 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
8035 /* fallthrough */
8036 case TGSI_TEXTURE_2D:
8037 case TGSI_TEXTURE_SHADOW2D:
8038 case TGSI_TEXTURE_RECT:
8039 case TGSI_TEXTURE_SHADOWRECT:
8040 case TGSI_TEXTURE_2D_ARRAY:
8041 case TGSI_TEXTURE_SHADOW2D_ARRAY:
8042 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
8043 /* fallthrough */
8044 case TGSI_TEXTURE_1D:
8045 case TGSI_TEXTURE_SHADOW1D:
8046 case TGSI_TEXTURE_1D_ARRAY:
8047 case TGSI_TEXTURE_SHADOW1D_ARRAY:
8048 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
8049 }
8050 }
8051 }
8052
8053 /* Obtain the sample index for reading a compressed MSAA color texture.
8054 * To read the FMASK, we use the ldfptr instruction, which tells us
8055 * where the samples are stored.
8056 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
8057 * which is the identity mapping. Each nibble says which physical sample
8058 * should be fetched to get that sample.
8059 *
8060 * Assume src.z contains the sample index. It should be modified like this:
8061 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
8062 * Then fetch the texel with src.
8063 */
8064 if (read_compressed_msaa) {
8065 unsigned sample_chan = 3;
8066 unsigned temp = r600_get_temp(ctx);
8067 assert(src_loaded);
8068
8069 /* temp.w = ldfptr() */
8070 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8071 tex.op = FETCH_OP_LD;
8072 tex.inst_mod = 1; /* to indicate this is ldfptr */
8073 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8074 tex.sampler_index_mode = sampler_index_mode;
8075 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
8076 tex.resource_index_mode = sampler_index_mode;
8077 tex.src_gpr = src_gpr;
8078 tex.dst_gpr = temp;
8079 tex.dst_sel_x = 7; /* mask out these components */
8080 tex.dst_sel_y = 7;
8081 tex.dst_sel_z = 7;
8082 tex.dst_sel_w = 0; /* store X */
8083 tex.src_sel_x = 0;
8084 tex.src_sel_y = 1;
8085 tex.src_sel_z = 2;
8086 tex.src_sel_w = 3;
8087 tex.offset_x = offset_x;
8088 tex.offset_y = offset_y;
8089 tex.offset_z = offset_z;
8090 r = r600_bytecode_add_tex(ctx->bc, &tex);
8091 if (r)
8092 return r;
8093
8094 /* temp.x = sample_index*4 */
8095 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8096 alu.op = ALU_OP2_MULLO_INT;
8097 alu.src[0].sel = src_gpr;
8098 alu.src[0].chan = sample_chan;
8099 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8100 alu.src[1].value = 4;
8101 alu.dst.sel = temp;
8102 alu.dst.chan = 0;
8103 alu.dst.write = 1;
8104 r = emit_mul_int_op(ctx->bc, &alu);
8105 if (r)
8106 return r;
8107
8108 /* sample_index = temp.w >> temp.x */
8109 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8110 alu.op = ALU_OP2_LSHR_INT;
8111 alu.src[0].sel = temp;
8112 alu.src[0].chan = 3;
8113 alu.src[1].sel = temp;
8114 alu.src[1].chan = 0;
8115 alu.dst.sel = src_gpr;
8116 alu.dst.chan = sample_chan;
8117 alu.dst.write = 1;
8118 alu.last = 1;
8119 r = r600_bytecode_add_alu(ctx->bc, &alu);
8120 if (r)
8121 return r;
8122
8123 /* sample_index & 0xF */
8124 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8125 alu.op = ALU_OP2_AND_INT;
8126 alu.src[0].sel = src_gpr;
8127 alu.src[0].chan = sample_chan;
8128 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8129 alu.src[1].value = 0xF;
8130 alu.dst.sel = src_gpr;
8131 alu.dst.chan = sample_chan;
8132 alu.dst.write = 1;
8133 alu.last = 1;
8134 r = r600_bytecode_add_alu(ctx->bc, &alu);
8135 if (r)
8136 return r;
8137 #if 0
8138 /* visualize the FMASK */
8139 for (i = 0; i < 4; i++) {
8140 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8141 alu.op = ALU_OP1_INT_TO_FLT;
8142 alu.src[0].sel = src_gpr;
8143 alu.src[0].chan = sample_chan;
8144 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8145 alu.dst.chan = i;
8146 alu.dst.write = 1;
8147 alu.last = 1;
8148 r = r600_bytecode_add_alu(ctx->bc, &alu);
8149 if (r)
8150 return r;
8151 }
8152 return 0;
8153 #endif
8154 }
8155
8156 /* does this shader want a num layers from TXQ for a cube array? */
8157 if (has_txq_cube_array_z) {
8158 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8159
8160 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8161 alu.op = ALU_OP1_MOV;
8162
8163 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8164 if (ctx->bc->chip_class >= EVERGREEN) {
8165 /* with eg each dword is number of cubes */
8166 alu.src[0].sel += id / 4;
8167 alu.src[0].chan = id % 4;
8168 } else {
8169 /* r600 we have them at channel 2 of the second dword */
8170 alu.src[0].sel += (id * 2) + 1;
8171 alu.src[0].chan = 2;
8172 }
8173 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8174 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8175 alu.last = 1;
8176 r = r600_bytecode_add_alu(ctx->bc, &alu);
8177 if (r)
8178 return r;
8179 /* disable writemask from texture instruction */
8180 inst->Dst[0].Register.WriteMask &= ~4;
8181 }
8182
8183 opcode = ctx->inst_info->op;
8184 if (opcode == FETCH_OP_GATHER4 &&
8185 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
8186 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
8187 opcode = FETCH_OP_GATHER4_O;
8188
8189 /* GATHER4_O/GATHER4_C_O use offset values loaded by
8190 SET_TEXTURE_OFFSETS instruction. The immediate offset values
8191 encoded in the instruction are ignored. */
8192 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8193 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
8194 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8195 tex.sampler_index_mode = sampler_index_mode;
8196 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
8197 tex.resource_index_mode = sampler_index_mode;
8198
8199 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
8200 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
8201 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
8202 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
8203 tex.src_sel_w = 4;
8204
8205 tex.dst_sel_x = 7;
8206 tex.dst_sel_y = 7;
8207 tex.dst_sel_z = 7;
8208 tex.dst_sel_w = 7;
8209
8210 r = r600_bytecode_add_tex(ctx->bc, &tex);
8211 if (r)
8212 return r;
8213 }
8214
8215 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
8216 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
8217 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
8218 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
8219 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
8220 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
8221 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
8222 switch (opcode) {
8223 case FETCH_OP_SAMPLE:
8224 opcode = FETCH_OP_SAMPLE_C;
8225 break;
8226 case FETCH_OP_SAMPLE_L:
8227 opcode = FETCH_OP_SAMPLE_C_L;
8228 break;
8229 case FETCH_OP_SAMPLE_LB:
8230 opcode = FETCH_OP_SAMPLE_C_LB;
8231 break;
8232 case FETCH_OP_SAMPLE_G:
8233 opcode = FETCH_OP_SAMPLE_C_G;
8234 break;
8235 /* Texture gather variants */
8236 case FETCH_OP_GATHER4:
8237 opcode = FETCH_OP_GATHER4_C;
8238 break;
8239 case FETCH_OP_GATHER4_O:
8240 opcode = FETCH_OP_GATHER4_C_O;
8241 break;
8242 }
8243 }
8244
8245 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8246 tex.op = opcode;
8247
8248 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8249 tex.sampler_index_mode = sampler_index_mode;
8250 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
8251 tex.resource_index_mode = sampler_index_mode;
8252 tex.src_gpr = src_gpr;
8253 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8254
8255 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
8256 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
8257 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
8258 }
8259
8260 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
8261 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
8262 tex.inst_mod = texture_component_select;
8263
8264 if (ctx->bc->chip_class == CAYMAN) {
8265 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8266 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8267 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8268 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8269 } else {
8270 /* GATHER4 result order is different from TGSI TG4 */
8271 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 1 : 7;
8272 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 2 : 7;
8273 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 0 : 7;
8274 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8275 }
8276 }
8277 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
8278 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8279 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8280 tex.dst_sel_z = 7;
8281 tex.dst_sel_w = 7;
8282 }
8283 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
8284 tex.dst_sel_x = 3;
8285 tex.dst_sel_y = 7;
8286 tex.dst_sel_z = 7;
8287 tex.dst_sel_w = 7;
8288 }
8289 else {
8290 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8291 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8292 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8293 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8294 }
8295
8296
8297 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
8298 tex.src_sel_x = 4;
8299 tex.src_sel_y = 4;
8300 tex.src_sel_z = 4;
8301 tex.src_sel_w = 4;
8302 } else if (src_loaded) {
8303 tex.src_sel_x = 0;
8304 tex.src_sel_y = 1;
8305 tex.src_sel_z = 2;
8306 tex.src_sel_w = 3;
8307 } else {
8308 tex.src_sel_x = ctx->src[0].swizzle[0];
8309 tex.src_sel_y = ctx->src[0].swizzle[1];
8310 tex.src_sel_z = ctx->src[0].swizzle[2];
8311 tex.src_sel_w = ctx->src[0].swizzle[3];
8312 tex.src_rel = ctx->src[0].rel;
8313 }
8314
8315 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
8316 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
8317 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
8318 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
8319 tex.src_sel_x = 1;
8320 tex.src_sel_y = 0;
8321 tex.src_sel_z = 3;
8322 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
8323 }
8324
8325 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
8326 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
8327 tex.coord_type_x = 1;
8328 tex.coord_type_y = 1;
8329 }
8330 tex.coord_type_z = 1;
8331 tex.coord_type_w = 1;
8332
8333 tex.offset_x = offset_x;
8334 tex.offset_y = offset_y;
8335 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
8336 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8337 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
8338 tex.offset_z = 0;
8339 }
8340 else {
8341 tex.offset_z = offset_z;
8342 }
8343
8344 /* Put the depth for comparison in W.
8345 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
8346 * Some instructions expect the depth in Z. */
8347 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
8348 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
8349 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
8350 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
8351 opcode != FETCH_OP_SAMPLE_C_L &&
8352 opcode != FETCH_OP_SAMPLE_C_LB) {
8353 tex.src_sel_w = tex.src_sel_z;
8354 }
8355
8356 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
8357 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
8358 if (opcode == FETCH_OP_SAMPLE_C_L ||
8359 opcode == FETCH_OP_SAMPLE_C_LB) {
8360 /* the array index is read from Y */
8361 tex.coord_type_y = 0;
8362 } else {
8363 /* the array index is read from Z */
8364 tex.coord_type_z = 0;
8365 tex.src_sel_z = tex.src_sel_y;
8366 }
8367 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8368 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
8369 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
8370 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
8371 (ctx->bc->chip_class >= EVERGREEN)))
8372 /* the array index is read from Z */
8373 tex.coord_type_z = 0;
8374
8375 /* mask unused source components */
8376 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
8377 switch (inst->Texture.Texture) {
8378 case TGSI_TEXTURE_2D:
8379 case TGSI_TEXTURE_RECT:
8380 tex.src_sel_z = 7;
8381 tex.src_sel_w = 7;
8382 break;
8383 case TGSI_TEXTURE_1D_ARRAY:
8384 tex.src_sel_y = 7;
8385 tex.src_sel_w = 7;
8386 break;
8387 case TGSI_TEXTURE_1D:
8388 tex.src_sel_y = 7;
8389 tex.src_sel_z = 7;
8390 tex.src_sel_w = 7;
8391 break;
8392 }
8393 }
8394
8395 r = r600_bytecode_add_tex(ctx->bc, &tex);
8396 if (r)
8397 return r;
8398
8399 /* add shadow ambient support - gallium doesn't do it yet */
8400 return 0;
8401 }
8402
8403 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
8404 struct tgsi_full_src_register *src)
8405 {
8406 unsigned i;
8407
8408 if (src->Register.Indirect) {
8409 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
8410 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
8411 return ctx->shader->atomics[i].hw_idx;
8412 }
8413 } else {
8414 uint32_t index = src->Register.Index;
8415 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
8416 if (ctx->shader->atomics[i].buffer_id != (unsigned)src->Dimension.Index)
8417 continue;
8418 if (index > ctx->shader->atomics[i].end)
8419 continue;
8420 if (index < ctx->shader->atomics[i].start)
8421 continue;
8422 uint32_t offset = (index - ctx->shader->atomics[i].start);
8423 return ctx->shader->atomics[i].hw_idx + offset;
8424 }
8425 }
8426 assert(0);
8427 return -1;
8428 }
8429
8430 static int tgsi_set_gds_temp(struct r600_shader_ctx *ctx,
8431 int *uav_id_p, int *uav_index_mode_p)
8432 {
8433 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8434 int uav_id, uav_index_mode = 0;
8435 int r;
8436 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8437
8438 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
8439
8440 if (inst->Src[0].Register.Indirect) {
8441 if (is_cm) {
8442 struct r600_bytecode_alu alu;
8443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8444 alu.op = ALU_OP2_LSHL_INT;
8445 alu.src[0].sel = get_address_file_reg(ctx, inst->Src[0].Indirect.Index);
8446 alu.src[0].chan = 0;
8447 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8448 alu.src[1].value = 2;
8449 alu.dst.sel = ctx->temp_reg;
8450 alu.dst.chan = 0;
8451 alu.dst.write = 1;
8452 alu.last = 1;
8453 r = r600_bytecode_add_alu(ctx->bc, &alu);
8454 if (r)
8455 return r;
8456
8457 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8458 ctx->temp_reg, 0,
8459 ctx->temp_reg, 0,
8460 V_SQ_ALU_SRC_LITERAL, uav_id * 4);
8461 if (r)
8462 return r;
8463 } else
8464 uav_index_mode = 2;
8465 } else if (is_cm) {
8466 r = single_alu_op2(ctx, ALU_OP1_MOV,
8467 ctx->temp_reg, 0,
8468 V_SQ_ALU_SRC_LITERAL, uav_id * 4,
8469 0, 0);
8470 if (r)
8471 return r;
8472 }
8473 *uav_id_p = uav_id;
8474 *uav_index_mode_p = uav_index_mode;
8475 return 0;
8476 }
8477
8478 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
8479 {
8480 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8481 int r;
8482 struct r600_bytecode_gds gds;
8483 int uav_id = 0;
8484 int uav_index_mode = 0;
8485 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8486
8487 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8488 if (r)
8489 return r;
8490
8491 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8492 gds.op = FETCH_OP_GDS_READ_RET;
8493 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8494 gds.uav_id = is_cm ? 0 : uav_id;
8495 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8496 gds.src_gpr = ctx->temp_reg;
8497 gds.src_sel_x = (is_cm) ? 0 : 4;
8498 gds.src_sel_y = 4;
8499 gds.src_sel_z = 4;
8500 gds.dst_sel_x = 0;
8501 gds.dst_sel_y = 7;
8502 gds.dst_sel_z = 7;
8503 gds.dst_sel_w = 7;
8504 gds.src_gpr2 = 0;
8505 gds.alloc_consume = !is_cm;
8506 r = r600_bytecode_add_gds(ctx->bc, &gds);
8507 if (r)
8508 return r;
8509
8510 ctx->bc->cf_last->vpm = 1;
8511 return 0;
8512 }
8513
8514 /* this fixes up 1D arrays properly */
8515 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
8516 {
8517 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8518 int r, i;
8519 struct r600_bytecode_alu alu;
8520 int temp_reg = r600_get_temp(ctx);
8521
8522 for (i = 0; i < 4; i++) {
8523 bool def_val = true, write_zero = false;
8524 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8525 alu.op = ALU_OP1_MOV;
8526 alu.dst.sel = temp_reg;
8527 alu.dst.chan = i;
8528
8529 switch (inst->Memory.Texture) {
8530 case TGSI_TEXTURE_BUFFER:
8531 case TGSI_TEXTURE_1D:
8532 if (i == 1 || i == 2 || i == 3) {
8533 write_zero = true;
8534 }
8535 break;
8536 case TGSI_TEXTURE_1D_ARRAY:
8537 if (i == 1 || i == 3)
8538 write_zero = true;
8539 else if (i == 2) {
8540 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
8541 def_val = false;
8542 }
8543 break;
8544 case TGSI_TEXTURE_2D:
8545 if (i == 2 || i == 3)
8546 write_zero = true;
8547 break;
8548 default:
8549 if (i == 3)
8550 write_zero = true;
8551 break;
8552 }
8553
8554 if (write_zero) {
8555 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8556 alu.src[0].value = 0;
8557 } else if (def_val) {
8558 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
8559 }
8560
8561 if (i == 3)
8562 alu.last = 1;
8563 alu.dst.write = 1;
8564 r = r600_bytecode_add_alu(ctx->bc, &alu);
8565 if (r)
8566 return r;
8567 }
8568 *idx_gpr = temp_reg;
8569 return 0;
8570 }
8571
8572 static int load_buffer_coord(struct r600_shader_ctx *ctx, int src_idx,
8573 int temp_reg)
8574 {
8575 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8576 int r;
8577 if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
8578 int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
8579 r = single_alu_op2(ctx, ALU_OP1_MOV,
8580 temp_reg, 0,
8581 V_SQ_ALU_SRC_LITERAL, value >> 2,
8582 0, 0);
8583 if (r)
8584 return r;
8585 } else {
8586 struct r600_bytecode_alu alu;
8587 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8588 alu.op = ALU_OP2_LSHR_INT;
8589 r600_bytecode_src(&alu.src[0], &ctx->src[src_idx], 0);
8590 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8591 alu.src[1].value = 2;
8592 alu.dst.sel = temp_reg;
8593 alu.dst.write = 1;
8594 alu.last = 1;
8595 r = r600_bytecode_add_alu(ctx->bc, &alu);
8596 if (r)
8597 return r;
8598 }
8599 return 0;
8600 }
8601
8602 static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
8603 {
8604 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8605 /* have to work out the offset into the RAT immediate return buffer */
8606 struct r600_bytecode_vtx vtx;
8607 struct r600_bytecode_cf *cf;
8608 int r;
8609 int temp_reg = r600_get_temp(ctx);
8610 unsigned rat_index_mode;
8611 unsigned base;
8612
8613 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8614 base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
8615
8616 r = load_buffer_coord(ctx, 1, temp_reg);
8617 if (r)
8618 return r;
8619 ctx->bc->cf_last->barrier = 1;
8620 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8621 vtx.op = FETCH_OP_VFETCH;
8622 vtx.buffer_id = inst->Src[0].Register.Index + base;
8623 vtx.buffer_index_mode = rat_index_mode;
8624 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8625 vtx.src_gpr = temp_reg;
8626 vtx.src_sel_x = 0;
8627 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8628 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
8629 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
8630 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
8631 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
8632 vtx.num_format_all = 1;
8633 vtx.format_comp_all = 1;
8634 vtx.srf_mode_all = 0;
8635
8636 if (inst->Dst[0].Register.WriteMask & 8) {
8637 vtx.data_format = FMT_32_32_32_32;
8638 vtx.use_const_fields = 0;
8639 } else if (inst->Dst[0].Register.WriteMask & 4) {
8640 vtx.data_format = FMT_32_32_32;
8641 vtx.use_const_fields = 0;
8642 } else if (inst->Dst[0].Register.WriteMask & 2) {
8643 vtx.data_format = FMT_32_32;
8644 vtx.use_const_fields = 0;
8645 } else {
8646 vtx.data_format = FMT_32;
8647 vtx.use_const_fields = 0;
8648 }
8649
8650 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8651 if (r)
8652 return r;
8653 cf = ctx->bc->cf_last;
8654 cf->barrier = 1;
8655 return 0;
8656 }
8657
8658 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
8659 {
8660 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8661 /* have to work out the offset into the RAT immediate return buffer */
8662 struct r600_bytecode_vtx vtx;
8663 struct r600_bytecode_cf *cf;
8664 int r;
8665 int idx_gpr;
8666 unsigned format, num_format, format_comp, endian;
8667 const struct util_format_description *desc;
8668 unsigned rat_index_mode;
8669 unsigned immed_base;
8670
8671 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8672
8673 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8674 r = load_index_src(ctx, 1, &idx_gpr);
8675 if (r)
8676 return r;
8677
8678 if (rat_index_mode)
8679 egcm_load_index_reg(ctx->bc, 1, false);
8680
8681 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8682 cf = ctx->bc->cf_last;
8683
8684 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8685 cf->rat.inst = V_RAT_INST_NOP_RTN;
8686 cf->rat.index_mode = rat_index_mode;
8687 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8688 cf->output.gpr = ctx->thread_id_gpr;
8689 cf->output.index_gpr = idx_gpr;
8690 cf->output.comp_mask = 0xf;
8691 cf->output.burst_count = 1;
8692 cf->vpm = 1;
8693 cf->barrier = 1;
8694 cf->mark = 1;
8695 cf->output.elem_size = 0;
8696
8697 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8698 cf = ctx->bc->cf_last;
8699 cf->barrier = 1;
8700
8701 desc = util_format_description(inst->Memory.Format);
8702 r600_vertex_data_type(inst->Memory.Format,
8703 &format, &num_format, &format_comp, &endian);
8704 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8705 vtx.op = FETCH_OP_VFETCH;
8706 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8707 vtx.buffer_index_mode = rat_index_mode;
8708 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8709 vtx.src_gpr = ctx->thread_id_gpr;
8710 vtx.src_sel_x = 1;
8711 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8712 vtx.dst_sel_x = desc->swizzle[0];
8713 vtx.dst_sel_y = desc->swizzle[1];
8714 vtx.dst_sel_z = desc->swizzle[2];
8715 vtx.dst_sel_w = desc->swizzle[3];
8716 vtx.srf_mode_all = 1;
8717 vtx.data_format = format;
8718 vtx.num_format_all = num_format;
8719 vtx.format_comp_all = format_comp;
8720 vtx.endian = endian;
8721 vtx.offset = 0;
8722 vtx.mega_fetch_count = 3;
8723 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8724 if (r)
8725 return r;
8726 cf = ctx->bc->cf_last;
8727 cf->barrier = 1;
8728 return 0;
8729 }
8730
8731 static int tgsi_load_lds(struct r600_shader_ctx *ctx)
8732 {
8733 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8734 struct r600_bytecode_alu alu;
8735 int r;
8736 int temp_reg = r600_get_temp(ctx);
8737
8738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8739 alu.op = ALU_OP1_MOV;
8740 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8741 alu.dst.sel = temp_reg;
8742 alu.dst.write = 1;
8743 alu.last = 1;
8744 r = r600_bytecode_add_alu(ctx->bc, &alu);
8745 if (r)
8746 return r;
8747
8748 r = do_lds_fetch_values(ctx, temp_reg,
8749 ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
8750 if (r)
8751 return r;
8752 return 0;
8753 }
8754
8755 static int tgsi_load(struct r600_shader_ctx *ctx)
8756 {
8757 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8758 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8759 return tgsi_load_rat(ctx);
8760 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8761 return tgsi_load_gds(ctx);
8762 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8763 return tgsi_load_buffer(ctx);
8764 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8765 return tgsi_load_lds(ctx);
8766 return 0;
8767 }
8768
8769 static int tgsi_store_buffer_rat(struct r600_shader_ctx *ctx)
8770 {
8771 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8772 struct r600_bytecode_cf *cf;
8773 int r, i;
8774 unsigned rat_index_mode;
8775 int lasti;
8776 int temp_reg = r600_get_temp(ctx), treg2 = r600_get_temp(ctx);
8777
8778 r = load_buffer_coord(ctx, 0, treg2);
8779 if (r)
8780 return r;
8781
8782 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8783 if (rat_index_mode)
8784 egcm_load_index_reg(ctx->bc, 1, false);
8785
8786 for (i = 0; i <= 3; i++) {
8787 struct r600_bytecode_alu alu;
8788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8789 alu.op = ALU_OP1_MOV;
8790 alu.dst.sel = temp_reg;
8791 alu.dst.chan = i;
8792 alu.src[0].sel = V_SQ_ALU_SRC_0;
8793 alu.last = (i == 3);
8794 alu.dst.write = 1;
8795 r = r600_bytecode_add_alu(ctx->bc, &alu);
8796 if (r)
8797 return r;
8798 }
8799
8800 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8801 for (i = 0; i <= lasti; i++) {
8802 struct r600_bytecode_alu alu;
8803 if (!((1 << i) & inst->Dst[0].Register.WriteMask))
8804 continue;
8805
8806 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8807 temp_reg, 0,
8808 treg2, 0,
8809 V_SQ_ALU_SRC_LITERAL, i);
8810 if (r)
8811 return r;
8812
8813 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8814 alu.op = ALU_OP1_MOV;
8815 alu.dst.sel = ctx->temp_reg;
8816 alu.dst.chan = 0;
8817
8818 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8819 alu.last = 1;
8820 alu.dst.write = 1;
8821 r = r600_bytecode_add_alu(ctx->bc, &alu);
8822 if (r)
8823 return r;
8824
8825 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8826 cf = ctx->bc->cf_last;
8827
8828 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index + ctx->info.file_count[TGSI_FILE_IMAGE];
8829 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8830 cf->rat.index_mode = rat_index_mode;
8831 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8832 cf->output.gpr = ctx->temp_reg;
8833 cf->output.index_gpr = temp_reg;
8834 cf->output.comp_mask = 1;
8835 cf->output.burst_count = 1;
8836 cf->vpm = 1;
8837 cf->barrier = 1;
8838 cf->output.elem_size = 0;
8839 }
8840 return 0;
8841 }
8842
8843 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
8844 {
8845 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8846 struct r600_bytecode_cf *cf;
8847 bool src_requires_loading = false;
8848 int val_gpr, idx_gpr;
8849 int r, i;
8850 unsigned rat_index_mode;
8851
8852 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8853
8854 r = load_index_src(ctx, 0, &idx_gpr);
8855 if (r)
8856 return r;
8857
8858 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
8859 src_requires_loading = true;
8860
8861 if (src_requires_loading) {
8862 struct r600_bytecode_alu alu;
8863 for (i = 0; i < 4; i++) {
8864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8865 alu.op = ALU_OP1_MOV;
8866 alu.dst.sel = ctx->temp_reg;
8867 alu.dst.chan = i;
8868
8869 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8870 if (i == 3)
8871 alu.last = 1;
8872 alu.dst.write = 1;
8873 r = r600_bytecode_add_alu(ctx->bc, &alu);
8874 if (r)
8875 return r;
8876 }
8877 val_gpr = ctx->temp_reg;
8878 } else
8879 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
8880 if (rat_index_mode)
8881 egcm_load_index_reg(ctx->bc, 1, false);
8882
8883 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8884 cf = ctx->bc->cf_last;
8885
8886 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
8887 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8888 cf->rat.index_mode = rat_index_mode;
8889 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8890 cf->output.gpr = val_gpr;
8891 cf->output.index_gpr = idx_gpr;
8892 cf->output.comp_mask = 0xf;
8893 cf->output.burst_count = 1;
8894 cf->vpm = 1;
8895 cf->barrier = 1;
8896 cf->output.elem_size = 0;
8897 return 0;
8898 }
8899
8900 static int tgsi_store_lds(struct r600_shader_ctx *ctx)
8901 {
8902 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8903 struct r600_bytecode_alu alu;
8904 int r, i, lasti;
8905 int write_mask = inst->Dst[0].Register.WriteMask;
8906 int temp_reg = r600_get_temp(ctx);
8907
8908 /* LDS write */
8909 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8910 alu.op = ALU_OP1_MOV;
8911 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8912 alu.dst.sel = temp_reg;
8913 alu.dst.write = 1;
8914 alu.last = 1;
8915 r = r600_bytecode_add_alu(ctx->bc, &alu);
8916 if (r)
8917 return r;
8918
8919 lasti = tgsi_last_instruction(write_mask);
8920 for (i = 1; i <= lasti; i++) {
8921 if (!(write_mask & (1 << i)))
8922 continue;
8923 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8924 temp_reg, i,
8925 temp_reg, 0,
8926 V_SQ_ALU_SRC_LITERAL, 4 * i);
8927 if (r)
8928 return r;
8929 }
8930 for (i = 0; i <= lasti; i++) {
8931 if (!(write_mask & (1 << i)))
8932 continue;
8933
8934 if ((i == 0 && ((write_mask & 3) == 3)) ||
8935 (i == 2 && ((write_mask & 0xc) == 0xc))) {
8936 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8937 alu.op = LDS_OP3_LDS_WRITE_REL;
8938
8939 alu.src[0].sel = temp_reg;
8940 alu.src[0].chan = i;
8941 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8942 r600_bytecode_src(&alu.src[2], &ctx->src[1], i + 1);
8943 alu.last = 1;
8944 alu.is_lds_idx_op = true;
8945 alu.lds_idx = 1;
8946 r = r600_bytecode_add_alu(ctx->bc, &alu);
8947 if (r)
8948 return r;
8949 i += 1;
8950 continue;
8951 }
8952 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8953 alu.op = LDS_OP2_LDS_WRITE;
8954
8955 alu.src[0].sel = temp_reg;
8956 alu.src[0].chan = i;
8957 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8958
8959 alu.last = 1;
8960 alu.is_lds_idx_op = true;
8961
8962 r = r600_bytecode_add_alu(ctx->bc, &alu);
8963 if (r)
8964 return r;
8965 }
8966 return 0;
8967 }
8968
8969 static int tgsi_store(struct r600_shader_ctx *ctx)
8970 {
8971 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8972 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
8973 return tgsi_store_buffer_rat(ctx);
8974 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
8975 return tgsi_store_lds(ctx);
8976 else
8977 return tgsi_store_rat(ctx);
8978 }
8979
8980 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
8981 {
8982 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8983 /* have to work out the offset into the RAT immediate return buffer */
8984 struct r600_bytecode_alu alu;
8985 struct r600_bytecode_vtx vtx;
8986 struct r600_bytecode_cf *cf;
8987 int r;
8988 int idx_gpr;
8989 unsigned format, num_format, format_comp, endian;
8990 const struct util_format_description *desc;
8991 unsigned rat_index_mode;
8992 unsigned immed_base;
8993 unsigned rat_base;
8994
8995 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8996 rat_base = ctx->shader->rat_base;
8997
8998 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
8999 immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
9000 rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
9001
9002 r = load_buffer_coord(ctx, 1, ctx->temp_reg);
9003 if (r)
9004 return r;
9005 idx_gpr = ctx->temp_reg;
9006 } else {
9007 r = load_index_src(ctx, 1, &idx_gpr);
9008 if (r)
9009 return r;
9010 }
9011
9012 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
9013
9014 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
9015 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9016 alu.op = ALU_OP1_MOV;
9017 alu.dst.sel = ctx->thread_id_gpr;
9018 alu.dst.chan = 0;
9019 alu.dst.write = 1;
9020 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
9021 alu.last = 1;
9022 r = r600_bytecode_add_alu(ctx->bc, &alu);
9023 if (r)
9024 return r;
9025
9026 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9027 alu.op = ALU_OP1_MOV;
9028 alu.dst.sel = ctx->thread_id_gpr;
9029 if (ctx->bc->chip_class == CAYMAN)
9030 alu.dst.chan = 2;
9031 else
9032 alu.dst.chan = 3;
9033 alu.dst.write = 1;
9034 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
9035 alu.last = 1;
9036 r = r600_bytecode_add_alu(ctx->bc, &alu);
9037 if (r)
9038 return r;
9039 } else {
9040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9041 alu.op = ALU_OP1_MOV;
9042 alu.dst.sel = ctx->thread_id_gpr;
9043 alu.dst.chan = 0;
9044 alu.dst.write = 1;
9045 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
9046 alu.last = 1;
9047 r = r600_bytecode_add_alu(ctx->bc, &alu);
9048 if (r)
9049 return r;
9050 }
9051
9052 if (rat_index_mode)
9053 egcm_load_index_reg(ctx->bc, 1, false);
9054 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
9055 cf = ctx->bc->cf_last;
9056
9057 cf->rat.id = rat_base + inst->Src[0].Register.Index;
9058 cf->rat.inst = ctx->inst_info->op;
9059 cf->rat.index_mode = rat_index_mode;
9060 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
9061 cf->output.gpr = ctx->thread_id_gpr;
9062 cf->output.index_gpr = idx_gpr;
9063 cf->output.comp_mask = 0xf;
9064 cf->output.burst_count = 1;
9065 cf->vpm = 1;
9066 cf->barrier = 1;
9067 cf->mark = 1;
9068 cf->output.elem_size = 0;
9069 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
9070 cf = ctx->bc->cf_last;
9071 cf->barrier = 1;
9072 cf->cf_addr = 1;
9073
9074 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
9075 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
9076 desc = util_format_description(inst->Memory.Format);
9077 r600_vertex_data_type(inst->Memory.Format,
9078 &format, &num_format, &format_comp, &endian);
9079 vtx.dst_sel_x = desc->swizzle[0];
9080 } else {
9081 format = FMT_32;
9082 num_format = 1;
9083 format_comp = 0;
9084 endian = 0;
9085 vtx.dst_sel_x = 0;
9086 }
9087 vtx.op = FETCH_OP_VFETCH;
9088 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
9089 vtx.buffer_index_mode = rat_index_mode;
9090 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
9091 vtx.src_gpr = ctx->thread_id_gpr;
9092 vtx.src_sel_x = 1;
9093 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9094 vtx.dst_sel_y = 7;
9095 vtx.dst_sel_z = 7;
9096 vtx.dst_sel_w = 7;
9097 vtx.use_const_fields = 0;
9098 vtx.srf_mode_all = 1;
9099 vtx.data_format = format;
9100 vtx.num_format_all = num_format;
9101 vtx.format_comp_all = format_comp;
9102 vtx.endian = endian;
9103 vtx.offset = 0;
9104 vtx.mega_fetch_count = 0xf;
9105 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
9106 if (r)
9107 return r;
9108 cf = ctx->bc->cf_last;
9109 cf->vpm = 1;
9110 cf->barrier = 1;
9111 return 0;
9112 }
9113
9114 static int get_gds_op(int opcode)
9115 {
9116 switch (opcode) {
9117 case TGSI_OPCODE_ATOMUADD:
9118 return FETCH_OP_GDS_ADD_RET;
9119 case TGSI_OPCODE_ATOMAND:
9120 return FETCH_OP_GDS_AND_RET;
9121 case TGSI_OPCODE_ATOMOR:
9122 return FETCH_OP_GDS_OR_RET;
9123 case TGSI_OPCODE_ATOMXOR:
9124 return FETCH_OP_GDS_XOR_RET;
9125 case TGSI_OPCODE_ATOMUMIN:
9126 return FETCH_OP_GDS_MIN_UINT_RET;
9127 case TGSI_OPCODE_ATOMUMAX:
9128 return FETCH_OP_GDS_MAX_UINT_RET;
9129 case TGSI_OPCODE_ATOMXCHG:
9130 return FETCH_OP_GDS_XCHG_RET;
9131 case TGSI_OPCODE_ATOMCAS:
9132 return FETCH_OP_GDS_CMP_XCHG_RET;
9133 default:
9134 return -1;
9135 }
9136 }
9137
9138 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
9139 {
9140 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9141 struct r600_bytecode_gds gds;
9142 struct r600_bytecode_alu alu;
9143 int gds_op = get_gds_op(inst->Instruction.Opcode);
9144 int r;
9145 int uav_id = 0;
9146 int uav_index_mode = 0;
9147 bool is_cm = (ctx->bc->chip_class == CAYMAN);
9148
9149 if (gds_op == -1) {
9150 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
9151 return -1;
9152 }
9153
9154 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
9155 if (r)
9156 return r;
9157
9158 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET) {
9159 if (inst->Src[3].Register.File == TGSI_FILE_IMMEDIATE) {
9160 int value = (ctx->literals[4 * inst->Src[3].Register.Index + inst->Src[3].Register.SwizzleX]);
9161 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9162 alu.op = ALU_OP1_MOV;
9163 alu.dst.sel = ctx->temp_reg;
9164 alu.dst.chan = is_cm ? 2 : 1;
9165 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
9166 alu.src[0].value = value;
9167 alu.last = 1;
9168 alu.dst.write = 1;
9169 r = r600_bytecode_add_alu(ctx->bc, &alu);
9170 if (r)
9171 return r;
9172 } else {
9173 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9174 alu.op = ALU_OP1_MOV;
9175 alu.dst.sel = ctx->temp_reg;
9176 alu.dst.chan = is_cm ? 2 : 1;
9177 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
9178 alu.last = 1;
9179 alu.dst.write = 1;
9180 r = r600_bytecode_add_alu(ctx->bc, &alu);
9181 if (r)
9182 return r;
9183 }
9184 }
9185 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
9186 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
9187 int abs_value = abs(value);
9188 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
9189 gds_op = FETCH_OP_GDS_SUB_RET;
9190 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9191 alu.op = ALU_OP1_MOV;
9192 alu.dst.sel = ctx->temp_reg;
9193 alu.dst.chan = is_cm ? 1 : 0;
9194 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
9195 alu.src[0].value = abs_value;
9196 alu.last = 1;
9197 alu.dst.write = 1;
9198 r = r600_bytecode_add_alu(ctx->bc, &alu);
9199 if (r)
9200 return r;
9201 } else {
9202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9203 alu.op = ALU_OP1_MOV;
9204 alu.dst.sel = ctx->temp_reg;
9205 alu.dst.chan = is_cm ? 1 : 0;
9206 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
9207 alu.last = 1;
9208 alu.dst.write = 1;
9209 r = r600_bytecode_add_alu(ctx->bc, &alu);
9210 if (r)
9211 return r;
9212 }
9213
9214
9215 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
9216 gds.op = gds_op;
9217 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9218 gds.uav_id = is_cm ? 0 : uav_id;
9219 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
9220 gds.src_gpr = ctx->temp_reg;
9221 gds.src_gpr2 = 0;
9222 gds.src_sel_x = is_cm ? 0 : 4;
9223 gds.src_sel_y = is_cm ? 1 : 0;
9224 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET)
9225 gds.src_sel_z = is_cm ? 2 : 1;
9226 else
9227 gds.src_sel_z = 7;
9228 gds.dst_sel_x = 0;
9229 gds.dst_sel_y = 7;
9230 gds.dst_sel_z = 7;
9231 gds.dst_sel_w = 7;
9232 gds.alloc_consume = !is_cm;
9233
9234 r = r600_bytecode_add_gds(ctx->bc, &gds);
9235 if (r)
9236 return r;
9237 ctx->bc->cf_last->vpm = 1;
9238 return 0;
9239 }
9240
9241 static int get_lds_op(int opcode)
9242 {
9243 switch (opcode) {
9244 case TGSI_OPCODE_ATOMUADD:
9245 return LDS_OP2_LDS_ADD_RET;
9246 case TGSI_OPCODE_ATOMAND:
9247 return LDS_OP2_LDS_AND_RET;
9248 case TGSI_OPCODE_ATOMOR:
9249 return LDS_OP2_LDS_OR_RET;
9250 case TGSI_OPCODE_ATOMXOR:
9251 return LDS_OP2_LDS_XOR_RET;
9252 case TGSI_OPCODE_ATOMUMIN:
9253 return LDS_OP2_LDS_MIN_UINT_RET;
9254 case TGSI_OPCODE_ATOMUMAX:
9255 return LDS_OP2_LDS_MAX_UINT_RET;
9256 case TGSI_OPCODE_ATOMIMIN:
9257 return LDS_OP2_LDS_MIN_INT_RET;
9258 case TGSI_OPCODE_ATOMIMAX:
9259 return LDS_OP2_LDS_MAX_INT_RET;
9260 case TGSI_OPCODE_ATOMXCHG:
9261 return LDS_OP2_LDS_XCHG_RET;
9262 case TGSI_OPCODE_ATOMCAS:
9263 return LDS_OP3_LDS_CMP_XCHG_RET;
9264 default:
9265 return -1;
9266 }
9267 }
9268
9269 static int tgsi_atomic_op_lds(struct r600_shader_ctx *ctx)
9270 {
9271 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9272 int lds_op = get_lds_op(inst->Instruction.Opcode);
9273 int r;
9274
9275 struct r600_bytecode_alu alu;
9276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9277 alu.op = lds_op;
9278 alu.is_lds_idx_op = true;
9279 alu.last = 1;
9280 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
9281 r600_bytecode_src(&alu.src[1], &ctx->src[2], 0);
9282 if (lds_op == LDS_OP3_LDS_CMP_XCHG_RET)
9283 r600_bytecode_src(&alu.src[2], &ctx->src[3], 0);
9284 else
9285 alu.src[2].sel = V_SQ_ALU_SRC_0;
9286 r = r600_bytecode_add_alu(ctx->bc, &alu);
9287 if (r)
9288 return r;
9289
9290 /* then read from LDS_OQ_A_POP */
9291 memset(&alu, 0, sizeof(alu));
9292
9293 alu.op = ALU_OP1_MOV;
9294 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
9295 alu.src[0].chan = 0;
9296 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
9297 alu.dst.write = 1;
9298 alu.last = 1;
9299 r = r600_bytecode_add_alu(ctx->bc, &alu);
9300 if (r)
9301 return r;
9302
9303 return 0;
9304 }
9305
9306 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
9307 {
9308 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9309 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
9310 return tgsi_atomic_op_rat(ctx);
9311 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
9312 return tgsi_atomic_op_gds(ctx);
9313 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
9314 return tgsi_atomic_op_rat(ctx);
9315 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
9316 return tgsi_atomic_op_lds(ctx);
9317 return 0;
9318 }
9319
9320 static int tgsi_resq(struct r600_shader_ctx *ctx)
9321 {
9322 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9323 unsigned sampler_index_mode;
9324 struct r600_bytecode_tex tex;
9325 int r;
9326 boolean has_txq_cube_array_z = false;
9327
9328 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
9329 (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
9330 if (ctx->bc->chip_class < EVERGREEN)
9331 ctx->shader->uses_tex_buffers = true;
9332 unsigned eg_buffer_base = 0;
9333 eg_buffer_base = R600_IMAGE_REAL_RESOURCE_OFFSET;
9334 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
9335 eg_buffer_base += ctx->info.file_count[TGSI_FILE_IMAGE];
9336 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset, eg_buffer_base);
9337 }
9338
9339 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
9340 inst->Dst[0].Register.WriteMask & 4) {
9341 ctx->shader->has_txq_cube_array_z_comp = true;
9342 has_txq_cube_array_z = true;
9343 }
9344
9345 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
9346 if (sampler_index_mode)
9347 egcm_load_index_reg(ctx->bc, 1, false);
9348
9349
9350 /* does this shader want a num layers from TXQ for a cube array? */
9351 if (has_txq_cube_array_z) {
9352 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
9353 struct r600_bytecode_alu alu;
9354
9355 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9356 alu.op = ALU_OP1_MOV;
9357
9358 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
9359 /* with eg each dword is either number of cubes */
9360 alu.src[0].sel += id / 4;
9361 alu.src[0].chan = id % 4;
9362 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
9363 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
9364 alu.last = 1;
9365 r = r600_bytecode_add_alu(ctx->bc, &alu);
9366 if (r)
9367 return r;
9368 /* disable writemask from texture instruction */
9369 inst->Dst[0].Register.WriteMask &= ~4;
9370 }
9371 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
9372 tex.op = ctx->inst_info->op;
9373 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
9374 tex.sampler_index_mode = sampler_index_mode;
9375 tex.resource_id = tex.sampler_id;
9376 tex.resource_index_mode = sampler_index_mode;
9377 tex.src_sel_x = 4;
9378 tex.src_sel_y = 4;
9379 tex.src_sel_z = 4;
9380 tex.src_sel_w = 4;
9381 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
9382 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
9383 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
9384 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
9385 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9386 r = r600_bytecode_add_tex(ctx->bc, &tex);
9387 if (r)
9388 return r;
9389
9390 return 0;
9391 }
9392
9393 static int tgsi_lrp(struct r600_shader_ctx *ctx)
9394 {
9395 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9396 struct r600_bytecode_alu alu;
9397 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9398 struct r600_bytecode_alu_src srcs[2][4];
9399 unsigned i;
9400 int r;
9401
9402 /* optimize if it's just an equal balance */
9403 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
9404 for (i = 0; i < lasti + 1; i++) {
9405 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9406 continue;
9407
9408 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9409 alu.op = ALU_OP2_ADD;
9410 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
9411 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9412 alu.omod = 3;
9413 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9414 alu.dst.chan = i;
9415 if (i == lasti) {
9416 alu.last = 1;
9417 }
9418 r = r600_bytecode_add_alu(ctx->bc, &alu);
9419 if (r)
9420 return r;
9421 }
9422 return 0;
9423 }
9424
9425 /* 1 - src0 */
9426 for (i = 0; i < lasti + 1; i++) {
9427 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9428 continue;
9429
9430 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9431 alu.op = ALU_OP2_ADD;
9432 alu.src[0].sel = V_SQ_ALU_SRC_1;
9433 alu.src[0].chan = 0;
9434 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
9435 r600_bytecode_src_toggle_neg(&alu.src[1]);
9436 alu.dst.sel = ctx->temp_reg;
9437 alu.dst.chan = i;
9438 if (i == lasti) {
9439 alu.last = 1;
9440 }
9441 alu.dst.write = 1;
9442 r = r600_bytecode_add_alu(ctx->bc, &alu);
9443 if (r)
9444 return r;
9445 }
9446
9447 /* (1 - src0) * src2 */
9448 for (i = 0; i < lasti + 1; i++) {
9449 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9450 continue;
9451
9452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9453 alu.op = ALU_OP2_MUL;
9454 alu.src[0].sel = ctx->temp_reg;
9455 alu.src[0].chan = i;
9456 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9457 alu.dst.sel = ctx->temp_reg;
9458 alu.dst.chan = i;
9459 if (i == lasti) {
9460 alu.last = 1;
9461 }
9462 alu.dst.write = 1;
9463 r = r600_bytecode_add_alu(ctx->bc, &alu);
9464 if (r)
9465 return r;
9466 }
9467
9468 /* src0 * src1 + (1 - src0) * src2 */
9469
9470 for (i = 0; i < 2; i++) {
9471 r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
9472 srcs[i], &ctx->src[i]);
9473 if (r)
9474 return r;
9475 }
9476
9477 for (i = 0; i < lasti + 1; i++) {
9478 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9479 continue;
9480
9481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9482 alu.op = ALU_OP3_MULADD;
9483 alu.is_op3 = 1;
9484 alu.src[0] = srcs[0][i];
9485 alu.src[1] = srcs[1][i];
9486 alu.src[2].sel = ctx->temp_reg;
9487 alu.src[2].chan = i;
9488
9489 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9490 alu.dst.chan = i;
9491 if (i == lasti) {
9492 alu.last = 1;
9493 }
9494 r = r600_bytecode_add_alu(ctx->bc, &alu);
9495 if (r)
9496 return r;
9497 }
9498 return 0;
9499 }
9500
9501 static int tgsi_cmp(struct r600_shader_ctx *ctx)
9502 {
9503 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9504 struct r600_bytecode_alu alu;
9505 int i, r, j;
9506 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9507 struct r600_bytecode_alu_src srcs[3][4];
9508
9509 unsigned op;
9510
9511 if (ctx->src[0].abs && ctx->src[0].neg) {
9512 op = ALU_OP3_CNDE;
9513 ctx->src[0].abs = 0;
9514 ctx->src[0].neg = 0;
9515 } else {
9516 op = ALU_OP3_CNDGE;
9517 }
9518
9519 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
9520 r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
9521 srcs[j], &ctx->src[j]);
9522 if (r)
9523 return r;
9524 }
9525
9526 for (i = 0; i < lasti + 1; i++) {
9527 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9528 continue;
9529
9530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9531 alu.op = op;
9532 alu.src[0] = srcs[0][i];
9533 alu.src[1] = srcs[2][i];
9534 alu.src[2] = srcs[1][i];
9535
9536 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9537 alu.dst.chan = i;
9538 alu.dst.write = 1;
9539 alu.is_op3 = 1;
9540 if (i == lasti)
9541 alu.last = 1;
9542 r = r600_bytecode_add_alu(ctx->bc, &alu);
9543 if (r)
9544 return r;
9545 }
9546 return 0;
9547 }
9548
9549 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
9550 {
9551 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9552 struct r600_bytecode_alu alu;
9553 int i, r;
9554 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9555
9556 for (i = 0; i < lasti + 1; i++) {
9557 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9558 continue;
9559
9560 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9561 alu.op = ALU_OP3_CNDE_INT;
9562 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9563 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9564 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
9565 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9566 alu.dst.chan = i;
9567 alu.dst.write = 1;
9568 alu.is_op3 = 1;
9569 if (i == lasti)
9570 alu.last = 1;
9571 r = r600_bytecode_add_alu(ctx->bc, &alu);
9572 if (r)
9573 return r;
9574 }
9575 return 0;
9576 }
9577
9578 static int tgsi_exp(struct r600_shader_ctx *ctx)
9579 {
9580 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9581 struct r600_bytecode_alu alu;
9582 int r;
9583 unsigned i;
9584
9585 /* result.x = 2^floor(src); */
9586 if (inst->Dst[0].Register.WriteMask & 1) {
9587 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9588
9589 alu.op = ALU_OP1_FLOOR;
9590 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9591
9592 alu.dst.sel = ctx->temp_reg;
9593 alu.dst.chan = 0;
9594 alu.dst.write = 1;
9595 alu.last = 1;
9596 r = r600_bytecode_add_alu(ctx->bc, &alu);
9597 if (r)
9598 return r;
9599
9600 if (ctx->bc->chip_class == CAYMAN) {
9601 for (i = 0; i < 3; i++) {
9602 alu.op = ALU_OP1_EXP_IEEE;
9603 alu.src[0].sel = ctx->temp_reg;
9604 alu.src[0].chan = 0;
9605
9606 alu.dst.sel = ctx->temp_reg;
9607 alu.dst.chan = i;
9608 alu.dst.write = i == 0;
9609 alu.last = i == 2;
9610 r = r600_bytecode_add_alu(ctx->bc, &alu);
9611 if (r)
9612 return r;
9613 }
9614 } else {
9615 alu.op = ALU_OP1_EXP_IEEE;
9616 alu.src[0].sel = ctx->temp_reg;
9617 alu.src[0].chan = 0;
9618
9619 alu.dst.sel = ctx->temp_reg;
9620 alu.dst.chan = 0;
9621 alu.dst.write = 1;
9622 alu.last = 1;
9623 r = r600_bytecode_add_alu(ctx->bc, &alu);
9624 if (r)
9625 return r;
9626 }
9627 }
9628
9629 /* result.y = tmp - floor(tmp); */
9630 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9632
9633 alu.op = ALU_OP1_FRACT;
9634 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9635
9636 alu.dst.sel = ctx->temp_reg;
9637 #if 0
9638 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9639 if (r)
9640 return r;
9641 #endif
9642 alu.dst.write = 1;
9643 alu.dst.chan = 1;
9644
9645 alu.last = 1;
9646
9647 r = r600_bytecode_add_alu(ctx->bc, &alu);
9648 if (r)
9649 return r;
9650 }
9651
9652 /* result.z = RoughApprox2ToX(tmp);*/
9653 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
9654 if (ctx->bc->chip_class == CAYMAN) {
9655 for (i = 0; i < 3; i++) {
9656 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9657 alu.op = ALU_OP1_EXP_IEEE;
9658 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9659
9660 alu.dst.sel = ctx->temp_reg;
9661 alu.dst.chan = i;
9662 if (i == 2) {
9663 alu.dst.write = 1;
9664 alu.last = 1;
9665 }
9666
9667 r = r600_bytecode_add_alu(ctx->bc, &alu);
9668 if (r)
9669 return r;
9670 }
9671 } else {
9672 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9673 alu.op = ALU_OP1_EXP_IEEE;
9674 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9675
9676 alu.dst.sel = ctx->temp_reg;
9677 alu.dst.write = 1;
9678 alu.dst.chan = 2;
9679
9680 alu.last = 1;
9681
9682 r = r600_bytecode_add_alu(ctx->bc, &alu);
9683 if (r)
9684 return r;
9685 }
9686 }
9687
9688 /* result.w = 1.0;*/
9689 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
9690 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9691
9692 alu.op = ALU_OP1_MOV;
9693 alu.src[0].sel = V_SQ_ALU_SRC_1;
9694 alu.src[0].chan = 0;
9695
9696 alu.dst.sel = ctx->temp_reg;
9697 alu.dst.chan = 3;
9698 alu.dst.write = 1;
9699 alu.last = 1;
9700 r = r600_bytecode_add_alu(ctx->bc, &alu);
9701 if (r)
9702 return r;
9703 }
9704 return tgsi_helper_copy(ctx, inst);
9705 }
9706
9707 static int tgsi_log(struct r600_shader_ctx *ctx)
9708 {
9709 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9710 struct r600_bytecode_alu alu;
9711 int r;
9712 unsigned i;
9713
9714 /* result.x = floor(log2(|src|)); */
9715 if (inst->Dst[0].Register.WriteMask & 1) {
9716 if (ctx->bc->chip_class == CAYMAN) {
9717 for (i = 0; i < 3; i++) {
9718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9719
9720 alu.op = ALU_OP1_LOG_IEEE;
9721 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9722 r600_bytecode_src_set_abs(&alu.src[0]);
9723
9724 alu.dst.sel = ctx->temp_reg;
9725 alu.dst.chan = i;
9726 if (i == 0)
9727 alu.dst.write = 1;
9728 if (i == 2)
9729 alu.last = 1;
9730 r = r600_bytecode_add_alu(ctx->bc, &alu);
9731 if (r)
9732 return r;
9733 }
9734
9735 } else {
9736 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9737
9738 alu.op = ALU_OP1_LOG_IEEE;
9739 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9740 r600_bytecode_src_set_abs(&alu.src[0]);
9741
9742 alu.dst.sel = ctx->temp_reg;
9743 alu.dst.chan = 0;
9744 alu.dst.write = 1;
9745 alu.last = 1;
9746 r = r600_bytecode_add_alu(ctx->bc, &alu);
9747 if (r)
9748 return r;
9749 }
9750
9751 alu.op = ALU_OP1_FLOOR;
9752 alu.src[0].sel = ctx->temp_reg;
9753 alu.src[0].chan = 0;
9754
9755 alu.dst.sel = ctx->temp_reg;
9756 alu.dst.chan = 0;
9757 alu.dst.write = 1;
9758 alu.last = 1;
9759
9760 r = r600_bytecode_add_alu(ctx->bc, &alu);
9761 if (r)
9762 return r;
9763 }
9764
9765 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
9766 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9767
9768 if (ctx->bc->chip_class == CAYMAN) {
9769 for (i = 0; i < 3; i++) {
9770 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9771
9772 alu.op = ALU_OP1_LOG_IEEE;
9773 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9774 r600_bytecode_src_set_abs(&alu.src[0]);
9775
9776 alu.dst.sel = ctx->temp_reg;
9777 alu.dst.chan = i;
9778 if (i == 1)
9779 alu.dst.write = 1;
9780 if (i == 2)
9781 alu.last = 1;
9782
9783 r = r600_bytecode_add_alu(ctx->bc, &alu);
9784 if (r)
9785 return r;
9786 }
9787 } else {
9788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9789
9790 alu.op = ALU_OP1_LOG_IEEE;
9791 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9792 r600_bytecode_src_set_abs(&alu.src[0]);
9793
9794 alu.dst.sel = ctx->temp_reg;
9795 alu.dst.chan = 1;
9796 alu.dst.write = 1;
9797 alu.last = 1;
9798
9799 r = r600_bytecode_add_alu(ctx->bc, &alu);
9800 if (r)
9801 return r;
9802 }
9803
9804 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9805
9806 alu.op = ALU_OP1_FLOOR;
9807 alu.src[0].sel = ctx->temp_reg;
9808 alu.src[0].chan = 1;
9809
9810 alu.dst.sel = ctx->temp_reg;
9811 alu.dst.chan = 1;
9812 alu.dst.write = 1;
9813 alu.last = 1;
9814
9815 r = r600_bytecode_add_alu(ctx->bc, &alu);
9816 if (r)
9817 return r;
9818
9819 if (ctx->bc->chip_class == CAYMAN) {
9820 for (i = 0; i < 3; i++) {
9821 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9822 alu.op = ALU_OP1_EXP_IEEE;
9823 alu.src[0].sel = ctx->temp_reg;
9824 alu.src[0].chan = 1;
9825
9826 alu.dst.sel = ctx->temp_reg;
9827 alu.dst.chan = i;
9828 if (i == 1)
9829 alu.dst.write = 1;
9830 if (i == 2)
9831 alu.last = 1;
9832
9833 r = r600_bytecode_add_alu(ctx->bc, &alu);
9834 if (r)
9835 return r;
9836 }
9837 } else {
9838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9839 alu.op = ALU_OP1_EXP_IEEE;
9840 alu.src[0].sel = ctx->temp_reg;
9841 alu.src[0].chan = 1;
9842
9843 alu.dst.sel = ctx->temp_reg;
9844 alu.dst.chan = 1;
9845 alu.dst.write = 1;
9846 alu.last = 1;
9847
9848 r = r600_bytecode_add_alu(ctx->bc, &alu);
9849 if (r)
9850 return r;
9851 }
9852
9853 if (ctx->bc->chip_class == CAYMAN) {
9854 for (i = 0; i < 3; i++) {
9855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9856 alu.op = ALU_OP1_RECIP_IEEE;
9857 alu.src[0].sel = ctx->temp_reg;
9858 alu.src[0].chan = 1;
9859
9860 alu.dst.sel = ctx->temp_reg;
9861 alu.dst.chan = i;
9862 if (i == 1)
9863 alu.dst.write = 1;
9864 if (i == 2)
9865 alu.last = 1;
9866
9867 r = r600_bytecode_add_alu(ctx->bc, &alu);
9868 if (r)
9869 return r;
9870 }
9871 } else {
9872 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9873 alu.op = ALU_OP1_RECIP_IEEE;
9874 alu.src[0].sel = ctx->temp_reg;
9875 alu.src[0].chan = 1;
9876
9877 alu.dst.sel = ctx->temp_reg;
9878 alu.dst.chan = 1;
9879 alu.dst.write = 1;
9880 alu.last = 1;
9881
9882 r = r600_bytecode_add_alu(ctx->bc, &alu);
9883 if (r)
9884 return r;
9885 }
9886
9887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9888
9889 alu.op = ALU_OP2_MUL;
9890
9891 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9892 r600_bytecode_src_set_abs(&alu.src[0]);
9893
9894 alu.src[1].sel = ctx->temp_reg;
9895 alu.src[1].chan = 1;
9896
9897 alu.dst.sel = ctx->temp_reg;
9898 alu.dst.chan = 1;
9899 alu.dst.write = 1;
9900 alu.last = 1;
9901
9902 r = r600_bytecode_add_alu(ctx->bc, &alu);
9903 if (r)
9904 return r;
9905 }
9906
9907 /* result.z = log2(|src|);*/
9908 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
9909 if (ctx->bc->chip_class == CAYMAN) {
9910 for (i = 0; i < 3; i++) {
9911 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9912
9913 alu.op = ALU_OP1_LOG_IEEE;
9914 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9915 r600_bytecode_src_set_abs(&alu.src[0]);
9916
9917 alu.dst.sel = ctx->temp_reg;
9918 if (i == 2)
9919 alu.dst.write = 1;
9920 alu.dst.chan = i;
9921 if (i == 2)
9922 alu.last = 1;
9923
9924 r = r600_bytecode_add_alu(ctx->bc, &alu);
9925 if (r)
9926 return r;
9927 }
9928 } else {
9929 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9930
9931 alu.op = ALU_OP1_LOG_IEEE;
9932 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9933 r600_bytecode_src_set_abs(&alu.src[0]);
9934
9935 alu.dst.sel = ctx->temp_reg;
9936 alu.dst.write = 1;
9937 alu.dst.chan = 2;
9938 alu.last = 1;
9939
9940 r = r600_bytecode_add_alu(ctx->bc, &alu);
9941 if (r)
9942 return r;
9943 }
9944 }
9945
9946 /* result.w = 1.0; */
9947 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
9948 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9949
9950 alu.op = ALU_OP1_MOV;
9951 alu.src[0].sel = V_SQ_ALU_SRC_1;
9952 alu.src[0].chan = 0;
9953
9954 alu.dst.sel = ctx->temp_reg;
9955 alu.dst.chan = 3;
9956 alu.dst.write = 1;
9957 alu.last = 1;
9958
9959 r = r600_bytecode_add_alu(ctx->bc, &alu);
9960 if (r)
9961 return r;
9962 }
9963
9964 return tgsi_helper_copy(ctx, inst);
9965 }
9966
9967 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
9968 {
9969 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9970 struct r600_bytecode_alu alu;
9971 int r;
9972 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9973 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
9974
9975 assert(inst->Dst[0].Register.Index < 3);
9976 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9977
9978 switch (inst->Instruction.Opcode) {
9979 case TGSI_OPCODE_ARL:
9980 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
9981 break;
9982 case TGSI_OPCODE_ARR:
9983 alu.op = ALU_OP1_FLT_TO_INT;
9984 break;
9985 case TGSI_OPCODE_UARL:
9986 alu.op = ALU_OP1_MOV;
9987 break;
9988 default:
9989 assert(0);
9990 return -1;
9991 }
9992
9993 for (i = 0; i <= lasti; ++i) {
9994 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9995 continue;
9996 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9997 alu.last = i == lasti;
9998 alu.dst.sel = reg;
9999 alu.dst.chan = i;
10000 alu.dst.write = 1;
10001 r = r600_bytecode_add_alu(ctx->bc, &alu);
10002 if (r)
10003 return r;
10004 }
10005
10006 if (inst->Dst[0].Register.Index > 0)
10007 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
10008 else
10009 ctx->bc->ar_loaded = 0;
10010
10011 return 0;
10012 }
10013 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
10014 {
10015 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10016 struct r600_bytecode_alu alu;
10017 int r;
10018 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10019
10020 switch (inst->Instruction.Opcode) {
10021 case TGSI_OPCODE_ARL:
10022 memset(&alu, 0, sizeof(alu));
10023 alu.op = ALU_OP1_FLOOR;
10024 alu.dst.sel = ctx->bc->ar_reg;
10025 alu.dst.write = 1;
10026 for (i = 0; i <= lasti; ++i) {
10027 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10028 alu.dst.chan = i;
10029 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10030 alu.last = i == lasti;
10031 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10032 return r;
10033 }
10034 }
10035
10036 memset(&alu, 0, sizeof(alu));
10037 alu.op = ALU_OP1_FLT_TO_INT;
10038 alu.src[0].sel = ctx->bc->ar_reg;
10039 alu.dst.sel = ctx->bc->ar_reg;
10040 alu.dst.write = 1;
10041 /* FLT_TO_INT is trans-only on r600/r700 */
10042 alu.last = TRUE;
10043 for (i = 0; i <= lasti; ++i) {
10044 alu.dst.chan = i;
10045 alu.src[0].chan = i;
10046 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10047 return r;
10048 }
10049 break;
10050 case TGSI_OPCODE_ARR:
10051 memset(&alu, 0, sizeof(alu));
10052 alu.op = ALU_OP1_FLT_TO_INT;
10053 alu.dst.sel = ctx->bc->ar_reg;
10054 alu.dst.write = 1;
10055 /* FLT_TO_INT is trans-only on r600/r700 */
10056 alu.last = TRUE;
10057 for (i = 0; i <= lasti; ++i) {
10058 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10059 alu.dst.chan = i;
10060 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10061 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10062 return r;
10063 }
10064 }
10065 break;
10066 case TGSI_OPCODE_UARL:
10067 memset(&alu, 0, sizeof(alu));
10068 alu.op = ALU_OP1_MOV;
10069 alu.dst.sel = ctx->bc->ar_reg;
10070 alu.dst.write = 1;
10071 for (i = 0; i <= lasti; ++i) {
10072 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10073 alu.dst.chan = i;
10074 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10075 alu.last = i == lasti;
10076 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10077 return r;
10078 }
10079 }
10080 break;
10081 default:
10082 assert(0);
10083 return -1;
10084 }
10085
10086 ctx->bc->ar_loaded = 0;
10087 return 0;
10088 }
10089
10090 static int tgsi_opdst(struct r600_shader_ctx *ctx)
10091 {
10092 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10093 struct r600_bytecode_alu alu;
10094 int i, r = 0;
10095
10096 for (i = 0; i < 4; i++) {
10097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10098
10099 alu.op = ALU_OP2_MUL;
10100 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10101
10102 if (i == 0 || i == 3) {
10103 alu.src[0].sel = V_SQ_ALU_SRC_1;
10104 } else {
10105 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10106 }
10107
10108 if (i == 0 || i == 2) {
10109 alu.src[1].sel = V_SQ_ALU_SRC_1;
10110 } else {
10111 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
10112 }
10113 if (i == 3)
10114 alu.last = 1;
10115 r = r600_bytecode_add_alu(ctx->bc, &alu);
10116 if (r)
10117 return r;
10118 }
10119 return 0;
10120 }
10121
10122 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type,
10123 struct r600_bytecode_alu_src *src)
10124 {
10125 struct r600_bytecode_alu alu;
10126 int r;
10127
10128 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10129 alu.op = opcode;
10130 alu.execute_mask = 1;
10131 alu.update_pred = 1;
10132
10133 alu.dst.sel = ctx->temp_reg;
10134 alu.dst.write = 1;
10135 alu.dst.chan = 0;
10136
10137 alu.src[0] = *src;
10138 alu.src[1].sel = V_SQ_ALU_SRC_0;
10139 alu.src[1].chan = 0;
10140
10141 alu.last = 1;
10142
10143 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
10144 if (r)
10145 return r;
10146 return 0;
10147 }
10148
10149 static int pops(struct r600_shader_ctx *ctx, int pops)
10150 {
10151 unsigned force_pop = ctx->bc->force_add_cf;
10152
10153 if (!force_pop) {
10154 int alu_pop = 3;
10155 if (ctx->bc->cf_last) {
10156 if (ctx->bc->cf_last->op == CF_OP_ALU)
10157 alu_pop = 0;
10158 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
10159 alu_pop = 1;
10160 }
10161 alu_pop += pops;
10162 if (alu_pop == 1) {
10163 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
10164 ctx->bc->force_add_cf = 1;
10165 } else if (alu_pop == 2) {
10166 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
10167 ctx->bc->force_add_cf = 1;
10168 } else {
10169 force_pop = 1;
10170 }
10171 }
10172
10173 if (force_pop) {
10174 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
10175 ctx->bc->cf_last->pop_count = pops;
10176 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
10177 }
10178
10179 return 0;
10180 }
10181
10182 static inline int callstack_update_max_depth(struct r600_shader_ctx *ctx,
10183 unsigned reason)
10184 {
10185 struct r600_stack_info *stack = &ctx->bc->stack;
10186 unsigned elements;
10187 int entries;
10188
10189 unsigned entry_size = stack->entry_size;
10190
10191 elements = (stack->loop + stack->push_wqm ) * entry_size;
10192 elements += stack->push;
10193
10194 switch (ctx->bc->chip_class) {
10195 case R600:
10196 case R700:
10197 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
10198 * the stack must be reserved to hold the current active/continue
10199 * masks */
10200 if (reason == FC_PUSH_VPM || stack->push > 0) {
10201 elements += 2;
10202 }
10203 break;
10204
10205 case CAYMAN:
10206 /* r9xx: any stack operation on empty stack consumes 2 additional
10207 * elements */
10208 elements += 2;
10209
10210 /* fallthrough */
10211 /* FIXME: do the two elements added above cover the cases for the
10212 * r8xx+ below? */
10213
10214 case EVERGREEN:
10215 /* r8xx+: 2 extra elements are not always required, but one extra
10216 * element must be added for each of the following cases:
10217 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
10218 * stack usage.
10219 * (Currently we don't use ALU_ELSE_AFTER.)
10220 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
10221 * PUSH instruction executed.
10222 *
10223 * NOTE: it seems we also need to reserve additional element in some
10224 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
10225 * then STACK_SIZE should be 2 instead of 1 */
10226 if (reason == FC_PUSH_VPM || stack->push > 0) {
10227 elements += 1;
10228 }
10229 break;
10230
10231 default:
10232 assert(0);
10233 break;
10234 }
10235
10236 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
10237 * for all chips, so we use 4 in the final formula, not the real entry_size
10238 * for the chip */
10239 entry_size = 4;
10240
10241 entries = (elements + (entry_size - 1)) / entry_size;
10242
10243 if (entries > stack->max_entries)
10244 stack->max_entries = entries;
10245 return elements;
10246 }
10247
10248 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
10249 {
10250 switch(reason) {
10251 case FC_PUSH_VPM:
10252 --ctx->bc->stack.push;
10253 assert(ctx->bc->stack.push >= 0);
10254 break;
10255 case FC_PUSH_WQM:
10256 --ctx->bc->stack.push_wqm;
10257 assert(ctx->bc->stack.push_wqm >= 0);
10258 break;
10259 case FC_LOOP:
10260 --ctx->bc->stack.loop;
10261 assert(ctx->bc->stack.loop >= 0);
10262 break;
10263 default:
10264 assert(0);
10265 break;
10266 }
10267 }
10268
10269 static inline int callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
10270 {
10271 switch (reason) {
10272 case FC_PUSH_VPM:
10273 ++ctx->bc->stack.push;
10274 break;
10275 case FC_PUSH_WQM:
10276 ++ctx->bc->stack.push_wqm;
10277 break;
10278 case FC_LOOP:
10279 ++ctx->bc->stack.loop;
10280 break;
10281 default:
10282 assert(0);
10283 }
10284
10285 return callstack_update_max_depth(ctx, reason);
10286 }
10287
10288 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
10289 {
10290 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
10291
10292 sp->mid = realloc((void *)sp->mid,
10293 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
10294 sp->mid[sp->num_mid] = ctx->bc->cf_last;
10295 sp->num_mid++;
10296 }
10297
10298 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
10299 {
10300 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
10301 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
10302 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
10303 ctx->bc->fc_sp++;
10304 }
10305
10306 static void fc_poplevel(struct r600_shader_ctx *ctx)
10307 {
10308 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
10309 free(sp->mid);
10310 sp->mid = NULL;
10311 sp->num_mid = 0;
10312 sp->start = NULL;
10313 sp->type = 0;
10314 ctx->bc->fc_sp--;
10315 }
10316
10317 #if 0
10318 static int emit_return(struct r600_shader_ctx *ctx)
10319 {
10320 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
10321 return 0;
10322 }
10323
10324 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
10325 {
10326
10327 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
10328 ctx->bc->cf_last->pop_count = pops;
10329 /* XXX work out offset */
10330 return 0;
10331 }
10332
10333 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
10334 {
10335 return 0;
10336 }
10337
10338 static void emit_testflag(struct r600_shader_ctx *ctx)
10339 {
10340
10341 }
10342
10343 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
10344 {
10345 emit_testflag(ctx);
10346 emit_jump_to_offset(ctx, 1, 4);
10347 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
10348 pops(ctx, ifidx + 1);
10349 emit_return(ctx);
10350 }
10351
10352 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
10353 {
10354 emit_testflag(ctx);
10355
10356 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10357 ctx->bc->cf_last->pop_count = 1;
10358
10359 fc_set_mid(ctx, fc_sp);
10360
10361 pops(ctx, 1);
10362 }
10363 #endif
10364
10365 static int emit_if(struct r600_shader_ctx *ctx, int opcode,
10366 struct r600_bytecode_alu_src *src)
10367 {
10368 int alu_type = CF_OP_ALU_PUSH_BEFORE;
10369 bool needs_workaround = false;
10370 int elems = callstack_push(ctx, FC_PUSH_VPM);
10371
10372 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1)
10373 needs_workaround = true;
10374
10375 if (ctx->bc->chip_class == EVERGREEN && ctx_needs_stack_workaround_8xx(ctx)) {
10376 unsigned dmod1 = (elems - 1) % ctx->bc->stack.entry_size;
10377 unsigned dmod2 = (elems) % ctx->bc->stack.entry_size;
10378
10379 if (elems && (!dmod1 || !dmod2))
10380 needs_workaround = true;
10381 }
10382
10383 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
10384 * LOOP_STARTxxx for nested loops may put the branch stack into a state
10385 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
10386 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
10387 if (needs_workaround) {
10388 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
10389 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
10390 alu_type = CF_OP_ALU;
10391 }
10392
10393 emit_logic_pred(ctx, opcode, alu_type, src);
10394
10395 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
10396
10397 fc_pushlevel(ctx, FC_IF);
10398
10399 return 0;
10400 }
10401
10402 static int tgsi_if(struct r600_shader_ctx *ctx)
10403 {
10404 struct r600_bytecode_alu_src alu_src;
10405 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
10406
10407 return emit_if(ctx, ALU_OP2_PRED_SETNE, &alu_src);
10408 }
10409
10410 static int tgsi_uif(struct r600_shader_ctx *ctx)
10411 {
10412 struct r600_bytecode_alu_src alu_src;
10413 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
10414 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10415 }
10416
10417 static int tgsi_else(struct r600_shader_ctx *ctx)
10418 {
10419 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
10420 ctx->bc->cf_last->pop_count = 1;
10421
10422 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
10423 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
10424 return 0;
10425 }
10426
10427 static int tgsi_endif(struct r600_shader_ctx *ctx)
10428 {
10429 int offset = 2;
10430 pops(ctx, 1);
10431 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
10432 R600_ERR("if/endif unbalanced in shader\n");
10433 return -1;
10434 }
10435
10436 /* ALU_EXTENDED needs 4 DWords instead of two, adjust jump target offset accordingly */
10437 if (ctx->bc->cf_last->eg_alu_extended)
10438 offset += 2;
10439
10440 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
10441 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + offset;
10442 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
10443 } else {
10444 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + offset;
10445 }
10446 fc_poplevel(ctx);
10447
10448 callstack_pop(ctx, FC_PUSH_VPM);
10449 return 0;
10450 }
10451
10452 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
10453 {
10454 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
10455 * limited to 4096 iterations, like the other LOOP_* instructions. */
10456 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
10457
10458 fc_pushlevel(ctx, FC_LOOP);
10459
10460 /* check stack depth */
10461 callstack_push(ctx, FC_LOOP);
10462 return 0;
10463 }
10464
10465 static int tgsi_endloop(struct r600_shader_ctx *ctx)
10466 {
10467 int i;
10468
10469 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
10470
10471 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
10472 R600_ERR("loop/endloop in shader code are not paired.\n");
10473 return -EINVAL;
10474 }
10475
10476 /* fixup loop pointers - from r600isa
10477 LOOP END points to CF after LOOP START,
10478 LOOP START point to CF after LOOP END
10479 BRK/CONT point to LOOP END CF
10480 */
10481 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
10482
10483 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
10484
10485 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
10486 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
10487 }
10488 /* XXX add LOOPRET support */
10489 fc_poplevel(ctx);
10490 callstack_pop(ctx, FC_LOOP);
10491 return 0;
10492 }
10493
10494 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
10495 {
10496 unsigned int fscp;
10497
10498 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
10499 {
10500 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
10501 break;
10502 }
10503
10504 if (fscp == 0) {
10505 R600_ERR("Break not inside loop/endloop pair\n");
10506 return -EINVAL;
10507 }
10508
10509 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10510
10511 fc_set_mid(ctx, fscp - 1);
10512
10513 return 0;
10514 }
10515
10516 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
10517 {
10518 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10519 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
10520 int r;
10521
10522 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10523 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
10524
10525 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10526 if (!r) {
10527 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
10528 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10529 return emit_inc_ring_offset(ctx, stream, TRUE);
10530 }
10531 return r;
10532 }
10533
10534 static int tgsi_umad(struct r600_shader_ctx *ctx)
10535 {
10536 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10537 struct r600_bytecode_alu alu;
10538 int i, j, r;
10539 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10540
10541 /* src0 * src1 */
10542 for (i = 0; i < lasti + 1; i++) {
10543 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10544 continue;
10545
10546 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10547
10548 alu.dst.chan = i;
10549 alu.dst.sel = ctx->temp_reg;
10550 alu.dst.write = 1;
10551
10552 alu.op = ALU_OP2_MULLO_UINT;
10553 for (j = 0; j < 2; j++) {
10554 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
10555 }
10556
10557 alu.last = 1;
10558 r = emit_mul_int_op(ctx->bc, &alu);
10559 if (r)
10560 return r;
10561 }
10562
10563
10564 for (i = 0; i < lasti + 1; i++) {
10565 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10566 continue;
10567
10568 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10569 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10570
10571 alu.op = ALU_OP2_ADD_INT;
10572
10573 alu.src[0].sel = ctx->temp_reg;
10574 alu.src[0].chan = i;
10575
10576 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
10577 if (i == lasti) {
10578 alu.last = 1;
10579 }
10580 r = r600_bytecode_add_alu(ctx->bc, &alu);
10581 if (r)
10582 return r;
10583 }
10584 return 0;
10585 }
10586
10587 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
10588 {
10589 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10590 struct r600_bytecode_alu alu;
10591 int r, i;
10592 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10593
10594 /* temp.xy = f32_to_f16(src) */
10595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10596 alu.op = ALU_OP1_FLT32_TO_FLT16;
10597 alu.dst.chan = 0;
10598 alu.dst.sel = ctx->temp_reg;
10599 alu.dst.write = 1;
10600 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10601 r = r600_bytecode_add_alu(ctx->bc, &alu);
10602 if (r)
10603 return r;
10604 alu.dst.chan = 1;
10605 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10606 alu.last = 1;
10607 r = r600_bytecode_add_alu(ctx->bc, &alu);
10608 if (r)
10609 return r;
10610
10611 /* dst.x = temp.y * 0x10000 + temp.x */
10612 for (i = 0; i < lasti + 1; i++) {
10613 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10614 continue;
10615
10616 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10617 alu.op = ALU_OP3_MULADD_UINT24;
10618 alu.is_op3 = 1;
10619 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10620 alu.last = i == lasti;
10621 alu.src[0].sel = ctx->temp_reg;
10622 alu.src[0].chan = 1;
10623 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10624 alu.src[1].value = 0x10000;
10625 alu.src[2].sel = ctx->temp_reg;
10626 alu.src[2].chan = 0;
10627 r = r600_bytecode_add_alu(ctx->bc, &alu);
10628 if (r)
10629 return r;
10630 }
10631
10632 return 0;
10633 }
10634
10635 static int tgsi_up2h(struct r600_shader_ctx *ctx)
10636 {
10637 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10638 struct r600_bytecode_alu alu;
10639 int r, i;
10640 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10641
10642 /* temp.x = src.x */
10643 /* note: no need to mask out the high bits */
10644 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10645 alu.op = ALU_OP1_MOV;
10646 alu.dst.chan = 0;
10647 alu.dst.sel = ctx->temp_reg;
10648 alu.dst.write = 1;
10649 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10650 r = r600_bytecode_add_alu(ctx->bc, &alu);
10651 if (r)
10652 return r;
10653
10654 /* temp.y = src.x >> 16 */
10655 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10656 alu.op = ALU_OP2_LSHR_INT;
10657 alu.dst.chan = 1;
10658 alu.dst.sel = ctx->temp_reg;
10659 alu.dst.write = 1;
10660 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10661 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10662 alu.src[1].value = 16;
10663 alu.last = 1;
10664 r = r600_bytecode_add_alu(ctx->bc, &alu);
10665 if (r)
10666 return r;
10667
10668 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
10669 for (i = 0; i < lasti + 1; i++) {
10670 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10671 continue;
10672 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10673 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10674 alu.op = ALU_OP1_FLT16_TO_FLT32;
10675 alu.src[0].sel = ctx->temp_reg;
10676 alu.src[0].chan = i % 2;
10677 alu.last = i == lasti;
10678 r = r600_bytecode_add_alu(ctx->bc, &alu);
10679 if (r)
10680 return r;
10681 }
10682
10683 return 0;
10684 }
10685
10686 static int tgsi_bfe(struct r600_shader_ctx *ctx)
10687 {
10688 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10689 struct r600_bytecode_alu alu;
10690 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10691 int r, i;
10692 int dst = -1;
10693
10694 if ((inst->Src[0].Register.File == inst->Dst[0].Register.File &&
10695 inst->Src[0].Register.Index == inst->Dst[0].Register.Index) ||
10696 (inst->Src[2].Register.File == inst->Dst[0].Register.File &&
10697 inst->Src[2].Register.Index == inst->Dst[0].Register.Index))
10698 dst = r600_get_temp(ctx);
10699
10700 r = tgsi_op3_dst(ctx, dst);
10701 if (r)
10702 return r;
10703
10704 for (i = 0; i < lasti + 1; i++) {
10705 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10706 alu.op = ALU_OP2_SETGE_INT;
10707 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
10708 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10709 alu.src[1].value = 32;
10710 alu.dst.sel = ctx->temp_reg;
10711 alu.dst.chan = i;
10712 alu.dst.write = 1;
10713 if (i == lasti)
10714 alu.last = 1;
10715 r = r600_bytecode_add_alu(ctx->bc, &alu);
10716 if (r)
10717 return r;
10718 }
10719
10720 for (i = 0; i < lasti + 1; i++) {
10721 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10722 alu.op = ALU_OP3_CNDE_INT;
10723 alu.is_op3 = 1;
10724 alu.src[0].sel = ctx->temp_reg;
10725 alu.src[0].chan = i;
10726
10727 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10728 if (dst != -1)
10729 alu.src[1].sel = dst;
10730 else
10731 alu.src[1].sel = alu.dst.sel;
10732 alu.src[1].chan = i;
10733 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
10734 alu.dst.write = 1;
10735 if (i == lasti)
10736 alu.last = 1;
10737 r = r600_bytecode_add_alu(ctx->bc, &alu);
10738 if (r)
10739 return r;
10740 }
10741
10742 return 0;
10743 }
10744
10745 static int tgsi_clock(struct r600_shader_ctx *ctx)
10746 {
10747 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10748 struct r600_bytecode_alu alu;
10749 int r;
10750
10751 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10752 alu.op = ALU_OP1_MOV;
10753 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10754 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_LO;
10755 r = r600_bytecode_add_alu(ctx->bc, &alu);
10756 if (r)
10757 return r;
10758 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10759 alu.op = ALU_OP1_MOV;
10760 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10761 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
10762 alu.last = 1;
10763 r = r600_bytecode_add_alu(ctx->bc, &alu);
10764 if (r)
10765 return r;
10766 return 0;
10767 }
10768
10769 static int emit_u64add(struct r600_shader_ctx *ctx, int op,
10770 int treg,
10771 int src0_sel, int src0_chan,
10772 int src1_sel, int src1_chan)
10773 {
10774 struct r600_bytecode_alu alu;
10775 int r;
10776 int opc;
10777
10778 if (op == ALU_OP2_ADD_INT)
10779 opc = ALU_OP2_ADDC_UINT;
10780 else
10781 opc = ALU_OP2_SUBB_UINT;
10782
10783 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10784 alu.op = op; ;
10785 alu.dst.sel = treg;
10786 alu.dst.chan = 0;
10787 alu.dst.write = 1;
10788 alu.src[0].sel = src0_sel;
10789 alu.src[0].chan = src0_chan + 0;
10790 alu.src[1].sel = src1_sel;
10791 alu.src[1].chan = src1_chan + 0;
10792 alu.src[1].neg = 0;
10793 r = r600_bytecode_add_alu(ctx->bc, &alu);
10794 if (r)
10795 return r;
10796
10797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10798 alu.op = op;
10799 alu.dst.sel = treg;
10800 alu.dst.chan = 1;
10801 alu.dst.write = 1;
10802 alu.src[0].sel = src0_sel;
10803 alu.src[0].chan = src0_chan + 1;
10804 alu.src[1].sel = src1_sel;
10805 alu.src[1].chan = src1_chan + 1;
10806 alu.src[1].neg = 0;
10807 r = r600_bytecode_add_alu(ctx->bc, &alu);
10808 if (r)
10809 return r;
10810
10811 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10812 alu.op = opc;
10813 alu.dst.sel = treg;
10814 alu.dst.chan = 2;
10815 alu.dst.write = 1;
10816 alu.last = 1;
10817 alu.src[0].sel = src0_sel;
10818 alu.src[0].chan = src0_chan + 0;
10819 alu.src[1].sel = src1_sel;
10820 alu.src[1].chan = src1_chan + 0;
10821 alu.src[1].neg = 0;
10822 r = r600_bytecode_add_alu(ctx->bc, &alu);
10823 if (r)
10824 return r;
10825
10826 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10827 alu.op = op;
10828 alu.dst.sel = treg;
10829 alu.dst.chan = 1;
10830 alu.dst.write = 1;
10831 alu.src[0].sel = treg;
10832 alu.src[0].chan = 1;
10833 alu.src[1].sel = treg;
10834 alu.src[1].chan = 2;
10835 alu.last = 1;
10836 r = r600_bytecode_add_alu(ctx->bc, &alu);
10837 if (r)
10838 return r;
10839 return 0;
10840 }
10841
10842 static int egcm_u64add(struct r600_shader_ctx *ctx)
10843 {
10844 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10845 struct r600_bytecode_alu alu;
10846 int r;
10847 int treg = ctx->temp_reg;
10848 int op = ALU_OP2_ADD_INT, opc = ALU_OP2_ADDC_UINT;
10849
10850 if (ctx->src[1].neg) {
10851 op = ALU_OP2_SUB_INT;
10852 opc = ALU_OP2_SUBB_UINT;
10853 }
10854 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10855 alu.op = op; ;
10856 alu.dst.sel = treg;
10857 alu.dst.chan = 0;
10858 alu.dst.write = 1;
10859 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10860 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10861 alu.src[1].neg = 0;
10862 r = r600_bytecode_add_alu(ctx->bc, &alu);
10863 if (r)
10864 return r;
10865
10866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10867 alu.op = op;
10868 alu.dst.sel = treg;
10869 alu.dst.chan = 1;
10870 alu.dst.write = 1;
10871 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10872 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10873 alu.src[1].neg = 0;
10874 r = r600_bytecode_add_alu(ctx->bc, &alu);
10875 if (r)
10876 return r;
10877
10878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10879 alu.op = opc ;
10880 alu.dst.sel = treg;
10881 alu.dst.chan = 2;
10882 alu.dst.write = 1;
10883 alu.last = 1;
10884 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10885 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10886 alu.src[1].neg = 0;
10887 r = r600_bytecode_add_alu(ctx->bc, &alu);
10888 if (r)
10889 return r;
10890
10891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10892 alu.op = op;
10893 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10894 alu.src[0].sel = treg;
10895 alu.src[0].chan = 1;
10896 alu.src[1].sel = treg;
10897 alu.src[1].chan = 2;
10898 alu.last = 1;
10899 r = r600_bytecode_add_alu(ctx->bc, &alu);
10900 if (r)
10901 return r;
10902 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10903 alu.op = ALU_OP1_MOV;
10904 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10905 alu.src[0].sel = treg;
10906 alu.src[0].chan = 0;
10907 alu.last = 1;
10908 r = r600_bytecode_add_alu(ctx->bc, &alu);
10909 if (r)
10910 return r;
10911 return 0;
10912 }
10913
10914 /* result.y = mul_high a, b
10915 result.x = mul a,b
10916 result.y += a.x * b.y + a.y * b.x;
10917 */
10918 static int egcm_u64mul(struct r600_shader_ctx *ctx)
10919 {
10920 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10921 struct r600_bytecode_alu alu;
10922 int r;
10923 int treg = ctx->temp_reg;
10924
10925 /* temp.x = mul_lo a.x, b.x */
10926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10927 alu.op = ALU_OP2_MULLO_UINT;
10928 alu.dst.sel = treg;
10929 alu.dst.chan = 0;
10930 alu.dst.write = 1;
10931 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10932 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10933 r = emit_mul_int_op(ctx->bc, &alu);
10934 if (r)
10935 return r;
10936
10937 /* temp.y = mul_hi a.x, b.x */
10938 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10939 alu.op = ALU_OP2_MULHI_UINT;
10940 alu.dst.sel = treg;
10941 alu.dst.chan = 1;
10942 alu.dst.write = 1;
10943 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10944 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10945 r = emit_mul_int_op(ctx->bc, &alu);
10946 if (r)
10947 return r;
10948
10949 /* temp.z = mul a.x, b.y */
10950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10951 alu.op = ALU_OP2_MULLO_UINT;
10952 alu.dst.sel = treg;
10953 alu.dst.chan = 2;
10954 alu.dst.write = 1;
10955 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10956 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10957 r = emit_mul_int_op(ctx->bc, &alu);
10958 if (r)
10959 return r;
10960
10961 /* temp.w = mul a.y, b.x */
10962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10963 alu.op = ALU_OP2_MULLO_UINT;
10964 alu.dst.sel = treg;
10965 alu.dst.chan = 3;
10966 alu.dst.write = 1;
10967 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10968 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10969 r = emit_mul_int_op(ctx->bc, &alu);
10970 if (r)
10971 return r;
10972
10973 /* temp.z = temp.z + temp.w */
10974 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10975 alu.op = ALU_OP2_ADD_INT;
10976 alu.dst.sel = treg;
10977 alu.dst.chan = 2;
10978 alu.dst.write = 1;
10979 alu.src[0].sel = treg;
10980 alu.src[0].chan = 2;
10981 alu.src[1].sel = treg;
10982 alu.src[1].chan = 3;
10983 alu.last = 1;
10984 r = r600_bytecode_add_alu(ctx->bc, &alu);
10985 if (r)
10986 return r;
10987
10988 /* temp.y = temp.y + temp.z */
10989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10990 alu.op = ALU_OP2_ADD_INT;
10991 alu.dst.sel = treg;
10992 alu.dst.chan = 1;
10993 alu.dst.write = 1;
10994 alu.src[0].sel = treg;
10995 alu.src[0].chan = 1;
10996 alu.src[1].sel = treg;
10997 alu.src[1].chan = 2;
10998 alu.last = 1;
10999 r = r600_bytecode_add_alu(ctx->bc, &alu);
11000 if (r)
11001 return r;
11002
11003 /* dst.x = temp.x */
11004 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11005 alu.op = ALU_OP1_MOV;
11006 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11007 alu.src[0].sel = treg;
11008 alu.src[0].chan = 0;
11009 r = r600_bytecode_add_alu(ctx->bc, &alu);
11010 if (r)
11011 return r;
11012
11013 /* dst.y = temp.y */
11014 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11015 alu.op = ALU_OP1_MOV;
11016 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11017 alu.src[0].sel = treg;
11018 alu.src[0].chan = 1;
11019 alu.last = 1;
11020 r = r600_bytecode_add_alu(ctx->bc, &alu);
11021 if (r)
11022 return r;
11023
11024 return 0;
11025 }
11026
11027 static int emit_u64sge(struct r600_shader_ctx *ctx,
11028 int treg,
11029 int src0_sel, int src0_base_chan,
11030 int src1_sel, int src1_base_chan)
11031 {
11032 int r;
11033 /* for 64-bit sge */
11034 /* result = (src0.y > src1.y) || ((src0.y == src1.y) && src0.x >= src1.x)) */
11035 r = single_alu_op2(ctx, ALU_OP2_SETGT_UINT,
11036 treg, 1,
11037 src0_sel, src0_base_chan + 1,
11038 src1_sel, src1_base_chan + 1);
11039 if (r)
11040 return r;
11041
11042 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11043 treg, 0,
11044 src0_sel, src0_base_chan,
11045 src1_sel, src1_base_chan);
11046 if (r)
11047 return r;
11048
11049 r = single_alu_op2(ctx, ALU_OP2_SETE_INT,
11050 treg, 2,
11051 src0_sel, src0_base_chan + 1,
11052 src1_sel, src1_base_chan + 1);
11053 if (r)
11054 return r;
11055
11056 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
11057 treg, 0,
11058 treg, 0,
11059 treg, 2);
11060 if (r)
11061 return r;
11062
11063 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11064 treg, 0,
11065 treg, 0,
11066 treg, 1);
11067 if (r)
11068 return r;
11069 return 0;
11070 }
11071
11072 /* this isn't a complete div it's just enough for qbo shader to work */
11073 static int egcm_u64div(struct r600_shader_ctx *ctx)
11074 {
11075 struct r600_bytecode_alu alu;
11076 struct r600_bytecode_alu_src alu_num_hi, alu_num_lo, alu_denom_hi, alu_denom_lo, alu_src;
11077 int r, i;
11078 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11079
11080 /* make sure we are dividing my a const with 0 in the high bits */
11081 if (ctx->src[1].sel != V_SQ_ALU_SRC_LITERAL)
11082 return -1;
11083 if (ctx->src[1].value[ctx->src[1].swizzle[1]] != 0)
11084 return -1;
11085 /* make sure we are doing one division */
11086 if (inst->Dst[0].Register.WriteMask != 0x3)
11087 return -1;
11088
11089 /* emit_if uses ctx->temp_reg so we can't */
11090 int treg = r600_get_temp(ctx);
11091 int tmp_num = r600_get_temp(ctx);
11092 int sub_tmp = r600_get_temp(ctx);
11093
11094 /* tmp quot are tmp_num.zw */
11095 r600_bytecode_src(&alu_num_lo, &ctx->src[0], 0);
11096 r600_bytecode_src(&alu_num_hi, &ctx->src[0], 1);
11097 r600_bytecode_src(&alu_denom_lo, &ctx->src[1], 0);
11098 r600_bytecode_src(&alu_denom_hi, &ctx->src[1], 1);
11099
11100 /* MOV tmp_num.xy, numerator */
11101 r = single_alu_op2(ctx, ALU_OP1_MOV,
11102 tmp_num, 0,
11103 alu_num_lo.sel, alu_num_lo.chan,
11104 0, 0);
11105 if (r)
11106 return r;
11107 r = single_alu_op2(ctx, ALU_OP1_MOV,
11108 tmp_num, 1,
11109 alu_num_hi.sel, alu_num_hi.chan,
11110 0, 0);
11111 if (r)
11112 return r;
11113
11114 r = single_alu_op2(ctx, ALU_OP1_MOV,
11115 tmp_num, 2,
11116 V_SQ_ALU_SRC_LITERAL, 0,
11117 0, 0);
11118 if (r)
11119 return r;
11120
11121 r = single_alu_op2(ctx, ALU_OP1_MOV,
11122 tmp_num, 3,
11123 V_SQ_ALU_SRC_LITERAL, 0,
11124 0, 0);
11125 if (r)
11126 return r;
11127
11128 /* treg 0 is log2_denom */
11129 /* normally this gets the MSB for the denom high value
11130 - however we know this will always be 0 here. */
11131 r = single_alu_op2(ctx,
11132 ALU_OP1_MOV,
11133 treg, 0,
11134 V_SQ_ALU_SRC_LITERAL, 32,
11135 0, 0);
11136 if (r)
11137 return r;
11138
11139 /* normally check demon hi for 0, but we know it is already */
11140 /* t0.z = num_hi >= denom_lo */
11141 r = single_alu_op2(ctx,
11142 ALU_OP2_SETGE_UINT,
11143 treg, 1,
11144 alu_num_hi.sel, alu_num_hi.chan,
11145 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
11146 if (r)
11147 return r;
11148
11149 memset(&alu_src, 0, sizeof(alu_src));
11150 alu_src.sel = treg;
11151 alu_src.chan = 1;
11152 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11153 if (r)
11154 return r;
11155
11156 /* for loops in here */
11157 /* get msb t0.x = msb(src[1].x) first */
11158 int msb_lo = util_last_bit(alu_denom_lo.value);
11159 r = single_alu_op2(ctx, ALU_OP1_MOV,
11160 treg, 0,
11161 V_SQ_ALU_SRC_LITERAL, msb_lo,
11162 0, 0);
11163 if (r)
11164 return r;
11165
11166 /* unroll the asm here */
11167 for (i = 0; i < 31; i++) {
11168 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11169 treg, 2,
11170 V_SQ_ALU_SRC_LITERAL, i,
11171 treg, 0);
11172 if (r)
11173 return r;
11174
11175 /* we can do this on the CPU */
11176 uint32_t denom_lo_shl = alu_denom_lo.value << (31 - i);
11177 /* t0.z = tmp_num.y >= t0.z */
11178 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11179 treg, 1,
11180 tmp_num, 1,
11181 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
11182 if (r)
11183 return r;
11184
11185 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
11186 treg, 1,
11187 treg, 1,
11188 treg, 2);
11189 if (r)
11190 return r;
11191
11192 memset(&alu_src, 0, sizeof(alu_src));
11193 alu_src.sel = treg;
11194 alu_src.chan = 1;
11195 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11196 if (r)
11197 return r;
11198
11199 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
11200 tmp_num, 1,
11201 tmp_num, 1,
11202 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
11203 if (r)
11204 return r;
11205
11206 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11207 tmp_num, 3,
11208 tmp_num, 3,
11209 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
11210 if (r)
11211 return r;
11212
11213 r = tgsi_endif(ctx);
11214 if (r)
11215 return r;
11216 }
11217
11218 /* log2_denom is always <= 31, so manually peel the last loop
11219 * iteration.
11220 */
11221 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11222 treg, 1,
11223 tmp_num, 1,
11224 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
11225 if (r)
11226 return r;
11227
11228 memset(&alu_src, 0, sizeof(alu_src));
11229 alu_src.sel = treg;
11230 alu_src.chan = 1;
11231 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11232 if (r)
11233 return r;
11234
11235 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
11236 tmp_num, 1,
11237 tmp_num, 1,
11238 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
11239 if (r)
11240 return r;
11241
11242 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11243 tmp_num, 3,
11244 tmp_num, 3,
11245 V_SQ_ALU_SRC_LITERAL, 1U);
11246 if (r)
11247 return r;
11248 r = tgsi_endif(ctx);
11249 if (r)
11250 return r;
11251
11252 r = tgsi_endif(ctx);
11253 if (r)
11254 return r;
11255
11256 /* onto the second loop to unroll */
11257 for (i = 0; i < 31; i++) {
11258 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11259 treg, 1,
11260 V_SQ_ALU_SRC_LITERAL, (63 - (31 - i)),
11261 treg, 0);
11262 if (r)
11263 return r;
11264
11265 uint64_t denom_shl = (uint64_t)alu_denom_lo.value << (31 - i);
11266 r = single_alu_op2(ctx, ALU_OP1_MOV,
11267 treg, 2,
11268 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
11269 0, 0);
11270 if (r)
11271 return r;
11272
11273 r = single_alu_op2(ctx, ALU_OP1_MOV,
11274 treg, 3,
11275 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
11276 0, 0);
11277 if (r)
11278 return r;
11279
11280 r = emit_u64sge(ctx, sub_tmp,
11281 tmp_num, 0,
11282 treg, 2);
11283 if (r)
11284 return r;
11285
11286 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
11287 treg, 1,
11288 treg, 1,
11289 sub_tmp, 0);
11290 if (r)
11291 return r;
11292
11293 memset(&alu_src, 0, sizeof(alu_src));
11294 alu_src.sel = treg;
11295 alu_src.chan = 1;
11296 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11297 if (r)
11298 return r;
11299
11300
11301 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
11302 sub_tmp,
11303 tmp_num, 0,
11304 treg, 2);
11305 if (r)
11306 return r;
11307
11308 r = single_alu_op2(ctx, ALU_OP1_MOV,
11309 tmp_num, 0,
11310 sub_tmp, 0,
11311 0, 0);
11312 if (r)
11313 return r;
11314
11315 r = single_alu_op2(ctx, ALU_OP1_MOV,
11316 tmp_num, 1,
11317 sub_tmp, 1,
11318 0, 0);
11319 if (r)
11320 return r;
11321
11322 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11323 tmp_num, 2,
11324 tmp_num, 2,
11325 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
11326 if (r)
11327 return r;
11328
11329 r = tgsi_endif(ctx);
11330 if (r)
11331 return r;
11332 }
11333
11334 /* log2_denom is always <= 63, so manually peel the last loop
11335 * iteration.
11336 */
11337 uint64_t denom_shl = (uint64_t)alu_denom_lo.value;
11338 r = single_alu_op2(ctx, ALU_OP1_MOV,
11339 treg, 2,
11340 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
11341 0, 0);
11342 if (r)
11343 return r;
11344
11345 r = single_alu_op2(ctx, ALU_OP1_MOV,
11346 treg, 3,
11347 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
11348 0, 0);
11349 if (r)
11350 return r;
11351
11352 r = emit_u64sge(ctx, sub_tmp,
11353 tmp_num, 0,
11354 treg, 2);
11355 if (r)
11356 return r;
11357
11358 memset(&alu_src, 0, sizeof(alu_src));
11359 alu_src.sel = sub_tmp;
11360 alu_src.chan = 0;
11361 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11362 if (r)
11363 return r;
11364
11365 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
11366 sub_tmp,
11367 tmp_num, 0,
11368 treg, 2);
11369 if (r)
11370 return r;
11371
11372 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11373 tmp_num, 2,
11374 tmp_num, 2,
11375 V_SQ_ALU_SRC_LITERAL, 1U);
11376 if (r)
11377 return r;
11378 r = tgsi_endif(ctx);
11379 if (r)
11380 return r;
11381
11382 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11383 alu.op = ALU_OP1_MOV;
11384 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11385 alu.src[0].sel = tmp_num;
11386 alu.src[0].chan = 2;
11387 r = r600_bytecode_add_alu(ctx->bc, &alu);
11388 if (r)
11389 return r;
11390
11391 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11392 alu.op = ALU_OP1_MOV;
11393 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11394 alu.src[0].sel = tmp_num;
11395 alu.src[0].chan = 3;
11396 alu.last = 1;
11397 r = r600_bytecode_add_alu(ctx->bc, &alu);
11398 if (r)
11399 return r;
11400 return 0;
11401 }
11402
11403 static int egcm_u64sne(struct r600_shader_ctx *ctx)
11404 {
11405 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11406 struct r600_bytecode_alu alu;
11407 int r;
11408 int treg = ctx->temp_reg;
11409
11410 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11411 alu.op = ALU_OP2_SETNE_INT;
11412 alu.dst.sel = treg;
11413 alu.dst.chan = 0;
11414 alu.dst.write = 1;
11415 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
11416 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
11417 r = r600_bytecode_add_alu(ctx->bc, &alu);
11418 if (r)
11419 return r;
11420
11421 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11422 alu.op = ALU_OP2_SETNE_INT;
11423 alu.dst.sel = treg;
11424 alu.dst.chan = 1;
11425 alu.dst.write = 1;
11426 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
11427 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
11428 alu.last = 1;
11429 r = r600_bytecode_add_alu(ctx->bc, &alu);
11430 if (r)
11431 return r;
11432
11433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11434 alu.op = ALU_OP2_OR_INT;
11435 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11436 alu.src[0].sel = treg;
11437 alu.src[0].chan = 0;
11438 alu.src[1].sel = treg;
11439 alu.src[1].chan = 1;
11440 alu.last = 1;
11441 r = r600_bytecode_add_alu(ctx->bc, &alu);
11442 if (r)
11443 return r;
11444 return 0;
11445 }
11446
11447 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
11448 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
11449 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11450 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11451
11452 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
11453
11454 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
11455 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11456 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11457 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11458 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11459 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11460 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11461 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11462 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
11463 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11464 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11465 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11466 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11467 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11468 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11469 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
11470 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
11471 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11472 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11473 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11474 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11475 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11476 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11477 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11478 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11479 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11480 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11481 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11482 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11483 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_unsupported},
11484 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11485 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11486 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11487 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11488 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11489 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11490 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
11491 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11492 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11493 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11494 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11495 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11496 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11497 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11498 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11499 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11500 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11501 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11502 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11503 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11504 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11505 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
11506 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11507 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11508 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11509 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11510 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11511 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
11512 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11513 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11514 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11515 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11516 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11517 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11518 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11519 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11520 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11521 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11522 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11523 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11524 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11525 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11526 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11527 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11528 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11529 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11530 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11531 [81] = { ALU_OP0_NOP, tgsi_unsupported},
11532 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11533 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11534 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11535 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11536 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11537 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
11538 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11539 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11540 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11541 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11542 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11543 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11544 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11545 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11546 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11547 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11548 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11549 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11550 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11551 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11552 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11553 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11554 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11555 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
11556 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11557 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11558 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11559 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11560 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11561 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11562 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
11563 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11564 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11565 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11566 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11567 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11568 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
11569 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
11570 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11571 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11572 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11573 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11574 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11575 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
11576 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11577 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
11578 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11579 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11580 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11581 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11582 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11583 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11584 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11585 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11586 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11587 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11588 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
11589 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11590 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
11591 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11592 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11593 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11594 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11595 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11596 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11597 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11598 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11599 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11600 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11601 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11602 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11603 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11604 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11605 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11606 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11607 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
11608 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11609 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11610 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11611 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
11612 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
11613 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11614 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11615 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11616 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
11617 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
11618 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
11619 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
11620 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
11621 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
11622 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
11623 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11624 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11625 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11626 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11627 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11628 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11629 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11630 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11631 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11632 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
11633 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
11634 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
11635 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
11636 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
11637 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
11638 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
11639 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
11640 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
11641 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
11642 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
11643 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
11644 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
11645 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11646 };
11647
11648 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
11649 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11650 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11651 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11652 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
11653 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
11654 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11655 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11656 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11657 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11658 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11659 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11660 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11661 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11662 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11663 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11664 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11665 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11666 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11667 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11668 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
11669 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11670 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11671 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11672 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11673 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11674 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11675 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11676 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11677 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11678 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11679 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11680 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11681 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11682 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11683 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11684 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11685 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11686 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11687 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11688 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11689 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11690 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11691 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11692 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11693 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11694 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11695 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11696 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11697 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11698 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11699 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11700 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11701 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11702 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11703 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11704 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11705 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11706 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11707 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11708 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11709 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11710 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11711 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11712 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11713 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11714 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11715 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11716 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11717 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11718 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11719 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11720 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11721 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11722 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11723 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11724 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11725 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11726 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11727 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11728 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11729 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11730 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11731 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11732 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11733 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11734 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
11735 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11736 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11737 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11738 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11739 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11740 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11741 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11742 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11743 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11744 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11745 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11746 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11747 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11748 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11749 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11750 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11751 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11752 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
11753 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11754 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11755 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11756 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11757 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11758 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11759 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11760 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11761 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11762 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11763 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11764 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11765 /* Refer below for TGSI_OPCODE_DFMA */
11766 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
11767 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11768 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11769 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11770 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11771 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11772 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
11773 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11774 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
11775 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11776 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11777 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11778 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11779 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11780 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11781 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11782 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11783 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11784 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11785 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
11786 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11787 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
11788 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11789 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11790 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11791 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11792 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11793 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11794 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11795 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11796 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11797 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11798 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11799 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11800 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11801 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11802 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11803 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11804 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
11805 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11806 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11807 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11808 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
11809 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
11810 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11811 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11812 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11813 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11814 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
11815 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
11816 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
11817 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
11818 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
11819 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
11820 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
11821 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
11822 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
11823 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
11824 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11825 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11826 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11827 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11828 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11829 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
11830 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
11831 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
11832 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
11833 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
11834 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
11835 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
11836 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
11837 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
11838 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
11839 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
11840 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
11841 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
11842 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
11843 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
11844 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
11845 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
11846 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
11847 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
11848 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
11849 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
11850 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
11851 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
11852 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
11853 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
11854 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
11855 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
11856 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
11857 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
11858 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
11859 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
11860 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
11861 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
11862 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
11863 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
11864 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
11865 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
11866 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
11867 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
11868 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
11869 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
11870 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
11871 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11872 };
11873
11874 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
11875 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11876 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11877 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11878 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
11879 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
11880 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11881 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11882 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11883 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11884 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11885 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11886 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11887 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11888 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11889 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11890 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11891 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11892 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11893 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11894 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
11895 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11896 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11897 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11898 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11899 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11900 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11901 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11902 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
11903 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
11904 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
11905 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11906 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11907 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11908 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11909 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11910 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
11911 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11912 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11913 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11914 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11915 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11916 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11917 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11918 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11919 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11920 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11921 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11922 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
11923 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11924 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11925 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11926 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11927 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11928 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11929 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11930 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11931 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11932 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11933 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11934 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11935 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11936 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11937 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11938 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11939 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11940 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11941 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11942 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11943 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11944 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11945 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11946 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11947 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11948 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11949 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11950 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11951 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11952 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11953 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11954 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11955 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11956 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11957 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
11958 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11959 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11960 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
11961 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11962 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11963 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11964 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11965 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11966 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11967 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11968 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11969 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11970 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11971 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11972 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11973 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11974 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11975 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11976 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11977 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11978 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
11979 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11980 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11981 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11982 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11983 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11984 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11985 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11986 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11987 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11988 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11989 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11990 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11991 /* Refer below for TGSI_OPCODE_DFMA */
11992 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
11993 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11994 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11995 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11996 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11997 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11998 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
11999 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
12000 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
12001 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
12002 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
12003 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
12004 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
12005 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
12006 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
12007 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
12008 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
12009 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
12010 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
12011 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
12012 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
12013 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
12014 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
12015 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
12016 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
12017 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
12018 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
12019 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
12020 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
12021 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
12022 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
12023 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
12024 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
12025 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
12026 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
12027 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
12028 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
12029 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
12030 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
12031 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
12032 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
12033 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
12034 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
12035 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
12036 [163] = { ALU_OP0_NOP, tgsi_unsupported},
12037 [164] = { ALU_OP0_NOP, tgsi_unsupported},
12038 [165] = { ALU_OP0_NOP, tgsi_unsupported},
12039 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
12040 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
12041 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
12042 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
12043 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
12044 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
12045 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
12046 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
12047 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
12048 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
12049 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
12050 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
12051 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
12052 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
12053 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
12054 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
12055 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
12056 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
12057 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
12058 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
12059 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
12060 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
12061 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
12062 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
12063 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
12064 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
12065 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
12066 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
12067 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
12068 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
12069 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
12070 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
12071 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
12072 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
12073 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
12074 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
12075 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
12076 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
12077 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
12078 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
12079 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
12080 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
12081 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
12082 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
12083 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
12084 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
12085 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
12086 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
12087 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
12088 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
12089 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
12090 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
12091 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
12092 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
12093 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
12094 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
12095 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
12096 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
12097 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
12098 };