2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
29 #include "sb/sb_public.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
43 Why CAYMAN got loops for lots of instructions is explained here.
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
63 /* Contents of r0 on entry to various shaders
69 GS - r0.xyw, r1.xyz = per-vertex offsets
75 .w = tess factor base.
77 TES - .x = TessCoord.x
79 - .z = RelPatchID (??)
82 PS - face_gpr.z = SampleMask
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
87 struct r600_pipe_shader
*pipeshader
,
88 union r600_shader_key key
);
90 static void r600_add_gpr_array(struct r600_shader
*ps
, int start_gpr
,
91 int size
, unsigned comp_mask
) {
96 if (ps
->num_arrays
== ps
->max_arrays
) {
98 ps
->arrays
= realloc(ps
->arrays
, ps
->max_arrays
*
99 sizeof(struct r600_shader_array
));
102 int n
= ps
->num_arrays
;
105 ps
->arrays
[n
].comp_mask
= comp_mask
;
106 ps
->arrays
[n
].gpr_start
= start_gpr
;
107 ps
->arrays
[n
].gpr_count
= size
;
110 static void r600_dump_streamout(struct pipe_stream_output_info
*so
)
114 fprintf(stderr
, "STREAMOUT\n");
115 for (i
= 0; i
< so
->num_outputs
; i
++) {
116 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
117 so
->output
[i
].start_component
;
118 fprintf(stderr
, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
120 so
->output
[i
].stream
,
121 so
->output
[i
].output_buffer
,
122 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
123 so
->output
[i
].register_index
,
128 so
->output
[i
].dst_offset
< so
->output
[i
].start_component
? " (will lower)" : "");
132 static int store_shader(struct pipe_context
*ctx
,
133 struct r600_pipe_shader
*shader
)
135 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
138 if (shader
->bo
== NULL
) {
139 shader
->bo
= (struct r600_resource
*)
140 pipe_buffer_create(ctx
->screen
, 0, PIPE_USAGE_IMMUTABLE
, shader
->shader
.bc
.ndw
* 4);
141 if (shader
->bo
== NULL
) {
144 ptr
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->bo
, PIPE_TRANSFER_WRITE
);
145 if (R600_BIG_ENDIAN
) {
146 for (i
= 0; i
< shader
->shader
.bc
.ndw
; ++i
) {
147 ptr
[i
] = util_cpu_to_le32(shader
->shader
.bc
.bytecode
[i
]);
150 memcpy(ptr
, shader
->shader
.bc
.bytecode
, shader
->shader
.bc
.ndw
* sizeof(*ptr
));
152 rctx
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
158 int r600_pipe_shader_create(struct pipe_context
*ctx
,
159 struct r600_pipe_shader
*shader
,
160 union r600_shader_key key
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_shader_selector
*sel
= shader
->selector
;
165 bool dump
= r600_can_dump_shader(&rctx
->screen
->b
,
166 tgsi_get_processor_type(sel
->tokens
));
167 unsigned use_sb
= !(rctx
->screen
->b
.debug_flags
& DBG_NO_SB
);
168 unsigned sb_disasm
= use_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
169 unsigned export_shader
;
171 shader
->shader
.bc
.isa
= rctx
->isa
;
174 fprintf(stderr
, "--------------------------------------------------------------\n");
175 tgsi_dump(sel
->tokens
, 0);
177 if (sel
->so
.num_outputs
) {
178 r600_dump_streamout(&sel
->so
);
181 r
= r600_shader_from_tgsi(rctx
, shader
, key
);
183 R600_ERR("translation from TGSI failed !\n");
186 if (shader
->shader
.processor_type
== PIPE_SHADER_VERTEX
) {
187 /* only disable for vertex shaders in tess paths */
191 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_CTRL
);
192 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_EVAL
);
194 /* disable SB for shaders using doubles */
195 use_sb
&= !shader
->shader
.uses_doubles
;
197 /* Check if the bytecode has already been built. */
198 if (!shader
->shader
.bc
.bytecode
) {
199 r
= r600_bytecode_build(&shader
->shader
.bc
);
201 R600_ERR("building bytecode failed !\n");
206 if (dump
&& !sb_disasm
) {
207 fprintf(stderr
, "--------------------------------------------------------------\n");
208 r600_bytecode_disasm(&shader
->shader
.bc
);
209 fprintf(stderr
, "______________________________________________________________\n");
210 } else if ((dump
&& sb_disasm
) || use_sb
) {
211 r
= r600_sb_bytecode_process(rctx
, &shader
->shader
.bc
, &shader
->shader
,
214 R600_ERR("r600_sb_bytecode_process failed !\n");
219 if (shader
->gs_copy_shader
) {
222 r
= r600_sb_bytecode_process(rctx
, &shader
->gs_copy_shader
->shader
.bc
,
223 &shader
->gs_copy_shader
->shader
, dump
, 0);
228 if ((r
= store_shader(ctx
, shader
->gs_copy_shader
)))
232 /* Store the shader in a buffer. */
233 if ((r
= store_shader(ctx
, shader
)))
237 switch (shader
->shader
.processor_type
) {
238 case PIPE_SHADER_TESS_CTRL
:
239 evergreen_update_hs_state(ctx
, shader
);
241 case PIPE_SHADER_TESS_EVAL
:
243 evergreen_update_es_state(ctx
, shader
);
245 evergreen_update_vs_state(ctx
, shader
);
247 case PIPE_SHADER_GEOMETRY
:
248 if (rctx
->b
.chip_class
>= EVERGREEN
) {
249 evergreen_update_gs_state(ctx
, shader
);
250 evergreen_update_vs_state(ctx
, shader
->gs_copy_shader
);
252 r600_update_gs_state(ctx
, shader
);
253 r600_update_vs_state(ctx
, shader
->gs_copy_shader
);
256 case PIPE_SHADER_VERTEX
:
257 export_shader
= key
.vs
.as_es
;
258 if (rctx
->b
.chip_class
>= EVERGREEN
) {
260 evergreen_update_ls_state(ctx
, shader
);
261 else if (key
.vs
.as_es
)
262 evergreen_update_es_state(ctx
, shader
);
264 evergreen_update_vs_state(ctx
, shader
);
267 r600_update_es_state(ctx
, shader
);
269 r600_update_vs_state(ctx
, shader
);
272 case PIPE_SHADER_FRAGMENT
:
273 if (rctx
->b
.chip_class
>= EVERGREEN
) {
274 evergreen_update_ps_state(ctx
, shader
);
276 r600_update_ps_state(ctx
, shader
);
286 r600_pipe_shader_destroy(ctx
, shader
);
290 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
292 r600_resource_reference(&shader
->bo
, NULL
);
293 r600_bytecode_clear(&shader
->shader
.bc
);
294 r600_release_command_buffer(&shader
->command_buffer
);
298 * tgsi -> r600 shader
300 struct r600_shader_tgsi_instruction
;
302 struct r600_shader_src
{
309 boolean kc_rel
; /* true if cache bank is indexed */
318 struct r600_shader_ctx
{
319 struct tgsi_shader_info info
;
320 struct tgsi_parse_context parse
;
321 const struct tgsi_token
*tokens
;
323 unsigned file_offset
[TGSI_FILE_COUNT
];
325 const struct r600_shader_tgsi_instruction
*inst_info
;
326 struct r600_bytecode
*bc
;
327 struct r600_shader
*shader
;
328 struct r600_shader_src src
[4];
331 uint32_t max_driver_temp_used
;
332 /* needed for evergreen interpolation */
333 struct eg_interp eg_interpolators
[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
334 /* evergreen/cayman also store sample mask in face register */
336 /* sample id is .w component stored in fixed point position register */
337 int fixed_pt_position_gpr
;
339 boolean clip_vertex_write
;
341 unsigned edgeflag_output
;
344 int next_ring_offset
;
345 int gs_out_ring_offset
;
347 struct r600_shader
*gs_for_vs
;
348 int gs_export_gpr_tregs
[4];
349 const struct pipe_stream_output_info
*gs_stream_output_info
;
350 unsigned enabled_stream_buffers_mask
;
351 unsigned tess_input_info
; /* temp with tess input offsets */
352 unsigned tess_output_info
; /* temp with tess input offsets */
355 struct r600_shader_tgsi_instruction
{
357 int (*process
)(struct r600_shader_ctx
*ctx
);
360 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
);
361 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
362 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
363 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
);
364 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
);
365 static int tgsi_else(struct r600_shader_ctx
*ctx
);
366 static int tgsi_endif(struct r600_shader_ctx
*ctx
);
367 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
);
368 static int tgsi_endloop(struct r600_shader_ctx
*ctx
);
369 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
);
370 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
371 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
372 unsigned int dst_reg
);
373 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
374 const struct r600_shader_src
*shader_src
,
376 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
379 static int tgsi_last_instruction(unsigned writemask
)
383 for (i
= 0; i
< 4; i
++) {
384 if (writemask
& (1 << i
)) {
391 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
393 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
396 if (i
->Instruction
.NumDstRegs
> 1 && i
->Instruction
.Opcode
!= TGSI_OPCODE_DFRACEXP
) {
397 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
401 if (i
->Instruction
.Label
) {
402 R600_ERR("label unsupported\n");
406 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
407 if (i
->Src
[j
].Register
.Dimension
) {
408 switch (i
->Src
[j
].Register
.File
) {
409 case TGSI_FILE_CONSTANT
:
411 case TGSI_FILE_INPUT
:
412 if (ctx
->type
== PIPE_SHADER_GEOMETRY
||
413 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
414 ctx
->type
== PIPE_SHADER_TESS_EVAL
)
416 case TGSI_FILE_OUTPUT
:
417 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
420 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j
,
421 i
->Src
[j
].Register
.File
,
422 i
->Src
[j
].Register
.Dimension
);
427 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
428 if (i
->Dst
[j
].Register
.Dimension
) {
429 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
431 R600_ERR("unsupported dst (dimension)\n");
438 int eg_get_interpolator_index(unsigned interpolate
, unsigned location
)
440 if (interpolate
== TGSI_INTERPOLATE_COLOR
||
441 interpolate
== TGSI_INTERPOLATE_LINEAR
||
442 interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
444 int is_linear
= interpolate
== TGSI_INTERPOLATE_LINEAR
;
448 case TGSI_INTERPOLATE_LOC_CENTER
:
451 case TGSI_INTERPOLATE_LOC_CENTROID
:
454 case TGSI_INTERPOLATE_LOC_SAMPLE
:
459 return is_linear
* 3 + loc
;
465 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx
*ctx
,
468 int i
= eg_get_interpolator_index(
469 ctx
->shader
->input
[input
].interpolate
,
470 ctx
->shader
->input
[input
].interpolate_location
);
472 ctx
->shader
->input
[input
].ij_index
= ctx
->eg_interpolators
[i
].ij_index
;
475 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
478 struct r600_bytecode_alu alu
;
479 int gpr
= 0, base_chan
= 0;
480 int ij_index
= ctx
->shader
->input
[input
].ij_index
;
482 /* work out gpr and base_chan from index */
484 base_chan
= (2 * (ij_index
% 2)) + 1;
486 for (i
= 0; i
< 8; i
++) {
487 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
490 alu
.op
= ALU_OP2_INTERP_ZW
;
492 alu
.op
= ALU_OP2_INTERP_XY
;
494 if ((i
> 1) && (i
< 6)) {
495 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
499 alu
.dst
.chan
= i
% 4;
501 alu
.src
[0].sel
= gpr
;
502 alu
.src
[0].chan
= (base_chan
- (i
% 2));
504 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
506 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
509 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
516 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
519 struct r600_bytecode_alu alu
;
521 for (i
= 0; i
< 4; i
++) {
522 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
524 alu
.op
= ALU_OP1_INTERP_LOAD_P0
;
526 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
531 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
536 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
544 * Special export handling in shaders
546 * shader export ARRAY_BASE for EXPORT_POS:
549 * 62, 63 are clip distance vectors
551 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
552 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
553 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
554 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
555 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
556 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
557 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
558 * exclusive from render target index)
559 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
562 * shader export ARRAY_BASE for EXPORT_PIXEL:
564 * 61 computed Z vector
566 * The use of the values exported in the computed Z vector are controlled
567 * by DB_SHADER_CONTROL:
568 * Z_EXPORT_ENABLE - Z as a float in RED
569 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
570 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
571 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
572 * DB_SOURCE_FORMAT - export control restrictions
577 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
578 static int r600_spi_sid(struct r600_shader_io
* io
)
580 int index
, name
= io
->name
;
582 /* These params are handled differently, they don't need
583 * semantic indices, so we'll use 0 for them.
585 if (name
== TGSI_SEMANTIC_POSITION
||
586 name
== TGSI_SEMANTIC_PSIZE
||
587 name
== TGSI_SEMANTIC_EDGEFLAG
||
588 name
== TGSI_SEMANTIC_FACE
||
589 name
== TGSI_SEMANTIC_SAMPLEMASK
)
592 if (name
== TGSI_SEMANTIC_GENERIC
) {
593 /* For generic params simply use sid from tgsi */
596 /* For non-generic params - pack name and sid into 8 bits */
597 index
= 0x80 | (name
<<3) | (io
->sid
);
600 /* Make sure that all really used indices have nonzero value, so
601 * we can just compare it to 0 later instead of comparing the name
602 * with different values to detect special cases. */
609 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
610 int r600_get_lds_unique_index(unsigned semantic_name
, unsigned index
)
612 switch (semantic_name
) {
613 case TGSI_SEMANTIC_POSITION
:
615 case TGSI_SEMANTIC_PSIZE
:
617 case TGSI_SEMANTIC_CLIPDIST
:
620 case TGSI_SEMANTIC_GENERIC
:
622 return 4 + index
- 9;
624 /* same explanation as in the default statement,
625 * the only user hitting this is st/nine.
629 /* patch indices are completely separate and thus start from 0 */
630 case TGSI_SEMANTIC_TESSOUTER
:
632 case TGSI_SEMANTIC_TESSINNER
:
634 case TGSI_SEMANTIC_PATCH
:
638 /* Don't fail here. The result of this function is only used
639 * for LS, TCS, TES, and GS, where legacy GL semantics can't
640 * occur, but this function is called for all vertex shaders
641 * before it's known whether LS will be compiled or not.
647 /* turn input into interpolate on EG */
648 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
652 if (ctx
->shader
->input
[index
].spi_sid
) {
653 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
654 if (ctx
->shader
->input
[index
].interpolate
> 0) {
655 evergreen_interp_assign_ij_index(ctx
, index
);
656 r
= evergreen_interp_alu(ctx
, index
);
658 r
= evergreen_interp_flat(ctx
, index
);
664 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
666 struct r600_bytecode_alu alu
;
668 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
669 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
671 for (i
= 0; i
< 4; i
++) {
672 memset(&alu
, 0, sizeof(alu
));
673 alu
.op
= ALU_OP3_CNDGT
;
676 alu
.dst
.sel
= gpr_front
;
677 alu
.src
[0].sel
= ctx
->face_gpr
;
678 alu
.src
[1].sel
= gpr_front
;
679 alu
.src
[2].sel
= gpr_back
;
686 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
693 /* execute a single slot ALU calculation */
694 static int single_alu_op2(struct r600_shader_ctx
*ctx
, int op
,
695 int dst_sel
, int dst_chan
,
696 int src0_sel
, unsigned src0_chan_val
,
697 int src1_sel
, unsigned src1_chan_val
)
699 struct r600_bytecode_alu alu
;
702 if (ctx
->bc
->chip_class
== CAYMAN
&& op
== ALU_OP2_MULLO_INT
) {
703 for (i
= 0; i
< 4; i
++) {
704 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
706 alu
.src
[0].sel
= src0_sel
;
707 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
708 alu
.src
[0].value
= src0_chan_val
;
710 alu
.src
[0].chan
= src0_chan_val
;
711 alu
.src
[1].sel
= src1_sel
;
712 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
713 alu
.src
[1].value
= src1_chan_val
;
715 alu
.src
[1].chan
= src1_chan_val
;
716 alu
.dst
.sel
= dst_sel
;
718 alu
.dst
.write
= i
== dst_chan
;
720 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
727 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
729 alu
.src
[0].sel
= src0_sel
;
730 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
731 alu
.src
[0].value
= src0_chan_val
;
733 alu
.src
[0].chan
= src0_chan_val
;
734 alu
.src
[1].sel
= src1_sel
;
735 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
736 alu
.src
[1].value
= src1_chan_val
;
738 alu
.src
[1].chan
= src1_chan_val
;
739 alu
.dst
.sel
= dst_sel
;
740 alu
.dst
.chan
= dst_chan
;
743 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
749 /* execute a single slot ALU calculation */
750 static int single_alu_op3(struct r600_shader_ctx
*ctx
, int op
,
751 int dst_sel
, int dst_chan
,
752 int src0_sel
, unsigned src0_chan_val
,
753 int src1_sel
, unsigned src1_chan_val
,
754 int src2_sel
, unsigned src2_chan_val
)
756 struct r600_bytecode_alu alu
;
759 /* validate this for other ops */
760 assert(op
== ALU_OP3_MULADD_UINT24
);
761 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
763 alu
.src
[0].sel
= src0_sel
;
764 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
765 alu
.src
[0].value
= src0_chan_val
;
767 alu
.src
[0].chan
= src0_chan_val
;
768 alu
.src
[1].sel
= src1_sel
;
769 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
770 alu
.src
[1].value
= src1_chan_val
;
772 alu
.src
[1].chan
= src1_chan_val
;
773 alu
.src
[2].sel
= src2_sel
;
774 if (src2_sel
== V_SQ_ALU_SRC_LITERAL
)
775 alu
.src
[2].value
= src2_chan_val
;
777 alu
.src
[2].chan
= src2_chan_val
;
778 alu
.dst
.sel
= dst_sel
;
779 alu
.dst
.chan
= dst_chan
;
782 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
788 /* put it in temp_reg.x */
789 static int get_lds_offset0(struct r600_shader_ctx
*ctx
,
791 int temp_reg
, bool is_patch_var
)
795 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
797 Dimension - patch0_offset (input_vals.z),
798 Non-dim - patch0_data_offset (input_vals.w)
800 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
802 ctx
->tess_output_info
, 0,
804 ctx
->tess_output_info
, is_patch_var
? 3 : 2);
810 static inline int get_address_file_reg(struct r600_shader_ctx
*ctx
, int index
)
812 return index
> 0 ? ctx
->bc
->index_reg
[index
- 1] : ctx
->bc
->ar_reg
;
815 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
817 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
820 static int vs_add_primid_output(struct r600_shader_ctx
*ctx
, int prim_id_sid
)
823 i
= ctx
->shader
->noutput
++;
824 ctx
->shader
->output
[i
].name
= TGSI_SEMANTIC_PRIMID
;
825 ctx
->shader
->output
[i
].sid
= 0;
826 ctx
->shader
->output
[i
].gpr
= 0;
827 ctx
->shader
->output
[i
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
828 ctx
->shader
->output
[i
].write_mask
= 0x4;
829 ctx
->shader
->output
[i
].spi_sid
= prim_id_sid
;
834 static int tgsi_barrier(struct r600_shader_ctx
*ctx
)
836 struct r600_bytecode_alu alu
;
839 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
840 alu
.op
= ctx
->inst_info
->op
;
843 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
849 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
851 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
852 int r
, i
, j
, count
= d
->Range
.Last
- d
->Range
.First
+ 1;
854 switch (d
->Declaration
.File
) {
855 case TGSI_FILE_INPUT
:
856 for (j
= 0; j
< count
; j
++) {
857 i
= ctx
->shader
->ninput
+ j
;
858 assert(i
< ARRAY_SIZE(ctx
->shader
->input
));
859 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
860 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
+ j
;
861 ctx
->shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
862 ctx
->shader
->input
[i
].interpolate_location
= d
->Interp
.Location
;
863 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
+ j
;
864 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
865 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
866 switch (ctx
->shader
->input
[i
].name
) {
867 case TGSI_SEMANTIC_FACE
:
868 if (ctx
->face_gpr
!= -1)
869 ctx
->shader
->input
[i
].gpr
= ctx
->face_gpr
; /* already allocated by allocate_system_value_inputs */
871 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
873 case TGSI_SEMANTIC_COLOR
:
876 case TGSI_SEMANTIC_POSITION
:
877 ctx
->fragcoord_input
= i
;
879 case TGSI_SEMANTIC_PRIMID
:
880 /* set this for now */
881 ctx
->shader
->gs_prim_id_input
= true;
882 ctx
->shader
->ps_prim_id_input
= i
;
885 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
886 if ((r
= evergreen_interp_input(ctx
, i
)))
889 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
890 /* FIXME probably skip inputs if they aren't passed in the ring */
891 ctx
->shader
->input
[i
].ring_offset
= ctx
->next_ring_offset
;
892 ctx
->next_ring_offset
+= 16;
893 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_PRIMID
)
894 ctx
->shader
->gs_prim_id_input
= true;
897 ctx
->shader
->ninput
+= count
;
899 case TGSI_FILE_OUTPUT
:
900 for (j
= 0; j
< count
; j
++) {
901 i
= ctx
->shader
->noutput
+ j
;
902 assert(i
< ARRAY_SIZE(ctx
->shader
->output
));
903 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
904 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
+ j
;
905 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
+ j
;
906 ctx
->shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
907 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
908 if (ctx
->type
== PIPE_SHADER_VERTEX
||
909 ctx
->type
== PIPE_SHADER_GEOMETRY
||
910 ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
911 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
912 switch (d
->Semantic
.Name
) {
913 case TGSI_SEMANTIC_CLIPDIST
:
914 ctx
->shader
->clip_dist_write
|= d
->Declaration
.UsageMask
<<
915 ((d
->Semantic
.Index
+ j
) << 2);
917 case TGSI_SEMANTIC_PSIZE
:
918 ctx
->shader
->vs_out_misc_write
= 1;
919 ctx
->shader
->vs_out_point_size
= 1;
921 case TGSI_SEMANTIC_EDGEFLAG
:
922 ctx
->shader
->vs_out_misc_write
= 1;
923 ctx
->shader
->vs_out_edgeflag
= 1;
924 ctx
->edgeflag_output
= i
;
926 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
927 ctx
->shader
->vs_out_misc_write
= 1;
928 ctx
->shader
->vs_out_viewport
= 1;
930 case TGSI_SEMANTIC_LAYER
:
931 ctx
->shader
->vs_out_misc_write
= 1;
932 ctx
->shader
->vs_out_layer
= 1;
934 case TGSI_SEMANTIC_CLIPVERTEX
:
935 ctx
->clip_vertex_write
= TRUE
;
939 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
940 ctx
->gs_out_ring_offset
+= 16;
942 } else if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
943 switch (d
->Semantic
.Name
) {
944 case TGSI_SEMANTIC_COLOR
:
945 ctx
->shader
->nr_ps_max_color_exports
++;
950 ctx
->shader
->noutput
+= count
;
952 case TGSI_FILE_TEMPORARY
:
953 if (ctx
->info
.indirect_files
& (1 << TGSI_FILE_TEMPORARY
)) {
954 if (d
->Array
.ArrayID
) {
955 r600_add_gpr_array(ctx
->shader
,
956 ctx
->file_offset
[TGSI_FILE_TEMPORARY
] +
958 d
->Range
.Last
- d
->Range
.First
+ 1, 0x0F);
963 case TGSI_FILE_CONSTANT
:
964 case TGSI_FILE_SAMPLER
:
965 case TGSI_FILE_SAMPLER_VIEW
:
966 case TGSI_FILE_ADDRESS
:
969 case TGSI_FILE_SYSTEM_VALUE
:
970 if (d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEMASK
||
971 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEID
||
972 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEPOS
) {
973 break; /* Already handled from allocate_system_value_inputs */
974 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
975 if (!ctx
->native_integers
) {
976 struct r600_bytecode_alu alu
;
977 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
979 alu
.op
= ALU_OP1_INT_TO_FLT
;
988 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
992 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
994 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INVOCATIONID
)
996 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
||
997 d
->Semantic
.Name
== TGSI_SEMANTIC_TESSOUTER
) {
998 int param
= r600_get_lds_unique_index(d
->Semantic
.Name
, 0);
999 int dreg
= d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
? 3 : 2;
1000 unsigned temp_reg
= r600_get_temp(ctx
);
1002 r
= get_lds_offset0(ctx
, 2, temp_reg
, true);
1006 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1009 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1013 do_lds_fetch_values(ctx
, temp_reg
, dreg
);
1015 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSCOORD
) {
1019 for (i
= 0; i
< 2; i
++) {
1020 struct r600_bytecode_alu alu
;
1021 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1022 alu
.op
= ALU_OP1_MOV
;
1024 alu
.src
[0].chan
= 0 + i
;
1026 alu
.dst
.chan
= 0 + i
;
1028 alu
.last
= (i
== 1) ? 1 : 0;
1029 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1032 /* ADD r1.z, 1.0f, -r0.x */
1033 struct r600_bytecode_alu alu
;
1034 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1035 alu
.op
= ALU_OP2_ADD
;
1036 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1038 alu
.src
[1].chan
= 0;
1044 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1047 /* ADD r1.z, r1.z, -r1.y */
1048 alu
.op
= ALU_OP2_ADD
;
1050 alu
.src
[0].chan
= 2;
1052 alu
.src
[1].chan
= 1;
1058 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1064 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
1070 static int allocate_system_value_inputs(struct r600_shader_ctx
*ctx
, int gpr_offset
)
1072 struct tgsi_parse_context parse
;
1076 unsigned name
, alternate_name
;
1078 { false, &ctx
->face_gpr
, TGSI_SEMANTIC_SAMPLEMASK
, ~0u }, /* lives in Front Face GPR.z */
1080 { false, &ctx
->fixed_pt_position_gpr
, TGSI_SEMANTIC_SAMPLEID
, TGSI_SEMANTIC_SAMPLEPOS
} /* SAMPLEID is in Fixed Point Position GPR.w */
1082 int i
, k
, num_regs
= 0;
1084 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1088 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1089 while (!tgsi_parse_end_of_tokens(&parse
)) {
1090 tgsi_parse_token(&parse
);
1092 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1093 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1094 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1095 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1096 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1098 int interpolate
, location
, k
;
1100 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1101 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1102 inputs
[1].enabled
= true; /* needs SAMPLEID */
1103 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1104 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1105 /* Needs sample positions, currently those are always available */
1107 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1110 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1111 k
= eg_get_interpolator_index(interpolate
, location
);
1113 ctx
->eg_interpolators
[k
].enabled
= true;
1115 } else if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_DECLARATION
) {
1116 struct tgsi_full_declaration
*d
= &parse
.FullToken
.FullDeclaration
;
1117 if (d
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1118 for (k
= 0; k
< ARRAY_SIZE(inputs
); k
++) {
1119 if (d
->Semantic
.Name
== inputs
[k
].name
||
1120 d
->Semantic
.Name
== inputs
[k
].alternate_name
) {
1121 inputs
[k
].enabled
= true;
1128 tgsi_parse_free(&parse
);
1130 for (i
= 0; i
< ARRAY_SIZE(inputs
); i
++) {
1131 boolean enabled
= inputs
[i
].enabled
;
1132 int *reg
= inputs
[i
].reg
;
1133 unsigned name
= inputs
[i
].name
;
1136 int gpr
= gpr_offset
+ num_regs
++;
1138 // add to inputs, allocate a gpr
1139 k
= ctx
->shader
->ninput
++;
1140 ctx
->shader
->input
[k
].name
= name
;
1141 ctx
->shader
->input
[k
].sid
= 0;
1142 ctx
->shader
->input
[k
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1143 ctx
->shader
->input
[k
].interpolate_location
= TGSI_INTERPOLATE_LOC_CENTER
;
1144 *reg
= ctx
->shader
->input
[k
].gpr
= gpr
;
1148 return gpr_offset
+ num_regs
;
1152 * for evergreen we need to scan the shader to find the number of GPRs we need to
1153 * reserve for interpolation and system values
1155 * we need to know if we are going to emit
1156 * any sample or centroid inputs
1157 * if perspective and linear are required
1159 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
1163 struct tgsi_parse_context parse
;
1165 memset(&ctx
->eg_interpolators
, 0, sizeof(ctx
->eg_interpolators
));
1167 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
1169 /* skip position/face/mask/sampleid */
1170 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
1171 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
||
1172 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEMASK
||
1173 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEID
)
1176 k
= eg_get_interpolator_index(
1177 ctx
->info
.input_interpolate
[i
],
1178 ctx
->info
.input_interpolate_loc
[i
]);
1180 ctx
->eg_interpolators
[k
].enabled
= TRUE
;
1183 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1187 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1188 while (!tgsi_parse_end_of_tokens(&parse
)) {
1189 tgsi_parse_token(&parse
);
1191 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1192 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1193 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1194 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1195 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1197 int interpolate
, location
, k
;
1199 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1200 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1201 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1202 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1204 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1207 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1208 k
= eg_get_interpolator_index(interpolate
, location
);
1210 ctx
->eg_interpolators
[k
].enabled
= true;
1215 tgsi_parse_free(&parse
);
1217 /* assign gpr to each interpolator according to priority */
1219 for (i
= 0; i
< ARRAY_SIZE(ctx
->eg_interpolators
); i
++) {
1220 if (ctx
->eg_interpolators
[i
].enabled
) {
1221 ctx
->eg_interpolators
[i
].ij_index
= num_baryc
;
1226 /* XXX PULL MODEL and LINE STIPPLE */
1228 num_baryc
= (num_baryc
+ 1) >> 1;
1229 return allocate_system_value_inputs(ctx
, num_baryc
);
1232 /* sample_id_sel == NULL means fetch for current sample */
1233 static int load_sample_position(struct r600_shader_ctx
*ctx
, struct r600_shader_src
*sample_id
, int chan_sel
)
1235 struct r600_bytecode_vtx vtx
;
1238 assert(ctx
->fixed_pt_position_gpr
!= -1);
1240 t1
= r600_get_temp(ctx
);
1242 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
1243 vtx
.op
= FETCH_OP_VFETCH
;
1244 vtx
.buffer_id
= R600_BUFFER_INFO_CONST_BUFFER
;
1245 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1246 if (sample_id
== NULL
) {
1247 vtx
.src_gpr
= ctx
->fixed_pt_position_gpr
; // SAMPLEID is in .w;
1251 struct r600_bytecode_alu alu
;
1253 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1254 alu
.op
= ALU_OP1_MOV
;
1255 r600_bytecode_src(&alu
.src
[0], sample_id
, chan_sel
);
1259 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1266 vtx
.mega_fetch_count
= 16;
1272 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1273 vtx
.num_format_all
= 2;
1274 vtx
.format_comp_all
= 1;
1275 vtx
.use_const_fields
= 0;
1276 vtx
.offset
= 1; // first element is size of buffer
1277 vtx
.endian
= r600_endian_swap(32);
1278 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
1280 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
1287 static void tgsi_src(struct r600_shader_ctx
*ctx
,
1288 const struct tgsi_full_src_register
*tgsi_src
,
1289 struct r600_shader_src
*r600_src
)
1291 memset(r600_src
, 0, sizeof(*r600_src
));
1292 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
1293 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
1294 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
1295 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
1296 r600_src
->neg
= tgsi_src
->Register
.Negate
;
1297 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
1299 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
1301 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
1302 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
1303 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
1305 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
1306 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
, r600_src
->abs
);
1307 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
1310 index
= tgsi_src
->Register
.Index
;
1311 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
1312 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
1313 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1314 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEMASK
) {
1315 r600_src
->swizzle
[0] = 2; // Z value
1316 r600_src
->swizzle
[1] = 2;
1317 r600_src
->swizzle
[2] = 2;
1318 r600_src
->swizzle
[3] = 2;
1319 r600_src
->sel
= ctx
->face_gpr
;
1320 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEID
) {
1321 r600_src
->swizzle
[0] = 3; // W value
1322 r600_src
->swizzle
[1] = 3;
1323 r600_src
->swizzle
[2] = 3;
1324 r600_src
->swizzle
[3] = 3;
1325 r600_src
->sel
= ctx
->fixed_pt_position_gpr
;
1326 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEPOS
) {
1327 r600_src
->swizzle
[0] = 0;
1328 r600_src
->swizzle
[1] = 1;
1329 r600_src
->swizzle
[2] = 4;
1330 r600_src
->swizzle
[3] = 4;
1331 r600_src
->sel
= load_sample_position(ctx
, NULL
, -1);
1332 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
1333 r600_src
->swizzle
[0] = 3;
1334 r600_src
->swizzle
[1] = 3;
1335 r600_src
->swizzle
[2] = 3;
1336 r600_src
->swizzle
[3] = 3;
1338 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
1339 r600_src
->swizzle
[0] = 0;
1340 r600_src
->swizzle
[1] = 0;
1341 r600_src
->swizzle
[2] = 0;
1342 r600_src
->swizzle
[3] = 0;
1344 } else if (ctx
->type
!= PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1345 r600_src
->swizzle
[0] = 3;
1346 r600_src
->swizzle
[1] = 3;
1347 r600_src
->swizzle
[2] = 3;
1348 r600_src
->swizzle
[3] = 3;
1350 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1351 r600_src
->swizzle
[0] = 2;
1352 r600_src
->swizzle
[1] = 2;
1353 r600_src
->swizzle
[2] = 2;
1354 r600_src
->swizzle
[3] = 2;
1356 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSCOORD
) {
1358 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSINNER
) {
1360 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSOUTER
) {
1362 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTICESIN
) {
1363 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
1364 r600_src
->sel
= ctx
->tess_input_info
;
1365 r600_src
->swizzle
[0] = 2;
1366 r600_src
->swizzle
[1] = 2;
1367 r600_src
->swizzle
[2] = 2;
1368 r600_src
->swizzle
[3] = 2;
1370 r600_src
->sel
= ctx
->tess_input_info
;
1371 r600_src
->swizzle
[0] = 3;
1372 r600_src
->swizzle
[1] = 3;
1373 r600_src
->swizzle
[2] = 3;
1374 r600_src
->swizzle
[3] = 3;
1376 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1378 r600_src
->swizzle
[0] = 0;
1379 r600_src
->swizzle
[1] = 0;
1380 r600_src
->swizzle
[2] = 0;
1381 r600_src
->swizzle
[3] = 0;
1382 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1384 r600_src
->swizzle
[0] = 3;
1385 r600_src
->swizzle
[1] = 3;
1386 r600_src
->swizzle
[2] = 3;
1387 r600_src
->swizzle
[3] = 3;
1390 if (tgsi_src
->Register
.Indirect
)
1391 r600_src
->rel
= V_SQ_REL_RELATIVE
;
1392 r600_src
->sel
= tgsi_src
->Register
.Index
;
1393 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
1395 if (tgsi_src
->Register
.File
== TGSI_FILE_CONSTANT
) {
1396 if (tgsi_src
->Register
.Dimension
) {
1397 r600_src
->kc_bank
= tgsi_src
->Dimension
.Index
;
1398 if (tgsi_src
->Dimension
.Indirect
) {
1399 r600_src
->kc_rel
= 1;
1405 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
1406 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
1407 unsigned int dst_reg
)
1409 struct r600_bytecode_vtx vtx
;
1410 unsigned int ar_reg
;
1414 struct r600_bytecode_alu alu
;
1416 memset(&alu
, 0, sizeof(alu
));
1418 alu
.op
= ALU_OP2_ADD_INT
;
1419 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
1420 alu
.src
[0].chan
= ar_chan
;
1422 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1423 alu
.src
[1].value
= offset
;
1425 alu
.dst
.sel
= dst_reg
;
1426 alu
.dst
.chan
= ar_chan
;
1430 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1435 ar_reg
= ctx
->bc
->ar_reg
;
1438 memset(&vtx
, 0, sizeof(vtx
));
1439 vtx
.buffer_id
= cb_idx
;
1440 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1441 vtx
.src_gpr
= ar_reg
;
1442 vtx
.src_sel_x
= ar_chan
;
1443 vtx
.mega_fetch_count
= 16;
1444 vtx
.dst_gpr
= dst_reg
;
1445 vtx
.dst_sel_x
= 0; /* SEL_X */
1446 vtx
.dst_sel_y
= 1; /* SEL_Y */
1447 vtx
.dst_sel_z
= 2; /* SEL_Z */
1448 vtx
.dst_sel_w
= 3; /* SEL_W */
1449 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1450 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
1451 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
1452 vtx
.endian
= r600_endian_swap(32);
1453 vtx
.buffer_index_mode
= cb_rel
; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1455 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1461 static int fetch_gs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1463 struct r600_bytecode_vtx vtx
;
1465 unsigned index
= src
->Register
.Index
;
1466 unsigned vtx_id
= src
->Dimension
.Index
;
1467 int offset_reg
= vtx_id
/ 3;
1468 int offset_chan
= vtx_id
% 3;
1471 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1472 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1474 if (offset_reg
== 0 && offset_chan
== 2)
1477 if (src
->Dimension
.Indirect
|| src
->Register
.Indirect
)
1478 t2
= r600_get_temp(ctx
);
1480 if (src
->Dimension
.Indirect
) {
1482 struct r600_bytecode_alu alu
;
1485 addr_reg
= get_address_file_reg(ctx
, src
->DimIndirect
.Index
);
1486 if (src
->DimIndirect
.Index
> 0) {
1487 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
1495 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1496 at least this is what fglrx seems to do. */
1497 for (i
= 0; i
< 3; i
++) {
1498 treg
[i
] = r600_get_temp(ctx
);
1500 r600_add_gpr_array(ctx
->shader
, treg
[0], 3, 0x0F);
1502 for (i
= 0; i
< 3; i
++) {
1503 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1504 alu
.op
= ALU_OP1_MOV
;
1506 alu
.src
[0].chan
= i
== 2 ? 3 : i
;
1507 alu
.dst
.sel
= treg
[i
];
1511 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1515 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1516 alu
.op
= ALU_OP1_MOV
;
1517 alu
.src
[0].sel
= treg
[0];
1522 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1529 if (src
->Register
.Indirect
) {
1531 unsigned first
= ctx
->info
.input_array_first
[src
->Indirect
.ArrayID
];
1533 addr_reg
= get_address_file_reg(ctx
, src
->Indirect
.Index
);
1535 /* pull the value from index_reg */
1536 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1539 V_SQ_ALU_SRC_LITERAL
, first
);
1542 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1545 V_SQ_ALU_SRC_LITERAL
, 4,
1546 offset_reg
, offset_chan
);
1551 index
= src
->Register
.Index
- first
;
1554 memset(&vtx
, 0, sizeof(vtx
));
1555 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
1556 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1557 vtx
.src_gpr
= offset_reg
;
1558 vtx
.src_sel_x
= offset_chan
;
1559 vtx
.offset
= index
* 16; /*bytes*/
1560 vtx
.mega_fetch_count
= 16;
1561 vtx
.dst_gpr
= dst_reg
;
1562 vtx
.dst_sel_x
= 0; /* SEL_X */
1563 vtx
.dst_sel_y
= 1; /* SEL_Y */
1564 vtx
.dst_sel_z
= 2; /* SEL_Z */
1565 vtx
.dst_sel_w
= 3; /* SEL_W */
1566 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1567 vtx
.use_const_fields
= 1;
1569 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1572 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1578 static int tgsi_split_gs_inputs(struct r600_shader_ctx
*ctx
)
1580 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1583 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1584 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1586 if (src
->Register
.File
== TGSI_FILE_INPUT
) {
1587 if (ctx
->shader
->input
[src
->Register
.Index
].name
== TGSI_SEMANTIC_PRIMID
) {
1588 /* primitive id is in R0.z */
1589 ctx
->src
[i
].sel
= 0;
1590 ctx
->src
[i
].swizzle
[0] = 2;
1593 if (src
->Register
.File
== TGSI_FILE_INPUT
&& src
->Register
.Dimension
) {
1594 int treg
= r600_get_temp(ctx
);
1596 fetch_gs_input(ctx
, src
, treg
);
1597 ctx
->src
[i
].sel
= treg
;
1598 ctx
->src
[i
].rel
= 0;
1605 /* Tessellation shaders pass outputs to the next shader using LDS.
1607 * LS outputs = TCS(HS) inputs
1608 * TCS(HS) outputs = TES(DS) inputs
1610 * The LDS layout is:
1611 * - TCS inputs for patch 0
1612 * - TCS inputs for patch 1
1613 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1615 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1616 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1617 * - TCS outputs for patch 1
1618 * - Per-patch TCS outputs for patch 1
1619 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1620 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1623 * All three shaders VS(LS), TCS, TES share the same LDS space.
1625 /* this will return with the dw address in temp_reg.x */
1626 static int r600_get_byte_address(struct r600_shader_ctx
*ctx
, int temp_reg
,
1627 const struct tgsi_full_dst_register
*dst
,
1628 const struct tgsi_full_src_register
*src
,
1629 int stride_bytes_reg
, int stride_bytes_chan
)
1631 struct tgsi_full_dst_register reg
;
1632 ubyte
*name
, *index
, *array_first
;
1635 struct tgsi_shader_info
*info
= &ctx
->info
;
1636 /* Set the register description. The address computation is the same
1637 * for sources and destinations. */
1639 reg
.Register
.File
= src
->Register
.File
;
1640 reg
.Register
.Index
= src
->Register
.Index
;
1641 reg
.Register
.Indirect
= src
->Register
.Indirect
;
1642 reg
.Register
.Dimension
= src
->Register
.Dimension
;
1643 reg
.Indirect
= src
->Indirect
;
1644 reg
.Dimension
= src
->Dimension
;
1645 reg
.DimIndirect
= src
->DimIndirect
;
1649 /* If the register is 2-dimensional (e.g. an array of vertices
1650 * in a primitive), calculate the base address of the vertex. */
1651 if (reg
.Register
.Dimension
) {
1653 if (reg
.Dimension
.Indirect
) {
1655 assert (reg
.DimIndirect
.File
== TGSI_FILE_ADDRESS
);
1657 addr_reg
= get_address_file_reg(ctx
, reg
.DimIndirect
.Index
);
1658 /* pull the value from index_reg */
1662 sel
= V_SQ_ALU_SRC_LITERAL
;
1663 chan
= reg
.Dimension
.Index
;
1666 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1668 stride_bytes_reg
, stride_bytes_chan
,
1675 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1676 name
= info
->input_semantic_name
;
1677 index
= info
->input_semantic_index
;
1678 array_first
= info
->input_array_first
;
1679 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1680 name
= info
->output_semantic_name
;
1681 index
= info
->output_semantic_index
;
1682 array_first
= info
->output_array_first
;
1687 if (reg
.Register
.Indirect
) {
1690 /* Add the relative address of the element. */
1691 if (reg
.Indirect
.ArrayID
)
1692 first
= array_first
[reg
.Indirect
.ArrayID
];
1694 first
= reg
.Register
.Index
;
1696 addr_reg
= get_address_file_reg(ctx
, reg
.Indirect
.Index
);
1698 /* pull the value from index_reg */
1699 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1701 V_SQ_ALU_SRC_LITERAL
, 16,
1707 param
= r600_get_lds_unique_index(name
[first
],
1711 param
= r600_get_lds_unique_index(name
[reg
.Register
.Index
],
1712 index
[reg
.Register
.Index
]);
1715 /* add to base_addr - passed in temp_reg.x */
1717 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1720 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1728 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
1731 struct r600_bytecode_alu alu
;
1734 if ((ctx
->bc
->cf_last
->ndw
>>1) >= 0x60)
1735 ctx
->bc
->force_add_cf
= 1;
1736 for (i
= 1; i
< 4; i
++) {
1737 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1740 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
1744 for (i
= 0; i
< 4; i
++) {
1745 /* emit an LDS_READ_RET */
1746 memset(&alu
, 0, sizeof(alu
));
1747 alu
.op
= LDS_OP1_LDS_READ_RET
;
1748 alu
.src
[0].sel
= temp_reg
;
1749 alu
.src
[0].chan
= i
;
1750 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1751 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
1753 alu
.is_lds_idx_op
= true;
1755 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1759 for (i
= 0; i
< 4; i
++) {
1760 /* then read from LDS_OQ_A_POP */
1761 memset(&alu
, 0, sizeof(alu
));
1763 alu
.op
= ALU_OP1_MOV
;
1764 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
;
1765 alu
.src
[0].chan
= 0;
1766 alu
.dst
.sel
= dst_reg
;
1770 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1777 static int fetch_tes_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1780 unsigned temp_reg
= r600_get_temp(ctx
);
1782 r
= get_lds_offset0(ctx
, 2, temp_reg
,
1783 src
->Register
.Dimension
? false : true);
1787 /* the base address is now in temp.x */
1788 r
= r600_get_byte_address(ctx
, temp_reg
,
1789 NULL
, src
, ctx
->tess_output_info
, 1);
1793 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1799 static int fetch_tcs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1802 unsigned temp_reg
= r600_get_temp(ctx
);
1804 /* t.x = ips * r0.y */
1805 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
1807 ctx
->tess_input_info
, 0,
1813 /* the base address is now in temp.x */
1814 r
= r600_get_byte_address(ctx
, temp_reg
,
1815 NULL
, src
, ctx
->tess_input_info
, 1);
1819 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1825 static int fetch_tcs_output(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1828 unsigned temp_reg
= r600_get_temp(ctx
);
1830 r
= get_lds_offset0(ctx
, 1, temp_reg
,
1831 src
->Register
.Dimension
? false : true);
1834 /* the base address is now in temp.x */
1835 r
= r600_get_byte_address(ctx
, temp_reg
,
1837 ctx
->tess_output_info
, 1);
1841 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1847 static int tgsi_split_lds_inputs(struct r600_shader_ctx
*ctx
)
1849 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1852 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1853 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1855 if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1856 int treg
= r600_get_temp(ctx
);
1857 fetch_tes_input(ctx
, src
, treg
);
1858 ctx
->src
[i
].sel
= treg
;
1859 ctx
->src
[i
].rel
= 0;
1861 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1862 int treg
= r600_get_temp(ctx
);
1863 fetch_tcs_input(ctx
, src
, treg
);
1864 ctx
->src
[i
].sel
= treg
;
1865 ctx
->src
[i
].rel
= 0;
1867 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_OUTPUT
) {
1868 int treg
= r600_get_temp(ctx
);
1869 fetch_tcs_output(ctx
, src
, treg
);
1870 ctx
->src
[i
].sel
= treg
;
1871 ctx
->src
[i
].rel
= 0;
1877 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
1879 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1880 struct r600_bytecode_alu alu
;
1881 int i
, j
, k
, nconst
, r
;
1883 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1884 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
1887 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
1889 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1890 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
1894 if (ctx
->src
[i
].rel
) {
1895 int chan
= inst
->Src
[i
].Indirect
.Swizzle
;
1896 int treg
= r600_get_temp(ctx
);
1897 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].kc_bank
, ctx
->src
[i
].kc_rel
, ctx
->src
[i
].sel
- 512, chan
, treg
)))
1900 ctx
->src
[i
].kc_bank
= 0;
1901 ctx
->src
[i
].kc_rel
= 0;
1902 ctx
->src
[i
].sel
= treg
;
1903 ctx
->src
[i
].rel
= 0;
1906 int treg
= r600_get_temp(ctx
);
1907 for (k
= 0; k
< 4; k
++) {
1908 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1909 alu
.op
= ALU_OP1_MOV
;
1910 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1911 alu
.src
[0].chan
= k
;
1912 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
1913 alu
.src
[0].kc_bank
= ctx
->src
[i
].kc_bank
;
1914 alu
.src
[0].kc_rel
= ctx
->src
[i
].kc_rel
;
1920 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1924 ctx
->src
[i
].sel
= treg
;
1932 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1933 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
1935 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1936 struct r600_bytecode_alu alu
;
1937 int i
, j
, k
, nliteral
, r
;
1939 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1940 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1944 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1945 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1946 int treg
= r600_get_temp(ctx
);
1947 for (k
= 0; k
< 4; k
++) {
1948 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1949 alu
.op
= ALU_OP1_MOV
;
1950 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1951 alu
.src
[0].chan
= k
;
1952 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
1958 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1962 ctx
->src
[i
].sel
= treg
;
1969 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
1971 int i
, r
, count
= ctx
->shader
->ninput
;
1973 for (i
= 0; i
< count
; i
++) {
1974 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1975 r
= select_twoside_color(ctx
, i
, ctx
->shader
->input
[i
].back_color_input
);
1983 static int emit_streamout(struct r600_shader_ctx
*ctx
, struct pipe_stream_output_info
*so
,
1984 int stream
, unsigned *stream_item_size
)
1986 unsigned so_gpr
[PIPE_MAX_SHADER_OUTPUTS
];
1987 unsigned start_comp
[PIPE_MAX_SHADER_OUTPUTS
];
1990 /* Sanity checking. */
1991 if (so
->num_outputs
> PIPE_MAX_SO_OUTPUTS
) {
1992 R600_ERR("Too many stream outputs: %d\n", so
->num_outputs
);
1996 for (i
= 0; i
< so
->num_outputs
; i
++) {
1997 if (so
->output
[i
].output_buffer
>= 4) {
1998 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1999 so
->output
[i
].output_buffer
);
2005 /* Initialize locations where the outputs are stored. */
2006 for (i
= 0; i
< so
->num_outputs
; i
++) {
2008 so_gpr
[i
] = ctx
->shader
->output
[so
->output
[i
].register_index
].gpr
;
2009 start_comp
[i
] = so
->output
[i
].start_component
;
2010 /* Lower outputs with dst_offset < start_component.
2012 * We can only output 4D vectors with a write mask, e.g. we can
2013 * only output the W component at offset 3, etc. If we want
2014 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2015 * to move it to X and output X. */
2016 if (so
->output
[i
].dst_offset
< so
->output
[i
].start_component
) {
2017 unsigned tmp
= r600_get_temp(ctx
);
2019 for (j
= 0; j
< so
->output
[i
].num_components
; j
++) {
2020 struct r600_bytecode_alu alu
;
2021 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2022 alu
.op
= ALU_OP1_MOV
;
2023 alu
.src
[0].sel
= so_gpr
[i
];
2024 alu
.src
[0].chan
= so
->output
[i
].start_component
+ j
;
2029 if (j
== so
->output
[i
].num_components
- 1)
2031 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2040 /* Write outputs to buffers. */
2041 for (i
= 0; i
< so
->num_outputs
; i
++) {
2042 struct r600_bytecode_output output
;
2044 if (stream
!= -1 && stream
!= so
->output
[i
].output_buffer
)
2047 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2048 output
.gpr
= so_gpr
[i
];
2049 output
.elem_size
= so
->output
[i
].num_components
- 1;
2050 if (output
.elem_size
== 2)
2051 output
.elem_size
= 3; // 3 not supported, write 4 with junk at end
2052 output
.array_base
= so
->output
[i
].dst_offset
- start_comp
[i
];
2053 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2054 output
.burst_count
= 1;
2055 /* array_size is an upper limit for the burst_count
2056 * with MEM_STREAM instructions */
2057 output
.array_size
= 0xFFF;
2058 output
.comp_mask
= ((1 << so
->output
[i
].num_components
) - 1) << start_comp
[i
];
2060 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
2061 switch (so
->output
[i
].output_buffer
) {
2063 output
.op
= CF_OP_MEM_STREAM0_BUF0
;
2066 output
.op
= CF_OP_MEM_STREAM0_BUF1
;
2069 output
.op
= CF_OP_MEM_STREAM0_BUF2
;
2072 output
.op
= CF_OP_MEM_STREAM0_BUF3
;
2075 output
.op
+= so
->output
[i
].stream
* 4;
2076 assert(output
.op
>= CF_OP_MEM_STREAM0_BUF0
&& output
.op
<= CF_OP_MEM_STREAM3_BUF3
);
2077 ctx
->enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << so
->output
[i
].stream
* 4;
2079 switch (so
->output
[i
].output_buffer
) {
2081 output
.op
= CF_OP_MEM_STREAM0
;
2084 output
.op
= CF_OP_MEM_STREAM1
;
2087 output
.op
= CF_OP_MEM_STREAM2
;
2090 output
.op
= CF_OP_MEM_STREAM3
;
2093 ctx
->enabled_stream_buffers_mask
|= 1 << so
->output
[i
].output_buffer
;
2095 r
= r600_bytecode_add_output(ctx
->bc
, &output
);
2104 static void convert_edgeflag_to_int(struct r600_shader_ctx
*ctx
)
2106 struct r600_bytecode_alu alu
;
2109 if (!ctx
->shader
->vs_out_edgeflag
)
2112 reg
= ctx
->shader
->output
[ctx
->edgeflag_output
].gpr
;
2114 /* clamp(x, 0, 1) */
2115 memset(&alu
, 0, sizeof(alu
));
2116 alu
.op
= ALU_OP1_MOV
;
2117 alu
.src
[0].sel
= reg
;
2122 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2124 memset(&alu
, 0, sizeof(alu
));
2125 alu
.op
= ALU_OP1_FLT_TO_INT
;
2126 alu
.src
[0].sel
= reg
;
2130 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2133 static int generate_gs_copy_shader(struct r600_context
*rctx
,
2134 struct r600_pipe_shader
*gs
,
2135 struct pipe_stream_output_info
*so
)
2137 struct r600_shader_ctx ctx
= {};
2138 struct r600_shader
*gs_shader
= &gs
->shader
;
2139 struct r600_pipe_shader
*cshader
;
2140 int ocnt
= gs_shader
->noutput
;
2141 struct r600_bytecode_alu alu
;
2142 struct r600_bytecode_vtx vtx
;
2143 struct r600_bytecode_output output
;
2144 struct r600_bytecode_cf
*cf_jump
, *cf_pop
,
2145 *last_exp_pos
= NULL
, *last_exp_param
= NULL
;
2146 int i
, j
, next_clip_pos
= 61, next_param
= 0;
2148 bool only_ring_0
= true;
2149 cshader
= calloc(1, sizeof(struct r600_pipe_shader
));
2153 memcpy(cshader
->shader
.output
, gs_shader
->output
, ocnt
*
2154 sizeof(struct r600_shader_io
));
2156 cshader
->shader
.noutput
= ocnt
;
2158 ctx
.shader
= &cshader
->shader
;
2159 ctx
.bc
= &ctx
.shader
->bc
;
2160 ctx
.type
= ctx
.bc
->type
= PIPE_SHADER_VERTEX
;
2162 r600_bytecode_init(ctx
.bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2163 rctx
->screen
->has_compressed_msaa_texturing
);
2165 ctx
.bc
->isa
= rctx
->isa
;
2168 memset(cshader
->shader
.ring_item_sizes
, 0, sizeof(cshader
->shader
.ring_item_sizes
));
2170 /* R0.x = R0.x & 0x3fffffff */
2171 memset(&alu
, 0, sizeof(alu
));
2172 alu
.op
= ALU_OP2_AND_INT
;
2173 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2174 alu
.src
[1].value
= 0x3fffffff;
2176 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2178 /* R0.y = R0.x >> 30 */
2179 memset(&alu
, 0, sizeof(alu
));
2180 alu
.op
= ALU_OP2_LSHR_INT
;
2181 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2182 alu
.src
[1].value
= 0x1e;
2186 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2188 /* fetch vertex data from GSVS ring */
2189 for (i
= 0; i
< ocnt
; ++i
) {
2190 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2193 out
->ring_offset
= i
* 16;
2195 memset(&vtx
, 0, sizeof(vtx
));
2196 vtx
.op
= FETCH_OP_VFETCH
;
2197 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
2198 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2199 vtx
.mega_fetch_count
= 16;
2200 vtx
.offset
= out
->ring_offset
;
2201 vtx
.dst_gpr
= out
->gpr
;
2207 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2208 vtx
.use_const_fields
= 1;
2210 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
2213 r600_bytecode_add_vtx(ctx
.bc
, &vtx
);
2215 ctx
.temp_reg
= i
+ 1;
2216 for (ring
= 3; ring
>= 0; --ring
) {
2217 bool enabled
= false;
2218 for (i
= 0; i
< so
->num_outputs
; i
++) {
2219 if (so
->output
[i
].stream
== ring
) {
2222 only_ring_0
= false;
2226 if (ring
!= 0 && !enabled
) {
2227 cshader
->shader
.ring_item_sizes
[ring
] = 0;
2232 // Patch up jump label
2233 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2234 cf_pop
= ctx
.bc
->cf_last
;
2236 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2237 cf_jump
->pop_count
= 1;
2238 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2239 cf_pop
->pop_count
= 1;
2242 /* PRED_SETE_INT __, R0.y, ring */
2243 memset(&alu
, 0, sizeof(alu
));
2244 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2245 alu
.src
[0].chan
= 1;
2246 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2247 alu
.src
[1].value
= ring
;
2248 alu
.execute_mask
= 1;
2249 alu
.update_pred
= 1;
2251 r600_bytecode_add_alu_type(ctx
.bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2253 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_JUMP
);
2254 cf_jump
= ctx
.bc
->cf_last
;
2257 emit_streamout(&ctx
, so
, only_ring_0
? -1 : ring
, &cshader
->shader
.ring_item_sizes
[ring
]);
2258 cshader
->shader
.ring_item_sizes
[ring
] = ocnt
* 16;
2261 /* bc adds nops - copy it */
2262 if (ctx
.bc
->chip_class
== R600
) {
2263 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2264 alu
.op
= ALU_OP0_NOP
;
2266 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2268 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2271 /* export vertex data */
2272 /* XXX factor out common code with r600_shader_from_tgsi ? */
2273 for (i
= 0; i
< ocnt
; ++i
) {
2274 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2275 bool instream0
= true;
2276 if (out
->name
== TGSI_SEMANTIC_CLIPVERTEX
)
2279 for (j
= 0; j
< so
->num_outputs
; j
++) {
2280 if (so
->output
[j
].register_index
== i
) {
2281 if (so
->output
[j
].stream
== 0)
2283 if (so
->output
[j
].stream
> 0)
2289 memset(&output
, 0, sizeof(output
));
2290 output
.gpr
= out
->gpr
;
2291 output
.elem_size
= 3;
2292 output
.swizzle_x
= 0;
2293 output
.swizzle_y
= 1;
2294 output
.swizzle_z
= 2;
2295 output
.swizzle_w
= 3;
2296 output
.burst_count
= 1;
2297 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2298 output
.op
= CF_OP_EXPORT
;
2299 switch (out
->name
) {
2300 case TGSI_SEMANTIC_POSITION
:
2301 output
.array_base
= 60;
2302 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2305 case TGSI_SEMANTIC_PSIZE
:
2306 output
.array_base
= 61;
2307 if (next_clip_pos
== 61)
2309 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2310 output
.swizzle_y
= 7;
2311 output
.swizzle_z
= 7;
2312 output
.swizzle_w
= 7;
2313 ctx
.shader
->vs_out_misc_write
= 1;
2314 ctx
.shader
->vs_out_point_size
= 1;
2316 case TGSI_SEMANTIC_LAYER
:
2318 /* duplicate it as PARAM to pass to the pixel shader */
2319 output
.array_base
= next_param
++;
2320 r600_bytecode_add_output(ctx
.bc
, &output
);
2321 last_exp_param
= ctx
.bc
->cf_last
;
2323 output
.array_base
= 61;
2324 if (next_clip_pos
== 61)
2326 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2327 output
.swizzle_x
= 7;
2328 output
.swizzle_y
= 7;
2329 output
.swizzle_z
= 0;
2330 output
.swizzle_w
= 7;
2331 ctx
.shader
->vs_out_misc_write
= 1;
2332 ctx
.shader
->vs_out_layer
= 1;
2334 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2336 /* duplicate it as PARAM to pass to the pixel shader */
2337 output
.array_base
= next_param
++;
2338 r600_bytecode_add_output(ctx
.bc
, &output
);
2339 last_exp_param
= ctx
.bc
->cf_last
;
2341 output
.array_base
= 61;
2342 if (next_clip_pos
== 61)
2344 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2345 ctx
.shader
->vs_out_misc_write
= 1;
2346 ctx
.shader
->vs_out_viewport
= 1;
2347 output
.swizzle_x
= 7;
2348 output
.swizzle_y
= 7;
2349 output
.swizzle_z
= 7;
2350 output
.swizzle_w
= 0;
2352 case TGSI_SEMANTIC_CLIPDIST
:
2353 /* spi_sid is 0 for clipdistance outputs that were generated
2354 * for clipvertex - we don't need to pass them to PS */
2355 ctx
.shader
->clip_dist_write
= gs
->shader
.clip_dist_write
;
2357 /* duplicate it as PARAM to pass to the pixel shader */
2358 output
.array_base
= next_param
++;
2359 r600_bytecode_add_output(ctx
.bc
, &output
);
2360 last_exp_param
= ctx
.bc
->cf_last
;
2362 output
.array_base
= next_clip_pos
++;
2363 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2365 case TGSI_SEMANTIC_FOG
:
2366 output
.swizzle_y
= 4; /* 0 */
2367 output
.swizzle_z
= 4; /* 0 */
2368 output
.swizzle_w
= 5; /* 1 */
2371 output
.array_base
= next_param
++;
2374 r600_bytecode_add_output(ctx
.bc
, &output
);
2375 if (output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
)
2376 last_exp_param
= ctx
.bc
->cf_last
;
2378 last_exp_pos
= ctx
.bc
->cf_last
;
2381 if (!last_exp_pos
) {
2382 memset(&output
, 0, sizeof(output
));
2384 output
.elem_size
= 3;
2385 output
.swizzle_x
= 7;
2386 output
.swizzle_y
= 7;
2387 output
.swizzle_z
= 7;
2388 output
.swizzle_w
= 7;
2389 output
.burst_count
= 1;
2391 output
.op
= CF_OP_EXPORT
;
2392 output
.array_base
= 60;
2393 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2394 r600_bytecode_add_output(ctx
.bc
, &output
);
2395 last_exp_pos
= ctx
.bc
->cf_last
;
2398 if (!last_exp_param
) {
2399 memset(&output
, 0, sizeof(output
));
2401 output
.elem_size
= 3;
2402 output
.swizzle_x
= 7;
2403 output
.swizzle_y
= 7;
2404 output
.swizzle_z
= 7;
2405 output
.swizzle_w
= 7;
2406 output
.burst_count
= 1;
2408 output
.op
= CF_OP_EXPORT
;
2409 output
.array_base
= next_param
++;
2410 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2411 r600_bytecode_add_output(ctx
.bc
, &output
);
2412 last_exp_param
= ctx
.bc
->cf_last
;
2415 last_exp_pos
->op
= CF_OP_EXPORT_DONE
;
2416 last_exp_param
->op
= CF_OP_EXPORT_DONE
;
2418 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2419 cf_pop
= ctx
.bc
->cf_last
;
2421 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2422 cf_jump
->pop_count
= 1;
2423 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2424 cf_pop
->pop_count
= 1;
2426 if (ctx
.bc
->chip_class
== CAYMAN
)
2427 cm_bytecode_add_cf_end(ctx
.bc
);
2429 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2430 ctx
.bc
->cf_last
->end_of_program
= 1;
2433 gs
->gs_copy_shader
= cshader
;
2434 cshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
2438 return r600_bytecode_build(ctx
.bc
);
2441 static int emit_inc_ring_offset(struct r600_shader_ctx
*ctx
, int idx
, bool ind
)
2444 struct r600_bytecode_alu alu
;
2447 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2448 alu
.op
= ALU_OP2_ADD_INT
;
2449 alu
.src
[0].sel
= ctx
->gs_export_gpr_tregs
[idx
];
2450 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2451 alu
.src
[1].value
= ctx
->gs_out_ring_offset
>> 4;
2452 alu
.dst
.sel
= ctx
->gs_export_gpr_tregs
[idx
];
2455 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2462 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
)
2464 struct r600_bytecode_output output
;
2465 int i
, k
, ring_offset
;
2466 int effective_stream
= stream
== -1 ? 0 : stream
;
2469 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2470 if (ctx
->gs_for_vs
) {
2471 /* for ES we need to lookup corresponding ring offset expected by GS
2472 * (map this output to GS input by name and sid) */
2473 /* FIXME precompute offsets */
2475 for(k
= 0; k
< ctx
->gs_for_vs
->ninput
; ++k
) {
2476 struct r600_shader_io
*in
= &ctx
->gs_for_vs
->input
[k
];
2477 struct r600_shader_io
*out
= &ctx
->shader
->output
[i
];
2478 if (in
->name
== out
->name
&& in
->sid
== out
->sid
)
2479 ring_offset
= in
->ring_offset
;
2482 if (ring_offset
== -1)
2485 ring_offset
= idx
* 16;
2489 if (stream
> 0 && ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2491 /* next_ring_offset after parsing input decls contains total size of
2492 * single vertex data, gs_next_vertex - current vertex index */
2494 ring_offset
+= ctx
->gs_out_ring_offset
* ctx
->gs_next_vertex
;
2496 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2497 output
.gpr
= ctx
->shader
->output
[i
].gpr
;
2498 output
.elem_size
= 3;
2499 output
.comp_mask
= 0xF;
2500 output
.burst_count
= 1;
2503 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
2505 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2510 output
.op
= CF_OP_MEM_RING
; break;
2512 output
.op
= CF_OP_MEM_RING1
; break;
2514 output
.op
= CF_OP_MEM_RING2
; break;
2516 output
.op
= CF_OP_MEM_RING3
; break;
2520 output
.array_base
= ring_offset
>> 2; /* in dwords */
2521 output
.array_size
= 0xfff;
2522 output
.index_gpr
= ctx
->gs_export_gpr_tregs
[effective_stream
];
2524 output
.array_base
= ring_offset
>> 2; /* in dwords */
2525 r600_bytecode_add_output(ctx
->bc
, &output
);
2528 ++ctx
->gs_next_vertex
;
2533 static int r600_fetch_tess_io_info(struct r600_shader_ctx
*ctx
)
2536 struct r600_bytecode_vtx vtx
;
2537 int temp_val
= ctx
->temp_reg
;
2538 /* need to store the TCS output somewhere */
2539 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2541 V_SQ_ALU_SRC_LITERAL
, 0,
2546 /* used by VS/TCS */
2547 if (ctx
->tess_input_info
) {
2548 /* fetch tcs input values into resv space */
2549 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2550 vtx
.op
= FETCH_OP_VFETCH
;
2551 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2552 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2553 vtx
.mega_fetch_count
= 16;
2554 vtx
.data_format
= FMT_32_32_32_32
;
2555 vtx
.num_format_all
= 2;
2556 vtx
.format_comp_all
= 1;
2557 vtx
.use_const_fields
= 0;
2558 vtx
.endian
= r600_endian_swap(32);
2559 vtx
.srf_mode_all
= 1;
2561 vtx
.dst_gpr
= ctx
->tess_input_info
;
2566 vtx
.src_gpr
= temp_val
;
2569 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2574 /* used by TCS/TES */
2575 if (ctx
->tess_output_info
) {
2576 /* fetch tcs output values into resv space */
2577 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2578 vtx
.op
= FETCH_OP_VFETCH
;
2579 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2580 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2581 vtx
.mega_fetch_count
= 16;
2582 vtx
.data_format
= FMT_32_32_32_32
;
2583 vtx
.num_format_all
= 2;
2584 vtx
.format_comp_all
= 1;
2585 vtx
.use_const_fields
= 0;
2586 vtx
.endian
= r600_endian_swap(32);
2587 vtx
.srf_mode_all
= 1;
2589 vtx
.dst_gpr
= ctx
->tess_output_info
;
2594 vtx
.src_gpr
= temp_val
;
2597 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2604 static int emit_lds_vs_writes(struct r600_shader_ctx
*ctx
)
2609 /* fetch tcs input values into input_vals */
2610 ctx
->tess_input_info
= r600_get_temp(ctx
);
2611 ctx
->tess_output_info
= 0;
2612 r
= r600_fetch_tess_io_info(ctx
);
2616 temp_reg
= r600_get_temp(ctx
);
2617 /* dst reg contains LDS address stride * idx */
2618 /* MUL vertexID, vertex_dw_stride */
2619 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
2621 ctx
->tess_input_info
, 1,
2622 0, 1); /* rel id in r0.y? */
2626 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2627 struct r600_bytecode_alu alu
;
2628 int param
= r600_get_lds_unique_index(ctx
->shader
->output
[i
].name
, ctx
->shader
->output
[i
].sid
);
2631 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2634 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2639 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2641 temp_reg
, param
? 1 : 0,
2642 V_SQ_ALU_SRC_LITERAL
, 8);
2647 for (j
= 0; j
< 2; j
++) {
2648 int chan
= (j
== 1) ? 2 : (param
? 1 : 0);
2649 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2650 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2651 alu
.src
[0].sel
= temp_reg
;
2652 alu
.src
[0].chan
= chan
;
2653 alu
.src
[1].sel
= ctx
->shader
->output
[i
].gpr
;
2654 alu
.src
[1].chan
= j
* 2;
2655 alu
.src
[2].sel
= ctx
->shader
->output
[i
].gpr
;
2656 alu
.src
[2].chan
= (j
* 2) + 1;
2660 alu
.is_lds_idx_op
= true;
2661 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2669 static int r600_store_tcs_output(struct r600_shader_ctx
*ctx
)
2671 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2672 const struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
2674 int temp_reg
= r600_get_temp(ctx
);
2675 struct r600_bytecode_alu alu
;
2676 unsigned write_mask
= dst
->Register
.WriteMask
;
2678 if (inst
->Dst
[0].Register
.File
!= TGSI_FILE_OUTPUT
)
2681 r
= get_lds_offset0(ctx
, 1, temp_reg
, dst
->Register
.Dimension
? false : true);
2685 /* the base address is now in temp.x */
2686 r
= r600_get_byte_address(ctx
, temp_reg
,
2687 &inst
->Dst
[0], NULL
, ctx
->tess_output_info
, 1);
2692 lasti
= tgsi_last_instruction(write_mask
);
2693 for (i
= 1; i
<= lasti
; i
++) {
2695 if (!(write_mask
& (1 << i
)))
2697 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2700 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2705 for (i
= 0; i
<= lasti
; i
++) {
2706 if (!(write_mask
& (1 << i
)))
2709 if ((i
== 0 && ((write_mask
& 3) == 3)) ||
2710 (i
== 2 && ((write_mask
& 0xc) == 0xc))) {
2711 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2712 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2713 alu
.src
[0].sel
= temp_reg
;
2714 alu
.src
[0].chan
= i
;
2716 alu
.src
[1].sel
= dst
->Register
.Index
;
2717 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2718 alu
.src
[1].chan
= i
;
2720 alu
.src
[2].sel
= dst
->Register
.Index
;
2721 alu
.src
[2].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2722 alu
.src
[2].chan
= i
+ 1;
2726 alu
.is_lds_idx_op
= true;
2727 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2733 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2734 alu
.op
= LDS_OP2_LDS_WRITE
;
2735 alu
.src
[0].sel
= temp_reg
;
2736 alu
.src
[0].chan
= i
;
2738 alu
.src
[1].sel
= dst
->Register
.Index
;
2739 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2740 alu
.src
[1].chan
= i
;
2742 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
2745 alu
.is_lds_idx_op
= true;
2746 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2753 static int r600_tess_factor_read(struct r600_shader_ctx
*ctx
,
2757 unsigned temp_reg
= r600_get_temp(ctx
);
2758 unsigned name
= ctx
->shader
->output
[output_idx
].name
;
2759 int dreg
= ctx
->shader
->output
[output_idx
].gpr
;
2762 param
= r600_get_lds_unique_index(name
, 0);
2763 r
= get_lds_offset0(ctx
, 1, temp_reg
, true);
2767 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2770 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2774 do_lds_fetch_values(ctx
, temp_reg
, dreg
);
2778 static int r600_emit_tess_factor(struct r600_shader_ctx
*ctx
)
2781 int stride
, outer_comps
, inner_comps
;
2782 int tessinner_idx
= -1, tessouter_idx
= -1;
2784 int temp_reg
= r600_get_temp(ctx
);
2785 int treg
[3] = {-1, -1, -1};
2786 struct r600_bytecode_alu alu
;
2787 struct r600_bytecode_cf
*cf_jump
, *cf_pop
;
2789 /* only execute factor emission for invocation 0 */
2790 /* PRED_SETE_INT __, R0.x, 0 */
2791 memset(&alu
, 0, sizeof(alu
));
2792 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2793 alu
.src
[0].chan
= 2;
2794 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2795 alu
.execute_mask
= 1;
2796 alu
.update_pred
= 1;
2798 r600_bytecode_add_alu_type(ctx
->bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2800 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
2801 cf_jump
= ctx
->bc
->cf_last
;
2803 treg
[0] = r600_get_temp(ctx
);
2804 switch (ctx
->shader
->tcs_prim_mode
) {
2805 case PIPE_PRIM_LINES
:
2806 stride
= 8; /* 2 dwords, 1 vec2 store */
2810 case PIPE_PRIM_TRIANGLES
:
2811 stride
= 16; /* 4 dwords, 1 vec4 store */
2814 treg
[1] = r600_get_temp(ctx
);
2816 case PIPE_PRIM_QUADS
:
2817 stride
= 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2820 treg
[1] = r600_get_temp(ctx
);
2821 treg
[2] = r600_get_temp(ctx
);
2828 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2829 /* TF_WRITE takes index in R.x, value in R.y */
2830 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2831 if (ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_TESSINNER
)
2833 if (ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_TESSOUTER
)
2837 if (tessouter_idx
== -1)
2840 if (tessinner_idx
== -1 && inner_comps
)
2843 if (tessouter_idx
!= -1) {
2844 r
= r600_tess_factor_read(ctx
, tessouter_idx
);
2849 if (tessinner_idx
!= -1) {
2850 r
= r600_tess_factor_read(ctx
, tessinner_idx
);
2855 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2856 /* r.x = relpatchid(r0.y) * tf_stride */
2858 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2859 /* add incoming r0.w to it: t.x = t.x + r0.w */
2860 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
2863 V_SQ_ALU_SRC_LITERAL
, stride
,
2868 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2869 int out_idx
= i
>= outer_comps
? tessinner_idx
: tessouter_idx
;
2870 int out_comp
= i
>= outer_comps
? i
- outer_comps
: i
;
2872 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2873 treg
[i
/ 2], (2 * (i
% 2)),
2875 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2878 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2879 treg
[i
/ 2], 1 + (2 * (i
%2)),
2880 ctx
->shader
->output
[out_idx
].gpr
, out_comp
,
2885 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2886 struct r600_bytecode_gds gds
;
2888 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
2889 gds
.src_gpr
= treg
[i
/ 2];
2890 gds
.src_sel_x
= 2 * (i
% 2);
2891 gds
.src_sel_y
= 1 + (2 * (i
% 2));
2897 gds
.op
= FETCH_OP_TF_WRITE
;
2898 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
2903 // Patch up jump label
2904 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
2905 cf_pop
= ctx
->bc
->cf_last
;
2907 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2908 cf_jump
->pop_count
= 1;
2909 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2910 cf_pop
->pop_count
= 1;
2915 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
2916 struct r600_pipe_shader
*pipeshader
,
2917 union r600_shader_key key
)
2919 struct r600_screen
*rscreen
= rctx
->screen
;
2920 struct r600_shader
*shader
= &pipeshader
->shader
;
2921 struct tgsi_token
*tokens
= pipeshader
->selector
->tokens
;
2922 struct pipe_stream_output_info so
= pipeshader
->selector
->so
;
2923 struct tgsi_full_immediate
*immediate
;
2924 struct r600_shader_ctx ctx
;
2925 struct r600_bytecode_output output
[ARRAY_SIZE(shader
->output
)];
2926 unsigned output_done
, noutput
;
2929 int next_param_base
= 0, next_clip_base
;
2930 int max_color_exports
= MAX2(key
.ps
.nr_cbufs
, 1);
2932 bool ring_outputs
= false;
2933 bool lds_outputs
= false;
2934 bool lds_inputs
= false;
2935 bool pos_emitted
= false;
2937 ctx
.bc
= &shader
->bc
;
2938 ctx
.shader
= shader
;
2939 ctx
.native_integers
= true;
2941 r600_bytecode_init(ctx
.bc
, rscreen
->b
.chip_class
, rscreen
->b
.family
,
2942 rscreen
->has_compressed_msaa_texturing
);
2943 ctx
.tokens
= tokens
;
2944 tgsi_scan_shader(tokens
, &ctx
.info
);
2945 shader
->indirect_files
= ctx
.info
.indirect_files
;
2947 shader
->uses_doubles
= ctx
.info
.uses_doubles
;
2949 indirect_gprs
= ctx
.info
.indirect_files
& ~((1 << TGSI_FILE_CONSTANT
) | (1 << TGSI_FILE_SAMPLER
));
2950 tgsi_parse_init(&ctx
.parse
, tokens
);
2951 ctx
.type
= ctx
.info
.processor
;
2952 shader
->processor_type
= ctx
.type
;
2953 ctx
.bc
->type
= shader
->processor_type
;
2956 case PIPE_SHADER_VERTEX
:
2957 shader
->vs_as_gs_a
= key
.vs
.as_gs_a
;
2958 shader
->vs_as_es
= key
.vs
.as_es
;
2959 shader
->vs_as_ls
= key
.vs
.as_ls
;
2960 if (shader
->vs_as_es
)
2961 ring_outputs
= true;
2962 if (shader
->vs_as_ls
)
2965 case PIPE_SHADER_GEOMETRY
:
2966 ring_outputs
= true;
2968 case PIPE_SHADER_TESS_CTRL
:
2969 shader
->tcs_prim_mode
= key
.tcs
.prim_mode
;
2973 case PIPE_SHADER_TESS_EVAL
:
2974 shader
->tes_as_es
= key
.tes
.as_es
;
2976 if (shader
->tes_as_es
)
2977 ring_outputs
= true;
2979 case PIPE_SHADER_FRAGMENT
:
2980 shader
->two_side
= key
.ps
.color_two_side
;
2986 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
2987 ctx
.gs_for_vs
= &rctx
->gs_shader
->current
->shader
;
2989 ctx
.gs_for_vs
= NULL
;
2992 ctx
.next_ring_offset
= 0;
2993 ctx
.gs_out_ring_offset
= 0;
2994 ctx
.gs_next_vertex
= 0;
2995 ctx
.gs_stream_output_info
= &so
;
2998 ctx
.fixed_pt_position_gpr
= -1;
2999 ctx
.fragcoord_input
= -1;
3000 ctx
.colors_used
= 0;
3001 ctx
.clip_vertex_write
= 0;
3003 shader
->nr_ps_color_exports
= 0;
3004 shader
->nr_ps_max_color_exports
= 0;
3007 /* register allocations */
3008 /* Values [0,127] correspond to GPR[0..127].
3009 * Values [128,159] correspond to constant buffer bank 0
3010 * Values [160,191] correspond to constant buffer bank 1
3011 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3012 * Values [256,287] correspond to constant buffer bank 2 (EG)
3013 * Values [288,319] correspond to constant buffer bank 3 (EG)
3014 * Other special values are shown in the list below.
3015 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3016 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3017 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3018 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3019 * 248 SQ_ALU_SRC_0: special constant 0.0.
3020 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3021 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3022 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3023 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3024 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3025 * 254 SQ_ALU_SRC_PV: previous vector result.
3026 * 255 SQ_ALU_SRC_PS: previous scalar result.
3028 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
3029 ctx
.file_offset
[i
] = 0;
3032 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3033 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3034 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CALL_FS
);
3036 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
3037 if (ctx
.bc
->chip_class
>= EVERGREEN
)
3038 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
3040 ctx
.file_offset
[TGSI_FILE_INPUT
] = allocate_system_value_inputs(&ctx
, ctx
.file_offset
[TGSI_FILE_INPUT
]);
3042 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3043 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3044 ctx
.file_offset
[TGSI_FILE_INPUT
] = 2;
3046 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3047 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3048 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3049 bool add_tesscoord
= false, add_tess_inout
= false;
3050 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3051 for (i
= 0; i
< PIPE_MAX_SHADER_INPUTS
; i
++) {
3052 /* if we have tesscoord save one reg */
3053 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSCOORD
)
3054 add_tesscoord
= true;
3055 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSINNER
||
3056 ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSOUTER
)
3057 add_tess_inout
= true;
3059 if (add_tesscoord
|| add_tess_inout
)
3060 ctx
.file_offset
[TGSI_FILE_INPUT
]++;
3062 ctx
.file_offset
[TGSI_FILE_INPUT
]+=2;
3065 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
3066 ctx
.file_offset
[TGSI_FILE_INPUT
] +
3067 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3068 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
3069 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
3071 /* Outside the GPR range. This will be translated to one of the
3072 * kcache banks later. */
3073 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
3075 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
3076 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
3077 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
3078 ctx
.bc
->index_reg
[0] = ctx
.bc
->ar_reg
+ 1;
3079 ctx
.bc
->index_reg
[1] = ctx
.bc
->ar_reg
+ 2;
3081 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3082 ctx
.tess_input_info
= ctx
.bc
->ar_reg
+ 3;
3083 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 4;
3084 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 5;
3085 } else if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3086 ctx
.tess_input_info
= 0;
3087 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 3;
3088 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 4;
3089 } else if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3090 ctx
.gs_export_gpr_tregs
[0] = ctx
.bc
->ar_reg
+ 3;
3091 ctx
.gs_export_gpr_tregs
[1] = ctx
.bc
->ar_reg
+ 4;
3092 ctx
.gs_export_gpr_tregs
[2] = ctx
.bc
->ar_reg
+ 5;
3093 ctx
.gs_export_gpr_tregs
[3] = ctx
.bc
->ar_reg
+ 6;
3094 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 7;
3096 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 3;
3099 shader
->max_arrays
= 0;
3100 shader
->num_arrays
= 0;
3101 if (indirect_gprs
) {
3103 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_INPUT
)) {
3104 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_INPUT
],
3105 ctx
.file_offset
[TGSI_FILE_OUTPUT
] -
3106 ctx
.file_offset
[TGSI_FILE_INPUT
],
3109 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_OUTPUT
)) {
3110 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3111 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] -
3112 ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3118 ctx
.literals
= NULL
;
3120 shader
->fs_write_all
= ctx
.info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
3121 ctx
.info
.colors_written
== 1;
3122 shader
->vs_position_window_space
= ctx
.info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
3123 shader
->ps_conservative_z
= (uint8_t)ctx
.info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
];
3125 if (shader
->vs_as_gs_a
)
3126 vs_add_primid_output(&ctx
, key
.vs
.prim_id_out
);
3128 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3129 r600_fetch_tess_io_info(&ctx
);
3131 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3132 tgsi_parse_token(&ctx
.parse
);
3133 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3134 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3135 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
3136 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
3137 if(ctx
.literals
== NULL
) {
3141 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
3142 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
3143 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
3144 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
3147 case TGSI_TOKEN_TYPE_DECLARATION
:
3148 r
= tgsi_declaration(&ctx
);
3152 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3153 case TGSI_TOKEN_TYPE_PROPERTY
:
3156 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
3162 shader
->ring_item_sizes
[0] = ctx
.next_ring_offset
;
3163 shader
->ring_item_sizes
[1] = 0;
3164 shader
->ring_item_sizes
[2] = 0;
3165 shader
->ring_item_sizes
[3] = 0;
3167 /* Process two side if needed */
3168 if (shader
->two_side
&& ctx
.colors_used
) {
3169 int i
, count
= ctx
.shader
->ninput
;
3170 unsigned next_lds_loc
= ctx
.shader
->nlds
;
3172 /* additional inputs will be allocated right after the existing inputs,
3173 * we won't need them after the color selection, so we don't need to
3174 * reserve these gprs for the rest of the shader code and to adjust
3175 * output offsets etc. */
3176 int gpr
= ctx
.file_offset
[TGSI_FILE_INPUT
] +
3177 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3179 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3180 if (ctx
.face_gpr
== -1) {
3181 i
= ctx
.shader
->ninput
++;
3182 ctx
.shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
3183 ctx
.shader
->input
[i
].spi_sid
= 0;
3184 ctx
.shader
->input
[i
].gpr
= gpr
++;
3185 ctx
.face_gpr
= ctx
.shader
->input
[i
].gpr
;
3188 for (i
= 0; i
< count
; i
++) {
3189 if (ctx
.shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3190 int ni
= ctx
.shader
->ninput
++;
3191 memcpy(&ctx
.shader
->input
[ni
],&ctx
.shader
->input
[i
], sizeof(struct r600_shader_io
));
3192 ctx
.shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
3193 ctx
.shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
.shader
->input
[ni
]);
3194 ctx
.shader
->input
[ni
].gpr
= gpr
++;
3195 // TGSI to LLVM needs to know the lds position of inputs.
3196 // Non LLVM path computes it later (in process_twoside_color)
3197 ctx
.shader
->input
[ni
].lds_pos
= next_lds_loc
++;
3198 ctx
.shader
->input
[i
].back_color_input
= ni
;
3199 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
3200 if ((r
= evergreen_interp_input(&ctx
, ni
)))
3207 if (shader
->fs_write_all
&& rscreen
->b
.chip_class
>= EVERGREEN
)
3208 shader
->nr_ps_max_color_exports
= 8;
3210 if (ctx
.fragcoord_input
>= 0) {
3211 if (ctx
.bc
->chip_class
== CAYMAN
) {
3212 for (j
= 0 ; j
< 4; j
++) {
3213 struct r600_bytecode_alu alu
;
3214 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3215 alu
.op
= ALU_OP1_RECIP_IEEE
;
3216 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3217 alu
.src
[0].chan
= 3;
3219 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3221 alu
.dst
.write
= (j
== 3);
3223 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3227 struct r600_bytecode_alu alu
;
3228 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3229 alu
.op
= ALU_OP1_RECIP_IEEE
;
3230 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3231 alu
.src
[0].chan
= 3;
3233 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3237 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3242 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3243 struct r600_bytecode_alu alu
;
3246 /* GS thread with no output workaround - emit a cut at start of GS */
3247 if (ctx
.bc
->chip_class
== R600
)
3248 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CUT_VERTEX
);
3250 for (j
= 0; j
< 4; j
++) {
3251 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3252 alu
.op
= ALU_OP1_MOV
;
3253 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
3254 alu
.src
[0].value
= 0;
3255 alu
.dst
.sel
= ctx
.gs_export_gpr_tregs
[j
];
3258 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3264 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3265 r600_fetch_tess_io_info(&ctx
);
3267 if (shader
->two_side
&& ctx
.colors_used
) {
3268 if ((r
= process_twoside_color_inputs(&ctx
)))
3272 tgsi_parse_init(&ctx
.parse
, tokens
);
3273 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3274 tgsi_parse_token(&ctx
.parse
);
3275 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3276 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3277 r
= tgsi_is_supported(&ctx
);
3280 ctx
.max_driver_temp_used
= 0;
3281 /* reserve first tmp for everyone */
3282 r600_get_temp(&ctx
);
3284 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3285 if ((r
= tgsi_split_constant(&ctx
)))
3287 if ((r
= tgsi_split_literal_constant(&ctx
)))
3289 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3290 if ((r
= tgsi_split_gs_inputs(&ctx
)))
3292 } else if (lds_inputs
) {
3293 if ((r
= tgsi_split_lds_inputs(&ctx
)))
3296 if (ctx
.bc
->chip_class
== CAYMAN
)
3297 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
3298 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
3299 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
3301 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
3302 r
= ctx
.inst_info
->process(&ctx
);
3306 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3307 r
= r600_store_tcs_output(&ctx
);
3317 /* Reset the temporary register counter. */
3318 ctx
.max_driver_temp_used
= 0;
3320 noutput
= shader
->noutput
;
3322 if (!ring_outputs
&& ctx
.clip_vertex_write
) {
3323 unsigned clipdist_temp
[2];
3325 clipdist_temp
[0] = r600_get_temp(&ctx
);
3326 clipdist_temp
[1] = r600_get_temp(&ctx
);
3328 /* need to convert a clipvertex write into clipdistance writes and not export
3329 the clip vertex anymore */
3331 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
3332 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3333 shader
->output
[noutput
].gpr
= clipdist_temp
[0];
3335 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3336 shader
->output
[noutput
].gpr
= clipdist_temp
[1];
3339 /* reset spi_sid for clipvertex output to avoid confusing spi */
3340 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
3342 shader
->clip_dist_write
= 0xFF;
3344 for (i
= 0; i
< 8; i
++) {
3348 for (j
= 0; j
< 4; j
++) {
3349 struct r600_bytecode_alu alu
;
3350 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3351 alu
.op
= ALU_OP2_DOT4
;
3352 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
3353 alu
.src
[0].chan
= j
;
3355 alu
.src
[1].sel
= 512 + i
;
3356 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
3357 alu
.src
[1].chan
= j
;
3359 alu
.dst
.sel
= clipdist_temp
[oreg
];
3361 alu
.dst
.write
= (j
== ochan
);
3364 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3371 /* Add stream outputs. */
3372 if (so
.num_outputs
) {
3374 if (!lds_outputs
&& !ring_outputs
&& ctx
.type
== PIPE_SHADER_VERTEX
)
3376 if (!ring_outputs
&& ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3379 emit_streamout(&ctx
, &so
, -1, NULL
);
3381 pipeshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
3382 convert_edgeflag_to_int(&ctx
);
3384 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3385 r600_emit_tess_factor(&ctx
);
3388 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3389 if (ctx
.shader
->noutput
)
3390 emit_lds_vs_writes(&ctx
);
3392 } else if (ring_outputs
) {
3393 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3394 ctx
.gs_export_gpr_tregs
[0] = r600_get_temp(&ctx
);
3395 ctx
.gs_export_gpr_tregs
[1] = -1;
3396 ctx
.gs_export_gpr_tregs
[2] = -1;
3397 ctx
.gs_export_gpr_tregs
[3] = -1;
3399 emit_gs_ring_writes(&ctx
, &so
, -1, FALSE
);
3403 next_clip_base
= shader
->vs_out_misc_write
? 62 : 61;
3405 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
3406 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3407 output
[j
].gpr
= shader
->output
[i
].gpr
;
3408 output
[j
].elem_size
= 3;
3409 output
[j
].swizzle_x
= 0;
3410 output
[j
].swizzle_y
= 1;
3411 output
[j
].swizzle_z
= 2;
3412 output
[j
].swizzle_w
= 3;
3413 output
[j
].burst_count
= 1;
3414 output
[j
].type
= -1;
3415 output
[j
].op
= CF_OP_EXPORT
;
3417 case PIPE_SHADER_VERTEX
:
3418 case PIPE_SHADER_TESS_EVAL
:
3419 switch (shader
->output
[i
].name
) {
3420 case TGSI_SEMANTIC_POSITION
:
3421 output
[j
].array_base
= 60;
3422 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3426 case TGSI_SEMANTIC_PSIZE
:
3427 output
[j
].array_base
= 61;
3428 output
[j
].swizzle_y
= 7;
3429 output
[j
].swizzle_z
= 7;
3430 output
[j
].swizzle_w
= 7;
3431 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3434 case TGSI_SEMANTIC_EDGEFLAG
:
3435 output
[j
].array_base
= 61;
3436 output
[j
].swizzle_x
= 7;
3437 output
[j
].swizzle_y
= 0;
3438 output
[j
].swizzle_z
= 7;
3439 output
[j
].swizzle_w
= 7;
3440 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3443 case TGSI_SEMANTIC_LAYER
:
3444 /* spi_sid is 0 for outputs that are
3445 * not consumed by PS */
3446 if (shader
->output
[i
].spi_sid
) {
3447 output
[j
].array_base
= next_param_base
++;
3448 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3450 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3452 output
[j
].array_base
= 61;
3453 output
[j
].swizzle_x
= 7;
3454 output
[j
].swizzle_y
= 7;
3455 output
[j
].swizzle_z
= 0;
3456 output
[j
].swizzle_w
= 7;
3457 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3460 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
3461 /* spi_sid is 0 for outputs that are
3462 * not consumed by PS */
3463 if (shader
->output
[i
].spi_sid
) {
3464 output
[j
].array_base
= next_param_base
++;
3465 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3467 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3469 output
[j
].array_base
= 61;
3470 output
[j
].swizzle_x
= 7;
3471 output
[j
].swizzle_y
= 7;
3472 output
[j
].swizzle_z
= 7;
3473 output
[j
].swizzle_w
= 0;
3474 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3477 case TGSI_SEMANTIC_CLIPVERTEX
:
3480 case TGSI_SEMANTIC_CLIPDIST
:
3481 output
[j
].array_base
= next_clip_base
++;
3482 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3484 /* spi_sid is 0 for clipdistance outputs that were generated
3485 * for clipvertex - we don't need to pass them to PS */
3486 if (shader
->output
[i
].spi_sid
) {
3488 /* duplicate it as PARAM to pass to the pixel shader */
3489 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3490 output
[j
].array_base
= next_param_base
++;
3491 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3494 case TGSI_SEMANTIC_FOG
:
3495 output
[j
].swizzle_y
= 4; /* 0 */
3496 output
[j
].swizzle_z
= 4; /* 0 */
3497 output
[j
].swizzle_w
= 5; /* 1 */
3499 case TGSI_SEMANTIC_PRIMID
:
3500 output
[j
].swizzle_x
= 2;
3501 output
[j
].swizzle_y
= 4; /* 0 */
3502 output
[j
].swizzle_z
= 4; /* 0 */
3503 output
[j
].swizzle_w
= 4; /* 0 */
3508 case PIPE_SHADER_FRAGMENT
:
3509 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3510 /* never export more colors than the number of CBs */
3511 if (shader
->output
[i
].sid
>= max_color_exports
) {
3516 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3517 output
[j
].array_base
= shader
->output
[i
].sid
;
3518 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3519 shader
->nr_ps_color_exports
++;
3520 if (shader
->fs_write_all
&& (rscreen
->b
.chip_class
>= EVERGREEN
)) {
3521 for (k
= 1; k
< max_color_exports
; k
++) {
3523 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3524 output
[j
].gpr
= shader
->output
[i
].gpr
;
3525 output
[j
].elem_size
= 3;
3526 output
[j
].swizzle_x
= 0;
3527 output
[j
].swizzle_y
= 1;
3528 output
[j
].swizzle_z
= 2;
3529 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3530 output
[j
].burst_count
= 1;
3531 output
[j
].array_base
= k
;
3532 output
[j
].op
= CF_OP_EXPORT
;
3533 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3534 shader
->nr_ps_color_exports
++;
3537 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
3538 output
[j
].array_base
= 61;
3539 output
[j
].swizzle_x
= 2;
3540 output
[j
].swizzle_y
= 7;
3541 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3542 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3543 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
3544 output
[j
].array_base
= 61;
3545 output
[j
].swizzle_x
= 7;
3546 output
[j
].swizzle_y
= 1;
3547 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3548 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3549 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
3550 output
[j
].array_base
= 61;
3551 output
[j
].swizzle_x
= 7;
3552 output
[j
].swizzle_y
= 7;
3553 output
[j
].swizzle_z
= 0;
3554 output
[j
].swizzle_w
= 7;
3555 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3557 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
3562 case PIPE_SHADER_TESS_CTRL
:
3565 R600_ERR("unsupported processor type %d\n", ctx
.type
);
3570 if (output
[j
].type
==-1) {
3571 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3572 output
[j
].array_base
= next_param_base
++;
3576 /* add fake position export */
3577 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && pos_emitted
== false) {
3578 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3580 output
[j
].elem_size
= 3;
3581 output
[j
].swizzle_x
= 7;
3582 output
[j
].swizzle_y
= 7;
3583 output
[j
].swizzle_z
= 7;
3584 output
[j
].swizzle_w
= 7;
3585 output
[j
].burst_count
= 1;
3586 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3587 output
[j
].array_base
= 60;
3588 output
[j
].op
= CF_OP_EXPORT
;
3592 /* add fake param output for vertex shader if no param is exported */
3593 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && next_param_base
== 0) {
3594 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3596 output
[j
].elem_size
= 3;
3597 output
[j
].swizzle_x
= 7;
3598 output
[j
].swizzle_y
= 7;
3599 output
[j
].swizzle_z
= 7;
3600 output
[j
].swizzle_w
= 7;
3601 output
[j
].burst_count
= 1;
3602 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3603 output
[j
].array_base
= 0;
3604 output
[j
].op
= CF_OP_EXPORT
;
3608 /* add fake pixel export */
3609 if (ctx
.type
== PIPE_SHADER_FRAGMENT
&& shader
->nr_ps_color_exports
== 0) {
3610 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3612 output
[j
].elem_size
= 3;
3613 output
[j
].swizzle_x
= 7;
3614 output
[j
].swizzle_y
= 7;
3615 output
[j
].swizzle_z
= 7;
3616 output
[j
].swizzle_w
= 7;
3617 output
[j
].burst_count
= 1;
3618 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3619 output
[j
].array_base
= 0;
3620 output
[j
].op
= CF_OP_EXPORT
;
3622 shader
->nr_ps_color_exports
++;
3627 /* set export done on last export of each type */
3628 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
3629 if (!(output_done
& (1 << output
[i
].type
))) {
3630 output_done
|= (1 << output
[i
].type
);
3631 output
[i
].op
= CF_OP_EXPORT_DONE
;
3634 /* add output to bytecode */
3635 for (i
= 0; i
< noutput
; i
++) {
3636 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
3642 /* add program end */
3643 if (ctx
.bc
->chip_class
== CAYMAN
)
3644 cm_bytecode_add_cf_end(ctx
.bc
);
3646 const struct cf_op_info
*last
= NULL
;
3648 if (ctx
.bc
->cf_last
)
3649 last
= r600_isa_cf(ctx
.bc
->cf_last
->op
);
3651 /* alu clause instructions don't have EOP bit, so add NOP */
3652 if (!last
|| last
->flags
& CF_ALU
|| ctx
.bc
->cf_last
->op
== CF_OP_LOOP_END
|| ctx
.bc
->cf_last
->op
== CF_OP_CALL_FS
|| ctx
.bc
->cf_last
->op
== CF_OP_POP
|| ctx
.bc
->cf_last
->op
== CF_OP_GDS
)
3653 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
3655 ctx
.bc
->cf_last
->end_of_program
= 1;
3658 /* check GPR limit - we have 124 = 128 - 4
3659 * (4 are reserved as alu clause temporary registers) */
3660 if (ctx
.bc
->ngpr
> 124) {
3661 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx
.bc
->ngpr
);
3666 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3667 if ((r
= generate_gs_copy_shader(rctx
, pipeshader
, &so
)))
3672 tgsi_parse_free(&ctx
.parse
);
3676 tgsi_parse_free(&ctx
.parse
);
3680 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
3682 const unsigned tgsi_opcode
=
3683 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3684 R600_ERR("%s tgsi opcode unsupported\n",
3685 tgsi_get_opcode_name(tgsi_opcode
));
3689 static int tgsi_end(struct r600_shader_ctx
*ctx
)
3694 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
3695 const struct r600_shader_src
*shader_src
,
3698 bc_src
->sel
= shader_src
->sel
;
3699 bc_src
->chan
= shader_src
->swizzle
[chan
];
3700 bc_src
->neg
= shader_src
->neg
;
3701 bc_src
->abs
= shader_src
->abs
;
3702 bc_src
->rel
= shader_src
->rel
;
3703 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
3704 bc_src
->kc_bank
= shader_src
->kc_bank
;
3705 bc_src
->kc_rel
= shader_src
->kc_rel
;
3708 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
3714 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
3716 bc_src
->neg
= !bc_src
->neg
;
3719 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
3720 const struct tgsi_full_dst_register
*tgsi_dst
,
3722 struct r600_bytecode_alu_dst
*r600_dst
)
3724 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3726 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
3727 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
3728 r600_dst
->chan
= swizzle
;
3729 r600_dst
->write
= 1;
3730 if (inst
->Instruction
.Saturate
) {
3731 r600_dst
->clamp
= 1;
3733 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
3734 if (tgsi_dst
->Register
.File
== TGSI_FILE_OUTPUT
) {
3738 if (tgsi_dst
->Register
.Indirect
)
3739 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
3743 static int tgsi_op2_64_params(struct r600_shader_ctx
*ctx
, bool singledest
, bool swap
)
3745 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3746 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3747 struct r600_bytecode_alu alu
;
3748 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
3752 switch (write_mask
) {
3770 lasti
= tgsi_last_instruction(write_mask
);
3771 for (i
= 0; i
<= lasti
; i
++) {
3773 if (!(write_mask
& (1 << i
)))
3776 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3779 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3781 alu
.dst
.sel
= ctx
->temp_reg
;
3785 if (i
== 1 || i
== 3)
3788 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3790 alu
.op
= ctx
->inst_info
->op
;
3791 if (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DABS
) {
3792 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3794 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3795 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
3798 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], fp64_switch(i
));
3799 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], fp64_switch(i
));
3802 /* handle some special cases */
3803 if (i
== 1 || i
== 3) {
3804 switch (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
) {
3805 case TGSI_OPCODE_DABS
:
3806 r600_bytecode_src_set_abs(&alu
.src
[0]);
3815 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3821 write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3823 /* move result from temp to dst */
3824 for (i
= 0; i
<= lasti
; i
++) {
3825 if (!(write_mask
& (1 << i
)))
3828 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3829 alu
.op
= ALU_OP1_MOV
;
3830 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3831 alu
.src
[0].sel
= ctx
->temp_reg
;
3832 alu
.src
[0].chan
= use_tmp
- 1;
3833 alu
.last
= (i
== lasti
);
3835 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3843 static int tgsi_op2_64(struct r600_shader_ctx
*ctx
)
3845 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3846 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3847 /* confirm writemasking */
3848 if ((write_mask
& 0x3) != 0x3 &&
3849 (write_mask
& 0xc) != 0xc) {
3850 fprintf(stderr
, "illegal writemask for 64-bit: 0x%x\n", write_mask
);
3853 return tgsi_op2_64_params(ctx
, false, false);
3856 static int tgsi_op2_64_single_dest(struct r600_shader_ctx
*ctx
)
3858 return tgsi_op2_64_params(ctx
, true, false);
3861 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx
*ctx
)
3863 return tgsi_op2_64_params(ctx
, true, true);
3866 static int tgsi_op3_64(struct r600_shader_ctx
*ctx
)
3868 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3869 struct r600_bytecode_alu alu
;
3872 int tmp
= r600_get_temp(ctx
);
3874 for (i
= 0; i
< lasti
+ 1; i
++) {
3876 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3877 alu
.op
= ctx
->inst_info
->op
;
3878 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3879 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
== 3 ? 0 : 1);
3882 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
))
3883 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3892 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3899 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
3901 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3902 struct r600_bytecode_alu alu
;
3903 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3904 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
3905 /* use temp register if trans_only and more than one dst component */
3906 int use_tmp
= trans_only
&& (write_mask
^ (1 << lasti
));
3907 unsigned op
= ctx
->inst_info
->op
;
3909 if (op
== ALU_OP2_MUL_IEEE
&&
3910 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
3913 for (i
= 0; i
<= lasti
; i
++) {
3914 if (!(write_mask
& (1 << i
)))
3917 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3919 alu
.dst
.sel
= ctx
->temp_reg
;
3923 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3927 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3928 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
3931 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
3932 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3934 if (i
== lasti
|| trans_only
) {
3937 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3943 /* move result from temp to dst */
3944 for (i
= 0; i
<= lasti
; i
++) {
3945 if (!(write_mask
& (1 << i
)))
3948 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3949 alu
.op
= ALU_OP1_MOV
;
3950 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3951 alu
.src
[0].sel
= ctx
->temp_reg
;
3952 alu
.src
[0].chan
= i
;
3953 alu
.last
= (i
== lasti
);
3955 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3963 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
3965 return tgsi_op2_s(ctx
, 0, 0);
3968 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
3970 return tgsi_op2_s(ctx
, 1, 0);
3973 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
3975 return tgsi_op2_s(ctx
, 0, 1);
3978 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
3980 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3981 struct r600_bytecode_alu alu
;
3983 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
3985 for (i
= 0; i
< lasti
+ 1; i
++) {
3987 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
3989 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3990 alu
.op
= ctx
->inst_info
->op
;
3992 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3994 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3996 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4001 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4009 static int tgsi_dneg(struct r600_shader_ctx
*ctx
)
4011 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4012 struct r600_bytecode_alu alu
;
4014 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4016 for (i
= 0; i
< lasti
+ 1; i
++) {
4018 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4020 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4021 alu
.op
= ALU_OP1_MOV
;
4023 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4025 if (i
== 1 || i
== 3)
4026 r600_bytecode_src_toggle_neg(&alu
.src
[0]);
4027 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4032 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4040 static int tgsi_dfracexp(struct r600_shader_ctx
*ctx
)
4042 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4043 struct r600_bytecode_alu alu
;
4044 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4046 int firsti
= write_mask
== 0xc ? 2 : 0;
4048 for (i
= 0; i
<= 3; i
++) {
4049 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4050 alu
.op
= ctx
->inst_info
->op
;
4052 alu
.dst
.sel
= ctx
->temp_reg
;
4055 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4056 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
4062 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4067 /* MOV first two channels to writemask dst0 */
4068 for (i
= 0; i
<= 1; i
++) {
4069 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4070 alu
.op
= ALU_OP1_MOV
;
4071 alu
.src
[0].chan
= i
+ 2;
4072 alu
.src
[0].sel
= ctx
->temp_reg
;
4074 tgsi_dst(ctx
, &inst
->Dst
[0], firsti
+ i
, &alu
.dst
);
4075 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> (firsti
+ i
)) & 1;
4077 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4082 for (i
= 0; i
<= 3; i
++) {
4083 if (inst
->Dst
[1].Register
.WriteMask
& (1 << i
)) {
4084 /* MOV third channels to writemask dst1 */
4085 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4086 alu
.op
= ALU_OP1_MOV
;
4087 alu
.src
[0].chan
= 1;
4088 alu
.src
[0].sel
= ctx
->temp_reg
;
4090 tgsi_dst(ctx
, &inst
->Dst
[1], i
, &alu
.dst
);
4092 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4102 static int egcm_int_to_double(struct r600_shader_ctx
*ctx
)
4104 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4105 struct r600_bytecode_alu alu
;
4107 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4109 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_I2D
||
4110 inst
->Instruction
.Opcode
== TGSI_OPCODE_U2D
);
4112 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4113 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4114 alu
.op
= ctx
->inst_info
->op
;
4116 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4117 alu
.dst
.sel
= ctx
->temp_reg
;
4122 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4127 for (i
= 0; i
<= lasti
; i
++) {
4128 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4129 alu
.op
= ALU_OP1_FLT32_TO_FLT64
;
4131 alu
.src
[0].chan
= i
/2;
4133 alu
.src
[0].sel
= ctx
->temp_reg
;
4135 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
4136 alu
.src
[0].value
= 0x0;
4138 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4139 alu
.last
= i
== lasti
;
4141 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4149 static int egcm_double_to_int(struct r600_shader_ctx
*ctx
)
4151 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4152 struct r600_bytecode_alu alu
;
4154 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4156 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_D2I
||
4157 inst
->Instruction
.Opcode
== TGSI_OPCODE_D2U
);
4159 for (i
= 0; i
<= lasti
; i
++) {
4160 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4161 alu
.op
= ALU_OP1_FLT64_TO_FLT32
;
4163 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], fp64_switch(i
));
4165 alu
.dst
.sel
= ctx
->temp_reg
;
4166 alu
.dst
.write
= i
%2 == 0;
4167 alu
.last
= i
== lasti
;
4169 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4174 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4175 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4176 alu
.op
= ctx
->inst_info
->op
;
4178 alu
.src
[0].chan
= i
*2;
4179 alu
.src
[0].sel
= ctx
->temp_reg
;
4180 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4183 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4191 static int cayman_emit_unary_double_raw(struct r600_bytecode
*bc
,
4194 struct r600_shader_src
*src
,
4197 struct r600_bytecode_alu alu
;
4198 const int last_slot
= 3;
4201 /* these have to write the result to X/Y by the looks of it */
4202 for (int i
= 0 ; i
< last_slot
; i
++) {
4203 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4206 r600_bytecode_src(&alu
.src
[0], src
, 1);
4207 r600_bytecode_src(&alu
.src
[1], src
, 0);
4210 r600_bytecode_src_set_abs(&alu
.src
[1]);
4212 alu
.dst
.sel
= dst_reg
;
4214 alu
.dst
.write
= (i
== 0 || i
== 1);
4216 if (bc
->chip_class
!= CAYMAN
|| i
== last_slot
- 1)
4218 r
= r600_bytecode_add_alu(bc
, &alu
);
4226 static int cayman_emit_double_instr(struct r600_shader_ctx
*ctx
)
4228 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4230 struct r600_bytecode_alu alu
;
4231 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4232 int t1
= ctx
->temp_reg
;
4234 /* should only be one src regs */
4235 assert(inst
->Instruction
.NumSrcRegs
== 1);
4237 /* only support one double at a time */
4238 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4239 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4241 r
= cayman_emit_unary_double_raw(
4242 ctx
->bc
, ctx
->inst_info
->op
, t1
,
4244 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DRSQ
||
4245 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DSQRT
);
4249 for (i
= 0 ; i
<= lasti
; i
++) {
4250 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4252 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4253 alu
.op
= ALU_OP1_MOV
;
4254 alu
.src
[0].sel
= t1
;
4255 alu
.src
[0].chan
= (i
== 0 || i
== 2) ? 0 : 1;
4256 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4260 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4267 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
4269 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4271 struct r600_bytecode_alu alu
;
4272 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4274 for (i
= 0 ; i
< last_slot
; i
++) {
4275 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4276 alu
.op
= ctx
->inst_info
->op
;
4277 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4278 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
4280 /* RSQ should take the absolute value of src */
4281 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_RSQ
) {
4282 r600_bytecode_src_set_abs(&alu
.src
[j
]);
4285 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4286 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4288 if (i
== last_slot
- 1)
4290 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4297 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
4299 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4301 struct r600_bytecode_alu alu
;
4302 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4303 int t1
= ctx
->temp_reg
;
4305 for (k
= 0; k
<= lasti
; k
++) {
4306 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
4309 for (i
= 0 ; i
< 4; i
++) {
4310 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4311 alu
.op
= ctx
->inst_info
->op
;
4312 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4313 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
4317 alu
.dst
.write
= (i
== k
);
4320 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4326 for (i
= 0 ; i
<= lasti
; i
++) {
4327 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4329 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4330 alu
.op
= ALU_OP1_MOV
;
4331 alu
.src
[0].sel
= t1
;
4332 alu
.src
[0].chan
= i
;
4333 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4337 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4346 static int cayman_mul_double_instr(struct r600_shader_ctx
*ctx
)
4348 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4350 struct r600_bytecode_alu alu
;
4351 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4352 int t1
= ctx
->temp_reg
;
4354 /* t1 would get overwritten below if we actually tried to
4355 * multiply two pairs of doubles at a time. */
4356 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4357 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4359 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4361 for (i
= 0; i
< 4; i
++) {
4362 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4363 alu
.op
= ctx
->inst_info
->op
;
4364 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4365 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
* 2 + ((i
== 3) ? 0 : 1));
4372 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4377 for (i
= 0; i
<= lasti
; i
++) {
4378 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4380 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4381 alu
.op
= ALU_OP1_MOV
;
4382 alu
.src
[0].sel
= t1
;
4383 alu
.src
[0].chan
= i
;
4384 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4388 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4397 * Emit RECIP_64 + MUL_64 to implement division.
4399 static int cayman_ddiv_instr(struct r600_shader_ctx
*ctx
)
4401 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4403 struct r600_bytecode_alu alu
;
4404 int t1
= ctx
->temp_reg
;
4407 /* Only support one double at a time. This is the same constraint as
4408 * in DMUL lowering. */
4409 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4410 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4412 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4414 r
= cayman_emit_unary_double_raw(ctx
->bc
, ALU_OP2_RECIP_64
, t1
, &ctx
->src
[1], false);
4418 for (int i
= 0; i
< 4; i
++) {
4419 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4420 alu
.op
= ALU_OP2_MUL_64
;
4422 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], k
* 2 + ((i
== 3) ? 0 : 1));
4424 alu
.src
[1].sel
= t1
;
4425 alu
.src
[1].chan
= (i
== 3) ? 0 : 1;
4432 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4437 for (int i
= 0; i
< 2; i
++) {
4438 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4439 alu
.op
= ALU_OP1_MOV
;
4440 alu
.src
[0].sel
= t1
;
4441 alu
.src
[0].chan
= i
;
4442 tgsi_dst(ctx
, &inst
->Dst
[0], k
* 2 + i
, &alu
.dst
);
4446 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4454 * r600 - trunc to -PI..PI range
4455 * r700 - normalize by dividing by 2PI
4458 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
4461 struct r600_bytecode_alu alu
;
4463 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4464 alu
.op
= ALU_OP3_MULADD
;
4468 alu
.dst
.sel
= ctx
->temp_reg
;
4471 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4473 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4474 alu
.src
[1].chan
= 0;
4475 alu
.src
[1].value
= u_bitcast_f2u(0.5f
* M_1_PI
);
4476 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4477 alu
.src
[2].chan
= 0;
4479 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4483 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4484 alu
.op
= ALU_OP1_FRACT
;
4487 alu
.dst
.sel
= ctx
->temp_reg
;
4490 alu
.src
[0].sel
= ctx
->temp_reg
;
4491 alu
.src
[0].chan
= 0;
4493 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4497 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4498 alu
.op
= ALU_OP3_MULADD
;
4502 alu
.dst
.sel
= ctx
->temp_reg
;
4505 alu
.src
[0].sel
= ctx
->temp_reg
;
4506 alu
.src
[0].chan
= 0;
4508 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4509 alu
.src
[1].chan
= 0;
4510 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
4511 alu
.src
[2].chan
= 0;
4513 if (ctx
->bc
->chip_class
== R600
) {
4514 alu
.src
[1].value
= u_bitcast_f2u(2.0f
* M_PI
);
4515 alu
.src
[2].value
= u_bitcast_f2u(-M_PI
);
4517 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4518 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4523 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4529 static int cayman_trig(struct r600_shader_ctx
*ctx
)
4531 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4532 struct r600_bytecode_alu alu
;
4533 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4536 r
= tgsi_setup_trig(ctx
);
4541 for (i
= 0; i
< last_slot
; i
++) {
4542 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4543 alu
.op
= ctx
->inst_info
->op
;
4546 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4547 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4549 alu
.src
[0].sel
= ctx
->temp_reg
;
4550 alu
.src
[0].chan
= 0;
4551 if (i
== last_slot
- 1)
4553 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4560 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
4562 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4563 struct r600_bytecode_alu alu
;
4565 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4567 r
= tgsi_setup_trig(ctx
);
4571 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4572 alu
.op
= ctx
->inst_info
->op
;
4574 alu
.dst
.sel
= ctx
->temp_reg
;
4577 alu
.src
[0].sel
= ctx
->temp_reg
;
4578 alu
.src
[0].chan
= 0;
4580 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4584 /* replicate result */
4585 for (i
= 0; i
< lasti
+ 1; i
++) {
4586 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4589 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4590 alu
.op
= ALU_OP1_MOV
;
4592 alu
.src
[0].sel
= ctx
->temp_reg
;
4593 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4596 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4603 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
4605 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4606 struct r600_bytecode_alu alu
;
4609 /* We'll only need the trig stuff if we are going to write to the
4610 * X or Y components of the destination vector.
4612 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
4613 r
= tgsi_setup_trig(ctx
);
4619 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
4620 if (ctx
->bc
->chip_class
== CAYMAN
) {
4621 for (i
= 0 ; i
< 3; i
++) {
4622 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4623 alu
.op
= ALU_OP1_COS
;
4624 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4630 alu
.src
[0].sel
= ctx
->temp_reg
;
4631 alu
.src
[0].chan
= 0;
4634 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4639 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4640 alu
.op
= ALU_OP1_COS
;
4641 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4643 alu
.src
[0].sel
= ctx
->temp_reg
;
4644 alu
.src
[0].chan
= 0;
4646 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4653 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
4654 if (ctx
->bc
->chip_class
== CAYMAN
) {
4655 for (i
= 0 ; i
< 3; i
++) {
4656 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4657 alu
.op
= ALU_OP1_SIN
;
4658 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4663 alu
.src
[0].sel
= ctx
->temp_reg
;
4664 alu
.src
[0].chan
= 0;
4667 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4672 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4673 alu
.op
= ALU_OP1_SIN
;
4674 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
4676 alu
.src
[0].sel
= ctx
->temp_reg
;
4677 alu
.src
[0].chan
= 0;
4679 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4686 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
4687 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4689 alu
.op
= ALU_OP1_MOV
;
4691 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
4693 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4694 alu
.src
[0].chan
= 0;
4698 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4704 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
4705 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4707 alu
.op
= ALU_OP1_MOV
;
4709 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
4711 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4712 alu
.src
[0].chan
= 0;
4716 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4724 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
4726 const struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4727 struct r600_bytecode_alu alu
;
4730 for (i
= 0; i
< 4; i
++) {
4731 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4732 alu
.op
= ctx
->inst_info
->op
;
4736 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4738 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_KILL
) {
4739 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4742 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4747 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4752 /* kill must be last in ALU */
4753 ctx
->bc
->force_add_cf
= 1;
4754 ctx
->shader
->uses_kill
= TRUE
;
4758 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
4760 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4761 struct r600_bytecode_alu alu
;
4764 /* tmp.x = max(src.y, 0.0) */
4765 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4766 alu
.op
= ALU_OP2_MAX
;
4767 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
4768 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4769 alu
.src
[1].chan
= 1;
4771 alu
.dst
.sel
= ctx
->temp_reg
;
4776 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4780 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
4786 if (ctx
->bc
->chip_class
== CAYMAN
) {
4787 for (i
= 0; i
< 3; i
++) {
4788 /* tmp.z = log(tmp.x) */
4789 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4790 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4791 alu
.src
[0].sel
= ctx
->temp_reg
;
4792 alu
.src
[0].chan
= 0;
4793 alu
.dst
.sel
= ctx
->temp_reg
;
4801 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4806 /* tmp.z = log(tmp.x) */
4807 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4808 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4809 alu
.src
[0].sel
= ctx
->temp_reg
;
4810 alu
.src
[0].chan
= 0;
4811 alu
.dst
.sel
= ctx
->temp_reg
;
4815 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4820 chan
= alu
.dst
.chan
;
4823 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4824 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4825 alu
.op
= ALU_OP3_MUL_LIT
;
4826 alu
.src
[0].sel
= sel
;
4827 alu
.src
[0].chan
= chan
;
4828 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
4829 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
4830 alu
.dst
.sel
= ctx
->temp_reg
;
4835 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4839 if (ctx
->bc
->chip_class
== CAYMAN
) {
4840 for (i
= 0; i
< 3; i
++) {
4841 /* dst.z = exp(tmp.x) */
4842 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4843 alu
.op
= ALU_OP1_EXP_IEEE
;
4844 alu
.src
[0].sel
= ctx
->temp_reg
;
4845 alu
.src
[0].chan
= 0;
4846 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4852 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4857 /* dst.z = exp(tmp.x) */
4858 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4859 alu
.op
= ALU_OP1_EXP_IEEE
;
4860 alu
.src
[0].sel
= ctx
->temp_reg
;
4861 alu
.src
[0].chan
= 0;
4862 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
4864 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4871 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4872 alu
.op
= ALU_OP1_MOV
;
4873 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
4874 alu
.src
[0].chan
= 0;
4875 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4876 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
4877 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4881 /* dst.y = max(src.x, 0.0) */
4882 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4883 alu
.op
= ALU_OP2_MAX
;
4884 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4885 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4886 alu
.src
[1].chan
= 0;
4887 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
4888 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
4889 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4894 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4895 alu
.op
= ALU_OP1_MOV
;
4896 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4897 alu
.src
[0].chan
= 0;
4898 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
4899 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
4901 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4908 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
4910 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4911 struct r600_bytecode_alu alu
;
4914 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4917 * For state trackers other than OpenGL, we'll want to use
4918 * _RECIPSQRT_IEEE instead.
4920 alu
.op
= ALU_OP1_RECIPSQRT_CLAMPED
;
4922 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
4923 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
4924 r600_bytecode_src_set_abs(&alu
.src
[i
]);
4926 alu
.dst
.sel
= ctx
->temp_reg
;
4929 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4932 /* replicate result */
4933 return tgsi_helper_tempx_replicate(ctx
);
4936 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
4938 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4939 struct r600_bytecode_alu alu
;
4942 for (i
= 0; i
< 4; i
++) {
4943 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4944 alu
.src
[0].sel
= ctx
->temp_reg
;
4945 alu
.op
= ALU_OP1_MOV
;
4947 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4948 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4951 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4958 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
4960 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4961 struct r600_bytecode_alu alu
;
4964 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4965 alu
.op
= ctx
->inst_info
->op
;
4966 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
4967 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
4969 alu
.dst
.sel
= ctx
->temp_reg
;
4972 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4975 /* replicate result */
4976 return tgsi_helper_tempx_replicate(ctx
);
4979 static int cayman_pow(struct r600_shader_ctx
*ctx
)
4981 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4983 struct r600_bytecode_alu alu
;
4984 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4986 for (i
= 0; i
< 3; i
++) {
4987 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4988 alu
.op
= ALU_OP1_LOG_IEEE
;
4989 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4990 alu
.dst
.sel
= ctx
->temp_reg
;
4995 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5001 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5002 alu
.op
= ALU_OP2_MUL
;
5003 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5004 alu
.src
[1].sel
= ctx
->temp_reg
;
5005 alu
.dst
.sel
= ctx
->temp_reg
;
5008 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5012 for (i
= 0; i
< last_slot
; i
++) {
5013 /* POW(a,b) = EXP2(b * LOG2(a))*/
5014 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5015 alu
.op
= ALU_OP1_EXP_IEEE
;
5016 alu
.src
[0].sel
= ctx
->temp_reg
;
5018 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5019 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
5020 if (i
== last_slot
- 1)
5022 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5029 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
5031 struct r600_bytecode_alu alu
;
5035 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5036 alu
.op
= ALU_OP1_LOG_IEEE
;
5037 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5038 alu
.dst
.sel
= ctx
->temp_reg
;
5041 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5045 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5046 alu
.op
= ALU_OP2_MUL
;
5047 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5048 alu
.src
[1].sel
= ctx
->temp_reg
;
5049 alu
.dst
.sel
= ctx
->temp_reg
;
5052 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5055 /* POW(a,b) = EXP2(b * LOG2(a))*/
5056 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5057 alu
.op
= ALU_OP1_EXP_IEEE
;
5058 alu
.src
[0].sel
= ctx
->temp_reg
;
5059 alu
.dst
.sel
= ctx
->temp_reg
;
5062 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5065 return tgsi_helper_tempx_replicate(ctx
);
5068 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
5070 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5071 struct r600_bytecode_alu alu
;
5073 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5074 int tmp0
= ctx
->temp_reg
;
5075 int tmp1
= r600_get_temp(ctx
);
5076 int tmp2
= r600_get_temp(ctx
);
5077 int tmp3
= r600_get_temp(ctx
);
5080 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5082 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5083 * 2. tmp0.z = lo (tmp0.x * src2)
5084 * 3. tmp0.w = -tmp0.z
5085 * 4. tmp0.y = hi (tmp0.x * src2)
5086 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5087 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5088 * 7. tmp1.x = tmp0.x - tmp0.w
5089 * 8. tmp1.y = tmp0.x + tmp0.w
5090 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5091 * 10. tmp0.z = hi(tmp0.x * src1) = q
5092 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5094 * 12. tmp0.w = src1 - tmp0.y = r
5095 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5096 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5100 * 15. tmp1.z = tmp0.z + 1 = q + 1
5101 * 16. tmp1.w = tmp0.z - 1 = q - 1
5105 * 15. tmp1.z = tmp0.w - src2 = r - src2
5106 * 16. tmp1.w = tmp0.w + src2 = r + src2
5110 * 17. tmp1.x = tmp1.x & tmp1.y
5112 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5113 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5115 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5116 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5120 * Same as unsigned, using abs values of the operands,
5121 * and fixing the sign of the result in the end.
5124 for (i
= 0; i
< 4; i
++) {
5125 if (!(write_mask
& (1<<i
)))
5130 /* tmp2.x = -src0 */
5131 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5132 alu
.op
= ALU_OP2_SUB_INT
;
5138 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5140 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5143 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5146 /* tmp2.y = -src1 */
5147 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5148 alu
.op
= ALU_OP2_SUB_INT
;
5154 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5156 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5159 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5162 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5163 /* it will be a sign of the quotient */
5166 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5167 alu
.op
= ALU_OP2_XOR_INT
;
5173 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5174 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5177 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5181 /* tmp2.x = |src0| */
5182 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5183 alu
.op
= ALU_OP3_CNDGE_INT
;
5190 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5191 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5192 alu
.src
[2].sel
= tmp2
;
5193 alu
.src
[2].chan
= 0;
5196 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5199 /* tmp2.y = |src1| */
5200 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5201 alu
.op
= ALU_OP3_CNDGE_INT
;
5208 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5209 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5210 alu
.src
[2].sel
= tmp2
;
5211 alu
.src
[2].chan
= 1;
5214 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5219 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5220 if (ctx
->bc
->chip_class
== CAYMAN
) {
5221 /* tmp3.x = u2f(src2) */
5222 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5223 alu
.op
= ALU_OP1_UINT_TO_FLT
;
5230 alu
.src
[0].sel
= tmp2
;
5231 alu
.src
[0].chan
= 1;
5233 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5237 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5240 /* tmp0.x = recip(tmp3.x) */
5241 for (j
= 0 ; j
< 3; j
++) {
5242 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5243 alu
.op
= ALU_OP1_RECIP_IEEE
;
5247 alu
.dst
.write
= (j
== 0);
5249 alu
.src
[0].sel
= tmp3
;
5250 alu
.src
[0].chan
= 0;
5254 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5258 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5259 alu
.op
= ALU_OP2_MUL
;
5261 alu
.src
[0].sel
= tmp0
;
5262 alu
.src
[0].chan
= 0;
5264 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5265 alu
.src
[1].value
= 0x4f800000;
5270 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5274 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5275 alu
.op
= ALU_OP1_FLT_TO_UINT
;
5281 alu
.src
[0].sel
= tmp3
;
5282 alu
.src
[0].chan
= 0;
5285 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5289 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5290 alu
.op
= ALU_OP1_RECIP_UINT
;
5297 alu
.src
[0].sel
= tmp2
;
5298 alu
.src
[0].chan
= 1;
5300 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5304 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5308 /* 2. tmp0.z = lo (tmp0.x * src2) */
5309 if (ctx
->bc
->chip_class
== CAYMAN
) {
5310 for (j
= 0 ; j
< 4; j
++) {
5311 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5312 alu
.op
= ALU_OP2_MULLO_UINT
;
5316 alu
.dst
.write
= (j
== 2);
5318 alu
.src
[0].sel
= tmp0
;
5319 alu
.src
[0].chan
= 0;
5321 alu
.src
[1].sel
= tmp2
;
5322 alu
.src
[1].chan
= 1;
5324 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5327 alu
.last
= (j
== 3);
5328 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5332 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5333 alu
.op
= ALU_OP2_MULLO_UINT
;
5339 alu
.src
[0].sel
= tmp0
;
5340 alu
.src
[0].chan
= 0;
5342 alu
.src
[1].sel
= tmp2
;
5343 alu
.src
[1].chan
= 1;
5345 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5349 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5353 /* 3. tmp0.w = -tmp0.z */
5354 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5355 alu
.op
= ALU_OP2_SUB_INT
;
5361 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5362 alu
.src
[1].sel
= tmp0
;
5363 alu
.src
[1].chan
= 2;
5366 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5369 /* 4. tmp0.y = hi (tmp0.x * src2) */
5370 if (ctx
->bc
->chip_class
== CAYMAN
) {
5371 for (j
= 0 ; j
< 4; j
++) {
5372 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5373 alu
.op
= ALU_OP2_MULHI_UINT
;
5377 alu
.dst
.write
= (j
== 1);
5379 alu
.src
[0].sel
= tmp0
;
5380 alu
.src
[0].chan
= 0;
5383 alu
.src
[1].sel
= tmp2
;
5384 alu
.src
[1].chan
= 1;
5386 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5388 alu
.last
= (j
== 3);
5389 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5393 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5394 alu
.op
= ALU_OP2_MULHI_UINT
;
5400 alu
.src
[0].sel
= tmp0
;
5401 alu
.src
[0].chan
= 0;
5404 alu
.src
[1].sel
= tmp2
;
5405 alu
.src
[1].chan
= 1;
5407 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5411 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5415 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5416 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5417 alu
.op
= ALU_OP3_CNDE_INT
;
5424 alu
.src
[0].sel
= tmp0
;
5425 alu
.src
[0].chan
= 1;
5426 alu
.src
[1].sel
= tmp0
;
5427 alu
.src
[1].chan
= 3;
5428 alu
.src
[2].sel
= tmp0
;
5429 alu
.src
[2].chan
= 2;
5432 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5435 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5436 if (ctx
->bc
->chip_class
== CAYMAN
) {
5437 for (j
= 0 ; j
< 4; j
++) {
5438 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5439 alu
.op
= ALU_OP2_MULHI_UINT
;
5443 alu
.dst
.write
= (j
== 3);
5445 alu
.src
[0].sel
= tmp0
;
5446 alu
.src
[0].chan
= 2;
5448 alu
.src
[1].sel
= tmp0
;
5449 alu
.src
[1].chan
= 0;
5451 alu
.last
= (j
== 3);
5452 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5456 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5457 alu
.op
= ALU_OP2_MULHI_UINT
;
5463 alu
.src
[0].sel
= tmp0
;
5464 alu
.src
[0].chan
= 2;
5466 alu
.src
[1].sel
= tmp0
;
5467 alu
.src
[1].chan
= 0;
5470 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5474 /* 7. tmp1.x = tmp0.x - tmp0.w */
5475 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5476 alu
.op
= ALU_OP2_SUB_INT
;
5482 alu
.src
[0].sel
= tmp0
;
5483 alu
.src
[0].chan
= 0;
5484 alu
.src
[1].sel
= tmp0
;
5485 alu
.src
[1].chan
= 3;
5488 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5491 /* 8. tmp1.y = tmp0.x + tmp0.w */
5492 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5493 alu
.op
= ALU_OP2_ADD_INT
;
5499 alu
.src
[0].sel
= tmp0
;
5500 alu
.src
[0].chan
= 0;
5501 alu
.src
[1].sel
= tmp0
;
5502 alu
.src
[1].chan
= 3;
5505 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5508 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5509 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5510 alu
.op
= ALU_OP3_CNDE_INT
;
5517 alu
.src
[0].sel
= tmp0
;
5518 alu
.src
[0].chan
= 1;
5519 alu
.src
[1].sel
= tmp1
;
5520 alu
.src
[1].chan
= 1;
5521 alu
.src
[2].sel
= tmp1
;
5522 alu
.src
[2].chan
= 0;
5525 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5528 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5529 if (ctx
->bc
->chip_class
== CAYMAN
) {
5530 for (j
= 0 ; j
< 4; j
++) {
5531 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5532 alu
.op
= ALU_OP2_MULHI_UINT
;
5536 alu
.dst
.write
= (j
== 2);
5538 alu
.src
[0].sel
= tmp0
;
5539 alu
.src
[0].chan
= 0;
5542 alu
.src
[1].sel
= tmp2
;
5543 alu
.src
[1].chan
= 0;
5545 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5548 alu
.last
= (j
== 3);
5549 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5553 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5554 alu
.op
= ALU_OP2_MULHI_UINT
;
5560 alu
.src
[0].sel
= tmp0
;
5561 alu
.src
[0].chan
= 0;
5564 alu
.src
[1].sel
= tmp2
;
5565 alu
.src
[1].chan
= 0;
5567 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5571 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5575 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5576 if (ctx
->bc
->chip_class
== CAYMAN
) {
5577 for (j
= 0 ; j
< 4; j
++) {
5578 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5579 alu
.op
= ALU_OP2_MULLO_UINT
;
5583 alu
.dst
.write
= (j
== 1);
5586 alu
.src
[0].sel
= tmp2
;
5587 alu
.src
[0].chan
= 1;
5589 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5592 alu
.src
[1].sel
= tmp0
;
5593 alu
.src
[1].chan
= 2;
5595 alu
.last
= (j
== 3);
5596 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5600 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5601 alu
.op
= ALU_OP2_MULLO_UINT
;
5608 alu
.src
[0].sel
= tmp2
;
5609 alu
.src
[0].chan
= 1;
5611 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5614 alu
.src
[1].sel
= tmp0
;
5615 alu
.src
[1].chan
= 2;
5618 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5622 /* 12. tmp0.w = src1 - tmp0.y = r */
5623 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5624 alu
.op
= ALU_OP2_SUB_INT
;
5631 alu
.src
[0].sel
= tmp2
;
5632 alu
.src
[0].chan
= 0;
5634 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5637 alu
.src
[1].sel
= tmp0
;
5638 alu
.src
[1].chan
= 1;
5641 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5644 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5645 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5646 alu
.op
= ALU_OP2_SETGE_UINT
;
5652 alu
.src
[0].sel
= tmp0
;
5653 alu
.src
[0].chan
= 3;
5655 alu
.src
[1].sel
= tmp2
;
5656 alu
.src
[1].chan
= 1;
5658 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5662 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5665 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5666 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5667 alu
.op
= ALU_OP2_SETGE_UINT
;
5674 alu
.src
[0].sel
= tmp2
;
5675 alu
.src
[0].chan
= 0;
5677 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5680 alu
.src
[1].sel
= tmp0
;
5681 alu
.src
[1].chan
= 1;
5684 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5687 if (mod
) { /* UMOD */
5689 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5690 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5691 alu
.op
= ALU_OP2_SUB_INT
;
5697 alu
.src
[0].sel
= tmp0
;
5698 alu
.src
[0].chan
= 3;
5701 alu
.src
[1].sel
= tmp2
;
5702 alu
.src
[1].chan
= 1;
5704 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5708 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5711 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5712 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5713 alu
.op
= ALU_OP2_ADD_INT
;
5719 alu
.src
[0].sel
= tmp0
;
5720 alu
.src
[0].chan
= 3;
5722 alu
.src
[1].sel
= tmp2
;
5723 alu
.src
[1].chan
= 1;
5725 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5729 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5734 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5735 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5736 alu
.op
= ALU_OP2_ADD_INT
;
5742 alu
.src
[0].sel
= tmp0
;
5743 alu
.src
[0].chan
= 2;
5744 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
5747 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5750 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5751 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5752 alu
.op
= ALU_OP2_ADD_INT
;
5758 alu
.src
[0].sel
= tmp0
;
5759 alu
.src
[0].chan
= 2;
5760 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
5763 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5768 /* 17. tmp1.x = tmp1.x & tmp1.y */
5769 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5770 alu
.op
= ALU_OP2_AND_INT
;
5776 alu
.src
[0].sel
= tmp1
;
5777 alu
.src
[0].chan
= 0;
5778 alu
.src
[1].sel
= tmp1
;
5779 alu
.src
[1].chan
= 1;
5782 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5785 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5786 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5787 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5788 alu
.op
= ALU_OP3_CNDE_INT
;
5795 alu
.src
[0].sel
= tmp1
;
5796 alu
.src
[0].chan
= 0;
5797 alu
.src
[1].sel
= tmp0
;
5798 alu
.src
[1].chan
= mod
? 3 : 2;
5799 alu
.src
[2].sel
= tmp1
;
5800 alu
.src
[2].chan
= 2;
5803 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5806 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5807 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5808 alu
.op
= ALU_OP3_CNDE_INT
;
5816 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5819 alu
.src
[0].sel
= tmp1
;
5820 alu
.src
[0].chan
= 1;
5821 alu
.src
[1].sel
= tmp1
;
5822 alu
.src
[1].chan
= 3;
5823 alu
.src
[2].sel
= tmp0
;
5824 alu
.src
[2].chan
= 2;
5827 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5832 /* fix the sign of the result */
5836 /* tmp0.x = -tmp0.z */
5837 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5838 alu
.op
= ALU_OP2_SUB_INT
;
5844 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5845 alu
.src
[1].sel
= tmp0
;
5846 alu
.src
[1].chan
= 2;
5849 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5852 /* sign of the remainder is the same as the sign of src0 */
5853 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5854 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5855 alu
.op
= ALU_OP3_CNDGE_INT
;
5858 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5860 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5861 alu
.src
[1].sel
= tmp0
;
5862 alu
.src
[1].chan
= 2;
5863 alu
.src
[2].sel
= tmp0
;
5864 alu
.src
[2].chan
= 0;
5867 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5872 /* tmp0.x = -tmp0.z */
5873 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5874 alu
.op
= ALU_OP2_SUB_INT
;
5880 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5881 alu
.src
[1].sel
= tmp0
;
5882 alu
.src
[1].chan
= 2;
5885 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5888 /* fix the quotient sign (same as the sign of src0*src1) */
5889 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5890 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5891 alu
.op
= ALU_OP3_CNDGE_INT
;
5894 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5896 alu
.src
[0].sel
= tmp2
;
5897 alu
.src
[0].chan
= 2;
5898 alu
.src
[1].sel
= tmp0
;
5899 alu
.src
[1].chan
= 2;
5900 alu
.src
[2].sel
= tmp0
;
5901 alu
.src
[2].chan
= 0;
5904 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5912 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
5914 return tgsi_divmod(ctx
, 0, 0);
5917 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
5919 return tgsi_divmod(ctx
, 1, 0);
5922 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
5924 return tgsi_divmod(ctx
, 0, 1);
5927 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
5929 return tgsi_divmod(ctx
, 1, 1);
5933 static int tgsi_f2i(struct r600_shader_ctx
*ctx
)
5935 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5936 struct r600_bytecode_alu alu
;
5938 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5939 int last_inst
= tgsi_last_instruction(write_mask
);
5941 for (i
= 0; i
< 4; i
++) {
5942 if (!(write_mask
& (1<<i
)))
5945 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5946 alu
.op
= ALU_OP1_TRUNC
;
5948 alu
.dst
.sel
= ctx
->temp_reg
;
5952 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5955 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5960 for (i
= 0; i
< 4; i
++) {
5961 if (!(write_mask
& (1<<i
)))
5964 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5965 alu
.op
= ctx
->inst_info
->op
;
5967 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5969 alu
.src
[0].sel
= ctx
->temp_reg
;
5970 alu
.src
[0].chan
= i
;
5972 if (i
== last_inst
|| alu
.op
== ALU_OP1_FLT_TO_UINT
)
5974 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5982 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
5984 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5985 struct r600_bytecode_alu alu
;
5987 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5988 int last_inst
= tgsi_last_instruction(write_mask
);
5991 for (i
= 0; i
< 4; i
++) {
5992 if (!(write_mask
& (1<<i
)))
5995 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5996 alu
.op
= ALU_OP2_SUB_INT
;
5998 alu
.dst
.sel
= ctx
->temp_reg
;
6002 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6003 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
6007 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6012 /* dst = (src >= 0 ? src : tmp) */
6013 for (i
= 0; i
< 4; i
++) {
6014 if (!(write_mask
& (1<<i
)))
6017 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6018 alu
.op
= ALU_OP3_CNDGE_INT
;
6022 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6024 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6025 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6026 alu
.src
[2].sel
= ctx
->temp_reg
;
6027 alu
.src
[2].chan
= i
;
6031 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6038 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
6040 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6041 struct r600_bytecode_alu alu
;
6043 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6044 int last_inst
= tgsi_last_instruction(write_mask
);
6046 /* tmp = (src >= 0 ? src : -1) */
6047 for (i
= 0; i
< 4; i
++) {
6048 if (!(write_mask
& (1<<i
)))
6051 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6052 alu
.op
= ALU_OP3_CNDGE_INT
;
6055 alu
.dst
.sel
= ctx
->temp_reg
;
6059 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6060 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6061 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
6065 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6070 /* dst = (tmp > 0 ? 1 : tmp) */
6071 for (i
= 0; i
< 4; i
++) {
6072 if (!(write_mask
& (1<<i
)))
6075 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6076 alu
.op
= ALU_OP3_CNDGT_INT
;
6080 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6082 alu
.src
[0].sel
= ctx
->temp_reg
;
6083 alu
.src
[0].chan
= i
;
6085 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
6087 alu
.src
[2].sel
= ctx
->temp_reg
;
6088 alu
.src
[2].chan
= i
;
6092 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6101 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
6103 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6104 struct r600_bytecode_alu alu
;
6107 /* tmp = (src > 0 ? 1 : src) */
6108 for (i
= 0; i
< 4; i
++) {
6109 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6110 alu
.op
= ALU_OP3_CNDGT
;
6113 alu
.dst
.sel
= ctx
->temp_reg
;
6116 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6117 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6118 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6122 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6127 /* dst = (-tmp > 0 ? -1 : tmp) */
6128 for (i
= 0; i
< 4; i
++) {
6129 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6130 alu
.op
= ALU_OP3_CNDGT
;
6132 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6134 alu
.src
[0].sel
= ctx
->temp_reg
;
6135 alu
.src
[0].chan
= i
;
6138 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6141 alu
.src
[2].sel
= ctx
->temp_reg
;
6142 alu
.src
[2].chan
= i
;
6146 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6153 static int tgsi_bfi(struct r600_shader_ctx
*ctx
)
6155 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6156 struct r600_bytecode_alu alu
;
6159 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6160 int last_inst
= tgsi_last_instruction(write_mask
);
6164 for (i
= 0; i
< 4; i
++) {
6165 if (!(write_mask
& (1<<i
)))
6168 /* create mask tmp */
6169 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6170 alu
.op
= ALU_OP2_BFM_INT
;
6174 alu
.last
= i
== last_inst
;
6176 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6177 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6179 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6184 t2
= r600_get_temp(ctx
);
6186 for (i
= 0; i
< 4; i
++) {
6187 if (!(write_mask
& (1<<i
)))
6190 /* shift insert left */
6191 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6192 alu
.op
= ALU_OP2_LSHL_INT
;
6196 alu
.last
= i
== last_inst
;
6198 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
6199 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6201 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6206 for (i
= 0; i
< 4; i
++) {
6207 if (!(write_mask
& (1<<i
)))
6210 /* actual bitfield insert */
6211 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6212 alu
.op
= ALU_OP3_BFI_INT
;
6214 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6217 alu
.last
= i
== last_inst
;
6219 alu
.src
[0].sel
= t1
;
6220 alu
.src
[0].chan
= i
;
6221 alu
.src
[1].sel
= t2
;
6222 alu
.src
[1].chan
= i
;
6223 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6225 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6233 static int tgsi_msb(struct r600_shader_ctx
*ctx
)
6235 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6236 struct r600_bytecode_alu alu
;
6239 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6240 int last_inst
= tgsi_last_instruction(write_mask
);
6242 assert(ctx
->inst_info
->op
== ALU_OP1_FFBH_INT
||
6243 ctx
->inst_info
->op
== ALU_OP1_FFBH_UINT
);
6247 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6248 for (i
= 0; i
< 4; i
++) {
6249 if (!(write_mask
& (1<<i
)))
6252 /* t1 = FFBH_INT / FFBH_UINT */
6253 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6254 alu
.op
= ctx
->inst_info
->op
;
6258 alu
.last
= i
== last_inst
;
6260 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6262 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6267 t2
= r600_get_temp(ctx
);
6269 for (i
= 0; i
< 4; i
++) {
6270 if (!(write_mask
& (1<<i
)))
6274 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6275 alu
.op
= ALU_OP2_SUB_INT
;
6279 alu
.last
= i
== last_inst
;
6281 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
6282 alu
.src
[0].value
= 31;
6283 alu
.src
[1].sel
= t1
;
6284 alu
.src
[1].chan
= i
;
6286 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6291 for (i
= 0; i
< 4; i
++) {
6292 if (!(write_mask
& (1<<i
)))
6295 /* result = t1 >= 0 ? t2 : t1 */
6296 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6297 alu
.op
= ALU_OP3_CNDGE_INT
;
6299 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6302 alu
.last
= i
== last_inst
;
6304 alu
.src
[0].sel
= t1
;
6305 alu
.src
[0].chan
= i
;
6306 alu
.src
[1].sel
= t2
;
6307 alu
.src
[1].chan
= i
;
6308 alu
.src
[2].sel
= t1
;
6309 alu
.src
[2].chan
= i
;
6311 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6319 static int tgsi_interp_egcm(struct r600_shader_ctx
*ctx
)
6321 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6322 struct r600_bytecode_alu alu
;
6323 int r
, i
= 0, k
, interp_gpr
, interp_base_chan
, tmp
, lasti
;
6327 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
6329 input
= inst
->Src
[0].Register
.Index
;
6331 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6332 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6333 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6334 location
= TGSI_INTERPOLATE_LOC_CENTER
; /* sample offset will be added explicitly */
6337 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
6340 k
= eg_get_interpolator_index(ctx
->shader
->input
[input
].interpolate
, location
);
6343 interp_gpr
= ctx
->eg_interpolators
[k
].ij_index
/ 2;
6344 interp_base_chan
= 2 * (ctx
->eg_interpolators
[k
].ij_index
% 2);
6346 /* NOTE: currently offset is not perspective correct */
6347 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6348 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6349 int sample_gpr
= -1;
6350 int gradientsH
, gradientsV
;
6351 struct r600_bytecode_tex tex
;
6353 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6354 sample_gpr
= load_sample_position(ctx
, &ctx
->src
[1], ctx
->src
[1].swizzle
[0]);
6357 gradientsH
= r600_get_temp(ctx
);
6358 gradientsV
= r600_get_temp(ctx
);
6359 for (i
= 0; i
< 2; i
++) {
6360 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
6361 tex
.op
= i
== 0 ? FETCH_OP_GET_GRADIENTS_H
: FETCH_OP_GET_GRADIENTS_V
;
6362 tex
.src_gpr
= interp_gpr
;
6363 tex
.src_sel_x
= interp_base_chan
+ 0;
6364 tex
.src_sel_y
= interp_base_chan
+ 1;
6367 tex
.dst_gpr
= i
== 0 ? gradientsH
: gradientsV
;
6372 tex
.inst_mod
= 1; // Use per pixel gradient calculation
6374 tex
.resource_id
= tex
.sampler_id
;
6375 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
6380 for (i
= 0; i
< 2; i
++) {
6381 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6382 alu
.op
= ALU_OP3_MULADD
;
6384 alu
.src
[0].sel
= gradientsH
;
6385 alu
.src
[0].chan
= i
;
6386 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6387 alu
.src
[1].sel
= sample_gpr
;
6388 alu
.src
[1].chan
= 2;
6391 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 0);
6393 alu
.src
[2].sel
= interp_gpr
;
6394 alu
.src
[2].chan
= interp_base_chan
+ i
;
6395 alu
.dst
.sel
= ctx
->temp_reg
;
6399 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6404 for (i
= 0; i
< 2; i
++) {
6405 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6406 alu
.op
= ALU_OP3_MULADD
;
6408 alu
.src
[0].sel
= gradientsV
;
6409 alu
.src
[0].chan
= i
;
6410 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6411 alu
.src
[1].sel
= sample_gpr
;
6412 alu
.src
[1].chan
= 3;
6415 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 1);
6417 alu
.src
[2].sel
= ctx
->temp_reg
;
6418 alu
.src
[2].chan
= i
;
6419 alu
.dst
.sel
= ctx
->temp_reg
;
6423 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6429 tmp
= r600_get_temp(ctx
);
6430 for (i
= 0; i
< 8; i
++) {
6431 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6432 alu
.op
= i
< 4 ? ALU_OP2_INTERP_ZW
: ALU_OP2_INTERP_XY
;
6435 if ((i
> 1 && i
< 6)) {
6441 alu
.dst
.chan
= i
% 4;
6443 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6444 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6445 alu
.src
[0].sel
= ctx
->temp_reg
;
6446 alu
.src
[0].chan
= 1 - (i
% 2);
6448 alu
.src
[0].sel
= interp_gpr
;
6449 alu
.src
[0].chan
= interp_base_chan
+ 1 - (i
% 2);
6451 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
6452 alu
.src
[1].chan
= 0;
6454 alu
.last
= i
% 4 == 3;
6455 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
6457 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6462 // INTERP can't swizzle dst
6463 lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6464 for (i
= 0; i
<= lasti
; i
++) {
6465 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6468 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6469 alu
.op
= ALU_OP1_MOV
;
6470 alu
.src
[0].sel
= tmp
;
6471 alu
.src
[0].chan
= ctx
->src
[0].swizzle
[i
];
6472 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6474 alu
.last
= i
== lasti
;
6475 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6484 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
6486 struct r600_bytecode_alu alu
;
6489 for (i
= 0; i
< 4; i
++) {
6490 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6491 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
6492 alu
.op
= ALU_OP0_NOP
;
6495 alu
.op
= ALU_OP1_MOV
;
6496 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6497 alu
.src
[0].sel
= ctx
->temp_reg
;
6498 alu
.src
[0].chan
= i
;
6503 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6510 static int tgsi_make_src_for_op3(struct r600_shader_ctx
*ctx
,
6511 unsigned temp
, int chan
,
6512 struct r600_bytecode_alu_src
*bc_src
,
6513 const struct r600_shader_src
*shader_src
)
6515 struct r600_bytecode_alu alu
;
6518 r600_bytecode_src(bc_src
, shader_src
, chan
);
6520 /* op3 operands don't support abs modifier */
6522 assert(temp
!=0); /* we actually need the extra register, make sure it is allocated. */
6523 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6524 alu
.op
= ALU_OP1_MOV
;
6526 alu
.dst
.chan
= chan
;
6529 alu
.src
[0] = *bc_src
;
6530 alu
.last
= true; // sufficient?
6531 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6535 memset(bc_src
, 0, sizeof(*bc_src
));
6537 bc_src
->chan
= chan
;
6542 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
6544 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6545 struct r600_bytecode_alu alu
;
6547 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6549 unsigned op
= ctx
->inst_info
->op
;
6551 if (op
== ALU_OP3_MULADD_IEEE
&&
6552 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6553 op
= ALU_OP3_MULADD
;
6555 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6557 if (ctx
->src
[j
].abs
)
6558 temp_regs
[j
] = r600_get_temp(ctx
);
6560 for (i
= 0; i
< lasti
+ 1; i
++) {
6561 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6564 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6566 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6567 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[j
], i
, &alu
.src
[j
], &ctx
->src
[j
]);
6572 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6579 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6586 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
6588 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6589 struct r600_bytecode_alu alu
;
6591 unsigned op
= ctx
->inst_info
->op
;
6592 if (op
== ALU_OP2_DOT4_IEEE
&&
6593 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6596 for (i
= 0; i
< 4; i
++) {
6597 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6599 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6600 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
6603 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6605 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
6606 /* handle some special cases */
6607 switch (inst
->Instruction
.Opcode
) {
6608 case TGSI_OPCODE_DP2
:
6610 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6611 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6614 case TGSI_OPCODE_DP3
:
6616 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6617 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6620 case TGSI_OPCODE_DPH
:
6622 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
6623 alu
.src
[0].chan
= 0;
6633 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6640 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
6643 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6644 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
6645 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
&&
6646 inst
->Src
[index
].Register
.File
!= TGSI_FILE_OUTPUT
) ||
6647 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
||
6648 (inst
->Src
[index
].Register
.File
== TGSI_FILE_INPUT
&& ctx
->type
== PIPE_SHADER_GEOMETRY
);
6651 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
6654 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6655 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
6658 static int do_vtx_fetch_inst(struct r600_shader_ctx
*ctx
, boolean src_requires_loading
)
6660 struct r600_bytecode_vtx vtx
;
6661 struct r600_bytecode_alu alu
;
6662 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6664 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6666 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6667 if (src_requires_loading
) {
6668 for (i
= 0; i
< 4; i
++) {
6669 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6670 alu
.op
= ALU_OP1_MOV
;
6671 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6672 alu
.dst
.sel
= ctx
->temp_reg
;
6677 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6681 src_gpr
= ctx
->temp_reg
;
6684 memset(&vtx
, 0, sizeof(vtx
));
6685 vtx
.op
= FETCH_OP_VFETCH
;
6686 vtx
.buffer_id
= id
+ R600_MAX_CONST_BUFFERS
;
6687 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
6688 vtx
.src_gpr
= src_gpr
;
6689 vtx
.mega_fetch_count
= 16;
6690 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
6691 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
6692 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7; /* SEL_Y */
6693 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7; /* SEL_Z */
6694 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7; /* SEL_W */
6695 vtx
.use_const_fields
= 1;
6697 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
6700 if (ctx
->bc
->chip_class
>= EVERGREEN
)
6703 for (i
= 0; i
< 4; i
++) {
6704 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6705 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6708 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6709 alu
.op
= ALU_OP2_AND_INT
;
6712 alu
.dst
.sel
= vtx
.dst_gpr
;
6715 alu
.src
[0].sel
= vtx
.dst_gpr
;
6716 alu
.src
[0].chan
= i
;
6718 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6719 alu
.src
[1].sel
+= (id
* 2);
6720 alu
.src
[1].chan
= i
% 4;
6721 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6725 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6730 if (inst
->Dst
[0].Register
.WriteMask
& 3) {
6731 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6732 alu
.op
= ALU_OP2_OR_INT
;
6735 alu
.dst
.sel
= vtx
.dst_gpr
;
6738 alu
.src
[0].sel
= vtx
.dst_gpr
;
6739 alu
.src
[0].chan
= 3;
6741 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
+ (id
* 2) + 1;
6742 alu
.src
[1].chan
= 0;
6743 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6746 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6753 static int r600_do_buffer_txq(struct r600_shader_ctx
*ctx
)
6755 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6756 struct r600_bytecode_alu alu
;
6758 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6760 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6761 alu
.op
= ALU_OP1_MOV
;
6762 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6763 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
6764 /* channel 0 or 2 of each word */
6765 alu
.src
[0].sel
+= (id
/ 2);
6766 alu
.src
[0].chan
= (id
% 2) * 2;
6768 /* r600 we have them at channel 2 of the second dword */
6769 alu
.src
[0].sel
+= (id
* 2) + 1;
6770 alu
.src
[0].chan
= 1;
6772 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6773 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
6775 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6781 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
6783 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6784 struct r600_bytecode_tex tex
;
6785 struct r600_bytecode_alu alu
;
6789 bool read_compressed_msaa
= ctx
->bc
->has_compressed_msaa_texturing
&&
6790 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6791 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
6792 inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
6794 bool txf_add_offsets
= inst
->Texture
.NumOffsets
&&
6795 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6796 inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
;
6798 /* Texture fetch instructions can only use gprs as source.
6799 * Also they cannot negate the source or take the absolute value */
6800 const boolean src_requires_loading
= (inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
&&
6801 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQS
&&
6802 tgsi_tex_src_requires_loading(ctx
, 0)) ||
6803 read_compressed_msaa
|| txf_add_offsets
;
6805 boolean src_loaded
= FALSE
;
6806 unsigned sampler_src_reg
= inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ_LZ
? 0 : 1;
6807 int8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
6808 boolean has_txq_cube_array_z
= false;
6809 unsigned sampler_index_mode
;
6811 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
6812 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
6813 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)))
6814 if (inst
->Dst
[0].Register
.WriteMask
& 4) {
6815 ctx
->shader
->has_txq_cube_array_z_comp
= true;
6816 has_txq_cube_array_z
= true;
6819 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
6820 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
6821 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
||
6822 inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
)
6823 sampler_src_reg
= 2;
6825 /* TGSI moves the sampler to src reg 3 for TXD */
6826 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
)
6827 sampler_src_reg
= 3;
6829 sampler_index_mode
= inst
->Src
[sampler_src_reg
].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6831 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6833 if (inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
6834 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
6835 ctx
->shader
->uses_tex_buffers
= true;
6836 return r600_do_buffer_txq(ctx
);
6838 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
6839 if (ctx
->bc
->chip_class
< EVERGREEN
)
6840 ctx
->shader
->uses_tex_buffers
= true;
6841 return do_vtx_fetch_inst(ctx
, src_requires_loading
);
6845 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
6847 /* Add perspective divide */
6848 if (ctx
->bc
->chip_class
== CAYMAN
) {
6850 for (i
= 0; i
< 3; i
++) {
6851 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6852 alu
.op
= ALU_OP1_RECIP_IEEE
;
6853 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6855 alu
.dst
.sel
= ctx
->temp_reg
;
6861 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6868 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6869 alu
.op
= ALU_OP1_RECIP_IEEE
;
6870 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6872 alu
.dst
.sel
= ctx
->temp_reg
;
6873 alu
.dst
.chan
= out_chan
;
6876 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6881 for (i
= 0; i
< 3; i
++) {
6882 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6883 alu
.op
= ALU_OP2_MUL
;
6884 alu
.src
[0].sel
= ctx
->temp_reg
;
6885 alu
.src
[0].chan
= out_chan
;
6886 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6887 alu
.dst
.sel
= ctx
->temp_reg
;
6890 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6894 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6895 alu
.op
= ALU_OP1_MOV
;
6896 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
6897 alu
.src
[0].chan
= 0;
6898 alu
.dst
.sel
= ctx
->temp_reg
;
6902 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6906 src_gpr
= ctx
->temp_reg
;
6910 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
6911 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
6912 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
6913 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
6914 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
6915 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
6917 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
6918 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
6920 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6921 for (i
= 0; i
< 4; i
++) {
6922 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6923 alu
.op
= ALU_OP2_CUBE
;
6924 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
6925 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
6926 alu
.dst
.sel
= ctx
->temp_reg
;
6931 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6936 /* tmp1.z = RCP_e(|tmp1.z|) */
6937 if (ctx
->bc
->chip_class
== CAYMAN
) {
6938 for (i
= 0; i
< 3; i
++) {
6939 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6940 alu
.op
= ALU_OP1_RECIP_IEEE
;
6941 alu
.src
[0].sel
= ctx
->temp_reg
;
6942 alu
.src
[0].chan
= 2;
6944 alu
.dst
.sel
= ctx
->temp_reg
;
6950 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6955 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6956 alu
.op
= ALU_OP1_RECIP_IEEE
;
6957 alu
.src
[0].sel
= ctx
->temp_reg
;
6958 alu
.src
[0].chan
= 2;
6960 alu
.dst
.sel
= ctx
->temp_reg
;
6964 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6969 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6970 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6971 * muladd has no writemask, have to use another temp
6973 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6974 alu
.op
= ALU_OP3_MULADD
;
6977 alu
.src
[0].sel
= ctx
->temp_reg
;
6978 alu
.src
[0].chan
= 0;
6979 alu
.src
[1].sel
= ctx
->temp_reg
;
6980 alu
.src
[1].chan
= 2;
6982 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
6983 alu
.src
[2].chan
= 0;
6984 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
6986 alu
.dst
.sel
= ctx
->temp_reg
;
6990 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6994 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6995 alu
.op
= ALU_OP3_MULADD
;
6998 alu
.src
[0].sel
= ctx
->temp_reg
;
6999 alu
.src
[0].chan
= 1;
7000 alu
.src
[1].sel
= ctx
->temp_reg
;
7001 alu
.src
[1].chan
= 2;
7003 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
7004 alu
.src
[2].chan
= 0;
7005 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
7007 alu
.dst
.sel
= ctx
->temp_reg
;
7012 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7015 /* write initial compare value into Z component
7016 - W src 0 for shadow cube
7017 - X src 1 for shadow cube array */
7018 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7019 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7020 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7021 alu
.op
= ALU_OP1_MOV
;
7022 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
7023 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7025 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7026 alu
.dst
.sel
= ctx
->temp_reg
;
7030 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7035 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7036 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7037 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7038 int mytmp
= r600_get_temp(ctx
);
7039 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7040 alu
.op
= ALU_OP1_MOV
;
7041 alu
.src
[0].sel
= ctx
->temp_reg
;
7042 alu
.src
[0].chan
= 3;
7043 alu
.dst
.sel
= mytmp
;
7047 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7051 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7052 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7053 alu
.op
= ALU_OP3_MULADD
;
7055 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7056 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7057 alu
.src
[1].chan
= 0;
7058 alu
.src
[1].value
= u_bitcast_f2u(8.0f
);
7059 alu
.src
[2].sel
= mytmp
;
7060 alu
.src
[2].chan
= 0;
7061 alu
.dst
.sel
= ctx
->temp_reg
;
7065 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7068 } else if (ctx
->bc
->chip_class
< EVERGREEN
) {
7069 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7070 tex
.op
= FETCH_OP_SET_CUBEMAP_INDEX
;
7071 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7072 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7073 tex
.src_gpr
= r600_get_temp(ctx
);
7078 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7079 tex
.coord_type_x
= 1;
7080 tex
.coord_type_y
= 1;
7081 tex
.coord_type_z
= 1;
7082 tex
.coord_type_w
= 1;
7083 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7084 alu
.op
= ALU_OP1_MOV
;
7085 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7086 alu
.dst
.sel
= tex
.src_gpr
;
7090 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7094 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7101 /* for cube forms of lod and bias we need to route things */
7102 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
||
7103 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
||
7104 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7105 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
7106 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7107 alu
.op
= ALU_OP1_MOV
;
7108 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7109 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
)
7110 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7112 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7113 alu
.dst
.sel
= ctx
->temp_reg
;
7117 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7123 src_gpr
= ctx
->temp_reg
;
7126 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
7127 int temp_h
= 0, temp_v
= 0;
7130 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7131 if (src_loaded
== TRUE
)
7135 for (i
= start_val
; i
< 3; i
++) {
7136 int treg
= r600_get_temp(ctx
);
7145 for (j
= 0; j
< 4; j
++) {
7146 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7147 alu
.op
= ALU_OP1_MOV
;
7148 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
7154 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7159 for (i
= 1; i
< 3; i
++) {
7160 /* set gradients h/v */
7161 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7162 tex
.op
= (i
== 1) ? FETCH_OP_SET_GRADIENTS_H
:
7163 FETCH_OP_SET_GRADIENTS_V
;
7164 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7165 tex
.sampler_index_mode
= sampler_index_mode
;
7166 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7167 tex
.resource_index_mode
= sampler_index_mode
;
7169 tex
.src_gpr
= (i
== 1) ? temp_h
: temp_v
;
7175 tex
.dst_gpr
= r600_get_temp(ctx
); /* just to avoid confusing the asm scheduler */
7176 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7177 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
7178 tex
.coord_type_x
= 1;
7179 tex
.coord_type_y
= 1;
7180 tex
.coord_type_z
= 1;
7181 tex
.coord_type_w
= 1;
7183 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7189 if (src_requires_loading
&& !src_loaded
) {
7190 for (i
= 0; i
< 4; i
++) {
7191 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7192 alu
.op
= ALU_OP1_MOV
;
7193 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
7194 alu
.dst
.sel
= ctx
->temp_reg
;
7199 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7204 src_gpr
= ctx
->temp_reg
;
7207 /* get offset values */
7208 if (inst
->Texture
.NumOffsets
) {
7209 assert(inst
->Texture
.NumOffsets
== 1);
7211 /* The texture offset feature doesn't work with the TXF instruction
7212 * and must be emulated by adding the offset to the texture coordinates. */
7213 if (txf_add_offsets
) {
7214 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
7216 switch (inst
->Texture
.Texture
) {
7217 case TGSI_TEXTURE_3D
:
7218 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7219 alu
.op
= ALU_OP2_ADD_INT
;
7220 alu
.src
[0].sel
= src_gpr
;
7221 alu
.src
[0].chan
= 2;
7222 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7223 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleZ
];
7224 alu
.dst
.sel
= src_gpr
;
7228 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7233 case TGSI_TEXTURE_2D
:
7234 case TGSI_TEXTURE_SHADOW2D
:
7235 case TGSI_TEXTURE_RECT
:
7236 case TGSI_TEXTURE_SHADOWRECT
:
7237 case TGSI_TEXTURE_2D_ARRAY
:
7238 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7239 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7240 alu
.op
= ALU_OP2_ADD_INT
;
7241 alu
.src
[0].sel
= src_gpr
;
7242 alu
.src
[0].chan
= 1;
7243 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7244 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleY
];
7245 alu
.dst
.sel
= src_gpr
;
7249 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7254 case TGSI_TEXTURE_1D
:
7255 case TGSI_TEXTURE_SHADOW1D
:
7256 case TGSI_TEXTURE_1D_ARRAY
:
7257 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7258 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7259 alu
.op
= ALU_OP2_ADD_INT
;
7260 alu
.src
[0].sel
= src_gpr
;
7261 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7262 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleX
];
7263 alu
.dst
.sel
= src_gpr
;
7266 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7270 /* texture offsets do not apply to other texture targets */
7273 switch (inst
->Texture
.Texture
) {
7274 case TGSI_TEXTURE_3D
:
7275 offset_z
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
7277 case TGSI_TEXTURE_2D
:
7278 case TGSI_TEXTURE_SHADOW2D
:
7279 case TGSI_TEXTURE_RECT
:
7280 case TGSI_TEXTURE_SHADOWRECT
:
7281 case TGSI_TEXTURE_2D_ARRAY
:
7282 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7283 offset_y
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
7285 case TGSI_TEXTURE_1D
:
7286 case TGSI_TEXTURE_SHADOW1D
:
7287 case TGSI_TEXTURE_1D_ARRAY
:
7288 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7289 offset_x
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
7294 /* Obtain the sample index for reading a compressed MSAA color texture.
7295 * To read the FMASK, we use the ldfptr instruction, which tells us
7296 * where the samples are stored.
7297 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7298 * which is the identity mapping. Each nibble says which physical sample
7299 * should be fetched to get that sample.
7301 * Assume src.z contains the sample index. It should be modified like this:
7302 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7303 * Then fetch the texel with src.
7305 if (read_compressed_msaa
) {
7306 unsigned sample_chan
= 3;
7307 unsigned temp
= r600_get_temp(ctx
);
7310 /* temp.w = ldfptr() */
7311 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7312 tex
.op
= FETCH_OP_LD
;
7313 tex
.inst_mod
= 1; /* to indicate this is ldfptr */
7314 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7315 tex
.sampler_index_mode
= sampler_index_mode
;
7316 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7317 tex
.resource_index_mode
= sampler_index_mode
;
7318 tex
.src_gpr
= src_gpr
;
7320 tex
.dst_sel_x
= 7; /* mask out these components */
7323 tex
.dst_sel_w
= 0; /* store X */
7328 tex
.offset_x
= offset_x
;
7329 tex
.offset_y
= offset_y
;
7330 tex
.offset_z
= offset_z
;
7331 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7335 /* temp.x = sample_index*4 */
7336 if (ctx
->bc
->chip_class
== CAYMAN
) {
7337 for (i
= 0 ; i
< 4; i
++) {
7338 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7339 alu
.op
= ALU_OP2_MULLO_INT
;
7340 alu
.src
[0].sel
= src_gpr
;
7341 alu
.src
[0].chan
= sample_chan
;
7342 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7343 alu
.src
[1].value
= 4;
7346 alu
.dst
.write
= i
== 0;
7349 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7354 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7355 alu
.op
= ALU_OP2_MULLO_INT
;
7356 alu
.src
[0].sel
= src_gpr
;
7357 alu
.src
[0].chan
= sample_chan
;
7358 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7359 alu
.src
[1].value
= 4;
7364 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7369 /* sample_index = temp.w >> temp.x */
7370 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7371 alu
.op
= ALU_OP2_LSHR_INT
;
7372 alu
.src
[0].sel
= temp
;
7373 alu
.src
[0].chan
= 3;
7374 alu
.src
[1].sel
= temp
;
7375 alu
.src
[1].chan
= 0;
7376 alu
.dst
.sel
= src_gpr
;
7377 alu
.dst
.chan
= sample_chan
;
7380 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7384 /* sample_index & 0xF */
7385 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7386 alu
.op
= ALU_OP2_AND_INT
;
7387 alu
.src
[0].sel
= src_gpr
;
7388 alu
.src
[0].chan
= sample_chan
;
7389 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7390 alu
.src
[1].value
= 0xF;
7391 alu
.dst
.sel
= src_gpr
;
7392 alu
.dst
.chan
= sample_chan
;
7395 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7399 /* visualize the FMASK */
7400 for (i
= 0; i
< 4; i
++) {
7401 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7402 alu
.op
= ALU_OP1_INT_TO_FLT
;
7403 alu
.src
[0].sel
= src_gpr
;
7404 alu
.src
[0].chan
= sample_chan
;
7405 alu
.dst
.sel
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7409 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7417 /* does this shader want a num layers from TXQ for a cube array? */
7418 if (has_txq_cube_array_z
) {
7419 int id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7421 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7422 alu
.op
= ALU_OP1_MOV
;
7424 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
7425 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7426 /* channel 1 or 3 of each word */
7427 alu
.src
[0].sel
+= (id
/ 2);
7428 alu
.src
[0].chan
= ((id
% 2) * 2) + 1;
7430 /* r600 we have them at channel 2 of the second dword */
7431 alu
.src
[0].sel
+= (id
* 2) + 1;
7432 alu
.src
[0].chan
= 2;
7434 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
7435 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
7437 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7440 /* disable writemask from texture instruction */
7441 inst
->Dst
[0].Register
.WriteMask
&= ~4;
7444 opcode
= ctx
->inst_info
->op
;
7445 if (opcode
== FETCH_OP_GATHER4
&&
7446 inst
->TexOffsets
[0].File
!= TGSI_FILE_NULL
&&
7447 inst
->TexOffsets
[0].File
!= TGSI_FILE_IMMEDIATE
) {
7448 opcode
= FETCH_OP_GATHER4_O
;
7450 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7451 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7452 encoded in the instruction are ignored. */
7453 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7454 tex
.op
= FETCH_OP_SET_TEXTURE_OFFSETS
;
7455 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7456 tex
.sampler_index_mode
= sampler_index_mode
;
7457 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7458 tex
.resource_index_mode
= sampler_index_mode
;
7460 tex
.src_gpr
= ctx
->file_offset
[inst
->TexOffsets
[0].File
] + inst
->TexOffsets
[0].Index
;
7461 tex
.src_sel_x
= inst
->TexOffsets
[0].SwizzleX
;
7462 tex
.src_sel_y
= inst
->TexOffsets
[0].SwizzleY
;
7463 tex
.src_sel_z
= inst
->TexOffsets
[0].SwizzleZ
;
7471 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7476 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7477 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7478 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7479 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7480 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
7481 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7482 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7484 case FETCH_OP_SAMPLE
:
7485 opcode
= FETCH_OP_SAMPLE_C
;
7487 case FETCH_OP_SAMPLE_L
:
7488 opcode
= FETCH_OP_SAMPLE_C_L
;
7490 case FETCH_OP_SAMPLE_LB
:
7491 opcode
= FETCH_OP_SAMPLE_C_LB
;
7493 case FETCH_OP_SAMPLE_G
:
7494 opcode
= FETCH_OP_SAMPLE_C_G
;
7496 /* Texture gather variants */
7497 case FETCH_OP_GATHER4
:
7498 opcode
= FETCH_OP_GATHER4_C
;
7500 case FETCH_OP_GATHER4_O
:
7501 opcode
= FETCH_OP_GATHER4_C_O
;
7506 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7509 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7510 tex
.sampler_index_mode
= sampler_index_mode
;
7511 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7512 tex
.resource_index_mode
= sampler_index_mode
;
7513 tex
.src_gpr
= src_gpr
;
7514 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7516 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_DDX_FINE
||
7517 inst
->Instruction
.Opcode
== TGSI_OPCODE_DDY_FINE
) {
7518 tex
.inst_mod
= 1; /* per pixel gradient calculation instead of per 2x2 quad */
7521 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
) {
7522 int8_t texture_component_select
= ctx
->literals
[4 * inst
->Src
[1].Register
.Index
+ inst
->Src
[1].Register
.SwizzleX
];
7523 tex
.inst_mod
= texture_component_select
;
7525 if (ctx
->bc
->chip_class
== CAYMAN
) {
7526 /* GATHER4 result order is different from TGSI TG4 */
7527 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 0 : 7;
7528 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 1 : 7;
7529 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 2 : 7;
7530 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7532 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7533 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7534 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7535 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7538 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LODQ
) {
7539 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7540 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7544 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7551 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7552 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7553 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7554 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7558 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ_LZ
||
7559 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7564 } else if (src_loaded
) {
7570 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
7571 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
7572 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
7573 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
7574 tex
.src_rel
= ctx
->src
[0].rel
;
7577 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
7578 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7579 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7580 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7584 tex
.src_sel_w
= 2; /* route Z compare or Lod value into W */
7587 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
7588 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
7589 tex
.coord_type_x
= 1;
7590 tex
.coord_type_y
= 1;
7592 tex
.coord_type_z
= 1;
7593 tex
.coord_type_w
= 1;
7595 tex
.offset_x
= offset_x
;
7596 tex
.offset_y
= offset_y
;
7597 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
&&
7598 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7599 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)) {
7603 tex
.offset_z
= offset_z
;
7606 /* Put the depth for comparison in W.
7607 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7608 * Some instructions expect the depth in Z. */
7609 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7610 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7611 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7612 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
7613 opcode
!= FETCH_OP_SAMPLE_C_L
&&
7614 opcode
!= FETCH_OP_SAMPLE_C_LB
) {
7615 tex
.src_sel_w
= tex
.src_sel_z
;
7618 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
7619 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
7620 if (opcode
== FETCH_OP_SAMPLE_C_L
||
7621 opcode
== FETCH_OP_SAMPLE_C_LB
) {
7622 /* the array index is read from Y */
7623 tex
.coord_type_y
= 0;
7625 /* the array index is read from Z */
7626 tex
.coord_type_z
= 0;
7627 tex
.src_sel_z
= tex
.src_sel_y
;
7629 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7630 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7631 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7632 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
7633 (ctx
->bc
->chip_class
>= EVERGREEN
)))
7634 /* the array index is read from Z */
7635 tex
.coord_type_z
= 0;
7637 /* mask unused source components */
7638 if (opcode
== FETCH_OP_SAMPLE
|| opcode
== FETCH_OP_GATHER4
) {
7639 switch (inst
->Texture
.Texture
) {
7640 case TGSI_TEXTURE_2D
:
7641 case TGSI_TEXTURE_RECT
:
7645 case TGSI_TEXTURE_1D_ARRAY
:
7649 case TGSI_TEXTURE_1D
:
7657 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7661 /* add shadow ambient support - gallium doesn't do it yet */
7665 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
7667 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7668 struct r600_bytecode_alu alu
;
7669 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7670 unsigned i
, temp_regs
[2];
7673 /* optimize if it's just an equal balance */
7674 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
7675 for (i
= 0; i
< lasti
+ 1; i
++) {
7676 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7679 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7680 alu
.op
= ALU_OP2_ADD
;
7681 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
7682 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7684 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7689 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7697 for (i
= 0; i
< lasti
+ 1; i
++) {
7698 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7701 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7702 alu
.op
= ALU_OP2_ADD
;
7703 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
7704 alu
.src
[0].chan
= 0;
7705 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
7706 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
7707 alu
.dst
.sel
= ctx
->temp_reg
;
7713 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7718 /* (1 - src0) * src2 */
7719 for (i
= 0; i
< lasti
+ 1; i
++) {
7720 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7723 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7724 alu
.op
= ALU_OP2_MUL
;
7725 alu
.src
[0].sel
= ctx
->temp_reg
;
7726 alu
.src
[0].chan
= i
;
7727 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7728 alu
.dst
.sel
= ctx
->temp_reg
;
7734 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7739 /* src0 * src1 + (1 - src0) * src2 */
7740 if (ctx
->src
[0].abs
)
7741 temp_regs
[0] = r600_get_temp(ctx
);
7744 if (ctx
->src
[1].abs
)
7745 temp_regs
[1] = r600_get_temp(ctx
);
7749 for (i
= 0; i
< lasti
+ 1; i
++) {
7750 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7753 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7754 alu
.op
= ALU_OP3_MULADD
;
7756 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
7759 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[1], &ctx
->src
[1]);
7762 alu
.src
[2].sel
= ctx
->temp_reg
;
7763 alu
.src
[2].chan
= i
;
7765 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7770 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7777 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
7779 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7780 struct r600_bytecode_alu alu
;
7782 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7786 if (ctx
->src
[0].abs
&& ctx
->src
[0].neg
) {
7788 ctx
->src
[0].abs
= 0;
7789 ctx
->src
[0].neg
= 0;
7794 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
7796 if (ctx
->src
[j
].abs
)
7797 temp_regs
[j
] = r600_get_temp(ctx
);
7800 for (i
= 0; i
< lasti
+ 1; i
++) {
7801 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7804 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7806 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
7809 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[2], i
, &alu
.src
[1], &ctx
->src
[2]);
7812 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[2], &ctx
->src
[1]);
7815 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7821 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7828 static int tgsi_ucmp(struct r600_shader_ctx
*ctx
)
7830 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7831 struct r600_bytecode_alu alu
;
7833 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7835 for (i
= 0; i
< lasti
+ 1; i
++) {
7836 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7839 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7840 alu
.op
= ALU_OP3_CNDE_INT
;
7841 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
7842 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7843 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
7844 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7850 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7857 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
7859 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7860 static const unsigned int src0_swizzle
[] = {2, 0, 1};
7861 static const unsigned int src1_swizzle
[] = {1, 2, 0};
7862 struct r600_bytecode_alu alu
;
7863 uint32_t use_temp
= 0;
7866 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
7869 for (i
= 0; i
< 4; i
++) {
7870 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7871 alu
.op
= ALU_OP2_MUL
;
7873 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
7874 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src1_swizzle
[i
]);
7876 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
7877 alu
.src
[0].chan
= i
;
7878 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
7879 alu
.src
[1].chan
= i
;
7882 alu
.dst
.sel
= ctx
->temp_reg
;
7888 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7893 for (i
= 0; i
< 4; i
++) {
7894 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7895 alu
.op
= ALU_OP3_MULADD
;
7898 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src1_swizzle
[i
]);
7899 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src0_swizzle
[i
]);
7901 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
7902 alu
.src
[0].chan
= i
;
7903 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
7904 alu
.src
[1].chan
= i
;
7907 alu
.src
[2].sel
= ctx
->temp_reg
;
7909 alu
.src
[2].chan
= i
;
7912 alu
.dst
.sel
= ctx
->temp_reg
;
7914 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7920 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7925 return tgsi_helper_copy(ctx
, inst
);
7929 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
7931 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7932 struct r600_bytecode_alu alu
;
7936 /* result.x = 2^floor(src); */
7937 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
7938 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7940 alu
.op
= ALU_OP1_FLOOR
;
7941 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
7943 alu
.dst
.sel
= ctx
->temp_reg
;
7947 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7951 if (ctx
->bc
->chip_class
== CAYMAN
) {
7952 for (i
= 0; i
< 3; i
++) {
7953 alu
.op
= ALU_OP1_EXP_IEEE
;
7954 alu
.src
[0].sel
= ctx
->temp_reg
;
7955 alu
.src
[0].chan
= 0;
7957 alu
.dst
.sel
= ctx
->temp_reg
;
7959 alu
.dst
.write
= i
== 0;
7961 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7966 alu
.op
= ALU_OP1_EXP_IEEE
;
7967 alu
.src
[0].sel
= ctx
->temp_reg
;
7968 alu
.src
[0].chan
= 0;
7970 alu
.dst
.sel
= ctx
->temp_reg
;
7974 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7980 /* result.y = tmp - floor(tmp); */
7981 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
7982 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7984 alu
.op
= ALU_OP1_FRACT
;
7985 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
7987 alu
.dst
.sel
= ctx
->temp_reg
;
7989 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7998 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8003 /* result.z = RoughApprox2ToX(tmp);*/
8004 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
8005 if (ctx
->bc
->chip_class
== CAYMAN
) {
8006 for (i
= 0; i
< 3; i
++) {
8007 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8008 alu
.op
= ALU_OP1_EXP_IEEE
;
8009 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8011 alu
.dst
.sel
= ctx
->temp_reg
;
8018 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8023 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8024 alu
.op
= ALU_OP1_EXP_IEEE
;
8025 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8027 alu
.dst
.sel
= ctx
->temp_reg
;
8033 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8039 /* result.w = 1.0;*/
8040 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
8041 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8043 alu
.op
= ALU_OP1_MOV
;
8044 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8045 alu
.src
[0].chan
= 0;
8047 alu
.dst
.sel
= ctx
->temp_reg
;
8051 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8055 return tgsi_helper_copy(ctx
, inst
);
8058 static int tgsi_log(struct r600_shader_ctx
*ctx
)
8060 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8061 struct r600_bytecode_alu alu
;
8065 /* result.x = floor(log2(|src|)); */
8066 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
8067 if (ctx
->bc
->chip_class
== CAYMAN
) {
8068 for (i
= 0; i
< 3; i
++) {
8069 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8071 alu
.op
= ALU_OP1_LOG_IEEE
;
8072 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8073 r600_bytecode_src_set_abs(&alu
.src
[0]);
8075 alu
.dst
.sel
= ctx
->temp_reg
;
8081 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8087 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8089 alu
.op
= ALU_OP1_LOG_IEEE
;
8090 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8091 r600_bytecode_src_set_abs(&alu
.src
[0]);
8093 alu
.dst
.sel
= ctx
->temp_reg
;
8097 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8102 alu
.op
= ALU_OP1_FLOOR
;
8103 alu
.src
[0].sel
= ctx
->temp_reg
;
8104 alu
.src
[0].chan
= 0;
8106 alu
.dst
.sel
= ctx
->temp_reg
;
8111 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8116 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8117 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
8119 if (ctx
->bc
->chip_class
== CAYMAN
) {
8120 for (i
= 0; i
< 3; i
++) {
8121 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8123 alu
.op
= ALU_OP1_LOG_IEEE
;
8124 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8125 r600_bytecode_src_set_abs(&alu
.src
[0]);
8127 alu
.dst
.sel
= ctx
->temp_reg
;
8134 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8139 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8141 alu
.op
= ALU_OP1_LOG_IEEE
;
8142 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8143 r600_bytecode_src_set_abs(&alu
.src
[0]);
8145 alu
.dst
.sel
= ctx
->temp_reg
;
8150 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8155 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8157 alu
.op
= ALU_OP1_FLOOR
;
8158 alu
.src
[0].sel
= ctx
->temp_reg
;
8159 alu
.src
[0].chan
= 1;
8161 alu
.dst
.sel
= ctx
->temp_reg
;
8166 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8170 if (ctx
->bc
->chip_class
== CAYMAN
) {
8171 for (i
= 0; i
< 3; i
++) {
8172 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8173 alu
.op
= ALU_OP1_EXP_IEEE
;
8174 alu
.src
[0].sel
= ctx
->temp_reg
;
8175 alu
.src
[0].chan
= 1;
8177 alu
.dst
.sel
= ctx
->temp_reg
;
8184 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8189 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8190 alu
.op
= ALU_OP1_EXP_IEEE
;
8191 alu
.src
[0].sel
= ctx
->temp_reg
;
8192 alu
.src
[0].chan
= 1;
8194 alu
.dst
.sel
= ctx
->temp_reg
;
8199 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8204 if (ctx
->bc
->chip_class
== CAYMAN
) {
8205 for (i
= 0; i
< 3; i
++) {
8206 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8207 alu
.op
= ALU_OP1_RECIP_IEEE
;
8208 alu
.src
[0].sel
= ctx
->temp_reg
;
8209 alu
.src
[0].chan
= 1;
8211 alu
.dst
.sel
= ctx
->temp_reg
;
8218 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8223 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8224 alu
.op
= ALU_OP1_RECIP_IEEE
;
8225 alu
.src
[0].sel
= ctx
->temp_reg
;
8226 alu
.src
[0].chan
= 1;
8228 alu
.dst
.sel
= ctx
->temp_reg
;
8233 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8238 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8240 alu
.op
= ALU_OP2_MUL
;
8242 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8243 r600_bytecode_src_set_abs(&alu
.src
[0]);
8245 alu
.src
[1].sel
= ctx
->temp_reg
;
8246 alu
.src
[1].chan
= 1;
8248 alu
.dst
.sel
= ctx
->temp_reg
;
8253 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8258 /* result.z = log2(|src|);*/
8259 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
8260 if (ctx
->bc
->chip_class
== CAYMAN
) {
8261 for (i
= 0; i
< 3; i
++) {
8262 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8264 alu
.op
= ALU_OP1_LOG_IEEE
;
8265 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8266 r600_bytecode_src_set_abs(&alu
.src
[0]);
8268 alu
.dst
.sel
= ctx
->temp_reg
;
8275 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8280 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8282 alu
.op
= ALU_OP1_LOG_IEEE
;
8283 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8284 r600_bytecode_src_set_abs(&alu
.src
[0]);
8286 alu
.dst
.sel
= ctx
->temp_reg
;
8291 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8297 /* result.w = 1.0; */
8298 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
8299 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8301 alu
.op
= ALU_OP1_MOV
;
8302 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8303 alu
.src
[0].chan
= 0;
8305 alu
.dst
.sel
= ctx
->temp_reg
;
8310 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8315 return tgsi_helper_copy(ctx
, inst
);
8318 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
8320 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8321 struct r600_bytecode_alu alu
;
8323 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8324 unsigned reg
= get_address_file_reg(ctx
, inst
->Dst
[0].Register
.Index
);
8326 assert(inst
->Dst
[0].Register
.Index
< 3);
8327 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8329 switch (inst
->Instruction
.Opcode
) {
8330 case TGSI_OPCODE_ARL
:
8331 alu
.op
= ALU_OP1_FLT_TO_INT_FLOOR
;
8333 case TGSI_OPCODE_ARR
:
8334 alu
.op
= ALU_OP1_FLT_TO_INT
;
8336 case TGSI_OPCODE_UARL
:
8337 alu
.op
= ALU_OP1_MOV
;
8344 for (i
= 0; i
<= lasti
; ++i
) {
8345 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8347 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8348 alu
.last
= i
== lasti
;
8352 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8357 if (inst
->Dst
[0].Register
.Index
> 0)
8358 ctx
->bc
->index_loaded
[inst
->Dst
[0].Register
.Index
- 1] = 0;
8360 ctx
->bc
->ar_loaded
= 0;
8364 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
8366 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8367 struct r600_bytecode_alu alu
;
8369 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8371 switch (inst
->Instruction
.Opcode
) {
8372 case TGSI_OPCODE_ARL
:
8373 memset(&alu
, 0, sizeof(alu
));
8374 alu
.op
= ALU_OP1_FLOOR
;
8375 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8377 for (i
= 0; i
<= lasti
; ++i
) {
8378 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8380 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8381 alu
.last
= i
== lasti
;
8382 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8387 memset(&alu
, 0, sizeof(alu
));
8388 alu
.op
= ALU_OP1_FLT_TO_INT
;
8389 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
8390 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8392 /* FLT_TO_INT is trans-only on r600/r700 */
8394 for (i
= 0; i
<= lasti
; ++i
) {
8396 alu
.src
[0].chan
= i
;
8397 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8401 case TGSI_OPCODE_ARR
:
8402 memset(&alu
, 0, sizeof(alu
));
8403 alu
.op
= ALU_OP1_FLT_TO_INT
;
8404 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8406 /* FLT_TO_INT is trans-only on r600/r700 */
8408 for (i
= 0; i
<= lasti
; ++i
) {
8409 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8411 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8412 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8417 case TGSI_OPCODE_UARL
:
8418 memset(&alu
, 0, sizeof(alu
));
8419 alu
.op
= ALU_OP1_MOV
;
8420 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8422 for (i
= 0; i
<= lasti
; ++i
) {
8423 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8425 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8426 alu
.last
= i
== lasti
;
8427 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8437 ctx
->bc
->ar_loaded
= 0;
8441 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
8443 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8444 struct r600_bytecode_alu alu
;
8447 for (i
= 0; i
< 4; i
++) {
8448 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8450 alu
.op
= ALU_OP2_MUL
;
8451 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8453 if (i
== 0 || i
== 3) {
8454 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8456 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8459 if (i
== 0 || i
== 2) {
8460 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
8462 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
8466 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8473 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
, int alu_type
)
8475 struct r600_bytecode_alu alu
;
8478 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8480 alu
.execute_mask
= 1;
8481 alu
.update_pred
= 1;
8483 alu
.dst
.sel
= ctx
->temp_reg
;
8487 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8488 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
8489 alu
.src
[1].chan
= 0;
8493 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, alu_type
);
8499 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
8501 unsigned force_pop
= ctx
->bc
->force_add_cf
;
8505 if (ctx
->bc
->cf_last
) {
8506 if (ctx
->bc
->cf_last
->op
== CF_OP_ALU
)
8508 else if (ctx
->bc
->cf_last
->op
== CF_OP_ALU_POP_AFTER
)
8513 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP_AFTER
;
8514 ctx
->bc
->force_add_cf
= 1;
8515 } else if (alu_pop
== 2) {
8516 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP2_AFTER
;
8517 ctx
->bc
->force_add_cf
= 1;
8524 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
8525 ctx
->bc
->cf_last
->pop_count
= pops
;
8526 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8532 static inline void callstack_update_max_depth(struct r600_shader_ctx
*ctx
,
8535 struct r600_stack_info
*stack
= &ctx
->bc
->stack
;
8536 unsigned elements
, entries
;
8538 unsigned entry_size
= stack
->entry_size
;
8540 elements
= (stack
->loop
+ stack
->push_wqm
) * entry_size
;
8541 elements
+= stack
->push
;
8543 switch (ctx
->bc
->chip_class
) {
8546 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8547 * the stack must be reserved to hold the current active/continue
8549 if (reason
== FC_PUSH_VPM
) {
8555 /* r9xx: any stack operation on empty stack consumes 2 additional
8560 /* FIXME: do the two elements added above cover the cases for the
8564 /* r8xx+: 2 extra elements are not always required, but one extra
8565 * element must be added for each of the following cases:
8566 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8568 * (Currently we don't use ALU_ELSE_AFTER.)
8569 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8570 * PUSH instruction executed.
8572 * NOTE: it seems we also need to reserve additional element in some
8573 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8574 * then STACK_SIZE should be 2 instead of 1 */
8575 if (reason
== FC_PUSH_VPM
) {
8585 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8586 * for all chips, so we use 4 in the final formula, not the real entry_size
8590 entries
= (elements
+ (entry_size
- 1)) / entry_size
;
8592 if (entries
> stack
->max_entries
)
8593 stack
->max_entries
= entries
;
8596 static inline void callstack_pop(struct r600_shader_ctx
*ctx
, unsigned reason
)
8600 --ctx
->bc
->stack
.push
;
8601 assert(ctx
->bc
->stack
.push
>= 0);
8604 --ctx
->bc
->stack
.push_wqm
;
8605 assert(ctx
->bc
->stack
.push_wqm
>= 0);
8608 --ctx
->bc
->stack
.loop
;
8609 assert(ctx
->bc
->stack
.loop
>= 0);
8617 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
)
8621 ++ctx
->bc
->stack
.push
;
8624 ++ctx
->bc
->stack
.push_wqm
;
8626 ++ctx
->bc
->stack
.loop
;
8632 callstack_update_max_depth(ctx
, reason
);
8635 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
8637 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
8639 sp
->mid
= realloc((void *)sp
->mid
,
8640 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
8641 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
8645 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
8647 assert(ctx
->bc
->fc_sp
< ARRAY_SIZE(ctx
->bc
->fc_stack
));
8648 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
8649 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
8653 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
8655 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1];
8665 static int emit_return(struct r600_shader_ctx
*ctx
)
8667 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_RETURN
));
8671 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
8674 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
));
8675 ctx
->bc
->cf_last
->pop_count
= pops
;
8676 /* XXX work out offset */
8680 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
8685 static void emit_testflag(struct r600_shader_ctx
*ctx
)
8690 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
8693 emit_jump_to_offset(ctx
, 1, 4);
8694 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
8695 pops(ctx
, ifidx
+ 1);
8699 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
8703 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
8704 ctx
->bc
->cf_last
->pop_count
= 1;
8706 fc_set_mid(ctx
, fc_sp
);
8712 static int emit_if(struct r600_shader_ctx
*ctx
, int opcode
)
8714 int alu_type
= CF_OP_ALU_PUSH_BEFORE
;
8716 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8717 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8718 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8719 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8720 if (ctx
->bc
->chip_class
== CAYMAN
&& ctx
->bc
->stack
.loop
> 1) {
8721 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_PUSH
);
8722 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8723 alu_type
= CF_OP_ALU
;
8726 emit_logic_pred(ctx
, opcode
, alu_type
);
8728 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
8730 fc_pushlevel(ctx
, FC_IF
);
8732 callstack_push(ctx
, FC_PUSH_VPM
);
8736 static int tgsi_if(struct r600_shader_ctx
*ctx
)
8738 return emit_if(ctx
, ALU_OP2_PRED_SETNE
);
8741 static int tgsi_uif(struct r600_shader_ctx
*ctx
)
8743 return emit_if(ctx
, ALU_OP2_PRED_SETNE_INT
);
8746 static int tgsi_else(struct r600_shader_ctx
*ctx
)
8748 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_ELSE
);
8749 ctx
->bc
->cf_last
->pop_count
= 1;
8751 fc_set_mid(ctx
, ctx
->bc
->fc_sp
- 1);
8752 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
8756 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
8759 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_IF
) {
8760 R600_ERR("if/endif unbalanced in shader\n");
8764 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
== NULL
) {
8765 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8766 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->pop_count
= 1;
8768 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8772 callstack_pop(ctx
, FC_PUSH_VPM
);
8776 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
8778 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8779 * limited to 4096 iterations, like the other LOOP_* instructions. */
8780 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_START_DX10
);
8782 fc_pushlevel(ctx
, FC_LOOP
);
8784 /* check stack depth */
8785 callstack_push(ctx
, FC_LOOP
);
8789 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
8793 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_END
);
8795 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_LOOP
) {
8796 R600_ERR("loop/endloop in shader code are not paired.\n");
8800 /* fixup loop pointers - from r600isa
8801 LOOP END points to CF after LOOP START,
8802 LOOP START point to CF after LOOP END
8803 BRK/CONT point to LOOP END CF
8805 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->id
+ 2;
8807 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8809 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].num_mid
; i
++) {
8810 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
8812 /* XXX add LOOPRET support */
8814 callstack_pop(ctx
, FC_LOOP
);
8818 static int tgsi_loop_breakc(struct r600_shader_ctx
*ctx
)
8823 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
8825 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
- 1].type
)
8829 R600_ERR("BREAKC not inside loop/endloop pair\n");
8833 if (ctx
->bc
->chip_class
== EVERGREEN
&&
8834 ctx
->bc
->family
!= CHIP_CYPRESS
&&
8835 ctx
->bc
->family
!= CHIP_JUNIPER
) {
8836 /* HW bug: ALU_BREAK does not save the active mask correctly */
8841 r
= r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_BREAK
);
8844 fc_set_mid(ctx
, fscp
- 1);
8846 return tgsi_endif(ctx
);
8848 r
= emit_logic_pred(ctx
, ALU_OP2_PRED_SETE_INT
, CF_OP_ALU_BREAK
);
8851 fc_set_mid(ctx
, fscp
- 1);
8857 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
8861 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
8863 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
- 1].type
)
8868 R600_ERR("Break not inside loop/endloop pair\n");
8872 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
8874 fc_set_mid(ctx
, fscp
- 1);
8879 static int tgsi_gs_emit(struct r600_shader_ctx
*ctx
)
8881 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8882 int stream
= ctx
->literals
[inst
->Src
[0].Register
.Index
* 4 + inst
->Src
[0].Register
.SwizzleX
];
8885 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
8886 emit_gs_ring_writes(ctx
, ctx
->gs_stream_output_info
, stream
, TRUE
);
8888 r
= r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
8890 ctx
->bc
->cf_last
->count
= stream
; // Count field for CUT/EMIT_VERTEX indicates which stream
8891 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
8892 return emit_inc_ring_offset(ctx
, stream
, TRUE
);
8897 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
8899 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8900 struct r600_bytecode_alu alu
;
8902 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8905 for (i
= 0; i
< lasti
+ 1; i
++) {
8906 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8909 if (ctx
->bc
->chip_class
== CAYMAN
) {
8910 for (j
= 0 ; j
< 4; j
++) {
8911 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8913 alu
.op
= ALU_OP2_MULLO_UINT
;
8914 for (k
= 0; k
< inst
->Instruction
.NumSrcRegs
; k
++) {
8915 r600_bytecode_src(&alu
.src
[k
], &ctx
->src
[k
], i
);
8918 alu
.dst
.sel
= ctx
->temp_reg
;
8919 alu
.dst
.write
= (j
== i
);
8922 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8927 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8930 alu
.dst
.sel
= ctx
->temp_reg
;
8933 alu
.op
= ALU_OP2_MULLO_UINT
;
8934 for (j
= 0; j
< 2; j
++) {
8935 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
8939 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8946 for (i
= 0; i
< lasti
+ 1; i
++) {
8947 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8950 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8951 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8953 alu
.op
= ALU_OP2_ADD_INT
;
8955 alu
.src
[0].sel
= ctx
->temp_reg
;
8956 alu
.src
[0].chan
= i
;
8958 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8962 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8969 static int tgsi_pk2h(struct r600_shader_ctx
*ctx
)
8971 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8972 struct r600_bytecode_alu alu
;
8974 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8976 /* temp.xy = f32_to_f16(src) */
8977 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8978 alu
.op
= ALU_OP1_FLT32_TO_FLT16
;
8980 alu
.dst
.sel
= ctx
->temp_reg
;
8982 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8983 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8987 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
8989 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8993 /* dst.x = temp.y * 0x10000 + temp.x */
8994 for (i
= 0; i
< lasti
+ 1; i
++) {
8995 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8998 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8999 alu
.op
= ALU_OP3_MULADD_UINT24
;
9001 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9002 alu
.last
= i
== lasti
;
9003 alu
.src
[0].sel
= ctx
->temp_reg
;
9004 alu
.src
[0].chan
= 1;
9005 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9006 alu
.src
[1].value
= 0x10000;
9007 alu
.src
[2].sel
= ctx
->temp_reg
;
9008 alu
.src
[2].chan
= 0;
9009 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9017 static int tgsi_up2h(struct r600_shader_ctx
*ctx
)
9019 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9020 struct r600_bytecode_alu alu
;
9022 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9024 /* temp.x = src.x */
9025 /* note: no need to mask out the high bits */
9026 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9027 alu
.op
= ALU_OP1_MOV
;
9029 alu
.dst
.sel
= ctx
->temp_reg
;
9031 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9032 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9036 /* temp.y = src.x >> 16 */
9037 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9038 alu
.op
= ALU_OP2_LSHR_INT
;
9040 alu
.dst
.sel
= ctx
->temp_reg
;
9042 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9043 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9044 alu
.src
[1].value
= 16;
9046 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9050 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9051 for (i
= 0; i
< lasti
+ 1; i
++) {
9052 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9054 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9055 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9056 alu
.op
= ALU_OP1_FLT16_TO_FLT32
;
9057 alu
.src
[0].sel
= ctx
->temp_reg
;
9058 alu
.src
[0].chan
= i
% 2;
9059 alu
.last
= i
== lasti
;
9060 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9068 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
9069 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
9070 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9071 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9074 * For state trackers other than OpenGL, we'll want to use
9075 * _RECIP_IEEE instead.
9077 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
9079 [TGSI_OPCODE_RSQ
] = { ALU_OP0_NOP
, tgsi_rsq
},
9080 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9081 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9082 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9083 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9084 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9085 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9086 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9087 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN
, tgsi_op2
},
9088 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX
, tgsi_op2
},
9089 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9090 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9091 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9092 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9093 [TGSI_OPCODE_FMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9094 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
9095 [TGSI_OPCODE_DP2A
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9096 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9097 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9098 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9099 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9100 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9101 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9102 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
9103 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
9104 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
9105 [TGSI_OPCODE_XPD
] = { ALU_OP0_NOP
, tgsi_xpd
},
9106 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9107 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
9108 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9109 [TGSI_OPCODE_DPH
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9110 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
9111 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9112 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9113 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9114 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9115 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9116 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9117 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9118 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9119 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9120 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9121 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9122 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
9123 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9124 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9125 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9126 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9127 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9128 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9129 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9130 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9131 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9132 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9133 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9134 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9135 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
9136 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9137 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9138 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9139 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9140 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9141 [TGSI_OPCODE_SCS
] = { ALU_OP0_NOP
, tgsi_scs
},
9142 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9143 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9144 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9145 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9146 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9147 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9148 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9149 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9150 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9151 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9152 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9153 [TGSI_OPCODE_DDX_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9154 [TGSI_OPCODE_DDY_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9155 [TGSI_OPCODE_PUSHA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9156 [TGSI_OPCODE_POPA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9157 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9158 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
9159 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9160 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9161 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2_trans
},
9162 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9163 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9164 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9165 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9166 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9167 [TGSI_OPCODE_SAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9168 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9169 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9170 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9171 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9172 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9173 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9174 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9175 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9176 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9177 [TGSI_OPCODE_TXQ_LZ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9178 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9179 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9180 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9181 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9182 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9183 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9184 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9185 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9186 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9187 [TGSI_OPCODE_CALLNZ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9188 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9189 [TGSI_OPCODE_BREAKC
] = { ALU_OP0_NOP
, tgsi_loop_breakc
},
9190 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9191 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9192 [TGSI_OPCODE_DFMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9193 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2_trans
},
9194 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9195 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9196 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9197 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9198 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9199 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2_trans
},
9200 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9201 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2_trans
},
9202 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
9203 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9204 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9205 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9206 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9207 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9208 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9209 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
9210 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9211 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9212 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2_trans
},
9213 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9214 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2_swap
},
9215 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9216 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9217 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9218 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9219 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9220 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9221 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9222 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9223 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9224 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9225 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9226 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9227 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9228 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9229 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9230 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9231 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_r600_arl
},
9232 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9233 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9234 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9235 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9236 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9237 [TGSI_OPCODE_MFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9238 [TGSI_OPCODE_LFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9239 [TGSI_OPCODE_SFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9240 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9241 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9242 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9243 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9244 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9245 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9246 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9247 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9248 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9249 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9250 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9251 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9252 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9253 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9254 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
9255 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
9256 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_unsupported
},
9257 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_unsupported
},
9258 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_unsupported
},
9259 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_unsupported
},
9260 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9261 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_unsupported
},
9262 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_unsupported
},
9263 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_unsupported
},
9264 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_unsupported
},
9265 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_unsupported
},
9266 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9267 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9268 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9269 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9272 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
9273 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9274 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9275 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9276 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
9277 [TGSI_OPCODE_RSQ
] = { ALU_OP1_RECIPSQRT_IEEE
, tgsi_rsq
},
9278 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9279 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9280 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9281 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9282 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9283 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9284 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9285 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN
, tgsi_op2
},
9286 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX
, tgsi_op2
},
9287 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9288 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9289 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9290 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9291 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
9292 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
9293 [TGSI_OPCODE_DP2A
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9294 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9295 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9296 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9297 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9298 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9299 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9300 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
9301 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
9302 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
9303 [TGSI_OPCODE_XPD
] = { ALU_OP0_NOP
, tgsi_xpd
},
9304 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9305 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
9306 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9307 [TGSI_OPCODE_DPH
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9308 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
9309 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9310 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9311 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9312 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
9313 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9314 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9315 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9316 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9317 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9318 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9319 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9320 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
9321 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9322 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9323 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9324 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9325 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9326 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9327 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
9328 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9329 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9330 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9331 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9332 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9333 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9334 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9335 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9336 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9337 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9338 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9339 [TGSI_OPCODE_SCS
] = { ALU_OP0_NOP
, tgsi_scs
},
9340 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9341 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9342 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9343 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9344 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9345 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9346 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9347 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9348 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9349 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9350 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9351 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9352 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9353 [TGSI_OPCODE_PUSHA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9354 [TGSI_OPCODE_POPA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9355 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9356 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
9357 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9358 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9359 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
9360 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9361 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9362 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9363 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9364 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9365 [TGSI_OPCODE_SAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9366 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9367 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9368 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9369 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9370 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9371 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9372 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9373 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9374 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9375 [TGSI_OPCODE_TXQ_LZ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9376 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9377 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9378 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9379 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9380 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9381 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9382 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9383 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9384 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9385 [TGSI_OPCODE_CALLNZ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9386 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9387 [TGSI_OPCODE_BREAKC
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9388 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9389 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9390 /* Refer below for TGSI_OPCODE_DFMA */
9391 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_f2i
},
9392 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9393 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9394 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9395 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9396 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9397 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
9398 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9399 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_f2i
},
9400 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
9401 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9402 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9403 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9404 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9405 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9406 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9407 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
9408 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9409 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9410 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
9411 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9412 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
9413 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9414 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9415 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9416 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9417 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9418 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9419 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9420 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9421 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9422 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9423 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9424 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9425 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9426 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9427 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9428 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9429 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
9430 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9431 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9432 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9433 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9434 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9435 [TGSI_OPCODE_MFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9436 [TGSI_OPCODE_LFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9437 [TGSI_OPCODE_SFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9438 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
9439 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9440 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9441 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9442 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9443 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9444 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9445 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9446 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9447 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9448 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9449 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9450 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9451 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9452 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
9453 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
9454 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
9455 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
9456 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_op3
},
9457 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_op3
},
9458 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
9459 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
9460 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
9461 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
9462 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
9463 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
9464 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9465 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9466 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9467 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
9468 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
9469 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
9470 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
9471 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
9472 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
9473 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
9474 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
9475 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
9476 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
9477 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
9478 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
9479 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
9480 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
9481 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
9482 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9483 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9484 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
9485 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
9486 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
9487 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
9488 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
9489 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
9490 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
9491 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
9492 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9495 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
9496 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9497 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9498 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9499 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, cayman_emit_float_instr
},
9500 [TGSI_OPCODE_RSQ
] = { ALU_OP1_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
9501 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9502 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9503 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9504 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9505 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9506 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9507 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9508 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN
, tgsi_op2
},
9509 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX
, tgsi_op2
},
9510 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9511 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9512 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9513 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9514 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
9515 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, cayman_emit_float_instr
},
9516 [TGSI_OPCODE_DP2A
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9517 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9518 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9519 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9520 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9521 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9522 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9523 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, cayman_emit_float_instr
},
9524 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, cayman_emit_float_instr
},
9525 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, cayman_pow
},
9526 [TGSI_OPCODE_XPD
] = { ALU_OP0_NOP
, tgsi_xpd
},
9527 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9528 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
9529 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9530 [TGSI_OPCODE_DPH
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9531 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, cayman_trig
},
9532 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9533 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9534 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9535 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
9536 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9537 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9538 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9539 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9540 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9541 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9542 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9543 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, cayman_trig
},
9544 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9545 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9546 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9547 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9548 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9549 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9550 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
9551 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9552 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9553 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9554 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9555 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9556 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9557 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9558 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9559 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9560 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9561 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9562 [TGSI_OPCODE_SCS
] = { ALU_OP0_NOP
, tgsi_scs
},
9563 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9564 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9565 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9566 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9567 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9568 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9569 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9570 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9571 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9572 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9573 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9574 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9575 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9576 [TGSI_OPCODE_PUSHA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9577 [TGSI_OPCODE_POPA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9578 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9579 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2
},
9580 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9581 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9582 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
9583 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9584 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9585 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9586 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9587 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9588 [TGSI_OPCODE_SAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9589 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9590 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9591 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9592 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9593 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9594 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9595 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9596 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9597 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9598 [TGSI_OPCODE_TXQ_LZ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9599 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9600 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9601 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9602 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9603 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9604 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9605 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9606 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9607 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9608 [TGSI_OPCODE_CALLNZ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9609 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9610 [TGSI_OPCODE_BREAKC
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9611 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9612 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9613 /* Refer below for TGSI_OPCODE_DFMA */
9614 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2
},
9615 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9616 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9617 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9618 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9619 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9620 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
9621 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9622 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2
},
9623 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2
},
9624 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9625 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9626 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9627 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9628 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9629 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9630 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_INT
, cayman_mul_int_instr
},
9631 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9632 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9633 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
9634 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9635 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
9636 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9637 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9638 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9639 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9640 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9641 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9642 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9643 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9644 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9645 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9646 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9647 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9648 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9649 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9650 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9651 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9652 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
9653 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9654 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9655 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9656 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9657 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9658 [TGSI_OPCODE_MFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9659 [TGSI_OPCODE_LFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9660 [TGSI_OPCODE_SFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9661 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
9662 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9663 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9664 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9665 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9666 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9667 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9668 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9669 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9670 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9671 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9672 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9673 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9674 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9675 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, cayman_mul_int_instr
},
9676 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, cayman_mul_int_instr
},
9677 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
9678 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
9679 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_op3
},
9680 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_op3
},
9681 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
9682 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
9683 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
9684 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
9685 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
9686 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
9687 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9688 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9689 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9690 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
9691 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
9692 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
9693 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
9694 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
9695 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
9696 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
9697 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
9698 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
9699 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
9700 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
9701 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
9702 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
9703 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
9704 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
9705 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9706 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9707 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
9708 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
9709 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
9710 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
9711 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
9712 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
9713 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
9714 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
9715 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},