2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
30 #include "sb/sb_public.h"
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
43 Why CAYMAN got loops for lots of instructions is explained here.
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
63 /* Contents of r0 on entry to various shaders
69 GS - r0.xyw, r1.xyz = per-vertex offsets
75 .w = tess factor base.
77 TES - .x = TessCoord.x
79 - .z = RelPatchID (??)
82 PS - face_gpr.z = SampleMask
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
87 struct r600_pipe_shader
*pipeshader
,
88 union r600_shader_key key
);
90 static void r600_add_gpr_array(struct r600_shader
*ps
, int start_gpr
,
91 int size
, unsigned comp_mask
) {
96 if (ps
->num_arrays
== ps
->max_arrays
) {
98 ps
->arrays
= realloc(ps
->arrays
, ps
->max_arrays
*
99 sizeof(struct r600_shader_array
));
102 int n
= ps
->num_arrays
;
105 ps
->arrays
[n
].comp_mask
= comp_mask
;
106 ps
->arrays
[n
].gpr_start
= start_gpr
;
107 ps
->arrays
[n
].gpr_count
= size
;
110 static void r600_dump_streamout(struct pipe_stream_output_info
*so
)
114 fprintf(stderr
, "STREAMOUT\n");
115 for (i
= 0; i
< so
->num_outputs
; i
++) {
116 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
117 so
->output
[i
].start_component
;
118 fprintf(stderr
, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
120 so
->output
[i
].stream
,
121 so
->output
[i
].output_buffer
,
122 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
123 so
->output
[i
].register_index
,
128 so
->output
[i
].dst_offset
< so
->output
[i
].start_component
? " (will lower)" : "");
132 static int store_shader(struct pipe_context
*ctx
,
133 struct r600_pipe_shader
*shader
)
135 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
138 if (shader
->bo
== NULL
) {
139 shader
->bo
= (struct r600_resource
*)
140 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_IMMUTABLE
, shader
->shader
.bc
.ndw
* 4);
141 if (shader
->bo
== NULL
) {
144 ptr
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->bo
, PIPE_TRANSFER_WRITE
);
145 if (R600_BIG_ENDIAN
) {
146 for (i
= 0; i
< shader
->shader
.bc
.ndw
; ++i
) {
147 ptr
[i
] = util_cpu_to_le32(shader
->shader
.bc
.bytecode
[i
]);
150 memcpy(ptr
, shader
->shader
.bc
.bytecode
, shader
->shader
.bc
.ndw
* sizeof(*ptr
));
152 rctx
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
158 int r600_pipe_shader_create(struct pipe_context
*ctx
,
159 struct r600_pipe_shader
*shader
,
160 union r600_shader_key key
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_shader_selector
*sel
= shader
->selector
;
165 bool dump
= r600_can_dump_shader(&rctx
->screen
->b
,
166 tgsi_get_processor_type(sel
->tokens
));
167 unsigned use_sb
= !(rctx
->screen
->b
.debug_flags
& DBG_NO_SB
);
168 unsigned sb_disasm
= use_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
169 unsigned export_shader
;
171 shader
->shader
.bc
.isa
= rctx
->isa
;
174 fprintf(stderr
, "--------------------------------------------------------------\n");
175 tgsi_dump(sel
->tokens
, 0);
177 if (sel
->so
.num_outputs
) {
178 r600_dump_streamout(&sel
->so
);
181 r
= r600_shader_from_tgsi(rctx
, shader
, key
);
183 R600_ERR("translation from TGSI failed !\n");
186 if (shader
->shader
.processor_type
== TGSI_PROCESSOR_VERTEX
) {
187 /* only disable for vertex shaders in tess paths */
191 use_sb
&= (shader
->shader
.processor_type
!= TGSI_PROCESSOR_TESS_CTRL
);
192 use_sb
&= (shader
->shader
.processor_type
!= TGSI_PROCESSOR_TESS_EVAL
);
194 /* disable SB for shaders using doubles */
195 use_sb
&= !shader
->shader
.uses_doubles
;
197 /* Check if the bytecode has already been built. When using the llvm
198 * backend, r600_shader_from_tgsi() will take care of building the
201 if (!shader
->shader
.bc
.bytecode
) {
202 r
= r600_bytecode_build(&shader
->shader
.bc
);
204 R600_ERR("building bytecode failed !\n");
209 if (dump
&& !sb_disasm
) {
210 fprintf(stderr
, "--------------------------------------------------------------\n");
211 r600_bytecode_disasm(&shader
->shader
.bc
);
212 fprintf(stderr
, "______________________________________________________________\n");
213 } else if ((dump
&& sb_disasm
) || use_sb
) {
214 r
= r600_sb_bytecode_process(rctx
, &shader
->shader
.bc
, &shader
->shader
,
217 R600_ERR("r600_sb_bytecode_process failed !\n");
222 if (shader
->gs_copy_shader
) {
225 r
= r600_sb_bytecode_process(rctx
, &shader
->gs_copy_shader
->shader
.bc
,
226 &shader
->gs_copy_shader
->shader
, dump
, 0);
231 if ((r
= store_shader(ctx
, shader
->gs_copy_shader
)))
235 /* Store the shader in a buffer. */
236 if ((r
= store_shader(ctx
, shader
)))
240 switch (shader
->shader
.processor_type
) {
241 case TGSI_PROCESSOR_TESS_CTRL
:
242 evergreen_update_hs_state(ctx
, shader
);
244 case TGSI_PROCESSOR_TESS_EVAL
:
246 evergreen_update_es_state(ctx
, shader
);
248 evergreen_update_vs_state(ctx
, shader
);
250 case TGSI_PROCESSOR_GEOMETRY
:
251 if (rctx
->b
.chip_class
>= EVERGREEN
) {
252 evergreen_update_gs_state(ctx
, shader
);
253 evergreen_update_vs_state(ctx
, shader
->gs_copy_shader
);
255 r600_update_gs_state(ctx
, shader
);
256 r600_update_vs_state(ctx
, shader
->gs_copy_shader
);
259 case TGSI_PROCESSOR_VERTEX
:
260 export_shader
= key
.vs
.as_es
;
261 if (rctx
->b
.chip_class
>= EVERGREEN
) {
263 evergreen_update_ls_state(ctx
, shader
);
264 else if (key
.vs
.as_es
)
265 evergreen_update_es_state(ctx
, shader
);
267 evergreen_update_vs_state(ctx
, shader
);
270 r600_update_es_state(ctx
, shader
);
272 r600_update_vs_state(ctx
, shader
);
275 case TGSI_PROCESSOR_FRAGMENT
:
276 if (rctx
->b
.chip_class
>= EVERGREEN
) {
277 evergreen_update_ps_state(ctx
, shader
);
279 r600_update_ps_state(ctx
, shader
);
289 r600_pipe_shader_destroy(ctx
, shader
);
293 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
295 pipe_resource_reference((struct pipe_resource
**)&shader
->bo
, NULL
);
296 r600_bytecode_clear(&shader
->shader
.bc
);
297 r600_release_command_buffer(&shader
->command_buffer
);
301 * tgsi -> r600 shader
303 struct r600_shader_tgsi_instruction
;
305 struct r600_shader_src
{
312 boolean kc_rel
; /* true if cache bank is indexed */
321 struct r600_shader_ctx
{
322 struct tgsi_shader_info info
;
323 struct tgsi_parse_context parse
;
324 const struct tgsi_token
*tokens
;
326 unsigned file_offset
[TGSI_FILE_COUNT
];
328 const struct r600_shader_tgsi_instruction
*inst_info
;
329 struct r600_bytecode
*bc
;
330 struct r600_shader
*shader
;
331 struct r600_shader_src src
[4];
334 uint32_t max_driver_temp_used
;
336 /* needed for evergreen interpolation */
337 struct eg_interp eg_interpolators
[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
338 /* evergreen/cayman also store sample mask in face register */
340 /* sample id is .w component stored in fixed point position register */
341 int fixed_pt_position_gpr
;
343 boolean clip_vertex_write
;
345 unsigned edgeflag_output
;
348 int next_ring_offset
;
349 int gs_out_ring_offset
;
351 struct r600_shader
*gs_for_vs
;
352 int gs_export_gpr_tregs
[4];
353 const struct pipe_stream_output_info
*gs_stream_output_info
;
354 unsigned enabled_stream_buffers_mask
;
355 unsigned tess_input_info
; /* temp with tess input offsets */
356 unsigned tess_output_info
; /* temp with tess input offsets */
359 struct r600_shader_tgsi_instruction
{
361 int (*process
)(struct r600_shader_ctx
*ctx
);
364 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
);
365 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
366 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
367 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
);
368 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
);
369 static int tgsi_else(struct r600_shader_ctx
*ctx
);
370 static int tgsi_endif(struct r600_shader_ctx
*ctx
);
371 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
);
372 static int tgsi_endloop(struct r600_shader_ctx
*ctx
);
373 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
);
374 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
375 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
376 unsigned int dst_reg
);
377 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
378 const struct r600_shader_src
*shader_src
,
380 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
383 static int tgsi_last_instruction(unsigned writemask
)
387 for (i
= 0; i
< 4; i
++) {
388 if (writemask
& (1 << i
)) {
395 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
397 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
400 if (i
->Instruction
.NumDstRegs
> 1 && i
->Instruction
.Opcode
!= TGSI_OPCODE_DFRACEXP
) {
401 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
404 if (i
->Instruction
.Predicate
) {
405 R600_ERR("predicate unsupported\n");
409 if (i
->Instruction
.Label
) {
410 R600_ERR("label unsupported\n");
414 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
415 if (i
->Src
[j
].Register
.Dimension
) {
416 switch (i
->Src
[j
].Register
.File
) {
417 case TGSI_FILE_CONSTANT
:
419 case TGSI_FILE_INPUT
:
420 if (ctx
->type
== TGSI_PROCESSOR_GEOMETRY
||
421 ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
||
422 ctx
->type
== TGSI_PROCESSOR_TESS_EVAL
)
424 case TGSI_FILE_OUTPUT
:
425 if (ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
)
428 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j
,
429 i
->Src
[j
].Register
.File
,
430 i
->Src
[j
].Register
.Dimension
);
435 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
436 if (i
->Dst
[j
].Register
.Dimension
) {
437 if (ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
)
439 R600_ERR("unsupported dst (dimension)\n");
446 int eg_get_interpolator_index(unsigned interpolate
, unsigned location
)
448 if (interpolate
== TGSI_INTERPOLATE_COLOR
||
449 interpolate
== TGSI_INTERPOLATE_LINEAR
||
450 interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
452 int is_linear
= interpolate
== TGSI_INTERPOLATE_LINEAR
;
456 case TGSI_INTERPOLATE_LOC_CENTER
:
459 case TGSI_INTERPOLATE_LOC_CENTROID
:
462 case TGSI_INTERPOLATE_LOC_SAMPLE
:
467 return is_linear
* 3 + loc
;
473 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx
*ctx
,
476 int i
= eg_get_interpolator_index(
477 ctx
->shader
->input
[input
].interpolate
,
478 ctx
->shader
->input
[input
].interpolate_location
);
480 ctx
->shader
->input
[input
].ij_index
= ctx
->eg_interpolators
[i
].ij_index
;
483 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
486 struct r600_bytecode_alu alu
;
487 int gpr
= 0, base_chan
= 0;
488 int ij_index
= ctx
->shader
->input
[input
].ij_index
;
490 /* work out gpr and base_chan from index */
492 base_chan
= (2 * (ij_index
% 2)) + 1;
494 for (i
= 0; i
< 8; i
++) {
495 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
498 alu
.op
= ALU_OP2_INTERP_ZW
;
500 alu
.op
= ALU_OP2_INTERP_XY
;
502 if ((i
> 1) && (i
< 6)) {
503 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
507 alu
.dst
.chan
= i
% 4;
509 alu
.src
[0].sel
= gpr
;
510 alu
.src
[0].chan
= (base_chan
- (i
% 2));
512 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
514 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
517 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
524 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
527 struct r600_bytecode_alu alu
;
529 for (i
= 0; i
< 4; i
++) {
530 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
532 alu
.op
= ALU_OP1_INTERP_LOAD_P0
;
534 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
539 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
544 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
552 * Special export handling in shaders
554 * shader export ARRAY_BASE for EXPORT_POS:
557 * 62, 63 are clip distance vectors
559 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
560 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
561 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
562 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
563 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
564 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
565 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
566 * exclusive from render target index)
567 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
570 * shader export ARRAY_BASE for EXPORT_PIXEL:
572 * 61 computed Z vector
574 * The use of the values exported in the computed Z vector are controlled
575 * by DB_SHADER_CONTROL:
576 * Z_EXPORT_ENABLE - Z as a float in RED
577 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
578 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
579 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
580 * DB_SOURCE_FORMAT - export control restrictions
585 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
586 static int r600_spi_sid(struct r600_shader_io
* io
)
588 int index
, name
= io
->name
;
590 /* These params are handled differently, they don't need
591 * semantic indices, so we'll use 0 for them.
593 if (name
== TGSI_SEMANTIC_POSITION
||
594 name
== TGSI_SEMANTIC_PSIZE
||
595 name
== TGSI_SEMANTIC_EDGEFLAG
||
596 name
== TGSI_SEMANTIC_FACE
||
597 name
== TGSI_SEMANTIC_SAMPLEMASK
)
600 if (name
== TGSI_SEMANTIC_GENERIC
) {
601 /* For generic params simply use sid from tgsi */
604 /* For non-generic params - pack name and sid into 8 bits */
605 index
= 0x80 | (name
<<3) | (io
->sid
);
608 /* Make sure that all really used indices have nonzero value, so
609 * we can just compare it to 0 later instead of comparing the name
610 * with different values to detect special cases. */
617 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
618 int r600_get_lds_unique_index(unsigned semantic_name
, unsigned index
)
620 switch (semantic_name
) {
621 case TGSI_SEMANTIC_POSITION
:
623 case TGSI_SEMANTIC_PSIZE
:
625 case TGSI_SEMANTIC_CLIPDIST
:
628 case TGSI_SEMANTIC_GENERIC
:
630 return 4 + index
- 9;
632 /* same explanation as in the default statement,
633 * the only user hitting this is st/nine.
637 /* patch indices are completely separate and thus start from 0 */
638 case TGSI_SEMANTIC_TESSOUTER
:
640 case TGSI_SEMANTIC_TESSINNER
:
642 case TGSI_SEMANTIC_PATCH
:
646 /* Don't fail here. The result of this function is only used
647 * for LS, TCS, TES, and GS, where legacy GL semantics can't
648 * occur, but this function is called for all vertex shaders
649 * before it's known whether LS will be compiled or not.
655 /* turn input into interpolate on EG */
656 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
660 if (ctx
->shader
->input
[index
].spi_sid
) {
661 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
662 if (ctx
->shader
->input
[index
].interpolate
> 0) {
663 evergreen_interp_assign_ij_index(ctx
, index
);
665 r
= evergreen_interp_alu(ctx
, index
);
668 r
= evergreen_interp_flat(ctx
, index
);
674 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
676 struct r600_bytecode_alu alu
;
678 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
679 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
681 for (i
= 0; i
< 4; i
++) {
682 memset(&alu
, 0, sizeof(alu
));
683 alu
.op
= ALU_OP3_CNDGT
;
686 alu
.dst
.sel
= gpr_front
;
687 alu
.src
[0].sel
= ctx
->face_gpr
;
688 alu
.src
[1].sel
= gpr_front
;
689 alu
.src
[2].sel
= gpr_back
;
696 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
703 /* execute a single slot ALU calculation */
704 static int single_alu_op2(struct r600_shader_ctx
*ctx
, int op
,
705 int dst_sel
, int dst_chan
,
706 int src0_sel
, unsigned src0_chan_val
,
707 int src1_sel
, unsigned src1_chan_val
)
709 struct r600_bytecode_alu alu
;
712 if (ctx
->bc
->chip_class
== CAYMAN
&& op
== ALU_OP2_MULLO_INT
) {
713 for (i
= 0; i
< 4; i
++) {
714 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
716 alu
.src
[0].sel
= src0_sel
;
717 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
718 alu
.src
[0].value
= src0_chan_val
;
720 alu
.src
[0].chan
= src0_chan_val
;
721 alu
.src
[1].sel
= src1_sel
;
722 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
723 alu
.src
[1].value
= src1_chan_val
;
725 alu
.src
[1].chan
= src1_chan_val
;
726 alu
.dst
.sel
= dst_sel
;
728 alu
.dst
.write
= i
== dst_chan
;
730 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
737 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
739 alu
.src
[0].sel
= src0_sel
;
740 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
741 alu
.src
[0].value
= src0_chan_val
;
743 alu
.src
[0].chan
= src0_chan_val
;
744 alu
.src
[1].sel
= src1_sel
;
745 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
746 alu
.src
[1].value
= src1_chan_val
;
748 alu
.src
[1].chan
= src1_chan_val
;
749 alu
.dst
.sel
= dst_sel
;
750 alu
.dst
.chan
= dst_chan
;
753 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
759 /* execute a single slot ALU calculation */
760 static int single_alu_op3(struct r600_shader_ctx
*ctx
, int op
,
761 int dst_sel
, int dst_chan
,
762 int src0_sel
, unsigned src0_chan_val
,
763 int src1_sel
, unsigned src1_chan_val
,
764 int src2_sel
, unsigned src2_chan_val
)
766 struct r600_bytecode_alu alu
;
769 /* validate this for other ops */
770 assert(op
== ALU_OP3_MULADD_UINT24
);
771 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
773 alu
.src
[0].sel
= src0_sel
;
774 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
775 alu
.src
[0].value
= src0_chan_val
;
777 alu
.src
[0].chan
= src0_chan_val
;
778 alu
.src
[1].sel
= src1_sel
;
779 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
780 alu
.src
[1].value
= src1_chan_val
;
782 alu
.src
[1].chan
= src1_chan_val
;
783 alu
.src
[2].sel
= src2_sel
;
784 if (src2_sel
== V_SQ_ALU_SRC_LITERAL
)
785 alu
.src
[2].value
= src2_chan_val
;
787 alu
.src
[2].chan
= src2_chan_val
;
788 alu
.dst
.sel
= dst_sel
;
789 alu
.dst
.chan
= dst_chan
;
792 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
798 /* put it in temp_reg.x */
799 static int get_lds_offset0(struct r600_shader_ctx
*ctx
,
801 int temp_reg
, bool is_patch_var
)
805 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
807 Dimension - patch0_offset (input_vals.z),
808 Non-dim - patch0_data_offset (input_vals.w)
810 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
812 ctx
->tess_output_info
, 0,
814 ctx
->tess_output_info
, is_patch_var
? 3 : 2);
820 static inline int get_address_file_reg(struct r600_shader_ctx
*ctx
, int index
)
822 return index
> 0 ? ctx
->bc
->index_reg
[index
- 1] : ctx
->bc
->ar_reg
;
825 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
827 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
830 static int vs_add_primid_output(struct r600_shader_ctx
*ctx
, int prim_id_sid
)
833 i
= ctx
->shader
->noutput
++;
834 ctx
->shader
->output
[i
].name
= TGSI_SEMANTIC_PRIMID
;
835 ctx
->shader
->output
[i
].sid
= 0;
836 ctx
->shader
->output
[i
].gpr
= 0;
837 ctx
->shader
->output
[i
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
838 ctx
->shader
->output
[i
].write_mask
= 0x4;
839 ctx
->shader
->output
[i
].spi_sid
= prim_id_sid
;
844 static int tgsi_barrier(struct r600_shader_ctx
*ctx
)
846 struct r600_bytecode_alu alu
;
849 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
850 alu
.op
= ctx
->inst_info
->op
;
853 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
859 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
861 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
862 int r
, i
, j
, count
= d
->Range
.Last
- d
->Range
.First
+ 1;
864 switch (d
->Declaration
.File
) {
865 case TGSI_FILE_INPUT
:
866 for (j
= 0; j
< count
; j
++) {
867 i
= ctx
->shader
->ninput
+ j
;
868 assert(i
< Elements(ctx
->shader
->input
));
869 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
870 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
+ j
;
871 ctx
->shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
872 ctx
->shader
->input
[i
].interpolate_location
= d
->Interp
.Location
;
873 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
+ j
;
874 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
875 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
876 switch (ctx
->shader
->input
[i
].name
) {
877 case TGSI_SEMANTIC_FACE
:
878 if (ctx
->face_gpr
!= -1)
879 ctx
->shader
->input
[i
].gpr
= ctx
->face_gpr
; /* already allocated by allocate_system_value_inputs */
881 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
883 case TGSI_SEMANTIC_COLOR
:
886 case TGSI_SEMANTIC_POSITION
:
887 ctx
->fragcoord_input
= i
;
889 case TGSI_SEMANTIC_PRIMID
:
890 /* set this for now */
891 ctx
->shader
->gs_prim_id_input
= true;
892 ctx
->shader
->ps_prim_id_input
= i
;
895 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
896 if ((r
= evergreen_interp_input(ctx
, i
)))
899 } else if (ctx
->type
== TGSI_PROCESSOR_GEOMETRY
) {
900 /* FIXME probably skip inputs if they aren't passed in the ring */
901 ctx
->shader
->input
[i
].ring_offset
= ctx
->next_ring_offset
;
902 ctx
->next_ring_offset
+= 16;
903 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_PRIMID
)
904 ctx
->shader
->gs_prim_id_input
= true;
907 ctx
->shader
->ninput
+= count
;
909 case TGSI_FILE_OUTPUT
:
910 for (j
= 0; j
< count
; j
++) {
911 i
= ctx
->shader
->noutput
+ j
;
912 assert(i
< Elements(ctx
->shader
->output
));
913 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
914 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
+ j
;
915 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
+ j
;
916 ctx
->shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
917 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
918 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
||
919 ctx
->type
== TGSI_PROCESSOR_GEOMETRY
||
920 ctx
->type
== TGSI_PROCESSOR_TESS_EVAL
) {
921 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
922 switch (d
->Semantic
.Name
) {
923 case TGSI_SEMANTIC_CLIPDIST
:
924 ctx
->shader
->clip_dist_write
|= d
->Declaration
.UsageMask
<<
925 ((d
->Semantic
.Index
+ j
) << 2);
927 case TGSI_SEMANTIC_PSIZE
:
928 ctx
->shader
->vs_out_misc_write
= 1;
929 ctx
->shader
->vs_out_point_size
= 1;
931 case TGSI_SEMANTIC_EDGEFLAG
:
932 ctx
->shader
->vs_out_misc_write
= 1;
933 ctx
->shader
->vs_out_edgeflag
= 1;
934 ctx
->edgeflag_output
= i
;
936 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
937 ctx
->shader
->vs_out_misc_write
= 1;
938 ctx
->shader
->vs_out_viewport
= 1;
940 case TGSI_SEMANTIC_LAYER
:
941 ctx
->shader
->vs_out_misc_write
= 1;
942 ctx
->shader
->vs_out_layer
= 1;
944 case TGSI_SEMANTIC_CLIPVERTEX
:
945 ctx
->clip_vertex_write
= TRUE
;
949 if (ctx
->type
== TGSI_PROCESSOR_GEOMETRY
) {
950 ctx
->gs_out_ring_offset
+= 16;
952 } else if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
953 switch (d
->Semantic
.Name
) {
954 case TGSI_SEMANTIC_COLOR
:
955 ctx
->shader
->nr_ps_max_color_exports
++;
960 ctx
->shader
->noutput
+= count
;
962 case TGSI_FILE_TEMPORARY
:
963 if (ctx
->info
.indirect_files
& (1 << TGSI_FILE_TEMPORARY
)) {
964 if (d
->Array
.ArrayID
) {
965 r600_add_gpr_array(ctx
->shader
,
966 ctx
->file_offset
[TGSI_FILE_TEMPORARY
] +
968 d
->Range
.Last
- d
->Range
.First
+ 1, 0x0F);
973 case TGSI_FILE_CONSTANT
:
974 case TGSI_FILE_SAMPLER
:
975 case TGSI_FILE_SAMPLER_VIEW
:
976 case TGSI_FILE_ADDRESS
:
979 case TGSI_FILE_SYSTEM_VALUE
:
980 if (d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEMASK
||
981 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEID
||
982 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEPOS
) {
983 break; /* Already handled from allocate_system_value_inputs */
984 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
985 if (!ctx
->native_integers
) {
986 struct r600_bytecode_alu alu
;
987 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
989 alu
.op
= ALU_OP1_INT_TO_FLT
;
998 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1002 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
1004 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INVOCATIONID
)
1006 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
||
1007 d
->Semantic
.Name
== TGSI_SEMANTIC_TESSOUTER
) {
1008 int param
= r600_get_lds_unique_index(d
->Semantic
.Name
, 0);
1009 int dreg
= d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
? 3 : 2;
1010 unsigned temp_reg
= r600_get_temp(ctx
);
1012 r
= get_lds_offset0(ctx
, 2, temp_reg
, true);
1016 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1019 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1023 do_lds_fetch_values(ctx
, temp_reg
, dreg
);
1025 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSCOORD
) {
1029 for (i
= 0; i
< 2; i
++) {
1030 struct r600_bytecode_alu alu
;
1031 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1032 alu
.op
= ALU_OP1_MOV
;
1034 alu
.src
[0].chan
= 0 + i
;
1036 alu
.dst
.chan
= 0 + i
;
1038 alu
.last
= (i
== 1) ? 1 : 0;
1039 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1042 /* ADD r1.z, 1.0f, -r0.x */
1043 struct r600_bytecode_alu alu
;
1044 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1045 alu
.op
= ALU_OP2_ADD
;
1046 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1048 alu
.src
[1].chan
= 0;
1054 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1057 /* ADD r1.z, r1.z, -r1.y */
1058 alu
.op
= ALU_OP2_ADD
;
1060 alu
.src
[0].chan
= 2;
1062 alu
.src
[1].chan
= 1;
1068 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1074 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
1080 static int allocate_system_value_inputs(struct r600_shader_ctx
*ctx
, int gpr_offset
)
1082 struct tgsi_parse_context parse
;
1086 unsigned name
, alternate_name
;
1088 { false, &ctx
->face_gpr
, TGSI_SEMANTIC_SAMPLEMASK
, ~0u }, /* lives in Front Face GPR.z */
1090 { false, &ctx
->fixed_pt_position_gpr
, TGSI_SEMANTIC_SAMPLEID
, TGSI_SEMANTIC_SAMPLEPOS
} /* SAMPLEID is in Fixed Point Position GPR.w */
1092 int i
, k
, num_regs
= 0;
1094 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1098 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1099 while (!tgsi_parse_end_of_tokens(&parse
)) {
1100 tgsi_parse_token(&parse
);
1102 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1103 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1104 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1105 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1106 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1108 int interpolate
, location
, k
;
1110 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1111 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1112 inputs
[1].enabled
= true; /* needs SAMPLEID */
1113 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1114 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1115 /* Needs sample positions, currently those are always available */
1117 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1120 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1121 k
= eg_get_interpolator_index(interpolate
, location
);
1122 ctx
->eg_interpolators
[k
].enabled
= true;
1124 } else if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_DECLARATION
) {
1125 struct tgsi_full_declaration
*d
= &parse
.FullToken
.FullDeclaration
;
1126 if (d
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1127 for (k
= 0; k
< Elements(inputs
); k
++) {
1128 if (d
->Semantic
.Name
== inputs
[k
].name
||
1129 d
->Semantic
.Name
== inputs
[k
].alternate_name
) {
1130 inputs
[k
].enabled
= true;
1137 tgsi_parse_free(&parse
);
1139 for (i
= 0; i
< Elements(inputs
); i
++) {
1140 boolean enabled
= inputs
[i
].enabled
;
1141 int *reg
= inputs
[i
].reg
;
1142 unsigned name
= inputs
[i
].name
;
1145 int gpr
= gpr_offset
+ num_regs
++;
1147 // add to inputs, allocate a gpr
1148 k
= ctx
->shader
->ninput
++;
1149 ctx
->shader
->input
[k
].name
= name
;
1150 ctx
->shader
->input
[k
].sid
= 0;
1151 ctx
->shader
->input
[k
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1152 ctx
->shader
->input
[k
].interpolate_location
= TGSI_INTERPOLATE_LOC_CENTER
;
1153 *reg
= ctx
->shader
->input
[k
].gpr
= gpr
;
1157 return gpr_offset
+ num_regs
;
1161 * for evergreen we need to scan the shader to find the number of GPRs we need to
1162 * reserve for interpolation and system values
1164 * we need to know if we are going to emit
1165 * any sample or centroid inputs
1166 * if perspective and linear are required
1168 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
1172 struct tgsi_parse_context parse
;
1174 memset(&ctx
->eg_interpolators
, 0, sizeof(ctx
->eg_interpolators
));
1176 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
1178 /* skip position/face/mask/sampleid */
1179 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
1180 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
||
1181 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEMASK
||
1182 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEID
)
1185 k
= eg_get_interpolator_index(
1186 ctx
->info
.input_interpolate
[i
],
1187 ctx
->info
.input_interpolate_loc
[i
]);
1189 ctx
->eg_interpolators
[k
].enabled
= TRUE
;
1192 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1196 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1197 while (!tgsi_parse_end_of_tokens(&parse
)) {
1198 tgsi_parse_token(&parse
);
1200 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1201 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1202 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1203 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1204 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1206 int interpolate
, location
, k
;
1208 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1209 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1210 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1211 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1213 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1216 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1217 k
= eg_get_interpolator_index(interpolate
, location
);
1218 ctx
->eg_interpolators
[k
].enabled
= true;
1223 tgsi_parse_free(&parse
);
1225 /* assign gpr to each interpolator according to priority */
1227 for (i
= 0; i
< Elements(ctx
->eg_interpolators
); i
++) {
1228 if (ctx
->eg_interpolators
[i
].enabled
) {
1229 ctx
->eg_interpolators
[i
].ij_index
= num_baryc
;
1234 /* XXX PULL MODEL and LINE STIPPLE */
1236 num_baryc
= (num_baryc
+ 1) >> 1;
1237 return allocate_system_value_inputs(ctx
, num_baryc
);
1240 /* sample_id_sel == NULL means fetch for current sample */
1241 static int load_sample_position(struct r600_shader_ctx
*ctx
, struct r600_shader_src
*sample_id
, int chan_sel
)
1243 struct r600_bytecode_vtx vtx
;
1246 assert(ctx
->fixed_pt_position_gpr
!= -1);
1248 t1
= r600_get_temp(ctx
);
1250 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
1251 vtx
.op
= FETCH_OP_VFETCH
;
1252 vtx
.buffer_id
= R600_BUFFER_INFO_CONST_BUFFER
;
1253 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1254 if (sample_id
== NULL
) {
1255 vtx
.src_gpr
= ctx
->fixed_pt_position_gpr
; // SAMPLEID is in .w;
1259 struct r600_bytecode_alu alu
;
1261 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1262 alu
.op
= ALU_OP1_MOV
;
1263 r600_bytecode_src(&alu
.src
[0], sample_id
, chan_sel
);
1267 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1274 vtx
.mega_fetch_count
= 16;
1280 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1281 vtx
.num_format_all
= 2;
1282 vtx
.format_comp_all
= 1;
1283 vtx
.use_const_fields
= 0;
1284 vtx
.offset
= 1; // first element is size of buffer
1285 vtx
.endian
= r600_endian_swap(32);
1286 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
1288 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
1295 static void tgsi_src(struct r600_shader_ctx
*ctx
,
1296 const struct tgsi_full_src_register
*tgsi_src
,
1297 struct r600_shader_src
*r600_src
)
1299 memset(r600_src
, 0, sizeof(*r600_src
));
1300 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
1301 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
1302 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
1303 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
1304 r600_src
->neg
= tgsi_src
->Register
.Negate
;
1305 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
1307 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
1309 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
1310 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
1311 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
1313 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
1314 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
, r600_src
->abs
);
1315 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
1318 index
= tgsi_src
->Register
.Index
;
1319 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
1320 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
1321 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1322 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEMASK
) {
1323 r600_src
->swizzle
[0] = 2; // Z value
1324 r600_src
->swizzle
[1] = 2;
1325 r600_src
->swizzle
[2] = 2;
1326 r600_src
->swizzle
[3] = 2;
1327 r600_src
->sel
= ctx
->face_gpr
;
1328 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEID
) {
1329 r600_src
->swizzle
[0] = 3; // W value
1330 r600_src
->swizzle
[1] = 3;
1331 r600_src
->swizzle
[2] = 3;
1332 r600_src
->swizzle
[3] = 3;
1333 r600_src
->sel
= ctx
->fixed_pt_position_gpr
;
1334 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEPOS
) {
1335 r600_src
->swizzle
[0] = 0;
1336 r600_src
->swizzle
[1] = 1;
1337 r600_src
->swizzle
[2] = 4;
1338 r600_src
->swizzle
[3] = 4;
1339 r600_src
->sel
= load_sample_position(ctx
, NULL
, -1);
1340 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
1341 r600_src
->swizzle
[0] = 3;
1342 r600_src
->swizzle
[1] = 3;
1343 r600_src
->swizzle
[2] = 3;
1344 r600_src
->swizzle
[3] = 3;
1346 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
1347 r600_src
->swizzle
[0] = 0;
1348 r600_src
->swizzle
[1] = 0;
1349 r600_src
->swizzle
[2] = 0;
1350 r600_src
->swizzle
[3] = 0;
1352 } else if (ctx
->type
!= TGSI_PROCESSOR_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1353 r600_src
->swizzle
[0] = 3;
1354 r600_src
->swizzle
[1] = 3;
1355 r600_src
->swizzle
[2] = 3;
1356 r600_src
->swizzle
[3] = 3;
1358 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1359 r600_src
->swizzle
[0] = 2;
1360 r600_src
->swizzle
[1] = 2;
1361 r600_src
->swizzle
[2] = 2;
1362 r600_src
->swizzle
[3] = 2;
1364 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSCOORD
) {
1366 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSINNER
) {
1368 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSOUTER
) {
1370 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTICESIN
) {
1371 if (ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
) {
1372 r600_src
->sel
= ctx
->tess_input_info
;
1373 r600_src
->swizzle
[0] = 2;
1374 r600_src
->swizzle
[1] = 2;
1375 r600_src
->swizzle
[2] = 2;
1376 r600_src
->swizzle
[3] = 2;
1378 r600_src
->sel
= ctx
->tess_input_info
;
1379 r600_src
->swizzle
[0] = 3;
1380 r600_src
->swizzle
[1] = 3;
1381 r600_src
->swizzle
[2] = 3;
1382 r600_src
->swizzle
[3] = 3;
1384 } else if (ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1386 r600_src
->swizzle
[0] = 0;
1387 r600_src
->swizzle
[1] = 0;
1388 r600_src
->swizzle
[2] = 0;
1389 r600_src
->swizzle
[3] = 0;
1390 } else if (ctx
->type
== TGSI_PROCESSOR_TESS_EVAL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1392 r600_src
->swizzle
[0] = 3;
1393 r600_src
->swizzle
[1] = 3;
1394 r600_src
->swizzle
[2] = 3;
1395 r600_src
->swizzle
[3] = 3;
1398 if (tgsi_src
->Register
.Indirect
)
1399 r600_src
->rel
= V_SQ_REL_RELATIVE
;
1400 r600_src
->sel
= tgsi_src
->Register
.Index
;
1401 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
1403 if (tgsi_src
->Register
.File
== TGSI_FILE_CONSTANT
) {
1404 if (tgsi_src
->Register
.Dimension
) {
1405 r600_src
->kc_bank
= tgsi_src
->Dimension
.Index
;
1406 if (tgsi_src
->Dimension
.Indirect
) {
1407 r600_src
->kc_rel
= 1;
1413 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
1414 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
1415 unsigned int dst_reg
)
1417 struct r600_bytecode_vtx vtx
;
1418 unsigned int ar_reg
;
1422 struct r600_bytecode_alu alu
;
1424 memset(&alu
, 0, sizeof(alu
));
1426 alu
.op
= ALU_OP2_ADD_INT
;
1427 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
1428 alu
.src
[0].chan
= ar_chan
;
1430 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1431 alu
.src
[1].value
= offset
;
1433 alu
.dst
.sel
= dst_reg
;
1434 alu
.dst
.chan
= ar_chan
;
1438 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1443 ar_reg
= ctx
->bc
->ar_reg
;
1446 memset(&vtx
, 0, sizeof(vtx
));
1447 vtx
.buffer_id
= cb_idx
;
1448 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1449 vtx
.src_gpr
= ar_reg
;
1450 vtx
.src_sel_x
= ar_chan
;
1451 vtx
.mega_fetch_count
= 16;
1452 vtx
.dst_gpr
= dst_reg
;
1453 vtx
.dst_sel_x
= 0; /* SEL_X */
1454 vtx
.dst_sel_y
= 1; /* SEL_Y */
1455 vtx
.dst_sel_z
= 2; /* SEL_Z */
1456 vtx
.dst_sel_w
= 3; /* SEL_W */
1457 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1458 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
1459 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
1460 vtx
.endian
= r600_endian_swap(32);
1461 vtx
.buffer_index_mode
= cb_rel
; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1463 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1469 static int fetch_gs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1471 struct r600_bytecode_vtx vtx
;
1473 unsigned index
= src
->Register
.Index
;
1474 unsigned vtx_id
= src
->Dimension
.Index
;
1475 int offset_reg
= vtx_id
/ 3;
1476 int offset_chan
= vtx_id
% 3;
1479 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1480 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1482 if (offset_reg
== 0 && offset_chan
== 2)
1485 if (src
->Dimension
.Indirect
|| src
->Register
.Indirect
)
1486 t2
= r600_get_temp(ctx
);
1488 if (src
->Dimension
.Indirect
) {
1490 struct r600_bytecode_alu alu
;
1493 addr_reg
= get_address_file_reg(ctx
, src
->DimIndirect
.Index
);
1494 if (src
->DimIndirect
.Index
> 0) {
1495 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
1503 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1504 at least this is what fglrx seems to do. */
1505 for (i
= 0; i
< 3; i
++) {
1506 treg
[i
] = r600_get_temp(ctx
);
1508 r600_add_gpr_array(ctx
->shader
, treg
[0], 3, 0x0F);
1510 for (i
= 0; i
< 3; i
++) {
1511 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1512 alu
.op
= ALU_OP1_MOV
;
1514 alu
.src
[0].chan
= i
== 2 ? 3 : i
;
1515 alu
.dst
.sel
= treg
[i
];
1519 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1523 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1524 alu
.op
= ALU_OP1_MOV
;
1525 alu
.src
[0].sel
= treg
[0];
1530 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1537 if (src
->Register
.Indirect
) {
1539 unsigned first
= ctx
->info
.input_array_first
[src
->Indirect
.ArrayID
];
1541 addr_reg
= get_address_file_reg(ctx
, src
->Indirect
.Index
);
1543 /* pull the value from index_reg */
1544 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1547 V_SQ_ALU_SRC_LITERAL
, first
);
1550 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1553 V_SQ_ALU_SRC_LITERAL
, 4,
1554 offset_reg
, offset_chan
);
1559 index
= src
->Register
.Index
- first
;
1562 memset(&vtx
, 0, sizeof(vtx
));
1563 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
1564 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1565 vtx
.src_gpr
= offset_reg
;
1566 vtx
.src_sel_x
= offset_chan
;
1567 vtx
.offset
= index
* 16; /*bytes*/
1568 vtx
.mega_fetch_count
= 16;
1569 vtx
.dst_gpr
= dst_reg
;
1570 vtx
.dst_sel_x
= 0; /* SEL_X */
1571 vtx
.dst_sel_y
= 1; /* SEL_Y */
1572 vtx
.dst_sel_z
= 2; /* SEL_Z */
1573 vtx
.dst_sel_w
= 3; /* SEL_W */
1574 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1575 vtx
.use_const_fields
= 1;
1577 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1580 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1586 static int tgsi_split_gs_inputs(struct r600_shader_ctx
*ctx
)
1588 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1591 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1592 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1594 if (src
->Register
.File
== TGSI_FILE_INPUT
) {
1595 if (ctx
->shader
->input
[src
->Register
.Index
].name
== TGSI_SEMANTIC_PRIMID
) {
1596 /* primitive id is in R0.z */
1597 ctx
->src
[i
].sel
= 0;
1598 ctx
->src
[i
].swizzle
[0] = 2;
1601 if (src
->Register
.File
== TGSI_FILE_INPUT
&& src
->Register
.Dimension
) {
1602 int treg
= r600_get_temp(ctx
);
1604 fetch_gs_input(ctx
, src
, treg
);
1605 ctx
->src
[i
].sel
= treg
;
1606 ctx
->src
[i
].rel
= 0;
1613 /* Tessellation shaders pass outputs to the next shader using LDS.
1615 * LS outputs = TCS(HS) inputs
1616 * TCS(HS) outputs = TES(DS) inputs
1618 * The LDS layout is:
1619 * - TCS inputs for patch 0
1620 * - TCS inputs for patch 1
1621 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1623 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1624 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1625 * - TCS outputs for patch 1
1626 * - Per-patch TCS outputs for patch 1
1627 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1628 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1631 * All three shaders VS(LS), TCS, TES share the same LDS space.
1633 /* this will return with the dw address in temp_reg.x */
1634 static int r600_get_byte_address(struct r600_shader_ctx
*ctx
, int temp_reg
,
1635 const struct tgsi_full_dst_register
*dst
,
1636 const struct tgsi_full_src_register
*src
,
1637 int stride_bytes_reg
, int stride_bytes_chan
)
1639 struct tgsi_full_dst_register reg
;
1640 ubyte
*name
, *index
, *array_first
;
1643 struct tgsi_shader_info
*info
= &ctx
->info
;
1644 /* Set the register description. The address computation is the same
1645 * for sources and destinations. */
1647 reg
.Register
.File
= src
->Register
.File
;
1648 reg
.Register
.Index
= src
->Register
.Index
;
1649 reg
.Register
.Indirect
= src
->Register
.Indirect
;
1650 reg
.Register
.Dimension
= src
->Register
.Dimension
;
1651 reg
.Indirect
= src
->Indirect
;
1652 reg
.Dimension
= src
->Dimension
;
1653 reg
.DimIndirect
= src
->DimIndirect
;
1657 /* If the register is 2-dimensional (e.g. an array of vertices
1658 * in a primitive), calculate the base address of the vertex. */
1659 if (reg
.Register
.Dimension
) {
1661 if (reg
.Dimension
.Indirect
) {
1663 assert (reg
.DimIndirect
.File
== TGSI_FILE_ADDRESS
);
1665 addr_reg
= get_address_file_reg(ctx
, reg
.DimIndirect
.Index
);
1666 /* pull the value from index_reg */
1670 sel
= V_SQ_ALU_SRC_LITERAL
;
1671 chan
= reg
.Dimension
.Index
;
1674 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1676 stride_bytes_reg
, stride_bytes_chan
,
1683 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1684 name
= info
->input_semantic_name
;
1685 index
= info
->input_semantic_index
;
1686 array_first
= info
->input_array_first
;
1687 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1688 name
= info
->output_semantic_name
;
1689 index
= info
->output_semantic_index
;
1690 array_first
= info
->output_array_first
;
1695 if (reg
.Register
.Indirect
) {
1698 /* Add the relative address of the element. */
1699 if (reg
.Indirect
.ArrayID
)
1700 first
= array_first
[reg
.Indirect
.ArrayID
];
1702 first
= reg
.Register
.Index
;
1704 addr_reg
= get_address_file_reg(ctx
, reg
.Indirect
.Index
);
1706 /* pull the value from index_reg */
1707 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1709 V_SQ_ALU_SRC_LITERAL
, 16,
1715 param
= r600_get_lds_unique_index(name
[first
],
1719 param
= r600_get_lds_unique_index(name
[reg
.Register
.Index
],
1720 index
[reg
.Register
.Index
]);
1723 /* add to base_addr - passed in temp_reg.x */
1725 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1728 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1736 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
1739 struct r600_bytecode_alu alu
;
1742 if ((ctx
->bc
->cf_last
->ndw
>>1) >= 0x60)
1743 ctx
->bc
->force_add_cf
= 1;
1744 for (i
= 1; i
< 4; i
++) {
1745 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1748 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
1752 for (i
= 0; i
< 4; i
++) {
1753 /* emit an LDS_READ_RET */
1754 memset(&alu
, 0, sizeof(alu
));
1755 alu
.op
= LDS_OP1_LDS_READ_RET
;
1756 alu
.src
[0].sel
= temp_reg
;
1757 alu
.src
[0].chan
= i
;
1758 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1759 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
1761 alu
.is_lds_idx_op
= true;
1763 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1767 for (i
= 0; i
< 4; i
++) {
1768 /* then read from LDS_OQ_A_POP */
1769 memset(&alu
, 0, sizeof(alu
));
1771 alu
.op
= ALU_OP1_MOV
;
1772 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
;
1773 alu
.src
[0].chan
= 0;
1774 alu
.dst
.sel
= dst_reg
;
1778 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1785 static int fetch_tes_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1788 unsigned temp_reg
= r600_get_temp(ctx
);
1790 r
= get_lds_offset0(ctx
, 2, temp_reg
,
1791 src
->Register
.Dimension
? false : true);
1795 /* the base address is now in temp.x */
1796 r
= r600_get_byte_address(ctx
, temp_reg
,
1797 NULL
, src
, ctx
->tess_output_info
, 1);
1801 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1807 static int fetch_tcs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1810 unsigned temp_reg
= r600_get_temp(ctx
);
1812 /* t.x = ips * r0.y */
1813 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
1815 ctx
->tess_input_info
, 0,
1821 /* the base address is now in temp.x */
1822 r
= r600_get_byte_address(ctx
, temp_reg
,
1823 NULL
, src
, ctx
->tess_input_info
, 1);
1827 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1833 static int fetch_tcs_output(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1836 unsigned temp_reg
= r600_get_temp(ctx
);
1838 r
= get_lds_offset0(ctx
, 1, temp_reg
,
1839 src
->Register
.Dimension
? false : true);
1842 /* the base address is now in temp.x */
1843 r
= r600_get_byte_address(ctx
, temp_reg
,
1845 ctx
->tess_output_info
, 1);
1849 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1855 static int tgsi_split_lds_inputs(struct r600_shader_ctx
*ctx
)
1857 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1860 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1861 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1863 if (ctx
->type
== TGSI_PROCESSOR_TESS_EVAL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1864 int treg
= r600_get_temp(ctx
);
1865 fetch_tes_input(ctx
, src
, treg
);
1866 ctx
->src
[i
].sel
= treg
;
1867 ctx
->src
[i
].rel
= 0;
1869 if (ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1870 int treg
= r600_get_temp(ctx
);
1871 fetch_tcs_input(ctx
, src
, treg
);
1872 ctx
->src
[i
].sel
= treg
;
1873 ctx
->src
[i
].rel
= 0;
1875 if (ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_OUTPUT
) {
1876 int treg
= r600_get_temp(ctx
);
1877 fetch_tcs_output(ctx
, src
, treg
);
1878 ctx
->src
[i
].sel
= treg
;
1879 ctx
->src
[i
].rel
= 0;
1885 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
1887 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1888 struct r600_bytecode_alu alu
;
1889 int i
, j
, k
, nconst
, r
;
1891 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1892 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
1895 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
1897 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1898 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
1902 if (ctx
->src
[i
].rel
) {
1903 int chan
= inst
->Src
[i
].Indirect
.Swizzle
;
1904 int treg
= r600_get_temp(ctx
);
1905 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].kc_bank
, ctx
->src
[i
].kc_rel
, ctx
->src
[i
].sel
- 512, chan
, treg
)))
1908 ctx
->src
[i
].kc_bank
= 0;
1909 ctx
->src
[i
].kc_rel
= 0;
1910 ctx
->src
[i
].sel
= treg
;
1911 ctx
->src
[i
].rel
= 0;
1914 int treg
= r600_get_temp(ctx
);
1915 for (k
= 0; k
< 4; k
++) {
1916 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1917 alu
.op
= ALU_OP1_MOV
;
1918 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1919 alu
.src
[0].chan
= k
;
1920 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
1921 alu
.src
[0].kc_bank
= ctx
->src
[i
].kc_bank
;
1922 alu
.src
[0].kc_rel
= ctx
->src
[i
].kc_rel
;
1928 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1932 ctx
->src
[i
].sel
= treg
;
1940 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1941 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
1943 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1944 struct r600_bytecode_alu alu
;
1945 int i
, j
, k
, nliteral
, r
;
1947 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1948 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1952 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1953 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1954 int treg
= r600_get_temp(ctx
);
1955 for (k
= 0; k
< 4; k
++) {
1956 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1957 alu
.op
= ALU_OP1_MOV
;
1958 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1959 alu
.src
[0].chan
= k
;
1960 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
1966 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1970 ctx
->src
[i
].sel
= treg
;
1977 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
1979 int i
, r
, count
= ctx
->shader
->ninput
;
1981 for (i
= 0; i
< count
; i
++) {
1982 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1983 r
= select_twoside_color(ctx
, i
, ctx
->shader
->input
[i
].back_color_input
);
1991 static int emit_streamout(struct r600_shader_ctx
*ctx
, struct pipe_stream_output_info
*so
,
1992 int stream
, unsigned *stream_item_size
)
1994 unsigned so_gpr
[PIPE_MAX_SHADER_OUTPUTS
];
1995 unsigned start_comp
[PIPE_MAX_SHADER_OUTPUTS
];
1998 /* Sanity checking. */
1999 if (so
->num_outputs
> PIPE_MAX_SO_OUTPUTS
) {
2000 R600_ERR("Too many stream outputs: %d\n", so
->num_outputs
);
2004 for (i
= 0; i
< so
->num_outputs
; i
++) {
2005 if (so
->output
[i
].output_buffer
>= 4) {
2006 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2007 so
->output
[i
].output_buffer
);
2013 /* Initialize locations where the outputs are stored. */
2014 for (i
= 0; i
< so
->num_outputs
; i
++) {
2016 so_gpr
[i
] = ctx
->shader
->output
[so
->output
[i
].register_index
].gpr
;
2017 start_comp
[i
] = so
->output
[i
].start_component
;
2018 /* Lower outputs with dst_offset < start_component.
2020 * We can only output 4D vectors with a write mask, e.g. we can
2021 * only output the W component at offset 3, etc. If we want
2022 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2023 * to move it to X and output X. */
2024 if (so
->output
[i
].dst_offset
< so
->output
[i
].start_component
) {
2025 unsigned tmp
= r600_get_temp(ctx
);
2027 for (j
= 0; j
< so
->output
[i
].num_components
; j
++) {
2028 struct r600_bytecode_alu alu
;
2029 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2030 alu
.op
= ALU_OP1_MOV
;
2031 alu
.src
[0].sel
= so_gpr
[i
];
2032 alu
.src
[0].chan
= so
->output
[i
].start_component
+ j
;
2037 if (j
== so
->output
[i
].num_components
- 1)
2039 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2048 /* Write outputs to buffers. */
2049 for (i
= 0; i
< so
->num_outputs
; i
++) {
2050 struct r600_bytecode_output output
;
2052 if (stream
!= -1 && stream
!= so
->output
[i
].output_buffer
)
2055 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2056 output
.gpr
= so_gpr
[i
];
2057 output
.elem_size
= so
->output
[i
].num_components
- 1;
2058 if (output
.elem_size
== 2)
2059 output
.elem_size
= 3; // 3 not supported, write 4 with junk at end
2060 output
.array_base
= so
->output
[i
].dst_offset
- start_comp
[i
];
2061 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2062 output
.burst_count
= 1;
2063 /* array_size is an upper limit for the burst_count
2064 * with MEM_STREAM instructions */
2065 output
.array_size
= 0xFFF;
2066 output
.comp_mask
= ((1 << so
->output
[i
].num_components
) - 1) << start_comp
[i
];
2068 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
2069 switch (so
->output
[i
].output_buffer
) {
2071 output
.op
= CF_OP_MEM_STREAM0_BUF0
;
2074 output
.op
= CF_OP_MEM_STREAM0_BUF1
;
2077 output
.op
= CF_OP_MEM_STREAM0_BUF2
;
2080 output
.op
= CF_OP_MEM_STREAM0_BUF3
;
2083 output
.op
+= so
->output
[i
].stream
* 4;
2084 assert(output
.op
>= CF_OP_MEM_STREAM0_BUF0
&& output
.op
<= CF_OP_MEM_STREAM3_BUF3
);
2085 ctx
->enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << so
->output
[i
].stream
* 4;
2087 switch (so
->output
[i
].output_buffer
) {
2089 output
.op
= CF_OP_MEM_STREAM0
;
2092 output
.op
= CF_OP_MEM_STREAM1
;
2095 output
.op
= CF_OP_MEM_STREAM2
;
2098 output
.op
= CF_OP_MEM_STREAM3
;
2101 ctx
->enabled_stream_buffers_mask
|= 1 << so
->output
[i
].output_buffer
;
2103 r
= r600_bytecode_add_output(ctx
->bc
, &output
);
2112 static void convert_edgeflag_to_int(struct r600_shader_ctx
*ctx
)
2114 struct r600_bytecode_alu alu
;
2117 if (!ctx
->shader
->vs_out_edgeflag
)
2120 reg
= ctx
->shader
->output
[ctx
->edgeflag_output
].gpr
;
2122 /* clamp(x, 0, 1) */
2123 memset(&alu
, 0, sizeof(alu
));
2124 alu
.op
= ALU_OP1_MOV
;
2125 alu
.src
[0].sel
= reg
;
2130 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2132 memset(&alu
, 0, sizeof(alu
));
2133 alu
.op
= ALU_OP1_FLT_TO_INT
;
2134 alu
.src
[0].sel
= reg
;
2138 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2141 static int generate_gs_copy_shader(struct r600_context
*rctx
,
2142 struct r600_pipe_shader
*gs
,
2143 struct pipe_stream_output_info
*so
)
2145 struct r600_shader_ctx ctx
= {};
2146 struct r600_shader
*gs_shader
= &gs
->shader
;
2147 struct r600_pipe_shader
*cshader
;
2148 int ocnt
= gs_shader
->noutput
;
2149 struct r600_bytecode_alu alu
;
2150 struct r600_bytecode_vtx vtx
;
2151 struct r600_bytecode_output output
;
2152 struct r600_bytecode_cf
*cf_jump
, *cf_pop
,
2153 *last_exp_pos
= NULL
, *last_exp_param
= NULL
;
2154 int i
, j
, next_clip_pos
= 61, next_param
= 0;
2156 bool only_ring_0
= true;
2157 cshader
= calloc(1, sizeof(struct r600_pipe_shader
));
2161 memcpy(cshader
->shader
.output
, gs_shader
->output
, ocnt
*
2162 sizeof(struct r600_shader_io
));
2164 cshader
->shader
.noutput
= ocnt
;
2166 ctx
.shader
= &cshader
->shader
;
2167 ctx
.bc
= &ctx
.shader
->bc
;
2168 ctx
.type
= ctx
.bc
->type
= TGSI_PROCESSOR_VERTEX
;
2170 r600_bytecode_init(ctx
.bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2171 rctx
->screen
->has_compressed_msaa_texturing
);
2173 ctx
.bc
->isa
= rctx
->isa
;
2176 memset(cshader
->shader
.ring_item_sizes
, 0, sizeof(cshader
->shader
.ring_item_sizes
));
2178 /* R0.x = R0.x & 0x3fffffff */
2179 memset(&alu
, 0, sizeof(alu
));
2180 alu
.op
= ALU_OP2_AND_INT
;
2181 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2182 alu
.src
[1].value
= 0x3fffffff;
2184 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2186 /* R0.y = R0.x >> 30 */
2187 memset(&alu
, 0, sizeof(alu
));
2188 alu
.op
= ALU_OP2_LSHR_INT
;
2189 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2190 alu
.src
[1].value
= 0x1e;
2194 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2196 /* fetch vertex data from GSVS ring */
2197 for (i
= 0; i
< ocnt
; ++i
) {
2198 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2201 out
->ring_offset
= i
* 16;
2203 memset(&vtx
, 0, sizeof(vtx
));
2204 vtx
.op
= FETCH_OP_VFETCH
;
2205 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
2206 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2207 vtx
.mega_fetch_count
= 16;
2208 vtx
.offset
= out
->ring_offset
;
2209 vtx
.dst_gpr
= out
->gpr
;
2215 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2216 vtx
.use_const_fields
= 1;
2218 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
2221 r600_bytecode_add_vtx(ctx
.bc
, &vtx
);
2223 ctx
.temp_reg
= i
+ 1;
2224 for (ring
= 3; ring
>= 0; --ring
) {
2225 bool enabled
= false;
2226 for (i
= 0; i
< so
->num_outputs
; i
++) {
2227 if (so
->output
[i
].stream
== ring
) {
2230 only_ring_0
= false;
2234 if (ring
!= 0 && !enabled
) {
2235 cshader
->shader
.ring_item_sizes
[ring
] = 0;
2240 // Patch up jump label
2241 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2242 cf_pop
= ctx
.bc
->cf_last
;
2244 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2245 cf_jump
->pop_count
= 1;
2246 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2247 cf_pop
->pop_count
= 1;
2250 /* PRED_SETE_INT __, R0.y, ring */
2251 memset(&alu
, 0, sizeof(alu
));
2252 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2253 alu
.src
[0].chan
= 1;
2254 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2255 alu
.src
[1].value
= ring
;
2256 alu
.execute_mask
= 1;
2257 alu
.update_pred
= 1;
2259 r600_bytecode_add_alu_type(ctx
.bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2261 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_JUMP
);
2262 cf_jump
= ctx
.bc
->cf_last
;
2265 emit_streamout(&ctx
, so
, only_ring_0
? -1 : ring
, &cshader
->shader
.ring_item_sizes
[ring
]);
2266 cshader
->shader
.ring_item_sizes
[ring
] = ocnt
* 16;
2269 /* bc adds nops - copy it */
2270 if (ctx
.bc
->chip_class
== R600
) {
2271 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2272 alu
.op
= ALU_OP0_NOP
;
2274 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2276 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2279 /* export vertex data */
2280 /* XXX factor out common code with r600_shader_from_tgsi ? */
2281 for (i
= 0; i
< ocnt
; ++i
) {
2282 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2283 bool instream0
= true;
2284 if (out
->name
== TGSI_SEMANTIC_CLIPVERTEX
)
2287 for (j
= 0; j
< so
->num_outputs
; j
++) {
2288 if (so
->output
[j
].register_index
== i
) {
2289 if (so
->output
[j
].stream
== 0)
2291 if (so
->output
[j
].stream
> 0)
2297 memset(&output
, 0, sizeof(output
));
2298 output
.gpr
= out
->gpr
;
2299 output
.elem_size
= 3;
2300 output
.swizzle_x
= 0;
2301 output
.swizzle_y
= 1;
2302 output
.swizzle_z
= 2;
2303 output
.swizzle_w
= 3;
2304 output
.burst_count
= 1;
2305 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2306 output
.op
= CF_OP_EXPORT
;
2307 switch (out
->name
) {
2308 case TGSI_SEMANTIC_POSITION
:
2309 output
.array_base
= 60;
2310 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2313 case TGSI_SEMANTIC_PSIZE
:
2314 output
.array_base
= 61;
2315 if (next_clip_pos
== 61)
2317 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2318 output
.swizzle_y
= 7;
2319 output
.swizzle_z
= 7;
2320 output
.swizzle_w
= 7;
2321 ctx
.shader
->vs_out_misc_write
= 1;
2322 ctx
.shader
->vs_out_point_size
= 1;
2324 case TGSI_SEMANTIC_LAYER
:
2326 /* duplicate it as PARAM to pass to the pixel shader */
2327 output
.array_base
= next_param
++;
2328 r600_bytecode_add_output(ctx
.bc
, &output
);
2329 last_exp_param
= ctx
.bc
->cf_last
;
2331 output
.array_base
= 61;
2332 if (next_clip_pos
== 61)
2334 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2335 output
.swizzle_x
= 7;
2336 output
.swizzle_y
= 7;
2337 output
.swizzle_z
= 0;
2338 output
.swizzle_w
= 7;
2339 ctx
.shader
->vs_out_misc_write
= 1;
2340 ctx
.shader
->vs_out_layer
= 1;
2342 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2344 /* duplicate it as PARAM to pass to the pixel shader */
2345 output
.array_base
= next_param
++;
2346 r600_bytecode_add_output(ctx
.bc
, &output
);
2347 last_exp_param
= ctx
.bc
->cf_last
;
2349 output
.array_base
= 61;
2350 if (next_clip_pos
== 61)
2352 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2353 ctx
.shader
->vs_out_misc_write
= 1;
2354 ctx
.shader
->vs_out_viewport
= 1;
2355 output
.swizzle_x
= 7;
2356 output
.swizzle_y
= 7;
2357 output
.swizzle_z
= 7;
2358 output
.swizzle_w
= 0;
2360 case TGSI_SEMANTIC_CLIPDIST
:
2361 /* spi_sid is 0 for clipdistance outputs that were generated
2362 * for clipvertex - we don't need to pass them to PS */
2363 ctx
.shader
->clip_dist_write
= gs
->shader
.clip_dist_write
;
2365 /* duplicate it as PARAM to pass to the pixel shader */
2366 output
.array_base
= next_param
++;
2367 r600_bytecode_add_output(ctx
.bc
, &output
);
2368 last_exp_param
= ctx
.bc
->cf_last
;
2370 output
.array_base
= next_clip_pos
++;
2371 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2373 case TGSI_SEMANTIC_FOG
:
2374 output
.swizzle_y
= 4; /* 0 */
2375 output
.swizzle_z
= 4; /* 0 */
2376 output
.swizzle_w
= 5; /* 1 */
2379 output
.array_base
= next_param
++;
2382 r600_bytecode_add_output(ctx
.bc
, &output
);
2383 if (output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
)
2384 last_exp_param
= ctx
.bc
->cf_last
;
2386 last_exp_pos
= ctx
.bc
->cf_last
;
2389 if (!last_exp_pos
) {
2390 memset(&output
, 0, sizeof(output
));
2392 output
.elem_size
= 3;
2393 output
.swizzle_x
= 7;
2394 output
.swizzle_y
= 7;
2395 output
.swizzle_z
= 7;
2396 output
.swizzle_w
= 7;
2397 output
.burst_count
= 1;
2399 output
.op
= CF_OP_EXPORT
;
2400 output
.array_base
= 60;
2401 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2402 r600_bytecode_add_output(ctx
.bc
, &output
);
2403 last_exp_pos
= ctx
.bc
->cf_last
;
2406 if (!last_exp_param
) {
2407 memset(&output
, 0, sizeof(output
));
2409 output
.elem_size
= 3;
2410 output
.swizzle_x
= 7;
2411 output
.swizzle_y
= 7;
2412 output
.swizzle_z
= 7;
2413 output
.swizzle_w
= 7;
2414 output
.burst_count
= 1;
2416 output
.op
= CF_OP_EXPORT
;
2417 output
.array_base
= next_param
++;
2418 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2419 r600_bytecode_add_output(ctx
.bc
, &output
);
2420 last_exp_param
= ctx
.bc
->cf_last
;
2423 last_exp_pos
->op
= CF_OP_EXPORT_DONE
;
2424 last_exp_param
->op
= CF_OP_EXPORT_DONE
;
2426 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2427 cf_pop
= ctx
.bc
->cf_last
;
2429 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2430 cf_jump
->pop_count
= 1;
2431 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2432 cf_pop
->pop_count
= 1;
2434 if (ctx
.bc
->chip_class
== CAYMAN
)
2435 cm_bytecode_add_cf_end(ctx
.bc
);
2437 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2438 ctx
.bc
->cf_last
->end_of_program
= 1;
2441 gs
->gs_copy_shader
= cshader
;
2442 cshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
2446 return r600_bytecode_build(ctx
.bc
);
2449 static int emit_inc_ring_offset(struct r600_shader_ctx
*ctx
, int idx
, bool ind
)
2452 struct r600_bytecode_alu alu
;
2455 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2456 alu
.op
= ALU_OP2_ADD_INT
;
2457 alu
.src
[0].sel
= ctx
->gs_export_gpr_tregs
[idx
];
2458 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2459 alu
.src
[1].value
= ctx
->gs_out_ring_offset
>> 4;
2460 alu
.dst
.sel
= ctx
->gs_export_gpr_tregs
[idx
];
2463 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2470 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
)
2472 struct r600_bytecode_output output
;
2473 int i
, k
, ring_offset
;
2474 int effective_stream
= stream
== -1 ? 0 : stream
;
2477 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2478 if (ctx
->gs_for_vs
) {
2479 /* for ES we need to lookup corresponding ring offset expected by GS
2480 * (map this output to GS input by name and sid) */
2481 /* FIXME precompute offsets */
2483 for(k
= 0; k
< ctx
->gs_for_vs
->ninput
; ++k
) {
2484 struct r600_shader_io
*in
= &ctx
->gs_for_vs
->input
[k
];
2485 struct r600_shader_io
*out
= &ctx
->shader
->output
[i
];
2486 if (in
->name
== out
->name
&& in
->sid
== out
->sid
)
2487 ring_offset
= in
->ring_offset
;
2490 if (ring_offset
== -1)
2493 ring_offset
= idx
* 16;
2497 if (stream
> 0 && ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2499 /* next_ring_offset after parsing input decls contains total size of
2500 * single vertex data, gs_next_vertex - current vertex index */
2502 ring_offset
+= ctx
->gs_out_ring_offset
* ctx
->gs_next_vertex
;
2504 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2505 output
.gpr
= ctx
->shader
->output
[i
].gpr
;
2506 output
.elem_size
= 3;
2507 output
.comp_mask
= 0xF;
2508 output
.burst_count
= 1;
2511 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
2513 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2518 output
.op
= CF_OP_MEM_RING
; break;
2520 output
.op
= CF_OP_MEM_RING1
; break;
2522 output
.op
= CF_OP_MEM_RING2
; break;
2524 output
.op
= CF_OP_MEM_RING3
; break;
2528 output
.array_base
= ring_offset
>> 2; /* in dwords */
2529 output
.array_size
= 0xfff;
2530 output
.index_gpr
= ctx
->gs_export_gpr_tregs
[effective_stream
];
2532 output
.array_base
= ring_offset
>> 2; /* in dwords */
2533 r600_bytecode_add_output(ctx
->bc
, &output
);
2536 ++ctx
->gs_next_vertex
;
2541 static int r600_fetch_tess_io_info(struct r600_shader_ctx
*ctx
)
2544 struct r600_bytecode_vtx vtx
;
2545 int temp_val
= ctx
->temp_reg
;
2546 /* need to store the TCS output somewhere */
2547 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2549 V_SQ_ALU_SRC_LITERAL
, 0,
2554 /* used by VS/TCS */
2555 if (ctx
->tess_input_info
) {
2556 /* fetch tcs input values into resv space */
2557 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2558 vtx
.op
= FETCH_OP_VFETCH
;
2559 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2560 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2561 vtx
.mega_fetch_count
= 16;
2562 vtx
.data_format
= FMT_32_32_32_32
;
2563 vtx
.num_format_all
= 2;
2564 vtx
.format_comp_all
= 1;
2565 vtx
.use_const_fields
= 0;
2566 vtx
.endian
= r600_endian_swap(32);
2567 vtx
.srf_mode_all
= 1;
2569 vtx
.dst_gpr
= ctx
->tess_input_info
;
2574 vtx
.src_gpr
= temp_val
;
2577 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2582 /* used by TCS/TES */
2583 if (ctx
->tess_output_info
) {
2584 /* fetch tcs output values into resv space */
2585 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2586 vtx
.op
= FETCH_OP_VFETCH
;
2587 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2588 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2589 vtx
.mega_fetch_count
= 16;
2590 vtx
.data_format
= FMT_32_32_32_32
;
2591 vtx
.num_format_all
= 2;
2592 vtx
.format_comp_all
= 1;
2593 vtx
.use_const_fields
= 0;
2594 vtx
.endian
= r600_endian_swap(32);
2595 vtx
.srf_mode_all
= 1;
2597 vtx
.dst_gpr
= ctx
->tess_output_info
;
2602 vtx
.src_gpr
= temp_val
;
2605 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2612 static int emit_lds_vs_writes(struct r600_shader_ctx
*ctx
)
2617 /* fetch tcs input values into input_vals */
2618 ctx
->tess_input_info
= r600_get_temp(ctx
);
2619 ctx
->tess_output_info
= 0;
2620 r
= r600_fetch_tess_io_info(ctx
);
2624 temp_reg
= r600_get_temp(ctx
);
2625 /* dst reg contains LDS address stride * idx */
2626 /* MUL vertexID, vertex_dw_stride */
2627 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
2629 ctx
->tess_input_info
, 1,
2630 0, 1); /* rel id in r0.y? */
2634 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2635 struct r600_bytecode_alu alu
;
2636 int param
= r600_get_lds_unique_index(ctx
->shader
->output
[i
].name
, ctx
->shader
->output
[i
].sid
);
2639 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2642 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2647 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2649 temp_reg
, param
? 1 : 0,
2650 V_SQ_ALU_SRC_LITERAL
, 8);
2655 for (j
= 0; j
< 2; j
++) {
2656 int chan
= (j
== 1) ? 2 : (param
? 1 : 0);
2657 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2658 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2659 alu
.src
[0].sel
= temp_reg
;
2660 alu
.src
[0].chan
= chan
;
2661 alu
.src
[1].sel
= ctx
->shader
->output
[i
].gpr
;
2662 alu
.src
[1].chan
= j
* 2;
2663 alu
.src
[2].sel
= ctx
->shader
->output
[i
].gpr
;
2664 alu
.src
[2].chan
= (j
* 2) + 1;
2668 alu
.is_lds_idx_op
= true;
2669 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2677 static int r600_store_tcs_output(struct r600_shader_ctx
*ctx
)
2679 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2680 const struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
2682 int temp_reg
= r600_get_temp(ctx
);
2683 struct r600_bytecode_alu alu
;
2684 unsigned write_mask
= dst
->Register
.WriteMask
;
2686 if (inst
->Dst
[0].Register
.File
!= TGSI_FILE_OUTPUT
)
2689 r
= get_lds_offset0(ctx
, 1, temp_reg
, dst
->Register
.Dimension
? false : true);
2693 /* the base address is now in temp.x */
2694 r
= r600_get_byte_address(ctx
, temp_reg
,
2695 &inst
->Dst
[0], NULL
, ctx
->tess_output_info
, 1);
2700 lasti
= tgsi_last_instruction(write_mask
);
2701 for (i
= 1; i
<= lasti
; i
++) {
2703 if (!(write_mask
& (1 << i
)))
2705 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2708 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2713 for (i
= 0; i
<= lasti
; i
++) {
2714 if (!(write_mask
& (1 << i
)))
2717 if ((i
== 0 && ((write_mask
& 3) == 3)) ||
2718 (i
== 2 && ((write_mask
& 0xc) == 0xc))) {
2719 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2720 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2721 alu
.src
[0].sel
= temp_reg
;
2722 alu
.src
[0].chan
= i
;
2724 alu
.src
[1].sel
= dst
->Register
.Index
;
2725 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2726 alu
.src
[1].chan
= i
;
2728 alu
.src
[2].sel
= dst
->Register
.Index
;
2729 alu
.src
[2].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2730 alu
.src
[2].chan
= i
+ 1;
2734 alu
.is_lds_idx_op
= true;
2735 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2741 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2742 alu
.op
= LDS_OP2_LDS_WRITE
;
2743 alu
.src
[0].sel
= temp_reg
;
2744 alu
.src
[0].chan
= i
;
2746 alu
.src
[1].sel
= dst
->Register
.Index
;
2747 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2748 alu
.src
[1].chan
= i
;
2750 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
2753 alu
.is_lds_idx_op
= true;
2754 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2761 static int r600_tess_factor_read(struct r600_shader_ctx
*ctx
,
2765 unsigned temp_reg
= r600_get_temp(ctx
);
2766 unsigned name
= ctx
->shader
->output
[output_idx
].name
;
2767 int dreg
= ctx
->shader
->output
[output_idx
].gpr
;
2770 param
= r600_get_lds_unique_index(name
, 0);
2771 r
= get_lds_offset0(ctx
, 1, temp_reg
, true);
2775 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2778 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2782 do_lds_fetch_values(ctx
, temp_reg
, dreg
);
2786 static int r600_emit_tess_factor(struct r600_shader_ctx
*ctx
)
2789 int stride
, outer_comps
, inner_comps
;
2790 int tessinner_idx
= -1, tessouter_idx
= -1;
2792 int temp_reg
= r600_get_temp(ctx
);
2793 int treg
[3] = {-1, -1, -1};
2794 struct r600_bytecode_alu alu
;
2795 struct r600_bytecode_cf
*cf_jump
, *cf_pop
;
2797 /* only execute factor emission for invocation 0 */
2798 /* PRED_SETE_INT __, R0.x, 0 */
2799 memset(&alu
, 0, sizeof(alu
));
2800 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2801 alu
.src
[0].chan
= 2;
2802 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2803 alu
.execute_mask
= 1;
2804 alu
.update_pred
= 1;
2806 r600_bytecode_add_alu_type(ctx
->bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2808 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
2809 cf_jump
= ctx
->bc
->cf_last
;
2811 treg
[0] = r600_get_temp(ctx
);
2812 switch (ctx
->shader
->tcs_prim_mode
) {
2813 case PIPE_PRIM_LINES
:
2814 stride
= 8; /* 2 dwords, 1 vec2 store */
2818 case PIPE_PRIM_TRIANGLES
:
2819 stride
= 16; /* 4 dwords, 1 vec4 store */
2822 treg
[1] = r600_get_temp(ctx
);
2824 case PIPE_PRIM_QUADS
:
2825 stride
= 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2828 treg
[1] = r600_get_temp(ctx
);
2829 treg
[2] = r600_get_temp(ctx
);
2836 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2837 /* TF_WRITE takes index in R.x, value in R.y */
2838 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2839 if (ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_TESSINNER
)
2841 if (ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_TESSOUTER
)
2845 if (tessouter_idx
== -1)
2848 if (tessinner_idx
== -1 && inner_comps
)
2851 if (tessouter_idx
!= -1) {
2852 r
= r600_tess_factor_read(ctx
, tessouter_idx
);
2857 if (tessinner_idx
!= -1) {
2858 r
= r600_tess_factor_read(ctx
, tessinner_idx
);
2863 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2864 /* r.x = relpatchid(r0.y) * tf_stride */
2866 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2867 /* add incoming r0.w to it: t.x = t.x + r0.w */
2868 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
2871 V_SQ_ALU_SRC_LITERAL
, stride
,
2876 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2877 int out_idx
= i
>= outer_comps
? tessinner_idx
: tessouter_idx
;
2878 int out_comp
= i
>= outer_comps
? i
- outer_comps
: i
;
2880 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2881 treg
[i
/ 2], (2 * (i
% 2)),
2883 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2886 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2887 treg
[i
/ 2], 1 + (2 * (i
%2)),
2888 ctx
->shader
->output
[out_idx
].gpr
, out_comp
,
2893 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2894 struct r600_bytecode_gds gds
;
2896 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
2897 gds
.src_gpr
= treg
[i
/ 2];
2898 gds
.src_sel_x
= 2 * (i
% 2);
2899 gds
.src_sel_y
= 1 + (2 * (i
% 2));
2905 gds
.op
= FETCH_OP_TF_WRITE
;
2906 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
2911 // Patch up jump label
2912 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
2913 cf_pop
= ctx
->bc
->cf_last
;
2915 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2916 cf_jump
->pop_count
= 1;
2917 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2918 cf_pop
->pop_count
= 1;
2923 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
2924 struct r600_pipe_shader
*pipeshader
,
2925 union r600_shader_key key
)
2927 struct r600_screen
*rscreen
= rctx
->screen
;
2928 struct r600_shader
*shader
= &pipeshader
->shader
;
2929 struct tgsi_token
*tokens
= pipeshader
->selector
->tokens
;
2930 struct pipe_stream_output_info so
= pipeshader
->selector
->so
;
2931 struct tgsi_full_immediate
*immediate
;
2932 struct r600_shader_ctx ctx
;
2933 struct r600_bytecode_output output
[32];
2934 unsigned output_done
, noutput
;
2937 int next_param_base
= 0, next_clip_base
;
2938 int max_color_exports
= MAX2(key
.ps
.nr_cbufs
, 1);
2939 /* Declarations used by llvm code */
2940 bool use_llvm
= false;
2942 bool ring_outputs
= false;
2943 bool lds_outputs
= false;
2944 bool lds_inputs
= false;
2945 bool pos_emitted
= false;
2947 #ifdef R600_USE_LLVM
2948 use_llvm
= rscreen
->b
.debug_flags
& DBG_LLVM
;
2950 ctx
.bc
= &shader
->bc
;
2951 ctx
.shader
= shader
;
2952 ctx
.native_integers
= true;
2955 r600_bytecode_init(ctx
.bc
, rscreen
->b
.chip_class
, rscreen
->b
.family
,
2956 rscreen
->has_compressed_msaa_texturing
);
2957 ctx
.tokens
= tokens
;
2958 tgsi_scan_shader(tokens
, &ctx
.info
);
2959 shader
->indirect_files
= ctx
.info
.indirect_files
;
2961 shader
->uses_doubles
= ctx
.info
.uses_doubles
;
2963 indirect_gprs
= ctx
.info
.indirect_files
& ~((1 << TGSI_FILE_CONSTANT
) | (1 << TGSI_FILE_SAMPLER
));
2964 tgsi_parse_init(&ctx
.parse
, tokens
);
2965 ctx
.type
= ctx
.info
.processor
;
2966 shader
->processor_type
= ctx
.type
;
2967 ctx
.bc
->type
= shader
->processor_type
;
2970 case TGSI_PROCESSOR_VERTEX
:
2971 shader
->vs_as_gs_a
= key
.vs
.as_gs_a
;
2972 shader
->vs_as_es
= key
.vs
.as_es
;
2973 shader
->vs_as_ls
= key
.vs
.as_ls
;
2974 if (shader
->vs_as_es
)
2975 ring_outputs
= true;
2976 if (shader
->vs_as_ls
)
2979 case TGSI_PROCESSOR_GEOMETRY
:
2980 ring_outputs
= true;
2982 case TGSI_PROCESSOR_TESS_CTRL
:
2983 shader
->tcs_prim_mode
= key
.tcs
.prim_mode
;
2987 case TGSI_PROCESSOR_TESS_EVAL
:
2988 shader
->tes_as_es
= key
.tes
.as_es
;
2990 if (shader
->tes_as_es
)
2991 ring_outputs
= true;
2993 case TGSI_PROCESSOR_FRAGMENT
:
2994 shader
->two_side
= key
.ps
.color_two_side
;
3000 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3001 ctx
.gs_for_vs
= &rctx
->gs_shader
->current
->shader
;
3003 ctx
.gs_for_vs
= NULL
;
3006 ctx
.next_ring_offset
= 0;
3007 ctx
.gs_out_ring_offset
= 0;
3008 ctx
.gs_next_vertex
= 0;
3009 ctx
.gs_stream_output_info
= &so
;
3012 ctx
.fixed_pt_position_gpr
= -1;
3013 ctx
.fragcoord_input
= -1;
3014 ctx
.colors_used
= 0;
3015 ctx
.clip_vertex_write
= 0;
3017 shader
->nr_ps_color_exports
= 0;
3018 shader
->nr_ps_max_color_exports
= 0;
3021 /* register allocations */
3022 /* Values [0,127] correspond to GPR[0..127].
3023 * Values [128,159] correspond to constant buffer bank 0
3024 * Values [160,191] correspond to constant buffer bank 1
3025 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3026 * Values [256,287] correspond to constant buffer bank 2 (EG)
3027 * Values [288,319] correspond to constant buffer bank 3 (EG)
3028 * Other special values are shown in the list below.
3029 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3030 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3031 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3032 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3033 * 248 SQ_ALU_SRC_0: special constant 0.0.
3034 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3035 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3036 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3037 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3038 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3039 * 254 SQ_ALU_SRC_PV: previous vector result.
3040 * 255 SQ_ALU_SRC_PS: previous scalar result.
3042 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
3043 ctx
.file_offset
[i
] = 0;
3046 #ifdef R600_USE_LLVM
3047 if (use_llvm
&& ctx
.info
.indirect_files
&& (ctx
.info
.indirect_files
& (1 << TGSI_FILE_CONSTANT
)) != ctx
.info
.indirect_files
) {
3048 fprintf(stderr
, "Warning: R600 LLVM backend does not support "
3049 "indirect adressing. Falling back to TGSI "
3054 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
3055 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3057 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CALL_FS
);
3060 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
) {
3061 if (ctx
.bc
->chip_class
>= EVERGREEN
)
3062 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
3064 ctx
.file_offset
[TGSI_FILE_INPUT
] = allocate_system_value_inputs(&ctx
, ctx
.file_offset
[TGSI_FILE_INPUT
]);
3066 if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
3067 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3068 ctx
.file_offset
[TGSI_FILE_INPUT
] = 2;
3070 if (ctx
.type
== TGSI_PROCESSOR_TESS_CTRL
)
3071 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3072 if (ctx
.type
== TGSI_PROCESSOR_TESS_EVAL
) {
3073 bool add_tesscoord
= false, add_tess_inout
= false;
3074 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3075 for (i
= 0; i
< PIPE_MAX_SHADER_INPUTS
; i
++) {
3076 /* if we have tesscoord save one reg */
3077 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSCOORD
)
3078 add_tesscoord
= true;
3079 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSINNER
||
3080 ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSOUTER
)
3081 add_tess_inout
= true;
3083 if (add_tesscoord
|| add_tess_inout
)
3084 ctx
.file_offset
[TGSI_FILE_INPUT
]++;
3086 ctx
.file_offset
[TGSI_FILE_INPUT
]+=2;
3088 ctx
.use_llvm
= use_llvm
;
3091 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
3092 ctx
.file_offset
[TGSI_FILE_INPUT
];
3094 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
3095 ctx
.file_offset
[TGSI_FILE_INPUT
] +
3096 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3098 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
3099 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
3101 /* Outside the GPR range. This will be translated to one of the
3102 * kcache banks later. */
3103 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
3105 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
3106 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
3107 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
3108 ctx
.bc
->index_reg
[0] = ctx
.bc
->ar_reg
+ 1;
3109 ctx
.bc
->index_reg
[1] = ctx
.bc
->ar_reg
+ 2;
3111 if (ctx
.type
== TGSI_PROCESSOR_TESS_CTRL
) {
3112 ctx
.tess_input_info
= ctx
.bc
->ar_reg
+ 3;
3113 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 4;
3114 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 5;
3115 } else if (ctx
.type
== TGSI_PROCESSOR_TESS_EVAL
) {
3116 ctx
.tess_input_info
= 0;
3117 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 3;
3118 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 4;
3119 } else if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
3120 ctx
.gs_export_gpr_tregs
[0] = ctx
.bc
->ar_reg
+ 3;
3121 ctx
.gs_export_gpr_tregs
[1] = ctx
.bc
->ar_reg
+ 4;
3122 ctx
.gs_export_gpr_tregs
[2] = ctx
.bc
->ar_reg
+ 5;
3123 ctx
.gs_export_gpr_tregs
[3] = ctx
.bc
->ar_reg
+ 6;
3124 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 7;
3126 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 3;
3129 shader
->max_arrays
= 0;
3130 shader
->num_arrays
= 0;
3131 if (indirect_gprs
) {
3133 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_INPUT
)) {
3134 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_INPUT
],
3135 ctx
.file_offset
[TGSI_FILE_OUTPUT
] -
3136 ctx
.file_offset
[TGSI_FILE_INPUT
],
3139 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_OUTPUT
)) {
3140 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3141 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] -
3142 ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3148 ctx
.literals
= NULL
;
3150 shader
->fs_write_all
= ctx
.info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
3151 ctx
.info
.colors_written
== 1;
3152 shader
->vs_position_window_space
= ctx
.info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
3153 shader
->ps_conservative_z
= (uint8_t)ctx
.info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
];
3155 if (shader
->vs_as_gs_a
)
3156 vs_add_primid_output(&ctx
, key
.vs
.prim_id_out
);
3158 if (ctx
.type
== TGSI_PROCESSOR_TESS_EVAL
)
3159 r600_fetch_tess_io_info(&ctx
);
3161 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3162 tgsi_parse_token(&ctx
.parse
);
3163 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3164 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3165 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
3166 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
3167 if(ctx
.literals
== NULL
) {
3171 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
3172 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
3173 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
3174 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
3177 case TGSI_TOKEN_TYPE_DECLARATION
:
3178 r
= tgsi_declaration(&ctx
);
3182 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3183 case TGSI_TOKEN_TYPE_PROPERTY
:
3186 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
3192 shader
->ring_item_sizes
[0] = ctx
.next_ring_offset
;
3193 shader
->ring_item_sizes
[1] = 0;
3194 shader
->ring_item_sizes
[2] = 0;
3195 shader
->ring_item_sizes
[3] = 0;
3197 /* Process two side if needed */
3198 if (shader
->two_side
&& ctx
.colors_used
) {
3199 int i
, count
= ctx
.shader
->ninput
;
3200 unsigned next_lds_loc
= ctx
.shader
->nlds
;
3202 /* additional inputs will be allocated right after the existing inputs,
3203 * we won't need them after the color selection, so we don't need to
3204 * reserve these gprs for the rest of the shader code and to adjust
3205 * output offsets etc. */
3206 int gpr
= ctx
.file_offset
[TGSI_FILE_INPUT
] +
3207 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3209 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3210 if (ctx
.face_gpr
== -1) {
3211 i
= ctx
.shader
->ninput
++;
3212 ctx
.shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
3213 ctx
.shader
->input
[i
].spi_sid
= 0;
3214 ctx
.shader
->input
[i
].gpr
= gpr
++;
3215 ctx
.face_gpr
= ctx
.shader
->input
[i
].gpr
;
3218 for (i
= 0; i
< count
; i
++) {
3219 if (ctx
.shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3220 int ni
= ctx
.shader
->ninput
++;
3221 memcpy(&ctx
.shader
->input
[ni
],&ctx
.shader
->input
[i
], sizeof(struct r600_shader_io
));
3222 ctx
.shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
3223 ctx
.shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
.shader
->input
[ni
]);
3224 ctx
.shader
->input
[ni
].gpr
= gpr
++;
3225 // TGSI to LLVM needs to know the lds position of inputs.
3226 // Non LLVM path computes it later (in process_twoside_color)
3227 ctx
.shader
->input
[ni
].lds_pos
= next_lds_loc
++;
3228 ctx
.shader
->input
[i
].back_color_input
= ni
;
3229 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
3230 if ((r
= evergreen_interp_input(&ctx
, ni
)))
3237 /* LLVM backend setup */
3238 #ifdef R600_USE_LLVM
3240 struct radeon_llvm_context radeon_llvm_ctx
;
3242 bool dump
= r600_can_dump_shader(&rscreen
->b
,
3243 tgsi_get_processor_type(tokens
));
3244 boolean use_kill
= false;
3246 memset(&radeon_llvm_ctx
, 0, sizeof(radeon_llvm_ctx
));
3247 radeon_llvm_ctx
.type
= ctx
.type
;
3248 radeon_llvm_ctx
.two_side
= shader
->two_side
;
3249 radeon_llvm_ctx
.face_gpr
= ctx
.face_gpr
;
3250 radeon_llvm_ctx
.inputs_count
= ctx
.shader
->ninput
+ 1;
3251 radeon_llvm_ctx
.r600_inputs
= ctx
.shader
->input
;
3252 radeon_llvm_ctx
.r600_outputs
= ctx
.shader
->output
;
3253 radeon_llvm_ctx
.color_buffer_count
= max_color_exports
;
3254 radeon_llvm_ctx
.chip_class
= ctx
.bc
->chip_class
;
3255 radeon_llvm_ctx
.fs_color_all
= shader
->fs_write_all
&& (rscreen
->b
.chip_class
>= EVERGREEN
);
3256 radeon_llvm_ctx
.stream_outputs
= &so
;
3257 radeon_llvm_ctx
.alpha_to_one
= key
.ps
.alpha_to_one
;
3258 radeon_llvm_ctx
.has_compressed_msaa_texturing
=
3259 ctx
.bc
->has_compressed_msaa_texturing
;
3260 mod
= r600_tgsi_llvm(&radeon_llvm_ctx
, tokens
);
3261 ctx
.shader
->has_txq_cube_array_z_comp
= radeon_llvm_ctx
.has_txq_cube_array_z_comp
;
3262 ctx
.shader
->uses_tex_buffers
= radeon_llvm_ctx
.uses_tex_buffers
;
3264 if (r600_llvm_compile(mod
, rscreen
->b
.family
, ctx
.bc
, &use_kill
,
3265 dump
, &rctx
->b
.debug
)) {
3266 radeon_llvm_dispose(&radeon_llvm_ctx
);
3268 fprintf(stderr
, "R600 LLVM backend failed to compile "
3269 "shader. Falling back to TGSI\n");
3271 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
3272 ctx
.file_offset
[TGSI_FILE_INPUT
];
3275 ctx
.shader
->uses_kill
= use_kill
;
3276 radeon_llvm_dispose(&radeon_llvm_ctx
);
3279 /* End of LLVM backend setup */
3281 if (shader
->fs_write_all
&& rscreen
->b
.chip_class
>= EVERGREEN
)
3282 shader
->nr_ps_max_color_exports
= 8;
3285 if (ctx
.fragcoord_input
>= 0) {
3286 if (ctx
.bc
->chip_class
== CAYMAN
) {
3287 for (j
= 0 ; j
< 4; j
++) {
3288 struct r600_bytecode_alu alu
;
3289 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3290 alu
.op
= ALU_OP1_RECIP_IEEE
;
3291 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3292 alu
.src
[0].chan
= 3;
3294 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3296 alu
.dst
.write
= (j
== 3);
3298 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3302 struct r600_bytecode_alu alu
;
3303 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3304 alu
.op
= ALU_OP1_RECIP_IEEE
;
3305 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3306 alu
.src
[0].chan
= 3;
3308 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3312 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3317 if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
3318 struct r600_bytecode_alu alu
;
3321 /* GS thread with no output workaround - emit a cut at start of GS */
3322 if (ctx
.bc
->chip_class
== R600
)
3323 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CUT_VERTEX
);
3325 for (j
= 0; j
< 4; j
++) {
3326 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3327 alu
.op
= ALU_OP1_MOV
;
3328 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
3329 alu
.src
[0].value
= 0;
3330 alu
.dst
.sel
= ctx
.gs_export_gpr_tregs
[j
];
3333 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3339 if (ctx
.type
== TGSI_PROCESSOR_TESS_CTRL
)
3340 r600_fetch_tess_io_info(&ctx
);
3342 if (shader
->two_side
&& ctx
.colors_used
) {
3343 if ((r
= process_twoside_color_inputs(&ctx
)))
3347 tgsi_parse_init(&ctx
.parse
, tokens
);
3348 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3349 tgsi_parse_token(&ctx
.parse
);
3350 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3351 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3352 r
= tgsi_is_supported(&ctx
);
3355 ctx
.max_driver_temp_used
= 0;
3356 /* reserve first tmp for everyone */
3357 r600_get_temp(&ctx
);
3359 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3360 if ((r
= tgsi_split_constant(&ctx
)))
3362 if ((r
= tgsi_split_literal_constant(&ctx
)))
3364 if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
3365 if ((r
= tgsi_split_gs_inputs(&ctx
)))
3367 } else if (lds_inputs
) {
3368 if ((r
= tgsi_split_lds_inputs(&ctx
)))
3371 if (ctx
.bc
->chip_class
== CAYMAN
)
3372 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
3373 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
3374 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
3376 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
3377 r
= ctx
.inst_info
->process(&ctx
);
3381 if (ctx
.type
== TGSI_PROCESSOR_TESS_CTRL
) {
3382 r
= r600_store_tcs_output(&ctx
);
3393 /* Reset the temporary register counter. */
3394 ctx
.max_driver_temp_used
= 0;
3396 noutput
= shader
->noutput
;
3398 if (!ring_outputs
&& ctx
.clip_vertex_write
) {
3399 unsigned clipdist_temp
[2];
3401 clipdist_temp
[0] = r600_get_temp(&ctx
);
3402 clipdist_temp
[1] = r600_get_temp(&ctx
);
3404 /* need to convert a clipvertex write into clipdistance writes and not export
3405 the clip vertex anymore */
3407 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
3408 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3409 shader
->output
[noutput
].gpr
= clipdist_temp
[0];
3411 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3412 shader
->output
[noutput
].gpr
= clipdist_temp
[1];
3415 /* reset spi_sid for clipvertex output to avoid confusing spi */
3416 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
3418 shader
->clip_dist_write
= 0xFF;
3420 for (i
= 0; i
< 8; i
++) {
3424 for (j
= 0; j
< 4; j
++) {
3425 struct r600_bytecode_alu alu
;
3426 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3427 alu
.op
= ALU_OP2_DOT4
;
3428 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
3429 alu
.src
[0].chan
= j
;
3431 alu
.src
[1].sel
= 512 + i
;
3432 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
3433 alu
.src
[1].chan
= j
;
3435 alu
.dst
.sel
= clipdist_temp
[oreg
];
3437 alu
.dst
.write
= (j
== ochan
);
3441 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3448 /* Add stream outputs. */
3449 if (!use_llvm
&& so
.num_outputs
) {
3451 if (!lds_outputs
&& !ring_outputs
&& ctx
.type
== TGSI_PROCESSOR_VERTEX
)
3453 if (!ring_outputs
&& ctx
.type
== TGSI_PROCESSOR_TESS_EVAL
)
3456 emit_streamout(&ctx
, &so
, -1, NULL
);
3458 pipeshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
3459 convert_edgeflag_to_int(&ctx
);
3461 if (ctx
.type
== TGSI_PROCESSOR_TESS_CTRL
)
3462 r600_emit_tess_factor(&ctx
);
3465 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
3466 if (ctx
.shader
->noutput
)
3467 emit_lds_vs_writes(&ctx
);
3469 } else if (ring_outputs
) {
3470 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3471 ctx
.gs_export_gpr_tregs
[0] = r600_get_temp(&ctx
);
3472 ctx
.gs_export_gpr_tregs
[1] = -1;
3473 ctx
.gs_export_gpr_tregs
[2] = -1;
3474 ctx
.gs_export_gpr_tregs
[3] = -1;
3476 emit_gs_ring_writes(&ctx
, &so
, -1, FALSE
);
3480 next_clip_base
= shader
->vs_out_misc_write
? 62 : 61;
3482 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
3483 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3484 output
[j
].gpr
= shader
->output
[i
].gpr
;
3485 output
[j
].elem_size
= 3;
3486 output
[j
].swizzle_x
= 0;
3487 output
[j
].swizzle_y
= 1;
3488 output
[j
].swizzle_z
= 2;
3489 output
[j
].swizzle_w
= 3;
3490 output
[j
].burst_count
= 1;
3491 output
[j
].type
= -1;
3492 output
[j
].op
= CF_OP_EXPORT
;
3494 case TGSI_PROCESSOR_VERTEX
:
3495 case TGSI_PROCESSOR_TESS_EVAL
:
3496 switch (shader
->output
[i
].name
) {
3497 case TGSI_SEMANTIC_POSITION
:
3498 output
[j
].array_base
= 60;
3499 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3503 case TGSI_SEMANTIC_PSIZE
:
3504 output
[j
].array_base
= 61;
3505 output
[j
].swizzle_y
= 7;
3506 output
[j
].swizzle_z
= 7;
3507 output
[j
].swizzle_w
= 7;
3508 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3511 case TGSI_SEMANTIC_EDGEFLAG
:
3512 output
[j
].array_base
= 61;
3513 output
[j
].swizzle_x
= 7;
3514 output
[j
].swizzle_y
= 0;
3515 output
[j
].swizzle_z
= 7;
3516 output
[j
].swizzle_w
= 7;
3517 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3520 case TGSI_SEMANTIC_LAYER
:
3521 /* spi_sid is 0 for outputs that are
3522 * not consumed by PS */
3523 if (shader
->output
[i
].spi_sid
) {
3524 output
[j
].array_base
= next_param_base
++;
3525 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3527 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3529 output
[j
].array_base
= 61;
3530 output
[j
].swizzle_x
= 7;
3531 output
[j
].swizzle_y
= 7;
3532 output
[j
].swizzle_z
= 0;
3533 output
[j
].swizzle_w
= 7;
3534 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3537 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
3538 /* spi_sid is 0 for outputs that are
3539 * not consumed by PS */
3540 if (shader
->output
[i
].spi_sid
) {
3541 output
[j
].array_base
= next_param_base
++;
3542 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3544 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3546 output
[j
].array_base
= 61;
3547 output
[j
].swizzle_x
= 7;
3548 output
[j
].swizzle_y
= 7;
3549 output
[j
].swizzle_z
= 7;
3550 output
[j
].swizzle_w
= 0;
3551 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3554 case TGSI_SEMANTIC_CLIPVERTEX
:
3557 case TGSI_SEMANTIC_CLIPDIST
:
3558 output
[j
].array_base
= next_clip_base
++;
3559 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3561 /* spi_sid is 0 for clipdistance outputs that were generated
3562 * for clipvertex - we don't need to pass them to PS */
3563 if (shader
->output
[i
].spi_sid
) {
3565 /* duplicate it as PARAM to pass to the pixel shader */
3566 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3567 output
[j
].array_base
= next_param_base
++;
3568 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3571 case TGSI_SEMANTIC_FOG
:
3572 output
[j
].swizzle_y
= 4; /* 0 */
3573 output
[j
].swizzle_z
= 4; /* 0 */
3574 output
[j
].swizzle_w
= 5; /* 1 */
3576 case TGSI_SEMANTIC_PRIMID
:
3577 output
[j
].swizzle_x
= 2;
3578 output
[j
].swizzle_y
= 4; /* 0 */
3579 output
[j
].swizzle_z
= 4; /* 0 */
3580 output
[j
].swizzle_w
= 4; /* 0 */
3585 case TGSI_PROCESSOR_FRAGMENT
:
3586 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3587 /* never export more colors than the number of CBs */
3588 if (shader
->output
[i
].sid
>= max_color_exports
) {
3593 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3594 output
[j
].array_base
= shader
->output
[i
].sid
;
3595 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3596 shader
->nr_ps_color_exports
++;
3597 if (shader
->fs_write_all
&& (rscreen
->b
.chip_class
>= EVERGREEN
)) {
3598 for (k
= 1; k
< max_color_exports
; k
++) {
3600 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3601 output
[j
].gpr
= shader
->output
[i
].gpr
;
3602 output
[j
].elem_size
= 3;
3603 output
[j
].swizzle_x
= 0;
3604 output
[j
].swizzle_y
= 1;
3605 output
[j
].swizzle_z
= 2;
3606 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3607 output
[j
].burst_count
= 1;
3608 output
[j
].array_base
= k
;
3609 output
[j
].op
= CF_OP_EXPORT
;
3610 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3611 shader
->nr_ps_color_exports
++;
3614 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
3615 output
[j
].array_base
= 61;
3616 output
[j
].swizzle_x
= 2;
3617 output
[j
].swizzle_y
= 7;
3618 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3619 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3620 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
3621 output
[j
].array_base
= 61;
3622 output
[j
].swizzle_x
= 7;
3623 output
[j
].swizzle_y
= 1;
3624 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3625 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3626 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
3627 output
[j
].array_base
= 61;
3628 output
[j
].swizzle_x
= 7;
3629 output
[j
].swizzle_y
= 7;
3630 output
[j
].swizzle_z
= 0;
3631 output
[j
].swizzle_w
= 7;
3632 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3634 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
3639 case TGSI_PROCESSOR_TESS_CTRL
:
3642 R600_ERR("unsupported processor type %d\n", ctx
.type
);
3647 if (output
[j
].type
==-1) {
3648 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3649 output
[j
].array_base
= next_param_base
++;
3653 /* add fake position export */
3654 if ((ctx
.type
== TGSI_PROCESSOR_VERTEX
|| ctx
.type
== TGSI_PROCESSOR_TESS_EVAL
) && pos_emitted
== false) {
3655 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3657 output
[j
].elem_size
= 3;
3658 output
[j
].swizzle_x
= 7;
3659 output
[j
].swizzle_y
= 7;
3660 output
[j
].swizzle_z
= 7;
3661 output
[j
].swizzle_w
= 7;
3662 output
[j
].burst_count
= 1;
3663 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3664 output
[j
].array_base
= 60;
3665 output
[j
].op
= CF_OP_EXPORT
;
3669 /* add fake param output for vertex shader if no param is exported */
3670 if ((ctx
.type
== TGSI_PROCESSOR_VERTEX
|| ctx
.type
== TGSI_PROCESSOR_TESS_EVAL
) && next_param_base
== 0) {
3671 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3673 output
[j
].elem_size
= 3;
3674 output
[j
].swizzle_x
= 7;
3675 output
[j
].swizzle_y
= 7;
3676 output
[j
].swizzle_z
= 7;
3677 output
[j
].swizzle_w
= 7;
3678 output
[j
].burst_count
= 1;
3679 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3680 output
[j
].array_base
= 0;
3681 output
[j
].op
= CF_OP_EXPORT
;
3685 /* add fake pixel export */
3686 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& shader
->nr_ps_color_exports
== 0) {
3687 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3689 output
[j
].elem_size
= 3;
3690 output
[j
].swizzle_x
= 7;
3691 output
[j
].swizzle_y
= 7;
3692 output
[j
].swizzle_z
= 7;
3693 output
[j
].swizzle_w
= 7;
3694 output
[j
].burst_count
= 1;
3695 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3696 output
[j
].array_base
= 0;
3697 output
[j
].op
= CF_OP_EXPORT
;
3699 shader
->nr_ps_color_exports
++;
3704 /* set export done on last export of each type */
3705 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
3706 if (!(output_done
& (1 << output
[i
].type
))) {
3707 output_done
|= (1 << output
[i
].type
);
3708 output
[i
].op
= CF_OP_EXPORT_DONE
;
3711 /* add output to bytecode */
3713 for (i
= 0; i
< noutput
; i
++) {
3714 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
3721 /* add program end */
3723 if (ctx
.bc
->chip_class
== CAYMAN
)
3724 cm_bytecode_add_cf_end(ctx
.bc
);
3726 const struct cf_op_info
*last
= NULL
;
3728 if (ctx
.bc
->cf_last
)
3729 last
= r600_isa_cf(ctx
.bc
->cf_last
->op
);
3731 /* alu clause instructions don't have EOP bit, so add NOP */
3732 if (!last
|| last
->flags
& CF_ALU
|| ctx
.bc
->cf_last
->op
== CF_OP_LOOP_END
|| ctx
.bc
->cf_last
->op
== CF_OP_CALL_FS
|| ctx
.bc
->cf_last
->op
== CF_OP_POP
|| ctx
.bc
->cf_last
->op
== CF_OP_GDS
)
3733 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
3735 ctx
.bc
->cf_last
->end_of_program
= 1;
3739 /* check GPR limit - we have 124 = 128 - 4
3740 * (4 are reserved as alu clause temporary registers) */
3741 if (ctx
.bc
->ngpr
> 124) {
3742 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx
.bc
->ngpr
);
3747 if (ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
3748 if ((r
= generate_gs_copy_shader(rctx
, pipeshader
, &so
)))
3753 tgsi_parse_free(&ctx
.parse
);
3757 tgsi_parse_free(&ctx
.parse
);
3761 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
3763 const unsigned tgsi_opcode
=
3764 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3765 R600_ERR("%s tgsi opcode unsupported\n",
3766 tgsi_get_opcode_name(tgsi_opcode
));
3770 static int tgsi_end(struct r600_shader_ctx
*ctx
)
3775 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
3776 const struct r600_shader_src
*shader_src
,
3779 bc_src
->sel
= shader_src
->sel
;
3780 bc_src
->chan
= shader_src
->swizzle
[chan
];
3781 bc_src
->neg
= shader_src
->neg
;
3782 bc_src
->abs
= shader_src
->abs
;
3783 bc_src
->rel
= shader_src
->rel
;
3784 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
3785 bc_src
->kc_bank
= shader_src
->kc_bank
;
3786 bc_src
->kc_rel
= shader_src
->kc_rel
;
3789 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
3795 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
3797 bc_src
->neg
= !bc_src
->neg
;
3800 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
3801 const struct tgsi_full_dst_register
*tgsi_dst
,
3803 struct r600_bytecode_alu_dst
*r600_dst
)
3805 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3807 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
3808 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
3809 r600_dst
->chan
= swizzle
;
3810 r600_dst
->write
= 1;
3811 if (inst
->Instruction
.Saturate
) {
3812 r600_dst
->clamp
= 1;
3814 if (ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
) {
3815 if (tgsi_dst
->Register
.File
== TGSI_FILE_OUTPUT
) {
3819 if (tgsi_dst
->Register
.Indirect
)
3820 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
3824 static int tgsi_op2_64_params(struct r600_shader_ctx
*ctx
, bool singledest
, bool swap
)
3826 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3827 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3828 struct r600_bytecode_alu alu
;
3829 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
3833 switch (write_mask
) {
3851 lasti
= tgsi_last_instruction(write_mask
);
3852 for (i
= 0; i
<= lasti
; i
++) {
3854 if (!(write_mask
& (1 << i
)))
3857 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3860 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3862 alu
.dst
.sel
= ctx
->temp_reg
;
3866 if (i
== 1 || i
== 3)
3869 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3871 alu
.op
= ctx
->inst_info
->op
;
3872 if (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DABS
) {
3873 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3875 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3876 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
3879 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], fp64_switch(i
));
3880 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], fp64_switch(i
));
3883 /* handle some special cases */
3884 if (i
== 1 || i
== 3) {
3885 switch (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
) {
3886 case TGSI_OPCODE_SUB
:
3887 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
3889 case TGSI_OPCODE_DABS
:
3890 r600_bytecode_src_set_abs(&alu
.src
[0]);
3899 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3905 write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3907 /* move result from temp to dst */
3908 for (i
= 0; i
<= lasti
; i
++) {
3909 if (!(write_mask
& (1 << i
)))
3912 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3913 alu
.op
= ALU_OP1_MOV
;
3914 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3915 alu
.src
[0].sel
= ctx
->temp_reg
;
3916 alu
.src
[0].chan
= use_tmp
- 1;
3917 alu
.last
= (i
== lasti
);
3919 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3927 static int tgsi_op2_64(struct r600_shader_ctx
*ctx
)
3929 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3930 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3931 /* confirm writemasking */
3932 if ((write_mask
& 0x3) != 0x3 &&
3933 (write_mask
& 0xc) != 0xc) {
3934 fprintf(stderr
, "illegal writemask for 64-bit: 0x%x\n", write_mask
);
3937 return tgsi_op2_64_params(ctx
, false, false);
3940 static int tgsi_op2_64_single_dest(struct r600_shader_ctx
*ctx
)
3942 return tgsi_op2_64_params(ctx
, true, false);
3945 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx
*ctx
)
3947 return tgsi_op2_64_params(ctx
, true, true);
3950 static int tgsi_op3_64(struct r600_shader_ctx
*ctx
)
3952 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3953 struct r600_bytecode_alu alu
;
3956 int tmp
= r600_get_temp(ctx
);
3958 for (i
= 0; i
< lasti
+ 1; i
++) {
3960 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3961 alu
.op
= ctx
->inst_info
->op
;
3962 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3963 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
== 3 ? 0 : 1);
3966 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
))
3967 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3976 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3983 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
3985 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3986 struct r600_bytecode_alu alu
;
3987 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3988 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
3989 /* use temp register if trans_only and more than one dst component */
3990 int use_tmp
= trans_only
&& (write_mask
^ (1 << lasti
));
3992 for (i
= 0; i
<= lasti
; i
++) {
3993 if (!(write_mask
& (1 << i
)))
3996 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3998 alu
.dst
.sel
= ctx
->temp_reg
;
4002 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4004 alu
.op
= ctx
->inst_info
->op
;
4006 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4007 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
4010 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
4011 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4013 /* handle some special cases */
4014 switch (inst
->Instruction
.Opcode
) {
4015 case TGSI_OPCODE_SUB
:
4016 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
4018 case TGSI_OPCODE_ABS
:
4019 r600_bytecode_src_set_abs(&alu
.src
[0]);
4024 if (i
== lasti
|| trans_only
) {
4027 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4033 /* move result from temp to dst */
4034 for (i
= 0; i
<= lasti
; i
++) {
4035 if (!(write_mask
& (1 << i
)))
4038 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4039 alu
.op
= ALU_OP1_MOV
;
4040 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4041 alu
.src
[0].sel
= ctx
->temp_reg
;
4042 alu
.src
[0].chan
= i
;
4043 alu
.last
= (i
== lasti
);
4045 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4053 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
4055 return tgsi_op2_s(ctx
, 0, 0);
4058 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
4060 return tgsi_op2_s(ctx
, 1, 0);
4063 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
4065 return tgsi_op2_s(ctx
, 0, 1);
4068 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
4070 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4071 struct r600_bytecode_alu alu
;
4073 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4075 for (i
= 0; i
< lasti
+ 1; i
++) {
4077 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4079 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4080 alu
.op
= ctx
->inst_info
->op
;
4082 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4084 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4086 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4091 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4099 static int tgsi_dneg(struct r600_shader_ctx
*ctx
)
4101 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4102 struct r600_bytecode_alu alu
;
4104 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4106 for (i
= 0; i
< lasti
+ 1; i
++) {
4108 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4110 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4111 alu
.op
= ALU_OP1_MOV
;
4113 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4115 if (i
== 1 || i
== 3)
4116 r600_bytecode_src_toggle_neg(&alu
.src
[0]);
4117 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4122 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4130 static int tgsi_dfracexp(struct r600_shader_ctx
*ctx
)
4132 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4133 struct r600_bytecode_alu alu
;
4134 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4136 int firsti
= write_mask
== 0xc ? 2 : 0;
4138 for (i
= 0; i
<= 3; i
++) {
4139 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4140 alu
.op
= ctx
->inst_info
->op
;
4142 alu
.dst
.sel
= ctx
->temp_reg
;
4145 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4146 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
4152 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4157 /* MOV first two channels to writemask dst0 */
4158 for (i
= 0; i
<= 1; i
++) {
4159 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4160 alu
.op
= ALU_OP1_MOV
;
4161 alu
.src
[0].chan
= i
+ 2;
4162 alu
.src
[0].sel
= ctx
->temp_reg
;
4164 tgsi_dst(ctx
, &inst
->Dst
[0], firsti
+ i
, &alu
.dst
);
4165 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> (firsti
+ i
)) & 1;
4167 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4172 for (i
= 0; i
<= 3; i
++) {
4173 if (inst
->Dst
[1].Register
.WriteMask
& (1 << i
)) {
4174 /* MOV third channels to writemask dst1 */
4175 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4176 alu
.op
= ALU_OP1_MOV
;
4177 alu
.src
[0].chan
= 1;
4178 alu
.src
[0].sel
= ctx
->temp_reg
;
4180 tgsi_dst(ctx
, &inst
->Dst
[1], i
, &alu
.dst
);
4182 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4192 static int egcm_int_to_double(struct r600_shader_ctx
*ctx
)
4194 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4195 struct r600_bytecode_alu alu
;
4197 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4199 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_I2D
||
4200 inst
->Instruction
.Opcode
== TGSI_OPCODE_U2D
);
4202 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4203 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4204 alu
.op
= ctx
->inst_info
->op
;
4206 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4207 alu
.dst
.sel
= ctx
->temp_reg
;
4212 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4217 for (i
= 0; i
<= lasti
; i
++) {
4218 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4219 alu
.op
= ALU_OP1_FLT32_TO_FLT64
;
4221 alu
.src
[0].chan
= i
/2;
4223 alu
.src
[0].sel
= ctx
->temp_reg
;
4225 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
4226 alu
.src
[0].value
= 0x0;
4228 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4229 alu
.last
= i
== lasti
;
4231 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4239 static int egcm_double_to_int(struct r600_shader_ctx
*ctx
)
4241 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4242 struct r600_bytecode_alu alu
;
4244 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4246 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_D2I
||
4247 inst
->Instruction
.Opcode
== TGSI_OPCODE_D2U
);
4249 for (i
= 0; i
<= lasti
; i
++) {
4250 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4251 alu
.op
= ALU_OP1_FLT64_TO_FLT32
;
4253 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], fp64_switch(i
));
4255 alu
.dst
.sel
= ctx
->temp_reg
;
4256 alu
.dst
.write
= i
%2 == 0;
4257 alu
.last
= i
== lasti
;
4259 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4264 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4265 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4266 alu
.op
= ctx
->inst_info
->op
;
4268 alu
.src
[0].chan
= i
*2;
4269 alu
.src
[0].sel
= ctx
->temp_reg
;
4270 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4273 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4281 static int cayman_emit_double_instr(struct r600_shader_ctx
*ctx
)
4283 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4285 struct r600_bytecode_alu alu
;
4287 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4288 int t1
= ctx
->temp_reg
;
4290 /* these have to write the result to X/Y by the looks of it */
4291 for (i
= 0 ; i
< last_slot
; i
++) {
4292 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4293 alu
.op
= ctx
->inst_info
->op
;
4295 /* should only be one src regs */
4296 assert (inst
->Instruction
.NumSrcRegs
== 1);
4298 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
4299 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 0);
4301 /* RSQ should take the absolute value of src */
4302 if (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DRSQ
||
4303 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DSQRT
) {
4304 r600_bytecode_src_set_abs(&alu
.src
[1]);
4308 alu
.dst
.write
= (i
== 0 || i
== 1);
4310 if (ctx
->bc
->chip_class
!= CAYMAN
|| i
== last_slot
- 1)
4312 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4317 for (i
= 0 ; i
<= lasti
; i
++) {
4318 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4320 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4321 alu
.op
= ALU_OP1_MOV
;
4322 alu
.src
[0].sel
= t1
;
4323 alu
.src
[0].chan
= (i
== 0 || i
== 2) ? 0 : 1;
4324 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4328 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4335 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
4337 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4339 struct r600_bytecode_alu alu
;
4340 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4342 for (i
= 0 ; i
< last_slot
; i
++) {
4343 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4344 alu
.op
= ctx
->inst_info
->op
;
4345 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4346 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
4348 /* RSQ should take the absolute value of src */
4349 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_RSQ
) {
4350 r600_bytecode_src_set_abs(&alu
.src
[j
]);
4353 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4354 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4356 if (i
== last_slot
- 1)
4358 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4365 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
4367 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4369 struct r600_bytecode_alu alu
;
4370 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4371 int t1
= ctx
->temp_reg
;
4373 for (k
= 0; k
<= lasti
; k
++) {
4374 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
4377 for (i
= 0 ; i
< 4; i
++) {
4378 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4379 alu
.op
= ctx
->inst_info
->op
;
4380 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4381 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
4385 alu
.dst
.write
= (i
== k
);
4388 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4394 for (i
= 0 ; i
<= lasti
; i
++) {
4395 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4397 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4398 alu
.op
= ALU_OP1_MOV
;
4399 alu
.src
[0].sel
= t1
;
4400 alu
.src
[0].chan
= i
;
4401 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4405 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4414 static int cayman_mul_double_instr(struct r600_shader_ctx
*ctx
)
4416 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4418 struct r600_bytecode_alu alu
;
4419 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4420 int t1
= ctx
->temp_reg
;
4422 for (k
= 0; k
< 2; k
++) {
4423 if (!(inst
->Dst
[0].Register
.WriteMask
& (0x3 << (k
* 2))))
4426 for (i
= 0; i
< 4; i
++) {
4427 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4428 alu
.op
= ctx
->inst_info
->op
;
4429 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4430 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
* 2 + ((i
== 3) ? 0 : 1));;
4437 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4443 for (i
= 0; i
<= lasti
; i
++) {
4444 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4446 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4447 alu
.op
= ALU_OP1_MOV
;
4448 alu
.src
[0].sel
= t1
;
4449 alu
.src
[0].chan
= i
;
4450 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4454 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4463 * r600 - trunc to -PI..PI range
4464 * r700 - normalize by dividing by 2PI
4467 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
4469 static float half_inv_pi
= 1.0 /(3.1415926535 * 2);
4470 static float double_pi
= 3.1415926535 * 2;
4471 static float neg_pi
= -3.1415926535;
4474 struct r600_bytecode_alu alu
;
4476 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4477 alu
.op
= ALU_OP3_MULADD
;
4481 alu
.dst
.sel
= ctx
->temp_reg
;
4484 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4486 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4487 alu
.src
[1].chan
= 0;
4488 alu
.src
[1].value
= *(uint32_t *)&half_inv_pi
;
4489 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4490 alu
.src
[2].chan
= 0;
4492 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4496 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4497 alu
.op
= ALU_OP1_FRACT
;
4500 alu
.dst
.sel
= ctx
->temp_reg
;
4503 alu
.src
[0].sel
= ctx
->temp_reg
;
4504 alu
.src
[0].chan
= 0;
4506 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4510 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4511 alu
.op
= ALU_OP3_MULADD
;
4515 alu
.dst
.sel
= ctx
->temp_reg
;
4518 alu
.src
[0].sel
= ctx
->temp_reg
;
4519 alu
.src
[0].chan
= 0;
4521 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4522 alu
.src
[1].chan
= 0;
4523 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
4524 alu
.src
[2].chan
= 0;
4526 if (ctx
->bc
->chip_class
== R600
) {
4527 alu
.src
[1].value
= *(uint32_t *)&double_pi
;
4528 alu
.src
[2].value
= *(uint32_t *)&neg_pi
;
4530 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4531 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4536 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4542 static int cayman_trig(struct r600_shader_ctx
*ctx
)
4544 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4545 struct r600_bytecode_alu alu
;
4546 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4549 r
= tgsi_setup_trig(ctx
);
4554 for (i
= 0; i
< last_slot
; i
++) {
4555 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4556 alu
.op
= ctx
->inst_info
->op
;
4559 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4560 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4562 alu
.src
[0].sel
= ctx
->temp_reg
;
4563 alu
.src
[0].chan
= 0;
4564 if (i
== last_slot
- 1)
4566 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4573 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
4575 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4576 struct r600_bytecode_alu alu
;
4578 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4580 r
= tgsi_setup_trig(ctx
);
4584 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4585 alu
.op
= ctx
->inst_info
->op
;
4587 alu
.dst
.sel
= ctx
->temp_reg
;
4590 alu
.src
[0].sel
= ctx
->temp_reg
;
4591 alu
.src
[0].chan
= 0;
4593 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4597 /* replicate result */
4598 for (i
= 0; i
< lasti
+ 1; i
++) {
4599 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4602 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4603 alu
.op
= ALU_OP1_MOV
;
4605 alu
.src
[0].sel
= ctx
->temp_reg
;
4606 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4609 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4616 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
4618 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4619 struct r600_bytecode_alu alu
;
4622 /* We'll only need the trig stuff if we are going to write to the
4623 * X or Y components of the destination vector.
4625 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
4626 r
= tgsi_setup_trig(ctx
);
4632 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
4633 if (ctx
->bc
->chip_class
== CAYMAN
) {
4634 for (i
= 0 ; i
< 3; i
++) {
4635 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4636 alu
.op
= ALU_OP1_COS
;
4637 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4643 alu
.src
[0].sel
= ctx
->temp_reg
;
4644 alu
.src
[0].chan
= 0;
4647 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4652 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4653 alu
.op
= ALU_OP1_COS
;
4654 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4656 alu
.src
[0].sel
= ctx
->temp_reg
;
4657 alu
.src
[0].chan
= 0;
4659 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4666 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
4667 if (ctx
->bc
->chip_class
== CAYMAN
) {
4668 for (i
= 0 ; i
< 3; i
++) {
4669 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4670 alu
.op
= ALU_OP1_SIN
;
4671 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4676 alu
.src
[0].sel
= ctx
->temp_reg
;
4677 alu
.src
[0].chan
= 0;
4680 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4685 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4686 alu
.op
= ALU_OP1_SIN
;
4687 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
4689 alu
.src
[0].sel
= ctx
->temp_reg
;
4690 alu
.src
[0].chan
= 0;
4692 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4699 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
4700 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4702 alu
.op
= ALU_OP1_MOV
;
4704 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
4706 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4707 alu
.src
[0].chan
= 0;
4711 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4717 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
4718 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4720 alu
.op
= ALU_OP1_MOV
;
4722 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
4724 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4725 alu
.src
[0].chan
= 0;
4729 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4737 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
4739 const struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4740 struct r600_bytecode_alu alu
;
4743 for (i
= 0; i
< 4; i
++) {
4744 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4745 alu
.op
= ctx
->inst_info
->op
;
4749 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4751 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_KILL
) {
4752 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4755 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4760 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4765 /* kill must be last in ALU */
4766 ctx
->bc
->force_add_cf
= 1;
4767 ctx
->shader
->uses_kill
= TRUE
;
4771 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
4773 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4774 struct r600_bytecode_alu alu
;
4777 /* tmp.x = max(src.y, 0.0) */
4778 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4779 alu
.op
= ALU_OP2_MAX
;
4780 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
4781 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4782 alu
.src
[1].chan
= 1;
4784 alu
.dst
.sel
= ctx
->temp_reg
;
4789 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4793 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
4799 if (ctx
->bc
->chip_class
== CAYMAN
) {
4800 for (i
= 0; i
< 3; i
++) {
4801 /* tmp.z = log(tmp.x) */
4802 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4803 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4804 alu
.src
[0].sel
= ctx
->temp_reg
;
4805 alu
.src
[0].chan
= 0;
4806 alu
.dst
.sel
= ctx
->temp_reg
;
4814 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4819 /* tmp.z = log(tmp.x) */
4820 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4821 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4822 alu
.src
[0].sel
= ctx
->temp_reg
;
4823 alu
.src
[0].chan
= 0;
4824 alu
.dst
.sel
= ctx
->temp_reg
;
4828 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4833 chan
= alu
.dst
.chan
;
4836 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4837 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4838 alu
.op
= ALU_OP3_MUL_LIT
;
4839 alu
.src
[0].sel
= sel
;
4840 alu
.src
[0].chan
= chan
;
4841 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
4842 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
4843 alu
.dst
.sel
= ctx
->temp_reg
;
4848 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4852 if (ctx
->bc
->chip_class
== CAYMAN
) {
4853 for (i
= 0; i
< 3; i
++) {
4854 /* dst.z = exp(tmp.x) */
4855 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4856 alu
.op
= ALU_OP1_EXP_IEEE
;
4857 alu
.src
[0].sel
= ctx
->temp_reg
;
4858 alu
.src
[0].chan
= 0;
4859 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4865 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4870 /* dst.z = exp(tmp.x) */
4871 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4872 alu
.op
= ALU_OP1_EXP_IEEE
;
4873 alu
.src
[0].sel
= ctx
->temp_reg
;
4874 alu
.src
[0].chan
= 0;
4875 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
4877 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4884 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4885 alu
.op
= ALU_OP1_MOV
;
4886 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
4887 alu
.src
[0].chan
= 0;
4888 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4889 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
4890 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4894 /* dst.y = max(src.x, 0.0) */
4895 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4896 alu
.op
= ALU_OP2_MAX
;
4897 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4898 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4899 alu
.src
[1].chan
= 0;
4900 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
4901 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
4902 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4907 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4908 alu
.op
= ALU_OP1_MOV
;
4909 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4910 alu
.src
[0].chan
= 0;
4911 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
4912 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
4914 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4921 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
4923 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4924 struct r600_bytecode_alu alu
;
4927 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4930 * For state trackers other than OpenGL, we'll want to use
4931 * _RECIPSQRT_IEEE instead.
4933 alu
.op
= ALU_OP1_RECIPSQRT_CLAMPED
;
4935 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
4936 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
4937 r600_bytecode_src_set_abs(&alu
.src
[i
]);
4939 alu
.dst
.sel
= ctx
->temp_reg
;
4942 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4945 /* replicate result */
4946 return tgsi_helper_tempx_replicate(ctx
);
4949 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
4951 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4952 struct r600_bytecode_alu alu
;
4955 for (i
= 0; i
< 4; i
++) {
4956 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4957 alu
.src
[0].sel
= ctx
->temp_reg
;
4958 alu
.op
= ALU_OP1_MOV
;
4960 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4961 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4964 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4971 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
4973 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4974 struct r600_bytecode_alu alu
;
4977 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4978 alu
.op
= ctx
->inst_info
->op
;
4979 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
4980 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
4982 alu
.dst
.sel
= ctx
->temp_reg
;
4985 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4988 /* replicate result */
4989 return tgsi_helper_tempx_replicate(ctx
);
4992 static int cayman_pow(struct r600_shader_ctx
*ctx
)
4994 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4996 struct r600_bytecode_alu alu
;
4997 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4999 for (i
= 0; i
< 3; i
++) {
5000 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5001 alu
.op
= ALU_OP1_LOG_IEEE
;
5002 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5003 alu
.dst
.sel
= ctx
->temp_reg
;
5008 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5014 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5015 alu
.op
= ALU_OP2_MUL
;
5016 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5017 alu
.src
[1].sel
= ctx
->temp_reg
;
5018 alu
.dst
.sel
= ctx
->temp_reg
;
5021 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5025 for (i
= 0; i
< last_slot
; i
++) {
5026 /* POW(a,b) = EXP2(b * LOG2(a))*/
5027 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5028 alu
.op
= ALU_OP1_EXP_IEEE
;
5029 alu
.src
[0].sel
= ctx
->temp_reg
;
5031 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5032 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
5033 if (i
== last_slot
- 1)
5035 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5042 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
5044 struct r600_bytecode_alu alu
;
5048 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5049 alu
.op
= ALU_OP1_LOG_IEEE
;
5050 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5051 alu
.dst
.sel
= ctx
->temp_reg
;
5054 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5058 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5059 alu
.op
= ALU_OP2_MUL
;
5060 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5061 alu
.src
[1].sel
= ctx
->temp_reg
;
5062 alu
.dst
.sel
= ctx
->temp_reg
;
5065 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5068 /* POW(a,b) = EXP2(b * LOG2(a))*/
5069 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5070 alu
.op
= ALU_OP1_EXP_IEEE
;
5071 alu
.src
[0].sel
= ctx
->temp_reg
;
5072 alu
.dst
.sel
= ctx
->temp_reg
;
5075 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5078 return tgsi_helper_tempx_replicate(ctx
);
5081 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
5083 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5084 struct r600_bytecode_alu alu
;
5086 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5087 int tmp0
= ctx
->temp_reg
;
5088 int tmp1
= r600_get_temp(ctx
);
5089 int tmp2
= r600_get_temp(ctx
);
5090 int tmp3
= r600_get_temp(ctx
);
5093 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5095 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5096 * 2. tmp0.z = lo (tmp0.x * src2)
5097 * 3. tmp0.w = -tmp0.z
5098 * 4. tmp0.y = hi (tmp0.x * src2)
5099 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5100 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5101 * 7. tmp1.x = tmp0.x - tmp0.w
5102 * 8. tmp1.y = tmp0.x + tmp0.w
5103 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5104 * 10. tmp0.z = hi(tmp0.x * src1) = q
5105 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5107 * 12. tmp0.w = src1 - tmp0.y = r
5108 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5109 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5113 * 15. tmp1.z = tmp0.z + 1 = q + 1
5114 * 16. tmp1.w = tmp0.z - 1 = q - 1
5118 * 15. tmp1.z = tmp0.w - src2 = r - src2
5119 * 16. tmp1.w = tmp0.w + src2 = r + src2
5123 * 17. tmp1.x = tmp1.x & tmp1.y
5125 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5126 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5128 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5129 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5133 * Same as unsigned, using abs values of the operands,
5134 * and fixing the sign of the result in the end.
5137 for (i
= 0; i
< 4; i
++) {
5138 if (!(write_mask
& (1<<i
)))
5143 /* tmp2.x = -src0 */
5144 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5145 alu
.op
= ALU_OP2_SUB_INT
;
5151 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5153 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5156 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5159 /* tmp2.y = -src1 */
5160 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5161 alu
.op
= ALU_OP2_SUB_INT
;
5167 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5169 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5172 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5175 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5176 /* it will be a sign of the quotient */
5179 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5180 alu
.op
= ALU_OP2_XOR_INT
;
5186 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5187 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5190 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5194 /* tmp2.x = |src0| */
5195 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5196 alu
.op
= ALU_OP3_CNDGE_INT
;
5203 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5204 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5205 alu
.src
[2].sel
= tmp2
;
5206 alu
.src
[2].chan
= 0;
5209 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5212 /* tmp2.y = |src1| */
5213 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5214 alu
.op
= ALU_OP3_CNDGE_INT
;
5221 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5222 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5223 alu
.src
[2].sel
= tmp2
;
5224 alu
.src
[2].chan
= 1;
5227 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5232 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5233 if (ctx
->bc
->chip_class
== CAYMAN
) {
5234 /* tmp3.x = u2f(src2) */
5235 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5236 alu
.op
= ALU_OP1_UINT_TO_FLT
;
5243 alu
.src
[0].sel
= tmp2
;
5244 alu
.src
[0].chan
= 1;
5246 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5250 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5253 /* tmp0.x = recip(tmp3.x) */
5254 for (j
= 0 ; j
< 3; j
++) {
5255 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5256 alu
.op
= ALU_OP1_RECIP_IEEE
;
5260 alu
.dst
.write
= (j
== 0);
5262 alu
.src
[0].sel
= tmp3
;
5263 alu
.src
[0].chan
= 0;
5267 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5271 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5272 alu
.op
= ALU_OP2_MUL
;
5274 alu
.src
[0].sel
= tmp0
;
5275 alu
.src
[0].chan
= 0;
5277 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5278 alu
.src
[1].value
= 0x4f800000;
5283 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5287 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5288 alu
.op
= ALU_OP1_FLT_TO_UINT
;
5294 alu
.src
[0].sel
= tmp3
;
5295 alu
.src
[0].chan
= 0;
5298 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5302 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5303 alu
.op
= ALU_OP1_RECIP_UINT
;
5310 alu
.src
[0].sel
= tmp2
;
5311 alu
.src
[0].chan
= 1;
5313 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5317 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5321 /* 2. tmp0.z = lo (tmp0.x * src2) */
5322 if (ctx
->bc
->chip_class
== CAYMAN
) {
5323 for (j
= 0 ; j
< 4; j
++) {
5324 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5325 alu
.op
= ALU_OP2_MULLO_UINT
;
5329 alu
.dst
.write
= (j
== 2);
5331 alu
.src
[0].sel
= tmp0
;
5332 alu
.src
[0].chan
= 0;
5334 alu
.src
[1].sel
= tmp2
;
5335 alu
.src
[1].chan
= 1;
5337 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5340 alu
.last
= (j
== 3);
5341 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5345 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5346 alu
.op
= ALU_OP2_MULLO_UINT
;
5352 alu
.src
[0].sel
= tmp0
;
5353 alu
.src
[0].chan
= 0;
5355 alu
.src
[1].sel
= tmp2
;
5356 alu
.src
[1].chan
= 1;
5358 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5362 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5366 /* 3. tmp0.w = -tmp0.z */
5367 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5368 alu
.op
= ALU_OP2_SUB_INT
;
5374 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5375 alu
.src
[1].sel
= tmp0
;
5376 alu
.src
[1].chan
= 2;
5379 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5382 /* 4. tmp0.y = hi (tmp0.x * src2) */
5383 if (ctx
->bc
->chip_class
== CAYMAN
) {
5384 for (j
= 0 ; j
< 4; j
++) {
5385 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5386 alu
.op
= ALU_OP2_MULHI_UINT
;
5390 alu
.dst
.write
= (j
== 1);
5392 alu
.src
[0].sel
= tmp0
;
5393 alu
.src
[0].chan
= 0;
5396 alu
.src
[1].sel
= tmp2
;
5397 alu
.src
[1].chan
= 1;
5399 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5401 alu
.last
= (j
== 3);
5402 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5406 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5407 alu
.op
= ALU_OP2_MULHI_UINT
;
5413 alu
.src
[0].sel
= tmp0
;
5414 alu
.src
[0].chan
= 0;
5417 alu
.src
[1].sel
= tmp2
;
5418 alu
.src
[1].chan
= 1;
5420 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5424 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5428 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5429 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5430 alu
.op
= ALU_OP3_CNDE_INT
;
5437 alu
.src
[0].sel
= tmp0
;
5438 alu
.src
[0].chan
= 1;
5439 alu
.src
[1].sel
= tmp0
;
5440 alu
.src
[1].chan
= 3;
5441 alu
.src
[2].sel
= tmp0
;
5442 alu
.src
[2].chan
= 2;
5445 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5448 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5449 if (ctx
->bc
->chip_class
== CAYMAN
) {
5450 for (j
= 0 ; j
< 4; j
++) {
5451 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5452 alu
.op
= ALU_OP2_MULHI_UINT
;
5456 alu
.dst
.write
= (j
== 3);
5458 alu
.src
[0].sel
= tmp0
;
5459 alu
.src
[0].chan
= 2;
5461 alu
.src
[1].sel
= tmp0
;
5462 alu
.src
[1].chan
= 0;
5464 alu
.last
= (j
== 3);
5465 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5469 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5470 alu
.op
= ALU_OP2_MULHI_UINT
;
5476 alu
.src
[0].sel
= tmp0
;
5477 alu
.src
[0].chan
= 2;
5479 alu
.src
[1].sel
= tmp0
;
5480 alu
.src
[1].chan
= 0;
5483 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5487 /* 7. tmp1.x = tmp0.x - tmp0.w */
5488 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5489 alu
.op
= ALU_OP2_SUB_INT
;
5495 alu
.src
[0].sel
= tmp0
;
5496 alu
.src
[0].chan
= 0;
5497 alu
.src
[1].sel
= tmp0
;
5498 alu
.src
[1].chan
= 3;
5501 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5504 /* 8. tmp1.y = tmp0.x + tmp0.w */
5505 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5506 alu
.op
= ALU_OP2_ADD_INT
;
5512 alu
.src
[0].sel
= tmp0
;
5513 alu
.src
[0].chan
= 0;
5514 alu
.src
[1].sel
= tmp0
;
5515 alu
.src
[1].chan
= 3;
5518 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5521 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5522 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5523 alu
.op
= ALU_OP3_CNDE_INT
;
5530 alu
.src
[0].sel
= tmp0
;
5531 alu
.src
[0].chan
= 1;
5532 alu
.src
[1].sel
= tmp1
;
5533 alu
.src
[1].chan
= 1;
5534 alu
.src
[2].sel
= tmp1
;
5535 alu
.src
[2].chan
= 0;
5538 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5541 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5542 if (ctx
->bc
->chip_class
== CAYMAN
) {
5543 for (j
= 0 ; j
< 4; j
++) {
5544 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5545 alu
.op
= ALU_OP2_MULHI_UINT
;
5549 alu
.dst
.write
= (j
== 2);
5551 alu
.src
[0].sel
= tmp0
;
5552 alu
.src
[0].chan
= 0;
5555 alu
.src
[1].sel
= tmp2
;
5556 alu
.src
[1].chan
= 0;
5558 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5561 alu
.last
= (j
== 3);
5562 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5566 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5567 alu
.op
= ALU_OP2_MULHI_UINT
;
5573 alu
.src
[0].sel
= tmp0
;
5574 alu
.src
[0].chan
= 0;
5577 alu
.src
[1].sel
= tmp2
;
5578 alu
.src
[1].chan
= 0;
5580 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5584 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5588 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5589 if (ctx
->bc
->chip_class
== CAYMAN
) {
5590 for (j
= 0 ; j
< 4; j
++) {
5591 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5592 alu
.op
= ALU_OP2_MULLO_UINT
;
5596 alu
.dst
.write
= (j
== 1);
5599 alu
.src
[0].sel
= tmp2
;
5600 alu
.src
[0].chan
= 1;
5602 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5605 alu
.src
[1].sel
= tmp0
;
5606 alu
.src
[1].chan
= 2;
5608 alu
.last
= (j
== 3);
5609 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5613 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5614 alu
.op
= ALU_OP2_MULLO_UINT
;
5621 alu
.src
[0].sel
= tmp2
;
5622 alu
.src
[0].chan
= 1;
5624 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5627 alu
.src
[1].sel
= tmp0
;
5628 alu
.src
[1].chan
= 2;
5631 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5635 /* 12. tmp0.w = src1 - tmp0.y = r */
5636 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5637 alu
.op
= ALU_OP2_SUB_INT
;
5644 alu
.src
[0].sel
= tmp2
;
5645 alu
.src
[0].chan
= 0;
5647 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5650 alu
.src
[1].sel
= tmp0
;
5651 alu
.src
[1].chan
= 1;
5654 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5657 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5658 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5659 alu
.op
= ALU_OP2_SETGE_UINT
;
5665 alu
.src
[0].sel
= tmp0
;
5666 alu
.src
[0].chan
= 3;
5668 alu
.src
[1].sel
= tmp2
;
5669 alu
.src
[1].chan
= 1;
5671 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5675 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5678 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5679 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5680 alu
.op
= ALU_OP2_SETGE_UINT
;
5687 alu
.src
[0].sel
= tmp2
;
5688 alu
.src
[0].chan
= 0;
5690 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5693 alu
.src
[1].sel
= tmp0
;
5694 alu
.src
[1].chan
= 1;
5697 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5700 if (mod
) { /* UMOD */
5702 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5703 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5704 alu
.op
= ALU_OP2_SUB_INT
;
5710 alu
.src
[0].sel
= tmp0
;
5711 alu
.src
[0].chan
= 3;
5714 alu
.src
[1].sel
= tmp2
;
5715 alu
.src
[1].chan
= 1;
5717 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5721 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5724 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5725 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5726 alu
.op
= ALU_OP2_ADD_INT
;
5732 alu
.src
[0].sel
= tmp0
;
5733 alu
.src
[0].chan
= 3;
5735 alu
.src
[1].sel
= tmp2
;
5736 alu
.src
[1].chan
= 1;
5738 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5742 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5747 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5748 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5749 alu
.op
= ALU_OP2_ADD_INT
;
5755 alu
.src
[0].sel
= tmp0
;
5756 alu
.src
[0].chan
= 2;
5757 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
5760 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5763 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5764 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5765 alu
.op
= ALU_OP2_ADD_INT
;
5771 alu
.src
[0].sel
= tmp0
;
5772 alu
.src
[0].chan
= 2;
5773 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
5776 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5781 /* 17. tmp1.x = tmp1.x & tmp1.y */
5782 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5783 alu
.op
= ALU_OP2_AND_INT
;
5789 alu
.src
[0].sel
= tmp1
;
5790 alu
.src
[0].chan
= 0;
5791 alu
.src
[1].sel
= tmp1
;
5792 alu
.src
[1].chan
= 1;
5795 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5798 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5799 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5800 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5801 alu
.op
= ALU_OP3_CNDE_INT
;
5808 alu
.src
[0].sel
= tmp1
;
5809 alu
.src
[0].chan
= 0;
5810 alu
.src
[1].sel
= tmp0
;
5811 alu
.src
[1].chan
= mod
? 3 : 2;
5812 alu
.src
[2].sel
= tmp1
;
5813 alu
.src
[2].chan
= 2;
5816 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5819 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5820 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5821 alu
.op
= ALU_OP3_CNDE_INT
;
5829 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5832 alu
.src
[0].sel
= tmp1
;
5833 alu
.src
[0].chan
= 1;
5834 alu
.src
[1].sel
= tmp1
;
5835 alu
.src
[1].chan
= 3;
5836 alu
.src
[2].sel
= tmp0
;
5837 alu
.src
[2].chan
= 2;
5840 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5845 /* fix the sign of the result */
5849 /* tmp0.x = -tmp0.z */
5850 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5851 alu
.op
= ALU_OP2_SUB_INT
;
5857 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5858 alu
.src
[1].sel
= tmp0
;
5859 alu
.src
[1].chan
= 2;
5862 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5865 /* sign of the remainder is the same as the sign of src0 */
5866 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5867 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5868 alu
.op
= ALU_OP3_CNDGE_INT
;
5871 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5873 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5874 alu
.src
[1].sel
= tmp0
;
5875 alu
.src
[1].chan
= 2;
5876 alu
.src
[2].sel
= tmp0
;
5877 alu
.src
[2].chan
= 0;
5880 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5885 /* tmp0.x = -tmp0.z */
5886 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5887 alu
.op
= ALU_OP2_SUB_INT
;
5893 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5894 alu
.src
[1].sel
= tmp0
;
5895 alu
.src
[1].chan
= 2;
5898 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5901 /* fix the quotient sign (same as the sign of src0*src1) */
5902 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5903 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5904 alu
.op
= ALU_OP3_CNDGE_INT
;
5907 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5909 alu
.src
[0].sel
= tmp2
;
5910 alu
.src
[0].chan
= 2;
5911 alu
.src
[1].sel
= tmp0
;
5912 alu
.src
[1].chan
= 2;
5913 alu
.src
[2].sel
= tmp0
;
5914 alu
.src
[2].chan
= 0;
5917 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5925 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
5927 return tgsi_divmod(ctx
, 0, 0);
5930 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
5932 return tgsi_divmod(ctx
, 1, 0);
5935 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
5937 return tgsi_divmod(ctx
, 0, 1);
5940 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
5942 return tgsi_divmod(ctx
, 1, 1);
5946 static int tgsi_f2i(struct r600_shader_ctx
*ctx
)
5948 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5949 struct r600_bytecode_alu alu
;
5951 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5952 int last_inst
= tgsi_last_instruction(write_mask
);
5954 for (i
= 0; i
< 4; i
++) {
5955 if (!(write_mask
& (1<<i
)))
5958 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5959 alu
.op
= ALU_OP1_TRUNC
;
5961 alu
.dst
.sel
= ctx
->temp_reg
;
5965 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5968 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5973 for (i
= 0; i
< 4; i
++) {
5974 if (!(write_mask
& (1<<i
)))
5977 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5978 alu
.op
= ctx
->inst_info
->op
;
5980 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5982 alu
.src
[0].sel
= ctx
->temp_reg
;
5983 alu
.src
[0].chan
= i
;
5985 if (i
== last_inst
|| alu
.op
== ALU_OP1_FLT_TO_UINT
)
5987 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5995 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
5997 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5998 struct r600_bytecode_alu alu
;
6000 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6001 int last_inst
= tgsi_last_instruction(write_mask
);
6004 for (i
= 0; i
< 4; i
++) {
6005 if (!(write_mask
& (1<<i
)))
6008 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6009 alu
.op
= ALU_OP2_SUB_INT
;
6011 alu
.dst
.sel
= ctx
->temp_reg
;
6015 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6016 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
6020 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6025 /* dst = (src >= 0 ? src : tmp) */
6026 for (i
= 0; i
< 4; i
++) {
6027 if (!(write_mask
& (1<<i
)))
6030 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6031 alu
.op
= ALU_OP3_CNDGE_INT
;
6035 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6037 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6038 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6039 alu
.src
[2].sel
= ctx
->temp_reg
;
6040 alu
.src
[2].chan
= i
;
6044 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6051 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
6053 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6054 struct r600_bytecode_alu alu
;
6056 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6057 int last_inst
= tgsi_last_instruction(write_mask
);
6059 /* tmp = (src >= 0 ? src : -1) */
6060 for (i
= 0; i
< 4; i
++) {
6061 if (!(write_mask
& (1<<i
)))
6064 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6065 alu
.op
= ALU_OP3_CNDGE_INT
;
6068 alu
.dst
.sel
= ctx
->temp_reg
;
6072 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6073 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6074 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
6078 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6083 /* dst = (tmp > 0 ? 1 : tmp) */
6084 for (i
= 0; i
< 4; i
++) {
6085 if (!(write_mask
& (1<<i
)))
6088 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6089 alu
.op
= ALU_OP3_CNDGT_INT
;
6093 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6095 alu
.src
[0].sel
= ctx
->temp_reg
;
6096 alu
.src
[0].chan
= i
;
6098 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
6100 alu
.src
[2].sel
= ctx
->temp_reg
;
6101 alu
.src
[2].chan
= i
;
6105 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6114 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
6116 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6117 struct r600_bytecode_alu alu
;
6120 /* tmp = (src > 0 ? 1 : src) */
6121 for (i
= 0; i
< 4; i
++) {
6122 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6123 alu
.op
= ALU_OP3_CNDGT
;
6126 alu
.dst
.sel
= ctx
->temp_reg
;
6129 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6130 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6131 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6135 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6140 /* dst = (-tmp > 0 ? -1 : tmp) */
6141 for (i
= 0; i
< 4; i
++) {
6142 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6143 alu
.op
= ALU_OP3_CNDGT
;
6145 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6147 alu
.src
[0].sel
= ctx
->temp_reg
;
6148 alu
.src
[0].chan
= i
;
6151 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6154 alu
.src
[2].sel
= ctx
->temp_reg
;
6155 alu
.src
[2].chan
= i
;
6159 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6166 static int tgsi_bfi(struct r600_shader_ctx
*ctx
)
6168 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6169 struct r600_bytecode_alu alu
;
6172 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6173 int last_inst
= tgsi_last_instruction(write_mask
);
6177 for (i
= 0; i
< 4; i
++) {
6178 if (!(write_mask
& (1<<i
)))
6181 /* create mask tmp */
6182 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6183 alu
.op
= ALU_OP2_BFM_INT
;
6187 alu
.last
= i
== last_inst
;
6189 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6190 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6192 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6197 t2
= r600_get_temp(ctx
);
6199 for (i
= 0; i
< 4; i
++) {
6200 if (!(write_mask
& (1<<i
)))
6203 /* shift insert left */
6204 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6205 alu
.op
= ALU_OP2_LSHL_INT
;
6209 alu
.last
= i
== last_inst
;
6211 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
6212 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6214 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6219 for (i
= 0; i
< 4; i
++) {
6220 if (!(write_mask
& (1<<i
)))
6223 /* actual bitfield insert */
6224 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6225 alu
.op
= ALU_OP3_BFI_INT
;
6227 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6230 alu
.last
= i
== last_inst
;
6232 alu
.src
[0].sel
= t1
;
6233 alu
.src
[0].chan
= i
;
6234 alu
.src
[1].sel
= t2
;
6235 alu
.src
[1].chan
= i
;
6236 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6238 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6246 static int tgsi_msb(struct r600_shader_ctx
*ctx
)
6248 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6249 struct r600_bytecode_alu alu
;
6252 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6253 int last_inst
= tgsi_last_instruction(write_mask
);
6255 assert(ctx
->inst_info
->op
== ALU_OP1_FFBH_INT
||
6256 ctx
->inst_info
->op
== ALU_OP1_FFBH_UINT
);
6260 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6261 for (i
= 0; i
< 4; i
++) {
6262 if (!(write_mask
& (1<<i
)))
6265 /* t1 = FFBH_INT / FFBH_UINT */
6266 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6267 alu
.op
= ctx
->inst_info
->op
;
6271 alu
.last
= i
== last_inst
;
6273 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6275 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6280 t2
= r600_get_temp(ctx
);
6282 for (i
= 0; i
< 4; i
++) {
6283 if (!(write_mask
& (1<<i
)))
6287 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6288 alu
.op
= ALU_OP2_SUB_INT
;
6292 alu
.last
= i
== last_inst
;
6294 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
6295 alu
.src
[0].value
= 31;
6296 alu
.src
[1].sel
= t1
;
6297 alu
.src
[1].chan
= i
;
6299 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6304 for (i
= 0; i
< 4; i
++) {
6305 if (!(write_mask
& (1<<i
)))
6308 /* result = t1 >= 0 ? t2 : t1 */
6309 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6310 alu
.op
= ALU_OP3_CNDGE_INT
;
6312 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6315 alu
.last
= i
== last_inst
;
6317 alu
.src
[0].sel
= t1
;
6318 alu
.src
[0].chan
= i
;
6319 alu
.src
[1].sel
= t2
;
6320 alu
.src
[1].chan
= i
;
6321 alu
.src
[2].sel
= t1
;
6322 alu
.src
[2].chan
= i
;
6324 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6332 static int tgsi_interp_egcm(struct r600_shader_ctx
*ctx
)
6334 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6335 struct r600_bytecode_alu alu
;
6336 int r
, i
= 0, k
, interp_gpr
, interp_base_chan
, tmp
, lasti
;
6340 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
6342 input
= inst
->Src
[0].Register
.Index
;
6344 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6345 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6346 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6347 location
= TGSI_INTERPOLATE_LOC_CENTER
; /* sample offset will be added explicitly */
6350 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
6353 k
= eg_get_interpolator_index(ctx
->shader
->input
[input
].interpolate
, location
);
6356 interp_gpr
= ctx
->eg_interpolators
[k
].ij_index
/ 2;
6357 interp_base_chan
= 2 * (ctx
->eg_interpolators
[k
].ij_index
% 2);
6359 /* NOTE: currently offset is not perspective correct */
6360 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6361 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6362 int sample_gpr
= -1;
6363 int gradientsH
, gradientsV
;
6364 struct r600_bytecode_tex tex
;
6366 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6367 sample_gpr
= load_sample_position(ctx
, &ctx
->src
[1], ctx
->src
[1].swizzle
[0]);
6370 gradientsH
= r600_get_temp(ctx
);
6371 gradientsV
= r600_get_temp(ctx
);
6372 for (i
= 0; i
< 2; i
++) {
6373 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
6374 tex
.op
= i
== 0 ? FETCH_OP_GET_GRADIENTS_H
: FETCH_OP_GET_GRADIENTS_V
;
6375 tex
.src_gpr
= interp_gpr
;
6376 tex
.src_sel_x
= interp_base_chan
+ 0;
6377 tex
.src_sel_y
= interp_base_chan
+ 1;
6380 tex
.dst_gpr
= i
== 0 ? gradientsH
: gradientsV
;
6385 tex
.inst_mod
= 1; // Use per pixel gradient calculation
6387 tex
.resource_id
= tex
.sampler_id
;
6388 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
6393 for (i
= 0; i
< 2; i
++) {
6394 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6395 alu
.op
= ALU_OP3_MULADD
;
6397 alu
.src
[0].sel
= gradientsH
;
6398 alu
.src
[0].chan
= i
;
6399 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6400 alu
.src
[1].sel
= sample_gpr
;
6401 alu
.src
[1].chan
= 2;
6404 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 0);
6406 alu
.src
[2].sel
= interp_gpr
;
6407 alu
.src
[2].chan
= interp_base_chan
+ i
;
6408 alu
.dst
.sel
= ctx
->temp_reg
;
6412 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6417 for (i
= 0; i
< 2; i
++) {
6418 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6419 alu
.op
= ALU_OP3_MULADD
;
6421 alu
.src
[0].sel
= gradientsV
;
6422 alu
.src
[0].chan
= i
;
6423 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6424 alu
.src
[1].sel
= sample_gpr
;
6425 alu
.src
[1].chan
= 3;
6428 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 1);
6430 alu
.src
[2].sel
= ctx
->temp_reg
;
6431 alu
.src
[2].chan
= i
;
6432 alu
.dst
.sel
= ctx
->temp_reg
;
6436 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6442 tmp
= r600_get_temp(ctx
);
6443 for (i
= 0; i
< 8; i
++) {
6444 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6445 alu
.op
= i
< 4 ? ALU_OP2_INTERP_ZW
: ALU_OP2_INTERP_XY
;
6448 if ((i
> 1 && i
< 6)) {
6454 alu
.dst
.chan
= i
% 4;
6456 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6457 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6458 alu
.src
[0].sel
= ctx
->temp_reg
;
6459 alu
.src
[0].chan
= 1 - (i
% 2);
6461 alu
.src
[0].sel
= interp_gpr
;
6462 alu
.src
[0].chan
= interp_base_chan
+ 1 - (i
% 2);
6464 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
6465 alu
.src
[1].chan
= 0;
6467 alu
.last
= i
% 4 == 3;
6468 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
6470 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6475 // INTERP can't swizzle dst
6476 lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6477 for (i
= 0; i
<= lasti
; i
++) {
6478 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6481 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6482 alu
.op
= ALU_OP1_MOV
;
6483 alu
.src
[0].sel
= tmp
;
6484 alu
.src
[0].chan
= ctx
->src
[0].swizzle
[i
];
6485 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6487 alu
.last
= i
== lasti
;
6488 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6497 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
6499 struct r600_bytecode_alu alu
;
6502 for (i
= 0; i
< 4; i
++) {
6503 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6504 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
6505 alu
.op
= ALU_OP0_NOP
;
6508 alu
.op
= ALU_OP1_MOV
;
6509 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6510 alu
.src
[0].sel
= ctx
->temp_reg
;
6511 alu
.src
[0].chan
= i
;
6516 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6523 static int tgsi_make_src_for_op3(struct r600_shader_ctx
*ctx
,
6524 unsigned temp
, int chan
,
6525 struct r600_bytecode_alu_src
*bc_src
,
6526 const struct r600_shader_src
*shader_src
)
6528 struct r600_bytecode_alu alu
;
6531 r600_bytecode_src(bc_src
, shader_src
, chan
);
6533 /* op3 operands don't support abs modifier */
6535 assert(temp
!=0); /* we actually need the extra register, make sure it is allocated. */
6536 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6537 alu
.op
= ALU_OP1_MOV
;
6539 alu
.dst
.chan
= chan
;
6542 alu
.src
[0] = *bc_src
;
6543 alu
.last
= true; // sufficient?
6544 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6548 memset(bc_src
, 0, sizeof(*bc_src
));
6550 bc_src
->chan
= chan
;
6555 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
6557 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6558 struct r600_bytecode_alu alu
;
6560 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6563 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6565 if (ctx
->src
[j
].abs
)
6566 temp_regs
[j
] = r600_get_temp(ctx
);
6568 for (i
= 0; i
< lasti
+ 1; i
++) {
6569 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6572 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6573 alu
.op
= ctx
->inst_info
->op
;
6574 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6575 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[j
], i
, &alu
.src
[j
], &ctx
->src
[j
]);
6580 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6587 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6594 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
6596 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6597 struct r600_bytecode_alu alu
;
6600 for (i
= 0; i
< 4; i
++) {
6601 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6602 alu
.op
= ctx
->inst_info
->op
;
6603 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6604 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
6607 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6609 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
6610 /* handle some special cases */
6611 switch (inst
->Instruction
.Opcode
) {
6612 case TGSI_OPCODE_DP2
:
6614 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6615 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6618 case TGSI_OPCODE_DP3
:
6620 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6621 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6624 case TGSI_OPCODE_DPH
:
6626 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
6627 alu
.src
[0].chan
= 0;
6637 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6644 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
6647 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6648 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
6649 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
&&
6650 inst
->Src
[index
].Register
.File
!= TGSI_FILE_OUTPUT
) ||
6651 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
||
6652 (inst
->Src
[index
].Register
.File
== TGSI_FILE_INPUT
&& ctx
->type
== TGSI_PROCESSOR_GEOMETRY
);
6655 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
6658 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6659 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
6662 static int do_vtx_fetch_inst(struct r600_shader_ctx
*ctx
, boolean src_requires_loading
)
6664 struct r600_bytecode_vtx vtx
;
6665 struct r600_bytecode_alu alu
;
6666 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6668 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6670 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6671 if (src_requires_loading
) {
6672 for (i
= 0; i
< 4; i
++) {
6673 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6674 alu
.op
= ALU_OP1_MOV
;
6675 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6676 alu
.dst
.sel
= ctx
->temp_reg
;
6681 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6685 src_gpr
= ctx
->temp_reg
;
6688 memset(&vtx
, 0, sizeof(vtx
));
6689 vtx
.op
= FETCH_OP_VFETCH
;
6690 vtx
.buffer_id
= id
+ R600_MAX_CONST_BUFFERS
;
6691 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
6692 vtx
.src_gpr
= src_gpr
;
6693 vtx
.mega_fetch_count
= 16;
6694 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
6695 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
6696 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7; /* SEL_Y */
6697 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7; /* SEL_Z */
6698 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7; /* SEL_W */
6699 vtx
.use_const_fields
= 1;
6701 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
6704 if (ctx
->bc
->chip_class
>= EVERGREEN
)
6707 for (i
= 0; i
< 4; i
++) {
6708 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6709 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6712 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6713 alu
.op
= ALU_OP2_AND_INT
;
6716 alu
.dst
.sel
= vtx
.dst_gpr
;
6719 alu
.src
[0].sel
= vtx
.dst_gpr
;
6720 alu
.src
[0].chan
= i
;
6722 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6723 alu
.src
[1].sel
+= (id
* 2);
6724 alu
.src
[1].chan
= i
% 4;
6725 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6729 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6734 if (inst
->Dst
[0].Register
.WriteMask
& 3) {
6735 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6736 alu
.op
= ALU_OP2_OR_INT
;
6739 alu
.dst
.sel
= vtx
.dst_gpr
;
6742 alu
.src
[0].sel
= vtx
.dst_gpr
;
6743 alu
.src
[0].chan
= 3;
6745 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
+ (id
* 2) + 1;
6746 alu
.src
[1].chan
= 0;
6747 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6750 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6757 static int r600_do_buffer_txq(struct r600_shader_ctx
*ctx
)
6759 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6760 struct r600_bytecode_alu alu
;
6762 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6764 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6765 alu
.op
= ALU_OP1_MOV
;
6766 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6767 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
6768 /* channel 0 or 2 of each word */
6769 alu
.src
[0].sel
+= (id
/ 2);
6770 alu
.src
[0].chan
= (id
% 2) * 2;
6772 /* r600 we have them at channel 2 of the second dword */
6773 alu
.src
[0].sel
+= (id
* 2) + 1;
6774 alu
.src
[0].chan
= 1;
6776 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6777 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
6779 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6785 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
6787 static float one_point_five
= 1.5f
;
6788 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6789 struct r600_bytecode_tex tex
;
6790 struct r600_bytecode_alu alu
;
6794 bool read_compressed_msaa
= ctx
->bc
->has_compressed_msaa_texturing
&&
6795 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6796 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
6797 inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
6799 bool txf_add_offsets
= inst
->Texture
.NumOffsets
&&
6800 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6801 inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
;
6803 /* Texture fetch instructions can only use gprs as source.
6804 * Also they cannot negate the source or take the absolute value */
6805 const boolean src_requires_loading
= (inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
&&
6806 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQS
&&
6807 tgsi_tex_src_requires_loading(ctx
, 0)) ||
6808 read_compressed_msaa
|| txf_add_offsets
;
6810 boolean src_loaded
= FALSE
;
6811 unsigned sampler_src_reg
= inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ_LZ
? 0 : 1;
6812 int8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
6813 boolean has_txq_cube_array_z
= false;
6814 unsigned sampler_index_mode
;
6816 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
6817 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
6818 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)))
6819 if (inst
->Dst
[0].Register
.WriteMask
& 4) {
6820 ctx
->shader
->has_txq_cube_array_z_comp
= true;
6821 has_txq_cube_array_z
= true;
6824 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
6825 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
6826 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
||
6827 inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
)
6828 sampler_src_reg
= 2;
6830 /* TGSI moves the sampler to src reg 3 for TXD */
6831 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
)
6832 sampler_src_reg
= 3;
6834 sampler_index_mode
= inst
->Src
[sampler_src_reg
].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6836 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6838 if (inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
6839 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
6840 ctx
->shader
->uses_tex_buffers
= true;
6841 return r600_do_buffer_txq(ctx
);
6843 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
6844 if (ctx
->bc
->chip_class
< EVERGREEN
)
6845 ctx
->shader
->uses_tex_buffers
= true;
6846 return do_vtx_fetch_inst(ctx
, src_requires_loading
);
6850 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
6852 /* Add perspective divide */
6853 if (ctx
->bc
->chip_class
== CAYMAN
) {
6855 for (i
= 0; i
< 3; i
++) {
6856 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6857 alu
.op
= ALU_OP1_RECIP_IEEE
;
6858 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6860 alu
.dst
.sel
= ctx
->temp_reg
;
6866 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6873 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6874 alu
.op
= ALU_OP1_RECIP_IEEE
;
6875 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6877 alu
.dst
.sel
= ctx
->temp_reg
;
6878 alu
.dst
.chan
= out_chan
;
6881 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6886 for (i
= 0; i
< 3; i
++) {
6887 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6888 alu
.op
= ALU_OP2_MUL
;
6889 alu
.src
[0].sel
= ctx
->temp_reg
;
6890 alu
.src
[0].chan
= out_chan
;
6891 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6892 alu
.dst
.sel
= ctx
->temp_reg
;
6895 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6899 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6900 alu
.op
= ALU_OP1_MOV
;
6901 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
6902 alu
.src
[0].chan
= 0;
6903 alu
.dst
.sel
= ctx
->temp_reg
;
6907 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6911 src_gpr
= ctx
->temp_reg
;
6915 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
6916 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
6917 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
6918 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
6919 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
6920 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
6922 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
6923 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
6925 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6926 for (i
= 0; i
< 4; i
++) {
6927 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6928 alu
.op
= ALU_OP2_CUBE
;
6929 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
6930 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
6931 alu
.dst
.sel
= ctx
->temp_reg
;
6936 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6941 /* tmp1.z = RCP_e(|tmp1.z|) */
6942 if (ctx
->bc
->chip_class
== CAYMAN
) {
6943 for (i
= 0; i
< 3; i
++) {
6944 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6945 alu
.op
= ALU_OP1_RECIP_IEEE
;
6946 alu
.src
[0].sel
= ctx
->temp_reg
;
6947 alu
.src
[0].chan
= 2;
6949 alu
.dst
.sel
= ctx
->temp_reg
;
6955 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6960 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6961 alu
.op
= ALU_OP1_RECIP_IEEE
;
6962 alu
.src
[0].sel
= ctx
->temp_reg
;
6963 alu
.src
[0].chan
= 2;
6965 alu
.dst
.sel
= ctx
->temp_reg
;
6969 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6974 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6975 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6976 * muladd has no writemask, have to use another temp
6978 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6979 alu
.op
= ALU_OP3_MULADD
;
6982 alu
.src
[0].sel
= ctx
->temp_reg
;
6983 alu
.src
[0].chan
= 0;
6984 alu
.src
[1].sel
= ctx
->temp_reg
;
6985 alu
.src
[1].chan
= 2;
6987 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
6988 alu
.src
[2].chan
= 0;
6989 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
6991 alu
.dst
.sel
= ctx
->temp_reg
;
6995 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6999 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7000 alu
.op
= ALU_OP3_MULADD
;
7003 alu
.src
[0].sel
= ctx
->temp_reg
;
7004 alu
.src
[0].chan
= 1;
7005 alu
.src
[1].sel
= ctx
->temp_reg
;
7006 alu
.src
[1].chan
= 2;
7008 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
7009 alu
.src
[2].chan
= 0;
7010 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
7012 alu
.dst
.sel
= ctx
->temp_reg
;
7017 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7020 /* write initial compare value into Z component
7021 - W src 0 for shadow cube
7022 - X src 1 for shadow cube array */
7023 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7024 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7025 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7026 alu
.op
= ALU_OP1_MOV
;
7027 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
7028 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7030 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7031 alu
.dst
.sel
= ctx
->temp_reg
;
7035 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7040 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7041 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7042 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7043 int mytmp
= r600_get_temp(ctx
);
7044 static const float eight
= 8.0f
;
7045 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7046 alu
.op
= ALU_OP1_MOV
;
7047 alu
.src
[0].sel
= ctx
->temp_reg
;
7048 alu
.src
[0].chan
= 3;
7049 alu
.dst
.sel
= mytmp
;
7053 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7057 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7058 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7059 alu
.op
= ALU_OP3_MULADD
;
7061 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7062 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7063 alu
.src
[1].chan
= 0;
7064 alu
.src
[1].value
= *(uint32_t *)&eight
;
7065 alu
.src
[2].sel
= mytmp
;
7066 alu
.src
[2].chan
= 0;
7067 alu
.dst
.sel
= ctx
->temp_reg
;
7071 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7074 } else if (ctx
->bc
->chip_class
< EVERGREEN
) {
7075 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7076 tex
.op
= FETCH_OP_SET_CUBEMAP_INDEX
;
7077 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7078 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7079 tex
.src_gpr
= r600_get_temp(ctx
);
7084 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7085 tex
.coord_type_x
= 1;
7086 tex
.coord_type_y
= 1;
7087 tex
.coord_type_z
= 1;
7088 tex
.coord_type_w
= 1;
7089 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7090 alu
.op
= ALU_OP1_MOV
;
7091 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7092 alu
.dst
.sel
= tex
.src_gpr
;
7096 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7100 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7107 /* for cube forms of lod and bias we need to route things */
7108 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
||
7109 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
||
7110 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7111 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
7112 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7113 alu
.op
= ALU_OP1_MOV
;
7114 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7115 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
)
7116 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7118 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7119 alu
.dst
.sel
= ctx
->temp_reg
;
7123 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7129 src_gpr
= ctx
->temp_reg
;
7132 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
7133 int temp_h
= 0, temp_v
= 0;
7136 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7137 if (src_loaded
== TRUE
)
7141 for (i
= start_val
; i
< 3; i
++) {
7142 int treg
= r600_get_temp(ctx
);
7151 for (j
= 0; j
< 4; j
++) {
7152 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7153 alu
.op
= ALU_OP1_MOV
;
7154 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
7160 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7165 for (i
= 1; i
< 3; i
++) {
7166 /* set gradients h/v */
7167 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7168 tex
.op
= (i
== 1) ? FETCH_OP_SET_GRADIENTS_H
:
7169 FETCH_OP_SET_GRADIENTS_V
;
7170 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7171 tex
.sampler_index_mode
= sampler_index_mode
;
7172 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7173 tex
.resource_index_mode
= sampler_index_mode
;
7175 tex
.src_gpr
= (i
== 1) ? temp_h
: temp_v
;
7181 tex
.dst_gpr
= r600_get_temp(ctx
); /* just to avoid confusing the asm scheduler */
7182 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7183 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
7184 tex
.coord_type_x
= 1;
7185 tex
.coord_type_y
= 1;
7186 tex
.coord_type_z
= 1;
7187 tex
.coord_type_w
= 1;
7189 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7195 if (src_requires_loading
&& !src_loaded
) {
7196 for (i
= 0; i
< 4; i
++) {
7197 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7198 alu
.op
= ALU_OP1_MOV
;
7199 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
7200 alu
.dst
.sel
= ctx
->temp_reg
;
7205 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7210 src_gpr
= ctx
->temp_reg
;
7213 /* get offset values */
7214 if (inst
->Texture
.NumOffsets
) {
7215 assert(inst
->Texture
.NumOffsets
== 1);
7217 /* The texture offset feature doesn't work with the TXF instruction
7218 * and must be emulated by adding the offset to the texture coordinates. */
7219 if (txf_add_offsets
) {
7220 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
7222 switch (inst
->Texture
.Texture
) {
7223 case TGSI_TEXTURE_3D
:
7224 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7225 alu
.op
= ALU_OP2_ADD_INT
;
7226 alu
.src
[0].sel
= src_gpr
;
7227 alu
.src
[0].chan
= 2;
7228 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7229 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleZ
];
7230 alu
.dst
.sel
= src_gpr
;
7234 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7239 case TGSI_TEXTURE_2D
:
7240 case TGSI_TEXTURE_SHADOW2D
:
7241 case TGSI_TEXTURE_RECT
:
7242 case TGSI_TEXTURE_SHADOWRECT
:
7243 case TGSI_TEXTURE_2D_ARRAY
:
7244 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7245 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7246 alu
.op
= ALU_OP2_ADD_INT
;
7247 alu
.src
[0].sel
= src_gpr
;
7248 alu
.src
[0].chan
= 1;
7249 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7250 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleY
];
7251 alu
.dst
.sel
= src_gpr
;
7255 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7260 case TGSI_TEXTURE_1D
:
7261 case TGSI_TEXTURE_SHADOW1D
:
7262 case TGSI_TEXTURE_1D_ARRAY
:
7263 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7264 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7265 alu
.op
= ALU_OP2_ADD_INT
;
7266 alu
.src
[0].sel
= src_gpr
;
7267 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7268 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleX
];
7269 alu
.dst
.sel
= src_gpr
;
7272 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7276 /* texture offsets do not apply to other texture targets */
7279 switch (inst
->Texture
.Texture
) {
7280 case TGSI_TEXTURE_3D
:
7281 offset_z
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
7283 case TGSI_TEXTURE_2D
:
7284 case TGSI_TEXTURE_SHADOW2D
:
7285 case TGSI_TEXTURE_RECT
:
7286 case TGSI_TEXTURE_SHADOWRECT
:
7287 case TGSI_TEXTURE_2D_ARRAY
:
7288 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7289 offset_y
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
7291 case TGSI_TEXTURE_1D
:
7292 case TGSI_TEXTURE_SHADOW1D
:
7293 case TGSI_TEXTURE_1D_ARRAY
:
7294 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7295 offset_x
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
7300 /* Obtain the sample index for reading a compressed MSAA color texture.
7301 * To read the FMASK, we use the ldfptr instruction, which tells us
7302 * where the samples are stored.
7303 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7304 * which is the identity mapping. Each nibble says which physical sample
7305 * should be fetched to get that sample.
7307 * Assume src.z contains the sample index. It should be modified like this:
7308 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7309 * Then fetch the texel with src.
7311 if (read_compressed_msaa
) {
7312 unsigned sample_chan
= 3;
7313 unsigned temp
= r600_get_temp(ctx
);
7316 /* temp.w = ldfptr() */
7317 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7318 tex
.op
= FETCH_OP_LD
;
7319 tex
.inst_mod
= 1; /* to indicate this is ldfptr */
7320 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7321 tex
.sampler_index_mode
= sampler_index_mode
;
7322 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7323 tex
.resource_index_mode
= sampler_index_mode
;
7324 tex
.src_gpr
= src_gpr
;
7326 tex
.dst_sel_x
= 7; /* mask out these components */
7329 tex
.dst_sel_w
= 0; /* store X */
7334 tex
.offset_x
= offset_x
;
7335 tex
.offset_y
= offset_y
;
7336 tex
.offset_z
= offset_z
;
7337 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7341 /* temp.x = sample_index*4 */
7342 if (ctx
->bc
->chip_class
== CAYMAN
) {
7343 for (i
= 0 ; i
< 4; i
++) {
7344 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7345 alu
.op
= ALU_OP2_MULLO_INT
;
7346 alu
.src
[0].sel
= src_gpr
;
7347 alu
.src
[0].chan
= sample_chan
;
7348 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7349 alu
.src
[1].value
= 4;
7352 alu
.dst
.write
= i
== 0;
7355 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7360 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7361 alu
.op
= ALU_OP2_MULLO_INT
;
7362 alu
.src
[0].sel
= src_gpr
;
7363 alu
.src
[0].chan
= sample_chan
;
7364 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7365 alu
.src
[1].value
= 4;
7370 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7375 /* sample_index = temp.w >> temp.x */
7376 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7377 alu
.op
= ALU_OP2_LSHR_INT
;
7378 alu
.src
[0].sel
= temp
;
7379 alu
.src
[0].chan
= 3;
7380 alu
.src
[1].sel
= temp
;
7381 alu
.src
[1].chan
= 0;
7382 alu
.dst
.sel
= src_gpr
;
7383 alu
.dst
.chan
= sample_chan
;
7386 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7390 /* sample_index & 0xF */
7391 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7392 alu
.op
= ALU_OP2_AND_INT
;
7393 alu
.src
[0].sel
= src_gpr
;
7394 alu
.src
[0].chan
= sample_chan
;
7395 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7396 alu
.src
[1].value
= 0xF;
7397 alu
.dst
.sel
= src_gpr
;
7398 alu
.dst
.chan
= sample_chan
;
7401 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7405 /* visualize the FMASK */
7406 for (i
= 0; i
< 4; i
++) {
7407 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7408 alu
.op
= ALU_OP1_INT_TO_FLT
;
7409 alu
.src
[0].sel
= src_gpr
;
7410 alu
.src
[0].chan
= sample_chan
;
7411 alu
.dst
.sel
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7415 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7423 /* does this shader want a num layers from TXQ for a cube array? */
7424 if (has_txq_cube_array_z
) {
7425 int id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7427 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7428 alu
.op
= ALU_OP1_MOV
;
7430 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
7431 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7432 /* channel 1 or 3 of each word */
7433 alu
.src
[0].sel
+= (id
/ 2);
7434 alu
.src
[0].chan
= ((id
% 2) * 2) + 1;
7436 /* r600 we have them at channel 2 of the second dword */
7437 alu
.src
[0].sel
+= (id
* 2) + 1;
7438 alu
.src
[0].chan
= 2;
7440 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
7441 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
7443 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7446 /* disable writemask from texture instruction */
7447 inst
->Dst
[0].Register
.WriteMask
&= ~4;
7450 opcode
= ctx
->inst_info
->op
;
7451 if (opcode
== FETCH_OP_GATHER4
&&
7452 inst
->TexOffsets
[0].File
!= TGSI_FILE_NULL
&&
7453 inst
->TexOffsets
[0].File
!= TGSI_FILE_IMMEDIATE
) {
7454 opcode
= FETCH_OP_GATHER4_O
;
7456 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7457 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7458 encoded in the instruction are ignored. */
7459 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7460 tex
.op
= FETCH_OP_SET_TEXTURE_OFFSETS
;
7461 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7462 tex
.sampler_index_mode
= sampler_index_mode
;
7463 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7464 tex
.resource_index_mode
= sampler_index_mode
;
7466 tex
.src_gpr
= ctx
->file_offset
[inst
->TexOffsets
[0].File
] + inst
->TexOffsets
[0].Index
;
7467 tex
.src_sel_x
= inst
->TexOffsets
[0].SwizzleX
;
7468 tex
.src_sel_y
= inst
->TexOffsets
[0].SwizzleY
;
7469 tex
.src_sel_z
= inst
->TexOffsets
[0].SwizzleZ
;
7477 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7482 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7483 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7484 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7485 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7486 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
7487 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7488 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7490 case FETCH_OP_SAMPLE
:
7491 opcode
= FETCH_OP_SAMPLE_C
;
7493 case FETCH_OP_SAMPLE_L
:
7494 opcode
= FETCH_OP_SAMPLE_C_L
;
7496 case FETCH_OP_SAMPLE_LB
:
7497 opcode
= FETCH_OP_SAMPLE_C_LB
;
7499 case FETCH_OP_SAMPLE_G
:
7500 opcode
= FETCH_OP_SAMPLE_C_G
;
7502 /* Texture gather variants */
7503 case FETCH_OP_GATHER4
:
7504 opcode
= FETCH_OP_GATHER4_C
;
7506 case FETCH_OP_GATHER4_O
:
7507 opcode
= FETCH_OP_GATHER4_C_O
;
7512 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7515 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7516 tex
.sampler_index_mode
= sampler_index_mode
;
7517 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7518 tex
.resource_index_mode
= sampler_index_mode
;
7519 tex
.src_gpr
= src_gpr
;
7520 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7522 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_DDX_FINE
||
7523 inst
->Instruction
.Opcode
== TGSI_OPCODE_DDY_FINE
) {
7524 tex
.inst_mod
= 1; /* per pixel gradient calculation instead of per 2x2 quad */
7527 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
) {
7528 int8_t texture_component_select
= ctx
->literals
[4 * inst
->Src
[1].Register
.Index
+ inst
->Src
[1].Register
.SwizzleX
];
7529 tex
.inst_mod
= texture_component_select
;
7531 if (ctx
->bc
->chip_class
== CAYMAN
) {
7532 /* GATHER4 result order is different from TGSI TG4 */
7533 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 0 : 7;
7534 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 1 : 7;
7535 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 2 : 7;
7536 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7538 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7539 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7540 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7541 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7544 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LODQ
) {
7545 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7546 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7550 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7557 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7558 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7559 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7560 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7564 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ_LZ
||
7565 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7570 } else if (src_loaded
) {
7576 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
7577 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
7578 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
7579 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
7580 tex
.src_rel
= ctx
->src
[0].rel
;
7583 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
7584 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7585 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7586 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7590 tex
.src_sel_w
= 2; /* route Z compare or Lod value into W */
7593 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
7594 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
7595 tex
.coord_type_x
= 1;
7596 tex
.coord_type_y
= 1;
7598 tex
.coord_type_z
= 1;
7599 tex
.coord_type_w
= 1;
7601 tex
.offset_x
= offset_x
;
7602 tex
.offset_y
= offset_y
;
7603 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
&&
7604 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7605 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)) {
7609 tex
.offset_z
= offset_z
;
7612 /* Put the depth for comparison in W.
7613 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7614 * Some instructions expect the depth in Z. */
7615 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7616 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7617 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7618 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
7619 opcode
!= FETCH_OP_SAMPLE_C_L
&&
7620 opcode
!= FETCH_OP_SAMPLE_C_LB
) {
7621 tex
.src_sel_w
= tex
.src_sel_z
;
7624 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
7625 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
7626 if (opcode
== FETCH_OP_SAMPLE_C_L
||
7627 opcode
== FETCH_OP_SAMPLE_C_LB
) {
7628 /* the array index is read from Y */
7629 tex
.coord_type_y
= 0;
7631 /* the array index is read from Z */
7632 tex
.coord_type_z
= 0;
7633 tex
.src_sel_z
= tex
.src_sel_y
;
7635 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7636 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7637 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7638 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
7639 (ctx
->bc
->chip_class
>= EVERGREEN
)))
7640 /* the array index is read from Z */
7641 tex
.coord_type_z
= 0;
7643 /* mask unused source components */
7644 if (opcode
== FETCH_OP_SAMPLE
|| opcode
== FETCH_OP_GATHER4
) {
7645 switch (inst
->Texture
.Texture
) {
7646 case TGSI_TEXTURE_2D
:
7647 case TGSI_TEXTURE_RECT
:
7651 case TGSI_TEXTURE_1D_ARRAY
:
7655 case TGSI_TEXTURE_1D
:
7663 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7667 /* add shadow ambient support - gallium doesn't do it yet */
7671 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
7673 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7674 struct r600_bytecode_alu alu
;
7675 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7676 unsigned i
, temp_regs
[2];
7679 /* optimize if it's just an equal balance */
7680 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
7681 for (i
= 0; i
< lasti
+ 1; i
++) {
7682 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7685 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7686 alu
.op
= ALU_OP2_ADD
;
7687 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
7688 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7690 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7695 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7703 for (i
= 0; i
< lasti
+ 1; i
++) {
7704 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7707 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7708 alu
.op
= ALU_OP2_ADD
;
7709 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
7710 alu
.src
[0].chan
= 0;
7711 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
7712 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
7713 alu
.dst
.sel
= ctx
->temp_reg
;
7719 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7724 /* (1 - src0) * src2 */
7725 for (i
= 0; i
< lasti
+ 1; i
++) {
7726 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7729 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7730 alu
.op
= ALU_OP2_MUL
;
7731 alu
.src
[0].sel
= ctx
->temp_reg
;
7732 alu
.src
[0].chan
= i
;
7733 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7734 alu
.dst
.sel
= ctx
->temp_reg
;
7740 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7745 /* src0 * src1 + (1 - src0) * src2 */
7746 if (ctx
->src
[0].abs
)
7747 temp_regs
[0] = r600_get_temp(ctx
);
7750 if (ctx
->src
[1].abs
)
7751 temp_regs
[1] = r600_get_temp(ctx
);
7755 for (i
= 0; i
< lasti
+ 1; i
++) {
7756 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7759 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7760 alu
.op
= ALU_OP3_MULADD
;
7762 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
7765 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[1], &ctx
->src
[1]);
7768 alu
.src
[2].sel
= ctx
->temp_reg
;
7769 alu
.src
[2].chan
= i
;
7771 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7776 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7783 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
7785 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7786 struct r600_bytecode_alu alu
;
7788 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7791 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
7793 if (ctx
->src
[j
].abs
)
7794 temp_regs
[j
] = r600_get_temp(ctx
);
7797 for (i
= 0; i
< lasti
+ 1; i
++) {
7798 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7801 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7802 alu
.op
= ALU_OP3_CNDGE
;
7803 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
7806 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[2], i
, &alu
.src
[1], &ctx
->src
[2]);
7809 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[2], &ctx
->src
[1]);
7812 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7818 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7825 static int tgsi_ucmp(struct r600_shader_ctx
*ctx
)
7827 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7828 struct r600_bytecode_alu alu
;
7830 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7832 for (i
= 0; i
< lasti
+ 1; i
++) {
7833 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7836 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7837 alu
.op
= ALU_OP3_CNDE_INT
;
7838 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
7839 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7840 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
7841 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7847 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7854 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
7856 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7857 static const unsigned int src0_swizzle
[] = {2, 0, 1};
7858 static const unsigned int src1_swizzle
[] = {1, 2, 0};
7859 struct r600_bytecode_alu alu
;
7860 uint32_t use_temp
= 0;
7863 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
7866 for (i
= 0; i
< 4; i
++) {
7867 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7868 alu
.op
= ALU_OP2_MUL
;
7870 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
7871 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src1_swizzle
[i
]);
7873 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
7874 alu
.src
[0].chan
= i
;
7875 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
7876 alu
.src
[1].chan
= i
;
7879 alu
.dst
.sel
= ctx
->temp_reg
;
7885 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7890 for (i
= 0; i
< 4; i
++) {
7891 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7892 alu
.op
= ALU_OP3_MULADD
;
7895 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src1_swizzle
[i
]);
7896 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src0_swizzle
[i
]);
7898 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
7899 alu
.src
[0].chan
= i
;
7900 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
7901 alu
.src
[1].chan
= i
;
7904 alu
.src
[2].sel
= ctx
->temp_reg
;
7906 alu
.src
[2].chan
= i
;
7909 alu
.dst
.sel
= ctx
->temp_reg
;
7911 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7917 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7922 return tgsi_helper_copy(ctx
, inst
);
7926 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
7928 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7929 struct r600_bytecode_alu alu
;
7933 /* result.x = 2^floor(src); */
7934 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
7935 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7937 alu
.op
= ALU_OP1_FLOOR
;
7938 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
7940 alu
.dst
.sel
= ctx
->temp_reg
;
7944 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7948 if (ctx
->bc
->chip_class
== CAYMAN
) {
7949 for (i
= 0; i
< 3; i
++) {
7950 alu
.op
= ALU_OP1_EXP_IEEE
;
7951 alu
.src
[0].sel
= ctx
->temp_reg
;
7952 alu
.src
[0].chan
= 0;
7954 alu
.dst
.sel
= ctx
->temp_reg
;
7956 alu
.dst
.write
= i
== 0;
7958 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7963 alu
.op
= ALU_OP1_EXP_IEEE
;
7964 alu
.src
[0].sel
= ctx
->temp_reg
;
7965 alu
.src
[0].chan
= 0;
7967 alu
.dst
.sel
= ctx
->temp_reg
;
7971 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7977 /* result.y = tmp - floor(tmp); */
7978 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
7979 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7981 alu
.op
= ALU_OP1_FRACT
;
7982 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
7984 alu
.dst
.sel
= ctx
->temp_reg
;
7986 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7995 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8000 /* result.z = RoughApprox2ToX(tmp);*/
8001 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
8002 if (ctx
->bc
->chip_class
== CAYMAN
) {
8003 for (i
= 0; i
< 3; i
++) {
8004 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8005 alu
.op
= ALU_OP1_EXP_IEEE
;
8006 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8008 alu
.dst
.sel
= ctx
->temp_reg
;
8015 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8020 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8021 alu
.op
= ALU_OP1_EXP_IEEE
;
8022 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8024 alu
.dst
.sel
= ctx
->temp_reg
;
8030 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8036 /* result.w = 1.0;*/
8037 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
8038 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8040 alu
.op
= ALU_OP1_MOV
;
8041 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8042 alu
.src
[0].chan
= 0;
8044 alu
.dst
.sel
= ctx
->temp_reg
;
8048 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8052 return tgsi_helper_copy(ctx
, inst
);
8055 static int tgsi_log(struct r600_shader_ctx
*ctx
)
8057 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8058 struct r600_bytecode_alu alu
;
8062 /* result.x = floor(log2(|src|)); */
8063 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
8064 if (ctx
->bc
->chip_class
== CAYMAN
) {
8065 for (i
= 0; i
< 3; i
++) {
8066 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8068 alu
.op
= ALU_OP1_LOG_IEEE
;
8069 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8070 r600_bytecode_src_set_abs(&alu
.src
[0]);
8072 alu
.dst
.sel
= ctx
->temp_reg
;
8078 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8084 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8086 alu
.op
= ALU_OP1_LOG_IEEE
;
8087 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8088 r600_bytecode_src_set_abs(&alu
.src
[0]);
8090 alu
.dst
.sel
= ctx
->temp_reg
;
8094 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8099 alu
.op
= ALU_OP1_FLOOR
;
8100 alu
.src
[0].sel
= ctx
->temp_reg
;
8101 alu
.src
[0].chan
= 0;
8103 alu
.dst
.sel
= ctx
->temp_reg
;
8108 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8113 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8114 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
8116 if (ctx
->bc
->chip_class
== CAYMAN
) {
8117 for (i
= 0; i
< 3; i
++) {
8118 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8120 alu
.op
= ALU_OP1_LOG_IEEE
;
8121 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8122 r600_bytecode_src_set_abs(&alu
.src
[0]);
8124 alu
.dst
.sel
= ctx
->temp_reg
;
8131 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8136 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8138 alu
.op
= ALU_OP1_LOG_IEEE
;
8139 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8140 r600_bytecode_src_set_abs(&alu
.src
[0]);
8142 alu
.dst
.sel
= ctx
->temp_reg
;
8147 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8152 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8154 alu
.op
= ALU_OP1_FLOOR
;
8155 alu
.src
[0].sel
= ctx
->temp_reg
;
8156 alu
.src
[0].chan
= 1;
8158 alu
.dst
.sel
= ctx
->temp_reg
;
8163 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8167 if (ctx
->bc
->chip_class
== CAYMAN
) {
8168 for (i
= 0; i
< 3; i
++) {
8169 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8170 alu
.op
= ALU_OP1_EXP_IEEE
;
8171 alu
.src
[0].sel
= ctx
->temp_reg
;
8172 alu
.src
[0].chan
= 1;
8174 alu
.dst
.sel
= ctx
->temp_reg
;
8181 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8186 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8187 alu
.op
= ALU_OP1_EXP_IEEE
;
8188 alu
.src
[0].sel
= ctx
->temp_reg
;
8189 alu
.src
[0].chan
= 1;
8191 alu
.dst
.sel
= ctx
->temp_reg
;
8196 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8201 if (ctx
->bc
->chip_class
== CAYMAN
) {
8202 for (i
= 0; i
< 3; i
++) {
8203 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8204 alu
.op
= ALU_OP1_RECIP_IEEE
;
8205 alu
.src
[0].sel
= ctx
->temp_reg
;
8206 alu
.src
[0].chan
= 1;
8208 alu
.dst
.sel
= ctx
->temp_reg
;
8215 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8220 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8221 alu
.op
= ALU_OP1_RECIP_IEEE
;
8222 alu
.src
[0].sel
= ctx
->temp_reg
;
8223 alu
.src
[0].chan
= 1;
8225 alu
.dst
.sel
= ctx
->temp_reg
;
8230 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8235 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8237 alu
.op
= ALU_OP2_MUL
;
8239 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8240 r600_bytecode_src_set_abs(&alu
.src
[0]);
8242 alu
.src
[1].sel
= ctx
->temp_reg
;
8243 alu
.src
[1].chan
= 1;
8245 alu
.dst
.sel
= ctx
->temp_reg
;
8250 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8255 /* result.z = log2(|src|);*/
8256 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
8257 if (ctx
->bc
->chip_class
== CAYMAN
) {
8258 for (i
= 0; i
< 3; i
++) {
8259 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8261 alu
.op
= ALU_OP1_LOG_IEEE
;
8262 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8263 r600_bytecode_src_set_abs(&alu
.src
[0]);
8265 alu
.dst
.sel
= ctx
->temp_reg
;
8272 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8277 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8279 alu
.op
= ALU_OP1_LOG_IEEE
;
8280 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8281 r600_bytecode_src_set_abs(&alu
.src
[0]);
8283 alu
.dst
.sel
= ctx
->temp_reg
;
8288 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8294 /* result.w = 1.0; */
8295 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
8296 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8298 alu
.op
= ALU_OP1_MOV
;
8299 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8300 alu
.src
[0].chan
= 0;
8302 alu
.dst
.sel
= ctx
->temp_reg
;
8307 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8312 return tgsi_helper_copy(ctx
, inst
);
8315 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
8317 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8318 struct r600_bytecode_alu alu
;
8320 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8321 unsigned reg
= get_address_file_reg(ctx
, inst
->Dst
[0].Register
.Index
);
8323 assert(inst
->Dst
[0].Register
.Index
< 3);
8324 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8326 switch (inst
->Instruction
.Opcode
) {
8327 case TGSI_OPCODE_ARL
:
8328 alu
.op
= ALU_OP1_FLT_TO_INT_FLOOR
;
8330 case TGSI_OPCODE_ARR
:
8331 alu
.op
= ALU_OP1_FLT_TO_INT
;
8333 case TGSI_OPCODE_UARL
:
8334 alu
.op
= ALU_OP1_MOV
;
8341 for (i
= 0; i
<= lasti
; ++i
) {
8342 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8344 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8345 alu
.last
= i
== lasti
;
8349 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8354 if (inst
->Dst
[0].Register
.Index
> 0)
8355 ctx
->bc
->index_loaded
[inst
->Dst
[0].Register
.Index
- 1] = 0;
8357 ctx
->bc
->ar_loaded
= 0;
8361 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
8363 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8364 struct r600_bytecode_alu alu
;
8366 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8368 switch (inst
->Instruction
.Opcode
) {
8369 case TGSI_OPCODE_ARL
:
8370 memset(&alu
, 0, sizeof(alu
));
8371 alu
.op
= ALU_OP1_FLOOR
;
8372 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8374 for (i
= 0; i
<= lasti
; ++i
) {
8375 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8377 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8378 alu
.last
= i
== lasti
;
8379 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8384 memset(&alu
, 0, sizeof(alu
));
8385 alu
.op
= ALU_OP1_FLT_TO_INT
;
8386 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
8387 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8389 /* FLT_TO_INT is trans-only on r600/r700 */
8391 for (i
= 0; i
<= lasti
; ++i
) {
8393 alu
.src
[0].chan
= i
;
8394 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8398 case TGSI_OPCODE_ARR
:
8399 memset(&alu
, 0, sizeof(alu
));
8400 alu
.op
= ALU_OP1_FLT_TO_INT
;
8401 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8403 /* FLT_TO_INT is trans-only on r600/r700 */
8405 for (i
= 0; i
<= lasti
; ++i
) {
8406 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8408 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8409 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8414 case TGSI_OPCODE_UARL
:
8415 memset(&alu
, 0, sizeof(alu
));
8416 alu
.op
= ALU_OP1_MOV
;
8417 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8419 for (i
= 0; i
<= lasti
; ++i
) {
8420 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8422 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8423 alu
.last
= i
== lasti
;
8424 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8434 ctx
->bc
->ar_loaded
= 0;
8438 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
8440 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8441 struct r600_bytecode_alu alu
;
8444 for (i
= 0; i
< 4; i
++) {
8445 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8447 alu
.op
= ALU_OP2_MUL
;
8448 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8450 if (i
== 0 || i
== 3) {
8451 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8453 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8456 if (i
== 0 || i
== 2) {
8457 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
8459 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
8463 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8470 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
, int alu_type
)
8472 struct r600_bytecode_alu alu
;
8475 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8477 alu
.execute_mask
= 1;
8478 alu
.update_pred
= 1;
8480 alu
.dst
.sel
= ctx
->temp_reg
;
8484 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8485 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
8486 alu
.src
[1].chan
= 0;
8490 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, alu_type
);
8496 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
8498 unsigned force_pop
= ctx
->bc
->force_add_cf
;
8502 if (ctx
->bc
->cf_last
) {
8503 if (ctx
->bc
->cf_last
->op
== CF_OP_ALU
)
8505 else if (ctx
->bc
->cf_last
->op
== CF_OP_ALU_POP_AFTER
)
8510 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP_AFTER
;
8511 ctx
->bc
->force_add_cf
= 1;
8512 } else if (alu_pop
== 2) {
8513 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP2_AFTER
;
8514 ctx
->bc
->force_add_cf
= 1;
8521 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
8522 ctx
->bc
->cf_last
->pop_count
= pops
;
8523 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8529 static inline void callstack_update_max_depth(struct r600_shader_ctx
*ctx
,
8532 struct r600_stack_info
*stack
= &ctx
->bc
->stack
;
8533 unsigned elements
, entries
;
8535 unsigned entry_size
= stack
->entry_size
;
8537 elements
= (stack
->loop
+ stack
->push_wqm
) * entry_size
;
8538 elements
+= stack
->push
;
8540 switch (ctx
->bc
->chip_class
) {
8543 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8544 * the stack must be reserved to hold the current active/continue
8546 if (reason
== FC_PUSH_VPM
) {
8552 /* r9xx: any stack operation on empty stack consumes 2 additional
8557 /* FIXME: do the two elements added above cover the cases for the
8561 /* r8xx+: 2 extra elements are not always required, but one extra
8562 * element must be added for each of the following cases:
8563 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8565 * (Currently we don't use ALU_ELSE_AFTER.)
8566 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8567 * PUSH instruction executed.
8569 * NOTE: it seems we also need to reserve additional element in some
8570 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8571 * then STACK_SIZE should be 2 instead of 1 */
8572 if (reason
== FC_PUSH_VPM
) {
8582 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8583 * for all chips, so we use 4 in the final formula, not the real entry_size
8587 entries
= (elements
+ (entry_size
- 1)) / entry_size
;
8589 if (entries
> stack
->max_entries
)
8590 stack
->max_entries
= entries
;
8593 static inline void callstack_pop(struct r600_shader_ctx
*ctx
, unsigned reason
)
8597 --ctx
->bc
->stack
.push
;
8598 assert(ctx
->bc
->stack
.push
>= 0);
8601 --ctx
->bc
->stack
.push_wqm
;
8602 assert(ctx
->bc
->stack
.push_wqm
>= 0);
8605 --ctx
->bc
->stack
.loop
;
8606 assert(ctx
->bc
->stack
.loop
>= 0);
8614 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
)
8618 ++ctx
->bc
->stack
.push
;
8621 ++ctx
->bc
->stack
.push_wqm
;
8623 ++ctx
->bc
->stack
.loop
;
8629 callstack_update_max_depth(ctx
, reason
);
8632 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
8634 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
8636 sp
->mid
= realloc((void *)sp
->mid
,
8637 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
8638 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
8642 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
8645 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
8646 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
8649 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
8651 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
8661 static int emit_return(struct r600_shader_ctx
*ctx
)
8663 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_RETURN
));
8667 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
8670 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
));
8671 ctx
->bc
->cf_last
->pop_count
= pops
;
8672 /* XXX work out offset */
8676 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
8681 static void emit_testflag(struct r600_shader_ctx
*ctx
)
8686 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
8689 emit_jump_to_offset(ctx
, 1, 4);
8690 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
8691 pops(ctx
, ifidx
+ 1);
8695 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
8699 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
8700 ctx
->bc
->cf_last
->pop_count
= 1;
8702 fc_set_mid(ctx
, fc_sp
);
8708 static int emit_if(struct r600_shader_ctx
*ctx
, int opcode
)
8710 int alu_type
= CF_OP_ALU_PUSH_BEFORE
;
8712 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8713 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8714 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8715 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8716 if (ctx
->bc
->chip_class
== CAYMAN
&& ctx
->bc
->stack
.loop
> 1) {
8717 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_PUSH
);
8718 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8719 alu_type
= CF_OP_ALU
;
8722 emit_logic_pred(ctx
, opcode
, alu_type
);
8724 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
8726 fc_pushlevel(ctx
, FC_IF
);
8728 callstack_push(ctx
, FC_PUSH_VPM
);
8732 static int tgsi_if(struct r600_shader_ctx
*ctx
)
8734 return emit_if(ctx
, ALU_OP2_PRED_SETNE
);
8737 static int tgsi_uif(struct r600_shader_ctx
*ctx
)
8739 return emit_if(ctx
, ALU_OP2_PRED_SETNE_INT
);
8742 static int tgsi_else(struct r600_shader_ctx
*ctx
)
8744 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_ELSE
);
8745 ctx
->bc
->cf_last
->pop_count
= 1;
8747 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
8748 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
8752 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
8755 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
8756 R600_ERR("if/endif unbalanced in shader\n");
8760 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
8761 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8762 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
8764 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8768 callstack_pop(ctx
, FC_PUSH_VPM
);
8772 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
8774 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8775 * limited to 4096 iterations, like the other LOOP_* instructions. */
8776 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_START_DX10
);
8778 fc_pushlevel(ctx
, FC_LOOP
);
8780 /* check stack depth */
8781 callstack_push(ctx
, FC_LOOP
);
8785 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
8789 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_END
);
8791 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
8792 R600_ERR("loop/endloop in shader code are not paired.\n");
8796 /* fixup loop pointers - from r600isa
8797 LOOP END points to CF after LOOP START,
8798 LOOP START point to CF after LOOP END
8799 BRK/CONT point to LOOP END CF
8801 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
8803 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8805 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
8806 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
8808 /* XXX add LOOPRET support */
8810 callstack_pop(ctx
, FC_LOOP
);
8814 static int tgsi_loop_breakc(struct r600_shader_ctx
*ctx
)
8819 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
8821 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
8825 R600_ERR("BREAKC not inside loop/endloop pair\n");
8829 if (ctx
->bc
->chip_class
== EVERGREEN
&&
8830 ctx
->bc
->family
!= CHIP_CYPRESS
&&
8831 ctx
->bc
->family
!= CHIP_JUNIPER
) {
8832 /* HW bug: ALU_BREAK does not save the active mask correctly */
8837 r
= r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_BREAK
);
8840 fc_set_mid(ctx
, fscp
);
8842 return tgsi_endif(ctx
);
8844 r
= emit_logic_pred(ctx
, ALU_OP2_PRED_SETE_INT
, CF_OP_ALU_BREAK
);
8847 fc_set_mid(ctx
, fscp
);
8853 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
8857 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
8859 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
8864 R600_ERR("Break not inside loop/endloop pair\n");
8868 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
8870 fc_set_mid(ctx
, fscp
);
8875 static int tgsi_gs_emit(struct r600_shader_ctx
*ctx
)
8877 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8878 int stream
= ctx
->literals
[inst
->Src
[0].Register
.Index
* 4 + inst
->Src
[0].Register
.SwizzleX
];
8881 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
8882 emit_gs_ring_writes(ctx
, ctx
->gs_stream_output_info
, stream
, TRUE
);
8884 r
= r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
8886 ctx
->bc
->cf_last
->count
= stream
; // Count field for CUT/EMIT_VERTEX indicates which stream
8887 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
8888 return emit_inc_ring_offset(ctx
, stream
, TRUE
);
8893 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
8895 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8896 struct r600_bytecode_alu alu
;
8898 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8901 for (i
= 0; i
< lasti
+ 1; i
++) {
8902 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8905 if (ctx
->bc
->chip_class
== CAYMAN
) {
8906 for (j
= 0 ; j
< 4; j
++) {
8907 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8909 alu
.op
= ALU_OP2_MULLO_UINT
;
8910 for (k
= 0; k
< inst
->Instruction
.NumSrcRegs
; k
++) {
8911 r600_bytecode_src(&alu
.src
[k
], &ctx
->src
[k
], i
);
8914 alu
.dst
.sel
= ctx
->temp_reg
;
8915 alu
.dst
.write
= (j
== i
);
8918 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8923 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8926 alu
.dst
.sel
= ctx
->temp_reg
;
8929 alu
.op
= ALU_OP2_MULLO_UINT
;
8930 for (j
= 0; j
< 2; j
++) {
8931 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
8935 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8942 for (i
= 0; i
< lasti
+ 1; i
++) {
8943 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8946 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8947 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8949 alu
.op
= ALU_OP2_ADD_INT
;
8951 alu
.src
[0].sel
= ctx
->temp_reg
;
8952 alu
.src
[0].chan
= i
;
8954 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8958 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8965 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
8966 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
8967 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
8968 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
8971 * For state trackers other than OpenGL, we'll want to use
8972 * _RECIP_IEEE instead.
8974 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
8976 [TGSI_OPCODE_RSQ
] = { ALU_OP0_NOP
, tgsi_rsq
},
8977 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
8978 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
8979 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL
, tgsi_op2
},
8980 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
8981 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4
, tgsi_dp
},
8982 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4
, tgsi_dp
},
8983 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
8984 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN
, tgsi_op2
},
8985 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX
, tgsi_op2
},
8986 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
8987 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
8988 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD
, tgsi_op3
},
8989 [TGSI_OPCODE_SUB
] = { ALU_OP2_ADD
, tgsi_op2
},
8990 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
8991 [TGSI_OPCODE_FMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
8992 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
8993 [TGSI_OPCODE_DP2A
] = { ALU_OP0_NOP
, tgsi_unsupported
},
8994 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
8995 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
8996 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
8997 [TGSI_OPCODE_CLAMP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
8998 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
8999 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9000 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
9001 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
9002 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
9003 [TGSI_OPCODE_XPD
] = { ALU_OP0_NOP
, tgsi_xpd
},
9004 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9005 [TGSI_OPCODE_ABS
] = { ALU_OP1_MOV
, tgsi_op2
},
9006 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9007 [TGSI_OPCODE_DPH
] = { ALU_OP2_DOT4
, tgsi_dp
},
9008 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
9009 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9010 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9011 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9012 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9013 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9014 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9015 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9016 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9017 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9018 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9019 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9020 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
9021 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9022 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9023 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9024 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9025 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9026 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9027 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9028 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9029 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9030 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9031 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9032 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9033 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
9034 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9035 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9036 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9037 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9038 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9039 [TGSI_OPCODE_SCS
] = { ALU_OP0_NOP
, tgsi_scs
},
9040 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9041 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9042 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9043 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4
, tgsi_dp
},
9044 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9045 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9046 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9047 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9048 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9049 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9050 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9051 [TGSI_OPCODE_DDX_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9052 [TGSI_OPCODE_DDY_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9053 [TGSI_OPCODE_PUSHA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9054 [TGSI_OPCODE_POPA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9055 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9056 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
9057 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9058 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9059 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2_trans
},
9060 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9061 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9062 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9063 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9064 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9065 [TGSI_OPCODE_SAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9066 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9067 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9068 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9069 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9070 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9071 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9072 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9073 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9074 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9075 [TGSI_OPCODE_TXQ_LZ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9076 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9077 [105] = { ALU_OP0_NOP
, tgsi_unsupported
},
9078 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9079 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9080 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9081 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9082 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9083 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9084 [112] = { ALU_OP0_NOP
, tgsi_unsupported
},
9085 [TGSI_OPCODE_CALLNZ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9086 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9087 [TGSI_OPCODE_BREAKC
] = { ALU_OP0_NOP
, tgsi_loop_breakc
},
9088 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9089 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9090 [118] = { ALU_OP0_NOP
, tgsi_unsupported
},
9091 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2_trans
},
9092 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9093 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9094 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9095 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9096 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9097 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2_trans
},
9098 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9099 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2_trans
},
9100 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
9101 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9102 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9103 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9104 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9105 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9106 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9107 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
9108 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9109 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9110 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2_trans
},
9111 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9112 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2_swap
},
9113 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9114 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9115 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9116 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9117 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9118 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9119 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9120 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9121 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9122 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9123 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9124 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9125 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9126 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9127 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9128 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9129 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_r600_arl
},
9130 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9131 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9132 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9133 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9134 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9135 [TGSI_OPCODE_MFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9136 [TGSI_OPCODE_LFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9137 [TGSI_OPCODE_SFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9138 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9139 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9140 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9141 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9142 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9143 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9144 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9145 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9146 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9147 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9148 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9149 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9150 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9151 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9152 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
9153 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
9154 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_unsupported
},
9155 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_unsupported
},
9156 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_unsupported
},
9157 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_unsupported
},
9158 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9159 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_unsupported
},
9160 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_unsupported
},
9161 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_unsupported
},
9162 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_unsupported
},
9163 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_unsupported
},
9164 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9165 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9166 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9167 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9170 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
9171 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9172 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9173 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9174 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
9175 [TGSI_OPCODE_RSQ
] = { ALU_OP1_RECIPSQRT_IEEE
, tgsi_rsq
},
9176 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9177 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9178 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL
, tgsi_op2
},
9179 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9180 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4
, tgsi_dp
},
9181 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4
, tgsi_dp
},
9182 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9183 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN
, tgsi_op2
},
9184 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX
, tgsi_op2
},
9185 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9186 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9187 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD
, tgsi_op3
},
9188 [TGSI_OPCODE_SUB
] = { ALU_OP2_ADD
, tgsi_op2
},
9189 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9190 [TGSI_OPCODE_FMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9191 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
9192 [TGSI_OPCODE_DP2A
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9193 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9194 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9195 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9196 [TGSI_OPCODE_CLAMP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9197 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9198 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9199 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
9200 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
9201 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
9202 [TGSI_OPCODE_XPD
] = { ALU_OP0_NOP
, tgsi_xpd
},
9203 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9204 [TGSI_OPCODE_ABS
] = { ALU_OP1_MOV
, tgsi_op2
},
9205 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9206 [TGSI_OPCODE_DPH
] = { ALU_OP2_DOT4
, tgsi_dp
},
9207 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
9208 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9209 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9210 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9211 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9212 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9213 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9214 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9215 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9216 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9217 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9218 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9219 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
9220 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9221 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9222 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9223 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9224 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9225 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9226 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9227 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9228 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9229 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9230 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9231 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9232 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9233 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9234 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9235 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9236 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9237 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9238 [TGSI_OPCODE_SCS
] = { ALU_OP0_NOP
, tgsi_scs
},
9239 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9240 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9241 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9242 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4
, tgsi_dp
},
9243 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9244 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9245 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9246 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9247 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9248 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9249 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9250 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9251 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9252 [TGSI_OPCODE_PUSHA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9253 [TGSI_OPCODE_POPA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9254 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9255 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
9256 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9257 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9258 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
9259 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9260 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9261 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9262 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9263 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9264 [TGSI_OPCODE_SAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9265 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9266 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9267 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9268 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9269 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9270 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9271 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9272 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9273 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9274 [TGSI_OPCODE_TXQ_LZ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9275 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9276 [105] = { ALU_OP0_NOP
, tgsi_unsupported
},
9277 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9278 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9279 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9280 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9281 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9282 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9283 [112] = { ALU_OP0_NOP
, tgsi_unsupported
},
9284 [TGSI_OPCODE_CALLNZ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9285 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9286 [TGSI_OPCODE_BREAKC
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9287 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9288 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9289 [118] = { ALU_OP0_NOP
, tgsi_unsupported
},
9290 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_f2i
},
9291 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9292 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9293 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9294 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9295 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9296 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
9297 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9298 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_f2i
},
9299 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
9300 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9301 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9302 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9303 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9304 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9305 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9306 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
9307 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9308 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9309 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
9310 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9311 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
9312 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9313 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9314 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9315 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9316 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9317 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9318 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9319 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9320 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9321 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9322 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9323 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9324 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9325 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9326 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9327 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9328 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
9329 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9330 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9331 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9332 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9333 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9334 [TGSI_OPCODE_MFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9335 [TGSI_OPCODE_LFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9336 [TGSI_OPCODE_SFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9337 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
9338 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9339 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9340 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9341 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9342 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9343 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9344 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9345 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9346 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9347 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9348 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9349 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9350 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9351 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
9352 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
9353 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
9354 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
9355 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_op3
},
9356 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_op3
},
9357 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
9358 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
9359 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
9360 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
9361 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
9362 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
9363 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9364 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9365 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9366 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
9367 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
9368 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
9369 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
9370 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
9371 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
9372 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
9373 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
9374 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
9375 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
9376 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
9377 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
9378 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
9379 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
9380 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9381 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
9382 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
9383 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
9384 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
9385 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
9386 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
9387 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
9388 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
9389 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9392 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
9393 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9394 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9395 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9396 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, cayman_emit_float_instr
},
9397 [TGSI_OPCODE_RSQ
] = { ALU_OP1_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
9398 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9399 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9400 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL
, tgsi_op2
},
9401 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9402 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4
, tgsi_dp
},
9403 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4
, tgsi_dp
},
9404 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9405 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN
, tgsi_op2
},
9406 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX
, tgsi_op2
},
9407 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9408 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9409 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD
, tgsi_op3
},
9410 [TGSI_OPCODE_SUB
] = { ALU_OP2_ADD
, tgsi_op2
},
9411 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9412 [TGSI_OPCODE_FMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9413 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, cayman_emit_float_instr
},
9414 [TGSI_OPCODE_DP2A
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9415 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9416 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9417 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9418 [TGSI_OPCODE_CLAMP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9419 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9420 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9421 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, cayman_emit_float_instr
},
9422 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, cayman_emit_float_instr
},
9423 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, cayman_pow
},
9424 [TGSI_OPCODE_XPD
] = { ALU_OP0_NOP
, tgsi_xpd
},
9425 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9426 [TGSI_OPCODE_ABS
] = { ALU_OP1_MOV
, tgsi_op2
},
9427 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9428 [TGSI_OPCODE_DPH
] = { ALU_OP2_DOT4
, tgsi_dp
},
9429 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, cayman_trig
},
9430 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9431 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9432 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9433 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9434 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9435 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9436 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9437 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9438 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9439 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9440 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9441 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, cayman_trig
},
9442 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9443 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9444 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9445 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9446 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9447 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9448 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9449 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9450 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9451 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9452 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9453 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9454 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9455 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9456 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9457 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9458 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9459 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9460 [TGSI_OPCODE_SCS
] = { ALU_OP0_NOP
, tgsi_scs
},
9461 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9462 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9463 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9464 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4
, tgsi_dp
},
9465 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9466 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9467 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9468 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9469 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9470 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9471 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9472 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9473 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9474 [TGSI_OPCODE_PUSHA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9475 [TGSI_OPCODE_POPA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9476 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9477 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2
},
9478 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9479 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9480 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
9481 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9482 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9483 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9484 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9485 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9486 [TGSI_OPCODE_SAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9487 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9488 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9489 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9490 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9491 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9492 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9493 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9494 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9495 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9496 [TGSI_OPCODE_TXQ_LZ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9497 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9498 [105] = { ALU_OP0_NOP
, tgsi_unsupported
},
9499 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9500 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9501 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9502 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9503 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9504 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9505 [112] = { ALU_OP0_NOP
, tgsi_unsupported
},
9506 [TGSI_OPCODE_CALLNZ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9507 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9508 [TGSI_OPCODE_BREAKC
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9509 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9510 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9511 [118] = { ALU_OP0_NOP
, tgsi_unsupported
},
9512 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2
},
9513 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9514 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9515 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9516 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9517 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9518 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
9519 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9520 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2
},
9521 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2
},
9522 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9523 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9524 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9525 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9526 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9527 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9528 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_INT
, cayman_mul_int_instr
},
9529 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9530 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9531 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
9532 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9533 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
9534 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9535 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9536 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9537 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9538 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9539 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9540 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9541 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9542 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9543 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9544 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9545 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9546 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9547 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9548 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9549 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9550 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
9551 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9552 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9553 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9554 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9555 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9556 [TGSI_OPCODE_MFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9557 [TGSI_OPCODE_LFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9558 [TGSI_OPCODE_SFENCE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9559 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
9560 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9561 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9562 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9563 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9564 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9565 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9566 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9567 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9568 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9569 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9570 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9571 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9572 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9573 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, cayman_mul_int_instr
},
9574 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, cayman_mul_int_instr
},
9575 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
9576 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
9577 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_op3
},
9578 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_op3
},
9579 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
9580 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
9581 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
9582 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
9583 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
9584 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
9585 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9586 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9587 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9588 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
9589 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
9590 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
9591 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
9592 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
9593 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
9594 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
9595 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
9596 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
9597 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
9598 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
9599 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
9600 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
9601 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
9602 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9603 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
9604 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
9605 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
9606 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
9607 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
9608 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
9609 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
9610 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
9611 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},