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llvmpipe: Optimize lp_rast_triangle_32_3_16 for POWER8
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 /* Check if the bytecode has already been built. When using the llvm
198 * backend, r600_shader_from_tgsi() will take care of building the
199 * bytecode.
200 */
201 if (!shader->shader.bc.bytecode) {
202 r = r600_bytecode_build(&shader->shader.bc);
203 if (r) {
204 R600_ERR("building bytecode failed !\n");
205 goto error;
206 }
207 }
208
209 if (dump && !sb_disasm) {
210 fprintf(stderr, "--------------------------------------------------------------\n");
211 r600_bytecode_disasm(&shader->shader.bc);
212 fprintf(stderr, "______________________________________________________________\n");
213 } else if ((dump && sb_disasm) || use_sb) {
214 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
215 dump, use_sb);
216 if (r) {
217 R600_ERR("r600_sb_bytecode_process failed !\n");
218 goto error;
219 }
220 }
221
222 if (shader->gs_copy_shader) {
223 if (dump) {
224 // dump copy shader
225 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
226 &shader->gs_copy_shader->shader, dump, 0);
227 if (r)
228 goto error;
229 }
230
231 if ((r = store_shader(ctx, shader->gs_copy_shader)))
232 goto error;
233 }
234
235 /* Store the shader in a buffer. */
236 if ((r = store_shader(ctx, shader)))
237 goto error;
238
239 /* Build state. */
240 switch (shader->shader.processor_type) {
241 case TGSI_PROCESSOR_TESS_CTRL:
242 evergreen_update_hs_state(ctx, shader);
243 break;
244 case TGSI_PROCESSOR_TESS_EVAL:
245 if (key.tes.as_es)
246 evergreen_update_es_state(ctx, shader);
247 else
248 evergreen_update_vs_state(ctx, shader);
249 break;
250 case TGSI_PROCESSOR_GEOMETRY:
251 if (rctx->b.chip_class >= EVERGREEN) {
252 evergreen_update_gs_state(ctx, shader);
253 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
254 } else {
255 r600_update_gs_state(ctx, shader);
256 r600_update_vs_state(ctx, shader->gs_copy_shader);
257 }
258 break;
259 case TGSI_PROCESSOR_VERTEX:
260 export_shader = key.vs.as_es;
261 if (rctx->b.chip_class >= EVERGREEN) {
262 if (key.vs.as_ls)
263 evergreen_update_ls_state(ctx, shader);
264 else if (key.vs.as_es)
265 evergreen_update_es_state(ctx, shader);
266 else
267 evergreen_update_vs_state(ctx, shader);
268 } else {
269 if (export_shader)
270 r600_update_es_state(ctx, shader);
271 else
272 r600_update_vs_state(ctx, shader);
273 }
274 break;
275 case TGSI_PROCESSOR_FRAGMENT:
276 if (rctx->b.chip_class >= EVERGREEN) {
277 evergreen_update_ps_state(ctx, shader);
278 } else {
279 r600_update_ps_state(ctx, shader);
280 }
281 break;
282 default:
283 r = -EINVAL;
284 goto error;
285 }
286 return 0;
287
288 error:
289 r600_pipe_shader_destroy(ctx, shader);
290 return r;
291 }
292
293 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
294 {
295 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
296 r600_bytecode_clear(&shader->shader.bc);
297 r600_release_command_buffer(&shader->command_buffer);
298 }
299
300 /*
301 * tgsi -> r600 shader
302 */
303 struct r600_shader_tgsi_instruction;
304
305 struct r600_shader_src {
306 unsigned sel;
307 unsigned swizzle[4];
308 unsigned neg;
309 unsigned abs;
310 unsigned rel;
311 unsigned kc_bank;
312 boolean kc_rel; /* true if cache bank is indexed */
313 uint32_t value[4];
314 };
315
316 struct eg_interp {
317 boolean enabled;
318 unsigned ij_index;
319 };
320
321 struct r600_shader_ctx {
322 struct tgsi_shader_info info;
323 struct tgsi_parse_context parse;
324 const struct tgsi_token *tokens;
325 unsigned type;
326 unsigned file_offset[TGSI_FILE_COUNT];
327 unsigned temp_reg;
328 const struct r600_shader_tgsi_instruction *inst_info;
329 struct r600_bytecode *bc;
330 struct r600_shader *shader;
331 struct r600_shader_src src[4];
332 uint32_t *literals;
333 uint32_t nliterals;
334 uint32_t max_driver_temp_used;
335 boolean use_llvm;
336 /* needed for evergreen interpolation */
337 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
338 /* evergreen/cayman also store sample mask in face register */
339 int face_gpr;
340 /* sample id is .w component stored in fixed point position register */
341 int fixed_pt_position_gpr;
342 int colors_used;
343 boolean clip_vertex_write;
344 unsigned cv_output;
345 unsigned edgeflag_output;
346 int fragcoord_input;
347 int native_integers;
348 int next_ring_offset;
349 int gs_out_ring_offset;
350 int gs_next_vertex;
351 struct r600_shader *gs_for_vs;
352 int gs_export_gpr_tregs[4];
353 const struct pipe_stream_output_info *gs_stream_output_info;
354 unsigned enabled_stream_buffers_mask;
355 unsigned tess_input_info; /* temp with tess input offsets */
356 unsigned tess_output_info; /* temp with tess input offsets */
357 };
358
359 struct r600_shader_tgsi_instruction {
360 unsigned op;
361 int (*process)(struct r600_shader_ctx *ctx);
362 };
363
364 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
365 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
366 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
367 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
368 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
369 static int tgsi_else(struct r600_shader_ctx *ctx);
370 static int tgsi_endif(struct r600_shader_ctx *ctx);
371 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
372 static int tgsi_endloop(struct r600_shader_ctx *ctx);
373 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
374 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
375 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
376 unsigned int dst_reg);
377 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
378 const struct r600_shader_src *shader_src,
379 unsigned chan);
380 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
381 unsigned dst_reg);
382
383 static int tgsi_last_instruction(unsigned writemask)
384 {
385 int i, lasti = 0;
386
387 for (i = 0; i < 4; i++) {
388 if (writemask & (1 << i)) {
389 lasti = i;
390 }
391 }
392 return lasti;
393 }
394
395 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
396 {
397 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
398 int j;
399
400 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
401 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
402 return -EINVAL;
403 }
404 if (i->Instruction.Predicate) {
405 R600_ERR("predicate unsupported\n");
406 return -EINVAL;
407 }
408 #if 0
409 if (i->Instruction.Label) {
410 R600_ERR("label unsupported\n");
411 return -EINVAL;
412 }
413 #endif
414 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
415 if (i->Src[j].Register.Dimension) {
416 switch (i->Src[j].Register.File) {
417 case TGSI_FILE_CONSTANT:
418 break;
419 case TGSI_FILE_INPUT:
420 if (ctx->type == TGSI_PROCESSOR_GEOMETRY ||
421 ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
422 ctx->type == TGSI_PROCESSOR_TESS_EVAL)
423 break;
424 case TGSI_FILE_OUTPUT:
425 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
426 break;
427 default:
428 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
429 i->Src[j].Register.File,
430 i->Src[j].Register.Dimension);
431 return -EINVAL;
432 }
433 }
434 }
435 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
436 if (i->Dst[j].Register.Dimension) {
437 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
438 continue;
439 R600_ERR("unsupported dst (dimension)\n");
440 return -EINVAL;
441 }
442 }
443 return 0;
444 }
445
446 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
447 {
448 if (interpolate == TGSI_INTERPOLATE_COLOR ||
449 interpolate == TGSI_INTERPOLATE_LINEAR ||
450 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
451 {
452 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
453 int loc;
454
455 switch(location) {
456 case TGSI_INTERPOLATE_LOC_CENTER:
457 loc = 1;
458 break;
459 case TGSI_INTERPOLATE_LOC_CENTROID:
460 loc = 2;
461 break;
462 case TGSI_INTERPOLATE_LOC_SAMPLE:
463 default:
464 loc = 0; break;
465 }
466
467 return is_linear * 3 + loc;
468 }
469
470 return -1;
471 }
472
473 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
474 int input)
475 {
476 int i = eg_get_interpolator_index(
477 ctx->shader->input[input].interpolate,
478 ctx->shader->input[input].interpolate_location);
479 assert(i >= 0);
480 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
481 }
482
483 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
484 {
485 int i, r;
486 struct r600_bytecode_alu alu;
487 int gpr = 0, base_chan = 0;
488 int ij_index = ctx->shader->input[input].ij_index;
489
490 /* work out gpr and base_chan from index */
491 gpr = ij_index / 2;
492 base_chan = (2 * (ij_index % 2)) + 1;
493
494 for (i = 0; i < 8; i++) {
495 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
496
497 if (i < 4)
498 alu.op = ALU_OP2_INTERP_ZW;
499 else
500 alu.op = ALU_OP2_INTERP_XY;
501
502 if ((i > 1) && (i < 6)) {
503 alu.dst.sel = ctx->shader->input[input].gpr;
504 alu.dst.write = 1;
505 }
506
507 alu.dst.chan = i % 4;
508
509 alu.src[0].sel = gpr;
510 alu.src[0].chan = (base_chan - (i % 2));
511
512 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
513
514 alu.bank_swizzle_force = SQ_ALU_VEC_210;
515 if ((i % 4) == 3)
516 alu.last = 1;
517 r = r600_bytecode_add_alu(ctx->bc, &alu);
518 if (r)
519 return r;
520 }
521 return 0;
522 }
523
524 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
525 {
526 int i, r;
527 struct r600_bytecode_alu alu;
528
529 for (i = 0; i < 4; i++) {
530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
531
532 alu.op = ALU_OP1_INTERP_LOAD_P0;
533
534 alu.dst.sel = ctx->shader->input[input].gpr;
535 alu.dst.write = 1;
536
537 alu.dst.chan = i;
538
539 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
540 alu.src[0].chan = i;
541
542 if (i == 3)
543 alu.last = 1;
544 r = r600_bytecode_add_alu(ctx->bc, &alu);
545 if (r)
546 return r;
547 }
548 return 0;
549 }
550
551 /*
552 * Special export handling in shaders
553 *
554 * shader export ARRAY_BASE for EXPORT_POS:
555 * 60 is position
556 * 61 is misc vector
557 * 62, 63 are clip distance vectors
558 *
559 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
560 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
561 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
562 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
563 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
564 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
565 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
566 * exclusive from render target index)
567 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
568 *
569 *
570 * shader export ARRAY_BASE for EXPORT_PIXEL:
571 * 0-7 CB targets
572 * 61 computed Z vector
573 *
574 * The use of the values exported in the computed Z vector are controlled
575 * by DB_SHADER_CONTROL:
576 * Z_EXPORT_ENABLE - Z as a float in RED
577 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
578 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
579 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
580 * DB_SOURCE_FORMAT - export control restrictions
581 *
582 */
583
584
585 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
586 static int r600_spi_sid(struct r600_shader_io * io)
587 {
588 int index, name = io->name;
589
590 /* These params are handled differently, they don't need
591 * semantic indices, so we'll use 0 for them.
592 */
593 if (name == TGSI_SEMANTIC_POSITION ||
594 name == TGSI_SEMANTIC_PSIZE ||
595 name == TGSI_SEMANTIC_EDGEFLAG ||
596 name == TGSI_SEMANTIC_FACE ||
597 name == TGSI_SEMANTIC_SAMPLEMASK)
598 index = 0;
599 else {
600 if (name == TGSI_SEMANTIC_GENERIC) {
601 /* For generic params simply use sid from tgsi */
602 index = io->sid;
603 } else {
604 /* For non-generic params - pack name and sid into 8 bits */
605 index = 0x80 | (name<<3) | (io->sid);
606 }
607
608 /* Make sure that all really used indices have nonzero value, so
609 * we can just compare it to 0 later instead of comparing the name
610 * with different values to detect special cases. */
611 index++;
612 }
613
614 return index;
615 };
616
617 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
618 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
619 {
620 switch (semantic_name) {
621 case TGSI_SEMANTIC_POSITION:
622 return 0;
623 case TGSI_SEMANTIC_PSIZE:
624 return 1;
625 case TGSI_SEMANTIC_CLIPDIST:
626 assert(index <= 1);
627 return 2 + index;
628 case TGSI_SEMANTIC_GENERIC:
629 if (index <= 63-4)
630 return 4 + index - 9;
631 else
632 /* same explanation as in the default statement,
633 * the only user hitting this is st/nine.
634 */
635 return 0;
636
637 /* patch indices are completely separate and thus start from 0 */
638 case TGSI_SEMANTIC_TESSOUTER:
639 return 0;
640 case TGSI_SEMANTIC_TESSINNER:
641 return 1;
642 case TGSI_SEMANTIC_PATCH:
643 return 2 + index;
644
645 default:
646 /* Don't fail here. The result of this function is only used
647 * for LS, TCS, TES, and GS, where legacy GL semantics can't
648 * occur, but this function is called for all vertex shaders
649 * before it's known whether LS will be compiled or not.
650 */
651 return 0;
652 }
653 }
654
655 /* turn input into interpolate on EG */
656 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
657 {
658 int r = 0;
659
660 if (ctx->shader->input[index].spi_sid) {
661 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
662 if (ctx->shader->input[index].interpolate > 0) {
663 evergreen_interp_assign_ij_index(ctx, index);
664 if (!ctx->use_llvm)
665 r = evergreen_interp_alu(ctx, index);
666 } else {
667 if (!ctx->use_llvm)
668 r = evergreen_interp_flat(ctx, index);
669 }
670 }
671 return r;
672 }
673
674 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
675 {
676 struct r600_bytecode_alu alu;
677 int i, r;
678 int gpr_front = ctx->shader->input[front].gpr;
679 int gpr_back = ctx->shader->input[back].gpr;
680
681 for (i = 0; i < 4; i++) {
682 memset(&alu, 0, sizeof(alu));
683 alu.op = ALU_OP3_CNDGT;
684 alu.is_op3 = 1;
685 alu.dst.write = 1;
686 alu.dst.sel = gpr_front;
687 alu.src[0].sel = ctx->face_gpr;
688 alu.src[1].sel = gpr_front;
689 alu.src[2].sel = gpr_back;
690
691 alu.dst.chan = i;
692 alu.src[1].chan = i;
693 alu.src[2].chan = i;
694 alu.last = (i==3);
695
696 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
697 return r;
698 }
699
700 return 0;
701 }
702
703 /* execute a single slot ALU calculation */
704 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
705 int dst_sel, int dst_chan,
706 int src0_sel, unsigned src0_chan_val,
707 int src1_sel, unsigned src1_chan_val)
708 {
709 struct r600_bytecode_alu alu;
710 int r, i;
711
712 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
713 for (i = 0; i < 4; i++) {
714 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
715 alu.op = op;
716 alu.src[0].sel = src0_sel;
717 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
718 alu.src[0].value = src0_chan_val;
719 else
720 alu.src[0].chan = src0_chan_val;
721 alu.src[1].sel = src1_sel;
722 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
723 alu.src[1].value = src1_chan_val;
724 else
725 alu.src[1].chan = src1_chan_val;
726 alu.dst.sel = dst_sel;
727 alu.dst.chan = i;
728 alu.dst.write = i == dst_chan;
729 alu.last = (i == 3);
730 r = r600_bytecode_add_alu(ctx->bc, &alu);
731 if (r)
732 return r;
733 }
734 return 0;
735 }
736
737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
738 alu.op = op;
739 alu.src[0].sel = src0_sel;
740 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
741 alu.src[0].value = src0_chan_val;
742 else
743 alu.src[0].chan = src0_chan_val;
744 alu.src[1].sel = src1_sel;
745 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
746 alu.src[1].value = src1_chan_val;
747 else
748 alu.src[1].chan = src1_chan_val;
749 alu.dst.sel = dst_sel;
750 alu.dst.chan = dst_chan;
751 alu.dst.write = 1;
752 alu.last = 1;
753 r = r600_bytecode_add_alu(ctx->bc, &alu);
754 if (r)
755 return r;
756 return 0;
757 }
758
759 /* execute a single slot ALU calculation */
760 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
761 int dst_sel, int dst_chan,
762 int src0_sel, unsigned src0_chan_val,
763 int src1_sel, unsigned src1_chan_val,
764 int src2_sel, unsigned src2_chan_val)
765 {
766 struct r600_bytecode_alu alu;
767 int r;
768
769 /* validate this for other ops */
770 assert(op == ALU_OP3_MULADD_UINT24);
771 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
772 alu.op = op;
773 alu.src[0].sel = src0_sel;
774 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
775 alu.src[0].value = src0_chan_val;
776 else
777 alu.src[0].chan = src0_chan_val;
778 alu.src[1].sel = src1_sel;
779 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
780 alu.src[1].value = src1_chan_val;
781 else
782 alu.src[1].chan = src1_chan_val;
783 alu.src[2].sel = src2_sel;
784 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
785 alu.src[2].value = src2_chan_val;
786 else
787 alu.src[2].chan = src2_chan_val;
788 alu.dst.sel = dst_sel;
789 alu.dst.chan = dst_chan;
790 alu.is_op3 = 1;
791 alu.last = 1;
792 r = r600_bytecode_add_alu(ctx->bc, &alu);
793 if (r)
794 return r;
795 return 0;
796 }
797
798 /* put it in temp_reg.x */
799 static int get_lds_offset0(struct r600_shader_ctx *ctx,
800 int rel_patch_chan,
801 int temp_reg, bool is_patch_var)
802 {
803 int r;
804
805 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
806 /* ADD
807 Dimension - patch0_offset (input_vals.z),
808 Non-dim - patch0_data_offset (input_vals.w)
809 */
810 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
811 temp_reg, 0,
812 ctx->tess_output_info, 0,
813 0, rel_patch_chan,
814 ctx->tess_output_info, is_patch_var ? 3 : 2);
815 if (r)
816 return r;
817 return 0;
818 }
819
820 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
821 {
822 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
823 }
824
825 static int r600_get_temp(struct r600_shader_ctx *ctx)
826 {
827 return ctx->temp_reg + ctx->max_driver_temp_used++;
828 }
829
830 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
831 {
832 int i;
833 i = ctx->shader->noutput++;
834 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
835 ctx->shader->output[i].sid = 0;
836 ctx->shader->output[i].gpr = 0;
837 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
838 ctx->shader->output[i].write_mask = 0x4;
839 ctx->shader->output[i].spi_sid = prim_id_sid;
840
841 return 0;
842 }
843
844 static int tgsi_barrier(struct r600_shader_ctx *ctx)
845 {
846 struct r600_bytecode_alu alu;
847 int r;
848
849 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
850 alu.op = ctx->inst_info->op;
851 alu.last = 1;
852
853 r = r600_bytecode_add_alu(ctx->bc, &alu);
854 if (r)
855 return r;
856 return 0;
857 }
858
859 static int tgsi_declaration(struct r600_shader_ctx *ctx)
860 {
861 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
862 int r, i, j, count = d->Range.Last - d->Range.First + 1;
863
864 switch (d->Declaration.File) {
865 case TGSI_FILE_INPUT:
866 for (j = 0; j < count; j++) {
867 i = ctx->shader->ninput + j;
868 assert(i < Elements(ctx->shader->input));
869 ctx->shader->input[i].name = d->Semantic.Name;
870 ctx->shader->input[i].sid = d->Semantic.Index + j;
871 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
872 ctx->shader->input[i].interpolate_location = d->Interp.Location;
873 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
874 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
875 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
876 switch (ctx->shader->input[i].name) {
877 case TGSI_SEMANTIC_FACE:
878 if (ctx->face_gpr != -1)
879 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
880 else
881 ctx->face_gpr = ctx->shader->input[i].gpr;
882 break;
883 case TGSI_SEMANTIC_COLOR:
884 ctx->colors_used++;
885 break;
886 case TGSI_SEMANTIC_POSITION:
887 ctx->fragcoord_input = i;
888 break;
889 case TGSI_SEMANTIC_PRIMID:
890 /* set this for now */
891 ctx->shader->gs_prim_id_input = true;
892 ctx->shader->ps_prim_id_input = i;
893 break;
894 }
895 if (ctx->bc->chip_class >= EVERGREEN) {
896 if ((r = evergreen_interp_input(ctx, i)))
897 return r;
898 }
899 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
900 /* FIXME probably skip inputs if they aren't passed in the ring */
901 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
902 ctx->next_ring_offset += 16;
903 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
904 ctx->shader->gs_prim_id_input = true;
905 }
906 }
907 ctx->shader->ninput += count;
908 break;
909 case TGSI_FILE_OUTPUT:
910 for (j = 0; j < count; j++) {
911 i = ctx->shader->noutput + j;
912 assert(i < Elements(ctx->shader->output));
913 ctx->shader->output[i].name = d->Semantic.Name;
914 ctx->shader->output[i].sid = d->Semantic.Index + j;
915 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
916 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
917 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
918 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
919 ctx->type == TGSI_PROCESSOR_GEOMETRY ||
920 ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
921 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
922 switch (d->Semantic.Name) {
923 case TGSI_SEMANTIC_CLIPDIST:
924 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
925 ((d->Semantic.Index + j) << 2);
926 break;
927 case TGSI_SEMANTIC_PSIZE:
928 ctx->shader->vs_out_misc_write = 1;
929 ctx->shader->vs_out_point_size = 1;
930 break;
931 case TGSI_SEMANTIC_EDGEFLAG:
932 ctx->shader->vs_out_misc_write = 1;
933 ctx->shader->vs_out_edgeflag = 1;
934 ctx->edgeflag_output = i;
935 break;
936 case TGSI_SEMANTIC_VIEWPORT_INDEX:
937 ctx->shader->vs_out_misc_write = 1;
938 ctx->shader->vs_out_viewport = 1;
939 break;
940 case TGSI_SEMANTIC_LAYER:
941 ctx->shader->vs_out_misc_write = 1;
942 ctx->shader->vs_out_layer = 1;
943 break;
944 case TGSI_SEMANTIC_CLIPVERTEX:
945 ctx->clip_vertex_write = TRUE;
946 ctx->cv_output = i;
947 break;
948 }
949 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
950 ctx->gs_out_ring_offset += 16;
951 }
952 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
953 switch (d->Semantic.Name) {
954 case TGSI_SEMANTIC_COLOR:
955 ctx->shader->nr_ps_max_color_exports++;
956 break;
957 }
958 }
959 }
960 ctx->shader->noutput += count;
961 break;
962 case TGSI_FILE_TEMPORARY:
963 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
964 if (d->Array.ArrayID) {
965 r600_add_gpr_array(ctx->shader,
966 ctx->file_offset[TGSI_FILE_TEMPORARY] +
967 d->Range.First,
968 d->Range.Last - d->Range.First + 1, 0x0F);
969 }
970 }
971 break;
972
973 case TGSI_FILE_CONSTANT:
974 case TGSI_FILE_SAMPLER:
975 case TGSI_FILE_SAMPLER_VIEW:
976 case TGSI_FILE_ADDRESS:
977 break;
978
979 case TGSI_FILE_SYSTEM_VALUE:
980 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
981 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
982 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
983 break; /* Already handled from allocate_system_value_inputs */
984 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
985 if (!ctx->native_integers) {
986 struct r600_bytecode_alu alu;
987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
988
989 alu.op = ALU_OP1_INT_TO_FLT;
990 alu.src[0].sel = 0;
991 alu.src[0].chan = 3;
992
993 alu.dst.sel = 0;
994 alu.dst.chan = 3;
995 alu.dst.write = 1;
996 alu.last = 1;
997
998 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
999 return r;
1000 }
1001 break;
1002 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1003 break;
1004 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1005 break;
1006 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1007 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1008 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1009 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1010 unsigned temp_reg = r600_get_temp(ctx);
1011
1012 r = get_lds_offset0(ctx, 2, temp_reg, true);
1013 if (r)
1014 return r;
1015
1016 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1017 temp_reg, 0,
1018 temp_reg, 0,
1019 V_SQ_ALU_SRC_LITERAL, param * 16);
1020 if (r)
1021 return r;
1022
1023 do_lds_fetch_values(ctx, temp_reg, dreg);
1024 }
1025 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1026 /* MOV r1.x, r0.x;
1027 MOV r1.y, r0.y;
1028 */
1029 for (i = 0; i < 2; i++) {
1030 struct r600_bytecode_alu alu;
1031 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1032 alu.op = ALU_OP1_MOV;
1033 alu.src[0].sel = 0;
1034 alu.src[0].chan = 0 + i;
1035 alu.dst.sel = 1;
1036 alu.dst.chan = 0 + i;
1037 alu.dst.write = 1;
1038 alu.last = (i == 1) ? 1 : 0;
1039 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1040 return r;
1041 }
1042 /* ADD r1.z, 1.0f, -r0.x */
1043 struct r600_bytecode_alu alu;
1044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1045 alu.op = ALU_OP2_ADD;
1046 alu.src[0].sel = V_SQ_ALU_SRC_1;
1047 alu.src[1].sel = 1;
1048 alu.src[1].chan = 0;
1049 alu.src[1].neg = 1;
1050 alu.dst.sel = 1;
1051 alu.dst.chan = 2;
1052 alu.dst.write = 1;
1053 alu.last = 1;
1054 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1055 return r;
1056
1057 /* ADD r1.z, r1.z, -r1.y */
1058 alu.op = ALU_OP2_ADD;
1059 alu.src[0].sel = 1;
1060 alu.src[0].chan = 2;
1061 alu.src[1].sel = 1;
1062 alu.src[1].chan = 1;
1063 alu.src[1].neg = 1;
1064 alu.dst.sel = 1;
1065 alu.dst.chan = 2;
1066 alu.dst.write = 1;
1067 alu.last = 1;
1068 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1069 return r;
1070 break;
1071 }
1072 break;
1073 default:
1074 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1075 return -EINVAL;
1076 }
1077 return 0;
1078 }
1079
1080 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1081 {
1082 struct tgsi_parse_context parse;
1083 struct {
1084 boolean enabled;
1085 int *reg;
1086 unsigned name, alternate_name;
1087 } inputs[2] = {
1088 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1089
1090 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1091 };
1092 int i, k, num_regs = 0;
1093
1094 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1095 return 0;
1096 }
1097
1098 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1099 while (!tgsi_parse_end_of_tokens(&parse)) {
1100 tgsi_parse_token(&parse);
1101
1102 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1103 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1104 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1105 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1106 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1107 {
1108 int interpolate, location, k;
1109
1110 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1111 location = TGSI_INTERPOLATE_LOC_CENTER;
1112 inputs[1].enabled = true; /* needs SAMPLEID */
1113 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1114 location = TGSI_INTERPOLATE_LOC_CENTER;
1115 /* Needs sample positions, currently those are always available */
1116 } else {
1117 location = TGSI_INTERPOLATE_LOC_CENTROID;
1118 }
1119
1120 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1121 k = eg_get_interpolator_index(interpolate, location);
1122 ctx->eg_interpolators[k].enabled = true;
1123 }
1124 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1125 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1126 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1127 for (k = 0; k < Elements(inputs); k++) {
1128 if (d->Semantic.Name == inputs[k].name ||
1129 d->Semantic.Name == inputs[k].alternate_name) {
1130 inputs[k].enabled = true;
1131 }
1132 }
1133 }
1134 }
1135 }
1136
1137 tgsi_parse_free(&parse);
1138
1139 for (i = 0; i < Elements(inputs); i++) {
1140 boolean enabled = inputs[i].enabled;
1141 int *reg = inputs[i].reg;
1142 unsigned name = inputs[i].name;
1143
1144 if (enabled) {
1145 int gpr = gpr_offset + num_regs++;
1146
1147 // add to inputs, allocate a gpr
1148 k = ctx->shader->ninput ++;
1149 ctx->shader->input[k].name = name;
1150 ctx->shader->input[k].sid = 0;
1151 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1152 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1153 *reg = ctx->shader->input[k].gpr = gpr;
1154 }
1155 }
1156
1157 return gpr_offset + num_regs;
1158 }
1159
1160 /*
1161 * for evergreen we need to scan the shader to find the number of GPRs we need to
1162 * reserve for interpolation and system values
1163 *
1164 * we need to know if we are going to emit
1165 * any sample or centroid inputs
1166 * if perspective and linear are required
1167 */
1168 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1169 {
1170 int i;
1171 int num_baryc;
1172 struct tgsi_parse_context parse;
1173
1174 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1175
1176 for (i = 0; i < ctx->info.num_inputs; i++) {
1177 int k;
1178 /* skip position/face/mask/sampleid */
1179 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1180 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1181 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1182 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1183 continue;
1184
1185 k = eg_get_interpolator_index(
1186 ctx->info.input_interpolate[i],
1187 ctx->info.input_interpolate_loc[i]);
1188 if (k >= 0)
1189 ctx->eg_interpolators[k].enabled = TRUE;
1190 }
1191
1192 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1193 return 0;
1194 }
1195
1196 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1197 while (!tgsi_parse_end_of_tokens(&parse)) {
1198 tgsi_parse_token(&parse);
1199
1200 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1201 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1202 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1203 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1204 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1205 {
1206 int interpolate, location, k;
1207
1208 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1209 location = TGSI_INTERPOLATE_LOC_CENTER;
1210 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1211 location = TGSI_INTERPOLATE_LOC_CENTER;
1212 } else {
1213 location = TGSI_INTERPOLATE_LOC_CENTROID;
1214 }
1215
1216 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1217 k = eg_get_interpolator_index(interpolate, location);
1218 ctx->eg_interpolators[k].enabled = true;
1219 }
1220 }
1221 }
1222
1223 tgsi_parse_free(&parse);
1224
1225 /* assign gpr to each interpolator according to priority */
1226 num_baryc = 0;
1227 for (i = 0; i < Elements(ctx->eg_interpolators); i++) {
1228 if (ctx->eg_interpolators[i].enabled) {
1229 ctx->eg_interpolators[i].ij_index = num_baryc;
1230 num_baryc ++;
1231 }
1232 }
1233
1234 /* XXX PULL MODEL and LINE STIPPLE */
1235
1236 num_baryc = (num_baryc + 1) >> 1;
1237 return allocate_system_value_inputs(ctx, num_baryc);
1238 }
1239
1240 /* sample_id_sel == NULL means fetch for current sample */
1241 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1242 {
1243 struct r600_bytecode_vtx vtx;
1244 int r, t1;
1245
1246 assert(ctx->fixed_pt_position_gpr != -1);
1247
1248 t1 = r600_get_temp(ctx);
1249
1250 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1251 vtx.op = FETCH_OP_VFETCH;
1252 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1253 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1254 if (sample_id == NULL) {
1255 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1256 vtx.src_sel_x = 3;
1257 }
1258 else {
1259 struct r600_bytecode_alu alu;
1260
1261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1262 alu.op = ALU_OP1_MOV;
1263 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1264 alu.dst.sel = t1;
1265 alu.dst.write = 1;
1266 alu.last = 1;
1267 r = r600_bytecode_add_alu(ctx->bc, &alu);
1268 if (r)
1269 return r;
1270
1271 vtx.src_gpr = t1;
1272 vtx.src_sel_x = 0;
1273 }
1274 vtx.mega_fetch_count = 16;
1275 vtx.dst_gpr = t1;
1276 vtx.dst_sel_x = 0;
1277 vtx.dst_sel_y = 1;
1278 vtx.dst_sel_z = 2;
1279 vtx.dst_sel_w = 3;
1280 vtx.data_format = FMT_32_32_32_32_FLOAT;
1281 vtx.num_format_all = 2;
1282 vtx.format_comp_all = 1;
1283 vtx.use_const_fields = 0;
1284 vtx.offset = 1; // first element is size of buffer
1285 vtx.endian = r600_endian_swap(32);
1286 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1287
1288 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1289 if (r)
1290 return r;
1291
1292 return t1;
1293 }
1294
1295 static void tgsi_src(struct r600_shader_ctx *ctx,
1296 const struct tgsi_full_src_register *tgsi_src,
1297 struct r600_shader_src *r600_src)
1298 {
1299 memset(r600_src, 0, sizeof(*r600_src));
1300 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1301 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1302 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1303 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1304 r600_src->neg = tgsi_src->Register.Negate;
1305 r600_src->abs = tgsi_src->Register.Absolute;
1306
1307 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1308 int index;
1309 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1310 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1311 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1312
1313 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1314 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1315 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1316 return;
1317 }
1318 index = tgsi_src->Register.Index;
1319 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1320 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1321 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1322 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1323 r600_src->swizzle[0] = 2; // Z value
1324 r600_src->swizzle[1] = 2;
1325 r600_src->swizzle[2] = 2;
1326 r600_src->swizzle[3] = 2;
1327 r600_src->sel = ctx->face_gpr;
1328 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1329 r600_src->swizzle[0] = 3; // W value
1330 r600_src->swizzle[1] = 3;
1331 r600_src->swizzle[2] = 3;
1332 r600_src->swizzle[3] = 3;
1333 r600_src->sel = ctx->fixed_pt_position_gpr;
1334 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1335 r600_src->swizzle[0] = 0;
1336 r600_src->swizzle[1] = 1;
1337 r600_src->swizzle[2] = 4;
1338 r600_src->swizzle[3] = 4;
1339 r600_src->sel = load_sample_position(ctx, NULL, -1);
1340 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1341 r600_src->swizzle[0] = 3;
1342 r600_src->swizzle[1] = 3;
1343 r600_src->swizzle[2] = 3;
1344 r600_src->swizzle[3] = 3;
1345 r600_src->sel = 0;
1346 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1347 r600_src->swizzle[0] = 0;
1348 r600_src->swizzle[1] = 0;
1349 r600_src->swizzle[2] = 0;
1350 r600_src->swizzle[3] = 0;
1351 r600_src->sel = 0;
1352 } else if (ctx->type != TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1353 r600_src->swizzle[0] = 3;
1354 r600_src->swizzle[1] = 3;
1355 r600_src->swizzle[2] = 3;
1356 r600_src->swizzle[3] = 3;
1357 r600_src->sel = 1;
1358 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1359 r600_src->swizzle[0] = 2;
1360 r600_src->swizzle[1] = 2;
1361 r600_src->swizzle[2] = 2;
1362 r600_src->swizzle[3] = 2;
1363 r600_src->sel = 0;
1364 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1365 r600_src->sel = 1;
1366 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1367 r600_src->sel = 3;
1368 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1369 r600_src->sel = 2;
1370 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1371 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
1372 r600_src->sel = ctx->tess_input_info;
1373 r600_src->swizzle[0] = 2;
1374 r600_src->swizzle[1] = 2;
1375 r600_src->swizzle[2] = 2;
1376 r600_src->swizzle[3] = 2;
1377 } else {
1378 r600_src->sel = ctx->tess_input_info;
1379 r600_src->swizzle[0] = 3;
1380 r600_src->swizzle[1] = 3;
1381 r600_src->swizzle[2] = 3;
1382 r600_src->swizzle[3] = 3;
1383 }
1384 } else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1385 r600_src->sel = 0;
1386 r600_src->swizzle[0] = 0;
1387 r600_src->swizzle[1] = 0;
1388 r600_src->swizzle[2] = 0;
1389 r600_src->swizzle[3] = 0;
1390 } else if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1391 r600_src->sel = 0;
1392 r600_src->swizzle[0] = 3;
1393 r600_src->swizzle[1] = 3;
1394 r600_src->swizzle[2] = 3;
1395 r600_src->swizzle[3] = 3;
1396 }
1397 } else {
1398 if (tgsi_src->Register.Indirect)
1399 r600_src->rel = V_SQ_REL_RELATIVE;
1400 r600_src->sel = tgsi_src->Register.Index;
1401 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1402 }
1403 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1404 if (tgsi_src->Register.Dimension) {
1405 r600_src->kc_bank = tgsi_src->Dimension.Index;
1406 if (tgsi_src->Dimension.Indirect) {
1407 r600_src->kc_rel = 1;
1408 }
1409 }
1410 }
1411 }
1412
1413 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1414 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1415 unsigned int dst_reg)
1416 {
1417 struct r600_bytecode_vtx vtx;
1418 unsigned int ar_reg;
1419 int r;
1420
1421 if (offset) {
1422 struct r600_bytecode_alu alu;
1423
1424 memset(&alu, 0, sizeof(alu));
1425
1426 alu.op = ALU_OP2_ADD_INT;
1427 alu.src[0].sel = ctx->bc->ar_reg;
1428 alu.src[0].chan = ar_chan;
1429
1430 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1431 alu.src[1].value = offset;
1432
1433 alu.dst.sel = dst_reg;
1434 alu.dst.chan = ar_chan;
1435 alu.dst.write = 1;
1436 alu.last = 1;
1437
1438 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1439 return r;
1440
1441 ar_reg = dst_reg;
1442 } else {
1443 ar_reg = ctx->bc->ar_reg;
1444 }
1445
1446 memset(&vtx, 0, sizeof(vtx));
1447 vtx.buffer_id = cb_idx;
1448 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1449 vtx.src_gpr = ar_reg;
1450 vtx.src_sel_x = ar_chan;
1451 vtx.mega_fetch_count = 16;
1452 vtx.dst_gpr = dst_reg;
1453 vtx.dst_sel_x = 0; /* SEL_X */
1454 vtx.dst_sel_y = 1; /* SEL_Y */
1455 vtx.dst_sel_z = 2; /* SEL_Z */
1456 vtx.dst_sel_w = 3; /* SEL_W */
1457 vtx.data_format = FMT_32_32_32_32_FLOAT;
1458 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1459 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1460 vtx.endian = r600_endian_swap(32);
1461 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1462
1463 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1464 return r;
1465
1466 return 0;
1467 }
1468
1469 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1470 {
1471 struct r600_bytecode_vtx vtx;
1472 int r;
1473 unsigned index = src->Register.Index;
1474 unsigned vtx_id = src->Dimension.Index;
1475 int offset_reg = vtx_id / 3;
1476 int offset_chan = vtx_id % 3;
1477 int t2 = 0;
1478
1479 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1480 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1481
1482 if (offset_reg == 0 && offset_chan == 2)
1483 offset_chan = 3;
1484
1485 if (src->Dimension.Indirect || src->Register.Indirect)
1486 t2 = r600_get_temp(ctx);
1487
1488 if (src->Dimension.Indirect) {
1489 int treg[3];
1490 struct r600_bytecode_alu alu;
1491 int r, i;
1492 unsigned addr_reg;
1493 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1494 if (src->DimIndirect.Index > 0) {
1495 r = single_alu_op2(ctx, ALU_OP1_MOV,
1496 ctx->bc->ar_reg, 0,
1497 addr_reg, 0,
1498 0, 0);
1499 if (r)
1500 return r;
1501 }
1502 /*
1503 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1504 at least this is what fglrx seems to do. */
1505 for (i = 0; i < 3; i++) {
1506 treg[i] = r600_get_temp(ctx);
1507 }
1508 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1509
1510 for (i = 0; i < 3; i++) {
1511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1512 alu.op = ALU_OP1_MOV;
1513 alu.src[0].sel = 0;
1514 alu.src[0].chan = i == 2 ? 3 : i;
1515 alu.dst.sel = treg[i];
1516 alu.dst.chan = 0;
1517 alu.dst.write = 1;
1518 alu.last = 1;
1519 r = r600_bytecode_add_alu(ctx->bc, &alu);
1520 if (r)
1521 return r;
1522 }
1523 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1524 alu.op = ALU_OP1_MOV;
1525 alu.src[0].sel = treg[0];
1526 alu.src[0].rel = 1;
1527 alu.dst.sel = t2;
1528 alu.dst.write = 1;
1529 alu.last = 1;
1530 r = r600_bytecode_add_alu(ctx->bc, &alu);
1531 if (r)
1532 return r;
1533 offset_reg = t2;
1534 offset_chan = 0;
1535 }
1536
1537 if (src->Register.Indirect) {
1538 int addr_reg;
1539 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1540
1541 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1542
1543 /* pull the value from index_reg */
1544 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1545 t2, 1,
1546 addr_reg, 0,
1547 V_SQ_ALU_SRC_LITERAL, first);
1548 if (r)
1549 return r;
1550 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1551 t2, 0,
1552 t2, 1,
1553 V_SQ_ALU_SRC_LITERAL, 4,
1554 offset_reg, offset_chan);
1555 if (r)
1556 return r;
1557 offset_reg = t2;
1558 offset_chan = 0;
1559 index = src->Register.Index - first;
1560 }
1561
1562 memset(&vtx, 0, sizeof(vtx));
1563 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1564 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1565 vtx.src_gpr = offset_reg;
1566 vtx.src_sel_x = offset_chan;
1567 vtx.offset = index * 16; /*bytes*/
1568 vtx.mega_fetch_count = 16;
1569 vtx.dst_gpr = dst_reg;
1570 vtx.dst_sel_x = 0; /* SEL_X */
1571 vtx.dst_sel_y = 1; /* SEL_Y */
1572 vtx.dst_sel_z = 2; /* SEL_Z */
1573 vtx.dst_sel_w = 3; /* SEL_W */
1574 if (ctx->bc->chip_class >= EVERGREEN) {
1575 vtx.use_const_fields = 1;
1576 } else {
1577 vtx.data_format = FMT_32_32_32_32_FLOAT;
1578 }
1579
1580 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1581 return r;
1582
1583 return 0;
1584 }
1585
1586 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1587 {
1588 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1589 int i;
1590
1591 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1592 struct tgsi_full_src_register *src = &inst->Src[i];
1593
1594 if (src->Register.File == TGSI_FILE_INPUT) {
1595 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1596 /* primitive id is in R0.z */
1597 ctx->src[i].sel = 0;
1598 ctx->src[i].swizzle[0] = 2;
1599 }
1600 }
1601 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1602 int treg = r600_get_temp(ctx);
1603
1604 fetch_gs_input(ctx, src, treg);
1605 ctx->src[i].sel = treg;
1606 ctx->src[i].rel = 0;
1607 }
1608 }
1609 return 0;
1610 }
1611
1612
1613 /* Tessellation shaders pass outputs to the next shader using LDS.
1614 *
1615 * LS outputs = TCS(HS) inputs
1616 * TCS(HS) outputs = TES(DS) inputs
1617 *
1618 * The LDS layout is:
1619 * - TCS inputs for patch 0
1620 * - TCS inputs for patch 1
1621 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1622 * - ...
1623 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1624 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1625 * - TCS outputs for patch 1
1626 * - Per-patch TCS outputs for patch 1
1627 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1628 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1629 * - ...
1630 *
1631 * All three shaders VS(LS), TCS, TES share the same LDS space.
1632 */
1633 /* this will return with the dw address in temp_reg.x */
1634 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1635 const struct tgsi_full_dst_register *dst,
1636 const struct tgsi_full_src_register *src,
1637 int stride_bytes_reg, int stride_bytes_chan)
1638 {
1639 struct tgsi_full_dst_register reg;
1640 ubyte *name, *index, *array_first;
1641 int r;
1642 int param;
1643 struct tgsi_shader_info *info = &ctx->info;
1644 /* Set the register description. The address computation is the same
1645 * for sources and destinations. */
1646 if (src) {
1647 reg.Register.File = src->Register.File;
1648 reg.Register.Index = src->Register.Index;
1649 reg.Register.Indirect = src->Register.Indirect;
1650 reg.Register.Dimension = src->Register.Dimension;
1651 reg.Indirect = src->Indirect;
1652 reg.Dimension = src->Dimension;
1653 reg.DimIndirect = src->DimIndirect;
1654 } else
1655 reg = *dst;
1656
1657 /* If the register is 2-dimensional (e.g. an array of vertices
1658 * in a primitive), calculate the base address of the vertex. */
1659 if (reg.Register.Dimension) {
1660 int sel, chan;
1661 if (reg.Dimension.Indirect) {
1662 unsigned addr_reg;
1663 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1664
1665 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1666 /* pull the value from index_reg */
1667 sel = addr_reg;
1668 chan = 0;
1669 } else {
1670 sel = V_SQ_ALU_SRC_LITERAL;
1671 chan = reg.Dimension.Index;
1672 }
1673
1674 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1675 temp_reg, 0,
1676 stride_bytes_reg, stride_bytes_chan,
1677 sel, chan,
1678 temp_reg, 0);
1679 if (r)
1680 return r;
1681 }
1682
1683 if (reg.Register.File == TGSI_FILE_INPUT) {
1684 name = info->input_semantic_name;
1685 index = info->input_semantic_index;
1686 array_first = info->input_array_first;
1687 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1688 name = info->output_semantic_name;
1689 index = info->output_semantic_index;
1690 array_first = info->output_array_first;
1691 } else {
1692 assert(0);
1693 return -1;
1694 }
1695 if (reg.Register.Indirect) {
1696 int addr_reg;
1697 int first;
1698 /* Add the relative address of the element. */
1699 if (reg.Indirect.ArrayID)
1700 first = array_first[reg.Indirect.ArrayID];
1701 else
1702 first = reg.Register.Index;
1703
1704 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1705
1706 /* pull the value from index_reg */
1707 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1708 temp_reg, 0,
1709 V_SQ_ALU_SRC_LITERAL, 16,
1710 addr_reg, 0,
1711 temp_reg, 0);
1712 if (r)
1713 return r;
1714
1715 param = r600_get_lds_unique_index(name[first],
1716 index[first]);
1717
1718 } else {
1719 param = r600_get_lds_unique_index(name[reg.Register.Index],
1720 index[reg.Register.Index]);
1721 }
1722
1723 /* add to base_addr - passed in temp_reg.x */
1724 if (param) {
1725 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1726 temp_reg, 0,
1727 temp_reg, 0,
1728 V_SQ_ALU_SRC_LITERAL, param * 16);
1729 if (r)
1730 return r;
1731
1732 }
1733 return 0;
1734 }
1735
1736 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1737 unsigned dst_reg)
1738 {
1739 struct r600_bytecode_alu alu;
1740 int r, i;
1741
1742 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1743 ctx->bc->force_add_cf = 1;
1744 for (i = 1; i < 4; i++) {
1745 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1746 temp_reg, i,
1747 temp_reg, 0,
1748 V_SQ_ALU_SRC_LITERAL, 4 * i);
1749 if (r)
1750 return r;
1751 }
1752 for (i = 0; i < 4; i++) {
1753 /* emit an LDS_READ_RET */
1754 memset(&alu, 0, sizeof(alu));
1755 alu.op = LDS_OP1_LDS_READ_RET;
1756 alu.src[0].sel = temp_reg;
1757 alu.src[0].chan = i;
1758 alu.src[1].sel = V_SQ_ALU_SRC_0;
1759 alu.src[2].sel = V_SQ_ALU_SRC_0;
1760 alu.dst.chan = 0;
1761 alu.is_lds_idx_op = true;
1762 alu.last = 1;
1763 r = r600_bytecode_add_alu(ctx->bc, &alu);
1764 if (r)
1765 return r;
1766 }
1767 for (i = 0; i < 4; i++) {
1768 /* then read from LDS_OQ_A_POP */
1769 memset(&alu, 0, sizeof(alu));
1770
1771 alu.op = ALU_OP1_MOV;
1772 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1773 alu.src[0].chan = 0;
1774 alu.dst.sel = dst_reg;
1775 alu.dst.chan = i;
1776 alu.dst.write = 1;
1777 alu.last = 1;
1778 r = r600_bytecode_add_alu(ctx->bc, &alu);
1779 if (r)
1780 return r;
1781 }
1782 return 0;
1783 }
1784
1785 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1786 {
1787 int r;
1788 unsigned temp_reg = r600_get_temp(ctx);
1789
1790 r = get_lds_offset0(ctx, 2, temp_reg,
1791 src->Register.Dimension ? false : true);
1792 if (r)
1793 return r;
1794
1795 /* the base address is now in temp.x */
1796 r = r600_get_byte_address(ctx, temp_reg,
1797 NULL, src, ctx->tess_output_info, 1);
1798 if (r)
1799 return r;
1800
1801 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1802 if (r)
1803 return r;
1804 return 0;
1805 }
1806
1807 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1808 {
1809 int r;
1810 unsigned temp_reg = r600_get_temp(ctx);
1811
1812 /* t.x = ips * r0.y */
1813 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1814 temp_reg, 0,
1815 ctx->tess_input_info, 0,
1816 0, 1);
1817
1818 if (r)
1819 return r;
1820
1821 /* the base address is now in temp.x */
1822 r = r600_get_byte_address(ctx, temp_reg,
1823 NULL, src, ctx->tess_input_info, 1);
1824 if (r)
1825 return r;
1826
1827 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1828 if (r)
1829 return r;
1830 return 0;
1831 }
1832
1833 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1834 {
1835 int r;
1836 unsigned temp_reg = r600_get_temp(ctx);
1837
1838 r = get_lds_offset0(ctx, 1, temp_reg,
1839 src->Register.Dimension ? false : true);
1840 if (r)
1841 return r;
1842 /* the base address is now in temp.x */
1843 r = r600_get_byte_address(ctx, temp_reg,
1844 NULL, src,
1845 ctx->tess_output_info, 1);
1846 if (r)
1847 return r;
1848
1849 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1850 if (r)
1851 return r;
1852 return 0;
1853 }
1854
1855 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1856 {
1857 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1858 int i;
1859
1860 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1861 struct tgsi_full_src_register *src = &inst->Src[i];
1862
1863 if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1864 int treg = r600_get_temp(ctx);
1865 fetch_tes_input(ctx, src, treg);
1866 ctx->src[i].sel = treg;
1867 ctx->src[i].rel = 0;
1868 }
1869 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1870 int treg = r600_get_temp(ctx);
1871 fetch_tcs_input(ctx, src, treg);
1872 ctx->src[i].sel = treg;
1873 ctx->src[i].rel = 0;
1874 }
1875 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1876 int treg = r600_get_temp(ctx);
1877 fetch_tcs_output(ctx, src, treg);
1878 ctx->src[i].sel = treg;
1879 ctx->src[i].rel = 0;
1880 }
1881 }
1882 return 0;
1883 }
1884
1885 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1886 {
1887 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1888 struct r600_bytecode_alu alu;
1889 int i, j, k, nconst, r;
1890
1891 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1892 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1893 nconst++;
1894 }
1895 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1896 }
1897 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1898 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1899 continue;
1900 }
1901
1902 if (ctx->src[i].rel) {
1903 int chan = inst->Src[i].Indirect.Swizzle;
1904 int treg = r600_get_temp(ctx);
1905 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1906 return r;
1907
1908 ctx->src[i].kc_bank = 0;
1909 ctx->src[i].kc_rel = 0;
1910 ctx->src[i].sel = treg;
1911 ctx->src[i].rel = 0;
1912 j--;
1913 } else if (j > 0) {
1914 int treg = r600_get_temp(ctx);
1915 for (k = 0; k < 4; k++) {
1916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1917 alu.op = ALU_OP1_MOV;
1918 alu.src[0].sel = ctx->src[i].sel;
1919 alu.src[0].chan = k;
1920 alu.src[0].rel = ctx->src[i].rel;
1921 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1922 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1923 alu.dst.sel = treg;
1924 alu.dst.chan = k;
1925 alu.dst.write = 1;
1926 if (k == 3)
1927 alu.last = 1;
1928 r = r600_bytecode_add_alu(ctx->bc, &alu);
1929 if (r)
1930 return r;
1931 }
1932 ctx->src[i].sel = treg;
1933 ctx->src[i].rel =0;
1934 j--;
1935 }
1936 }
1937 return 0;
1938 }
1939
1940 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1941 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1942 {
1943 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1944 struct r600_bytecode_alu alu;
1945 int i, j, k, nliteral, r;
1946
1947 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1948 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1949 nliteral++;
1950 }
1951 }
1952 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1953 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1954 int treg = r600_get_temp(ctx);
1955 for (k = 0; k < 4; k++) {
1956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1957 alu.op = ALU_OP1_MOV;
1958 alu.src[0].sel = ctx->src[i].sel;
1959 alu.src[0].chan = k;
1960 alu.src[0].value = ctx->src[i].value[k];
1961 alu.dst.sel = treg;
1962 alu.dst.chan = k;
1963 alu.dst.write = 1;
1964 if (k == 3)
1965 alu.last = 1;
1966 r = r600_bytecode_add_alu(ctx->bc, &alu);
1967 if (r)
1968 return r;
1969 }
1970 ctx->src[i].sel = treg;
1971 j--;
1972 }
1973 }
1974 return 0;
1975 }
1976
1977 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1978 {
1979 int i, r, count = ctx->shader->ninput;
1980
1981 for (i = 0; i < count; i++) {
1982 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1983 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1984 if (r)
1985 return r;
1986 }
1987 }
1988 return 0;
1989 }
1990
1991 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1992 int stream, unsigned *stream_item_size)
1993 {
1994 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1995 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1996 int i, j, r;
1997
1998 /* Sanity checking. */
1999 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2000 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2001 r = -EINVAL;
2002 goto out_err;
2003 }
2004 for (i = 0; i < so->num_outputs; i++) {
2005 if (so->output[i].output_buffer >= 4) {
2006 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2007 so->output[i].output_buffer);
2008 r = -EINVAL;
2009 goto out_err;
2010 }
2011 }
2012
2013 /* Initialize locations where the outputs are stored. */
2014 for (i = 0; i < so->num_outputs; i++) {
2015
2016 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2017 start_comp[i] = so->output[i].start_component;
2018 /* Lower outputs with dst_offset < start_component.
2019 *
2020 * We can only output 4D vectors with a write mask, e.g. we can
2021 * only output the W component at offset 3, etc. If we want
2022 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2023 * to move it to X and output X. */
2024 if (so->output[i].dst_offset < so->output[i].start_component) {
2025 unsigned tmp = r600_get_temp(ctx);
2026
2027 for (j = 0; j < so->output[i].num_components; j++) {
2028 struct r600_bytecode_alu alu;
2029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2030 alu.op = ALU_OP1_MOV;
2031 alu.src[0].sel = so_gpr[i];
2032 alu.src[0].chan = so->output[i].start_component + j;
2033
2034 alu.dst.sel = tmp;
2035 alu.dst.chan = j;
2036 alu.dst.write = 1;
2037 if (j == so->output[i].num_components - 1)
2038 alu.last = 1;
2039 r = r600_bytecode_add_alu(ctx->bc, &alu);
2040 if (r)
2041 return r;
2042 }
2043 start_comp[i] = 0;
2044 so_gpr[i] = tmp;
2045 }
2046 }
2047
2048 /* Write outputs to buffers. */
2049 for (i = 0; i < so->num_outputs; i++) {
2050 struct r600_bytecode_output output;
2051
2052 if (stream != -1 && stream != so->output[i].output_buffer)
2053 continue;
2054
2055 memset(&output, 0, sizeof(struct r600_bytecode_output));
2056 output.gpr = so_gpr[i];
2057 output.elem_size = so->output[i].num_components - 1;
2058 if (output.elem_size == 2)
2059 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2060 output.array_base = so->output[i].dst_offset - start_comp[i];
2061 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2062 output.burst_count = 1;
2063 /* array_size is an upper limit for the burst_count
2064 * with MEM_STREAM instructions */
2065 output.array_size = 0xFFF;
2066 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2067
2068 if (ctx->bc->chip_class >= EVERGREEN) {
2069 switch (so->output[i].output_buffer) {
2070 case 0:
2071 output.op = CF_OP_MEM_STREAM0_BUF0;
2072 break;
2073 case 1:
2074 output.op = CF_OP_MEM_STREAM0_BUF1;
2075 break;
2076 case 2:
2077 output.op = CF_OP_MEM_STREAM0_BUF2;
2078 break;
2079 case 3:
2080 output.op = CF_OP_MEM_STREAM0_BUF3;
2081 break;
2082 }
2083 output.op += so->output[i].stream * 4;
2084 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2085 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2086 } else {
2087 switch (so->output[i].output_buffer) {
2088 case 0:
2089 output.op = CF_OP_MEM_STREAM0;
2090 break;
2091 case 1:
2092 output.op = CF_OP_MEM_STREAM1;
2093 break;
2094 case 2:
2095 output.op = CF_OP_MEM_STREAM2;
2096 break;
2097 case 3:
2098 output.op = CF_OP_MEM_STREAM3;
2099 break;
2100 }
2101 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2102 }
2103 r = r600_bytecode_add_output(ctx->bc, &output);
2104 if (r)
2105 goto out_err;
2106 }
2107 return 0;
2108 out_err:
2109 return r;
2110 }
2111
2112 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2113 {
2114 struct r600_bytecode_alu alu;
2115 unsigned reg;
2116
2117 if (!ctx->shader->vs_out_edgeflag)
2118 return;
2119
2120 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2121
2122 /* clamp(x, 0, 1) */
2123 memset(&alu, 0, sizeof(alu));
2124 alu.op = ALU_OP1_MOV;
2125 alu.src[0].sel = reg;
2126 alu.dst.sel = reg;
2127 alu.dst.write = 1;
2128 alu.dst.clamp = 1;
2129 alu.last = 1;
2130 r600_bytecode_add_alu(ctx->bc, &alu);
2131
2132 memset(&alu, 0, sizeof(alu));
2133 alu.op = ALU_OP1_FLT_TO_INT;
2134 alu.src[0].sel = reg;
2135 alu.dst.sel = reg;
2136 alu.dst.write = 1;
2137 alu.last = 1;
2138 r600_bytecode_add_alu(ctx->bc, &alu);
2139 }
2140
2141 static int generate_gs_copy_shader(struct r600_context *rctx,
2142 struct r600_pipe_shader *gs,
2143 struct pipe_stream_output_info *so)
2144 {
2145 struct r600_shader_ctx ctx = {};
2146 struct r600_shader *gs_shader = &gs->shader;
2147 struct r600_pipe_shader *cshader;
2148 int ocnt = gs_shader->noutput;
2149 struct r600_bytecode_alu alu;
2150 struct r600_bytecode_vtx vtx;
2151 struct r600_bytecode_output output;
2152 struct r600_bytecode_cf *cf_jump, *cf_pop,
2153 *last_exp_pos = NULL, *last_exp_param = NULL;
2154 int i, j, next_clip_pos = 61, next_param = 0;
2155 int ring;
2156 bool only_ring_0 = true;
2157 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2158 if (!cshader)
2159 return 0;
2160
2161 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2162 sizeof(struct r600_shader_io));
2163
2164 cshader->shader.noutput = ocnt;
2165
2166 ctx.shader = &cshader->shader;
2167 ctx.bc = &ctx.shader->bc;
2168 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
2169
2170 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2171 rctx->screen->has_compressed_msaa_texturing);
2172
2173 ctx.bc->isa = rctx->isa;
2174
2175 cf_jump = NULL;
2176 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2177
2178 /* R0.x = R0.x & 0x3fffffff */
2179 memset(&alu, 0, sizeof(alu));
2180 alu.op = ALU_OP2_AND_INT;
2181 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2182 alu.src[1].value = 0x3fffffff;
2183 alu.dst.write = 1;
2184 r600_bytecode_add_alu(ctx.bc, &alu);
2185
2186 /* R0.y = R0.x >> 30 */
2187 memset(&alu, 0, sizeof(alu));
2188 alu.op = ALU_OP2_LSHR_INT;
2189 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2190 alu.src[1].value = 0x1e;
2191 alu.dst.chan = 1;
2192 alu.dst.write = 1;
2193 alu.last = 1;
2194 r600_bytecode_add_alu(ctx.bc, &alu);
2195
2196 /* fetch vertex data from GSVS ring */
2197 for (i = 0; i < ocnt; ++i) {
2198 struct r600_shader_io *out = &ctx.shader->output[i];
2199
2200 out->gpr = i + 1;
2201 out->ring_offset = i * 16;
2202
2203 memset(&vtx, 0, sizeof(vtx));
2204 vtx.op = FETCH_OP_VFETCH;
2205 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2206 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2207 vtx.mega_fetch_count = 16;
2208 vtx.offset = out->ring_offset;
2209 vtx.dst_gpr = out->gpr;
2210 vtx.src_gpr = 0;
2211 vtx.dst_sel_x = 0;
2212 vtx.dst_sel_y = 1;
2213 vtx.dst_sel_z = 2;
2214 vtx.dst_sel_w = 3;
2215 if (rctx->b.chip_class >= EVERGREEN) {
2216 vtx.use_const_fields = 1;
2217 } else {
2218 vtx.data_format = FMT_32_32_32_32_FLOAT;
2219 }
2220
2221 r600_bytecode_add_vtx(ctx.bc, &vtx);
2222 }
2223 ctx.temp_reg = i + 1;
2224 for (ring = 3; ring >= 0; --ring) {
2225 bool enabled = false;
2226 for (i = 0; i < so->num_outputs; i++) {
2227 if (so->output[i].stream == ring) {
2228 enabled = true;
2229 if (ring > 0)
2230 only_ring_0 = false;
2231 break;
2232 }
2233 }
2234 if (ring != 0 && !enabled) {
2235 cshader->shader.ring_item_sizes[ring] = 0;
2236 continue;
2237 }
2238
2239 if (cf_jump) {
2240 // Patch up jump label
2241 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2242 cf_pop = ctx.bc->cf_last;
2243
2244 cf_jump->cf_addr = cf_pop->id + 2;
2245 cf_jump->pop_count = 1;
2246 cf_pop->cf_addr = cf_pop->id + 2;
2247 cf_pop->pop_count = 1;
2248 }
2249
2250 /* PRED_SETE_INT __, R0.y, ring */
2251 memset(&alu, 0, sizeof(alu));
2252 alu.op = ALU_OP2_PRED_SETE_INT;
2253 alu.src[0].chan = 1;
2254 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2255 alu.src[1].value = ring;
2256 alu.execute_mask = 1;
2257 alu.update_pred = 1;
2258 alu.last = 1;
2259 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2260
2261 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2262 cf_jump = ctx.bc->cf_last;
2263
2264 if (enabled)
2265 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2266 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2267 }
2268
2269 /* bc adds nops - copy it */
2270 if (ctx.bc->chip_class == R600) {
2271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2272 alu.op = ALU_OP0_NOP;
2273 alu.last = 1;
2274 r600_bytecode_add_alu(ctx.bc, &alu);
2275
2276 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2277 }
2278
2279 /* export vertex data */
2280 /* XXX factor out common code with r600_shader_from_tgsi ? */
2281 for (i = 0; i < ocnt; ++i) {
2282 struct r600_shader_io *out = &ctx.shader->output[i];
2283 bool instream0 = true;
2284 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2285 continue;
2286
2287 for (j = 0; j < so->num_outputs; j++) {
2288 if (so->output[j].register_index == i) {
2289 if (so->output[j].stream == 0)
2290 break;
2291 if (so->output[j].stream > 0)
2292 instream0 = false;
2293 }
2294 }
2295 if (!instream0)
2296 continue;
2297 memset(&output, 0, sizeof(output));
2298 output.gpr = out->gpr;
2299 output.elem_size = 3;
2300 output.swizzle_x = 0;
2301 output.swizzle_y = 1;
2302 output.swizzle_z = 2;
2303 output.swizzle_w = 3;
2304 output.burst_count = 1;
2305 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2306 output.op = CF_OP_EXPORT;
2307 switch (out->name) {
2308 case TGSI_SEMANTIC_POSITION:
2309 output.array_base = 60;
2310 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2311 break;
2312
2313 case TGSI_SEMANTIC_PSIZE:
2314 output.array_base = 61;
2315 if (next_clip_pos == 61)
2316 next_clip_pos = 62;
2317 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2318 output.swizzle_y = 7;
2319 output.swizzle_z = 7;
2320 output.swizzle_w = 7;
2321 ctx.shader->vs_out_misc_write = 1;
2322 ctx.shader->vs_out_point_size = 1;
2323 break;
2324 case TGSI_SEMANTIC_LAYER:
2325 if (out->spi_sid) {
2326 /* duplicate it as PARAM to pass to the pixel shader */
2327 output.array_base = next_param++;
2328 r600_bytecode_add_output(ctx.bc, &output);
2329 last_exp_param = ctx.bc->cf_last;
2330 }
2331 output.array_base = 61;
2332 if (next_clip_pos == 61)
2333 next_clip_pos = 62;
2334 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2335 output.swizzle_x = 7;
2336 output.swizzle_y = 7;
2337 output.swizzle_z = 0;
2338 output.swizzle_w = 7;
2339 ctx.shader->vs_out_misc_write = 1;
2340 ctx.shader->vs_out_layer = 1;
2341 break;
2342 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2343 if (out->spi_sid) {
2344 /* duplicate it as PARAM to pass to the pixel shader */
2345 output.array_base = next_param++;
2346 r600_bytecode_add_output(ctx.bc, &output);
2347 last_exp_param = ctx.bc->cf_last;
2348 }
2349 output.array_base = 61;
2350 if (next_clip_pos == 61)
2351 next_clip_pos = 62;
2352 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2353 ctx.shader->vs_out_misc_write = 1;
2354 ctx.shader->vs_out_viewport = 1;
2355 output.swizzle_x = 7;
2356 output.swizzle_y = 7;
2357 output.swizzle_z = 7;
2358 output.swizzle_w = 0;
2359 break;
2360 case TGSI_SEMANTIC_CLIPDIST:
2361 /* spi_sid is 0 for clipdistance outputs that were generated
2362 * for clipvertex - we don't need to pass them to PS */
2363 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2364 if (out->spi_sid) {
2365 /* duplicate it as PARAM to pass to the pixel shader */
2366 output.array_base = next_param++;
2367 r600_bytecode_add_output(ctx.bc, &output);
2368 last_exp_param = ctx.bc->cf_last;
2369 }
2370 output.array_base = next_clip_pos++;
2371 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2372 break;
2373 case TGSI_SEMANTIC_FOG:
2374 output.swizzle_y = 4; /* 0 */
2375 output.swizzle_z = 4; /* 0 */
2376 output.swizzle_w = 5; /* 1 */
2377 break;
2378 default:
2379 output.array_base = next_param++;
2380 break;
2381 }
2382 r600_bytecode_add_output(ctx.bc, &output);
2383 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2384 last_exp_param = ctx.bc->cf_last;
2385 else
2386 last_exp_pos = ctx.bc->cf_last;
2387 }
2388
2389 if (!last_exp_pos) {
2390 memset(&output, 0, sizeof(output));
2391 output.gpr = 0;
2392 output.elem_size = 3;
2393 output.swizzle_x = 7;
2394 output.swizzle_y = 7;
2395 output.swizzle_z = 7;
2396 output.swizzle_w = 7;
2397 output.burst_count = 1;
2398 output.type = 2;
2399 output.op = CF_OP_EXPORT;
2400 output.array_base = 60;
2401 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2402 r600_bytecode_add_output(ctx.bc, &output);
2403 last_exp_pos = ctx.bc->cf_last;
2404 }
2405
2406 if (!last_exp_param) {
2407 memset(&output, 0, sizeof(output));
2408 output.gpr = 0;
2409 output.elem_size = 3;
2410 output.swizzle_x = 7;
2411 output.swizzle_y = 7;
2412 output.swizzle_z = 7;
2413 output.swizzle_w = 7;
2414 output.burst_count = 1;
2415 output.type = 2;
2416 output.op = CF_OP_EXPORT;
2417 output.array_base = next_param++;
2418 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2419 r600_bytecode_add_output(ctx.bc, &output);
2420 last_exp_param = ctx.bc->cf_last;
2421 }
2422
2423 last_exp_pos->op = CF_OP_EXPORT_DONE;
2424 last_exp_param->op = CF_OP_EXPORT_DONE;
2425
2426 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2427 cf_pop = ctx.bc->cf_last;
2428
2429 cf_jump->cf_addr = cf_pop->id + 2;
2430 cf_jump->pop_count = 1;
2431 cf_pop->cf_addr = cf_pop->id + 2;
2432 cf_pop->pop_count = 1;
2433
2434 if (ctx.bc->chip_class == CAYMAN)
2435 cm_bytecode_add_cf_end(ctx.bc);
2436 else {
2437 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2438 ctx.bc->cf_last->end_of_program = 1;
2439 }
2440
2441 gs->gs_copy_shader = cshader;
2442 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2443
2444 ctx.bc->nstack = 1;
2445
2446 return r600_bytecode_build(ctx.bc);
2447 }
2448
2449 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2450 {
2451 if (ind) {
2452 struct r600_bytecode_alu alu;
2453 int r;
2454
2455 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2456 alu.op = ALU_OP2_ADD_INT;
2457 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2458 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2459 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2460 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2461 alu.dst.write = 1;
2462 alu.last = 1;
2463 r = r600_bytecode_add_alu(ctx->bc, &alu);
2464 if (r)
2465 return r;
2466 }
2467 return 0;
2468 }
2469
2470 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2471 {
2472 struct r600_bytecode_output output;
2473 int i, k, ring_offset;
2474 int effective_stream = stream == -1 ? 0 : stream;
2475 int idx = 0;
2476
2477 for (i = 0; i < ctx->shader->noutput; i++) {
2478 if (ctx->gs_for_vs) {
2479 /* for ES we need to lookup corresponding ring offset expected by GS
2480 * (map this output to GS input by name and sid) */
2481 /* FIXME precompute offsets */
2482 ring_offset = -1;
2483 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2484 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2485 struct r600_shader_io *out = &ctx->shader->output[i];
2486 if (in->name == out->name && in->sid == out->sid)
2487 ring_offset = in->ring_offset;
2488 }
2489
2490 if (ring_offset == -1)
2491 continue;
2492 } else {
2493 ring_offset = idx * 16;
2494 idx++;
2495 }
2496
2497 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2498 continue;
2499 /* next_ring_offset after parsing input decls contains total size of
2500 * single vertex data, gs_next_vertex - current vertex index */
2501 if (!ind)
2502 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2503
2504 memset(&output, 0, sizeof(struct r600_bytecode_output));
2505 output.gpr = ctx->shader->output[i].gpr;
2506 output.elem_size = 3;
2507 output.comp_mask = 0xF;
2508 output.burst_count = 1;
2509
2510 if (ind)
2511 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2512 else
2513 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2514
2515 switch (stream) {
2516 default:
2517 case 0:
2518 output.op = CF_OP_MEM_RING; break;
2519 case 1:
2520 output.op = CF_OP_MEM_RING1; break;
2521 case 2:
2522 output.op = CF_OP_MEM_RING2; break;
2523 case 3:
2524 output.op = CF_OP_MEM_RING3; break;
2525 }
2526
2527 if (ind) {
2528 output.array_base = ring_offset >> 2; /* in dwords */
2529 output.array_size = 0xfff;
2530 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2531 } else
2532 output.array_base = ring_offset >> 2; /* in dwords */
2533 r600_bytecode_add_output(ctx->bc, &output);
2534 }
2535
2536 ++ctx->gs_next_vertex;
2537 return 0;
2538 }
2539
2540
2541 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2542 {
2543 int r;
2544 struct r600_bytecode_vtx vtx;
2545 int temp_val = ctx->temp_reg;
2546 /* need to store the TCS output somewhere */
2547 r = single_alu_op2(ctx, ALU_OP1_MOV,
2548 temp_val, 0,
2549 V_SQ_ALU_SRC_LITERAL, 0,
2550 0, 0);
2551 if (r)
2552 return r;
2553
2554 /* used by VS/TCS */
2555 if (ctx->tess_input_info) {
2556 /* fetch tcs input values into resv space */
2557 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2558 vtx.op = FETCH_OP_VFETCH;
2559 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2560 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2561 vtx.mega_fetch_count = 16;
2562 vtx.data_format = FMT_32_32_32_32;
2563 vtx.num_format_all = 2;
2564 vtx.format_comp_all = 1;
2565 vtx.use_const_fields = 0;
2566 vtx.endian = r600_endian_swap(32);
2567 vtx.srf_mode_all = 1;
2568 vtx.offset = 0;
2569 vtx.dst_gpr = ctx->tess_input_info;
2570 vtx.dst_sel_x = 0;
2571 vtx.dst_sel_y = 1;
2572 vtx.dst_sel_z = 2;
2573 vtx.dst_sel_w = 3;
2574 vtx.src_gpr = temp_val;
2575 vtx.src_sel_x = 0;
2576
2577 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2578 if (r)
2579 return r;
2580 }
2581
2582 /* used by TCS/TES */
2583 if (ctx->tess_output_info) {
2584 /* fetch tcs output values into resv space */
2585 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2586 vtx.op = FETCH_OP_VFETCH;
2587 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2588 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2589 vtx.mega_fetch_count = 16;
2590 vtx.data_format = FMT_32_32_32_32;
2591 vtx.num_format_all = 2;
2592 vtx.format_comp_all = 1;
2593 vtx.use_const_fields = 0;
2594 vtx.endian = r600_endian_swap(32);
2595 vtx.srf_mode_all = 1;
2596 vtx.offset = 16;
2597 vtx.dst_gpr = ctx->tess_output_info;
2598 vtx.dst_sel_x = 0;
2599 vtx.dst_sel_y = 1;
2600 vtx.dst_sel_z = 2;
2601 vtx.dst_sel_w = 3;
2602 vtx.src_gpr = temp_val;
2603 vtx.src_sel_x = 0;
2604
2605 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2606 if (r)
2607 return r;
2608 }
2609 return 0;
2610 }
2611
2612 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2613 {
2614 int i, j, r;
2615 int temp_reg;
2616
2617 /* fetch tcs input values into input_vals */
2618 ctx->tess_input_info = r600_get_temp(ctx);
2619 ctx->tess_output_info = 0;
2620 r = r600_fetch_tess_io_info(ctx);
2621 if (r)
2622 return r;
2623
2624 temp_reg = r600_get_temp(ctx);
2625 /* dst reg contains LDS address stride * idx */
2626 /* MUL vertexID, vertex_dw_stride */
2627 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2628 temp_reg, 0,
2629 ctx->tess_input_info, 1,
2630 0, 1); /* rel id in r0.y? */
2631 if (r)
2632 return r;
2633
2634 for (i = 0; i < ctx->shader->noutput; i++) {
2635 struct r600_bytecode_alu alu;
2636 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2637
2638 if (param) {
2639 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2640 temp_reg, 1,
2641 temp_reg, 0,
2642 V_SQ_ALU_SRC_LITERAL, param * 16);
2643 if (r)
2644 return r;
2645 }
2646
2647 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2648 temp_reg, 2,
2649 temp_reg, param ? 1 : 0,
2650 V_SQ_ALU_SRC_LITERAL, 8);
2651 if (r)
2652 return r;
2653
2654
2655 for (j = 0; j < 2; j++) {
2656 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2657 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2658 alu.op = LDS_OP3_LDS_WRITE_REL;
2659 alu.src[0].sel = temp_reg;
2660 alu.src[0].chan = chan;
2661 alu.src[1].sel = ctx->shader->output[i].gpr;
2662 alu.src[1].chan = j * 2;
2663 alu.src[2].sel = ctx->shader->output[i].gpr;
2664 alu.src[2].chan = (j * 2) + 1;
2665 alu.last = 1;
2666 alu.dst.chan = 0;
2667 alu.lds_idx = 1;
2668 alu.is_lds_idx_op = true;
2669 r = r600_bytecode_add_alu(ctx->bc, &alu);
2670 if (r)
2671 return r;
2672 }
2673 }
2674 return 0;
2675 }
2676
2677 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2678 {
2679 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2680 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2681 int i, r, lasti;
2682 int temp_reg = r600_get_temp(ctx);
2683 struct r600_bytecode_alu alu;
2684 unsigned write_mask = dst->Register.WriteMask;
2685
2686 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2687 return 0;
2688
2689 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2690 if (r)
2691 return r;
2692
2693 /* the base address is now in temp.x */
2694 r = r600_get_byte_address(ctx, temp_reg,
2695 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2696 if (r)
2697 return r;
2698
2699 /* LDS write */
2700 lasti = tgsi_last_instruction(write_mask);
2701 for (i = 1; i <= lasti; i++) {
2702
2703 if (!(write_mask & (1 << i)))
2704 continue;
2705 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2706 temp_reg, i,
2707 temp_reg, 0,
2708 V_SQ_ALU_SRC_LITERAL, 4 * i);
2709 if (r)
2710 return r;
2711 }
2712
2713 for (i = 0; i <= lasti; i++) {
2714 if (!(write_mask & (1 << i)))
2715 continue;
2716
2717 if ((i == 0 && ((write_mask & 3) == 3)) ||
2718 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2720 alu.op = LDS_OP3_LDS_WRITE_REL;
2721 alu.src[0].sel = temp_reg;
2722 alu.src[0].chan = i;
2723
2724 alu.src[1].sel = dst->Register.Index;
2725 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2726 alu.src[1].chan = i;
2727
2728 alu.src[2].sel = dst->Register.Index;
2729 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2730 alu.src[2].chan = i + 1;
2731 alu.lds_idx = 1;
2732 alu.dst.chan = 0;
2733 alu.last = 1;
2734 alu.is_lds_idx_op = true;
2735 r = r600_bytecode_add_alu(ctx->bc, &alu);
2736 if (r)
2737 return r;
2738 i += 1;
2739 continue;
2740 }
2741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2742 alu.op = LDS_OP2_LDS_WRITE;
2743 alu.src[0].sel = temp_reg;
2744 alu.src[0].chan = i;
2745
2746 alu.src[1].sel = dst->Register.Index;
2747 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2748 alu.src[1].chan = i;
2749
2750 alu.src[2].sel = V_SQ_ALU_SRC_0;
2751 alu.dst.chan = 0;
2752 alu.last = 1;
2753 alu.is_lds_idx_op = true;
2754 r = r600_bytecode_add_alu(ctx->bc, &alu);
2755 if (r)
2756 return r;
2757 }
2758 return 0;
2759 }
2760
2761 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2762 int output_idx)
2763 {
2764 int param;
2765 unsigned temp_reg = r600_get_temp(ctx);
2766 unsigned name = ctx->shader->output[output_idx].name;
2767 int dreg = ctx->shader->output[output_idx].gpr;
2768 int r;
2769
2770 param = r600_get_lds_unique_index(name, 0);
2771 r = get_lds_offset0(ctx, 1, temp_reg, true);
2772 if (r)
2773 return r;
2774
2775 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2776 temp_reg, 0,
2777 temp_reg, 0,
2778 V_SQ_ALU_SRC_LITERAL, param * 16);
2779 if (r)
2780 return r;
2781
2782 do_lds_fetch_values(ctx, temp_reg, dreg);
2783 return 0;
2784 }
2785
2786 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2787 {
2788 int i;
2789 int stride, outer_comps, inner_comps;
2790 int tessinner_idx = -1, tessouter_idx = -1;
2791 int r;
2792 int temp_reg = r600_get_temp(ctx);
2793 int treg[3] = {-1, -1, -1};
2794 struct r600_bytecode_alu alu;
2795 struct r600_bytecode_cf *cf_jump, *cf_pop;
2796
2797 /* only execute factor emission for invocation 0 */
2798 /* PRED_SETE_INT __, R0.x, 0 */
2799 memset(&alu, 0, sizeof(alu));
2800 alu.op = ALU_OP2_PRED_SETE_INT;
2801 alu.src[0].chan = 2;
2802 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2803 alu.execute_mask = 1;
2804 alu.update_pred = 1;
2805 alu.last = 1;
2806 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2807
2808 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2809 cf_jump = ctx->bc->cf_last;
2810
2811 treg[0] = r600_get_temp(ctx);
2812 switch (ctx->shader->tcs_prim_mode) {
2813 case PIPE_PRIM_LINES:
2814 stride = 8; /* 2 dwords, 1 vec2 store */
2815 outer_comps = 2;
2816 inner_comps = 0;
2817 break;
2818 case PIPE_PRIM_TRIANGLES:
2819 stride = 16; /* 4 dwords, 1 vec4 store */
2820 outer_comps = 3;
2821 inner_comps = 1;
2822 treg[1] = r600_get_temp(ctx);
2823 break;
2824 case PIPE_PRIM_QUADS:
2825 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2826 outer_comps = 4;
2827 inner_comps = 2;
2828 treg[1] = r600_get_temp(ctx);
2829 treg[2] = r600_get_temp(ctx);
2830 break;
2831 default:
2832 assert(0);
2833 return -1;
2834 }
2835
2836 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2837 /* TF_WRITE takes index in R.x, value in R.y */
2838 for (i = 0; i < ctx->shader->noutput; i++) {
2839 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2840 tessinner_idx = i;
2841 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2842 tessouter_idx = i;
2843 }
2844
2845 if (tessouter_idx == -1)
2846 return -1;
2847
2848 if (tessinner_idx == -1 && inner_comps)
2849 return -1;
2850
2851 if (tessouter_idx != -1) {
2852 r = r600_tess_factor_read(ctx, tessouter_idx);
2853 if (r)
2854 return r;
2855 }
2856
2857 if (tessinner_idx != -1) {
2858 r = r600_tess_factor_read(ctx, tessinner_idx);
2859 if (r)
2860 return r;
2861 }
2862
2863 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2864 /* r.x = relpatchid(r0.y) * tf_stride */
2865
2866 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2867 /* add incoming r0.w to it: t.x = t.x + r0.w */
2868 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2869 temp_reg, 0,
2870 0, 1,
2871 V_SQ_ALU_SRC_LITERAL, stride,
2872 0, 3);
2873 if (r)
2874 return r;
2875
2876 for (i = 0; i < outer_comps + inner_comps; i++) {
2877 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2878 int out_comp = i >= outer_comps ? i - outer_comps : i;
2879
2880 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2881 treg[i / 2], (2 * (i % 2)),
2882 temp_reg, 0,
2883 V_SQ_ALU_SRC_LITERAL, 4 * i);
2884 if (r)
2885 return r;
2886 r = single_alu_op2(ctx, ALU_OP1_MOV,
2887 treg[i / 2], 1 + (2 * (i%2)),
2888 ctx->shader->output[out_idx].gpr, out_comp,
2889 0, 0);
2890 if (r)
2891 return r;
2892 }
2893 for (i = 0; i < outer_comps + inner_comps; i++) {
2894 struct r600_bytecode_gds gds;
2895
2896 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2897 gds.src_gpr = treg[i / 2];
2898 gds.src_sel_x = 2 * (i % 2);
2899 gds.src_sel_y = 1 + (2 * (i % 2));
2900 gds.src_sel_z = 4;
2901 gds.dst_sel_x = 7;
2902 gds.dst_sel_y = 7;
2903 gds.dst_sel_z = 7;
2904 gds.dst_sel_w = 7;
2905 gds.op = FETCH_OP_TF_WRITE;
2906 r = r600_bytecode_add_gds(ctx->bc, &gds);
2907 if (r)
2908 return r;
2909 }
2910
2911 // Patch up jump label
2912 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2913 cf_pop = ctx->bc->cf_last;
2914
2915 cf_jump->cf_addr = cf_pop->id + 2;
2916 cf_jump->pop_count = 1;
2917 cf_pop->cf_addr = cf_pop->id + 2;
2918 cf_pop->pop_count = 1;
2919
2920 return 0;
2921 }
2922
2923 static int r600_shader_from_tgsi(struct r600_context *rctx,
2924 struct r600_pipe_shader *pipeshader,
2925 union r600_shader_key key)
2926 {
2927 struct r600_screen *rscreen = rctx->screen;
2928 struct r600_shader *shader = &pipeshader->shader;
2929 struct tgsi_token *tokens = pipeshader->selector->tokens;
2930 struct pipe_stream_output_info so = pipeshader->selector->so;
2931 struct tgsi_full_immediate *immediate;
2932 struct r600_shader_ctx ctx;
2933 struct r600_bytecode_output output[32];
2934 unsigned output_done, noutput;
2935 unsigned opcode;
2936 int i, j, k, r = 0;
2937 int next_param_base = 0, next_clip_base;
2938 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2939 /* Declarations used by llvm code */
2940 bool use_llvm = false;
2941 bool indirect_gprs;
2942 bool ring_outputs = false;
2943 bool lds_outputs = false;
2944 bool lds_inputs = false;
2945 bool pos_emitted = false;
2946
2947 #ifdef R600_USE_LLVM
2948 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
2949 #endif
2950 ctx.bc = &shader->bc;
2951 ctx.shader = shader;
2952 ctx.native_integers = true;
2953
2954
2955 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2956 rscreen->has_compressed_msaa_texturing);
2957 ctx.tokens = tokens;
2958 tgsi_scan_shader(tokens, &ctx.info);
2959 shader->indirect_files = ctx.info.indirect_files;
2960
2961 shader->uses_doubles = ctx.info.uses_doubles;
2962
2963 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2964 tgsi_parse_init(&ctx.parse, tokens);
2965 ctx.type = ctx.info.processor;
2966 shader->processor_type = ctx.type;
2967 ctx.bc->type = shader->processor_type;
2968
2969 switch (ctx.type) {
2970 case TGSI_PROCESSOR_VERTEX:
2971 shader->vs_as_gs_a = key.vs.as_gs_a;
2972 shader->vs_as_es = key.vs.as_es;
2973 shader->vs_as_ls = key.vs.as_ls;
2974 if (shader->vs_as_es)
2975 ring_outputs = true;
2976 if (shader->vs_as_ls)
2977 lds_outputs = true;
2978 break;
2979 case TGSI_PROCESSOR_GEOMETRY:
2980 ring_outputs = true;
2981 break;
2982 case TGSI_PROCESSOR_TESS_CTRL:
2983 shader->tcs_prim_mode = key.tcs.prim_mode;
2984 lds_outputs = true;
2985 lds_inputs = true;
2986 break;
2987 case TGSI_PROCESSOR_TESS_EVAL:
2988 shader->tes_as_es = key.tes.as_es;
2989 lds_inputs = true;
2990 if (shader->tes_as_es)
2991 ring_outputs = true;
2992 break;
2993 case TGSI_PROCESSOR_FRAGMENT:
2994 shader->two_side = key.ps.color_two_side;
2995 break;
2996 default:
2997 break;
2998 }
2999
3000 if (shader->vs_as_es || shader->tes_as_es) {
3001 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3002 } else {
3003 ctx.gs_for_vs = NULL;
3004 }
3005
3006 ctx.next_ring_offset = 0;
3007 ctx.gs_out_ring_offset = 0;
3008 ctx.gs_next_vertex = 0;
3009 ctx.gs_stream_output_info = &so;
3010
3011 ctx.face_gpr = -1;
3012 ctx.fixed_pt_position_gpr = -1;
3013 ctx.fragcoord_input = -1;
3014 ctx.colors_used = 0;
3015 ctx.clip_vertex_write = 0;
3016
3017 shader->nr_ps_color_exports = 0;
3018 shader->nr_ps_max_color_exports = 0;
3019
3020
3021 /* register allocations */
3022 /* Values [0,127] correspond to GPR[0..127].
3023 * Values [128,159] correspond to constant buffer bank 0
3024 * Values [160,191] correspond to constant buffer bank 1
3025 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3026 * Values [256,287] correspond to constant buffer bank 2 (EG)
3027 * Values [288,319] correspond to constant buffer bank 3 (EG)
3028 * Other special values are shown in the list below.
3029 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3030 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3031 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3032 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3033 * 248 SQ_ALU_SRC_0: special constant 0.0.
3034 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3035 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3036 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3037 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3038 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3039 * 254 SQ_ALU_SRC_PV: previous vector result.
3040 * 255 SQ_ALU_SRC_PS: previous scalar result.
3041 */
3042 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3043 ctx.file_offset[i] = 0;
3044 }
3045
3046 #ifdef R600_USE_LLVM
3047 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
3048 fprintf(stderr, "Warning: R600 LLVM backend does not support "
3049 "indirect adressing. Falling back to TGSI "
3050 "backend.\n");
3051 use_llvm = 0;
3052 }
3053 #endif
3054 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
3055 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3056 if (!use_llvm) {
3057 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3058 }
3059 }
3060 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
3061 if (ctx.bc->chip_class >= EVERGREEN)
3062 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3063 else
3064 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3065 }
3066 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3067 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3068 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3069 }
3070 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
3071 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3072 if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) {
3073 bool add_tesscoord = false, add_tess_inout = false;
3074 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3075 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3076 /* if we have tesscoord save one reg */
3077 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3078 add_tesscoord = true;
3079 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3080 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3081 add_tess_inout = true;
3082 }
3083 if (add_tesscoord || add_tess_inout)
3084 ctx.file_offset[TGSI_FILE_INPUT]++;
3085 if (add_tess_inout)
3086 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3087 }
3088 ctx.use_llvm = use_llvm;
3089
3090 if (use_llvm) {
3091 ctx.file_offset[TGSI_FILE_OUTPUT] =
3092 ctx.file_offset[TGSI_FILE_INPUT];
3093 } else {
3094 ctx.file_offset[TGSI_FILE_OUTPUT] =
3095 ctx.file_offset[TGSI_FILE_INPUT] +
3096 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3097 }
3098 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3099 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3100
3101 /* Outside the GPR range. This will be translated to one of the
3102 * kcache banks later. */
3103 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3104
3105 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3106 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3107 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3108 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3109 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3110
3111 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
3112 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3113 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3114 ctx.temp_reg = ctx.bc->ar_reg + 5;
3115 } else if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) {
3116 ctx.tess_input_info = 0;
3117 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3118 ctx.temp_reg = ctx.bc->ar_reg + 4;
3119 } else if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3120 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3121 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3122 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3123 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3124 ctx.temp_reg = ctx.bc->ar_reg + 7;
3125 } else {
3126 ctx.temp_reg = ctx.bc->ar_reg + 3;
3127 }
3128
3129 shader->max_arrays = 0;
3130 shader->num_arrays = 0;
3131 if (indirect_gprs) {
3132
3133 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3134 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3135 ctx.file_offset[TGSI_FILE_OUTPUT] -
3136 ctx.file_offset[TGSI_FILE_INPUT],
3137 0x0F);
3138 }
3139 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3140 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3141 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3142 ctx.file_offset[TGSI_FILE_OUTPUT],
3143 0x0F);
3144 }
3145 }
3146
3147 ctx.nliterals = 0;
3148 ctx.literals = NULL;
3149
3150 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3151 ctx.info.colors_written == 1;
3152 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3153 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3154
3155 if (shader->vs_as_gs_a)
3156 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3157
3158 if (ctx.type == TGSI_PROCESSOR_TESS_EVAL)
3159 r600_fetch_tess_io_info(&ctx);
3160
3161 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3162 tgsi_parse_token(&ctx.parse);
3163 switch (ctx.parse.FullToken.Token.Type) {
3164 case TGSI_TOKEN_TYPE_IMMEDIATE:
3165 immediate = &ctx.parse.FullToken.FullImmediate;
3166 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3167 if(ctx.literals == NULL) {
3168 r = -ENOMEM;
3169 goto out_err;
3170 }
3171 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3172 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3173 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3174 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3175 ctx.nliterals++;
3176 break;
3177 case TGSI_TOKEN_TYPE_DECLARATION:
3178 r = tgsi_declaration(&ctx);
3179 if (r)
3180 goto out_err;
3181 break;
3182 case TGSI_TOKEN_TYPE_INSTRUCTION:
3183 case TGSI_TOKEN_TYPE_PROPERTY:
3184 break;
3185 default:
3186 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3187 r = -EINVAL;
3188 goto out_err;
3189 }
3190 }
3191
3192 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3193 shader->ring_item_sizes[1] = 0;
3194 shader->ring_item_sizes[2] = 0;
3195 shader->ring_item_sizes[3] = 0;
3196
3197 /* Process two side if needed */
3198 if (shader->two_side && ctx.colors_used) {
3199 int i, count = ctx.shader->ninput;
3200 unsigned next_lds_loc = ctx.shader->nlds;
3201
3202 /* additional inputs will be allocated right after the existing inputs,
3203 * we won't need them after the color selection, so we don't need to
3204 * reserve these gprs for the rest of the shader code and to adjust
3205 * output offsets etc. */
3206 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3207 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3208
3209 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3210 if (ctx.face_gpr == -1) {
3211 i = ctx.shader->ninput++;
3212 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3213 ctx.shader->input[i].spi_sid = 0;
3214 ctx.shader->input[i].gpr = gpr++;
3215 ctx.face_gpr = ctx.shader->input[i].gpr;
3216 }
3217
3218 for (i = 0; i < count; i++) {
3219 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3220 int ni = ctx.shader->ninput++;
3221 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3222 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3223 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3224 ctx.shader->input[ni].gpr = gpr++;
3225 // TGSI to LLVM needs to know the lds position of inputs.
3226 // Non LLVM path computes it later (in process_twoside_color)
3227 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3228 ctx.shader->input[i].back_color_input = ni;
3229 if (ctx.bc->chip_class >= EVERGREEN) {
3230 if ((r = evergreen_interp_input(&ctx, ni)))
3231 return r;
3232 }
3233 }
3234 }
3235 }
3236
3237 /* LLVM backend setup */
3238 #ifdef R600_USE_LLVM
3239 if (use_llvm) {
3240 struct radeon_llvm_context radeon_llvm_ctx;
3241 LLVMModuleRef mod;
3242 bool dump = r600_can_dump_shader(&rscreen->b,
3243 tgsi_get_processor_type(tokens));
3244 boolean use_kill = false;
3245
3246 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
3247 radeon_llvm_ctx.type = ctx.type;
3248 radeon_llvm_ctx.two_side = shader->two_side;
3249 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
3250 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
3251 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
3252 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
3253 radeon_llvm_ctx.color_buffer_count = max_color_exports;
3254 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
3255 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
3256 radeon_llvm_ctx.stream_outputs = &so;
3257 radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
3258 radeon_llvm_ctx.has_compressed_msaa_texturing =
3259 ctx.bc->has_compressed_msaa_texturing;
3260 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
3261 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
3262 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
3263
3264 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill,
3265 dump, &rctx->b.debug)) {
3266 radeon_llvm_dispose(&radeon_llvm_ctx);
3267 use_llvm = 0;
3268 fprintf(stderr, "R600 LLVM backend failed to compile "
3269 "shader. Falling back to TGSI\n");
3270 } else {
3271 ctx.file_offset[TGSI_FILE_OUTPUT] =
3272 ctx.file_offset[TGSI_FILE_INPUT];
3273 }
3274 if (use_kill)
3275 ctx.shader->uses_kill = use_kill;
3276 radeon_llvm_dispose(&radeon_llvm_ctx);
3277 }
3278 #endif
3279 /* End of LLVM backend setup */
3280
3281 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3282 shader->nr_ps_max_color_exports = 8;
3283
3284 if (!use_llvm) {
3285 if (ctx.fragcoord_input >= 0) {
3286 if (ctx.bc->chip_class == CAYMAN) {
3287 for (j = 0 ; j < 4; j++) {
3288 struct r600_bytecode_alu alu;
3289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3290 alu.op = ALU_OP1_RECIP_IEEE;
3291 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3292 alu.src[0].chan = 3;
3293
3294 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3295 alu.dst.chan = j;
3296 alu.dst.write = (j == 3);
3297 alu.last = 1;
3298 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3299 return r;
3300 }
3301 } else {
3302 struct r600_bytecode_alu alu;
3303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3304 alu.op = ALU_OP1_RECIP_IEEE;
3305 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3306 alu.src[0].chan = 3;
3307
3308 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3309 alu.dst.chan = 3;
3310 alu.dst.write = 1;
3311 alu.last = 1;
3312 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3313 return r;
3314 }
3315 }
3316
3317 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3318 struct r600_bytecode_alu alu;
3319 int r;
3320
3321 /* GS thread with no output workaround - emit a cut at start of GS */
3322 if (ctx.bc->chip_class == R600)
3323 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3324
3325 for (j = 0; j < 4; j++) {
3326 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3327 alu.op = ALU_OP1_MOV;
3328 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3329 alu.src[0].value = 0;
3330 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3331 alu.dst.write = 1;
3332 alu.last = 1;
3333 r = r600_bytecode_add_alu(ctx.bc, &alu);
3334 if (r)
3335 return r;
3336 }
3337 }
3338
3339 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
3340 r600_fetch_tess_io_info(&ctx);
3341
3342 if (shader->two_side && ctx.colors_used) {
3343 if ((r = process_twoside_color_inputs(&ctx)))
3344 return r;
3345 }
3346
3347 tgsi_parse_init(&ctx.parse, tokens);
3348 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3349 tgsi_parse_token(&ctx.parse);
3350 switch (ctx.parse.FullToken.Token.Type) {
3351 case TGSI_TOKEN_TYPE_INSTRUCTION:
3352 r = tgsi_is_supported(&ctx);
3353 if (r)
3354 goto out_err;
3355 ctx.max_driver_temp_used = 0;
3356 /* reserve first tmp for everyone */
3357 r600_get_temp(&ctx);
3358
3359 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3360 if ((r = tgsi_split_constant(&ctx)))
3361 goto out_err;
3362 if ((r = tgsi_split_literal_constant(&ctx)))
3363 goto out_err;
3364 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3365 if ((r = tgsi_split_gs_inputs(&ctx)))
3366 goto out_err;
3367 } else if (lds_inputs) {
3368 if ((r = tgsi_split_lds_inputs(&ctx)))
3369 goto out_err;
3370 }
3371 if (ctx.bc->chip_class == CAYMAN)
3372 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3373 else if (ctx.bc->chip_class >= EVERGREEN)
3374 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3375 else
3376 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3377 r = ctx.inst_info->process(&ctx);
3378 if (r)
3379 goto out_err;
3380
3381 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
3382 r = r600_store_tcs_output(&ctx);
3383 if (r)
3384 goto out_err;
3385 }
3386 break;
3387 default:
3388 break;
3389 }
3390 }
3391 }
3392
3393 /* Reset the temporary register counter. */
3394 ctx.max_driver_temp_used = 0;
3395
3396 noutput = shader->noutput;
3397
3398 if (!ring_outputs && ctx.clip_vertex_write) {
3399 unsigned clipdist_temp[2];
3400
3401 clipdist_temp[0] = r600_get_temp(&ctx);
3402 clipdist_temp[1] = r600_get_temp(&ctx);
3403
3404 /* need to convert a clipvertex write into clipdistance writes and not export
3405 the clip vertex anymore */
3406
3407 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3408 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3409 shader->output[noutput].gpr = clipdist_temp[0];
3410 noutput++;
3411 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3412 shader->output[noutput].gpr = clipdist_temp[1];
3413 noutput++;
3414
3415 /* reset spi_sid for clipvertex output to avoid confusing spi */
3416 shader->output[ctx.cv_output].spi_sid = 0;
3417
3418 shader->clip_dist_write = 0xFF;
3419
3420 for (i = 0; i < 8; i++) {
3421 int oreg = i >> 2;
3422 int ochan = i & 3;
3423
3424 for (j = 0; j < 4; j++) {
3425 struct r600_bytecode_alu alu;
3426 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3427 alu.op = ALU_OP2_DOT4;
3428 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3429 alu.src[0].chan = j;
3430
3431 alu.src[1].sel = 512 + i;
3432 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3433 alu.src[1].chan = j;
3434
3435 alu.dst.sel = clipdist_temp[oreg];
3436 alu.dst.chan = j;
3437 alu.dst.write = (j == ochan);
3438 if (j == 3)
3439 alu.last = 1;
3440 if (!use_llvm)
3441 r = r600_bytecode_add_alu(ctx.bc, &alu);
3442 if (r)
3443 return r;
3444 }
3445 }
3446 }
3447
3448 /* Add stream outputs. */
3449 if (!use_llvm && so.num_outputs) {
3450 bool emit = false;
3451 if (!lds_outputs && !ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX)
3452 emit = true;
3453 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_TESS_EVAL)
3454 emit = true;
3455 if (emit)
3456 emit_streamout(&ctx, &so, -1, NULL);
3457 }
3458 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3459 convert_edgeflag_to_int(&ctx);
3460
3461 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
3462 r600_emit_tess_factor(&ctx);
3463
3464 if (lds_outputs) {
3465 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
3466 if (ctx.shader->noutput)
3467 emit_lds_vs_writes(&ctx);
3468 }
3469 } else if (ring_outputs) {
3470 if (shader->vs_as_es || shader->tes_as_es) {
3471 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3472 ctx.gs_export_gpr_tregs[1] = -1;
3473 ctx.gs_export_gpr_tregs[2] = -1;
3474 ctx.gs_export_gpr_tregs[3] = -1;
3475
3476 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3477 }
3478 } else {
3479 /* Export output */
3480 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3481
3482 for (i = 0, j = 0; i < noutput; i++, j++) {
3483 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3484 output[j].gpr = shader->output[i].gpr;
3485 output[j].elem_size = 3;
3486 output[j].swizzle_x = 0;
3487 output[j].swizzle_y = 1;
3488 output[j].swizzle_z = 2;
3489 output[j].swizzle_w = 3;
3490 output[j].burst_count = 1;
3491 output[j].type = -1;
3492 output[j].op = CF_OP_EXPORT;
3493 switch (ctx.type) {
3494 case TGSI_PROCESSOR_VERTEX:
3495 case TGSI_PROCESSOR_TESS_EVAL:
3496 switch (shader->output[i].name) {
3497 case TGSI_SEMANTIC_POSITION:
3498 output[j].array_base = 60;
3499 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3500 pos_emitted = true;
3501 break;
3502
3503 case TGSI_SEMANTIC_PSIZE:
3504 output[j].array_base = 61;
3505 output[j].swizzle_y = 7;
3506 output[j].swizzle_z = 7;
3507 output[j].swizzle_w = 7;
3508 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3509 pos_emitted = true;
3510 break;
3511 case TGSI_SEMANTIC_EDGEFLAG:
3512 output[j].array_base = 61;
3513 output[j].swizzle_x = 7;
3514 output[j].swizzle_y = 0;
3515 output[j].swizzle_z = 7;
3516 output[j].swizzle_w = 7;
3517 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3518 pos_emitted = true;
3519 break;
3520 case TGSI_SEMANTIC_LAYER:
3521 /* spi_sid is 0 for outputs that are
3522 * not consumed by PS */
3523 if (shader->output[i].spi_sid) {
3524 output[j].array_base = next_param_base++;
3525 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3526 j++;
3527 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3528 }
3529 output[j].array_base = 61;
3530 output[j].swizzle_x = 7;
3531 output[j].swizzle_y = 7;
3532 output[j].swizzle_z = 0;
3533 output[j].swizzle_w = 7;
3534 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3535 pos_emitted = true;
3536 break;
3537 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3538 /* spi_sid is 0 for outputs that are
3539 * not consumed by PS */
3540 if (shader->output[i].spi_sid) {
3541 output[j].array_base = next_param_base++;
3542 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3543 j++;
3544 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3545 }
3546 output[j].array_base = 61;
3547 output[j].swizzle_x = 7;
3548 output[j].swizzle_y = 7;
3549 output[j].swizzle_z = 7;
3550 output[j].swizzle_w = 0;
3551 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3552 pos_emitted = true;
3553 break;
3554 case TGSI_SEMANTIC_CLIPVERTEX:
3555 j--;
3556 break;
3557 case TGSI_SEMANTIC_CLIPDIST:
3558 output[j].array_base = next_clip_base++;
3559 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3560 pos_emitted = true;
3561 /* spi_sid is 0 for clipdistance outputs that were generated
3562 * for clipvertex - we don't need to pass them to PS */
3563 if (shader->output[i].spi_sid) {
3564 j++;
3565 /* duplicate it as PARAM to pass to the pixel shader */
3566 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3567 output[j].array_base = next_param_base++;
3568 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3569 }
3570 break;
3571 case TGSI_SEMANTIC_FOG:
3572 output[j].swizzle_y = 4; /* 0 */
3573 output[j].swizzle_z = 4; /* 0 */
3574 output[j].swizzle_w = 5; /* 1 */
3575 break;
3576 case TGSI_SEMANTIC_PRIMID:
3577 output[j].swizzle_x = 2;
3578 output[j].swizzle_y = 4; /* 0 */
3579 output[j].swizzle_z = 4; /* 0 */
3580 output[j].swizzle_w = 4; /* 0 */
3581 break;
3582 }
3583
3584 break;
3585 case TGSI_PROCESSOR_FRAGMENT:
3586 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3587 /* never export more colors than the number of CBs */
3588 if (shader->output[i].sid >= max_color_exports) {
3589 /* skip export */
3590 j--;
3591 continue;
3592 }
3593 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3594 output[j].array_base = shader->output[i].sid;
3595 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3596 shader->nr_ps_color_exports++;
3597 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3598 for (k = 1; k < max_color_exports; k++) {
3599 j++;
3600 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3601 output[j].gpr = shader->output[i].gpr;
3602 output[j].elem_size = 3;
3603 output[j].swizzle_x = 0;
3604 output[j].swizzle_y = 1;
3605 output[j].swizzle_z = 2;
3606 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3607 output[j].burst_count = 1;
3608 output[j].array_base = k;
3609 output[j].op = CF_OP_EXPORT;
3610 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3611 shader->nr_ps_color_exports++;
3612 }
3613 }
3614 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3615 output[j].array_base = 61;
3616 output[j].swizzle_x = 2;
3617 output[j].swizzle_y = 7;
3618 output[j].swizzle_z = output[j].swizzle_w = 7;
3619 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3620 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3621 output[j].array_base = 61;
3622 output[j].swizzle_x = 7;
3623 output[j].swizzle_y = 1;
3624 output[j].swizzle_z = output[j].swizzle_w = 7;
3625 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3626 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3627 output[j].array_base = 61;
3628 output[j].swizzle_x = 7;
3629 output[j].swizzle_y = 7;
3630 output[j].swizzle_z = 0;
3631 output[j].swizzle_w = 7;
3632 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3633 } else {
3634 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3635 r = -EINVAL;
3636 goto out_err;
3637 }
3638 break;
3639 case TGSI_PROCESSOR_TESS_CTRL:
3640 break;
3641 default:
3642 R600_ERR("unsupported processor type %d\n", ctx.type);
3643 r = -EINVAL;
3644 goto out_err;
3645 }
3646
3647 if (output[j].type==-1) {
3648 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3649 output[j].array_base = next_param_base++;
3650 }
3651 }
3652
3653 /* add fake position export */
3654 if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && pos_emitted == false) {
3655 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3656 output[j].gpr = 0;
3657 output[j].elem_size = 3;
3658 output[j].swizzle_x = 7;
3659 output[j].swizzle_y = 7;
3660 output[j].swizzle_z = 7;
3661 output[j].swizzle_w = 7;
3662 output[j].burst_count = 1;
3663 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3664 output[j].array_base = 60;
3665 output[j].op = CF_OP_EXPORT;
3666 j++;
3667 }
3668
3669 /* add fake param output for vertex shader if no param is exported */
3670 if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && next_param_base == 0) {
3671 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3672 output[j].gpr = 0;
3673 output[j].elem_size = 3;
3674 output[j].swizzle_x = 7;
3675 output[j].swizzle_y = 7;
3676 output[j].swizzle_z = 7;
3677 output[j].swizzle_w = 7;
3678 output[j].burst_count = 1;
3679 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3680 output[j].array_base = 0;
3681 output[j].op = CF_OP_EXPORT;
3682 j++;
3683 }
3684
3685 /* add fake pixel export */
3686 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
3687 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3688 output[j].gpr = 0;
3689 output[j].elem_size = 3;
3690 output[j].swizzle_x = 7;
3691 output[j].swizzle_y = 7;
3692 output[j].swizzle_z = 7;
3693 output[j].swizzle_w = 7;
3694 output[j].burst_count = 1;
3695 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3696 output[j].array_base = 0;
3697 output[j].op = CF_OP_EXPORT;
3698 j++;
3699 shader->nr_ps_color_exports++;
3700 }
3701
3702 noutput = j;
3703
3704 /* set export done on last export of each type */
3705 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3706 if (!(output_done & (1 << output[i].type))) {
3707 output_done |= (1 << output[i].type);
3708 output[i].op = CF_OP_EXPORT_DONE;
3709 }
3710 }
3711 /* add output to bytecode */
3712 if (!use_llvm) {
3713 for (i = 0; i < noutput; i++) {
3714 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3715 if (r)
3716 goto out_err;
3717 }
3718 }
3719 }
3720
3721 /* add program end */
3722 if (!use_llvm) {
3723 if (ctx.bc->chip_class == CAYMAN)
3724 cm_bytecode_add_cf_end(ctx.bc);
3725 else {
3726 const struct cf_op_info *last = NULL;
3727
3728 if (ctx.bc->cf_last)
3729 last = r600_isa_cf(ctx.bc->cf_last->op);
3730
3731 /* alu clause instructions don't have EOP bit, so add NOP */
3732 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3733 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3734
3735 ctx.bc->cf_last->end_of_program = 1;
3736 }
3737 }
3738
3739 /* check GPR limit - we have 124 = 128 - 4
3740 * (4 are reserved as alu clause temporary registers) */
3741 if (ctx.bc->ngpr > 124) {
3742 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3743 r = -ENOMEM;
3744 goto out_err;
3745 }
3746
3747 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3748 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3749 return r;
3750 }
3751
3752 free(ctx.literals);
3753 tgsi_parse_free(&ctx.parse);
3754 return 0;
3755 out_err:
3756 free(ctx.literals);
3757 tgsi_parse_free(&ctx.parse);
3758 return r;
3759 }
3760
3761 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3762 {
3763 const unsigned tgsi_opcode =
3764 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3765 R600_ERR("%s tgsi opcode unsupported\n",
3766 tgsi_get_opcode_name(tgsi_opcode));
3767 return -EINVAL;
3768 }
3769
3770 static int tgsi_end(struct r600_shader_ctx *ctx)
3771 {
3772 return 0;
3773 }
3774
3775 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3776 const struct r600_shader_src *shader_src,
3777 unsigned chan)
3778 {
3779 bc_src->sel = shader_src->sel;
3780 bc_src->chan = shader_src->swizzle[chan];
3781 bc_src->neg = shader_src->neg;
3782 bc_src->abs = shader_src->abs;
3783 bc_src->rel = shader_src->rel;
3784 bc_src->value = shader_src->value[bc_src->chan];
3785 bc_src->kc_bank = shader_src->kc_bank;
3786 bc_src->kc_rel = shader_src->kc_rel;
3787 }
3788
3789 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3790 {
3791 bc_src->abs = 1;
3792 bc_src->neg = 0;
3793 }
3794
3795 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3796 {
3797 bc_src->neg = !bc_src->neg;
3798 }
3799
3800 static void tgsi_dst(struct r600_shader_ctx *ctx,
3801 const struct tgsi_full_dst_register *tgsi_dst,
3802 unsigned swizzle,
3803 struct r600_bytecode_alu_dst *r600_dst)
3804 {
3805 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3806
3807 r600_dst->sel = tgsi_dst->Register.Index;
3808 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3809 r600_dst->chan = swizzle;
3810 r600_dst->write = 1;
3811 if (inst->Instruction.Saturate) {
3812 r600_dst->clamp = 1;
3813 }
3814 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
3815 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3816 return;
3817 }
3818 }
3819 if (tgsi_dst->Register.Indirect)
3820 r600_dst->rel = V_SQ_REL_RELATIVE;
3821
3822 }
3823
3824 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3825 {
3826 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3827 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3828 struct r600_bytecode_alu alu;
3829 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3830 int use_tmp = 0;
3831
3832 if (singledest) {
3833 switch (write_mask) {
3834 case 0x1:
3835 write_mask = 0x3;
3836 break;
3837 case 0x2:
3838 use_tmp = 1;
3839 write_mask = 0x3;
3840 break;
3841 case 0x4:
3842 write_mask = 0xc;
3843 break;
3844 case 0x8:
3845 write_mask = 0xc;
3846 use_tmp = 3;
3847 break;
3848 }
3849 }
3850
3851 lasti = tgsi_last_instruction(write_mask);
3852 for (i = 0; i <= lasti; i++) {
3853
3854 if (!(write_mask & (1 << i)))
3855 continue;
3856
3857 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3858
3859 if (singledest) {
3860 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3861 if (use_tmp) {
3862 alu.dst.sel = ctx->temp_reg;
3863 alu.dst.chan = i;
3864 alu.dst.write = 1;
3865 }
3866 if (i == 1 || i == 3)
3867 alu.dst.write = 0;
3868 } else
3869 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3870
3871 alu.op = ctx->inst_info->op;
3872 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3873 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3874 } else if (!swap) {
3875 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3876 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3877 }
3878 } else {
3879 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3880 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3881 }
3882
3883 /* handle some special cases */
3884 if (i == 1 || i == 3) {
3885 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3886 case TGSI_OPCODE_SUB:
3887 r600_bytecode_src_toggle_neg(&alu.src[1]);
3888 break;
3889 case TGSI_OPCODE_DABS:
3890 r600_bytecode_src_set_abs(&alu.src[0]);
3891 break;
3892 default:
3893 break;
3894 }
3895 }
3896 if (i == lasti) {
3897 alu.last = 1;
3898 }
3899 r = r600_bytecode_add_alu(ctx->bc, &alu);
3900 if (r)
3901 return r;
3902 }
3903
3904 if (use_tmp) {
3905 write_mask = inst->Dst[0].Register.WriteMask;
3906
3907 /* move result from temp to dst */
3908 for (i = 0; i <= lasti; i++) {
3909 if (!(write_mask & (1 << i)))
3910 continue;
3911
3912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3913 alu.op = ALU_OP1_MOV;
3914 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3915 alu.src[0].sel = ctx->temp_reg;
3916 alu.src[0].chan = use_tmp - 1;
3917 alu.last = (i == lasti);
3918
3919 r = r600_bytecode_add_alu(ctx->bc, &alu);
3920 if (r)
3921 return r;
3922 }
3923 }
3924 return 0;
3925 }
3926
3927 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3928 {
3929 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3930 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3931 /* confirm writemasking */
3932 if ((write_mask & 0x3) != 0x3 &&
3933 (write_mask & 0xc) != 0xc) {
3934 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3935 return -1;
3936 }
3937 return tgsi_op2_64_params(ctx, false, false);
3938 }
3939
3940 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
3941 {
3942 return tgsi_op2_64_params(ctx, true, false);
3943 }
3944
3945 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
3946 {
3947 return tgsi_op2_64_params(ctx, true, true);
3948 }
3949
3950 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3951 {
3952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3953 struct r600_bytecode_alu alu;
3954 int i, j, r;
3955 int lasti = 3;
3956 int tmp = r600_get_temp(ctx);
3957
3958 for (i = 0; i < lasti + 1; i++) {
3959
3960 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3961 alu.op = ctx->inst_info->op;
3962 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3963 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3964 }
3965
3966 if (inst->Dst[0].Register.WriteMask & (1 << i))
3967 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3968 else
3969 alu.dst.sel = tmp;
3970
3971 alu.dst.chan = i;
3972 alu.is_op3 = 1;
3973 if (i == lasti) {
3974 alu.last = 1;
3975 }
3976 r = r600_bytecode_add_alu(ctx->bc, &alu);
3977 if (r)
3978 return r;
3979 }
3980 return 0;
3981 }
3982
3983 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3984 {
3985 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3986 struct r600_bytecode_alu alu;
3987 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3988 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3989 /* use temp register if trans_only and more than one dst component */
3990 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3991
3992 for (i = 0; i <= lasti; i++) {
3993 if (!(write_mask & (1 << i)))
3994 continue;
3995
3996 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3997 if (use_tmp) {
3998 alu.dst.sel = ctx->temp_reg;
3999 alu.dst.chan = i;
4000 alu.dst.write = 1;
4001 } else
4002 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4003
4004 alu.op = ctx->inst_info->op;
4005 if (!swap) {
4006 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4007 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4008 }
4009 } else {
4010 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4011 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4012 }
4013 /* handle some special cases */
4014 switch (inst->Instruction.Opcode) {
4015 case TGSI_OPCODE_SUB:
4016 r600_bytecode_src_toggle_neg(&alu.src[1]);
4017 break;
4018 case TGSI_OPCODE_ABS:
4019 r600_bytecode_src_set_abs(&alu.src[0]);
4020 break;
4021 default:
4022 break;
4023 }
4024 if (i == lasti || trans_only) {
4025 alu.last = 1;
4026 }
4027 r = r600_bytecode_add_alu(ctx->bc, &alu);
4028 if (r)
4029 return r;
4030 }
4031
4032 if (use_tmp) {
4033 /* move result from temp to dst */
4034 for (i = 0; i <= lasti; i++) {
4035 if (!(write_mask & (1 << i)))
4036 continue;
4037
4038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4039 alu.op = ALU_OP1_MOV;
4040 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4041 alu.src[0].sel = ctx->temp_reg;
4042 alu.src[0].chan = i;
4043 alu.last = (i == lasti);
4044
4045 r = r600_bytecode_add_alu(ctx->bc, &alu);
4046 if (r)
4047 return r;
4048 }
4049 }
4050 return 0;
4051 }
4052
4053 static int tgsi_op2(struct r600_shader_ctx *ctx)
4054 {
4055 return tgsi_op2_s(ctx, 0, 0);
4056 }
4057
4058 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4059 {
4060 return tgsi_op2_s(ctx, 1, 0);
4061 }
4062
4063 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4064 {
4065 return tgsi_op2_s(ctx, 0, 1);
4066 }
4067
4068 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4069 {
4070 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4071 struct r600_bytecode_alu alu;
4072 int i, r;
4073 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4074
4075 for (i = 0; i < lasti + 1; i++) {
4076
4077 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4078 continue;
4079 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4080 alu.op = ctx->inst_info->op;
4081
4082 alu.src[0].sel = V_SQ_ALU_SRC_0;
4083
4084 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4085
4086 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4087
4088 if (i == lasti) {
4089 alu.last = 1;
4090 }
4091 r = r600_bytecode_add_alu(ctx->bc, &alu);
4092 if (r)
4093 return r;
4094 }
4095 return 0;
4096
4097 }
4098
4099 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4100 {
4101 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4102 struct r600_bytecode_alu alu;
4103 int i, r;
4104 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4105
4106 for (i = 0; i < lasti + 1; i++) {
4107
4108 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4109 continue;
4110 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4111 alu.op = ALU_OP1_MOV;
4112
4113 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4114
4115 if (i == 1 || i == 3)
4116 r600_bytecode_src_toggle_neg(&alu.src[0]);
4117 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4118
4119 if (i == lasti) {
4120 alu.last = 1;
4121 }
4122 r = r600_bytecode_add_alu(ctx->bc, &alu);
4123 if (r)
4124 return r;
4125 }
4126 return 0;
4127
4128 }
4129
4130 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4131 {
4132 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4133 struct r600_bytecode_alu alu;
4134 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4135 int i, j, r;
4136 int firsti = write_mask == 0xc ? 2 : 0;
4137
4138 for (i = 0; i <= 3; i++) {
4139 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4140 alu.op = ctx->inst_info->op;
4141
4142 alu.dst.sel = ctx->temp_reg;
4143 alu.dst.chan = i;
4144 alu.dst.write = 1;
4145 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4146 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4147 }
4148
4149 if (i == 3)
4150 alu.last = 1;
4151
4152 r = r600_bytecode_add_alu(ctx->bc, &alu);
4153 if (r)
4154 return r;
4155 }
4156
4157 /* MOV first two channels to writemask dst0 */
4158 for (i = 0; i <= 1; i++) {
4159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4160 alu.op = ALU_OP1_MOV;
4161 alu.src[0].chan = i + 2;
4162 alu.src[0].sel = ctx->temp_reg;
4163
4164 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
4165 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
4166 alu.last = 1;
4167 r = r600_bytecode_add_alu(ctx->bc, &alu);
4168 if (r)
4169 return r;
4170 }
4171
4172 for (i = 0; i <= 3; i++) {
4173 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4174 /* MOV third channels to writemask dst1 */
4175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4176 alu.op = ALU_OP1_MOV;
4177 alu.src[0].chan = 1;
4178 alu.src[0].sel = ctx->temp_reg;
4179
4180 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4181 alu.last = 1;
4182 r = r600_bytecode_add_alu(ctx->bc, &alu);
4183 if (r)
4184 return r;
4185 break;
4186 }
4187 }
4188 return 0;
4189 }
4190
4191
4192 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4193 {
4194 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4195 struct r600_bytecode_alu alu;
4196 int i, r;
4197 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4198
4199 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4200 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4201
4202 for (i = 0; i <= (lasti+1)/2; i++) {
4203 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4204 alu.op = ctx->inst_info->op;
4205
4206 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4207 alu.dst.sel = ctx->temp_reg;
4208 alu.dst.chan = i;
4209 alu.dst.write = 1;
4210 alu.last = 1;
4211
4212 r = r600_bytecode_add_alu(ctx->bc, &alu);
4213 if (r)
4214 return r;
4215 }
4216
4217 for (i = 0; i <= lasti; i++) {
4218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4219 alu.op = ALU_OP1_FLT32_TO_FLT64;
4220
4221 alu.src[0].chan = i/2;
4222 if (i%2 == 0)
4223 alu.src[0].sel = ctx->temp_reg;
4224 else {
4225 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4226 alu.src[0].value = 0x0;
4227 }
4228 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4229 alu.last = i == lasti;
4230
4231 r = r600_bytecode_add_alu(ctx->bc, &alu);
4232 if (r)
4233 return r;
4234 }
4235
4236 return 0;
4237 }
4238
4239 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4240 {
4241 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4242 struct r600_bytecode_alu alu;
4243 int i, r;
4244 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4245
4246 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4247 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4248
4249 for (i = 0; i <= lasti; i++) {
4250 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4251 alu.op = ALU_OP1_FLT64_TO_FLT32;
4252
4253 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4254 alu.dst.chan = i;
4255 alu.dst.sel = ctx->temp_reg;
4256 alu.dst.write = i%2 == 0;
4257 alu.last = i == lasti;
4258
4259 r = r600_bytecode_add_alu(ctx->bc, &alu);
4260 if (r)
4261 return r;
4262 }
4263
4264 for (i = 0; i <= (lasti+1)/2; i++) {
4265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4266 alu.op = ctx->inst_info->op;
4267
4268 alu.src[0].chan = i*2;
4269 alu.src[0].sel = ctx->temp_reg;
4270 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4271 alu.last = 1;
4272
4273 r = r600_bytecode_add_alu(ctx->bc, &alu);
4274 if (r)
4275 return r;
4276 }
4277
4278 return 0;
4279 }
4280
4281 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4282 {
4283 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4284 int i, r;
4285 struct r600_bytecode_alu alu;
4286 int last_slot = 3;
4287 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4288 int t1 = ctx->temp_reg;
4289
4290 /* these have to write the result to X/Y by the looks of it */
4291 for (i = 0 ; i < last_slot; i++) {
4292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4293 alu.op = ctx->inst_info->op;
4294
4295 /* should only be one src regs */
4296 assert (inst->Instruction.NumSrcRegs == 1);
4297
4298 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4299 r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
4300
4301 /* RSQ should take the absolute value of src */
4302 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4303 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT) {
4304 r600_bytecode_src_set_abs(&alu.src[1]);
4305 }
4306 alu.dst.sel = t1;
4307 alu.dst.chan = i;
4308 alu.dst.write = (i == 0 || i == 1);
4309
4310 if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
4311 alu.last = 1;
4312 r = r600_bytecode_add_alu(ctx->bc, &alu);
4313 if (r)
4314 return r;
4315 }
4316
4317 for (i = 0 ; i <= lasti; i++) {
4318 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4319 continue;
4320 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4321 alu.op = ALU_OP1_MOV;
4322 alu.src[0].sel = t1;
4323 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4324 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4325 alu.dst.write = 1;
4326 if (i == lasti)
4327 alu.last = 1;
4328 r = r600_bytecode_add_alu(ctx->bc, &alu);
4329 if (r)
4330 return r;
4331 }
4332 return 0;
4333 }
4334
4335 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4336 {
4337 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4338 int i, j, r;
4339 struct r600_bytecode_alu alu;
4340 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4341
4342 for (i = 0 ; i < last_slot; i++) {
4343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4344 alu.op = ctx->inst_info->op;
4345 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4346 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4347
4348 /* RSQ should take the absolute value of src */
4349 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4350 r600_bytecode_src_set_abs(&alu.src[j]);
4351 }
4352 }
4353 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4354 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4355
4356 if (i == last_slot - 1)
4357 alu.last = 1;
4358 r = r600_bytecode_add_alu(ctx->bc, &alu);
4359 if (r)
4360 return r;
4361 }
4362 return 0;
4363 }
4364
4365 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4366 {
4367 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4368 int i, j, k, r;
4369 struct r600_bytecode_alu alu;
4370 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4371 int t1 = ctx->temp_reg;
4372
4373 for (k = 0; k <= lasti; k++) {
4374 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4375 continue;
4376
4377 for (i = 0 ; i < 4; i++) {
4378 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4379 alu.op = ctx->inst_info->op;
4380 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4381 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4382 }
4383 alu.dst.sel = t1;
4384 alu.dst.chan = i;
4385 alu.dst.write = (i == k);
4386 if (i == 3)
4387 alu.last = 1;
4388 r = r600_bytecode_add_alu(ctx->bc, &alu);
4389 if (r)
4390 return r;
4391 }
4392 }
4393
4394 for (i = 0 ; i <= lasti; i++) {
4395 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4396 continue;
4397 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4398 alu.op = ALU_OP1_MOV;
4399 alu.src[0].sel = t1;
4400 alu.src[0].chan = i;
4401 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4402 alu.dst.write = 1;
4403 if (i == lasti)
4404 alu.last = 1;
4405 r = r600_bytecode_add_alu(ctx->bc, &alu);
4406 if (r)
4407 return r;
4408 }
4409
4410 return 0;
4411 }
4412
4413
4414 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4415 {
4416 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4417 int i, j, k, r;
4418 struct r600_bytecode_alu alu;
4419 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4420 int t1 = ctx->temp_reg;
4421
4422 for (k = 0; k < 2; k++) {
4423 if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2))))
4424 continue;
4425
4426 for (i = 0; i < 4; i++) {
4427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4428 alu.op = ctx->inst_info->op;
4429 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4430 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));;
4431 }
4432 alu.dst.sel = t1;
4433 alu.dst.chan = i;
4434 alu.dst.write = 1;
4435 if (i == 3)
4436 alu.last = 1;
4437 r = r600_bytecode_add_alu(ctx->bc, &alu);
4438 if (r)
4439 return r;
4440 }
4441 }
4442
4443 for (i = 0; i <= lasti; i++) {
4444 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4445 continue;
4446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4447 alu.op = ALU_OP1_MOV;
4448 alu.src[0].sel = t1;
4449 alu.src[0].chan = i;
4450 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4451 alu.dst.write = 1;
4452 if (i == lasti)
4453 alu.last = 1;
4454 r = r600_bytecode_add_alu(ctx->bc, &alu);
4455 if (r)
4456 return r;
4457 }
4458
4459 return 0;
4460 }
4461
4462 /*
4463 * r600 - trunc to -PI..PI range
4464 * r700 - normalize by dividing by 2PI
4465 * see fdo bug 27901
4466 */
4467 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4468 {
4469 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
4470 static float double_pi = 3.1415926535 * 2;
4471 static float neg_pi = -3.1415926535;
4472
4473 int r;
4474 struct r600_bytecode_alu alu;
4475
4476 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4477 alu.op = ALU_OP3_MULADD;
4478 alu.is_op3 = 1;
4479
4480 alu.dst.chan = 0;
4481 alu.dst.sel = ctx->temp_reg;
4482 alu.dst.write = 1;
4483
4484 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4485
4486 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4487 alu.src[1].chan = 0;
4488 alu.src[1].value = *(uint32_t *)&half_inv_pi;
4489 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4490 alu.src[2].chan = 0;
4491 alu.last = 1;
4492 r = r600_bytecode_add_alu(ctx->bc, &alu);
4493 if (r)
4494 return r;
4495
4496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4497 alu.op = ALU_OP1_FRACT;
4498
4499 alu.dst.chan = 0;
4500 alu.dst.sel = ctx->temp_reg;
4501 alu.dst.write = 1;
4502
4503 alu.src[0].sel = ctx->temp_reg;
4504 alu.src[0].chan = 0;
4505 alu.last = 1;
4506 r = r600_bytecode_add_alu(ctx->bc, &alu);
4507 if (r)
4508 return r;
4509
4510 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4511 alu.op = ALU_OP3_MULADD;
4512 alu.is_op3 = 1;
4513
4514 alu.dst.chan = 0;
4515 alu.dst.sel = ctx->temp_reg;
4516 alu.dst.write = 1;
4517
4518 alu.src[0].sel = ctx->temp_reg;
4519 alu.src[0].chan = 0;
4520
4521 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4522 alu.src[1].chan = 0;
4523 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4524 alu.src[2].chan = 0;
4525
4526 if (ctx->bc->chip_class == R600) {
4527 alu.src[1].value = *(uint32_t *)&double_pi;
4528 alu.src[2].value = *(uint32_t *)&neg_pi;
4529 } else {
4530 alu.src[1].sel = V_SQ_ALU_SRC_1;
4531 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4532 alu.src[2].neg = 1;
4533 }
4534
4535 alu.last = 1;
4536 r = r600_bytecode_add_alu(ctx->bc, &alu);
4537 if (r)
4538 return r;
4539 return 0;
4540 }
4541
4542 static int cayman_trig(struct r600_shader_ctx *ctx)
4543 {
4544 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4545 struct r600_bytecode_alu alu;
4546 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4547 int i, r;
4548
4549 r = tgsi_setup_trig(ctx);
4550 if (r)
4551 return r;
4552
4553
4554 for (i = 0; i < last_slot; i++) {
4555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4556 alu.op = ctx->inst_info->op;
4557 alu.dst.chan = i;
4558
4559 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4560 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4561
4562 alu.src[0].sel = ctx->temp_reg;
4563 alu.src[0].chan = 0;
4564 if (i == last_slot - 1)
4565 alu.last = 1;
4566 r = r600_bytecode_add_alu(ctx->bc, &alu);
4567 if (r)
4568 return r;
4569 }
4570 return 0;
4571 }
4572
4573 static int tgsi_trig(struct r600_shader_ctx *ctx)
4574 {
4575 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4576 struct r600_bytecode_alu alu;
4577 int i, r;
4578 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4579
4580 r = tgsi_setup_trig(ctx);
4581 if (r)
4582 return r;
4583
4584 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4585 alu.op = ctx->inst_info->op;
4586 alu.dst.chan = 0;
4587 alu.dst.sel = ctx->temp_reg;
4588 alu.dst.write = 1;
4589
4590 alu.src[0].sel = ctx->temp_reg;
4591 alu.src[0].chan = 0;
4592 alu.last = 1;
4593 r = r600_bytecode_add_alu(ctx->bc, &alu);
4594 if (r)
4595 return r;
4596
4597 /* replicate result */
4598 for (i = 0; i < lasti + 1; i++) {
4599 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4600 continue;
4601
4602 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4603 alu.op = ALU_OP1_MOV;
4604
4605 alu.src[0].sel = ctx->temp_reg;
4606 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4607 if (i == lasti)
4608 alu.last = 1;
4609 r = r600_bytecode_add_alu(ctx->bc, &alu);
4610 if (r)
4611 return r;
4612 }
4613 return 0;
4614 }
4615
4616 static int tgsi_scs(struct r600_shader_ctx *ctx)
4617 {
4618 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4619 struct r600_bytecode_alu alu;
4620 int i, r;
4621
4622 /* We'll only need the trig stuff if we are going to write to the
4623 * X or Y components of the destination vector.
4624 */
4625 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
4626 r = tgsi_setup_trig(ctx);
4627 if (r)
4628 return r;
4629 }
4630
4631 /* dst.x = COS */
4632 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4633 if (ctx->bc->chip_class == CAYMAN) {
4634 for (i = 0 ; i < 3; i++) {
4635 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4636 alu.op = ALU_OP1_COS;
4637 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4638
4639 if (i == 0)
4640 alu.dst.write = 1;
4641 else
4642 alu.dst.write = 0;
4643 alu.src[0].sel = ctx->temp_reg;
4644 alu.src[0].chan = 0;
4645 if (i == 2)
4646 alu.last = 1;
4647 r = r600_bytecode_add_alu(ctx->bc, &alu);
4648 if (r)
4649 return r;
4650 }
4651 } else {
4652 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4653 alu.op = ALU_OP1_COS;
4654 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4655
4656 alu.src[0].sel = ctx->temp_reg;
4657 alu.src[0].chan = 0;
4658 alu.last = 1;
4659 r = r600_bytecode_add_alu(ctx->bc, &alu);
4660 if (r)
4661 return r;
4662 }
4663 }
4664
4665 /* dst.y = SIN */
4666 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4667 if (ctx->bc->chip_class == CAYMAN) {
4668 for (i = 0 ; i < 3; i++) {
4669 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4670 alu.op = ALU_OP1_SIN;
4671 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4672 if (i == 1)
4673 alu.dst.write = 1;
4674 else
4675 alu.dst.write = 0;
4676 alu.src[0].sel = ctx->temp_reg;
4677 alu.src[0].chan = 0;
4678 if (i == 2)
4679 alu.last = 1;
4680 r = r600_bytecode_add_alu(ctx->bc, &alu);
4681 if (r)
4682 return r;
4683 }
4684 } else {
4685 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4686 alu.op = ALU_OP1_SIN;
4687 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4688
4689 alu.src[0].sel = ctx->temp_reg;
4690 alu.src[0].chan = 0;
4691 alu.last = 1;
4692 r = r600_bytecode_add_alu(ctx->bc, &alu);
4693 if (r)
4694 return r;
4695 }
4696 }
4697
4698 /* dst.z = 0.0; */
4699 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4700 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4701
4702 alu.op = ALU_OP1_MOV;
4703
4704 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4705
4706 alu.src[0].sel = V_SQ_ALU_SRC_0;
4707 alu.src[0].chan = 0;
4708
4709 alu.last = 1;
4710
4711 r = r600_bytecode_add_alu(ctx->bc, &alu);
4712 if (r)
4713 return r;
4714 }
4715
4716 /* dst.w = 1.0; */
4717 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4719
4720 alu.op = ALU_OP1_MOV;
4721
4722 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4723
4724 alu.src[0].sel = V_SQ_ALU_SRC_1;
4725 alu.src[0].chan = 0;
4726
4727 alu.last = 1;
4728
4729 r = r600_bytecode_add_alu(ctx->bc, &alu);
4730 if (r)
4731 return r;
4732 }
4733
4734 return 0;
4735 }
4736
4737 static int tgsi_kill(struct r600_shader_ctx *ctx)
4738 {
4739 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4740 struct r600_bytecode_alu alu;
4741 int i, r;
4742
4743 for (i = 0; i < 4; i++) {
4744 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4745 alu.op = ctx->inst_info->op;
4746
4747 alu.dst.chan = i;
4748
4749 alu.src[0].sel = V_SQ_ALU_SRC_0;
4750
4751 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4752 alu.src[1].sel = V_SQ_ALU_SRC_1;
4753 alu.src[1].neg = 1;
4754 } else {
4755 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4756 }
4757 if (i == 3) {
4758 alu.last = 1;
4759 }
4760 r = r600_bytecode_add_alu(ctx->bc, &alu);
4761 if (r)
4762 return r;
4763 }
4764
4765 /* kill must be last in ALU */
4766 ctx->bc->force_add_cf = 1;
4767 ctx->shader->uses_kill = TRUE;
4768 return 0;
4769 }
4770
4771 static int tgsi_lit(struct r600_shader_ctx *ctx)
4772 {
4773 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4774 struct r600_bytecode_alu alu;
4775 int r;
4776
4777 /* tmp.x = max(src.y, 0.0) */
4778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4779 alu.op = ALU_OP2_MAX;
4780 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4781 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4782 alu.src[1].chan = 1;
4783
4784 alu.dst.sel = ctx->temp_reg;
4785 alu.dst.chan = 0;
4786 alu.dst.write = 1;
4787
4788 alu.last = 1;
4789 r = r600_bytecode_add_alu(ctx->bc, &alu);
4790 if (r)
4791 return r;
4792
4793 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4794 {
4795 int chan;
4796 int sel;
4797 int i;
4798
4799 if (ctx->bc->chip_class == CAYMAN) {
4800 for (i = 0; i < 3; i++) {
4801 /* tmp.z = log(tmp.x) */
4802 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4803 alu.op = ALU_OP1_LOG_CLAMPED;
4804 alu.src[0].sel = ctx->temp_reg;
4805 alu.src[0].chan = 0;
4806 alu.dst.sel = ctx->temp_reg;
4807 alu.dst.chan = i;
4808 if (i == 2) {
4809 alu.dst.write = 1;
4810 alu.last = 1;
4811 } else
4812 alu.dst.write = 0;
4813
4814 r = r600_bytecode_add_alu(ctx->bc, &alu);
4815 if (r)
4816 return r;
4817 }
4818 } else {
4819 /* tmp.z = log(tmp.x) */
4820 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4821 alu.op = ALU_OP1_LOG_CLAMPED;
4822 alu.src[0].sel = ctx->temp_reg;
4823 alu.src[0].chan = 0;
4824 alu.dst.sel = ctx->temp_reg;
4825 alu.dst.chan = 2;
4826 alu.dst.write = 1;
4827 alu.last = 1;
4828 r = r600_bytecode_add_alu(ctx->bc, &alu);
4829 if (r)
4830 return r;
4831 }
4832
4833 chan = alu.dst.chan;
4834 sel = alu.dst.sel;
4835
4836 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4837 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4838 alu.op = ALU_OP3_MUL_LIT;
4839 alu.src[0].sel = sel;
4840 alu.src[0].chan = chan;
4841 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4842 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4843 alu.dst.sel = ctx->temp_reg;
4844 alu.dst.chan = 0;
4845 alu.dst.write = 1;
4846 alu.is_op3 = 1;
4847 alu.last = 1;
4848 r = r600_bytecode_add_alu(ctx->bc, &alu);
4849 if (r)
4850 return r;
4851
4852 if (ctx->bc->chip_class == CAYMAN) {
4853 for (i = 0; i < 3; i++) {
4854 /* dst.z = exp(tmp.x) */
4855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4856 alu.op = ALU_OP1_EXP_IEEE;
4857 alu.src[0].sel = ctx->temp_reg;
4858 alu.src[0].chan = 0;
4859 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4860 if (i == 2) {
4861 alu.dst.write = 1;
4862 alu.last = 1;
4863 } else
4864 alu.dst.write = 0;
4865 r = r600_bytecode_add_alu(ctx->bc, &alu);
4866 if (r)
4867 return r;
4868 }
4869 } else {
4870 /* dst.z = exp(tmp.x) */
4871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4872 alu.op = ALU_OP1_EXP_IEEE;
4873 alu.src[0].sel = ctx->temp_reg;
4874 alu.src[0].chan = 0;
4875 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4876 alu.last = 1;
4877 r = r600_bytecode_add_alu(ctx->bc, &alu);
4878 if (r)
4879 return r;
4880 }
4881 }
4882
4883 /* dst.x, <- 1.0 */
4884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4885 alu.op = ALU_OP1_MOV;
4886 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4887 alu.src[0].chan = 0;
4888 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4889 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4890 r = r600_bytecode_add_alu(ctx->bc, &alu);
4891 if (r)
4892 return r;
4893
4894 /* dst.y = max(src.x, 0.0) */
4895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4896 alu.op = ALU_OP2_MAX;
4897 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4898 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4899 alu.src[1].chan = 0;
4900 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4901 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4902 r = r600_bytecode_add_alu(ctx->bc, &alu);
4903 if (r)
4904 return r;
4905
4906 /* dst.w, <- 1.0 */
4907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4908 alu.op = ALU_OP1_MOV;
4909 alu.src[0].sel = V_SQ_ALU_SRC_1;
4910 alu.src[0].chan = 0;
4911 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4912 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4913 alu.last = 1;
4914 r = r600_bytecode_add_alu(ctx->bc, &alu);
4915 if (r)
4916 return r;
4917
4918 return 0;
4919 }
4920
4921 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4922 {
4923 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4924 struct r600_bytecode_alu alu;
4925 int i, r;
4926
4927 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4928
4929 /* XXX:
4930 * For state trackers other than OpenGL, we'll want to use
4931 * _RECIPSQRT_IEEE instead.
4932 */
4933 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
4934
4935 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4936 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4937 r600_bytecode_src_set_abs(&alu.src[i]);
4938 }
4939 alu.dst.sel = ctx->temp_reg;
4940 alu.dst.write = 1;
4941 alu.last = 1;
4942 r = r600_bytecode_add_alu(ctx->bc, &alu);
4943 if (r)
4944 return r;
4945 /* replicate result */
4946 return tgsi_helper_tempx_replicate(ctx);
4947 }
4948
4949 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4950 {
4951 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4952 struct r600_bytecode_alu alu;
4953 int i, r;
4954
4955 for (i = 0; i < 4; i++) {
4956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4957 alu.src[0].sel = ctx->temp_reg;
4958 alu.op = ALU_OP1_MOV;
4959 alu.dst.chan = i;
4960 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4961 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4962 if (i == 3)
4963 alu.last = 1;
4964 r = r600_bytecode_add_alu(ctx->bc, &alu);
4965 if (r)
4966 return r;
4967 }
4968 return 0;
4969 }
4970
4971 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4972 {
4973 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4974 struct r600_bytecode_alu alu;
4975 int i, r;
4976
4977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4978 alu.op = ctx->inst_info->op;
4979 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4980 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4981 }
4982 alu.dst.sel = ctx->temp_reg;
4983 alu.dst.write = 1;
4984 alu.last = 1;
4985 r = r600_bytecode_add_alu(ctx->bc, &alu);
4986 if (r)
4987 return r;
4988 /* replicate result */
4989 return tgsi_helper_tempx_replicate(ctx);
4990 }
4991
4992 static int cayman_pow(struct r600_shader_ctx *ctx)
4993 {
4994 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4995 int i, r;
4996 struct r600_bytecode_alu alu;
4997 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4998
4999 for (i = 0; i < 3; i++) {
5000 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5001 alu.op = ALU_OP1_LOG_IEEE;
5002 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5003 alu.dst.sel = ctx->temp_reg;
5004 alu.dst.chan = i;
5005 alu.dst.write = 1;
5006 if (i == 2)
5007 alu.last = 1;
5008 r = r600_bytecode_add_alu(ctx->bc, &alu);
5009 if (r)
5010 return r;
5011 }
5012
5013 /* b * LOG2(a) */
5014 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5015 alu.op = ALU_OP2_MUL;
5016 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5017 alu.src[1].sel = ctx->temp_reg;
5018 alu.dst.sel = ctx->temp_reg;
5019 alu.dst.write = 1;
5020 alu.last = 1;
5021 r = r600_bytecode_add_alu(ctx->bc, &alu);
5022 if (r)
5023 return r;
5024
5025 for (i = 0; i < last_slot; i++) {
5026 /* POW(a,b) = EXP2(b * LOG2(a))*/
5027 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5028 alu.op = ALU_OP1_EXP_IEEE;
5029 alu.src[0].sel = ctx->temp_reg;
5030
5031 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5032 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5033 if (i == last_slot - 1)
5034 alu.last = 1;
5035 r = r600_bytecode_add_alu(ctx->bc, &alu);
5036 if (r)
5037 return r;
5038 }
5039 return 0;
5040 }
5041
5042 static int tgsi_pow(struct r600_shader_ctx *ctx)
5043 {
5044 struct r600_bytecode_alu alu;
5045 int r;
5046
5047 /* LOG2(a) */
5048 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5049 alu.op = ALU_OP1_LOG_IEEE;
5050 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5051 alu.dst.sel = ctx->temp_reg;
5052 alu.dst.write = 1;
5053 alu.last = 1;
5054 r = r600_bytecode_add_alu(ctx->bc, &alu);
5055 if (r)
5056 return r;
5057 /* b * LOG2(a) */
5058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5059 alu.op = ALU_OP2_MUL;
5060 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5061 alu.src[1].sel = ctx->temp_reg;
5062 alu.dst.sel = ctx->temp_reg;
5063 alu.dst.write = 1;
5064 alu.last = 1;
5065 r = r600_bytecode_add_alu(ctx->bc, &alu);
5066 if (r)
5067 return r;
5068 /* POW(a,b) = EXP2(b * LOG2(a))*/
5069 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5070 alu.op = ALU_OP1_EXP_IEEE;
5071 alu.src[0].sel = ctx->temp_reg;
5072 alu.dst.sel = ctx->temp_reg;
5073 alu.dst.write = 1;
5074 alu.last = 1;
5075 r = r600_bytecode_add_alu(ctx->bc, &alu);
5076 if (r)
5077 return r;
5078 return tgsi_helper_tempx_replicate(ctx);
5079 }
5080
5081 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5082 {
5083 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5084 struct r600_bytecode_alu alu;
5085 int i, r, j;
5086 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5087 int tmp0 = ctx->temp_reg;
5088 int tmp1 = r600_get_temp(ctx);
5089 int tmp2 = r600_get_temp(ctx);
5090 int tmp3 = r600_get_temp(ctx);
5091 /* Unsigned path:
5092 *
5093 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5094 *
5095 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5096 * 2. tmp0.z = lo (tmp0.x * src2)
5097 * 3. tmp0.w = -tmp0.z
5098 * 4. tmp0.y = hi (tmp0.x * src2)
5099 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5100 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5101 * 7. tmp1.x = tmp0.x - tmp0.w
5102 * 8. tmp1.y = tmp0.x + tmp0.w
5103 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5104 * 10. tmp0.z = hi(tmp0.x * src1) = q
5105 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5106 *
5107 * 12. tmp0.w = src1 - tmp0.y = r
5108 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5109 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5110 *
5111 * if DIV
5112 *
5113 * 15. tmp1.z = tmp0.z + 1 = q + 1
5114 * 16. tmp1.w = tmp0.z - 1 = q - 1
5115 *
5116 * else MOD
5117 *
5118 * 15. tmp1.z = tmp0.w - src2 = r - src2
5119 * 16. tmp1.w = tmp0.w + src2 = r + src2
5120 *
5121 * endif
5122 *
5123 * 17. tmp1.x = tmp1.x & tmp1.y
5124 *
5125 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5126 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5127 *
5128 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5129 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5130 *
5131 * Signed path:
5132 *
5133 * Same as unsigned, using abs values of the operands,
5134 * and fixing the sign of the result in the end.
5135 */
5136
5137 for (i = 0; i < 4; i++) {
5138 if (!(write_mask & (1<<i)))
5139 continue;
5140
5141 if (signed_op) {
5142
5143 /* tmp2.x = -src0 */
5144 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5145 alu.op = ALU_OP2_SUB_INT;
5146
5147 alu.dst.sel = tmp2;
5148 alu.dst.chan = 0;
5149 alu.dst.write = 1;
5150
5151 alu.src[0].sel = V_SQ_ALU_SRC_0;
5152
5153 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5154
5155 alu.last = 1;
5156 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5157 return r;
5158
5159 /* tmp2.y = -src1 */
5160 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5161 alu.op = ALU_OP2_SUB_INT;
5162
5163 alu.dst.sel = tmp2;
5164 alu.dst.chan = 1;
5165 alu.dst.write = 1;
5166
5167 alu.src[0].sel = V_SQ_ALU_SRC_0;
5168
5169 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5170
5171 alu.last = 1;
5172 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5173 return r;
5174
5175 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5176 /* it will be a sign of the quotient */
5177 if (!mod) {
5178
5179 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5180 alu.op = ALU_OP2_XOR_INT;
5181
5182 alu.dst.sel = tmp2;
5183 alu.dst.chan = 2;
5184 alu.dst.write = 1;
5185
5186 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5187 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5188
5189 alu.last = 1;
5190 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5191 return r;
5192 }
5193
5194 /* tmp2.x = |src0| */
5195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5196 alu.op = ALU_OP3_CNDGE_INT;
5197 alu.is_op3 = 1;
5198
5199 alu.dst.sel = tmp2;
5200 alu.dst.chan = 0;
5201 alu.dst.write = 1;
5202
5203 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5204 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5205 alu.src[2].sel = tmp2;
5206 alu.src[2].chan = 0;
5207
5208 alu.last = 1;
5209 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5210 return r;
5211
5212 /* tmp2.y = |src1| */
5213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5214 alu.op = ALU_OP3_CNDGE_INT;
5215 alu.is_op3 = 1;
5216
5217 alu.dst.sel = tmp2;
5218 alu.dst.chan = 1;
5219 alu.dst.write = 1;
5220
5221 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5222 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5223 alu.src[2].sel = tmp2;
5224 alu.src[2].chan = 1;
5225
5226 alu.last = 1;
5227 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5228 return r;
5229
5230 }
5231
5232 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5233 if (ctx->bc->chip_class == CAYMAN) {
5234 /* tmp3.x = u2f(src2) */
5235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5236 alu.op = ALU_OP1_UINT_TO_FLT;
5237
5238 alu.dst.sel = tmp3;
5239 alu.dst.chan = 0;
5240 alu.dst.write = 1;
5241
5242 if (signed_op) {
5243 alu.src[0].sel = tmp2;
5244 alu.src[0].chan = 1;
5245 } else {
5246 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5247 }
5248
5249 alu.last = 1;
5250 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5251 return r;
5252
5253 /* tmp0.x = recip(tmp3.x) */
5254 for (j = 0 ; j < 3; j++) {
5255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5256 alu.op = ALU_OP1_RECIP_IEEE;
5257
5258 alu.dst.sel = tmp0;
5259 alu.dst.chan = j;
5260 alu.dst.write = (j == 0);
5261
5262 alu.src[0].sel = tmp3;
5263 alu.src[0].chan = 0;
5264
5265 if (j == 2)
5266 alu.last = 1;
5267 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5268 return r;
5269 }
5270
5271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5272 alu.op = ALU_OP2_MUL;
5273
5274 alu.src[0].sel = tmp0;
5275 alu.src[0].chan = 0;
5276
5277 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5278 alu.src[1].value = 0x4f800000;
5279
5280 alu.dst.sel = tmp3;
5281 alu.dst.write = 1;
5282 alu.last = 1;
5283 r = r600_bytecode_add_alu(ctx->bc, &alu);
5284 if (r)
5285 return r;
5286
5287 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5288 alu.op = ALU_OP1_FLT_TO_UINT;
5289
5290 alu.dst.sel = tmp0;
5291 alu.dst.chan = 0;
5292 alu.dst.write = 1;
5293
5294 alu.src[0].sel = tmp3;
5295 alu.src[0].chan = 0;
5296
5297 alu.last = 1;
5298 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5299 return r;
5300
5301 } else {
5302 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5303 alu.op = ALU_OP1_RECIP_UINT;
5304
5305 alu.dst.sel = tmp0;
5306 alu.dst.chan = 0;
5307 alu.dst.write = 1;
5308
5309 if (signed_op) {
5310 alu.src[0].sel = tmp2;
5311 alu.src[0].chan = 1;
5312 } else {
5313 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5314 }
5315
5316 alu.last = 1;
5317 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5318 return r;
5319 }
5320
5321 /* 2. tmp0.z = lo (tmp0.x * src2) */
5322 if (ctx->bc->chip_class == CAYMAN) {
5323 for (j = 0 ; j < 4; j++) {
5324 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5325 alu.op = ALU_OP2_MULLO_UINT;
5326
5327 alu.dst.sel = tmp0;
5328 alu.dst.chan = j;
5329 alu.dst.write = (j == 2);
5330
5331 alu.src[0].sel = tmp0;
5332 alu.src[0].chan = 0;
5333 if (signed_op) {
5334 alu.src[1].sel = tmp2;
5335 alu.src[1].chan = 1;
5336 } else {
5337 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5338 }
5339
5340 alu.last = (j == 3);
5341 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5342 return r;
5343 }
5344 } else {
5345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5346 alu.op = ALU_OP2_MULLO_UINT;
5347
5348 alu.dst.sel = tmp0;
5349 alu.dst.chan = 2;
5350 alu.dst.write = 1;
5351
5352 alu.src[0].sel = tmp0;
5353 alu.src[0].chan = 0;
5354 if (signed_op) {
5355 alu.src[1].sel = tmp2;
5356 alu.src[1].chan = 1;
5357 } else {
5358 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5359 }
5360
5361 alu.last = 1;
5362 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5363 return r;
5364 }
5365
5366 /* 3. tmp0.w = -tmp0.z */
5367 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5368 alu.op = ALU_OP2_SUB_INT;
5369
5370 alu.dst.sel = tmp0;
5371 alu.dst.chan = 3;
5372 alu.dst.write = 1;
5373
5374 alu.src[0].sel = V_SQ_ALU_SRC_0;
5375 alu.src[1].sel = tmp0;
5376 alu.src[1].chan = 2;
5377
5378 alu.last = 1;
5379 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5380 return r;
5381
5382 /* 4. tmp0.y = hi (tmp0.x * src2) */
5383 if (ctx->bc->chip_class == CAYMAN) {
5384 for (j = 0 ; j < 4; j++) {
5385 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5386 alu.op = ALU_OP2_MULHI_UINT;
5387
5388 alu.dst.sel = tmp0;
5389 alu.dst.chan = j;
5390 alu.dst.write = (j == 1);
5391
5392 alu.src[0].sel = tmp0;
5393 alu.src[0].chan = 0;
5394
5395 if (signed_op) {
5396 alu.src[1].sel = tmp2;
5397 alu.src[1].chan = 1;
5398 } else {
5399 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5400 }
5401 alu.last = (j == 3);
5402 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5403 return r;
5404 }
5405 } else {
5406 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5407 alu.op = ALU_OP2_MULHI_UINT;
5408
5409 alu.dst.sel = tmp0;
5410 alu.dst.chan = 1;
5411 alu.dst.write = 1;
5412
5413 alu.src[0].sel = tmp0;
5414 alu.src[0].chan = 0;
5415
5416 if (signed_op) {
5417 alu.src[1].sel = tmp2;
5418 alu.src[1].chan = 1;
5419 } else {
5420 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5421 }
5422
5423 alu.last = 1;
5424 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5425 return r;
5426 }
5427
5428 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5429 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5430 alu.op = ALU_OP3_CNDE_INT;
5431 alu.is_op3 = 1;
5432
5433 alu.dst.sel = tmp0;
5434 alu.dst.chan = 2;
5435 alu.dst.write = 1;
5436
5437 alu.src[0].sel = tmp0;
5438 alu.src[0].chan = 1;
5439 alu.src[1].sel = tmp0;
5440 alu.src[1].chan = 3;
5441 alu.src[2].sel = tmp0;
5442 alu.src[2].chan = 2;
5443
5444 alu.last = 1;
5445 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5446 return r;
5447
5448 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5449 if (ctx->bc->chip_class == CAYMAN) {
5450 for (j = 0 ; j < 4; j++) {
5451 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5452 alu.op = ALU_OP2_MULHI_UINT;
5453
5454 alu.dst.sel = tmp0;
5455 alu.dst.chan = j;
5456 alu.dst.write = (j == 3);
5457
5458 alu.src[0].sel = tmp0;
5459 alu.src[0].chan = 2;
5460
5461 alu.src[1].sel = tmp0;
5462 alu.src[1].chan = 0;
5463
5464 alu.last = (j == 3);
5465 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5466 return r;
5467 }
5468 } else {
5469 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5470 alu.op = ALU_OP2_MULHI_UINT;
5471
5472 alu.dst.sel = tmp0;
5473 alu.dst.chan = 3;
5474 alu.dst.write = 1;
5475
5476 alu.src[0].sel = tmp0;
5477 alu.src[0].chan = 2;
5478
5479 alu.src[1].sel = tmp0;
5480 alu.src[1].chan = 0;
5481
5482 alu.last = 1;
5483 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5484 return r;
5485 }
5486
5487 /* 7. tmp1.x = tmp0.x - tmp0.w */
5488 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5489 alu.op = ALU_OP2_SUB_INT;
5490
5491 alu.dst.sel = tmp1;
5492 alu.dst.chan = 0;
5493 alu.dst.write = 1;
5494
5495 alu.src[0].sel = tmp0;
5496 alu.src[0].chan = 0;
5497 alu.src[1].sel = tmp0;
5498 alu.src[1].chan = 3;
5499
5500 alu.last = 1;
5501 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5502 return r;
5503
5504 /* 8. tmp1.y = tmp0.x + tmp0.w */
5505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5506 alu.op = ALU_OP2_ADD_INT;
5507
5508 alu.dst.sel = tmp1;
5509 alu.dst.chan = 1;
5510 alu.dst.write = 1;
5511
5512 alu.src[0].sel = tmp0;
5513 alu.src[0].chan = 0;
5514 alu.src[1].sel = tmp0;
5515 alu.src[1].chan = 3;
5516
5517 alu.last = 1;
5518 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5519 return r;
5520
5521 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5523 alu.op = ALU_OP3_CNDE_INT;
5524 alu.is_op3 = 1;
5525
5526 alu.dst.sel = tmp0;
5527 alu.dst.chan = 0;
5528 alu.dst.write = 1;
5529
5530 alu.src[0].sel = tmp0;
5531 alu.src[0].chan = 1;
5532 alu.src[1].sel = tmp1;
5533 alu.src[1].chan = 1;
5534 alu.src[2].sel = tmp1;
5535 alu.src[2].chan = 0;
5536
5537 alu.last = 1;
5538 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5539 return r;
5540
5541 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5542 if (ctx->bc->chip_class == CAYMAN) {
5543 for (j = 0 ; j < 4; j++) {
5544 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5545 alu.op = ALU_OP2_MULHI_UINT;
5546
5547 alu.dst.sel = tmp0;
5548 alu.dst.chan = j;
5549 alu.dst.write = (j == 2);
5550
5551 alu.src[0].sel = tmp0;
5552 alu.src[0].chan = 0;
5553
5554 if (signed_op) {
5555 alu.src[1].sel = tmp2;
5556 alu.src[1].chan = 0;
5557 } else {
5558 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5559 }
5560
5561 alu.last = (j == 3);
5562 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5563 return r;
5564 }
5565 } else {
5566 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5567 alu.op = ALU_OP2_MULHI_UINT;
5568
5569 alu.dst.sel = tmp0;
5570 alu.dst.chan = 2;
5571 alu.dst.write = 1;
5572
5573 alu.src[0].sel = tmp0;
5574 alu.src[0].chan = 0;
5575
5576 if (signed_op) {
5577 alu.src[1].sel = tmp2;
5578 alu.src[1].chan = 0;
5579 } else {
5580 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5581 }
5582
5583 alu.last = 1;
5584 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5585 return r;
5586 }
5587
5588 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5589 if (ctx->bc->chip_class == CAYMAN) {
5590 for (j = 0 ; j < 4; j++) {
5591 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5592 alu.op = ALU_OP2_MULLO_UINT;
5593
5594 alu.dst.sel = tmp0;
5595 alu.dst.chan = j;
5596 alu.dst.write = (j == 1);
5597
5598 if (signed_op) {
5599 alu.src[0].sel = tmp2;
5600 alu.src[0].chan = 1;
5601 } else {
5602 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5603 }
5604
5605 alu.src[1].sel = tmp0;
5606 alu.src[1].chan = 2;
5607
5608 alu.last = (j == 3);
5609 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5610 return r;
5611 }
5612 } else {
5613 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5614 alu.op = ALU_OP2_MULLO_UINT;
5615
5616 alu.dst.sel = tmp0;
5617 alu.dst.chan = 1;
5618 alu.dst.write = 1;
5619
5620 if (signed_op) {
5621 alu.src[0].sel = tmp2;
5622 alu.src[0].chan = 1;
5623 } else {
5624 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5625 }
5626
5627 alu.src[1].sel = tmp0;
5628 alu.src[1].chan = 2;
5629
5630 alu.last = 1;
5631 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5632 return r;
5633 }
5634
5635 /* 12. tmp0.w = src1 - tmp0.y = r */
5636 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5637 alu.op = ALU_OP2_SUB_INT;
5638
5639 alu.dst.sel = tmp0;
5640 alu.dst.chan = 3;
5641 alu.dst.write = 1;
5642
5643 if (signed_op) {
5644 alu.src[0].sel = tmp2;
5645 alu.src[0].chan = 0;
5646 } else {
5647 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5648 }
5649
5650 alu.src[1].sel = tmp0;
5651 alu.src[1].chan = 1;
5652
5653 alu.last = 1;
5654 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5655 return r;
5656
5657 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5658 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5659 alu.op = ALU_OP2_SETGE_UINT;
5660
5661 alu.dst.sel = tmp1;
5662 alu.dst.chan = 0;
5663 alu.dst.write = 1;
5664
5665 alu.src[0].sel = tmp0;
5666 alu.src[0].chan = 3;
5667 if (signed_op) {
5668 alu.src[1].sel = tmp2;
5669 alu.src[1].chan = 1;
5670 } else {
5671 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5672 }
5673
5674 alu.last = 1;
5675 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5676 return r;
5677
5678 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5679 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5680 alu.op = ALU_OP2_SETGE_UINT;
5681
5682 alu.dst.sel = tmp1;
5683 alu.dst.chan = 1;
5684 alu.dst.write = 1;
5685
5686 if (signed_op) {
5687 alu.src[0].sel = tmp2;
5688 alu.src[0].chan = 0;
5689 } else {
5690 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5691 }
5692
5693 alu.src[1].sel = tmp0;
5694 alu.src[1].chan = 1;
5695
5696 alu.last = 1;
5697 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5698 return r;
5699
5700 if (mod) { /* UMOD */
5701
5702 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5704 alu.op = ALU_OP2_SUB_INT;
5705
5706 alu.dst.sel = tmp1;
5707 alu.dst.chan = 2;
5708 alu.dst.write = 1;
5709
5710 alu.src[0].sel = tmp0;
5711 alu.src[0].chan = 3;
5712
5713 if (signed_op) {
5714 alu.src[1].sel = tmp2;
5715 alu.src[1].chan = 1;
5716 } else {
5717 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5718 }
5719
5720 alu.last = 1;
5721 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5722 return r;
5723
5724 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5726 alu.op = ALU_OP2_ADD_INT;
5727
5728 alu.dst.sel = tmp1;
5729 alu.dst.chan = 3;
5730 alu.dst.write = 1;
5731
5732 alu.src[0].sel = tmp0;
5733 alu.src[0].chan = 3;
5734 if (signed_op) {
5735 alu.src[1].sel = tmp2;
5736 alu.src[1].chan = 1;
5737 } else {
5738 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5739 }
5740
5741 alu.last = 1;
5742 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5743 return r;
5744
5745 } else { /* UDIV */
5746
5747 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5748 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5749 alu.op = ALU_OP2_ADD_INT;
5750
5751 alu.dst.sel = tmp1;
5752 alu.dst.chan = 2;
5753 alu.dst.write = 1;
5754
5755 alu.src[0].sel = tmp0;
5756 alu.src[0].chan = 2;
5757 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5758
5759 alu.last = 1;
5760 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5761 return r;
5762
5763 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5765 alu.op = ALU_OP2_ADD_INT;
5766
5767 alu.dst.sel = tmp1;
5768 alu.dst.chan = 3;
5769 alu.dst.write = 1;
5770
5771 alu.src[0].sel = tmp0;
5772 alu.src[0].chan = 2;
5773 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5774
5775 alu.last = 1;
5776 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5777 return r;
5778
5779 }
5780
5781 /* 17. tmp1.x = tmp1.x & tmp1.y */
5782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5783 alu.op = ALU_OP2_AND_INT;
5784
5785 alu.dst.sel = tmp1;
5786 alu.dst.chan = 0;
5787 alu.dst.write = 1;
5788
5789 alu.src[0].sel = tmp1;
5790 alu.src[0].chan = 0;
5791 alu.src[1].sel = tmp1;
5792 alu.src[1].chan = 1;
5793
5794 alu.last = 1;
5795 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5796 return r;
5797
5798 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5799 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5800 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5801 alu.op = ALU_OP3_CNDE_INT;
5802 alu.is_op3 = 1;
5803
5804 alu.dst.sel = tmp0;
5805 alu.dst.chan = 2;
5806 alu.dst.write = 1;
5807
5808 alu.src[0].sel = tmp1;
5809 alu.src[0].chan = 0;
5810 alu.src[1].sel = tmp0;
5811 alu.src[1].chan = mod ? 3 : 2;
5812 alu.src[2].sel = tmp1;
5813 alu.src[2].chan = 2;
5814
5815 alu.last = 1;
5816 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5817 return r;
5818
5819 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5820 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5821 alu.op = ALU_OP3_CNDE_INT;
5822 alu.is_op3 = 1;
5823
5824 if (signed_op) {
5825 alu.dst.sel = tmp0;
5826 alu.dst.chan = 2;
5827 alu.dst.write = 1;
5828 } else {
5829 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5830 }
5831
5832 alu.src[0].sel = tmp1;
5833 alu.src[0].chan = 1;
5834 alu.src[1].sel = tmp1;
5835 alu.src[1].chan = 3;
5836 alu.src[2].sel = tmp0;
5837 alu.src[2].chan = 2;
5838
5839 alu.last = 1;
5840 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5841 return r;
5842
5843 if (signed_op) {
5844
5845 /* fix the sign of the result */
5846
5847 if (mod) {
5848
5849 /* tmp0.x = -tmp0.z */
5850 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5851 alu.op = ALU_OP2_SUB_INT;
5852
5853 alu.dst.sel = tmp0;
5854 alu.dst.chan = 0;
5855 alu.dst.write = 1;
5856
5857 alu.src[0].sel = V_SQ_ALU_SRC_0;
5858 alu.src[1].sel = tmp0;
5859 alu.src[1].chan = 2;
5860
5861 alu.last = 1;
5862 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5863 return r;
5864
5865 /* sign of the remainder is the same as the sign of src0 */
5866 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5867 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5868 alu.op = ALU_OP3_CNDGE_INT;
5869 alu.is_op3 = 1;
5870
5871 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5872
5873 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5874 alu.src[1].sel = tmp0;
5875 alu.src[1].chan = 2;
5876 alu.src[2].sel = tmp0;
5877 alu.src[2].chan = 0;
5878
5879 alu.last = 1;
5880 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5881 return r;
5882
5883 } else {
5884
5885 /* tmp0.x = -tmp0.z */
5886 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5887 alu.op = ALU_OP2_SUB_INT;
5888
5889 alu.dst.sel = tmp0;
5890 alu.dst.chan = 0;
5891 alu.dst.write = 1;
5892
5893 alu.src[0].sel = V_SQ_ALU_SRC_0;
5894 alu.src[1].sel = tmp0;
5895 alu.src[1].chan = 2;
5896
5897 alu.last = 1;
5898 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5899 return r;
5900
5901 /* fix the quotient sign (same as the sign of src0*src1) */
5902 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5903 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5904 alu.op = ALU_OP3_CNDGE_INT;
5905 alu.is_op3 = 1;
5906
5907 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5908
5909 alu.src[0].sel = tmp2;
5910 alu.src[0].chan = 2;
5911 alu.src[1].sel = tmp0;
5912 alu.src[1].chan = 2;
5913 alu.src[2].sel = tmp0;
5914 alu.src[2].chan = 0;
5915
5916 alu.last = 1;
5917 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5918 return r;
5919 }
5920 }
5921 }
5922 return 0;
5923 }
5924
5925 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5926 {
5927 return tgsi_divmod(ctx, 0, 0);
5928 }
5929
5930 static int tgsi_umod(struct r600_shader_ctx *ctx)
5931 {
5932 return tgsi_divmod(ctx, 1, 0);
5933 }
5934
5935 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5936 {
5937 return tgsi_divmod(ctx, 0, 1);
5938 }
5939
5940 static int tgsi_imod(struct r600_shader_ctx *ctx)
5941 {
5942 return tgsi_divmod(ctx, 1, 1);
5943 }
5944
5945
5946 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5947 {
5948 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5949 struct r600_bytecode_alu alu;
5950 int i, r;
5951 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5952 int last_inst = tgsi_last_instruction(write_mask);
5953
5954 for (i = 0; i < 4; i++) {
5955 if (!(write_mask & (1<<i)))
5956 continue;
5957
5958 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5959 alu.op = ALU_OP1_TRUNC;
5960
5961 alu.dst.sel = ctx->temp_reg;
5962 alu.dst.chan = i;
5963 alu.dst.write = 1;
5964
5965 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5966 if (i == last_inst)
5967 alu.last = 1;
5968 r = r600_bytecode_add_alu(ctx->bc, &alu);
5969 if (r)
5970 return r;
5971 }
5972
5973 for (i = 0; i < 4; i++) {
5974 if (!(write_mask & (1<<i)))
5975 continue;
5976
5977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5978 alu.op = ctx->inst_info->op;
5979
5980 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5981
5982 alu.src[0].sel = ctx->temp_reg;
5983 alu.src[0].chan = i;
5984
5985 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5986 alu.last = 1;
5987 r = r600_bytecode_add_alu(ctx->bc, &alu);
5988 if (r)
5989 return r;
5990 }
5991
5992 return 0;
5993 }
5994
5995 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5996 {
5997 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5998 struct r600_bytecode_alu alu;
5999 int i, r;
6000 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6001 int last_inst = tgsi_last_instruction(write_mask);
6002
6003 /* tmp = -src */
6004 for (i = 0; i < 4; i++) {
6005 if (!(write_mask & (1<<i)))
6006 continue;
6007
6008 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6009 alu.op = ALU_OP2_SUB_INT;
6010
6011 alu.dst.sel = ctx->temp_reg;
6012 alu.dst.chan = i;
6013 alu.dst.write = 1;
6014
6015 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6016 alu.src[0].sel = V_SQ_ALU_SRC_0;
6017
6018 if (i == last_inst)
6019 alu.last = 1;
6020 r = r600_bytecode_add_alu(ctx->bc, &alu);
6021 if (r)
6022 return r;
6023 }
6024
6025 /* dst = (src >= 0 ? src : tmp) */
6026 for (i = 0; i < 4; i++) {
6027 if (!(write_mask & (1<<i)))
6028 continue;
6029
6030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6031 alu.op = ALU_OP3_CNDGE_INT;
6032 alu.is_op3 = 1;
6033 alu.dst.write = 1;
6034
6035 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6036
6037 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6038 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6039 alu.src[2].sel = ctx->temp_reg;
6040 alu.src[2].chan = i;
6041
6042 if (i == last_inst)
6043 alu.last = 1;
6044 r = r600_bytecode_add_alu(ctx->bc, &alu);
6045 if (r)
6046 return r;
6047 }
6048 return 0;
6049 }
6050
6051 static int tgsi_issg(struct r600_shader_ctx *ctx)
6052 {
6053 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6054 struct r600_bytecode_alu alu;
6055 int i, r;
6056 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6057 int last_inst = tgsi_last_instruction(write_mask);
6058
6059 /* tmp = (src >= 0 ? src : -1) */
6060 for (i = 0; i < 4; i++) {
6061 if (!(write_mask & (1<<i)))
6062 continue;
6063
6064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6065 alu.op = ALU_OP3_CNDGE_INT;
6066 alu.is_op3 = 1;
6067
6068 alu.dst.sel = ctx->temp_reg;
6069 alu.dst.chan = i;
6070 alu.dst.write = 1;
6071
6072 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6073 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6074 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6075
6076 if (i == last_inst)
6077 alu.last = 1;
6078 r = r600_bytecode_add_alu(ctx->bc, &alu);
6079 if (r)
6080 return r;
6081 }
6082
6083 /* dst = (tmp > 0 ? 1 : tmp) */
6084 for (i = 0; i < 4; i++) {
6085 if (!(write_mask & (1<<i)))
6086 continue;
6087
6088 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6089 alu.op = ALU_OP3_CNDGT_INT;
6090 alu.is_op3 = 1;
6091 alu.dst.write = 1;
6092
6093 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6094
6095 alu.src[0].sel = ctx->temp_reg;
6096 alu.src[0].chan = i;
6097
6098 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6099
6100 alu.src[2].sel = ctx->temp_reg;
6101 alu.src[2].chan = i;
6102
6103 if (i == last_inst)
6104 alu.last = 1;
6105 r = r600_bytecode_add_alu(ctx->bc, &alu);
6106 if (r)
6107 return r;
6108 }
6109 return 0;
6110 }
6111
6112
6113
6114 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6115 {
6116 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6117 struct r600_bytecode_alu alu;
6118 int i, r;
6119
6120 /* tmp = (src > 0 ? 1 : src) */
6121 for (i = 0; i < 4; i++) {
6122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6123 alu.op = ALU_OP3_CNDGT;
6124 alu.is_op3 = 1;
6125
6126 alu.dst.sel = ctx->temp_reg;
6127 alu.dst.chan = i;
6128
6129 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6130 alu.src[1].sel = V_SQ_ALU_SRC_1;
6131 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6132
6133 if (i == 3)
6134 alu.last = 1;
6135 r = r600_bytecode_add_alu(ctx->bc, &alu);
6136 if (r)
6137 return r;
6138 }
6139
6140 /* dst = (-tmp > 0 ? -1 : tmp) */
6141 for (i = 0; i < 4; i++) {
6142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6143 alu.op = ALU_OP3_CNDGT;
6144 alu.is_op3 = 1;
6145 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6146
6147 alu.src[0].sel = ctx->temp_reg;
6148 alu.src[0].chan = i;
6149 alu.src[0].neg = 1;
6150
6151 alu.src[1].sel = V_SQ_ALU_SRC_1;
6152 alu.src[1].neg = 1;
6153
6154 alu.src[2].sel = ctx->temp_reg;
6155 alu.src[2].chan = i;
6156
6157 if (i == 3)
6158 alu.last = 1;
6159 r = r600_bytecode_add_alu(ctx->bc, &alu);
6160 if (r)
6161 return r;
6162 }
6163 return 0;
6164 }
6165
6166 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6167 {
6168 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6169 struct r600_bytecode_alu alu;
6170 int i, r, t1, t2;
6171
6172 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6173 int last_inst = tgsi_last_instruction(write_mask);
6174
6175 t1 = ctx->temp_reg;
6176
6177 for (i = 0; i < 4; i++) {
6178 if (!(write_mask & (1<<i)))
6179 continue;
6180
6181 /* create mask tmp */
6182 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6183 alu.op = ALU_OP2_BFM_INT;
6184 alu.dst.sel = t1;
6185 alu.dst.chan = i;
6186 alu.dst.write = 1;
6187 alu.last = i == last_inst;
6188
6189 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6190 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6191
6192 r = r600_bytecode_add_alu(ctx->bc, &alu);
6193 if (r)
6194 return r;
6195 }
6196
6197 t2 = r600_get_temp(ctx);
6198
6199 for (i = 0; i < 4; i++) {
6200 if (!(write_mask & (1<<i)))
6201 continue;
6202
6203 /* shift insert left */
6204 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6205 alu.op = ALU_OP2_LSHL_INT;
6206 alu.dst.sel = t2;
6207 alu.dst.chan = i;
6208 alu.dst.write = 1;
6209 alu.last = i == last_inst;
6210
6211 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6212 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6213
6214 r = r600_bytecode_add_alu(ctx->bc, &alu);
6215 if (r)
6216 return r;
6217 }
6218
6219 for (i = 0; i < 4; i++) {
6220 if (!(write_mask & (1<<i)))
6221 continue;
6222
6223 /* actual bitfield insert */
6224 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6225 alu.op = ALU_OP3_BFI_INT;
6226 alu.is_op3 = 1;
6227 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6228 alu.dst.chan = i;
6229 alu.dst.write = 1;
6230 alu.last = i == last_inst;
6231
6232 alu.src[0].sel = t1;
6233 alu.src[0].chan = i;
6234 alu.src[1].sel = t2;
6235 alu.src[1].chan = i;
6236 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6237
6238 r = r600_bytecode_add_alu(ctx->bc, &alu);
6239 if (r)
6240 return r;
6241 }
6242
6243 return 0;
6244 }
6245
6246 static int tgsi_msb(struct r600_shader_ctx *ctx)
6247 {
6248 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6249 struct r600_bytecode_alu alu;
6250 int i, r, t1, t2;
6251
6252 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6253 int last_inst = tgsi_last_instruction(write_mask);
6254
6255 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6256 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6257
6258 t1 = ctx->temp_reg;
6259
6260 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6261 for (i = 0; i < 4; i++) {
6262 if (!(write_mask & (1<<i)))
6263 continue;
6264
6265 /* t1 = FFBH_INT / FFBH_UINT */
6266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6267 alu.op = ctx->inst_info->op;
6268 alu.dst.sel = t1;
6269 alu.dst.chan = i;
6270 alu.dst.write = 1;
6271 alu.last = i == last_inst;
6272
6273 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6274
6275 r = r600_bytecode_add_alu(ctx->bc, &alu);
6276 if (r)
6277 return r;
6278 }
6279
6280 t2 = r600_get_temp(ctx);
6281
6282 for (i = 0; i < 4; i++) {
6283 if (!(write_mask & (1<<i)))
6284 continue;
6285
6286 /* t2 = 31 - t1 */
6287 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6288 alu.op = ALU_OP2_SUB_INT;
6289 alu.dst.sel = t2;
6290 alu.dst.chan = i;
6291 alu.dst.write = 1;
6292 alu.last = i == last_inst;
6293
6294 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6295 alu.src[0].value = 31;
6296 alu.src[1].sel = t1;
6297 alu.src[1].chan = i;
6298
6299 r = r600_bytecode_add_alu(ctx->bc, &alu);
6300 if (r)
6301 return r;
6302 }
6303
6304 for (i = 0; i < 4; i++) {
6305 if (!(write_mask & (1<<i)))
6306 continue;
6307
6308 /* result = t1 >= 0 ? t2 : t1 */
6309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6310 alu.op = ALU_OP3_CNDGE_INT;
6311 alu.is_op3 = 1;
6312 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6313 alu.dst.chan = i;
6314 alu.dst.write = 1;
6315 alu.last = i == last_inst;
6316
6317 alu.src[0].sel = t1;
6318 alu.src[0].chan = i;
6319 alu.src[1].sel = t2;
6320 alu.src[1].chan = i;
6321 alu.src[2].sel = t1;
6322 alu.src[2].chan = i;
6323
6324 r = r600_bytecode_add_alu(ctx->bc, &alu);
6325 if (r)
6326 return r;
6327 }
6328
6329 return 0;
6330 }
6331
6332 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6333 {
6334 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6335 struct r600_bytecode_alu alu;
6336 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6337 unsigned location;
6338 int input;
6339
6340 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6341
6342 input = inst->Src[0].Register.Index;
6343
6344 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6345 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6346 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6347 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6348 }
6349 else {
6350 location = TGSI_INTERPOLATE_LOC_CENTROID;
6351 }
6352
6353 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6354 if (k < 0)
6355 k = 0;
6356 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6357 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6358
6359 /* NOTE: currently offset is not perspective correct */
6360 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6361 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6362 int sample_gpr = -1;
6363 int gradientsH, gradientsV;
6364 struct r600_bytecode_tex tex;
6365
6366 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6367 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6368 }
6369
6370 gradientsH = r600_get_temp(ctx);
6371 gradientsV = r600_get_temp(ctx);
6372 for (i = 0; i < 2; i++) {
6373 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6374 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6375 tex.src_gpr = interp_gpr;
6376 tex.src_sel_x = interp_base_chan + 0;
6377 tex.src_sel_y = interp_base_chan + 1;
6378 tex.src_sel_z = 0;
6379 tex.src_sel_w = 0;
6380 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6381 tex.dst_sel_x = 0;
6382 tex.dst_sel_y = 1;
6383 tex.dst_sel_z = 7;
6384 tex.dst_sel_w = 7;
6385 tex.inst_mod = 1; // Use per pixel gradient calculation
6386 tex.sampler_id = 0;
6387 tex.resource_id = tex.sampler_id;
6388 r = r600_bytecode_add_tex(ctx->bc, &tex);
6389 if (r)
6390 return r;
6391 }
6392
6393 for (i = 0; i < 2; i++) {
6394 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6395 alu.op = ALU_OP3_MULADD;
6396 alu.is_op3 = 1;
6397 alu.src[0].sel = gradientsH;
6398 alu.src[0].chan = i;
6399 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6400 alu.src[1].sel = sample_gpr;
6401 alu.src[1].chan = 2;
6402 }
6403 else {
6404 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6405 }
6406 alu.src[2].sel = interp_gpr;
6407 alu.src[2].chan = interp_base_chan + i;
6408 alu.dst.sel = ctx->temp_reg;
6409 alu.dst.chan = i;
6410 alu.last = i == 1;
6411
6412 r = r600_bytecode_add_alu(ctx->bc, &alu);
6413 if (r)
6414 return r;
6415 }
6416
6417 for (i = 0; i < 2; i++) {
6418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6419 alu.op = ALU_OP3_MULADD;
6420 alu.is_op3 = 1;
6421 alu.src[0].sel = gradientsV;
6422 alu.src[0].chan = i;
6423 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6424 alu.src[1].sel = sample_gpr;
6425 alu.src[1].chan = 3;
6426 }
6427 else {
6428 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6429 }
6430 alu.src[2].sel = ctx->temp_reg;
6431 alu.src[2].chan = i;
6432 alu.dst.sel = ctx->temp_reg;
6433 alu.dst.chan = i;
6434 alu.last = i == 1;
6435
6436 r = r600_bytecode_add_alu(ctx->bc, &alu);
6437 if (r)
6438 return r;
6439 }
6440 }
6441
6442 tmp = r600_get_temp(ctx);
6443 for (i = 0; i < 8; i++) {
6444 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6445 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6446
6447 alu.dst.sel = tmp;
6448 if ((i > 1 && i < 6)) {
6449 alu.dst.write = 1;
6450 }
6451 else {
6452 alu.dst.write = 0;
6453 }
6454 alu.dst.chan = i % 4;
6455
6456 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6457 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6458 alu.src[0].sel = ctx->temp_reg;
6459 alu.src[0].chan = 1 - (i % 2);
6460 } else {
6461 alu.src[0].sel = interp_gpr;
6462 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6463 }
6464 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6465 alu.src[1].chan = 0;
6466
6467 alu.last = i % 4 == 3;
6468 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6469
6470 r = r600_bytecode_add_alu(ctx->bc, &alu);
6471 if (r)
6472 return r;
6473 }
6474
6475 // INTERP can't swizzle dst
6476 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6477 for (i = 0; i <= lasti; i++) {
6478 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6479 continue;
6480
6481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6482 alu.op = ALU_OP1_MOV;
6483 alu.src[0].sel = tmp;
6484 alu.src[0].chan = ctx->src[0].swizzle[i];
6485 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6486 alu.dst.write = 1;
6487 alu.last = i == lasti;
6488 r = r600_bytecode_add_alu(ctx->bc, &alu);
6489 if (r)
6490 return r;
6491 }
6492
6493 return 0;
6494 }
6495
6496
6497 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6498 {
6499 struct r600_bytecode_alu alu;
6500 int i, r;
6501
6502 for (i = 0; i < 4; i++) {
6503 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6504 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6505 alu.op = ALU_OP0_NOP;
6506 alu.dst.chan = i;
6507 } else {
6508 alu.op = ALU_OP1_MOV;
6509 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6510 alu.src[0].sel = ctx->temp_reg;
6511 alu.src[0].chan = i;
6512 }
6513 if (i == 3) {
6514 alu.last = 1;
6515 }
6516 r = r600_bytecode_add_alu(ctx->bc, &alu);
6517 if (r)
6518 return r;
6519 }
6520 return 0;
6521 }
6522
6523 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6524 unsigned temp, int chan,
6525 struct r600_bytecode_alu_src *bc_src,
6526 const struct r600_shader_src *shader_src)
6527 {
6528 struct r600_bytecode_alu alu;
6529 int r;
6530
6531 r600_bytecode_src(bc_src, shader_src, chan);
6532
6533 /* op3 operands don't support abs modifier */
6534 if (bc_src->abs) {
6535 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6537 alu.op = ALU_OP1_MOV;
6538 alu.dst.sel = temp;
6539 alu.dst.chan = chan;
6540 alu.dst.write = 1;
6541
6542 alu.src[0] = *bc_src;
6543 alu.last = true; // sufficient?
6544 r = r600_bytecode_add_alu(ctx->bc, &alu);
6545 if (r)
6546 return r;
6547
6548 memset(bc_src, 0, sizeof(*bc_src));
6549 bc_src->sel = temp;
6550 bc_src->chan = chan;
6551 }
6552 return 0;
6553 }
6554
6555 static int tgsi_op3(struct r600_shader_ctx *ctx)
6556 {
6557 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6558 struct r600_bytecode_alu alu;
6559 int i, j, r;
6560 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6561 int temp_regs[4];
6562
6563 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6564 temp_regs[j] = 0;
6565 if (ctx->src[j].abs)
6566 temp_regs[j] = r600_get_temp(ctx);
6567 }
6568 for (i = 0; i < lasti + 1; i++) {
6569 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6570 continue;
6571
6572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6573 alu.op = ctx->inst_info->op;
6574 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6575 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6576 if (r)
6577 return r;
6578 }
6579
6580 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6581 alu.dst.chan = i;
6582 alu.dst.write = 1;
6583 alu.is_op3 = 1;
6584 if (i == lasti) {
6585 alu.last = 1;
6586 }
6587 r = r600_bytecode_add_alu(ctx->bc, &alu);
6588 if (r)
6589 return r;
6590 }
6591 return 0;
6592 }
6593
6594 static int tgsi_dp(struct r600_shader_ctx *ctx)
6595 {
6596 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6597 struct r600_bytecode_alu alu;
6598 int i, j, r;
6599
6600 for (i = 0; i < 4; i++) {
6601 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6602 alu.op = ctx->inst_info->op;
6603 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6604 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6605 }
6606
6607 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6608 alu.dst.chan = i;
6609 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6610 /* handle some special cases */
6611 switch (inst->Instruction.Opcode) {
6612 case TGSI_OPCODE_DP2:
6613 if (i > 1) {
6614 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6615 alu.src[0].chan = alu.src[1].chan = 0;
6616 }
6617 break;
6618 case TGSI_OPCODE_DP3:
6619 if (i > 2) {
6620 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6621 alu.src[0].chan = alu.src[1].chan = 0;
6622 }
6623 break;
6624 case TGSI_OPCODE_DPH:
6625 if (i == 3) {
6626 alu.src[0].sel = V_SQ_ALU_SRC_1;
6627 alu.src[0].chan = 0;
6628 alu.src[0].neg = 0;
6629 }
6630 break;
6631 default:
6632 break;
6633 }
6634 if (i == 3) {
6635 alu.last = 1;
6636 }
6637 r = r600_bytecode_add_alu(ctx->bc, &alu);
6638 if (r)
6639 return r;
6640 }
6641 return 0;
6642 }
6643
6644 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6645 unsigned index)
6646 {
6647 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6648 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6649 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6650 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6651 ctx->src[index].neg || ctx->src[index].abs ||
6652 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
6653 }
6654
6655 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6656 unsigned index)
6657 {
6658 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6659 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6660 }
6661
6662 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6663 {
6664 struct r600_bytecode_vtx vtx;
6665 struct r600_bytecode_alu alu;
6666 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6667 int src_gpr, r, i;
6668 int id = tgsi_tex_get_src_gpr(ctx, 1);
6669
6670 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6671 if (src_requires_loading) {
6672 for (i = 0; i < 4; i++) {
6673 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6674 alu.op = ALU_OP1_MOV;
6675 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6676 alu.dst.sel = ctx->temp_reg;
6677 alu.dst.chan = i;
6678 if (i == 3)
6679 alu.last = 1;
6680 alu.dst.write = 1;
6681 r = r600_bytecode_add_alu(ctx->bc, &alu);
6682 if (r)
6683 return r;
6684 }
6685 src_gpr = ctx->temp_reg;
6686 }
6687
6688 memset(&vtx, 0, sizeof(vtx));
6689 vtx.op = FETCH_OP_VFETCH;
6690 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6691 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6692 vtx.src_gpr = src_gpr;
6693 vtx.mega_fetch_count = 16;
6694 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6695 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6696 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6697 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6698 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6699 vtx.use_const_fields = 1;
6700
6701 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6702 return r;
6703
6704 if (ctx->bc->chip_class >= EVERGREEN)
6705 return 0;
6706
6707 for (i = 0; i < 4; i++) {
6708 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6709 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6710 continue;
6711
6712 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6713 alu.op = ALU_OP2_AND_INT;
6714
6715 alu.dst.chan = i;
6716 alu.dst.sel = vtx.dst_gpr;
6717 alu.dst.write = 1;
6718
6719 alu.src[0].sel = vtx.dst_gpr;
6720 alu.src[0].chan = i;
6721
6722 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6723 alu.src[1].sel += (id * 2);
6724 alu.src[1].chan = i % 4;
6725 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6726
6727 if (i == lasti)
6728 alu.last = 1;
6729 r = r600_bytecode_add_alu(ctx->bc, &alu);
6730 if (r)
6731 return r;
6732 }
6733
6734 if (inst->Dst[0].Register.WriteMask & 3) {
6735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6736 alu.op = ALU_OP2_OR_INT;
6737
6738 alu.dst.chan = 3;
6739 alu.dst.sel = vtx.dst_gpr;
6740 alu.dst.write = 1;
6741
6742 alu.src[0].sel = vtx.dst_gpr;
6743 alu.src[0].chan = 3;
6744
6745 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6746 alu.src[1].chan = 0;
6747 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6748
6749 alu.last = 1;
6750 r = r600_bytecode_add_alu(ctx->bc, &alu);
6751 if (r)
6752 return r;
6753 }
6754 return 0;
6755 }
6756
6757 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6758 {
6759 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6760 struct r600_bytecode_alu alu;
6761 int r;
6762 int id = tgsi_tex_get_src_gpr(ctx, 1);
6763
6764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6765 alu.op = ALU_OP1_MOV;
6766 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6767 if (ctx->bc->chip_class >= EVERGREEN) {
6768 /* channel 0 or 2 of each word */
6769 alu.src[0].sel += (id / 2);
6770 alu.src[0].chan = (id % 2) * 2;
6771 } else {
6772 /* r600 we have them at channel 2 of the second dword */
6773 alu.src[0].sel += (id * 2) + 1;
6774 alu.src[0].chan = 1;
6775 }
6776 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6777 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6778 alu.last = 1;
6779 r = r600_bytecode_add_alu(ctx->bc, &alu);
6780 if (r)
6781 return r;
6782 return 0;
6783 }
6784
6785 static int tgsi_tex(struct r600_shader_ctx *ctx)
6786 {
6787 static float one_point_five = 1.5f;
6788 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6789 struct r600_bytecode_tex tex;
6790 struct r600_bytecode_alu alu;
6791 unsigned src_gpr;
6792 int r, i, j;
6793 int opcode;
6794 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6795 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6796 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6797 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6798
6799 bool txf_add_offsets = inst->Texture.NumOffsets &&
6800 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6801 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6802
6803 /* Texture fetch instructions can only use gprs as source.
6804 * Also they cannot negate the source or take the absolute value */
6805 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
6806 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6807 tgsi_tex_src_requires_loading(ctx, 0)) ||
6808 read_compressed_msaa || txf_add_offsets;
6809
6810 boolean src_loaded = FALSE;
6811 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
6812 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6813 boolean has_txq_cube_array_z = false;
6814 unsigned sampler_index_mode;
6815
6816 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6817 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6818 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6819 if (inst->Dst[0].Register.WriteMask & 4) {
6820 ctx->shader->has_txq_cube_array_z_comp = true;
6821 has_txq_cube_array_z = true;
6822 }
6823
6824 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6825 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6826 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6827 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6828 sampler_src_reg = 2;
6829
6830 /* TGSI moves the sampler to src reg 3 for TXD */
6831 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6832 sampler_src_reg = 3;
6833
6834 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6835
6836 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6837
6838 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6839 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6840 ctx->shader->uses_tex_buffers = true;
6841 return r600_do_buffer_txq(ctx);
6842 }
6843 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6844 if (ctx->bc->chip_class < EVERGREEN)
6845 ctx->shader->uses_tex_buffers = true;
6846 return do_vtx_fetch_inst(ctx, src_requires_loading);
6847 }
6848 }
6849
6850 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6851 int out_chan;
6852 /* Add perspective divide */
6853 if (ctx->bc->chip_class == CAYMAN) {
6854 out_chan = 2;
6855 for (i = 0; i < 3; i++) {
6856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6857 alu.op = ALU_OP1_RECIP_IEEE;
6858 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6859
6860 alu.dst.sel = ctx->temp_reg;
6861 alu.dst.chan = i;
6862 if (i == 2)
6863 alu.last = 1;
6864 if (out_chan == i)
6865 alu.dst.write = 1;
6866 r = r600_bytecode_add_alu(ctx->bc, &alu);
6867 if (r)
6868 return r;
6869 }
6870
6871 } else {
6872 out_chan = 3;
6873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6874 alu.op = ALU_OP1_RECIP_IEEE;
6875 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6876
6877 alu.dst.sel = ctx->temp_reg;
6878 alu.dst.chan = out_chan;
6879 alu.last = 1;
6880 alu.dst.write = 1;
6881 r = r600_bytecode_add_alu(ctx->bc, &alu);
6882 if (r)
6883 return r;
6884 }
6885
6886 for (i = 0; i < 3; i++) {
6887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6888 alu.op = ALU_OP2_MUL;
6889 alu.src[0].sel = ctx->temp_reg;
6890 alu.src[0].chan = out_chan;
6891 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6892 alu.dst.sel = ctx->temp_reg;
6893 alu.dst.chan = i;
6894 alu.dst.write = 1;
6895 r = r600_bytecode_add_alu(ctx->bc, &alu);
6896 if (r)
6897 return r;
6898 }
6899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6900 alu.op = ALU_OP1_MOV;
6901 alu.src[0].sel = V_SQ_ALU_SRC_1;
6902 alu.src[0].chan = 0;
6903 alu.dst.sel = ctx->temp_reg;
6904 alu.dst.chan = 3;
6905 alu.last = 1;
6906 alu.dst.write = 1;
6907 r = r600_bytecode_add_alu(ctx->bc, &alu);
6908 if (r)
6909 return r;
6910 src_loaded = TRUE;
6911 src_gpr = ctx->temp_reg;
6912 }
6913
6914
6915 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6916 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6917 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6918 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6919 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
6920 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
6921
6922 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6923 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6924
6925 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6926 for (i = 0; i < 4; i++) {
6927 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6928 alu.op = ALU_OP2_CUBE;
6929 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6930 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6931 alu.dst.sel = ctx->temp_reg;
6932 alu.dst.chan = i;
6933 if (i == 3)
6934 alu.last = 1;
6935 alu.dst.write = 1;
6936 r = r600_bytecode_add_alu(ctx->bc, &alu);
6937 if (r)
6938 return r;
6939 }
6940
6941 /* tmp1.z = RCP_e(|tmp1.z|) */
6942 if (ctx->bc->chip_class == CAYMAN) {
6943 for (i = 0; i < 3; i++) {
6944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6945 alu.op = ALU_OP1_RECIP_IEEE;
6946 alu.src[0].sel = ctx->temp_reg;
6947 alu.src[0].chan = 2;
6948 alu.src[0].abs = 1;
6949 alu.dst.sel = ctx->temp_reg;
6950 alu.dst.chan = i;
6951 if (i == 2)
6952 alu.dst.write = 1;
6953 if (i == 2)
6954 alu.last = 1;
6955 r = r600_bytecode_add_alu(ctx->bc, &alu);
6956 if (r)
6957 return r;
6958 }
6959 } else {
6960 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6961 alu.op = ALU_OP1_RECIP_IEEE;
6962 alu.src[0].sel = ctx->temp_reg;
6963 alu.src[0].chan = 2;
6964 alu.src[0].abs = 1;
6965 alu.dst.sel = ctx->temp_reg;
6966 alu.dst.chan = 2;
6967 alu.dst.write = 1;
6968 alu.last = 1;
6969 r = r600_bytecode_add_alu(ctx->bc, &alu);
6970 if (r)
6971 return r;
6972 }
6973
6974 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6975 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6976 * muladd has no writemask, have to use another temp
6977 */
6978 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6979 alu.op = ALU_OP3_MULADD;
6980 alu.is_op3 = 1;
6981
6982 alu.src[0].sel = ctx->temp_reg;
6983 alu.src[0].chan = 0;
6984 alu.src[1].sel = ctx->temp_reg;
6985 alu.src[1].chan = 2;
6986
6987 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6988 alu.src[2].chan = 0;
6989 alu.src[2].value = *(uint32_t *)&one_point_five;
6990
6991 alu.dst.sel = ctx->temp_reg;
6992 alu.dst.chan = 0;
6993 alu.dst.write = 1;
6994
6995 r = r600_bytecode_add_alu(ctx->bc, &alu);
6996 if (r)
6997 return r;
6998
6999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7000 alu.op = ALU_OP3_MULADD;
7001 alu.is_op3 = 1;
7002
7003 alu.src[0].sel = ctx->temp_reg;
7004 alu.src[0].chan = 1;
7005 alu.src[1].sel = ctx->temp_reg;
7006 alu.src[1].chan = 2;
7007
7008 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7009 alu.src[2].chan = 0;
7010 alu.src[2].value = *(uint32_t *)&one_point_five;
7011
7012 alu.dst.sel = ctx->temp_reg;
7013 alu.dst.chan = 1;
7014 alu.dst.write = 1;
7015
7016 alu.last = 1;
7017 r = r600_bytecode_add_alu(ctx->bc, &alu);
7018 if (r)
7019 return r;
7020 /* write initial compare value into Z component
7021 - W src 0 for shadow cube
7022 - X src 1 for shadow cube array */
7023 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7024 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7026 alu.op = ALU_OP1_MOV;
7027 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7028 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7029 else
7030 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7031 alu.dst.sel = ctx->temp_reg;
7032 alu.dst.chan = 2;
7033 alu.dst.write = 1;
7034 alu.last = 1;
7035 r = r600_bytecode_add_alu(ctx->bc, &alu);
7036 if (r)
7037 return r;
7038 }
7039
7040 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7041 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7042 if (ctx->bc->chip_class >= EVERGREEN) {
7043 int mytmp = r600_get_temp(ctx);
7044 static const float eight = 8.0f;
7045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7046 alu.op = ALU_OP1_MOV;
7047 alu.src[0].sel = ctx->temp_reg;
7048 alu.src[0].chan = 3;
7049 alu.dst.sel = mytmp;
7050 alu.dst.chan = 0;
7051 alu.dst.write = 1;
7052 alu.last = 1;
7053 r = r600_bytecode_add_alu(ctx->bc, &alu);
7054 if (r)
7055 return r;
7056
7057 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7059 alu.op = ALU_OP3_MULADD;
7060 alu.is_op3 = 1;
7061 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7062 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7063 alu.src[1].chan = 0;
7064 alu.src[1].value = *(uint32_t *)&eight;
7065 alu.src[2].sel = mytmp;
7066 alu.src[2].chan = 0;
7067 alu.dst.sel = ctx->temp_reg;
7068 alu.dst.chan = 3;
7069 alu.dst.write = 1;
7070 alu.last = 1;
7071 r = r600_bytecode_add_alu(ctx->bc, &alu);
7072 if (r)
7073 return r;
7074 } else if (ctx->bc->chip_class < EVERGREEN) {
7075 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7076 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7077 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7078 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7079 tex.src_gpr = r600_get_temp(ctx);
7080 tex.src_sel_x = 0;
7081 tex.src_sel_y = 0;
7082 tex.src_sel_z = 0;
7083 tex.src_sel_w = 0;
7084 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7085 tex.coord_type_x = 1;
7086 tex.coord_type_y = 1;
7087 tex.coord_type_z = 1;
7088 tex.coord_type_w = 1;
7089 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7090 alu.op = ALU_OP1_MOV;
7091 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7092 alu.dst.sel = tex.src_gpr;
7093 alu.dst.chan = 0;
7094 alu.last = 1;
7095 alu.dst.write = 1;
7096 r = r600_bytecode_add_alu(ctx->bc, &alu);
7097 if (r)
7098 return r;
7099
7100 r = r600_bytecode_add_tex(ctx->bc, &tex);
7101 if (r)
7102 return r;
7103 }
7104
7105 }
7106
7107 /* for cube forms of lod and bias we need to route things */
7108 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7109 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7110 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7111 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7112 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7113 alu.op = ALU_OP1_MOV;
7114 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7115 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7116 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7117 else
7118 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7119 alu.dst.sel = ctx->temp_reg;
7120 alu.dst.chan = 2;
7121 alu.last = 1;
7122 alu.dst.write = 1;
7123 r = r600_bytecode_add_alu(ctx->bc, &alu);
7124 if (r)
7125 return r;
7126 }
7127
7128 src_loaded = TRUE;
7129 src_gpr = ctx->temp_reg;
7130 }
7131
7132 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7133 int temp_h = 0, temp_v = 0;
7134 int start_val = 0;
7135
7136 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7137 if (src_loaded == TRUE)
7138 start_val = 1;
7139 else
7140 src_loaded = TRUE;
7141 for (i = start_val; i < 3; i++) {
7142 int treg = r600_get_temp(ctx);
7143
7144 if (i == 0)
7145 src_gpr = treg;
7146 else if (i == 1)
7147 temp_h = treg;
7148 else
7149 temp_v = treg;
7150
7151 for (j = 0; j < 4; j++) {
7152 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7153 alu.op = ALU_OP1_MOV;
7154 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7155 alu.dst.sel = treg;
7156 alu.dst.chan = j;
7157 if (j == 3)
7158 alu.last = 1;
7159 alu.dst.write = 1;
7160 r = r600_bytecode_add_alu(ctx->bc, &alu);
7161 if (r)
7162 return r;
7163 }
7164 }
7165 for (i = 1; i < 3; i++) {
7166 /* set gradients h/v */
7167 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7168 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7169 FETCH_OP_SET_GRADIENTS_V;
7170 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7171 tex.sampler_index_mode = sampler_index_mode;
7172 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7173 tex.resource_index_mode = sampler_index_mode;
7174
7175 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7176 tex.src_sel_x = 0;
7177 tex.src_sel_y = 1;
7178 tex.src_sel_z = 2;
7179 tex.src_sel_w = 3;
7180
7181 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7182 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7183 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7184 tex.coord_type_x = 1;
7185 tex.coord_type_y = 1;
7186 tex.coord_type_z = 1;
7187 tex.coord_type_w = 1;
7188 }
7189 r = r600_bytecode_add_tex(ctx->bc, &tex);
7190 if (r)
7191 return r;
7192 }
7193 }
7194
7195 if (src_requires_loading && !src_loaded) {
7196 for (i = 0; i < 4; i++) {
7197 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7198 alu.op = ALU_OP1_MOV;
7199 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7200 alu.dst.sel = ctx->temp_reg;
7201 alu.dst.chan = i;
7202 if (i == 3)
7203 alu.last = 1;
7204 alu.dst.write = 1;
7205 r = r600_bytecode_add_alu(ctx->bc, &alu);
7206 if (r)
7207 return r;
7208 }
7209 src_loaded = TRUE;
7210 src_gpr = ctx->temp_reg;
7211 }
7212
7213 /* get offset values */
7214 if (inst->Texture.NumOffsets) {
7215 assert(inst->Texture.NumOffsets == 1);
7216
7217 /* The texture offset feature doesn't work with the TXF instruction
7218 * and must be emulated by adding the offset to the texture coordinates. */
7219 if (txf_add_offsets) {
7220 const struct tgsi_texture_offset *off = inst->TexOffsets;
7221
7222 switch (inst->Texture.Texture) {
7223 case TGSI_TEXTURE_3D:
7224 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7225 alu.op = ALU_OP2_ADD_INT;
7226 alu.src[0].sel = src_gpr;
7227 alu.src[0].chan = 2;
7228 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7229 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7230 alu.dst.sel = src_gpr;
7231 alu.dst.chan = 2;
7232 alu.dst.write = 1;
7233 alu.last = 1;
7234 r = r600_bytecode_add_alu(ctx->bc, &alu);
7235 if (r)
7236 return r;
7237 /* fall through */
7238
7239 case TGSI_TEXTURE_2D:
7240 case TGSI_TEXTURE_SHADOW2D:
7241 case TGSI_TEXTURE_RECT:
7242 case TGSI_TEXTURE_SHADOWRECT:
7243 case TGSI_TEXTURE_2D_ARRAY:
7244 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7245 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7246 alu.op = ALU_OP2_ADD_INT;
7247 alu.src[0].sel = src_gpr;
7248 alu.src[0].chan = 1;
7249 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7250 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7251 alu.dst.sel = src_gpr;
7252 alu.dst.chan = 1;
7253 alu.dst.write = 1;
7254 alu.last = 1;
7255 r = r600_bytecode_add_alu(ctx->bc, &alu);
7256 if (r)
7257 return r;
7258 /* fall through */
7259
7260 case TGSI_TEXTURE_1D:
7261 case TGSI_TEXTURE_SHADOW1D:
7262 case TGSI_TEXTURE_1D_ARRAY:
7263 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7264 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7265 alu.op = ALU_OP2_ADD_INT;
7266 alu.src[0].sel = src_gpr;
7267 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7268 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7269 alu.dst.sel = src_gpr;
7270 alu.dst.write = 1;
7271 alu.last = 1;
7272 r = r600_bytecode_add_alu(ctx->bc, &alu);
7273 if (r)
7274 return r;
7275 break;
7276 /* texture offsets do not apply to other texture targets */
7277 }
7278 } else {
7279 switch (inst->Texture.Texture) {
7280 case TGSI_TEXTURE_3D:
7281 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7282 /* fallthrough */
7283 case TGSI_TEXTURE_2D:
7284 case TGSI_TEXTURE_SHADOW2D:
7285 case TGSI_TEXTURE_RECT:
7286 case TGSI_TEXTURE_SHADOWRECT:
7287 case TGSI_TEXTURE_2D_ARRAY:
7288 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7289 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7290 /* fallthrough */
7291 case TGSI_TEXTURE_1D:
7292 case TGSI_TEXTURE_SHADOW1D:
7293 case TGSI_TEXTURE_1D_ARRAY:
7294 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7295 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7296 }
7297 }
7298 }
7299
7300 /* Obtain the sample index for reading a compressed MSAA color texture.
7301 * To read the FMASK, we use the ldfptr instruction, which tells us
7302 * where the samples are stored.
7303 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7304 * which is the identity mapping. Each nibble says which physical sample
7305 * should be fetched to get that sample.
7306 *
7307 * Assume src.z contains the sample index. It should be modified like this:
7308 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7309 * Then fetch the texel with src.
7310 */
7311 if (read_compressed_msaa) {
7312 unsigned sample_chan = 3;
7313 unsigned temp = r600_get_temp(ctx);
7314 assert(src_loaded);
7315
7316 /* temp.w = ldfptr() */
7317 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7318 tex.op = FETCH_OP_LD;
7319 tex.inst_mod = 1; /* to indicate this is ldfptr */
7320 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7321 tex.sampler_index_mode = sampler_index_mode;
7322 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7323 tex.resource_index_mode = sampler_index_mode;
7324 tex.src_gpr = src_gpr;
7325 tex.dst_gpr = temp;
7326 tex.dst_sel_x = 7; /* mask out these components */
7327 tex.dst_sel_y = 7;
7328 tex.dst_sel_z = 7;
7329 tex.dst_sel_w = 0; /* store X */
7330 tex.src_sel_x = 0;
7331 tex.src_sel_y = 1;
7332 tex.src_sel_z = 2;
7333 tex.src_sel_w = 3;
7334 tex.offset_x = offset_x;
7335 tex.offset_y = offset_y;
7336 tex.offset_z = offset_z;
7337 r = r600_bytecode_add_tex(ctx->bc, &tex);
7338 if (r)
7339 return r;
7340
7341 /* temp.x = sample_index*4 */
7342 if (ctx->bc->chip_class == CAYMAN) {
7343 for (i = 0 ; i < 4; i++) {
7344 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7345 alu.op = ALU_OP2_MULLO_INT;
7346 alu.src[0].sel = src_gpr;
7347 alu.src[0].chan = sample_chan;
7348 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7349 alu.src[1].value = 4;
7350 alu.dst.sel = temp;
7351 alu.dst.chan = i;
7352 alu.dst.write = i == 0;
7353 if (i == 3)
7354 alu.last = 1;
7355 r = r600_bytecode_add_alu(ctx->bc, &alu);
7356 if (r)
7357 return r;
7358 }
7359 } else {
7360 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7361 alu.op = ALU_OP2_MULLO_INT;
7362 alu.src[0].sel = src_gpr;
7363 alu.src[0].chan = sample_chan;
7364 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7365 alu.src[1].value = 4;
7366 alu.dst.sel = temp;
7367 alu.dst.chan = 0;
7368 alu.dst.write = 1;
7369 alu.last = 1;
7370 r = r600_bytecode_add_alu(ctx->bc, &alu);
7371 if (r)
7372 return r;
7373 }
7374
7375 /* sample_index = temp.w >> temp.x */
7376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7377 alu.op = ALU_OP2_LSHR_INT;
7378 alu.src[0].sel = temp;
7379 alu.src[0].chan = 3;
7380 alu.src[1].sel = temp;
7381 alu.src[1].chan = 0;
7382 alu.dst.sel = src_gpr;
7383 alu.dst.chan = sample_chan;
7384 alu.dst.write = 1;
7385 alu.last = 1;
7386 r = r600_bytecode_add_alu(ctx->bc, &alu);
7387 if (r)
7388 return r;
7389
7390 /* sample_index & 0xF */
7391 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7392 alu.op = ALU_OP2_AND_INT;
7393 alu.src[0].sel = src_gpr;
7394 alu.src[0].chan = sample_chan;
7395 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7396 alu.src[1].value = 0xF;
7397 alu.dst.sel = src_gpr;
7398 alu.dst.chan = sample_chan;
7399 alu.dst.write = 1;
7400 alu.last = 1;
7401 r = r600_bytecode_add_alu(ctx->bc, &alu);
7402 if (r)
7403 return r;
7404 #if 0
7405 /* visualize the FMASK */
7406 for (i = 0; i < 4; i++) {
7407 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7408 alu.op = ALU_OP1_INT_TO_FLT;
7409 alu.src[0].sel = src_gpr;
7410 alu.src[0].chan = sample_chan;
7411 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7412 alu.dst.chan = i;
7413 alu.dst.write = 1;
7414 alu.last = 1;
7415 r = r600_bytecode_add_alu(ctx->bc, &alu);
7416 if (r)
7417 return r;
7418 }
7419 return 0;
7420 #endif
7421 }
7422
7423 /* does this shader want a num layers from TXQ for a cube array? */
7424 if (has_txq_cube_array_z) {
7425 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7426
7427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7428 alu.op = ALU_OP1_MOV;
7429
7430 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7431 if (ctx->bc->chip_class >= EVERGREEN) {
7432 /* channel 1 or 3 of each word */
7433 alu.src[0].sel += (id / 2);
7434 alu.src[0].chan = ((id % 2) * 2) + 1;
7435 } else {
7436 /* r600 we have them at channel 2 of the second dword */
7437 alu.src[0].sel += (id * 2) + 1;
7438 alu.src[0].chan = 2;
7439 }
7440 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7441 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7442 alu.last = 1;
7443 r = r600_bytecode_add_alu(ctx->bc, &alu);
7444 if (r)
7445 return r;
7446 /* disable writemask from texture instruction */
7447 inst->Dst[0].Register.WriteMask &= ~4;
7448 }
7449
7450 opcode = ctx->inst_info->op;
7451 if (opcode == FETCH_OP_GATHER4 &&
7452 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7453 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7454 opcode = FETCH_OP_GATHER4_O;
7455
7456 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7457 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7458 encoded in the instruction are ignored. */
7459 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7460 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7461 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7462 tex.sampler_index_mode = sampler_index_mode;
7463 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7464 tex.resource_index_mode = sampler_index_mode;
7465
7466 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7467 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7468 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7469 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7470 tex.src_sel_w = 4;
7471
7472 tex.dst_sel_x = 7;
7473 tex.dst_sel_y = 7;
7474 tex.dst_sel_z = 7;
7475 tex.dst_sel_w = 7;
7476
7477 r = r600_bytecode_add_tex(ctx->bc, &tex);
7478 if (r)
7479 return r;
7480 }
7481
7482 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7483 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7484 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7485 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7486 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7487 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7488 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7489 switch (opcode) {
7490 case FETCH_OP_SAMPLE:
7491 opcode = FETCH_OP_SAMPLE_C;
7492 break;
7493 case FETCH_OP_SAMPLE_L:
7494 opcode = FETCH_OP_SAMPLE_C_L;
7495 break;
7496 case FETCH_OP_SAMPLE_LB:
7497 opcode = FETCH_OP_SAMPLE_C_LB;
7498 break;
7499 case FETCH_OP_SAMPLE_G:
7500 opcode = FETCH_OP_SAMPLE_C_G;
7501 break;
7502 /* Texture gather variants */
7503 case FETCH_OP_GATHER4:
7504 opcode = FETCH_OP_GATHER4_C;
7505 break;
7506 case FETCH_OP_GATHER4_O:
7507 opcode = FETCH_OP_GATHER4_C_O;
7508 break;
7509 }
7510 }
7511
7512 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7513 tex.op = opcode;
7514
7515 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7516 tex.sampler_index_mode = sampler_index_mode;
7517 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7518 tex.resource_index_mode = sampler_index_mode;
7519 tex.src_gpr = src_gpr;
7520 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7521
7522 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7523 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7524 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7525 }
7526
7527 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7528 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7529 tex.inst_mod = texture_component_select;
7530
7531 if (ctx->bc->chip_class == CAYMAN) {
7532 /* GATHER4 result order is different from TGSI TG4 */
7533 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7534 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7535 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7536 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7537 } else {
7538 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7539 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7540 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7541 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7542 }
7543 }
7544 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7545 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7546 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7547 tex.dst_sel_z = 7;
7548 tex.dst_sel_w = 7;
7549 }
7550 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7551 tex.dst_sel_x = 3;
7552 tex.dst_sel_y = 7;
7553 tex.dst_sel_z = 7;
7554 tex.dst_sel_w = 7;
7555 }
7556 else {
7557 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7558 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7559 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7560 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7561 }
7562
7563
7564 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
7565 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7566 tex.src_sel_x = 4;
7567 tex.src_sel_y = 4;
7568 tex.src_sel_z = 4;
7569 tex.src_sel_w = 4;
7570 } else if (src_loaded) {
7571 tex.src_sel_x = 0;
7572 tex.src_sel_y = 1;
7573 tex.src_sel_z = 2;
7574 tex.src_sel_w = 3;
7575 } else {
7576 tex.src_sel_x = ctx->src[0].swizzle[0];
7577 tex.src_sel_y = ctx->src[0].swizzle[1];
7578 tex.src_sel_z = ctx->src[0].swizzle[2];
7579 tex.src_sel_w = ctx->src[0].swizzle[3];
7580 tex.src_rel = ctx->src[0].rel;
7581 }
7582
7583 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7584 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7585 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7586 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7587 tex.src_sel_x = 1;
7588 tex.src_sel_y = 0;
7589 tex.src_sel_z = 3;
7590 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7591 }
7592
7593 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7594 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7595 tex.coord_type_x = 1;
7596 tex.coord_type_y = 1;
7597 }
7598 tex.coord_type_z = 1;
7599 tex.coord_type_w = 1;
7600
7601 tex.offset_x = offset_x;
7602 tex.offset_y = offset_y;
7603 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7604 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7605 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7606 tex.offset_z = 0;
7607 }
7608 else {
7609 tex.offset_z = offset_z;
7610 }
7611
7612 /* Put the depth for comparison in W.
7613 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7614 * Some instructions expect the depth in Z. */
7615 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7616 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7617 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7618 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7619 opcode != FETCH_OP_SAMPLE_C_L &&
7620 opcode != FETCH_OP_SAMPLE_C_LB) {
7621 tex.src_sel_w = tex.src_sel_z;
7622 }
7623
7624 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7625 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7626 if (opcode == FETCH_OP_SAMPLE_C_L ||
7627 opcode == FETCH_OP_SAMPLE_C_LB) {
7628 /* the array index is read from Y */
7629 tex.coord_type_y = 0;
7630 } else {
7631 /* the array index is read from Z */
7632 tex.coord_type_z = 0;
7633 tex.src_sel_z = tex.src_sel_y;
7634 }
7635 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7636 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7637 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7638 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7639 (ctx->bc->chip_class >= EVERGREEN)))
7640 /* the array index is read from Z */
7641 tex.coord_type_z = 0;
7642
7643 /* mask unused source components */
7644 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7645 switch (inst->Texture.Texture) {
7646 case TGSI_TEXTURE_2D:
7647 case TGSI_TEXTURE_RECT:
7648 tex.src_sel_z = 7;
7649 tex.src_sel_w = 7;
7650 break;
7651 case TGSI_TEXTURE_1D_ARRAY:
7652 tex.src_sel_y = 7;
7653 tex.src_sel_w = 7;
7654 break;
7655 case TGSI_TEXTURE_1D:
7656 tex.src_sel_y = 7;
7657 tex.src_sel_z = 7;
7658 tex.src_sel_w = 7;
7659 break;
7660 }
7661 }
7662
7663 r = r600_bytecode_add_tex(ctx->bc, &tex);
7664 if (r)
7665 return r;
7666
7667 /* add shadow ambient support - gallium doesn't do it yet */
7668 return 0;
7669 }
7670
7671 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7672 {
7673 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7674 struct r600_bytecode_alu alu;
7675 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7676 unsigned i, temp_regs[2];
7677 int r;
7678
7679 /* optimize if it's just an equal balance */
7680 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7681 for (i = 0; i < lasti + 1; i++) {
7682 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7683 continue;
7684
7685 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7686 alu.op = ALU_OP2_ADD;
7687 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7688 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7689 alu.omod = 3;
7690 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7691 alu.dst.chan = i;
7692 if (i == lasti) {
7693 alu.last = 1;
7694 }
7695 r = r600_bytecode_add_alu(ctx->bc, &alu);
7696 if (r)
7697 return r;
7698 }
7699 return 0;
7700 }
7701
7702 /* 1 - src0 */
7703 for (i = 0; i < lasti + 1; i++) {
7704 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7705 continue;
7706
7707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7708 alu.op = ALU_OP2_ADD;
7709 alu.src[0].sel = V_SQ_ALU_SRC_1;
7710 alu.src[0].chan = 0;
7711 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7712 r600_bytecode_src_toggle_neg(&alu.src[1]);
7713 alu.dst.sel = ctx->temp_reg;
7714 alu.dst.chan = i;
7715 if (i == lasti) {
7716 alu.last = 1;
7717 }
7718 alu.dst.write = 1;
7719 r = r600_bytecode_add_alu(ctx->bc, &alu);
7720 if (r)
7721 return r;
7722 }
7723
7724 /* (1 - src0) * src2 */
7725 for (i = 0; i < lasti + 1; i++) {
7726 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7727 continue;
7728
7729 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7730 alu.op = ALU_OP2_MUL;
7731 alu.src[0].sel = ctx->temp_reg;
7732 alu.src[0].chan = i;
7733 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7734 alu.dst.sel = ctx->temp_reg;
7735 alu.dst.chan = i;
7736 if (i == lasti) {
7737 alu.last = 1;
7738 }
7739 alu.dst.write = 1;
7740 r = r600_bytecode_add_alu(ctx->bc, &alu);
7741 if (r)
7742 return r;
7743 }
7744
7745 /* src0 * src1 + (1 - src0) * src2 */
7746 if (ctx->src[0].abs)
7747 temp_regs[0] = r600_get_temp(ctx);
7748 else
7749 temp_regs[0] = 0;
7750 if (ctx->src[1].abs)
7751 temp_regs[1] = r600_get_temp(ctx);
7752 else
7753 temp_regs[1] = 0;
7754
7755 for (i = 0; i < lasti + 1; i++) {
7756 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7757 continue;
7758
7759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7760 alu.op = ALU_OP3_MULADD;
7761 alu.is_op3 = 1;
7762 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7763 if (r)
7764 return r;
7765 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7766 if (r)
7767 return r;
7768 alu.src[2].sel = ctx->temp_reg;
7769 alu.src[2].chan = i;
7770
7771 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7772 alu.dst.chan = i;
7773 if (i == lasti) {
7774 alu.last = 1;
7775 }
7776 r = r600_bytecode_add_alu(ctx->bc, &alu);
7777 if (r)
7778 return r;
7779 }
7780 return 0;
7781 }
7782
7783 static int tgsi_cmp(struct r600_shader_ctx *ctx)
7784 {
7785 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7786 struct r600_bytecode_alu alu;
7787 int i, r, j;
7788 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7789 int temp_regs[3];
7790
7791 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7792 temp_regs[j] = 0;
7793 if (ctx->src[j].abs)
7794 temp_regs[j] = r600_get_temp(ctx);
7795 }
7796
7797 for (i = 0; i < lasti + 1; i++) {
7798 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7799 continue;
7800
7801 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7802 alu.op = ALU_OP3_CNDGE;
7803 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7804 if (r)
7805 return r;
7806 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
7807 if (r)
7808 return r;
7809 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
7810 if (r)
7811 return r;
7812 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7813 alu.dst.chan = i;
7814 alu.dst.write = 1;
7815 alu.is_op3 = 1;
7816 if (i == lasti)
7817 alu.last = 1;
7818 r = r600_bytecode_add_alu(ctx->bc, &alu);
7819 if (r)
7820 return r;
7821 }
7822 return 0;
7823 }
7824
7825 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
7826 {
7827 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7828 struct r600_bytecode_alu alu;
7829 int i, r;
7830 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7831
7832 for (i = 0; i < lasti + 1; i++) {
7833 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7834 continue;
7835
7836 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7837 alu.op = ALU_OP3_CNDE_INT;
7838 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7839 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7840 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
7841 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7842 alu.dst.chan = i;
7843 alu.dst.write = 1;
7844 alu.is_op3 = 1;
7845 if (i == lasti)
7846 alu.last = 1;
7847 r = r600_bytecode_add_alu(ctx->bc, &alu);
7848 if (r)
7849 return r;
7850 }
7851 return 0;
7852 }
7853
7854 static int tgsi_xpd(struct r600_shader_ctx *ctx)
7855 {
7856 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7857 static const unsigned int src0_swizzle[] = {2, 0, 1};
7858 static const unsigned int src1_swizzle[] = {1, 2, 0};
7859 struct r600_bytecode_alu alu;
7860 uint32_t use_temp = 0;
7861 int i, r;
7862
7863 if (inst->Dst[0].Register.WriteMask != 0xf)
7864 use_temp = 1;
7865
7866 for (i = 0; i < 4; i++) {
7867 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7868 alu.op = ALU_OP2_MUL;
7869 if (i < 3) {
7870 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7871 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
7872 } else {
7873 alu.src[0].sel = V_SQ_ALU_SRC_0;
7874 alu.src[0].chan = i;
7875 alu.src[1].sel = V_SQ_ALU_SRC_0;
7876 alu.src[1].chan = i;
7877 }
7878
7879 alu.dst.sel = ctx->temp_reg;
7880 alu.dst.chan = i;
7881 alu.dst.write = 1;
7882
7883 if (i == 3)
7884 alu.last = 1;
7885 r = r600_bytecode_add_alu(ctx->bc, &alu);
7886 if (r)
7887 return r;
7888 }
7889
7890 for (i = 0; i < 4; i++) {
7891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7892 alu.op = ALU_OP3_MULADD;
7893
7894 if (i < 3) {
7895 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
7896 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
7897 } else {
7898 alu.src[0].sel = V_SQ_ALU_SRC_0;
7899 alu.src[0].chan = i;
7900 alu.src[1].sel = V_SQ_ALU_SRC_0;
7901 alu.src[1].chan = i;
7902 }
7903
7904 alu.src[2].sel = ctx->temp_reg;
7905 alu.src[2].neg = 1;
7906 alu.src[2].chan = i;
7907
7908 if (use_temp)
7909 alu.dst.sel = ctx->temp_reg;
7910 else
7911 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7912 alu.dst.chan = i;
7913 alu.dst.write = 1;
7914 alu.is_op3 = 1;
7915 if (i == 3)
7916 alu.last = 1;
7917 r = r600_bytecode_add_alu(ctx->bc, &alu);
7918 if (r)
7919 return r;
7920 }
7921 if (use_temp)
7922 return tgsi_helper_copy(ctx, inst);
7923 return 0;
7924 }
7925
7926 static int tgsi_exp(struct r600_shader_ctx *ctx)
7927 {
7928 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7929 struct r600_bytecode_alu alu;
7930 int r;
7931 int i;
7932
7933 /* result.x = 2^floor(src); */
7934 if (inst->Dst[0].Register.WriteMask & 1) {
7935 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7936
7937 alu.op = ALU_OP1_FLOOR;
7938 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7939
7940 alu.dst.sel = ctx->temp_reg;
7941 alu.dst.chan = 0;
7942 alu.dst.write = 1;
7943 alu.last = 1;
7944 r = r600_bytecode_add_alu(ctx->bc, &alu);
7945 if (r)
7946 return r;
7947
7948 if (ctx->bc->chip_class == CAYMAN) {
7949 for (i = 0; i < 3; i++) {
7950 alu.op = ALU_OP1_EXP_IEEE;
7951 alu.src[0].sel = ctx->temp_reg;
7952 alu.src[0].chan = 0;
7953
7954 alu.dst.sel = ctx->temp_reg;
7955 alu.dst.chan = i;
7956 alu.dst.write = i == 0;
7957 alu.last = i == 2;
7958 r = r600_bytecode_add_alu(ctx->bc, &alu);
7959 if (r)
7960 return r;
7961 }
7962 } else {
7963 alu.op = ALU_OP1_EXP_IEEE;
7964 alu.src[0].sel = ctx->temp_reg;
7965 alu.src[0].chan = 0;
7966
7967 alu.dst.sel = ctx->temp_reg;
7968 alu.dst.chan = 0;
7969 alu.dst.write = 1;
7970 alu.last = 1;
7971 r = r600_bytecode_add_alu(ctx->bc, &alu);
7972 if (r)
7973 return r;
7974 }
7975 }
7976
7977 /* result.y = tmp - floor(tmp); */
7978 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7980
7981 alu.op = ALU_OP1_FRACT;
7982 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7983
7984 alu.dst.sel = ctx->temp_reg;
7985 #if 0
7986 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7987 if (r)
7988 return r;
7989 #endif
7990 alu.dst.write = 1;
7991 alu.dst.chan = 1;
7992
7993 alu.last = 1;
7994
7995 r = r600_bytecode_add_alu(ctx->bc, &alu);
7996 if (r)
7997 return r;
7998 }
7999
8000 /* result.z = RoughApprox2ToX(tmp);*/
8001 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8002 if (ctx->bc->chip_class == CAYMAN) {
8003 for (i = 0; i < 3; i++) {
8004 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8005 alu.op = ALU_OP1_EXP_IEEE;
8006 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8007
8008 alu.dst.sel = ctx->temp_reg;
8009 alu.dst.chan = i;
8010 if (i == 2) {
8011 alu.dst.write = 1;
8012 alu.last = 1;
8013 }
8014
8015 r = r600_bytecode_add_alu(ctx->bc, &alu);
8016 if (r)
8017 return r;
8018 }
8019 } else {
8020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8021 alu.op = ALU_OP1_EXP_IEEE;
8022 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8023
8024 alu.dst.sel = ctx->temp_reg;
8025 alu.dst.write = 1;
8026 alu.dst.chan = 2;
8027
8028 alu.last = 1;
8029
8030 r = r600_bytecode_add_alu(ctx->bc, &alu);
8031 if (r)
8032 return r;
8033 }
8034 }
8035
8036 /* result.w = 1.0;*/
8037 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8039
8040 alu.op = ALU_OP1_MOV;
8041 alu.src[0].sel = V_SQ_ALU_SRC_1;
8042 alu.src[0].chan = 0;
8043
8044 alu.dst.sel = ctx->temp_reg;
8045 alu.dst.chan = 3;
8046 alu.dst.write = 1;
8047 alu.last = 1;
8048 r = r600_bytecode_add_alu(ctx->bc, &alu);
8049 if (r)
8050 return r;
8051 }
8052 return tgsi_helper_copy(ctx, inst);
8053 }
8054
8055 static int tgsi_log(struct r600_shader_ctx *ctx)
8056 {
8057 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8058 struct r600_bytecode_alu alu;
8059 int r;
8060 int i;
8061
8062 /* result.x = floor(log2(|src|)); */
8063 if (inst->Dst[0].Register.WriteMask & 1) {
8064 if (ctx->bc->chip_class == CAYMAN) {
8065 for (i = 0; i < 3; i++) {
8066 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8067
8068 alu.op = ALU_OP1_LOG_IEEE;
8069 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8070 r600_bytecode_src_set_abs(&alu.src[0]);
8071
8072 alu.dst.sel = ctx->temp_reg;
8073 alu.dst.chan = i;
8074 if (i == 0)
8075 alu.dst.write = 1;
8076 if (i == 2)
8077 alu.last = 1;
8078 r = r600_bytecode_add_alu(ctx->bc, &alu);
8079 if (r)
8080 return r;
8081 }
8082
8083 } else {
8084 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8085
8086 alu.op = ALU_OP1_LOG_IEEE;
8087 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8088 r600_bytecode_src_set_abs(&alu.src[0]);
8089
8090 alu.dst.sel = ctx->temp_reg;
8091 alu.dst.chan = 0;
8092 alu.dst.write = 1;
8093 alu.last = 1;
8094 r = r600_bytecode_add_alu(ctx->bc, &alu);
8095 if (r)
8096 return r;
8097 }
8098
8099 alu.op = ALU_OP1_FLOOR;
8100 alu.src[0].sel = ctx->temp_reg;
8101 alu.src[0].chan = 0;
8102
8103 alu.dst.sel = ctx->temp_reg;
8104 alu.dst.chan = 0;
8105 alu.dst.write = 1;
8106 alu.last = 1;
8107
8108 r = r600_bytecode_add_alu(ctx->bc, &alu);
8109 if (r)
8110 return r;
8111 }
8112
8113 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8114 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8115
8116 if (ctx->bc->chip_class == CAYMAN) {
8117 for (i = 0; i < 3; i++) {
8118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8119
8120 alu.op = ALU_OP1_LOG_IEEE;
8121 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8122 r600_bytecode_src_set_abs(&alu.src[0]);
8123
8124 alu.dst.sel = ctx->temp_reg;
8125 alu.dst.chan = i;
8126 if (i == 1)
8127 alu.dst.write = 1;
8128 if (i == 2)
8129 alu.last = 1;
8130
8131 r = r600_bytecode_add_alu(ctx->bc, &alu);
8132 if (r)
8133 return r;
8134 }
8135 } else {
8136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8137
8138 alu.op = ALU_OP1_LOG_IEEE;
8139 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8140 r600_bytecode_src_set_abs(&alu.src[0]);
8141
8142 alu.dst.sel = ctx->temp_reg;
8143 alu.dst.chan = 1;
8144 alu.dst.write = 1;
8145 alu.last = 1;
8146
8147 r = r600_bytecode_add_alu(ctx->bc, &alu);
8148 if (r)
8149 return r;
8150 }
8151
8152 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8153
8154 alu.op = ALU_OP1_FLOOR;
8155 alu.src[0].sel = ctx->temp_reg;
8156 alu.src[0].chan = 1;
8157
8158 alu.dst.sel = ctx->temp_reg;
8159 alu.dst.chan = 1;
8160 alu.dst.write = 1;
8161 alu.last = 1;
8162
8163 r = r600_bytecode_add_alu(ctx->bc, &alu);
8164 if (r)
8165 return r;
8166
8167 if (ctx->bc->chip_class == CAYMAN) {
8168 for (i = 0; i < 3; i++) {
8169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8170 alu.op = ALU_OP1_EXP_IEEE;
8171 alu.src[0].sel = ctx->temp_reg;
8172 alu.src[0].chan = 1;
8173
8174 alu.dst.sel = ctx->temp_reg;
8175 alu.dst.chan = i;
8176 if (i == 1)
8177 alu.dst.write = 1;
8178 if (i == 2)
8179 alu.last = 1;
8180
8181 r = r600_bytecode_add_alu(ctx->bc, &alu);
8182 if (r)
8183 return r;
8184 }
8185 } else {
8186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8187 alu.op = ALU_OP1_EXP_IEEE;
8188 alu.src[0].sel = ctx->temp_reg;
8189 alu.src[0].chan = 1;
8190
8191 alu.dst.sel = ctx->temp_reg;
8192 alu.dst.chan = 1;
8193 alu.dst.write = 1;
8194 alu.last = 1;
8195
8196 r = r600_bytecode_add_alu(ctx->bc, &alu);
8197 if (r)
8198 return r;
8199 }
8200
8201 if (ctx->bc->chip_class == CAYMAN) {
8202 for (i = 0; i < 3; i++) {
8203 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8204 alu.op = ALU_OP1_RECIP_IEEE;
8205 alu.src[0].sel = ctx->temp_reg;
8206 alu.src[0].chan = 1;
8207
8208 alu.dst.sel = ctx->temp_reg;
8209 alu.dst.chan = i;
8210 if (i == 1)
8211 alu.dst.write = 1;
8212 if (i == 2)
8213 alu.last = 1;
8214
8215 r = r600_bytecode_add_alu(ctx->bc, &alu);
8216 if (r)
8217 return r;
8218 }
8219 } else {
8220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8221 alu.op = ALU_OP1_RECIP_IEEE;
8222 alu.src[0].sel = ctx->temp_reg;
8223 alu.src[0].chan = 1;
8224
8225 alu.dst.sel = ctx->temp_reg;
8226 alu.dst.chan = 1;
8227 alu.dst.write = 1;
8228 alu.last = 1;
8229
8230 r = r600_bytecode_add_alu(ctx->bc, &alu);
8231 if (r)
8232 return r;
8233 }
8234
8235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8236
8237 alu.op = ALU_OP2_MUL;
8238
8239 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8240 r600_bytecode_src_set_abs(&alu.src[0]);
8241
8242 alu.src[1].sel = ctx->temp_reg;
8243 alu.src[1].chan = 1;
8244
8245 alu.dst.sel = ctx->temp_reg;
8246 alu.dst.chan = 1;
8247 alu.dst.write = 1;
8248 alu.last = 1;
8249
8250 r = r600_bytecode_add_alu(ctx->bc, &alu);
8251 if (r)
8252 return r;
8253 }
8254
8255 /* result.z = log2(|src|);*/
8256 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8257 if (ctx->bc->chip_class == CAYMAN) {
8258 for (i = 0; i < 3; i++) {
8259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8260
8261 alu.op = ALU_OP1_LOG_IEEE;
8262 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8263 r600_bytecode_src_set_abs(&alu.src[0]);
8264
8265 alu.dst.sel = ctx->temp_reg;
8266 if (i == 2)
8267 alu.dst.write = 1;
8268 alu.dst.chan = i;
8269 if (i == 2)
8270 alu.last = 1;
8271
8272 r = r600_bytecode_add_alu(ctx->bc, &alu);
8273 if (r)
8274 return r;
8275 }
8276 } else {
8277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8278
8279 alu.op = ALU_OP1_LOG_IEEE;
8280 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8281 r600_bytecode_src_set_abs(&alu.src[0]);
8282
8283 alu.dst.sel = ctx->temp_reg;
8284 alu.dst.write = 1;
8285 alu.dst.chan = 2;
8286 alu.last = 1;
8287
8288 r = r600_bytecode_add_alu(ctx->bc, &alu);
8289 if (r)
8290 return r;
8291 }
8292 }
8293
8294 /* result.w = 1.0; */
8295 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8297
8298 alu.op = ALU_OP1_MOV;
8299 alu.src[0].sel = V_SQ_ALU_SRC_1;
8300 alu.src[0].chan = 0;
8301
8302 alu.dst.sel = ctx->temp_reg;
8303 alu.dst.chan = 3;
8304 alu.dst.write = 1;
8305 alu.last = 1;
8306
8307 r = r600_bytecode_add_alu(ctx->bc, &alu);
8308 if (r)
8309 return r;
8310 }
8311
8312 return tgsi_helper_copy(ctx, inst);
8313 }
8314
8315 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8316 {
8317 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8318 struct r600_bytecode_alu alu;
8319 int r;
8320 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8321 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8322
8323 assert(inst->Dst[0].Register.Index < 3);
8324 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8325
8326 switch (inst->Instruction.Opcode) {
8327 case TGSI_OPCODE_ARL:
8328 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8329 break;
8330 case TGSI_OPCODE_ARR:
8331 alu.op = ALU_OP1_FLT_TO_INT;
8332 break;
8333 case TGSI_OPCODE_UARL:
8334 alu.op = ALU_OP1_MOV;
8335 break;
8336 default:
8337 assert(0);
8338 return -1;
8339 }
8340
8341 for (i = 0; i <= lasti; ++i) {
8342 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8343 continue;
8344 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8345 alu.last = i == lasti;
8346 alu.dst.sel = reg;
8347 alu.dst.chan = i;
8348 alu.dst.write = 1;
8349 r = r600_bytecode_add_alu(ctx->bc, &alu);
8350 if (r)
8351 return r;
8352 }
8353
8354 if (inst->Dst[0].Register.Index > 0)
8355 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8356 else
8357 ctx->bc->ar_loaded = 0;
8358
8359 return 0;
8360 }
8361 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8362 {
8363 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8364 struct r600_bytecode_alu alu;
8365 int r;
8366 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8367
8368 switch (inst->Instruction.Opcode) {
8369 case TGSI_OPCODE_ARL:
8370 memset(&alu, 0, sizeof(alu));
8371 alu.op = ALU_OP1_FLOOR;
8372 alu.dst.sel = ctx->bc->ar_reg;
8373 alu.dst.write = 1;
8374 for (i = 0; i <= lasti; ++i) {
8375 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8376 alu.dst.chan = i;
8377 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8378 alu.last = i == lasti;
8379 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8380 return r;
8381 }
8382 }
8383
8384 memset(&alu, 0, sizeof(alu));
8385 alu.op = ALU_OP1_FLT_TO_INT;
8386 alu.src[0].sel = ctx->bc->ar_reg;
8387 alu.dst.sel = ctx->bc->ar_reg;
8388 alu.dst.write = 1;
8389 /* FLT_TO_INT is trans-only on r600/r700 */
8390 alu.last = TRUE;
8391 for (i = 0; i <= lasti; ++i) {
8392 alu.dst.chan = i;
8393 alu.src[0].chan = i;
8394 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8395 return r;
8396 }
8397 break;
8398 case TGSI_OPCODE_ARR:
8399 memset(&alu, 0, sizeof(alu));
8400 alu.op = ALU_OP1_FLT_TO_INT;
8401 alu.dst.sel = ctx->bc->ar_reg;
8402 alu.dst.write = 1;
8403 /* FLT_TO_INT is trans-only on r600/r700 */
8404 alu.last = TRUE;
8405 for (i = 0; i <= lasti; ++i) {
8406 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8407 alu.dst.chan = i;
8408 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8409 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8410 return r;
8411 }
8412 }
8413 break;
8414 case TGSI_OPCODE_UARL:
8415 memset(&alu, 0, sizeof(alu));
8416 alu.op = ALU_OP1_MOV;
8417 alu.dst.sel = ctx->bc->ar_reg;
8418 alu.dst.write = 1;
8419 for (i = 0; i <= lasti; ++i) {
8420 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8421 alu.dst.chan = i;
8422 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8423 alu.last = i == lasti;
8424 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8425 return r;
8426 }
8427 }
8428 break;
8429 default:
8430 assert(0);
8431 return -1;
8432 }
8433
8434 ctx->bc->ar_loaded = 0;
8435 return 0;
8436 }
8437
8438 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8439 {
8440 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8441 struct r600_bytecode_alu alu;
8442 int i, r = 0;
8443
8444 for (i = 0; i < 4; i++) {
8445 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8446
8447 alu.op = ALU_OP2_MUL;
8448 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8449
8450 if (i == 0 || i == 3) {
8451 alu.src[0].sel = V_SQ_ALU_SRC_1;
8452 } else {
8453 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8454 }
8455
8456 if (i == 0 || i == 2) {
8457 alu.src[1].sel = V_SQ_ALU_SRC_1;
8458 } else {
8459 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8460 }
8461 if (i == 3)
8462 alu.last = 1;
8463 r = r600_bytecode_add_alu(ctx->bc, &alu);
8464 if (r)
8465 return r;
8466 }
8467 return 0;
8468 }
8469
8470 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8471 {
8472 struct r600_bytecode_alu alu;
8473 int r;
8474
8475 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8476 alu.op = opcode;
8477 alu.execute_mask = 1;
8478 alu.update_pred = 1;
8479
8480 alu.dst.sel = ctx->temp_reg;
8481 alu.dst.write = 1;
8482 alu.dst.chan = 0;
8483
8484 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8485 alu.src[1].sel = V_SQ_ALU_SRC_0;
8486 alu.src[1].chan = 0;
8487
8488 alu.last = 1;
8489
8490 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8491 if (r)
8492 return r;
8493 return 0;
8494 }
8495
8496 static int pops(struct r600_shader_ctx *ctx, int pops)
8497 {
8498 unsigned force_pop = ctx->bc->force_add_cf;
8499
8500 if (!force_pop) {
8501 int alu_pop = 3;
8502 if (ctx->bc->cf_last) {
8503 if (ctx->bc->cf_last->op == CF_OP_ALU)
8504 alu_pop = 0;
8505 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8506 alu_pop = 1;
8507 }
8508 alu_pop += pops;
8509 if (alu_pop == 1) {
8510 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8511 ctx->bc->force_add_cf = 1;
8512 } else if (alu_pop == 2) {
8513 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8514 ctx->bc->force_add_cf = 1;
8515 } else {
8516 force_pop = 1;
8517 }
8518 }
8519
8520 if (force_pop) {
8521 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8522 ctx->bc->cf_last->pop_count = pops;
8523 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8524 }
8525
8526 return 0;
8527 }
8528
8529 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8530 unsigned reason)
8531 {
8532 struct r600_stack_info *stack = &ctx->bc->stack;
8533 unsigned elements, entries;
8534
8535 unsigned entry_size = stack->entry_size;
8536
8537 elements = (stack->loop + stack->push_wqm ) * entry_size;
8538 elements += stack->push;
8539
8540 switch (ctx->bc->chip_class) {
8541 case R600:
8542 case R700:
8543 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8544 * the stack must be reserved to hold the current active/continue
8545 * masks */
8546 if (reason == FC_PUSH_VPM) {
8547 elements += 2;
8548 }
8549 break;
8550
8551 case CAYMAN:
8552 /* r9xx: any stack operation on empty stack consumes 2 additional
8553 * elements */
8554 elements += 2;
8555
8556 /* fallthrough */
8557 /* FIXME: do the two elements added above cover the cases for the
8558 * r8xx+ below? */
8559
8560 case EVERGREEN:
8561 /* r8xx+: 2 extra elements are not always required, but one extra
8562 * element must be added for each of the following cases:
8563 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8564 * stack usage.
8565 * (Currently we don't use ALU_ELSE_AFTER.)
8566 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8567 * PUSH instruction executed.
8568 *
8569 * NOTE: it seems we also need to reserve additional element in some
8570 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8571 * then STACK_SIZE should be 2 instead of 1 */
8572 if (reason == FC_PUSH_VPM) {
8573 elements += 1;
8574 }
8575 break;
8576
8577 default:
8578 assert(0);
8579 break;
8580 }
8581
8582 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8583 * for all chips, so we use 4 in the final formula, not the real entry_size
8584 * for the chip */
8585 entry_size = 4;
8586
8587 entries = (elements + (entry_size - 1)) / entry_size;
8588
8589 if (entries > stack->max_entries)
8590 stack->max_entries = entries;
8591 }
8592
8593 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8594 {
8595 switch(reason) {
8596 case FC_PUSH_VPM:
8597 --ctx->bc->stack.push;
8598 assert(ctx->bc->stack.push >= 0);
8599 break;
8600 case FC_PUSH_WQM:
8601 --ctx->bc->stack.push_wqm;
8602 assert(ctx->bc->stack.push_wqm >= 0);
8603 break;
8604 case FC_LOOP:
8605 --ctx->bc->stack.loop;
8606 assert(ctx->bc->stack.loop >= 0);
8607 break;
8608 default:
8609 assert(0);
8610 break;
8611 }
8612 }
8613
8614 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8615 {
8616 switch (reason) {
8617 case FC_PUSH_VPM:
8618 ++ctx->bc->stack.push;
8619 break;
8620 case FC_PUSH_WQM:
8621 ++ctx->bc->stack.push_wqm;
8622 case FC_LOOP:
8623 ++ctx->bc->stack.loop;
8624 break;
8625 default:
8626 assert(0);
8627 }
8628
8629 callstack_update_max_depth(ctx, reason);
8630 }
8631
8632 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8633 {
8634 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8635
8636 sp->mid = realloc((void *)sp->mid,
8637 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8638 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8639 sp->num_mid++;
8640 }
8641
8642 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8643 {
8644 ctx->bc->fc_sp++;
8645 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8646 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8647 }
8648
8649 static void fc_poplevel(struct r600_shader_ctx *ctx)
8650 {
8651 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
8652 free(sp->mid);
8653 sp->mid = NULL;
8654 sp->num_mid = 0;
8655 sp->start = NULL;
8656 sp->type = 0;
8657 ctx->bc->fc_sp--;
8658 }
8659
8660 #if 0
8661 static int emit_return(struct r600_shader_ctx *ctx)
8662 {
8663 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8664 return 0;
8665 }
8666
8667 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8668 {
8669
8670 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8671 ctx->bc->cf_last->pop_count = pops;
8672 /* XXX work out offset */
8673 return 0;
8674 }
8675
8676 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8677 {
8678 return 0;
8679 }
8680
8681 static void emit_testflag(struct r600_shader_ctx *ctx)
8682 {
8683
8684 }
8685
8686 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8687 {
8688 emit_testflag(ctx);
8689 emit_jump_to_offset(ctx, 1, 4);
8690 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8691 pops(ctx, ifidx + 1);
8692 emit_return(ctx);
8693 }
8694
8695 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8696 {
8697 emit_testflag(ctx);
8698
8699 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8700 ctx->bc->cf_last->pop_count = 1;
8701
8702 fc_set_mid(ctx, fc_sp);
8703
8704 pops(ctx, 1);
8705 }
8706 #endif
8707
8708 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8709 {
8710 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8711
8712 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8713 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8714 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8715 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8716 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8717 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8718 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8719 alu_type = CF_OP_ALU;
8720 }
8721
8722 emit_logic_pred(ctx, opcode, alu_type);
8723
8724 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8725
8726 fc_pushlevel(ctx, FC_IF);
8727
8728 callstack_push(ctx, FC_PUSH_VPM);
8729 return 0;
8730 }
8731
8732 static int tgsi_if(struct r600_shader_ctx *ctx)
8733 {
8734 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8735 }
8736
8737 static int tgsi_uif(struct r600_shader_ctx *ctx)
8738 {
8739 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8740 }
8741
8742 static int tgsi_else(struct r600_shader_ctx *ctx)
8743 {
8744 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8745 ctx->bc->cf_last->pop_count = 1;
8746
8747 fc_set_mid(ctx, ctx->bc->fc_sp);
8748 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
8749 return 0;
8750 }
8751
8752 static int tgsi_endif(struct r600_shader_ctx *ctx)
8753 {
8754 pops(ctx, 1);
8755 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
8756 R600_ERR("if/endif unbalanced in shader\n");
8757 return -1;
8758 }
8759
8760 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
8761 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8762 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
8763 } else {
8764 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8765 }
8766 fc_poplevel(ctx);
8767
8768 callstack_pop(ctx, FC_PUSH_VPM);
8769 return 0;
8770 }
8771
8772 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8773 {
8774 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8775 * limited to 4096 iterations, like the other LOOP_* instructions. */
8776 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8777
8778 fc_pushlevel(ctx, FC_LOOP);
8779
8780 /* check stack depth */
8781 callstack_push(ctx, FC_LOOP);
8782 return 0;
8783 }
8784
8785 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8786 {
8787 int i;
8788
8789 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8790
8791 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
8792 R600_ERR("loop/endloop in shader code are not paired.\n");
8793 return -EINVAL;
8794 }
8795
8796 /* fixup loop pointers - from r600isa
8797 LOOP END points to CF after LOOP START,
8798 LOOP START point to CF after LOOP END
8799 BRK/CONT point to LOOP END CF
8800 */
8801 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
8802
8803 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8804
8805 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
8806 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
8807 }
8808 /* XXX add LOOPRET support */
8809 fc_poplevel(ctx);
8810 callstack_pop(ctx, FC_LOOP);
8811 return 0;
8812 }
8813
8814 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
8815 {
8816 int r;
8817 unsigned int fscp;
8818
8819 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8820 {
8821 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8822 break;
8823 }
8824 if (fscp == 0) {
8825 R600_ERR("BREAKC not inside loop/endloop pair\n");
8826 return -EINVAL;
8827 }
8828
8829 if (ctx->bc->chip_class == EVERGREEN &&
8830 ctx->bc->family != CHIP_CYPRESS &&
8831 ctx->bc->family != CHIP_JUNIPER) {
8832 /* HW bug: ALU_BREAK does not save the active mask correctly */
8833 r = tgsi_uif(ctx);
8834 if (r)
8835 return r;
8836
8837 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
8838 if (r)
8839 return r;
8840 fc_set_mid(ctx, fscp);
8841
8842 return tgsi_endif(ctx);
8843 } else {
8844 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
8845 if (r)
8846 return r;
8847 fc_set_mid(ctx, fscp);
8848 }
8849
8850 return 0;
8851 }
8852
8853 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8854 {
8855 unsigned int fscp;
8856
8857 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8858 {
8859 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8860 break;
8861 }
8862
8863 if (fscp == 0) {
8864 R600_ERR("Break not inside loop/endloop pair\n");
8865 return -EINVAL;
8866 }
8867
8868 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8869
8870 fc_set_mid(ctx, fscp);
8871
8872 return 0;
8873 }
8874
8875 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8876 {
8877 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8878 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8879 int r;
8880
8881 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8882 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
8883
8884 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8885 if (!r) {
8886 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
8887 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8888 return emit_inc_ring_offset(ctx, stream, TRUE);
8889 }
8890 return r;
8891 }
8892
8893 static int tgsi_umad(struct r600_shader_ctx *ctx)
8894 {
8895 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8896 struct r600_bytecode_alu alu;
8897 int i, j, k, r;
8898 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8899
8900 /* src0 * src1 */
8901 for (i = 0; i < lasti + 1; i++) {
8902 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8903 continue;
8904
8905 if (ctx->bc->chip_class == CAYMAN) {
8906 for (j = 0 ; j < 4; j++) {
8907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8908
8909 alu.op = ALU_OP2_MULLO_UINT;
8910 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
8911 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
8912 }
8913 alu.dst.chan = j;
8914 alu.dst.sel = ctx->temp_reg;
8915 alu.dst.write = (j == i);
8916 if (j == 3)
8917 alu.last = 1;
8918 r = r600_bytecode_add_alu(ctx->bc, &alu);
8919 if (r)
8920 return r;
8921 }
8922 } else {
8923 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8924
8925 alu.dst.chan = i;
8926 alu.dst.sel = ctx->temp_reg;
8927 alu.dst.write = 1;
8928
8929 alu.op = ALU_OP2_MULLO_UINT;
8930 for (j = 0; j < 2; j++) {
8931 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
8932 }
8933
8934 alu.last = 1;
8935 r = r600_bytecode_add_alu(ctx->bc, &alu);
8936 if (r)
8937 return r;
8938 }
8939 }
8940
8941
8942 for (i = 0; i < lasti + 1; i++) {
8943 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8944 continue;
8945
8946 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8947 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8948
8949 alu.op = ALU_OP2_ADD_INT;
8950
8951 alu.src[0].sel = ctx->temp_reg;
8952 alu.src[0].chan = i;
8953
8954 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8955 if (i == lasti) {
8956 alu.last = 1;
8957 }
8958 r = r600_bytecode_add_alu(ctx->bc, &alu);
8959 if (r)
8960 return r;
8961 }
8962 return 0;
8963 }
8964
8965 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
8966 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
8967 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8968 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8969
8970 /* XXX:
8971 * For state trackers other than OpenGL, we'll want to use
8972 * _RECIP_IEEE instead.
8973 */
8974 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
8975
8976 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
8977 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8978 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8979 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8980 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8981 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8982 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8983 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8984 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8985 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8986 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8987 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8988 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8989 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8990 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8991 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8992 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
8993 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8994 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8995 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8996 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8997 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8998 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8999 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9000 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9001 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9002 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9003 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9004 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9005 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
9006 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9007 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9008 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9009 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9010 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9011 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9012 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9013 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9014 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9015 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9016 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9017 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9018 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9019 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9020 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9021 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9022 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9023 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9024 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9025 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9026 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9027 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9028 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9029 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9030 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9031 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9032 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9033 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9034 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9035 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9036 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9037 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9038 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9039 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9040 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9041 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9042 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9043 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9044 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9045 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9046 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9047 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9048 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9049 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9050 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9051 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9052 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9053 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9054 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9055 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9056 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9057 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9058 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9059 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9060 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9061 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9062 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9063 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9064 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9065 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9066 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9067 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9068 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9069 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9070 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9071 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9072 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9073 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9074 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9075 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9076 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9077 [105] = { ALU_OP0_NOP, tgsi_unsupported},
9078 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9079 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9080 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9081 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9082 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9083 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9084 [112] = { ALU_OP0_NOP, tgsi_unsupported},
9085 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9086 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9087 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
9088 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9089 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9090 [118] = { ALU_OP0_NOP, tgsi_unsupported},
9091 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9092 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9093 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9094 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9095 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9096 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9097 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9098 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9099 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9100 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9101 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9102 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9103 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9104 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9105 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9106 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9107 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9108 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9109 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9110 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9111 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9112 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9113 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9114 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9115 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9116 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9117 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9118 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9119 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9120 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9121 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9122 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9123 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9124 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9125 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9126 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9127 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9128 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9129 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9130 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9131 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9132 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9133 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9134 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9135 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9136 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9137 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9138 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9139 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9140 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9141 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9142 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9143 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9144 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9145 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9146 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9147 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9148 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9149 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9150 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9151 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9152 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9153 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9154 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9155 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9156 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9157 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9158 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9159 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9160 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9161 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9162 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9163 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9164 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9165 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9166 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9167 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9168 };
9169
9170 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9171 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9172 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9173 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9174 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9175 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
9176 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9177 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9178 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9179 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9180 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9181 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9182 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9183 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9184 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9185 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9186 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9187 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9188 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
9189 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9190 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9191 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9192 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9193 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9194 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9195 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9196 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9197 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9198 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9199 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9200 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9201 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9202 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9203 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9204 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
9205 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9206 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9207 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9208 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9209 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9210 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9211 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9212 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9213 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9214 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9215 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9216 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9217 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9218 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9219 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9220 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9221 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9222 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9223 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9224 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9225 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9226 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9227 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9228 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9229 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9230 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9231 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9232 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9233 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9234 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9235 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9236 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9237 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9238 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9239 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9240 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9241 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9242 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9243 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9244 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9245 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9246 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9247 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9248 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9249 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9250 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9251 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9252 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9253 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9254 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9255 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9256 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9257 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9258 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9259 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9260 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9261 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9262 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9263 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9264 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9265 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9266 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9267 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9268 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9269 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9270 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9271 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9272 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9273 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9274 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9275 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9276 [105] = { ALU_OP0_NOP, tgsi_unsupported},
9277 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9278 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9279 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9280 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9281 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9282 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9283 [112] = { ALU_OP0_NOP, tgsi_unsupported},
9284 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9285 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9286 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9287 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9288 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9289 [118] = { ALU_OP0_NOP, tgsi_unsupported},
9290 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9291 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9292 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9293 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9294 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9295 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9296 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9297 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9298 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9299 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9300 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9301 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9302 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9303 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9304 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9305 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9306 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9307 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9308 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9309 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9310 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9311 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9312 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9313 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9314 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9315 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9316 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9317 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9318 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9319 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9320 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9321 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9322 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9323 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9324 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9325 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9326 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9327 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9328 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9329 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9330 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9331 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9332 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9333 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9334 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9335 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9336 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9337 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9338 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9339 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9340 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9341 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9342 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9343 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9344 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9345 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9346 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9347 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9348 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9349 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9350 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9351 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9352 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9353 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9354 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9355 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9356 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9357 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9358 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9359 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9360 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9361 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9362 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9363 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9364 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9365 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9366 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9367 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9368 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9369 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9370 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9371 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9372 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9373 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9374 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9375 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9376 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9377 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9378 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9379 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9380 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9381 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9382 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9383 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9384 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9385 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9386 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9387 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9388 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9389 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9390 };
9391
9392 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9393 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9394 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9395 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9396 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9397 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9398 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9399 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9400 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9401 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9402 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9403 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9404 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9405 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9406 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9407 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9408 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9409 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9410 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
9411 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9412 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9413 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9414 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9415 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9416 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9417 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9418 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9419 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9420 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9421 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9422 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9423 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9424 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9425 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9426 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
9427 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9428 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9429 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9430 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9431 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9432 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9433 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9434 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9435 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9436 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9437 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9438 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9439 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9440 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9441 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9442 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9443 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9444 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9445 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9446 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9447 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9448 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9449 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9450 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9451 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9452 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9453 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9454 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9455 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9456 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9457 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9458 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9459 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9460 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9461 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9462 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9463 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9464 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9465 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9466 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9467 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9468 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9469 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9470 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9471 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9472 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9473 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9474 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9475 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9476 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9477 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9478 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9479 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9480 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9481 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9482 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9483 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9484 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9485 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9486 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9487 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9488 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9489 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9490 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9491 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9492 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9493 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9494 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9495 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9496 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9497 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9498 [105] = { ALU_OP0_NOP, tgsi_unsupported},
9499 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9500 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9501 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9502 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9503 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9504 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9505 [112] = { ALU_OP0_NOP, tgsi_unsupported},
9506 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9507 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9508 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9509 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9510 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9511 [118] = { ALU_OP0_NOP, tgsi_unsupported},
9512 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9513 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9514 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9515 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9516 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9517 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9518 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9519 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9520 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9521 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9522 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9523 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9524 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9525 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9526 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9527 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9528 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9529 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9530 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9531 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9532 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9533 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9534 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9535 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9536 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9537 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9538 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9539 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9540 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9541 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9542 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9543 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9544 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9545 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9546 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9547 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9548 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9549 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9550 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9551 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9552 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9553 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9554 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9555 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9556 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9557 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9558 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9559 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9560 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9561 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9562 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9563 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9564 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9565 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9566 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9567 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9568 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9569 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9570 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9571 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9572 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9573 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9574 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9575 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9576 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9577 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9578 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9579 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9580 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9581 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9582 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9583 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9584 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9585 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9586 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9587 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9588 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9589 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9590 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9591 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9592 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9593 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9594 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9595 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9596 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9597 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9598 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9599 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9600 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9601 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9602 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9603 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9604 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9605 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9606 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9607 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9608 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9609 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9610 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9611 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9612 };