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gallium: remove TGSI_OPCODE_ABS
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 /* Check if the bytecode has already been built. */
198 if (!shader->shader.bc.bytecode) {
199 r = r600_bytecode_build(&shader->shader.bc);
200 if (r) {
201 R600_ERR("building bytecode failed !\n");
202 goto error;
203 }
204 }
205
206 if (dump && !sb_disasm) {
207 fprintf(stderr, "--------------------------------------------------------------\n");
208 r600_bytecode_disasm(&shader->shader.bc);
209 fprintf(stderr, "______________________________________________________________\n");
210 } else if ((dump && sb_disasm) || use_sb) {
211 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
212 dump, use_sb);
213 if (r) {
214 R600_ERR("r600_sb_bytecode_process failed !\n");
215 goto error;
216 }
217 }
218
219 if (shader->gs_copy_shader) {
220 if (dump) {
221 // dump copy shader
222 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
223 &shader->gs_copy_shader->shader, dump, 0);
224 if (r)
225 goto error;
226 }
227
228 if ((r = store_shader(ctx, shader->gs_copy_shader)))
229 goto error;
230 }
231
232 /* Store the shader in a buffer. */
233 if ((r = store_shader(ctx, shader)))
234 goto error;
235
236 /* Build state. */
237 switch (shader->shader.processor_type) {
238 case PIPE_SHADER_TESS_CTRL:
239 evergreen_update_hs_state(ctx, shader);
240 break;
241 case PIPE_SHADER_TESS_EVAL:
242 if (key.tes.as_es)
243 evergreen_update_es_state(ctx, shader);
244 else
245 evergreen_update_vs_state(ctx, shader);
246 break;
247 case PIPE_SHADER_GEOMETRY:
248 if (rctx->b.chip_class >= EVERGREEN) {
249 evergreen_update_gs_state(ctx, shader);
250 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
251 } else {
252 r600_update_gs_state(ctx, shader);
253 r600_update_vs_state(ctx, shader->gs_copy_shader);
254 }
255 break;
256 case PIPE_SHADER_VERTEX:
257 export_shader = key.vs.as_es;
258 if (rctx->b.chip_class >= EVERGREEN) {
259 if (key.vs.as_ls)
260 evergreen_update_ls_state(ctx, shader);
261 else if (key.vs.as_es)
262 evergreen_update_es_state(ctx, shader);
263 else
264 evergreen_update_vs_state(ctx, shader);
265 } else {
266 if (export_shader)
267 r600_update_es_state(ctx, shader);
268 else
269 r600_update_vs_state(ctx, shader);
270 }
271 break;
272 case PIPE_SHADER_FRAGMENT:
273 if (rctx->b.chip_class >= EVERGREEN) {
274 evergreen_update_ps_state(ctx, shader);
275 } else {
276 r600_update_ps_state(ctx, shader);
277 }
278 break;
279 default:
280 r = -EINVAL;
281 goto error;
282 }
283 return 0;
284
285 error:
286 r600_pipe_shader_destroy(ctx, shader);
287 return r;
288 }
289
290 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
291 {
292 r600_resource_reference(&shader->bo, NULL);
293 r600_bytecode_clear(&shader->shader.bc);
294 r600_release_command_buffer(&shader->command_buffer);
295 }
296
297 /*
298 * tgsi -> r600 shader
299 */
300 struct r600_shader_tgsi_instruction;
301
302 struct r600_shader_src {
303 unsigned sel;
304 unsigned swizzle[4];
305 unsigned neg;
306 unsigned abs;
307 unsigned rel;
308 unsigned kc_bank;
309 boolean kc_rel; /* true if cache bank is indexed */
310 uint32_t value[4];
311 };
312
313 struct eg_interp {
314 boolean enabled;
315 unsigned ij_index;
316 };
317
318 struct r600_shader_ctx {
319 struct tgsi_shader_info info;
320 struct tgsi_parse_context parse;
321 const struct tgsi_token *tokens;
322 unsigned type;
323 unsigned file_offset[TGSI_FILE_COUNT];
324 unsigned temp_reg;
325 const struct r600_shader_tgsi_instruction *inst_info;
326 struct r600_bytecode *bc;
327 struct r600_shader *shader;
328 struct r600_shader_src src[4];
329 uint32_t *literals;
330 uint32_t nliterals;
331 uint32_t max_driver_temp_used;
332 /* needed for evergreen interpolation */
333 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
334 /* evergreen/cayman also store sample mask in face register */
335 int face_gpr;
336 /* sample id is .w component stored in fixed point position register */
337 int fixed_pt_position_gpr;
338 int colors_used;
339 boolean clip_vertex_write;
340 unsigned cv_output;
341 unsigned edgeflag_output;
342 int fragcoord_input;
343 int native_integers;
344 int next_ring_offset;
345 int gs_out_ring_offset;
346 int gs_next_vertex;
347 struct r600_shader *gs_for_vs;
348 int gs_export_gpr_tregs[4];
349 const struct pipe_stream_output_info *gs_stream_output_info;
350 unsigned enabled_stream_buffers_mask;
351 unsigned tess_input_info; /* temp with tess input offsets */
352 unsigned tess_output_info; /* temp with tess input offsets */
353 };
354
355 struct r600_shader_tgsi_instruction {
356 unsigned op;
357 int (*process)(struct r600_shader_ctx *ctx);
358 };
359
360 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
361 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
362 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
363 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
364 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
365 static int tgsi_else(struct r600_shader_ctx *ctx);
366 static int tgsi_endif(struct r600_shader_ctx *ctx);
367 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
368 static int tgsi_endloop(struct r600_shader_ctx *ctx);
369 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
370 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
371 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
372 unsigned int dst_reg);
373 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
374 const struct r600_shader_src *shader_src,
375 unsigned chan);
376 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
377 unsigned dst_reg);
378
379 static int tgsi_last_instruction(unsigned writemask)
380 {
381 int i, lasti = 0;
382
383 for (i = 0; i < 4; i++) {
384 if (writemask & (1 << i)) {
385 lasti = i;
386 }
387 }
388 return lasti;
389 }
390
391 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
392 {
393 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
394 unsigned j;
395
396 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
397 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
398 return -EINVAL;
399 }
400 if (i->Instruction.Predicate) {
401 R600_ERR("predicate unsupported\n");
402 return -EINVAL;
403 }
404 #if 0
405 if (i->Instruction.Label) {
406 R600_ERR("label unsupported\n");
407 return -EINVAL;
408 }
409 #endif
410 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
411 if (i->Src[j].Register.Dimension) {
412 switch (i->Src[j].Register.File) {
413 case TGSI_FILE_CONSTANT:
414 break;
415 case TGSI_FILE_INPUT:
416 if (ctx->type == PIPE_SHADER_GEOMETRY ||
417 ctx->type == PIPE_SHADER_TESS_CTRL ||
418 ctx->type == PIPE_SHADER_TESS_EVAL)
419 break;
420 case TGSI_FILE_OUTPUT:
421 if (ctx->type == PIPE_SHADER_TESS_CTRL)
422 break;
423 default:
424 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
425 i->Src[j].Register.File,
426 i->Src[j].Register.Dimension);
427 return -EINVAL;
428 }
429 }
430 }
431 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
432 if (i->Dst[j].Register.Dimension) {
433 if (ctx->type == PIPE_SHADER_TESS_CTRL)
434 continue;
435 R600_ERR("unsupported dst (dimension)\n");
436 return -EINVAL;
437 }
438 }
439 return 0;
440 }
441
442 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
443 {
444 if (interpolate == TGSI_INTERPOLATE_COLOR ||
445 interpolate == TGSI_INTERPOLATE_LINEAR ||
446 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
447 {
448 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
449 int loc;
450
451 switch(location) {
452 case TGSI_INTERPOLATE_LOC_CENTER:
453 loc = 1;
454 break;
455 case TGSI_INTERPOLATE_LOC_CENTROID:
456 loc = 2;
457 break;
458 case TGSI_INTERPOLATE_LOC_SAMPLE:
459 default:
460 loc = 0; break;
461 }
462
463 return is_linear * 3 + loc;
464 }
465
466 return -1;
467 }
468
469 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
470 int input)
471 {
472 int i = eg_get_interpolator_index(
473 ctx->shader->input[input].interpolate,
474 ctx->shader->input[input].interpolate_location);
475 assert(i >= 0);
476 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
477 }
478
479 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
480 {
481 int i, r;
482 struct r600_bytecode_alu alu;
483 int gpr = 0, base_chan = 0;
484 int ij_index = ctx->shader->input[input].ij_index;
485
486 /* work out gpr and base_chan from index */
487 gpr = ij_index / 2;
488 base_chan = (2 * (ij_index % 2)) + 1;
489
490 for (i = 0; i < 8; i++) {
491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
492
493 if (i < 4)
494 alu.op = ALU_OP2_INTERP_ZW;
495 else
496 alu.op = ALU_OP2_INTERP_XY;
497
498 if ((i > 1) && (i < 6)) {
499 alu.dst.sel = ctx->shader->input[input].gpr;
500 alu.dst.write = 1;
501 }
502
503 alu.dst.chan = i % 4;
504
505 alu.src[0].sel = gpr;
506 alu.src[0].chan = (base_chan - (i % 2));
507
508 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
509
510 alu.bank_swizzle_force = SQ_ALU_VEC_210;
511 if ((i % 4) == 3)
512 alu.last = 1;
513 r = r600_bytecode_add_alu(ctx->bc, &alu);
514 if (r)
515 return r;
516 }
517 return 0;
518 }
519
520 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
521 {
522 int i, r;
523 struct r600_bytecode_alu alu;
524
525 for (i = 0; i < 4; i++) {
526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
527
528 alu.op = ALU_OP1_INTERP_LOAD_P0;
529
530 alu.dst.sel = ctx->shader->input[input].gpr;
531 alu.dst.write = 1;
532
533 alu.dst.chan = i;
534
535 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
536 alu.src[0].chan = i;
537
538 if (i == 3)
539 alu.last = 1;
540 r = r600_bytecode_add_alu(ctx->bc, &alu);
541 if (r)
542 return r;
543 }
544 return 0;
545 }
546
547 /*
548 * Special export handling in shaders
549 *
550 * shader export ARRAY_BASE for EXPORT_POS:
551 * 60 is position
552 * 61 is misc vector
553 * 62, 63 are clip distance vectors
554 *
555 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
556 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
557 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
558 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
559 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
560 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
561 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
562 * exclusive from render target index)
563 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
564 *
565 *
566 * shader export ARRAY_BASE for EXPORT_PIXEL:
567 * 0-7 CB targets
568 * 61 computed Z vector
569 *
570 * The use of the values exported in the computed Z vector are controlled
571 * by DB_SHADER_CONTROL:
572 * Z_EXPORT_ENABLE - Z as a float in RED
573 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
574 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
575 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
576 * DB_SOURCE_FORMAT - export control restrictions
577 *
578 */
579
580
581 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
582 static int r600_spi_sid(struct r600_shader_io * io)
583 {
584 int index, name = io->name;
585
586 /* These params are handled differently, they don't need
587 * semantic indices, so we'll use 0 for them.
588 */
589 if (name == TGSI_SEMANTIC_POSITION ||
590 name == TGSI_SEMANTIC_PSIZE ||
591 name == TGSI_SEMANTIC_EDGEFLAG ||
592 name == TGSI_SEMANTIC_FACE ||
593 name == TGSI_SEMANTIC_SAMPLEMASK)
594 index = 0;
595 else {
596 if (name == TGSI_SEMANTIC_GENERIC) {
597 /* For generic params simply use sid from tgsi */
598 index = io->sid;
599 } else {
600 /* For non-generic params - pack name and sid into 8 bits */
601 index = 0x80 | (name<<3) | (io->sid);
602 }
603
604 /* Make sure that all really used indices have nonzero value, so
605 * we can just compare it to 0 later instead of comparing the name
606 * with different values to detect special cases. */
607 index++;
608 }
609
610 return index;
611 };
612
613 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
614 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
615 {
616 switch (semantic_name) {
617 case TGSI_SEMANTIC_POSITION:
618 return 0;
619 case TGSI_SEMANTIC_PSIZE:
620 return 1;
621 case TGSI_SEMANTIC_CLIPDIST:
622 assert(index <= 1);
623 return 2 + index;
624 case TGSI_SEMANTIC_GENERIC:
625 if (index <= 63-4)
626 return 4 + index - 9;
627 else
628 /* same explanation as in the default statement,
629 * the only user hitting this is st/nine.
630 */
631 return 0;
632
633 /* patch indices are completely separate and thus start from 0 */
634 case TGSI_SEMANTIC_TESSOUTER:
635 return 0;
636 case TGSI_SEMANTIC_TESSINNER:
637 return 1;
638 case TGSI_SEMANTIC_PATCH:
639 return 2 + index;
640
641 default:
642 /* Don't fail here. The result of this function is only used
643 * for LS, TCS, TES, and GS, where legacy GL semantics can't
644 * occur, but this function is called for all vertex shaders
645 * before it's known whether LS will be compiled or not.
646 */
647 return 0;
648 }
649 }
650
651 /* turn input into interpolate on EG */
652 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
653 {
654 int r = 0;
655
656 if (ctx->shader->input[index].spi_sid) {
657 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
658 if (ctx->shader->input[index].interpolate > 0) {
659 evergreen_interp_assign_ij_index(ctx, index);
660 r = evergreen_interp_alu(ctx, index);
661 } else {
662 r = evergreen_interp_flat(ctx, index);
663 }
664 }
665 return r;
666 }
667
668 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
669 {
670 struct r600_bytecode_alu alu;
671 int i, r;
672 int gpr_front = ctx->shader->input[front].gpr;
673 int gpr_back = ctx->shader->input[back].gpr;
674
675 for (i = 0; i < 4; i++) {
676 memset(&alu, 0, sizeof(alu));
677 alu.op = ALU_OP3_CNDGT;
678 alu.is_op3 = 1;
679 alu.dst.write = 1;
680 alu.dst.sel = gpr_front;
681 alu.src[0].sel = ctx->face_gpr;
682 alu.src[1].sel = gpr_front;
683 alu.src[2].sel = gpr_back;
684
685 alu.dst.chan = i;
686 alu.src[1].chan = i;
687 alu.src[2].chan = i;
688 alu.last = (i==3);
689
690 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
691 return r;
692 }
693
694 return 0;
695 }
696
697 /* execute a single slot ALU calculation */
698 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
699 int dst_sel, int dst_chan,
700 int src0_sel, unsigned src0_chan_val,
701 int src1_sel, unsigned src1_chan_val)
702 {
703 struct r600_bytecode_alu alu;
704 int r, i;
705
706 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
707 for (i = 0; i < 4; i++) {
708 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
709 alu.op = op;
710 alu.src[0].sel = src0_sel;
711 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
712 alu.src[0].value = src0_chan_val;
713 else
714 alu.src[0].chan = src0_chan_val;
715 alu.src[1].sel = src1_sel;
716 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
717 alu.src[1].value = src1_chan_val;
718 else
719 alu.src[1].chan = src1_chan_val;
720 alu.dst.sel = dst_sel;
721 alu.dst.chan = i;
722 alu.dst.write = i == dst_chan;
723 alu.last = (i == 3);
724 r = r600_bytecode_add_alu(ctx->bc, &alu);
725 if (r)
726 return r;
727 }
728 return 0;
729 }
730
731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
732 alu.op = op;
733 alu.src[0].sel = src0_sel;
734 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
735 alu.src[0].value = src0_chan_val;
736 else
737 alu.src[0].chan = src0_chan_val;
738 alu.src[1].sel = src1_sel;
739 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
740 alu.src[1].value = src1_chan_val;
741 else
742 alu.src[1].chan = src1_chan_val;
743 alu.dst.sel = dst_sel;
744 alu.dst.chan = dst_chan;
745 alu.dst.write = 1;
746 alu.last = 1;
747 r = r600_bytecode_add_alu(ctx->bc, &alu);
748 if (r)
749 return r;
750 return 0;
751 }
752
753 /* execute a single slot ALU calculation */
754 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
755 int dst_sel, int dst_chan,
756 int src0_sel, unsigned src0_chan_val,
757 int src1_sel, unsigned src1_chan_val,
758 int src2_sel, unsigned src2_chan_val)
759 {
760 struct r600_bytecode_alu alu;
761 int r;
762
763 /* validate this for other ops */
764 assert(op == ALU_OP3_MULADD_UINT24);
765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
766 alu.op = op;
767 alu.src[0].sel = src0_sel;
768 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
769 alu.src[0].value = src0_chan_val;
770 else
771 alu.src[0].chan = src0_chan_val;
772 alu.src[1].sel = src1_sel;
773 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
774 alu.src[1].value = src1_chan_val;
775 else
776 alu.src[1].chan = src1_chan_val;
777 alu.src[2].sel = src2_sel;
778 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
779 alu.src[2].value = src2_chan_val;
780 else
781 alu.src[2].chan = src2_chan_val;
782 alu.dst.sel = dst_sel;
783 alu.dst.chan = dst_chan;
784 alu.is_op3 = 1;
785 alu.last = 1;
786 r = r600_bytecode_add_alu(ctx->bc, &alu);
787 if (r)
788 return r;
789 return 0;
790 }
791
792 /* put it in temp_reg.x */
793 static int get_lds_offset0(struct r600_shader_ctx *ctx,
794 int rel_patch_chan,
795 int temp_reg, bool is_patch_var)
796 {
797 int r;
798
799 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
800 /* ADD
801 Dimension - patch0_offset (input_vals.z),
802 Non-dim - patch0_data_offset (input_vals.w)
803 */
804 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
805 temp_reg, 0,
806 ctx->tess_output_info, 0,
807 0, rel_patch_chan,
808 ctx->tess_output_info, is_patch_var ? 3 : 2);
809 if (r)
810 return r;
811 return 0;
812 }
813
814 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
815 {
816 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
817 }
818
819 static int r600_get_temp(struct r600_shader_ctx *ctx)
820 {
821 return ctx->temp_reg + ctx->max_driver_temp_used++;
822 }
823
824 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
825 {
826 int i;
827 i = ctx->shader->noutput++;
828 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
829 ctx->shader->output[i].sid = 0;
830 ctx->shader->output[i].gpr = 0;
831 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
832 ctx->shader->output[i].write_mask = 0x4;
833 ctx->shader->output[i].spi_sid = prim_id_sid;
834
835 return 0;
836 }
837
838 static int tgsi_barrier(struct r600_shader_ctx *ctx)
839 {
840 struct r600_bytecode_alu alu;
841 int r;
842
843 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
844 alu.op = ctx->inst_info->op;
845 alu.last = 1;
846
847 r = r600_bytecode_add_alu(ctx->bc, &alu);
848 if (r)
849 return r;
850 return 0;
851 }
852
853 static int tgsi_declaration(struct r600_shader_ctx *ctx)
854 {
855 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
856 int r, i, j, count = d->Range.Last - d->Range.First + 1;
857
858 switch (d->Declaration.File) {
859 case TGSI_FILE_INPUT:
860 for (j = 0; j < count; j++) {
861 i = ctx->shader->ninput + j;
862 assert(i < ARRAY_SIZE(ctx->shader->input));
863 ctx->shader->input[i].name = d->Semantic.Name;
864 ctx->shader->input[i].sid = d->Semantic.Index + j;
865 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
866 ctx->shader->input[i].interpolate_location = d->Interp.Location;
867 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
868 if (ctx->type == PIPE_SHADER_FRAGMENT) {
869 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
870 switch (ctx->shader->input[i].name) {
871 case TGSI_SEMANTIC_FACE:
872 if (ctx->face_gpr != -1)
873 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
874 else
875 ctx->face_gpr = ctx->shader->input[i].gpr;
876 break;
877 case TGSI_SEMANTIC_COLOR:
878 ctx->colors_used++;
879 break;
880 case TGSI_SEMANTIC_POSITION:
881 ctx->fragcoord_input = i;
882 break;
883 case TGSI_SEMANTIC_PRIMID:
884 /* set this for now */
885 ctx->shader->gs_prim_id_input = true;
886 ctx->shader->ps_prim_id_input = i;
887 break;
888 }
889 if (ctx->bc->chip_class >= EVERGREEN) {
890 if ((r = evergreen_interp_input(ctx, i)))
891 return r;
892 }
893 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
894 /* FIXME probably skip inputs if they aren't passed in the ring */
895 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
896 ctx->next_ring_offset += 16;
897 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
898 ctx->shader->gs_prim_id_input = true;
899 }
900 }
901 ctx->shader->ninput += count;
902 break;
903 case TGSI_FILE_OUTPUT:
904 for (j = 0; j < count; j++) {
905 i = ctx->shader->noutput + j;
906 assert(i < ARRAY_SIZE(ctx->shader->output));
907 ctx->shader->output[i].name = d->Semantic.Name;
908 ctx->shader->output[i].sid = d->Semantic.Index + j;
909 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
910 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
911 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
912 if (ctx->type == PIPE_SHADER_VERTEX ||
913 ctx->type == PIPE_SHADER_GEOMETRY ||
914 ctx->type == PIPE_SHADER_TESS_EVAL) {
915 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
916 switch (d->Semantic.Name) {
917 case TGSI_SEMANTIC_CLIPDIST:
918 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
919 ((d->Semantic.Index + j) << 2);
920 break;
921 case TGSI_SEMANTIC_PSIZE:
922 ctx->shader->vs_out_misc_write = 1;
923 ctx->shader->vs_out_point_size = 1;
924 break;
925 case TGSI_SEMANTIC_EDGEFLAG:
926 ctx->shader->vs_out_misc_write = 1;
927 ctx->shader->vs_out_edgeflag = 1;
928 ctx->edgeflag_output = i;
929 break;
930 case TGSI_SEMANTIC_VIEWPORT_INDEX:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_viewport = 1;
933 break;
934 case TGSI_SEMANTIC_LAYER:
935 ctx->shader->vs_out_misc_write = 1;
936 ctx->shader->vs_out_layer = 1;
937 break;
938 case TGSI_SEMANTIC_CLIPVERTEX:
939 ctx->clip_vertex_write = TRUE;
940 ctx->cv_output = i;
941 break;
942 }
943 if (ctx->type == PIPE_SHADER_GEOMETRY) {
944 ctx->gs_out_ring_offset += 16;
945 }
946 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
947 switch (d->Semantic.Name) {
948 case TGSI_SEMANTIC_COLOR:
949 ctx->shader->nr_ps_max_color_exports++;
950 break;
951 }
952 }
953 }
954 ctx->shader->noutput += count;
955 break;
956 case TGSI_FILE_TEMPORARY:
957 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
958 if (d->Array.ArrayID) {
959 r600_add_gpr_array(ctx->shader,
960 ctx->file_offset[TGSI_FILE_TEMPORARY] +
961 d->Range.First,
962 d->Range.Last - d->Range.First + 1, 0x0F);
963 }
964 }
965 break;
966
967 case TGSI_FILE_CONSTANT:
968 case TGSI_FILE_SAMPLER:
969 case TGSI_FILE_SAMPLER_VIEW:
970 case TGSI_FILE_ADDRESS:
971 break;
972
973 case TGSI_FILE_SYSTEM_VALUE:
974 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
975 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
976 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
977 break; /* Already handled from allocate_system_value_inputs */
978 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
979 if (!ctx->native_integers) {
980 struct r600_bytecode_alu alu;
981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
982
983 alu.op = ALU_OP1_INT_TO_FLT;
984 alu.src[0].sel = 0;
985 alu.src[0].chan = 3;
986
987 alu.dst.sel = 0;
988 alu.dst.chan = 3;
989 alu.dst.write = 1;
990 alu.last = 1;
991
992 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
993 return r;
994 }
995 break;
996 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
997 break;
998 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
999 break;
1000 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1001 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1002 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1003 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1004 unsigned temp_reg = r600_get_temp(ctx);
1005
1006 r = get_lds_offset0(ctx, 2, temp_reg, true);
1007 if (r)
1008 return r;
1009
1010 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1011 temp_reg, 0,
1012 temp_reg, 0,
1013 V_SQ_ALU_SRC_LITERAL, param * 16);
1014 if (r)
1015 return r;
1016
1017 do_lds_fetch_values(ctx, temp_reg, dreg);
1018 }
1019 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1020 /* MOV r1.x, r0.x;
1021 MOV r1.y, r0.y;
1022 */
1023 for (i = 0; i < 2; i++) {
1024 struct r600_bytecode_alu alu;
1025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1026 alu.op = ALU_OP1_MOV;
1027 alu.src[0].sel = 0;
1028 alu.src[0].chan = 0 + i;
1029 alu.dst.sel = 1;
1030 alu.dst.chan = 0 + i;
1031 alu.dst.write = 1;
1032 alu.last = (i == 1) ? 1 : 0;
1033 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1034 return r;
1035 }
1036 /* ADD r1.z, 1.0f, -r0.x */
1037 struct r600_bytecode_alu alu;
1038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1039 alu.op = ALU_OP2_ADD;
1040 alu.src[0].sel = V_SQ_ALU_SRC_1;
1041 alu.src[1].sel = 1;
1042 alu.src[1].chan = 0;
1043 alu.src[1].neg = 1;
1044 alu.dst.sel = 1;
1045 alu.dst.chan = 2;
1046 alu.dst.write = 1;
1047 alu.last = 1;
1048 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1049 return r;
1050
1051 /* ADD r1.z, r1.z, -r1.y */
1052 alu.op = ALU_OP2_ADD;
1053 alu.src[0].sel = 1;
1054 alu.src[0].chan = 2;
1055 alu.src[1].sel = 1;
1056 alu.src[1].chan = 1;
1057 alu.src[1].neg = 1;
1058 alu.dst.sel = 1;
1059 alu.dst.chan = 2;
1060 alu.dst.write = 1;
1061 alu.last = 1;
1062 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1063 return r;
1064 break;
1065 }
1066 break;
1067 default:
1068 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1069 return -EINVAL;
1070 }
1071 return 0;
1072 }
1073
1074 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1075 {
1076 struct tgsi_parse_context parse;
1077 struct {
1078 boolean enabled;
1079 int *reg;
1080 unsigned name, alternate_name;
1081 } inputs[2] = {
1082 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1083
1084 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1085 };
1086 int i, k, num_regs = 0;
1087
1088 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1089 return 0;
1090 }
1091
1092 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1093 while (!tgsi_parse_end_of_tokens(&parse)) {
1094 tgsi_parse_token(&parse);
1095
1096 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1097 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1098 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1099 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1100 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1101 {
1102 int interpolate, location, k;
1103
1104 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1105 location = TGSI_INTERPOLATE_LOC_CENTER;
1106 inputs[1].enabled = true; /* needs SAMPLEID */
1107 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1108 location = TGSI_INTERPOLATE_LOC_CENTER;
1109 /* Needs sample positions, currently those are always available */
1110 } else {
1111 location = TGSI_INTERPOLATE_LOC_CENTROID;
1112 }
1113
1114 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1115 k = eg_get_interpolator_index(interpolate, location);
1116 ctx->eg_interpolators[k].enabled = true;
1117 }
1118 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1119 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1120 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1121 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1122 if (d->Semantic.Name == inputs[k].name ||
1123 d->Semantic.Name == inputs[k].alternate_name) {
1124 inputs[k].enabled = true;
1125 }
1126 }
1127 }
1128 }
1129 }
1130
1131 tgsi_parse_free(&parse);
1132
1133 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1134 boolean enabled = inputs[i].enabled;
1135 int *reg = inputs[i].reg;
1136 unsigned name = inputs[i].name;
1137
1138 if (enabled) {
1139 int gpr = gpr_offset + num_regs++;
1140
1141 // add to inputs, allocate a gpr
1142 k = ctx->shader->ninput ++;
1143 ctx->shader->input[k].name = name;
1144 ctx->shader->input[k].sid = 0;
1145 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1146 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1147 *reg = ctx->shader->input[k].gpr = gpr;
1148 }
1149 }
1150
1151 return gpr_offset + num_regs;
1152 }
1153
1154 /*
1155 * for evergreen we need to scan the shader to find the number of GPRs we need to
1156 * reserve for interpolation and system values
1157 *
1158 * we need to know if we are going to emit
1159 * any sample or centroid inputs
1160 * if perspective and linear are required
1161 */
1162 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1163 {
1164 unsigned i;
1165 int num_baryc;
1166 struct tgsi_parse_context parse;
1167
1168 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1169
1170 for (i = 0; i < ctx->info.num_inputs; i++) {
1171 int k;
1172 /* skip position/face/mask/sampleid */
1173 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1174 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1175 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1176 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1177 continue;
1178
1179 k = eg_get_interpolator_index(
1180 ctx->info.input_interpolate[i],
1181 ctx->info.input_interpolate_loc[i]);
1182 if (k >= 0)
1183 ctx->eg_interpolators[k].enabled = TRUE;
1184 }
1185
1186 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1187 return 0;
1188 }
1189
1190 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1191 while (!tgsi_parse_end_of_tokens(&parse)) {
1192 tgsi_parse_token(&parse);
1193
1194 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1195 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1196 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1197 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1198 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1199 {
1200 int interpolate, location, k;
1201
1202 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1203 location = TGSI_INTERPOLATE_LOC_CENTER;
1204 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1205 location = TGSI_INTERPOLATE_LOC_CENTER;
1206 } else {
1207 location = TGSI_INTERPOLATE_LOC_CENTROID;
1208 }
1209
1210 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1211 k = eg_get_interpolator_index(interpolate, location);
1212 ctx->eg_interpolators[k].enabled = true;
1213 }
1214 }
1215 }
1216
1217 tgsi_parse_free(&parse);
1218
1219 /* assign gpr to each interpolator according to priority */
1220 num_baryc = 0;
1221 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1222 if (ctx->eg_interpolators[i].enabled) {
1223 ctx->eg_interpolators[i].ij_index = num_baryc;
1224 num_baryc ++;
1225 }
1226 }
1227
1228 /* XXX PULL MODEL and LINE STIPPLE */
1229
1230 num_baryc = (num_baryc + 1) >> 1;
1231 return allocate_system_value_inputs(ctx, num_baryc);
1232 }
1233
1234 /* sample_id_sel == NULL means fetch for current sample */
1235 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1236 {
1237 struct r600_bytecode_vtx vtx;
1238 int r, t1;
1239
1240 assert(ctx->fixed_pt_position_gpr != -1);
1241
1242 t1 = r600_get_temp(ctx);
1243
1244 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1245 vtx.op = FETCH_OP_VFETCH;
1246 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1247 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1248 if (sample_id == NULL) {
1249 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1250 vtx.src_sel_x = 3;
1251 }
1252 else {
1253 struct r600_bytecode_alu alu;
1254
1255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1256 alu.op = ALU_OP1_MOV;
1257 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1258 alu.dst.sel = t1;
1259 alu.dst.write = 1;
1260 alu.last = 1;
1261 r = r600_bytecode_add_alu(ctx->bc, &alu);
1262 if (r)
1263 return r;
1264
1265 vtx.src_gpr = t1;
1266 vtx.src_sel_x = 0;
1267 }
1268 vtx.mega_fetch_count = 16;
1269 vtx.dst_gpr = t1;
1270 vtx.dst_sel_x = 0;
1271 vtx.dst_sel_y = 1;
1272 vtx.dst_sel_z = 2;
1273 vtx.dst_sel_w = 3;
1274 vtx.data_format = FMT_32_32_32_32_FLOAT;
1275 vtx.num_format_all = 2;
1276 vtx.format_comp_all = 1;
1277 vtx.use_const_fields = 0;
1278 vtx.offset = 1; // first element is size of buffer
1279 vtx.endian = r600_endian_swap(32);
1280 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1281
1282 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1283 if (r)
1284 return r;
1285
1286 return t1;
1287 }
1288
1289 static void tgsi_src(struct r600_shader_ctx *ctx,
1290 const struct tgsi_full_src_register *tgsi_src,
1291 struct r600_shader_src *r600_src)
1292 {
1293 memset(r600_src, 0, sizeof(*r600_src));
1294 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1295 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1296 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1297 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1298 r600_src->neg = tgsi_src->Register.Negate;
1299 r600_src->abs = tgsi_src->Register.Absolute;
1300
1301 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1302 int index;
1303 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1304 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1305 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1306
1307 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1308 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1309 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1310 return;
1311 }
1312 index = tgsi_src->Register.Index;
1313 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1314 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1315 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1316 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1317 r600_src->swizzle[0] = 2; // Z value
1318 r600_src->swizzle[1] = 2;
1319 r600_src->swizzle[2] = 2;
1320 r600_src->swizzle[3] = 2;
1321 r600_src->sel = ctx->face_gpr;
1322 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1323 r600_src->swizzle[0] = 3; // W value
1324 r600_src->swizzle[1] = 3;
1325 r600_src->swizzle[2] = 3;
1326 r600_src->swizzle[3] = 3;
1327 r600_src->sel = ctx->fixed_pt_position_gpr;
1328 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1329 r600_src->swizzle[0] = 0;
1330 r600_src->swizzle[1] = 1;
1331 r600_src->swizzle[2] = 4;
1332 r600_src->swizzle[3] = 4;
1333 r600_src->sel = load_sample_position(ctx, NULL, -1);
1334 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1335 r600_src->swizzle[0] = 3;
1336 r600_src->swizzle[1] = 3;
1337 r600_src->swizzle[2] = 3;
1338 r600_src->swizzle[3] = 3;
1339 r600_src->sel = 0;
1340 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1341 r600_src->swizzle[0] = 0;
1342 r600_src->swizzle[1] = 0;
1343 r600_src->swizzle[2] = 0;
1344 r600_src->swizzle[3] = 0;
1345 r600_src->sel = 0;
1346 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1347 r600_src->swizzle[0] = 3;
1348 r600_src->swizzle[1] = 3;
1349 r600_src->swizzle[2] = 3;
1350 r600_src->swizzle[3] = 3;
1351 r600_src->sel = 1;
1352 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1353 r600_src->swizzle[0] = 2;
1354 r600_src->swizzle[1] = 2;
1355 r600_src->swizzle[2] = 2;
1356 r600_src->swizzle[3] = 2;
1357 r600_src->sel = 0;
1358 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1359 r600_src->sel = 1;
1360 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1361 r600_src->sel = 3;
1362 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1363 r600_src->sel = 2;
1364 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1365 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1366 r600_src->sel = ctx->tess_input_info;
1367 r600_src->swizzle[0] = 2;
1368 r600_src->swizzle[1] = 2;
1369 r600_src->swizzle[2] = 2;
1370 r600_src->swizzle[3] = 2;
1371 } else {
1372 r600_src->sel = ctx->tess_input_info;
1373 r600_src->swizzle[0] = 3;
1374 r600_src->swizzle[1] = 3;
1375 r600_src->swizzle[2] = 3;
1376 r600_src->swizzle[3] = 3;
1377 }
1378 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1379 r600_src->sel = 0;
1380 r600_src->swizzle[0] = 0;
1381 r600_src->swizzle[1] = 0;
1382 r600_src->swizzle[2] = 0;
1383 r600_src->swizzle[3] = 0;
1384 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1385 r600_src->sel = 0;
1386 r600_src->swizzle[0] = 3;
1387 r600_src->swizzle[1] = 3;
1388 r600_src->swizzle[2] = 3;
1389 r600_src->swizzle[3] = 3;
1390 }
1391 } else {
1392 if (tgsi_src->Register.Indirect)
1393 r600_src->rel = V_SQ_REL_RELATIVE;
1394 r600_src->sel = tgsi_src->Register.Index;
1395 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1396 }
1397 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1398 if (tgsi_src->Register.Dimension) {
1399 r600_src->kc_bank = tgsi_src->Dimension.Index;
1400 if (tgsi_src->Dimension.Indirect) {
1401 r600_src->kc_rel = 1;
1402 }
1403 }
1404 }
1405 }
1406
1407 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1408 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1409 unsigned int dst_reg)
1410 {
1411 struct r600_bytecode_vtx vtx;
1412 unsigned int ar_reg;
1413 int r;
1414
1415 if (offset) {
1416 struct r600_bytecode_alu alu;
1417
1418 memset(&alu, 0, sizeof(alu));
1419
1420 alu.op = ALU_OP2_ADD_INT;
1421 alu.src[0].sel = ctx->bc->ar_reg;
1422 alu.src[0].chan = ar_chan;
1423
1424 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1425 alu.src[1].value = offset;
1426
1427 alu.dst.sel = dst_reg;
1428 alu.dst.chan = ar_chan;
1429 alu.dst.write = 1;
1430 alu.last = 1;
1431
1432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1433 return r;
1434
1435 ar_reg = dst_reg;
1436 } else {
1437 ar_reg = ctx->bc->ar_reg;
1438 }
1439
1440 memset(&vtx, 0, sizeof(vtx));
1441 vtx.buffer_id = cb_idx;
1442 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1443 vtx.src_gpr = ar_reg;
1444 vtx.src_sel_x = ar_chan;
1445 vtx.mega_fetch_count = 16;
1446 vtx.dst_gpr = dst_reg;
1447 vtx.dst_sel_x = 0; /* SEL_X */
1448 vtx.dst_sel_y = 1; /* SEL_Y */
1449 vtx.dst_sel_z = 2; /* SEL_Z */
1450 vtx.dst_sel_w = 3; /* SEL_W */
1451 vtx.data_format = FMT_32_32_32_32_FLOAT;
1452 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1453 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1454 vtx.endian = r600_endian_swap(32);
1455 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1456
1457 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1458 return r;
1459
1460 return 0;
1461 }
1462
1463 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1464 {
1465 struct r600_bytecode_vtx vtx;
1466 int r;
1467 unsigned index = src->Register.Index;
1468 unsigned vtx_id = src->Dimension.Index;
1469 int offset_reg = vtx_id / 3;
1470 int offset_chan = vtx_id % 3;
1471 int t2 = 0;
1472
1473 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1474 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1475
1476 if (offset_reg == 0 && offset_chan == 2)
1477 offset_chan = 3;
1478
1479 if (src->Dimension.Indirect || src->Register.Indirect)
1480 t2 = r600_get_temp(ctx);
1481
1482 if (src->Dimension.Indirect) {
1483 int treg[3];
1484 struct r600_bytecode_alu alu;
1485 int r, i;
1486 unsigned addr_reg;
1487 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1488 if (src->DimIndirect.Index > 0) {
1489 r = single_alu_op2(ctx, ALU_OP1_MOV,
1490 ctx->bc->ar_reg, 0,
1491 addr_reg, 0,
1492 0, 0);
1493 if (r)
1494 return r;
1495 }
1496 /*
1497 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1498 at least this is what fglrx seems to do. */
1499 for (i = 0; i < 3; i++) {
1500 treg[i] = r600_get_temp(ctx);
1501 }
1502 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1503
1504 for (i = 0; i < 3; i++) {
1505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1506 alu.op = ALU_OP1_MOV;
1507 alu.src[0].sel = 0;
1508 alu.src[0].chan = i == 2 ? 3 : i;
1509 alu.dst.sel = treg[i];
1510 alu.dst.chan = 0;
1511 alu.dst.write = 1;
1512 alu.last = 1;
1513 r = r600_bytecode_add_alu(ctx->bc, &alu);
1514 if (r)
1515 return r;
1516 }
1517 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1518 alu.op = ALU_OP1_MOV;
1519 alu.src[0].sel = treg[0];
1520 alu.src[0].rel = 1;
1521 alu.dst.sel = t2;
1522 alu.dst.write = 1;
1523 alu.last = 1;
1524 r = r600_bytecode_add_alu(ctx->bc, &alu);
1525 if (r)
1526 return r;
1527 offset_reg = t2;
1528 offset_chan = 0;
1529 }
1530
1531 if (src->Register.Indirect) {
1532 int addr_reg;
1533 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1534
1535 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1536
1537 /* pull the value from index_reg */
1538 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1539 t2, 1,
1540 addr_reg, 0,
1541 V_SQ_ALU_SRC_LITERAL, first);
1542 if (r)
1543 return r;
1544 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1545 t2, 0,
1546 t2, 1,
1547 V_SQ_ALU_SRC_LITERAL, 4,
1548 offset_reg, offset_chan);
1549 if (r)
1550 return r;
1551 offset_reg = t2;
1552 offset_chan = 0;
1553 index = src->Register.Index - first;
1554 }
1555
1556 memset(&vtx, 0, sizeof(vtx));
1557 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1558 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1559 vtx.src_gpr = offset_reg;
1560 vtx.src_sel_x = offset_chan;
1561 vtx.offset = index * 16; /*bytes*/
1562 vtx.mega_fetch_count = 16;
1563 vtx.dst_gpr = dst_reg;
1564 vtx.dst_sel_x = 0; /* SEL_X */
1565 vtx.dst_sel_y = 1; /* SEL_Y */
1566 vtx.dst_sel_z = 2; /* SEL_Z */
1567 vtx.dst_sel_w = 3; /* SEL_W */
1568 if (ctx->bc->chip_class >= EVERGREEN) {
1569 vtx.use_const_fields = 1;
1570 } else {
1571 vtx.data_format = FMT_32_32_32_32_FLOAT;
1572 }
1573
1574 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1575 return r;
1576
1577 return 0;
1578 }
1579
1580 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1581 {
1582 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1583 unsigned i;
1584
1585 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1586 struct tgsi_full_src_register *src = &inst->Src[i];
1587
1588 if (src->Register.File == TGSI_FILE_INPUT) {
1589 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1590 /* primitive id is in R0.z */
1591 ctx->src[i].sel = 0;
1592 ctx->src[i].swizzle[0] = 2;
1593 }
1594 }
1595 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1596 int treg = r600_get_temp(ctx);
1597
1598 fetch_gs_input(ctx, src, treg);
1599 ctx->src[i].sel = treg;
1600 ctx->src[i].rel = 0;
1601 }
1602 }
1603 return 0;
1604 }
1605
1606
1607 /* Tessellation shaders pass outputs to the next shader using LDS.
1608 *
1609 * LS outputs = TCS(HS) inputs
1610 * TCS(HS) outputs = TES(DS) inputs
1611 *
1612 * The LDS layout is:
1613 * - TCS inputs for patch 0
1614 * - TCS inputs for patch 1
1615 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1616 * - ...
1617 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1618 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1619 * - TCS outputs for patch 1
1620 * - Per-patch TCS outputs for patch 1
1621 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1622 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1623 * - ...
1624 *
1625 * All three shaders VS(LS), TCS, TES share the same LDS space.
1626 */
1627 /* this will return with the dw address in temp_reg.x */
1628 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1629 const struct tgsi_full_dst_register *dst,
1630 const struct tgsi_full_src_register *src,
1631 int stride_bytes_reg, int stride_bytes_chan)
1632 {
1633 struct tgsi_full_dst_register reg;
1634 ubyte *name, *index, *array_first;
1635 int r;
1636 int param;
1637 struct tgsi_shader_info *info = &ctx->info;
1638 /* Set the register description. The address computation is the same
1639 * for sources and destinations. */
1640 if (src) {
1641 reg.Register.File = src->Register.File;
1642 reg.Register.Index = src->Register.Index;
1643 reg.Register.Indirect = src->Register.Indirect;
1644 reg.Register.Dimension = src->Register.Dimension;
1645 reg.Indirect = src->Indirect;
1646 reg.Dimension = src->Dimension;
1647 reg.DimIndirect = src->DimIndirect;
1648 } else
1649 reg = *dst;
1650
1651 /* If the register is 2-dimensional (e.g. an array of vertices
1652 * in a primitive), calculate the base address of the vertex. */
1653 if (reg.Register.Dimension) {
1654 int sel, chan;
1655 if (reg.Dimension.Indirect) {
1656 unsigned addr_reg;
1657 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1658
1659 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1660 /* pull the value from index_reg */
1661 sel = addr_reg;
1662 chan = 0;
1663 } else {
1664 sel = V_SQ_ALU_SRC_LITERAL;
1665 chan = reg.Dimension.Index;
1666 }
1667
1668 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1669 temp_reg, 0,
1670 stride_bytes_reg, stride_bytes_chan,
1671 sel, chan,
1672 temp_reg, 0);
1673 if (r)
1674 return r;
1675 }
1676
1677 if (reg.Register.File == TGSI_FILE_INPUT) {
1678 name = info->input_semantic_name;
1679 index = info->input_semantic_index;
1680 array_first = info->input_array_first;
1681 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1682 name = info->output_semantic_name;
1683 index = info->output_semantic_index;
1684 array_first = info->output_array_first;
1685 } else {
1686 assert(0);
1687 return -1;
1688 }
1689 if (reg.Register.Indirect) {
1690 int addr_reg;
1691 int first;
1692 /* Add the relative address of the element. */
1693 if (reg.Indirect.ArrayID)
1694 first = array_first[reg.Indirect.ArrayID];
1695 else
1696 first = reg.Register.Index;
1697
1698 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1699
1700 /* pull the value from index_reg */
1701 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1702 temp_reg, 0,
1703 V_SQ_ALU_SRC_LITERAL, 16,
1704 addr_reg, 0,
1705 temp_reg, 0);
1706 if (r)
1707 return r;
1708
1709 param = r600_get_lds_unique_index(name[first],
1710 index[first]);
1711
1712 } else {
1713 param = r600_get_lds_unique_index(name[reg.Register.Index],
1714 index[reg.Register.Index]);
1715 }
1716
1717 /* add to base_addr - passed in temp_reg.x */
1718 if (param) {
1719 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1720 temp_reg, 0,
1721 temp_reg, 0,
1722 V_SQ_ALU_SRC_LITERAL, param * 16);
1723 if (r)
1724 return r;
1725
1726 }
1727 return 0;
1728 }
1729
1730 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1731 unsigned dst_reg)
1732 {
1733 struct r600_bytecode_alu alu;
1734 int r, i;
1735
1736 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1737 ctx->bc->force_add_cf = 1;
1738 for (i = 1; i < 4; i++) {
1739 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1740 temp_reg, i,
1741 temp_reg, 0,
1742 V_SQ_ALU_SRC_LITERAL, 4 * i);
1743 if (r)
1744 return r;
1745 }
1746 for (i = 0; i < 4; i++) {
1747 /* emit an LDS_READ_RET */
1748 memset(&alu, 0, sizeof(alu));
1749 alu.op = LDS_OP1_LDS_READ_RET;
1750 alu.src[0].sel = temp_reg;
1751 alu.src[0].chan = i;
1752 alu.src[1].sel = V_SQ_ALU_SRC_0;
1753 alu.src[2].sel = V_SQ_ALU_SRC_0;
1754 alu.dst.chan = 0;
1755 alu.is_lds_idx_op = true;
1756 alu.last = 1;
1757 r = r600_bytecode_add_alu(ctx->bc, &alu);
1758 if (r)
1759 return r;
1760 }
1761 for (i = 0; i < 4; i++) {
1762 /* then read from LDS_OQ_A_POP */
1763 memset(&alu, 0, sizeof(alu));
1764
1765 alu.op = ALU_OP1_MOV;
1766 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1767 alu.src[0].chan = 0;
1768 alu.dst.sel = dst_reg;
1769 alu.dst.chan = i;
1770 alu.dst.write = 1;
1771 alu.last = 1;
1772 r = r600_bytecode_add_alu(ctx->bc, &alu);
1773 if (r)
1774 return r;
1775 }
1776 return 0;
1777 }
1778
1779 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1780 {
1781 int r;
1782 unsigned temp_reg = r600_get_temp(ctx);
1783
1784 r = get_lds_offset0(ctx, 2, temp_reg,
1785 src->Register.Dimension ? false : true);
1786 if (r)
1787 return r;
1788
1789 /* the base address is now in temp.x */
1790 r = r600_get_byte_address(ctx, temp_reg,
1791 NULL, src, ctx->tess_output_info, 1);
1792 if (r)
1793 return r;
1794
1795 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1796 if (r)
1797 return r;
1798 return 0;
1799 }
1800
1801 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1802 {
1803 int r;
1804 unsigned temp_reg = r600_get_temp(ctx);
1805
1806 /* t.x = ips * r0.y */
1807 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1808 temp_reg, 0,
1809 ctx->tess_input_info, 0,
1810 0, 1);
1811
1812 if (r)
1813 return r;
1814
1815 /* the base address is now in temp.x */
1816 r = r600_get_byte_address(ctx, temp_reg,
1817 NULL, src, ctx->tess_input_info, 1);
1818 if (r)
1819 return r;
1820
1821 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1822 if (r)
1823 return r;
1824 return 0;
1825 }
1826
1827 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1828 {
1829 int r;
1830 unsigned temp_reg = r600_get_temp(ctx);
1831
1832 r = get_lds_offset0(ctx, 1, temp_reg,
1833 src->Register.Dimension ? false : true);
1834 if (r)
1835 return r;
1836 /* the base address is now in temp.x */
1837 r = r600_get_byte_address(ctx, temp_reg,
1838 NULL, src,
1839 ctx->tess_output_info, 1);
1840 if (r)
1841 return r;
1842
1843 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1844 if (r)
1845 return r;
1846 return 0;
1847 }
1848
1849 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1850 {
1851 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1852 unsigned i;
1853
1854 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1855 struct tgsi_full_src_register *src = &inst->Src[i];
1856
1857 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1858 int treg = r600_get_temp(ctx);
1859 fetch_tes_input(ctx, src, treg);
1860 ctx->src[i].sel = treg;
1861 ctx->src[i].rel = 0;
1862 }
1863 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1864 int treg = r600_get_temp(ctx);
1865 fetch_tcs_input(ctx, src, treg);
1866 ctx->src[i].sel = treg;
1867 ctx->src[i].rel = 0;
1868 }
1869 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1870 int treg = r600_get_temp(ctx);
1871 fetch_tcs_output(ctx, src, treg);
1872 ctx->src[i].sel = treg;
1873 ctx->src[i].rel = 0;
1874 }
1875 }
1876 return 0;
1877 }
1878
1879 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1880 {
1881 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1882 struct r600_bytecode_alu alu;
1883 int i, j, k, nconst, r;
1884
1885 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1886 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1887 nconst++;
1888 }
1889 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1890 }
1891 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1892 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1893 continue;
1894 }
1895
1896 if (ctx->src[i].rel) {
1897 int chan = inst->Src[i].Indirect.Swizzle;
1898 int treg = r600_get_temp(ctx);
1899 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1900 return r;
1901
1902 ctx->src[i].kc_bank = 0;
1903 ctx->src[i].kc_rel = 0;
1904 ctx->src[i].sel = treg;
1905 ctx->src[i].rel = 0;
1906 j--;
1907 } else if (j > 0) {
1908 int treg = r600_get_temp(ctx);
1909 for (k = 0; k < 4; k++) {
1910 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1911 alu.op = ALU_OP1_MOV;
1912 alu.src[0].sel = ctx->src[i].sel;
1913 alu.src[0].chan = k;
1914 alu.src[0].rel = ctx->src[i].rel;
1915 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1916 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1917 alu.dst.sel = treg;
1918 alu.dst.chan = k;
1919 alu.dst.write = 1;
1920 if (k == 3)
1921 alu.last = 1;
1922 r = r600_bytecode_add_alu(ctx->bc, &alu);
1923 if (r)
1924 return r;
1925 }
1926 ctx->src[i].sel = treg;
1927 ctx->src[i].rel =0;
1928 j--;
1929 }
1930 }
1931 return 0;
1932 }
1933
1934 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1935 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1936 {
1937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1938 struct r600_bytecode_alu alu;
1939 int i, j, k, nliteral, r;
1940
1941 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1942 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1943 nliteral++;
1944 }
1945 }
1946 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1947 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1948 int treg = r600_get_temp(ctx);
1949 for (k = 0; k < 4; k++) {
1950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1951 alu.op = ALU_OP1_MOV;
1952 alu.src[0].sel = ctx->src[i].sel;
1953 alu.src[0].chan = k;
1954 alu.src[0].value = ctx->src[i].value[k];
1955 alu.dst.sel = treg;
1956 alu.dst.chan = k;
1957 alu.dst.write = 1;
1958 if (k == 3)
1959 alu.last = 1;
1960 r = r600_bytecode_add_alu(ctx->bc, &alu);
1961 if (r)
1962 return r;
1963 }
1964 ctx->src[i].sel = treg;
1965 j--;
1966 }
1967 }
1968 return 0;
1969 }
1970
1971 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1972 {
1973 int i, r, count = ctx->shader->ninput;
1974
1975 for (i = 0; i < count; i++) {
1976 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1977 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1978 if (r)
1979 return r;
1980 }
1981 }
1982 return 0;
1983 }
1984
1985 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1986 int stream, unsigned *stream_item_size)
1987 {
1988 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1989 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1990 int i, j, r;
1991
1992 /* Sanity checking. */
1993 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1994 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1995 r = -EINVAL;
1996 goto out_err;
1997 }
1998 for (i = 0; i < so->num_outputs; i++) {
1999 if (so->output[i].output_buffer >= 4) {
2000 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2001 so->output[i].output_buffer);
2002 r = -EINVAL;
2003 goto out_err;
2004 }
2005 }
2006
2007 /* Initialize locations where the outputs are stored. */
2008 for (i = 0; i < so->num_outputs; i++) {
2009
2010 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2011 start_comp[i] = so->output[i].start_component;
2012 /* Lower outputs with dst_offset < start_component.
2013 *
2014 * We can only output 4D vectors with a write mask, e.g. we can
2015 * only output the W component at offset 3, etc. If we want
2016 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2017 * to move it to X and output X. */
2018 if (so->output[i].dst_offset < so->output[i].start_component) {
2019 unsigned tmp = r600_get_temp(ctx);
2020
2021 for (j = 0; j < so->output[i].num_components; j++) {
2022 struct r600_bytecode_alu alu;
2023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2024 alu.op = ALU_OP1_MOV;
2025 alu.src[0].sel = so_gpr[i];
2026 alu.src[0].chan = so->output[i].start_component + j;
2027
2028 alu.dst.sel = tmp;
2029 alu.dst.chan = j;
2030 alu.dst.write = 1;
2031 if (j == so->output[i].num_components - 1)
2032 alu.last = 1;
2033 r = r600_bytecode_add_alu(ctx->bc, &alu);
2034 if (r)
2035 return r;
2036 }
2037 start_comp[i] = 0;
2038 so_gpr[i] = tmp;
2039 }
2040 }
2041
2042 /* Write outputs to buffers. */
2043 for (i = 0; i < so->num_outputs; i++) {
2044 struct r600_bytecode_output output;
2045
2046 if (stream != -1 && stream != so->output[i].output_buffer)
2047 continue;
2048
2049 memset(&output, 0, sizeof(struct r600_bytecode_output));
2050 output.gpr = so_gpr[i];
2051 output.elem_size = so->output[i].num_components - 1;
2052 if (output.elem_size == 2)
2053 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2054 output.array_base = so->output[i].dst_offset - start_comp[i];
2055 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2056 output.burst_count = 1;
2057 /* array_size is an upper limit for the burst_count
2058 * with MEM_STREAM instructions */
2059 output.array_size = 0xFFF;
2060 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2061
2062 if (ctx->bc->chip_class >= EVERGREEN) {
2063 switch (so->output[i].output_buffer) {
2064 case 0:
2065 output.op = CF_OP_MEM_STREAM0_BUF0;
2066 break;
2067 case 1:
2068 output.op = CF_OP_MEM_STREAM0_BUF1;
2069 break;
2070 case 2:
2071 output.op = CF_OP_MEM_STREAM0_BUF2;
2072 break;
2073 case 3:
2074 output.op = CF_OP_MEM_STREAM0_BUF3;
2075 break;
2076 }
2077 output.op += so->output[i].stream * 4;
2078 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2079 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2080 } else {
2081 switch (so->output[i].output_buffer) {
2082 case 0:
2083 output.op = CF_OP_MEM_STREAM0;
2084 break;
2085 case 1:
2086 output.op = CF_OP_MEM_STREAM1;
2087 break;
2088 case 2:
2089 output.op = CF_OP_MEM_STREAM2;
2090 break;
2091 case 3:
2092 output.op = CF_OP_MEM_STREAM3;
2093 break;
2094 }
2095 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2096 }
2097 r = r600_bytecode_add_output(ctx->bc, &output);
2098 if (r)
2099 goto out_err;
2100 }
2101 return 0;
2102 out_err:
2103 return r;
2104 }
2105
2106 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2107 {
2108 struct r600_bytecode_alu alu;
2109 unsigned reg;
2110
2111 if (!ctx->shader->vs_out_edgeflag)
2112 return;
2113
2114 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2115
2116 /* clamp(x, 0, 1) */
2117 memset(&alu, 0, sizeof(alu));
2118 alu.op = ALU_OP1_MOV;
2119 alu.src[0].sel = reg;
2120 alu.dst.sel = reg;
2121 alu.dst.write = 1;
2122 alu.dst.clamp = 1;
2123 alu.last = 1;
2124 r600_bytecode_add_alu(ctx->bc, &alu);
2125
2126 memset(&alu, 0, sizeof(alu));
2127 alu.op = ALU_OP1_FLT_TO_INT;
2128 alu.src[0].sel = reg;
2129 alu.dst.sel = reg;
2130 alu.dst.write = 1;
2131 alu.last = 1;
2132 r600_bytecode_add_alu(ctx->bc, &alu);
2133 }
2134
2135 static int generate_gs_copy_shader(struct r600_context *rctx,
2136 struct r600_pipe_shader *gs,
2137 struct pipe_stream_output_info *so)
2138 {
2139 struct r600_shader_ctx ctx = {};
2140 struct r600_shader *gs_shader = &gs->shader;
2141 struct r600_pipe_shader *cshader;
2142 int ocnt = gs_shader->noutput;
2143 struct r600_bytecode_alu alu;
2144 struct r600_bytecode_vtx vtx;
2145 struct r600_bytecode_output output;
2146 struct r600_bytecode_cf *cf_jump, *cf_pop,
2147 *last_exp_pos = NULL, *last_exp_param = NULL;
2148 int i, j, next_clip_pos = 61, next_param = 0;
2149 int ring;
2150 bool only_ring_0 = true;
2151 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2152 if (!cshader)
2153 return 0;
2154
2155 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2156 sizeof(struct r600_shader_io));
2157
2158 cshader->shader.noutput = ocnt;
2159
2160 ctx.shader = &cshader->shader;
2161 ctx.bc = &ctx.shader->bc;
2162 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2163
2164 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2165 rctx->screen->has_compressed_msaa_texturing);
2166
2167 ctx.bc->isa = rctx->isa;
2168
2169 cf_jump = NULL;
2170 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2171
2172 /* R0.x = R0.x & 0x3fffffff */
2173 memset(&alu, 0, sizeof(alu));
2174 alu.op = ALU_OP2_AND_INT;
2175 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2176 alu.src[1].value = 0x3fffffff;
2177 alu.dst.write = 1;
2178 r600_bytecode_add_alu(ctx.bc, &alu);
2179
2180 /* R0.y = R0.x >> 30 */
2181 memset(&alu, 0, sizeof(alu));
2182 alu.op = ALU_OP2_LSHR_INT;
2183 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2184 alu.src[1].value = 0x1e;
2185 alu.dst.chan = 1;
2186 alu.dst.write = 1;
2187 alu.last = 1;
2188 r600_bytecode_add_alu(ctx.bc, &alu);
2189
2190 /* fetch vertex data from GSVS ring */
2191 for (i = 0; i < ocnt; ++i) {
2192 struct r600_shader_io *out = &ctx.shader->output[i];
2193
2194 out->gpr = i + 1;
2195 out->ring_offset = i * 16;
2196
2197 memset(&vtx, 0, sizeof(vtx));
2198 vtx.op = FETCH_OP_VFETCH;
2199 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2200 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2201 vtx.mega_fetch_count = 16;
2202 vtx.offset = out->ring_offset;
2203 vtx.dst_gpr = out->gpr;
2204 vtx.src_gpr = 0;
2205 vtx.dst_sel_x = 0;
2206 vtx.dst_sel_y = 1;
2207 vtx.dst_sel_z = 2;
2208 vtx.dst_sel_w = 3;
2209 if (rctx->b.chip_class >= EVERGREEN) {
2210 vtx.use_const_fields = 1;
2211 } else {
2212 vtx.data_format = FMT_32_32_32_32_FLOAT;
2213 }
2214
2215 r600_bytecode_add_vtx(ctx.bc, &vtx);
2216 }
2217 ctx.temp_reg = i + 1;
2218 for (ring = 3; ring >= 0; --ring) {
2219 bool enabled = false;
2220 for (i = 0; i < so->num_outputs; i++) {
2221 if (so->output[i].stream == ring) {
2222 enabled = true;
2223 if (ring > 0)
2224 only_ring_0 = false;
2225 break;
2226 }
2227 }
2228 if (ring != 0 && !enabled) {
2229 cshader->shader.ring_item_sizes[ring] = 0;
2230 continue;
2231 }
2232
2233 if (cf_jump) {
2234 // Patch up jump label
2235 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2236 cf_pop = ctx.bc->cf_last;
2237
2238 cf_jump->cf_addr = cf_pop->id + 2;
2239 cf_jump->pop_count = 1;
2240 cf_pop->cf_addr = cf_pop->id + 2;
2241 cf_pop->pop_count = 1;
2242 }
2243
2244 /* PRED_SETE_INT __, R0.y, ring */
2245 memset(&alu, 0, sizeof(alu));
2246 alu.op = ALU_OP2_PRED_SETE_INT;
2247 alu.src[0].chan = 1;
2248 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2249 alu.src[1].value = ring;
2250 alu.execute_mask = 1;
2251 alu.update_pred = 1;
2252 alu.last = 1;
2253 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2254
2255 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2256 cf_jump = ctx.bc->cf_last;
2257
2258 if (enabled)
2259 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2260 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2261 }
2262
2263 /* bc adds nops - copy it */
2264 if (ctx.bc->chip_class == R600) {
2265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2266 alu.op = ALU_OP0_NOP;
2267 alu.last = 1;
2268 r600_bytecode_add_alu(ctx.bc, &alu);
2269
2270 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2271 }
2272
2273 /* export vertex data */
2274 /* XXX factor out common code with r600_shader_from_tgsi ? */
2275 for (i = 0; i < ocnt; ++i) {
2276 struct r600_shader_io *out = &ctx.shader->output[i];
2277 bool instream0 = true;
2278 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2279 continue;
2280
2281 for (j = 0; j < so->num_outputs; j++) {
2282 if (so->output[j].register_index == i) {
2283 if (so->output[j].stream == 0)
2284 break;
2285 if (so->output[j].stream > 0)
2286 instream0 = false;
2287 }
2288 }
2289 if (!instream0)
2290 continue;
2291 memset(&output, 0, sizeof(output));
2292 output.gpr = out->gpr;
2293 output.elem_size = 3;
2294 output.swizzle_x = 0;
2295 output.swizzle_y = 1;
2296 output.swizzle_z = 2;
2297 output.swizzle_w = 3;
2298 output.burst_count = 1;
2299 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2300 output.op = CF_OP_EXPORT;
2301 switch (out->name) {
2302 case TGSI_SEMANTIC_POSITION:
2303 output.array_base = 60;
2304 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2305 break;
2306
2307 case TGSI_SEMANTIC_PSIZE:
2308 output.array_base = 61;
2309 if (next_clip_pos == 61)
2310 next_clip_pos = 62;
2311 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2312 output.swizzle_y = 7;
2313 output.swizzle_z = 7;
2314 output.swizzle_w = 7;
2315 ctx.shader->vs_out_misc_write = 1;
2316 ctx.shader->vs_out_point_size = 1;
2317 break;
2318 case TGSI_SEMANTIC_LAYER:
2319 if (out->spi_sid) {
2320 /* duplicate it as PARAM to pass to the pixel shader */
2321 output.array_base = next_param++;
2322 r600_bytecode_add_output(ctx.bc, &output);
2323 last_exp_param = ctx.bc->cf_last;
2324 }
2325 output.array_base = 61;
2326 if (next_clip_pos == 61)
2327 next_clip_pos = 62;
2328 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2329 output.swizzle_x = 7;
2330 output.swizzle_y = 7;
2331 output.swizzle_z = 0;
2332 output.swizzle_w = 7;
2333 ctx.shader->vs_out_misc_write = 1;
2334 ctx.shader->vs_out_layer = 1;
2335 break;
2336 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2337 if (out->spi_sid) {
2338 /* duplicate it as PARAM to pass to the pixel shader */
2339 output.array_base = next_param++;
2340 r600_bytecode_add_output(ctx.bc, &output);
2341 last_exp_param = ctx.bc->cf_last;
2342 }
2343 output.array_base = 61;
2344 if (next_clip_pos == 61)
2345 next_clip_pos = 62;
2346 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2347 ctx.shader->vs_out_misc_write = 1;
2348 ctx.shader->vs_out_viewport = 1;
2349 output.swizzle_x = 7;
2350 output.swizzle_y = 7;
2351 output.swizzle_z = 7;
2352 output.swizzle_w = 0;
2353 break;
2354 case TGSI_SEMANTIC_CLIPDIST:
2355 /* spi_sid is 0 for clipdistance outputs that were generated
2356 * for clipvertex - we don't need to pass them to PS */
2357 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2358 if (out->spi_sid) {
2359 /* duplicate it as PARAM to pass to the pixel shader */
2360 output.array_base = next_param++;
2361 r600_bytecode_add_output(ctx.bc, &output);
2362 last_exp_param = ctx.bc->cf_last;
2363 }
2364 output.array_base = next_clip_pos++;
2365 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2366 break;
2367 case TGSI_SEMANTIC_FOG:
2368 output.swizzle_y = 4; /* 0 */
2369 output.swizzle_z = 4; /* 0 */
2370 output.swizzle_w = 5; /* 1 */
2371 break;
2372 default:
2373 output.array_base = next_param++;
2374 break;
2375 }
2376 r600_bytecode_add_output(ctx.bc, &output);
2377 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2378 last_exp_param = ctx.bc->cf_last;
2379 else
2380 last_exp_pos = ctx.bc->cf_last;
2381 }
2382
2383 if (!last_exp_pos) {
2384 memset(&output, 0, sizeof(output));
2385 output.gpr = 0;
2386 output.elem_size = 3;
2387 output.swizzle_x = 7;
2388 output.swizzle_y = 7;
2389 output.swizzle_z = 7;
2390 output.swizzle_w = 7;
2391 output.burst_count = 1;
2392 output.type = 2;
2393 output.op = CF_OP_EXPORT;
2394 output.array_base = 60;
2395 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2396 r600_bytecode_add_output(ctx.bc, &output);
2397 last_exp_pos = ctx.bc->cf_last;
2398 }
2399
2400 if (!last_exp_param) {
2401 memset(&output, 0, sizeof(output));
2402 output.gpr = 0;
2403 output.elem_size = 3;
2404 output.swizzle_x = 7;
2405 output.swizzle_y = 7;
2406 output.swizzle_z = 7;
2407 output.swizzle_w = 7;
2408 output.burst_count = 1;
2409 output.type = 2;
2410 output.op = CF_OP_EXPORT;
2411 output.array_base = next_param++;
2412 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2413 r600_bytecode_add_output(ctx.bc, &output);
2414 last_exp_param = ctx.bc->cf_last;
2415 }
2416
2417 last_exp_pos->op = CF_OP_EXPORT_DONE;
2418 last_exp_param->op = CF_OP_EXPORT_DONE;
2419
2420 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2421 cf_pop = ctx.bc->cf_last;
2422
2423 cf_jump->cf_addr = cf_pop->id + 2;
2424 cf_jump->pop_count = 1;
2425 cf_pop->cf_addr = cf_pop->id + 2;
2426 cf_pop->pop_count = 1;
2427
2428 if (ctx.bc->chip_class == CAYMAN)
2429 cm_bytecode_add_cf_end(ctx.bc);
2430 else {
2431 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2432 ctx.bc->cf_last->end_of_program = 1;
2433 }
2434
2435 gs->gs_copy_shader = cshader;
2436 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2437
2438 ctx.bc->nstack = 1;
2439
2440 return r600_bytecode_build(ctx.bc);
2441 }
2442
2443 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2444 {
2445 if (ind) {
2446 struct r600_bytecode_alu alu;
2447 int r;
2448
2449 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2450 alu.op = ALU_OP2_ADD_INT;
2451 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2452 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2453 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2454 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2455 alu.dst.write = 1;
2456 alu.last = 1;
2457 r = r600_bytecode_add_alu(ctx->bc, &alu);
2458 if (r)
2459 return r;
2460 }
2461 return 0;
2462 }
2463
2464 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2465 {
2466 struct r600_bytecode_output output;
2467 int i, k, ring_offset;
2468 int effective_stream = stream == -1 ? 0 : stream;
2469 int idx = 0;
2470
2471 for (i = 0; i < ctx->shader->noutput; i++) {
2472 if (ctx->gs_for_vs) {
2473 /* for ES we need to lookup corresponding ring offset expected by GS
2474 * (map this output to GS input by name and sid) */
2475 /* FIXME precompute offsets */
2476 ring_offset = -1;
2477 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2478 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2479 struct r600_shader_io *out = &ctx->shader->output[i];
2480 if (in->name == out->name && in->sid == out->sid)
2481 ring_offset = in->ring_offset;
2482 }
2483
2484 if (ring_offset == -1)
2485 continue;
2486 } else {
2487 ring_offset = idx * 16;
2488 idx++;
2489 }
2490
2491 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2492 continue;
2493 /* next_ring_offset after parsing input decls contains total size of
2494 * single vertex data, gs_next_vertex - current vertex index */
2495 if (!ind)
2496 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2497
2498 memset(&output, 0, sizeof(struct r600_bytecode_output));
2499 output.gpr = ctx->shader->output[i].gpr;
2500 output.elem_size = 3;
2501 output.comp_mask = 0xF;
2502 output.burst_count = 1;
2503
2504 if (ind)
2505 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2506 else
2507 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2508
2509 switch (stream) {
2510 default:
2511 case 0:
2512 output.op = CF_OP_MEM_RING; break;
2513 case 1:
2514 output.op = CF_OP_MEM_RING1; break;
2515 case 2:
2516 output.op = CF_OP_MEM_RING2; break;
2517 case 3:
2518 output.op = CF_OP_MEM_RING3; break;
2519 }
2520
2521 if (ind) {
2522 output.array_base = ring_offset >> 2; /* in dwords */
2523 output.array_size = 0xfff;
2524 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2525 } else
2526 output.array_base = ring_offset >> 2; /* in dwords */
2527 r600_bytecode_add_output(ctx->bc, &output);
2528 }
2529
2530 ++ctx->gs_next_vertex;
2531 return 0;
2532 }
2533
2534
2535 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2536 {
2537 int r;
2538 struct r600_bytecode_vtx vtx;
2539 int temp_val = ctx->temp_reg;
2540 /* need to store the TCS output somewhere */
2541 r = single_alu_op2(ctx, ALU_OP1_MOV,
2542 temp_val, 0,
2543 V_SQ_ALU_SRC_LITERAL, 0,
2544 0, 0);
2545 if (r)
2546 return r;
2547
2548 /* used by VS/TCS */
2549 if (ctx->tess_input_info) {
2550 /* fetch tcs input values into resv space */
2551 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2552 vtx.op = FETCH_OP_VFETCH;
2553 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2554 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2555 vtx.mega_fetch_count = 16;
2556 vtx.data_format = FMT_32_32_32_32;
2557 vtx.num_format_all = 2;
2558 vtx.format_comp_all = 1;
2559 vtx.use_const_fields = 0;
2560 vtx.endian = r600_endian_swap(32);
2561 vtx.srf_mode_all = 1;
2562 vtx.offset = 0;
2563 vtx.dst_gpr = ctx->tess_input_info;
2564 vtx.dst_sel_x = 0;
2565 vtx.dst_sel_y = 1;
2566 vtx.dst_sel_z = 2;
2567 vtx.dst_sel_w = 3;
2568 vtx.src_gpr = temp_val;
2569 vtx.src_sel_x = 0;
2570
2571 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2572 if (r)
2573 return r;
2574 }
2575
2576 /* used by TCS/TES */
2577 if (ctx->tess_output_info) {
2578 /* fetch tcs output values into resv space */
2579 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2580 vtx.op = FETCH_OP_VFETCH;
2581 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2582 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2583 vtx.mega_fetch_count = 16;
2584 vtx.data_format = FMT_32_32_32_32;
2585 vtx.num_format_all = 2;
2586 vtx.format_comp_all = 1;
2587 vtx.use_const_fields = 0;
2588 vtx.endian = r600_endian_swap(32);
2589 vtx.srf_mode_all = 1;
2590 vtx.offset = 16;
2591 vtx.dst_gpr = ctx->tess_output_info;
2592 vtx.dst_sel_x = 0;
2593 vtx.dst_sel_y = 1;
2594 vtx.dst_sel_z = 2;
2595 vtx.dst_sel_w = 3;
2596 vtx.src_gpr = temp_val;
2597 vtx.src_sel_x = 0;
2598
2599 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2600 if (r)
2601 return r;
2602 }
2603 return 0;
2604 }
2605
2606 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2607 {
2608 int i, j, r;
2609 int temp_reg;
2610
2611 /* fetch tcs input values into input_vals */
2612 ctx->tess_input_info = r600_get_temp(ctx);
2613 ctx->tess_output_info = 0;
2614 r = r600_fetch_tess_io_info(ctx);
2615 if (r)
2616 return r;
2617
2618 temp_reg = r600_get_temp(ctx);
2619 /* dst reg contains LDS address stride * idx */
2620 /* MUL vertexID, vertex_dw_stride */
2621 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2622 temp_reg, 0,
2623 ctx->tess_input_info, 1,
2624 0, 1); /* rel id in r0.y? */
2625 if (r)
2626 return r;
2627
2628 for (i = 0; i < ctx->shader->noutput; i++) {
2629 struct r600_bytecode_alu alu;
2630 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2631
2632 if (param) {
2633 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2634 temp_reg, 1,
2635 temp_reg, 0,
2636 V_SQ_ALU_SRC_LITERAL, param * 16);
2637 if (r)
2638 return r;
2639 }
2640
2641 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2642 temp_reg, 2,
2643 temp_reg, param ? 1 : 0,
2644 V_SQ_ALU_SRC_LITERAL, 8);
2645 if (r)
2646 return r;
2647
2648
2649 for (j = 0; j < 2; j++) {
2650 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2651 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2652 alu.op = LDS_OP3_LDS_WRITE_REL;
2653 alu.src[0].sel = temp_reg;
2654 alu.src[0].chan = chan;
2655 alu.src[1].sel = ctx->shader->output[i].gpr;
2656 alu.src[1].chan = j * 2;
2657 alu.src[2].sel = ctx->shader->output[i].gpr;
2658 alu.src[2].chan = (j * 2) + 1;
2659 alu.last = 1;
2660 alu.dst.chan = 0;
2661 alu.lds_idx = 1;
2662 alu.is_lds_idx_op = true;
2663 r = r600_bytecode_add_alu(ctx->bc, &alu);
2664 if (r)
2665 return r;
2666 }
2667 }
2668 return 0;
2669 }
2670
2671 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2672 {
2673 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2674 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2675 int i, r, lasti;
2676 int temp_reg = r600_get_temp(ctx);
2677 struct r600_bytecode_alu alu;
2678 unsigned write_mask = dst->Register.WriteMask;
2679
2680 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2681 return 0;
2682
2683 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2684 if (r)
2685 return r;
2686
2687 /* the base address is now in temp.x */
2688 r = r600_get_byte_address(ctx, temp_reg,
2689 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2690 if (r)
2691 return r;
2692
2693 /* LDS write */
2694 lasti = tgsi_last_instruction(write_mask);
2695 for (i = 1; i <= lasti; i++) {
2696
2697 if (!(write_mask & (1 << i)))
2698 continue;
2699 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2700 temp_reg, i,
2701 temp_reg, 0,
2702 V_SQ_ALU_SRC_LITERAL, 4 * i);
2703 if (r)
2704 return r;
2705 }
2706
2707 for (i = 0; i <= lasti; i++) {
2708 if (!(write_mask & (1 << i)))
2709 continue;
2710
2711 if ((i == 0 && ((write_mask & 3) == 3)) ||
2712 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2713 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2714 alu.op = LDS_OP3_LDS_WRITE_REL;
2715 alu.src[0].sel = temp_reg;
2716 alu.src[0].chan = i;
2717
2718 alu.src[1].sel = dst->Register.Index;
2719 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2720 alu.src[1].chan = i;
2721
2722 alu.src[2].sel = dst->Register.Index;
2723 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2724 alu.src[2].chan = i + 1;
2725 alu.lds_idx = 1;
2726 alu.dst.chan = 0;
2727 alu.last = 1;
2728 alu.is_lds_idx_op = true;
2729 r = r600_bytecode_add_alu(ctx->bc, &alu);
2730 if (r)
2731 return r;
2732 i += 1;
2733 continue;
2734 }
2735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2736 alu.op = LDS_OP2_LDS_WRITE;
2737 alu.src[0].sel = temp_reg;
2738 alu.src[0].chan = i;
2739
2740 alu.src[1].sel = dst->Register.Index;
2741 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2742 alu.src[1].chan = i;
2743
2744 alu.src[2].sel = V_SQ_ALU_SRC_0;
2745 alu.dst.chan = 0;
2746 alu.last = 1;
2747 alu.is_lds_idx_op = true;
2748 r = r600_bytecode_add_alu(ctx->bc, &alu);
2749 if (r)
2750 return r;
2751 }
2752 return 0;
2753 }
2754
2755 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2756 int output_idx)
2757 {
2758 int param;
2759 unsigned temp_reg = r600_get_temp(ctx);
2760 unsigned name = ctx->shader->output[output_idx].name;
2761 int dreg = ctx->shader->output[output_idx].gpr;
2762 int r;
2763
2764 param = r600_get_lds_unique_index(name, 0);
2765 r = get_lds_offset0(ctx, 1, temp_reg, true);
2766 if (r)
2767 return r;
2768
2769 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2770 temp_reg, 0,
2771 temp_reg, 0,
2772 V_SQ_ALU_SRC_LITERAL, param * 16);
2773 if (r)
2774 return r;
2775
2776 do_lds_fetch_values(ctx, temp_reg, dreg);
2777 return 0;
2778 }
2779
2780 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2781 {
2782 unsigned i;
2783 int stride, outer_comps, inner_comps;
2784 int tessinner_idx = -1, tessouter_idx = -1;
2785 int r;
2786 int temp_reg = r600_get_temp(ctx);
2787 int treg[3] = {-1, -1, -1};
2788 struct r600_bytecode_alu alu;
2789 struct r600_bytecode_cf *cf_jump, *cf_pop;
2790
2791 /* only execute factor emission for invocation 0 */
2792 /* PRED_SETE_INT __, R0.x, 0 */
2793 memset(&alu, 0, sizeof(alu));
2794 alu.op = ALU_OP2_PRED_SETE_INT;
2795 alu.src[0].chan = 2;
2796 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2797 alu.execute_mask = 1;
2798 alu.update_pred = 1;
2799 alu.last = 1;
2800 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2801
2802 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2803 cf_jump = ctx->bc->cf_last;
2804
2805 treg[0] = r600_get_temp(ctx);
2806 switch (ctx->shader->tcs_prim_mode) {
2807 case PIPE_PRIM_LINES:
2808 stride = 8; /* 2 dwords, 1 vec2 store */
2809 outer_comps = 2;
2810 inner_comps = 0;
2811 break;
2812 case PIPE_PRIM_TRIANGLES:
2813 stride = 16; /* 4 dwords, 1 vec4 store */
2814 outer_comps = 3;
2815 inner_comps = 1;
2816 treg[1] = r600_get_temp(ctx);
2817 break;
2818 case PIPE_PRIM_QUADS:
2819 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2820 outer_comps = 4;
2821 inner_comps = 2;
2822 treg[1] = r600_get_temp(ctx);
2823 treg[2] = r600_get_temp(ctx);
2824 break;
2825 default:
2826 assert(0);
2827 return -1;
2828 }
2829
2830 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2831 /* TF_WRITE takes index in R.x, value in R.y */
2832 for (i = 0; i < ctx->shader->noutput; i++) {
2833 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2834 tessinner_idx = i;
2835 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2836 tessouter_idx = i;
2837 }
2838
2839 if (tessouter_idx == -1)
2840 return -1;
2841
2842 if (tessinner_idx == -1 && inner_comps)
2843 return -1;
2844
2845 if (tessouter_idx != -1) {
2846 r = r600_tess_factor_read(ctx, tessouter_idx);
2847 if (r)
2848 return r;
2849 }
2850
2851 if (tessinner_idx != -1) {
2852 r = r600_tess_factor_read(ctx, tessinner_idx);
2853 if (r)
2854 return r;
2855 }
2856
2857 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2858 /* r.x = relpatchid(r0.y) * tf_stride */
2859
2860 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2861 /* add incoming r0.w to it: t.x = t.x + r0.w */
2862 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2863 temp_reg, 0,
2864 0, 1,
2865 V_SQ_ALU_SRC_LITERAL, stride,
2866 0, 3);
2867 if (r)
2868 return r;
2869
2870 for (i = 0; i < outer_comps + inner_comps; i++) {
2871 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2872 int out_comp = i >= outer_comps ? i - outer_comps : i;
2873
2874 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2875 treg[i / 2], (2 * (i % 2)),
2876 temp_reg, 0,
2877 V_SQ_ALU_SRC_LITERAL, 4 * i);
2878 if (r)
2879 return r;
2880 r = single_alu_op2(ctx, ALU_OP1_MOV,
2881 treg[i / 2], 1 + (2 * (i%2)),
2882 ctx->shader->output[out_idx].gpr, out_comp,
2883 0, 0);
2884 if (r)
2885 return r;
2886 }
2887 for (i = 0; i < outer_comps + inner_comps; i++) {
2888 struct r600_bytecode_gds gds;
2889
2890 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2891 gds.src_gpr = treg[i / 2];
2892 gds.src_sel_x = 2 * (i % 2);
2893 gds.src_sel_y = 1 + (2 * (i % 2));
2894 gds.src_sel_z = 4;
2895 gds.dst_sel_x = 7;
2896 gds.dst_sel_y = 7;
2897 gds.dst_sel_z = 7;
2898 gds.dst_sel_w = 7;
2899 gds.op = FETCH_OP_TF_WRITE;
2900 r = r600_bytecode_add_gds(ctx->bc, &gds);
2901 if (r)
2902 return r;
2903 }
2904
2905 // Patch up jump label
2906 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2907 cf_pop = ctx->bc->cf_last;
2908
2909 cf_jump->cf_addr = cf_pop->id + 2;
2910 cf_jump->pop_count = 1;
2911 cf_pop->cf_addr = cf_pop->id + 2;
2912 cf_pop->pop_count = 1;
2913
2914 return 0;
2915 }
2916
2917 static int r600_shader_from_tgsi(struct r600_context *rctx,
2918 struct r600_pipe_shader *pipeshader,
2919 union r600_shader_key key)
2920 {
2921 struct r600_screen *rscreen = rctx->screen;
2922 struct r600_shader *shader = &pipeshader->shader;
2923 struct tgsi_token *tokens = pipeshader->selector->tokens;
2924 struct pipe_stream_output_info so = pipeshader->selector->so;
2925 struct tgsi_full_immediate *immediate;
2926 struct r600_shader_ctx ctx;
2927 struct r600_bytecode_output output[32];
2928 unsigned output_done, noutput;
2929 unsigned opcode;
2930 int i, j, k, r = 0;
2931 int next_param_base = 0, next_clip_base;
2932 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2933 bool indirect_gprs;
2934 bool ring_outputs = false;
2935 bool lds_outputs = false;
2936 bool lds_inputs = false;
2937 bool pos_emitted = false;
2938
2939 ctx.bc = &shader->bc;
2940 ctx.shader = shader;
2941 ctx.native_integers = true;
2942
2943 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2944 rscreen->has_compressed_msaa_texturing);
2945 ctx.tokens = tokens;
2946 tgsi_scan_shader(tokens, &ctx.info);
2947 shader->indirect_files = ctx.info.indirect_files;
2948
2949 shader->uses_doubles = ctx.info.uses_doubles;
2950
2951 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2952 tgsi_parse_init(&ctx.parse, tokens);
2953 ctx.type = ctx.info.processor;
2954 shader->processor_type = ctx.type;
2955 ctx.bc->type = shader->processor_type;
2956
2957 switch (ctx.type) {
2958 case PIPE_SHADER_VERTEX:
2959 shader->vs_as_gs_a = key.vs.as_gs_a;
2960 shader->vs_as_es = key.vs.as_es;
2961 shader->vs_as_ls = key.vs.as_ls;
2962 if (shader->vs_as_es)
2963 ring_outputs = true;
2964 if (shader->vs_as_ls)
2965 lds_outputs = true;
2966 break;
2967 case PIPE_SHADER_GEOMETRY:
2968 ring_outputs = true;
2969 break;
2970 case PIPE_SHADER_TESS_CTRL:
2971 shader->tcs_prim_mode = key.tcs.prim_mode;
2972 lds_outputs = true;
2973 lds_inputs = true;
2974 break;
2975 case PIPE_SHADER_TESS_EVAL:
2976 shader->tes_as_es = key.tes.as_es;
2977 lds_inputs = true;
2978 if (shader->tes_as_es)
2979 ring_outputs = true;
2980 break;
2981 case PIPE_SHADER_FRAGMENT:
2982 shader->two_side = key.ps.color_two_side;
2983 break;
2984 default:
2985 break;
2986 }
2987
2988 if (shader->vs_as_es || shader->tes_as_es) {
2989 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
2990 } else {
2991 ctx.gs_for_vs = NULL;
2992 }
2993
2994 ctx.next_ring_offset = 0;
2995 ctx.gs_out_ring_offset = 0;
2996 ctx.gs_next_vertex = 0;
2997 ctx.gs_stream_output_info = &so;
2998
2999 ctx.face_gpr = -1;
3000 ctx.fixed_pt_position_gpr = -1;
3001 ctx.fragcoord_input = -1;
3002 ctx.colors_used = 0;
3003 ctx.clip_vertex_write = 0;
3004
3005 shader->nr_ps_color_exports = 0;
3006 shader->nr_ps_max_color_exports = 0;
3007
3008
3009 /* register allocations */
3010 /* Values [0,127] correspond to GPR[0..127].
3011 * Values [128,159] correspond to constant buffer bank 0
3012 * Values [160,191] correspond to constant buffer bank 1
3013 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3014 * Values [256,287] correspond to constant buffer bank 2 (EG)
3015 * Values [288,319] correspond to constant buffer bank 3 (EG)
3016 * Other special values are shown in the list below.
3017 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3018 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3019 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3020 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3021 * 248 SQ_ALU_SRC_0: special constant 0.0.
3022 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3023 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3024 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3025 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3026 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3027 * 254 SQ_ALU_SRC_PV: previous vector result.
3028 * 255 SQ_ALU_SRC_PS: previous scalar result.
3029 */
3030 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3031 ctx.file_offset[i] = 0;
3032 }
3033
3034 if (ctx.type == PIPE_SHADER_VERTEX) {
3035 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3036 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3037 }
3038 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3039 if (ctx.bc->chip_class >= EVERGREEN)
3040 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3041 else
3042 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3043 }
3044 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3045 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3046 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3047 }
3048 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3049 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3050 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3051 bool add_tesscoord = false, add_tess_inout = false;
3052 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3053 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3054 /* if we have tesscoord save one reg */
3055 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3056 add_tesscoord = true;
3057 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3058 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3059 add_tess_inout = true;
3060 }
3061 if (add_tesscoord || add_tess_inout)
3062 ctx.file_offset[TGSI_FILE_INPUT]++;
3063 if (add_tess_inout)
3064 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3065 }
3066
3067 ctx.file_offset[TGSI_FILE_OUTPUT] =
3068 ctx.file_offset[TGSI_FILE_INPUT] +
3069 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3070 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3071 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3072
3073 /* Outside the GPR range. This will be translated to one of the
3074 * kcache banks later. */
3075 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3076
3077 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3078 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3079 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3080 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3081 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3082
3083 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3084 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3085 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3086 ctx.temp_reg = ctx.bc->ar_reg + 5;
3087 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3088 ctx.tess_input_info = 0;
3089 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3090 ctx.temp_reg = ctx.bc->ar_reg + 4;
3091 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3092 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3093 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3094 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3095 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3096 ctx.temp_reg = ctx.bc->ar_reg + 7;
3097 } else {
3098 ctx.temp_reg = ctx.bc->ar_reg + 3;
3099 }
3100
3101 shader->max_arrays = 0;
3102 shader->num_arrays = 0;
3103 if (indirect_gprs) {
3104
3105 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3106 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3107 ctx.file_offset[TGSI_FILE_OUTPUT] -
3108 ctx.file_offset[TGSI_FILE_INPUT],
3109 0x0F);
3110 }
3111 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3112 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3113 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3114 ctx.file_offset[TGSI_FILE_OUTPUT],
3115 0x0F);
3116 }
3117 }
3118
3119 ctx.nliterals = 0;
3120 ctx.literals = NULL;
3121
3122 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3123 ctx.info.colors_written == 1;
3124 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3125 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3126
3127 if (shader->vs_as_gs_a)
3128 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3129
3130 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3131 r600_fetch_tess_io_info(&ctx);
3132
3133 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3134 tgsi_parse_token(&ctx.parse);
3135 switch (ctx.parse.FullToken.Token.Type) {
3136 case TGSI_TOKEN_TYPE_IMMEDIATE:
3137 immediate = &ctx.parse.FullToken.FullImmediate;
3138 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3139 if(ctx.literals == NULL) {
3140 r = -ENOMEM;
3141 goto out_err;
3142 }
3143 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3144 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3145 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3146 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3147 ctx.nliterals++;
3148 break;
3149 case TGSI_TOKEN_TYPE_DECLARATION:
3150 r = tgsi_declaration(&ctx);
3151 if (r)
3152 goto out_err;
3153 break;
3154 case TGSI_TOKEN_TYPE_INSTRUCTION:
3155 case TGSI_TOKEN_TYPE_PROPERTY:
3156 break;
3157 default:
3158 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3159 r = -EINVAL;
3160 goto out_err;
3161 }
3162 }
3163
3164 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3165 shader->ring_item_sizes[1] = 0;
3166 shader->ring_item_sizes[2] = 0;
3167 shader->ring_item_sizes[3] = 0;
3168
3169 /* Process two side if needed */
3170 if (shader->two_side && ctx.colors_used) {
3171 int i, count = ctx.shader->ninput;
3172 unsigned next_lds_loc = ctx.shader->nlds;
3173
3174 /* additional inputs will be allocated right after the existing inputs,
3175 * we won't need them after the color selection, so we don't need to
3176 * reserve these gprs for the rest of the shader code and to adjust
3177 * output offsets etc. */
3178 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3179 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3180
3181 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3182 if (ctx.face_gpr == -1) {
3183 i = ctx.shader->ninput++;
3184 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3185 ctx.shader->input[i].spi_sid = 0;
3186 ctx.shader->input[i].gpr = gpr++;
3187 ctx.face_gpr = ctx.shader->input[i].gpr;
3188 }
3189
3190 for (i = 0; i < count; i++) {
3191 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3192 int ni = ctx.shader->ninput++;
3193 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3194 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3195 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3196 ctx.shader->input[ni].gpr = gpr++;
3197 // TGSI to LLVM needs to know the lds position of inputs.
3198 // Non LLVM path computes it later (in process_twoside_color)
3199 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3200 ctx.shader->input[i].back_color_input = ni;
3201 if (ctx.bc->chip_class >= EVERGREEN) {
3202 if ((r = evergreen_interp_input(&ctx, ni)))
3203 return r;
3204 }
3205 }
3206 }
3207 }
3208
3209 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3210 shader->nr_ps_max_color_exports = 8;
3211
3212 if (ctx.fragcoord_input >= 0) {
3213 if (ctx.bc->chip_class == CAYMAN) {
3214 for (j = 0 ; j < 4; j++) {
3215 struct r600_bytecode_alu alu;
3216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3217 alu.op = ALU_OP1_RECIP_IEEE;
3218 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3219 alu.src[0].chan = 3;
3220
3221 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3222 alu.dst.chan = j;
3223 alu.dst.write = (j == 3);
3224 alu.last = 1;
3225 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3226 return r;
3227 }
3228 } else {
3229 struct r600_bytecode_alu alu;
3230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3231 alu.op = ALU_OP1_RECIP_IEEE;
3232 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3233 alu.src[0].chan = 3;
3234
3235 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3236 alu.dst.chan = 3;
3237 alu.dst.write = 1;
3238 alu.last = 1;
3239 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3240 return r;
3241 }
3242 }
3243
3244 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3245 struct r600_bytecode_alu alu;
3246 int r;
3247
3248 /* GS thread with no output workaround - emit a cut at start of GS */
3249 if (ctx.bc->chip_class == R600)
3250 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3251
3252 for (j = 0; j < 4; j++) {
3253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3254 alu.op = ALU_OP1_MOV;
3255 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3256 alu.src[0].value = 0;
3257 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3258 alu.dst.write = 1;
3259 alu.last = 1;
3260 r = r600_bytecode_add_alu(ctx.bc, &alu);
3261 if (r)
3262 return r;
3263 }
3264 }
3265
3266 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3267 r600_fetch_tess_io_info(&ctx);
3268
3269 if (shader->two_side && ctx.colors_used) {
3270 if ((r = process_twoside_color_inputs(&ctx)))
3271 return r;
3272 }
3273
3274 tgsi_parse_init(&ctx.parse, tokens);
3275 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3276 tgsi_parse_token(&ctx.parse);
3277 switch (ctx.parse.FullToken.Token.Type) {
3278 case TGSI_TOKEN_TYPE_INSTRUCTION:
3279 r = tgsi_is_supported(&ctx);
3280 if (r)
3281 goto out_err;
3282 ctx.max_driver_temp_used = 0;
3283 /* reserve first tmp for everyone */
3284 r600_get_temp(&ctx);
3285
3286 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3287 if ((r = tgsi_split_constant(&ctx)))
3288 goto out_err;
3289 if ((r = tgsi_split_literal_constant(&ctx)))
3290 goto out_err;
3291 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3292 if ((r = tgsi_split_gs_inputs(&ctx)))
3293 goto out_err;
3294 } else if (lds_inputs) {
3295 if ((r = tgsi_split_lds_inputs(&ctx)))
3296 goto out_err;
3297 }
3298 if (ctx.bc->chip_class == CAYMAN)
3299 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3300 else if (ctx.bc->chip_class >= EVERGREEN)
3301 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3302 else
3303 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3304 r = ctx.inst_info->process(&ctx);
3305 if (r)
3306 goto out_err;
3307
3308 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3309 r = r600_store_tcs_output(&ctx);
3310 if (r)
3311 goto out_err;
3312 }
3313 break;
3314 default:
3315 break;
3316 }
3317 }
3318
3319 /* Reset the temporary register counter. */
3320 ctx.max_driver_temp_used = 0;
3321
3322 noutput = shader->noutput;
3323
3324 if (!ring_outputs && ctx.clip_vertex_write) {
3325 unsigned clipdist_temp[2];
3326
3327 clipdist_temp[0] = r600_get_temp(&ctx);
3328 clipdist_temp[1] = r600_get_temp(&ctx);
3329
3330 /* need to convert a clipvertex write into clipdistance writes and not export
3331 the clip vertex anymore */
3332
3333 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3334 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3335 shader->output[noutput].gpr = clipdist_temp[0];
3336 noutput++;
3337 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3338 shader->output[noutput].gpr = clipdist_temp[1];
3339 noutput++;
3340
3341 /* reset spi_sid for clipvertex output to avoid confusing spi */
3342 shader->output[ctx.cv_output].spi_sid = 0;
3343
3344 shader->clip_dist_write = 0xFF;
3345
3346 for (i = 0; i < 8; i++) {
3347 int oreg = i >> 2;
3348 int ochan = i & 3;
3349
3350 for (j = 0; j < 4; j++) {
3351 struct r600_bytecode_alu alu;
3352 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3353 alu.op = ALU_OP2_DOT4;
3354 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3355 alu.src[0].chan = j;
3356
3357 alu.src[1].sel = 512 + i;
3358 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3359 alu.src[1].chan = j;
3360
3361 alu.dst.sel = clipdist_temp[oreg];
3362 alu.dst.chan = j;
3363 alu.dst.write = (j == ochan);
3364 if (j == 3)
3365 alu.last = 1;
3366 r = r600_bytecode_add_alu(ctx.bc, &alu);
3367 if (r)
3368 return r;
3369 }
3370 }
3371 }
3372
3373 /* Add stream outputs. */
3374 if (so.num_outputs) {
3375 bool emit = false;
3376 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3377 emit = true;
3378 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3379 emit = true;
3380 if (emit)
3381 emit_streamout(&ctx, &so, -1, NULL);
3382 }
3383 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3384 convert_edgeflag_to_int(&ctx);
3385
3386 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3387 r600_emit_tess_factor(&ctx);
3388
3389 if (lds_outputs) {
3390 if (ctx.type == PIPE_SHADER_VERTEX) {
3391 if (ctx.shader->noutput)
3392 emit_lds_vs_writes(&ctx);
3393 }
3394 } else if (ring_outputs) {
3395 if (shader->vs_as_es || shader->tes_as_es) {
3396 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3397 ctx.gs_export_gpr_tregs[1] = -1;
3398 ctx.gs_export_gpr_tregs[2] = -1;
3399 ctx.gs_export_gpr_tregs[3] = -1;
3400
3401 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3402 }
3403 } else {
3404 /* Export output */
3405 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3406
3407 for (i = 0, j = 0; i < noutput; i++, j++) {
3408 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3409 output[j].gpr = shader->output[i].gpr;
3410 output[j].elem_size = 3;
3411 output[j].swizzle_x = 0;
3412 output[j].swizzle_y = 1;
3413 output[j].swizzle_z = 2;
3414 output[j].swizzle_w = 3;
3415 output[j].burst_count = 1;
3416 output[j].type = -1;
3417 output[j].op = CF_OP_EXPORT;
3418 switch (ctx.type) {
3419 case PIPE_SHADER_VERTEX:
3420 case PIPE_SHADER_TESS_EVAL:
3421 switch (shader->output[i].name) {
3422 case TGSI_SEMANTIC_POSITION:
3423 output[j].array_base = 60;
3424 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3425 pos_emitted = true;
3426 break;
3427
3428 case TGSI_SEMANTIC_PSIZE:
3429 output[j].array_base = 61;
3430 output[j].swizzle_y = 7;
3431 output[j].swizzle_z = 7;
3432 output[j].swizzle_w = 7;
3433 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3434 pos_emitted = true;
3435 break;
3436 case TGSI_SEMANTIC_EDGEFLAG:
3437 output[j].array_base = 61;
3438 output[j].swizzle_x = 7;
3439 output[j].swizzle_y = 0;
3440 output[j].swizzle_z = 7;
3441 output[j].swizzle_w = 7;
3442 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3443 pos_emitted = true;
3444 break;
3445 case TGSI_SEMANTIC_LAYER:
3446 /* spi_sid is 0 for outputs that are
3447 * not consumed by PS */
3448 if (shader->output[i].spi_sid) {
3449 output[j].array_base = next_param_base++;
3450 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3451 j++;
3452 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3453 }
3454 output[j].array_base = 61;
3455 output[j].swizzle_x = 7;
3456 output[j].swizzle_y = 7;
3457 output[j].swizzle_z = 0;
3458 output[j].swizzle_w = 7;
3459 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3460 pos_emitted = true;
3461 break;
3462 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3463 /* spi_sid is 0 for outputs that are
3464 * not consumed by PS */
3465 if (shader->output[i].spi_sid) {
3466 output[j].array_base = next_param_base++;
3467 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3468 j++;
3469 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3470 }
3471 output[j].array_base = 61;
3472 output[j].swizzle_x = 7;
3473 output[j].swizzle_y = 7;
3474 output[j].swizzle_z = 7;
3475 output[j].swizzle_w = 0;
3476 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3477 pos_emitted = true;
3478 break;
3479 case TGSI_SEMANTIC_CLIPVERTEX:
3480 j--;
3481 break;
3482 case TGSI_SEMANTIC_CLIPDIST:
3483 output[j].array_base = next_clip_base++;
3484 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3485 pos_emitted = true;
3486 /* spi_sid is 0 for clipdistance outputs that were generated
3487 * for clipvertex - we don't need to pass them to PS */
3488 if (shader->output[i].spi_sid) {
3489 j++;
3490 /* duplicate it as PARAM to pass to the pixel shader */
3491 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3492 output[j].array_base = next_param_base++;
3493 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3494 }
3495 break;
3496 case TGSI_SEMANTIC_FOG:
3497 output[j].swizzle_y = 4; /* 0 */
3498 output[j].swizzle_z = 4; /* 0 */
3499 output[j].swizzle_w = 5; /* 1 */
3500 break;
3501 case TGSI_SEMANTIC_PRIMID:
3502 output[j].swizzle_x = 2;
3503 output[j].swizzle_y = 4; /* 0 */
3504 output[j].swizzle_z = 4; /* 0 */
3505 output[j].swizzle_w = 4; /* 0 */
3506 break;
3507 }
3508
3509 break;
3510 case PIPE_SHADER_FRAGMENT:
3511 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3512 /* never export more colors than the number of CBs */
3513 if (shader->output[i].sid >= max_color_exports) {
3514 /* skip export */
3515 j--;
3516 continue;
3517 }
3518 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3519 output[j].array_base = shader->output[i].sid;
3520 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3521 shader->nr_ps_color_exports++;
3522 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3523 for (k = 1; k < max_color_exports; k++) {
3524 j++;
3525 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3526 output[j].gpr = shader->output[i].gpr;
3527 output[j].elem_size = 3;
3528 output[j].swizzle_x = 0;
3529 output[j].swizzle_y = 1;
3530 output[j].swizzle_z = 2;
3531 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3532 output[j].burst_count = 1;
3533 output[j].array_base = k;
3534 output[j].op = CF_OP_EXPORT;
3535 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3536 shader->nr_ps_color_exports++;
3537 }
3538 }
3539 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3540 output[j].array_base = 61;
3541 output[j].swizzle_x = 2;
3542 output[j].swizzle_y = 7;
3543 output[j].swizzle_z = output[j].swizzle_w = 7;
3544 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3545 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3546 output[j].array_base = 61;
3547 output[j].swizzle_x = 7;
3548 output[j].swizzle_y = 1;
3549 output[j].swizzle_z = output[j].swizzle_w = 7;
3550 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3551 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3552 output[j].array_base = 61;
3553 output[j].swizzle_x = 7;
3554 output[j].swizzle_y = 7;
3555 output[j].swizzle_z = 0;
3556 output[j].swizzle_w = 7;
3557 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3558 } else {
3559 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3560 r = -EINVAL;
3561 goto out_err;
3562 }
3563 break;
3564 case PIPE_SHADER_TESS_CTRL:
3565 break;
3566 default:
3567 R600_ERR("unsupported processor type %d\n", ctx.type);
3568 r = -EINVAL;
3569 goto out_err;
3570 }
3571
3572 if (output[j].type==-1) {
3573 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3574 output[j].array_base = next_param_base++;
3575 }
3576 }
3577
3578 /* add fake position export */
3579 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3580 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3581 output[j].gpr = 0;
3582 output[j].elem_size = 3;
3583 output[j].swizzle_x = 7;
3584 output[j].swizzle_y = 7;
3585 output[j].swizzle_z = 7;
3586 output[j].swizzle_w = 7;
3587 output[j].burst_count = 1;
3588 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3589 output[j].array_base = 60;
3590 output[j].op = CF_OP_EXPORT;
3591 j++;
3592 }
3593
3594 /* add fake param output for vertex shader if no param is exported */
3595 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3596 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3597 output[j].gpr = 0;
3598 output[j].elem_size = 3;
3599 output[j].swizzle_x = 7;
3600 output[j].swizzle_y = 7;
3601 output[j].swizzle_z = 7;
3602 output[j].swizzle_w = 7;
3603 output[j].burst_count = 1;
3604 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3605 output[j].array_base = 0;
3606 output[j].op = CF_OP_EXPORT;
3607 j++;
3608 }
3609
3610 /* add fake pixel export */
3611 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3612 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3613 output[j].gpr = 0;
3614 output[j].elem_size = 3;
3615 output[j].swizzle_x = 7;
3616 output[j].swizzle_y = 7;
3617 output[j].swizzle_z = 7;
3618 output[j].swizzle_w = 7;
3619 output[j].burst_count = 1;
3620 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3621 output[j].array_base = 0;
3622 output[j].op = CF_OP_EXPORT;
3623 j++;
3624 shader->nr_ps_color_exports++;
3625 }
3626
3627 noutput = j;
3628
3629 /* set export done on last export of each type */
3630 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3631 if (!(output_done & (1 << output[i].type))) {
3632 output_done |= (1 << output[i].type);
3633 output[i].op = CF_OP_EXPORT_DONE;
3634 }
3635 }
3636 /* add output to bytecode */
3637 for (i = 0; i < noutput; i++) {
3638 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3639 if (r)
3640 goto out_err;
3641 }
3642 }
3643
3644 /* add program end */
3645 if (ctx.bc->chip_class == CAYMAN)
3646 cm_bytecode_add_cf_end(ctx.bc);
3647 else {
3648 const struct cf_op_info *last = NULL;
3649
3650 if (ctx.bc->cf_last)
3651 last = r600_isa_cf(ctx.bc->cf_last->op);
3652
3653 /* alu clause instructions don't have EOP bit, so add NOP */
3654 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3655 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3656
3657 ctx.bc->cf_last->end_of_program = 1;
3658 }
3659
3660 /* check GPR limit - we have 124 = 128 - 4
3661 * (4 are reserved as alu clause temporary registers) */
3662 if (ctx.bc->ngpr > 124) {
3663 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3664 r = -ENOMEM;
3665 goto out_err;
3666 }
3667
3668 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3669 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3670 return r;
3671 }
3672
3673 free(ctx.literals);
3674 tgsi_parse_free(&ctx.parse);
3675 return 0;
3676 out_err:
3677 free(ctx.literals);
3678 tgsi_parse_free(&ctx.parse);
3679 return r;
3680 }
3681
3682 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3683 {
3684 const unsigned tgsi_opcode =
3685 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3686 R600_ERR("%s tgsi opcode unsupported\n",
3687 tgsi_get_opcode_name(tgsi_opcode));
3688 return -EINVAL;
3689 }
3690
3691 static int tgsi_end(struct r600_shader_ctx *ctx)
3692 {
3693 return 0;
3694 }
3695
3696 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3697 const struct r600_shader_src *shader_src,
3698 unsigned chan)
3699 {
3700 bc_src->sel = shader_src->sel;
3701 bc_src->chan = shader_src->swizzle[chan];
3702 bc_src->neg = shader_src->neg;
3703 bc_src->abs = shader_src->abs;
3704 bc_src->rel = shader_src->rel;
3705 bc_src->value = shader_src->value[bc_src->chan];
3706 bc_src->kc_bank = shader_src->kc_bank;
3707 bc_src->kc_rel = shader_src->kc_rel;
3708 }
3709
3710 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3711 {
3712 bc_src->abs = 1;
3713 bc_src->neg = 0;
3714 }
3715
3716 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3717 {
3718 bc_src->neg = !bc_src->neg;
3719 }
3720
3721 static void tgsi_dst(struct r600_shader_ctx *ctx,
3722 const struct tgsi_full_dst_register *tgsi_dst,
3723 unsigned swizzle,
3724 struct r600_bytecode_alu_dst *r600_dst)
3725 {
3726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3727
3728 r600_dst->sel = tgsi_dst->Register.Index;
3729 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3730 r600_dst->chan = swizzle;
3731 r600_dst->write = 1;
3732 if (inst->Instruction.Saturate) {
3733 r600_dst->clamp = 1;
3734 }
3735 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3736 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3737 return;
3738 }
3739 }
3740 if (tgsi_dst->Register.Indirect)
3741 r600_dst->rel = V_SQ_REL_RELATIVE;
3742
3743 }
3744
3745 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3746 {
3747 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3748 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3749 struct r600_bytecode_alu alu;
3750 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3751 int use_tmp = 0;
3752
3753 if (singledest) {
3754 switch (write_mask) {
3755 case 0x1:
3756 write_mask = 0x3;
3757 break;
3758 case 0x2:
3759 use_tmp = 1;
3760 write_mask = 0x3;
3761 break;
3762 case 0x4:
3763 write_mask = 0xc;
3764 break;
3765 case 0x8:
3766 write_mask = 0xc;
3767 use_tmp = 3;
3768 break;
3769 }
3770 }
3771
3772 lasti = tgsi_last_instruction(write_mask);
3773 for (i = 0; i <= lasti; i++) {
3774
3775 if (!(write_mask & (1 << i)))
3776 continue;
3777
3778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3779
3780 if (singledest) {
3781 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3782 if (use_tmp) {
3783 alu.dst.sel = ctx->temp_reg;
3784 alu.dst.chan = i;
3785 alu.dst.write = 1;
3786 }
3787 if (i == 1 || i == 3)
3788 alu.dst.write = 0;
3789 } else
3790 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3791
3792 alu.op = ctx->inst_info->op;
3793 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3794 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3795 } else if (!swap) {
3796 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3797 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3798 }
3799 } else {
3800 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3801 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3802 }
3803
3804 /* handle some special cases */
3805 if (i == 1 || i == 3) {
3806 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3807 case TGSI_OPCODE_SUB:
3808 r600_bytecode_src_toggle_neg(&alu.src[1]);
3809 break;
3810 case TGSI_OPCODE_DABS:
3811 r600_bytecode_src_set_abs(&alu.src[0]);
3812 break;
3813 default:
3814 break;
3815 }
3816 }
3817 if (i == lasti) {
3818 alu.last = 1;
3819 }
3820 r = r600_bytecode_add_alu(ctx->bc, &alu);
3821 if (r)
3822 return r;
3823 }
3824
3825 if (use_tmp) {
3826 write_mask = inst->Dst[0].Register.WriteMask;
3827
3828 /* move result from temp to dst */
3829 for (i = 0; i <= lasti; i++) {
3830 if (!(write_mask & (1 << i)))
3831 continue;
3832
3833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3834 alu.op = ALU_OP1_MOV;
3835 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3836 alu.src[0].sel = ctx->temp_reg;
3837 alu.src[0].chan = use_tmp - 1;
3838 alu.last = (i == lasti);
3839
3840 r = r600_bytecode_add_alu(ctx->bc, &alu);
3841 if (r)
3842 return r;
3843 }
3844 }
3845 return 0;
3846 }
3847
3848 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3849 {
3850 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3851 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3852 /* confirm writemasking */
3853 if ((write_mask & 0x3) != 0x3 &&
3854 (write_mask & 0xc) != 0xc) {
3855 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3856 return -1;
3857 }
3858 return tgsi_op2_64_params(ctx, false, false);
3859 }
3860
3861 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
3862 {
3863 return tgsi_op2_64_params(ctx, true, false);
3864 }
3865
3866 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
3867 {
3868 return tgsi_op2_64_params(ctx, true, true);
3869 }
3870
3871 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3872 {
3873 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3874 struct r600_bytecode_alu alu;
3875 int i, j, r;
3876 int lasti = 3;
3877 int tmp = r600_get_temp(ctx);
3878
3879 for (i = 0; i < lasti + 1; i++) {
3880
3881 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3882 alu.op = ctx->inst_info->op;
3883 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3884 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3885 }
3886
3887 if (inst->Dst[0].Register.WriteMask & (1 << i))
3888 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3889 else
3890 alu.dst.sel = tmp;
3891
3892 alu.dst.chan = i;
3893 alu.is_op3 = 1;
3894 if (i == lasti) {
3895 alu.last = 1;
3896 }
3897 r = r600_bytecode_add_alu(ctx->bc, &alu);
3898 if (r)
3899 return r;
3900 }
3901 return 0;
3902 }
3903
3904 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3905 {
3906 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3907 struct r600_bytecode_alu alu;
3908 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3909 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3910 /* use temp register if trans_only and more than one dst component */
3911 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3912
3913 for (i = 0; i <= lasti; i++) {
3914 if (!(write_mask & (1 << i)))
3915 continue;
3916
3917 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3918 if (use_tmp) {
3919 alu.dst.sel = ctx->temp_reg;
3920 alu.dst.chan = i;
3921 alu.dst.write = 1;
3922 } else
3923 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3924
3925 alu.op = ctx->inst_info->op;
3926 if (!swap) {
3927 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3928 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3929 }
3930 } else {
3931 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3932 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3933 }
3934 /* handle some special cases */
3935 switch (inst->Instruction.Opcode) {
3936 case TGSI_OPCODE_SUB:
3937 r600_bytecode_src_toggle_neg(&alu.src[1]);
3938 break;
3939 default:
3940 break;
3941 }
3942 if (i == lasti || trans_only) {
3943 alu.last = 1;
3944 }
3945 r = r600_bytecode_add_alu(ctx->bc, &alu);
3946 if (r)
3947 return r;
3948 }
3949
3950 if (use_tmp) {
3951 /* move result from temp to dst */
3952 for (i = 0; i <= lasti; i++) {
3953 if (!(write_mask & (1 << i)))
3954 continue;
3955
3956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3957 alu.op = ALU_OP1_MOV;
3958 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3959 alu.src[0].sel = ctx->temp_reg;
3960 alu.src[0].chan = i;
3961 alu.last = (i == lasti);
3962
3963 r = r600_bytecode_add_alu(ctx->bc, &alu);
3964 if (r)
3965 return r;
3966 }
3967 }
3968 return 0;
3969 }
3970
3971 static int tgsi_op2(struct r600_shader_ctx *ctx)
3972 {
3973 return tgsi_op2_s(ctx, 0, 0);
3974 }
3975
3976 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
3977 {
3978 return tgsi_op2_s(ctx, 1, 0);
3979 }
3980
3981 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
3982 {
3983 return tgsi_op2_s(ctx, 0, 1);
3984 }
3985
3986 static int tgsi_ineg(struct r600_shader_ctx *ctx)
3987 {
3988 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3989 struct r600_bytecode_alu alu;
3990 int i, r;
3991 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3992
3993 for (i = 0; i < lasti + 1; i++) {
3994
3995 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3996 continue;
3997 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3998 alu.op = ctx->inst_info->op;
3999
4000 alu.src[0].sel = V_SQ_ALU_SRC_0;
4001
4002 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4003
4004 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4005
4006 if (i == lasti) {
4007 alu.last = 1;
4008 }
4009 r = r600_bytecode_add_alu(ctx->bc, &alu);
4010 if (r)
4011 return r;
4012 }
4013 return 0;
4014
4015 }
4016
4017 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4018 {
4019 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4020 struct r600_bytecode_alu alu;
4021 int i, r;
4022 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4023
4024 for (i = 0; i < lasti + 1; i++) {
4025
4026 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4027 continue;
4028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4029 alu.op = ALU_OP1_MOV;
4030
4031 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4032
4033 if (i == 1 || i == 3)
4034 r600_bytecode_src_toggle_neg(&alu.src[0]);
4035 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4036
4037 if (i == lasti) {
4038 alu.last = 1;
4039 }
4040 r = r600_bytecode_add_alu(ctx->bc, &alu);
4041 if (r)
4042 return r;
4043 }
4044 return 0;
4045
4046 }
4047
4048 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4049 {
4050 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4051 struct r600_bytecode_alu alu;
4052 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4053 int i, j, r;
4054 int firsti = write_mask == 0xc ? 2 : 0;
4055
4056 for (i = 0; i <= 3; i++) {
4057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4058 alu.op = ctx->inst_info->op;
4059
4060 alu.dst.sel = ctx->temp_reg;
4061 alu.dst.chan = i;
4062 alu.dst.write = 1;
4063 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4064 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4065 }
4066
4067 if (i == 3)
4068 alu.last = 1;
4069
4070 r = r600_bytecode_add_alu(ctx->bc, &alu);
4071 if (r)
4072 return r;
4073 }
4074
4075 /* MOV first two channels to writemask dst0 */
4076 for (i = 0; i <= 1; i++) {
4077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4078 alu.op = ALU_OP1_MOV;
4079 alu.src[0].chan = i + 2;
4080 alu.src[0].sel = ctx->temp_reg;
4081
4082 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
4083 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
4084 alu.last = 1;
4085 r = r600_bytecode_add_alu(ctx->bc, &alu);
4086 if (r)
4087 return r;
4088 }
4089
4090 for (i = 0; i <= 3; i++) {
4091 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4092 /* MOV third channels to writemask dst1 */
4093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4094 alu.op = ALU_OP1_MOV;
4095 alu.src[0].chan = 1;
4096 alu.src[0].sel = ctx->temp_reg;
4097
4098 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4099 alu.last = 1;
4100 r = r600_bytecode_add_alu(ctx->bc, &alu);
4101 if (r)
4102 return r;
4103 break;
4104 }
4105 }
4106 return 0;
4107 }
4108
4109
4110 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4111 {
4112 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4113 struct r600_bytecode_alu alu;
4114 int i, r;
4115 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4116
4117 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4118 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4119
4120 for (i = 0; i <= (lasti+1)/2; i++) {
4121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4122 alu.op = ctx->inst_info->op;
4123
4124 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4125 alu.dst.sel = ctx->temp_reg;
4126 alu.dst.chan = i;
4127 alu.dst.write = 1;
4128 alu.last = 1;
4129
4130 r = r600_bytecode_add_alu(ctx->bc, &alu);
4131 if (r)
4132 return r;
4133 }
4134
4135 for (i = 0; i <= lasti; i++) {
4136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4137 alu.op = ALU_OP1_FLT32_TO_FLT64;
4138
4139 alu.src[0].chan = i/2;
4140 if (i%2 == 0)
4141 alu.src[0].sel = ctx->temp_reg;
4142 else {
4143 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4144 alu.src[0].value = 0x0;
4145 }
4146 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4147 alu.last = i == lasti;
4148
4149 r = r600_bytecode_add_alu(ctx->bc, &alu);
4150 if (r)
4151 return r;
4152 }
4153
4154 return 0;
4155 }
4156
4157 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4158 {
4159 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4160 struct r600_bytecode_alu alu;
4161 int i, r;
4162 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4163
4164 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4165 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4166
4167 for (i = 0; i <= lasti; i++) {
4168 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4169 alu.op = ALU_OP1_FLT64_TO_FLT32;
4170
4171 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4172 alu.dst.chan = i;
4173 alu.dst.sel = ctx->temp_reg;
4174 alu.dst.write = i%2 == 0;
4175 alu.last = i == lasti;
4176
4177 r = r600_bytecode_add_alu(ctx->bc, &alu);
4178 if (r)
4179 return r;
4180 }
4181
4182 for (i = 0; i <= (lasti+1)/2; i++) {
4183 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4184 alu.op = ctx->inst_info->op;
4185
4186 alu.src[0].chan = i*2;
4187 alu.src[0].sel = ctx->temp_reg;
4188 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4189 alu.last = 1;
4190
4191 r = r600_bytecode_add_alu(ctx->bc, &alu);
4192 if (r)
4193 return r;
4194 }
4195
4196 return 0;
4197 }
4198
4199 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4200 {
4201 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4202 int i, r;
4203 struct r600_bytecode_alu alu;
4204 int last_slot = 3;
4205 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4206 int t1 = ctx->temp_reg;
4207
4208 /* these have to write the result to X/Y by the looks of it */
4209 for (i = 0 ; i < last_slot; i++) {
4210 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4211 alu.op = ctx->inst_info->op;
4212
4213 /* should only be one src regs */
4214 assert (inst->Instruction.NumSrcRegs == 1);
4215
4216 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4217 r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
4218
4219 /* RSQ should take the absolute value of src */
4220 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4221 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT) {
4222 r600_bytecode_src_set_abs(&alu.src[1]);
4223 }
4224 alu.dst.sel = t1;
4225 alu.dst.chan = i;
4226 alu.dst.write = (i == 0 || i == 1);
4227
4228 if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
4229 alu.last = 1;
4230 r = r600_bytecode_add_alu(ctx->bc, &alu);
4231 if (r)
4232 return r;
4233 }
4234
4235 for (i = 0 ; i <= lasti; i++) {
4236 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4237 continue;
4238 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4239 alu.op = ALU_OP1_MOV;
4240 alu.src[0].sel = t1;
4241 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4242 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4243 alu.dst.write = 1;
4244 if (i == lasti)
4245 alu.last = 1;
4246 r = r600_bytecode_add_alu(ctx->bc, &alu);
4247 if (r)
4248 return r;
4249 }
4250 return 0;
4251 }
4252
4253 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4254 {
4255 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4256 int i, j, r;
4257 struct r600_bytecode_alu alu;
4258 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4259
4260 for (i = 0 ; i < last_slot; i++) {
4261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4262 alu.op = ctx->inst_info->op;
4263 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4264 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4265
4266 /* RSQ should take the absolute value of src */
4267 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4268 r600_bytecode_src_set_abs(&alu.src[j]);
4269 }
4270 }
4271 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4272 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4273
4274 if (i == last_slot - 1)
4275 alu.last = 1;
4276 r = r600_bytecode_add_alu(ctx->bc, &alu);
4277 if (r)
4278 return r;
4279 }
4280 return 0;
4281 }
4282
4283 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4284 {
4285 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4286 int i, j, k, r;
4287 struct r600_bytecode_alu alu;
4288 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4289 int t1 = ctx->temp_reg;
4290
4291 for (k = 0; k <= lasti; k++) {
4292 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4293 continue;
4294
4295 for (i = 0 ; i < 4; i++) {
4296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4297 alu.op = ctx->inst_info->op;
4298 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4299 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4300 }
4301 alu.dst.sel = t1;
4302 alu.dst.chan = i;
4303 alu.dst.write = (i == k);
4304 if (i == 3)
4305 alu.last = 1;
4306 r = r600_bytecode_add_alu(ctx->bc, &alu);
4307 if (r)
4308 return r;
4309 }
4310 }
4311
4312 for (i = 0 ; i <= lasti; i++) {
4313 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4314 continue;
4315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4316 alu.op = ALU_OP1_MOV;
4317 alu.src[0].sel = t1;
4318 alu.src[0].chan = i;
4319 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4320 alu.dst.write = 1;
4321 if (i == lasti)
4322 alu.last = 1;
4323 r = r600_bytecode_add_alu(ctx->bc, &alu);
4324 if (r)
4325 return r;
4326 }
4327
4328 return 0;
4329 }
4330
4331
4332 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4333 {
4334 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4335 int i, j, k, r;
4336 struct r600_bytecode_alu alu;
4337 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4338 int t1 = ctx->temp_reg;
4339
4340 for (k = 0; k < 2; k++) {
4341 if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2))))
4342 continue;
4343
4344 for (i = 0; i < 4; i++) {
4345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4346 alu.op = ctx->inst_info->op;
4347 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4348 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4349 }
4350 alu.dst.sel = t1;
4351 alu.dst.chan = i;
4352 alu.dst.write = 1;
4353 if (i == 3)
4354 alu.last = 1;
4355 r = r600_bytecode_add_alu(ctx->bc, &alu);
4356 if (r)
4357 return r;
4358 }
4359 }
4360
4361 for (i = 0; i <= lasti; i++) {
4362 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4363 continue;
4364 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4365 alu.op = ALU_OP1_MOV;
4366 alu.src[0].sel = t1;
4367 alu.src[0].chan = i;
4368 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4369 alu.dst.write = 1;
4370 if (i == lasti)
4371 alu.last = 1;
4372 r = r600_bytecode_add_alu(ctx->bc, &alu);
4373 if (r)
4374 return r;
4375 }
4376
4377 return 0;
4378 }
4379
4380 /*
4381 * r600 - trunc to -PI..PI range
4382 * r700 - normalize by dividing by 2PI
4383 * see fdo bug 27901
4384 */
4385 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4386 {
4387 int r;
4388 struct r600_bytecode_alu alu;
4389
4390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4391 alu.op = ALU_OP3_MULADD;
4392 alu.is_op3 = 1;
4393
4394 alu.dst.chan = 0;
4395 alu.dst.sel = ctx->temp_reg;
4396 alu.dst.write = 1;
4397
4398 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4399
4400 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4401 alu.src[1].chan = 0;
4402 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4403 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4404 alu.src[2].chan = 0;
4405 alu.last = 1;
4406 r = r600_bytecode_add_alu(ctx->bc, &alu);
4407 if (r)
4408 return r;
4409
4410 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4411 alu.op = ALU_OP1_FRACT;
4412
4413 alu.dst.chan = 0;
4414 alu.dst.sel = ctx->temp_reg;
4415 alu.dst.write = 1;
4416
4417 alu.src[0].sel = ctx->temp_reg;
4418 alu.src[0].chan = 0;
4419 alu.last = 1;
4420 r = r600_bytecode_add_alu(ctx->bc, &alu);
4421 if (r)
4422 return r;
4423
4424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4425 alu.op = ALU_OP3_MULADD;
4426 alu.is_op3 = 1;
4427
4428 alu.dst.chan = 0;
4429 alu.dst.sel = ctx->temp_reg;
4430 alu.dst.write = 1;
4431
4432 alu.src[0].sel = ctx->temp_reg;
4433 alu.src[0].chan = 0;
4434
4435 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4436 alu.src[1].chan = 0;
4437 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4438 alu.src[2].chan = 0;
4439
4440 if (ctx->bc->chip_class == R600) {
4441 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4442 alu.src[2].value = u_bitcast_f2u(-M_PI);
4443 } else {
4444 alu.src[1].sel = V_SQ_ALU_SRC_1;
4445 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4446 alu.src[2].neg = 1;
4447 }
4448
4449 alu.last = 1;
4450 r = r600_bytecode_add_alu(ctx->bc, &alu);
4451 if (r)
4452 return r;
4453 return 0;
4454 }
4455
4456 static int cayman_trig(struct r600_shader_ctx *ctx)
4457 {
4458 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4459 struct r600_bytecode_alu alu;
4460 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4461 int i, r;
4462
4463 r = tgsi_setup_trig(ctx);
4464 if (r)
4465 return r;
4466
4467
4468 for (i = 0; i < last_slot; i++) {
4469 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4470 alu.op = ctx->inst_info->op;
4471 alu.dst.chan = i;
4472
4473 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4474 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4475
4476 alu.src[0].sel = ctx->temp_reg;
4477 alu.src[0].chan = 0;
4478 if (i == last_slot - 1)
4479 alu.last = 1;
4480 r = r600_bytecode_add_alu(ctx->bc, &alu);
4481 if (r)
4482 return r;
4483 }
4484 return 0;
4485 }
4486
4487 static int tgsi_trig(struct r600_shader_ctx *ctx)
4488 {
4489 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4490 struct r600_bytecode_alu alu;
4491 int i, r;
4492 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4493
4494 r = tgsi_setup_trig(ctx);
4495 if (r)
4496 return r;
4497
4498 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4499 alu.op = ctx->inst_info->op;
4500 alu.dst.chan = 0;
4501 alu.dst.sel = ctx->temp_reg;
4502 alu.dst.write = 1;
4503
4504 alu.src[0].sel = ctx->temp_reg;
4505 alu.src[0].chan = 0;
4506 alu.last = 1;
4507 r = r600_bytecode_add_alu(ctx->bc, &alu);
4508 if (r)
4509 return r;
4510
4511 /* replicate result */
4512 for (i = 0; i < lasti + 1; i++) {
4513 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4514 continue;
4515
4516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4517 alu.op = ALU_OP1_MOV;
4518
4519 alu.src[0].sel = ctx->temp_reg;
4520 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4521 if (i == lasti)
4522 alu.last = 1;
4523 r = r600_bytecode_add_alu(ctx->bc, &alu);
4524 if (r)
4525 return r;
4526 }
4527 return 0;
4528 }
4529
4530 static int tgsi_scs(struct r600_shader_ctx *ctx)
4531 {
4532 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4533 struct r600_bytecode_alu alu;
4534 int i, r;
4535
4536 /* We'll only need the trig stuff if we are going to write to the
4537 * X or Y components of the destination vector.
4538 */
4539 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
4540 r = tgsi_setup_trig(ctx);
4541 if (r)
4542 return r;
4543 }
4544
4545 /* dst.x = COS */
4546 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4547 if (ctx->bc->chip_class == CAYMAN) {
4548 for (i = 0 ; i < 3; i++) {
4549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4550 alu.op = ALU_OP1_COS;
4551 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4552
4553 if (i == 0)
4554 alu.dst.write = 1;
4555 else
4556 alu.dst.write = 0;
4557 alu.src[0].sel = ctx->temp_reg;
4558 alu.src[0].chan = 0;
4559 if (i == 2)
4560 alu.last = 1;
4561 r = r600_bytecode_add_alu(ctx->bc, &alu);
4562 if (r)
4563 return r;
4564 }
4565 } else {
4566 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4567 alu.op = ALU_OP1_COS;
4568 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4569
4570 alu.src[0].sel = ctx->temp_reg;
4571 alu.src[0].chan = 0;
4572 alu.last = 1;
4573 r = r600_bytecode_add_alu(ctx->bc, &alu);
4574 if (r)
4575 return r;
4576 }
4577 }
4578
4579 /* dst.y = SIN */
4580 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4581 if (ctx->bc->chip_class == CAYMAN) {
4582 for (i = 0 ; i < 3; i++) {
4583 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4584 alu.op = ALU_OP1_SIN;
4585 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4586 if (i == 1)
4587 alu.dst.write = 1;
4588 else
4589 alu.dst.write = 0;
4590 alu.src[0].sel = ctx->temp_reg;
4591 alu.src[0].chan = 0;
4592 if (i == 2)
4593 alu.last = 1;
4594 r = r600_bytecode_add_alu(ctx->bc, &alu);
4595 if (r)
4596 return r;
4597 }
4598 } else {
4599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4600 alu.op = ALU_OP1_SIN;
4601 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4602
4603 alu.src[0].sel = ctx->temp_reg;
4604 alu.src[0].chan = 0;
4605 alu.last = 1;
4606 r = r600_bytecode_add_alu(ctx->bc, &alu);
4607 if (r)
4608 return r;
4609 }
4610 }
4611
4612 /* dst.z = 0.0; */
4613 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4615
4616 alu.op = ALU_OP1_MOV;
4617
4618 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4619
4620 alu.src[0].sel = V_SQ_ALU_SRC_0;
4621 alu.src[0].chan = 0;
4622
4623 alu.last = 1;
4624
4625 r = r600_bytecode_add_alu(ctx->bc, &alu);
4626 if (r)
4627 return r;
4628 }
4629
4630 /* dst.w = 1.0; */
4631 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4633
4634 alu.op = ALU_OP1_MOV;
4635
4636 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4637
4638 alu.src[0].sel = V_SQ_ALU_SRC_1;
4639 alu.src[0].chan = 0;
4640
4641 alu.last = 1;
4642
4643 r = r600_bytecode_add_alu(ctx->bc, &alu);
4644 if (r)
4645 return r;
4646 }
4647
4648 return 0;
4649 }
4650
4651 static int tgsi_kill(struct r600_shader_ctx *ctx)
4652 {
4653 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4654 struct r600_bytecode_alu alu;
4655 int i, r;
4656
4657 for (i = 0; i < 4; i++) {
4658 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4659 alu.op = ctx->inst_info->op;
4660
4661 alu.dst.chan = i;
4662
4663 alu.src[0].sel = V_SQ_ALU_SRC_0;
4664
4665 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4666 alu.src[1].sel = V_SQ_ALU_SRC_1;
4667 alu.src[1].neg = 1;
4668 } else {
4669 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4670 }
4671 if (i == 3) {
4672 alu.last = 1;
4673 }
4674 r = r600_bytecode_add_alu(ctx->bc, &alu);
4675 if (r)
4676 return r;
4677 }
4678
4679 /* kill must be last in ALU */
4680 ctx->bc->force_add_cf = 1;
4681 ctx->shader->uses_kill = TRUE;
4682 return 0;
4683 }
4684
4685 static int tgsi_lit(struct r600_shader_ctx *ctx)
4686 {
4687 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4688 struct r600_bytecode_alu alu;
4689 int r;
4690
4691 /* tmp.x = max(src.y, 0.0) */
4692 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4693 alu.op = ALU_OP2_MAX;
4694 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4695 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4696 alu.src[1].chan = 1;
4697
4698 alu.dst.sel = ctx->temp_reg;
4699 alu.dst.chan = 0;
4700 alu.dst.write = 1;
4701
4702 alu.last = 1;
4703 r = r600_bytecode_add_alu(ctx->bc, &alu);
4704 if (r)
4705 return r;
4706
4707 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4708 {
4709 int chan;
4710 int sel;
4711 unsigned i;
4712
4713 if (ctx->bc->chip_class == CAYMAN) {
4714 for (i = 0; i < 3; i++) {
4715 /* tmp.z = log(tmp.x) */
4716 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4717 alu.op = ALU_OP1_LOG_CLAMPED;
4718 alu.src[0].sel = ctx->temp_reg;
4719 alu.src[0].chan = 0;
4720 alu.dst.sel = ctx->temp_reg;
4721 alu.dst.chan = i;
4722 if (i == 2) {
4723 alu.dst.write = 1;
4724 alu.last = 1;
4725 } else
4726 alu.dst.write = 0;
4727
4728 r = r600_bytecode_add_alu(ctx->bc, &alu);
4729 if (r)
4730 return r;
4731 }
4732 } else {
4733 /* tmp.z = log(tmp.x) */
4734 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4735 alu.op = ALU_OP1_LOG_CLAMPED;
4736 alu.src[0].sel = ctx->temp_reg;
4737 alu.src[0].chan = 0;
4738 alu.dst.sel = ctx->temp_reg;
4739 alu.dst.chan = 2;
4740 alu.dst.write = 1;
4741 alu.last = 1;
4742 r = r600_bytecode_add_alu(ctx->bc, &alu);
4743 if (r)
4744 return r;
4745 }
4746
4747 chan = alu.dst.chan;
4748 sel = alu.dst.sel;
4749
4750 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4751 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4752 alu.op = ALU_OP3_MUL_LIT;
4753 alu.src[0].sel = sel;
4754 alu.src[0].chan = chan;
4755 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4756 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4757 alu.dst.sel = ctx->temp_reg;
4758 alu.dst.chan = 0;
4759 alu.dst.write = 1;
4760 alu.is_op3 = 1;
4761 alu.last = 1;
4762 r = r600_bytecode_add_alu(ctx->bc, &alu);
4763 if (r)
4764 return r;
4765
4766 if (ctx->bc->chip_class == CAYMAN) {
4767 for (i = 0; i < 3; i++) {
4768 /* dst.z = exp(tmp.x) */
4769 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4770 alu.op = ALU_OP1_EXP_IEEE;
4771 alu.src[0].sel = ctx->temp_reg;
4772 alu.src[0].chan = 0;
4773 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4774 if (i == 2) {
4775 alu.dst.write = 1;
4776 alu.last = 1;
4777 } else
4778 alu.dst.write = 0;
4779 r = r600_bytecode_add_alu(ctx->bc, &alu);
4780 if (r)
4781 return r;
4782 }
4783 } else {
4784 /* dst.z = exp(tmp.x) */
4785 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4786 alu.op = ALU_OP1_EXP_IEEE;
4787 alu.src[0].sel = ctx->temp_reg;
4788 alu.src[0].chan = 0;
4789 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4790 alu.last = 1;
4791 r = r600_bytecode_add_alu(ctx->bc, &alu);
4792 if (r)
4793 return r;
4794 }
4795 }
4796
4797 /* dst.x, <- 1.0 */
4798 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4799 alu.op = ALU_OP1_MOV;
4800 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4801 alu.src[0].chan = 0;
4802 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4803 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4804 r = r600_bytecode_add_alu(ctx->bc, &alu);
4805 if (r)
4806 return r;
4807
4808 /* dst.y = max(src.x, 0.0) */
4809 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4810 alu.op = ALU_OP2_MAX;
4811 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4812 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4813 alu.src[1].chan = 0;
4814 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4815 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4816 r = r600_bytecode_add_alu(ctx->bc, &alu);
4817 if (r)
4818 return r;
4819
4820 /* dst.w, <- 1.0 */
4821 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4822 alu.op = ALU_OP1_MOV;
4823 alu.src[0].sel = V_SQ_ALU_SRC_1;
4824 alu.src[0].chan = 0;
4825 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4826 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4827 alu.last = 1;
4828 r = r600_bytecode_add_alu(ctx->bc, &alu);
4829 if (r)
4830 return r;
4831
4832 return 0;
4833 }
4834
4835 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4836 {
4837 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4838 struct r600_bytecode_alu alu;
4839 int i, r;
4840
4841 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4842
4843 /* XXX:
4844 * For state trackers other than OpenGL, we'll want to use
4845 * _RECIPSQRT_IEEE instead.
4846 */
4847 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
4848
4849 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4850 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4851 r600_bytecode_src_set_abs(&alu.src[i]);
4852 }
4853 alu.dst.sel = ctx->temp_reg;
4854 alu.dst.write = 1;
4855 alu.last = 1;
4856 r = r600_bytecode_add_alu(ctx->bc, &alu);
4857 if (r)
4858 return r;
4859 /* replicate result */
4860 return tgsi_helper_tempx_replicate(ctx);
4861 }
4862
4863 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4864 {
4865 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4866 struct r600_bytecode_alu alu;
4867 int i, r;
4868
4869 for (i = 0; i < 4; i++) {
4870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4871 alu.src[0].sel = ctx->temp_reg;
4872 alu.op = ALU_OP1_MOV;
4873 alu.dst.chan = i;
4874 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4875 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4876 if (i == 3)
4877 alu.last = 1;
4878 r = r600_bytecode_add_alu(ctx->bc, &alu);
4879 if (r)
4880 return r;
4881 }
4882 return 0;
4883 }
4884
4885 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4886 {
4887 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4888 struct r600_bytecode_alu alu;
4889 int i, r;
4890
4891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4892 alu.op = ctx->inst_info->op;
4893 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4894 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4895 }
4896 alu.dst.sel = ctx->temp_reg;
4897 alu.dst.write = 1;
4898 alu.last = 1;
4899 r = r600_bytecode_add_alu(ctx->bc, &alu);
4900 if (r)
4901 return r;
4902 /* replicate result */
4903 return tgsi_helper_tempx_replicate(ctx);
4904 }
4905
4906 static int cayman_pow(struct r600_shader_ctx *ctx)
4907 {
4908 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4909 int i, r;
4910 struct r600_bytecode_alu alu;
4911 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4912
4913 for (i = 0; i < 3; i++) {
4914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4915 alu.op = ALU_OP1_LOG_IEEE;
4916 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4917 alu.dst.sel = ctx->temp_reg;
4918 alu.dst.chan = i;
4919 alu.dst.write = 1;
4920 if (i == 2)
4921 alu.last = 1;
4922 r = r600_bytecode_add_alu(ctx->bc, &alu);
4923 if (r)
4924 return r;
4925 }
4926
4927 /* b * LOG2(a) */
4928 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4929 alu.op = ALU_OP2_MUL;
4930 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4931 alu.src[1].sel = ctx->temp_reg;
4932 alu.dst.sel = ctx->temp_reg;
4933 alu.dst.write = 1;
4934 alu.last = 1;
4935 r = r600_bytecode_add_alu(ctx->bc, &alu);
4936 if (r)
4937 return r;
4938
4939 for (i = 0; i < last_slot; i++) {
4940 /* POW(a,b) = EXP2(b * LOG2(a))*/
4941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4942 alu.op = ALU_OP1_EXP_IEEE;
4943 alu.src[0].sel = ctx->temp_reg;
4944
4945 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4946 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4947 if (i == last_slot - 1)
4948 alu.last = 1;
4949 r = r600_bytecode_add_alu(ctx->bc, &alu);
4950 if (r)
4951 return r;
4952 }
4953 return 0;
4954 }
4955
4956 static int tgsi_pow(struct r600_shader_ctx *ctx)
4957 {
4958 struct r600_bytecode_alu alu;
4959 int r;
4960
4961 /* LOG2(a) */
4962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4963 alu.op = ALU_OP1_LOG_IEEE;
4964 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4965 alu.dst.sel = ctx->temp_reg;
4966 alu.dst.write = 1;
4967 alu.last = 1;
4968 r = r600_bytecode_add_alu(ctx->bc, &alu);
4969 if (r)
4970 return r;
4971 /* b * LOG2(a) */
4972 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4973 alu.op = ALU_OP2_MUL;
4974 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4975 alu.src[1].sel = ctx->temp_reg;
4976 alu.dst.sel = ctx->temp_reg;
4977 alu.dst.write = 1;
4978 alu.last = 1;
4979 r = r600_bytecode_add_alu(ctx->bc, &alu);
4980 if (r)
4981 return r;
4982 /* POW(a,b) = EXP2(b * LOG2(a))*/
4983 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4984 alu.op = ALU_OP1_EXP_IEEE;
4985 alu.src[0].sel = ctx->temp_reg;
4986 alu.dst.sel = ctx->temp_reg;
4987 alu.dst.write = 1;
4988 alu.last = 1;
4989 r = r600_bytecode_add_alu(ctx->bc, &alu);
4990 if (r)
4991 return r;
4992 return tgsi_helper_tempx_replicate(ctx);
4993 }
4994
4995 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
4996 {
4997 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4998 struct r600_bytecode_alu alu;
4999 int i, r, j;
5000 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5001 int tmp0 = ctx->temp_reg;
5002 int tmp1 = r600_get_temp(ctx);
5003 int tmp2 = r600_get_temp(ctx);
5004 int tmp3 = r600_get_temp(ctx);
5005 /* Unsigned path:
5006 *
5007 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5008 *
5009 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5010 * 2. tmp0.z = lo (tmp0.x * src2)
5011 * 3. tmp0.w = -tmp0.z
5012 * 4. tmp0.y = hi (tmp0.x * src2)
5013 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5014 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5015 * 7. tmp1.x = tmp0.x - tmp0.w
5016 * 8. tmp1.y = tmp0.x + tmp0.w
5017 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5018 * 10. tmp0.z = hi(tmp0.x * src1) = q
5019 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5020 *
5021 * 12. tmp0.w = src1 - tmp0.y = r
5022 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5023 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5024 *
5025 * if DIV
5026 *
5027 * 15. tmp1.z = tmp0.z + 1 = q + 1
5028 * 16. tmp1.w = tmp0.z - 1 = q - 1
5029 *
5030 * else MOD
5031 *
5032 * 15. tmp1.z = tmp0.w - src2 = r - src2
5033 * 16. tmp1.w = tmp0.w + src2 = r + src2
5034 *
5035 * endif
5036 *
5037 * 17. tmp1.x = tmp1.x & tmp1.y
5038 *
5039 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5040 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5041 *
5042 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5043 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5044 *
5045 * Signed path:
5046 *
5047 * Same as unsigned, using abs values of the operands,
5048 * and fixing the sign of the result in the end.
5049 */
5050
5051 for (i = 0; i < 4; i++) {
5052 if (!(write_mask & (1<<i)))
5053 continue;
5054
5055 if (signed_op) {
5056
5057 /* tmp2.x = -src0 */
5058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5059 alu.op = ALU_OP2_SUB_INT;
5060
5061 alu.dst.sel = tmp2;
5062 alu.dst.chan = 0;
5063 alu.dst.write = 1;
5064
5065 alu.src[0].sel = V_SQ_ALU_SRC_0;
5066
5067 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5068
5069 alu.last = 1;
5070 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5071 return r;
5072
5073 /* tmp2.y = -src1 */
5074 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5075 alu.op = ALU_OP2_SUB_INT;
5076
5077 alu.dst.sel = tmp2;
5078 alu.dst.chan = 1;
5079 alu.dst.write = 1;
5080
5081 alu.src[0].sel = V_SQ_ALU_SRC_0;
5082
5083 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5084
5085 alu.last = 1;
5086 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5087 return r;
5088
5089 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5090 /* it will be a sign of the quotient */
5091 if (!mod) {
5092
5093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5094 alu.op = ALU_OP2_XOR_INT;
5095
5096 alu.dst.sel = tmp2;
5097 alu.dst.chan = 2;
5098 alu.dst.write = 1;
5099
5100 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5101 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5102
5103 alu.last = 1;
5104 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5105 return r;
5106 }
5107
5108 /* tmp2.x = |src0| */
5109 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5110 alu.op = ALU_OP3_CNDGE_INT;
5111 alu.is_op3 = 1;
5112
5113 alu.dst.sel = tmp2;
5114 alu.dst.chan = 0;
5115 alu.dst.write = 1;
5116
5117 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5118 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5119 alu.src[2].sel = tmp2;
5120 alu.src[2].chan = 0;
5121
5122 alu.last = 1;
5123 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5124 return r;
5125
5126 /* tmp2.y = |src1| */
5127 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5128 alu.op = ALU_OP3_CNDGE_INT;
5129 alu.is_op3 = 1;
5130
5131 alu.dst.sel = tmp2;
5132 alu.dst.chan = 1;
5133 alu.dst.write = 1;
5134
5135 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5136 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5137 alu.src[2].sel = tmp2;
5138 alu.src[2].chan = 1;
5139
5140 alu.last = 1;
5141 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5142 return r;
5143
5144 }
5145
5146 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5147 if (ctx->bc->chip_class == CAYMAN) {
5148 /* tmp3.x = u2f(src2) */
5149 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5150 alu.op = ALU_OP1_UINT_TO_FLT;
5151
5152 alu.dst.sel = tmp3;
5153 alu.dst.chan = 0;
5154 alu.dst.write = 1;
5155
5156 if (signed_op) {
5157 alu.src[0].sel = tmp2;
5158 alu.src[0].chan = 1;
5159 } else {
5160 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5161 }
5162
5163 alu.last = 1;
5164 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5165 return r;
5166
5167 /* tmp0.x = recip(tmp3.x) */
5168 for (j = 0 ; j < 3; j++) {
5169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5170 alu.op = ALU_OP1_RECIP_IEEE;
5171
5172 alu.dst.sel = tmp0;
5173 alu.dst.chan = j;
5174 alu.dst.write = (j == 0);
5175
5176 alu.src[0].sel = tmp3;
5177 alu.src[0].chan = 0;
5178
5179 if (j == 2)
5180 alu.last = 1;
5181 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5182 return r;
5183 }
5184
5185 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5186 alu.op = ALU_OP2_MUL;
5187
5188 alu.src[0].sel = tmp0;
5189 alu.src[0].chan = 0;
5190
5191 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5192 alu.src[1].value = 0x4f800000;
5193
5194 alu.dst.sel = tmp3;
5195 alu.dst.write = 1;
5196 alu.last = 1;
5197 r = r600_bytecode_add_alu(ctx->bc, &alu);
5198 if (r)
5199 return r;
5200
5201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5202 alu.op = ALU_OP1_FLT_TO_UINT;
5203
5204 alu.dst.sel = tmp0;
5205 alu.dst.chan = 0;
5206 alu.dst.write = 1;
5207
5208 alu.src[0].sel = tmp3;
5209 alu.src[0].chan = 0;
5210
5211 alu.last = 1;
5212 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5213 return r;
5214
5215 } else {
5216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5217 alu.op = ALU_OP1_RECIP_UINT;
5218
5219 alu.dst.sel = tmp0;
5220 alu.dst.chan = 0;
5221 alu.dst.write = 1;
5222
5223 if (signed_op) {
5224 alu.src[0].sel = tmp2;
5225 alu.src[0].chan = 1;
5226 } else {
5227 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5228 }
5229
5230 alu.last = 1;
5231 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5232 return r;
5233 }
5234
5235 /* 2. tmp0.z = lo (tmp0.x * src2) */
5236 if (ctx->bc->chip_class == CAYMAN) {
5237 for (j = 0 ; j < 4; j++) {
5238 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5239 alu.op = ALU_OP2_MULLO_UINT;
5240
5241 alu.dst.sel = tmp0;
5242 alu.dst.chan = j;
5243 alu.dst.write = (j == 2);
5244
5245 alu.src[0].sel = tmp0;
5246 alu.src[0].chan = 0;
5247 if (signed_op) {
5248 alu.src[1].sel = tmp2;
5249 alu.src[1].chan = 1;
5250 } else {
5251 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5252 }
5253
5254 alu.last = (j == 3);
5255 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5256 return r;
5257 }
5258 } else {
5259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5260 alu.op = ALU_OP2_MULLO_UINT;
5261
5262 alu.dst.sel = tmp0;
5263 alu.dst.chan = 2;
5264 alu.dst.write = 1;
5265
5266 alu.src[0].sel = tmp0;
5267 alu.src[0].chan = 0;
5268 if (signed_op) {
5269 alu.src[1].sel = tmp2;
5270 alu.src[1].chan = 1;
5271 } else {
5272 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5273 }
5274
5275 alu.last = 1;
5276 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5277 return r;
5278 }
5279
5280 /* 3. tmp0.w = -tmp0.z */
5281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5282 alu.op = ALU_OP2_SUB_INT;
5283
5284 alu.dst.sel = tmp0;
5285 alu.dst.chan = 3;
5286 alu.dst.write = 1;
5287
5288 alu.src[0].sel = V_SQ_ALU_SRC_0;
5289 alu.src[1].sel = tmp0;
5290 alu.src[1].chan = 2;
5291
5292 alu.last = 1;
5293 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5294 return r;
5295
5296 /* 4. tmp0.y = hi (tmp0.x * src2) */
5297 if (ctx->bc->chip_class == CAYMAN) {
5298 for (j = 0 ; j < 4; j++) {
5299 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5300 alu.op = ALU_OP2_MULHI_UINT;
5301
5302 alu.dst.sel = tmp0;
5303 alu.dst.chan = j;
5304 alu.dst.write = (j == 1);
5305
5306 alu.src[0].sel = tmp0;
5307 alu.src[0].chan = 0;
5308
5309 if (signed_op) {
5310 alu.src[1].sel = tmp2;
5311 alu.src[1].chan = 1;
5312 } else {
5313 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5314 }
5315 alu.last = (j == 3);
5316 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5317 return r;
5318 }
5319 } else {
5320 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5321 alu.op = ALU_OP2_MULHI_UINT;
5322
5323 alu.dst.sel = tmp0;
5324 alu.dst.chan = 1;
5325 alu.dst.write = 1;
5326
5327 alu.src[0].sel = tmp0;
5328 alu.src[0].chan = 0;
5329
5330 if (signed_op) {
5331 alu.src[1].sel = tmp2;
5332 alu.src[1].chan = 1;
5333 } else {
5334 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5335 }
5336
5337 alu.last = 1;
5338 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5339 return r;
5340 }
5341
5342 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5344 alu.op = ALU_OP3_CNDE_INT;
5345 alu.is_op3 = 1;
5346
5347 alu.dst.sel = tmp0;
5348 alu.dst.chan = 2;
5349 alu.dst.write = 1;
5350
5351 alu.src[0].sel = tmp0;
5352 alu.src[0].chan = 1;
5353 alu.src[1].sel = tmp0;
5354 alu.src[1].chan = 3;
5355 alu.src[2].sel = tmp0;
5356 alu.src[2].chan = 2;
5357
5358 alu.last = 1;
5359 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5360 return r;
5361
5362 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5363 if (ctx->bc->chip_class == CAYMAN) {
5364 for (j = 0 ; j < 4; j++) {
5365 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5366 alu.op = ALU_OP2_MULHI_UINT;
5367
5368 alu.dst.sel = tmp0;
5369 alu.dst.chan = j;
5370 alu.dst.write = (j == 3);
5371
5372 alu.src[0].sel = tmp0;
5373 alu.src[0].chan = 2;
5374
5375 alu.src[1].sel = tmp0;
5376 alu.src[1].chan = 0;
5377
5378 alu.last = (j == 3);
5379 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5380 return r;
5381 }
5382 } else {
5383 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5384 alu.op = ALU_OP2_MULHI_UINT;
5385
5386 alu.dst.sel = tmp0;
5387 alu.dst.chan = 3;
5388 alu.dst.write = 1;
5389
5390 alu.src[0].sel = tmp0;
5391 alu.src[0].chan = 2;
5392
5393 alu.src[1].sel = tmp0;
5394 alu.src[1].chan = 0;
5395
5396 alu.last = 1;
5397 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5398 return r;
5399 }
5400
5401 /* 7. tmp1.x = tmp0.x - tmp0.w */
5402 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5403 alu.op = ALU_OP2_SUB_INT;
5404
5405 alu.dst.sel = tmp1;
5406 alu.dst.chan = 0;
5407 alu.dst.write = 1;
5408
5409 alu.src[0].sel = tmp0;
5410 alu.src[0].chan = 0;
5411 alu.src[1].sel = tmp0;
5412 alu.src[1].chan = 3;
5413
5414 alu.last = 1;
5415 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5416 return r;
5417
5418 /* 8. tmp1.y = tmp0.x + tmp0.w */
5419 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5420 alu.op = ALU_OP2_ADD_INT;
5421
5422 alu.dst.sel = tmp1;
5423 alu.dst.chan = 1;
5424 alu.dst.write = 1;
5425
5426 alu.src[0].sel = tmp0;
5427 alu.src[0].chan = 0;
5428 alu.src[1].sel = tmp0;
5429 alu.src[1].chan = 3;
5430
5431 alu.last = 1;
5432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5433 return r;
5434
5435 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5437 alu.op = ALU_OP3_CNDE_INT;
5438 alu.is_op3 = 1;
5439
5440 alu.dst.sel = tmp0;
5441 alu.dst.chan = 0;
5442 alu.dst.write = 1;
5443
5444 alu.src[0].sel = tmp0;
5445 alu.src[0].chan = 1;
5446 alu.src[1].sel = tmp1;
5447 alu.src[1].chan = 1;
5448 alu.src[2].sel = tmp1;
5449 alu.src[2].chan = 0;
5450
5451 alu.last = 1;
5452 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5453 return r;
5454
5455 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5456 if (ctx->bc->chip_class == CAYMAN) {
5457 for (j = 0 ; j < 4; j++) {
5458 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5459 alu.op = ALU_OP2_MULHI_UINT;
5460
5461 alu.dst.sel = tmp0;
5462 alu.dst.chan = j;
5463 alu.dst.write = (j == 2);
5464
5465 alu.src[0].sel = tmp0;
5466 alu.src[0].chan = 0;
5467
5468 if (signed_op) {
5469 alu.src[1].sel = tmp2;
5470 alu.src[1].chan = 0;
5471 } else {
5472 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5473 }
5474
5475 alu.last = (j == 3);
5476 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5477 return r;
5478 }
5479 } else {
5480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5481 alu.op = ALU_OP2_MULHI_UINT;
5482
5483 alu.dst.sel = tmp0;
5484 alu.dst.chan = 2;
5485 alu.dst.write = 1;
5486
5487 alu.src[0].sel = tmp0;
5488 alu.src[0].chan = 0;
5489
5490 if (signed_op) {
5491 alu.src[1].sel = tmp2;
5492 alu.src[1].chan = 0;
5493 } else {
5494 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5495 }
5496
5497 alu.last = 1;
5498 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5499 return r;
5500 }
5501
5502 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5503 if (ctx->bc->chip_class == CAYMAN) {
5504 for (j = 0 ; j < 4; j++) {
5505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5506 alu.op = ALU_OP2_MULLO_UINT;
5507
5508 alu.dst.sel = tmp0;
5509 alu.dst.chan = j;
5510 alu.dst.write = (j == 1);
5511
5512 if (signed_op) {
5513 alu.src[0].sel = tmp2;
5514 alu.src[0].chan = 1;
5515 } else {
5516 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5517 }
5518
5519 alu.src[1].sel = tmp0;
5520 alu.src[1].chan = 2;
5521
5522 alu.last = (j == 3);
5523 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5524 return r;
5525 }
5526 } else {
5527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5528 alu.op = ALU_OP2_MULLO_UINT;
5529
5530 alu.dst.sel = tmp0;
5531 alu.dst.chan = 1;
5532 alu.dst.write = 1;
5533
5534 if (signed_op) {
5535 alu.src[0].sel = tmp2;
5536 alu.src[0].chan = 1;
5537 } else {
5538 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5539 }
5540
5541 alu.src[1].sel = tmp0;
5542 alu.src[1].chan = 2;
5543
5544 alu.last = 1;
5545 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5546 return r;
5547 }
5548
5549 /* 12. tmp0.w = src1 - tmp0.y = r */
5550 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5551 alu.op = ALU_OP2_SUB_INT;
5552
5553 alu.dst.sel = tmp0;
5554 alu.dst.chan = 3;
5555 alu.dst.write = 1;
5556
5557 if (signed_op) {
5558 alu.src[0].sel = tmp2;
5559 alu.src[0].chan = 0;
5560 } else {
5561 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5562 }
5563
5564 alu.src[1].sel = tmp0;
5565 alu.src[1].chan = 1;
5566
5567 alu.last = 1;
5568 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5569 return r;
5570
5571 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5573 alu.op = ALU_OP2_SETGE_UINT;
5574
5575 alu.dst.sel = tmp1;
5576 alu.dst.chan = 0;
5577 alu.dst.write = 1;
5578
5579 alu.src[0].sel = tmp0;
5580 alu.src[0].chan = 3;
5581 if (signed_op) {
5582 alu.src[1].sel = tmp2;
5583 alu.src[1].chan = 1;
5584 } else {
5585 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5586 }
5587
5588 alu.last = 1;
5589 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5590 return r;
5591
5592 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5593 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5594 alu.op = ALU_OP2_SETGE_UINT;
5595
5596 alu.dst.sel = tmp1;
5597 alu.dst.chan = 1;
5598 alu.dst.write = 1;
5599
5600 if (signed_op) {
5601 alu.src[0].sel = tmp2;
5602 alu.src[0].chan = 0;
5603 } else {
5604 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5605 }
5606
5607 alu.src[1].sel = tmp0;
5608 alu.src[1].chan = 1;
5609
5610 alu.last = 1;
5611 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5612 return r;
5613
5614 if (mod) { /* UMOD */
5615
5616 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5617 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5618 alu.op = ALU_OP2_SUB_INT;
5619
5620 alu.dst.sel = tmp1;
5621 alu.dst.chan = 2;
5622 alu.dst.write = 1;
5623
5624 alu.src[0].sel = tmp0;
5625 alu.src[0].chan = 3;
5626
5627 if (signed_op) {
5628 alu.src[1].sel = tmp2;
5629 alu.src[1].chan = 1;
5630 } else {
5631 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5632 }
5633
5634 alu.last = 1;
5635 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5636 return r;
5637
5638 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5639 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5640 alu.op = ALU_OP2_ADD_INT;
5641
5642 alu.dst.sel = tmp1;
5643 alu.dst.chan = 3;
5644 alu.dst.write = 1;
5645
5646 alu.src[0].sel = tmp0;
5647 alu.src[0].chan = 3;
5648 if (signed_op) {
5649 alu.src[1].sel = tmp2;
5650 alu.src[1].chan = 1;
5651 } else {
5652 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5653 }
5654
5655 alu.last = 1;
5656 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5657 return r;
5658
5659 } else { /* UDIV */
5660
5661 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5662 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5663 alu.op = ALU_OP2_ADD_INT;
5664
5665 alu.dst.sel = tmp1;
5666 alu.dst.chan = 2;
5667 alu.dst.write = 1;
5668
5669 alu.src[0].sel = tmp0;
5670 alu.src[0].chan = 2;
5671 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5672
5673 alu.last = 1;
5674 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5675 return r;
5676
5677 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5679 alu.op = ALU_OP2_ADD_INT;
5680
5681 alu.dst.sel = tmp1;
5682 alu.dst.chan = 3;
5683 alu.dst.write = 1;
5684
5685 alu.src[0].sel = tmp0;
5686 alu.src[0].chan = 2;
5687 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5688
5689 alu.last = 1;
5690 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5691 return r;
5692
5693 }
5694
5695 /* 17. tmp1.x = tmp1.x & tmp1.y */
5696 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5697 alu.op = ALU_OP2_AND_INT;
5698
5699 alu.dst.sel = tmp1;
5700 alu.dst.chan = 0;
5701 alu.dst.write = 1;
5702
5703 alu.src[0].sel = tmp1;
5704 alu.src[0].chan = 0;
5705 alu.src[1].sel = tmp1;
5706 alu.src[1].chan = 1;
5707
5708 alu.last = 1;
5709 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5710 return r;
5711
5712 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5713 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5714 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5715 alu.op = ALU_OP3_CNDE_INT;
5716 alu.is_op3 = 1;
5717
5718 alu.dst.sel = tmp0;
5719 alu.dst.chan = 2;
5720 alu.dst.write = 1;
5721
5722 alu.src[0].sel = tmp1;
5723 alu.src[0].chan = 0;
5724 alu.src[1].sel = tmp0;
5725 alu.src[1].chan = mod ? 3 : 2;
5726 alu.src[2].sel = tmp1;
5727 alu.src[2].chan = 2;
5728
5729 alu.last = 1;
5730 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5731 return r;
5732
5733 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5734 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5735 alu.op = ALU_OP3_CNDE_INT;
5736 alu.is_op3 = 1;
5737
5738 if (signed_op) {
5739 alu.dst.sel = tmp0;
5740 alu.dst.chan = 2;
5741 alu.dst.write = 1;
5742 } else {
5743 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5744 }
5745
5746 alu.src[0].sel = tmp1;
5747 alu.src[0].chan = 1;
5748 alu.src[1].sel = tmp1;
5749 alu.src[1].chan = 3;
5750 alu.src[2].sel = tmp0;
5751 alu.src[2].chan = 2;
5752
5753 alu.last = 1;
5754 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5755 return r;
5756
5757 if (signed_op) {
5758
5759 /* fix the sign of the result */
5760
5761 if (mod) {
5762
5763 /* tmp0.x = -tmp0.z */
5764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5765 alu.op = ALU_OP2_SUB_INT;
5766
5767 alu.dst.sel = tmp0;
5768 alu.dst.chan = 0;
5769 alu.dst.write = 1;
5770
5771 alu.src[0].sel = V_SQ_ALU_SRC_0;
5772 alu.src[1].sel = tmp0;
5773 alu.src[1].chan = 2;
5774
5775 alu.last = 1;
5776 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5777 return r;
5778
5779 /* sign of the remainder is the same as the sign of src0 */
5780 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5781 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5782 alu.op = ALU_OP3_CNDGE_INT;
5783 alu.is_op3 = 1;
5784
5785 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5786
5787 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5788 alu.src[1].sel = tmp0;
5789 alu.src[1].chan = 2;
5790 alu.src[2].sel = tmp0;
5791 alu.src[2].chan = 0;
5792
5793 alu.last = 1;
5794 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5795 return r;
5796
5797 } else {
5798
5799 /* tmp0.x = -tmp0.z */
5800 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5801 alu.op = ALU_OP2_SUB_INT;
5802
5803 alu.dst.sel = tmp0;
5804 alu.dst.chan = 0;
5805 alu.dst.write = 1;
5806
5807 alu.src[0].sel = V_SQ_ALU_SRC_0;
5808 alu.src[1].sel = tmp0;
5809 alu.src[1].chan = 2;
5810
5811 alu.last = 1;
5812 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5813 return r;
5814
5815 /* fix the quotient sign (same as the sign of src0*src1) */
5816 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5817 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5818 alu.op = ALU_OP3_CNDGE_INT;
5819 alu.is_op3 = 1;
5820
5821 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5822
5823 alu.src[0].sel = tmp2;
5824 alu.src[0].chan = 2;
5825 alu.src[1].sel = tmp0;
5826 alu.src[1].chan = 2;
5827 alu.src[2].sel = tmp0;
5828 alu.src[2].chan = 0;
5829
5830 alu.last = 1;
5831 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5832 return r;
5833 }
5834 }
5835 }
5836 return 0;
5837 }
5838
5839 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5840 {
5841 return tgsi_divmod(ctx, 0, 0);
5842 }
5843
5844 static int tgsi_umod(struct r600_shader_ctx *ctx)
5845 {
5846 return tgsi_divmod(ctx, 1, 0);
5847 }
5848
5849 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5850 {
5851 return tgsi_divmod(ctx, 0, 1);
5852 }
5853
5854 static int tgsi_imod(struct r600_shader_ctx *ctx)
5855 {
5856 return tgsi_divmod(ctx, 1, 1);
5857 }
5858
5859
5860 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5861 {
5862 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5863 struct r600_bytecode_alu alu;
5864 int i, r;
5865 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5866 int last_inst = tgsi_last_instruction(write_mask);
5867
5868 for (i = 0; i < 4; i++) {
5869 if (!(write_mask & (1<<i)))
5870 continue;
5871
5872 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5873 alu.op = ALU_OP1_TRUNC;
5874
5875 alu.dst.sel = ctx->temp_reg;
5876 alu.dst.chan = i;
5877 alu.dst.write = 1;
5878
5879 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5880 if (i == last_inst)
5881 alu.last = 1;
5882 r = r600_bytecode_add_alu(ctx->bc, &alu);
5883 if (r)
5884 return r;
5885 }
5886
5887 for (i = 0; i < 4; i++) {
5888 if (!(write_mask & (1<<i)))
5889 continue;
5890
5891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5892 alu.op = ctx->inst_info->op;
5893
5894 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5895
5896 alu.src[0].sel = ctx->temp_reg;
5897 alu.src[0].chan = i;
5898
5899 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5900 alu.last = 1;
5901 r = r600_bytecode_add_alu(ctx->bc, &alu);
5902 if (r)
5903 return r;
5904 }
5905
5906 return 0;
5907 }
5908
5909 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5910 {
5911 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5912 struct r600_bytecode_alu alu;
5913 int i, r;
5914 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5915 int last_inst = tgsi_last_instruction(write_mask);
5916
5917 /* tmp = -src */
5918 for (i = 0; i < 4; i++) {
5919 if (!(write_mask & (1<<i)))
5920 continue;
5921
5922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5923 alu.op = ALU_OP2_SUB_INT;
5924
5925 alu.dst.sel = ctx->temp_reg;
5926 alu.dst.chan = i;
5927 alu.dst.write = 1;
5928
5929 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5930 alu.src[0].sel = V_SQ_ALU_SRC_0;
5931
5932 if (i == last_inst)
5933 alu.last = 1;
5934 r = r600_bytecode_add_alu(ctx->bc, &alu);
5935 if (r)
5936 return r;
5937 }
5938
5939 /* dst = (src >= 0 ? src : tmp) */
5940 for (i = 0; i < 4; i++) {
5941 if (!(write_mask & (1<<i)))
5942 continue;
5943
5944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5945 alu.op = ALU_OP3_CNDGE_INT;
5946 alu.is_op3 = 1;
5947 alu.dst.write = 1;
5948
5949 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5950
5951 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5952 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5953 alu.src[2].sel = ctx->temp_reg;
5954 alu.src[2].chan = i;
5955
5956 if (i == last_inst)
5957 alu.last = 1;
5958 r = r600_bytecode_add_alu(ctx->bc, &alu);
5959 if (r)
5960 return r;
5961 }
5962 return 0;
5963 }
5964
5965 static int tgsi_issg(struct r600_shader_ctx *ctx)
5966 {
5967 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5968 struct r600_bytecode_alu alu;
5969 int i, r;
5970 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5971 int last_inst = tgsi_last_instruction(write_mask);
5972
5973 /* tmp = (src >= 0 ? src : -1) */
5974 for (i = 0; i < 4; i++) {
5975 if (!(write_mask & (1<<i)))
5976 continue;
5977
5978 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5979 alu.op = ALU_OP3_CNDGE_INT;
5980 alu.is_op3 = 1;
5981
5982 alu.dst.sel = ctx->temp_reg;
5983 alu.dst.chan = i;
5984 alu.dst.write = 1;
5985
5986 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5987 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5988 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
5989
5990 if (i == last_inst)
5991 alu.last = 1;
5992 r = r600_bytecode_add_alu(ctx->bc, &alu);
5993 if (r)
5994 return r;
5995 }
5996
5997 /* dst = (tmp > 0 ? 1 : tmp) */
5998 for (i = 0; i < 4; i++) {
5999 if (!(write_mask & (1<<i)))
6000 continue;
6001
6002 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6003 alu.op = ALU_OP3_CNDGT_INT;
6004 alu.is_op3 = 1;
6005 alu.dst.write = 1;
6006
6007 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6008
6009 alu.src[0].sel = ctx->temp_reg;
6010 alu.src[0].chan = i;
6011
6012 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6013
6014 alu.src[2].sel = ctx->temp_reg;
6015 alu.src[2].chan = i;
6016
6017 if (i == last_inst)
6018 alu.last = 1;
6019 r = r600_bytecode_add_alu(ctx->bc, &alu);
6020 if (r)
6021 return r;
6022 }
6023 return 0;
6024 }
6025
6026
6027
6028 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6029 {
6030 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6031 struct r600_bytecode_alu alu;
6032 int i, r;
6033
6034 /* tmp = (src > 0 ? 1 : src) */
6035 for (i = 0; i < 4; i++) {
6036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6037 alu.op = ALU_OP3_CNDGT;
6038 alu.is_op3 = 1;
6039
6040 alu.dst.sel = ctx->temp_reg;
6041 alu.dst.chan = i;
6042
6043 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6044 alu.src[1].sel = V_SQ_ALU_SRC_1;
6045 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6046
6047 if (i == 3)
6048 alu.last = 1;
6049 r = r600_bytecode_add_alu(ctx->bc, &alu);
6050 if (r)
6051 return r;
6052 }
6053
6054 /* dst = (-tmp > 0 ? -1 : tmp) */
6055 for (i = 0; i < 4; i++) {
6056 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6057 alu.op = ALU_OP3_CNDGT;
6058 alu.is_op3 = 1;
6059 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6060
6061 alu.src[0].sel = ctx->temp_reg;
6062 alu.src[0].chan = i;
6063 alu.src[0].neg = 1;
6064
6065 alu.src[1].sel = V_SQ_ALU_SRC_1;
6066 alu.src[1].neg = 1;
6067
6068 alu.src[2].sel = ctx->temp_reg;
6069 alu.src[2].chan = i;
6070
6071 if (i == 3)
6072 alu.last = 1;
6073 r = r600_bytecode_add_alu(ctx->bc, &alu);
6074 if (r)
6075 return r;
6076 }
6077 return 0;
6078 }
6079
6080 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6081 {
6082 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6083 struct r600_bytecode_alu alu;
6084 int i, r, t1, t2;
6085
6086 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6087 int last_inst = tgsi_last_instruction(write_mask);
6088
6089 t1 = ctx->temp_reg;
6090
6091 for (i = 0; i < 4; i++) {
6092 if (!(write_mask & (1<<i)))
6093 continue;
6094
6095 /* create mask tmp */
6096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6097 alu.op = ALU_OP2_BFM_INT;
6098 alu.dst.sel = t1;
6099 alu.dst.chan = i;
6100 alu.dst.write = 1;
6101 alu.last = i == last_inst;
6102
6103 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6104 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6105
6106 r = r600_bytecode_add_alu(ctx->bc, &alu);
6107 if (r)
6108 return r;
6109 }
6110
6111 t2 = r600_get_temp(ctx);
6112
6113 for (i = 0; i < 4; i++) {
6114 if (!(write_mask & (1<<i)))
6115 continue;
6116
6117 /* shift insert left */
6118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6119 alu.op = ALU_OP2_LSHL_INT;
6120 alu.dst.sel = t2;
6121 alu.dst.chan = i;
6122 alu.dst.write = 1;
6123 alu.last = i == last_inst;
6124
6125 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6126 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6127
6128 r = r600_bytecode_add_alu(ctx->bc, &alu);
6129 if (r)
6130 return r;
6131 }
6132
6133 for (i = 0; i < 4; i++) {
6134 if (!(write_mask & (1<<i)))
6135 continue;
6136
6137 /* actual bitfield insert */
6138 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6139 alu.op = ALU_OP3_BFI_INT;
6140 alu.is_op3 = 1;
6141 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6142 alu.dst.chan = i;
6143 alu.dst.write = 1;
6144 alu.last = i == last_inst;
6145
6146 alu.src[0].sel = t1;
6147 alu.src[0].chan = i;
6148 alu.src[1].sel = t2;
6149 alu.src[1].chan = i;
6150 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6151
6152 r = r600_bytecode_add_alu(ctx->bc, &alu);
6153 if (r)
6154 return r;
6155 }
6156
6157 return 0;
6158 }
6159
6160 static int tgsi_msb(struct r600_shader_ctx *ctx)
6161 {
6162 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6163 struct r600_bytecode_alu alu;
6164 int i, r, t1, t2;
6165
6166 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6167 int last_inst = tgsi_last_instruction(write_mask);
6168
6169 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6170 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6171
6172 t1 = ctx->temp_reg;
6173
6174 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6175 for (i = 0; i < 4; i++) {
6176 if (!(write_mask & (1<<i)))
6177 continue;
6178
6179 /* t1 = FFBH_INT / FFBH_UINT */
6180 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6181 alu.op = ctx->inst_info->op;
6182 alu.dst.sel = t1;
6183 alu.dst.chan = i;
6184 alu.dst.write = 1;
6185 alu.last = i == last_inst;
6186
6187 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6188
6189 r = r600_bytecode_add_alu(ctx->bc, &alu);
6190 if (r)
6191 return r;
6192 }
6193
6194 t2 = r600_get_temp(ctx);
6195
6196 for (i = 0; i < 4; i++) {
6197 if (!(write_mask & (1<<i)))
6198 continue;
6199
6200 /* t2 = 31 - t1 */
6201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6202 alu.op = ALU_OP2_SUB_INT;
6203 alu.dst.sel = t2;
6204 alu.dst.chan = i;
6205 alu.dst.write = 1;
6206 alu.last = i == last_inst;
6207
6208 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6209 alu.src[0].value = 31;
6210 alu.src[1].sel = t1;
6211 alu.src[1].chan = i;
6212
6213 r = r600_bytecode_add_alu(ctx->bc, &alu);
6214 if (r)
6215 return r;
6216 }
6217
6218 for (i = 0; i < 4; i++) {
6219 if (!(write_mask & (1<<i)))
6220 continue;
6221
6222 /* result = t1 >= 0 ? t2 : t1 */
6223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6224 alu.op = ALU_OP3_CNDGE_INT;
6225 alu.is_op3 = 1;
6226 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6227 alu.dst.chan = i;
6228 alu.dst.write = 1;
6229 alu.last = i == last_inst;
6230
6231 alu.src[0].sel = t1;
6232 alu.src[0].chan = i;
6233 alu.src[1].sel = t2;
6234 alu.src[1].chan = i;
6235 alu.src[2].sel = t1;
6236 alu.src[2].chan = i;
6237
6238 r = r600_bytecode_add_alu(ctx->bc, &alu);
6239 if (r)
6240 return r;
6241 }
6242
6243 return 0;
6244 }
6245
6246 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6247 {
6248 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6249 struct r600_bytecode_alu alu;
6250 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6251 unsigned location;
6252 int input;
6253
6254 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6255
6256 input = inst->Src[0].Register.Index;
6257
6258 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6259 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6260 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6261 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6262 }
6263 else {
6264 location = TGSI_INTERPOLATE_LOC_CENTROID;
6265 }
6266
6267 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6268 if (k < 0)
6269 k = 0;
6270 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6271 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6272
6273 /* NOTE: currently offset is not perspective correct */
6274 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6275 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6276 int sample_gpr = -1;
6277 int gradientsH, gradientsV;
6278 struct r600_bytecode_tex tex;
6279
6280 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6281 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6282 }
6283
6284 gradientsH = r600_get_temp(ctx);
6285 gradientsV = r600_get_temp(ctx);
6286 for (i = 0; i < 2; i++) {
6287 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6288 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6289 tex.src_gpr = interp_gpr;
6290 tex.src_sel_x = interp_base_chan + 0;
6291 tex.src_sel_y = interp_base_chan + 1;
6292 tex.src_sel_z = 0;
6293 tex.src_sel_w = 0;
6294 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6295 tex.dst_sel_x = 0;
6296 tex.dst_sel_y = 1;
6297 tex.dst_sel_z = 7;
6298 tex.dst_sel_w = 7;
6299 tex.inst_mod = 1; // Use per pixel gradient calculation
6300 tex.sampler_id = 0;
6301 tex.resource_id = tex.sampler_id;
6302 r = r600_bytecode_add_tex(ctx->bc, &tex);
6303 if (r)
6304 return r;
6305 }
6306
6307 for (i = 0; i < 2; i++) {
6308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6309 alu.op = ALU_OP3_MULADD;
6310 alu.is_op3 = 1;
6311 alu.src[0].sel = gradientsH;
6312 alu.src[0].chan = i;
6313 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6314 alu.src[1].sel = sample_gpr;
6315 alu.src[1].chan = 2;
6316 }
6317 else {
6318 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6319 }
6320 alu.src[2].sel = interp_gpr;
6321 alu.src[2].chan = interp_base_chan + i;
6322 alu.dst.sel = ctx->temp_reg;
6323 alu.dst.chan = i;
6324 alu.last = i == 1;
6325
6326 r = r600_bytecode_add_alu(ctx->bc, &alu);
6327 if (r)
6328 return r;
6329 }
6330
6331 for (i = 0; i < 2; i++) {
6332 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6333 alu.op = ALU_OP3_MULADD;
6334 alu.is_op3 = 1;
6335 alu.src[0].sel = gradientsV;
6336 alu.src[0].chan = i;
6337 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6338 alu.src[1].sel = sample_gpr;
6339 alu.src[1].chan = 3;
6340 }
6341 else {
6342 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6343 }
6344 alu.src[2].sel = ctx->temp_reg;
6345 alu.src[2].chan = i;
6346 alu.dst.sel = ctx->temp_reg;
6347 alu.dst.chan = i;
6348 alu.last = i == 1;
6349
6350 r = r600_bytecode_add_alu(ctx->bc, &alu);
6351 if (r)
6352 return r;
6353 }
6354 }
6355
6356 tmp = r600_get_temp(ctx);
6357 for (i = 0; i < 8; i++) {
6358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6359 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6360
6361 alu.dst.sel = tmp;
6362 if ((i > 1 && i < 6)) {
6363 alu.dst.write = 1;
6364 }
6365 else {
6366 alu.dst.write = 0;
6367 }
6368 alu.dst.chan = i % 4;
6369
6370 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6371 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6372 alu.src[0].sel = ctx->temp_reg;
6373 alu.src[0].chan = 1 - (i % 2);
6374 } else {
6375 alu.src[0].sel = interp_gpr;
6376 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6377 }
6378 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6379 alu.src[1].chan = 0;
6380
6381 alu.last = i % 4 == 3;
6382 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6383
6384 r = r600_bytecode_add_alu(ctx->bc, &alu);
6385 if (r)
6386 return r;
6387 }
6388
6389 // INTERP can't swizzle dst
6390 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6391 for (i = 0; i <= lasti; i++) {
6392 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6393 continue;
6394
6395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6396 alu.op = ALU_OP1_MOV;
6397 alu.src[0].sel = tmp;
6398 alu.src[0].chan = ctx->src[0].swizzle[i];
6399 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6400 alu.dst.write = 1;
6401 alu.last = i == lasti;
6402 r = r600_bytecode_add_alu(ctx->bc, &alu);
6403 if (r)
6404 return r;
6405 }
6406
6407 return 0;
6408 }
6409
6410
6411 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6412 {
6413 struct r600_bytecode_alu alu;
6414 int i, r;
6415
6416 for (i = 0; i < 4; i++) {
6417 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6418 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6419 alu.op = ALU_OP0_NOP;
6420 alu.dst.chan = i;
6421 } else {
6422 alu.op = ALU_OP1_MOV;
6423 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6424 alu.src[0].sel = ctx->temp_reg;
6425 alu.src[0].chan = i;
6426 }
6427 if (i == 3) {
6428 alu.last = 1;
6429 }
6430 r = r600_bytecode_add_alu(ctx->bc, &alu);
6431 if (r)
6432 return r;
6433 }
6434 return 0;
6435 }
6436
6437 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6438 unsigned temp, int chan,
6439 struct r600_bytecode_alu_src *bc_src,
6440 const struct r600_shader_src *shader_src)
6441 {
6442 struct r600_bytecode_alu alu;
6443 int r;
6444
6445 r600_bytecode_src(bc_src, shader_src, chan);
6446
6447 /* op3 operands don't support abs modifier */
6448 if (bc_src->abs) {
6449 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6450 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6451 alu.op = ALU_OP1_MOV;
6452 alu.dst.sel = temp;
6453 alu.dst.chan = chan;
6454 alu.dst.write = 1;
6455
6456 alu.src[0] = *bc_src;
6457 alu.last = true; // sufficient?
6458 r = r600_bytecode_add_alu(ctx->bc, &alu);
6459 if (r)
6460 return r;
6461
6462 memset(bc_src, 0, sizeof(*bc_src));
6463 bc_src->sel = temp;
6464 bc_src->chan = chan;
6465 }
6466 return 0;
6467 }
6468
6469 static int tgsi_op3(struct r600_shader_ctx *ctx)
6470 {
6471 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6472 struct r600_bytecode_alu alu;
6473 int i, j, r;
6474 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6475 int temp_regs[4];
6476
6477 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6478 temp_regs[j] = 0;
6479 if (ctx->src[j].abs)
6480 temp_regs[j] = r600_get_temp(ctx);
6481 }
6482 for (i = 0; i < lasti + 1; i++) {
6483 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6484 continue;
6485
6486 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6487 alu.op = ctx->inst_info->op;
6488 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6489 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6490 if (r)
6491 return r;
6492 }
6493
6494 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6495 alu.dst.chan = i;
6496 alu.dst.write = 1;
6497 alu.is_op3 = 1;
6498 if (i == lasti) {
6499 alu.last = 1;
6500 }
6501 r = r600_bytecode_add_alu(ctx->bc, &alu);
6502 if (r)
6503 return r;
6504 }
6505 return 0;
6506 }
6507
6508 static int tgsi_dp(struct r600_shader_ctx *ctx)
6509 {
6510 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6511 struct r600_bytecode_alu alu;
6512 int i, j, r;
6513
6514 for (i = 0; i < 4; i++) {
6515 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6516 alu.op = ctx->inst_info->op;
6517 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6518 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6519 }
6520
6521 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6522 alu.dst.chan = i;
6523 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6524 /* handle some special cases */
6525 switch (inst->Instruction.Opcode) {
6526 case TGSI_OPCODE_DP2:
6527 if (i > 1) {
6528 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6529 alu.src[0].chan = alu.src[1].chan = 0;
6530 }
6531 break;
6532 case TGSI_OPCODE_DP3:
6533 if (i > 2) {
6534 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6535 alu.src[0].chan = alu.src[1].chan = 0;
6536 }
6537 break;
6538 case TGSI_OPCODE_DPH:
6539 if (i == 3) {
6540 alu.src[0].sel = V_SQ_ALU_SRC_1;
6541 alu.src[0].chan = 0;
6542 alu.src[0].neg = 0;
6543 }
6544 break;
6545 default:
6546 break;
6547 }
6548 if (i == 3) {
6549 alu.last = 1;
6550 }
6551 r = r600_bytecode_add_alu(ctx->bc, &alu);
6552 if (r)
6553 return r;
6554 }
6555 return 0;
6556 }
6557
6558 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6559 unsigned index)
6560 {
6561 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6562 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6563 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6564 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6565 ctx->src[index].neg || ctx->src[index].abs ||
6566 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6567 }
6568
6569 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6570 unsigned index)
6571 {
6572 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6573 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6574 }
6575
6576 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6577 {
6578 struct r600_bytecode_vtx vtx;
6579 struct r600_bytecode_alu alu;
6580 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6581 int src_gpr, r, i;
6582 int id = tgsi_tex_get_src_gpr(ctx, 1);
6583
6584 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6585 if (src_requires_loading) {
6586 for (i = 0; i < 4; i++) {
6587 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6588 alu.op = ALU_OP1_MOV;
6589 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6590 alu.dst.sel = ctx->temp_reg;
6591 alu.dst.chan = i;
6592 if (i == 3)
6593 alu.last = 1;
6594 alu.dst.write = 1;
6595 r = r600_bytecode_add_alu(ctx->bc, &alu);
6596 if (r)
6597 return r;
6598 }
6599 src_gpr = ctx->temp_reg;
6600 }
6601
6602 memset(&vtx, 0, sizeof(vtx));
6603 vtx.op = FETCH_OP_VFETCH;
6604 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6605 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6606 vtx.src_gpr = src_gpr;
6607 vtx.mega_fetch_count = 16;
6608 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6609 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6610 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6611 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6612 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6613 vtx.use_const_fields = 1;
6614
6615 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6616 return r;
6617
6618 if (ctx->bc->chip_class >= EVERGREEN)
6619 return 0;
6620
6621 for (i = 0; i < 4; i++) {
6622 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6623 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6624 continue;
6625
6626 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6627 alu.op = ALU_OP2_AND_INT;
6628
6629 alu.dst.chan = i;
6630 alu.dst.sel = vtx.dst_gpr;
6631 alu.dst.write = 1;
6632
6633 alu.src[0].sel = vtx.dst_gpr;
6634 alu.src[0].chan = i;
6635
6636 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6637 alu.src[1].sel += (id * 2);
6638 alu.src[1].chan = i % 4;
6639 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6640
6641 if (i == lasti)
6642 alu.last = 1;
6643 r = r600_bytecode_add_alu(ctx->bc, &alu);
6644 if (r)
6645 return r;
6646 }
6647
6648 if (inst->Dst[0].Register.WriteMask & 3) {
6649 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6650 alu.op = ALU_OP2_OR_INT;
6651
6652 alu.dst.chan = 3;
6653 alu.dst.sel = vtx.dst_gpr;
6654 alu.dst.write = 1;
6655
6656 alu.src[0].sel = vtx.dst_gpr;
6657 alu.src[0].chan = 3;
6658
6659 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6660 alu.src[1].chan = 0;
6661 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6662
6663 alu.last = 1;
6664 r = r600_bytecode_add_alu(ctx->bc, &alu);
6665 if (r)
6666 return r;
6667 }
6668 return 0;
6669 }
6670
6671 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6672 {
6673 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6674 struct r600_bytecode_alu alu;
6675 int r;
6676 int id = tgsi_tex_get_src_gpr(ctx, 1);
6677
6678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6679 alu.op = ALU_OP1_MOV;
6680 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6681 if (ctx->bc->chip_class >= EVERGREEN) {
6682 /* channel 0 or 2 of each word */
6683 alu.src[0].sel += (id / 2);
6684 alu.src[0].chan = (id % 2) * 2;
6685 } else {
6686 /* r600 we have them at channel 2 of the second dword */
6687 alu.src[0].sel += (id * 2) + 1;
6688 alu.src[0].chan = 1;
6689 }
6690 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6691 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6692 alu.last = 1;
6693 r = r600_bytecode_add_alu(ctx->bc, &alu);
6694 if (r)
6695 return r;
6696 return 0;
6697 }
6698
6699 static int tgsi_tex(struct r600_shader_ctx *ctx)
6700 {
6701 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6702 struct r600_bytecode_tex tex;
6703 struct r600_bytecode_alu alu;
6704 unsigned src_gpr;
6705 int r, i, j;
6706 int opcode;
6707 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6708 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6709 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6710 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6711
6712 bool txf_add_offsets = inst->Texture.NumOffsets &&
6713 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6714 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6715
6716 /* Texture fetch instructions can only use gprs as source.
6717 * Also they cannot negate the source or take the absolute value */
6718 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
6719 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6720 tgsi_tex_src_requires_loading(ctx, 0)) ||
6721 read_compressed_msaa || txf_add_offsets;
6722
6723 boolean src_loaded = FALSE;
6724 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
6725 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6726 boolean has_txq_cube_array_z = false;
6727 unsigned sampler_index_mode;
6728
6729 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6730 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6731 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6732 if (inst->Dst[0].Register.WriteMask & 4) {
6733 ctx->shader->has_txq_cube_array_z_comp = true;
6734 has_txq_cube_array_z = true;
6735 }
6736
6737 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6738 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6739 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6740 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6741 sampler_src_reg = 2;
6742
6743 /* TGSI moves the sampler to src reg 3 for TXD */
6744 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6745 sampler_src_reg = 3;
6746
6747 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6748
6749 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6750
6751 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6752 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6753 ctx->shader->uses_tex_buffers = true;
6754 return r600_do_buffer_txq(ctx);
6755 }
6756 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6757 if (ctx->bc->chip_class < EVERGREEN)
6758 ctx->shader->uses_tex_buffers = true;
6759 return do_vtx_fetch_inst(ctx, src_requires_loading);
6760 }
6761 }
6762
6763 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6764 int out_chan;
6765 /* Add perspective divide */
6766 if (ctx->bc->chip_class == CAYMAN) {
6767 out_chan = 2;
6768 for (i = 0; i < 3; i++) {
6769 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6770 alu.op = ALU_OP1_RECIP_IEEE;
6771 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6772
6773 alu.dst.sel = ctx->temp_reg;
6774 alu.dst.chan = i;
6775 if (i == 2)
6776 alu.last = 1;
6777 if (out_chan == i)
6778 alu.dst.write = 1;
6779 r = r600_bytecode_add_alu(ctx->bc, &alu);
6780 if (r)
6781 return r;
6782 }
6783
6784 } else {
6785 out_chan = 3;
6786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6787 alu.op = ALU_OP1_RECIP_IEEE;
6788 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6789
6790 alu.dst.sel = ctx->temp_reg;
6791 alu.dst.chan = out_chan;
6792 alu.last = 1;
6793 alu.dst.write = 1;
6794 r = r600_bytecode_add_alu(ctx->bc, &alu);
6795 if (r)
6796 return r;
6797 }
6798
6799 for (i = 0; i < 3; i++) {
6800 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6801 alu.op = ALU_OP2_MUL;
6802 alu.src[0].sel = ctx->temp_reg;
6803 alu.src[0].chan = out_chan;
6804 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6805 alu.dst.sel = ctx->temp_reg;
6806 alu.dst.chan = i;
6807 alu.dst.write = 1;
6808 r = r600_bytecode_add_alu(ctx->bc, &alu);
6809 if (r)
6810 return r;
6811 }
6812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6813 alu.op = ALU_OP1_MOV;
6814 alu.src[0].sel = V_SQ_ALU_SRC_1;
6815 alu.src[0].chan = 0;
6816 alu.dst.sel = ctx->temp_reg;
6817 alu.dst.chan = 3;
6818 alu.last = 1;
6819 alu.dst.write = 1;
6820 r = r600_bytecode_add_alu(ctx->bc, &alu);
6821 if (r)
6822 return r;
6823 src_loaded = TRUE;
6824 src_gpr = ctx->temp_reg;
6825 }
6826
6827
6828 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6829 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6830 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6831 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6832 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
6833 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
6834
6835 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6836 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6837
6838 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6839 for (i = 0; i < 4; i++) {
6840 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6841 alu.op = ALU_OP2_CUBE;
6842 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6843 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6844 alu.dst.sel = ctx->temp_reg;
6845 alu.dst.chan = i;
6846 if (i == 3)
6847 alu.last = 1;
6848 alu.dst.write = 1;
6849 r = r600_bytecode_add_alu(ctx->bc, &alu);
6850 if (r)
6851 return r;
6852 }
6853
6854 /* tmp1.z = RCP_e(|tmp1.z|) */
6855 if (ctx->bc->chip_class == CAYMAN) {
6856 for (i = 0; i < 3; i++) {
6857 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6858 alu.op = ALU_OP1_RECIP_IEEE;
6859 alu.src[0].sel = ctx->temp_reg;
6860 alu.src[0].chan = 2;
6861 alu.src[0].abs = 1;
6862 alu.dst.sel = ctx->temp_reg;
6863 alu.dst.chan = i;
6864 if (i == 2)
6865 alu.dst.write = 1;
6866 if (i == 2)
6867 alu.last = 1;
6868 r = r600_bytecode_add_alu(ctx->bc, &alu);
6869 if (r)
6870 return r;
6871 }
6872 } else {
6873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6874 alu.op = ALU_OP1_RECIP_IEEE;
6875 alu.src[0].sel = ctx->temp_reg;
6876 alu.src[0].chan = 2;
6877 alu.src[0].abs = 1;
6878 alu.dst.sel = ctx->temp_reg;
6879 alu.dst.chan = 2;
6880 alu.dst.write = 1;
6881 alu.last = 1;
6882 r = r600_bytecode_add_alu(ctx->bc, &alu);
6883 if (r)
6884 return r;
6885 }
6886
6887 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6888 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6889 * muladd has no writemask, have to use another temp
6890 */
6891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6892 alu.op = ALU_OP3_MULADD;
6893 alu.is_op3 = 1;
6894
6895 alu.src[0].sel = ctx->temp_reg;
6896 alu.src[0].chan = 0;
6897 alu.src[1].sel = ctx->temp_reg;
6898 alu.src[1].chan = 2;
6899
6900 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6901 alu.src[2].chan = 0;
6902 alu.src[2].value = u_bitcast_f2u(1.5f);
6903
6904 alu.dst.sel = ctx->temp_reg;
6905 alu.dst.chan = 0;
6906 alu.dst.write = 1;
6907
6908 r = r600_bytecode_add_alu(ctx->bc, &alu);
6909 if (r)
6910 return r;
6911
6912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6913 alu.op = ALU_OP3_MULADD;
6914 alu.is_op3 = 1;
6915
6916 alu.src[0].sel = ctx->temp_reg;
6917 alu.src[0].chan = 1;
6918 alu.src[1].sel = ctx->temp_reg;
6919 alu.src[1].chan = 2;
6920
6921 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6922 alu.src[2].chan = 0;
6923 alu.src[2].value = u_bitcast_f2u(1.5f);
6924
6925 alu.dst.sel = ctx->temp_reg;
6926 alu.dst.chan = 1;
6927 alu.dst.write = 1;
6928
6929 alu.last = 1;
6930 r = r600_bytecode_add_alu(ctx->bc, &alu);
6931 if (r)
6932 return r;
6933 /* write initial compare value into Z component
6934 - W src 0 for shadow cube
6935 - X src 1 for shadow cube array */
6936 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6937 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6938 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6939 alu.op = ALU_OP1_MOV;
6940 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
6941 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
6942 else
6943 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6944 alu.dst.sel = ctx->temp_reg;
6945 alu.dst.chan = 2;
6946 alu.dst.write = 1;
6947 alu.last = 1;
6948 r = r600_bytecode_add_alu(ctx->bc, &alu);
6949 if (r)
6950 return r;
6951 }
6952
6953 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6954 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6955 if (ctx->bc->chip_class >= EVERGREEN) {
6956 int mytmp = r600_get_temp(ctx);
6957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6958 alu.op = ALU_OP1_MOV;
6959 alu.src[0].sel = ctx->temp_reg;
6960 alu.src[0].chan = 3;
6961 alu.dst.sel = mytmp;
6962 alu.dst.chan = 0;
6963 alu.dst.write = 1;
6964 alu.last = 1;
6965 r = r600_bytecode_add_alu(ctx->bc, &alu);
6966 if (r)
6967 return r;
6968
6969 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
6970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6971 alu.op = ALU_OP3_MULADD;
6972 alu.is_op3 = 1;
6973 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6974 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6975 alu.src[1].chan = 0;
6976 alu.src[1].value = u_bitcast_f2u(8.0f);
6977 alu.src[2].sel = mytmp;
6978 alu.src[2].chan = 0;
6979 alu.dst.sel = ctx->temp_reg;
6980 alu.dst.chan = 3;
6981 alu.dst.write = 1;
6982 alu.last = 1;
6983 r = r600_bytecode_add_alu(ctx->bc, &alu);
6984 if (r)
6985 return r;
6986 } else if (ctx->bc->chip_class < EVERGREEN) {
6987 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6988 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
6989 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6990 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6991 tex.src_gpr = r600_get_temp(ctx);
6992 tex.src_sel_x = 0;
6993 tex.src_sel_y = 0;
6994 tex.src_sel_z = 0;
6995 tex.src_sel_w = 0;
6996 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
6997 tex.coord_type_x = 1;
6998 tex.coord_type_y = 1;
6999 tex.coord_type_z = 1;
7000 tex.coord_type_w = 1;
7001 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7002 alu.op = ALU_OP1_MOV;
7003 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7004 alu.dst.sel = tex.src_gpr;
7005 alu.dst.chan = 0;
7006 alu.last = 1;
7007 alu.dst.write = 1;
7008 r = r600_bytecode_add_alu(ctx->bc, &alu);
7009 if (r)
7010 return r;
7011
7012 r = r600_bytecode_add_tex(ctx->bc, &tex);
7013 if (r)
7014 return r;
7015 }
7016
7017 }
7018
7019 /* for cube forms of lod and bias we need to route things */
7020 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7021 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7022 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7023 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7025 alu.op = ALU_OP1_MOV;
7026 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7027 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7028 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7029 else
7030 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7031 alu.dst.sel = ctx->temp_reg;
7032 alu.dst.chan = 2;
7033 alu.last = 1;
7034 alu.dst.write = 1;
7035 r = r600_bytecode_add_alu(ctx->bc, &alu);
7036 if (r)
7037 return r;
7038 }
7039
7040 src_loaded = TRUE;
7041 src_gpr = ctx->temp_reg;
7042 }
7043
7044 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7045 int temp_h = 0, temp_v = 0;
7046 int start_val = 0;
7047
7048 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7049 if (src_loaded == TRUE)
7050 start_val = 1;
7051 else
7052 src_loaded = TRUE;
7053 for (i = start_val; i < 3; i++) {
7054 int treg = r600_get_temp(ctx);
7055
7056 if (i == 0)
7057 src_gpr = treg;
7058 else if (i == 1)
7059 temp_h = treg;
7060 else
7061 temp_v = treg;
7062
7063 for (j = 0; j < 4; j++) {
7064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7065 alu.op = ALU_OP1_MOV;
7066 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7067 alu.dst.sel = treg;
7068 alu.dst.chan = j;
7069 if (j == 3)
7070 alu.last = 1;
7071 alu.dst.write = 1;
7072 r = r600_bytecode_add_alu(ctx->bc, &alu);
7073 if (r)
7074 return r;
7075 }
7076 }
7077 for (i = 1; i < 3; i++) {
7078 /* set gradients h/v */
7079 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7080 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7081 FETCH_OP_SET_GRADIENTS_V;
7082 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7083 tex.sampler_index_mode = sampler_index_mode;
7084 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7085 tex.resource_index_mode = sampler_index_mode;
7086
7087 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7088 tex.src_sel_x = 0;
7089 tex.src_sel_y = 1;
7090 tex.src_sel_z = 2;
7091 tex.src_sel_w = 3;
7092
7093 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7094 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7095 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7096 tex.coord_type_x = 1;
7097 tex.coord_type_y = 1;
7098 tex.coord_type_z = 1;
7099 tex.coord_type_w = 1;
7100 }
7101 r = r600_bytecode_add_tex(ctx->bc, &tex);
7102 if (r)
7103 return r;
7104 }
7105 }
7106
7107 if (src_requires_loading && !src_loaded) {
7108 for (i = 0; i < 4; i++) {
7109 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7110 alu.op = ALU_OP1_MOV;
7111 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7112 alu.dst.sel = ctx->temp_reg;
7113 alu.dst.chan = i;
7114 if (i == 3)
7115 alu.last = 1;
7116 alu.dst.write = 1;
7117 r = r600_bytecode_add_alu(ctx->bc, &alu);
7118 if (r)
7119 return r;
7120 }
7121 src_loaded = TRUE;
7122 src_gpr = ctx->temp_reg;
7123 }
7124
7125 /* get offset values */
7126 if (inst->Texture.NumOffsets) {
7127 assert(inst->Texture.NumOffsets == 1);
7128
7129 /* The texture offset feature doesn't work with the TXF instruction
7130 * and must be emulated by adding the offset to the texture coordinates. */
7131 if (txf_add_offsets) {
7132 const struct tgsi_texture_offset *off = inst->TexOffsets;
7133
7134 switch (inst->Texture.Texture) {
7135 case TGSI_TEXTURE_3D:
7136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7137 alu.op = ALU_OP2_ADD_INT;
7138 alu.src[0].sel = src_gpr;
7139 alu.src[0].chan = 2;
7140 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7141 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7142 alu.dst.sel = src_gpr;
7143 alu.dst.chan = 2;
7144 alu.dst.write = 1;
7145 alu.last = 1;
7146 r = r600_bytecode_add_alu(ctx->bc, &alu);
7147 if (r)
7148 return r;
7149 /* fall through */
7150
7151 case TGSI_TEXTURE_2D:
7152 case TGSI_TEXTURE_SHADOW2D:
7153 case TGSI_TEXTURE_RECT:
7154 case TGSI_TEXTURE_SHADOWRECT:
7155 case TGSI_TEXTURE_2D_ARRAY:
7156 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7158 alu.op = ALU_OP2_ADD_INT;
7159 alu.src[0].sel = src_gpr;
7160 alu.src[0].chan = 1;
7161 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7162 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7163 alu.dst.sel = src_gpr;
7164 alu.dst.chan = 1;
7165 alu.dst.write = 1;
7166 alu.last = 1;
7167 r = r600_bytecode_add_alu(ctx->bc, &alu);
7168 if (r)
7169 return r;
7170 /* fall through */
7171
7172 case TGSI_TEXTURE_1D:
7173 case TGSI_TEXTURE_SHADOW1D:
7174 case TGSI_TEXTURE_1D_ARRAY:
7175 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7176 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7177 alu.op = ALU_OP2_ADD_INT;
7178 alu.src[0].sel = src_gpr;
7179 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7180 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7181 alu.dst.sel = src_gpr;
7182 alu.dst.write = 1;
7183 alu.last = 1;
7184 r = r600_bytecode_add_alu(ctx->bc, &alu);
7185 if (r)
7186 return r;
7187 break;
7188 /* texture offsets do not apply to other texture targets */
7189 }
7190 } else {
7191 switch (inst->Texture.Texture) {
7192 case TGSI_TEXTURE_3D:
7193 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7194 /* fallthrough */
7195 case TGSI_TEXTURE_2D:
7196 case TGSI_TEXTURE_SHADOW2D:
7197 case TGSI_TEXTURE_RECT:
7198 case TGSI_TEXTURE_SHADOWRECT:
7199 case TGSI_TEXTURE_2D_ARRAY:
7200 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7201 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7202 /* fallthrough */
7203 case TGSI_TEXTURE_1D:
7204 case TGSI_TEXTURE_SHADOW1D:
7205 case TGSI_TEXTURE_1D_ARRAY:
7206 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7207 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7208 }
7209 }
7210 }
7211
7212 /* Obtain the sample index for reading a compressed MSAA color texture.
7213 * To read the FMASK, we use the ldfptr instruction, which tells us
7214 * where the samples are stored.
7215 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7216 * which is the identity mapping. Each nibble says which physical sample
7217 * should be fetched to get that sample.
7218 *
7219 * Assume src.z contains the sample index. It should be modified like this:
7220 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7221 * Then fetch the texel with src.
7222 */
7223 if (read_compressed_msaa) {
7224 unsigned sample_chan = 3;
7225 unsigned temp = r600_get_temp(ctx);
7226 assert(src_loaded);
7227
7228 /* temp.w = ldfptr() */
7229 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7230 tex.op = FETCH_OP_LD;
7231 tex.inst_mod = 1; /* to indicate this is ldfptr */
7232 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7233 tex.sampler_index_mode = sampler_index_mode;
7234 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7235 tex.resource_index_mode = sampler_index_mode;
7236 tex.src_gpr = src_gpr;
7237 tex.dst_gpr = temp;
7238 tex.dst_sel_x = 7; /* mask out these components */
7239 tex.dst_sel_y = 7;
7240 tex.dst_sel_z = 7;
7241 tex.dst_sel_w = 0; /* store X */
7242 tex.src_sel_x = 0;
7243 tex.src_sel_y = 1;
7244 tex.src_sel_z = 2;
7245 tex.src_sel_w = 3;
7246 tex.offset_x = offset_x;
7247 tex.offset_y = offset_y;
7248 tex.offset_z = offset_z;
7249 r = r600_bytecode_add_tex(ctx->bc, &tex);
7250 if (r)
7251 return r;
7252
7253 /* temp.x = sample_index*4 */
7254 if (ctx->bc->chip_class == CAYMAN) {
7255 for (i = 0 ; i < 4; i++) {
7256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7257 alu.op = ALU_OP2_MULLO_INT;
7258 alu.src[0].sel = src_gpr;
7259 alu.src[0].chan = sample_chan;
7260 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7261 alu.src[1].value = 4;
7262 alu.dst.sel = temp;
7263 alu.dst.chan = i;
7264 alu.dst.write = i == 0;
7265 if (i == 3)
7266 alu.last = 1;
7267 r = r600_bytecode_add_alu(ctx->bc, &alu);
7268 if (r)
7269 return r;
7270 }
7271 } else {
7272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7273 alu.op = ALU_OP2_MULLO_INT;
7274 alu.src[0].sel = src_gpr;
7275 alu.src[0].chan = sample_chan;
7276 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7277 alu.src[1].value = 4;
7278 alu.dst.sel = temp;
7279 alu.dst.chan = 0;
7280 alu.dst.write = 1;
7281 alu.last = 1;
7282 r = r600_bytecode_add_alu(ctx->bc, &alu);
7283 if (r)
7284 return r;
7285 }
7286
7287 /* sample_index = temp.w >> temp.x */
7288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7289 alu.op = ALU_OP2_LSHR_INT;
7290 alu.src[0].sel = temp;
7291 alu.src[0].chan = 3;
7292 alu.src[1].sel = temp;
7293 alu.src[1].chan = 0;
7294 alu.dst.sel = src_gpr;
7295 alu.dst.chan = sample_chan;
7296 alu.dst.write = 1;
7297 alu.last = 1;
7298 r = r600_bytecode_add_alu(ctx->bc, &alu);
7299 if (r)
7300 return r;
7301
7302 /* sample_index & 0xF */
7303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7304 alu.op = ALU_OP2_AND_INT;
7305 alu.src[0].sel = src_gpr;
7306 alu.src[0].chan = sample_chan;
7307 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7308 alu.src[1].value = 0xF;
7309 alu.dst.sel = src_gpr;
7310 alu.dst.chan = sample_chan;
7311 alu.dst.write = 1;
7312 alu.last = 1;
7313 r = r600_bytecode_add_alu(ctx->bc, &alu);
7314 if (r)
7315 return r;
7316 #if 0
7317 /* visualize the FMASK */
7318 for (i = 0; i < 4; i++) {
7319 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7320 alu.op = ALU_OP1_INT_TO_FLT;
7321 alu.src[0].sel = src_gpr;
7322 alu.src[0].chan = sample_chan;
7323 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7324 alu.dst.chan = i;
7325 alu.dst.write = 1;
7326 alu.last = 1;
7327 r = r600_bytecode_add_alu(ctx->bc, &alu);
7328 if (r)
7329 return r;
7330 }
7331 return 0;
7332 #endif
7333 }
7334
7335 /* does this shader want a num layers from TXQ for a cube array? */
7336 if (has_txq_cube_array_z) {
7337 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7338
7339 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7340 alu.op = ALU_OP1_MOV;
7341
7342 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7343 if (ctx->bc->chip_class >= EVERGREEN) {
7344 /* channel 1 or 3 of each word */
7345 alu.src[0].sel += (id / 2);
7346 alu.src[0].chan = ((id % 2) * 2) + 1;
7347 } else {
7348 /* r600 we have them at channel 2 of the second dword */
7349 alu.src[0].sel += (id * 2) + 1;
7350 alu.src[0].chan = 2;
7351 }
7352 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7353 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7354 alu.last = 1;
7355 r = r600_bytecode_add_alu(ctx->bc, &alu);
7356 if (r)
7357 return r;
7358 /* disable writemask from texture instruction */
7359 inst->Dst[0].Register.WriteMask &= ~4;
7360 }
7361
7362 opcode = ctx->inst_info->op;
7363 if (opcode == FETCH_OP_GATHER4 &&
7364 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7365 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7366 opcode = FETCH_OP_GATHER4_O;
7367
7368 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7369 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7370 encoded in the instruction are ignored. */
7371 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7372 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7373 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7374 tex.sampler_index_mode = sampler_index_mode;
7375 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7376 tex.resource_index_mode = sampler_index_mode;
7377
7378 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7379 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7380 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7381 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7382 tex.src_sel_w = 4;
7383
7384 tex.dst_sel_x = 7;
7385 tex.dst_sel_y = 7;
7386 tex.dst_sel_z = 7;
7387 tex.dst_sel_w = 7;
7388
7389 r = r600_bytecode_add_tex(ctx->bc, &tex);
7390 if (r)
7391 return r;
7392 }
7393
7394 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7395 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7396 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7397 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7398 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7399 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7400 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7401 switch (opcode) {
7402 case FETCH_OP_SAMPLE:
7403 opcode = FETCH_OP_SAMPLE_C;
7404 break;
7405 case FETCH_OP_SAMPLE_L:
7406 opcode = FETCH_OP_SAMPLE_C_L;
7407 break;
7408 case FETCH_OP_SAMPLE_LB:
7409 opcode = FETCH_OP_SAMPLE_C_LB;
7410 break;
7411 case FETCH_OP_SAMPLE_G:
7412 opcode = FETCH_OP_SAMPLE_C_G;
7413 break;
7414 /* Texture gather variants */
7415 case FETCH_OP_GATHER4:
7416 opcode = FETCH_OP_GATHER4_C;
7417 break;
7418 case FETCH_OP_GATHER4_O:
7419 opcode = FETCH_OP_GATHER4_C_O;
7420 break;
7421 }
7422 }
7423
7424 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7425 tex.op = opcode;
7426
7427 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7428 tex.sampler_index_mode = sampler_index_mode;
7429 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7430 tex.resource_index_mode = sampler_index_mode;
7431 tex.src_gpr = src_gpr;
7432 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7433
7434 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7435 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7436 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7437 }
7438
7439 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7440 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7441 tex.inst_mod = texture_component_select;
7442
7443 if (ctx->bc->chip_class == CAYMAN) {
7444 /* GATHER4 result order is different from TGSI TG4 */
7445 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7446 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7447 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7448 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7449 } else {
7450 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7451 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7452 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7453 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7454 }
7455 }
7456 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7457 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7458 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7459 tex.dst_sel_z = 7;
7460 tex.dst_sel_w = 7;
7461 }
7462 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7463 tex.dst_sel_x = 3;
7464 tex.dst_sel_y = 7;
7465 tex.dst_sel_z = 7;
7466 tex.dst_sel_w = 7;
7467 }
7468 else {
7469 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7470 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7471 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7472 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7473 }
7474
7475
7476 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
7477 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7478 tex.src_sel_x = 4;
7479 tex.src_sel_y = 4;
7480 tex.src_sel_z = 4;
7481 tex.src_sel_w = 4;
7482 } else if (src_loaded) {
7483 tex.src_sel_x = 0;
7484 tex.src_sel_y = 1;
7485 tex.src_sel_z = 2;
7486 tex.src_sel_w = 3;
7487 } else {
7488 tex.src_sel_x = ctx->src[0].swizzle[0];
7489 tex.src_sel_y = ctx->src[0].swizzle[1];
7490 tex.src_sel_z = ctx->src[0].swizzle[2];
7491 tex.src_sel_w = ctx->src[0].swizzle[3];
7492 tex.src_rel = ctx->src[0].rel;
7493 }
7494
7495 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7496 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7497 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7498 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7499 tex.src_sel_x = 1;
7500 tex.src_sel_y = 0;
7501 tex.src_sel_z = 3;
7502 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7503 }
7504
7505 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7506 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7507 tex.coord_type_x = 1;
7508 tex.coord_type_y = 1;
7509 }
7510 tex.coord_type_z = 1;
7511 tex.coord_type_w = 1;
7512
7513 tex.offset_x = offset_x;
7514 tex.offset_y = offset_y;
7515 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7516 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7517 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7518 tex.offset_z = 0;
7519 }
7520 else {
7521 tex.offset_z = offset_z;
7522 }
7523
7524 /* Put the depth for comparison in W.
7525 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7526 * Some instructions expect the depth in Z. */
7527 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7528 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7529 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7530 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7531 opcode != FETCH_OP_SAMPLE_C_L &&
7532 opcode != FETCH_OP_SAMPLE_C_LB) {
7533 tex.src_sel_w = tex.src_sel_z;
7534 }
7535
7536 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7537 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7538 if (opcode == FETCH_OP_SAMPLE_C_L ||
7539 opcode == FETCH_OP_SAMPLE_C_LB) {
7540 /* the array index is read from Y */
7541 tex.coord_type_y = 0;
7542 } else {
7543 /* the array index is read from Z */
7544 tex.coord_type_z = 0;
7545 tex.src_sel_z = tex.src_sel_y;
7546 }
7547 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7548 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7549 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7550 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7551 (ctx->bc->chip_class >= EVERGREEN)))
7552 /* the array index is read from Z */
7553 tex.coord_type_z = 0;
7554
7555 /* mask unused source components */
7556 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7557 switch (inst->Texture.Texture) {
7558 case TGSI_TEXTURE_2D:
7559 case TGSI_TEXTURE_RECT:
7560 tex.src_sel_z = 7;
7561 tex.src_sel_w = 7;
7562 break;
7563 case TGSI_TEXTURE_1D_ARRAY:
7564 tex.src_sel_y = 7;
7565 tex.src_sel_w = 7;
7566 break;
7567 case TGSI_TEXTURE_1D:
7568 tex.src_sel_y = 7;
7569 tex.src_sel_z = 7;
7570 tex.src_sel_w = 7;
7571 break;
7572 }
7573 }
7574
7575 r = r600_bytecode_add_tex(ctx->bc, &tex);
7576 if (r)
7577 return r;
7578
7579 /* add shadow ambient support - gallium doesn't do it yet */
7580 return 0;
7581 }
7582
7583 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7584 {
7585 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7586 struct r600_bytecode_alu alu;
7587 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7588 unsigned i, temp_regs[2];
7589 int r;
7590
7591 /* optimize if it's just an equal balance */
7592 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7593 for (i = 0; i < lasti + 1; i++) {
7594 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7595 continue;
7596
7597 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7598 alu.op = ALU_OP2_ADD;
7599 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7600 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7601 alu.omod = 3;
7602 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7603 alu.dst.chan = i;
7604 if (i == lasti) {
7605 alu.last = 1;
7606 }
7607 r = r600_bytecode_add_alu(ctx->bc, &alu);
7608 if (r)
7609 return r;
7610 }
7611 return 0;
7612 }
7613
7614 /* 1 - src0 */
7615 for (i = 0; i < lasti + 1; i++) {
7616 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7617 continue;
7618
7619 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7620 alu.op = ALU_OP2_ADD;
7621 alu.src[0].sel = V_SQ_ALU_SRC_1;
7622 alu.src[0].chan = 0;
7623 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7624 r600_bytecode_src_toggle_neg(&alu.src[1]);
7625 alu.dst.sel = ctx->temp_reg;
7626 alu.dst.chan = i;
7627 if (i == lasti) {
7628 alu.last = 1;
7629 }
7630 alu.dst.write = 1;
7631 r = r600_bytecode_add_alu(ctx->bc, &alu);
7632 if (r)
7633 return r;
7634 }
7635
7636 /* (1 - src0) * src2 */
7637 for (i = 0; i < lasti + 1; i++) {
7638 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7639 continue;
7640
7641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7642 alu.op = ALU_OP2_MUL;
7643 alu.src[0].sel = ctx->temp_reg;
7644 alu.src[0].chan = i;
7645 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7646 alu.dst.sel = ctx->temp_reg;
7647 alu.dst.chan = i;
7648 if (i == lasti) {
7649 alu.last = 1;
7650 }
7651 alu.dst.write = 1;
7652 r = r600_bytecode_add_alu(ctx->bc, &alu);
7653 if (r)
7654 return r;
7655 }
7656
7657 /* src0 * src1 + (1 - src0) * src2 */
7658 if (ctx->src[0].abs)
7659 temp_regs[0] = r600_get_temp(ctx);
7660 else
7661 temp_regs[0] = 0;
7662 if (ctx->src[1].abs)
7663 temp_regs[1] = r600_get_temp(ctx);
7664 else
7665 temp_regs[1] = 0;
7666
7667 for (i = 0; i < lasti + 1; i++) {
7668 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7669 continue;
7670
7671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7672 alu.op = ALU_OP3_MULADD;
7673 alu.is_op3 = 1;
7674 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7675 if (r)
7676 return r;
7677 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7678 if (r)
7679 return r;
7680 alu.src[2].sel = ctx->temp_reg;
7681 alu.src[2].chan = i;
7682
7683 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7684 alu.dst.chan = i;
7685 if (i == lasti) {
7686 alu.last = 1;
7687 }
7688 r = r600_bytecode_add_alu(ctx->bc, &alu);
7689 if (r)
7690 return r;
7691 }
7692 return 0;
7693 }
7694
7695 static int tgsi_cmp(struct r600_shader_ctx *ctx)
7696 {
7697 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7698 struct r600_bytecode_alu alu;
7699 int i, r, j;
7700 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7701 int temp_regs[3];
7702 unsigned op;
7703
7704 if (ctx->src[0].abs && ctx->src[0].neg) {
7705 op = ALU_OP3_CNDE;
7706 ctx->src[0].abs = 0;
7707 ctx->src[0].neg = 0;
7708 } else {
7709 op = ALU_OP3_CNDGE;
7710 }
7711
7712 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7713 temp_regs[j] = 0;
7714 if (ctx->src[j].abs)
7715 temp_regs[j] = r600_get_temp(ctx);
7716 }
7717
7718 for (i = 0; i < lasti + 1; i++) {
7719 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7720 continue;
7721
7722 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7723 alu.op = op;
7724 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7725 if (r)
7726 return r;
7727 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
7728 if (r)
7729 return r;
7730 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
7731 if (r)
7732 return r;
7733 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7734 alu.dst.chan = i;
7735 alu.dst.write = 1;
7736 alu.is_op3 = 1;
7737 if (i == lasti)
7738 alu.last = 1;
7739 r = r600_bytecode_add_alu(ctx->bc, &alu);
7740 if (r)
7741 return r;
7742 }
7743 return 0;
7744 }
7745
7746 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
7747 {
7748 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7749 struct r600_bytecode_alu alu;
7750 int i, r;
7751 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7752
7753 for (i = 0; i < lasti + 1; i++) {
7754 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7755 continue;
7756
7757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7758 alu.op = ALU_OP3_CNDE_INT;
7759 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7760 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7761 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
7762 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7763 alu.dst.chan = i;
7764 alu.dst.write = 1;
7765 alu.is_op3 = 1;
7766 if (i == lasti)
7767 alu.last = 1;
7768 r = r600_bytecode_add_alu(ctx->bc, &alu);
7769 if (r)
7770 return r;
7771 }
7772 return 0;
7773 }
7774
7775 static int tgsi_xpd(struct r600_shader_ctx *ctx)
7776 {
7777 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7778 static const unsigned int src0_swizzle[] = {2, 0, 1};
7779 static const unsigned int src1_swizzle[] = {1, 2, 0};
7780 struct r600_bytecode_alu alu;
7781 uint32_t use_temp = 0;
7782 int i, r;
7783
7784 if (inst->Dst[0].Register.WriteMask != 0xf)
7785 use_temp = 1;
7786
7787 for (i = 0; i < 4; i++) {
7788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7789 alu.op = ALU_OP2_MUL;
7790 if (i < 3) {
7791 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7792 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
7793 } else {
7794 alu.src[0].sel = V_SQ_ALU_SRC_0;
7795 alu.src[0].chan = i;
7796 alu.src[1].sel = V_SQ_ALU_SRC_0;
7797 alu.src[1].chan = i;
7798 }
7799
7800 alu.dst.sel = ctx->temp_reg;
7801 alu.dst.chan = i;
7802 alu.dst.write = 1;
7803
7804 if (i == 3)
7805 alu.last = 1;
7806 r = r600_bytecode_add_alu(ctx->bc, &alu);
7807 if (r)
7808 return r;
7809 }
7810
7811 for (i = 0; i < 4; i++) {
7812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7813 alu.op = ALU_OP3_MULADD;
7814
7815 if (i < 3) {
7816 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
7817 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
7818 } else {
7819 alu.src[0].sel = V_SQ_ALU_SRC_0;
7820 alu.src[0].chan = i;
7821 alu.src[1].sel = V_SQ_ALU_SRC_0;
7822 alu.src[1].chan = i;
7823 }
7824
7825 alu.src[2].sel = ctx->temp_reg;
7826 alu.src[2].neg = 1;
7827 alu.src[2].chan = i;
7828
7829 if (use_temp)
7830 alu.dst.sel = ctx->temp_reg;
7831 else
7832 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7833 alu.dst.chan = i;
7834 alu.dst.write = 1;
7835 alu.is_op3 = 1;
7836 if (i == 3)
7837 alu.last = 1;
7838 r = r600_bytecode_add_alu(ctx->bc, &alu);
7839 if (r)
7840 return r;
7841 }
7842 if (use_temp)
7843 return tgsi_helper_copy(ctx, inst);
7844 return 0;
7845 }
7846
7847 static int tgsi_exp(struct r600_shader_ctx *ctx)
7848 {
7849 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7850 struct r600_bytecode_alu alu;
7851 int r;
7852 unsigned i;
7853
7854 /* result.x = 2^floor(src); */
7855 if (inst->Dst[0].Register.WriteMask & 1) {
7856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7857
7858 alu.op = ALU_OP1_FLOOR;
7859 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7860
7861 alu.dst.sel = ctx->temp_reg;
7862 alu.dst.chan = 0;
7863 alu.dst.write = 1;
7864 alu.last = 1;
7865 r = r600_bytecode_add_alu(ctx->bc, &alu);
7866 if (r)
7867 return r;
7868
7869 if (ctx->bc->chip_class == CAYMAN) {
7870 for (i = 0; i < 3; i++) {
7871 alu.op = ALU_OP1_EXP_IEEE;
7872 alu.src[0].sel = ctx->temp_reg;
7873 alu.src[0].chan = 0;
7874
7875 alu.dst.sel = ctx->temp_reg;
7876 alu.dst.chan = i;
7877 alu.dst.write = i == 0;
7878 alu.last = i == 2;
7879 r = r600_bytecode_add_alu(ctx->bc, &alu);
7880 if (r)
7881 return r;
7882 }
7883 } else {
7884 alu.op = ALU_OP1_EXP_IEEE;
7885 alu.src[0].sel = ctx->temp_reg;
7886 alu.src[0].chan = 0;
7887
7888 alu.dst.sel = ctx->temp_reg;
7889 alu.dst.chan = 0;
7890 alu.dst.write = 1;
7891 alu.last = 1;
7892 r = r600_bytecode_add_alu(ctx->bc, &alu);
7893 if (r)
7894 return r;
7895 }
7896 }
7897
7898 /* result.y = tmp - floor(tmp); */
7899 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7901
7902 alu.op = ALU_OP1_FRACT;
7903 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7904
7905 alu.dst.sel = ctx->temp_reg;
7906 #if 0
7907 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7908 if (r)
7909 return r;
7910 #endif
7911 alu.dst.write = 1;
7912 alu.dst.chan = 1;
7913
7914 alu.last = 1;
7915
7916 r = r600_bytecode_add_alu(ctx->bc, &alu);
7917 if (r)
7918 return r;
7919 }
7920
7921 /* result.z = RoughApprox2ToX(tmp);*/
7922 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
7923 if (ctx->bc->chip_class == CAYMAN) {
7924 for (i = 0; i < 3; i++) {
7925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7926 alu.op = ALU_OP1_EXP_IEEE;
7927 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7928
7929 alu.dst.sel = ctx->temp_reg;
7930 alu.dst.chan = i;
7931 if (i == 2) {
7932 alu.dst.write = 1;
7933 alu.last = 1;
7934 }
7935
7936 r = r600_bytecode_add_alu(ctx->bc, &alu);
7937 if (r)
7938 return r;
7939 }
7940 } else {
7941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7942 alu.op = ALU_OP1_EXP_IEEE;
7943 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7944
7945 alu.dst.sel = ctx->temp_reg;
7946 alu.dst.write = 1;
7947 alu.dst.chan = 2;
7948
7949 alu.last = 1;
7950
7951 r = r600_bytecode_add_alu(ctx->bc, &alu);
7952 if (r)
7953 return r;
7954 }
7955 }
7956
7957 /* result.w = 1.0;*/
7958 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
7959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7960
7961 alu.op = ALU_OP1_MOV;
7962 alu.src[0].sel = V_SQ_ALU_SRC_1;
7963 alu.src[0].chan = 0;
7964
7965 alu.dst.sel = ctx->temp_reg;
7966 alu.dst.chan = 3;
7967 alu.dst.write = 1;
7968 alu.last = 1;
7969 r = r600_bytecode_add_alu(ctx->bc, &alu);
7970 if (r)
7971 return r;
7972 }
7973 return tgsi_helper_copy(ctx, inst);
7974 }
7975
7976 static int tgsi_log(struct r600_shader_ctx *ctx)
7977 {
7978 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7979 struct r600_bytecode_alu alu;
7980 int r;
7981 unsigned i;
7982
7983 /* result.x = floor(log2(|src|)); */
7984 if (inst->Dst[0].Register.WriteMask & 1) {
7985 if (ctx->bc->chip_class == CAYMAN) {
7986 for (i = 0; i < 3; i++) {
7987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7988
7989 alu.op = ALU_OP1_LOG_IEEE;
7990 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7991 r600_bytecode_src_set_abs(&alu.src[0]);
7992
7993 alu.dst.sel = ctx->temp_reg;
7994 alu.dst.chan = i;
7995 if (i == 0)
7996 alu.dst.write = 1;
7997 if (i == 2)
7998 alu.last = 1;
7999 r = r600_bytecode_add_alu(ctx->bc, &alu);
8000 if (r)
8001 return r;
8002 }
8003
8004 } else {
8005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8006
8007 alu.op = ALU_OP1_LOG_IEEE;
8008 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8009 r600_bytecode_src_set_abs(&alu.src[0]);
8010
8011 alu.dst.sel = ctx->temp_reg;
8012 alu.dst.chan = 0;
8013 alu.dst.write = 1;
8014 alu.last = 1;
8015 r = r600_bytecode_add_alu(ctx->bc, &alu);
8016 if (r)
8017 return r;
8018 }
8019
8020 alu.op = ALU_OP1_FLOOR;
8021 alu.src[0].sel = ctx->temp_reg;
8022 alu.src[0].chan = 0;
8023
8024 alu.dst.sel = ctx->temp_reg;
8025 alu.dst.chan = 0;
8026 alu.dst.write = 1;
8027 alu.last = 1;
8028
8029 r = r600_bytecode_add_alu(ctx->bc, &alu);
8030 if (r)
8031 return r;
8032 }
8033
8034 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8035 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8036
8037 if (ctx->bc->chip_class == CAYMAN) {
8038 for (i = 0; i < 3; i++) {
8039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8040
8041 alu.op = ALU_OP1_LOG_IEEE;
8042 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8043 r600_bytecode_src_set_abs(&alu.src[0]);
8044
8045 alu.dst.sel = ctx->temp_reg;
8046 alu.dst.chan = i;
8047 if (i == 1)
8048 alu.dst.write = 1;
8049 if (i == 2)
8050 alu.last = 1;
8051
8052 r = r600_bytecode_add_alu(ctx->bc, &alu);
8053 if (r)
8054 return r;
8055 }
8056 } else {
8057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8058
8059 alu.op = ALU_OP1_LOG_IEEE;
8060 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8061 r600_bytecode_src_set_abs(&alu.src[0]);
8062
8063 alu.dst.sel = ctx->temp_reg;
8064 alu.dst.chan = 1;
8065 alu.dst.write = 1;
8066 alu.last = 1;
8067
8068 r = r600_bytecode_add_alu(ctx->bc, &alu);
8069 if (r)
8070 return r;
8071 }
8072
8073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8074
8075 alu.op = ALU_OP1_FLOOR;
8076 alu.src[0].sel = ctx->temp_reg;
8077 alu.src[0].chan = 1;
8078
8079 alu.dst.sel = ctx->temp_reg;
8080 alu.dst.chan = 1;
8081 alu.dst.write = 1;
8082 alu.last = 1;
8083
8084 r = r600_bytecode_add_alu(ctx->bc, &alu);
8085 if (r)
8086 return r;
8087
8088 if (ctx->bc->chip_class == CAYMAN) {
8089 for (i = 0; i < 3; i++) {
8090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8091 alu.op = ALU_OP1_EXP_IEEE;
8092 alu.src[0].sel = ctx->temp_reg;
8093 alu.src[0].chan = 1;
8094
8095 alu.dst.sel = ctx->temp_reg;
8096 alu.dst.chan = i;
8097 if (i == 1)
8098 alu.dst.write = 1;
8099 if (i == 2)
8100 alu.last = 1;
8101
8102 r = r600_bytecode_add_alu(ctx->bc, &alu);
8103 if (r)
8104 return r;
8105 }
8106 } else {
8107 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8108 alu.op = ALU_OP1_EXP_IEEE;
8109 alu.src[0].sel = ctx->temp_reg;
8110 alu.src[0].chan = 1;
8111
8112 alu.dst.sel = ctx->temp_reg;
8113 alu.dst.chan = 1;
8114 alu.dst.write = 1;
8115 alu.last = 1;
8116
8117 r = r600_bytecode_add_alu(ctx->bc, &alu);
8118 if (r)
8119 return r;
8120 }
8121
8122 if (ctx->bc->chip_class == CAYMAN) {
8123 for (i = 0; i < 3; i++) {
8124 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8125 alu.op = ALU_OP1_RECIP_IEEE;
8126 alu.src[0].sel = ctx->temp_reg;
8127 alu.src[0].chan = 1;
8128
8129 alu.dst.sel = ctx->temp_reg;
8130 alu.dst.chan = i;
8131 if (i == 1)
8132 alu.dst.write = 1;
8133 if (i == 2)
8134 alu.last = 1;
8135
8136 r = r600_bytecode_add_alu(ctx->bc, &alu);
8137 if (r)
8138 return r;
8139 }
8140 } else {
8141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8142 alu.op = ALU_OP1_RECIP_IEEE;
8143 alu.src[0].sel = ctx->temp_reg;
8144 alu.src[0].chan = 1;
8145
8146 alu.dst.sel = ctx->temp_reg;
8147 alu.dst.chan = 1;
8148 alu.dst.write = 1;
8149 alu.last = 1;
8150
8151 r = r600_bytecode_add_alu(ctx->bc, &alu);
8152 if (r)
8153 return r;
8154 }
8155
8156 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8157
8158 alu.op = ALU_OP2_MUL;
8159
8160 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8161 r600_bytecode_src_set_abs(&alu.src[0]);
8162
8163 alu.src[1].sel = ctx->temp_reg;
8164 alu.src[1].chan = 1;
8165
8166 alu.dst.sel = ctx->temp_reg;
8167 alu.dst.chan = 1;
8168 alu.dst.write = 1;
8169 alu.last = 1;
8170
8171 r = r600_bytecode_add_alu(ctx->bc, &alu);
8172 if (r)
8173 return r;
8174 }
8175
8176 /* result.z = log2(|src|);*/
8177 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8178 if (ctx->bc->chip_class == CAYMAN) {
8179 for (i = 0; i < 3; i++) {
8180 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8181
8182 alu.op = ALU_OP1_LOG_IEEE;
8183 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8184 r600_bytecode_src_set_abs(&alu.src[0]);
8185
8186 alu.dst.sel = ctx->temp_reg;
8187 if (i == 2)
8188 alu.dst.write = 1;
8189 alu.dst.chan = i;
8190 if (i == 2)
8191 alu.last = 1;
8192
8193 r = r600_bytecode_add_alu(ctx->bc, &alu);
8194 if (r)
8195 return r;
8196 }
8197 } else {
8198 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8199
8200 alu.op = ALU_OP1_LOG_IEEE;
8201 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8202 r600_bytecode_src_set_abs(&alu.src[0]);
8203
8204 alu.dst.sel = ctx->temp_reg;
8205 alu.dst.write = 1;
8206 alu.dst.chan = 2;
8207 alu.last = 1;
8208
8209 r = r600_bytecode_add_alu(ctx->bc, &alu);
8210 if (r)
8211 return r;
8212 }
8213 }
8214
8215 /* result.w = 1.0; */
8216 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8218
8219 alu.op = ALU_OP1_MOV;
8220 alu.src[0].sel = V_SQ_ALU_SRC_1;
8221 alu.src[0].chan = 0;
8222
8223 alu.dst.sel = ctx->temp_reg;
8224 alu.dst.chan = 3;
8225 alu.dst.write = 1;
8226 alu.last = 1;
8227
8228 r = r600_bytecode_add_alu(ctx->bc, &alu);
8229 if (r)
8230 return r;
8231 }
8232
8233 return tgsi_helper_copy(ctx, inst);
8234 }
8235
8236 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8237 {
8238 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8239 struct r600_bytecode_alu alu;
8240 int r;
8241 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8242 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8243
8244 assert(inst->Dst[0].Register.Index < 3);
8245 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8246
8247 switch (inst->Instruction.Opcode) {
8248 case TGSI_OPCODE_ARL:
8249 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8250 break;
8251 case TGSI_OPCODE_ARR:
8252 alu.op = ALU_OP1_FLT_TO_INT;
8253 break;
8254 case TGSI_OPCODE_UARL:
8255 alu.op = ALU_OP1_MOV;
8256 break;
8257 default:
8258 assert(0);
8259 return -1;
8260 }
8261
8262 for (i = 0; i <= lasti; ++i) {
8263 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8264 continue;
8265 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8266 alu.last = i == lasti;
8267 alu.dst.sel = reg;
8268 alu.dst.chan = i;
8269 alu.dst.write = 1;
8270 r = r600_bytecode_add_alu(ctx->bc, &alu);
8271 if (r)
8272 return r;
8273 }
8274
8275 if (inst->Dst[0].Register.Index > 0)
8276 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8277 else
8278 ctx->bc->ar_loaded = 0;
8279
8280 return 0;
8281 }
8282 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8283 {
8284 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8285 struct r600_bytecode_alu alu;
8286 int r;
8287 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8288
8289 switch (inst->Instruction.Opcode) {
8290 case TGSI_OPCODE_ARL:
8291 memset(&alu, 0, sizeof(alu));
8292 alu.op = ALU_OP1_FLOOR;
8293 alu.dst.sel = ctx->bc->ar_reg;
8294 alu.dst.write = 1;
8295 for (i = 0; i <= lasti; ++i) {
8296 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8297 alu.dst.chan = i;
8298 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8299 alu.last = i == lasti;
8300 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8301 return r;
8302 }
8303 }
8304
8305 memset(&alu, 0, sizeof(alu));
8306 alu.op = ALU_OP1_FLT_TO_INT;
8307 alu.src[0].sel = ctx->bc->ar_reg;
8308 alu.dst.sel = ctx->bc->ar_reg;
8309 alu.dst.write = 1;
8310 /* FLT_TO_INT is trans-only on r600/r700 */
8311 alu.last = TRUE;
8312 for (i = 0; i <= lasti; ++i) {
8313 alu.dst.chan = i;
8314 alu.src[0].chan = i;
8315 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8316 return r;
8317 }
8318 break;
8319 case TGSI_OPCODE_ARR:
8320 memset(&alu, 0, sizeof(alu));
8321 alu.op = ALU_OP1_FLT_TO_INT;
8322 alu.dst.sel = ctx->bc->ar_reg;
8323 alu.dst.write = 1;
8324 /* FLT_TO_INT is trans-only on r600/r700 */
8325 alu.last = TRUE;
8326 for (i = 0; i <= lasti; ++i) {
8327 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8328 alu.dst.chan = i;
8329 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8330 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8331 return r;
8332 }
8333 }
8334 break;
8335 case TGSI_OPCODE_UARL:
8336 memset(&alu, 0, sizeof(alu));
8337 alu.op = ALU_OP1_MOV;
8338 alu.dst.sel = ctx->bc->ar_reg;
8339 alu.dst.write = 1;
8340 for (i = 0; i <= lasti; ++i) {
8341 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8342 alu.dst.chan = i;
8343 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8344 alu.last = i == lasti;
8345 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8346 return r;
8347 }
8348 }
8349 break;
8350 default:
8351 assert(0);
8352 return -1;
8353 }
8354
8355 ctx->bc->ar_loaded = 0;
8356 return 0;
8357 }
8358
8359 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8360 {
8361 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8362 struct r600_bytecode_alu alu;
8363 int i, r = 0;
8364
8365 for (i = 0; i < 4; i++) {
8366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8367
8368 alu.op = ALU_OP2_MUL;
8369 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8370
8371 if (i == 0 || i == 3) {
8372 alu.src[0].sel = V_SQ_ALU_SRC_1;
8373 } else {
8374 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8375 }
8376
8377 if (i == 0 || i == 2) {
8378 alu.src[1].sel = V_SQ_ALU_SRC_1;
8379 } else {
8380 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8381 }
8382 if (i == 3)
8383 alu.last = 1;
8384 r = r600_bytecode_add_alu(ctx->bc, &alu);
8385 if (r)
8386 return r;
8387 }
8388 return 0;
8389 }
8390
8391 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8392 {
8393 struct r600_bytecode_alu alu;
8394 int r;
8395
8396 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8397 alu.op = opcode;
8398 alu.execute_mask = 1;
8399 alu.update_pred = 1;
8400
8401 alu.dst.sel = ctx->temp_reg;
8402 alu.dst.write = 1;
8403 alu.dst.chan = 0;
8404
8405 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8406 alu.src[1].sel = V_SQ_ALU_SRC_0;
8407 alu.src[1].chan = 0;
8408
8409 alu.last = 1;
8410
8411 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8412 if (r)
8413 return r;
8414 return 0;
8415 }
8416
8417 static int pops(struct r600_shader_ctx *ctx, int pops)
8418 {
8419 unsigned force_pop = ctx->bc->force_add_cf;
8420
8421 if (!force_pop) {
8422 int alu_pop = 3;
8423 if (ctx->bc->cf_last) {
8424 if (ctx->bc->cf_last->op == CF_OP_ALU)
8425 alu_pop = 0;
8426 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8427 alu_pop = 1;
8428 }
8429 alu_pop += pops;
8430 if (alu_pop == 1) {
8431 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8432 ctx->bc->force_add_cf = 1;
8433 } else if (alu_pop == 2) {
8434 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8435 ctx->bc->force_add_cf = 1;
8436 } else {
8437 force_pop = 1;
8438 }
8439 }
8440
8441 if (force_pop) {
8442 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8443 ctx->bc->cf_last->pop_count = pops;
8444 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8445 }
8446
8447 return 0;
8448 }
8449
8450 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8451 unsigned reason)
8452 {
8453 struct r600_stack_info *stack = &ctx->bc->stack;
8454 unsigned elements, entries;
8455
8456 unsigned entry_size = stack->entry_size;
8457
8458 elements = (stack->loop + stack->push_wqm ) * entry_size;
8459 elements += stack->push;
8460
8461 switch (ctx->bc->chip_class) {
8462 case R600:
8463 case R700:
8464 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8465 * the stack must be reserved to hold the current active/continue
8466 * masks */
8467 if (reason == FC_PUSH_VPM) {
8468 elements += 2;
8469 }
8470 break;
8471
8472 case CAYMAN:
8473 /* r9xx: any stack operation on empty stack consumes 2 additional
8474 * elements */
8475 elements += 2;
8476
8477 /* fallthrough */
8478 /* FIXME: do the two elements added above cover the cases for the
8479 * r8xx+ below? */
8480
8481 case EVERGREEN:
8482 /* r8xx+: 2 extra elements are not always required, but one extra
8483 * element must be added for each of the following cases:
8484 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8485 * stack usage.
8486 * (Currently we don't use ALU_ELSE_AFTER.)
8487 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8488 * PUSH instruction executed.
8489 *
8490 * NOTE: it seems we also need to reserve additional element in some
8491 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8492 * then STACK_SIZE should be 2 instead of 1 */
8493 if (reason == FC_PUSH_VPM) {
8494 elements += 1;
8495 }
8496 break;
8497
8498 default:
8499 assert(0);
8500 break;
8501 }
8502
8503 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8504 * for all chips, so we use 4 in the final formula, not the real entry_size
8505 * for the chip */
8506 entry_size = 4;
8507
8508 entries = (elements + (entry_size - 1)) / entry_size;
8509
8510 if (entries > stack->max_entries)
8511 stack->max_entries = entries;
8512 }
8513
8514 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8515 {
8516 switch(reason) {
8517 case FC_PUSH_VPM:
8518 --ctx->bc->stack.push;
8519 assert(ctx->bc->stack.push >= 0);
8520 break;
8521 case FC_PUSH_WQM:
8522 --ctx->bc->stack.push_wqm;
8523 assert(ctx->bc->stack.push_wqm >= 0);
8524 break;
8525 case FC_LOOP:
8526 --ctx->bc->stack.loop;
8527 assert(ctx->bc->stack.loop >= 0);
8528 break;
8529 default:
8530 assert(0);
8531 break;
8532 }
8533 }
8534
8535 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8536 {
8537 switch (reason) {
8538 case FC_PUSH_VPM:
8539 ++ctx->bc->stack.push;
8540 break;
8541 case FC_PUSH_WQM:
8542 ++ctx->bc->stack.push_wqm;
8543 case FC_LOOP:
8544 ++ctx->bc->stack.loop;
8545 break;
8546 default:
8547 assert(0);
8548 }
8549
8550 callstack_update_max_depth(ctx, reason);
8551 }
8552
8553 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8554 {
8555 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8556
8557 sp->mid = realloc((void *)sp->mid,
8558 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8559 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8560 sp->num_mid++;
8561 }
8562
8563 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8564 {
8565 ctx->bc->fc_sp++;
8566 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8567 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8568 }
8569
8570 static void fc_poplevel(struct r600_shader_ctx *ctx)
8571 {
8572 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
8573 free(sp->mid);
8574 sp->mid = NULL;
8575 sp->num_mid = 0;
8576 sp->start = NULL;
8577 sp->type = 0;
8578 ctx->bc->fc_sp--;
8579 }
8580
8581 #if 0
8582 static int emit_return(struct r600_shader_ctx *ctx)
8583 {
8584 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8585 return 0;
8586 }
8587
8588 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8589 {
8590
8591 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8592 ctx->bc->cf_last->pop_count = pops;
8593 /* XXX work out offset */
8594 return 0;
8595 }
8596
8597 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8598 {
8599 return 0;
8600 }
8601
8602 static void emit_testflag(struct r600_shader_ctx *ctx)
8603 {
8604
8605 }
8606
8607 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8608 {
8609 emit_testflag(ctx);
8610 emit_jump_to_offset(ctx, 1, 4);
8611 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8612 pops(ctx, ifidx + 1);
8613 emit_return(ctx);
8614 }
8615
8616 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8617 {
8618 emit_testflag(ctx);
8619
8620 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8621 ctx->bc->cf_last->pop_count = 1;
8622
8623 fc_set_mid(ctx, fc_sp);
8624
8625 pops(ctx, 1);
8626 }
8627 #endif
8628
8629 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8630 {
8631 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8632
8633 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8634 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8635 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8636 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8637 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8638 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8639 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8640 alu_type = CF_OP_ALU;
8641 }
8642
8643 emit_logic_pred(ctx, opcode, alu_type);
8644
8645 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8646
8647 fc_pushlevel(ctx, FC_IF);
8648
8649 callstack_push(ctx, FC_PUSH_VPM);
8650 return 0;
8651 }
8652
8653 static int tgsi_if(struct r600_shader_ctx *ctx)
8654 {
8655 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8656 }
8657
8658 static int tgsi_uif(struct r600_shader_ctx *ctx)
8659 {
8660 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8661 }
8662
8663 static int tgsi_else(struct r600_shader_ctx *ctx)
8664 {
8665 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8666 ctx->bc->cf_last->pop_count = 1;
8667
8668 fc_set_mid(ctx, ctx->bc->fc_sp);
8669 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
8670 return 0;
8671 }
8672
8673 static int tgsi_endif(struct r600_shader_ctx *ctx)
8674 {
8675 pops(ctx, 1);
8676 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
8677 R600_ERR("if/endif unbalanced in shader\n");
8678 return -1;
8679 }
8680
8681 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
8682 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8683 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
8684 } else {
8685 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8686 }
8687 fc_poplevel(ctx);
8688
8689 callstack_pop(ctx, FC_PUSH_VPM);
8690 return 0;
8691 }
8692
8693 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8694 {
8695 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8696 * limited to 4096 iterations, like the other LOOP_* instructions. */
8697 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8698
8699 fc_pushlevel(ctx, FC_LOOP);
8700
8701 /* check stack depth */
8702 callstack_push(ctx, FC_LOOP);
8703 return 0;
8704 }
8705
8706 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8707 {
8708 unsigned i;
8709
8710 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8711
8712 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
8713 R600_ERR("loop/endloop in shader code are not paired.\n");
8714 return -EINVAL;
8715 }
8716
8717 /* fixup loop pointers - from r600isa
8718 LOOP END points to CF after LOOP START,
8719 LOOP START point to CF after LOOP END
8720 BRK/CONT point to LOOP END CF
8721 */
8722 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
8723
8724 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8725
8726 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
8727 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
8728 }
8729 /* XXX add LOOPRET support */
8730 fc_poplevel(ctx);
8731 callstack_pop(ctx, FC_LOOP);
8732 return 0;
8733 }
8734
8735 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
8736 {
8737 int r;
8738 unsigned int fscp;
8739
8740 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8741 {
8742 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8743 break;
8744 }
8745 if (fscp == 0) {
8746 R600_ERR("BREAKC not inside loop/endloop pair\n");
8747 return -EINVAL;
8748 }
8749
8750 if (ctx->bc->chip_class == EVERGREEN &&
8751 ctx->bc->family != CHIP_CYPRESS &&
8752 ctx->bc->family != CHIP_JUNIPER) {
8753 /* HW bug: ALU_BREAK does not save the active mask correctly */
8754 r = tgsi_uif(ctx);
8755 if (r)
8756 return r;
8757
8758 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
8759 if (r)
8760 return r;
8761 fc_set_mid(ctx, fscp);
8762
8763 return tgsi_endif(ctx);
8764 } else {
8765 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
8766 if (r)
8767 return r;
8768 fc_set_mid(ctx, fscp);
8769 }
8770
8771 return 0;
8772 }
8773
8774 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8775 {
8776 unsigned int fscp;
8777
8778 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8779 {
8780 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8781 break;
8782 }
8783
8784 if (fscp == 0) {
8785 R600_ERR("Break not inside loop/endloop pair\n");
8786 return -EINVAL;
8787 }
8788
8789 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8790
8791 fc_set_mid(ctx, fscp);
8792
8793 return 0;
8794 }
8795
8796 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8797 {
8798 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8799 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8800 int r;
8801
8802 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8803 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
8804
8805 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8806 if (!r) {
8807 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
8808 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8809 return emit_inc_ring_offset(ctx, stream, TRUE);
8810 }
8811 return r;
8812 }
8813
8814 static int tgsi_umad(struct r600_shader_ctx *ctx)
8815 {
8816 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8817 struct r600_bytecode_alu alu;
8818 int i, j, k, r;
8819 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8820
8821 /* src0 * src1 */
8822 for (i = 0; i < lasti + 1; i++) {
8823 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8824 continue;
8825
8826 if (ctx->bc->chip_class == CAYMAN) {
8827 for (j = 0 ; j < 4; j++) {
8828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8829
8830 alu.op = ALU_OP2_MULLO_UINT;
8831 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
8832 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
8833 }
8834 alu.dst.chan = j;
8835 alu.dst.sel = ctx->temp_reg;
8836 alu.dst.write = (j == i);
8837 if (j == 3)
8838 alu.last = 1;
8839 r = r600_bytecode_add_alu(ctx->bc, &alu);
8840 if (r)
8841 return r;
8842 }
8843 } else {
8844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8845
8846 alu.dst.chan = i;
8847 alu.dst.sel = ctx->temp_reg;
8848 alu.dst.write = 1;
8849
8850 alu.op = ALU_OP2_MULLO_UINT;
8851 for (j = 0; j < 2; j++) {
8852 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
8853 }
8854
8855 alu.last = 1;
8856 r = r600_bytecode_add_alu(ctx->bc, &alu);
8857 if (r)
8858 return r;
8859 }
8860 }
8861
8862
8863 for (i = 0; i < lasti + 1; i++) {
8864 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8865 continue;
8866
8867 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8868 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8869
8870 alu.op = ALU_OP2_ADD_INT;
8871
8872 alu.src[0].sel = ctx->temp_reg;
8873 alu.src[0].chan = i;
8874
8875 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8876 if (i == lasti) {
8877 alu.last = 1;
8878 }
8879 r = r600_bytecode_add_alu(ctx->bc, &alu);
8880 if (r)
8881 return r;
8882 }
8883 return 0;
8884 }
8885
8886 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
8887 {
8888 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8889 struct r600_bytecode_alu alu;
8890 int r, i;
8891 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8892
8893 /* temp.xy = f32_to_f16(src) */
8894 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8895 alu.op = ALU_OP1_FLT32_TO_FLT16;
8896 alu.dst.chan = 0;
8897 alu.dst.sel = ctx->temp_reg;
8898 alu.dst.write = 1;
8899 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8900 r = r600_bytecode_add_alu(ctx->bc, &alu);
8901 if (r)
8902 return r;
8903 alu.dst.chan = 1;
8904 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
8905 alu.last = 1;
8906 r = r600_bytecode_add_alu(ctx->bc, &alu);
8907 if (r)
8908 return r;
8909
8910 /* dst.x = temp.y * 0x10000 + temp.x */
8911 for (i = 0; i < lasti + 1; i++) {
8912 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8913 continue;
8914
8915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8916 alu.op = ALU_OP3_MULADD_UINT24;
8917 alu.is_op3 = 1;
8918 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8919 alu.last = i == lasti;
8920 alu.src[0].sel = ctx->temp_reg;
8921 alu.src[0].chan = 1;
8922 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8923 alu.src[1].value = 0x10000;
8924 alu.src[2].sel = ctx->temp_reg;
8925 alu.src[2].chan = 0;
8926 r = r600_bytecode_add_alu(ctx->bc, &alu);
8927 if (r)
8928 return r;
8929 }
8930
8931 return 0;
8932 }
8933
8934 static int tgsi_up2h(struct r600_shader_ctx *ctx)
8935 {
8936 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8937 struct r600_bytecode_alu alu;
8938 int r, i;
8939 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8940
8941 /* temp.x = src.x */
8942 /* note: no need to mask out the high bits */
8943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8944 alu.op = ALU_OP1_MOV;
8945 alu.dst.chan = 0;
8946 alu.dst.sel = ctx->temp_reg;
8947 alu.dst.write = 1;
8948 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8949 r = r600_bytecode_add_alu(ctx->bc, &alu);
8950 if (r)
8951 return r;
8952
8953 /* temp.y = src.x >> 16 */
8954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8955 alu.op = ALU_OP2_LSHR_INT;
8956 alu.dst.chan = 1;
8957 alu.dst.sel = ctx->temp_reg;
8958 alu.dst.write = 1;
8959 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8960 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8961 alu.src[1].value = 16;
8962 alu.last = 1;
8963 r = r600_bytecode_add_alu(ctx->bc, &alu);
8964 if (r)
8965 return r;
8966
8967 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
8968 for (i = 0; i < lasti + 1; i++) {
8969 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8970 continue;
8971 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8972 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8973 alu.op = ALU_OP1_FLT16_TO_FLT32;
8974 alu.src[0].sel = ctx->temp_reg;
8975 alu.src[0].chan = i % 2;
8976 alu.last = i == lasti;
8977 r = r600_bytecode_add_alu(ctx->bc, &alu);
8978 if (r)
8979 return r;
8980 }
8981
8982 return 0;
8983 }
8984
8985 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
8986 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
8987 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8988 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8989
8990 /* XXX:
8991 * For state trackers other than OpenGL, we'll want to use
8992 * _RECIP_IEEE instead.
8993 */
8994 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
8995
8996 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
8997 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8998 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8999 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9000 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9001 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9002 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9003 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9004 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9005 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9006 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9007 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9008 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9009 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
9010 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9011 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9012 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9013 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9014 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9015 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9016 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9017 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9018 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9019 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9020 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9021 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9022 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9023 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9024 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9025 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9026 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9027 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9028 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9029 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9030 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9031 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9032 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9033 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9034 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9035 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9036 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9037 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9038 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9039 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9040 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9041 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9042 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9043 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9044 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9045 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9046 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9047 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9048 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9049 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9050 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9051 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9052 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9053 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9054 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9055 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9056 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9057 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9058 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9059 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9060 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9061 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9062 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9063 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9064 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9065 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9066 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9067 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9068 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9069 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9070 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9071 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9072 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9073 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9074 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9075 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9076 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9077 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9078 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9079 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9080 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9081 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9082 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9083 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9084 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9085 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9086 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9087 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9088 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9089 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9090 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9091 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9092 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9093 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9094 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9095 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9096 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9097 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9098 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9099 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9100 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9101 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9102 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9103 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9104 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9105 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9106 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9107 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
9108 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9109 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9110 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9111 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9112 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9113 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9114 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9115 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9116 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9117 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9118 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9119 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9120 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9121 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9122 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9123 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9124 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9125 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9126 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9127 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9128 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9129 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9130 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9131 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9132 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9133 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9134 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9135 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9136 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9137 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9138 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9139 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9140 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9141 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9142 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9143 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9144 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9145 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9146 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9147 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9148 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9149 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9150 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9151 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9152 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9153 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9154 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9155 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9156 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9157 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9158 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9159 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9160 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9161 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9162 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9163 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9164 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9165 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9166 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9167 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9168 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9169 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9170 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9171 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9172 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9173 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9174 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9175 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9176 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9177 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9178 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9179 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9180 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9181 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9182 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9183 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9184 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9185 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9186 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9187 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9188 };
9189
9190 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9191 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9192 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9193 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9194 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9195 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
9196 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9197 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9198 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9199 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9200 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9201 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9202 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9203 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9204 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9205 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9206 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9207 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9208 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
9209 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9210 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9211 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9212 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9213 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9214 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9215 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9216 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9217 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9218 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9219 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9220 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9221 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9222 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9223 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9224 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9225 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9226 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9227 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9228 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9229 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9230 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9231 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9232 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9233 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9234 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9235 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9236 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9237 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9238 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9239 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9240 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9241 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9242 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9243 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9244 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9245 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9246 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9247 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9248 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9249 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9250 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9251 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9252 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9253 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9254 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9255 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9256 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9257 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9258 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9259 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9260 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9261 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9262 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9263 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9264 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9265 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9266 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9267 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9268 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9269 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9270 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9271 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9272 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9273 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9274 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9275 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9276 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9277 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9278 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9279 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9280 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9281 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9282 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9283 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9284 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9285 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9286 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9287 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9288 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9289 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9290 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9291 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9292 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9293 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9294 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9295 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9296 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9297 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9298 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9299 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9300 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9301 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9302 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9303 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9304 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9305 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9306 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9307 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9308 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9309 /* Refer below for TGSI_OPCODE_DFMA */
9310 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9311 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9312 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9313 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9314 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9315 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9316 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9317 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9318 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9319 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9320 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9321 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9322 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9323 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9324 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9325 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9326 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9327 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9328 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9329 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9330 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9331 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9332 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9333 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9334 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9335 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9336 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9337 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9338 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9339 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9340 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9341 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9342 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9343 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9344 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9345 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9346 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9347 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9348 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9349 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9350 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9351 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9352 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9353 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9354 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9355 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9356 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9357 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9358 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9359 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9360 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9361 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9362 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9363 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9364 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9365 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9366 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9367 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9368 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9369 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9370 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9371 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9372 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9373 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9374 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9375 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9376 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9377 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9378 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9379 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9380 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9381 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9382 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9383 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9384 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9385 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9386 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9387 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9388 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9389 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9390 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9391 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9392 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9393 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9394 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9395 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9396 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9397 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9398 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9399 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9400 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9401 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9402 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9403 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9404 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9405 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9406 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9407 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9408 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9409 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9410 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9411 };
9412
9413 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9414 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9415 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9416 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9417 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9418 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9419 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9420 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9421 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9422 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9423 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9424 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9425 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9426 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9427 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9428 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9429 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9430 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9431 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
9432 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9433 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9434 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9435 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9436 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9437 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9438 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9439 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9440 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9441 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9442 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9443 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9444 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9445 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9446 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9447 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9448 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9449 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9450 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9451 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9452 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9453 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9454 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9455 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9456 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9457 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9458 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9459 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9460 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9461 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9462 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9463 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9464 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9465 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9466 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9467 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9468 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9469 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9470 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9471 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9472 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9473 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9474 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9475 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9476 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9477 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9478 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9479 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9480 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9481 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9482 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9483 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9484 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9485 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9486 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9487 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9488 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9489 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9490 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9491 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9492 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9493 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9494 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9495 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9496 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9497 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9498 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9499 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9500 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9501 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9502 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9503 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9504 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9505 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9506 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9507 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9508 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9509 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9510 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9511 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9512 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9513 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9514 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9515 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9516 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9517 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9518 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9519 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9520 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9521 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9522 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9523 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9524 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9525 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9526 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9527 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9528 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9529 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9530 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9531 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9532 /* Refer below for TGSI_OPCODE_DFMA */
9533 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9534 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9535 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9536 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9537 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9538 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9539 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9540 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9541 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9542 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9543 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9544 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9545 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9546 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9547 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9548 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9549 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9550 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9551 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9552 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9553 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9554 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9555 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9556 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9557 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9558 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9559 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9560 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9561 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9562 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9563 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9564 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9565 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9566 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9567 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9568 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9569 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9570 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9571 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9572 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9573 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9574 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9575 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9576 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9577 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9578 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9579 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9580 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9581 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9582 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9583 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9584 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9585 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9586 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9587 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9588 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9589 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9590 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9591 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9592 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9593 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9594 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9595 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9596 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9597 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9598 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9599 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9600 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9601 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9602 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9603 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9604 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9605 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9606 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9607 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9608 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9609 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9610 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9611 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9612 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9613 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9614 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9615 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9616 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9617 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9618 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9619 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9620 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9621 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9622 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9623 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9624 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9625 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9626 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9627 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9628 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9629 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9630 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9631 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9632 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9633 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9634 };