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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193 use_sb &= (shader->shader.processor_type != PIPE_SHADER_COMPUTE);
194
195 /* disable SB for shaders using doubles */
196 use_sb &= !shader->shader.uses_doubles;
197
198 use_sb &= !shader->shader.uses_atomics;
199 use_sb &= !shader->shader.uses_images;
200 use_sb &= !shader->shader.uses_helper_invocation;
201
202 /* Check if the bytecode has already been built. */
203 if (!shader->shader.bc.bytecode) {
204 r = r600_bytecode_build(&shader->shader.bc);
205 if (r) {
206 R600_ERR("building bytecode failed !\n");
207 goto error;
208 }
209 }
210
211 if (dump && !sb_disasm) {
212 fprintf(stderr, "--------------------------------------------------------------\n");
213 r600_bytecode_disasm(&shader->shader.bc);
214 fprintf(stderr, "______________________________________________________________\n");
215 } else if ((dump && sb_disasm) || use_sb) {
216 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
217 dump, use_sb);
218 if (r) {
219 R600_ERR("r600_sb_bytecode_process failed !\n");
220 goto error;
221 }
222 }
223
224 if (shader->gs_copy_shader) {
225 if (dump) {
226 // dump copy shader
227 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
228 &shader->gs_copy_shader->shader, dump, 0);
229 if (r)
230 goto error;
231 }
232
233 if ((r = store_shader(ctx, shader->gs_copy_shader)))
234 goto error;
235 }
236
237 /* Store the shader in a buffer. */
238 if ((r = store_shader(ctx, shader)))
239 goto error;
240
241 /* Build state. */
242 switch (shader->shader.processor_type) {
243 case PIPE_SHADER_TESS_CTRL:
244 evergreen_update_hs_state(ctx, shader);
245 break;
246 case PIPE_SHADER_TESS_EVAL:
247 if (key.tes.as_es)
248 evergreen_update_es_state(ctx, shader);
249 else
250 evergreen_update_vs_state(ctx, shader);
251 break;
252 case PIPE_SHADER_GEOMETRY:
253 if (rctx->b.chip_class >= EVERGREEN) {
254 evergreen_update_gs_state(ctx, shader);
255 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
256 } else {
257 r600_update_gs_state(ctx, shader);
258 r600_update_vs_state(ctx, shader->gs_copy_shader);
259 }
260 break;
261 case PIPE_SHADER_VERTEX:
262 export_shader = key.vs.as_es;
263 if (rctx->b.chip_class >= EVERGREEN) {
264 if (key.vs.as_ls)
265 evergreen_update_ls_state(ctx, shader);
266 else if (key.vs.as_es)
267 evergreen_update_es_state(ctx, shader);
268 else
269 evergreen_update_vs_state(ctx, shader);
270 } else {
271 if (export_shader)
272 r600_update_es_state(ctx, shader);
273 else
274 r600_update_vs_state(ctx, shader);
275 }
276 break;
277 case PIPE_SHADER_FRAGMENT:
278 if (rctx->b.chip_class >= EVERGREEN) {
279 evergreen_update_ps_state(ctx, shader);
280 } else {
281 r600_update_ps_state(ctx, shader);
282 }
283 break;
284 case PIPE_SHADER_COMPUTE:
285 evergreen_update_ls_state(ctx, shader);
286 break;
287 default:
288 r = -EINVAL;
289 goto error;
290 }
291 return 0;
292
293 error:
294 r600_pipe_shader_destroy(ctx, shader);
295 return r;
296 }
297
298 void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
299 {
300 r600_resource_reference(&shader->bo, NULL);
301 r600_bytecode_clear(&shader->shader.bc);
302 r600_release_command_buffer(&shader->command_buffer);
303 }
304
305 /*
306 * tgsi -> r600 shader
307 */
308 struct r600_shader_tgsi_instruction;
309
310 struct r600_shader_src {
311 unsigned sel;
312 unsigned swizzle[4];
313 unsigned neg;
314 unsigned abs;
315 unsigned rel;
316 unsigned kc_bank;
317 boolean kc_rel; /* true if cache bank is indexed */
318 uint32_t value[4];
319 };
320
321 struct eg_interp {
322 boolean enabled;
323 unsigned ij_index;
324 };
325
326 struct r600_shader_ctx {
327 struct tgsi_shader_info info;
328 struct tgsi_parse_context parse;
329 const struct tgsi_token *tokens;
330 unsigned type;
331 unsigned file_offset[TGSI_FILE_COUNT];
332 unsigned temp_reg;
333 const struct r600_shader_tgsi_instruction *inst_info;
334 struct r600_bytecode *bc;
335 struct r600_shader *shader;
336 struct r600_shader_src src[4];
337 uint32_t *literals;
338 uint32_t nliterals;
339 uint32_t max_driver_temp_used;
340 /* needed for evergreen interpolation */
341 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
342 /* evergreen/cayman also store sample mask in face register */
343 int face_gpr;
344 /* sample id is .w component stored in fixed point position register */
345 int fixed_pt_position_gpr;
346 int colors_used;
347 boolean clip_vertex_write;
348 unsigned cv_output;
349 unsigned edgeflag_output;
350 int helper_invoc_reg;
351 int cs_block_size_reg;
352 int cs_grid_size_reg;
353 bool cs_block_size_loaded, cs_grid_size_loaded;
354 int fragcoord_input;
355 int next_ring_offset;
356 int gs_out_ring_offset;
357 int gs_next_vertex;
358 struct r600_shader *gs_for_vs;
359 int gs_export_gpr_tregs[4];
360 int gs_rotated_input[2];
361 const struct pipe_stream_output_info *gs_stream_output_info;
362 unsigned enabled_stream_buffers_mask;
363 unsigned tess_input_info; /* temp with tess input offsets */
364 unsigned tess_output_info; /* temp with tess input offsets */
365 unsigned thread_id_gpr; /* temp with thread id calculated for images */
366 bool thread_id_gpr_loaded;
367 };
368
369 struct r600_shader_tgsi_instruction {
370 unsigned op;
371 int (*process)(struct r600_shader_ctx *ctx);
372 };
373
374 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
375 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
376 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
377 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
378 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
379 static int tgsi_else(struct r600_shader_ctx *ctx);
380 static int tgsi_endif(struct r600_shader_ctx *ctx);
381 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
382 static int tgsi_endloop(struct r600_shader_ctx *ctx);
383 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
384 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
385 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
386 unsigned int dst_reg);
387 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
388 const struct r600_shader_src *shader_src,
389 unsigned chan);
390 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
391 unsigned dst_reg, unsigned mask);
392
393 static int tgsi_last_instruction(unsigned writemask)
394 {
395 int i, lasti = 0;
396
397 for (i = 0; i < 4; i++) {
398 if (writemask & (1 << i)) {
399 lasti = i;
400 }
401 }
402 return lasti;
403 }
404
405 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
406 {
407 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
408 unsigned j;
409
410 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
411 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
412 return -EINVAL;
413 }
414 #if 0
415 if (i->Instruction.Label) {
416 R600_ERR("label unsupported\n");
417 return -EINVAL;
418 }
419 #endif
420 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
421 if (i->Src[j].Register.Dimension) {
422 switch (i->Src[j].Register.File) {
423 case TGSI_FILE_CONSTANT:
424 case TGSI_FILE_HW_ATOMIC:
425 break;
426 case TGSI_FILE_INPUT:
427 if (ctx->type == PIPE_SHADER_GEOMETRY ||
428 ctx->type == PIPE_SHADER_TESS_CTRL ||
429 ctx->type == PIPE_SHADER_TESS_EVAL)
430 break;
431 case TGSI_FILE_OUTPUT:
432 if (ctx->type == PIPE_SHADER_TESS_CTRL)
433 break;
434 default:
435 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
436 i->Src[j].Register.File,
437 i->Src[j].Register.Dimension);
438 return -EINVAL;
439 }
440 }
441 }
442 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
443 if (i->Dst[j].Register.Dimension) {
444 if (ctx->type == PIPE_SHADER_TESS_CTRL)
445 continue;
446 R600_ERR("unsupported dst (dimension)\n");
447 return -EINVAL;
448 }
449 }
450 return 0;
451 }
452
453 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
454 {
455 if (interpolate == TGSI_INTERPOLATE_COLOR ||
456 interpolate == TGSI_INTERPOLATE_LINEAR ||
457 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
458 {
459 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
460 int loc;
461
462 switch(location) {
463 case TGSI_INTERPOLATE_LOC_CENTER:
464 loc = 1;
465 break;
466 case TGSI_INTERPOLATE_LOC_CENTROID:
467 loc = 2;
468 break;
469 case TGSI_INTERPOLATE_LOC_SAMPLE:
470 default:
471 loc = 0; break;
472 }
473
474 return is_linear * 3 + loc;
475 }
476
477 return -1;
478 }
479
480 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
481 int input)
482 {
483 int i = eg_get_interpolator_index(
484 ctx->shader->input[input].interpolate,
485 ctx->shader->input[input].interpolate_location);
486 assert(i >= 0);
487 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
488 }
489
490 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
491 {
492 int i, r;
493 struct r600_bytecode_alu alu;
494 int gpr = 0, base_chan = 0;
495 int ij_index = ctx->shader->input[input].ij_index;
496
497 /* work out gpr and base_chan from index */
498 gpr = ij_index / 2;
499 base_chan = (2 * (ij_index % 2)) + 1;
500
501 for (i = 0; i < 8; i++) {
502 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
503
504 if (i < 4)
505 alu.op = ALU_OP2_INTERP_ZW;
506 else
507 alu.op = ALU_OP2_INTERP_XY;
508
509 if ((i > 1) && (i < 6)) {
510 alu.dst.sel = ctx->shader->input[input].gpr;
511 alu.dst.write = 1;
512 }
513
514 alu.dst.chan = i % 4;
515
516 alu.src[0].sel = gpr;
517 alu.src[0].chan = (base_chan - (i % 2));
518
519 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
520
521 alu.bank_swizzle_force = SQ_ALU_VEC_210;
522 if ((i % 4) == 3)
523 alu.last = 1;
524 r = r600_bytecode_add_alu(ctx->bc, &alu);
525 if (r)
526 return r;
527 }
528 return 0;
529 }
530
531 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
532 {
533 int i, r;
534 struct r600_bytecode_alu alu;
535
536 for (i = 0; i < 4; i++) {
537 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
538
539 alu.op = ALU_OP1_INTERP_LOAD_P0;
540
541 alu.dst.sel = ctx->shader->input[input].gpr;
542 alu.dst.write = 1;
543
544 alu.dst.chan = i;
545
546 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
547 alu.src[0].chan = i;
548
549 if (i == 3)
550 alu.last = 1;
551 r = r600_bytecode_add_alu(ctx->bc, &alu);
552 if (r)
553 return r;
554 }
555 return 0;
556 }
557
558 /*
559 * Special export handling in shaders
560 *
561 * shader export ARRAY_BASE for EXPORT_POS:
562 * 60 is position
563 * 61 is misc vector
564 * 62, 63 are clip distance vectors
565 *
566 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
567 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
568 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
569 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
570 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
571 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
572 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
573 * exclusive from render target index)
574 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
575 *
576 *
577 * shader export ARRAY_BASE for EXPORT_PIXEL:
578 * 0-7 CB targets
579 * 61 computed Z vector
580 *
581 * The use of the values exported in the computed Z vector are controlled
582 * by DB_SHADER_CONTROL:
583 * Z_EXPORT_ENABLE - Z as a float in RED
584 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
585 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
586 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
587 * DB_SOURCE_FORMAT - export control restrictions
588 *
589 */
590
591
592 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
593 static int r600_spi_sid(struct r600_shader_io * io)
594 {
595 int index, name = io->name;
596
597 /* These params are handled differently, they don't need
598 * semantic indices, so we'll use 0 for them.
599 */
600 if (name == TGSI_SEMANTIC_POSITION ||
601 name == TGSI_SEMANTIC_PSIZE ||
602 name == TGSI_SEMANTIC_EDGEFLAG ||
603 name == TGSI_SEMANTIC_FACE ||
604 name == TGSI_SEMANTIC_SAMPLEMASK)
605 index = 0;
606 else {
607 if (name == TGSI_SEMANTIC_GENERIC) {
608 /* For generic params simply use sid from tgsi */
609 index = io->sid;
610 } else {
611 /* For non-generic params - pack name and sid into 8 bits */
612 index = 0x80 | (name<<3) | (io->sid);
613 }
614
615 /* Make sure that all really used indices have nonzero value, so
616 * we can just compare it to 0 later instead of comparing the name
617 * with different values to detect special cases. */
618 index++;
619 }
620
621 return index;
622 };
623
624 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
625 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
626 {
627 switch (semantic_name) {
628 case TGSI_SEMANTIC_POSITION:
629 return 0;
630 case TGSI_SEMANTIC_PSIZE:
631 return 1;
632 case TGSI_SEMANTIC_CLIPDIST:
633 assert(index <= 1);
634 return 2 + index;
635 case TGSI_SEMANTIC_GENERIC:
636 if (index <= 63-4)
637 return 4 + index - 9;
638 else
639 /* same explanation as in the default statement,
640 * the only user hitting this is st/nine.
641 */
642 return 0;
643
644 /* patch indices are completely separate and thus start from 0 */
645 case TGSI_SEMANTIC_TESSOUTER:
646 return 0;
647 case TGSI_SEMANTIC_TESSINNER:
648 return 1;
649 case TGSI_SEMANTIC_PATCH:
650 return 2 + index;
651
652 default:
653 /* Don't fail here. The result of this function is only used
654 * for LS, TCS, TES, and GS, where legacy GL semantics can't
655 * occur, but this function is called for all vertex shaders
656 * before it's known whether LS will be compiled or not.
657 */
658 return 0;
659 }
660 }
661
662 /* turn input into interpolate on EG */
663 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
664 {
665 int r = 0;
666
667 if (ctx->shader->input[index].spi_sid) {
668 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
669 if (ctx->shader->input[index].interpolate > 0) {
670 evergreen_interp_assign_ij_index(ctx, index);
671 r = evergreen_interp_alu(ctx, index);
672 } else {
673 r = evergreen_interp_flat(ctx, index);
674 }
675 }
676 return r;
677 }
678
679 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
680 {
681 struct r600_bytecode_alu alu;
682 int i, r;
683 int gpr_front = ctx->shader->input[front].gpr;
684 int gpr_back = ctx->shader->input[back].gpr;
685
686 for (i = 0; i < 4; i++) {
687 memset(&alu, 0, sizeof(alu));
688 alu.op = ALU_OP3_CNDGT;
689 alu.is_op3 = 1;
690 alu.dst.write = 1;
691 alu.dst.sel = gpr_front;
692 alu.src[0].sel = ctx->face_gpr;
693 alu.src[1].sel = gpr_front;
694 alu.src[2].sel = gpr_back;
695
696 alu.dst.chan = i;
697 alu.src[1].chan = i;
698 alu.src[2].chan = i;
699 alu.last = (i==3);
700
701 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
702 return r;
703 }
704
705 return 0;
706 }
707
708 /* execute a single slot ALU calculation */
709 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
710 int dst_sel, int dst_chan,
711 int src0_sel, unsigned src0_chan_val,
712 int src1_sel, unsigned src1_chan_val)
713 {
714 struct r600_bytecode_alu alu;
715 int r, i;
716
717 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
718 for (i = 0; i < 4; i++) {
719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
720 alu.op = op;
721 alu.src[0].sel = src0_sel;
722 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
723 alu.src[0].value = src0_chan_val;
724 else
725 alu.src[0].chan = src0_chan_val;
726 alu.src[1].sel = src1_sel;
727 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
728 alu.src[1].value = src1_chan_val;
729 else
730 alu.src[1].chan = src1_chan_val;
731 alu.dst.sel = dst_sel;
732 alu.dst.chan = i;
733 alu.dst.write = i == dst_chan;
734 alu.last = (i == 3);
735 r = r600_bytecode_add_alu(ctx->bc, &alu);
736 if (r)
737 return r;
738 }
739 return 0;
740 }
741
742 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
743 alu.op = op;
744 alu.src[0].sel = src0_sel;
745 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
746 alu.src[0].value = src0_chan_val;
747 else
748 alu.src[0].chan = src0_chan_val;
749 alu.src[1].sel = src1_sel;
750 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
751 alu.src[1].value = src1_chan_val;
752 else
753 alu.src[1].chan = src1_chan_val;
754 alu.dst.sel = dst_sel;
755 alu.dst.chan = dst_chan;
756 alu.dst.write = 1;
757 alu.last = 1;
758 r = r600_bytecode_add_alu(ctx->bc, &alu);
759 if (r)
760 return r;
761 return 0;
762 }
763
764 /* execute a single slot ALU calculation */
765 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
766 int dst_sel, int dst_chan,
767 int src0_sel, unsigned src0_chan_val,
768 int src1_sel, unsigned src1_chan_val,
769 int src2_sel, unsigned src2_chan_val)
770 {
771 struct r600_bytecode_alu alu;
772 int r;
773
774 /* validate this for other ops */
775 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT || op == ALU_OP3_BFE_UINT);
776 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
777 alu.op = op;
778 alu.src[0].sel = src0_sel;
779 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
780 alu.src[0].value = src0_chan_val;
781 else
782 alu.src[0].chan = src0_chan_val;
783 alu.src[1].sel = src1_sel;
784 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
785 alu.src[1].value = src1_chan_val;
786 else
787 alu.src[1].chan = src1_chan_val;
788 alu.src[2].sel = src2_sel;
789 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
790 alu.src[2].value = src2_chan_val;
791 else
792 alu.src[2].chan = src2_chan_val;
793 alu.dst.sel = dst_sel;
794 alu.dst.chan = dst_chan;
795 alu.is_op3 = 1;
796 alu.last = 1;
797 r = r600_bytecode_add_alu(ctx->bc, &alu);
798 if (r)
799 return r;
800 return 0;
801 }
802
803 /* put it in temp_reg.x */
804 static int get_lds_offset0(struct r600_shader_ctx *ctx,
805 int rel_patch_chan,
806 int temp_reg, bool is_patch_var)
807 {
808 int r;
809
810 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
811 /* ADD
812 Dimension - patch0_offset (input_vals.z),
813 Non-dim - patch0_data_offset (input_vals.w)
814 */
815 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
816 temp_reg, 0,
817 ctx->tess_output_info, 0,
818 0, rel_patch_chan,
819 ctx->tess_output_info, is_patch_var ? 3 : 2);
820 if (r)
821 return r;
822 return 0;
823 }
824
825 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
826 {
827 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
828 }
829
830 static int r600_get_temp(struct r600_shader_ctx *ctx)
831 {
832 return ctx->temp_reg + ctx->max_driver_temp_used++;
833 }
834
835 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
836 {
837 int i;
838 i = ctx->shader->noutput++;
839 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
840 ctx->shader->output[i].sid = 0;
841 ctx->shader->output[i].gpr = 0;
842 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
843 ctx->shader->output[i].write_mask = 0x4;
844 ctx->shader->output[i].spi_sid = prim_id_sid;
845
846 return 0;
847 }
848
849 static int tgsi_barrier(struct r600_shader_ctx *ctx)
850 {
851 struct r600_bytecode_alu alu;
852 int r;
853
854 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
855 alu.op = ctx->inst_info->op;
856 alu.last = 1;
857
858 r = r600_bytecode_add_alu(ctx->bc, &alu);
859 if (r)
860 return r;
861 return 0;
862 }
863
864 static int tgsi_declaration(struct r600_shader_ctx *ctx)
865 {
866 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
867 int r, i, j, count = d->Range.Last - d->Range.First + 1;
868
869 switch (d->Declaration.File) {
870 case TGSI_FILE_INPUT:
871 for (j = 0; j < count; j++) {
872 i = ctx->shader->ninput + j;
873 assert(i < ARRAY_SIZE(ctx->shader->input));
874 ctx->shader->input[i].name = d->Semantic.Name;
875 ctx->shader->input[i].sid = d->Semantic.Index + j;
876 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
877 ctx->shader->input[i].interpolate_location = d->Interp.Location;
878 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
879 if (ctx->type == PIPE_SHADER_FRAGMENT) {
880 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
881 switch (ctx->shader->input[i].name) {
882 case TGSI_SEMANTIC_FACE:
883 if (ctx->face_gpr != -1)
884 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
885 else
886 ctx->face_gpr = ctx->shader->input[i].gpr;
887 break;
888 case TGSI_SEMANTIC_COLOR:
889 ctx->colors_used++;
890 break;
891 case TGSI_SEMANTIC_POSITION:
892 ctx->fragcoord_input = i;
893 break;
894 case TGSI_SEMANTIC_PRIMID:
895 /* set this for now */
896 ctx->shader->gs_prim_id_input = true;
897 ctx->shader->ps_prim_id_input = i;
898 break;
899 }
900 if (ctx->bc->chip_class >= EVERGREEN) {
901 if ((r = evergreen_interp_input(ctx, i)))
902 return r;
903 }
904 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
905 /* FIXME probably skip inputs if they aren't passed in the ring */
906 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
907 ctx->next_ring_offset += 16;
908 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
909 ctx->shader->gs_prim_id_input = true;
910 }
911 }
912 ctx->shader->ninput += count;
913 break;
914 case TGSI_FILE_OUTPUT:
915 for (j = 0; j < count; j++) {
916 i = ctx->shader->noutput + j;
917 assert(i < ARRAY_SIZE(ctx->shader->output));
918 ctx->shader->output[i].name = d->Semantic.Name;
919 ctx->shader->output[i].sid = d->Semantic.Index + j;
920 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
921 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
922 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
923 if (ctx->type == PIPE_SHADER_VERTEX ||
924 ctx->type == PIPE_SHADER_GEOMETRY ||
925 ctx->type == PIPE_SHADER_TESS_EVAL) {
926 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
927 switch (d->Semantic.Name) {
928 case TGSI_SEMANTIC_CLIPDIST:
929 break;
930 case TGSI_SEMANTIC_PSIZE:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_point_size = 1;
933 break;
934 case TGSI_SEMANTIC_EDGEFLAG:
935 ctx->shader->vs_out_misc_write = 1;
936 ctx->shader->vs_out_edgeflag = 1;
937 ctx->edgeflag_output = i;
938 break;
939 case TGSI_SEMANTIC_VIEWPORT_INDEX:
940 ctx->shader->vs_out_misc_write = 1;
941 ctx->shader->vs_out_viewport = 1;
942 break;
943 case TGSI_SEMANTIC_LAYER:
944 ctx->shader->vs_out_misc_write = 1;
945 ctx->shader->vs_out_layer = 1;
946 break;
947 case TGSI_SEMANTIC_CLIPVERTEX:
948 ctx->clip_vertex_write = TRUE;
949 ctx->cv_output = i;
950 break;
951 }
952 if (ctx->type == PIPE_SHADER_GEOMETRY) {
953 ctx->gs_out_ring_offset += 16;
954 }
955 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
956 switch (d->Semantic.Name) {
957 case TGSI_SEMANTIC_COLOR:
958 ctx->shader->nr_ps_max_color_exports++;
959 break;
960 }
961 }
962 }
963 ctx->shader->noutput += count;
964 break;
965 case TGSI_FILE_TEMPORARY:
966 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
967 if (d->Array.ArrayID) {
968 r600_add_gpr_array(ctx->shader,
969 ctx->file_offset[TGSI_FILE_TEMPORARY] +
970 d->Range.First,
971 d->Range.Last - d->Range.First + 1, 0x0F);
972 }
973 }
974 break;
975
976 case TGSI_FILE_CONSTANT:
977 case TGSI_FILE_SAMPLER:
978 case TGSI_FILE_SAMPLER_VIEW:
979 case TGSI_FILE_ADDRESS:
980 case TGSI_FILE_BUFFER:
981 case TGSI_FILE_IMAGE:
982 case TGSI_FILE_MEMORY:
983 break;
984
985 case TGSI_FILE_HW_ATOMIC:
986 i = ctx->shader->nhwatomic_ranges;
987 ctx->shader->atomics[i].start = d->Range.First;
988 ctx->shader->atomics[i].end = d->Range.Last;
989 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
990 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
991 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
992 ctx->shader->nhwatomic_ranges++;
993 ctx->shader->nhwatomic += count;
994 break;
995
996 case TGSI_FILE_SYSTEM_VALUE:
997 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
998 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
999 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
1000 break; /* Already handled from allocate_system_value_inputs */
1001 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
1002 break;
1003 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1004 break;
1005 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1006 break;
1007 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1008 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1009 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1010 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1011 unsigned temp_reg = r600_get_temp(ctx);
1012
1013 r = get_lds_offset0(ctx, 2, temp_reg, true);
1014 if (r)
1015 return r;
1016
1017 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1018 temp_reg, 0,
1019 temp_reg, 0,
1020 V_SQ_ALU_SRC_LITERAL, param * 16);
1021 if (r)
1022 return r;
1023
1024 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
1025 }
1026 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1027 /* MOV r1.x, r0.x;
1028 MOV r1.y, r0.y;
1029 */
1030 for (i = 0; i < 2; i++) {
1031 struct r600_bytecode_alu alu;
1032 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1033 alu.op = ALU_OP1_MOV;
1034 alu.src[0].sel = 0;
1035 alu.src[0].chan = 0 + i;
1036 alu.dst.sel = 1;
1037 alu.dst.chan = 0 + i;
1038 alu.dst.write = 1;
1039 alu.last = (i == 1) ? 1 : 0;
1040 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1041 return r;
1042 }
1043 /* ADD r1.z, 1.0f, -r0.x */
1044 struct r600_bytecode_alu alu;
1045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1046 alu.op = ALU_OP2_ADD;
1047 alu.src[0].sel = V_SQ_ALU_SRC_1;
1048 alu.src[1].sel = 1;
1049 alu.src[1].chan = 0;
1050 alu.src[1].neg = 1;
1051 alu.dst.sel = 1;
1052 alu.dst.chan = 2;
1053 alu.dst.write = 1;
1054 alu.last = 1;
1055 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1056 return r;
1057
1058 /* ADD r1.z, r1.z, -r1.y */
1059 alu.op = ALU_OP2_ADD;
1060 alu.src[0].sel = 1;
1061 alu.src[0].chan = 2;
1062 alu.src[1].sel = 1;
1063 alu.src[1].chan = 1;
1064 alu.src[1].neg = 1;
1065 alu.dst.sel = 1;
1066 alu.dst.chan = 2;
1067 alu.dst.write = 1;
1068 alu.last = 1;
1069 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1070 return r;
1071 break;
1072 }
1073 break;
1074 default:
1075 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1076 return -EINVAL;
1077 }
1078 return 0;
1079 }
1080
1081 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1082 {
1083 struct tgsi_parse_context parse;
1084 struct {
1085 boolean enabled;
1086 int *reg;
1087 unsigned name, alternate_name;
1088 } inputs[2] = {
1089 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1090
1091 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1092 };
1093 int num_regs = 0;
1094 unsigned k, i;
1095
1096 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1097 return 0;
1098 }
1099
1100 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1101 while (!tgsi_parse_end_of_tokens(&parse)) {
1102 tgsi_parse_token(&parse);
1103
1104 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1105 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1106 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1107 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1108 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1109 {
1110 int interpolate, location, k;
1111
1112 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1113 location = TGSI_INTERPOLATE_LOC_CENTER;
1114 inputs[1].enabled = true; /* needs SAMPLEID */
1115 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1116 location = TGSI_INTERPOLATE_LOC_CENTER;
1117 /* Needs sample positions, currently those are always available */
1118 } else {
1119 location = TGSI_INTERPOLATE_LOC_CENTROID;
1120 }
1121
1122 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1123 k = eg_get_interpolator_index(interpolate, location);
1124 if (k >= 0)
1125 ctx->eg_interpolators[k].enabled = true;
1126 }
1127 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1128 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1129 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1130 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1131 if (d->Semantic.Name == inputs[k].name ||
1132 d->Semantic.Name == inputs[k].alternate_name) {
1133 inputs[k].enabled = true;
1134 }
1135 }
1136 }
1137 }
1138 }
1139
1140 tgsi_parse_free(&parse);
1141
1142 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1143 boolean enabled = inputs[i].enabled;
1144 int *reg = inputs[i].reg;
1145 unsigned name = inputs[i].name;
1146
1147 if (enabled) {
1148 int gpr = gpr_offset + num_regs++;
1149 ctx->shader->nsys_inputs++;
1150
1151 // add to inputs, allocate a gpr
1152 k = ctx->shader->ninput++;
1153 ctx->shader->input[k].name = name;
1154 ctx->shader->input[k].sid = 0;
1155 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1156 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1157 *reg = ctx->shader->input[k].gpr = gpr;
1158 }
1159 }
1160
1161 return gpr_offset + num_regs;
1162 }
1163
1164 /*
1165 * for evergreen we need to scan the shader to find the number of GPRs we need to
1166 * reserve for interpolation and system values
1167 *
1168 * we need to know if we are going to emit
1169 * any sample or centroid inputs
1170 * if perspective and linear are required
1171 */
1172 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1173 {
1174 unsigned i;
1175 int num_baryc;
1176 struct tgsi_parse_context parse;
1177
1178 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1179
1180 for (i = 0; i < ctx->info.num_inputs; i++) {
1181 int k;
1182 /* skip position/face/mask/sampleid */
1183 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1184 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1185 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1186 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1187 continue;
1188
1189 k = eg_get_interpolator_index(
1190 ctx->info.input_interpolate[i],
1191 ctx->info.input_interpolate_loc[i]);
1192 if (k >= 0)
1193 ctx->eg_interpolators[k].enabled = TRUE;
1194 }
1195
1196 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1197 return 0;
1198 }
1199
1200 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1201 while (!tgsi_parse_end_of_tokens(&parse)) {
1202 tgsi_parse_token(&parse);
1203
1204 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1205 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1206 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1207 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1208 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1209 {
1210 int interpolate, location, k;
1211
1212 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1213 location = TGSI_INTERPOLATE_LOC_CENTER;
1214 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1215 location = TGSI_INTERPOLATE_LOC_CENTER;
1216 } else {
1217 location = TGSI_INTERPOLATE_LOC_CENTROID;
1218 }
1219
1220 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1221 k = eg_get_interpolator_index(interpolate, location);
1222 if (k >= 0)
1223 ctx->eg_interpolators[k].enabled = true;
1224 }
1225 }
1226 }
1227
1228 tgsi_parse_free(&parse);
1229
1230 /* assign gpr to each interpolator according to priority */
1231 num_baryc = 0;
1232 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1233 if (ctx->eg_interpolators[i].enabled) {
1234 ctx->eg_interpolators[i].ij_index = num_baryc;
1235 num_baryc ++;
1236 }
1237 }
1238
1239 /* XXX PULL MODEL and LINE STIPPLE */
1240
1241 num_baryc = (num_baryc + 1) >> 1;
1242 return allocate_system_value_inputs(ctx, num_baryc);
1243 }
1244
1245 /* sample_id_sel == NULL means fetch for current sample */
1246 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1247 {
1248 struct r600_bytecode_vtx vtx;
1249 int r, t1;
1250
1251 assert(ctx->fixed_pt_position_gpr != -1);
1252
1253 t1 = r600_get_temp(ctx);
1254
1255 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1256 vtx.op = FETCH_OP_VFETCH;
1257 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1258 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1259 if (sample_id == NULL) {
1260 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1261 vtx.src_sel_x = 3;
1262 }
1263 else {
1264 struct r600_bytecode_alu alu;
1265
1266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1267 alu.op = ALU_OP1_MOV;
1268 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1269 alu.dst.sel = t1;
1270 alu.dst.write = 1;
1271 alu.last = 1;
1272 r = r600_bytecode_add_alu(ctx->bc, &alu);
1273 if (r)
1274 return r;
1275
1276 vtx.src_gpr = t1;
1277 vtx.src_sel_x = 0;
1278 }
1279 vtx.mega_fetch_count = 16;
1280 vtx.dst_gpr = t1;
1281 vtx.dst_sel_x = 0;
1282 vtx.dst_sel_y = 1;
1283 vtx.dst_sel_z = 2;
1284 vtx.dst_sel_w = 3;
1285 vtx.data_format = FMT_32_32_32_32_FLOAT;
1286 vtx.num_format_all = 2;
1287 vtx.format_comp_all = 1;
1288 vtx.use_const_fields = 0;
1289 vtx.offset = 0;
1290 vtx.endian = r600_endian_swap(32);
1291 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1292
1293 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1294 if (r)
1295 return r;
1296
1297 return t1;
1298 }
1299
1300 static int eg_load_helper_invocation(struct r600_shader_ctx *ctx)
1301 {
1302 int r;
1303 struct r600_bytecode_alu alu;
1304
1305 /* do a vtx fetch with wqm set on the vtx fetch */
1306 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1307 alu.op = ALU_OP1_MOV;
1308 alu.dst.sel = ctx->helper_invoc_reg;
1309 alu.dst.chan = 0;
1310 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1311 alu.src[0].value = 0xffffffff;
1312 alu.dst.write = 1;
1313 alu.last = 1;
1314 r = r600_bytecode_add_alu(ctx->bc, &alu);
1315 if (r)
1316 return r;
1317
1318 /* do a vtx fetch in VPM mode */
1319 struct r600_bytecode_vtx vtx;
1320 memset(&vtx, 0, sizeof(vtx));
1321 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
1322 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1323 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1324 vtx.src_gpr = 0;
1325 vtx.mega_fetch_count = 16; /* no idea here really... */
1326 vtx.dst_gpr = ctx->helper_invoc_reg;
1327 vtx.dst_sel_x = 4;
1328 vtx.dst_sel_y = 7; /* SEL_Y */
1329 vtx.dst_sel_z = 7; /* SEL_Z */
1330 vtx.dst_sel_w = 7; /* SEL_W */
1331 vtx.data_format = FMT_32;
1332 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
1333 return r;
1334 ctx->bc->cf_last->vpm = 1;
1335 return 0;
1336 }
1337
1338 static int cm_load_helper_invocation(struct r600_shader_ctx *ctx)
1339 {
1340 int r;
1341 struct r600_bytecode_alu alu;
1342
1343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1344 alu.op = ALU_OP1_MOV;
1345 alu.dst.sel = ctx->helper_invoc_reg;
1346 alu.dst.chan = 0;
1347 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1348 alu.src[0].value = 0xffffffff;
1349 alu.dst.write = 1;
1350 alu.last = 1;
1351 r = r600_bytecode_add_alu(ctx->bc, &alu);
1352 if (r)
1353 return r;
1354
1355 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1356 alu.op = ALU_OP1_MOV;
1357 alu.dst.sel = ctx->helper_invoc_reg;
1358 alu.dst.chan = 0;
1359 alu.src[0].sel = V_SQ_ALU_SRC_0;
1360 alu.dst.write = 1;
1361 alu.last = 1;
1362 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_VALID_PIXEL_MODE);
1363 if (r)
1364 return r;
1365
1366 return ctx->helper_invoc_reg;
1367 }
1368
1369 static int load_block_grid_size(struct r600_shader_ctx *ctx, bool load_block)
1370 {
1371 struct r600_bytecode_vtx vtx;
1372 int r, t1;
1373
1374 if (ctx->cs_block_size_loaded)
1375 return ctx->cs_block_size_reg;
1376 if (ctx->cs_grid_size_loaded)
1377 return ctx->cs_grid_size_reg;
1378
1379 t1 = load_block ? ctx->cs_block_size_reg : ctx->cs_grid_size_reg;
1380 struct r600_bytecode_alu alu;
1381 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1382 alu.op = ALU_OP1_MOV;
1383 alu.src[0].sel = V_SQ_ALU_SRC_0;
1384 alu.dst.sel = t1;
1385 alu.dst.write = 1;
1386 alu.last = 1;
1387 r = r600_bytecode_add_alu(ctx->bc, &alu);
1388 if (r)
1389 return r;
1390
1391 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1392 vtx.op = FETCH_OP_VFETCH;
1393 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1394 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1395 vtx.src_gpr = t1;
1396 vtx.src_sel_x = 0;
1397
1398 vtx.mega_fetch_count = 16;
1399 vtx.dst_gpr = t1;
1400 vtx.dst_sel_x = 0;
1401 vtx.dst_sel_y = 1;
1402 vtx.dst_sel_z = 2;
1403 vtx.dst_sel_w = 7;
1404 vtx.data_format = FMT_32_32_32_32;
1405 vtx.num_format_all = 1;
1406 vtx.format_comp_all = 0;
1407 vtx.use_const_fields = 0;
1408 vtx.offset = load_block ? 0 : 16; // first element is size of buffer
1409 vtx.endian = r600_endian_swap(32);
1410 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1411
1412 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1413 if (r)
1414 return r;
1415
1416 if (load_block)
1417 ctx->cs_block_size_loaded = true;
1418 else
1419 ctx->cs_grid_size_loaded = true;
1420 return t1;
1421 }
1422
1423 static void tgsi_src(struct r600_shader_ctx *ctx,
1424 const struct tgsi_full_src_register *tgsi_src,
1425 struct r600_shader_src *r600_src)
1426 {
1427 memset(r600_src, 0, sizeof(*r600_src));
1428 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1429 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1430 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1431 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1432 r600_src->neg = tgsi_src->Register.Negate;
1433 r600_src->abs = tgsi_src->Register.Absolute;
1434
1435 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1436 int index;
1437 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1438 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1439 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1440
1441 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1442 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1443 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1444 return;
1445 }
1446 index = tgsi_src->Register.Index;
1447 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1448 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1449 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1450 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1451 r600_src->swizzle[0] = 2; // Z value
1452 r600_src->swizzle[1] = 2;
1453 r600_src->swizzle[2] = 2;
1454 r600_src->swizzle[3] = 2;
1455 r600_src->sel = ctx->face_gpr;
1456 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1457 r600_src->swizzle[0] = 3; // W value
1458 r600_src->swizzle[1] = 3;
1459 r600_src->swizzle[2] = 3;
1460 r600_src->swizzle[3] = 3;
1461 r600_src->sel = ctx->fixed_pt_position_gpr;
1462 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1463 r600_src->swizzle[0] = 0;
1464 r600_src->swizzle[1] = 1;
1465 r600_src->swizzle[2] = 4;
1466 r600_src->swizzle[3] = 4;
1467 r600_src->sel = load_sample_position(ctx, NULL, -1);
1468 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1469 r600_src->swizzle[0] = 3;
1470 r600_src->swizzle[1] = 3;
1471 r600_src->swizzle[2] = 3;
1472 r600_src->swizzle[3] = 3;
1473 r600_src->sel = 0;
1474 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1475 r600_src->swizzle[0] = 0;
1476 r600_src->swizzle[1] = 0;
1477 r600_src->swizzle[2] = 0;
1478 r600_src->swizzle[3] = 0;
1479 r600_src->sel = 0;
1480 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_THREAD_ID) {
1481 r600_src->sel = 0;
1482 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_ID) {
1483 r600_src->sel = 1;
1484 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1485 r600_src->swizzle[0] = 3;
1486 r600_src->swizzle[1] = 3;
1487 r600_src->swizzle[2] = 3;
1488 r600_src->swizzle[3] = 3;
1489 r600_src->sel = 1;
1490 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1491 r600_src->swizzle[0] = 2;
1492 r600_src->swizzle[1] = 2;
1493 r600_src->swizzle[2] = 2;
1494 r600_src->swizzle[3] = 2;
1495 r600_src->sel = 0;
1496 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1497 r600_src->sel = 1;
1498 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1499 r600_src->sel = 3;
1500 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1501 r600_src->sel = 2;
1502 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1503 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1504 r600_src->sel = ctx->tess_input_info;
1505 r600_src->swizzle[0] = 2;
1506 r600_src->swizzle[1] = 2;
1507 r600_src->swizzle[2] = 2;
1508 r600_src->swizzle[3] = 2;
1509 } else {
1510 r600_src->sel = ctx->tess_input_info;
1511 r600_src->swizzle[0] = 3;
1512 r600_src->swizzle[1] = 3;
1513 r600_src->swizzle[2] = 3;
1514 r600_src->swizzle[3] = 3;
1515 }
1516 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1517 r600_src->sel = 0;
1518 r600_src->swizzle[0] = 0;
1519 r600_src->swizzle[1] = 0;
1520 r600_src->swizzle[2] = 0;
1521 r600_src->swizzle[3] = 0;
1522 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1523 r600_src->sel = 0;
1524 r600_src->swizzle[0] = 3;
1525 r600_src->swizzle[1] = 3;
1526 r600_src->swizzle[2] = 3;
1527 r600_src->swizzle[3] = 3;
1528 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_GRID_SIZE) {
1529 r600_src->sel = load_block_grid_size(ctx, false);
1530 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_SIZE) {
1531 r600_src->sel = load_block_grid_size(ctx, true);
1532 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_HELPER_INVOCATION) {
1533 r600_src->sel = ctx->helper_invoc_reg;
1534 r600_src->swizzle[0] = 0;
1535 r600_src->swizzle[1] = 0;
1536 r600_src->swizzle[2] = 0;
1537 r600_src->swizzle[3] = 0;
1538 }
1539 } else {
1540 if (tgsi_src->Register.Indirect)
1541 r600_src->rel = V_SQ_REL_RELATIVE;
1542 r600_src->sel = tgsi_src->Register.Index;
1543 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1544 }
1545 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1546 if (tgsi_src->Register.Dimension) {
1547 r600_src->kc_bank = tgsi_src->Dimension.Index;
1548 if (tgsi_src->Dimension.Indirect) {
1549 r600_src->kc_rel = 1;
1550 }
1551 }
1552 }
1553 }
1554
1555 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1556 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1557 unsigned int dst_reg)
1558 {
1559 struct r600_bytecode_vtx vtx;
1560 unsigned int ar_reg;
1561 int r;
1562
1563 if (offset) {
1564 struct r600_bytecode_alu alu;
1565
1566 memset(&alu, 0, sizeof(alu));
1567
1568 alu.op = ALU_OP2_ADD_INT;
1569 alu.src[0].sel = ctx->bc->ar_reg;
1570 alu.src[0].chan = ar_chan;
1571
1572 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1573 alu.src[1].value = offset;
1574
1575 alu.dst.sel = dst_reg;
1576 alu.dst.chan = ar_chan;
1577 alu.dst.write = 1;
1578 alu.last = 1;
1579
1580 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1581 return r;
1582
1583 ar_reg = dst_reg;
1584 } else {
1585 ar_reg = ctx->bc->ar_reg;
1586 }
1587
1588 memset(&vtx, 0, sizeof(vtx));
1589 vtx.buffer_id = cb_idx;
1590 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1591 vtx.src_gpr = ar_reg;
1592 vtx.src_sel_x = ar_chan;
1593 vtx.mega_fetch_count = 16;
1594 vtx.dst_gpr = dst_reg;
1595 vtx.dst_sel_x = 0; /* SEL_X */
1596 vtx.dst_sel_y = 1; /* SEL_Y */
1597 vtx.dst_sel_z = 2; /* SEL_Z */
1598 vtx.dst_sel_w = 3; /* SEL_W */
1599 vtx.data_format = FMT_32_32_32_32_FLOAT;
1600 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1601 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1602 vtx.endian = r600_endian_swap(32);
1603 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1604
1605 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1606 return r;
1607
1608 return 0;
1609 }
1610
1611 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1612 {
1613 struct r600_bytecode_vtx vtx;
1614 int r;
1615 unsigned index = src->Register.Index;
1616 unsigned vtx_id = src->Dimension.Index;
1617 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1618 int offset_chan = vtx_id % 3;
1619 int t2 = 0;
1620
1621 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1622 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1623
1624 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1625 offset_chan = 3;
1626
1627 if (src->Dimension.Indirect || src->Register.Indirect)
1628 t2 = r600_get_temp(ctx);
1629
1630 if (src->Dimension.Indirect) {
1631 int treg[3];
1632 struct r600_bytecode_alu alu;
1633 int r, i;
1634 unsigned addr_reg;
1635 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1636 if (src->DimIndirect.Index > 0) {
1637 r = single_alu_op2(ctx, ALU_OP1_MOV,
1638 ctx->bc->ar_reg, 0,
1639 addr_reg, 0,
1640 0, 0);
1641 if (r)
1642 return r;
1643 }
1644 /*
1645 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1646 at least this is what fglrx seems to do. */
1647 for (i = 0; i < 3; i++) {
1648 treg[i] = r600_get_temp(ctx);
1649 }
1650 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1651
1652 for (i = 0; i < 3; i++) {
1653 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1654 alu.op = ALU_OP1_MOV;
1655 alu.src[0].sel = ctx->gs_rotated_input[0];
1656 alu.src[0].chan = i == 2 ? 3 : i;
1657 alu.dst.sel = treg[i];
1658 alu.dst.chan = 0;
1659 alu.dst.write = 1;
1660 alu.last = 1;
1661 r = r600_bytecode_add_alu(ctx->bc, &alu);
1662 if (r)
1663 return r;
1664 }
1665 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1666 alu.op = ALU_OP1_MOV;
1667 alu.src[0].sel = treg[0];
1668 alu.src[0].rel = 1;
1669 alu.dst.sel = t2;
1670 alu.dst.write = 1;
1671 alu.last = 1;
1672 r = r600_bytecode_add_alu(ctx->bc, &alu);
1673 if (r)
1674 return r;
1675 offset_reg = t2;
1676 offset_chan = 0;
1677 }
1678
1679 if (src->Register.Indirect) {
1680 int addr_reg;
1681 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1682
1683 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1684
1685 /* pull the value from index_reg */
1686 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1687 t2, 1,
1688 addr_reg, 0,
1689 V_SQ_ALU_SRC_LITERAL, first);
1690 if (r)
1691 return r;
1692 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1693 t2, 0,
1694 t2, 1,
1695 V_SQ_ALU_SRC_LITERAL, 4,
1696 offset_reg, offset_chan);
1697 if (r)
1698 return r;
1699 offset_reg = t2;
1700 offset_chan = 0;
1701 index = src->Register.Index - first;
1702 }
1703
1704 memset(&vtx, 0, sizeof(vtx));
1705 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1706 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1707 vtx.src_gpr = offset_reg;
1708 vtx.src_sel_x = offset_chan;
1709 vtx.offset = index * 16; /*bytes*/
1710 vtx.mega_fetch_count = 16;
1711 vtx.dst_gpr = dst_reg;
1712 vtx.dst_sel_x = 0; /* SEL_X */
1713 vtx.dst_sel_y = 1; /* SEL_Y */
1714 vtx.dst_sel_z = 2; /* SEL_Z */
1715 vtx.dst_sel_w = 3; /* SEL_W */
1716 if (ctx->bc->chip_class >= EVERGREEN) {
1717 vtx.use_const_fields = 1;
1718 } else {
1719 vtx.data_format = FMT_32_32_32_32_FLOAT;
1720 }
1721
1722 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1723 return r;
1724
1725 return 0;
1726 }
1727
1728 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1729 {
1730 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1731 unsigned i;
1732
1733 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1734 struct tgsi_full_src_register *src = &inst->Src[i];
1735
1736 if (src->Register.File == TGSI_FILE_INPUT) {
1737 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1738 /* primitive id is in R0.z */
1739 ctx->src[i].sel = 0;
1740 ctx->src[i].swizzle[0] = 2;
1741 }
1742 }
1743 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1744 int treg = r600_get_temp(ctx);
1745
1746 fetch_gs_input(ctx, src, treg);
1747 ctx->src[i].sel = treg;
1748 ctx->src[i].rel = 0;
1749 }
1750 }
1751 return 0;
1752 }
1753
1754
1755 /* Tessellation shaders pass outputs to the next shader using LDS.
1756 *
1757 * LS outputs = TCS(HS) inputs
1758 * TCS(HS) outputs = TES(DS) inputs
1759 *
1760 * The LDS layout is:
1761 * - TCS inputs for patch 0
1762 * - TCS inputs for patch 1
1763 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1764 * - ...
1765 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1766 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1767 * - TCS outputs for patch 1
1768 * - Per-patch TCS outputs for patch 1
1769 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1770 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1771 * - ...
1772 *
1773 * All three shaders VS(LS), TCS, TES share the same LDS space.
1774 */
1775 /* this will return with the dw address in temp_reg.x */
1776 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1777 const struct tgsi_full_dst_register *dst,
1778 const struct tgsi_full_src_register *src,
1779 int stride_bytes_reg, int stride_bytes_chan)
1780 {
1781 struct tgsi_full_dst_register reg;
1782 ubyte *name, *index, *array_first;
1783 int r;
1784 int param;
1785 struct tgsi_shader_info *info = &ctx->info;
1786 /* Set the register description. The address computation is the same
1787 * for sources and destinations. */
1788 if (src) {
1789 reg.Register.File = src->Register.File;
1790 reg.Register.Index = src->Register.Index;
1791 reg.Register.Indirect = src->Register.Indirect;
1792 reg.Register.Dimension = src->Register.Dimension;
1793 reg.Indirect = src->Indirect;
1794 reg.Dimension = src->Dimension;
1795 reg.DimIndirect = src->DimIndirect;
1796 } else
1797 reg = *dst;
1798
1799 /* If the register is 2-dimensional (e.g. an array of vertices
1800 * in a primitive), calculate the base address of the vertex. */
1801 if (reg.Register.Dimension) {
1802 int sel, chan;
1803 if (reg.Dimension.Indirect) {
1804 unsigned addr_reg;
1805 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1806
1807 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1808 /* pull the value from index_reg */
1809 sel = addr_reg;
1810 chan = 0;
1811 } else {
1812 sel = V_SQ_ALU_SRC_LITERAL;
1813 chan = reg.Dimension.Index;
1814 }
1815
1816 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1817 temp_reg, 0,
1818 stride_bytes_reg, stride_bytes_chan,
1819 sel, chan,
1820 temp_reg, 0);
1821 if (r)
1822 return r;
1823 }
1824
1825 if (reg.Register.File == TGSI_FILE_INPUT) {
1826 name = info->input_semantic_name;
1827 index = info->input_semantic_index;
1828 array_first = info->input_array_first;
1829 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1830 name = info->output_semantic_name;
1831 index = info->output_semantic_index;
1832 array_first = info->output_array_first;
1833 } else {
1834 assert(0);
1835 return -1;
1836 }
1837 if (reg.Register.Indirect) {
1838 int addr_reg;
1839 int first;
1840 /* Add the relative address of the element. */
1841 if (reg.Indirect.ArrayID)
1842 first = array_first[reg.Indirect.ArrayID];
1843 else
1844 first = reg.Register.Index;
1845
1846 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1847
1848 /* pull the value from index_reg */
1849 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1850 temp_reg, 0,
1851 V_SQ_ALU_SRC_LITERAL, 16,
1852 addr_reg, 0,
1853 temp_reg, 0);
1854 if (r)
1855 return r;
1856
1857 param = r600_get_lds_unique_index(name[first],
1858 index[first]);
1859
1860 } else {
1861 param = r600_get_lds_unique_index(name[reg.Register.Index],
1862 index[reg.Register.Index]);
1863 }
1864
1865 /* add to base_addr - passed in temp_reg.x */
1866 if (param) {
1867 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1868 temp_reg, 0,
1869 temp_reg, 0,
1870 V_SQ_ALU_SRC_LITERAL, param * 16);
1871 if (r)
1872 return r;
1873
1874 }
1875 return 0;
1876 }
1877
1878 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1879 unsigned dst_reg, unsigned mask)
1880 {
1881 struct r600_bytecode_alu alu;
1882 int r, i, lasti;
1883
1884 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1885 ctx->bc->force_add_cf = 1;
1886
1887 lasti = tgsi_last_instruction(mask);
1888 for (i = 1; i <= lasti; i++) {
1889 if (!(mask & (1 << i)))
1890 continue;
1891
1892 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1893 temp_reg, i,
1894 temp_reg, 0,
1895 V_SQ_ALU_SRC_LITERAL, 4 * i);
1896 if (r)
1897 return r;
1898 }
1899 for (i = 0; i <= lasti; i++) {
1900 if (!(mask & (1 << i)))
1901 continue;
1902
1903 /* emit an LDS_READ_RET */
1904 memset(&alu, 0, sizeof(alu));
1905 alu.op = LDS_OP1_LDS_READ_RET;
1906 alu.src[0].sel = temp_reg;
1907 alu.src[0].chan = i;
1908 alu.src[1].sel = V_SQ_ALU_SRC_0;
1909 alu.src[2].sel = V_SQ_ALU_SRC_0;
1910 alu.dst.chan = 0;
1911 alu.is_lds_idx_op = true;
1912 alu.last = 1;
1913 r = r600_bytecode_add_alu(ctx->bc, &alu);
1914 if (r)
1915 return r;
1916 }
1917 for (i = 0; i <= lasti; i++) {
1918 if (!(mask & (1 << i)))
1919 continue;
1920
1921 /* then read from LDS_OQ_A_POP */
1922 memset(&alu, 0, sizeof(alu));
1923
1924 alu.op = ALU_OP1_MOV;
1925 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1926 alu.src[0].chan = 0;
1927 alu.dst.sel = dst_reg;
1928 alu.dst.chan = i;
1929 alu.dst.write = 1;
1930 alu.last = 1;
1931 r = r600_bytecode_add_alu(ctx->bc, &alu);
1932 if (r)
1933 return r;
1934 }
1935 return 0;
1936 }
1937
1938 static int fetch_mask(struct tgsi_src_register *reg)
1939 {
1940 int mask = 0;
1941 mask |= 1 << reg->SwizzleX;
1942 mask |= 1 << reg->SwizzleY;
1943 mask |= 1 << reg->SwizzleZ;
1944 mask |= 1 << reg->SwizzleW;
1945 return mask;
1946 }
1947
1948 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1949 {
1950 int r;
1951 unsigned temp_reg = r600_get_temp(ctx);
1952
1953 r = get_lds_offset0(ctx, 2, temp_reg,
1954 src->Register.Dimension ? false : true);
1955 if (r)
1956 return r;
1957
1958 /* the base address is now in temp.x */
1959 r = r600_get_byte_address(ctx, temp_reg,
1960 NULL, src, ctx->tess_output_info, 1);
1961 if (r)
1962 return r;
1963
1964 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1965 if (r)
1966 return r;
1967 return 0;
1968 }
1969
1970 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1971 {
1972 int r;
1973 unsigned temp_reg = r600_get_temp(ctx);
1974
1975 /* t.x = ips * r0.y */
1976 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1977 temp_reg, 0,
1978 ctx->tess_input_info, 0,
1979 0, 1);
1980
1981 if (r)
1982 return r;
1983
1984 /* the base address is now in temp.x */
1985 r = r600_get_byte_address(ctx, temp_reg,
1986 NULL, src, ctx->tess_input_info, 1);
1987 if (r)
1988 return r;
1989
1990 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1991 if (r)
1992 return r;
1993 return 0;
1994 }
1995
1996 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1997 {
1998 int r;
1999 unsigned temp_reg = r600_get_temp(ctx);
2000
2001 r = get_lds_offset0(ctx, 1, temp_reg,
2002 src->Register.Dimension ? false : true);
2003 if (r)
2004 return r;
2005 /* the base address is now in temp.x */
2006 r = r600_get_byte_address(ctx, temp_reg,
2007 NULL, src,
2008 ctx->tess_output_info, 1);
2009 if (r)
2010 return r;
2011
2012 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2013 if (r)
2014 return r;
2015 return 0;
2016 }
2017
2018 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
2019 {
2020 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2021 unsigned i;
2022
2023 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2024 struct tgsi_full_src_register *src = &inst->Src[i];
2025
2026 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
2027 int treg = r600_get_temp(ctx);
2028 fetch_tes_input(ctx, src, treg);
2029 ctx->src[i].sel = treg;
2030 ctx->src[i].rel = 0;
2031 }
2032 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
2033 int treg = r600_get_temp(ctx);
2034 fetch_tcs_input(ctx, src, treg);
2035 ctx->src[i].sel = treg;
2036 ctx->src[i].rel = 0;
2037 }
2038 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
2039 int treg = r600_get_temp(ctx);
2040 fetch_tcs_output(ctx, src, treg);
2041 ctx->src[i].sel = treg;
2042 ctx->src[i].rel = 0;
2043 }
2044 }
2045 return 0;
2046 }
2047
2048 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
2049 {
2050 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2051 struct r600_bytecode_alu alu;
2052 int i, j, k, nconst, r;
2053
2054 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
2055 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
2056 nconst++;
2057 }
2058 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
2059 }
2060 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
2061 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
2062 continue;
2063 }
2064
2065 if (ctx->src[i].rel) {
2066 int chan = inst->Src[i].Indirect.Swizzle;
2067 int treg = r600_get_temp(ctx);
2068 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
2069 return r;
2070
2071 ctx->src[i].kc_bank = 0;
2072 ctx->src[i].kc_rel = 0;
2073 ctx->src[i].sel = treg;
2074 ctx->src[i].rel = 0;
2075 j--;
2076 } else if (j > 0) {
2077 int treg = r600_get_temp(ctx);
2078 for (k = 0; k < 4; k++) {
2079 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2080 alu.op = ALU_OP1_MOV;
2081 alu.src[0].sel = ctx->src[i].sel;
2082 alu.src[0].chan = k;
2083 alu.src[0].rel = ctx->src[i].rel;
2084 alu.src[0].kc_bank = ctx->src[i].kc_bank;
2085 alu.src[0].kc_rel = ctx->src[i].kc_rel;
2086 alu.dst.sel = treg;
2087 alu.dst.chan = k;
2088 alu.dst.write = 1;
2089 if (k == 3)
2090 alu.last = 1;
2091 r = r600_bytecode_add_alu(ctx->bc, &alu);
2092 if (r)
2093 return r;
2094 }
2095 ctx->src[i].sel = treg;
2096 ctx->src[i].rel =0;
2097 j--;
2098 }
2099 }
2100 return 0;
2101 }
2102
2103 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
2104 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
2105 {
2106 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2107 struct r600_bytecode_alu alu;
2108 int i, j, k, nliteral, r;
2109
2110 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
2111 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2112 nliteral++;
2113 }
2114 }
2115 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
2116 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2117 int treg = r600_get_temp(ctx);
2118 for (k = 0; k < 4; k++) {
2119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2120 alu.op = ALU_OP1_MOV;
2121 alu.src[0].sel = ctx->src[i].sel;
2122 alu.src[0].chan = k;
2123 alu.src[0].value = ctx->src[i].value[k];
2124 alu.dst.sel = treg;
2125 alu.dst.chan = k;
2126 alu.dst.write = 1;
2127 if (k == 3)
2128 alu.last = 1;
2129 r = r600_bytecode_add_alu(ctx->bc, &alu);
2130 if (r)
2131 return r;
2132 }
2133 ctx->src[i].sel = treg;
2134 j--;
2135 }
2136 }
2137 return 0;
2138 }
2139
2140 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
2141 {
2142 int i, r, count = ctx->shader->ninput;
2143
2144 for (i = 0; i < count; i++) {
2145 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2146 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
2147 if (r)
2148 return r;
2149 }
2150 }
2151 return 0;
2152 }
2153
2154 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2155 int stream, unsigned *stream_item_size UNUSED)
2156 {
2157 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2158 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2159 int j, r;
2160 unsigned i;
2161
2162 /* Sanity checking. */
2163 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2164 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2165 r = -EINVAL;
2166 goto out_err;
2167 }
2168 for (i = 0; i < so->num_outputs; i++) {
2169 if (so->output[i].output_buffer >= 4) {
2170 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2171 so->output[i].output_buffer);
2172 r = -EINVAL;
2173 goto out_err;
2174 }
2175 }
2176
2177 /* Initialize locations where the outputs are stored. */
2178 for (i = 0; i < so->num_outputs; i++) {
2179
2180 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2181 start_comp[i] = so->output[i].start_component;
2182 /* Lower outputs with dst_offset < start_component.
2183 *
2184 * We can only output 4D vectors with a write mask, e.g. we can
2185 * only output the W component at offset 3, etc. If we want
2186 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2187 * to move it to X and output X. */
2188 if (so->output[i].dst_offset < so->output[i].start_component) {
2189 unsigned tmp = r600_get_temp(ctx);
2190
2191 for (j = 0; j < so->output[i].num_components; j++) {
2192 struct r600_bytecode_alu alu;
2193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2194 alu.op = ALU_OP1_MOV;
2195 alu.src[0].sel = so_gpr[i];
2196 alu.src[0].chan = so->output[i].start_component + j;
2197
2198 alu.dst.sel = tmp;
2199 alu.dst.chan = j;
2200 alu.dst.write = 1;
2201 if (j == so->output[i].num_components - 1)
2202 alu.last = 1;
2203 r = r600_bytecode_add_alu(ctx->bc, &alu);
2204 if (r)
2205 return r;
2206 }
2207 start_comp[i] = 0;
2208 so_gpr[i] = tmp;
2209 }
2210 }
2211
2212 /* Write outputs to buffers. */
2213 for (i = 0; i < so->num_outputs; i++) {
2214 struct r600_bytecode_output output;
2215
2216 if (stream != -1 && stream != so->output[i].stream)
2217 continue;
2218
2219 memset(&output, 0, sizeof(struct r600_bytecode_output));
2220 output.gpr = so_gpr[i];
2221 output.elem_size = so->output[i].num_components - 1;
2222 if (output.elem_size == 2)
2223 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2224 output.array_base = so->output[i].dst_offset - start_comp[i];
2225 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2226 output.burst_count = 1;
2227 /* array_size is an upper limit for the burst_count
2228 * with MEM_STREAM instructions */
2229 output.array_size = 0xFFF;
2230 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2231
2232 if (ctx->bc->chip_class >= EVERGREEN) {
2233 switch (so->output[i].output_buffer) {
2234 case 0:
2235 output.op = CF_OP_MEM_STREAM0_BUF0;
2236 break;
2237 case 1:
2238 output.op = CF_OP_MEM_STREAM0_BUF1;
2239 break;
2240 case 2:
2241 output.op = CF_OP_MEM_STREAM0_BUF2;
2242 break;
2243 case 3:
2244 output.op = CF_OP_MEM_STREAM0_BUF3;
2245 break;
2246 }
2247 output.op += so->output[i].stream * 4;
2248 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2249 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2250 } else {
2251 switch (so->output[i].output_buffer) {
2252 case 0:
2253 output.op = CF_OP_MEM_STREAM0;
2254 break;
2255 case 1:
2256 output.op = CF_OP_MEM_STREAM1;
2257 break;
2258 case 2:
2259 output.op = CF_OP_MEM_STREAM2;
2260 break;
2261 case 3:
2262 output.op = CF_OP_MEM_STREAM3;
2263 break;
2264 }
2265 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2266 }
2267 r = r600_bytecode_add_output(ctx->bc, &output);
2268 if (r)
2269 goto out_err;
2270 }
2271 return 0;
2272 out_err:
2273 return r;
2274 }
2275
2276 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2277 {
2278 struct r600_bytecode_alu alu;
2279 unsigned reg;
2280
2281 if (!ctx->shader->vs_out_edgeflag)
2282 return;
2283
2284 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2285
2286 /* clamp(x, 0, 1) */
2287 memset(&alu, 0, sizeof(alu));
2288 alu.op = ALU_OP1_MOV;
2289 alu.src[0].sel = reg;
2290 alu.dst.sel = reg;
2291 alu.dst.write = 1;
2292 alu.dst.clamp = 1;
2293 alu.last = 1;
2294 r600_bytecode_add_alu(ctx->bc, &alu);
2295
2296 memset(&alu, 0, sizeof(alu));
2297 alu.op = ALU_OP1_FLT_TO_INT;
2298 alu.src[0].sel = reg;
2299 alu.dst.sel = reg;
2300 alu.dst.write = 1;
2301 alu.last = 1;
2302 r600_bytecode_add_alu(ctx->bc, &alu);
2303 }
2304
2305 static int generate_gs_copy_shader(struct r600_context *rctx,
2306 struct r600_pipe_shader *gs,
2307 struct pipe_stream_output_info *so)
2308 {
2309 struct r600_shader_ctx ctx = {};
2310 struct r600_shader *gs_shader = &gs->shader;
2311 struct r600_pipe_shader *cshader;
2312 unsigned ocnt = gs_shader->noutput;
2313 struct r600_bytecode_alu alu;
2314 struct r600_bytecode_vtx vtx;
2315 struct r600_bytecode_output output;
2316 struct r600_bytecode_cf *cf_jump, *cf_pop,
2317 *last_exp_pos = NULL, *last_exp_param = NULL;
2318 int next_clip_pos = 61, next_param = 0;
2319 unsigned i, j;
2320 int ring;
2321 bool only_ring_0 = true;
2322 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2323 if (!cshader)
2324 return 0;
2325
2326 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2327 sizeof(struct r600_shader_io));
2328
2329 cshader->shader.noutput = ocnt;
2330
2331 ctx.shader = &cshader->shader;
2332 ctx.bc = &ctx.shader->bc;
2333 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2334
2335 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2336 rctx->screen->has_compressed_msaa_texturing);
2337
2338 ctx.bc->isa = rctx->isa;
2339
2340 cf_jump = NULL;
2341 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2342
2343 /* R0.x = R0.x & 0x3fffffff */
2344 memset(&alu, 0, sizeof(alu));
2345 alu.op = ALU_OP2_AND_INT;
2346 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2347 alu.src[1].value = 0x3fffffff;
2348 alu.dst.write = 1;
2349 r600_bytecode_add_alu(ctx.bc, &alu);
2350
2351 /* R0.y = R0.x >> 30 */
2352 memset(&alu, 0, sizeof(alu));
2353 alu.op = ALU_OP2_LSHR_INT;
2354 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2355 alu.src[1].value = 0x1e;
2356 alu.dst.chan = 1;
2357 alu.dst.write = 1;
2358 alu.last = 1;
2359 r600_bytecode_add_alu(ctx.bc, &alu);
2360
2361 /* fetch vertex data from GSVS ring */
2362 for (i = 0; i < ocnt; ++i) {
2363 struct r600_shader_io *out = &ctx.shader->output[i];
2364
2365 out->gpr = i + 1;
2366 out->ring_offset = i * 16;
2367
2368 memset(&vtx, 0, sizeof(vtx));
2369 vtx.op = FETCH_OP_VFETCH;
2370 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2371 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2372 vtx.mega_fetch_count = 16;
2373 vtx.offset = out->ring_offset;
2374 vtx.dst_gpr = out->gpr;
2375 vtx.src_gpr = 0;
2376 vtx.dst_sel_x = 0;
2377 vtx.dst_sel_y = 1;
2378 vtx.dst_sel_z = 2;
2379 vtx.dst_sel_w = 3;
2380 if (rctx->b.chip_class >= EVERGREEN) {
2381 vtx.use_const_fields = 1;
2382 } else {
2383 vtx.data_format = FMT_32_32_32_32_FLOAT;
2384 }
2385
2386 r600_bytecode_add_vtx(ctx.bc, &vtx);
2387 }
2388 ctx.temp_reg = i + 1;
2389 for (ring = 3; ring >= 0; --ring) {
2390 bool enabled = false;
2391 for (i = 0; i < so->num_outputs; i++) {
2392 if (so->output[i].stream == ring) {
2393 enabled = true;
2394 if (ring > 0)
2395 only_ring_0 = false;
2396 break;
2397 }
2398 }
2399 if (ring != 0 && !enabled) {
2400 cshader->shader.ring_item_sizes[ring] = 0;
2401 continue;
2402 }
2403
2404 if (cf_jump) {
2405 // Patch up jump label
2406 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2407 cf_pop = ctx.bc->cf_last;
2408
2409 cf_jump->cf_addr = cf_pop->id + 2;
2410 cf_jump->pop_count = 1;
2411 cf_pop->cf_addr = cf_pop->id + 2;
2412 cf_pop->pop_count = 1;
2413 }
2414
2415 /* PRED_SETE_INT __, R0.y, ring */
2416 memset(&alu, 0, sizeof(alu));
2417 alu.op = ALU_OP2_PRED_SETE_INT;
2418 alu.src[0].chan = 1;
2419 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2420 alu.src[1].value = ring;
2421 alu.execute_mask = 1;
2422 alu.update_pred = 1;
2423 alu.last = 1;
2424 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2425
2426 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2427 cf_jump = ctx.bc->cf_last;
2428
2429 if (enabled)
2430 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2431 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2432 }
2433
2434 /* bc adds nops - copy it */
2435 if (ctx.bc->chip_class == R600) {
2436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2437 alu.op = ALU_OP0_NOP;
2438 alu.last = 1;
2439 r600_bytecode_add_alu(ctx.bc, &alu);
2440
2441 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2442 }
2443
2444 /* export vertex data */
2445 /* XXX factor out common code with r600_shader_from_tgsi ? */
2446 for (i = 0; i < ocnt; ++i) {
2447 struct r600_shader_io *out = &ctx.shader->output[i];
2448 bool instream0 = true;
2449 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2450 continue;
2451
2452 for (j = 0; j < so->num_outputs; j++) {
2453 if (so->output[j].register_index == i) {
2454 if (so->output[j].stream == 0)
2455 break;
2456 if (so->output[j].stream > 0)
2457 instream0 = false;
2458 }
2459 }
2460 if (!instream0)
2461 continue;
2462 memset(&output, 0, sizeof(output));
2463 output.gpr = out->gpr;
2464 output.elem_size = 3;
2465 output.swizzle_x = 0;
2466 output.swizzle_y = 1;
2467 output.swizzle_z = 2;
2468 output.swizzle_w = 3;
2469 output.burst_count = 1;
2470 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2471 output.op = CF_OP_EXPORT;
2472 switch (out->name) {
2473 case TGSI_SEMANTIC_POSITION:
2474 output.array_base = 60;
2475 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2476 break;
2477
2478 case TGSI_SEMANTIC_PSIZE:
2479 output.array_base = 61;
2480 if (next_clip_pos == 61)
2481 next_clip_pos = 62;
2482 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2483 output.swizzle_y = 7;
2484 output.swizzle_z = 7;
2485 output.swizzle_w = 7;
2486 ctx.shader->vs_out_misc_write = 1;
2487 ctx.shader->vs_out_point_size = 1;
2488 break;
2489 case TGSI_SEMANTIC_LAYER:
2490 if (out->spi_sid) {
2491 /* duplicate it as PARAM to pass to the pixel shader */
2492 output.array_base = next_param++;
2493 r600_bytecode_add_output(ctx.bc, &output);
2494 last_exp_param = ctx.bc->cf_last;
2495 }
2496 output.array_base = 61;
2497 if (next_clip_pos == 61)
2498 next_clip_pos = 62;
2499 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2500 output.swizzle_x = 7;
2501 output.swizzle_y = 7;
2502 output.swizzle_z = 0;
2503 output.swizzle_w = 7;
2504 ctx.shader->vs_out_misc_write = 1;
2505 ctx.shader->vs_out_layer = 1;
2506 break;
2507 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2508 if (out->spi_sid) {
2509 /* duplicate it as PARAM to pass to the pixel shader */
2510 output.array_base = next_param++;
2511 r600_bytecode_add_output(ctx.bc, &output);
2512 last_exp_param = ctx.bc->cf_last;
2513 }
2514 output.array_base = 61;
2515 if (next_clip_pos == 61)
2516 next_clip_pos = 62;
2517 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2518 ctx.shader->vs_out_misc_write = 1;
2519 ctx.shader->vs_out_viewport = 1;
2520 output.swizzle_x = 7;
2521 output.swizzle_y = 7;
2522 output.swizzle_z = 7;
2523 output.swizzle_w = 0;
2524 break;
2525 case TGSI_SEMANTIC_CLIPDIST:
2526 /* spi_sid is 0 for clipdistance outputs that were generated
2527 * for clipvertex - we don't need to pass them to PS */
2528 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2529 ctx.shader->cull_dist_write = gs->shader.cull_dist_write;
2530 ctx.shader->cc_dist_mask = gs->shader.cc_dist_mask;
2531 if (out->spi_sid) {
2532 /* duplicate it as PARAM to pass to the pixel shader */
2533 output.array_base = next_param++;
2534 r600_bytecode_add_output(ctx.bc, &output);
2535 last_exp_param = ctx.bc->cf_last;
2536 }
2537 output.array_base = next_clip_pos++;
2538 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2539 break;
2540 case TGSI_SEMANTIC_FOG:
2541 output.swizzle_y = 4; /* 0 */
2542 output.swizzle_z = 4; /* 0 */
2543 output.swizzle_w = 5; /* 1 */
2544 break;
2545 default:
2546 output.array_base = next_param++;
2547 break;
2548 }
2549 r600_bytecode_add_output(ctx.bc, &output);
2550 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2551 last_exp_param = ctx.bc->cf_last;
2552 else
2553 last_exp_pos = ctx.bc->cf_last;
2554 }
2555
2556 if (!last_exp_pos) {
2557 memset(&output, 0, sizeof(output));
2558 output.gpr = 0;
2559 output.elem_size = 3;
2560 output.swizzle_x = 7;
2561 output.swizzle_y = 7;
2562 output.swizzle_z = 7;
2563 output.swizzle_w = 7;
2564 output.burst_count = 1;
2565 output.type = 2;
2566 output.op = CF_OP_EXPORT;
2567 output.array_base = 60;
2568 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2569 r600_bytecode_add_output(ctx.bc, &output);
2570 last_exp_pos = ctx.bc->cf_last;
2571 }
2572
2573 if (!last_exp_param) {
2574 memset(&output, 0, sizeof(output));
2575 output.gpr = 0;
2576 output.elem_size = 3;
2577 output.swizzle_x = 7;
2578 output.swizzle_y = 7;
2579 output.swizzle_z = 7;
2580 output.swizzle_w = 7;
2581 output.burst_count = 1;
2582 output.type = 2;
2583 output.op = CF_OP_EXPORT;
2584 output.array_base = next_param++;
2585 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2586 r600_bytecode_add_output(ctx.bc, &output);
2587 last_exp_param = ctx.bc->cf_last;
2588 }
2589
2590 last_exp_pos->op = CF_OP_EXPORT_DONE;
2591 last_exp_param->op = CF_OP_EXPORT_DONE;
2592
2593 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2594 cf_pop = ctx.bc->cf_last;
2595
2596 cf_jump->cf_addr = cf_pop->id + 2;
2597 cf_jump->pop_count = 1;
2598 cf_pop->cf_addr = cf_pop->id + 2;
2599 cf_pop->pop_count = 1;
2600
2601 if (ctx.bc->chip_class == CAYMAN)
2602 cm_bytecode_add_cf_end(ctx.bc);
2603 else {
2604 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2605 ctx.bc->cf_last->end_of_program = 1;
2606 }
2607
2608 gs->gs_copy_shader = cshader;
2609 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2610
2611 ctx.bc->nstack = 1;
2612
2613 return r600_bytecode_build(ctx.bc);
2614 }
2615
2616 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2617 {
2618 if (ind) {
2619 struct r600_bytecode_alu alu;
2620 int r;
2621
2622 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2623 alu.op = ALU_OP2_ADD_INT;
2624 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2625 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2626 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2627 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2628 alu.dst.write = 1;
2629 alu.last = 1;
2630 r = r600_bytecode_add_alu(ctx->bc, &alu);
2631 if (r)
2632 return r;
2633 }
2634 return 0;
2635 }
2636
2637 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so UNUSED, int stream, bool ind)
2638 {
2639 struct r600_bytecode_output output;
2640 int ring_offset;
2641 unsigned i, k;
2642 int effective_stream = stream == -1 ? 0 : stream;
2643 int idx = 0;
2644
2645 for (i = 0; i < ctx->shader->noutput; i++) {
2646 if (ctx->gs_for_vs) {
2647 /* for ES we need to lookup corresponding ring offset expected by GS
2648 * (map this output to GS input by name and sid) */
2649 /* FIXME precompute offsets */
2650 ring_offset = -1;
2651 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2652 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2653 struct r600_shader_io *out = &ctx->shader->output[i];
2654 if (in->name == out->name && in->sid == out->sid)
2655 ring_offset = in->ring_offset;
2656 }
2657
2658 if (ring_offset == -1)
2659 continue;
2660 } else {
2661 ring_offset = idx * 16;
2662 idx++;
2663 }
2664
2665 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2666 continue;
2667 /* next_ring_offset after parsing input decls contains total size of
2668 * single vertex data, gs_next_vertex - current vertex index */
2669 if (!ind)
2670 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2671
2672 memset(&output, 0, sizeof(struct r600_bytecode_output));
2673 output.gpr = ctx->shader->output[i].gpr;
2674 output.elem_size = 3;
2675 output.comp_mask = 0xF;
2676 output.burst_count = 1;
2677
2678 if (ind)
2679 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2680 else
2681 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2682
2683 switch (stream) {
2684 default:
2685 case 0:
2686 output.op = CF_OP_MEM_RING; break;
2687 case 1:
2688 output.op = CF_OP_MEM_RING1; break;
2689 case 2:
2690 output.op = CF_OP_MEM_RING2; break;
2691 case 3:
2692 output.op = CF_OP_MEM_RING3; break;
2693 }
2694
2695 if (ind) {
2696 output.array_base = ring_offset >> 2; /* in dwords */
2697 output.array_size = 0xfff;
2698 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2699 } else
2700 output.array_base = ring_offset >> 2; /* in dwords */
2701 r600_bytecode_add_output(ctx->bc, &output);
2702 }
2703
2704 ++ctx->gs_next_vertex;
2705 return 0;
2706 }
2707
2708
2709 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2710 {
2711 int r;
2712 struct r600_bytecode_vtx vtx;
2713 int temp_val = ctx->temp_reg;
2714 /* need to store the TCS output somewhere */
2715 r = single_alu_op2(ctx, ALU_OP1_MOV,
2716 temp_val, 0,
2717 V_SQ_ALU_SRC_LITERAL, 0,
2718 0, 0);
2719 if (r)
2720 return r;
2721
2722 /* used by VS/TCS */
2723 if (ctx->tess_input_info) {
2724 /* fetch tcs input values into resv space */
2725 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2726 vtx.op = FETCH_OP_VFETCH;
2727 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2728 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2729 vtx.mega_fetch_count = 16;
2730 vtx.data_format = FMT_32_32_32_32;
2731 vtx.num_format_all = 2;
2732 vtx.format_comp_all = 1;
2733 vtx.use_const_fields = 0;
2734 vtx.endian = r600_endian_swap(32);
2735 vtx.srf_mode_all = 1;
2736 vtx.offset = 0;
2737 vtx.dst_gpr = ctx->tess_input_info;
2738 vtx.dst_sel_x = 0;
2739 vtx.dst_sel_y = 1;
2740 vtx.dst_sel_z = 2;
2741 vtx.dst_sel_w = 3;
2742 vtx.src_gpr = temp_val;
2743 vtx.src_sel_x = 0;
2744
2745 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2746 if (r)
2747 return r;
2748 }
2749
2750 /* used by TCS/TES */
2751 if (ctx->tess_output_info) {
2752 /* fetch tcs output values into resv space */
2753 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2754 vtx.op = FETCH_OP_VFETCH;
2755 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2756 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2757 vtx.mega_fetch_count = 16;
2758 vtx.data_format = FMT_32_32_32_32;
2759 vtx.num_format_all = 2;
2760 vtx.format_comp_all = 1;
2761 vtx.use_const_fields = 0;
2762 vtx.endian = r600_endian_swap(32);
2763 vtx.srf_mode_all = 1;
2764 vtx.offset = 16;
2765 vtx.dst_gpr = ctx->tess_output_info;
2766 vtx.dst_sel_x = 0;
2767 vtx.dst_sel_y = 1;
2768 vtx.dst_sel_z = 2;
2769 vtx.dst_sel_w = 3;
2770 vtx.src_gpr = temp_val;
2771 vtx.src_sel_x = 0;
2772
2773 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2774 if (r)
2775 return r;
2776 }
2777 return 0;
2778 }
2779
2780 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2781 {
2782 int j, r;
2783 int temp_reg;
2784 unsigned i;
2785
2786 /* fetch tcs input values into input_vals */
2787 ctx->tess_input_info = r600_get_temp(ctx);
2788 ctx->tess_output_info = 0;
2789 r = r600_fetch_tess_io_info(ctx);
2790 if (r)
2791 return r;
2792
2793 temp_reg = r600_get_temp(ctx);
2794 /* dst reg contains LDS address stride * idx */
2795 /* MUL vertexID, vertex_dw_stride */
2796 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2797 temp_reg, 0,
2798 ctx->tess_input_info, 1,
2799 0, 1); /* rel id in r0.y? */
2800 if (r)
2801 return r;
2802
2803 for (i = 0; i < ctx->shader->noutput; i++) {
2804 struct r600_bytecode_alu alu;
2805 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2806
2807 if (param) {
2808 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2809 temp_reg, 1,
2810 temp_reg, 0,
2811 V_SQ_ALU_SRC_LITERAL, param * 16);
2812 if (r)
2813 return r;
2814 }
2815
2816 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2817 temp_reg, 2,
2818 temp_reg, param ? 1 : 0,
2819 V_SQ_ALU_SRC_LITERAL, 8);
2820 if (r)
2821 return r;
2822
2823
2824 for (j = 0; j < 2; j++) {
2825 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2826 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2827 alu.op = LDS_OP3_LDS_WRITE_REL;
2828 alu.src[0].sel = temp_reg;
2829 alu.src[0].chan = chan;
2830 alu.src[1].sel = ctx->shader->output[i].gpr;
2831 alu.src[1].chan = j * 2;
2832 alu.src[2].sel = ctx->shader->output[i].gpr;
2833 alu.src[2].chan = (j * 2) + 1;
2834 alu.last = 1;
2835 alu.dst.chan = 0;
2836 alu.lds_idx = 1;
2837 alu.is_lds_idx_op = true;
2838 r = r600_bytecode_add_alu(ctx->bc, &alu);
2839 if (r)
2840 return r;
2841 }
2842 }
2843 return 0;
2844 }
2845
2846 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2847 {
2848 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2849 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2850 int i, r, lasti;
2851 int temp_reg = r600_get_temp(ctx);
2852 struct r600_bytecode_alu alu;
2853 unsigned write_mask = dst->Register.WriteMask;
2854
2855 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2856 return 0;
2857
2858 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2859 if (r)
2860 return r;
2861
2862 /* the base address is now in temp.x */
2863 r = r600_get_byte_address(ctx, temp_reg,
2864 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2865 if (r)
2866 return r;
2867
2868 /* LDS write */
2869 lasti = tgsi_last_instruction(write_mask);
2870 for (i = 1; i <= lasti; i++) {
2871
2872 if (!(write_mask & (1 << i)))
2873 continue;
2874 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2875 temp_reg, i,
2876 temp_reg, 0,
2877 V_SQ_ALU_SRC_LITERAL, 4 * i);
2878 if (r)
2879 return r;
2880 }
2881
2882 for (i = 0; i <= lasti; i++) {
2883 if (!(write_mask & (1 << i)))
2884 continue;
2885
2886 if ((i == 0 && ((write_mask & 3) == 3)) ||
2887 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2888 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2889 alu.op = LDS_OP3_LDS_WRITE_REL;
2890 alu.src[0].sel = temp_reg;
2891 alu.src[0].chan = i;
2892
2893 alu.src[1].sel = dst->Register.Index;
2894 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2895 alu.src[1].chan = i;
2896
2897 alu.src[2].sel = dst->Register.Index;
2898 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2899 alu.src[2].chan = i + 1;
2900 alu.lds_idx = 1;
2901 alu.dst.chan = 0;
2902 alu.last = 1;
2903 alu.is_lds_idx_op = true;
2904 r = r600_bytecode_add_alu(ctx->bc, &alu);
2905 if (r)
2906 return r;
2907 i += 1;
2908 continue;
2909 }
2910 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2911 alu.op = LDS_OP2_LDS_WRITE;
2912 alu.src[0].sel = temp_reg;
2913 alu.src[0].chan = i;
2914
2915 alu.src[1].sel = dst->Register.Index;
2916 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2917 alu.src[1].chan = i;
2918
2919 alu.src[2].sel = V_SQ_ALU_SRC_0;
2920 alu.dst.chan = 0;
2921 alu.last = 1;
2922 alu.is_lds_idx_op = true;
2923 r = r600_bytecode_add_alu(ctx->bc, &alu);
2924 if (r)
2925 return r;
2926 }
2927 return 0;
2928 }
2929
2930 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2931 int output_idx, int nc)
2932 {
2933 int param;
2934 unsigned temp_reg = r600_get_temp(ctx);
2935 unsigned name = ctx->shader->output[output_idx].name;
2936 int dreg = ctx->shader->output[output_idx].gpr;
2937 int r;
2938
2939 param = r600_get_lds_unique_index(name, 0);
2940 r = get_lds_offset0(ctx, 1, temp_reg, true);
2941 if (r)
2942 return r;
2943
2944 if (param) {
2945 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2946 temp_reg, 0,
2947 temp_reg, 0,
2948 V_SQ_ALU_SRC_LITERAL, param * 16);
2949 if (r)
2950 return r;
2951 }
2952
2953 do_lds_fetch_values(ctx, temp_reg, dreg, ((1u << nc) - 1));
2954 return 0;
2955 }
2956
2957 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2958 {
2959 int stride, outer_comps, inner_comps;
2960 int tessinner_idx = -1, tessouter_idx = -1;
2961 int i, r;
2962 unsigned j;
2963 int temp_reg = r600_get_temp(ctx);
2964 int treg[3] = {-1, -1, -1};
2965 struct r600_bytecode_alu alu;
2966 struct r600_bytecode_cf *cf_jump, *cf_pop;
2967
2968 /* only execute factor emission for invocation 0 */
2969 /* PRED_SETE_INT __, R0.x, 0 */
2970 memset(&alu, 0, sizeof(alu));
2971 alu.op = ALU_OP2_PRED_SETE_INT;
2972 alu.src[0].chan = 2;
2973 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2974 alu.execute_mask = 1;
2975 alu.update_pred = 1;
2976 alu.last = 1;
2977 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2978
2979 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2980 cf_jump = ctx->bc->cf_last;
2981
2982 treg[0] = r600_get_temp(ctx);
2983 switch (ctx->shader->tcs_prim_mode) {
2984 case PIPE_PRIM_LINES:
2985 stride = 8; /* 2 dwords, 1 vec2 store */
2986 outer_comps = 2;
2987 inner_comps = 0;
2988 break;
2989 case PIPE_PRIM_TRIANGLES:
2990 stride = 16; /* 4 dwords, 1 vec4 store */
2991 outer_comps = 3;
2992 inner_comps = 1;
2993 treg[1] = r600_get_temp(ctx);
2994 break;
2995 case PIPE_PRIM_QUADS:
2996 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2997 outer_comps = 4;
2998 inner_comps = 2;
2999 treg[1] = r600_get_temp(ctx);
3000 treg[2] = r600_get_temp(ctx);
3001 break;
3002 default:
3003 assert(0);
3004 return -1;
3005 }
3006
3007 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
3008 /* TF_WRITE takes index in R.x, value in R.y */
3009 for (j = 0; j < ctx->shader->noutput; j++) {
3010 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSINNER)
3011 tessinner_idx = j;
3012 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSOUTER)
3013 tessouter_idx = j;
3014 }
3015
3016 if (tessouter_idx == -1)
3017 return -1;
3018
3019 if (tessinner_idx == -1 && inner_comps)
3020 return -1;
3021
3022 if (tessouter_idx != -1) {
3023 r = r600_tess_factor_read(ctx, tessouter_idx, outer_comps);
3024 if (r)
3025 return r;
3026 }
3027
3028 if (tessinner_idx != -1) {
3029 r = r600_tess_factor_read(ctx, tessinner_idx, inner_comps);
3030 if (r)
3031 return r;
3032 }
3033
3034 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
3035 /* r.x = relpatchid(r0.y) * tf_stride */
3036
3037 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
3038 /* add incoming r0.w to it: t.x = t.x + r0.w */
3039 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3040 temp_reg, 0,
3041 0, 1,
3042 V_SQ_ALU_SRC_LITERAL, stride,
3043 0, 3);
3044 if (r)
3045 return r;
3046
3047 for (i = 0; i < outer_comps + inner_comps; i++) {
3048 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
3049 int out_comp = i >= outer_comps ? i - outer_comps : i;
3050
3051 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
3052 if (out_comp == 1)
3053 out_comp = 0;
3054 else if (out_comp == 0)
3055 out_comp = 1;
3056 }
3057
3058 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3059 treg[i / 2], (2 * (i % 2)),
3060 temp_reg, 0,
3061 V_SQ_ALU_SRC_LITERAL, 4 * i);
3062 if (r)
3063 return r;
3064 r = single_alu_op2(ctx, ALU_OP1_MOV,
3065 treg[i / 2], 1 + (2 * (i%2)),
3066 ctx->shader->output[out_idx].gpr, out_comp,
3067 0, 0);
3068 if (r)
3069 return r;
3070 }
3071 for (i = 0; i < outer_comps + inner_comps; i++) {
3072 struct r600_bytecode_gds gds;
3073
3074 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
3075 gds.src_gpr = treg[i / 2];
3076 gds.src_sel_x = 2 * (i % 2);
3077 gds.src_sel_y = 1 + (2 * (i % 2));
3078 gds.src_sel_z = 4;
3079 gds.dst_sel_x = 7;
3080 gds.dst_sel_y = 7;
3081 gds.dst_sel_z = 7;
3082 gds.dst_sel_w = 7;
3083 gds.op = FETCH_OP_TF_WRITE;
3084 r = r600_bytecode_add_gds(ctx->bc, &gds);
3085 if (r)
3086 return r;
3087 }
3088
3089 // Patch up jump label
3090 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
3091 cf_pop = ctx->bc->cf_last;
3092
3093 cf_jump->cf_addr = cf_pop->id + 2;
3094 cf_jump->pop_count = 1;
3095 cf_pop->cf_addr = cf_pop->id + 2;
3096 cf_pop->pop_count = 1;
3097
3098 return 0;
3099 }
3100
3101 /*
3102 * We have to work out the thread ID for load and atomic
3103 * operations, which store the returned value to an index
3104 * in an intermediate buffer.
3105 * The index is calculated by taking the thread id,
3106 * calculated from the MBCNT instructions.
3107 * Then the shader engine ID is multiplied by 256,
3108 * and the wave id is added.
3109 * Then the result is multipled by 64 and thread id is
3110 * added.
3111 */
3112 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
3113 {
3114 struct r600_bytecode_alu alu;
3115 int r;
3116
3117 if (ctx->thread_id_gpr_loaded)
3118 return 0;
3119
3120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3121 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
3122 alu.dst.sel = ctx->temp_reg;
3123 alu.dst.chan = 0;
3124 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3125 alu.src[0].value = 0xffffffff;
3126 alu.dst.write = 1;
3127 r = r600_bytecode_add_alu(ctx->bc, &alu);
3128 if (r)
3129 return r;
3130
3131 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3132 alu.op = ALU_OP1_MBCNT_32HI_INT;
3133 alu.dst.sel = ctx->temp_reg;
3134 alu.dst.chan = 1;
3135 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3136 alu.src[0].value = 0xffffffff;
3137 alu.dst.write = 1;
3138 r = r600_bytecode_add_alu(ctx->bc, &alu);
3139 if (r)
3140 return r;
3141
3142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3143 alu.op = ALU_OP3_MULADD_UINT24;
3144 alu.dst.sel = ctx->temp_reg;
3145 alu.dst.chan = 2;
3146 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
3147 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3148 alu.src[1].value = 256;
3149 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
3150 alu.dst.write = 1;
3151 alu.is_op3 = 1;
3152 alu.last = 1;
3153 r = r600_bytecode_add_alu(ctx->bc, &alu);
3154 if (r)
3155 return r;
3156
3157 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3158 ctx->thread_id_gpr, 1,
3159 ctx->temp_reg, 2,
3160 V_SQ_ALU_SRC_LITERAL, 0x40,
3161 ctx->temp_reg, 0);
3162 if (r)
3163 return r;
3164 ctx->thread_id_gpr_loaded = true;
3165 return 0;
3166 }
3167
3168 static int r600_shader_from_tgsi(struct r600_context *rctx,
3169 struct r600_pipe_shader *pipeshader,
3170 union r600_shader_key key)
3171 {
3172 struct r600_screen *rscreen = rctx->screen;
3173 struct r600_shader *shader = &pipeshader->shader;
3174 struct tgsi_token *tokens = pipeshader->selector->tokens;
3175 struct pipe_stream_output_info so = pipeshader->selector->so;
3176 struct tgsi_full_immediate *immediate;
3177 struct r600_shader_ctx ctx;
3178 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3179 unsigned output_done, noutput;
3180 unsigned opcode;
3181 int j, k, r = 0;
3182 unsigned i;
3183 int next_param_base = 0, next_clip_base;
3184 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3185 bool indirect_gprs;
3186 bool ring_outputs = false;
3187 bool lds_outputs = false;
3188 bool lds_inputs = false;
3189 bool pos_emitted = false;
3190
3191 ctx.bc = &shader->bc;
3192 ctx.shader = shader;
3193
3194 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3195 rscreen->has_compressed_msaa_texturing);
3196 ctx.tokens = tokens;
3197 tgsi_scan_shader(tokens, &ctx.info);
3198 shader->indirect_files = ctx.info.indirect_files;
3199
3200 shader->uses_helper_invocation = false;
3201 shader->uses_doubles = ctx.info.uses_doubles;
3202 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3203 shader->nsys_inputs = 0;
3204
3205 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0 ||
3206 ctx.info.file_count[TGSI_FILE_BUFFER] > 0;
3207 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3208 tgsi_parse_init(&ctx.parse, tokens);
3209 ctx.type = ctx.info.processor;
3210 shader->processor_type = ctx.type;
3211 ctx.bc->type = shader->processor_type;
3212
3213 switch (ctx.type) {
3214 case PIPE_SHADER_VERTEX:
3215 shader->vs_as_gs_a = key.vs.as_gs_a;
3216 shader->vs_as_es = key.vs.as_es;
3217 shader->vs_as_ls = key.vs.as_ls;
3218 shader->atomic_base = key.vs.first_atomic_counter;
3219 if (shader->vs_as_es)
3220 ring_outputs = true;
3221 if (shader->vs_as_ls)
3222 lds_outputs = true;
3223 break;
3224 case PIPE_SHADER_GEOMETRY:
3225 ring_outputs = true;
3226 shader->atomic_base = key.gs.first_atomic_counter;
3227 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3228 break;
3229 case PIPE_SHADER_TESS_CTRL:
3230 shader->tcs_prim_mode = key.tcs.prim_mode;
3231 shader->atomic_base = key.tcs.first_atomic_counter;
3232 lds_outputs = true;
3233 lds_inputs = true;
3234 break;
3235 case PIPE_SHADER_TESS_EVAL:
3236 shader->tes_as_es = key.tes.as_es;
3237 shader->atomic_base = key.tes.first_atomic_counter;
3238 lds_inputs = true;
3239 if (shader->tes_as_es)
3240 ring_outputs = true;
3241 break;
3242 case PIPE_SHADER_FRAGMENT:
3243 shader->two_side = key.ps.color_two_side;
3244 shader->atomic_base = key.ps.first_atomic_counter;
3245 shader->rat_base = key.ps.nr_cbufs;
3246 shader->image_size_const_offset = key.ps.image_size_const_offset;
3247 break;
3248 case PIPE_SHADER_COMPUTE:
3249 shader->rat_base = 0;
3250 shader->image_size_const_offset = ctx.info.file_count[TGSI_FILE_SAMPLER];
3251 break;
3252 default:
3253 break;
3254 }
3255
3256 if (shader->vs_as_es || shader->tes_as_es) {
3257 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3258 } else {
3259 ctx.gs_for_vs = NULL;
3260 }
3261
3262 ctx.next_ring_offset = 0;
3263 ctx.gs_out_ring_offset = 0;
3264 ctx.gs_next_vertex = 0;
3265 ctx.gs_stream_output_info = &so;
3266
3267 ctx.face_gpr = -1;
3268 ctx.fixed_pt_position_gpr = -1;
3269 ctx.fragcoord_input = -1;
3270 ctx.colors_used = 0;
3271 ctx.clip_vertex_write = 0;
3272 ctx.thread_id_gpr_loaded = false;
3273
3274 ctx.helper_invoc_reg = -1;
3275 ctx.cs_block_size_reg = -1;
3276 ctx.cs_grid_size_reg = -1;
3277 ctx.cs_block_size_loaded = false;
3278 ctx.cs_grid_size_loaded = false;
3279
3280 shader->nr_ps_color_exports = 0;
3281 shader->nr_ps_max_color_exports = 0;
3282
3283
3284 /* register allocations */
3285 /* Values [0,127] correspond to GPR[0..127].
3286 * Values [128,159] correspond to constant buffer bank 0
3287 * Values [160,191] correspond to constant buffer bank 1
3288 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3289 * Values [256,287] correspond to constant buffer bank 2 (EG)
3290 * Values [288,319] correspond to constant buffer bank 3 (EG)
3291 * Other special values are shown in the list below.
3292 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3293 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3294 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3295 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3296 * 248 SQ_ALU_SRC_0: special constant 0.0.
3297 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3298 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3299 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3300 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3301 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3302 * 254 SQ_ALU_SRC_PV: previous vector result.
3303 * 255 SQ_ALU_SRC_PS: previous scalar result.
3304 */
3305 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3306 ctx.file_offset[i] = 0;
3307 }
3308
3309 if (ctx.type == PIPE_SHADER_VERTEX) {
3310
3311 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3312 if (ctx.info.num_inputs)
3313 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3314 }
3315 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3316 if (ctx.bc->chip_class >= EVERGREEN)
3317 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3318 else
3319 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3320
3321 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3322 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_HELPER_INVOCATION) {
3323 ctx.helper_invoc_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3324 shader->uses_helper_invocation = true;
3325 }
3326 }
3327 }
3328 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3329 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3330 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3331 }
3332 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3333 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3334 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3335 bool add_tesscoord = false, add_tess_inout = false;
3336 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3337 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3338 /* if we have tesscoord save one reg */
3339 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3340 add_tesscoord = true;
3341 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3342 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3343 add_tess_inout = true;
3344 }
3345 if (add_tesscoord || add_tess_inout)
3346 ctx.file_offset[TGSI_FILE_INPUT]++;
3347 if (add_tess_inout)
3348 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3349 }
3350 if (ctx.type == PIPE_SHADER_COMPUTE) {
3351 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3352 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3353 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_GRID_SIZE)
3354 ctx.cs_grid_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3355 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_BLOCK_SIZE)
3356 ctx.cs_block_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3357 }
3358 }
3359
3360 ctx.file_offset[TGSI_FILE_OUTPUT] =
3361 ctx.file_offset[TGSI_FILE_INPUT] +
3362 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3363 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3364 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3365
3366 /* Outside the GPR range. This will be translated to one of the
3367 * kcache banks later. */
3368 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3369
3370 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3371 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3372 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3373 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3374 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3375
3376 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3377 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3378 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3379 ctx.temp_reg = ctx.bc->ar_reg + 5;
3380 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3381 ctx.tess_input_info = 0;
3382 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3383 ctx.temp_reg = ctx.bc->ar_reg + 4;
3384 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3385 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3386 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3387 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3388 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3389 ctx.temp_reg = ctx.bc->ar_reg + 7;
3390 if (ctx.shader->gs_tri_strip_adj_fix) {
3391 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3392 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3393 ctx.temp_reg += 2;
3394 } else {
3395 ctx.gs_rotated_input[0] = 0;
3396 ctx.gs_rotated_input[1] = 1;
3397 }
3398 } else {
3399 ctx.temp_reg = ctx.bc->ar_reg + 3;
3400 }
3401
3402 if (shader->uses_images) {
3403 ctx.thread_id_gpr = ctx.temp_reg++;
3404 ctx.thread_id_gpr_loaded = false;
3405 }
3406
3407 shader->max_arrays = 0;
3408 shader->num_arrays = 0;
3409 if (indirect_gprs) {
3410
3411 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3412 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3413 ctx.file_offset[TGSI_FILE_OUTPUT] -
3414 ctx.file_offset[TGSI_FILE_INPUT],
3415 0x0F);
3416 }
3417 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3418 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3419 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3420 ctx.file_offset[TGSI_FILE_OUTPUT],
3421 0x0F);
3422 }
3423 }
3424
3425 ctx.nliterals = 0;
3426 ctx.literals = NULL;
3427 ctx.max_driver_temp_used = 0;
3428
3429 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3430 ctx.info.colors_written == 1;
3431 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3432 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3433
3434 if (ctx.type == PIPE_SHADER_VERTEX ||
3435 ctx.type == PIPE_SHADER_GEOMETRY ||
3436 ctx.type == PIPE_SHADER_TESS_EVAL) {
3437 shader->cc_dist_mask = (1 << (ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED] +
3438 ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED])) - 1;
3439 shader->clip_dist_write = (1 << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED]) - 1;
3440 shader->cull_dist_write = ((1 << ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED]) - 1) << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED];
3441 }
3442
3443 if (shader->vs_as_gs_a)
3444 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3445
3446 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3447 r600_fetch_tess_io_info(&ctx);
3448
3449 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3450 tgsi_parse_token(&ctx.parse);
3451 switch (ctx.parse.FullToken.Token.Type) {
3452 case TGSI_TOKEN_TYPE_IMMEDIATE:
3453 immediate = &ctx.parse.FullToken.FullImmediate;
3454 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3455 if(ctx.literals == NULL) {
3456 r = -ENOMEM;
3457 goto out_err;
3458 }
3459 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3460 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3461 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3462 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3463 ctx.nliterals++;
3464 break;
3465 case TGSI_TOKEN_TYPE_DECLARATION:
3466 r = tgsi_declaration(&ctx);
3467 if (r)
3468 goto out_err;
3469 break;
3470 case TGSI_TOKEN_TYPE_INSTRUCTION:
3471 case TGSI_TOKEN_TYPE_PROPERTY:
3472 break;
3473 default:
3474 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3475 r = -EINVAL;
3476 goto out_err;
3477 }
3478 }
3479
3480 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3481 shader->ring_item_sizes[1] = 0;
3482 shader->ring_item_sizes[2] = 0;
3483 shader->ring_item_sizes[3] = 0;
3484
3485 /* Process two side if needed */
3486 if (shader->two_side && ctx.colors_used) {
3487 int i, count = ctx.shader->ninput;
3488 unsigned next_lds_loc = ctx.shader->nlds;
3489
3490 /* additional inputs will be allocated right after the existing inputs,
3491 * we won't need them after the color selection, so we don't need to
3492 * reserve these gprs for the rest of the shader code and to adjust
3493 * output offsets etc. */
3494 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3495 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3496
3497 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3498 if (ctx.face_gpr == -1) {
3499 i = ctx.shader->ninput++;
3500 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3501 ctx.shader->input[i].spi_sid = 0;
3502 ctx.shader->input[i].gpr = gpr++;
3503 ctx.face_gpr = ctx.shader->input[i].gpr;
3504 }
3505
3506 for (i = 0; i < count; i++) {
3507 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3508 int ni = ctx.shader->ninput++;
3509 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3510 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3511 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3512 ctx.shader->input[ni].gpr = gpr++;
3513 // TGSI to LLVM needs to know the lds position of inputs.
3514 // Non LLVM path computes it later (in process_twoside_color)
3515 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3516 ctx.shader->input[i].back_color_input = ni;
3517 if (ctx.bc->chip_class >= EVERGREEN) {
3518 if ((r = evergreen_interp_input(&ctx, ni)))
3519 return r;
3520 }
3521 }
3522 }
3523 }
3524
3525 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3526 shader->nr_ps_max_color_exports = 8;
3527
3528 if (ctx.shader->uses_helper_invocation) {
3529 if (ctx.bc->chip_class == CAYMAN)
3530 r = cm_load_helper_invocation(&ctx);
3531 else
3532 r = eg_load_helper_invocation(&ctx);
3533 if (r)
3534 return r;
3535
3536 }
3537 if (ctx.fragcoord_input >= 0) {
3538 if (ctx.bc->chip_class == CAYMAN) {
3539 for (j = 0 ; j < 4; j++) {
3540 struct r600_bytecode_alu alu;
3541 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3542 alu.op = ALU_OP1_RECIP_IEEE;
3543 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3544 alu.src[0].chan = 3;
3545
3546 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3547 alu.dst.chan = j;
3548 alu.dst.write = (j == 3);
3549 alu.last = 1;
3550 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3551 return r;
3552 }
3553 } else {
3554 struct r600_bytecode_alu alu;
3555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3556 alu.op = ALU_OP1_RECIP_IEEE;
3557 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3558 alu.src[0].chan = 3;
3559
3560 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3561 alu.dst.chan = 3;
3562 alu.dst.write = 1;
3563 alu.last = 1;
3564 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3565 return r;
3566 }
3567 }
3568
3569 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3570 struct r600_bytecode_alu alu;
3571 int r;
3572
3573 /* GS thread with no output workaround - emit a cut at start of GS */
3574 if (ctx.bc->chip_class == R600)
3575 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3576
3577 for (j = 0; j < 4; j++) {
3578 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3579 alu.op = ALU_OP1_MOV;
3580 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3581 alu.src[0].value = 0;
3582 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3583 alu.dst.write = 1;
3584 alu.last = 1;
3585 r = r600_bytecode_add_alu(ctx.bc, &alu);
3586 if (r)
3587 return r;
3588 }
3589
3590 if (ctx.shader->gs_tri_strip_adj_fix) {
3591 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3592 ctx.gs_rotated_input[0], 2,
3593 0, 2,
3594 V_SQ_ALU_SRC_LITERAL, 1);
3595 if (r)
3596 return r;
3597
3598 for (i = 0; i < 6; i++) {
3599 int rotated = (i + 4) % 6;
3600 int offset_reg = i / 3;
3601 int offset_chan = i % 3;
3602 int rotated_offset_reg = rotated / 3;
3603 int rotated_offset_chan = rotated % 3;
3604
3605 if (offset_reg == 0 && offset_chan == 2)
3606 offset_chan = 3;
3607 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3608 rotated_offset_chan = 3;
3609
3610 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3611 ctx.gs_rotated_input[offset_reg], offset_chan,
3612 ctx.gs_rotated_input[0], 2,
3613 offset_reg, offset_chan,
3614 rotated_offset_reg, rotated_offset_chan);
3615 if (r)
3616 return r;
3617 }
3618 }
3619 }
3620
3621 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3622 r600_fetch_tess_io_info(&ctx);
3623
3624 if (shader->two_side && ctx.colors_used) {
3625 if ((r = process_twoside_color_inputs(&ctx)))
3626 return r;
3627 }
3628
3629 tgsi_parse_init(&ctx.parse, tokens);
3630 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3631 tgsi_parse_token(&ctx.parse);
3632 switch (ctx.parse.FullToken.Token.Type) {
3633 case TGSI_TOKEN_TYPE_INSTRUCTION:
3634 r = tgsi_is_supported(&ctx);
3635 if (r)
3636 goto out_err;
3637 ctx.max_driver_temp_used = 0;
3638 /* reserve first tmp for everyone */
3639 r600_get_temp(&ctx);
3640
3641 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3642 if ((r = tgsi_split_constant(&ctx)))
3643 goto out_err;
3644 if ((r = tgsi_split_literal_constant(&ctx)))
3645 goto out_err;
3646 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3647 if ((r = tgsi_split_gs_inputs(&ctx)))
3648 goto out_err;
3649 } else if (lds_inputs) {
3650 if ((r = tgsi_split_lds_inputs(&ctx)))
3651 goto out_err;
3652 }
3653 if (ctx.bc->chip_class == CAYMAN)
3654 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3655 else if (ctx.bc->chip_class >= EVERGREEN)
3656 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3657 else
3658 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3659 r = ctx.inst_info->process(&ctx);
3660 if (r)
3661 goto out_err;
3662
3663 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3664 r = r600_store_tcs_output(&ctx);
3665 if (r)
3666 goto out_err;
3667 }
3668 break;
3669 default:
3670 break;
3671 }
3672 }
3673
3674 /* Reset the temporary register counter. */
3675 ctx.max_driver_temp_used = 0;
3676
3677 noutput = shader->noutput;
3678
3679 if (!ring_outputs && ctx.clip_vertex_write) {
3680 unsigned clipdist_temp[2];
3681
3682 clipdist_temp[0] = r600_get_temp(&ctx);
3683 clipdist_temp[1] = r600_get_temp(&ctx);
3684
3685 /* need to convert a clipvertex write into clipdistance writes and not export
3686 the clip vertex anymore */
3687
3688 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3689 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3690 shader->output[noutput].gpr = clipdist_temp[0];
3691 noutput++;
3692 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3693 shader->output[noutput].gpr = clipdist_temp[1];
3694 noutput++;
3695
3696 /* reset spi_sid for clipvertex output to avoid confusing spi */
3697 shader->output[ctx.cv_output].spi_sid = 0;
3698
3699 shader->clip_dist_write = 0xFF;
3700 shader->cc_dist_mask = 0xFF;
3701
3702 for (i = 0; i < 8; i++) {
3703 int oreg = i >> 2;
3704 int ochan = i & 3;
3705
3706 for (j = 0; j < 4; j++) {
3707 struct r600_bytecode_alu alu;
3708 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3709 alu.op = ALU_OP2_DOT4;
3710 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3711 alu.src[0].chan = j;
3712
3713 alu.src[1].sel = 512 + i;
3714 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3715 alu.src[1].chan = j;
3716
3717 alu.dst.sel = clipdist_temp[oreg];
3718 alu.dst.chan = j;
3719 alu.dst.write = (j == ochan);
3720 if (j == 3)
3721 alu.last = 1;
3722 r = r600_bytecode_add_alu(ctx.bc, &alu);
3723 if (r)
3724 return r;
3725 }
3726 }
3727 }
3728
3729 /* Add stream outputs. */
3730 if (so.num_outputs) {
3731 bool emit = false;
3732 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3733 emit = true;
3734 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3735 emit = true;
3736 if (emit)
3737 emit_streamout(&ctx, &so, -1, NULL);
3738 }
3739 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3740 convert_edgeflag_to_int(&ctx);
3741
3742 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3743 r600_emit_tess_factor(&ctx);
3744
3745 if (lds_outputs) {
3746 if (ctx.type == PIPE_SHADER_VERTEX) {
3747 if (ctx.shader->noutput)
3748 emit_lds_vs_writes(&ctx);
3749 }
3750 } else if (ring_outputs) {
3751 if (shader->vs_as_es || shader->tes_as_es) {
3752 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3753 ctx.gs_export_gpr_tregs[1] = -1;
3754 ctx.gs_export_gpr_tregs[2] = -1;
3755 ctx.gs_export_gpr_tregs[3] = -1;
3756
3757 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3758 }
3759 } else {
3760 /* Export output */
3761 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3762
3763 for (i = 0, j = 0; i < noutput; i++, j++) {
3764 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3765 output[j].gpr = shader->output[i].gpr;
3766 output[j].elem_size = 3;
3767 output[j].swizzle_x = 0;
3768 output[j].swizzle_y = 1;
3769 output[j].swizzle_z = 2;
3770 output[j].swizzle_w = 3;
3771 output[j].burst_count = 1;
3772 output[j].type = 0xffffffff;
3773 output[j].op = CF_OP_EXPORT;
3774 switch (ctx.type) {
3775 case PIPE_SHADER_VERTEX:
3776 case PIPE_SHADER_TESS_EVAL:
3777 switch (shader->output[i].name) {
3778 case TGSI_SEMANTIC_POSITION:
3779 output[j].array_base = 60;
3780 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3781 pos_emitted = true;
3782 break;
3783
3784 case TGSI_SEMANTIC_PSIZE:
3785 output[j].array_base = 61;
3786 output[j].swizzle_y = 7;
3787 output[j].swizzle_z = 7;
3788 output[j].swizzle_w = 7;
3789 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3790 pos_emitted = true;
3791 break;
3792 case TGSI_SEMANTIC_EDGEFLAG:
3793 output[j].array_base = 61;
3794 output[j].swizzle_x = 7;
3795 output[j].swizzle_y = 0;
3796 output[j].swizzle_z = 7;
3797 output[j].swizzle_w = 7;
3798 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3799 pos_emitted = true;
3800 break;
3801 case TGSI_SEMANTIC_LAYER:
3802 /* spi_sid is 0 for outputs that are
3803 * not consumed by PS */
3804 if (shader->output[i].spi_sid) {
3805 output[j].array_base = next_param_base++;
3806 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3807 j++;
3808 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3809 }
3810 output[j].array_base = 61;
3811 output[j].swizzle_x = 7;
3812 output[j].swizzle_y = 7;
3813 output[j].swizzle_z = 0;
3814 output[j].swizzle_w = 7;
3815 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3816 pos_emitted = true;
3817 break;
3818 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3819 /* spi_sid is 0 for outputs that are
3820 * not consumed by PS */
3821 if (shader->output[i].spi_sid) {
3822 output[j].array_base = next_param_base++;
3823 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3824 j++;
3825 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3826 }
3827 output[j].array_base = 61;
3828 output[j].swizzle_x = 7;
3829 output[j].swizzle_y = 7;
3830 output[j].swizzle_z = 7;
3831 output[j].swizzle_w = 0;
3832 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3833 pos_emitted = true;
3834 break;
3835 case TGSI_SEMANTIC_CLIPVERTEX:
3836 j--;
3837 break;
3838 case TGSI_SEMANTIC_CLIPDIST:
3839 output[j].array_base = next_clip_base++;
3840 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3841 pos_emitted = true;
3842 /* spi_sid is 0 for clipdistance outputs that were generated
3843 * for clipvertex - we don't need to pass them to PS */
3844 if (shader->output[i].spi_sid) {
3845 j++;
3846 /* duplicate it as PARAM to pass to the pixel shader */
3847 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3848 output[j].array_base = next_param_base++;
3849 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3850 }
3851 break;
3852 case TGSI_SEMANTIC_FOG:
3853 output[j].swizzle_y = 4; /* 0 */
3854 output[j].swizzle_z = 4; /* 0 */
3855 output[j].swizzle_w = 5; /* 1 */
3856 break;
3857 case TGSI_SEMANTIC_PRIMID:
3858 output[j].swizzle_x = 2;
3859 output[j].swizzle_y = 4; /* 0 */
3860 output[j].swizzle_z = 4; /* 0 */
3861 output[j].swizzle_w = 4; /* 0 */
3862 break;
3863 }
3864
3865 break;
3866 case PIPE_SHADER_FRAGMENT:
3867 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3868 /* never export more colors than the number of CBs */
3869 if (shader->output[i].sid >= max_color_exports) {
3870 /* skip export */
3871 j--;
3872 continue;
3873 }
3874 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3875 output[j].array_base = shader->output[i].sid;
3876 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3877 shader->nr_ps_color_exports++;
3878 shader->ps_color_export_mask |= (0xf << (shader->output[i].sid * 4));
3879
3880 /* If the i-th target format is set, all previous target formats must
3881 * be non-zero to avoid hangs. - from radeonsi, seems to apply to eg as well.
3882 */
3883 if (shader->output[i].sid > 0)
3884 for (unsigned x = 0; x < shader->output[i].sid; x++)
3885 shader->ps_color_export_mask |= (1 << (x*4));
3886
3887 if (shader->output[i].sid > shader->ps_export_highest)
3888 shader->ps_export_highest = shader->output[i].sid;
3889 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3890 for (k = 1; k < max_color_exports; k++) {
3891 j++;
3892 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3893 output[j].gpr = shader->output[i].gpr;
3894 output[j].elem_size = 3;
3895 output[j].swizzle_x = 0;
3896 output[j].swizzle_y = 1;
3897 output[j].swizzle_z = 2;
3898 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3899 output[j].burst_count = 1;
3900 output[j].array_base = k;
3901 output[j].op = CF_OP_EXPORT;
3902 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3903 shader->nr_ps_color_exports++;
3904 shader->ps_color_export_mask |= (0xf << (j * 4));
3905 }
3906 }
3907 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3908 output[j].array_base = 61;
3909 output[j].swizzle_x = 2;
3910 output[j].swizzle_y = 7;
3911 output[j].swizzle_z = output[j].swizzle_w = 7;
3912 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3913 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3914 output[j].array_base = 61;
3915 output[j].swizzle_x = 7;
3916 output[j].swizzle_y = 1;
3917 output[j].swizzle_z = output[j].swizzle_w = 7;
3918 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3919 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3920 output[j].array_base = 61;
3921 output[j].swizzle_x = 7;
3922 output[j].swizzle_y = 7;
3923 output[j].swizzle_z = 0;
3924 output[j].swizzle_w = 7;
3925 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3926 } else {
3927 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3928 r = -EINVAL;
3929 goto out_err;
3930 }
3931 break;
3932 case PIPE_SHADER_TESS_CTRL:
3933 break;
3934 default:
3935 R600_ERR("unsupported processor type %d\n", ctx.type);
3936 r = -EINVAL;
3937 goto out_err;
3938 }
3939
3940 if (output[j].type == 0xffffffff) {
3941 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3942 output[j].array_base = next_param_base++;
3943 }
3944 }
3945
3946 /* add fake position export */
3947 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3948 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3949 output[j].gpr = 0;
3950 output[j].elem_size = 3;
3951 output[j].swizzle_x = 7;
3952 output[j].swizzle_y = 7;
3953 output[j].swizzle_z = 7;
3954 output[j].swizzle_w = 7;
3955 output[j].burst_count = 1;
3956 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3957 output[j].array_base = 60;
3958 output[j].op = CF_OP_EXPORT;
3959 j++;
3960 }
3961
3962 /* add fake param output for vertex shader if no param is exported */
3963 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3964 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3965 output[j].gpr = 0;
3966 output[j].elem_size = 3;
3967 output[j].swizzle_x = 7;
3968 output[j].swizzle_y = 7;
3969 output[j].swizzle_z = 7;
3970 output[j].swizzle_w = 7;
3971 output[j].burst_count = 1;
3972 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3973 output[j].array_base = 0;
3974 output[j].op = CF_OP_EXPORT;
3975 j++;
3976 }
3977
3978 /* add fake pixel export */
3979 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3980 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3981 output[j].gpr = 0;
3982 output[j].elem_size = 3;
3983 output[j].swizzle_x = 7;
3984 output[j].swizzle_y = 7;
3985 output[j].swizzle_z = 7;
3986 output[j].swizzle_w = 7;
3987 output[j].burst_count = 1;
3988 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3989 output[j].array_base = 0;
3990 output[j].op = CF_OP_EXPORT;
3991 j++;
3992 shader->nr_ps_color_exports++;
3993 shader->ps_color_export_mask = 0xf;
3994 }
3995
3996 noutput = j;
3997
3998 /* set export done on last export of each type */
3999 for (k = noutput - 1, output_done = 0; k >= 0; k--) {
4000 if (!(output_done & (1 << output[k].type))) {
4001 output_done |= (1 << output[k].type);
4002 output[k].op = CF_OP_EXPORT_DONE;
4003 }
4004 }
4005 /* add output to bytecode */
4006 for (i = 0; i < noutput; i++) {
4007 r = r600_bytecode_add_output(ctx.bc, &output[i]);
4008 if (r)
4009 goto out_err;
4010 }
4011 }
4012
4013 /* add program end */
4014 if (ctx.bc->chip_class == CAYMAN)
4015 cm_bytecode_add_cf_end(ctx.bc);
4016 else {
4017 const struct cf_op_info *last = NULL;
4018
4019 if (ctx.bc->cf_last)
4020 last = r600_isa_cf(ctx.bc->cf_last->op);
4021
4022 /* alu clause instructions don't have EOP bit, so add NOP */
4023 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_POP)
4024 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
4025
4026 ctx.bc->cf_last->end_of_program = 1;
4027 }
4028
4029 /* check GPR limit - we have 124 = 128 - 4
4030 * (4 are reserved as alu clause temporary registers) */
4031 if (ctx.bc->ngpr > 124) {
4032 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
4033 r = -ENOMEM;
4034 goto out_err;
4035 }
4036
4037 if (ctx.type == PIPE_SHADER_GEOMETRY) {
4038 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
4039 return r;
4040 }
4041
4042 free(ctx.literals);
4043 tgsi_parse_free(&ctx.parse);
4044 return 0;
4045 out_err:
4046 free(ctx.literals);
4047 tgsi_parse_free(&ctx.parse);
4048 return r;
4049 }
4050
4051 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
4052 {
4053 const unsigned tgsi_opcode =
4054 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
4055 R600_ERR("%s tgsi opcode unsupported\n",
4056 tgsi_get_opcode_name(tgsi_opcode));
4057 return -EINVAL;
4058 }
4059
4060 static int tgsi_end(struct r600_shader_ctx *ctx UNUSED)
4061 {
4062 return 0;
4063 }
4064
4065 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
4066 const struct r600_shader_src *shader_src,
4067 unsigned chan)
4068 {
4069 bc_src->sel = shader_src->sel;
4070 bc_src->chan = shader_src->swizzle[chan];
4071 bc_src->neg = shader_src->neg;
4072 bc_src->abs = shader_src->abs;
4073 bc_src->rel = shader_src->rel;
4074 bc_src->value = shader_src->value[bc_src->chan];
4075 bc_src->kc_bank = shader_src->kc_bank;
4076 bc_src->kc_rel = shader_src->kc_rel;
4077 }
4078
4079 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
4080 {
4081 bc_src->abs = 1;
4082 bc_src->neg = 0;
4083 }
4084
4085 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
4086 {
4087 bc_src->neg = !bc_src->neg;
4088 }
4089
4090 static void tgsi_dst(struct r600_shader_ctx *ctx,
4091 const struct tgsi_full_dst_register *tgsi_dst,
4092 unsigned swizzle,
4093 struct r600_bytecode_alu_dst *r600_dst)
4094 {
4095 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4096
4097 r600_dst->sel = tgsi_dst->Register.Index;
4098 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
4099 r600_dst->chan = swizzle;
4100 r600_dst->write = 1;
4101 if (inst->Instruction.Saturate) {
4102 r600_dst->clamp = 1;
4103 }
4104 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
4105 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
4106 return;
4107 }
4108 }
4109 if (tgsi_dst->Register.Indirect)
4110 r600_dst->rel = V_SQ_REL_RELATIVE;
4111
4112 }
4113
4114 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap, int dest_temp, int op_override)
4115 {
4116 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4117 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4118 struct r600_bytecode_alu alu;
4119 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4120 int use_tmp = 0;
4121 int swizzle_x = inst->Src[0].Register.SwizzleX;
4122
4123 if (singledest) {
4124 switch (write_mask) {
4125 case 0x1:
4126 if (swizzle_x == 2) {
4127 write_mask = 0xc;
4128 use_tmp = 3;
4129 } else
4130 write_mask = 0x3;
4131 break;
4132 case 0x2:
4133 if (swizzle_x == 2) {
4134 write_mask = 0xc;
4135 use_tmp = 3;
4136 } else {
4137 write_mask = 0x3;
4138 use_tmp = 1;
4139 }
4140 break;
4141 case 0x4:
4142 if (swizzle_x == 0) {
4143 write_mask = 0x3;
4144 use_tmp = 1;
4145 } else
4146 write_mask = 0xc;
4147 break;
4148 case 0x8:
4149 if (swizzle_x == 0) {
4150 write_mask = 0x3;
4151 use_tmp = 1;
4152 } else {
4153 write_mask = 0xc;
4154 use_tmp = 3;
4155 }
4156 break;
4157 }
4158 }
4159
4160 lasti = tgsi_last_instruction(write_mask);
4161 for (i = 0; i <= lasti; i++) {
4162
4163 if (!(write_mask & (1 << i)))
4164 continue;
4165
4166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4167
4168 if (singledest) {
4169 if (use_tmp || dest_temp) {
4170 alu.dst.sel = use_tmp ? ctx->temp_reg : dest_temp;
4171 alu.dst.chan = i;
4172 alu.dst.write = 1;
4173 } else {
4174 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4175 }
4176 if (i == 1 || i == 3)
4177 alu.dst.write = 0;
4178 } else
4179 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4180
4181 alu.op = op_override ? op_override : ctx->inst_info->op;
4182 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
4183 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4184 } else if (!swap) {
4185 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4186 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4187 }
4188 } else {
4189 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
4190 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
4191 }
4192
4193 /* handle some special cases */
4194 if (i == 1 || i == 3) {
4195 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
4196 case TGSI_OPCODE_DABS:
4197 r600_bytecode_src_set_abs(&alu.src[0]);
4198 break;
4199 default:
4200 break;
4201 }
4202 }
4203 if (i == lasti) {
4204 alu.last = 1;
4205 }
4206 r = r600_bytecode_add_alu(ctx->bc, &alu);
4207 if (r)
4208 return r;
4209 }
4210
4211 if (use_tmp) {
4212 write_mask = inst->Dst[0].Register.WriteMask;
4213
4214 lasti = tgsi_last_instruction(write_mask);
4215 /* move result from temp to dst */
4216 for (i = 0; i <= lasti; i++) {
4217 if (!(write_mask & (1 << i)))
4218 continue;
4219
4220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4221 alu.op = ALU_OP1_MOV;
4222
4223 if (dest_temp) {
4224 alu.dst.sel = dest_temp;
4225 alu.dst.chan = i;
4226 alu.dst.write = 1;
4227 } else
4228 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4229 alu.src[0].sel = ctx->temp_reg;
4230 alu.src[0].chan = use_tmp - 1;
4231 alu.last = (i == lasti);
4232
4233 r = r600_bytecode_add_alu(ctx->bc, &alu);
4234 if (r)
4235 return r;
4236 }
4237 }
4238 return 0;
4239 }
4240
4241 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
4242 {
4243 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4244 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4245 /* confirm writemasking */
4246 if ((write_mask & 0x3) != 0x3 &&
4247 (write_mask & 0xc) != 0xc) {
4248 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4249 return -1;
4250 }
4251 return tgsi_op2_64_params(ctx, false, false, 0, 0);
4252 }
4253
4254 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4255 {
4256 return tgsi_op2_64_params(ctx, true, false, 0, 0);
4257 }
4258
4259 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4260 {
4261 return tgsi_op2_64_params(ctx, true, true, 0, 0);
4262 }
4263
4264 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4265 {
4266 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4267 struct r600_bytecode_alu alu;
4268 int i, j, r;
4269 int lasti = 3;
4270 int tmp = r600_get_temp(ctx);
4271
4272 for (i = 0; i < lasti + 1; i++) {
4273
4274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4275 alu.op = ctx->inst_info->op;
4276 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4277 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4278 }
4279
4280 if (inst->Dst[0].Register.WriteMask & (1 << i))
4281 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4282 else
4283 alu.dst.sel = tmp;
4284
4285 alu.dst.chan = i;
4286 alu.is_op3 = 1;
4287 if (i == lasti) {
4288 alu.last = 1;
4289 }
4290 r = r600_bytecode_add_alu(ctx->bc, &alu);
4291 if (r)
4292 return r;
4293 }
4294 return 0;
4295 }
4296
4297 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4298 {
4299 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4300 struct r600_bytecode_alu alu;
4301 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4302 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4303 /* use temp register if trans_only and more than one dst component */
4304 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4305 unsigned op = ctx->inst_info->op;
4306
4307 if (op == ALU_OP2_MUL_IEEE &&
4308 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4309 op = ALU_OP2_MUL;
4310
4311 for (i = 0; i <= lasti; i++) {
4312 if (!(write_mask & (1 << i)))
4313 continue;
4314
4315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4316 if (use_tmp) {
4317 alu.dst.sel = ctx->temp_reg;
4318 alu.dst.chan = i;
4319 alu.dst.write = 1;
4320 } else
4321 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4322
4323 alu.op = op;
4324 if (!swap) {
4325 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4326 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4327 }
4328 } else {
4329 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4330 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4331 }
4332 if (i == lasti || trans_only) {
4333 alu.last = 1;
4334 }
4335 r = r600_bytecode_add_alu(ctx->bc, &alu);
4336 if (r)
4337 return r;
4338 }
4339
4340 if (use_tmp) {
4341 /* move result from temp to dst */
4342 for (i = 0; i <= lasti; i++) {
4343 if (!(write_mask & (1 << i)))
4344 continue;
4345
4346 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4347 alu.op = ALU_OP1_MOV;
4348 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4349 alu.src[0].sel = ctx->temp_reg;
4350 alu.src[0].chan = i;
4351 alu.last = (i == lasti);
4352
4353 r = r600_bytecode_add_alu(ctx->bc, &alu);
4354 if (r)
4355 return r;
4356 }
4357 }
4358 return 0;
4359 }
4360
4361 static int tgsi_op2(struct r600_shader_ctx *ctx)
4362 {
4363 return tgsi_op2_s(ctx, 0, 0);
4364 }
4365
4366 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4367 {
4368 return tgsi_op2_s(ctx, 1, 0);
4369 }
4370
4371 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4372 {
4373 return tgsi_op2_s(ctx, 0, 1);
4374 }
4375
4376 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4377 {
4378 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4379 struct r600_bytecode_alu alu;
4380 int i, r;
4381 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4382
4383 for (i = 0; i < lasti + 1; i++) {
4384
4385 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4386 continue;
4387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4388 alu.op = ctx->inst_info->op;
4389
4390 alu.src[0].sel = V_SQ_ALU_SRC_0;
4391
4392 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4393
4394 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4395
4396 if (i == lasti) {
4397 alu.last = 1;
4398 }
4399 r = r600_bytecode_add_alu(ctx->bc, &alu);
4400 if (r)
4401 return r;
4402 }
4403 return 0;
4404
4405 }
4406
4407 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4408 {
4409 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4410 struct r600_bytecode_alu alu;
4411 int i, r;
4412 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4413
4414 for (i = 0; i < lasti + 1; i++) {
4415
4416 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4417 continue;
4418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4419 alu.op = ALU_OP1_MOV;
4420
4421 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4422
4423 if (i == 1 || i == 3)
4424 r600_bytecode_src_toggle_neg(&alu.src[0]);
4425 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4426
4427 if (i == lasti) {
4428 alu.last = 1;
4429 }
4430 r = r600_bytecode_add_alu(ctx->bc, &alu);
4431 if (r)
4432 return r;
4433 }
4434 return 0;
4435
4436 }
4437
4438 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4439 {
4440 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4441 struct r600_bytecode_alu alu;
4442 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4443 int i, j, r;
4444
4445 for (i = 0; i <= 3; i++) {
4446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4447 alu.op = ctx->inst_info->op;
4448
4449 alu.dst.sel = ctx->temp_reg;
4450 alu.dst.chan = i;
4451 alu.dst.write = 1;
4452 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4453 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4454 }
4455
4456 if (i == 3)
4457 alu.last = 1;
4458
4459 r = r600_bytecode_add_alu(ctx->bc, &alu);
4460 if (r)
4461 return r;
4462 }
4463
4464 /* Replicate significand result across channels. */
4465 for (i = 0; i <= 3; i++) {
4466 if (!(write_mask & (1 << i)))
4467 continue;
4468
4469 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4470 alu.op = ALU_OP1_MOV;
4471 alu.src[0].chan = (i & 1) + 2;
4472 alu.src[0].sel = ctx->temp_reg;
4473
4474 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4475 alu.dst.write = 1;
4476 alu.last = 1;
4477 r = r600_bytecode_add_alu(ctx->bc, &alu);
4478 if (r)
4479 return r;
4480 }
4481
4482 for (i = 0; i <= 3; i++) {
4483 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4484 /* MOV third channels to writemask dst1 */
4485 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4486 alu.op = ALU_OP1_MOV;
4487 alu.src[0].chan = 1;
4488 alu.src[0].sel = ctx->temp_reg;
4489
4490 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4491 alu.last = 1;
4492 r = r600_bytecode_add_alu(ctx->bc, &alu);
4493 if (r)
4494 return r;
4495 break;
4496 }
4497 }
4498 return 0;
4499 }
4500
4501
4502 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4503 {
4504 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4505 struct r600_bytecode_alu alu;
4506 int i, c, r;
4507 int write_mask = inst->Dst[0].Register.WriteMask;
4508 int temp_reg = r600_get_temp(ctx);
4509
4510 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4511 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4512
4513 for (c = 0; c < 2; c++) {
4514 int dchan = c * 2;
4515 if (write_mask & (0x3 << dchan)) {
4516 /* split into 24-bit int and 8-bit int */
4517 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4518 alu.op = ALU_OP2_AND_INT;
4519 alu.dst.sel = temp_reg;
4520 alu.dst.chan = dchan;
4521 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4522 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4523 alu.src[1].value = 0xffffff00;
4524 alu.dst.write = 1;
4525 r = r600_bytecode_add_alu(ctx->bc, &alu);
4526 if (r)
4527 return r;
4528
4529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4530 alu.op = ALU_OP2_AND_INT;
4531 alu.dst.sel = temp_reg;
4532 alu.dst.chan = dchan + 1;
4533 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4534 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4535 alu.src[1].value = 0xff;
4536 alu.dst.write = 1;
4537 alu.last = 1;
4538 r = r600_bytecode_add_alu(ctx->bc, &alu);
4539 if (r)
4540 return r;
4541 }
4542 }
4543
4544 for (c = 0; c < 2; c++) {
4545 int dchan = c * 2;
4546 if (write_mask & (0x3 << dchan)) {
4547 for (i = dchan; i <= dchan + 1; i++) {
4548 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4549 alu.op = i == dchan ? ctx->inst_info->op : ALU_OP1_UINT_TO_FLT;
4550
4551 alu.src[0].sel = temp_reg;
4552 alu.src[0].chan = i;
4553 alu.dst.sel = temp_reg;
4554 alu.dst.chan = i;
4555 alu.dst.write = 1;
4556 if (ctx->bc->chip_class == CAYMAN)
4557 alu.last = i == dchan + 1;
4558 else
4559 alu.last = 1; /* trans only ops on evergreen */
4560
4561 r = r600_bytecode_add_alu(ctx->bc, &alu);
4562 if (r)
4563 return r;
4564 }
4565 }
4566 }
4567
4568 for (c = 0; c < 2; c++) {
4569 int dchan = c * 2;
4570 if (write_mask & (0x3 << dchan)) {
4571 for (i = 0; i < 4; i++) {
4572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4573 alu.op = ALU_OP1_FLT32_TO_FLT64;
4574
4575 alu.src[0].chan = dchan + (i / 2);
4576 if (i == 0 || i == 2)
4577 alu.src[0].sel = temp_reg;
4578 else {
4579 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4580 alu.src[0].value = 0x0;
4581 }
4582 alu.dst.sel = ctx->temp_reg;
4583 alu.dst.chan = i;
4584 alu.last = i == 3;
4585 alu.dst.write = 1;
4586
4587 r = r600_bytecode_add_alu(ctx->bc, &alu);
4588 if (r)
4589 return r;
4590 }
4591
4592 for (i = 0; i <= 1; i++) {
4593 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4594 alu.op = ALU_OP2_ADD_64;
4595
4596 alu.src[0].chan = fp64_switch(i);
4597 alu.src[0].sel = ctx->temp_reg;
4598
4599 alu.src[1].chan = fp64_switch(i + 2);
4600 alu.src[1].sel = ctx->temp_reg;
4601 tgsi_dst(ctx, &inst->Dst[0], dchan + i, &alu.dst);
4602 alu.last = i == 1;
4603
4604 r = r600_bytecode_add_alu(ctx->bc, &alu);
4605 if (r)
4606 return r;
4607 }
4608 }
4609 }
4610
4611 return 0;
4612 }
4613
4614 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4615 {
4616 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4617 struct r600_bytecode_alu alu;
4618 int i, r;
4619 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4620 int treg = r600_get_temp(ctx);
4621 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4622 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4623
4624 /* do a 64->32 into a temp register */
4625 r = tgsi_op2_64_params(ctx, true, false, treg, ALU_OP1_FLT64_TO_FLT32);
4626 if (r)
4627 return r;
4628
4629 for (i = 0; i <= lasti; i++) {
4630 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4631 continue;
4632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4633 alu.op = ctx->inst_info->op;
4634
4635 alu.src[0].chan = i;
4636 alu.src[0].sel = treg;
4637 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4638 alu.last = (i == lasti);
4639
4640 r = r600_bytecode_add_alu(ctx->bc, &alu);
4641 if (r)
4642 return r;
4643 }
4644
4645 return 0;
4646 }
4647
4648 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4649 unsigned op,
4650 int dst_reg,
4651 struct r600_shader_src *src,
4652 bool abs)
4653 {
4654 struct r600_bytecode_alu alu;
4655 const int last_slot = 3;
4656 int r;
4657
4658 /* these have to write the result to X/Y by the looks of it */
4659 for (int i = 0 ; i < last_slot; i++) {
4660 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4661 alu.op = op;
4662
4663 r600_bytecode_src(&alu.src[0], src, 1);
4664 r600_bytecode_src(&alu.src[1], src, 0);
4665
4666 if (abs)
4667 r600_bytecode_src_set_abs(&alu.src[1]);
4668
4669 alu.dst.sel = dst_reg;
4670 alu.dst.chan = i;
4671 alu.dst.write = (i == 0 || i == 1);
4672
4673 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4674 alu.last = 1;
4675 r = r600_bytecode_add_alu(bc, &alu);
4676 if (r)
4677 return r;
4678 }
4679
4680 return 0;
4681 }
4682
4683 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4684 {
4685 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4686 int i, r;
4687 struct r600_bytecode_alu alu;
4688 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4689 int t1 = ctx->temp_reg;
4690
4691 /* should only be one src regs */
4692 assert(inst->Instruction.NumSrcRegs == 1);
4693
4694 /* only support one double at a time */
4695 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4696 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4697
4698 r = cayman_emit_unary_double_raw(
4699 ctx->bc, ctx->inst_info->op, t1,
4700 &ctx->src[0],
4701 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4702 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4703 if (r)
4704 return r;
4705
4706 for (i = 0 ; i <= lasti; i++) {
4707 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4708 continue;
4709 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4710 alu.op = ALU_OP1_MOV;
4711 alu.src[0].sel = t1;
4712 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4713 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4714 alu.dst.write = 1;
4715 if (i == lasti)
4716 alu.last = 1;
4717 r = r600_bytecode_add_alu(ctx->bc, &alu);
4718 if (r)
4719 return r;
4720 }
4721 return 0;
4722 }
4723
4724 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4725 {
4726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4727 int i, j, r;
4728 struct r600_bytecode_alu alu;
4729 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4730
4731 for (i = 0 ; i < last_slot; i++) {
4732 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4733 alu.op = ctx->inst_info->op;
4734 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4735 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4736
4737 /* RSQ should take the absolute value of src */
4738 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4739 r600_bytecode_src_set_abs(&alu.src[j]);
4740 }
4741 }
4742 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4743 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4744
4745 if (i == last_slot - 1)
4746 alu.last = 1;
4747 r = r600_bytecode_add_alu(ctx->bc, &alu);
4748 if (r)
4749 return r;
4750 }
4751 return 0;
4752 }
4753
4754 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4755 {
4756 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4757 int i, j, k, r;
4758 struct r600_bytecode_alu alu;
4759 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4760 int t1 = ctx->temp_reg;
4761
4762 for (k = 0; k <= lasti; k++) {
4763 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4764 continue;
4765
4766 for (i = 0 ; i < 4; i++) {
4767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4768 alu.op = ctx->inst_info->op;
4769 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4770 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4771 }
4772 alu.dst.sel = t1;
4773 alu.dst.chan = i;
4774 alu.dst.write = (i == k);
4775 if (i == 3)
4776 alu.last = 1;
4777 r = r600_bytecode_add_alu(ctx->bc, &alu);
4778 if (r)
4779 return r;
4780 }
4781 }
4782
4783 for (i = 0 ; i <= lasti; i++) {
4784 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4785 continue;
4786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4787 alu.op = ALU_OP1_MOV;
4788 alu.src[0].sel = t1;
4789 alu.src[0].chan = i;
4790 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4791 alu.dst.write = 1;
4792 if (i == lasti)
4793 alu.last = 1;
4794 r = r600_bytecode_add_alu(ctx->bc, &alu);
4795 if (r)
4796 return r;
4797 }
4798
4799 return 0;
4800 }
4801
4802
4803 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4804 {
4805 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4806 int i, j, k, r;
4807 struct r600_bytecode_alu alu;
4808 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4809 int t1 = ctx->temp_reg;
4810
4811 /* t1 would get overwritten below if we actually tried to
4812 * multiply two pairs of doubles at a time. */
4813 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4814 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4815
4816 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4817
4818 for (i = 0; i < 4; i++) {
4819 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4820 alu.op = ctx->inst_info->op;
4821 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4822 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4823 }
4824 alu.dst.sel = t1;
4825 alu.dst.chan = i;
4826 alu.dst.write = 1;
4827 if (i == 3)
4828 alu.last = 1;
4829 r = r600_bytecode_add_alu(ctx->bc, &alu);
4830 if (r)
4831 return r;
4832 }
4833
4834 for (i = 0; i <= lasti; i++) {
4835 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4836 continue;
4837 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4838 alu.op = ALU_OP1_MOV;
4839 alu.src[0].sel = t1;
4840 alu.src[0].chan = i;
4841 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4842 alu.dst.write = 1;
4843 if (i == lasti)
4844 alu.last = 1;
4845 r = r600_bytecode_add_alu(ctx->bc, &alu);
4846 if (r)
4847 return r;
4848 }
4849
4850 return 0;
4851 }
4852
4853 /*
4854 * Emit RECIP_64 + MUL_64 to implement division.
4855 */
4856 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4857 {
4858 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4859 int r;
4860 struct r600_bytecode_alu alu;
4861 int t1 = ctx->temp_reg;
4862 int k;
4863
4864 /* Only support one double at a time. This is the same constraint as
4865 * in DMUL lowering. */
4866 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4867 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4868
4869 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4870
4871 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4872 if (r)
4873 return r;
4874
4875 for (int i = 0; i < 4; i++) {
4876 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4877 alu.op = ALU_OP2_MUL_64;
4878
4879 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4880
4881 alu.src[1].sel = t1;
4882 alu.src[1].chan = (i == 3) ? 0 : 1;
4883
4884 alu.dst.sel = t1;
4885 alu.dst.chan = i;
4886 alu.dst.write = 1;
4887 if (i == 3)
4888 alu.last = 1;
4889 r = r600_bytecode_add_alu(ctx->bc, &alu);
4890 if (r)
4891 return r;
4892 }
4893
4894 for (int i = 0; i < 2; i++) {
4895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4896 alu.op = ALU_OP1_MOV;
4897 alu.src[0].sel = t1;
4898 alu.src[0].chan = i;
4899 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4900 alu.dst.write = 1;
4901 if (i == 1)
4902 alu.last = 1;
4903 r = r600_bytecode_add_alu(ctx->bc, &alu);
4904 if (r)
4905 return r;
4906 }
4907 return 0;
4908 }
4909
4910 /*
4911 * r600 - trunc to -PI..PI range
4912 * r700 - normalize by dividing by 2PI
4913 * see fdo bug 27901
4914 */
4915 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4916 {
4917 int r;
4918 struct r600_bytecode_alu alu;
4919
4920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4921 alu.op = ALU_OP3_MULADD;
4922 alu.is_op3 = 1;
4923
4924 alu.dst.chan = 0;
4925 alu.dst.sel = ctx->temp_reg;
4926 alu.dst.write = 1;
4927
4928 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4929
4930 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4931 alu.src[1].chan = 0;
4932 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4933 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4934 alu.src[2].chan = 0;
4935 alu.last = 1;
4936 r = r600_bytecode_add_alu(ctx->bc, &alu);
4937 if (r)
4938 return r;
4939
4940 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4941 alu.op = ALU_OP1_FRACT;
4942
4943 alu.dst.chan = 0;
4944 alu.dst.sel = ctx->temp_reg;
4945 alu.dst.write = 1;
4946
4947 alu.src[0].sel = ctx->temp_reg;
4948 alu.src[0].chan = 0;
4949 alu.last = 1;
4950 r = r600_bytecode_add_alu(ctx->bc, &alu);
4951 if (r)
4952 return r;
4953
4954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4955 alu.op = ALU_OP3_MULADD;
4956 alu.is_op3 = 1;
4957
4958 alu.dst.chan = 0;
4959 alu.dst.sel = ctx->temp_reg;
4960 alu.dst.write = 1;
4961
4962 alu.src[0].sel = ctx->temp_reg;
4963 alu.src[0].chan = 0;
4964
4965 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4966 alu.src[1].chan = 0;
4967 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4968 alu.src[2].chan = 0;
4969
4970 if (ctx->bc->chip_class == R600) {
4971 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4972 alu.src[2].value = u_bitcast_f2u(-M_PI);
4973 } else {
4974 alu.src[1].sel = V_SQ_ALU_SRC_1;
4975 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4976 alu.src[2].neg = 1;
4977 }
4978
4979 alu.last = 1;
4980 r = r600_bytecode_add_alu(ctx->bc, &alu);
4981 if (r)
4982 return r;
4983 return 0;
4984 }
4985
4986 static int cayman_trig(struct r600_shader_ctx *ctx)
4987 {
4988 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4989 struct r600_bytecode_alu alu;
4990 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4991 int i, r;
4992
4993 r = tgsi_setup_trig(ctx);
4994 if (r)
4995 return r;
4996
4997
4998 for (i = 0; i < last_slot; i++) {
4999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5000 alu.op = ctx->inst_info->op;
5001 alu.dst.chan = i;
5002
5003 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5004 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5005
5006 alu.src[0].sel = ctx->temp_reg;
5007 alu.src[0].chan = 0;
5008 if (i == last_slot - 1)
5009 alu.last = 1;
5010 r = r600_bytecode_add_alu(ctx->bc, &alu);
5011 if (r)
5012 return r;
5013 }
5014 return 0;
5015 }
5016
5017 static int tgsi_trig(struct r600_shader_ctx *ctx)
5018 {
5019 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5020 struct r600_bytecode_alu alu;
5021 int i, r;
5022 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5023
5024 r = tgsi_setup_trig(ctx);
5025 if (r)
5026 return r;
5027
5028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5029 alu.op = ctx->inst_info->op;
5030 alu.dst.chan = 0;
5031 alu.dst.sel = ctx->temp_reg;
5032 alu.dst.write = 1;
5033
5034 alu.src[0].sel = ctx->temp_reg;
5035 alu.src[0].chan = 0;
5036 alu.last = 1;
5037 r = r600_bytecode_add_alu(ctx->bc, &alu);
5038 if (r)
5039 return r;
5040
5041 /* replicate result */
5042 for (i = 0; i < lasti + 1; i++) {
5043 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5044 continue;
5045
5046 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5047 alu.op = ALU_OP1_MOV;
5048
5049 alu.src[0].sel = ctx->temp_reg;
5050 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5051 if (i == lasti)
5052 alu.last = 1;
5053 r = r600_bytecode_add_alu(ctx->bc, &alu);
5054 if (r)
5055 return r;
5056 }
5057 return 0;
5058 }
5059
5060 static int tgsi_kill(struct r600_shader_ctx *ctx)
5061 {
5062 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5063 struct r600_bytecode_alu alu;
5064 int i, r;
5065
5066 for (i = 0; i < 4; i++) {
5067 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5068 alu.op = ctx->inst_info->op;
5069
5070 alu.dst.chan = i;
5071
5072 alu.src[0].sel = V_SQ_ALU_SRC_0;
5073
5074 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
5075 alu.src[1].sel = V_SQ_ALU_SRC_1;
5076 alu.src[1].neg = 1;
5077 } else {
5078 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5079 }
5080 if (i == 3) {
5081 alu.last = 1;
5082 }
5083 r = r600_bytecode_add_alu(ctx->bc, &alu);
5084 if (r)
5085 return r;
5086 }
5087
5088 /* kill must be last in ALU */
5089 ctx->bc->force_add_cf = 1;
5090 ctx->shader->uses_kill = TRUE;
5091 return 0;
5092 }
5093
5094 static int tgsi_lit(struct r600_shader_ctx *ctx)
5095 {
5096 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5097 struct r600_bytecode_alu alu;
5098 int r;
5099
5100 /* tmp.x = max(src.y, 0.0) */
5101 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5102 alu.op = ALU_OP2_MAX;
5103 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
5104 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5105 alu.src[1].chan = 1;
5106
5107 alu.dst.sel = ctx->temp_reg;
5108 alu.dst.chan = 0;
5109 alu.dst.write = 1;
5110
5111 alu.last = 1;
5112 r = r600_bytecode_add_alu(ctx->bc, &alu);
5113 if (r)
5114 return r;
5115
5116 if (inst->Dst[0].Register.WriteMask & (1 << 2))
5117 {
5118 int chan;
5119 int sel;
5120 unsigned i;
5121
5122 if (ctx->bc->chip_class == CAYMAN) {
5123 for (i = 0; i < 3; i++) {
5124 /* tmp.z = log(tmp.x) */
5125 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5126 alu.op = ALU_OP1_LOG_CLAMPED;
5127 alu.src[0].sel = ctx->temp_reg;
5128 alu.src[0].chan = 0;
5129 alu.dst.sel = ctx->temp_reg;
5130 alu.dst.chan = i;
5131 if (i == 2) {
5132 alu.dst.write = 1;
5133 alu.last = 1;
5134 } else
5135 alu.dst.write = 0;
5136
5137 r = r600_bytecode_add_alu(ctx->bc, &alu);
5138 if (r)
5139 return r;
5140 }
5141 } else {
5142 /* tmp.z = log(tmp.x) */
5143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5144 alu.op = ALU_OP1_LOG_CLAMPED;
5145 alu.src[0].sel = ctx->temp_reg;
5146 alu.src[0].chan = 0;
5147 alu.dst.sel = ctx->temp_reg;
5148 alu.dst.chan = 2;
5149 alu.dst.write = 1;
5150 alu.last = 1;
5151 r = r600_bytecode_add_alu(ctx->bc, &alu);
5152 if (r)
5153 return r;
5154 }
5155
5156 chan = alu.dst.chan;
5157 sel = alu.dst.sel;
5158
5159 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
5160 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5161 alu.op = ALU_OP3_MUL_LIT;
5162 alu.src[0].sel = sel;
5163 alu.src[0].chan = chan;
5164 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
5165 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
5166 alu.dst.sel = ctx->temp_reg;
5167 alu.dst.chan = 0;
5168 alu.dst.write = 1;
5169 alu.is_op3 = 1;
5170 alu.last = 1;
5171 r = r600_bytecode_add_alu(ctx->bc, &alu);
5172 if (r)
5173 return r;
5174
5175 if (ctx->bc->chip_class == CAYMAN) {
5176 for (i = 0; i < 3; i++) {
5177 /* dst.z = exp(tmp.x) */
5178 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5179 alu.op = ALU_OP1_EXP_IEEE;
5180 alu.src[0].sel = ctx->temp_reg;
5181 alu.src[0].chan = 0;
5182 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5183 if (i == 2) {
5184 alu.dst.write = 1;
5185 alu.last = 1;
5186 } else
5187 alu.dst.write = 0;
5188 r = r600_bytecode_add_alu(ctx->bc, &alu);
5189 if (r)
5190 return r;
5191 }
5192 } else {
5193 /* dst.z = exp(tmp.x) */
5194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5195 alu.op = ALU_OP1_EXP_IEEE;
5196 alu.src[0].sel = ctx->temp_reg;
5197 alu.src[0].chan = 0;
5198 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5199 alu.last = 1;
5200 r = r600_bytecode_add_alu(ctx->bc, &alu);
5201 if (r)
5202 return r;
5203 }
5204 }
5205
5206 /* dst.x, <- 1.0 */
5207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5208 alu.op = ALU_OP1_MOV;
5209 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
5210 alu.src[0].chan = 0;
5211 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5212 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
5213 r = r600_bytecode_add_alu(ctx->bc, &alu);
5214 if (r)
5215 return r;
5216
5217 /* dst.y = max(src.x, 0.0) */
5218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5219 alu.op = ALU_OP2_MAX;
5220 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5221 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5222 alu.src[1].chan = 0;
5223 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
5224 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
5225 r = r600_bytecode_add_alu(ctx->bc, &alu);
5226 if (r)
5227 return r;
5228
5229 /* dst.w, <- 1.0 */
5230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5231 alu.op = ALU_OP1_MOV;
5232 alu.src[0].sel = V_SQ_ALU_SRC_1;
5233 alu.src[0].chan = 0;
5234 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
5235 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
5236 alu.last = 1;
5237 r = r600_bytecode_add_alu(ctx->bc, &alu);
5238 if (r)
5239 return r;
5240
5241 return 0;
5242 }
5243
5244 static int tgsi_rsq(struct r600_shader_ctx *ctx)
5245 {
5246 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5247 struct r600_bytecode_alu alu;
5248 int i, r;
5249
5250 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5251
5252 alu.op = ALU_OP1_RECIPSQRT_IEEE;
5253
5254 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5255 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5256 r600_bytecode_src_set_abs(&alu.src[i]);
5257 }
5258 alu.dst.sel = ctx->temp_reg;
5259 alu.dst.write = 1;
5260 alu.last = 1;
5261 r = r600_bytecode_add_alu(ctx->bc, &alu);
5262 if (r)
5263 return r;
5264 /* replicate result */
5265 return tgsi_helper_tempx_replicate(ctx);
5266 }
5267
5268 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
5269 {
5270 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5271 struct r600_bytecode_alu alu;
5272 int i, r;
5273
5274 for (i = 0; i < 4; i++) {
5275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5276 alu.src[0].sel = ctx->temp_reg;
5277 alu.op = ALU_OP1_MOV;
5278 alu.dst.chan = i;
5279 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5280 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5281 if (i == 3)
5282 alu.last = 1;
5283 r = r600_bytecode_add_alu(ctx->bc, &alu);
5284 if (r)
5285 return r;
5286 }
5287 return 0;
5288 }
5289
5290 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
5291 {
5292 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5293 struct r600_bytecode_alu alu;
5294 int i, r;
5295
5296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5297 alu.op = ctx->inst_info->op;
5298 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5299 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5300 }
5301 alu.dst.sel = ctx->temp_reg;
5302 alu.dst.write = 1;
5303 alu.last = 1;
5304 r = r600_bytecode_add_alu(ctx->bc, &alu);
5305 if (r)
5306 return r;
5307 /* replicate result */
5308 return tgsi_helper_tempx_replicate(ctx);
5309 }
5310
5311 static int cayman_pow(struct r600_shader_ctx *ctx)
5312 {
5313 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5314 int i, r;
5315 struct r600_bytecode_alu alu;
5316 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5317
5318 for (i = 0; i < 3; i++) {
5319 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5320 alu.op = ALU_OP1_LOG_IEEE;
5321 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5322 alu.dst.sel = ctx->temp_reg;
5323 alu.dst.chan = i;
5324 alu.dst.write = 1;
5325 if (i == 2)
5326 alu.last = 1;
5327 r = r600_bytecode_add_alu(ctx->bc, &alu);
5328 if (r)
5329 return r;
5330 }
5331
5332 /* b * LOG2(a) */
5333 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5334 alu.op = ALU_OP2_MUL;
5335 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5336 alu.src[1].sel = ctx->temp_reg;
5337 alu.dst.sel = ctx->temp_reg;
5338 alu.dst.write = 1;
5339 alu.last = 1;
5340 r = r600_bytecode_add_alu(ctx->bc, &alu);
5341 if (r)
5342 return r;
5343
5344 for (i = 0; i < last_slot; i++) {
5345 /* POW(a,b) = EXP2(b * LOG2(a))*/
5346 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5347 alu.op = ALU_OP1_EXP_IEEE;
5348 alu.src[0].sel = ctx->temp_reg;
5349
5350 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5351 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5352 if (i == last_slot - 1)
5353 alu.last = 1;
5354 r = r600_bytecode_add_alu(ctx->bc, &alu);
5355 if (r)
5356 return r;
5357 }
5358 return 0;
5359 }
5360
5361 static int tgsi_pow(struct r600_shader_ctx *ctx)
5362 {
5363 struct r600_bytecode_alu alu;
5364 int r;
5365
5366 /* LOG2(a) */
5367 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5368 alu.op = ALU_OP1_LOG_IEEE;
5369 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5370 alu.dst.sel = ctx->temp_reg;
5371 alu.dst.write = 1;
5372 alu.last = 1;
5373 r = r600_bytecode_add_alu(ctx->bc, &alu);
5374 if (r)
5375 return r;
5376 /* b * LOG2(a) */
5377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5378 alu.op = ALU_OP2_MUL;
5379 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5380 alu.src[1].sel = ctx->temp_reg;
5381 alu.dst.sel = ctx->temp_reg;
5382 alu.dst.write = 1;
5383 alu.last = 1;
5384 r = r600_bytecode_add_alu(ctx->bc, &alu);
5385 if (r)
5386 return r;
5387 /* POW(a,b) = EXP2(b * LOG2(a))*/
5388 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5389 alu.op = ALU_OP1_EXP_IEEE;
5390 alu.src[0].sel = ctx->temp_reg;
5391 alu.dst.sel = ctx->temp_reg;
5392 alu.dst.write = 1;
5393 alu.last = 1;
5394 r = r600_bytecode_add_alu(ctx->bc, &alu);
5395 if (r)
5396 return r;
5397 return tgsi_helper_tempx_replicate(ctx);
5398 }
5399
5400 static int emit_mul_int_op(struct r600_bytecode *bc,
5401 struct r600_bytecode_alu *alu_src)
5402 {
5403 struct r600_bytecode_alu alu;
5404 int i, r;
5405 alu = *alu_src;
5406 if (bc->chip_class == CAYMAN) {
5407 for (i = 0; i < 4; i++) {
5408 alu.dst.chan = i;
5409 alu.dst.write = (i == alu_src->dst.chan);
5410 alu.last = (i == 3);
5411
5412 r = r600_bytecode_add_alu(bc, &alu);
5413 if (r)
5414 return r;
5415 }
5416 } else {
5417 alu.last = 1;
5418 r = r600_bytecode_add_alu(bc, &alu);
5419 if (r)
5420 return r;
5421 }
5422 return 0;
5423 }
5424
5425 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5426 {
5427 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5428 struct r600_bytecode_alu alu;
5429 int i, r, j;
5430 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5431 int tmp0 = ctx->temp_reg;
5432 int tmp1 = r600_get_temp(ctx);
5433 int tmp2 = r600_get_temp(ctx);
5434 int tmp3 = r600_get_temp(ctx);
5435 /* Unsigned path:
5436 *
5437 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5438 *
5439 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5440 * 2. tmp0.z = lo (tmp0.x * src2)
5441 * 3. tmp0.w = -tmp0.z
5442 * 4. tmp0.y = hi (tmp0.x * src2)
5443 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5444 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5445 * 7. tmp1.x = tmp0.x - tmp0.w
5446 * 8. tmp1.y = tmp0.x + tmp0.w
5447 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5448 * 10. tmp0.z = hi(tmp0.x * src1) = q
5449 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5450 *
5451 * 12. tmp0.w = src1 - tmp0.y = r
5452 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5453 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5454 *
5455 * if DIV
5456 *
5457 * 15. tmp1.z = tmp0.z + 1 = q + 1
5458 * 16. tmp1.w = tmp0.z - 1 = q - 1
5459 *
5460 * else MOD
5461 *
5462 * 15. tmp1.z = tmp0.w - src2 = r - src2
5463 * 16. tmp1.w = tmp0.w + src2 = r + src2
5464 *
5465 * endif
5466 *
5467 * 17. tmp1.x = tmp1.x & tmp1.y
5468 *
5469 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5470 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5471 *
5472 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5473 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5474 *
5475 * Signed path:
5476 *
5477 * Same as unsigned, using abs values of the operands,
5478 * and fixing the sign of the result in the end.
5479 */
5480
5481 for (i = 0; i < 4; i++) {
5482 if (!(write_mask & (1<<i)))
5483 continue;
5484
5485 if (signed_op) {
5486
5487 /* tmp2.x = -src0 */
5488 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5489 alu.op = ALU_OP2_SUB_INT;
5490
5491 alu.dst.sel = tmp2;
5492 alu.dst.chan = 0;
5493 alu.dst.write = 1;
5494
5495 alu.src[0].sel = V_SQ_ALU_SRC_0;
5496
5497 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5498
5499 alu.last = 1;
5500 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5501 return r;
5502
5503 /* tmp2.y = -src1 */
5504 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5505 alu.op = ALU_OP2_SUB_INT;
5506
5507 alu.dst.sel = tmp2;
5508 alu.dst.chan = 1;
5509 alu.dst.write = 1;
5510
5511 alu.src[0].sel = V_SQ_ALU_SRC_0;
5512
5513 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5514
5515 alu.last = 1;
5516 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5517 return r;
5518
5519 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5520 /* it will be a sign of the quotient */
5521 if (!mod) {
5522
5523 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5524 alu.op = ALU_OP2_XOR_INT;
5525
5526 alu.dst.sel = tmp2;
5527 alu.dst.chan = 2;
5528 alu.dst.write = 1;
5529
5530 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5531 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5532
5533 alu.last = 1;
5534 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5535 return r;
5536 }
5537
5538 /* tmp2.x = |src0| */
5539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5540 alu.op = ALU_OP3_CNDGE_INT;
5541 alu.is_op3 = 1;
5542
5543 alu.dst.sel = tmp2;
5544 alu.dst.chan = 0;
5545 alu.dst.write = 1;
5546
5547 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5548 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5549 alu.src[2].sel = tmp2;
5550 alu.src[2].chan = 0;
5551
5552 alu.last = 1;
5553 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5554 return r;
5555
5556 /* tmp2.y = |src1| */
5557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5558 alu.op = ALU_OP3_CNDGE_INT;
5559 alu.is_op3 = 1;
5560
5561 alu.dst.sel = tmp2;
5562 alu.dst.chan = 1;
5563 alu.dst.write = 1;
5564
5565 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5566 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5567 alu.src[2].sel = tmp2;
5568 alu.src[2].chan = 1;
5569
5570 alu.last = 1;
5571 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5572 return r;
5573
5574 }
5575
5576 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5577 if (ctx->bc->chip_class == CAYMAN) {
5578 /* tmp3.x = u2f(src2) */
5579 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5580 alu.op = ALU_OP1_UINT_TO_FLT;
5581
5582 alu.dst.sel = tmp3;
5583 alu.dst.chan = 0;
5584 alu.dst.write = 1;
5585
5586 if (signed_op) {
5587 alu.src[0].sel = tmp2;
5588 alu.src[0].chan = 1;
5589 } else {
5590 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5591 }
5592
5593 alu.last = 1;
5594 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5595 return r;
5596
5597 /* tmp0.x = recip(tmp3.x) */
5598 for (j = 0 ; j < 3; j++) {
5599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5600 alu.op = ALU_OP1_RECIP_IEEE;
5601
5602 alu.dst.sel = tmp0;
5603 alu.dst.chan = j;
5604 alu.dst.write = (j == 0);
5605
5606 alu.src[0].sel = tmp3;
5607 alu.src[0].chan = 0;
5608
5609 if (j == 2)
5610 alu.last = 1;
5611 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5612 return r;
5613 }
5614
5615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5616 alu.op = ALU_OP2_MUL;
5617
5618 alu.src[0].sel = tmp0;
5619 alu.src[0].chan = 0;
5620
5621 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5622 alu.src[1].value = 0x4f800000;
5623
5624 alu.dst.sel = tmp3;
5625 alu.dst.write = 1;
5626 alu.last = 1;
5627 r = r600_bytecode_add_alu(ctx->bc, &alu);
5628 if (r)
5629 return r;
5630
5631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5632 alu.op = ALU_OP1_FLT_TO_UINT;
5633
5634 alu.dst.sel = tmp0;
5635 alu.dst.chan = 0;
5636 alu.dst.write = 1;
5637
5638 alu.src[0].sel = tmp3;
5639 alu.src[0].chan = 0;
5640
5641 alu.last = 1;
5642 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5643 return r;
5644
5645 } else {
5646 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5647 alu.op = ALU_OP1_RECIP_UINT;
5648
5649 alu.dst.sel = tmp0;
5650 alu.dst.chan = 0;
5651 alu.dst.write = 1;
5652
5653 if (signed_op) {
5654 alu.src[0].sel = tmp2;
5655 alu.src[0].chan = 1;
5656 } else {
5657 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5658 }
5659
5660 alu.last = 1;
5661 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5662 return r;
5663 }
5664
5665 /* 2. tmp0.z = lo (tmp0.x * src2) */
5666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5667 alu.op = ALU_OP2_MULLO_UINT;
5668
5669 alu.dst.sel = tmp0;
5670 alu.dst.chan = 2;
5671 alu.dst.write = 1;
5672
5673 alu.src[0].sel = tmp0;
5674 alu.src[0].chan = 0;
5675 if (signed_op) {
5676 alu.src[1].sel = tmp2;
5677 alu.src[1].chan = 1;
5678 } else {
5679 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5680 }
5681
5682 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5683 return r;
5684
5685 /* 3. tmp0.w = -tmp0.z */
5686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5687 alu.op = ALU_OP2_SUB_INT;
5688
5689 alu.dst.sel = tmp0;
5690 alu.dst.chan = 3;
5691 alu.dst.write = 1;
5692
5693 alu.src[0].sel = V_SQ_ALU_SRC_0;
5694 alu.src[1].sel = tmp0;
5695 alu.src[1].chan = 2;
5696
5697 alu.last = 1;
5698 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5699 return r;
5700
5701 /* 4. tmp0.y = hi (tmp0.x * src2) */
5702 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5703 alu.op = ALU_OP2_MULHI_UINT;
5704
5705 alu.dst.sel = tmp0;
5706 alu.dst.chan = 1;
5707 alu.dst.write = 1;
5708
5709 alu.src[0].sel = tmp0;
5710 alu.src[0].chan = 0;
5711
5712 if (signed_op) {
5713 alu.src[1].sel = tmp2;
5714 alu.src[1].chan = 1;
5715 } else {
5716 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5717 }
5718
5719 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5720 return r;
5721
5722 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5723 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5724 alu.op = ALU_OP3_CNDE_INT;
5725 alu.is_op3 = 1;
5726
5727 alu.dst.sel = tmp0;
5728 alu.dst.chan = 2;
5729 alu.dst.write = 1;
5730
5731 alu.src[0].sel = tmp0;
5732 alu.src[0].chan = 1;
5733 alu.src[1].sel = tmp0;
5734 alu.src[1].chan = 3;
5735 alu.src[2].sel = tmp0;
5736 alu.src[2].chan = 2;
5737
5738 alu.last = 1;
5739 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5740 return r;
5741
5742 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5743 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5744 alu.op = ALU_OP2_MULHI_UINT;
5745
5746 alu.dst.sel = tmp0;
5747 alu.dst.chan = 3;
5748 alu.dst.write = 1;
5749
5750 alu.src[0].sel = tmp0;
5751 alu.src[0].chan = 2;
5752
5753 alu.src[1].sel = tmp0;
5754 alu.src[1].chan = 0;
5755
5756 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5757 return r;
5758
5759 /* 7. tmp1.x = tmp0.x - tmp0.w */
5760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5761 alu.op = ALU_OP2_SUB_INT;
5762
5763 alu.dst.sel = tmp1;
5764 alu.dst.chan = 0;
5765 alu.dst.write = 1;
5766
5767 alu.src[0].sel = tmp0;
5768 alu.src[0].chan = 0;
5769 alu.src[1].sel = tmp0;
5770 alu.src[1].chan = 3;
5771
5772 alu.last = 1;
5773 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5774 return r;
5775
5776 /* 8. tmp1.y = tmp0.x + tmp0.w */
5777 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5778 alu.op = ALU_OP2_ADD_INT;
5779
5780 alu.dst.sel = tmp1;
5781 alu.dst.chan = 1;
5782 alu.dst.write = 1;
5783
5784 alu.src[0].sel = tmp0;
5785 alu.src[0].chan = 0;
5786 alu.src[1].sel = tmp0;
5787 alu.src[1].chan = 3;
5788
5789 alu.last = 1;
5790 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5791 return r;
5792
5793 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5794 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5795 alu.op = ALU_OP3_CNDE_INT;
5796 alu.is_op3 = 1;
5797
5798 alu.dst.sel = tmp0;
5799 alu.dst.chan = 0;
5800 alu.dst.write = 1;
5801
5802 alu.src[0].sel = tmp0;
5803 alu.src[0].chan = 1;
5804 alu.src[1].sel = tmp1;
5805 alu.src[1].chan = 1;
5806 alu.src[2].sel = tmp1;
5807 alu.src[2].chan = 0;
5808
5809 alu.last = 1;
5810 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5811 return r;
5812
5813 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5815 alu.op = ALU_OP2_MULHI_UINT;
5816
5817 alu.dst.sel = tmp0;
5818 alu.dst.chan = 2;
5819 alu.dst.write = 1;
5820
5821 alu.src[0].sel = tmp0;
5822 alu.src[0].chan = 0;
5823
5824 if (signed_op) {
5825 alu.src[1].sel = tmp2;
5826 alu.src[1].chan = 0;
5827 } else {
5828 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5829 }
5830
5831 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5832 return r;
5833
5834 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5835 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5836 alu.op = ALU_OP2_MULLO_UINT;
5837
5838 alu.dst.sel = tmp0;
5839 alu.dst.chan = 1;
5840 alu.dst.write = 1;
5841
5842 if (signed_op) {
5843 alu.src[0].sel = tmp2;
5844 alu.src[0].chan = 1;
5845 } else {
5846 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5847 }
5848
5849 alu.src[1].sel = tmp0;
5850 alu.src[1].chan = 2;
5851
5852 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5853 return r;
5854
5855 /* 12. tmp0.w = src1 - tmp0.y = r */
5856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5857 alu.op = ALU_OP2_SUB_INT;
5858
5859 alu.dst.sel = tmp0;
5860 alu.dst.chan = 3;
5861 alu.dst.write = 1;
5862
5863 if (signed_op) {
5864 alu.src[0].sel = tmp2;
5865 alu.src[0].chan = 0;
5866 } else {
5867 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5868 }
5869
5870 alu.src[1].sel = tmp0;
5871 alu.src[1].chan = 1;
5872
5873 alu.last = 1;
5874 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5875 return r;
5876
5877 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5879 alu.op = ALU_OP2_SETGE_UINT;
5880
5881 alu.dst.sel = tmp1;
5882 alu.dst.chan = 0;
5883 alu.dst.write = 1;
5884
5885 alu.src[0].sel = tmp0;
5886 alu.src[0].chan = 3;
5887 if (signed_op) {
5888 alu.src[1].sel = tmp2;
5889 alu.src[1].chan = 1;
5890 } else {
5891 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5892 }
5893
5894 alu.last = 1;
5895 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5896 return r;
5897
5898 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5900 alu.op = ALU_OP2_SETGE_UINT;
5901
5902 alu.dst.sel = tmp1;
5903 alu.dst.chan = 1;
5904 alu.dst.write = 1;
5905
5906 if (signed_op) {
5907 alu.src[0].sel = tmp2;
5908 alu.src[0].chan = 0;
5909 } else {
5910 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5911 }
5912
5913 alu.src[1].sel = tmp0;
5914 alu.src[1].chan = 1;
5915
5916 alu.last = 1;
5917 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5918 return r;
5919
5920 if (mod) { /* UMOD */
5921
5922 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5923 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5924 alu.op = ALU_OP2_SUB_INT;
5925
5926 alu.dst.sel = tmp1;
5927 alu.dst.chan = 2;
5928 alu.dst.write = 1;
5929
5930 alu.src[0].sel = tmp0;
5931 alu.src[0].chan = 3;
5932
5933 if (signed_op) {
5934 alu.src[1].sel = tmp2;
5935 alu.src[1].chan = 1;
5936 } else {
5937 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5938 }
5939
5940 alu.last = 1;
5941 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5942 return r;
5943
5944 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5946 alu.op = ALU_OP2_ADD_INT;
5947
5948 alu.dst.sel = tmp1;
5949 alu.dst.chan = 3;
5950 alu.dst.write = 1;
5951
5952 alu.src[0].sel = tmp0;
5953 alu.src[0].chan = 3;
5954 if (signed_op) {
5955 alu.src[1].sel = tmp2;
5956 alu.src[1].chan = 1;
5957 } else {
5958 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5959 }
5960
5961 alu.last = 1;
5962 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5963 return r;
5964
5965 } else { /* UDIV */
5966
5967 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5969 alu.op = ALU_OP2_ADD_INT;
5970
5971 alu.dst.sel = tmp1;
5972 alu.dst.chan = 2;
5973 alu.dst.write = 1;
5974
5975 alu.src[0].sel = tmp0;
5976 alu.src[0].chan = 2;
5977 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5978
5979 alu.last = 1;
5980 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5981 return r;
5982
5983 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5985 alu.op = ALU_OP2_ADD_INT;
5986
5987 alu.dst.sel = tmp1;
5988 alu.dst.chan = 3;
5989 alu.dst.write = 1;
5990
5991 alu.src[0].sel = tmp0;
5992 alu.src[0].chan = 2;
5993 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5994
5995 alu.last = 1;
5996 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5997 return r;
5998
5999 }
6000
6001 /* 17. tmp1.x = tmp1.x & tmp1.y */
6002 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6003 alu.op = ALU_OP2_AND_INT;
6004
6005 alu.dst.sel = tmp1;
6006 alu.dst.chan = 0;
6007 alu.dst.write = 1;
6008
6009 alu.src[0].sel = tmp1;
6010 alu.src[0].chan = 0;
6011 alu.src[1].sel = tmp1;
6012 alu.src[1].chan = 1;
6013
6014 alu.last = 1;
6015 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6016 return r;
6017
6018 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
6019 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
6020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6021 alu.op = ALU_OP3_CNDE_INT;
6022 alu.is_op3 = 1;
6023
6024 alu.dst.sel = tmp0;
6025 alu.dst.chan = 2;
6026 alu.dst.write = 1;
6027
6028 alu.src[0].sel = tmp1;
6029 alu.src[0].chan = 0;
6030 alu.src[1].sel = tmp0;
6031 alu.src[1].chan = mod ? 3 : 2;
6032 alu.src[2].sel = tmp1;
6033 alu.src[2].chan = 2;
6034
6035 alu.last = 1;
6036 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6037 return r;
6038
6039 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
6040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6041 alu.op = ALU_OP3_CNDE_INT;
6042 alu.is_op3 = 1;
6043
6044 if (signed_op) {
6045 alu.dst.sel = tmp0;
6046 alu.dst.chan = 2;
6047 alu.dst.write = 1;
6048 } else {
6049 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6050 }
6051
6052 alu.src[0].sel = tmp1;
6053 alu.src[0].chan = 1;
6054 alu.src[1].sel = tmp1;
6055 alu.src[1].chan = 3;
6056 alu.src[2].sel = tmp0;
6057 alu.src[2].chan = 2;
6058
6059 alu.last = 1;
6060 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6061 return r;
6062
6063 if (signed_op) {
6064
6065 /* fix the sign of the result */
6066
6067 if (mod) {
6068
6069 /* tmp0.x = -tmp0.z */
6070 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6071 alu.op = ALU_OP2_SUB_INT;
6072
6073 alu.dst.sel = tmp0;
6074 alu.dst.chan = 0;
6075 alu.dst.write = 1;
6076
6077 alu.src[0].sel = V_SQ_ALU_SRC_0;
6078 alu.src[1].sel = tmp0;
6079 alu.src[1].chan = 2;
6080
6081 alu.last = 1;
6082 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6083 return r;
6084
6085 /* sign of the remainder is the same as the sign of src0 */
6086 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
6087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6088 alu.op = ALU_OP3_CNDGE_INT;
6089 alu.is_op3 = 1;
6090
6091 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6092
6093 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6094 alu.src[1].sel = tmp0;
6095 alu.src[1].chan = 2;
6096 alu.src[2].sel = tmp0;
6097 alu.src[2].chan = 0;
6098
6099 alu.last = 1;
6100 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6101 return r;
6102
6103 } else {
6104
6105 /* tmp0.x = -tmp0.z */
6106 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6107 alu.op = ALU_OP2_SUB_INT;
6108
6109 alu.dst.sel = tmp0;
6110 alu.dst.chan = 0;
6111 alu.dst.write = 1;
6112
6113 alu.src[0].sel = V_SQ_ALU_SRC_0;
6114 alu.src[1].sel = tmp0;
6115 alu.src[1].chan = 2;
6116
6117 alu.last = 1;
6118 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6119 return r;
6120
6121 /* fix the quotient sign (same as the sign of src0*src1) */
6122 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
6123 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6124 alu.op = ALU_OP3_CNDGE_INT;
6125 alu.is_op3 = 1;
6126
6127 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6128
6129 alu.src[0].sel = tmp2;
6130 alu.src[0].chan = 2;
6131 alu.src[1].sel = tmp0;
6132 alu.src[1].chan = 2;
6133 alu.src[2].sel = tmp0;
6134 alu.src[2].chan = 0;
6135
6136 alu.last = 1;
6137 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6138 return r;
6139 }
6140 }
6141 }
6142 return 0;
6143 }
6144
6145 static int tgsi_udiv(struct r600_shader_ctx *ctx)
6146 {
6147 return tgsi_divmod(ctx, 0, 0);
6148 }
6149
6150 static int tgsi_umod(struct r600_shader_ctx *ctx)
6151 {
6152 return tgsi_divmod(ctx, 1, 0);
6153 }
6154
6155 static int tgsi_idiv(struct r600_shader_ctx *ctx)
6156 {
6157 return tgsi_divmod(ctx, 0, 1);
6158 }
6159
6160 static int tgsi_imod(struct r600_shader_ctx *ctx)
6161 {
6162 return tgsi_divmod(ctx, 1, 1);
6163 }
6164
6165
6166 static int tgsi_f2i(struct r600_shader_ctx *ctx)
6167 {
6168 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6169 struct r600_bytecode_alu alu;
6170 int i, r;
6171 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6172 int last_inst = tgsi_last_instruction(write_mask);
6173
6174 for (i = 0; i < 4; i++) {
6175 if (!(write_mask & (1<<i)))
6176 continue;
6177
6178 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6179 alu.op = ALU_OP1_TRUNC;
6180
6181 alu.dst.sel = ctx->temp_reg;
6182 alu.dst.chan = i;
6183 alu.dst.write = 1;
6184
6185 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6186 if (i == last_inst)
6187 alu.last = 1;
6188 r = r600_bytecode_add_alu(ctx->bc, &alu);
6189 if (r)
6190 return r;
6191 }
6192
6193 for (i = 0; i < 4; i++) {
6194 if (!(write_mask & (1<<i)))
6195 continue;
6196
6197 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6198 alu.op = ctx->inst_info->op;
6199
6200 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6201
6202 alu.src[0].sel = ctx->temp_reg;
6203 alu.src[0].chan = i;
6204
6205 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6206 alu.last = 1;
6207 r = r600_bytecode_add_alu(ctx->bc, &alu);
6208 if (r)
6209 return r;
6210 }
6211
6212 return 0;
6213 }
6214
6215 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6216 {
6217 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6218 struct r600_bytecode_alu alu;
6219 int i, r;
6220 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6221 int last_inst = tgsi_last_instruction(write_mask);
6222
6223 /* tmp = -src */
6224 for (i = 0; i < 4; i++) {
6225 if (!(write_mask & (1<<i)))
6226 continue;
6227
6228 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6229 alu.op = ALU_OP2_SUB_INT;
6230
6231 alu.dst.sel = ctx->temp_reg;
6232 alu.dst.chan = i;
6233 alu.dst.write = 1;
6234
6235 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6236 alu.src[0].sel = V_SQ_ALU_SRC_0;
6237
6238 if (i == last_inst)
6239 alu.last = 1;
6240 r = r600_bytecode_add_alu(ctx->bc, &alu);
6241 if (r)
6242 return r;
6243 }
6244
6245 /* dst = (src >= 0 ? src : tmp) */
6246 for (i = 0; i < 4; i++) {
6247 if (!(write_mask & (1<<i)))
6248 continue;
6249
6250 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6251 alu.op = ALU_OP3_CNDGE_INT;
6252 alu.is_op3 = 1;
6253 alu.dst.write = 1;
6254
6255 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6256
6257 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6258 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6259 alu.src[2].sel = ctx->temp_reg;
6260 alu.src[2].chan = i;
6261
6262 if (i == last_inst)
6263 alu.last = 1;
6264 r = r600_bytecode_add_alu(ctx->bc, &alu);
6265 if (r)
6266 return r;
6267 }
6268 return 0;
6269 }
6270
6271 static int tgsi_issg(struct r600_shader_ctx *ctx)
6272 {
6273 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6274 struct r600_bytecode_alu alu;
6275 int i, r;
6276 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6277 int last_inst = tgsi_last_instruction(write_mask);
6278
6279 /* tmp = (src >= 0 ? src : -1) */
6280 for (i = 0; i < 4; i++) {
6281 if (!(write_mask & (1<<i)))
6282 continue;
6283
6284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6285 alu.op = ALU_OP3_CNDGE_INT;
6286 alu.is_op3 = 1;
6287
6288 alu.dst.sel = ctx->temp_reg;
6289 alu.dst.chan = i;
6290 alu.dst.write = 1;
6291
6292 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6293 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6294 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6295
6296 if (i == last_inst)
6297 alu.last = 1;
6298 r = r600_bytecode_add_alu(ctx->bc, &alu);
6299 if (r)
6300 return r;
6301 }
6302
6303 /* dst = (tmp > 0 ? 1 : tmp) */
6304 for (i = 0; i < 4; i++) {
6305 if (!(write_mask & (1<<i)))
6306 continue;
6307
6308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6309 alu.op = ALU_OP3_CNDGT_INT;
6310 alu.is_op3 = 1;
6311 alu.dst.write = 1;
6312
6313 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6314
6315 alu.src[0].sel = ctx->temp_reg;
6316 alu.src[0].chan = i;
6317
6318 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6319
6320 alu.src[2].sel = ctx->temp_reg;
6321 alu.src[2].chan = i;
6322
6323 if (i == last_inst)
6324 alu.last = 1;
6325 r = r600_bytecode_add_alu(ctx->bc, &alu);
6326 if (r)
6327 return r;
6328 }
6329 return 0;
6330 }
6331
6332
6333
6334 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6335 {
6336 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6337 struct r600_bytecode_alu alu;
6338 int i, r;
6339
6340 /* tmp = (src > 0 ? 1 : src) */
6341 for (i = 0; i < 4; i++) {
6342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6343 alu.op = ALU_OP3_CNDGT;
6344 alu.is_op3 = 1;
6345
6346 alu.dst.sel = ctx->temp_reg;
6347 alu.dst.chan = i;
6348
6349 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6350 alu.src[1].sel = V_SQ_ALU_SRC_1;
6351 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6352
6353 if (i == 3)
6354 alu.last = 1;
6355 r = r600_bytecode_add_alu(ctx->bc, &alu);
6356 if (r)
6357 return r;
6358 }
6359
6360 /* dst = (-tmp > 0 ? -1 : tmp) */
6361 for (i = 0; i < 4; i++) {
6362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6363 alu.op = ALU_OP3_CNDGT;
6364 alu.is_op3 = 1;
6365 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6366
6367 alu.src[0].sel = ctx->temp_reg;
6368 alu.src[0].chan = i;
6369 alu.src[0].neg = 1;
6370
6371 alu.src[1].sel = V_SQ_ALU_SRC_1;
6372 alu.src[1].neg = 1;
6373
6374 alu.src[2].sel = ctx->temp_reg;
6375 alu.src[2].chan = i;
6376
6377 if (i == 3)
6378 alu.last = 1;
6379 r = r600_bytecode_add_alu(ctx->bc, &alu);
6380 if (r)
6381 return r;
6382 }
6383 return 0;
6384 }
6385
6386 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6387 {
6388 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6389 struct r600_bytecode_alu alu;
6390 int i, r, t1, t2;
6391
6392 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6393 int last_inst = tgsi_last_instruction(write_mask);
6394
6395 t1 = r600_get_temp(ctx);
6396
6397 for (i = 0; i < 4; i++) {
6398 if (!(write_mask & (1<<i)))
6399 continue;
6400
6401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6402 alu.op = ALU_OP2_SETGE_INT;
6403 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6404 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6405 alu.src[1].value = 32;
6406 alu.dst.sel = ctx->temp_reg;
6407 alu.dst.chan = i;
6408 alu.dst.write = 1;
6409 alu.last = i == last_inst;
6410 r = r600_bytecode_add_alu(ctx->bc, &alu);
6411 if (r)
6412 return r;
6413 }
6414
6415 for (i = 0; i < 4; i++) {
6416 if (!(write_mask & (1<<i)))
6417 continue;
6418
6419 /* create mask tmp */
6420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6421 alu.op = ALU_OP2_BFM_INT;
6422 alu.dst.sel = t1;
6423 alu.dst.chan = i;
6424 alu.dst.write = 1;
6425 alu.last = i == last_inst;
6426
6427 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6428 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6429
6430 r = r600_bytecode_add_alu(ctx->bc, &alu);
6431 if (r)
6432 return r;
6433 }
6434
6435 t2 = r600_get_temp(ctx);
6436
6437 for (i = 0; i < 4; i++) {
6438 if (!(write_mask & (1<<i)))
6439 continue;
6440
6441 /* shift insert left */
6442 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6443 alu.op = ALU_OP2_LSHL_INT;
6444 alu.dst.sel = t2;
6445 alu.dst.chan = i;
6446 alu.dst.write = 1;
6447 alu.last = i == last_inst;
6448
6449 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6450 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6451
6452 r = r600_bytecode_add_alu(ctx->bc, &alu);
6453 if (r)
6454 return r;
6455 }
6456
6457 for (i = 0; i < 4; i++) {
6458 if (!(write_mask & (1<<i)))
6459 continue;
6460
6461 /* actual bitfield insert */
6462 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6463 alu.op = ALU_OP3_BFI_INT;
6464 alu.is_op3 = 1;
6465 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6466 alu.dst.chan = i;
6467 alu.dst.write = 1;
6468 alu.last = i == last_inst;
6469
6470 alu.src[0].sel = t1;
6471 alu.src[0].chan = i;
6472 alu.src[1].sel = t2;
6473 alu.src[1].chan = i;
6474 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6475
6476 r = r600_bytecode_add_alu(ctx->bc, &alu);
6477 if (r)
6478 return r;
6479 }
6480
6481 for (i = 0; i < 4; i++) {
6482 if (!(write_mask & (1<<i)))
6483 continue;
6484 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6485 alu.op = ALU_OP3_CNDE_INT;
6486 alu.is_op3 = 1;
6487 alu.src[0].sel = ctx->temp_reg;
6488 alu.src[0].chan = i;
6489 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6490
6491 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6492
6493 alu.src[1].sel = alu.dst.sel;
6494 alu.src[1].chan = i;
6495
6496 alu.last = i == last_inst;
6497 r = r600_bytecode_add_alu(ctx->bc, &alu);
6498 if (r)
6499 return r;
6500 }
6501 return 0;
6502 }
6503
6504 static int tgsi_msb(struct r600_shader_ctx *ctx)
6505 {
6506 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6507 struct r600_bytecode_alu alu;
6508 int i, r, t1, t2;
6509
6510 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6511 int last_inst = tgsi_last_instruction(write_mask);
6512
6513 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6514 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6515
6516 t1 = ctx->temp_reg;
6517
6518 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6519 for (i = 0; i < 4; i++) {
6520 if (!(write_mask & (1<<i)))
6521 continue;
6522
6523 /* t1 = FFBH_INT / FFBH_UINT */
6524 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6525 alu.op = ctx->inst_info->op;
6526 alu.dst.sel = t1;
6527 alu.dst.chan = i;
6528 alu.dst.write = 1;
6529 alu.last = i == last_inst;
6530
6531 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6532
6533 r = r600_bytecode_add_alu(ctx->bc, &alu);
6534 if (r)
6535 return r;
6536 }
6537
6538 t2 = r600_get_temp(ctx);
6539
6540 for (i = 0; i < 4; i++) {
6541 if (!(write_mask & (1<<i)))
6542 continue;
6543
6544 /* t2 = 31 - t1 */
6545 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6546 alu.op = ALU_OP2_SUB_INT;
6547 alu.dst.sel = t2;
6548 alu.dst.chan = i;
6549 alu.dst.write = 1;
6550 alu.last = i == last_inst;
6551
6552 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6553 alu.src[0].value = 31;
6554 alu.src[1].sel = t1;
6555 alu.src[1].chan = i;
6556
6557 r = r600_bytecode_add_alu(ctx->bc, &alu);
6558 if (r)
6559 return r;
6560 }
6561
6562 for (i = 0; i < 4; i++) {
6563 if (!(write_mask & (1<<i)))
6564 continue;
6565
6566 /* result = t1 >= 0 ? t2 : t1 */
6567 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6568 alu.op = ALU_OP3_CNDGE_INT;
6569 alu.is_op3 = 1;
6570 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6571 alu.dst.chan = i;
6572 alu.dst.write = 1;
6573 alu.last = i == last_inst;
6574
6575 alu.src[0].sel = t1;
6576 alu.src[0].chan = i;
6577 alu.src[1].sel = t2;
6578 alu.src[1].chan = i;
6579 alu.src[2].sel = t1;
6580 alu.src[2].chan = i;
6581
6582 r = r600_bytecode_add_alu(ctx->bc, &alu);
6583 if (r)
6584 return r;
6585 }
6586
6587 return 0;
6588 }
6589
6590 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6591 {
6592 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6593 struct r600_bytecode_alu alu;
6594 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6595 unsigned location;
6596 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6597
6598 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6599
6600 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6601 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6602 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6603 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6604 }
6605 else {
6606 location = TGSI_INTERPOLATE_LOC_CENTROID;
6607 }
6608
6609 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6610 if (k < 0)
6611 k = 0;
6612 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6613 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6614
6615 /* NOTE: currently offset is not perspective correct */
6616 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6617 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6618 int sample_gpr = -1;
6619 int gradientsH, gradientsV;
6620 struct r600_bytecode_tex tex;
6621
6622 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6623 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6624 }
6625
6626 gradientsH = r600_get_temp(ctx);
6627 gradientsV = r600_get_temp(ctx);
6628 for (i = 0; i < 2; i++) {
6629 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6630 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6631 tex.src_gpr = interp_gpr;
6632 tex.src_sel_x = interp_base_chan + 0;
6633 tex.src_sel_y = interp_base_chan + 1;
6634 tex.src_sel_z = 0;
6635 tex.src_sel_w = 0;
6636 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6637 tex.dst_sel_x = 0;
6638 tex.dst_sel_y = 1;
6639 tex.dst_sel_z = 7;
6640 tex.dst_sel_w = 7;
6641 tex.inst_mod = 1; // Use per pixel gradient calculation
6642 tex.sampler_id = 0;
6643 tex.resource_id = tex.sampler_id;
6644 r = r600_bytecode_add_tex(ctx->bc, &tex);
6645 if (r)
6646 return r;
6647 }
6648
6649 for (i = 0; i < 2; i++) {
6650 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6651 alu.op = ALU_OP3_MULADD;
6652 alu.is_op3 = 1;
6653 alu.src[0].sel = gradientsH;
6654 alu.src[0].chan = i;
6655 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6656 alu.src[1].sel = sample_gpr;
6657 alu.src[1].chan = 2;
6658 }
6659 else {
6660 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6661 }
6662 alu.src[2].sel = interp_gpr;
6663 alu.src[2].chan = interp_base_chan + i;
6664 alu.dst.sel = ctx->temp_reg;
6665 alu.dst.chan = i;
6666 alu.last = i == 1;
6667
6668 r = r600_bytecode_add_alu(ctx->bc, &alu);
6669 if (r)
6670 return r;
6671 }
6672
6673 for (i = 0; i < 2; i++) {
6674 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6675 alu.op = ALU_OP3_MULADD;
6676 alu.is_op3 = 1;
6677 alu.src[0].sel = gradientsV;
6678 alu.src[0].chan = i;
6679 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6680 alu.src[1].sel = sample_gpr;
6681 alu.src[1].chan = 3;
6682 }
6683 else {
6684 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6685 }
6686 alu.src[2].sel = ctx->temp_reg;
6687 alu.src[2].chan = i;
6688 alu.dst.sel = ctx->temp_reg;
6689 alu.dst.chan = i;
6690 alu.last = i == 1;
6691
6692 r = r600_bytecode_add_alu(ctx->bc, &alu);
6693 if (r)
6694 return r;
6695 }
6696 }
6697
6698 tmp = r600_get_temp(ctx);
6699 for (i = 0; i < 8; i++) {
6700 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6701 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6702
6703 alu.dst.sel = tmp;
6704 if ((i > 1 && i < 6)) {
6705 alu.dst.write = 1;
6706 }
6707 else {
6708 alu.dst.write = 0;
6709 }
6710 alu.dst.chan = i % 4;
6711
6712 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6713 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6714 alu.src[0].sel = ctx->temp_reg;
6715 alu.src[0].chan = 1 - (i % 2);
6716 } else {
6717 alu.src[0].sel = interp_gpr;
6718 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6719 }
6720 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6721 alu.src[1].chan = 0;
6722
6723 alu.last = i % 4 == 3;
6724 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6725
6726 r = r600_bytecode_add_alu(ctx->bc, &alu);
6727 if (r)
6728 return r;
6729 }
6730
6731 // INTERP can't swizzle dst
6732 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6733 for (i = 0; i <= lasti; i++) {
6734 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6735 continue;
6736
6737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6738 alu.op = ALU_OP1_MOV;
6739 alu.src[0].sel = tmp;
6740 alu.src[0].chan = ctx->src[0].swizzle[i];
6741 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6742 alu.dst.write = 1;
6743 alu.last = i == lasti;
6744 r = r600_bytecode_add_alu(ctx->bc, &alu);
6745 if (r)
6746 return r;
6747 }
6748
6749 return 0;
6750 }
6751
6752
6753 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6754 {
6755 struct r600_bytecode_alu alu;
6756 int i, r;
6757
6758 for (i = 0; i < 4; i++) {
6759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6760 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6761 alu.op = ALU_OP0_NOP;
6762 alu.dst.chan = i;
6763 } else {
6764 alu.op = ALU_OP1_MOV;
6765 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6766 alu.src[0].sel = ctx->temp_reg;
6767 alu.src[0].chan = i;
6768 }
6769 if (i == 3) {
6770 alu.last = 1;
6771 }
6772 r = r600_bytecode_add_alu(ctx->bc, &alu);
6773 if (r)
6774 return r;
6775 }
6776 return 0;
6777 }
6778
6779 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6780 unsigned temp, int chan,
6781 struct r600_bytecode_alu_src *bc_src,
6782 const struct r600_shader_src *shader_src)
6783 {
6784 struct r600_bytecode_alu alu;
6785 int r;
6786
6787 r600_bytecode_src(bc_src, shader_src, chan);
6788
6789 /* op3 operands don't support abs modifier */
6790 if (bc_src->abs) {
6791 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6792 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6793 alu.op = ALU_OP1_MOV;
6794 alu.dst.sel = temp;
6795 alu.dst.chan = chan;
6796 alu.dst.write = 1;
6797
6798 alu.src[0] = *bc_src;
6799 alu.last = true; // sufficient?
6800 r = r600_bytecode_add_alu(ctx->bc, &alu);
6801 if (r)
6802 return r;
6803
6804 memset(bc_src, 0, sizeof(*bc_src));
6805 bc_src->sel = temp;
6806 bc_src->chan = chan;
6807 }
6808 return 0;
6809 }
6810
6811 static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
6812 {
6813 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6814 struct r600_bytecode_alu alu;
6815 int i, j, r;
6816 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6817 int temp_regs[4];
6818 unsigned op = ctx->inst_info->op;
6819
6820 if (op == ALU_OP3_MULADD_IEEE &&
6821 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6822 op = ALU_OP3_MULADD;
6823
6824 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6825 temp_regs[j] = 0;
6826 if (ctx->src[j].abs)
6827 temp_regs[j] = r600_get_temp(ctx);
6828 }
6829 for (i = 0; i < lasti + 1; i++) {
6830 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6831 continue;
6832
6833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6834 alu.op = op;
6835 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6836 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6837 if (r)
6838 return r;
6839 }
6840
6841 if (dst == -1) {
6842 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6843 } else {
6844 alu.dst.sel = dst;
6845 }
6846 alu.dst.chan = i;
6847 alu.dst.write = 1;
6848 alu.is_op3 = 1;
6849 if (i == lasti) {
6850 alu.last = 1;
6851 }
6852 r = r600_bytecode_add_alu(ctx->bc, &alu);
6853 if (r)
6854 return r;
6855 }
6856 return 0;
6857 }
6858
6859 static int tgsi_op3(struct r600_shader_ctx *ctx)
6860 {
6861 return tgsi_op3_dst(ctx, -1);
6862 }
6863
6864 static int tgsi_dp(struct r600_shader_ctx *ctx)
6865 {
6866 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6867 struct r600_bytecode_alu alu;
6868 int i, j, r;
6869 unsigned op = ctx->inst_info->op;
6870 if (op == ALU_OP2_DOT4_IEEE &&
6871 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6872 op = ALU_OP2_DOT4;
6873
6874 for (i = 0; i < 4; i++) {
6875 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6876 alu.op = op;
6877 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6878 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6879 }
6880
6881 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6882 alu.dst.chan = i;
6883 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6884 /* handle some special cases */
6885 switch (inst->Instruction.Opcode) {
6886 case TGSI_OPCODE_DP2:
6887 if (i > 1) {
6888 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6889 alu.src[0].chan = alu.src[1].chan = 0;
6890 }
6891 break;
6892 case TGSI_OPCODE_DP3:
6893 if (i > 2) {
6894 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6895 alu.src[0].chan = alu.src[1].chan = 0;
6896 }
6897 break;
6898 default:
6899 break;
6900 }
6901 if (i == 3) {
6902 alu.last = 1;
6903 }
6904 r = r600_bytecode_add_alu(ctx->bc, &alu);
6905 if (r)
6906 return r;
6907 }
6908 return 0;
6909 }
6910
6911 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6912 unsigned index)
6913 {
6914 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6915 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6916 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6917 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6918 ctx->src[index].neg || ctx->src[index].abs ||
6919 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6920 }
6921
6922 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6923 unsigned index)
6924 {
6925 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6926 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6927 }
6928
6929 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6930 {
6931 struct r600_bytecode_vtx vtx;
6932 struct r600_bytecode_alu alu;
6933 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6934 int src_gpr, r, i;
6935 int id = tgsi_tex_get_src_gpr(ctx, 1);
6936 int sampler_index_mode = inst->Src[1].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6937
6938 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6939 if (src_requires_loading) {
6940 for (i = 0; i < 4; i++) {
6941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6942 alu.op = ALU_OP1_MOV;
6943 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6944 alu.dst.sel = ctx->temp_reg;
6945 alu.dst.chan = i;
6946 if (i == 3)
6947 alu.last = 1;
6948 alu.dst.write = 1;
6949 r = r600_bytecode_add_alu(ctx->bc, &alu);
6950 if (r)
6951 return r;
6952 }
6953 src_gpr = ctx->temp_reg;
6954 }
6955
6956 memset(&vtx, 0, sizeof(vtx));
6957 vtx.op = FETCH_OP_VFETCH;
6958 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6959 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6960 vtx.src_gpr = src_gpr;
6961 vtx.mega_fetch_count = 16;
6962 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6963 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6964 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6965 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6966 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6967 vtx.use_const_fields = 1;
6968 vtx.buffer_index_mode = sampler_index_mode;
6969
6970 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6971 return r;
6972
6973 if (ctx->bc->chip_class >= EVERGREEN)
6974 return 0;
6975
6976 for (i = 0; i < 4; i++) {
6977 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6978 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6979 continue;
6980
6981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6982 alu.op = ALU_OP2_AND_INT;
6983
6984 alu.dst.chan = i;
6985 alu.dst.sel = vtx.dst_gpr;
6986 alu.dst.write = 1;
6987
6988 alu.src[0].sel = vtx.dst_gpr;
6989 alu.src[0].chan = i;
6990
6991 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6992 alu.src[1].sel += (id * 2);
6993 alu.src[1].chan = i % 4;
6994 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6995
6996 if (i == lasti)
6997 alu.last = 1;
6998 r = r600_bytecode_add_alu(ctx->bc, &alu);
6999 if (r)
7000 return r;
7001 }
7002
7003 if (inst->Dst[0].Register.WriteMask & 3) {
7004 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7005 alu.op = ALU_OP2_OR_INT;
7006
7007 alu.dst.chan = 3;
7008 alu.dst.sel = vtx.dst_gpr;
7009 alu.dst.write = 1;
7010
7011 alu.src[0].sel = vtx.dst_gpr;
7012 alu.src[0].chan = 3;
7013
7014 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
7015 alu.src[1].chan = 0;
7016 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7017
7018 alu.last = 1;
7019 r = r600_bytecode_add_alu(ctx->bc, &alu);
7020 if (r)
7021 return r;
7022 }
7023 return 0;
7024 }
7025
7026 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset, int eg_buffer_base)
7027 {
7028 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7029 int r;
7030 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
7031 int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7032
7033 if (ctx->bc->chip_class < EVERGREEN) {
7034 struct r600_bytecode_alu alu;
7035 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7036 alu.op = ALU_OP1_MOV;
7037 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7038 /* r600 we have them at channel 2 of the second dword */
7039 alu.src[0].sel += (id * 2) + 1;
7040 alu.src[0].chan = 1;
7041 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7042 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
7043 alu.last = 1;
7044 r = r600_bytecode_add_alu(ctx->bc, &alu);
7045 if (r)
7046 return r;
7047 return 0;
7048 } else {
7049 struct r600_bytecode_vtx vtx;
7050 memset(&vtx, 0, sizeof(vtx));
7051 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
7052 vtx.buffer_id = id + eg_buffer_base;
7053 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7054 vtx.src_gpr = 0;
7055 vtx.mega_fetch_count = 16; /* no idea here really... */
7056 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7057 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7058 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 4 : 7; /* SEL_Y */
7059 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 4 : 7; /* SEL_Z */
7060 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 4 : 7; /* SEL_W */
7061 vtx.data_format = FMT_32_32_32_32;
7062 vtx.buffer_index_mode = sampler_index_mode;
7063
7064 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
7065 return r;
7066 return 0;
7067 }
7068 }
7069
7070
7071 static int tgsi_tex(struct r600_shader_ctx *ctx)
7072 {
7073 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7074 struct r600_bytecode_tex tex;
7075 struct r600_bytecode_alu alu;
7076 unsigned src_gpr;
7077 int r, i, j;
7078 int opcode;
7079 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
7080 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7081 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
7082 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
7083
7084 bool txf_add_offsets = inst->Texture.NumOffsets &&
7085 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7086 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
7087
7088 /* Texture fetch instructions can only use gprs as source.
7089 * Also they cannot negate the source or take the absolute value */
7090 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
7091 tgsi_tex_src_requires_loading(ctx, 0)) ||
7092 read_compressed_msaa || txf_add_offsets;
7093
7094 boolean src_loaded = FALSE;
7095 unsigned sampler_src_reg = 1;
7096 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
7097 boolean has_txq_cube_array_z = false;
7098 unsigned sampler_index_mode;
7099
7100 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
7101 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7102 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
7103 if (inst->Dst[0].Register.WriteMask & 4) {
7104 ctx->shader->has_txq_cube_array_z_comp = true;
7105 has_txq_cube_array_z = true;
7106 }
7107
7108 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
7109 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7110 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
7111 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
7112 sampler_src_reg = 2;
7113
7114 /* TGSI moves the sampler to src reg 3 for TXD */
7115 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
7116 sampler_src_reg = 3;
7117
7118 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7119
7120 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7121
7122 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
7123 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
7124 if (ctx->bc->chip_class < EVERGREEN)
7125 ctx->shader->uses_tex_buffers = true;
7126 return r600_do_buffer_txq(ctx, 1, 0, R600_MAX_CONST_BUFFERS);
7127 }
7128 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
7129 if (ctx->bc->chip_class < EVERGREEN)
7130 ctx->shader->uses_tex_buffers = true;
7131 return do_vtx_fetch_inst(ctx, src_requires_loading);
7132 }
7133 }
7134
7135 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
7136 int out_chan;
7137 /* Add perspective divide */
7138 if (ctx->bc->chip_class == CAYMAN) {
7139 out_chan = 2;
7140 for (i = 0; i < 3; i++) {
7141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7142 alu.op = ALU_OP1_RECIP_IEEE;
7143 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7144
7145 alu.dst.sel = ctx->temp_reg;
7146 alu.dst.chan = i;
7147 if (i == 2)
7148 alu.last = 1;
7149 if (out_chan == i)
7150 alu.dst.write = 1;
7151 r = r600_bytecode_add_alu(ctx->bc, &alu);
7152 if (r)
7153 return r;
7154 }
7155
7156 } else {
7157 out_chan = 3;
7158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7159 alu.op = ALU_OP1_RECIP_IEEE;
7160 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7161
7162 alu.dst.sel = ctx->temp_reg;
7163 alu.dst.chan = out_chan;
7164 alu.last = 1;
7165 alu.dst.write = 1;
7166 r = r600_bytecode_add_alu(ctx->bc, &alu);
7167 if (r)
7168 return r;
7169 }
7170
7171 for (i = 0; i < 3; i++) {
7172 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7173 alu.op = ALU_OP2_MUL;
7174 alu.src[0].sel = ctx->temp_reg;
7175 alu.src[0].chan = out_chan;
7176 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7177 alu.dst.sel = ctx->temp_reg;
7178 alu.dst.chan = i;
7179 alu.dst.write = 1;
7180 r = r600_bytecode_add_alu(ctx->bc, &alu);
7181 if (r)
7182 return r;
7183 }
7184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7185 alu.op = ALU_OP1_MOV;
7186 alu.src[0].sel = V_SQ_ALU_SRC_1;
7187 alu.src[0].chan = 0;
7188 alu.dst.sel = ctx->temp_reg;
7189 alu.dst.chan = 3;
7190 alu.last = 1;
7191 alu.dst.write = 1;
7192 r = r600_bytecode_add_alu(ctx->bc, &alu);
7193 if (r)
7194 return r;
7195 src_loaded = TRUE;
7196 src_gpr = ctx->temp_reg;
7197 }
7198
7199
7200 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7201 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7202 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7203 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7204 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
7205
7206 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
7207 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
7208
7209 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7210 for (i = 0; i < 4; i++) {
7211 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7212 alu.op = ALU_OP2_CUBE;
7213 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7214 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
7215 alu.dst.sel = ctx->temp_reg;
7216 alu.dst.chan = i;
7217 if (i == 3)
7218 alu.last = 1;
7219 alu.dst.write = 1;
7220 r = r600_bytecode_add_alu(ctx->bc, &alu);
7221 if (r)
7222 return r;
7223 }
7224
7225 /* tmp1.z = RCP_e(|tmp1.z|) */
7226 if (ctx->bc->chip_class == CAYMAN) {
7227 for (i = 0; i < 3; i++) {
7228 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7229 alu.op = ALU_OP1_RECIP_IEEE;
7230 alu.src[0].sel = ctx->temp_reg;
7231 alu.src[0].chan = 2;
7232 alu.src[0].abs = 1;
7233 alu.dst.sel = ctx->temp_reg;
7234 alu.dst.chan = i;
7235 if (i == 2)
7236 alu.dst.write = 1;
7237 if (i == 2)
7238 alu.last = 1;
7239 r = r600_bytecode_add_alu(ctx->bc, &alu);
7240 if (r)
7241 return r;
7242 }
7243 } else {
7244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7245 alu.op = ALU_OP1_RECIP_IEEE;
7246 alu.src[0].sel = ctx->temp_reg;
7247 alu.src[0].chan = 2;
7248 alu.src[0].abs = 1;
7249 alu.dst.sel = ctx->temp_reg;
7250 alu.dst.chan = 2;
7251 alu.dst.write = 1;
7252 alu.last = 1;
7253 r = r600_bytecode_add_alu(ctx->bc, &alu);
7254 if (r)
7255 return r;
7256 }
7257
7258 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7259 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7260 * muladd has no writemask, have to use another temp
7261 */
7262 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7263 alu.op = ALU_OP3_MULADD;
7264 alu.is_op3 = 1;
7265
7266 alu.src[0].sel = ctx->temp_reg;
7267 alu.src[0].chan = 0;
7268 alu.src[1].sel = ctx->temp_reg;
7269 alu.src[1].chan = 2;
7270
7271 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7272 alu.src[2].chan = 0;
7273 alu.src[2].value = u_bitcast_f2u(1.5f);
7274
7275 alu.dst.sel = ctx->temp_reg;
7276 alu.dst.chan = 0;
7277 alu.dst.write = 1;
7278
7279 r = r600_bytecode_add_alu(ctx->bc, &alu);
7280 if (r)
7281 return r;
7282
7283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7284 alu.op = ALU_OP3_MULADD;
7285 alu.is_op3 = 1;
7286
7287 alu.src[0].sel = ctx->temp_reg;
7288 alu.src[0].chan = 1;
7289 alu.src[1].sel = ctx->temp_reg;
7290 alu.src[1].chan = 2;
7291
7292 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7293 alu.src[2].chan = 0;
7294 alu.src[2].value = u_bitcast_f2u(1.5f);
7295
7296 alu.dst.sel = ctx->temp_reg;
7297 alu.dst.chan = 1;
7298 alu.dst.write = 1;
7299
7300 alu.last = 1;
7301 r = r600_bytecode_add_alu(ctx->bc, &alu);
7302 if (r)
7303 return r;
7304 /* write initial compare value into Z component
7305 - W src 0 for shadow cube
7306 - X src 1 for shadow cube array */
7307 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7308 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7310 alu.op = ALU_OP1_MOV;
7311 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7312 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7313 else
7314 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7315 alu.dst.sel = ctx->temp_reg;
7316 alu.dst.chan = 2;
7317 alu.dst.write = 1;
7318 alu.last = 1;
7319 r = r600_bytecode_add_alu(ctx->bc, &alu);
7320 if (r)
7321 return r;
7322 }
7323
7324 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7325 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7326 if (ctx->bc->chip_class >= EVERGREEN) {
7327 int mytmp = r600_get_temp(ctx);
7328 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7329 alu.op = ALU_OP1_MOV;
7330 alu.src[0].sel = ctx->temp_reg;
7331 alu.src[0].chan = 3;
7332 alu.dst.sel = mytmp;
7333 alu.dst.chan = 0;
7334 alu.dst.write = 1;
7335 alu.last = 1;
7336 r = r600_bytecode_add_alu(ctx->bc, &alu);
7337 if (r)
7338 return r;
7339
7340 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7341 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7342 alu.op = ALU_OP3_MULADD;
7343 alu.is_op3 = 1;
7344 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7345 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7346 alu.src[1].chan = 0;
7347 alu.src[1].value = u_bitcast_f2u(8.0f);
7348 alu.src[2].sel = mytmp;
7349 alu.src[2].chan = 0;
7350 alu.dst.sel = ctx->temp_reg;
7351 alu.dst.chan = 3;
7352 alu.dst.write = 1;
7353 alu.last = 1;
7354 r = r600_bytecode_add_alu(ctx->bc, &alu);
7355 if (r)
7356 return r;
7357 } else if (ctx->bc->chip_class < EVERGREEN) {
7358 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7359 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7360 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7361 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7362 tex.src_gpr = r600_get_temp(ctx);
7363 tex.src_sel_x = 0;
7364 tex.src_sel_y = 0;
7365 tex.src_sel_z = 0;
7366 tex.src_sel_w = 0;
7367 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7368 tex.coord_type_x = 1;
7369 tex.coord_type_y = 1;
7370 tex.coord_type_z = 1;
7371 tex.coord_type_w = 1;
7372 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7373 alu.op = ALU_OP1_MOV;
7374 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7375 alu.dst.sel = tex.src_gpr;
7376 alu.dst.chan = 0;
7377 alu.last = 1;
7378 alu.dst.write = 1;
7379 r = r600_bytecode_add_alu(ctx->bc, &alu);
7380 if (r)
7381 return r;
7382
7383 r = r600_bytecode_add_tex(ctx->bc, &tex);
7384 if (r)
7385 return r;
7386 }
7387
7388 }
7389
7390 /* for cube forms of lod and bias we need to route things */
7391 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7392 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7393 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7394 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7396 alu.op = ALU_OP1_MOV;
7397 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7398 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7399 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7400 else
7401 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7402 alu.dst.sel = ctx->temp_reg;
7403 alu.dst.chan = 2;
7404 alu.last = 1;
7405 alu.dst.write = 1;
7406 r = r600_bytecode_add_alu(ctx->bc, &alu);
7407 if (r)
7408 return r;
7409 }
7410
7411 src_loaded = TRUE;
7412 src_gpr = ctx->temp_reg;
7413 }
7414
7415 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7416 int temp_h = 0, temp_v = 0;
7417 int start_val = 0;
7418
7419 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7420 if (src_loaded == TRUE)
7421 start_val = 1;
7422 else
7423 src_loaded = TRUE;
7424 for (i = start_val; i < 3; i++) {
7425 int treg = r600_get_temp(ctx);
7426
7427 if (i == 0)
7428 src_gpr = treg;
7429 else if (i == 1)
7430 temp_h = treg;
7431 else
7432 temp_v = treg;
7433
7434 for (j = 0; j < 4; j++) {
7435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7436 alu.op = ALU_OP1_MOV;
7437 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7438 alu.dst.sel = treg;
7439 alu.dst.chan = j;
7440 if (j == 3)
7441 alu.last = 1;
7442 alu.dst.write = 1;
7443 r = r600_bytecode_add_alu(ctx->bc, &alu);
7444 if (r)
7445 return r;
7446 }
7447 }
7448 for (i = 1; i < 3; i++) {
7449 /* set gradients h/v */
7450 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7451 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7452 FETCH_OP_SET_GRADIENTS_V;
7453 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7454 tex.sampler_index_mode = sampler_index_mode;
7455 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7456 tex.resource_index_mode = sampler_index_mode;
7457
7458 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7459 tex.src_sel_x = 0;
7460 tex.src_sel_y = 1;
7461 tex.src_sel_z = 2;
7462 tex.src_sel_w = 3;
7463
7464 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7465 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7466 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7467 tex.coord_type_x = 1;
7468 tex.coord_type_y = 1;
7469 tex.coord_type_z = 1;
7470 tex.coord_type_w = 1;
7471 }
7472 r = r600_bytecode_add_tex(ctx->bc, &tex);
7473 if (r)
7474 return r;
7475 }
7476 }
7477
7478 if (src_requires_loading && !src_loaded) {
7479 for (i = 0; i < 4; i++) {
7480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7481 alu.op = ALU_OP1_MOV;
7482 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7483 alu.dst.sel = ctx->temp_reg;
7484 alu.dst.chan = i;
7485 if (i == 3)
7486 alu.last = 1;
7487 alu.dst.write = 1;
7488 r = r600_bytecode_add_alu(ctx->bc, &alu);
7489 if (r)
7490 return r;
7491 }
7492 src_loaded = TRUE;
7493 src_gpr = ctx->temp_reg;
7494 }
7495
7496 /* get offset values */
7497 if (inst->Texture.NumOffsets) {
7498 assert(inst->Texture.NumOffsets == 1);
7499
7500 /* The texture offset feature doesn't work with the TXF instruction
7501 * and must be emulated by adding the offset to the texture coordinates. */
7502 if (txf_add_offsets) {
7503 const struct tgsi_texture_offset *off = inst->TexOffsets;
7504
7505 switch (inst->Texture.Texture) {
7506 case TGSI_TEXTURE_3D:
7507 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7508 alu.op = ALU_OP2_ADD_INT;
7509 alu.src[0].sel = src_gpr;
7510 alu.src[0].chan = 2;
7511 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7512 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7513 alu.dst.sel = src_gpr;
7514 alu.dst.chan = 2;
7515 alu.dst.write = 1;
7516 alu.last = 1;
7517 r = r600_bytecode_add_alu(ctx->bc, &alu);
7518 if (r)
7519 return r;
7520 /* fall through */
7521
7522 case TGSI_TEXTURE_2D:
7523 case TGSI_TEXTURE_SHADOW2D:
7524 case TGSI_TEXTURE_RECT:
7525 case TGSI_TEXTURE_SHADOWRECT:
7526 case TGSI_TEXTURE_2D_ARRAY:
7527 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7529 alu.op = ALU_OP2_ADD_INT;
7530 alu.src[0].sel = src_gpr;
7531 alu.src[0].chan = 1;
7532 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7533 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7534 alu.dst.sel = src_gpr;
7535 alu.dst.chan = 1;
7536 alu.dst.write = 1;
7537 alu.last = 1;
7538 r = r600_bytecode_add_alu(ctx->bc, &alu);
7539 if (r)
7540 return r;
7541 /* fall through */
7542
7543 case TGSI_TEXTURE_1D:
7544 case TGSI_TEXTURE_SHADOW1D:
7545 case TGSI_TEXTURE_1D_ARRAY:
7546 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7548 alu.op = ALU_OP2_ADD_INT;
7549 alu.src[0].sel = src_gpr;
7550 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7551 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7552 alu.dst.sel = src_gpr;
7553 alu.dst.write = 1;
7554 alu.last = 1;
7555 r = r600_bytecode_add_alu(ctx->bc, &alu);
7556 if (r)
7557 return r;
7558 break;
7559 /* texture offsets do not apply to other texture targets */
7560 }
7561 } else {
7562 switch (inst->Texture.Texture) {
7563 case TGSI_TEXTURE_3D:
7564 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7565 /* fallthrough */
7566 case TGSI_TEXTURE_2D:
7567 case TGSI_TEXTURE_SHADOW2D:
7568 case TGSI_TEXTURE_RECT:
7569 case TGSI_TEXTURE_SHADOWRECT:
7570 case TGSI_TEXTURE_2D_ARRAY:
7571 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7572 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7573 /* fallthrough */
7574 case TGSI_TEXTURE_1D:
7575 case TGSI_TEXTURE_SHADOW1D:
7576 case TGSI_TEXTURE_1D_ARRAY:
7577 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7578 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7579 }
7580 }
7581 }
7582
7583 /* Obtain the sample index for reading a compressed MSAA color texture.
7584 * To read the FMASK, we use the ldfptr instruction, which tells us
7585 * where the samples are stored.
7586 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7587 * which is the identity mapping. Each nibble says which physical sample
7588 * should be fetched to get that sample.
7589 *
7590 * Assume src.z contains the sample index. It should be modified like this:
7591 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7592 * Then fetch the texel with src.
7593 */
7594 if (read_compressed_msaa) {
7595 unsigned sample_chan = 3;
7596 unsigned temp = r600_get_temp(ctx);
7597 assert(src_loaded);
7598
7599 /* temp.w = ldfptr() */
7600 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7601 tex.op = FETCH_OP_LD;
7602 tex.inst_mod = 1; /* to indicate this is ldfptr */
7603 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7604 tex.sampler_index_mode = sampler_index_mode;
7605 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7606 tex.resource_index_mode = sampler_index_mode;
7607 tex.src_gpr = src_gpr;
7608 tex.dst_gpr = temp;
7609 tex.dst_sel_x = 7; /* mask out these components */
7610 tex.dst_sel_y = 7;
7611 tex.dst_sel_z = 7;
7612 tex.dst_sel_w = 0; /* store X */
7613 tex.src_sel_x = 0;
7614 tex.src_sel_y = 1;
7615 tex.src_sel_z = 2;
7616 tex.src_sel_w = 3;
7617 tex.offset_x = offset_x;
7618 tex.offset_y = offset_y;
7619 tex.offset_z = offset_z;
7620 r = r600_bytecode_add_tex(ctx->bc, &tex);
7621 if (r)
7622 return r;
7623
7624 /* temp.x = sample_index*4 */
7625 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7626 alu.op = ALU_OP2_MULLO_INT;
7627 alu.src[0].sel = src_gpr;
7628 alu.src[0].chan = sample_chan;
7629 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7630 alu.src[1].value = 4;
7631 alu.dst.sel = temp;
7632 alu.dst.chan = 0;
7633 alu.dst.write = 1;
7634 r = emit_mul_int_op(ctx->bc, &alu);
7635 if (r)
7636 return r;
7637
7638 /* sample_index = temp.w >> temp.x */
7639 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7640 alu.op = ALU_OP2_LSHR_INT;
7641 alu.src[0].sel = temp;
7642 alu.src[0].chan = 3;
7643 alu.src[1].sel = temp;
7644 alu.src[1].chan = 0;
7645 alu.dst.sel = src_gpr;
7646 alu.dst.chan = sample_chan;
7647 alu.dst.write = 1;
7648 alu.last = 1;
7649 r = r600_bytecode_add_alu(ctx->bc, &alu);
7650 if (r)
7651 return r;
7652
7653 /* sample_index & 0xF */
7654 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7655 alu.op = ALU_OP2_AND_INT;
7656 alu.src[0].sel = src_gpr;
7657 alu.src[0].chan = sample_chan;
7658 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7659 alu.src[1].value = 0xF;
7660 alu.dst.sel = src_gpr;
7661 alu.dst.chan = sample_chan;
7662 alu.dst.write = 1;
7663 alu.last = 1;
7664 r = r600_bytecode_add_alu(ctx->bc, &alu);
7665 if (r)
7666 return r;
7667 #if 0
7668 /* visualize the FMASK */
7669 for (i = 0; i < 4; i++) {
7670 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7671 alu.op = ALU_OP1_INT_TO_FLT;
7672 alu.src[0].sel = src_gpr;
7673 alu.src[0].chan = sample_chan;
7674 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7675 alu.dst.chan = i;
7676 alu.dst.write = 1;
7677 alu.last = 1;
7678 r = r600_bytecode_add_alu(ctx->bc, &alu);
7679 if (r)
7680 return r;
7681 }
7682 return 0;
7683 #endif
7684 }
7685
7686 /* does this shader want a num layers from TXQ for a cube array? */
7687 if (has_txq_cube_array_z) {
7688 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7689
7690 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7691 alu.op = ALU_OP1_MOV;
7692
7693 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7694 if (ctx->bc->chip_class >= EVERGREEN) {
7695 /* with eg each dword is number of cubes */
7696 alu.src[0].sel += id / 4;
7697 alu.src[0].chan = id % 4;
7698 } else {
7699 /* r600 we have them at channel 2 of the second dword */
7700 alu.src[0].sel += (id * 2) + 1;
7701 alu.src[0].chan = 2;
7702 }
7703 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7704 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7705 alu.last = 1;
7706 r = r600_bytecode_add_alu(ctx->bc, &alu);
7707 if (r)
7708 return r;
7709 /* disable writemask from texture instruction */
7710 inst->Dst[0].Register.WriteMask &= ~4;
7711 }
7712
7713 opcode = ctx->inst_info->op;
7714 if (opcode == FETCH_OP_GATHER4 &&
7715 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7716 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7717 opcode = FETCH_OP_GATHER4_O;
7718
7719 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7720 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7721 encoded in the instruction are ignored. */
7722 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7723 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7724 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7725 tex.sampler_index_mode = sampler_index_mode;
7726 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7727 tex.resource_index_mode = sampler_index_mode;
7728
7729 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7730 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7731 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7732 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7733 tex.src_sel_w = 4;
7734
7735 tex.dst_sel_x = 7;
7736 tex.dst_sel_y = 7;
7737 tex.dst_sel_z = 7;
7738 tex.dst_sel_w = 7;
7739
7740 r = r600_bytecode_add_tex(ctx->bc, &tex);
7741 if (r)
7742 return r;
7743 }
7744
7745 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7746 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7747 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7748 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7749 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7750 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7751 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7752 switch (opcode) {
7753 case FETCH_OP_SAMPLE:
7754 opcode = FETCH_OP_SAMPLE_C;
7755 break;
7756 case FETCH_OP_SAMPLE_L:
7757 opcode = FETCH_OP_SAMPLE_C_L;
7758 break;
7759 case FETCH_OP_SAMPLE_LB:
7760 opcode = FETCH_OP_SAMPLE_C_LB;
7761 break;
7762 case FETCH_OP_SAMPLE_G:
7763 opcode = FETCH_OP_SAMPLE_C_G;
7764 break;
7765 /* Texture gather variants */
7766 case FETCH_OP_GATHER4:
7767 opcode = FETCH_OP_GATHER4_C;
7768 break;
7769 case FETCH_OP_GATHER4_O:
7770 opcode = FETCH_OP_GATHER4_C_O;
7771 break;
7772 }
7773 }
7774
7775 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7776 tex.op = opcode;
7777
7778 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7779 tex.sampler_index_mode = sampler_index_mode;
7780 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7781 tex.resource_index_mode = sampler_index_mode;
7782 tex.src_gpr = src_gpr;
7783 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7784
7785 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7786 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7787 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7788 }
7789
7790 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7791 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7792 tex.inst_mod = texture_component_select;
7793
7794 if (ctx->bc->chip_class == CAYMAN) {
7795 /* GATHER4 result order is different from TGSI TG4 */
7796 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7797 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7798 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7799 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7800 } else {
7801 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7802 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7803 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7804 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7805 }
7806 }
7807 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7808 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7809 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7810 tex.dst_sel_z = 7;
7811 tex.dst_sel_w = 7;
7812 }
7813 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7814 tex.dst_sel_x = 3;
7815 tex.dst_sel_y = 7;
7816 tex.dst_sel_z = 7;
7817 tex.dst_sel_w = 7;
7818 }
7819 else {
7820 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7821 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7822 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7823 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7824 }
7825
7826
7827 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7828 tex.src_sel_x = 4;
7829 tex.src_sel_y = 4;
7830 tex.src_sel_z = 4;
7831 tex.src_sel_w = 4;
7832 } else if (src_loaded) {
7833 tex.src_sel_x = 0;
7834 tex.src_sel_y = 1;
7835 tex.src_sel_z = 2;
7836 tex.src_sel_w = 3;
7837 } else {
7838 tex.src_sel_x = ctx->src[0].swizzle[0];
7839 tex.src_sel_y = ctx->src[0].swizzle[1];
7840 tex.src_sel_z = ctx->src[0].swizzle[2];
7841 tex.src_sel_w = ctx->src[0].swizzle[3];
7842 tex.src_rel = ctx->src[0].rel;
7843 }
7844
7845 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7846 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7847 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7848 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7849 tex.src_sel_x = 1;
7850 tex.src_sel_y = 0;
7851 tex.src_sel_z = 3;
7852 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7853 }
7854
7855 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7856 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7857 tex.coord_type_x = 1;
7858 tex.coord_type_y = 1;
7859 }
7860 tex.coord_type_z = 1;
7861 tex.coord_type_w = 1;
7862
7863 tex.offset_x = offset_x;
7864 tex.offset_y = offset_y;
7865 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7866 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7867 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7868 tex.offset_z = 0;
7869 }
7870 else {
7871 tex.offset_z = offset_z;
7872 }
7873
7874 /* Put the depth for comparison in W.
7875 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7876 * Some instructions expect the depth in Z. */
7877 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7878 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7879 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7880 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7881 opcode != FETCH_OP_SAMPLE_C_L &&
7882 opcode != FETCH_OP_SAMPLE_C_LB) {
7883 tex.src_sel_w = tex.src_sel_z;
7884 }
7885
7886 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7887 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7888 if (opcode == FETCH_OP_SAMPLE_C_L ||
7889 opcode == FETCH_OP_SAMPLE_C_LB) {
7890 /* the array index is read from Y */
7891 tex.coord_type_y = 0;
7892 } else {
7893 /* the array index is read from Z */
7894 tex.coord_type_z = 0;
7895 tex.src_sel_z = tex.src_sel_y;
7896 }
7897 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7898 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7899 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7900 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7901 (ctx->bc->chip_class >= EVERGREEN)))
7902 /* the array index is read from Z */
7903 tex.coord_type_z = 0;
7904
7905 /* mask unused source components */
7906 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7907 switch (inst->Texture.Texture) {
7908 case TGSI_TEXTURE_2D:
7909 case TGSI_TEXTURE_RECT:
7910 tex.src_sel_z = 7;
7911 tex.src_sel_w = 7;
7912 break;
7913 case TGSI_TEXTURE_1D_ARRAY:
7914 tex.src_sel_y = 7;
7915 tex.src_sel_w = 7;
7916 break;
7917 case TGSI_TEXTURE_1D:
7918 tex.src_sel_y = 7;
7919 tex.src_sel_z = 7;
7920 tex.src_sel_w = 7;
7921 break;
7922 }
7923 }
7924
7925 r = r600_bytecode_add_tex(ctx->bc, &tex);
7926 if (r)
7927 return r;
7928
7929 /* add shadow ambient support - gallium doesn't do it yet */
7930 return 0;
7931 }
7932
7933 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7934 struct tgsi_full_src_register *src)
7935 {
7936 unsigned i;
7937
7938 if (src->Register.Indirect) {
7939 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7940 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7941 return ctx->shader->atomics[i].hw_idx;
7942 }
7943 } else {
7944 uint32_t index = src->Register.Index;
7945 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7946 if (ctx->shader->atomics[i].buffer_id != (unsigned)src->Dimension.Index)
7947 continue;
7948 if (index > ctx->shader->atomics[i].end)
7949 continue;
7950 if (index < ctx->shader->atomics[i].start)
7951 continue;
7952 uint32_t offset = (index - ctx->shader->atomics[i].start);
7953 return ctx->shader->atomics[i].hw_idx + offset;
7954 }
7955 }
7956 assert(0);
7957 return -1;
7958 }
7959
7960 static int tgsi_set_gds_temp(struct r600_shader_ctx *ctx,
7961 int *uav_id_p, int *uav_index_mode_p)
7962 {
7963 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7964 int uav_id, uav_index_mode = 0;
7965 int r;
7966 bool is_cm = (ctx->bc->chip_class == CAYMAN);
7967
7968 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7969
7970 if (inst->Src[0].Register.Indirect) {
7971 if (is_cm) {
7972 struct r600_bytecode_alu alu;
7973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7974 alu.op = ALU_OP2_LSHL_INT;
7975 alu.src[0].sel = get_address_file_reg(ctx, inst->Src[0].Indirect.Index);
7976 alu.src[0].chan = 0;
7977 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7978 alu.src[1].value = 2;
7979 alu.dst.sel = ctx->temp_reg;
7980 alu.dst.chan = 0;
7981 alu.dst.write = 1;
7982 alu.last = 1;
7983 r = r600_bytecode_add_alu(ctx->bc, &alu);
7984 if (r)
7985 return r;
7986
7987 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
7988 ctx->temp_reg, 0,
7989 ctx->temp_reg, 0,
7990 V_SQ_ALU_SRC_LITERAL, uav_id * 4);
7991 if (r)
7992 return r;
7993 } else
7994 uav_index_mode = 2;
7995 } else if (is_cm) {
7996 r = single_alu_op2(ctx, ALU_OP1_MOV,
7997 ctx->temp_reg, 0,
7998 V_SQ_ALU_SRC_LITERAL, uav_id * 4,
7999 0, 0);
8000 if (r)
8001 return r;
8002 }
8003 *uav_id_p = uav_id;
8004 *uav_index_mode_p = uav_index_mode;
8005 return 0;
8006 }
8007
8008 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
8009 {
8010 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8011 int r;
8012 struct r600_bytecode_gds gds;
8013 int uav_id = 0;
8014 int uav_index_mode = 0;
8015 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8016
8017 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8018 if (r)
8019 return r;
8020
8021 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8022 gds.op = FETCH_OP_GDS_READ_RET;
8023 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8024 gds.uav_id = is_cm ? 0 : uav_id;
8025 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8026 gds.src_gpr = ctx->temp_reg;
8027 gds.src_sel_x = (is_cm) ? 0 : 4;
8028 gds.src_sel_y = 4;
8029 gds.src_sel_z = 4;
8030 gds.dst_sel_x = 0;
8031 gds.dst_sel_y = 7;
8032 gds.dst_sel_z = 7;
8033 gds.dst_sel_w = 7;
8034 gds.src_gpr2 = 0;
8035 gds.alloc_consume = !is_cm;
8036 r = r600_bytecode_add_gds(ctx->bc, &gds);
8037 if (r)
8038 return r;
8039
8040 ctx->bc->cf_last->vpm = 1;
8041 return 0;
8042 }
8043
8044 /* this fixes up 1D arrays properly */
8045 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
8046 {
8047 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8048 int r, i;
8049 struct r600_bytecode_alu alu;
8050 int temp_reg = r600_get_temp(ctx);
8051
8052 for (i = 0; i < 4; i++) {
8053 bool def_val = true, write_zero = false;
8054 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8055 alu.op = ALU_OP1_MOV;
8056 alu.dst.sel = temp_reg;
8057 alu.dst.chan = i;
8058
8059 switch (inst->Memory.Texture) {
8060 case TGSI_TEXTURE_BUFFER:
8061 case TGSI_TEXTURE_1D:
8062 if (i == 1 || i == 2 || i == 3) {
8063 write_zero = true;
8064 }
8065 break;
8066 case TGSI_TEXTURE_1D_ARRAY:
8067 if (i == 1 || i == 3)
8068 write_zero = true;
8069 else if (i == 2) {
8070 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
8071 def_val = false;
8072 }
8073 break;
8074 case TGSI_TEXTURE_2D:
8075 if (i == 2 || i == 3)
8076 write_zero = true;
8077 break;
8078 default:
8079 if (i == 3)
8080 write_zero = true;
8081 break;
8082 }
8083
8084 if (write_zero) {
8085 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8086 alu.src[0].value = 0;
8087 } else if (def_val) {
8088 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
8089 }
8090
8091 if (i == 3)
8092 alu.last = 1;
8093 alu.dst.write = 1;
8094 r = r600_bytecode_add_alu(ctx->bc, &alu);
8095 if (r)
8096 return r;
8097 }
8098 *idx_gpr = temp_reg;
8099 return 0;
8100 }
8101
8102 static int load_buffer_coord(struct r600_shader_ctx *ctx, int src_idx,
8103 int temp_reg)
8104 {
8105 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8106 int r;
8107 if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
8108 int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
8109 r = single_alu_op2(ctx, ALU_OP1_MOV,
8110 temp_reg, 0,
8111 V_SQ_ALU_SRC_LITERAL, value >> 2,
8112 0, 0);
8113 if (r)
8114 return r;
8115 } else {
8116 struct r600_bytecode_alu alu;
8117 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8118 alu.op = ALU_OP2_LSHR_INT;
8119 r600_bytecode_src(&alu.src[0], &ctx->src[src_idx], 0);
8120 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8121 alu.src[1].value = 2;
8122 alu.dst.sel = temp_reg;
8123 alu.dst.write = 1;
8124 alu.last = 1;
8125 r = r600_bytecode_add_alu(ctx->bc, &alu);
8126 if (r)
8127 return r;
8128 }
8129 return 0;
8130 }
8131
8132 static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
8133 {
8134 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8135 /* have to work out the offset into the RAT immediate return buffer */
8136 struct r600_bytecode_vtx vtx;
8137 struct r600_bytecode_cf *cf;
8138 int r;
8139 int temp_reg = r600_get_temp(ctx);
8140 unsigned rat_index_mode;
8141 unsigned base;
8142
8143 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8144 base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
8145
8146 r = load_buffer_coord(ctx, 1, temp_reg);
8147 if (r)
8148 return r;
8149 ctx->bc->cf_last->barrier = 1;
8150 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8151 vtx.op = FETCH_OP_VFETCH;
8152 vtx.buffer_id = inst->Src[0].Register.Index + base;
8153 vtx.buffer_index_mode = rat_index_mode;
8154 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8155 vtx.src_gpr = temp_reg;
8156 vtx.src_sel_x = 0;
8157 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8158 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
8159 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
8160 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
8161 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
8162 vtx.num_format_all = 1;
8163 vtx.format_comp_all = 1;
8164 vtx.srf_mode_all = 0;
8165
8166 if (inst->Dst[0].Register.WriteMask & 8) {
8167 vtx.data_format = FMT_32_32_32_32;
8168 vtx.use_const_fields = 0;
8169 } else if (inst->Dst[0].Register.WriteMask & 4) {
8170 vtx.data_format = FMT_32_32_32;
8171 vtx.use_const_fields = 0;
8172 } else if (inst->Dst[0].Register.WriteMask & 2) {
8173 vtx.data_format = FMT_32_32;
8174 vtx.use_const_fields = 0;
8175 } else {
8176 vtx.data_format = FMT_32;
8177 vtx.use_const_fields = 0;
8178 }
8179
8180 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8181 if (r)
8182 return r;
8183 cf = ctx->bc->cf_last;
8184 cf->barrier = 1;
8185 return 0;
8186 }
8187
8188 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
8189 {
8190 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8191 /* have to work out the offset into the RAT immediate return buffer */
8192 struct r600_bytecode_vtx vtx;
8193 struct r600_bytecode_cf *cf;
8194 int r;
8195 int idx_gpr;
8196 unsigned format, num_format, format_comp, endian;
8197 const struct util_format_description *desc;
8198 unsigned rat_index_mode;
8199 unsigned immed_base;
8200
8201 r = load_thread_id_gpr(ctx);
8202 if (r)
8203 return r;
8204
8205 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8206
8207 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8208 r = load_index_src(ctx, 1, &idx_gpr);
8209 if (r)
8210 return r;
8211
8212 if (rat_index_mode)
8213 egcm_load_index_reg(ctx->bc, 1, false);
8214
8215 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8216 cf = ctx->bc->cf_last;
8217
8218 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8219 cf->rat.inst = V_RAT_INST_NOP_RTN;
8220 cf->rat.index_mode = rat_index_mode;
8221 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8222 cf->output.gpr = ctx->thread_id_gpr;
8223 cf->output.index_gpr = idx_gpr;
8224 cf->output.comp_mask = 0xf;
8225 cf->output.burst_count = 1;
8226 cf->vpm = 1;
8227 cf->barrier = 1;
8228 cf->mark = 1;
8229 cf->output.elem_size = 0;
8230
8231 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8232 cf = ctx->bc->cf_last;
8233 cf->barrier = 1;
8234
8235 desc = util_format_description(inst->Memory.Format);
8236 r600_vertex_data_type(inst->Memory.Format,
8237 &format, &num_format, &format_comp, &endian);
8238 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8239 vtx.op = FETCH_OP_VFETCH;
8240 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8241 vtx.buffer_index_mode = rat_index_mode;
8242 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8243 vtx.src_gpr = ctx->thread_id_gpr;
8244 vtx.src_sel_x = 1;
8245 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8246 vtx.dst_sel_x = desc->swizzle[0];
8247 vtx.dst_sel_y = desc->swizzle[1];
8248 vtx.dst_sel_z = desc->swizzle[2];
8249 vtx.dst_sel_w = desc->swizzle[3];
8250 vtx.srf_mode_all = 1;
8251 vtx.data_format = format;
8252 vtx.num_format_all = num_format;
8253 vtx.format_comp_all = format_comp;
8254 vtx.endian = endian;
8255 vtx.offset = 0;
8256 vtx.mega_fetch_count = 3;
8257 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8258 if (r)
8259 return r;
8260 cf = ctx->bc->cf_last;
8261 cf->barrier = 1;
8262 return 0;
8263 }
8264
8265 static int tgsi_load_lds(struct r600_shader_ctx *ctx)
8266 {
8267 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8268 struct r600_bytecode_alu alu;
8269 int r;
8270 int temp_reg = r600_get_temp(ctx);
8271
8272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8273 alu.op = ALU_OP1_MOV;
8274 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8275 alu.dst.sel = temp_reg;
8276 alu.dst.write = 1;
8277 alu.last = 1;
8278 r = r600_bytecode_add_alu(ctx->bc, &alu);
8279 if (r)
8280 return r;
8281
8282 r = do_lds_fetch_values(ctx, temp_reg,
8283 ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
8284 if (r)
8285 return r;
8286 return 0;
8287 }
8288
8289 static int tgsi_load(struct r600_shader_ctx *ctx)
8290 {
8291 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8292 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8293 return tgsi_load_rat(ctx);
8294 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8295 return tgsi_load_gds(ctx);
8296 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8297 return tgsi_load_buffer(ctx);
8298 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8299 return tgsi_load_lds(ctx);
8300 return 0;
8301 }
8302
8303 static int tgsi_store_buffer_rat(struct r600_shader_ctx *ctx)
8304 {
8305 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8306 struct r600_bytecode_cf *cf;
8307 int r, i;
8308 unsigned rat_index_mode;
8309 int lasti;
8310 int temp_reg = r600_get_temp(ctx), treg2 = r600_get_temp(ctx);
8311
8312 r = load_buffer_coord(ctx, 0, treg2);
8313 if (r)
8314 return r;
8315
8316 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8317 if (rat_index_mode)
8318 egcm_load_index_reg(ctx->bc, 1, false);
8319
8320 for (i = 0; i <= 3; i++) {
8321 struct r600_bytecode_alu alu;
8322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8323 alu.op = ALU_OP1_MOV;
8324 alu.dst.sel = temp_reg;
8325 alu.dst.chan = i;
8326 alu.src[0].sel = V_SQ_ALU_SRC_0;
8327 alu.last = (i == 3);
8328 alu.dst.write = 1;
8329 r = r600_bytecode_add_alu(ctx->bc, &alu);
8330 if (r)
8331 return r;
8332 }
8333
8334 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8335 for (i = 0; i <= lasti; i++) {
8336 struct r600_bytecode_alu alu;
8337 if (!((1 << i) & inst->Dst[0].Register.WriteMask))
8338 continue;
8339
8340 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8341 temp_reg, 0,
8342 treg2, 0,
8343 V_SQ_ALU_SRC_LITERAL, i);
8344 if (r)
8345 return r;
8346
8347 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8348 alu.op = ALU_OP1_MOV;
8349 alu.dst.sel = ctx->temp_reg;
8350 alu.dst.chan = 0;
8351
8352 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8353 alu.last = 1;
8354 alu.dst.write = 1;
8355 r = r600_bytecode_add_alu(ctx->bc, &alu);
8356 if (r)
8357 return r;
8358
8359 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8360 cf = ctx->bc->cf_last;
8361
8362 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index + ctx->info.file_count[TGSI_FILE_IMAGE];
8363 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8364 cf->rat.index_mode = rat_index_mode;
8365 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8366 cf->output.gpr = ctx->temp_reg;
8367 cf->output.index_gpr = temp_reg;
8368 cf->output.comp_mask = 1;
8369 cf->output.burst_count = 1;
8370 cf->vpm = 1;
8371 cf->barrier = 1;
8372 cf->output.elem_size = 0;
8373 }
8374 return 0;
8375 }
8376
8377 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
8378 {
8379 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8380 struct r600_bytecode_cf *cf;
8381 bool src_requires_loading = false;
8382 int val_gpr, idx_gpr;
8383 int r, i;
8384 unsigned rat_index_mode;
8385
8386 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8387
8388 r = load_index_src(ctx, 0, &idx_gpr);
8389 if (r)
8390 return r;
8391
8392 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
8393 src_requires_loading = true;
8394
8395 if (src_requires_loading) {
8396 struct r600_bytecode_alu alu;
8397 for (i = 0; i < 4; i++) {
8398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8399 alu.op = ALU_OP1_MOV;
8400 alu.dst.sel = ctx->temp_reg;
8401 alu.dst.chan = i;
8402
8403 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8404 if (i == 3)
8405 alu.last = 1;
8406 alu.dst.write = 1;
8407 r = r600_bytecode_add_alu(ctx->bc, &alu);
8408 if (r)
8409 return r;
8410 }
8411 val_gpr = ctx->temp_reg;
8412 } else
8413 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
8414 if (rat_index_mode)
8415 egcm_load_index_reg(ctx->bc, 1, false);
8416
8417 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8418 cf = ctx->bc->cf_last;
8419
8420 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
8421 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8422 cf->rat.index_mode = rat_index_mode;
8423 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8424 cf->output.gpr = val_gpr;
8425 cf->output.index_gpr = idx_gpr;
8426 cf->output.comp_mask = 0xf;
8427 cf->output.burst_count = 1;
8428 cf->vpm = 1;
8429 cf->barrier = 1;
8430 cf->output.elem_size = 0;
8431 return 0;
8432 }
8433
8434 static int tgsi_store_lds(struct r600_shader_ctx *ctx)
8435 {
8436 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8437 struct r600_bytecode_alu alu;
8438 int r, i, lasti;
8439 int write_mask = inst->Dst[0].Register.WriteMask;
8440 int temp_reg = r600_get_temp(ctx);
8441
8442 /* LDS write */
8443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8444 alu.op = ALU_OP1_MOV;
8445 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8446 alu.dst.sel = temp_reg;
8447 alu.dst.write = 1;
8448 alu.last = 1;
8449 r = r600_bytecode_add_alu(ctx->bc, &alu);
8450 if (r)
8451 return r;
8452
8453 lasti = tgsi_last_instruction(write_mask);
8454 for (i = 1; i <= lasti; i++) {
8455 if (!(write_mask & (1 << i)))
8456 continue;
8457 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8458 temp_reg, i,
8459 temp_reg, 0,
8460 V_SQ_ALU_SRC_LITERAL, 4 * i);
8461 if (r)
8462 return r;
8463 }
8464 for (i = 0; i <= lasti; i++) {
8465 if (!(write_mask & (1 << i)))
8466 continue;
8467
8468 if ((i == 0 && ((write_mask & 3) == 3)) ||
8469 (i == 2 && ((write_mask & 0xc) == 0xc))) {
8470 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8471 alu.op = LDS_OP3_LDS_WRITE_REL;
8472
8473 alu.src[0].sel = temp_reg;
8474 alu.src[0].chan = i;
8475 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8476 r600_bytecode_src(&alu.src[2], &ctx->src[1], i + 1);
8477 alu.last = 1;
8478 alu.is_lds_idx_op = true;
8479 alu.lds_idx = 1;
8480 r = r600_bytecode_add_alu(ctx->bc, &alu);
8481 if (r)
8482 return r;
8483 i += 1;
8484 continue;
8485 }
8486 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8487 alu.op = LDS_OP2_LDS_WRITE;
8488
8489 alu.src[0].sel = temp_reg;
8490 alu.src[0].chan = i;
8491 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8492
8493 alu.last = 1;
8494 alu.is_lds_idx_op = true;
8495
8496 r = r600_bytecode_add_alu(ctx->bc, &alu);
8497 if (r)
8498 return r;
8499 }
8500 return 0;
8501 }
8502
8503 static int tgsi_store(struct r600_shader_ctx *ctx)
8504 {
8505 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8506 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
8507 return tgsi_store_buffer_rat(ctx);
8508 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
8509 return tgsi_store_lds(ctx);
8510 else
8511 return tgsi_store_rat(ctx);
8512 }
8513
8514 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
8515 {
8516 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8517 /* have to work out the offset into the RAT immediate return buffer */
8518 struct r600_bytecode_alu alu;
8519 struct r600_bytecode_vtx vtx;
8520 struct r600_bytecode_cf *cf;
8521 int r;
8522 int idx_gpr;
8523 unsigned format, num_format, format_comp, endian;
8524 const struct util_format_description *desc;
8525 unsigned rat_index_mode;
8526 unsigned immed_base;
8527 unsigned rat_base;
8528
8529 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8530 rat_base = ctx->shader->rat_base;
8531
8532 r = load_thread_id_gpr(ctx);
8533 if (r)
8534 return r;
8535
8536 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
8537 immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8538 rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8539
8540 r = load_buffer_coord(ctx, 1, ctx->temp_reg);
8541 if (r)
8542 return r;
8543 idx_gpr = ctx->temp_reg;
8544 } else {
8545 r = load_index_src(ctx, 1, &idx_gpr);
8546 if (r)
8547 return r;
8548 }
8549
8550 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8551
8552 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
8553 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8554 alu.op = ALU_OP1_MOV;
8555 alu.dst.sel = ctx->thread_id_gpr;
8556 alu.dst.chan = 0;
8557 alu.dst.write = 1;
8558 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8559 alu.last = 1;
8560 r = r600_bytecode_add_alu(ctx->bc, &alu);
8561 if (r)
8562 return r;
8563
8564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8565 alu.op = ALU_OP1_MOV;
8566 alu.dst.sel = ctx->thread_id_gpr;
8567 if (ctx->bc->chip_class == CAYMAN)
8568 alu.dst.chan = 2;
8569 else
8570 alu.dst.chan = 3;
8571 alu.dst.write = 1;
8572 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8573 alu.last = 1;
8574 r = r600_bytecode_add_alu(ctx->bc, &alu);
8575 if (r)
8576 return r;
8577 } else {
8578 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8579 alu.op = ALU_OP1_MOV;
8580 alu.dst.sel = ctx->thread_id_gpr;
8581 alu.dst.chan = 0;
8582 alu.dst.write = 1;
8583 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8584 alu.last = 1;
8585 r = r600_bytecode_add_alu(ctx->bc, &alu);
8586 if (r)
8587 return r;
8588 }
8589
8590 if (rat_index_mode)
8591 egcm_load_index_reg(ctx->bc, 1, false);
8592 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8593 cf = ctx->bc->cf_last;
8594
8595 cf->rat.id = rat_base + inst->Src[0].Register.Index;
8596 cf->rat.inst = ctx->inst_info->op;
8597 cf->rat.index_mode = rat_index_mode;
8598 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8599 cf->output.gpr = ctx->thread_id_gpr;
8600 cf->output.index_gpr = idx_gpr;
8601 cf->output.comp_mask = 0xf;
8602 cf->output.burst_count = 1;
8603 cf->vpm = 1;
8604 cf->barrier = 1;
8605 cf->mark = 1;
8606 cf->output.elem_size = 0;
8607 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8608 cf = ctx->bc->cf_last;
8609 cf->barrier = 1;
8610 cf->cf_addr = 1;
8611
8612 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8613 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
8614 desc = util_format_description(inst->Memory.Format);
8615 r600_vertex_data_type(inst->Memory.Format,
8616 &format, &num_format, &format_comp, &endian);
8617 vtx.dst_sel_x = desc->swizzle[0];
8618 } else {
8619 format = FMT_32;
8620 num_format = 1;
8621 format_comp = 0;
8622 endian = 0;
8623 vtx.dst_sel_x = 0;
8624 }
8625 vtx.op = FETCH_OP_VFETCH;
8626 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8627 vtx.buffer_index_mode = rat_index_mode;
8628 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8629 vtx.src_gpr = ctx->thread_id_gpr;
8630 vtx.src_sel_x = 1;
8631 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8632 vtx.dst_sel_y = 7;
8633 vtx.dst_sel_z = 7;
8634 vtx.dst_sel_w = 7;
8635 vtx.use_const_fields = 0;
8636 vtx.srf_mode_all = 1;
8637 vtx.data_format = format;
8638 vtx.num_format_all = num_format;
8639 vtx.format_comp_all = format_comp;
8640 vtx.endian = endian;
8641 vtx.offset = 0;
8642 vtx.mega_fetch_count = 0xf;
8643 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8644 if (r)
8645 return r;
8646 cf = ctx->bc->cf_last;
8647 cf->vpm = 1;
8648 cf->barrier = 1;
8649 return 0;
8650 }
8651
8652 static int get_gds_op(int opcode)
8653 {
8654 switch (opcode) {
8655 case TGSI_OPCODE_ATOMUADD:
8656 return FETCH_OP_GDS_ADD_RET;
8657 case TGSI_OPCODE_ATOMAND:
8658 return FETCH_OP_GDS_AND_RET;
8659 case TGSI_OPCODE_ATOMOR:
8660 return FETCH_OP_GDS_OR_RET;
8661 case TGSI_OPCODE_ATOMXOR:
8662 return FETCH_OP_GDS_XOR_RET;
8663 case TGSI_OPCODE_ATOMUMIN:
8664 return FETCH_OP_GDS_MIN_UINT_RET;
8665 case TGSI_OPCODE_ATOMUMAX:
8666 return FETCH_OP_GDS_MAX_UINT_RET;
8667 case TGSI_OPCODE_ATOMXCHG:
8668 return FETCH_OP_GDS_XCHG_RET;
8669 case TGSI_OPCODE_ATOMCAS:
8670 return FETCH_OP_GDS_CMP_XCHG_RET;
8671 default:
8672 return -1;
8673 }
8674 }
8675
8676 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
8677 {
8678 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8679 struct r600_bytecode_gds gds;
8680 struct r600_bytecode_alu alu;
8681 int gds_op = get_gds_op(inst->Instruction.Opcode);
8682 int r;
8683 int uav_id = 0;
8684 int uav_index_mode = 0;
8685 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8686
8687 if (gds_op == -1) {
8688 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
8689 return -1;
8690 }
8691
8692 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8693 if (r)
8694 return r;
8695
8696 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET) {
8697 if (inst->Src[3].Register.File == TGSI_FILE_IMMEDIATE) {
8698 int value = (ctx->literals[4 * inst->Src[3].Register.Index + inst->Src[3].Register.SwizzleX]);
8699 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8700 alu.op = ALU_OP1_MOV;
8701 alu.dst.sel = ctx->temp_reg;
8702 alu.dst.chan = is_cm ? 2 : 1;
8703 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8704 alu.src[0].value = value;
8705 alu.last = 1;
8706 alu.dst.write = 1;
8707 r = r600_bytecode_add_alu(ctx->bc, &alu);
8708 if (r)
8709 return r;
8710 } else {
8711 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8712 alu.op = ALU_OP1_MOV;
8713 alu.dst.sel = ctx->temp_reg;
8714 alu.dst.chan = is_cm ? 2 : 1;
8715 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8716 alu.last = 1;
8717 alu.dst.write = 1;
8718 r = r600_bytecode_add_alu(ctx->bc, &alu);
8719 if (r)
8720 return r;
8721 }
8722 }
8723 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
8724 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
8725 int abs_value = abs(value);
8726 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
8727 gds_op = FETCH_OP_GDS_SUB_RET;
8728 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8729 alu.op = ALU_OP1_MOV;
8730 alu.dst.sel = ctx->temp_reg;
8731 alu.dst.chan = is_cm ? 1 : 0;
8732 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8733 alu.src[0].value = abs_value;
8734 alu.last = 1;
8735 alu.dst.write = 1;
8736 r = r600_bytecode_add_alu(ctx->bc, &alu);
8737 if (r)
8738 return r;
8739 } else {
8740 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8741 alu.op = ALU_OP1_MOV;
8742 alu.dst.sel = ctx->temp_reg;
8743 alu.dst.chan = is_cm ? 1 : 0;
8744 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8745 alu.last = 1;
8746 alu.dst.write = 1;
8747 r = r600_bytecode_add_alu(ctx->bc, &alu);
8748 if (r)
8749 return r;
8750 }
8751
8752
8753 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8754 gds.op = gds_op;
8755 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8756 gds.uav_id = is_cm ? 0 : uav_id;
8757 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8758 gds.src_gpr = ctx->temp_reg;
8759 gds.src_gpr2 = 0;
8760 gds.src_sel_x = is_cm ? 0 : 4;
8761 gds.src_sel_y = is_cm ? 1 : 0;
8762 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET)
8763 gds.src_sel_z = is_cm ? 2 : 1;
8764 else
8765 gds.src_sel_z = 7;
8766 gds.dst_sel_x = 0;
8767 gds.dst_sel_y = 7;
8768 gds.dst_sel_z = 7;
8769 gds.dst_sel_w = 7;
8770 gds.alloc_consume = !is_cm;
8771
8772 r = r600_bytecode_add_gds(ctx->bc, &gds);
8773 if (r)
8774 return r;
8775 ctx->bc->cf_last->vpm = 1;
8776 return 0;
8777 }
8778
8779 static int get_lds_op(int opcode)
8780 {
8781 switch (opcode) {
8782 case TGSI_OPCODE_ATOMUADD:
8783 return LDS_OP2_LDS_ADD_RET;
8784 case TGSI_OPCODE_ATOMAND:
8785 return LDS_OP2_LDS_AND_RET;
8786 case TGSI_OPCODE_ATOMOR:
8787 return LDS_OP2_LDS_OR_RET;
8788 case TGSI_OPCODE_ATOMXOR:
8789 return LDS_OP2_LDS_XOR_RET;
8790 case TGSI_OPCODE_ATOMUMIN:
8791 return LDS_OP2_LDS_MIN_UINT_RET;
8792 case TGSI_OPCODE_ATOMUMAX:
8793 return LDS_OP2_LDS_MAX_UINT_RET;
8794 case TGSI_OPCODE_ATOMIMIN:
8795 return LDS_OP2_LDS_MIN_INT_RET;
8796 case TGSI_OPCODE_ATOMIMAX:
8797 return LDS_OP2_LDS_MAX_INT_RET;
8798 case TGSI_OPCODE_ATOMXCHG:
8799 return LDS_OP2_LDS_XCHG_RET;
8800 case TGSI_OPCODE_ATOMCAS:
8801 return LDS_OP3_LDS_CMP_XCHG_RET;
8802 default:
8803 return -1;
8804 }
8805 }
8806
8807 static int tgsi_atomic_op_lds(struct r600_shader_ctx *ctx)
8808 {
8809 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8810 int lds_op = get_lds_op(inst->Instruction.Opcode);
8811 int r;
8812
8813 struct r600_bytecode_alu alu;
8814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8815 alu.op = lds_op;
8816 alu.is_lds_idx_op = true;
8817 alu.last = 1;
8818 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8819 r600_bytecode_src(&alu.src[1], &ctx->src[2], 0);
8820 if (lds_op == LDS_OP3_LDS_CMP_XCHG_RET)
8821 r600_bytecode_src(&alu.src[2], &ctx->src[3], 0);
8822 else
8823 alu.src[2].sel = V_SQ_ALU_SRC_0;
8824 r = r600_bytecode_add_alu(ctx->bc, &alu);
8825 if (r)
8826 return r;
8827
8828 /* then read from LDS_OQ_A_POP */
8829 memset(&alu, 0, sizeof(alu));
8830
8831 alu.op = ALU_OP1_MOV;
8832 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
8833 alu.src[0].chan = 0;
8834 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
8835 alu.dst.write = 1;
8836 alu.last = 1;
8837 r = r600_bytecode_add_alu(ctx->bc, &alu);
8838 if (r)
8839 return r;
8840
8841 return 0;
8842 }
8843
8844 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
8845 {
8846 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8847 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8848 return tgsi_atomic_op_rat(ctx);
8849 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8850 return tgsi_atomic_op_gds(ctx);
8851 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8852 return tgsi_atomic_op_rat(ctx);
8853 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8854 return tgsi_atomic_op_lds(ctx);
8855 return 0;
8856 }
8857
8858 static int tgsi_resq(struct r600_shader_ctx *ctx)
8859 {
8860 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8861 unsigned sampler_index_mode;
8862 struct r600_bytecode_tex tex;
8863 int r;
8864 boolean has_txq_cube_array_z = false;
8865
8866 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
8867 (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
8868 if (ctx->bc->chip_class < EVERGREEN)
8869 ctx->shader->uses_tex_buffers = true;
8870 unsigned eg_buffer_base = 0;
8871 eg_buffer_base = R600_IMAGE_REAL_RESOURCE_OFFSET;
8872 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8873 eg_buffer_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8874 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset, eg_buffer_base);
8875 }
8876
8877 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
8878 inst->Dst[0].Register.WriteMask & 4) {
8879 ctx->shader->has_txq_cube_array_z_comp = true;
8880 has_txq_cube_array_z = true;
8881 }
8882
8883 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8884 if (sampler_index_mode)
8885 egcm_load_index_reg(ctx->bc, 1, false);
8886
8887
8888 /* does this shader want a num layers from TXQ for a cube array? */
8889 if (has_txq_cube_array_z) {
8890 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
8891 struct r600_bytecode_alu alu;
8892
8893 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8894 alu.op = ALU_OP1_MOV;
8895
8896 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8897 /* with eg each dword is either number of cubes */
8898 alu.src[0].sel += id / 4;
8899 alu.src[0].chan = id % 4;
8900 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8901 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8902 alu.last = 1;
8903 r = r600_bytecode_add_alu(ctx->bc, &alu);
8904 if (r)
8905 return r;
8906 /* disable writemask from texture instruction */
8907 inst->Dst[0].Register.WriteMask &= ~4;
8908 }
8909 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8910 tex.op = ctx->inst_info->op;
8911 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
8912 tex.sampler_index_mode = sampler_index_mode;
8913 tex.resource_id = tex.sampler_id;
8914 tex.resource_index_mode = sampler_index_mode;
8915 tex.src_sel_x = 4;
8916 tex.src_sel_y = 4;
8917 tex.src_sel_z = 4;
8918 tex.src_sel_w = 4;
8919 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8920 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8921 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8922 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8923 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8924 r = r600_bytecode_add_tex(ctx->bc, &tex);
8925 if (r)
8926 return r;
8927
8928 return 0;
8929 }
8930
8931 static int tgsi_lrp(struct r600_shader_ctx *ctx)
8932 {
8933 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8934 struct r600_bytecode_alu alu;
8935 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8936 unsigned i, temp_regs[2];
8937 int r;
8938
8939 /* optimize if it's just an equal balance */
8940 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
8941 for (i = 0; i < lasti + 1; i++) {
8942 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8943 continue;
8944
8945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8946 alu.op = ALU_OP2_ADD;
8947 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8948 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8949 alu.omod = 3;
8950 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8951 alu.dst.chan = i;
8952 if (i == lasti) {
8953 alu.last = 1;
8954 }
8955 r = r600_bytecode_add_alu(ctx->bc, &alu);
8956 if (r)
8957 return r;
8958 }
8959 return 0;
8960 }
8961
8962 /* 1 - src0 */
8963 for (i = 0; i < lasti + 1; i++) {
8964 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8965 continue;
8966
8967 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8968 alu.op = ALU_OP2_ADD;
8969 alu.src[0].sel = V_SQ_ALU_SRC_1;
8970 alu.src[0].chan = 0;
8971 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
8972 r600_bytecode_src_toggle_neg(&alu.src[1]);
8973 alu.dst.sel = ctx->temp_reg;
8974 alu.dst.chan = i;
8975 if (i == lasti) {
8976 alu.last = 1;
8977 }
8978 alu.dst.write = 1;
8979 r = r600_bytecode_add_alu(ctx->bc, &alu);
8980 if (r)
8981 return r;
8982 }
8983
8984 /* (1 - src0) * src2 */
8985 for (i = 0; i < lasti + 1; i++) {
8986 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8987 continue;
8988
8989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8990 alu.op = ALU_OP2_MUL;
8991 alu.src[0].sel = ctx->temp_reg;
8992 alu.src[0].chan = i;
8993 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8994 alu.dst.sel = ctx->temp_reg;
8995 alu.dst.chan = i;
8996 if (i == lasti) {
8997 alu.last = 1;
8998 }
8999 alu.dst.write = 1;
9000 r = r600_bytecode_add_alu(ctx->bc, &alu);
9001 if (r)
9002 return r;
9003 }
9004
9005 /* src0 * src1 + (1 - src0) * src2 */
9006 if (ctx->src[0].abs)
9007 temp_regs[0] = r600_get_temp(ctx);
9008 else
9009 temp_regs[0] = 0;
9010 if (ctx->src[1].abs)
9011 temp_regs[1] = r600_get_temp(ctx);
9012 else
9013 temp_regs[1] = 0;
9014
9015 for (i = 0; i < lasti + 1; i++) {
9016 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9017 continue;
9018
9019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9020 alu.op = ALU_OP3_MULADD;
9021 alu.is_op3 = 1;
9022 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
9023 if (r)
9024 return r;
9025 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
9026 if (r)
9027 return r;
9028 alu.src[2].sel = ctx->temp_reg;
9029 alu.src[2].chan = i;
9030
9031 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9032 alu.dst.chan = i;
9033 if (i == lasti) {
9034 alu.last = 1;
9035 }
9036 r = r600_bytecode_add_alu(ctx->bc, &alu);
9037 if (r)
9038 return r;
9039 }
9040 return 0;
9041 }
9042
9043 static int tgsi_cmp(struct r600_shader_ctx *ctx)
9044 {
9045 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9046 struct r600_bytecode_alu alu;
9047 int i, r, j;
9048 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9049 int temp_regs[3];
9050 unsigned op;
9051
9052 if (ctx->src[0].abs && ctx->src[0].neg) {
9053 op = ALU_OP3_CNDE;
9054 ctx->src[0].abs = 0;
9055 ctx->src[0].neg = 0;
9056 } else {
9057 op = ALU_OP3_CNDGE;
9058 }
9059
9060 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
9061 temp_regs[j] = 0;
9062 if (ctx->src[j].abs)
9063 temp_regs[j] = r600_get_temp(ctx);
9064 }
9065
9066 for (i = 0; i < lasti + 1; i++) {
9067 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9068 continue;
9069
9070 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9071 alu.op = op;
9072 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
9073 if (r)
9074 return r;
9075 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
9076 if (r)
9077 return r;
9078 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
9079 if (r)
9080 return r;
9081 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9082 alu.dst.chan = i;
9083 alu.dst.write = 1;
9084 alu.is_op3 = 1;
9085 if (i == lasti)
9086 alu.last = 1;
9087 r = r600_bytecode_add_alu(ctx->bc, &alu);
9088 if (r)
9089 return r;
9090 }
9091 return 0;
9092 }
9093
9094 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
9095 {
9096 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9097 struct r600_bytecode_alu alu;
9098 int i, r;
9099 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9100
9101 for (i = 0; i < lasti + 1; i++) {
9102 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9103 continue;
9104
9105 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9106 alu.op = ALU_OP3_CNDE_INT;
9107 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9108 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9109 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
9110 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9111 alu.dst.chan = i;
9112 alu.dst.write = 1;
9113 alu.is_op3 = 1;
9114 if (i == lasti)
9115 alu.last = 1;
9116 r = r600_bytecode_add_alu(ctx->bc, &alu);
9117 if (r)
9118 return r;
9119 }
9120 return 0;
9121 }
9122
9123 static int tgsi_exp(struct r600_shader_ctx *ctx)
9124 {
9125 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9126 struct r600_bytecode_alu alu;
9127 int r;
9128 unsigned i;
9129
9130 /* result.x = 2^floor(src); */
9131 if (inst->Dst[0].Register.WriteMask & 1) {
9132 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9133
9134 alu.op = ALU_OP1_FLOOR;
9135 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9136
9137 alu.dst.sel = ctx->temp_reg;
9138 alu.dst.chan = 0;
9139 alu.dst.write = 1;
9140 alu.last = 1;
9141 r = r600_bytecode_add_alu(ctx->bc, &alu);
9142 if (r)
9143 return r;
9144
9145 if (ctx->bc->chip_class == CAYMAN) {
9146 for (i = 0; i < 3; i++) {
9147 alu.op = ALU_OP1_EXP_IEEE;
9148 alu.src[0].sel = ctx->temp_reg;
9149 alu.src[0].chan = 0;
9150
9151 alu.dst.sel = ctx->temp_reg;
9152 alu.dst.chan = i;
9153 alu.dst.write = i == 0;
9154 alu.last = i == 2;
9155 r = r600_bytecode_add_alu(ctx->bc, &alu);
9156 if (r)
9157 return r;
9158 }
9159 } else {
9160 alu.op = ALU_OP1_EXP_IEEE;
9161 alu.src[0].sel = ctx->temp_reg;
9162 alu.src[0].chan = 0;
9163
9164 alu.dst.sel = ctx->temp_reg;
9165 alu.dst.chan = 0;
9166 alu.dst.write = 1;
9167 alu.last = 1;
9168 r = r600_bytecode_add_alu(ctx->bc, &alu);
9169 if (r)
9170 return r;
9171 }
9172 }
9173
9174 /* result.y = tmp - floor(tmp); */
9175 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9176 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9177
9178 alu.op = ALU_OP1_FRACT;
9179 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9180
9181 alu.dst.sel = ctx->temp_reg;
9182 #if 0
9183 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9184 if (r)
9185 return r;
9186 #endif
9187 alu.dst.write = 1;
9188 alu.dst.chan = 1;
9189
9190 alu.last = 1;
9191
9192 r = r600_bytecode_add_alu(ctx->bc, &alu);
9193 if (r)
9194 return r;
9195 }
9196
9197 /* result.z = RoughApprox2ToX(tmp);*/
9198 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
9199 if (ctx->bc->chip_class == CAYMAN) {
9200 for (i = 0; i < 3; i++) {
9201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9202 alu.op = ALU_OP1_EXP_IEEE;
9203 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9204
9205 alu.dst.sel = ctx->temp_reg;
9206 alu.dst.chan = i;
9207 if (i == 2) {
9208 alu.dst.write = 1;
9209 alu.last = 1;
9210 }
9211
9212 r = r600_bytecode_add_alu(ctx->bc, &alu);
9213 if (r)
9214 return r;
9215 }
9216 } else {
9217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9218 alu.op = ALU_OP1_EXP_IEEE;
9219 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9220
9221 alu.dst.sel = ctx->temp_reg;
9222 alu.dst.write = 1;
9223 alu.dst.chan = 2;
9224
9225 alu.last = 1;
9226
9227 r = r600_bytecode_add_alu(ctx->bc, &alu);
9228 if (r)
9229 return r;
9230 }
9231 }
9232
9233 /* result.w = 1.0;*/
9234 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
9235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9236
9237 alu.op = ALU_OP1_MOV;
9238 alu.src[0].sel = V_SQ_ALU_SRC_1;
9239 alu.src[0].chan = 0;
9240
9241 alu.dst.sel = ctx->temp_reg;
9242 alu.dst.chan = 3;
9243 alu.dst.write = 1;
9244 alu.last = 1;
9245 r = r600_bytecode_add_alu(ctx->bc, &alu);
9246 if (r)
9247 return r;
9248 }
9249 return tgsi_helper_copy(ctx, inst);
9250 }
9251
9252 static int tgsi_log(struct r600_shader_ctx *ctx)
9253 {
9254 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9255 struct r600_bytecode_alu alu;
9256 int r;
9257 unsigned i;
9258
9259 /* result.x = floor(log2(|src|)); */
9260 if (inst->Dst[0].Register.WriteMask & 1) {
9261 if (ctx->bc->chip_class == CAYMAN) {
9262 for (i = 0; i < 3; i++) {
9263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9264
9265 alu.op = ALU_OP1_LOG_IEEE;
9266 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9267 r600_bytecode_src_set_abs(&alu.src[0]);
9268
9269 alu.dst.sel = ctx->temp_reg;
9270 alu.dst.chan = i;
9271 if (i == 0)
9272 alu.dst.write = 1;
9273 if (i == 2)
9274 alu.last = 1;
9275 r = r600_bytecode_add_alu(ctx->bc, &alu);
9276 if (r)
9277 return r;
9278 }
9279
9280 } else {
9281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9282
9283 alu.op = ALU_OP1_LOG_IEEE;
9284 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9285 r600_bytecode_src_set_abs(&alu.src[0]);
9286
9287 alu.dst.sel = ctx->temp_reg;
9288 alu.dst.chan = 0;
9289 alu.dst.write = 1;
9290 alu.last = 1;
9291 r = r600_bytecode_add_alu(ctx->bc, &alu);
9292 if (r)
9293 return r;
9294 }
9295
9296 alu.op = ALU_OP1_FLOOR;
9297 alu.src[0].sel = ctx->temp_reg;
9298 alu.src[0].chan = 0;
9299
9300 alu.dst.sel = ctx->temp_reg;
9301 alu.dst.chan = 0;
9302 alu.dst.write = 1;
9303 alu.last = 1;
9304
9305 r = r600_bytecode_add_alu(ctx->bc, &alu);
9306 if (r)
9307 return r;
9308 }
9309
9310 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
9311 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9312
9313 if (ctx->bc->chip_class == CAYMAN) {
9314 for (i = 0; i < 3; i++) {
9315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9316
9317 alu.op = ALU_OP1_LOG_IEEE;
9318 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9319 r600_bytecode_src_set_abs(&alu.src[0]);
9320
9321 alu.dst.sel = ctx->temp_reg;
9322 alu.dst.chan = i;
9323 if (i == 1)
9324 alu.dst.write = 1;
9325 if (i == 2)
9326 alu.last = 1;
9327
9328 r = r600_bytecode_add_alu(ctx->bc, &alu);
9329 if (r)
9330 return r;
9331 }
9332 } else {
9333 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9334
9335 alu.op = ALU_OP1_LOG_IEEE;
9336 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9337 r600_bytecode_src_set_abs(&alu.src[0]);
9338
9339 alu.dst.sel = ctx->temp_reg;
9340 alu.dst.chan = 1;
9341 alu.dst.write = 1;
9342 alu.last = 1;
9343
9344 r = r600_bytecode_add_alu(ctx->bc, &alu);
9345 if (r)
9346 return r;
9347 }
9348
9349 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9350
9351 alu.op = ALU_OP1_FLOOR;
9352 alu.src[0].sel = ctx->temp_reg;
9353 alu.src[0].chan = 1;
9354
9355 alu.dst.sel = ctx->temp_reg;
9356 alu.dst.chan = 1;
9357 alu.dst.write = 1;
9358 alu.last = 1;
9359
9360 r = r600_bytecode_add_alu(ctx->bc, &alu);
9361 if (r)
9362 return r;
9363
9364 if (ctx->bc->chip_class == CAYMAN) {
9365 for (i = 0; i < 3; i++) {
9366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9367 alu.op = ALU_OP1_EXP_IEEE;
9368 alu.src[0].sel = ctx->temp_reg;
9369 alu.src[0].chan = 1;
9370
9371 alu.dst.sel = ctx->temp_reg;
9372 alu.dst.chan = i;
9373 if (i == 1)
9374 alu.dst.write = 1;
9375 if (i == 2)
9376 alu.last = 1;
9377
9378 r = r600_bytecode_add_alu(ctx->bc, &alu);
9379 if (r)
9380 return r;
9381 }
9382 } else {
9383 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9384 alu.op = ALU_OP1_EXP_IEEE;
9385 alu.src[0].sel = ctx->temp_reg;
9386 alu.src[0].chan = 1;
9387
9388 alu.dst.sel = ctx->temp_reg;
9389 alu.dst.chan = 1;
9390 alu.dst.write = 1;
9391 alu.last = 1;
9392
9393 r = r600_bytecode_add_alu(ctx->bc, &alu);
9394 if (r)
9395 return r;
9396 }
9397
9398 if (ctx->bc->chip_class == CAYMAN) {
9399 for (i = 0; i < 3; i++) {
9400 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9401 alu.op = ALU_OP1_RECIP_IEEE;
9402 alu.src[0].sel = ctx->temp_reg;
9403 alu.src[0].chan = 1;
9404
9405 alu.dst.sel = ctx->temp_reg;
9406 alu.dst.chan = i;
9407 if (i == 1)
9408 alu.dst.write = 1;
9409 if (i == 2)
9410 alu.last = 1;
9411
9412 r = r600_bytecode_add_alu(ctx->bc, &alu);
9413 if (r)
9414 return r;
9415 }
9416 } else {
9417 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9418 alu.op = ALU_OP1_RECIP_IEEE;
9419 alu.src[0].sel = ctx->temp_reg;
9420 alu.src[0].chan = 1;
9421
9422 alu.dst.sel = ctx->temp_reg;
9423 alu.dst.chan = 1;
9424 alu.dst.write = 1;
9425 alu.last = 1;
9426
9427 r = r600_bytecode_add_alu(ctx->bc, &alu);
9428 if (r)
9429 return r;
9430 }
9431
9432 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9433
9434 alu.op = ALU_OP2_MUL;
9435
9436 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9437 r600_bytecode_src_set_abs(&alu.src[0]);
9438
9439 alu.src[1].sel = ctx->temp_reg;
9440 alu.src[1].chan = 1;
9441
9442 alu.dst.sel = ctx->temp_reg;
9443 alu.dst.chan = 1;
9444 alu.dst.write = 1;
9445 alu.last = 1;
9446
9447 r = r600_bytecode_add_alu(ctx->bc, &alu);
9448 if (r)
9449 return r;
9450 }
9451
9452 /* result.z = log2(|src|);*/
9453 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
9454 if (ctx->bc->chip_class == CAYMAN) {
9455 for (i = 0; i < 3; i++) {
9456 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9457
9458 alu.op = ALU_OP1_LOG_IEEE;
9459 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9460 r600_bytecode_src_set_abs(&alu.src[0]);
9461
9462 alu.dst.sel = ctx->temp_reg;
9463 if (i == 2)
9464 alu.dst.write = 1;
9465 alu.dst.chan = i;
9466 if (i == 2)
9467 alu.last = 1;
9468
9469 r = r600_bytecode_add_alu(ctx->bc, &alu);
9470 if (r)
9471 return r;
9472 }
9473 } else {
9474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9475
9476 alu.op = ALU_OP1_LOG_IEEE;
9477 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9478 r600_bytecode_src_set_abs(&alu.src[0]);
9479
9480 alu.dst.sel = ctx->temp_reg;
9481 alu.dst.write = 1;
9482 alu.dst.chan = 2;
9483 alu.last = 1;
9484
9485 r = r600_bytecode_add_alu(ctx->bc, &alu);
9486 if (r)
9487 return r;
9488 }
9489 }
9490
9491 /* result.w = 1.0; */
9492 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
9493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9494
9495 alu.op = ALU_OP1_MOV;
9496 alu.src[0].sel = V_SQ_ALU_SRC_1;
9497 alu.src[0].chan = 0;
9498
9499 alu.dst.sel = ctx->temp_reg;
9500 alu.dst.chan = 3;
9501 alu.dst.write = 1;
9502 alu.last = 1;
9503
9504 r = r600_bytecode_add_alu(ctx->bc, &alu);
9505 if (r)
9506 return r;
9507 }
9508
9509 return tgsi_helper_copy(ctx, inst);
9510 }
9511
9512 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
9513 {
9514 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9515 struct r600_bytecode_alu alu;
9516 int r;
9517 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9518 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
9519
9520 assert(inst->Dst[0].Register.Index < 3);
9521 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9522
9523 switch (inst->Instruction.Opcode) {
9524 case TGSI_OPCODE_ARL:
9525 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
9526 break;
9527 case TGSI_OPCODE_ARR:
9528 alu.op = ALU_OP1_FLT_TO_INT;
9529 break;
9530 case TGSI_OPCODE_UARL:
9531 alu.op = ALU_OP1_MOV;
9532 break;
9533 default:
9534 assert(0);
9535 return -1;
9536 }
9537
9538 for (i = 0; i <= lasti; ++i) {
9539 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9540 continue;
9541 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9542 alu.last = i == lasti;
9543 alu.dst.sel = reg;
9544 alu.dst.chan = i;
9545 alu.dst.write = 1;
9546 r = r600_bytecode_add_alu(ctx->bc, &alu);
9547 if (r)
9548 return r;
9549 }
9550
9551 if (inst->Dst[0].Register.Index > 0)
9552 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
9553 else
9554 ctx->bc->ar_loaded = 0;
9555
9556 return 0;
9557 }
9558 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
9559 {
9560 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9561 struct r600_bytecode_alu alu;
9562 int r;
9563 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9564
9565 switch (inst->Instruction.Opcode) {
9566 case TGSI_OPCODE_ARL:
9567 memset(&alu, 0, sizeof(alu));
9568 alu.op = ALU_OP1_FLOOR;
9569 alu.dst.sel = ctx->bc->ar_reg;
9570 alu.dst.write = 1;
9571 for (i = 0; i <= lasti; ++i) {
9572 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9573 alu.dst.chan = i;
9574 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9575 alu.last = i == lasti;
9576 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9577 return r;
9578 }
9579 }
9580
9581 memset(&alu, 0, sizeof(alu));
9582 alu.op = ALU_OP1_FLT_TO_INT;
9583 alu.src[0].sel = ctx->bc->ar_reg;
9584 alu.dst.sel = ctx->bc->ar_reg;
9585 alu.dst.write = 1;
9586 /* FLT_TO_INT is trans-only on r600/r700 */
9587 alu.last = TRUE;
9588 for (i = 0; i <= lasti; ++i) {
9589 alu.dst.chan = i;
9590 alu.src[0].chan = i;
9591 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9592 return r;
9593 }
9594 break;
9595 case TGSI_OPCODE_ARR:
9596 memset(&alu, 0, sizeof(alu));
9597 alu.op = ALU_OP1_FLT_TO_INT;
9598 alu.dst.sel = ctx->bc->ar_reg;
9599 alu.dst.write = 1;
9600 /* FLT_TO_INT is trans-only on r600/r700 */
9601 alu.last = TRUE;
9602 for (i = 0; i <= lasti; ++i) {
9603 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9604 alu.dst.chan = i;
9605 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9606 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9607 return r;
9608 }
9609 }
9610 break;
9611 case TGSI_OPCODE_UARL:
9612 memset(&alu, 0, sizeof(alu));
9613 alu.op = ALU_OP1_MOV;
9614 alu.dst.sel = ctx->bc->ar_reg;
9615 alu.dst.write = 1;
9616 for (i = 0; i <= lasti; ++i) {
9617 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9618 alu.dst.chan = i;
9619 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9620 alu.last = i == lasti;
9621 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9622 return r;
9623 }
9624 }
9625 break;
9626 default:
9627 assert(0);
9628 return -1;
9629 }
9630
9631 ctx->bc->ar_loaded = 0;
9632 return 0;
9633 }
9634
9635 static int tgsi_opdst(struct r600_shader_ctx *ctx)
9636 {
9637 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9638 struct r600_bytecode_alu alu;
9639 int i, r = 0;
9640
9641 for (i = 0; i < 4; i++) {
9642 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9643
9644 alu.op = ALU_OP2_MUL;
9645 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9646
9647 if (i == 0 || i == 3) {
9648 alu.src[0].sel = V_SQ_ALU_SRC_1;
9649 } else {
9650 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9651 }
9652
9653 if (i == 0 || i == 2) {
9654 alu.src[1].sel = V_SQ_ALU_SRC_1;
9655 } else {
9656 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
9657 }
9658 if (i == 3)
9659 alu.last = 1;
9660 r = r600_bytecode_add_alu(ctx->bc, &alu);
9661 if (r)
9662 return r;
9663 }
9664 return 0;
9665 }
9666
9667 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type,
9668 struct r600_bytecode_alu_src *src)
9669 {
9670 struct r600_bytecode_alu alu;
9671 int r;
9672
9673 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9674 alu.op = opcode;
9675 alu.execute_mask = 1;
9676 alu.update_pred = 1;
9677
9678 alu.dst.sel = ctx->temp_reg;
9679 alu.dst.write = 1;
9680 alu.dst.chan = 0;
9681
9682 alu.src[0] = *src;
9683 alu.src[1].sel = V_SQ_ALU_SRC_0;
9684 alu.src[1].chan = 0;
9685
9686 alu.last = 1;
9687
9688 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
9689 if (r)
9690 return r;
9691 return 0;
9692 }
9693
9694 static int pops(struct r600_shader_ctx *ctx, int pops)
9695 {
9696 unsigned force_pop = ctx->bc->force_add_cf;
9697
9698 if (!force_pop) {
9699 int alu_pop = 3;
9700 if (ctx->bc->cf_last) {
9701 if (ctx->bc->cf_last->op == CF_OP_ALU)
9702 alu_pop = 0;
9703 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
9704 alu_pop = 1;
9705 }
9706 alu_pop += pops;
9707 if (alu_pop == 1) {
9708 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
9709 ctx->bc->force_add_cf = 1;
9710 } else if (alu_pop == 2) {
9711 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
9712 ctx->bc->force_add_cf = 1;
9713 } else {
9714 force_pop = 1;
9715 }
9716 }
9717
9718 if (force_pop) {
9719 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
9720 ctx->bc->cf_last->pop_count = pops;
9721 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9722 }
9723
9724 return 0;
9725 }
9726
9727 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
9728 unsigned reason)
9729 {
9730 struct r600_stack_info *stack = &ctx->bc->stack;
9731 unsigned elements;
9732 int entries;
9733
9734 unsigned entry_size = stack->entry_size;
9735
9736 elements = (stack->loop + stack->push_wqm ) * entry_size;
9737 elements += stack->push;
9738
9739 switch (ctx->bc->chip_class) {
9740 case R600:
9741 case R700:
9742 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9743 * the stack must be reserved to hold the current active/continue
9744 * masks */
9745 if (reason == FC_PUSH_VPM) {
9746 elements += 2;
9747 }
9748 break;
9749
9750 case CAYMAN:
9751 /* r9xx: any stack operation on empty stack consumes 2 additional
9752 * elements */
9753 elements += 2;
9754
9755 /* fallthrough */
9756 /* FIXME: do the two elements added above cover the cases for the
9757 * r8xx+ below? */
9758
9759 case EVERGREEN:
9760 /* r8xx+: 2 extra elements are not always required, but one extra
9761 * element must be added for each of the following cases:
9762 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9763 * stack usage.
9764 * (Currently we don't use ALU_ELSE_AFTER.)
9765 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9766 * PUSH instruction executed.
9767 *
9768 * NOTE: it seems we also need to reserve additional element in some
9769 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9770 * then STACK_SIZE should be 2 instead of 1 */
9771 if (reason == FC_PUSH_VPM) {
9772 elements += 1;
9773 }
9774 break;
9775
9776 default:
9777 assert(0);
9778 break;
9779 }
9780
9781 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9782 * for all chips, so we use 4 in the final formula, not the real entry_size
9783 * for the chip */
9784 entry_size = 4;
9785
9786 entries = (elements + (entry_size - 1)) / entry_size;
9787
9788 if (entries > stack->max_entries)
9789 stack->max_entries = entries;
9790 }
9791
9792 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
9793 {
9794 switch(reason) {
9795 case FC_PUSH_VPM:
9796 --ctx->bc->stack.push;
9797 assert(ctx->bc->stack.push >= 0);
9798 break;
9799 case FC_PUSH_WQM:
9800 --ctx->bc->stack.push_wqm;
9801 assert(ctx->bc->stack.push_wqm >= 0);
9802 break;
9803 case FC_LOOP:
9804 --ctx->bc->stack.loop;
9805 assert(ctx->bc->stack.loop >= 0);
9806 break;
9807 default:
9808 assert(0);
9809 break;
9810 }
9811 }
9812
9813 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
9814 {
9815 switch (reason) {
9816 case FC_PUSH_VPM:
9817 ++ctx->bc->stack.push;
9818 break;
9819 case FC_PUSH_WQM:
9820 ++ctx->bc->stack.push_wqm;
9821 case FC_LOOP:
9822 ++ctx->bc->stack.loop;
9823 break;
9824 default:
9825 assert(0);
9826 }
9827
9828 callstack_update_max_depth(ctx, reason);
9829 }
9830
9831 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
9832 {
9833 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
9834
9835 sp->mid = realloc((void *)sp->mid,
9836 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
9837 sp->mid[sp->num_mid] = ctx->bc->cf_last;
9838 sp->num_mid++;
9839 }
9840
9841 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
9842 {
9843 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
9844 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
9845 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
9846 ctx->bc->fc_sp++;
9847 }
9848
9849 static void fc_poplevel(struct r600_shader_ctx *ctx)
9850 {
9851 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
9852 free(sp->mid);
9853 sp->mid = NULL;
9854 sp->num_mid = 0;
9855 sp->start = NULL;
9856 sp->type = 0;
9857 ctx->bc->fc_sp--;
9858 }
9859
9860 #if 0
9861 static int emit_return(struct r600_shader_ctx *ctx)
9862 {
9863 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
9864 return 0;
9865 }
9866
9867 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
9868 {
9869
9870 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
9871 ctx->bc->cf_last->pop_count = pops;
9872 /* XXX work out offset */
9873 return 0;
9874 }
9875
9876 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
9877 {
9878 return 0;
9879 }
9880
9881 static void emit_testflag(struct r600_shader_ctx *ctx)
9882 {
9883
9884 }
9885
9886 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
9887 {
9888 emit_testflag(ctx);
9889 emit_jump_to_offset(ctx, 1, 4);
9890 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
9891 pops(ctx, ifidx + 1);
9892 emit_return(ctx);
9893 }
9894
9895 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
9896 {
9897 emit_testflag(ctx);
9898
9899 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9900 ctx->bc->cf_last->pop_count = 1;
9901
9902 fc_set_mid(ctx, fc_sp);
9903
9904 pops(ctx, 1);
9905 }
9906 #endif
9907
9908 static int emit_if(struct r600_shader_ctx *ctx, int opcode,
9909 struct r600_bytecode_alu_src *src)
9910 {
9911 int alu_type = CF_OP_ALU_PUSH_BEFORE;
9912
9913 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9914 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9915 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9916 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9917 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
9918 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
9919 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9920 alu_type = CF_OP_ALU;
9921 }
9922
9923 emit_logic_pred(ctx, opcode, alu_type, src);
9924
9925 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
9926
9927 fc_pushlevel(ctx, FC_IF);
9928
9929 callstack_push(ctx, FC_PUSH_VPM);
9930 return 0;
9931 }
9932
9933 static int tgsi_if(struct r600_shader_ctx *ctx)
9934 {
9935 struct r600_bytecode_alu_src alu_src;
9936 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
9937
9938 return emit_if(ctx, ALU_OP2_PRED_SETNE, &alu_src);
9939 }
9940
9941 static int tgsi_uif(struct r600_shader_ctx *ctx)
9942 {
9943 struct r600_bytecode_alu_src alu_src;
9944 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
9945 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
9946 }
9947
9948 static int tgsi_else(struct r600_shader_ctx *ctx)
9949 {
9950 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
9951 ctx->bc->cf_last->pop_count = 1;
9952
9953 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
9954 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
9955 return 0;
9956 }
9957
9958 static int tgsi_endif(struct r600_shader_ctx *ctx)
9959 {
9960 pops(ctx, 1);
9961 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
9962 R600_ERR("if/endif unbalanced in shader\n");
9963 return -1;
9964 }
9965
9966 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
9967 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9968 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
9969 } else {
9970 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
9971 }
9972 fc_poplevel(ctx);
9973
9974 callstack_pop(ctx, FC_PUSH_VPM);
9975 return 0;
9976 }
9977
9978 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
9979 {
9980 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9981 * limited to 4096 iterations, like the other LOOP_* instructions. */
9982 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
9983
9984 fc_pushlevel(ctx, FC_LOOP);
9985
9986 /* check stack depth */
9987 callstack_push(ctx, FC_LOOP);
9988 return 0;
9989 }
9990
9991 static int tgsi_endloop(struct r600_shader_ctx *ctx)
9992 {
9993 int i;
9994
9995 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
9996
9997 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
9998 R600_ERR("loop/endloop in shader code are not paired.\n");
9999 return -EINVAL;
10000 }
10001
10002 /* fixup loop pointers - from r600isa
10003 LOOP END points to CF after LOOP START,
10004 LOOP START point to CF after LOOP END
10005 BRK/CONT point to LOOP END CF
10006 */
10007 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
10008
10009 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
10010
10011 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
10012 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
10013 }
10014 /* XXX add LOOPRET support */
10015 fc_poplevel(ctx);
10016 callstack_pop(ctx, FC_LOOP);
10017 return 0;
10018 }
10019
10020 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
10021 {
10022 unsigned int fscp;
10023
10024 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
10025 {
10026 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
10027 break;
10028 }
10029
10030 if (fscp == 0) {
10031 R600_ERR("Break not inside loop/endloop pair\n");
10032 return -EINVAL;
10033 }
10034
10035 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10036
10037 fc_set_mid(ctx, fscp - 1);
10038
10039 return 0;
10040 }
10041
10042 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
10043 {
10044 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10045 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
10046 int r;
10047
10048 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10049 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
10050
10051 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10052 if (!r) {
10053 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
10054 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10055 return emit_inc_ring_offset(ctx, stream, TRUE);
10056 }
10057 return r;
10058 }
10059
10060 static int tgsi_umad(struct r600_shader_ctx *ctx)
10061 {
10062 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10063 struct r600_bytecode_alu alu;
10064 int i, j, r;
10065 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10066
10067 /* src0 * src1 */
10068 for (i = 0; i < lasti + 1; i++) {
10069 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10070 continue;
10071
10072 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10073
10074 alu.dst.chan = i;
10075 alu.dst.sel = ctx->temp_reg;
10076 alu.dst.write = 1;
10077
10078 alu.op = ALU_OP2_MULLO_UINT;
10079 for (j = 0; j < 2; j++) {
10080 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
10081 }
10082
10083 alu.last = 1;
10084 r = emit_mul_int_op(ctx->bc, &alu);
10085 if (r)
10086 return r;
10087 }
10088
10089
10090 for (i = 0; i < lasti + 1; i++) {
10091 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10092 continue;
10093
10094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10095 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10096
10097 alu.op = ALU_OP2_ADD_INT;
10098
10099 alu.src[0].sel = ctx->temp_reg;
10100 alu.src[0].chan = i;
10101
10102 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
10103 if (i == lasti) {
10104 alu.last = 1;
10105 }
10106 r = r600_bytecode_add_alu(ctx->bc, &alu);
10107 if (r)
10108 return r;
10109 }
10110 return 0;
10111 }
10112
10113 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
10114 {
10115 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10116 struct r600_bytecode_alu alu;
10117 int r, i;
10118 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10119
10120 /* temp.xy = f32_to_f16(src) */
10121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10122 alu.op = ALU_OP1_FLT32_TO_FLT16;
10123 alu.dst.chan = 0;
10124 alu.dst.sel = ctx->temp_reg;
10125 alu.dst.write = 1;
10126 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10127 r = r600_bytecode_add_alu(ctx->bc, &alu);
10128 if (r)
10129 return r;
10130 alu.dst.chan = 1;
10131 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10132 alu.last = 1;
10133 r = r600_bytecode_add_alu(ctx->bc, &alu);
10134 if (r)
10135 return r;
10136
10137 /* dst.x = temp.y * 0x10000 + temp.x */
10138 for (i = 0; i < lasti + 1; i++) {
10139 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10140 continue;
10141
10142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10143 alu.op = ALU_OP3_MULADD_UINT24;
10144 alu.is_op3 = 1;
10145 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10146 alu.last = i == lasti;
10147 alu.src[0].sel = ctx->temp_reg;
10148 alu.src[0].chan = 1;
10149 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10150 alu.src[1].value = 0x10000;
10151 alu.src[2].sel = ctx->temp_reg;
10152 alu.src[2].chan = 0;
10153 r = r600_bytecode_add_alu(ctx->bc, &alu);
10154 if (r)
10155 return r;
10156 }
10157
10158 return 0;
10159 }
10160
10161 static int tgsi_up2h(struct r600_shader_ctx *ctx)
10162 {
10163 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10164 struct r600_bytecode_alu alu;
10165 int r, i;
10166 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10167
10168 /* temp.x = src.x */
10169 /* note: no need to mask out the high bits */
10170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10171 alu.op = ALU_OP1_MOV;
10172 alu.dst.chan = 0;
10173 alu.dst.sel = ctx->temp_reg;
10174 alu.dst.write = 1;
10175 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10176 r = r600_bytecode_add_alu(ctx->bc, &alu);
10177 if (r)
10178 return r;
10179
10180 /* temp.y = src.x >> 16 */
10181 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10182 alu.op = ALU_OP2_LSHR_INT;
10183 alu.dst.chan = 1;
10184 alu.dst.sel = ctx->temp_reg;
10185 alu.dst.write = 1;
10186 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10187 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10188 alu.src[1].value = 16;
10189 alu.last = 1;
10190 r = r600_bytecode_add_alu(ctx->bc, &alu);
10191 if (r)
10192 return r;
10193
10194 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
10195 for (i = 0; i < lasti + 1; i++) {
10196 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10197 continue;
10198 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10199 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10200 alu.op = ALU_OP1_FLT16_TO_FLT32;
10201 alu.src[0].sel = ctx->temp_reg;
10202 alu.src[0].chan = i % 2;
10203 alu.last = i == lasti;
10204 r = r600_bytecode_add_alu(ctx->bc, &alu);
10205 if (r)
10206 return r;
10207 }
10208
10209 return 0;
10210 }
10211
10212 static int tgsi_bfe(struct r600_shader_ctx *ctx)
10213 {
10214 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10215 struct r600_bytecode_alu alu;
10216 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10217 int r, i;
10218 int dst = -1;
10219
10220 if ((inst->Src[0].Register.File == inst->Dst[0].Register.File &&
10221 inst->Src[0].Register.Index == inst->Dst[0].Register.Index) ||
10222 (inst->Src[2].Register.File == inst->Dst[0].Register.File &&
10223 inst->Src[2].Register.Index == inst->Dst[0].Register.Index))
10224 dst = r600_get_temp(ctx);
10225
10226 r = tgsi_op3_dst(ctx, dst);
10227 if (r)
10228 return r;
10229
10230 for (i = 0; i < lasti + 1; i++) {
10231 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10232 alu.op = ALU_OP2_SETGE_INT;
10233 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
10234 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10235 alu.src[1].value = 32;
10236 alu.dst.sel = ctx->temp_reg;
10237 alu.dst.chan = i;
10238 alu.dst.write = 1;
10239 if (i == lasti)
10240 alu.last = 1;
10241 r = r600_bytecode_add_alu(ctx->bc, &alu);
10242 if (r)
10243 return r;
10244 }
10245
10246 for (i = 0; i < lasti + 1; i++) {
10247 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10248 alu.op = ALU_OP3_CNDE_INT;
10249 alu.is_op3 = 1;
10250 alu.src[0].sel = ctx->temp_reg;
10251 alu.src[0].chan = i;
10252
10253 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10254 if (dst != -1)
10255 alu.src[1].sel = dst;
10256 else
10257 alu.src[1].sel = alu.dst.sel;
10258 alu.src[1].chan = i;
10259 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
10260 alu.dst.write = 1;
10261 if (i == lasti)
10262 alu.last = 1;
10263 r = r600_bytecode_add_alu(ctx->bc, &alu);
10264 if (r)
10265 return r;
10266 }
10267
10268 return 0;
10269 }
10270
10271 static int tgsi_clock(struct r600_shader_ctx *ctx)
10272 {
10273 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10274 struct r600_bytecode_alu alu;
10275 int r;
10276
10277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10278 alu.op = ALU_OP1_MOV;
10279 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10280 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_LO;
10281 r = r600_bytecode_add_alu(ctx->bc, &alu);
10282 if (r)
10283 return r;
10284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10285 alu.op = ALU_OP1_MOV;
10286 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10287 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
10288 r = r600_bytecode_add_alu(ctx->bc, &alu);
10289 if (r)
10290 return r;
10291 return 0;
10292 }
10293
10294 static int emit_u64add(struct r600_shader_ctx *ctx, int op,
10295 int treg,
10296 int src0_sel, int src0_chan,
10297 int src1_sel, int src1_chan)
10298 {
10299 struct r600_bytecode_alu alu;
10300 int r;
10301 int opc;
10302
10303 if (op == ALU_OP2_ADD_INT)
10304 opc = ALU_OP2_ADDC_UINT;
10305 else
10306 opc = ALU_OP2_SUBB_UINT;
10307
10308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10309 alu.op = op; ;
10310 alu.dst.sel = treg;
10311 alu.dst.chan = 0;
10312 alu.dst.write = 1;
10313 alu.src[0].sel = src0_sel;
10314 alu.src[0].chan = src0_chan + 0;
10315 alu.src[1].sel = src1_sel;
10316 alu.src[1].chan = src1_chan + 0;
10317 alu.src[1].neg = 0;
10318 r = r600_bytecode_add_alu(ctx->bc, &alu);
10319 if (r)
10320 return r;
10321
10322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10323 alu.op = op;
10324 alu.dst.sel = treg;
10325 alu.dst.chan = 1;
10326 alu.dst.write = 1;
10327 alu.src[0].sel = src0_sel;
10328 alu.src[0].chan = src0_chan + 1;
10329 alu.src[1].sel = src1_sel;
10330 alu.src[1].chan = src1_chan + 1;
10331 alu.src[1].neg = 0;
10332 r = r600_bytecode_add_alu(ctx->bc, &alu);
10333 if (r)
10334 return r;
10335
10336 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10337 alu.op = opc;
10338 alu.dst.sel = treg;
10339 alu.dst.chan = 2;
10340 alu.dst.write = 1;
10341 alu.last = 1;
10342 alu.src[0].sel = src0_sel;
10343 alu.src[0].chan = src0_chan + 0;
10344 alu.src[1].sel = src1_sel;
10345 alu.src[1].chan = src1_chan + 0;
10346 alu.src[1].neg = 0;
10347 r = r600_bytecode_add_alu(ctx->bc, &alu);
10348 if (r)
10349 return r;
10350
10351 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10352 alu.op = op;
10353 alu.dst.sel = treg;
10354 alu.dst.chan = 1;
10355 alu.dst.write = 1;
10356 alu.src[0].sel = treg;
10357 alu.src[0].chan = 1;
10358 alu.src[1].sel = treg;
10359 alu.src[1].chan = 2;
10360 alu.last = 1;
10361 r = r600_bytecode_add_alu(ctx->bc, &alu);
10362 if (r)
10363 return r;
10364 return 0;
10365 }
10366
10367 static int egcm_u64add(struct r600_shader_ctx *ctx)
10368 {
10369 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10370 struct r600_bytecode_alu alu;
10371 int r;
10372 int treg = ctx->temp_reg;
10373 int op = ALU_OP2_ADD_INT, opc = ALU_OP2_ADDC_UINT;
10374
10375 if (ctx->src[1].neg) {
10376 op = ALU_OP2_SUB_INT;
10377 opc = ALU_OP2_SUBB_UINT;
10378 }
10379 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10380 alu.op = op; ;
10381 alu.dst.sel = treg;
10382 alu.dst.chan = 0;
10383 alu.dst.write = 1;
10384 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10385 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10386 alu.src[1].neg = 0;
10387 r = r600_bytecode_add_alu(ctx->bc, &alu);
10388 if (r)
10389 return r;
10390
10391 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10392 alu.op = op;
10393 alu.dst.sel = treg;
10394 alu.dst.chan = 1;
10395 alu.dst.write = 1;
10396 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10397 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10398 alu.src[1].neg = 0;
10399 r = r600_bytecode_add_alu(ctx->bc, &alu);
10400 if (r)
10401 return r;
10402
10403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10404 alu.op = opc ;
10405 alu.dst.sel = treg;
10406 alu.dst.chan = 2;
10407 alu.dst.write = 1;
10408 alu.last = 1;
10409 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10410 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10411 alu.src[1].neg = 0;
10412 r = r600_bytecode_add_alu(ctx->bc, &alu);
10413 if (r)
10414 return r;
10415
10416 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10417 alu.op = op;
10418 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10419 alu.src[0].sel = treg;
10420 alu.src[0].chan = 1;
10421 alu.src[1].sel = treg;
10422 alu.src[1].chan = 2;
10423 alu.last = 1;
10424 r = r600_bytecode_add_alu(ctx->bc, &alu);
10425 if (r)
10426 return r;
10427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10428 alu.op = ALU_OP1_MOV;
10429 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10430 alu.src[0].sel = treg;
10431 alu.src[0].chan = 0;
10432 alu.last = 1;
10433 r = r600_bytecode_add_alu(ctx->bc, &alu);
10434 if (r)
10435 return r;
10436 return 0;
10437 }
10438
10439 /* result.y = mul_high a, b
10440 result.x = mul a,b
10441 result.y += a.x * b.y + a.y * b.x;
10442 */
10443 static int egcm_u64mul(struct r600_shader_ctx *ctx)
10444 {
10445 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10446 struct r600_bytecode_alu alu;
10447 int r;
10448 int treg = ctx->temp_reg;
10449
10450 /* temp.x = mul_lo a.x, b.x */
10451 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10452 alu.op = ALU_OP2_MULLO_UINT;
10453 alu.dst.sel = treg;
10454 alu.dst.chan = 0;
10455 alu.dst.write = 1;
10456 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10457 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10458 r = emit_mul_int_op(ctx->bc, &alu);
10459 if (r)
10460 return r;
10461
10462 /* temp.y = mul_hi a.x, b.x */
10463 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10464 alu.op = ALU_OP2_MULHI_UINT;
10465 alu.dst.sel = treg;
10466 alu.dst.chan = 1;
10467 alu.dst.write = 1;
10468 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10469 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10470 r = emit_mul_int_op(ctx->bc, &alu);
10471 if (r)
10472 return r;
10473
10474 /* temp.z = mul a.x, b.y */
10475 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10476 alu.op = ALU_OP2_MULLO_UINT;
10477 alu.dst.sel = treg;
10478 alu.dst.chan = 2;
10479 alu.dst.write = 1;
10480 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10481 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10482 r = emit_mul_int_op(ctx->bc, &alu);
10483 if (r)
10484 return r;
10485
10486 /* temp.w = mul a.y, b.x */
10487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10488 alu.op = ALU_OP2_MULLO_UINT;
10489 alu.dst.sel = treg;
10490 alu.dst.chan = 3;
10491 alu.dst.write = 1;
10492 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10493 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10494 r = emit_mul_int_op(ctx->bc, &alu);
10495 if (r)
10496 return r;
10497
10498 /* temp.z = temp.z + temp.w */
10499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10500 alu.op = ALU_OP2_ADD_INT;
10501 alu.dst.sel = treg;
10502 alu.dst.chan = 2;
10503 alu.dst.write = 1;
10504 alu.src[0].sel = treg;
10505 alu.src[0].chan = 2;
10506 alu.src[1].sel = treg;
10507 alu.src[1].chan = 3;
10508 alu.last = 1;
10509 r = r600_bytecode_add_alu(ctx->bc, &alu);
10510 if (r)
10511 return r;
10512
10513 /* temp.y = temp.y + temp.z */
10514 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10515 alu.op = ALU_OP2_ADD_INT;
10516 alu.dst.sel = treg;
10517 alu.dst.chan = 1;
10518 alu.dst.write = 1;
10519 alu.src[0].sel = treg;
10520 alu.src[0].chan = 1;
10521 alu.src[1].sel = treg;
10522 alu.src[1].chan = 2;
10523 alu.last = 1;
10524 r = r600_bytecode_add_alu(ctx->bc, &alu);
10525 if (r)
10526 return r;
10527
10528 /* dst.x = temp.x */
10529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10530 alu.op = ALU_OP1_MOV;
10531 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10532 alu.src[0].sel = treg;
10533 alu.src[0].chan = 0;
10534 r = r600_bytecode_add_alu(ctx->bc, &alu);
10535 if (r)
10536 return r;
10537
10538 /* dst.y = temp.y */
10539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10540 alu.op = ALU_OP1_MOV;
10541 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10542 alu.src[0].sel = treg;
10543 alu.src[0].chan = 1;
10544 alu.last = 1;
10545 r = r600_bytecode_add_alu(ctx->bc, &alu);
10546 if (r)
10547 return r;
10548
10549 return 0;
10550 }
10551
10552 static int emit_u64sge(struct r600_shader_ctx *ctx,
10553 int treg,
10554 int src0_sel, int src0_base_chan,
10555 int src1_sel, int src1_base_chan)
10556 {
10557 int r;
10558 /* for 64-bit sge */
10559 /* result = (src0.y > src1.y) || ((src0.y == src1.y) && src0.x >= src1.x)) */
10560 r = single_alu_op2(ctx, ALU_OP2_SETGT_UINT,
10561 treg, 1,
10562 src0_sel, src0_base_chan + 1,
10563 src1_sel, src1_base_chan + 1);
10564 if (r)
10565 return r;
10566
10567 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10568 treg, 0,
10569 src0_sel, src0_base_chan,
10570 src1_sel, src1_base_chan);
10571 if (r)
10572 return r;
10573
10574 r = single_alu_op2(ctx, ALU_OP2_SETE_INT,
10575 treg, 2,
10576 src0_sel, src0_base_chan + 1,
10577 src1_sel, src1_base_chan + 1);
10578 if (r)
10579 return r;
10580
10581 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
10582 treg, 0,
10583 treg, 0,
10584 treg, 2);
10585 if (r)
10586 return r;
10587
10588 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10589 treg, 0,
10590 treg, 0,
10591 treg, 1);
10592 if (r)
10593 return r;
10594 return 0;
10595 }
10596
10597 /* this isn't a complete div it's just enough for qbo shader to work */
10598 static int egcm_u64div(struct r600_shader_ctx *ctx)
10599 {
10600 struct r600_bytecode_alu alu;
10601 struct r600_bytecode_alu_src alu_num_hi, alu_num_lo, alu_denom_hi, alu_denom_lo, alu_src;
10602 int r, i;
10603 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10604
10605 /* make sure we are dividing my a const with 0 in the high bits */
10606 if (ctx->src[1].sel != V_SQ_ALU_SRC_LITERAL)
10607 return -1;
10608 if (ctx->src[1].value[ctx->src[1].swizzle[1]] != 0)
10609 return -1;
10610 /* make sure we are doing one division */
10611 if (inst->Dst[0].Register.WriteMask != 0x3)
10612 return -1;
10613
10614 /* emit_if uses ctx->temp_reg so we can't */
10615 int treg = r600_get_temp(ctx);
10616 int tmp_num = r600_get_temp(ctx);
10617 int sub_tmp = r600_get_temp(ctx);
10618
10619 /* tmp quot are tmp_num.zw */
10620 r600_bytecode_src(&alu_num_lo, &ctx->src[0], 0);
10621 r600_bytecode_src(&alu_num_hi, &ctx->src[0], 1);
10622 r600_bytecode_src(&alu_denom_lo, &ctx->src[1], 0);
10623 r600_bytecode_src(&alu_denom_hi, &ctx->src[1], 1);
10624
10625 /* MOV tmp_num.xy, numerator */
10626 r = single_alu_op2(ctx, ALU_OP1_MOV,
10627 tmp_num, 0,
10628 alu_num_lo.sel, alu_num_lo.chan,
10629 0, 0);
10630 if (r)
10631 return r;
10632 r = single_alu_op2(ctx, ALU_OP1_MOV,
10633 tmp_num, 1,
10634 alu_num_hi.sel, alu_num_hi.chan,
10635 0, 0);
10636 if (r)
10637 return r;
10638
10639 r = single_alu_op2(ctx, ALU_OP1_MOV,
10640 tmp_num, 2,
10641 V_SQ_ALU_SRC_LITERAL, 0,
10642 0, 0);
10643 if (r)
10644 return r;
10645
10646 r = single_alu_op2(ctx, ALU_OP1_MOV,
10647 tmp_num, 3,
10648 V_SQ_ALU_SRC_LITERAL, 0,
10649 0, 0);
10650 if (r)
10651 return r;
10652
10653 /* treg 0 is log2_denom */
10654 /* normally this gets the MSB for the denom high value
10655 - however we know this will always be 0 here. */
10656 r = single_alu_op2(ctx,
10657 ALU_OP1_MOV,
10658 treg, 0,
10659 V_SQ_ALU_SRC_LITERAL, 32,
10660 0, 0);
10661 if (r)
10662 return r;
10663
10664 /* normally check demon hi for 0, but we know it is already */
10665 /* t0.z = num_hi >= denom_lo */
10666 r = single_alu_op2(ctx,
10667 ALU_OP2_SETGE_UINT,
10668 treg, 1,
10669 alu_num_hi.sel, alu_num_hi.chan,
10670 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
10671 if (r)
10672 return r;
10673
10674 memset(&alu_src, 0, sizeof(alu_src));
10675 alu_src.sel = treg;
10676 alu_src.chan = 1;
10677 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10678 if (r)
10679 return r;
10680
10681 /* for loops in here */
10682 /* get msb t0.x = msb(src[1].x) first */
10683 int msb_lo = util_last_bit(alu_denom_lo.value);
10684 r = single_alu_op2(ctx, ALU_OP1_MOV,
10685 treg, 0,
10686 V_SQ_ALU_SRC_LITERAL, msb_lo,
10687 0, 0);
10688 if (r)
10689 return r;
10690
10691 /* unroll the asm here */
10692 for (i = 0; i < 31; i++) {
10693 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10694 treg, 2,
10695 V_SQ_ALU_SRC_LITERAL, i,
10696 treg, 0);
10697 if (r)
10698 return r;
10699
10700 /* we can do this on the CPU */
10701 uint32_t denom_lo_shl = alu_denom_lo.value << (31 - i);
10702 /* t0.z = tmp_num.y >= t0.z */
10703 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10704 treg, 1,
10705 tmp_num, 1,
10706 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
10707 if (r)
10708 return r;
10709
10710 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
10711 treg, 1,
10712 treg, 1,
10713 treg, 2);
10714 if (r)
10715 return r;
10716
10717 memset(&alu_src, 0, sizeof(alu_src));
10718 alu_src.sel = treg;
10719 alu_src.chan = 1;
10720 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10721 if (r)
10722 return r;
10723
10724 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
10725 tmp_num, 1,
10726 tmp_num, 1,
10727 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
10728 if (r)
10729 return r;
10730
10731 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10732 tmp_num, 3,
10733 tmp_num, 3,
10734 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
10735 if (r)
10736 return r;
10737
10738 r = tgsi_endif(ctx);
10739 if (r)
10740 return r;
10741 }
10742
10743 /* log2_denom is always <= 31, so manually peel the last loop
10744 * iteration.
10745 */
10746 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10747 treg, 1,
10748 tmp_num, 1,
10749 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
10750 if (r)
10751 return r;
10752
10753 memset(&alu_src, 0, sizeof(alu_src));
10754 alu_src.sel = treg;
10755 alu_src.chan = 1;
10756 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10757 if (r)
10758 return r;
10759
10760 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
10761 tmp_num, 1,
10762 tmp_num, 1,
10763 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
10764 if (r)
10765 return r;
10766
10767 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10768 tmp_num, 3,
10769 tmp_num, 3,
10770 V_SQ_ALU_SRC_LITERAL, 1U);
10771 if (r)
10772 return r;
10773 r = tgsi_endif(ctx);
10774 if (r)
10775 return r;
10776
10777 r = tgsi_endif(ctx);
10778 if (r)
10779 return r;
10780
10781 /* onto the second loop to unroll */
10782 for (i = 0; i < 31; i++) {
10783 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
10784 treg, 1,
10785 V_SQ_ALU_SRC_LITERAL, (63 - (31 - i)),
10786 treg, 0);
10787 if (r)
10788 return r;
10789
10790 uint64_t denom_shl = (uint64_t)alu_denom_lo.value << (31 - i);
10791 r = single_alu_op2(ctx, ALU_OP1_MOV,
10792 treg, 2,
10793 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
10794 0, 0);
10795 if (r)
10796 return r;
10797
10798 r = single_alu_op2(ctx, ALU_OP1_MOV,
10799 treg, 3,
10800 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
10801 0, 0);
10802 if (r)
10803 return r;
10804
10805 r = emit_u64sge(ctx, sub_tmp,
10806 tmp_num, 0,
10807 treg, 2);
10808 if (r)
10809 return r;
10810
10811 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
10812 treg, 1,
10813 treg, 1,
10814 sub_tmp, 0);
10815 if (r)
10816 return r;
10817
10818 memset(&alu_src, 0, sizeof(alu_src));
10819 alu_src.sel = treg;
10820 alu_src.chan = 1;
10821 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10822 if (r)
10823 return r;
10824
10825
10826 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
10827 sub_tmp,
10828 tmp_num, 0,
10829 treg, 2);
10830 if (r)
10831 return r;
10832
10833 r = single_alu_op2(ctx, ALU_OP1_MOV,
10834 tmp_num, 0,
10835 sub_tmp, 0,
10836 0, 0);
10837 if (r)
10838 return r;
10839
10840 r = single_alu_op2(ctx, ALU_OP1_MOV,
10841 tmp_num, 1,
10842 sub_tmp, 1,
10843 0, 0);
10844 if (r)
10845 return r;
10846
10847 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10848 tmp_num, 2,
10849 tmp_num, 2,
10850 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
10851 if (r)
10852 return r;
10853
10854 r = tgsi_endif(ctx);
10855 if (r)
10856 return r;
10857 }
10858
10859 /* log2_denom is always <= 63, so manually peel the last loop
10860 * iteration.
10861 */
10862 uint64_t denom_shl = (uint64_t)alu_denom_lo.value;
10863 r = single_alu_op2(ctx, ALU_OP1_MOV,
10864 treg, 2,
10865 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
10866 0, 0);
10867 if (r)
10868 return r;
10869
10870 r = single_alu_op2(ctx, ALU_OP1_MOV,
10871 treg, 3,
10872 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
10873 0, 0);
10874 if (r)
10875 return r;
10876
10877 r = emit_u64sge(ctx, sub_tmp,
10878 tmp_num, 0,
10879 treg, 2);
10880 if (r)
10881 return r;
10882
10883 memset(&alu_src, 0, sizeof(alu_src));
10884 alu_src.sel = sub_tmp;
10885 alu_src.chan = 0;
10886 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10887 if (r)
10888 return r;
10889
10890 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
10891 sub_tmp,
10892 tmp_num, 0,
10893 treg, 2);
10894 if (r)
10895 return r;
10896
10897 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
10898 tmp_num, 2,
10899 tmp_num, 2,
10900 V_SQ_ALU_SRC_LITERAL, 1U);
10901 if (r)
10902 return r;
10903 r = tgsi_endif(ctx);
10904 if (r)
10905 return r;
10906
10907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10908 alu.op = ALU_OP1_MOV;
10909 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10910 alu.src[0].sel = tmp_num;
10911 alu.src[0].chan = 2;
10912 r = r600_bytecode_add_alu(ctx->bc, &alu);
10913 if (r)
10914 return r;
10915
10916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10917 alu.op = ALU_OP1_MOV;
10918 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10919 alu.src[0].sel = tmp_num;
10920 alu.src[0].chan = 3;
10921 alu.last = 1;
10922 r = r600_bytecode_add_alu(ctx->bc, &alu);
10923 if (r)
10924 return r;
10925 return 0;
10926 }
10927
10928 static int egcm_u64sne(struct r600_shader_ctx *ctx)
10929 {
10930 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10931 struct r600_bytecode_alu alu;
10932 int r;
10933 int treg = ctx->temp_reg;
10934
10935 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10936 alu.op = ALU_OP2_SETNE_INT;
10937 alu.dst.sel = treg;
10938 alu.dst.chan = 0;
10939 alu.dst.write = 1;
10940 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10941 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10942 r = r600_bytecode_add_alu(ctx->bc, &alu);
10943 if (r)
10944 return r;
10945
10946 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10947 alu.op = ALU_OP2_SETNE_INT;
10948 alu.dst.sel = treg;
10949 alu.dst.chan = 1;
10950 alu.dst.write = 1;
10951 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10952 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10953 alu.last = 1;
10954 r = r600_bytecode_add_alu(ctx->bc, &alu);
10955 if (r)
10956 return r;
10957
10958 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10959 alu.op = ALU_OP2_OR_INT;
10960 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10961 alu.src[0].sel = treg;
10962 alu.src[0].chan = 0;
10963 alu.src[1].sel = treg;
10964 alu.src[1].chan = 1;
10965 alu.last = 1;
10966 r = r600_bytecode_add_alu(ctx->bc, &alu);
10967 if (r)
10968 return r;
10969 return 0;
10970 }
10971
10972 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
10973 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
10974 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10975 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10976
10977 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
10978
10979 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
10980 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10981 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10982 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10983 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10984 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10985 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10986 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10987 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
10988 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10989 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10990 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10991 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10992 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10993 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10994 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
10995 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
10996 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10997 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10998 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10999 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11000 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11001 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11002 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11003 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11004 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11005 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11006 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11007 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11008 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_unsupported},
11009 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11010 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11011 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11012 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11013 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11014 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11015 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
11016 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11017 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11018 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11019 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11020 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11021 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11022 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11023 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11024 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11025 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11026 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11027 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11028 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11029 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11030 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
11031 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11032 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11033 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11034 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11035 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11036 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
11037 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11038 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11039 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11040 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11041 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11042 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11043 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11044 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11045 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11046 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11047 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11048 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11049 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11050 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11051 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11052 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11053 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11054 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11055 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11056 [81] = { ALU_OP0_NOP, tgsi_unsupported},
11057 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11058 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11059 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11060 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11061 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11062 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
11063 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11064 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11065 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11066 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11067 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11068 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11069 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11070 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11071 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11072 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11073 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11074 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11075 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11076 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11077 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11078 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11079 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11080 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
11081 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11082 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11083 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11084 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11085 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11086 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11087 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
11088 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11089 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11090 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11091 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11092 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11093 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
11094 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
11095 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11096 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11097 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11098 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11099 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11100 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
11101 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11102 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
11103 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11104 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11105 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11106 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11107 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11108 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11109 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11110 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11111 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11112 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11113 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
11114 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11115 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
11116 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11117 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11118 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11119 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11120 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11121 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11122 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11123 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11124 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11125 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11126 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11127 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11128 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11129 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11130 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11131 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11132 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
11133 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11134 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11135 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11136 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
11137 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
11138 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11139 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11140 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11141 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
11142 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
11143 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
11144 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
11145 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
11146 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
11147 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
11148 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11149 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11150 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11151 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11152 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11153 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11154 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11155 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11156 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11157 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
11158 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
11159 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
11160 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
11161 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
11162 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
11163 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
11164 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
11165 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
11166 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
11167 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
11168 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
11169 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
11170 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11171 };
11172
11173 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
11174 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11175 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11176 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11177 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
11178 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
11179 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11180 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11181 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11182 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11183 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11184 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11185 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11186 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11187 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11188 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11189 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11190 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11191 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11192 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11193 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
11194 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11195 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11196 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11197 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11198 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11199 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11200 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11201 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11202 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11203 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11204 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11205 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11206 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11207 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11208 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11209 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11210 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11211 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11212 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11213 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11214 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11215 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11216 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11217 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11218 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11219 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11220 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11221 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11222 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11223 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11224 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11225 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11226 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11227 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11228 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11229 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11230 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11231 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11232 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11233 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11234 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11235 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11236 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11237 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11238 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11239 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11240 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11241 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11242 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11243 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11244 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11245 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11246 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11247 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11248 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11249 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11250 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11251 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11252 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11253 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11254 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11255 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11256 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11257 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11258 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11259 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
11260 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11261 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11262 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11263 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11264 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11265 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11266 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11267 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11268 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11269 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11270 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11271 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11272 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11273 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11274 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11275 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11276 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11277 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
11278 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11279 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11280 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11281 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11282 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11283 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11284 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11285 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11286 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11287 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11288 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11289 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11290 /* Refer below for TGSI_OPCODE_DFMA */
11291 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
11292 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11293 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11294 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11295 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11296 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11297 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
11298 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11299 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
11300 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11301 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11302 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11303 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11304 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11305 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11306 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11307 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11308 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11309 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11310 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
11311 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11312 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
11313 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11314 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11315 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11316 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11317 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11318 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11319 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11320 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11321 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11322 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11323 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11324 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11325 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11326 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11327 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11328 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11329 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
11330 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11331 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11332 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11333 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
11334 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
11335 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11336 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11337 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11338 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11339 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
11340 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
11341 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
11342 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
11343 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
11344 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
11345 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
11346 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
11347 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
11348 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
11349 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11350 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11351 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11352 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11353 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11354 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
11355 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
11356 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
11357 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
11358 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
11359 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
11360 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
11361 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
11362 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
11363 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
11364 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
11365 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
11366 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
11367 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
11368 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
11369 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
11370 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
11371 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
11372 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
11373 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
11374 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
11375 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
11376 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
11377 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
11378 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
11379 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
11380 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
11381 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
11382 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
11383 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
11384 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
11385 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
11386 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
11387 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
11388 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
11389 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
11390 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
11391 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
11392 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
11393 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
11394 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
11395 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
11396 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11397 };
11398
11399 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
11400 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11401 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11402 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11403 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
11404 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
11405 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11406 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11407 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11408 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11409 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11410 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11411 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11412 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11413 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11414 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11415 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11416 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11417 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11418 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11419 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
11420 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11421 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11422 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11423 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11424 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11425 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11426 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11427 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
11428 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
11429 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
11430 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11431 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11432 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11433 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11434 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11435 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
11436 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11437 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11438 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11439 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11440 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11441 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11442 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11443 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11444 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11445 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11446 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11447 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
11448 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11449 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11450 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11451 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11452 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11453 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11454 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11455 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11456 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11457 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11458 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11459 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11460 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11461 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11462 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11463 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11464 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11465 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11466 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11467 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11468 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11469 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11470 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11471 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11472 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11473 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11474 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11475 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11476 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11477 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11478 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11479 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11480 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11481 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11482 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
11483 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11484 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11485 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
11486 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11487 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11488 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11489 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11490 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11491 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11492 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11493 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11494 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11495 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11496 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11497 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11498 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11499 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11500 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11501 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11502 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11503 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
11504 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11505 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11506 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11507 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11508 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11509 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11510 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11511 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11512 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11513 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11514 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11515 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11516 /* Refer below for TGSI_OPCODE_DFMA */
11517 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
11518 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11519 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11520 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11521 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11522 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11523 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
11524 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11525 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
11526 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
11527 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11528 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11529 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11530 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11531 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11532 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11533 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
11534 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11535 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11536 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
11537 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11538 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
11539 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11540 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11541 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11542 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11543 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11544 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11545 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11546 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11547 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11548 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11549 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11550 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11551 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11552 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11553 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11554 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11555 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
11556 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11557 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11558 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11559 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
11560 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
11561 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11562 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11563 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11564 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11565 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
11566 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
11567 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
11568 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
11569 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
11570 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
11571 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
11572 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
11573 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
11574 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
11575 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11576 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11577 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11578 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
11579 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
11580 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
11581 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
11582 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
11583 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
11584 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
11585 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
11586 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
11587 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
11588 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
11589 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
11590 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
11591 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
11592 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
11593 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
11594 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
11595 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
11596 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
11597 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
11598 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
11599 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
11600 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
11601 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
11602 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
11603 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
11604 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
11605 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
11606 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
11607 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
11608 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
11609 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
11610 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
11611 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
11612 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
11613 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
11614 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
11615 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
11616 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
11617 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
11618 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
11619 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
11620 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
11621 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
11622 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11623 };