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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
31 #include "r600_asm.h"
32 #include "r600_sq.h"
33 #include "r600d.h"
34 #include <stdio.h>
35 #include <errno.h>
36
37
38 struct r600_shader_tgsi_instruction;
39
40 struct r600_shader_ctx {
41 struct tgsi_shader_info info;
42 struct tgsi_parse_context parse;
43 const struct tgsi_token *tokens;
44 unsigned type;
45 unsigned file_offset[TGSI_FILE_COUNT];
46 unsigned temp_reg;
47 struct r600_shader_tgsi_instruction *inst_info;
48 struct r600_bc *bc;
49 struct r600_shader *shader;
50 u32 value[4];
51 };
52
53 struct r600_shader_tgsi_instruction {
54 unsigned tgsi_opcode;
55 unsigned is_op3;
56 unsigned r600_opcode;
57 int (*process)(struct r600_shader_ctx *ctx);
58 };
59
60 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
61 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
62
63 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
64 {
65 struct r600_context *rctx = r600_context(ctx);
66 const struct util_format_description *desc;
67 enum pipe_format resource_format[160];
68 unsigned i, nresources = 0;
69 struct r600_bc *bc = &shader->bc;
70 struct r600_bc_cf *cf;
71 struct r600_bc_vtx *vtx;
72
73 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
74 return 0;
75 for (i = 0; i < rctx->vertex_elements->count; i++) {
76 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
77 }
78 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
79 switch (cf->inst) {
80 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
81 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
82 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
83 desc = util_format_description(resource_format[vtx->buffer_id]);
84 if (desc == NULL) {
85 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
86 return -EINVAL;
87 }
88 vtx->dst_sel_x = desc->swizzle[0];
89 vtx->dst_sel_y = desc->swizzle[1];
90 vtx->dst_sel_z = desc->swizzle[2];
91 vtx->dst_sel_w = desc->swizzle[3];
92 }
93 break;
94 default:
95 break;
96 }
97 }
98 return r600_bc_build(&shader->bc);
99 }
100
101 int r600_pipe_shader_create(struct pipe_context *ctx,
102 struct r600_context_state *rpshader,
103 const struct tgsi_token *tokens)
104 {
105 struct r600_screen *rscreen = r600_screen(ctx->screen);
106 int r;
107
108 fprintf(stderr, "--------------------------------------------------------------\n");
109 tgsi_dump(tokens, 0);
110 if (rpshader == NULL)
111 return -ENOMEM;
112 rpshader->shader.family = radeon_get_family(rscreen->rw);
113 r = r600_shader_from_tgsi(tokens, &rpshader->shader);
114 if (r) {
115 R600_ERR("translation from TGSI failed !\n");
116 return r;
117 }
118 r = r600_bc_build(&rpshader->shader.bc);
119 if (r) {
120 R600_ERR("building bytecode failed !\n");
121 return r;
122 }
123 fprintf(stderr, "______________________________________________________________\n");
124 return 0;
125 }
126
127 static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
128 {
129 struct r600_screen *rscreen = r600_screen(ctx->screen);
130 struct r600_shader *rshader = &rpshader->shader;
131 struct radeon_state *state;
132 unsigned i, tmp;
133
134 rpshader->rstate = radeon_state_decref(rpshader->rstate);
135 state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
136 if (state == NULL)
137 return -ENOMEM;
138 for (i = 0; i < 10; i++) {
139 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
140 }
141 /* so far never got proper semantic id from tgsi */
142 for (i = 0; i < 32; i++) {
143 tmp = i << ((i & 3) * 8);
144 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
145 }
146 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
147 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
148 rpshader->rstate = state;
149 rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
150 rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
151 rpshader->rstate->nbo = 2;
152 rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
153 return radeon_state_pm4(state);
154 }
155
156 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
157 {
158 const struct pipe_rasterizer_state *rasterizer;
159 struct r600_screen *rscreen = r600_screen(ctx->screen);
160 struct r600_shader *rshader = &rpshader->shader;
161 struct r600_context *rctx = r600_context(ctx);
162 struct radeon_state *state;
163 unsigned i, tmp, exports_ps, num_cout;
164
165 rasterizer = &rctx->rasterizer->state.rasterizer;
166 rpshader->rstate = radeon_state_decref(rpshader->rstate);
167 state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
168 if (state == NULL)
169 return -ENOMEM;
170 for (i = 0; i < rshader->ninput; i++) {
171 tmp = S_028644_SEMANTIC(i);
172 tmp |= S_028644_SEL_CENTROID(1);
173 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
174 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR) {
175 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
176 }
177 if (rasterizer->sprite_coord_enable & (1 << i)) {
178 tmp |= S_028644_PT_SPRITE_TEX(1);
179 }
180 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
181 }
182
183 exports_ps = 0;
184 num_cout = 0;
185 for (i = 0; i < rshader->noutput; i++) {
186 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
187 exports_ps |= 1;
188 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
189 exports_ps |= (1 << (num_cout+1));
190 num_cout++;
191 }
192 }
193 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
194 S_0286CC_PERSP_GRADIENT_ENA(1);
195 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
196 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
197 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
198 rpshader->rstate = state;
199 rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
200 rpshader->rstate->nbo = 1;
201 rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
202 return radeon_state_pm4(state);
203 }
204
205 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
206 {
207 struct r600_screen *rscreen = r600_screen(ctx->screen);
208 struct r600_context *rctx = r600_context(ctx);
209 struct r600_shader *rshader = &rpshader->shader;
210 int r;
211
212 /* copy new shader */
213 radeon_bo_decref(rscreen->rw, rpshader->bo);
214 rpshader->bo = NULL;
215 rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->bc.ndw * 4,
216 4096, NULL);
217 if (rpshader->bo == NULL) {
218 return -ENOMEM;
219 }
220 radeon_bo_map(rscreen->rw, rpshader->bo);
221 memcpy(rpshader->bo->data, rshader->bc.bytecode, rshader->bc.ndw * 4);
222 radeon_bo_unmap(rscreen->rw, rpshader->bo);
223 /* build state */
224 rshader->flat_shade = rctx->flat_shade;
225 switch (rshader->processor_type) {
226 case TGSI_PROCESSOR_VERTEX:
227 r = r600_pipe_shader_vs(ctx, rpshader);
228 break;
229 case TGSI_PROCESSOR_FRAGMENT:
230 r = r600_pipe_shader_ps(ctx, rpshader);
231 break;
232 default:
233 r = -EINVAL;
234 break;
235 }
236 return r;
237 }
238
239 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
240 {
241 struct r600_context *rctx = r600_context(ctx);
242 int r;
243
244 if (rpshader == NULL)
245 return -EINVAL;
246 /* there should be enough input */
247 if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
248 R600_ERR("%d resources provided, expecting %d\n",
249 rctx->vertex_elements->count, rpshader->shader.bc.nresource);
250 return -EINVAL;
251 }
252 r = r600_shader_update(ctx, &rpshader->shader);
253 if (r)
254 return r;
255 return r600_pipe_shader(ctx, rpshader);
256 }
257
258 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
259 {
260 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
261 int j;
262
263 if (i->Instruction.NumDstRegs > 1) {
264 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
265 return -EINVAL;
266 }
267 if (i->Instruction.Predicate) {
268 R600_ERR("predicate unsupported\n");
269 return -EINVAL;
270 }
271 if (i->Instruction.Label) {
272 R600_ERR("label unsupported\n");
273 return -EINVAL;
274 }
275 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
276 if (i->Src[j].Register.Indirect ||
277 i->Src[j].Register.Dimension ||
278 i->Src[j].Register.Absolute) {
279 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
280 return -EINVAL;
281 }
282 }
283 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
284 if (i->Dst[j].Register.Indirect || i->Dst[j].Register.Dimension) {
285 R600_ERR("unsupported dst (indirect|dimension)\n");
286 return -EINVAL;
287 }
288 }
289 return 0;
290 }
291
292 static int tgsi_declaration(struct r600_shader_ctx *ctx)
293 {
294 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
295 struct r600_bc_vtx vtx;
296 unsigned i;
297 int r;
298
299 switch (d->Declaration.File) {
300 case TGSI_FILE_INPUT:
301 i = ctx->shader->ninput++;
302 ctx->shader->input[i].name = d->Semantic.Name;
303 ctx->shader->input[i].sid = d->Semantic.Index;
304 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
305 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
306 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
307 /* turn input into fetch */
308 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
309 vtx.inst = 0;
310 vtx.fetch_type = 0;
311 vtx.buffer_id = i;
312 /* register containing the index into the buffer */
313 vtx.src_gpr = 0;
314 vtx.src_sel_x = 0;
315 vtx.mega_fetch_count = 0x1F;
316 vtx.dst_gpr = ctx->shader->input[i].gpr;
317 vtx.dst_sel_x = 0;
318 vtx.dst_sel_y = 1;
319 vtx.dst_sel_z = 2;
320 vtx.dst_sel_w = 3;
321 r = r600_bc_add_vtx(ctx->bc, &vtx);
322 if (r)
323 return r;
324 }
325 break;
326 case TGSI_FILE_OUTPUT:
327 i = ctx->shader->noutput++;
328 ctx->shader->output[i].name = d->Semantic.Name;
329 ctx->shader->output[i].sid = d->Semantic.Index;
330 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
331 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
332 break;
333 case TGSI_FILE_CONSTANT:
334 case TGSI_FILE_TEMPORARY:
335 case TGSI_FILE_SAMPLER:
336 break;
337 default:
338 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
339 return -EINVAL;
340 }
341 return 0;
342 }
343
344 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
345 {
346 struct tgsi_full_immediate *immediate;
347 struct r600_shader_ctx ctx;
348 struct r600_bc_output output[32];
349 unsigned output_done, noutput;
350 unsigned opcode;
351 int i, r = 0, pos0;
352
353 ctx.bc = &shader->bc;
354 ctx.shader = shader;
355 r = r600_bc_init(ctx.bc, shader->family);
356 if (r)
357 return r;
358 ctx.tokens = tokens;
359 tgsi_scan_shader(tokens, &ctx.info);
360 tgsi_parse_init(&ctx.parse, tokens);
361 ctx.type = ctx.parse.FullHeader.Processor.Processor;
362 shader->processor_type = ctx.type;
363
364 /* register allocations */
365 /* Values [0,127] correspond to GPR[0..127].
366 * Values [256,511] correspond to cfile constants c[0..255].
367 * Other special values are shown in the list below.
368 * 248 SQ_ALU_SRC_0: special constant 0.0.
369 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
370 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
371 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
372 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
373 * 253 SQ_ALU_SRC_LITERAL: literal constant.
374 * 254 SQ_ALU_SRC_PV: previous vector result.
375 * 255 SQ_ALU_SRC_PS: previous scalar result.
376 */
377 for (i = 0; i < TGSI_FILE_COUNT; i++) {
378 ctx.file_offset[i] = 0;
379 }
380 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
381 ctx.file_offset[TGSI_FILE_INPUT] = 1;
382 }
383 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
384 ctx.info.file_count[TGSI_FILE_INPUT];
385 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
386 ctx.info.file_count[TGSI_FILE_OUTPUT];
387 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
388 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
389 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
390 ctx.info.file_count[TGSI_FILE_TEMPORARY];
391
392 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
393 tgsi_parse_token(&ctx.parse);
394 switch (ctx.parse.FullToken.Token.Type) {
395 case TGSI_TOKEN_TYPE_IMMEDIATE:
396 immediate = &ctx.parse.FullToken.FullImmediate;
397 ctx.value[0] = immediate->u[0].Uint;
398 ctx.value[1] = immediate->u[1].Uint;
399 ctx.value[2] = immediate->u[2].Uint;
400 ctx.value[3] = immediate->u[3].Uint;
401 break;
402 case TGSI_TOKEN_TYPE_DECLARATION:
403 r = tgsi_declaration(&ctx);
404 if (r)
405 goto out_err;
406 break;
407 case TGSI_TOKEN_TYPE_INSTRUCTION:
408 r = tgsi_is_supported(&ctx);
409 if (r)
410 goto out_err;
411 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
412 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
413 r = ctx.inst_info->process(&ctx);
414 if (r)
415 goto out_err;
416 r = r600_bc_add_literal(ctx.bc, ctx.value);
417 if (r)
418 goto out_err;
419 break;
420 default:
421 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
422 r = -EINVAL;
423 goto out_err;
424 }
425 }
426 /* export output */
427 noutput = shader->noutput;
428 for (i = 0, pos0 = 0; i < noutput; i++) {
429 memset(&output[i], 0, sizeof(struct r600_bc_output));
430 output[i].gpr = shader->output[i].gpr;
431 output[i].elem_size = 3;
432 output[i].swizzle_x = 0;
433 output[i].swizzle_y = 1;
434 output[i].swizzle_z = 2;
435 output[i].swizzle_w = 3;
436 output[i].barrier = 1;
437 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
438 output[i].array_base = i - pos0;
439 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
440 switch (ctx.type) {
441 case TGSI_PROCESSOR_VERTEX:
442 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
443 output[i].array_base = 60;
444 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
445 /* position doesn't count in array_base */
446 pos0++;
447 }
448 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
449 output[i].array_base = 61;
450 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
451 /* position doesn't count in array_base */
452 pos0++;
453 }
454 break;
455 case TGSI_PROCESSOR_FRAGMENT:
456 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
457 output[i].array_base = shader->output[i].sid;
458 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
459 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
460 output[i].array_base = 61;
461 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
462 } else {
463 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
464 r = -EINVAL;
465 goto out_err;
466 }
467 break;
468 default:
469 R600_ERR("unsupported processor type %d\n", ctx.type);
470 r = -EINVAL;
471 goto out_err;
472 }
473 }
474 /* add fake param output for vertex shader if no param is exported */
475 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
476 for (i = 0, pos0 = 0; i < noutput; i++) {
477 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
478 pos0 = 1;
479 break;
480 }
481 }
482 if (!pos0) {
483 memset(&output[i], 0, sizeof(struct r600_bc_output));
484 output[i].gpr = 0;
485 output[i].elem_size = 3;
486 output[i].swizzle_x = 0;
487 output[i].swizzle_y = 1;
488 output[i].swizzle_z = 2;
489 output[i].swizzle_w = 3;
490 output[i].barrier = 1;
491 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
492 output[i].array_base = 0;
493 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
494 noutput++;
495 }
496 }
497 /* set export done on last export of each type */
498 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
499 if (i == (noutput - 1)) {
500 output[i].end_of_program = 1;
501 }
502 if (!(output_done & (1 << output[i].type))) {
503 output_done |= (1 << output[i].type);
504 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
505 }
506 }
507 /* add output to bytecode */
508 for (i = 0; i < noutput; i++) {
509 r = r600_bc_add_output(ctx.bc, &output[i]);
510 if (r)
511 goto out_err;
512 }
513 tgsi_parse_free(&ctx.parse);
514 return 0;
515 out_err:
516 tgsi_parse_free(&ctx.parse);
517 return r;
518 }
519
520 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
521 {
522 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
523 return -EINVAL;
524 }
525
526 static int tgsi_end(struct r600_shader_ctx *ctx)
527 {
528 return 0;
529 }
530
531 static int tgsi_src(struct r600_shader_ctx *ctx,
532 const struct tgsi_full_src_register *tgsi_src,
533 struct r600_bc_alu_src *r600_src)
534 {
535 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
536 r600_src->sel = tgsi_src->Register.Index;
537 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
538 r600_src->sel = 0;
539 }
540 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
541 return 0;
542 }
543
544 static int tgsi_dst(struct r600_shader_ctx *ctx,
545 const struct tgsi_full_dst_register *tgsi_dst,
546 unsigned swizzle,
547 struct r600_bc_alu_dst *r600_dst)
548 {
549 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
550
551 r600_dst->sel = tgsi_dst->Register.Index;
552 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
553 r600_dst->chan = swizzle;
554 r600_dst->write = 1;
555 if (inst->Instruction.Saturate) {
556 r600_dst->clamp = 1;
557 }
558 return 0;
559 }
560
561 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
562 {
563 switch (swizzle) {
564 case 0:
565 return tgsi_src->Register.SwizzleX;
566 case 1:
567 return tgsi_src->Register.SwizzleY;
568 case 2:
569 return tgsi_src->Register.SwizzleZ;
570 case 3:
571 return tgsi_src->Register.SwizzleW;
572 default:
573 return 0;
574 }
575 }
576
577 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
578 {
579 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
580 struct r600_bc_alu alu;
581 int i, j, k, nconst, r;
582
583 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
584 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
585 nconst++;
586 }
587 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
588 if (r) {
589 return r;
590 }
591 }
592 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
593 if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
594 for (k = 0; k < 4; k++) {
595 memset(&alu, 0, sizeof(struct r600_bc_alu));
596 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
597 alu.src[0].sel = r600_src[0].sel;
598 alu.src[0].chan = k;
599 alu.dst.sel = ctx->temp_reg + j;
600 alu.dst.chan = k;
601 alu.dst.write = 1;
602 if (k == 3)
603 alu.last = 1;
604 r = r600_bc_add_alu(ctx->bc, &alu);
605 if (r)
606 return r;
607 }
608 r600_src[0].sel = ctx->temp_reg + j;
609 j--;
610 }
611 }
612 return 0;
613 }
614
615 static int tgsi_op2(struct r600_shader_ctx *ctx)
616 {
617 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
618 struct r600_bc_alu_src r600_src[3];
619 struct r600_bc_alu alu;
620 int i, j, r;
621
622 r = tgsi_split_constant(ctx, r600_src);
623 if (r)
624 return r;
625 for (i = 0; i < 4; i++) {
626 memset(&alu, 0, sizeof(struct r600_bc_alu));
627 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
628 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
629 alu.dst.chan = i;
630 } else {
631 alu.inst = ctx->inst_info->r600_opcode;
632 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
633 alu.src[j] = r600_src[j];
634 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
635 }
636 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
637 if (r)
638 return r;
639 }
640 /* handle some special cases */
641 switch (ctx->inst_info->tgsi_opcode) {
642 case TGSI_OPCODE_SUB:
643 alu.src[1].neg = 1;
644 break;
645 case TGSI_OPCODE_ABS:
646 alu.src[0].abs = 1;
647 break;
648 default:
649 break;
650 }
651 if (i == 3) {
652 alu.last = 1;
653 }
654 r = r600_bc_add_alu(ctx->bc, &alu);
655 if (r)
656 return r;
657 }
658 return 0;
659 }
660
661 static int tgsi_kill(struct r600_shader_ctx *ctx)
662 {
663 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
664 struct r600_bc_alu alu;
665 int i, r;
666
667 for (i = 0; i < 4; i++) {
668 memset(&alu, 0, sizeof(struct r600_bc_alu));
669 alu.inst = ctx->inst_info->r600_opcode;
670 alu.dst.chan = i;
671 alu.src[0].sel = 248;
672 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
673 if (r)
674 return r;
675 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
676 if (i == 3) {
677 alu.last = 1;
678 }
679 r = r600_bc_add_alu(ctx->bc, &alu);
680 if (r)
681 return r;
682 }
683 return 0;
684 }
685
686 static int tgsi_slt(struct r600_shader_ctx *ctx)
687 {
688 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
689 struct r600_bc_alu_src r600_src[3];
690 struct r600_bc_alu alu;
691 int i, r;
692
693 r = tgsi_split_constant(ctx, r600_src);
694 if (r)
695 return r;
696 for (i = 0; i < 4; i++) {
697 memset(&alu, 0, sizeof(struct r600_bc_alu));
698 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
699 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
700 alu.dst.chan = i;
701 } else {
702 alu.inst = ctx->inst_info->r600_opcode;
703 alu.src[1] = r600_src[0];
704 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
705 alu.src[0] = r600_src[1];
706 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
707 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
708 if (r)
709 return r;
710 }
711 if (i == 3) {
712 alu.last = 1;
713 }
714 r = r600_bc_add_alu(ctx->bc, &alu);
715 if (r)
716 return r;
717 }
718 return 0;
719 }
720
721 static int tgsi_lit(struct r600_shader_ctx *ctx)
722 {
723 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
724 struct r600_bc_alu alu;
725 int r;
726
727 /* dst.x, <- 1.0 */
728 memset(&alu, 0, sizeof(struct r600_bc_alu));
729 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
730 alu.src[0].sel = 249; /*1.0*/
731 alu.src[0].chan = 0;
732 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
733 if (r)
734 return r;
735 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
736 r = r600_bc_add_alu(ctx->bc, &alu);
737 if (r)
738 return r;
739
740 /* dst.y = max(src.x, 0.0) */
741 memset(&alu, 0, sizeof(struct r600_bc_alu));
742 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX;
743 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
744 if (r)
745 return r;
746 alu.src[1].sel = 248; /*0.0*/
747 alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
748 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
749 if (r)
750 return r;
751 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
752 r = r600_bc_add_alu(ctx->bc, &alu);
753 if (r)
754 return r;
755
756 /* dst.z = NOP - fill Z slot */
757 memset(&alu, 0, sizeof(struct r600_bc_alu));
758 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
759 alu.dst.chan = 2;
760 r = r600_bc_add_alu(ctx->bc, &alu);
761 if (r)
762 return r;
763
764 /* dst.w, <- 1.0 */
765 memset(&alu, 0, sizeof(struct r600_bc_alu));
766 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
767 alu.src[0].sel = 249;
768 alu.src[0].chan = 0;
769 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
770 if (r)
771 return r;
772 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
773 alu.last = 1;
774 r = r600_bc_add_alu(ctx->bc, &alu);
775 if (r)
776 return r;
777
778 if (inst->Dst[0].Register.WriteMask & (1 << 2))
779 {
780 int chan;
781 int sel;
782
783 /* dst.z = log(src.y) */
784 memset(&alu, 0, sizeof(struct r600_bc_alu));
785 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED;
786 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
787 if (r)
788 return r;
789 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
790 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
791 if (r)
792 return r;
793 alu.last = 1;
794 r = r600_bc_add_alu(ctx->bc, &alu);
795 if (r)
796 return r;
797
798 chan = alu.dst.chan;
799 sel = alu.dst.sel;
800
801 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
802 memset(&alu, 0, sizeof(struct r600_bc_alu));
803 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
804 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
805 if (r)
806 return r;
807 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
808 alu.src[1].sel = sel;
809 alu.src[1].chan = chan;
810 r = tgsi_src(ctx, &inst->Src[0], &alu.src[2]);
811 if (r)
812 return r;
813 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
814 alu.dst.sel = ctx->temp_reg;
815 alu.dst.chan = 0;
816 alu.dst.write = 1;
817 alu.is_op3 = 1;
818 alu.last = 1;
819 r = r600_bc_add_alu(ctx->bc, &alu);
820 if (r)
821 return r;
822
823 /* dst.z = exp(tmp.x) */
824 memset(&alu, 0, sizeof(struct r600_bc_alu));
825 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
826 alu.src[0].sel = ctx->temp_reg;
827 alu.src[0].chan = 0;
828 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
829 if (r)
830 return r;
831 alu.last = 1;
832 r = r600_bc_add_alu(ctx->bc, &alu);
833 if (r)
834 return r;
835 }
836 return 0;
837 }
838
839 static int tgsi_trans(struct r600_shader_ctx *ctx)
840 {
841 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
842 struct r600_bc_alu alu;
843 int i, j, r;
844
845 for (i = 0; i < 4; i++) {
846 memset(&alu, 0, sizeof(struct r600_bc_alu));
847 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
848 alu.inst = ctx->inst_info->r600_opcode;
849 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
850 r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
851 if (r)
852 return r;
853 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
854 }
855 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
856 if (r)
857 return r;
858 alu.last = 1;
859 r = r600_bc_add_alu(ctx->bc, &alu);
860 if (r)
861 return r;
862 }
863 }
864 return 0;
865 }
866
867 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
868 {
869 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
870 struct r600_bc_alu alu;
871 int i, j, r;
872
873 memset(&alu, 0, sizeof(struct r600_bc_alu));
874 alu.inst = ctx->inst_info->r600_opcode;
875 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
876 r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
877 if (r)
878 return r;
879 alu.src[j].chan = tgsi_chan(&inst->Src[j], 0);
880 }
881 alu.dst.sel = ctx->temp_reg;
882 alu.dst.write = 1;
883 alu.last = 1;
884 r = r600_bc_add_alu(ctx->bc, &alu);
885 if (r)
886 return r;
887 /* replicate result */
888 for (i = 0; i < 4; i++) {
889 memset(&alu, 0, sizeof(struct r600_bc_alu));
890 alu.src[0].sel = ctx->temp_reg;
891 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
892 alu.dst.chan = i;
893 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
894 if (r)
895 return r;
896 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
897 if (i == 3)
898 alu.last = 1;
899 r = r600_bc_add_alu(ctx->bc, &alu);
900 if (r)
901 return r;
902 }
903 return 0;
904 }
905
906 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
907 {
908 struct r600_bc_alu alu;
909 int i, r;
910
911 r = r600_bc_add_literal(ctx->bc, ctx->value);
912 if (r)
913 return r;
914 for (i = 0; i < 4; i++) {
915 memset(&alu, 0, sizeof(struct r600_bc_alu));
916 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
917 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
918 alu.dst.chan = i;
919 } else {
920 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
921 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
922 if (r)
923 return r;
924 alu.src[0].sel = ctx->temp_reg;
925 alu.src[0].chan = i;
926 }
927 if (i == 3) {
928 alu.last = 1;
929 }
930 r = r600_bc_add_alu(ctx->bc, &alu);
931 if (r)
932 return r;
933 }
934 return 0;
935 }
936
937 static int tgsi_op3(struct r600_shader_ctx *ctx)
938 {
939 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
940 struct r600_bc_alu_src r600_src[3];
941 struct r600_bc_alu alu;
942 int i, j, r;
943
944 r = tgsi_split_constant(ctx, r600_src);
945 if (r)
946 return r;
947 /* do it in 2 step as op3 doesn't support writemask */
948 for (i = 0; i < 4; i++) {
949 memset(&alu, 0, sizeof(struct r600_bc_alu));
950 alu.inst = ctx->inst_info->r600_opcode;
951 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
952 alu.src[j] = r600_src[j];
953 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
954 }
955 alu.dst.sel = ctx->temp_reg;
956 alu.dst.chan = i;
957 alu.dst.write = 1;
958 alu.is_op3 = 1;
959 if (i == 3) {
960 alu.last = 1;
961 }
962 r = r600_bc_add_alu(ctx->bc, &alu);
963 if (r)
964 return r;
965 }
966 return tgsi_helper_copy(ctx, inst);
967 }
968
969 static int tgsi_dp(struct r600_shader_ctx *ctx)
970 {
971 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
972 struct r600_bc_alu_src r600_src[3];
973 struct r600_bc_alu alu;
974 int i, j, r;
975
976 r = tgsi_split_constant(ctx, r600_src);
977 if (r)
978 return r;
979 for (i = 0; i < 4; i++) {
980 memset(&alu, 0, sizeof(struct r600_bc_alu));
981 alu.inst = ctx->inst_info->r600_opcode;
982 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
983 alu.src[j] = r600_src[j];
984 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
985 }
986 alu.dst.sel = ctx->temp_reg;
987 alu.dst.chan = i;
988 alu.dst.write = 1;
989 /* handle some special cases */
990 switch (ctx->inst_info->tgsi_opcode) {
991 case TGSI_OPCODE_DP2:
992 if (i > 1) {
993 alu.src[0].sel = alu.src[1].sel = 248;
994 alu.src[0].chan = alu.src[1].chan = 0;
995 }
996 break;
997 case TGSI_OPCODE_DP3:
998 if (i > 2) {
999 alu.src[0].sel = alu.src[1].sel = 248;
1000 alu.src[0].chan = alu.src[1].chan = 0;
1001 }
1002 break;
1003 default:
1004 break;
1005 }
1006 if (i == 3) {
1007 alu.last = 1;
1008 }
1009 r = r600_bc_add_alu(ctx->bc, &alu);
1010 if (r)
1011 return r;
1012 }
1013 return tgsi_helper_copy(ctx, inst);
1014 }
1015
1016 static int tgsi_tex(struct r600_shader_ctx *ctx)
1017 {
1018 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1019 struct r600_bc_tex tex;
1020 struct r600_bc_alu alu;
1021 unsigned src_gpr;
1022 int r;
1023
1024 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1025
1026 /* Add perspective divide */
1027 memset(&alu, 0, sizeof(struct r600_bc_alu));
1028 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
1029 alu.src[0].sel = src_gpr;
1030 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1031 alu.dst.sel = ctx->temp_reg;
1032 alu.dst.chan = 3;
1033 alu.last = 1;
1034 alu.dst.write = 1;
1035 r = r600_bc_add_alu(ctx->bc, &alu);
1036 if (r)
1037 return r;
1038
1039 memset(&alu, 0, sizeof(struct r600_bc_alu));
1040 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1041 alu.src[0].sel = ctx->temp_reg;
1042 alu.src[0].chan = 3;
1043 alu.src[1].sel = src_gpr;
1044 alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
1045 alu.dst.sel = ctx->temp_reg;
1046 alu.dst.chan = 0;
1047 alu.dst.write = 1;
1048 r = r600_bc_add_alu(ctx->bc, &alu);
1049 if (r)
1050 return r;
1051 memset(&alu, 0, sizeof(struct r600_bc_alu));
1052 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1053 alu.src[0].sel = ctx->temp_reg;
1054 alu.src[0].chan = 3;
1055 alu.src[1].sel = src_gpr;
1056 alu.src[1].chan = tgsi_chan(&inst->Src[0], 1);
1057 alu.dst.sel = ctx->temp_reg;
1058 alu.dst.chan = 1;
1059 alu.dst.write = 1;
1060 r = r600_bc_add_alu(ctx->bc, &alu);
1061 if (r)
1062 return r;
1063 memset(&alu, 0, sizeof(struct r600_bc_alu));
1064 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1065 alu.src[0].sel = ctx->temp_reg;
1066 alu.src[0].chan = 3;
1067 alu.src[1].sel = src_gpr;
1068 alu.src[1].chan = tgsi_chan(&inst->Src[0], 2);
1069 alu.dst.sel = ctx->temp_reg;
1070 alu.dst.chan = 2;
1071 alu.dst.write = 1;
1072 r = r600_bc_add_alu(ctx->bc, &alu);
1073 if (r)
1074 return r;
1075 memset(&alu, 0, sizeof(struct r600_bc_alu));
1076 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1077 alu.src[0].sel = 249;
1078 alu.src[0].chan = 0;
1079 alu.dst.sel = ctx->temp_reg;
1080 alu.dst.chan = 3;
1081 alu.last = 1;
1082 alu.dst.write = 1;
1083 r = r600_bc_add_alu(ctx->bc, &alu);
1084 if (r)
1085 return r;
1086 src_gpr = ctx->temp_reg;
1087
1088 /* TODO use temp if src_gpr is not a temporary reg (File != TEMPORARY) */
1089 memset(&tex, 0, sizeof(struct r600_bc_tex));
1090 tex.inst = ctx->inst_info->r600_opcode;
1091 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1092 tex.sampler_id = tex.resource_id;
1093 tex.src_gpr = src_gpr;
1094 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1095 tex.dst_sel_x = 0;
1096 tex.dst_sel_y = 1;
1097 tex.dst_sel_z = 2;
1098 tex.dst_sel_w = 3;
1099 tex.src_sel_x = 0;
1100 tex.src_sel_y = 1;
1101 tex.src_sel_z = 2;
1102 tex.src_sel_w = 3;
1103
1104 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1105 tex.coord_type_x = 1;
1106 tex.coord_type_y = 1;
1107 tex.coord_type_z = 1;
1108 tex.coord_type_w = 1;
1109 }
1110 return r600_bc_add_tex(ctx->bc, &tex);
1111 }
1112
1113 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1114 {
1115 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1116 struct r600_bc_alu_src r600_src[3];
1117 struct r600_bc_alu alu;
1118 unsigned i;
1119 int r;
1120
1121 r = tgsi_split_constant(ctx, r600_src);
1122 if (r)
1123 return r;
1124 /* 1 - src0 */
1125 for (i = 0; i < 4; i++) {
1126 memset(&alu, 0, sizeof(struct r600_bc_alu));
1127 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD;
1128 alu.src[0].sel = 249;
1129 alu.src[0].chan = 0;
1130 alu.src[1] = r600_src[0];
1131 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1132 alu.src[1].neg = 1;
1133 alu.dst.sel = ctx->temp_reg;
1134 alu.dst.chan = i;
1135 if (i == 3) {
1136 alu.last = 1;
1137 }
1138 alu.dst.write = 1;
1139 r = r600_bc_add_alu(ctx->bc, &alu);
1140 if (r)
1141 return r;
1142 }
1143 r = r600_bc_add_literal(ctx->bc, ctx->value);
1144 if (r)
1145 return r;
1146
1147 /* (1 - src0) * src2 */
1148 for (i = 0; i < 4; i++) {
1149 memset(&alu, 0, sizeof(struct r600_bc_alu));
1150 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1151 alu.src[0].sel = ctx->temp_reg;
1152 alu.src[0].chan = i;
1153 alu.src[1] = r600_src[2];
1154 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1155 alu.dst.sel = ctx->temp_reg;
1156 alu.dst.chan = i;
1157 if (i == 3) {
1158 alu.last = 1;
1159 }
1160 alu.dst.write = 1;
1161 r = r600_bc_add_alu(ctx->bc, &alu);
1162 if (r)
1163 return r;
1164 }
1165 r = r600_bc_add_literal(ctx->bc, ctx->value);
1166 if (r)
1167 return r;
1168
1169 /* src0 * src1 + (1 - src0) * src2 */
1170 for (i = 0; i < 4; i++) {
1171 memset(&alu, 0, sizeof(struct r600_bc_alu));
1172 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
1173 alu.is_op3 = 1;
1174 alu.src[0] = r600_src[0];
1175 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1176 alu.src[1] = r600_src[1];
1177 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1178 alu.src[2].sel = ctx->temp_reg;
1179 alu.src[2].chan = i;
1180 alu.dst.sel = ctx->temp_reg;
1181 alu.dst.chan = i;
1182 if (i == 3) {
1183 alu.last = 1;
1184 }
1185 r = r600_bc_add_alu(ctx->bc, &alu);
1186 if (r)
1187 return r;
1188 }
1189 return tgsi_helper_copy(ctx, inst);
1190 }
1191
1192 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
1193 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1194 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
1195 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
1196 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
1197 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
1198 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1199 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1200 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
1201 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
1202 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1203 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1204 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1205 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
1206 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
1207 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_slt},
1208 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1209 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
1210 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
1211 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
1212 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1213 /* gap */
1214 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1215 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1216 /* gap */
1217 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1218 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1219 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1220 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1221 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1222 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1223 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
1224 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1225 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1226 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1227 /* gap */
1228 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1229 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
1230 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1231 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1232 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1233 {TGSI_OPCODE_DDX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1234 {TGSI_OPCODE_DDY, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1235 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* predicated kill */
1236 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1237 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1238 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1239 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1240 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1241 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1242 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1243 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1244 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1245 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1246 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1247 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1248 {TGSI_OPCODE_TEX, 0, 0x10, tgsi_tex},
1249 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1250 {TGSI_OPCODE_TXP, 0, 0x10, tgsi_tex},
1251 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1252 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1253 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1254 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1255 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1256 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1257 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1258 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1259 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1260 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1261 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* SGN */
1262 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1263 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1264 {TGSI_OPCODE_TXB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1265 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1266 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1267 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1268 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1269 {TGSI_OPCODE_BRK, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1270 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1271 /* gap */
1272 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1273 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1274 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1275 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1276 /* gap */
1277 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1278 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1279 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1280 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1281 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1282 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1283 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1284 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1285 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1286 /* gap */
1287 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1288 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1289 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1290 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1291 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1292 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1293 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1294 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1295 {TGSI_OPCODE_CONT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1296 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1297 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1298 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1299 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1300 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1301 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1302 /* gap */
1303 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1304 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1305 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1306 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1307 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1308 /* gap */
1309 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1310 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1311 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1312 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1313 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1314 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1315 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1316 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1317 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
1318 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
1319 /* gap */
1320 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1321 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1322 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1323 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1324 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1325 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1326 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1327 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1328 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1329 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1330 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1331 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1332 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1333 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1334 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1335 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1336 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1337 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1338 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1339 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1340 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1341 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1342 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1343 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1344 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1345 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1346 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1347 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1348 };