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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_info.h"
25 #include "tgsi/tgsi_parse.h"
26 #include "tgsi/tgsi_scan.h"
27 #include "tgsi/tgsi_dump.h"
28 #include "util/u_format.h"
29 #include "r600_pipe.h"
30 #include "r600_asm.h"
31 #include "r600_sq.h"
32 #include "r600_formats.h"
33 #include "r600_opcodes.h"
34 #include "r600d.h"
35 #include <stdio.h>
36 #include <errno.h>
37 #include <byteswap.h>
38
39 /* CAYMAN notes
40 Why CAYMAN got loops for lots of instructions is explained here.
41
42 -These 8xx t-slot only ops are implemented in all vector slots.
43 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
44 These 8xx t-slot only opcodes become vector ops, with all four
45 slots expecting the arguments on sources a and b. Result is
46 broadcast to all channels.
47 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
48 These 8xx t-slot only opcodes become vector ops in the z, y, and
49 x slots.
50 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
51 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
52 SQRT_IEEE/_64
53 SIN/COS
54 The w slot may have an independent co-issued operation, or if the
55 result is required to be in the w slot, the opcode above may be
56 issued in the w slot as well.
57 The compiler must issue the source argument to slots z, y, and x
58 */
59
60 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
61 {
62 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
63 struct r600_shader *rshader = &shader->shader;
64 uint32_t *ptr;
65 int i;
66
67 /* copy new shader */
68 if (shader->bo == NULL) {
69 shader->bo = (struct r600_resource*)
70 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, rshader->bc.ndw * 4);
71 if (shader->bo == NULL) {
72 return -ENOMEM;
73 }
74 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
75 if (R600_BIG_ENDIAN) {
76 for (i = 0; i < rshader->bc.ndw; ++i) {
77 ptr[i] = bswap_32(rshader->bc.bytecode[i]);
78 }
79 } else {
80 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * sizeof(*ptr));
81 }
82 rctx->ws->buffer_unmap(shader->bo->buf);
83 }
84 /* build state */
85 switch (rshader->processor_type) {
86 case TGSI_PROCESSOR_VERTEX:
87 if (rctx->chip_class >= EVERGREEN) {
88 evergreen_pipe_shader_vs(ctx, shader);
89 } else {
90 r600_pipe_shader_vs(ctx, shader);
91 }
92 break;
93 case TGSI_PROCESSOR_FRAGMENT:
94 if (rctx->chip_class >= EVERGREEN) {
95 evergreen_pipe_shader_ps(ctx, shader);
96 } else {
97 r600_pipe_shader_ps(ctx, shader);
98 }
99 break;
100 default:
101 return -EINVAL;
102 }
103 return 0;
104 }
105
106 static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pipe_shader *pipeshader);
107
108 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader)
109 {
110 static int dump_shaders = -1;
111 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
112 int r;
113
114 /* Would like some magic "get_bool_option_once" routine.
115 */
116 if (dump_shaders == -1)
117 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
118
119 if (dump_shaders) {
120 fprintf(stderr, "--------------------------------------------------------------\n");
121 tgsi_dump(shader->tokens, 0);
122
123 if (shader->so.num_outputs) {
124 unsigned i;
125 fprintf(stderr, "STREAMOUT\n");
126 for (i = 0; i < shader->so.num_outputs; i++) {
127 unsigned mask = ((1 << shader->so.output[i].num_components) - 1) <<
128 shader->so.output[i].start_component;
129 fprintf(stderr, " %i: MEM_STREAM0_BUF%i OUT[%i].%s%s%s%s\n", i,
130 shader->so.output[i].output_buffer, shader->so.output[i].register_index,
131 mask & 1 ? "x" : "_",
132 (mask >> 1) & 1 ? "y" : "_",
133 (mask >> 2) & 1 ? "z" : "_",
134 (mask >> 3) & 1 ? "w" : "_");
135 }
136 }
137 }
138 r = r600_shader_from_tgsi(rctx, shader);
139 if (r) {
140 R600_ERR("translation from TGSI failed !\n");
141 return r;
142 }
143 r = r600_bytecode_build(&shader->shader.bc);
144 if (r) {
145 R600_ERR("building bytecode failed !\n");
146 return r;
147 }
148 if (dump_shaders) {
149 r600_bytecode_dump(&shader->shader.bc);
150 fprintf(stderr, "______________________________________________________________\n");
151 }
152 return r600_pipe_shader(ctx, shader);
153 }
154
155 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
156 {
157 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
158 r600_bytecode_clear(&shader->shader.bc);
159
160 memset(&shader->shader,0,sizeof(struct r600_shader));
161 }
162
163 /*
164 * tgsi -> r600 shader
165 */
166 struct r600_shader_tgsi_instruction;
167
168 struct r600_shader_src {
169 unsigned sel;
170 unsigned swizzle[4];
171 unsigned neg;
172 unsigned abs;
173 unsigned rel;
174 uint32_t value[4];
175 };
176
177 struct r600_shader_ctx {
178 struct tgsi_shader_info info;
179 struct tgsi_parse_context parse;
180 const struct tgsi_token *tokens;
181 unsigned type;
182 unsigned file_offset[TGSI_FILE_COUNT];
183 unsigned temp_reg;
184 struct r600_shader_tgsi_instruction *inst_info;
185 struct r600_bytecode *bc;
186 struct r600_shader *shader;
187 struct r600_shader_src src[4];
188 u32 *literals;
189 u32 nliterals;
190 u32 max_driver_temp_used;
191 /* needed for evergreen interpolation */
192 boolean input_centroid;
193 boolean input_linear;
194 boolean input_perspective;
195 int num_interp_gpr;
196 int face_gpr;
197 int colors_used;
198 };
199
200 struct r600_shader_tgsi_instruction {
201 unsigned tgsi_opcode;
202 unsigned is_op3;
203 unsigned r600_opcode;
204 int (*process)(struct r600_shader_ctx *ctx);
205 };
206
207 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
208 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
209
210 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
211 {
212 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
213 int j;
214
215 if (i->Instruction.NumDstRegs > 1) {
216 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
217 return -EINVAL;
218 }
219 if (i->Instruction.Predicate) {
220 R600_ERR("predicate unsupported\n");
221 return -EINVAL;
222 }
223 #if 0
224 if (i->Instruction.Label) {
225 R600_ERR("label unsupported\n");
226 return -EINVAL;
227 }
228 #endif
229 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
230 if (i->Src[j].Register.Dimension) {
231 R600_ERR("unsupported src %d (dimension %d)\n", j,
232 i->Src[j].Register.Dimension);
233 return -EINVAL;
234 }
235 }
236 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
237 if (i->Dst[j].Register.Dimension) {
238 R600_ERR("unsupported dst (dimension)\n");
239 return -EINVAL;
240 }
241 }
242 return 0;
243 }
244
245 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
246 {
247 int i, r;
248 struct r600_bytecode_alu alu;
249 int gpr = 0, base_chan = 0;
250 int ij_index = 0;
251
252 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
253 ij_index = 0;
254 if (ctx->shader->input[input].centroid)
255 ij_index++;
256 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
257 ij_index = 0;
258 /* if we have perspective add one */
259 if (ctx->input_perspective) {
260 ij_index++;
261 /* if we have perspective centroid */
262 if (ctx->input_centroid)
263 ij_index++;
264 }
265 if (ctx->shader->input[input].centroid)
266 ij_index++;
267 }
268
269 /* work out gpr and base_chan from index */
270 gpr = ij_index / 2;
271 base_chan = (2 * (ij_index % 2)) + 1;
272
273 for (i = 0; i < 8; i++) {
274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
275
276 if (i < 4)
277 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
278 else
279 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
280
281 if ((i > 1) && (i < 6)) {
282 alu.dst.sel = ctx->shader->input[input].gpr;
283 alu.dst.write = 1;
284 }
285
286 alu.dst.chan = i % 4;
287
288 alu.src[0].sel = gpr;
289 alu.src[0].chan = (base_chan - (i % 2));
290
291 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
292
293 alu.bank_swizzle_force = SQ_ALU_VEC_210;
294 if ((i % 4) == 3)
295 alu.last = 1;
296 r = r600_bytecode_add_alu(ctx->bc, &alu);
297 if (r)
298 return r;
299 }
300 return 0;
301 }
302
303 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
304 {
305 int i, r;
306 struct r600_bytecode_alu alu;
307
308 for (i = 0; i < 4; i++) {
309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
310
311 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_LOAD_P0;
312
313 alu.dst.sel = ctx->shader->input[input].gpr;
314 alu.dst.write = 1;
315
316 alu.dst.chan = i;
317
318 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
319 alu.src[0].chan = i;
320
321 if (i == 3)
322 alu.last = 1;
323 r = r600_bytecode_add_alu(ctx->bc, &alu);
324 if (r)
325 return r;
326 }
327 return 0;
328 }
329
330 /*
331 * Special export handling in shaders
332 *
333 * shader export ARRAY_BASE for EXPORT_POS:
334 * 60 is position
335 * 61 is misc vector
336 * 62, 63 are clip distance vectors
337 *
338 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
339 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
340 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
341 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
342 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
343 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
344 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
345 * exclusive from render target index)
346 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
347 *
348 *
349 * shader export ARRAY_BASE for EXPORT_PIXEL:
350 * 0-7 CB targets
351 * 61 computed Z vector
352 *
353 * The use of the values exported in the computed Z vector are controlled
354 * by DB_SHADER_CONTROL:
355 * Z_EXPORT_ENABLE - Z as a float in RED
356 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
357 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
358 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
359 * DB_SOURCE_FORMAT - export control restrictions
360 *
361 */
362
363
364 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
365 static int r600_spi_sid(struct r600_shader_io * io)
366 {
367 int index, name = io->name;
368
369 /* These params are handled differently, they don't need
370 * semantic indices, so we'll use 0 for them.
371 */
372 if (name == TGSI_SEMANTIC_POSITION ||
373 name == TGSI_SEMANTIC_PSIZE ||
374 name == TGSI_SEMANTIC_FACE)
375 index = 0;
376 else {
377 if (name == TGSI_SEMANTIC_GENERIC) {
378 /* For generic params simply use sid from tgsi */
379 index = io->sid;
380 } else {
381 /* For non-generic params - pack name and sid into 8 bits */
382 index = 0x80 | (name<<3) | (io->sid);
383 }
384
385 /* Make sure that all really used indices have nonzero value, so
386 * we can just compare it to 0 later instead of comparing the name
387 * with different values to detect special cases. */
388 index++;
389 }
390
391 return index;
392 };
393
394 /* turn input into interpolate on EG */
395 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
396 {
397 int r = 0;
398
399 if (ctx->shader->input[index].spi_sid) {
400 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
401 if (ctx->shader->input[index].interpolate > 0) {
402 r = evergreen_interp_alu(ctx, index);
403 } else {
404 r = evergreen_interp_flat(ctx, index);
405 }
406 }
407 return r;
408 }
409
410 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
411 {
412 struct r600_bytecode_alu alu;
413 int i, r;
414 int gpr_front = ctx->shader->input[front].gpr;
415 int gpr_back = ctx->shader->input[back].gpr;
416
417 for (i = 0; i < 4; i++) {
418 memset(&alu, 0, sizeof(alu));
419 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
420 alu.is_op3 = 1;
421 alu.dst.write = 1;
422 alu.dst.sel = gpr_front;
423 alu.src[0].sel = ctx->face_gpr;
424 alu.src[1].sel = gpr_front;
425 alu.src[2].sel = gpr_back;
426
427 alu.dst.chan = i;
428 alu.src[1].chan = i;
429 alu.src[2].chan = i;
430 alu.last = (i==3);
431
432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
433 return r;
434 }
435
436 return 0;
437 }
438
439 static int tgsi_declaration(struct r600_shader_ctx *ctx)
440 {
441 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
442 unsigned i;
443 int r;
444
445 switch (d->Declaration.File) {
446 case TGSI_FILE_INPUT:
447 i = ctx->shader->ninput++;
448 ctx->shader->input[i].name = d->Semantic.Name;
449 ctx->shader->input[i].sid = d->Semantic.Index;
450 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
451 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
452 ctx->shader->input[i].centroid = d->Declaration.Centroid;
453 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
454 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
455 if (ctx->shader->input[i].name == TGSI_SEMANTIC_FACE)
456 ctx->face_gpr = ctx->shader->input[i].gpr;
457 else if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR)
458 ctx->colors_used++;
459 if (ctx->bc->chip_class >= EVERGREEN) {
460 r = evergreen_interp_input(ctx, i);
461 if (r)
462 return r;
463 }
464 }
465 break;
466 case TGSI_FILE_OUTPUT:
467 i = ctx->shader->noutput++;
468 ctx->shader->output[i].name = d->Semantic.Name;
469 ctx->shader->output[i].sid = d->Semantic.Index;
470 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
471 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
472 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
473 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
474 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
475 switch (d->Semantic.Name) {
476 case TGSI_SEMANTIC_CLIPDIST:
477 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
478 break;
479 case TGSI_SEMANTIC_PSIZE:
480 ctx->shader->vs_out_misc_write = 1;
481 break;
482 }
483 }
484 break;
485 case TGSI_FILE_CONSTANT:
486 case TGSI_FILE_TEMPORARY:
487 case TGSI_FILE_SAMPLER:
488 case TGSI_FILE_ADDRESS:
489 break;
490
491 case TGSI_FILE_SYSTEM_VALUE:
492 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
493 struct r600_bytecode_alu alu;
494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
495
496 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
497 alu.src[0].sel = 0;
498 alu.src[0].chan = 3;
499
500 alu.dst.sel = 0;
501 alu.dst.chan = 3;
502 alu.dst.write = 1;
503 alu.last = 1;
504
505 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
506 return r;
507 break;
508 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
509 break;
510 default:
511 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
512 return -EINVAL;
513 }
514 return 0;
515 }
516
517 static int r600_get_temp(struct r600_shader_ctx *ctx)
518 {
519 return ctx->temp_reg + ctx->max_driver_temp_used++;
520 }
521
522 /*
523 * for evergreen we need to scan the shader to find the number of GPRs we need to
524 * reserve for interpolation.
525 *
526 * we need to know if we are going to emit
527 * any centroid inputs
528 * if perspective and linear are required
529 */
530 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
531 {
532 int i;
533 int num_baryc;
534
535 ctx->input_linear = FALSE;
536 ctx->input_perspective = FALSE;
537 ctx->input_centroid = FALSE;
538 ctx->num_interp_gpr = 1;
539
540 /* any centroid inputs */
541 for (i = 0; i < ctx->info.num_inputs; i++) {
542 /* skip position/face */
543 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
544 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
545 continue;
546 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
547 ctx->input_linear = TRUE;
548 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
549 ctx->input_perspective = TRUE;
550 if (ctx->info.input_centroid[i])
551 ctx->input_centroid = TRUE;
552 }
553
554 num_baryc = 0;
555 /* ignoring sample for now */
556 if (ctx->input_perspective)
557 num_baryc++;
558 if (ctx->input_linear)
559 num_baryc++;
560 if (ctx->input_centroid)
561 num_baryc *= 2;
562
563 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
564
565 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
566 return ctx->num_interp_gpr;
567 }
568
569 static void tgsi_src(struct r600_shader_ctx *ctx,
570 const struct tgsi_full_src_register *tgsi_src,
571 struct r600_shader_src *r600_src)
572 {
573 memset(r600_src, 0, sizeof(*r600_src));
574 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
575 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
576 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
577 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
578 r600_src->neg = tgsi_src->Register.Negate;
579 r600_src->abs = tgsi_src->Register.Absolute;
580
581 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
582 int index;
583 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
584 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
585 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
586
587 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
588 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
589 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
590 return;
591 }
592 index = tgsi_src->Register.Index;
593 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
594 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
595 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
596 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
597 r600_src->swizzle[0] = 3;
598 r600_src->swizzle[1] = 3;
599 r600_src->swizzle[2] = 3;
600 r600_src->swizzle[3] = 3;
601 r600_src->sel = 0;
602 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
603 r600_src->swizzle[0] = 0;
604 r600_src->swizzle[1] = 0;
605 r600_src->swizzle[2] = 0;
606 r600_src->swizzle[3] = 0;
607 r600_src->sel = 0;
608 }
609 } else {
610 if (tgsi_src->Register.Indirect)
611 r600_src->rel = V_SQ_REL_RELATIVE;
612 r600_src->sel = tgsi_src->Register.Index;
613 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
614 }
615 }
616
617 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int offset, unsigned int dst_reg)
618 {
619 struct r600_bytecode_vtx vtx;
620 unsigned int ar_reg;
621 int r;
622
623 if (offset) {
624 struct r600_bytecode_alu alu;
625
626 memset(&alu, 0, sizeof(alu));
627
628 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
629 alu.src[0].sel = ctx->bc->ar_reg;
630
631 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
632 alu.src[1].value = offset;
633
634 alu.dst.sel = dst_reg;
635 alu.dst.write = 1;
636 alu.last = 1;
637
638 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
639 return r;
640
641 ar_reg = dst_reg;
642 } else {
643 ar_reg = ctx->bc->ar_reg;
644 }
645
646 memset(&vtx, 0, sizeof(vtx));
647 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
648 vtx.src_gpr = ar_reg;
649 vtx.mega_fetch_count = 16;
650 vtx.dst_gpr = dst_reg;
651 vtx.dst_sel_x = 0; /* SEL_X */
652 vtx.dst_sel_y = 1; /* SEL_Y */
653 vtx.dst_sel_z = 2; /* SEL_Z */
654 vtx.dst_sel_w = 3; /* SEL_W */
655 vtx.data_format = FMT_32_32_32_32_FLOAT;
656 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
657 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
658 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
659 vtx.endian = r600_endian_swap(32);
660
661 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
662 return r;
663
664 return 0;
665 }
666
667 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
668 {
669 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
670 struct r600_bytecode_alu alu;
671 int i, j, k, nconst, r;
672
673 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
674 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
675 nconst++;
676 }
677 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
678 }
679 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
680 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
681 continue;
682 }
683
684 if (ctx->src[i].rel) {
685 int treg = r600_get_temp(ctx);
686 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].sel - 512, treg)))
687 return r;
688
689 ctx->src[i].sel = treg;
690 ctx->src[i].rel = 0;
691 j--;
692 } else if (j > 0) {
693 int treg = r600_get_temp(ctx);
694 for (k = 0; k < 4; k++) {
695 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
696 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
697 alu.src[0].sel = ctx->src[i].sel;
698 alu.src[0].chan = k;
699 alu.src[0].rel = ctx->src[i].rel;
700 alu.dst.sel = treg;
701 alu.dst.chan = k;
702 alu.dst.write = 1;
703 if (k == 3)
704 alu.last = 1;
705 r = r600_bytecode_add_alu(ctx->bc, &alu);
706 if (r)
707 return r;
708 }
709 ctx->src[i].sel = treg;
710 ctx->src[i].rel =0;
711 j--;
712 }
713 }
714 return 0;
715 }
716
717 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
718 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
719 {
720 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
721 struct r600_bytecode_alu alu;
722 int i, j, k, nliteral, r;
723
724 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
725 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
726 nliteral++;
727 }
728 }
729 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
730 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
731 int treg = r600_get_temp(ctx);
732 for (k = 0; k < 4; k++) {
733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
734 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
735 alu.src[0].sel = ctx->src[i].sel;
736 alu.src[0].chan = k;
737 alu.src[0].value = ctx->src[i].value[k];
738 alu.dst.sel = treg;
739 alu.dst.chan = k;
740 alu.dst.write = 1;
741 if (k == 3)
742 alu.last = 1;
743 r = r600_bytecode_add_alu(ctx->bc, &alu);
744 if (r)
745 return r;
746 }
747 ctx->src[i].sel = treg;
748 j--;
749 }
750 }
751 return 0;
752 }
753
754 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
755 {
756 int i, r, count = ctx->shader->ninput;
757
758 /* additional inputs will be allocated right after the existing inputs,
759 * we won't need them after the color selection, so we don't need to
760 * reserve these gprs for the rest of the shader code and to adjust
761 * output offsets etc. */
762 int gpr = ctx->file_offset[TGSI_FILE_INPUT] +
763 ctx->info.file_max[TGSI_FILE_INPUT] + 1;
764
765 if (ctx->face_gpr == -1) {
766 i = ctx->shader->ninput++;
767 ctx->shader->input[i].name = TGSI_SEMANTIC_FACE;
768 ctx->shader->input[i].spi_sid = 0;
769 ctx->shader->input[i].gpr = gpr++;
770 ctx->face_gpr = ctx->shader->input[i].gpr;
771 }
772
773 for (i = 0; i < count; i++) {
774 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
775 int ni = ctx->shader->ninput++;
776 memcpy(&ctx->shader->input[ni],&ctx->shader->input[i], sizeof(struct r600_shader_io));
777 ctx->shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
778 ctx->shader->input[ni].spi_sid = r600_spi_sid(&ctx->shader->input[ni]);
779 ctx->shader->input[ni].gpr = gpr++;
780
781 if (ctx->bc->chip_class >= EVERGREEN) {
782 r = evergreen_interp_input(ctx, ni);
783 if (r)
784 return r;
785 }
786
787 r = select_twoside_color(ctx, i, ni);
788 if (r)
789 return r;
790 }
791 }
792 return 0;
793 }
794
795 static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pipe_shader *pipeshader)
796 {
797 struct r600_shader *shader = &pipeshader->shader;
798 struct tgsi_token *tokens = pipeshader->tokens;
799 struct pipe_stream_output_info so = pipeshader->so;
800 struct tgsi_full_immediate *immediate;
801 struct tgsi_full_property *property;
802 struct r600_shader_ctx ctx;
803 struct r600_bytecode_output output[32];
804 unsigned output_done, noutput;
805 unsigned opcode;
806 int i, j, r = 0, pos0;
807
808 ctx.bc = &shader->bc;
809 ctx.shader = shader;
810 r600_bytecode_init(ctx.bc, rctx->chip_class, rctx->family);
811 ctx.tokens = tokens;
812 tgsi_scan_shader(tokens, &ctx.info);
813 tgsi_parse_init(&ctx.parse, tokens);
814 ctx.type = ctx.parse.FullHeader.Processor.Processor;
815 shader->processor_type = ctx.type;
816 ctx.bc->type = shader->processor_type;
817
818 ctx.face_gpr = -1;
819 ctx.colors_used = 0;
820
821 shader->two_side = (ctx.type == TGSI_PROCESSOR_FRAGMENT) && rctx->two_side;
822
823 shader->clamp_color = (((ctx.type == TGSI_PROCESSOR_FRAGMENT) && rctx->clamp_fragment_color) ||
824 ((ctx.type == TGSI_PROCESSOR_VERTEX) && rctx->clamp_vertex_color));
825
826 shader->nr_cbufs = rctx->nr_cbufs;
827
828 /* register allocations */
829 /* Values [0,127] correspond to GPR[0..127].
830 * Values [128,159] correspond to constant buffer bank 0
831 * Values [160,191] correspond to constant buffer bank 1
832 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
833 * Values [256,287] correspond to constant buffer bank 2 (EG)
834 * Values [288,319] correspond to constant buffer bank 3 (EG)
835 * Other special values are shown in the list below.
836 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
837 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
838 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
839 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
840 * 248 SQ_ALU_SRC_0: special constant 0.0.
841 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
842 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
843 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
844 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
845 * 253 SQ_ALU_SRC_LITERAL: literal constant.
846 * 254 SQ_ALU_SRC_PV: previous vector result.
847 * 255 SQ_ALU_SRC_PS: previous scalar result.
848 */
849 for (i = 0; i < TGSI_FILE_COUNT; i++) {
850 ctx.file_offset[i] = 0;
851 }
852 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
853 ctx.file_offset[TGSI_FILE_INPUT] = 1;
854 if (ctx.bc->chip_class >= EVERGREEN) {
855 r600_bytecode_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
856 } else {
857 r600_bytecode_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
858 }
859 }
860 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
861 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
862 }
863 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
864 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
865 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
866 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
867
868 /* Outside the GPR range. This will be translated to one of the
869 * kcache banks later. */
870 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
871
872 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
873 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
874 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
875 ctx.temp_reg = ctx.bc->ar_reg + 1;
876
877 ctx.nliterals = 0;
878 ctx.literals = NULL;
879 shader->fs_write_all = FALSE;
880 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
881 tgsi_parse_token(&ctx.parse);
882 switch (ctx.parse.FullToken.Token.Type) {
883 case TGSI_TOKEN_TYPE_IMMEDIATE:
884 immediate = &ctx.parse.FullToken.FullImmediate;
885 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
886 if(ctx.literals == NULL) {
887 r = -ENOMEM;
888 goto out_err;
889 }
890 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
891 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
892 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
893 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
894 ctx.nliterals++;
895 break;
896 case TGSI_TOKEN_TYPE_DECLARATION:
897 r = tgsi_declaration(&ctx);
898 if (r)
899 goto out_err;
900 break;
901 case TGSI_TOKEN_TYPE_INSTRUCTION:
902 break;
903 case TGSI_TOKEN_TYPE_PROPERTY:
904 property = &ctx.parse.FullToken.FullProperty;
905 switch (property->Property.PropertyName) {
906 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
907 if (property->u[0].Data == 1)
908 shader->fs_write_all = TRUE;
909 break;
910 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
911 if (property->u[0].Data == 1)
912 shader->vs_prohibit_ucps = TRUE;
913 break;
914 }
915 break;
916 default:
917 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
918 r = -EINVAL;
919 goto out_err;
920 }
921 }
922
923 if (shader->two_side && ctx.colors_used) {
924 if ((r = process_twoside_color_inputs(&ctx)))
925 return r;
926 }
927
928 tgsi_parse_init(&ctx.parse, tokens);
929 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
930 tgsi_parse_token(&ctx.parse);
931 switch (ctx.parse.FullToken.Token.Type) {
932 case TGSI_TOKEN_TYPE_INSTRUCTION:
933 r = tgsi_is_supported(&ctx);
934 if (r)
935 goto out_err;
936 ctx.max_driver_temp_used = 0;
937 /* reserve first tmp for everyone */
938 r600_get_temp(&ctx);
939
940 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
941 if ((r = tgsi_split_constant(&ctx)))
942 goto out_err;
943 if ((r = tgsi_split_literal_constant(&ctx)))
944 goto out_err;
945 if (ctx.bc->chip_class == CAYMAN)
946 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
947 else if (ctx.bc->chip_class >= EVERGREEN)
948 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
949 else
950 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
951 r = ctx.inst_info->process(&ctx);
952 if (r)
953 goto out_err;
954 break;
955 default:
956 break;
957 }
958 }
959
960 noutput = shader->noutput;
961
962 /* clamp color outputs */
963 if (shader->clamp_color) {
964 for (i = 0; i < noutput; i++) {
965 if (shader->output[i].name == TGSI_SEMANTIC_COLOR ||
966 shader->output[i].name == TGSI_SEMANTIC_BCOLOR) {
967
968 int j;
969 for (j = 0; j < 4; j++) {
970 struct r600_bytecode_alu alu;
971 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
972
973 /* MOV_SAT R, R */
974 alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
975 alu.dst.sel = shader->output[i].gpr;
976 alu.dst.chan = j;
977 alu.dst.write = 1;
978 alu.dst.clamp = 1;
979 alu.src[0].sel = alu.dst.sel;
980 alu.src[0].chan = j;
981
982 if (j == 3) {
983 alu.last = 1;
984 }
985 r = r600_bytecode_add_alu(ctx.bc, &alu);
986 if (r)
987 return r;
988 }
989 }
990 }
991 }
992
993 /* Add stream outputs. */
994 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs) {
995 for (i = 0; i < so.num_outputs; i++) {
996 struct r600_bytecode_output output;
997
998 if (so.output[i].output_buffer >= 4) {
999 R600_ERR("exceeded the max number of stream output buffers, got: %d\n",
1000 so.output[i].output_buffer);
1001 r = -EINVAL;
1002 goto out_err;
1003 }
1004 if (so.output[i].start_component) {
1005 R600_ERR("stream_output - start_component cannot be non-zero\n");
1006 r = -EINVAL;
1007 goto out_err;
1008 }
1009
1010 memset(&output, 0, sizeof(struct r600_bytecode_output));
1011 output.gpr = shader->output[so.output[i].register_index].gpr;
1012 output.elem_size = 0;
1013 output.array_base = so.output[i].dst_offset;
1014 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1015 output.burst_count = 1;
1016 output.barrier = 1;
1017 /* array_size is an upper limit for the burst_count
1018 * with MEM_STREAM instructions */
1019 output.array_size = 0xFFF;
1020 output.comp_mask = (1 << so.output[i].num_components) - 1;
1021 if (ctx.bc->chip_class >= EVERGREEN) {
1022 switch (so.output[i].output_buffer) {
1023 case 0:
1024 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0;
1025 break;
1026 case 1:
1027 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1;
1028 break;
1029 case 2:
1030 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2;
1031 break;
1032 case 3:
1033 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3;
1034 break;
1035 }
1036 } else {
1037 switch (so.output[i].output_buffer) {
1038 case 0:
1039 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0;
1040 break;
1041 case 1:
1042 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1;
1043 break;
1044 case 2:
1045 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2;
1046 break;
1047 case 3:
1048 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3;
1049 break;
1050 }
1051 }
1052 r = r600_bytecode_add_output(ctx.bc, &output);
1053 if (r)
1054 goto out_err;
1055 }
1056 }
1057
1058 /* export output */
1059 j = 0;
1060
1061 for (i = 0, pos0 = 0; i < noutput; i++) {
1062 memset(&output[i+j], 0, sizeof(struct r600_bytecode_output));
1063 output[i + j].gpr = shader->output[i].gpr;
1064 output[i + j].elem_size = 3;
1065 output[i + j].swizzle_x = 0;
1066 output[i + j].swizzle_y = 1;
1067 output[i + j].swizzle_z = 2;
1068 output[i + j].swizzle_w = 3;
1069 output[i + j].burst_count = 1;
1070 output[i + j].barrier = 1;
1071 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1072 output[i + j].array_base = i+j - pos0;
1073 output[i + j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1074 switch (ctx.type) {
1075 case TGSI_PROCESSOR_VERTEX:
1076 switch (shader->output[i].name) {
1077 case TGSI_SEMANTIC_POSITION:
1078 output[i + j].array_base = 60;
1079 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1080 /* position doesn't count in array_base */
1081 pos0++;
1082 break;
1083
1084 case TGSI_SEMANTIC_PSIZE:
1085 output[i + j].array_base = 61;
1086 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1087 /* position doesn't count in array_base */
1088 pos0++;
1089 break;
1090
1091 case TGSI_SEMANTIC_CLIPDIST:
1092 /* array base for enabled OUT_MISC_VEC & CCDIST[0|1]_VEC
1093 * vectors is allocated sequentially, starting from 61 */
1094 output[i + j].array_base = 61 + shader->output[i].sid
1095 /* +1 if OUT_MISC_VEC is enabled */
1096 + shader->vs_out_misc_write
1097 /* -1 if OUT_CCDIST0_VEC is disabled */
1098 - (((shader->clip_dist_write & 0xF) == 0)? 1 : 0);
1099 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1100 j++;
1101 pos0++;
1102 /* duplicate it as PARAM to pass to the pixel shader */
1103 memcpy(&output[i+j], &output[i+j-1], sizeof(struct r600_bytecode_output));
1104 output[i + j].array_base = i+j-pos0;
1105 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1106 break;
1107 }
1108 break;
1109 case TGSI_PROCESSOR_FRAGMENT:
1110 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1111 output[i + j].array_base = shader->output[i].sid;
1112 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1113 if (shader->fs_write_all && (rctx->chip_class >= EVERGREEN)) {
1114 for (j = 1; j < shader->nr_cbufs; j++) {
1115 memset(&output[i + j], 0, sizeof(struct r600_bytecode_output));
1116 output[i + j].gpr = shader->output[i].gpr;
1117 output[i + j].elem_size = 3;
1118 output[i + j].swizzle_x = 0;
1119 output[i + j].swizzle_y = 1;
1120 output[i + j].swizzle_z = 2;
1121 output[i + j].swizzle_w = 3;
1122 output[i + j].burst_count = 1;
1123 output[i + j].barrier = 1;
1124 output[i + j].array_base = shader->output[i].sid + j;
1125 output[i + j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1126 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1127 }
1128 j = shader->nr_cbufs-1;
1129 }
1130 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1131 output[i + j].array_base = 61;
1132 output[i + j].swizzle_x = 2;
1133 output[i + j].swizzle_y = 7;
1134 output[i + j].swizzle_z = output[i + j].swizzle_w = 7;
1135 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1136 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1137 output[i + j].array_base = 61;
1138 output[i + j].swizzle_x = 7;
1139 output[i + j].swizzle_y = 1;
1140 output[i + j].swizzle_z = output[i + j].swizzle_w = 7;
1141 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1142 } else {
1143 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1144 r = -EINVAL;
1145 goto out_err;
1146 }
1147 break;
1148 default:
1149 R600_ERR("unsupported processor type %d\n", ctx.type);
1150 r = -EINVAL;
1151 goto out_err;
1152 }
1153 }
1154 noutput += j;
1155 /* add fake param output for vertex shader if no param is exported */
1156 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1157 for (i = 0, pos0 = 0; i < noutput; i++) {
1158 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
1159 pos0 = 1;
1160 break;
1161 }
1162 }
1163 if (!pos0) {
1164 memset(&output[i], 0, sizeof(struct r600_bytecode_output));
1165 output[i].gpr = 0;
1166 output[i].elem_size = 3;
1167 output[i].swizzle_x = 7;
1168 output[i].swizzle_y = 7;
1169 output[i].swizzle_z = 7;
1170 output[i].swizzle_w = 7;
1171 output[i].burst_count = 1;
1172 output[i].barrier = 1;
1173 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1174 output[i].array_base = 0;
1175 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1176 noutput++;
1177 }
1178 }
1179 /* add fake pixel export */
1180 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
1181 memset(&output[0], 0, sizeof(struct r600_bytecode_output));
1182 output[0].gpr = 0;
1183 output[0].elem_size = 3;
1184 output[0].swizzle_x = 7;
1185 output[0].swizzle_y = 7;
1186 output[0].swizzle_z = 7;
1187 output[0].swizzle_w = 7;
1188 output[0].burst_count = 1;
1189 output[0].barrier = 1;
1190 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1191 output[0].array_base = 0;
1192 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1193 noutput++;
1194 }
1195 /* set export done on last export of each type */
1196 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1197 if (ctx.bc->chip_class < CAYMAN) {
1198 if (i == (noutput - 1)) {
1199 output[i].end_of_program = 1;
1200 }
1201 }
1202 if (!(output_done & (1 << output[i].type))) {
1203 output_done |= (1 << output[i].type);
1204 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
1205 }
1206 }
1207 /* add output to bytecode */
1208 for (i = 0; i < noutput; i++) {
1209 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1210 if (r)
1211 goto out_err;
1212 }
1213 /* add program end */
1214 if (ctx.bc->chip_class == CAYMAN)
1215 cm_bytecode_add_cf_end(ctx.bc);
1216
1217 free(ctx.literals);
1218 tgsi_parse_free(&ctx.parse);
1219 return 0;
1220 out_err:
1221 free(ctx.literals);
1222 tgsi_parse_free(&ctx.parse);
1223 return r;
1224 }
1225
1226 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1227 {
1228 R600_ERR("%s tgsi opcode unsupported\n",
1229 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1230 return -EINVAL;
1231 }
1232
1233 static int tgsi_end(struct r600_shader_ctx *ctx)
1234 {
1235 return 0;
1236 }
1237
1238 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1239 const struct r600_shader_src *shader_src,
1240 unsigned chan)
1241 {
1242 bc_src->sel = shader_src->sel;
1243 bc_src->chan = shader_src->swizzle[chan];
1244 bc_src->neg = shader_src->neg;
1245 bc_src->abs = shader_src->abs;
1246 bc_src->rel = shader_src->rel;
1247 bc_src->value = shader_src->value[bc_src->chan];
1248 }
1249
1250 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1251 {
1252 bc_src->abs = 1;
1253 bc_src->neg = 0;
1254 }
1255
1256 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1257 {
1258 bc_src->neg = !bc_src->neg;
1259 }
1260
1261 static void tgsi_dst(struct r600_shader_ctx *ctx,
1262 const struct tgsi_full_dst_register *tgsi_dst,
1263 unsigned swizzle,
1264 struct r600_bytecode_alu_dst *r600_dst)
1265 {
1266 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1267
1268 r600_dst->sel = tgsi_dst->Register.Index;
1269 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1270 r600_dst->chan = swizzle;
1271 r600_dst->write = 1;
1272 if (tgsi_dst->Register.Indirect)
1273 r600_dst->rel = V_SQ_REL_RELATIVE;
1274 if (inst->Instruction.Saturate) {
1275 r600_dst->clamp = 1;
1276 }
1277 }
1278
1279 static int tgsi_last_instruction(unsigned writemask)
1280 {
1281 int i, lasti = 0;
1282
1283 for (i = 0; i < 4; i++) {
1284 if (writemask & (1 << i)) {
1285 lasti = i;
1286 }
1287 }
1288 return lasti;
1289 }
1290
1291 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1292 {
1293 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1294 struct r600_bytecode_alu alu;
1295 int i, j, r;
1296 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1297
1298 for (i = 0; i < lasti + 1; i++) {
1299 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1300 continue;
1301
1302 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1303 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1304
1305 alu.inst = ctx->inst_info->r600_opcode;
1306 if (!swap) {
1307 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1308 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1309 }
1310 } else {
1311 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1312 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1313 }
1314 /* handle some special cases */
1315 switch (ctx->inst_info->tgsi_opcode) {
1316 case TGSI_OPCODE_SUB:
1317 r600_bytecode_src_toggle_neg(&alu.src[1]);
1318 break;
1319 case TGSI_OPCODE_ABS:
1320 r600_bytecode_src_set_abs(&alu.src[0]);
1321 break;
1322 default:
1323 break;
1324 }
1325 if (i == lasti || trans_only) {
1326 alu.last = 1;
1327 }
1328 r = r600_bytecode_add_alu(ctx->bc, &alu);
1329 if (r)
1330 return r;
1331 }
1332 return 0;
1333 }
1334
1335 static int tgsi_op2(struct r600_shader_ctx *ctx)
1336 {
1337 return tgsi_op2_s(ctx, 0, 0);
1338 }
1339
1340 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1341 {
1342 return tgsi_op2_s(ctx, 1, 0);
1343 }
1344
1345 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1346 {
1347 return tgsi_op2_s(ctx, 0, 1);
1348 }
1349
1350 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1351 {
1352 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1353 struct r600_bytecode_alu alu;
1354 int i, r;
1355 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1356
1357 for (i = 0; i < lasti + 1; i++) {
1358
1359 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1360 continue;
1361 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1362 alu.inst = ctx->inst_info->r600_opcode;
1363
1364 alu.src[0].sel = V_SQ_ALU_SRC_0;
1365
1366 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1367
1368 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1369
1370 if (i == lasti) {
1371 alu.last = 1;
1372 }
1373 r = r600_bytecode_add_alu(ctx->bc, &alu);
1374 if (r)
1375 return r;
1376 }
1377 return 0;
1378
1379 }
1380
1381 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1382 {
1383 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1384 int i, j, r;
1385 struct r600_bytecode_alu alu;
1386 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1387
1388 for (i = 0 ; i < last_slot; i++) {
1389 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1390 alu.inst = ctx->inst_info->r600_opcode;
1391 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1392 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1393 }
1394 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1395 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1396
1397 if (i == last_slot - 1)
1398 alu.last = 1;
1399 r = r600_bytecode_add_alu(ctx->bc, &alu);
1400 if (r)
1401 return r;
1402 }
1403 return 0;
1404 }
1405
1406 /*
1407 * r600 - trunc to -PI..PI range
1408 * r700 - normalize by dividing by 2PI
1409 * see fdo bug 27901
1410 */
1411 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1412 {
1413 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1414 static float double_pi = 3.1415926535 * 2;
1415 static float neg_pi = -3.1415926535;
1416
1417 int r;
1418 struct r600_bytecode_alu alu;
1419
1420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1421 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1422 alu.is_op3 = 1;
1423
1424 alu.dst.chan = 0;
1425 alu.dst.sel = ctx->temp_reg;
1426 alu.dst.write = 1;
1427
1428 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1429
1430 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1431 alu.src[1].chan = 0;
1432 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1433 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1434 alu.src[2].chan = 0;
1435 alu.last = 1;
1436 r = r600_bytecode_add_alu(ctx->bc, &alu);
1437 if (r)
1438 return r;
1439
1440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1441 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1442
1443 alu.dst.chan = 0;
1444 alu.dst.sel = ctx->temp_reg;
1445 alu.dst.write = 1;
1446
1447 alu.src[0].sel = ctx->temp_reg;
1448 alu.src[0].chan = 0;
1449 alu.last = 1;
1450 r = r600_bytecode_add_alu(ctx->bc, &alu);
1451 if (r)
1452 return r;
1453
1454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1455 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1456 alu.is_op3 = 1;
1457
1458 alu.dst.chan = 0;
1459 alu.dst.sel = ctx->temp_reg;
1460 alu.dst.write = 1;
1461
1462 alu.src[0].sel = ctx->temp_reg;
1463 alu.src[0].chan = 0;
1464
1465 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1466 alu.src[1].chan = 0;
1467 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1468 alu.src[2].chan = 0;
1469
1470 if (ctx->bc->chip_class == R600) {
1471 alu.src[1].value = *(uint32_t *)&double_pi;
1472 alu.src[2].value = *(uint32_t *)&neg_pi;
1473 } else {
1474 alu.src[1].sel = V_SQ_ALU_SRC_1;
1475 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1476 alu.src[2].neg = 1;
1477 }
1478
1479 alu.last = 1;
1480 r = r600_bytecode_add_alu(ctx->bc, &alu);
1481 if (r)
1482 return r;
1483 return 0;
1484 }
1485
1486 static int cayman_trig(struct r600_shader_ctx *ctx)
1487 {
1488 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1489 struct r600_bytecode_alu alu;
1490 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1491 int i, r;
1492
1493 r = tgsi_setup_trig(ctx);
1494 if (r)
1495 return r;
1496
1497
1498 for (i = 0; i < last_slot; i++) {
1499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1500 alu.inst = ctx->inst_info->r600_opcode;
1501 alu.dst.chan = i;
1502
1503 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1504 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1505
1506 alu.src[0].sel = ctx->temp_reg;
1507 alu.src[0].chan = 0;
1508 if (i == last_slot - 1)
1509 alu.last = 1;
1510 r = r600_bytecode_add_alu(ctx->bc, &alu);
1511 if (r)
1512 return r;
1513 }
1514 return 0;
1515 }
1516
1517 static int tgsi_trig(struct r600_shader_ctx *ctx)
1518 {
1519 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1520 struct r600_bytecode_alu alu;
1521 int i, r;
1522 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1523
1524 r = tgsi_setup_trig(ctx);
1525 if (r)
1526 return r;
1527
1528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1529 alu.inst = ctx->inst_info->r600_opcode;
1530 alu.dst.chan = 0;
1531 alu.dst.sel = ctx->temp_reg;
1532 alu.dst.write = 1;
1533
1534 alu.src[0].sel = ctx->temp_reg;
1535 alu.src[0].chan = 0;
1536 alu.last = 1;
1537 r = r600_bytecode_add_alu(ctx->bc, &alu);
1538 if (r)
1539 return r;
1540
1541 /* replicate result */
1542 for (i = 0; i < lasti + 1; i++) {
1543 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1544 continue;
1545
1546 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1547 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1548
1549 alu.src[0].sel = ctx->temp_reg;
1550 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1551 if (i == lasti)
1552 alu.last = 1;
1553 r = r600_bytecode_add_alu(ctx->bc, &alu);
1554 if (r)
1555 return r;
1556 }
1557 return 0;
1558 }
1559
1560 static int tgsi_scs(struct r600_shader_ctx *ctx)
1561 {
1562 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1563 struct r600_bytecode_alu alu;
1564 int i, r;
1565
1566 /* We'll only need the trig stuff if we are going to write to the
1567 * X or Y components of the destination vector.
1568 */
1569 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1570 r = tgsi_setup_trig(ctx);
1571 if (r)
1572 return r;
1573 }
1574
1575 /* dst.x = COS */
1576 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1577 if (ctx->bc->chip_class == CAYMAN) {
1578 for (i = 0 ; i < 3; i++) {
1579 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1580 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1581 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1582
1583 if (i == 0)
1584 alu.dst.write = 1;
1585 else
1586 alu.dst.write = 0;
1587 alu.src[0].sel = ctx->temp_reg;
1588 alu.src[0].chan = 0;
1589 if (i == 2)
1590 alu.last = 1;
1591 r = r600_bytecode_add_alu(ctx->bc, &alu);
1592 if (r)
1593 return r;
1594 }
1595 } else {
1596 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1597 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1598 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1599
1600 alu.src[0].sel = ctx->temp_reg;
1601 alu.src[0].chan = 0;
1602 alu.last = 1;
1603 r = r600_bytecode_add_alu(ctx->bc, &alu);
1604 if (r)
1605 return r;
1606 }
1607 }
1608
1609 /* dst.y = SIN */
1610 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1611 if (ctx->bc->chip_class == CAYMAN) {
1612 for (i = 0 ; i < 3; i++) {
1613 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1614 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1615 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1616 if (i == 1)
1617 alu.dst.write = 1;
1618 else
1619 alu.dst.write = 0;
1620 alu.src[0].sel = ctx->temp_reg;
1621 alu.src[0].chan = 0;
1622 if (i == 2)
1623 alu.last = 1;
1624 r = r600_bytecode_add_alu(ctx->bc, &alu);
1625 if (r)
1626 return r;
1627 }
1628 } else {
1629 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1630 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1631 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1632
1633 alu.src[0].sel = ctx->temp_reg;
1634 alu.src[0].chan = 0;
1635 alu.last = 1;
1636 r = r600_bytecode_add_alu(ctx->bc, &alu);
1637 if (r)
1638 return r;
1639 }
1640 }
1641
1642 /* dst.z = 0.0; */
1643 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1644 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1645
1646 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1647
1648 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1649
1650 alu.src[0].sel = V_SQ_ALU_SRC_0;
1651 alu.src[0].chan = 0;
1652
1653 alu.last = 1;
1654
1655 r = r600_bytecode_add_alu(ctx->bc, &alu);
1656 if (r)
1657 return r;
1658 }
1659
1660 /* dst.w = 1.0; */
1661 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1662 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1663
1664 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1665
1666 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1667
1668 alu.src[0].sel = V_SQ_ALU_SRC_1;
1669 alu.src[0].chan = 0;
1670
1671 alu.last = 1;
1672
1673 r = r600_bytecode_add_alu(ctx->bc, &alu);
1674 if (r)
1675 return r;
1676 }
1677
1678 return 0;
1679 }
1680
1681 static int tgsi_kill(struct r600_shader_ctx *ctx)
1682 {
1683 struct r600_bytecode_alu alu;
1684 int i, r;
1685
1686 for (i = 0; i < 4; i++) {
1687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1688 alu.inst = ctx->inst_info->r600_opcode;
1689
1690 alu.dst.chan = i;
1691
1692 alu.src[0].sel = V_SQ_ALU_SRC_0;
1693
1694 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1695 alu.src[1].sel = V_SQ_ALU_SRC_1;
1696 alu.src[1].neg = 1;
1697 } else {
1698 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1699 }
1700 if (i == 3) {
1701 alu.last = 1;
1702 }
1703 r = r600_bytecode_add_alu(ctx->bc, &alu);
1704 if (r)
1705 return r;
1706 }
1707
1708 /* kill must be last in ALU */
1709 ctx->bc->force_add_cf = 1;
1710 ctx->shader->uses_kill = TRUE;
1711 return 0;
1712 }
1713
1714 static int tgsi_lit(struct r600_shader_ctx *ctx)
1715 {
1716 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1717 struct r600_bytecode_alu alu;
1718 int r;
1719
1720 /* tmp.x = max(src.y, 0.0) */
1721 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1722 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1723 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
1724 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1725 alu.src[1].chan = 1;
1726
1727 alu.dst.sel = ctx->temp_reg;
1728 alu.dst.chan = 0;
1729 alu.dst.write = 1;
1730
1731 alu.last = 1;
1732 r = r600_bytecode_add_alu(ctx->bc, &alu);
1733 if (r)
1734 return r;
1735
1736 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1737 {
1738 int chan;
1739 int sel;
1740 int i;
1741
1742 if (ctx->bc->chip_class == CAYMAN) {
1743 for (i = 0; i < 3; i++) {
1744 /* tmp.z = log(tmp.x) */
1745 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1746 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1747 alu.src[0].sel = ctx->temp_reg;
1748 alu.src[0].chan = 0;
1749 alu.dst.sel = ctx->temp_reg;
1750 alu.dst.chan = i;
1751 if (i == 2) {
1752 alu.dst.write = 1;
1753 alu.last = 1;
1754 } else
1755 alu.dst.write = 0;
1756
1757 r = r600_bytecode_add_alu(ctx->bc, &alu);
1758 if (r)
1759 return r;
1760 }
1761 } else {
1762 /* tmp.z = log(tmp.x) */
1763 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1764 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1765 alu.src[0].sel = ctx->temp_reg;
1766 alu.src[0].chan = 0;
1767 alu.dst.sel = ctx->temp_reg;
1768 alu.dst.chan = 2;
1769 alu.dst.write = 1;
1770 alu.last = 1;
1771 r = r600_bytecode_add_alu(ctx->bc, &alu);
1772 if (r)
1773 return r;
1774 }
1775
1776 chan = alu.dst.chan;
1777 sel = alu.dst.sel;
1778
1779 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
1780 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1781 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1782 alu.src[0].sel = sel;
1783 alu.src[0].chan = chan;
1784 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
1785 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
1786 alu.dst.sel = ctx->temp_reg;
1787 alu.dst.chan = 0;
1788 alu.dst.write = 1;
1789 alu.is_op3 = 1;
1790 alu.last = 1;
1791 r = r600_bytecode_add_alu(ctx->bc, &alu);
1792 if (r)
1793 return r;
1794
1795 if (ctx->bc->chip_class == CAYMAN) {
1796 for (i = 0; i < 3; i++) {
1797 /* dst.z = exp(tmp.x) */
1798 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1799 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1800 alu.src[0].sel = ctx->temp_reg;
1801 alu.src[0].chan = 0;
1802 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1803 if (i == 2) {
1804 alu.dst.write = 1;
1805 alu.last = 1;
1806 } else
1807 alu.dst.write = 0;
1808 r = r600_bytecode_add_alu(ctx->bc, &alu);
1809 if (r)
1810 return r;
1811 }
1812 } else {
1813 /* dst.z = exp(tmp.x) */
1814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1815 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1816 alu.src[0].sel = ctx->temp_reg;
1817 alu.src[0].chan = 0;
1818 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1819 alu.last = 1;
1820 r = r600_bytecode_add_alu(ctx->bc, &alu);
1821 if (r)
1822 return r;
1823 }
1824 }
1825
1826 /* dst.x, <- 1.0 */
1827 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1828 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1829 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1830 alu.src[0].chan = 0;
1831 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1832 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1833 r = r600_bytecode_add_alu(ctx->bc, &alu);
1834 if (r)
1835 return r;
1836
1837 /* dst.y = max(src.x, 0.0) */
1838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1839 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1840 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1841 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1842 alu.src[1].chan = 0;
1843 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1844 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1845 r = r600_bytecode_add_alu(ctx->bc, &alu);
1846 if (r)
1847 return r;
1848
1849 /* dst.w, <- 1.0 */
1850 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1851 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1852 alu.src[0].sel = V_SQ_ALU_SRC_1;
1853 alu.src[0].chan = 0;
1854 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1855 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1856 alu.last = 1;
1857 r = r600_bytecode_add_alu(ctx->bc, &alu);
1858 if (r)
1859 return r;
1860
1861 return 0;
1862 }
1863
1864 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1865 {
1866 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1867 struct r600_bytecode_alu alu;
1868 int i, r;
1869
1870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1871
1872 /* FIXME:
1873 * For state trackers other than OpenGL, we'll want to use
1874 * _RECIPSQRT_IEEE instead.
1875 */
1876 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1877
1878 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1879 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
1880 r600_bytecode_src_set_abs(&alu.src[i]);
1881 }
1882 alu.dst.sel = ctx->temp_reg;
1883 alu.dst.write = 1;
1884 alu.last = 1;
1885 r = r600_bytecode_add_alu(ctx->bc, &alu);
1886 if (r)
1887 return r;
1888 /* replicate result */
1889 return tgsi_helper_tempx_replicate(ctx);
1890 }
1891
1892 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1893 {
1894 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1895 struct r600_bytecode_alu alu;
1896 int i, r;
1897
1898 for (i = 0; i < 4; i++) {
1899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1900 alu.src[0].sel = ctx->temp_reg;
1901 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1902 alu.dst.chan = i;
1903 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1904 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1905 if (i == 3)
1906 alu.last = 1;
1907 r = r600_bytecode_add_alu(ctx->bc, &alu);
1908 if (r)
1909 return r;
1910 }
1911 return 0;
1912 }
1913
1914 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1915 {
1916 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1917 struct r600_bytecode_alu alu;
1918 int i, r;
1919
1920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1921 alu.inst = ctx->inst_info->r600_opcode;
1922 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1923 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
1924 }
1925 alu.dst.sel = ctx->temp_reg;
1926 alu.dst.write = 1;
1927 alu.last = 1;
1928 r = r600_bytecode_add_alu(ctx->bc, &alu);
1929 if (r)
1930 return r;
1931 /* replicate result */
1932 return tgsi_helper_tempx_replicate(ctx);
1933 }
1934
1935 static int cayman_pow(struct r600_shader_ctx *ctx)
1936 {
1937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1938 int i, r;
1939 struct r600_bytecode_alu alu;
1940 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1941
1942 for (i = 0; i < 3; i++) {
1943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1944 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1945 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1946 alu.dst.sel = ctx->temp_reg;
1947 alu.dst.chan = i;
1948 alu.dst.write = 1;
1949 if (i == 2)
1950 alu.last = 1;
1951 r = r600_bytecode_add_alu(ctx->bc, &alu);
1952 if (r)
1953 return r;
1954 }
1955
1956 /* b * LOG2(a) */
1957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1958 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1959 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
1960 alu.src[1].sel = ctx->temp_reg;
1961 alu.dst.sel = ctx->temp_reg;
1962 alu.dst.write = 1;
1963 alu.last = 1;
1964 r = r600_bytecode_add_alu(ctx->bc, &alu);
1965 if (r)
1966 return r;
1967
1968 for (i = 0; i < last_slot; i++) {
1969 /* POW(a,b) = EXP2(b * LOG2(a))*/
1970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1971 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1972 alu.src[0].sel = ctx->temp_reg;
1973
1974 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1975 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1976 if (i == last_slot - 1)
1977 alu.last = 1;
1978 r = r600_bytecode_add_alu(ctx->bc, &alu);
1979 if (r)
1980 return r;
1981 }
1982 return 0;
1983 }
1984
1985 static int tgsi_pow(struct r600_shader_ctx *ctx)
1986 {
1987 struct r600_bytecode_alu alu;
1988 int r;
1989
1990 /* LOG2(a) */
1991 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1992 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1993 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1994 alu.dst.sel = ctx->temp_reg;
1995 alu.dst.write = 1;
1996 alu.last = 1;
1997 r = r600_bytecode_add_alu(ctx->bc, &alu);
1998 if (r)
1999 return r;
2000 /* b * LOG2(a) */
2001 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2002 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2003 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2004 alu.src[1].sel = ctx->temp_reg;
2005 alu.dst.sel = ctx->temp_reg;
2006 alu.dst.write = 1;
2007 alu.last = 1;
2008 r = r600_bytecode_add_alu(ctx->bc, &alu);
2009 if (r)
2010 return r;
2011 /* POW(a,b) = EXP2(b * LOG2(a))*/
2012 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2013 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2014 alu.src[0].sel = ctx->temp_reg;
2015 alu.dst.sel = ctx->temp_reg;
2016 alu.dst.write = 1;
2017 alu.last = 1;
2018 r = r600_bytecode_add_alu(ctx->bc, &alu);
2019 if (r)
2020 return r;
2021 return tgsi_helper_tempx_replicate(ctx);
2022 }
2023
2024 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2025 {
2026 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2027 struct r600_bytecode_alu alu;
2028 int i, r;
2029 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2030 int tmp0 = ctx->temp_reg;
2031 int tmp1 = r600_get_temp(ctx);
2032 int tmp2 = r600_get_temp(ctx);
2033
2034 /* Unsigned path:
2035 *
2036 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2037 *
2038 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2039 * 2. tmp0.z = lo (tmp0.x * src2)
2040 * 3. tmp0.w = -tmp0.z
2041 * 4. tmp0.y = hi (tmp0.x * src2)
2042 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2043 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2044 * 7. tmp1.x = tmp0.x - tmp0.w
2045 * 8. tmp1.y = tmp0.x + tmp0.w
2046 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2047 * 10. tmp0.z = hi(tmp0.x * src1) = q
2048 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2049 *
2050 * 12. tmp0.w = src1 - tmp0.y = r
2051 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2052 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2053 *
2054 * if DIV
2055 *
2056 * 15. tmp1.z = tmp0.z + 1 = q + 1
2057 * 16. tmp1.w = tmp0.z - 1 = q - 1
2058 *
2059 * else MOD
2060 *
2061 * 15. tmp1.z = tmp0.w - src2 = r - src2
2062 * 16. tmp1.w = tmp0.w + src2 = r + src2
2063 *
2064 * endif
2065 *
2066 * 17. tmp1.x = tmp1.x & tmp1.y
2067 *
2068 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2069 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2070 *
2071 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2072 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2073 *
2074 * Signed path:
2075 *
2076 * Same as unsigned, using abs values of the operands,
2077 * and fixing the sign of the result in the end.
2078 */
2079
2080 for (i = 0; i < 4; i++) {
2081 if (!(write_mask & (1<<i)))
2082 continue;
2083
2084 if (signed_op) {
2085
2086 /* tmp2.x = -src0 */
2087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2088 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2089
2090 alu.dst.sel = tmp2;
2091 alu.dst.chan = 0;
2092 alu.dst.write = 1;
2093
2094 alu.src[0].sel = V_SQ_ALU_SRC_0;
2095
2096 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2097
2098 alu.last = 1;
2099 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2100 return r;
2101
2102 /* tmp2.y = -src1 */
2103 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2104 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2105
2106 alu.dst.sel = tmp2;
2107 alu.dst.chan = 1;
2108 alu.dst.write = 1;
2109
2110 alu.src[0].sel = V_SQ_ALU_SRC_0;
2111
2112 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2113
2114 alu.last = 1;
2115 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2116 return r;
2117
2118 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2119 /* it will be a sign of the quotient */
2120 if (!mod) {
2121
2122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2123 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT);
2124
2125 alu.dst.sel = tmp2;
2126 alu.dst.chan = 2;
2127 alu.dst.write = 1;
2128
2129 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2130 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2131
2132 alu.last = 1;
2133 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2134 return r;
2135 }
2136
2137 /* tmp2.x = |src0| */
2138 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2139 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2140 alu.is_op3 = 1;
2141
2142 alu.dst.sel = tmp2;
2143 alu.dst.chan = 0;
2144 alu.dst.write = 1;
2145
2146 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2147 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2148 alu.src[2].sel = tmp2;
2149 alu.src[2].chan = 0;
2150
2151 alu.last = 1;
2152 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2153 return r;
2154
2155 /* tmp2.y = |src1| */
2156 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2157 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2158 alu.is_op3 = 1;
2159
2160 alu.dst.sel = tmp2;
2161 alu.dst.chan = 1;
2162 alu.dst.write = 1;
2163
2164 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2165 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2166 alu.src[2].sel = tmp2;
2167 alu.src[2].chan = 1;
2168
2169 alu.last = 1;
2170 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2171 return r;
2172
2173 }
2174
2175 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2176 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2177 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT);
2178
2179 alu.dst.sel = tmp0;
2180 alu.dst.chan = 0;
2181 alu.dst.write = 1;
2182
2183 if (signed_op) {
2184 alu.src[0].sel = tmp2;
2185 alu.src[0].chan = 1;
2186 } else {
2187 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2188 }
2189
2190 alu.last = 1;
2191 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2192 return r;
2193
2194 /* 2. tmp0.z = lo (tmp0.x * src2) */
2195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2196 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
2197
2198 alu.dst.sel = tmp0;
2199 alu.dst.chan = 2;
2200 alu.dst.write = 1;
2201
2202 alu.src[0].sel = tmp0;
2203 alu.src[0].chan = 0;
2204 if (signed_op) {
2205 alu.src[1].sel = tmp2;
2206 alu.src[1].chan = 1;
2207 } else {
2208 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2209 }
2210
2211 alu.last = 1;
2212 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2213 return r;
2214
2215 /* 3. tmp0.w = -tmp0.z */
2216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2217 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2218
2219 alu.dst.sel = tmp0;
2220 alu.dst.chan = 3;
2221 alu.dst.write = 1;
2222
2223 alu.src[0].sel = V_SQ_ALU_SRC_0;
2224 alu.src[1].sel = tmp0;
2225 alu.src[1].chan = 2;
2226
2227 alu.last = 1;
2228 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2229 return r;
2230
2231 /* 4. tmp0.y = hi (tmp0.x * src2) */
2232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2233 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2234
2235 alu.dst.sel = tmp0;
2236 alu.dst.chan = 1;
2237 alu.dst.write = 1;
2238
2239 alu.src[0].sel = tmp0;
2240 alu.src[0].chan = 0;
2241
2242 if (signed_op) {
2243 alu.src[1].sel = tmp2;
2244 alu.src[1].chan = 1;
2245 } else {
2246 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2247 }
2248
2249 alu.last = 1;
2250 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2251 return r;
2252
2253 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2254 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2255 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
2256 alu.is_op3 = 1;
2257
2258 alu.dst.sel = tmp0;
2259 alu.dst.chan = 2;
2260 alu.dst.write = 1;
2261
2262 alu.src[0].sel = tmp0;
2263 alu.src[0].chan = 1;
2264 alu.src[1].sel = tmp0;
2265 alu.src[1].chan = 3;
2266 alu.src[2].sel = tmp0;
2267 alu.src[2].chan = 2;
2268
2269 alu.last = 1;
2270 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2271 return r;
2272
2273 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2275 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2276
2277 alu.dst.sel = tmp0;
2278 alu.dst.chan = 3;
2279 alu.dst.write = 1;
2280
2281 alu.src[0].sel = tmp0;
2282 alu.src[0].chan = 2;
2283
2284 alu.src[1].sel = tmp0;
2285 alu.src[1].chan = 0;
2286
2287 alu.last = 1;
2288 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2289 return r;
2290
2291 /* 7. tmp1.x = tmp0.x - tmp0.w */
2292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2293 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2294
2295 alu.dst.sel = tmp1;
2296 alu.dst.chan = 0;
2297 alu.dst.write = 1;
2298
2299 alu.src[0].sel = tmp0;
2300 alu.src[0].chan = 0;
2301 alu.src[1].sel = tmp0;
2302 alu.src[1].chan = 3;
2303
2304 alu.last = 1;
2305 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2306 return r;
2307
2308 /* 8. tmp1.y = tmp0.x + tmp0.w */
2309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2310 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
2311
2312 alu.dst.sel = tmp1;
2313 alu.dst.chan = 1;
2314 alu.dst.write = 1;
2315
2316 alu.src[0].sel = tmp0;
2317 alu.src[0].chan = 0;
2318 alu.src[1].sel = tmp0;
2319 alu.src[1].chan = 3;
2320
2321 alu.last = 1;
2322 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2323 return r;
2324
2325 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2326 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2327 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
2328 alu.is_op3 = 1;
2329
2330 alu.dst.sel = tmp0;
2331 alu.dst.chan = 0;
2332 alu.dst.write = 1;
2333
2334 alu.src[0].sel = tmp0;
2335 alu.src[0].chan = 1;
2336 alu.src[1].sel = tmp1;
2337 alu.src[1].chan = 1;
2338 alu.src[2].sel = tmp1;
2339 alu.src[2].chan = 0;
2340
2341 alu.last = 1;
2342 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2343 return r;
2344
2345 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2346 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2347 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2348
2349 alu.dst.sel = tmp0;
2350 alu.dst.chan = 2;
2351 alu.dst.write = 1;
2352
2353 alu.src[0].sel = tmp0;
2354 alu.src[0].chan = 0;
2355
2356 if (signed_op) {
2357 alu.src[1].sel = tmp2;
2358 alu.src[1].chan = 0;
2359 } else {
2360 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2361 }
2362
2363 alu.last = 1;
2364 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2365 return r;
2366
2367 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
2368 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2369 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
2370
2371 alu.dst.sel = tmp0;
2372 alu.dst.chan = 1;
2373 alu.dst.write = 1;
2374
2375 if (signed_op) {
2376 alu.src[0].sel = tmp2;
2377 alu.src[0].chan = 1;
2378 } else {
2379 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2380 }
2381
2382 alu.src[1].sel = tmp0;
2383 alu.src[1].chan = 2;
2384
2385 alu.last = 1;
2386 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2387 return r;
2388
2389 /* 12. tmp0.w = src1 - tmp0.y = r */
2390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2391 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2392
2393 alu.dst.sel = tmp0;
2394 alu.dst.chan = 3;
2395 alu.dst.write = 1;
2396
2397 if (signed_op) {
2398 alu.src[0].sel = tmp2;
2399 alu.src[0].chan = 0;
2400 } else {
2401 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2402 }
2403
2404 alu.src[1].sel = tmp0;
2405 alu.src[1].chan = 1;
2406
2407 alu.last = 1;
2408 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2409 return r;
2410
2411 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
2412 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2413 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT);
2414
2415 alu.dst.sel = tmp1;
2416 alu.dst.chan = 0;
2417 alu.dst.write = 1;
2418
2419 alu.src[0].sel = tmp0;
2420 alu.src[0].chan = 3;
2421 if (signed_op) {
2422 alu.src[1].sel = tmp2;
2423 alu.src[1].chan = 1;
2424 } else {
2425 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2426 }
2427
2428 alu.last = 1;
2429 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2430 return r;
2431
2432 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
2433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2434 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT);
2435
2436 alu.dst.sel = tmp1;
2437 alu.dst.chan = 1;
2438 alu.dst.write = 1;
2439
2440 if (signed_op) {
2441 alu.src[0].sel = tmp2;
2442 alu.src[0].chan = 0;
2443 } else {
2444 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2445 }
2446
2447 alu.src[1].sel = tmp0;
2448 alu.src[1].chan = 1;
2449
2450 alu.last = 1;
2451 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2452 return r;
2453
2454 if (mod) { /* UMOD */
2455
2456 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
2457 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2458 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2459
2460 alu.dst.sel = tmp1;
2461 alu.dst.chan = 2;
2462 alu.dst.write = 1;
2463
2464 alu.src[0].sel = tmp0;
2465 alu.src[0].chan = 3;
2466
2467 if (signed_op) {
2468 alu.src[1].sel = tmp2;
2469 alu.src[1].chan = 1;
2470 } else {
2471 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2472 }
2473
2474 alu.last = 1;
2475 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2476 return r;
2477
2478 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
2479 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2480 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
2481
2482 alu.dst.sel = tmp1;
2483 alu.dst.chan = 3;
2484 alu.dst.write = 1;
2485
2486 alu.src[0].sel = tmp0;
2487 alu.src[0].chan = 3;
2488 if (signed_op) {
2489 alu.src[1].sel = tmp2;
2490 alu.src[1].chan = 1;
2491 } else {
2492 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2493 }
2494
2495 alu.last = 1;
2496 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2497 return r;
2498
2499 } else { /* UDIV */
2500
2501 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
2502 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2503 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
2504
2505 alu.dst.sel = tmp1;
2506 alu.dst.chan = 2;
2507 alu.dst.write = 1;
2508
2509 alu.src[0].sel = tmp0;
2510 alu.src[0].chan = 2;
2511 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
2512
2513 alu.last = 1;
2514 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2515 return r;
2516
2517 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
2518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2519 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
2520
2521 alu.dst.sel = tmp1;
2522 alu.dst.chan = 3;
2523 alu.dst.write = 1;
2524
2525 alu.src[0].sel = tmp0;
2526 alu.src[0].chan = 2;
2527 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
2528
2529 alu.last = 1;
2530 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2531 return r;
2532
2533 }
2534
2535 /* 17. tmp1.x = tmp1.x & tmp1.y */
2536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2537 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT);
2538
2539 alu.dst.sel = tmp1;
2540 alu.dst.chan = 0;
2541 alu.dst.write = 1;
2542
2543 alu.src[0].sel = tmp1;
2544 alu.src[0].chan = 0;
2545 alu.src[1].sel = tmp1;
2546 alu.src[1].chan = 1;
2547
2548 alu.last = 1;
2549 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2550 return r;
2551
2552 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
2553 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
2554 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2555 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
2556 alu.is_op3 = 1;
2557
2558 alu.dst.sel = tmp0;
2559 alu.dst.chan = 2;
2560 alu.dst.write = 1;
2561
2562 alu.src[0].sel = tmp1;
2563 alu.src[0].chan = 0;
2564 alu.src[1].sel = tmp0;
2565 alu.src[1].chan = mod ? 3 : 2;
2566 alu.src[2].sel = tmp1;
2567 alu.src[2].chan = 2;
2568
2569 alu.last = 1;
2570 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2571 return r;
2572
2573 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
2574 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2575 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
2576 alu.is_op3 = 1;
2577
2578 if (signed_op) {
2579 alu.dst.sel = tmp0;
2580 alu.dst.chan = 2;
2581 alu.dst.write = 1;
2582 } else {
2583 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2584 }
2585
2586 alu.src[0].sel = tmp1;
2587 alu.src[0].chan = 1;
2588 alu.src[1].sel = tmp1;
2589 alu.src[1].chan = 3;
2590 alu.src[2].sel = tmp0;
2591 alu.src[2].chan = 2;
2592
2593 alu.last = 1;
2594 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2595 return r;
2596
2597 if (signed_op) {
2598
2599 /* fix the sign of the result */
2600
2601 if (mod) {
2602
2603 /* tmp0.x = -tmp0.z */
2604 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2605 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2606
2607 alu.dst.sel = tmp0;
2608 alu.dst.chan = 0;
2609 alu.dst.write = 1;
2610
2611 alu.src[0].sel = V_SQ_ALU_SRC_0;
2612 alu.src[1].sel = tmp0;
2613 alu.src[1].chan = 2;
2614
2615 alu.last = 1;
2616 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2617 return r;
2618
2619 /* sign of the remainder is the same as the sign of src0 */
2620 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
2621 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2622 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2623 alu.is_op3 = 1;
2624
2625 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2626
2627 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2628 alu.src[1].sel = tmp0;
2629 alu.src[1].chan = 2;
2630 alu.src[2].sel = tmp0;
2631 alu.src[2].chan = 0;
2632
2633 alu.last = 1;
2634 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2635 return r;
2636
2637 } else {
2638
2639 /* tmp0.x = -tmp0.z */
2640 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2641 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2642
2643 alu.dst.sel = tmp0;
2644 alu.dst.chan = 0;
2645 alu.dst.write = 1;
2646
2647 alu.src[0].sel = V_SQ_ALU_SRC_0;
2648 alu.src[1].sel = tmp0;
2649 alu.src[1].chan = 2;
2650
2651 alu.last = 1;
2652 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2653 return r;
2654
2655 /* fix the quotient sign (same as the sign of src0*src1) */
2656 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
2657 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2658 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2659 alu.is_op3 = 1;
2660
2661 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2662
2663 alu.src[0].sel = tmp2;
2664 alu.src[0].chan = 2;
2665 alu.src[1].sel = tmp0;
2666 alu.src[1].chan = 2;
2667 alu.src[2].sel = tmp0;
2668 alu.src[2].chan = 0;
2669
2670 alu.last = 1;
2671 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2672 return r;
2673 }
2674 }
2675 }
2676 return 0;
2677 }
2678
2679 static int tgsi_udiv(struct r600_shader_ctx *ctx)
2680 {
2681 return tgsi_divmod(ctx, 0, 0);
2682 }
2683
2684 static int tgsi_umod(struct r600_shader_ctx *ctx)
2685 {
2686 return tgsi_divmod(ctx, 1, 0);
2687 }
2688
2689 static int tgsi_idiv(struct r600_shader_ctx *ctx)
2690 {
2691 return tgsi_divmod(ctx, 0, 1);
2692 }
2693
2694 static int tgsi_imod(struct r600_shader_ctx *ctx)
2695 {
2696 return tgsi_divmod(ctx, 1, 1);
2697 }
2698
2699
2700 static int tgsi_f2i(struct r600_shader_ctx *ctx)
2701 {
2702 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2703 struct r600_bytecode_alu alu;
2704 int i, r;
2705 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2706 int last_inst = tgsi_last_instruction(write_mask);
2707
2708 for (i = 0; i < 4; i++) {
2709 if (!(write_mask & (1<<i)))
2710 continue;
2711
2712 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2713 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC);
2714
2715 alu.dst.sel = ctx->temp_reg;
2716 alu.dst.chan = i;
2717 alu.dst.write = 1;
2718
2719 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2720 if (i == last_inst)
2721 alu.last = 1;
2722 r = r600_bytecode_add_alu(ctx->bc, &alu);
2723 if (r)
2724 return r;
2725 }
2726
2727 for (i = 0; i < 4; i++) {
2728 if (!(write_mask & (1<<i)))
2729 continue;
2730
2731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2732 alu.inst = ctx->inst_info->r600_opcode;
2733
2734 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2735
2736 alu.src[0].sel = ctx->temp_reg;
2737 alu.src[0].chan = i;
2738
2739 if (i == last_inst)
2740 alu.last = 1;
2741 r = r600_bytecode_add_alu(ctx->bc, &alu);
2742 if (r)
2743 return r;
2744 }
2745
2746 return 0;
2747 }
2748
2749 static int tgsi_iabs(struct r600_shader_ctx *ctx)
2750 {
2751 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2752 struct r600_bytecode_alu alu;
2753 int i, r;
2754 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2755 int last_inst = tgsi_last_instruction(write_mask);
2756
2757 /* tmp = -src */
2758 for (i = 0; i < 4; i++) {
2759 if (!(write_mask & (1<<i)))
2760 continue;
2761
2762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2763 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2764
2765 alu.dst.sel = ctx->temp_reg;
2766 alu.dst.chan = i;
2767 alu.dst.write = 1;
2768
2769 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2770 alu.src[0].sel = V_SQ_ALU_SRC_0;
2771
2772 if (i == last_inst)
2773 alu.last = 1;
2774 r = r600_bytecode_add_alu(ctx->bc, &alu);
2775 if (r)
2776 return r;
2777 }
2778
2779 /* dst = (src >= 0 ? src : tmp) */
2780 for (i = 0; i < 4; i++) {
2781 if (!(write_mask & (1<<i)))
2782 continue;
2783
2784 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2785 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2786 alu.is_op3 = 1;
2787 alu.dst.write = 1;
2788
2789 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2790
2791 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2792 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2793 alu.src[2].sel = ctx->temp_reg;
2794 alu.src[2].chan = i;
2795
2796 if (i == last_inst)
2797 alu.last = 1;
2798 r = r600_bytecode_add_alu(ctx->bc, &alu);
2799 if (r)
2800 return r;
2801 }
2802 return 0;
2803 }
2804
2805 static int tgsi_issg(struct r600_shader_ctx *ctx)
2806 {
2807 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2808 struct r600_bytecode_alu alu;
2809 int i, r;
2810 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2811 int last_inst = tgsi_last_instruction(write_mask);
2812
2813 /* tmp = (src >= 0 ? src : -1) */
2814 for (i = 0; i < 4; i++) {
2815 if (!(write_mask & (1<<i)))
2816 continue;
2817
2818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2819 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2820 alu.is_op3 = 1;
2821
2822 alu.dst.sel = ctx->temp_reg;
2823 alu.dst.chan = i;
2824 alu.dst.write = 1;
2825
2826 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2827 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2828 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
2829
2830 if (i == last_inst)
2831 alu.last = 1;
2832 r = r600_bytecode_add_alu(ctx->bc, &alu);
2833 if (r)
2834 return r;
2835 }
2836
2837 /* dst = (tmp > 0 ? 1 : tmp) */
2838 for (i = 0; i < 4; i++) {
2839 if (!(write_mask & (1<<i)))
2840 continue;
2841
2842 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2843 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT);
2844 alu.is_op3 = 1;
2845 alu.dst.write = 1;
2846
2847 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2848
2849 alu.src[0].sel = ctx->temp_reg;
2850 alu.src[0].chan = i;
2851
2852 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
2853
2854 alu.src[2].sel = ctx->temp_reg;
2855 alu.src[2].chan = i;
2856
2857 if (i == last_inst)
2858 alu.last = 1;
2859 r = r600_bytecode_add_alu(ctx->bc, &alu);
2860 if (r)
2861 return r;
2862 }
2863 return 0;
2864 }
2865
2866
2867
2868 static int tgsi_ssg(struct r600_shader_ctx *ctx)
2869 {
2870 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2871 struct r600_bytecode_alu alu;
2872 int i, r;
2873
2874 /* tmp = (src > 0 ? 1 : src) */
2875 for (i = 0; i < 4; i++) {
2876 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2877 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
2878 alu.is_op3 = 1;
2879
2880 alu.dst.sel = ctx->temp_reg;
2881 alu.dst.chan = i;
2882
2883 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2884 alu.src[1].sel = V_SQ_ALU_SRC_1;
2885 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
2886
2887 if (i == 3)
2888 alu.last = 1;
2889 r = r600_bytecode_add_alu(ctx->bc, &alu);
2890 if (r)
2891 return r;
2892 }
2893
2894 /* dst = (-tmp > 0 ? -1 : tmp) */
2895 for (i = 0; i < 4; i++) {
2896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2897 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
2898 alu.is_op3 = 1;
2899 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2900
2901 alu.src[0].sel = ctx->temp_reg;
2902 alu.src[0].chan = i;
2903 alu.src[0].neg = 1;
2904
2905 alu.src[1].sel = V_SQ_ALU_SRC_1;
2906 alu.src[1].neg = 1;
2907
2908 alu.src[2].sel = ctx->temp_reg;
2909 alu.src[2].chan = i;
2910
2911 if (i == 3)
2912 alu.last = 1;
2913 r = r600_bytecode_add_alu(ctx->bc, &alu);
2914 if (r)
2915 return r;
2916 }
2917 return 0;
2918 }
2919
2920 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
2921 {
2922 struct r600_bytecode_alu alu;
2923 int i, r;
2924
2925 for (i = 0; i < 4; i++) {
2926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2927 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
2928 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
2929 alu.dst.chan = i;
2930 } else {
2931 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2932 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2933 alu.src[0].sel = ctx->temp_reg;
2934 alu.src[0].chan = i;
2935 }
2936 if (i == 3) {
2937 alu.last = 1;
2938 }
2939 r = r600_bytecode_add_alu(ctx->bc, &alu);
2940 if (r)
2941 return r;
2942 }
2943 return 0;
2944 }
2945
2946 static int tgsi_op3(struct r600_shader_ctx *ctx)
2947 {
2948 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2949 struct r600_bytecode_alu alu;
2950 int i, j, r;
2951 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2952
2953 for (i = 0; i < lasti + 1; i++) {
2954 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2955 continue;
2956
2957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2958 alu.inst = ctx->inst_info->r600_opcode;
2959 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2960 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2961 }
2962
2963 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2964 alu.dst.chan = i;
2965 alu.dst.write = 1;
2966 alu.is_op3 = 1;
2967 if (i == lasti) {
2968 alu.last = 1;
2969 }
2970 r = r600_bytecode_add_alu(ctx->bc, &alu);
2971 if (r)
2972 return r;
2973 }
2974 return 0;
2975 }
2976
2977 static int tgsi_dp(struct r600_shader_ctx *ctx)
2978 {
2979 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2980 struct r600_bytecode_alu alu;
2981 int i, j, r;
2982
2983 for (i = 0; i < 4; i++) {
2984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2985 alu.inst = ctx->inst_info->r600_opcode;
2986 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2987 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2988 }
2989
2990 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2991 alu.dst.chan = i;
2992 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2993 /* handle some special cases */
2994 switch (ctx->inst_info->tgsi_opcode) {
2995 case TGSI_OPCODE_DP2:
2996 if (i > 1) {
2997 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
2998 alu.src[0].chan = alu.src[1].chan = 0;
2999 }
3000 break;
3001 case TGSI_OPCODE_DP3:
3002 if (i > 2) {
3003 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3004 alu.src[0].chan = alu.src[1].chan = 0;
3005 }
3006 break;
3007 case TGSI_OPCODE_DPH:
3008 if (i == 3) {
3009 alu.src[0].sel = V_SQ_ALU_SRC_1;
3010 alu.src[0].chan = 0;
3011 alu.src[0].neg = 0;
3012 }
3013 break;
3014 default:
3015 break;
3016 }
3017 if (i == 3) {
3018 alu.last = 1;
3019 }
3020 r = r600_bytecode_add_alu(ctx->bc, &alu);
3021 if (r)
3022 return r;
3023 }
3024 return 0;
3025 }
3026
3027 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3028 unsigned index)
3029 {
3030 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3031 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3032 inst->Src[index].Register.File != TGSI_FILE_INPUT) ||
3033 ctx->src[index].neg || ctx->src[index].abs;
3034 }
3035
3036 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3037 unsigned index)
3038 {
3039 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3040 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3041 }
3042
3043 static int tgsi_tex(struct r600_shader_ctx *ctx)
3044 {
3045 static float one_point_five = 1.5f;
3046 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3047 struct r600_bytecode_tex tex;
3048 struct r600_bytecode_alu alu;
3049 unsigned src_gpr;
3050 int r, i, j;
3051 int opcode;
3052 /* Texture fetch instructions can only use gprs as source.
3053 * Also they cannot negate the source or take the absolute value */
3054 const boolean src_requires_loading = tgsi_tex_src_requires_loading(ctx, 0);
3055 boolean src_loaded = FALSE;
3056 unsigned sampler_src_reg = 1;
3057 u8 offset_x = 0, offset_y = 0, offset_z = 0;
3058
3059 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3060
3061 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3062 /* get offset values */
3063 if (inst->Texture.NumOffsets) {
3064 assert(inst->Texture.NumOffsets == 1);
3065
3066 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
3067 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
3068 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
3069 }
3070 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3071 /* TGSI moves the sampler to src reg 3 for TXD */
3072 sampler_src_reg = 3;
3073
3074 for (i = 1; i < 3; i++) {
3075 /* set gradients h/v */
3076 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3077 tex.inst = (i == 1) ? SQ_TEX_INST_SET_GRADIENTS_H :
3078 SQ_TEX_INST_SET_GRADIENTS_V;
3079 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3080 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3081
3082 if (tgsi_tex_src_requires_loading(ctx, i)) {
3083 tex.src_gpr = r600_get_temp(ctx);
3084 tex.src_sel_x = 0;
3085 tex.src_sel_y = 1;
3086 tex.src_sel_z = 2;
3087 tex.src_sel_w = 3;
3088
3089 for (j = 0; j < 4; j++) {
3090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3091 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3092 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
3093 alu.dst.sel = tex.src_gpr;
3094 alu.dst.chan = j;
3095 if (j == 3)
3096 alu.last = 1;
3097 alu.dst.write = 1;
3098 r = r600_bytecode_add_alu(ctx->bc, &alu);
3099 if (r)
3100 return r;
3101 }
3102
3103 } else {
3104 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
3105 tex.src_sel_x = ctx->src[i].swizzle[0];
3106 tex.src_sel_y = ctx->src[i].swizzle[1];
3107 tex.src_sel_z = ctx->src[i].swizzle[2];
3108 tex.src_sel_w = ctx->src[i].swizzle[3];
3109 tex.src_rel = ctx->src[i].rel;
3110 }
3111 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
3112 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
3113 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
3114 tex.coord_type_x = 1;
3115 tex.coord_type_y = 1;
3116 tex.coord_type_z = 1;
3117 tex.coord_type_w = 1;
3118 }
3119 r = r600_bytecode_add_tex(ctx->bc, &tex);
3120 if (r)
3121 return r;
3122 }
3123 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3124 int out_chan;
3125 /* Add perspective divide */
3126 if (ctx->bc->chip_class == CAYMAN) {
3127 out_chan = 2;
3128 for (i = 0; i < 3; i++) {
3129 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3130 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3131 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3132
3133 alu.dst.sel = ctx->temp_reg;
3134 alu.dst.chan = i;
3135 if (i == 2)
3136 alu.last = 1;
3137 if (out_chan == i)
3138 alu.dst.write = 1;
3139 r = r600_bytecode_add_alu(ctx->bc, &alu);
3140 if (r)
3141 return r;
3142 }
3143
3144 } else {
3145 out_chan = 3;
3146 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3147 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3148 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3149
3150 alu.dst.sel = ctx->temp_reg;
3151 alu.dst.chan = out_chan;
3152 alu.last = 1;
3153 alu.dst.write = 1;
3154 r = r600_bytecode_add_alu(ctx->bc, &alu);
3155 if (r)
3156 return r;
3157 }
3158
3159 for (i = 0; i < 3; i++) {
3160 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3161 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3162 alu.src[0].sel = ctx->temp_reg;
3163 alu.src[0].chan = out_chan;
3164 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3165 alu.dst.sel = ctx->temp_reg;
3166 alu.dst.chan = i;
3167 alu.dst.write = 1;
3168 r = r600_bytecode_add_alu(ctx->bc, &alu);
3169 if (r)
3170 return r;
3171 }
3172 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3173 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3174 alu.src[0].sel = V_SQ_ALU_SRC_1;
3175 alu.src[0].chan = 0;
3176 alu.dst.sel = ctx->temp_reg;
3177 alu.dst.chan = 3;
3178 alu.last = 1;
3179 alu.dst.write = 1;
3180 r = r600_bytecode_add_alu(ctx->bc, &alu);
3181 if (r)
3182 return r;
3183 src_loaded = TRUE;
3184 src_gpr = ctx->temp_reg;
3185 }
3186
3187 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
3188 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
3189 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
3190
3191 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3192 for (i = 0; i < 4; i++) {
3193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3194 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
3195 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3196 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
3197 alu.dst.sel = ctx->temp_reg;
3198 alu.dst.chan = i;
3199 if (i == 3)
3200 alu.last = 1;
3201 alu.dst.write = 1;
3202 r = r600_bytecode_add_alu(ctx->bc, &alu);
3203 if (r)
3204 return r;
3205 }
3206
3207 /* tmp1.z = RCP_e(|tmp1.z|) */
3208 if (ctx->bc->chip_class == CAYMAN) {
3209 for (i = 0; i < 3; i++) {
3210 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3211 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3212 alu.src[0].sel = ctx->temp_reg;
3213 alu.src[0].chan = 2;
3214 alu.src[0].abs = 1;
3215 alu.dst.sel = ctx->temp_reg;
3216 alu.dst.chan = i;
3217 if (i == 2)
3218 alu.dst.write = 1;
3219 if (i == 2)
3220 alu.last = 1;
3221 r = r600_bytecode_add_alu(ctx->bc, &alu);
3222 if (r)
3223 return r;
3224 }
3225 } else {
3226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3227 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3228 alu.src[0].sel = ctx->temp_reg;
3229 alu.src[0].chan = 2;
3230 alu.src[0].abs = 1;
3231 alu.dst.sel = ctx->temp_reg;
3232 alu.dst.chan = 2;
3233 alu.dst.write = 1;
3234 alu.last = 1;
3235 r = r600_bytecode_add_alu(ctx->bc, &alu);
3236 if (r)
3237 return r;
3238 }
3239
3240 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
3241 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
3242 * muladd has no writemask, have to use another temp
3243 */
3244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3245 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
3246 alu.is_op3 = 1;
3247
3248 alu.src[0].sel = ctx->temp_reg;
3249 alu.src[0].chan = 0;
3250 alu.src[1].sel = ctx->temp_reg;
3251 alu.src[1].chan = 2;
3252
3253 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3254 alu.src[2].chan = 0;
3255 alu.src[2].value = *(uint32_t *)&one_point_five;
3256
3257 alu.dst.sel = ctx->temp_reg;
3258 alu.dst.chan = 0;
3259 alu.dst.write = 1;
3260
3261 r = r600_bytecode_add_alu(ctx->bc, &alu);
3262 if (r)
3263 return r;
3264
3265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3266 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
3267 alu.is_op3 = 1;
3268
3269 alu.src[0].sel = ctx->temp_reg;
3270 alu.src[0].chan = 1;
3271 alu.src[1].sel = ctx->temp_reg;
3272 alu.src[1].chan = 2;
3273
3274 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3275 alu.src[2].chan = 0;
3276 alu.src[2].value = *(uint32_t *)&one_point_five;
3277
3278 alu.dst.sel = ctx->temp_reg;
3279 alu.dst.chan = 1;
3280 alu.dst.write = 1;
3281
3282 alu.last = 1;
3283 r = r600_bytecode_add_alu(ctx->bc, &alu);
3284 if (r)
3285 return r;
3286
3287 src_loaded = TRUE;
3288 src_gpr = ctx->temp_reg;
3289 }
3290
3291 if (src_requires_loading && !src_loaded) {
3292 for (i = 0; i < 4; i++) {
3293 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3294 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3295 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3296 alu.dst.sel = ctx->temp_reg;
3297 alu.dst.chan = i;
3298 if (i == 3)
3299 alu.last = 1;
3300 alu.dst.write = 1;
3301 r = r600_bytecode_add_alu(ctx->bc, &alu);
3302 if (r)
3303 return r;
3304 }
3305 src_loaded = TRUE;
3306 src_gpr = ctx->temp_reg;
3307 }
3308
3309 opcode = ctx->inst_info->r600_opcode;
3310 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
3311 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
3312 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
3313 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3314 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) {
3315 switch (opcode) {
3316 case SQ_TEX_INST_SAMPLE:
3317 opcode = SQ_TEX_INST_SAMPLE_C;
3318 break;
3319 case SQ_TEX_INST_SAMPLE_L:
3320 opcode = SQ_TEX_INST_SAMPLE_C_L;
3321 break;
3322 case SQ_TEX_INST_SAMPLE_LB:
3323 opcode = SQ_TEX_INST_SAMPLE_C_LB;
3324 break;
3325 case SQ_TEX_INST_SAMPLE_G:
3326 opcode = SQ_TEX_INST_SAMPLE_C_G;
3327 break;
3328 }
3329 }
3330
3331 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3332 tex.inst = opcode;
3333
3334 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3335 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3336 tex.src_gpr = src_gpr;
3337 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3338 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
3339 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
3340 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
3341 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
3342 if (src_loaded) {
3343 tex.src_sel_x = 0;
3344 tex.src_sel_y = 1;
3345 tex.src_sel_z = 2;
3346 tex.src_sel_w = 3;
3347 } else {
3348 tex.src_sel_x = ctx->src[0].swizzle[0];
3349 tex.src_sel_y = ctx->src[0].swizzle[1];
3350 tex.src_sel_z = ctx->src[0].swizzle[2];
3351 tex.src_sel_w = ctx->src[0].swizzle[3];
3352 tex.src_rel = ctx->src[0].rel;
3353 }
3354
3355 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
3356 tex.src_sel_x = 1;
3357 tex.src_sel_y = 0;
3358 tex.src_sel_z = 3;
3359 tex.src_sel_w = 1;
3360 }
3361
3362 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
3363 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
3364 tex.coord_type_x = 1;
3365 tex.coord_type_y = 1;
3366 }
3367 tex.coord_type_z = 1;
3368 tex.coord_type_w = 1;
3369
3370 tex.offset_x = offset_x;
3371 tex.offset_y = offset_y;
3372 tex.offset_z = offset_z;
3373
3374 /* Put the depth for comparison in W.
3375 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
3376 * Some instructions expect the depth in Z. */
3377 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
3378 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
3379 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
3380 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
3381 opcode != SQ_TEX_INST_SAMPLE_C_L &&
3382 opcode != SQ_TEX_INST_SAMPLE_C_LB) {
3383 tex.src_sel_w = tex.src_sel_z;
3384 }
3385
3386 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
3387 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
3388 if (opcode == SQ_TEX_INST_SAMPLE_C_L ||
3389 opcode == SQ_TEX_INST_SAMPLE_C_LB) {
3390 /* the array index is read from Y */
3391 tex.coord_type_y = 0;
3392 } else {
3393 /* the array index is read from Z */
3394 tex.coord_type_z = 0;
3395 tex.src_sel_z = tex.src_sel_y;
3396 }
3397 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
3398 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)
3399 /* the array index is read from Z */
3400 tex.coord_type_z = 0;
3401
3402 r = r600_bytecode_add_tex(ctx->bc, &tex);
3403 if (r)
3404 return r;
3405
3406 /* add shadow ambient support - gallium doesn't do it yet */
3407 return 0;
3408 }
3409
3410 static int tgsi_lrp(struct r600_shader_ctx *ctx)
3411 {
3412 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3413 struct r600_bytecode_alu alu;
3414 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3415 unsigned i;
3416 int r;
3417
3418 /* optimize if it's just an equal balance */
3419 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
3420 for (i = 0; i < lasti + 1; i++) {
3421 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3422 continue;
3423
3424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3425 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
3426 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3427 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
3428 alu.omod = 3;
3429 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3430 alu.dst.chan = i;
3431 if (i == lasti) {
3432 alu.last = 1;
3433 }
3434 r = r600_bytecode_add_alu(ctx->bc, &alu);
3435 if (r)
3436 return r;
3437 }
3438 return 0;
3439 }
3440
3441 /* 1 - src0 */
3442 for (i = 0; i < lasti + 1; i++) {
3443 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3444 continue;
3445
3446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3447 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
3448 alu.src[0].sel = V_SQ_ALU_SRC_1;
3449 alu.src[0].chan = 0;
3450 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3451 r600_bytecode_src_toggle_neg(&alu.src[1]);
3452 alu.dst.sel = ctx->temp_reg;
3453 alu.dst.chan = i;
3454 if (i == lasti) {
3455 alu.last = 1;
3456 }
3457 alu.dst.write = 1;
3458 r = r600_bytecode_add_alu(ctx->bc, &alu);
3459 if (r)
3460 return r;
3461 }
3462
3463 /* (1 - src0) * src2 */
3464 for (i = 0; i < lasti + 1; i++) {
3465 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3466 continue;
3467
3468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3469 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3470 alu.src[0].sel = ctx->temp_reg;
3471 alu.src[0].chan = i;
3472 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
3473 alu.dst.sel = ctx->temp_reg;
3474 alu.dst.chan = i;
3475 if (i == lasti) {
3476 alu.last = 1;
3477 }
3478 alu.dst.write = 1;
3479 r = r600_bytecode_add_alu(ctx->bc, &alu);
3480 if (r)
3481 return r;
3482 }
3483
3484 /* src0 * src1 + (1 - src0) * src2 */
3485 for (i = 0; i < lasti + 1; i++) {
3486 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3487 continue;
3488
3489 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3490 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
3491 alu.is_op3 = 1;
3492 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3493 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3494 alu.src[2].sel = ctx->temp_reg;
3495 alu.src[2].chan = i;
3496
3497 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3498 alu.dst.chan = i;
3499 if (i == lasti) {
3500 alu.last = 1;
3501 }
3502 r = r600_bytecode_add_alu(ctx->bc, &alu);
3503 if (r)
3504 return r;
3505 }
3506 return 0;
3507 }
3508
3509 static int tgsi_cmp(struct r600_shader_ctx *ctx)
3510 {
3511 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3512 struct r600_bytecode_alu alu;
3513 int i, r;
3514 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3515
3516 for (i = 0; i < lasti + 1; i++) {
3517 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3518 continue;
3519
3520 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3521 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
3522 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3523 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
3524 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
3525 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3526 alu.dst.chan = i;
3527 alu.dst.write = 1;
3528 alu.is_op3 = 1;
3529 if (i == lasti)
3530 alu.last = 1;
3531 r = r600_bytecode_add_alu(ctx->bc, &alu);
3532 if (r)
3533 return r;
3534 }
3535 return 0;
3536 }
3537
3538 static int tgsi_xpd(struct r600_shader_ctx *ctx)
3539 {
3540 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3541 static const unsigned int src0_swizzle[] = {2, 0, 1};
3542 static const unsigned int src1_swizzle[] = {1, 2, 0};
3543 struct r600_bytecode_alu alu;
3544 uint32_t use_temp = 0;
3545 int i, r;
3546
3547 if (inst->Dst[0].Register.WriteMask != 0xf)
3548 use_temp = 1;
3549
3550 for (i = 0; i < 4; i++) {
3551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3552 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3553 if (i < 3) {
3554 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3555 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
3556 } else {
3557 alu.src[0].sel = V_SQ_ALU_SRC_0;
3558 alu.src[0].chan = i;
3559 alu.src[1].sel = V_SQ_ALU_SRC_0;
3560 alu.src[1].chan = i;
3561 }
3562
3563 alu.dst.sel = ctx->temp_reg;
3564 alu.dst.chan = i;
3565 alu.dst.write = 1;
3566
3567 if (i == 3)
3568 alu.last = 1;
3569 r = r600_bytecode_add_alu(ctx->bc, &alu);
3570 if (r)
3571 return r;
3572 }
3573
3574 for (i = 0; i < 4; i++) {
3575 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3576 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
3577
3578 if (i < 3) {
3579 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
3580 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
3581 } else {
3582 alu.src[0].sel = V_SQ_ALU_SRC_0;
3583 alu.src[0].chan = i;
3584 alu.src[1].sel = V_SQ_ALU_SRC_0;
3585 alu.src[1].chan = i;
3586 }
3587
3588 alu.src[2].sel = ctx->temp_reg;
3589 alu.src[2].neg = 1;
3590 alu.src[2].chan = i;
3591
3592 if (use_temp)
3593 alu.dst.sel = ctx->temp_reg;
3594 else
3595 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3596 alu.dst.chan = i;
3597 alu.dst.write = 1;
3598 alu.is_op3 = 1;
3599 if (i == 3)
3600 alu.last = 1;
3601 r = r600_bytecode_add_alu(ctx->bc, &alu);
3602 if (r)
3603 return r;
3604 }
3605 if (use_temp)
3606 return tgsi_helper_copy(ctx, inst);
3607 return 0;
3608 }
3609
3610 static int tgsi_exp(struct r600_shader_ctx *ctx)
3611 {
3612 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3613 struct r600_bytecode_alu alu;
3614 int r;
3615 int i;
3616
3617 /* result.x = 2^floor(src); */
3618 if (inst->Dst[0].Register.WriteMask & 1) {
3619 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3620
3621 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
3622 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3623
3624 alu.dst.sel = ctx->temp_reg;
3625 alu.dst.chan = 0;
3626 alu.dst.write = 1;
3627 alu.last = 1;
3628 r = r600_bytecode_add_alu(ctx->bc, &alu);
3629 if (r)
3630 return r;
3631
3632 if (ctx->bc->chip_class == CAYMAN) {
3633 for (i = 0; i < 3; i++) {
3634 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3635 alu.src[0].sel = ctx->temp_reg;
3636 alu.src[0].chan = 0;
3637
3638 alu.dst.sel = ctx->temp_reg;
3639 alu.dst.chan = i;
3640 if (i == 0)
3641 alu.dst.write = 1;
3642 if (i == 2)
3643 alu.last = 1;
3644 r = r600_bytecode_add_alu(ctx->bc, &alu);
3645 if (r)
3646 return r;
3647 }
3648 } else {
3649 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3650 alu.src[0].sel = ctx->temp_reg;
3651 alu.src[0].chan = 0;
3652
3653 alu.dst.sel = ctx->temp_reg;
3654 alu.dst.chan = 0;
3655 alu.dst.write = 1;
3656 alu.last = 1;
3657 r = r600_bytecode_add_alu(ctx->bc, &alu);
3658 if (r)
3659 return r;
3660 }
3661 }
3662
3663 /* result.y = tmp - floor(tmp); */
3664 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
3665 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3666
3667 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
3668 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3669
3670 alu.dst.sel = ctx->temp_reg;
3671 #if 0
3672 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3673 if (r)
3674 return r;
3675 #endif
3676 alu.dst.write = 1;
3677 alu.dst.chan = 1;
3678
3679 alu.last = 1;
3680
3681 r = r600_bytecode_add_alu(ctx->bc, &alu);
3682 if (r)
3683 return r;
3684 }
3685
3686 /* result.z = RoughApprox2ToX(tmp);*/
3687 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
3688 if (ctx->bc->chip_class == CAYMAN) {
3689 for (i = 0; i < 3; i++) {
3690 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3691 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3692 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3693
3694 alu.dst.sel = ctx->temp_reg;
3695 alu.dst.chan = i;
3696 if (i == 2) {
3697 alu.dst.write = 1;
3698 alu.last = 1;
3699 }
3700
3701 r = r600_bytecode_add_alu(ctx->bc, &alu);
3702 if (r)
3703 return r;
3704 }
3705 } else {
3706 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3707 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3708 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3709
3710 alu.dst.sel = ctx->temp_reg;
3711 alu.dst.write = 1;
3712 alu.dst.chan = 2;
3713
3714 alu.last = 1;
3715
3716 r = r600_bytecode_add_alu(ctx->bc, &alu);
3717 if (r)
3718 return r;
3719 }
3720 }
3721
3722 /* result.w = 1.0;*/
3723 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
3724 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3725
3726 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3727 alu.src[0].sel = V_SQ_ALU_SRC_1;
3728 alu.src[0].chan = 0;
3729
3730 alu.dst.sel = ctx->temp_reg;
3731 alu.dst.chan = 3;
3732 alu.dst.write = 1;
3733 alu.last = 1;
3734 r = r600_bytecode_add_alu(ctx->bc, &alu);
3735 if (r)
3736 return r;
3737 }
3738 return tgsi_helper_copy(ctx, inst);
3739 }
3740
3741 static int tgsi_log(struct r600_shader_ctx *ctx)
3742 {
3743 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3744 struct r600_bytecode_alu alu;
3745 int r;
3746 int i;
3747
3748 /* result.x = floor(log2(|src|)); */
3749 if (inst->Dst[0].Register.WriteMask & 1) {
3750 if (ctx->bc->chip_class == CAYMAN) {
3751 for (i = 0; i < 3; i++) {
3752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3753
3754 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3755 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3756 r600_bytecode_src_set_abs(&alu.src[0]);
3757
3758 alu.dst.sel = ctx->temp_reg;
3759 alu.dst.chan = i;
3760 if (i == 0)
3761 alu.dst.write = 1;
3762 if (i == 2)
3763 alu.last = 1;
3764 r = r600_bytecode_add_alu(ctx->bc, &alu);
3765 if (r)
3766 return r;
3767 }
3768
3769 } else {
3770 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3771
3772 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3773 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3774 r600_bytecode_src_set_abs(&alu.src[0]);
3775
3776 alu.dst.sel = ctx->temp_reg;
3777 alu.dst.chan = 0;
3778 alu.dst.write = 1;
3779 alu.last = 1;
3780 r = r600_bytecode_add_alu(ctx->bc, &alu);
3781 if (r)
3782 return r;
3783 }
3784
3785 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
3786 alu.src[0].sel = ctx->temp_reg;
3787 alu.src[0].chan = 0;
3788
3789 alu.dst.sel = ctx->temp_reg;
3790 alu.dst.chan = 0;
3791 alu.dst.write = 1;
3792 alu.last = 1;
3793
3794 r = r600_bytecode_add_alu(ctx->bc, &alu);
3795 if (r)
3796 return r;
3797 }
3798
3799 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
3800 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
3801
3802 if (ctx->bc->chip_class == CAYMAN) {
3803 for (i = 0; i < 3; i++) {
3804 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3805
3806 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3807 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3808 r600_bytecode_src_set_abs(&alu.src[0]);
3809
3810 alu.dst.sel = ctx->temp_reg;
3811 alu.dst.chan = i;
3812 if (i == 1)
3813 alu.dst.write = 1;
3814 if (i == 2)
3815 alu.last = 1;
3816
3817 r = r600_bytecode_add_alu(ctx->bc, &alu);
3818 if (r)
3819 return r;
3820 }
3821 } else {
3822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3823
3824 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3825 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3826 r600_bytecode_src_set_abs(&alu.src[0]);
3827
3828 alu.dst.sel = ctx->temp_reg;
3829 alu.dst.chan = 1;
3830 alu.dst.write = 1;
3831 alu.last = 1;
3832
3833 r = r600_bytecode_add_alu(ctx->bc, &alu);
3834 if (r)
3835 return r;
3836 }
3837
3838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3839
3840 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
3841 alu.src[0].sel = ctx->temp_reg;
3842 alu.src[0].chan = 1;
3843
3844 alu.dst.sel = ctx->temp_reg;
3845 alu.dst.chan = 1;
3846 alu.dst.write = 1;
3847 alu.last = 1;
3848
3849 r = r600_bytecode_add_alu(ctx->bc, &alu);
3850 if (r)
3851 return r;
3852
3853 if (ctx->bc->chip_class == CAYMAN) {
3854 for (i = 0; i < 3; i++) {
3855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3856 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3857 alu.src[0].sel = ctx->temp_reg;
3858 alu.src[0].chan = 1;
3859
3860 alu.dst.sel = ctx->temp_reg;
3861 alu.dst.chan = i;
3862 if (i == 1)
3863 alu.dst.write = 1;
3864 if (i == 2)
3865 alu.last = 1;
3866
3867 r = r600_bytecode_add_alu(ctx->bc, &alu);
3868 if (r)
3869 return r;
3870 }
3871 } else {
3872 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3873 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3874 alu.src[0].sel = ctx->temp_reg;
3875 alu.src[0].chan = 1;
3876
3877 alu.dst.sel = ctx->temp_reg;
3878 alu.dst.chan = 1;
3879 alu.dst.write = 1;
3880 alu.last = 1;
3881
3882 r = r600_bytecode_add_alu(ctx->bc, &alu);
3883 if (r)
3884 return r;
3885 }
3886
3887 if (ctx->bc->chip_class == CAYMAN) {
3888 for (i = 0; i < 3; i++) {
3889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3890 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3891 alu.src[0].sel = ctx->temp_reg;
3892 alu.src[0].chan = 1;
3893
3894 alu.dst.sel = ctx->temp_reg;
3895 alu.dst.chan = i;
3896 if (i == 1)
3897 alu.dst.write = 1;
3898 if (i == 2)
3899 alu.last = 1;
3900
3901 r = r600_bytecode_add_alu(ctx->bc, &alu);
3902 if (r)
3903 return r;
3904 }
3905 } else {
3906 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3907 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3908 alu.src[0].sel = ctx->temp_reg;
3909 alu.src[0].chan = 1;
3910
3911 alu.dst.sel = ctx->temp_reg;
3912 alu.dst.chan = 1;
3913 alu.dst.write = 1;
3914 alu.last = 1;
3915
3916 r = r600_bytecode_add_alu(ctx->bc, &alu);
3917 if (r)
3918 return r;
3919 }
3920
3921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3922
3923 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3924
3925 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3926 r600_bytecode_src_set_abs(&alu.src[0]);
3927
3928 alu.src[1].sel = ctx->temp_reg;
3929 alu.src[1].chan = 1;
3930
3931 alu.dst.sel = ctx->temp_reg;
3932 alu.dst.chan = 1;
3933 alu.dst.write = 1;
3934 alu.last = 1;
3935
3936 r = r600_bytecode_add_alu(ctx->bc, &alu);
3937 if (r)
3938 return r;
3939 }
3940
3941 /* result.z = log2(|src|);*/
3942 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
3943 if (ctx->bc->chip_class == CAYMAN) {
3944 for (i = 0; i < 3; i++) {
3945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3946
3947 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3948 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3949 r600_bytecode_src_set_abs(&alu.src[0]);
3950
3951 alu.dst.sel = ctx->temp_reg;
3952 if (i == 2)
3953 alu.dst.write = 1;
3954 alu.dst.chan = i;
3955 if (i == 2)
3956 alu.last = 1;
3957
3958 r = r600_bytecode_add_alu(ctx->bc, &alu);
3959 if (r)
3960 return r;
3961 }
3962 } else {
3963 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3964
3965 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3966 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3967 r600_bytecode_src_set_abs(&alu.src[0]);
3968
3969 alu.dst.sel = ctx->temp_reg;
3970 alu.dst.write = 1;
3971 alu.dst.chan = 2;
3972 alu.last = 1;
3973
3974 r = r600_bytecode_add_alu(ctx->bc, &alu);
3975 if (r)
3976 return r;
3977 }
3978 }
3979
3980 /* result.w = 1.0; */
3981 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
3982 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3983
3984 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3985 alu.src[0].sel = V_SQ_ALU_SRC_1;
3986 alu.src[0].chan = 0;
3987
3988 alu.dst.sel = ctx->temp_reg;
3989 alu.dst.chan = 3;
3990 alu.dst.write = 1;
3991 alu.last = 1;
3992
3993 r = r600_bytecode_add_alu(ctx->bc, &alu);
3994 if (r)
3995 return r;
3996 }
3997
3998 return tgsi_helper_copy(ctx, inst);
3999 }
4000
4001 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
4002 {
4003 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4004 struct r600_bytecode_alu alu;
4005 int r;
4006
4007 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4008
4009 switch (inst->Instruction.Opcode) {
4010 case TGSI_OPCODE_ARL:
4011 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
4012 break;
4013 case TGSI_OPCODE_ARR:
4014 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
4015 break;
4016 case TGSI_OPCODE_UARL:
4017 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
4018 break;
4019 default:
4020 assert(0);
4021 return -1;
4022 }
4023
4024 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4025 alu.last = 1;
4026 alu.dst.sel = ctx->bc->ar_reg;
4027 alu.dst.write = 1;
4028 r = r600_bytecode_add_alu(ctx->bc, &alu);
4029 if (r)
4030 return r;
4031
4032 ctx->bc->ar_loaded = 0;
4033 return 0;
4034 }
4035 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
4036 {
4037 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4038 struct r600_bytecode_alu alu;
4039 int r;
4040
4041 switch (inst->Instruction.Opcode) {
4042 case TGSI_OPCODE_ARL:
4043 memset(&alu, 0, sizeof(alu));
4044 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
4045 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4046 alu.dst.sel = ctx->bc->ar_reg;
4047 alu.dst.write = 1;
4048 alu.last = 1;
4049
4050 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4051 return r;
4052
4053 memset(&alu, 0, sizeof(alu));
4054 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
4055 alu.src[0].sel = ctx->bc->ar_reg;
4056 alu.dst.sel = ctx->bc->ar_reg;
4057 alu.dst.write = 1;
4058 alu.last = 1;
4059
4060 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4061 return r;
4062 break;
4063 case TGSI_OPCODE_ARR:
4064 memset(&alu, 0, sizeof(alu));
4065 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
4066 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4067 alu.dst.sel = ctx->bc->ar_reg;
4068 alu.dst.write = 1;
4069 alu.last = 1;
4070
4071 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4072 return r;
4073 break;
4074 case TGSI_OPCODE_UARL:
4075 memset(&alu, 0, sizeof(alu));
4076 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
4077 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4078 alu.dst.sel = ctx->bc->ar_reg;
4079 alu.dst.write = 1;
4080 alu.last = 1;
4081
4082 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4083 return r;
4084 break;
4085 default:
4086 assert(0);
4087 return -1;
4088 }
4089
4090 ctx->bc->ar_loaded = 0;
4091 return 0;
4092 }
4093
4094 static int tgsi_opdst(struct r600_shader_ctx *ctx)
4095 {
4096 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4097 struct r600_bytecode_alu alu;
4098 int i, r = 0;
4099
4100 for (i = 0; i < 4; i++) {
4101 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4102
4103 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
4104 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4105
4106 if (i == 0 || i == 3) {
4107 alu.src[0].sel = V_SQ_ALU_SRC_1;
4108 } else {
4109 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4110 }
4111
4112 if (i == 0 || i == 2) {
4113 alu.src[1].sel = V_SQ_ALU_SRC_1;
4114 } else {
4115 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4116 }
4117 if (i == 3)
4118 alu.last = 1;
4119 r = r600_bytecode_add_alu(ctx->bc, &alu);
4120 if (r)
4121 return r;
4122 }
4123 return 0;
4124 }
4125
4126 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
4127 {
4128 struct r600_bytecode_alu alu;
4129 int r;
4130
4131 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4132 alu.inst = opcode;
4133 alu.predicate = 1;
4134
4135 alu.dst.sel = ctx->temp_reg;
4136 alu.dst.write = 1;
4137 alu.dst.chan = 0;
4138
4139 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4140 alu.src[1].sel = V_SQ_ALU_SRC_0;
4141 alu.src[1].chan = 0;
4142
4143 alu.last = 1;
4144
4145 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
4146 if (r)
4147 return r;
4148 return 0;
4149 }
4150
4151 static int pops(struct r600_shader_ctx *ctx, int pops)
4152 {
4153 unsigned force_pop = ctx->bc->force_add_cf;
4154
4155 if (!force_pop) {
4156 int alu_pop = 3;
4157 if (ctx->bc->cf_last) {
4158 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU))
4159 alu_pop = 0;
4160 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER))
4161 alu_pop = 1;
4162 }
4163 alu_pop += pops;
4164 if (alu_pop == 1) {
4165 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER);
4166 ctx->bc->force_add_cf = 1;
4167 } else if (alu_pop == 2) {
4168 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER);
4169 ctx->bc->force_add_cf = 1;
4170 } else {
4171 force_pop = 1;
4172 }
4173 }
4174
4175 if (force_pop) {
4176 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
4177 ctx->bc->cf_last->pop_count = pops;
4178 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
4179 }
4180
4181 return 0;
4182 }
4183
4184 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
4185 {
4186 switch(reason) {
4187 case FC_PUSH_VPM:
4188 ctx->bc->callstack[ctx->bc->call_sp].current--;
4189 break;
4190 case FC_PUSH_WQM:
4191 case FC_LOOP:
4192 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
4193 break;
4194 case FC_REP:
4195 /* TOODO : for 16 vp asic should -= 2; */
4196 ctx->bc->callstack[ctx->bc->call_sp].current --;
4197 break;
4198 }
4199 }
4200
4201 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
4202 {
4203 if (check_max_only) {
4204 int diff;
4205 switch (reason) {
4206 case FC_PUSH_VPM:
4207 diff = 1;
4208 break;
4209 case FC_PUSH_WQM:
4210 diff = 4;
4211 break;
4212 default:
4213 assert(0);
4214 diff = 0;
4215 }
4216 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
4217 ctx->bc->callstack[ctx->bc->call_sp].max) {
4218 ctx->bc->callstack[ctx->bc->call_sp].max =
4219 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
4220 }
4221 return;
4222 }
4223 switch (reason) {
4224 case FC_PUSH_VPM:
4225 ctx->bc->callstack[ctx->bc->call_sp].current++;
4226 break;
4227 case FC_PUSH_WQM:
4228 case FC_LOOP:
4229 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
4230 break;
4231 case FC_REP:
4232 ctx->bc->callstack[ctx->bc->call_sp].current++;
4233 break;
4234 }
4235
4236 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
4237 ctx->bc->callstack[ctx->bc->call_sp].max) {
4238 ctx->bc->callstack[ctx->bc->call_sp].max =
4239 ctx->bc->callstack[ctx->bc->call_sp].current;
4240 }
4241 }
4242
4243 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
4244 {
4245 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
4246
4247 sp->mid = (struct r600_bytecode_cf **)realloc((void *)sp->mid,
4248 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
4249 sp->mid[sp->num_mid] = ctx->bc->cf_last;
4250 sp->num_mid++;
4251 }
4252
4253 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
4254 {
4255 ctx->bc->fc_sp++;
4256 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
4257 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
4258 }
4259
4260 static void fc_poplevel(struct r600_shader_ctx *ctx)
4261 {
4262 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
4263 if (sp->mid) {
4264 free(sp->mid);
4265 sp->mid = NULL;
4266 }
4267 sp->num_mid = 0;
4268 sp->start = NULL;
4269 sp->type = 0;
4270 ctx->bc->fc_sp--;
4271 }
4272
4273 #if 0
4274 static int emit_return(struct r600_shader_ctx *ctx)
4275 {
4276 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
4277 return 0;
4278 }
4279
4280 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
4281 {
4282
4283 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
4284 ctx->bc->cf_last->pop_count = pops;
4285 /* TODO work out offset */
4286 return 0;
4287 }
4288
4289 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
4290 {
4291 return 0;
4292 }
4293
4294 static void emit_testflag(struct r600_shader_ctx *ctx)
4295 {
4296
4297 }
4298
4299 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
4300 {
4301 emit_testflag(ctx);
4302 emit_jump_to_offset(ctx, 1, 4);
4303 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
4304 pops(ctx, ifidx + 1);
4305 emit_return(ctx);
4306 }
4307
4308 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
4309 {
4310 emit_testflag(ctx);
4311
4312 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
4313 ctx->bc->cf_last->pop_count = 1;
4314
4315 fc_set_mid(ctx, fc_sp);
4316
4317 pops(ctx, 1);
4318 }
4319 #endif
4320
4321 static int tgsi_if(struct r600_shader_ctx *ctx)
4322 {
4323 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
4324
4325 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
4326
4327 fc_pushlevel(ctx, FC_IF);
4328
4329 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
4330 return 0;
4331 }
4332
4333 static int tgsi_else(struct r600_shader_ctx *ctx)
4334 {
4335 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
4336 ctx->bc->cf_last->pop_count = 1;
4337
4338 fc_set_mid(ctx, ctx->bc->fc_sp);
4339 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
4340 return 0;
4341 }
4342
4343 static int tgsi_endif(struct r600_shader_ctx *ctx)
4344 {
4345 pops(ctx, 1);
4346 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
4347 R600_ERR("if/endif unbalanced in shader\n");
4348 return -1;
4349 }
4350
4351 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
4352 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
4353 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
4354 } else {
4355 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
4356 }
4357 fc_poplevel(ctx);
4358
4359 callstack_decrease_current(ctx, FC_PUSH_VPM);
4360 return 0;
4361 }
4362
4363 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
4364 {
4365 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
4366
4367 fc_pushlevel(ctx, FC_LOOP);
4368
4369 /* check stack depth */
4370 callstack_check_depth(ctx, FC_LOOP, 0);
4371 return 0;
4372 }
4373
4374 static int tgsi_endloop(struct r600_shader_ctx *ctx)
4375 {
4376 int i;
4377
4378 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
4379
4380 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
4381 R600_ERR("loop/endloop in shader code are not paired.\n");
4382 return -EINVAL;
4383 }
4384
4385 /* fixup loop pointers - from r600isa
4386 LOOP END points to CF after LOOP START,
4387 LOOP START point to CF after LOOP END
4388 BRK/CONT point to LOOP END CF
4389 */
4390 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
4391
4392 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
4393
4394 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
4395 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
4396 }
4397 /* TODO add LOOPRET support */
4398 fc_poplevel(ctx);
4399 callstack_decrease_current(ctx, FC_LOOP);
4400 return 0;
4401 }
4402
4403 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
4404 {
4405 unsigned int fscp;
4406
4407 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
4408 {
4409 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
4410 break;
4411 }
4412
4413 if (fscp == 0) {
4414 R600_ERR("Break not inside loop/endloop pair\n");
4415 return -EINVAL;
4416 }
4417
4418 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
4419 ctx->bc->cf_last->pop_count = 1;
4420
4421 fc_set_mid(ctx, fscp);
4422
4423 pops(ctx, 1);
4424 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
4425 return 0;
4426 }
4427
4428 static int tgsi_umad(struct r600_shader_ctx *ctx)
4429 {
4430 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4431 struct r600_bytecode_alu alu;
4432 int i, j, r;
4433 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4434
4435 /* src0 * src1 */
4436 for (i = 0; i < lasti + 1; i++) {
4437 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4438 continue;
4439
4440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4441
4442 alu.dst.chan = i;
4443 alu.dst.sel = ctx->temp_reg;
4444 alu.dst.write = 1;
4445
4446 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
4447 for (j = 0; j < 2; j++) {
4448 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4449 }
4450
4451 alu.last = 1;
4452 r = r600_bytecode_add_alu(ctx->bc, &alu);
4453 if (r)
4454 return r;
4455 }
4456
4457
4458 for (i = 0; i < lasti + 1; i++) {
4459 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4460 continue;
4461
4462 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4463 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4464
4465 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
4466
4467 alu.src[0].sel = ctx->temp_reg;
4468 alu.src[0].chan = i;
4469
4470 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4471 if (i == lasti) {
4472 alu.last = 1;
4473 }
4474 r = r600_bytecode_add_alu(ctx->bc, &alu);
4475 if (r)
4476 return r;
4477 }
4478 return 0;
4479 }
4480
4481 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
4482 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
4483 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4484 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
4485
4486 /* FIXME:
4487 * For state trackers other than OpenGL, we'll want to use
4488 * _RECIP_IEEE instead.
4489 */
4490 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
4491
4492 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
4493 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
4494 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
4495 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
4496 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4497 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4498 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4499 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
4500 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
4501 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
4502 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
4503 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
4504 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
4505 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4506 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
4507 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4508 /* gap */
4509 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4510 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4511 /* gap */
4512 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4513 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4514 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
4515 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4516 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
4517 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
4518 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
4519 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
4520 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
4521 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
4522 /* gap */
4523 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4524 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4525 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4526 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4527 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
4528 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
4529 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
4530 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
4531 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4532 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4533 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4534 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4535 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4536 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
4537 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4538 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
4539 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
4540 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
4541 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
4542 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4543 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4544 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
4545 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4546 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4547 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4548 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4549 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4550 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4551 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4552 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
4553 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4554 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4555 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4556 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
4557 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
4558 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
4559 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
4560 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4561 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4562 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4563 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
4564 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
4565 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
4566 /* gap */
4567 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4568 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4569 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
4570 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
4571 /* gap */
4572 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4573 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4574 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4575 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4576 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4577 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
4578 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
4579 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
4580 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2_trans},
4581 /* gap */
4582 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4583 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
4584 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
4585 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
4586 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
4587 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4588 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
4589 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
4590 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
4591 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4592 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4593 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
4594 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4595 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
4596 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4597 /* gap */
4598 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4599 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4600 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4601 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4602 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4603 /* gap */
4604 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4605 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4606 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4607 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4608 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4609 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4610 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4611 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4612 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
4613 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
4614 /* gap */
4615 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4616 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2_trans},
4617 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
4618 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
4619 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
4620 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
4621 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
4622 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2_trans},
4623 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
4624 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2},
4625 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
4626 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
4627 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
4628 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
4629 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
4630 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
4631 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
4632 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
4633 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
4634 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
4635 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2_trans},
4636 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
4637 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2_swap},
4638 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4639 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4640 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4641 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4642 {TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
4643 {TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
4644 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
4645 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
4646 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
4647 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
4648 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
4649 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
4650 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
4651 {TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
4652 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
4653 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
4654 {TGSI_OPCODE_UARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
4655 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
4656 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
4657 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
4658 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4659 };
4660
4661 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
4662 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
4663 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4664 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
4665 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
4666 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_rsq},
4667 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
4668 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
4669 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
4670 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4671 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4672 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4673 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
4674 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
4675 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
4676 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
4677 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
4678 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
4679 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4680 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
4681 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4682 /* gap */
4683 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4684 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4685 /* gap */
4686 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4687 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4688 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
4689 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4690 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
4691 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
4692 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
4693 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
4694 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
4695 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
4696 /* gap */
4697 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4698 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4699 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4700 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4701 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
4702 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
4703 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
4704 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
4705 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4706 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4707 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4708 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4709 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4710 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
4711 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4712 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
4713 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
4714 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
4715 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
4716 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4717 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4718 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
4719 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4720 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4721 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4722 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4723 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4724 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4725 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4726 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
4727 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4728 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4729 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4730 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
4731 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
4732 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
4733 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
4734 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4735 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4736 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4737 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
4738 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
4739 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
4740 /* gap */
4741 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4742 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4743 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
4744 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
4745 /* gap */
4746 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4747 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4748 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4749 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4750 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4751 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
4752 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
4753 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
4754 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
4755 /* gap */
4756 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4757 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
4758 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
4759 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
4760 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
4761 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4762 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
4763 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
4764 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
4765 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4766 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4767 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
4768 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4769 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
4770 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4771 /* gap */
4772 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4773 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4774 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4775 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4776 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4777 /* gap */
4778 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4779 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4780 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4781 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4782 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4783 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4784 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4785 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4786 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
4787 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
4788 /* gap */
4789 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4790 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_f2i},
4791 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
4792 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
4793 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
4794 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
4795 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
4796 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2},
4797 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
4798 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_f2i},
4799 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
4800 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
4801 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
4802 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
4803 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
4804 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
4805 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
4806 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
4807 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
4808 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
4809 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2},
4810 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
4811 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
4812 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4813 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4814 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4815 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4816 {TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
4817 {TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
4818 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
4819 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
4820 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
4821 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
4822 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
4823 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
4824 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
4825 {TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
4826 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
4827 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
4828 {TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
4829 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
4830 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
4831 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
4832 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4833 };
4834
4835 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
4836 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
4837 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4838 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
4839 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, cayman_emit_float_instr},
4840 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, cayman_emit_float_instr},
4841 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
4842 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
4843 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
4844 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4845 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4846 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4847 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
4848 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
4849 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
4850 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
4851 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
4852 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
4853 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4854 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
4855 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4856 /* gap */
4857 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4858 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4859 /* gap */
4860 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4861 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4862 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
4863 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4864 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
4865 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
4866 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, cayman_emit_float_instr},
4867 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, cayman_emit_float_instr},
4868 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, cayman_pow},
4869 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
4870 /* gap */
4871 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4872 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4873 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4874 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4875 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, cayman_trig},
4876 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
4877 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
4878 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
4879 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4880 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4881 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4882 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4883 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4884 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
4885 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4886 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
4887 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, cayman_trig},
4888 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
4889 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
4890 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4891 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4892 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
4893 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4894 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4895 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4896 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4897 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4898 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4899 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4900 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
4901 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4902 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4903 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4904 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
4905 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
4906 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
4907 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
4908 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4909 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4910 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4911 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
4912 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
4913 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
4914 /* gap */
4915 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4916 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4917 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
4918 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
4919 /* gap */
4920 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4921 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4922 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4923 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4924 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4925 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4926 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
4927 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
4928 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4929 /* gap */
4930 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4931 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4932 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4933 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4934 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
4935 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4936 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
4937 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
4938 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
4939 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4940 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4941 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
4942 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4943 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
4944 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4945 /* gap */
4946 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4947 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4948 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4949 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4950 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4951 /* gap */
4952 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4953 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4954 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4955 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4956 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4957 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4958 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4959 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4960 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
4961 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
4962 /* gap */
4963 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4964 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4965 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4966 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
4967 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
4968 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4969 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4970 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4971 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4972 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4973 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4974 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4975 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4976 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4977 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4978 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4979 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4980 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4981 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4982 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4983 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4984 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4985 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4986 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4987 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4988 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4989 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4990 {TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
4991 {TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
4992 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
4993 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
4994 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
4995 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
4996 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
4997 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
4998 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
4999 {TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
5000 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5001 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5002 {TGSI_OPCODE_UARL, 0, 0, tgsi_unsupported},
5003 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
5004 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5005 };