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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
64 static int r600_shader_from_tgsi(struct r600_context *rctx,
65 struct r600_pipe_shader *pipeshader,
66 union r600_shader_key key);
67
68
69 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
70 int size, unsigned comp_mask) {
71
72 if (!size)
73 return;
74
75 if (ps->num_arrays == ps->max_arrays) {
76 ps->max_arrays += 64;
77 ps->arrays = realloc(ps->arrays, ps->max_arrays *
78 sizeof(struct r600_shader_array));
79 }
80
81 int n = ps->num_arrays;
82 ++ps->num_arrays;
83
84 ps->arrays[n].comp_mask = comp_mask;
85 ps->arrays[n].gpr_start = start_gpr;
86 ps->arrays[n].gpr_count = size;
87 }
88
89 static void r600_dump_streamout(struct pipe_stream_output_info *so)
90 {
91 unsigned i;
92
93 fprintf(stderr, "STREAMOUT\n");
94 for (i = 0; i < so->num_outputs; i++) {
95 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
96 so->output[i].start_component;
97 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
98 i,
99 so->output[i].stream,
100 so->output[i].output_buffer,
101 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
102 so->output[i].register_index,
103 mask & 1 ? "x" : "",
104 mask & 2 ? "y" : "",
105 mask & 4 ? "z" : "",
106 mask & 8 ? "w" : "",
107 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
108 }
109 }
110
111 static int store_shader(struct pipe_context *ctx,
112 struct r600_pipe_shader *shader)
113 {
114 struct r600_context *rctx = (struct r600_context *)ctx;
115 uint32_t *ptr, i;
116
117 if (shader->bo == NULL) {
118 shader->bo = (struct r600_resource*)
119 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
120 if (shader->bo == NULL) {
121 return -ENOMEM;
122 }
123 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
124 if (R600_BIG_ENDIAN) {
125 for (i = 0; i < shader->shader.bc.ndw; ++i) {
126 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
127 }
128 } else {
129 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
130 }
131 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
132 }
133
134 return 0;
135 }
136
137 int r600_pipe_shader_create(struct pipe_context *ctx,
138 struct r600_pipe_shader *shader,
139 union r600_shader_key key)
140 {
141 struct r600_context *rctx = (struct r600_context *)ctx;
142 struct r600_pipe_shader_selector *sel = shader->selector;
143 int r;
144 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
145 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
146 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
147 unsigned export_shader;
148
149 shader->shader.bc.isa = rctx->isa;
150
151 if (dump) {
152 fprintf(stderr, "--------------------------------------------------------------\n");
153 tgsi_dump(sel->tokens, 0);
154
155 if (sel->so.num_outputs) {
156 r600_dump_streamout(&sel->so);
157 }
158 }
159 r = r600_shader_from_tgsi(rctx, shader, key);
160 if (r) {
161 R600_ERR("translation from TGSI failed !\n");
162 goto error;
163 }
164
165 /* disable SB for shaders using doubles */
166 use_sb &= !shader->shader.uses_doubles;
167
168 /* Check if the bytecode has already been built. When using the llvm
169 * backend, r600_shader_from_tgsi() will take care of building the
170 * bytecode.
171 */
172 if (!shader->shader.bc.bytecode) {
173 r = r600_bytecode_build(&shader->shader.bc);
174 if (r) {
175 R600_ERR("building bytecode failed !\n");
176 goto error;
177 }
178 }
179
180 if (dump && !sb_disasm) {
181 fprintf(stderr, "--------------------------------------------------------------\n");
182 r600_bytecode_disasm(&shader->shader.bc);
183 fprintf(stderr, "______________________________________________________________\n");
184 } else if ((dump && sb_disasm) || use_sb) {
185 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
186 dump, use_sb);
187 if (r) {
188 R600_ERR("r600_sb_bytecode_process failed !\n");
189 goto error;
190 }
191 }
192
193 if (shader->gs_copy_shader) {
194 if (dump) {
195 // dump copy shader
196 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
197 &shader->gs_copy_shader->shader, dump, 0);
198 if (r)
199 goto error;
200 }
201
202 if ((r = store_shader(ctx, shader->gs_copy_shader)))
203 goto error;
204 }
205
206 /* Store the shader in a buffer. */
207 if ((r = store_shader(ctx, shader)))
208 goto error;
209
210 /* Build state. */
211 switch (shader->shader.processor_type) {
212 case TGSI_PROCESSOR_GEOMETRY:
213 if (rctx->b.chip_class >= EVERGREEN) {
214 evergreen_update_gs_state(ctx, shader);
215 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
216 } else {
217 r600_update_gs_state(ctx, shader);
218 r600_update_vs_state(ctx, shader->gs_copy_shader);
219 }
220 break;
221 case TGSI_PROCESSOR_VERTEX:
222 export_shader = key.vs.as_es;
223 if (rctx->b.chip_class >= EVERGREEN) {
224 if (export_shader)
225 evergreen_update_es_state(ctx, shader);
226 else
227 evergreen_update_vs_state(ctx, shader);
228 } else {
229 if (export_shader)
230 r600_update_es_state(ctx, shader);
231 else
232 r600_update_vs_state(ctx, shader);
233 }
234 break;
235 case TGSI_PROCESSOR_FRAGMENT:
236 if (rctx->b.chip_class >= EVERGREEN) {
237 evergreen_update_ps_state(ctx, shader);
238 } else {
239 r600_update_ps_state(ctx, shader);
240 }
241 break;
242 default:
243 r = -EINVAL;
244 goto error;
245 }
246 return 0;
247
248 error:
249 r600_pipe_shader_destroy(ctx, shader);
250 return r;
251 }
252
253 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
254 {
255 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
256 r600_bytecode_clear(&shader->shader.bc);
257 r600_release_command_buffer(&shader->command_buffer);
258 }
259
260 /*
261 * tgsi -> r600 shader
262 */
263 struct r600_shader_tgsi_instruction;
264
265 struct r600_shader_src {
266 unsigned sel;
267 unsigned swizzle[4];
268 unsigned neg;
269 unsigned abs;
270 unsigned rel;
271 unsigned kc_bank;
272 boolean kc_rel; /* true if cache bank is indexed */
273 uint32_t value[4];
274 };
275
276 struct eg_interp {
277 boolean enabled;
278 unsigned ij_index;
279 };
280
281 struct r600_shader_ctx {
282 struct tgsi_shader_info info;
283 struct tgsi_parse_context parse;
284 const struct tgsi_token *tokens;
285 unsigned type;
286 unsigned file_offset[TGSI_FILE_COUNT];
287 unsigned temp_reg;
288 const struct r600_shader_tgsi_instruction *inst_info;
289 struct r600_bytecode *bc;
290 struct r600_shader *shader;
291 struct r600_shader_src src[4];
292 uint32_t *literals;
293 uint32_t nliterals;
294 uint32_t max_driver_temp_used;
295 boolean use_llvm;
296 /* needed for evergreen interpolation */
297 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
298 /* evergreen/cayman also store sample mask in face register */
299 int face_gpr;
300 /* sample id is .w component stored in fixed point position register */
301 int fixed_pt_position_gpr;
302 int colors_used;
303 boolean clip_vertex_write;
304 unsigned cv_output;
305 unsigned edgeflag_output;
306 int fragcoord_input;
307 int native_integers;
308 int next_ring_offset;
309 int gs_out_ring_offset;
310 int gs_next_vertex;
311 struct r600_shader *gs_for_vs;
312 int gs_export_gpr_tregs[4];
313 const struct pipe_stream_output_info *gs_stream_output_info;
314 unsigned enabled_stream_buffers_mask;
315 };
316
317 struct r600_shader_tgsi_instruction {
318 unsigned op;
319 int (*process)(struct r600_shader_ctx *ctx);
320 };
321
322 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
323 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
324 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
325 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
326 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
327 static int tgsi_else(struct r600_shader_ctx *ctx);
328 static int tgsi_endif(struct r600_shader_ctx *ctx);
329 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
330 static int tgsi_endloop(struct r600_shader_ctx *ctx);
331 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
332 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
333 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
334 unsigned int dst_reg);
335 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
336 const struct r600_shader_src *shader_src,
337 unsigned chan);
338
339 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
340 {
341 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
342 int j;
343
344 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
345 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
346 return -EINVAL;
347 }
348 if (i->Instruction.Predicate) {
349 R600_ERR("predicate unsupported\n");
350 return -EINVAL;
351 }
352 #if 0
353 if (i->Instruction.Label) {
354 R600_ERR("label unsupported\n");
355 return -EINVAL;
356 }
357 #endif
358 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
359 if (i->Src[j].Register.Dimension) {
360 switch (i->Src[j].Register.File) {
361 case TGSI_FILE_CONSTANT:
362 break;
363 case TGSI_FILE_INPUT:
364 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
365 break;
366 default:
367 R600_ERR("unsupported src %d (dimension %d)\n", j,
368 i->Src[j].Register.Dimension);
369 return -EINVAL;
370 }
371 }
372 }
373 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
374 if (i->Dst[j].Register.Dimension) {
375 R600_ERR("unsupported dst (dimension)\n");
376 return -EINVAL;
377 }
378 }
379 return 0;
380 }
381
382 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
383 {
384 if (interpolate == TGSI_INTERPOLATE_COLOR ||
385 interpolate == TGSI_INTERPOLATE_LINEAR ||
386 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
387 {
388 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
389 int loc;
390
391 switch(location) {
392 case TGSI_INTERPOLATE_LOC_CENTER:
393 loc = 1;
394 break;
395 case TGSI_INTERPOLATE_LOC_CENTROID:
396 loc = 2;
397 break;
398 case TGSI_INTERPOLATE_LOC_SAMPLE:
399 default:
400 loc = 0; break;
401 }
402
403 return is_linear * 3 + loc;
404 }
405
406 return -1;
407 }
408
409 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
410 int input)
411 {
412 int i = eg_get_interpolator_index(
413 ctx->shader->input[input].interpolate,
414 ctx->shader->input[input].interpolate_location);
415 assert(i >= 0);
416 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
417 }
418
419 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
420 {
421 int i, r;
422 struct r600_bytecode_alu alu;
423 int gpr = 0, base_chan = 0;
424 int ij_index = ctx->shader->input[input].ij_index;
425
426 /* work out gpr and base_chan from index */
427 gpr = ij_index / 2;
428 base_chan = (2 * (ij_index % 2)) + 1;
429
430 for (i = 0; i < 8; i++) {
431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
432
433 if (i < 4)
434 alu.op = ALU_OP2_INTERP_ZW;
435 else
436 alu.op = ALU_OP2_INTERP_XY;
437
438 if ((i > 1) && (i < 6)) {
439 alu.dst.sel = ctx->shader->input[input].gpr;
440 alu.dst.write = 1;
441 }
442
443 alu.dst.chan = i % 4;
444
445 alu.src[0].sel = gpr;
446 alu.src[0].chan = (base_chan - (i % 2));
447
448 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
449
450 alu.bank_swizzle_force = SQ_ALU_VEC_210;
451 if ((i % 4) == 3)
452 alu.last = 1;
453 r = r600_bytecode_add_alu(ctx->bc, &alu);
454 if (r)
455 return r;
456 }
457 return 0;
458 }
459
460 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
461 {
462 int i, r;
463 struct r600_bytecode_alu alu;
464
465 for (i = 0; i < 4; i++) {
466 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
467
468 alu.op = ALU_OP1_INTERP_LOAD_P0;
469
470 alu.dst.sel = ctx->shader->input[input].gpr;
471 alu.dst.write = 1;
472
473 alu.dst.chan = i;
474
475 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
476 alu.src[0].chan = i;
477
478 if (i == 3)
479 alu.last = 1;
480 r = r600_bytecode_add_alu(ctx->bc, &alu);
481 if (r)
482 return r;
483 }
484 return 0;
485 }
486
487 /*
488 * Special export handling in shaders
489 *
490 * shader export ARRAY_BASE for EXPORT_POS:
491 * 60 is position
492 * 61 is misc vector
493 * 62, 63 are clip distance vectors
494 *
495 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
496 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
497 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
498 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
499 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
500 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
501 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
502 * exclusive from render target index)
503 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
504 *
505 *
506 * shader export ARRAY_BASE for EXPORT_PIXEL:
507 * 0-7 CB targets
508 * 61 computed Z vector
509 *
510 * The use of the values exported in the computed Z vector are controlled
511 * by DB_SHADER_CONTROL:
512 * Z_EXPORT_ENABLE - Z as a float in RED
513 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
514 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
515 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
516 * DB_SOURCE_FORMAT - export control restrictions
517 *
518 */
519
520
521 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
522 static int r600_spi_sid(struct r600_shader_io * io)
523 {
524 int index, name = io->name;
525
526 /* These params are handled differently, they don't need
527 * semantic indices, so we'll use 0 for them.
528 */
529 if (name == TGSI_SEMANTIC_POSITION ||
530 name == TGSI_SEMANTIC_PSIZE ||
531 name == TGSI_SEMANTIC_EDGEFLAG ||
532 name == TGSI_SEMANTIC_FACE ||
533 name == TGSI_SEMANTIC_SAMPLEMASK)
534 index = 0;
535 else {
536 if (name == TGSI_SEMANTIC_GENERIC) {
537 /* For generic params simply use sid from tgsi */
538 index = io->sid;
539 } else {
540 /* For non-generic params - pack name and sid into 8 bits */
541 index = 0x80 | (name<<3) | (io->sid);
542 }
543
544 /* Make sure that all really used indices have nonzero value, so
545 * we can just compare it to 0 later instead of comparing the name
546 * with different values to detect special cases. */
547 index++;
548 }
549
550 return index;
551 };
552
553 /* turn input into interpolate on EG */
554 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
555 {
556 int r = 0;
557
558 if (ctx->shader->input[index].spi_sid) {
559 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
560 if (ctx->shader->input[index].interpolate > 0) {
561 evergreen_interp_assign_ij_index(ctx, index);
562 if (!ctx->use_llvm)
563 r = evergreen_interp_alu(ctx, index);
564 } else {
565 if (!ctx->use_llvm)
566 r = evergreen_interp_flat(ctx, index);
567 }
568 }
569 return r;
570 }
571
572 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
573 {
574 struct r600_bytecode_alu alu;
575 int i, r;
576 int gpr_front = ctx->shader->input[front].gpr;
577 int gpr_back = ctx->shader->input[back].gpr;
578
579 for (i = 0; i < 4; i++) {
580 memset(&alu, 0, sizeof(alu));
581 alu.op = ALU_OP3_CNDGT;
582 alu.is_op3 = 1;
583 alu.dst.write = 1;
584 alu.dst.sel = gpr_front;
585 alu.src[0].sel = ctx->face_gpr;
586 alu.src[1].sel = gpr_front;
587 alu.src[2].sel = gpr_back;
588
589 alu.dst.chan = i;
590 alu.src[1].chan = i;
591 alu.src[2].chan = i;
592 alu.last = (i==3);
593
594 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
595 return r;
596 }
597
598 return 0;
599 }
600
601 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
602 {
603 int i;
604 i = ctx->shader->noutput++;
605 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
606 ctx->shader->output[i].sid = 0;
607 ctx->shader->output[i].gpr = 0;
608 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
609 ctx->shader->output[i].write_mask = 0x4;
610 ctx->shader->output[i].spi_sid = prim_id_sid;
611
612 return 0;
613 }
614
615 static int tgsi_declaration(struct r600_shader_ctx *ctx)
616 {
617 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
618 int r, i, j, count = d->Range.Last - d->Range.First + 1;
619
620 switch (d->Declaration.File) {
621 case TGSI_FILE_INPUT:
622 for (j = 0; j < count; j++) {
623 i = ctx->shader->ninput + j;
624 assert(i < Elements(ctx->shader->input));
625 ctx->shader->input[i].name = d->Semantic.Name;
626 ctx->shader->input[i].sid = d->Semantic.Index + j;
627 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
628 ctx->shader->input[i].interpolate_location = d->Interp.Location;
629 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
630 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
631 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
632 switch (ctx->shader->input[i].name) {
633 case TGSI_SEMANTIC_FACE:
634 if (ctx->face_gpr != -1)
635 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
636 else
637 ctx->face_gpr = ctx->shader->input[i].gpr;
638 break;
639 case TGSI_SEMANTIC_COLOR:
640 ctx->colors_used++;
641 break;
642 case TGSI_SEMANTIC_POSITION:
643 ctx->fragcoord_input = i;
644 break;
645 case TGSI_SEMANTIC_PRIMID:
646 /* set this for now */
647 ctx->shader->gs_prim_id_input = true;
648 ctx->shader->ps_prim_id_input = i;
649 break;
650 }
651 if (ctx->bc->chip_class >= EVERGREEN) {
652 if ((r = evergreen_interp_input(ctx, i)))
653 return r;
654 }
655 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
656 /* FIXME probably skip inputs if they aren't passed in the ring */
657 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
658 ctx->next_ring_offset += 16;
659 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
660 ctx->shader->gs_prim_id_input = true;
661 }
662 }
663 ctx->shader->ninput += count;
664 break;
665 case TGSI_FILE_OUTPUT:
666 for (j = 0; j < count; j++) {
667 i = ctx->shader->noutput + j;
668 assert(i < Elements(ctx->shader->output));
669 ctx->shader->output[i].name = d->Semantic.Name;
670 ctx->shader->output[i].sid = d->Semantic.Index + j;
671 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
672 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
673 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
674 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
675 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
676 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
677 switch (d->Semantic.Name) {
678 case TGSI_SEMANTIC_CLIPDIST:
679 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
680 ((d->Semantic.Index + j) << 2);
681 break;
682 case TGSI_SEMANTIC_PSIZE:
683 ctx->shader->vs_out_misc_write = 1;
684 ctx->shader->vs_out_point_size = 1;
685 break;
686 case TGSI_SEMANTIC_EDGEFLAG:
687 ctx->shader->vs_out_misc_write = 1;
688 ctx->shader->vs_out_edgeflag = 1;
689 ctx->edgeflag_output = i;
690 break;
691 case TGSI_SEMANTIC_VIEWPORT_INDEX:
692 ctx->shader->vs_out_misc_write = 1;
693 ctx->shader->vs_out_viewport = 1;
694 break;
695 case TGSI_SEMANTIC_LAYER:
696 ctx->shader->vs_out_misc_write = 1;
697 ctx->shader->vs_out_layer = 1;
698 break;
699 case TGSI_SEMANTIC_CLIPVERTEX:
700 ctx->clip_vertex_write = TRUE;
701 ctx->cv_output = i;
702 break;
703 }
704 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
705 ctx->gs_out_ring_offset += 16;
706 }
707 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
708 switch (d->Semantic.Name) {
709 case TGSI_SEMANTIC_COLOR:
710 ctx->shader->nr_ps_max_color_exports++;
711 break;
712 }
713 }
714 }
715 ctx->shader->noutput += count;
716 break;
717 case TGSI_FILE_TEMPORARY:
718 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
719 if (d->Array.ArrayID) {
720 r600_add_gpr_array(ctx->shader,
721 ctx->file_offset[TGSI_FILE_TEMPORARY] +
722 d->Range.First,
723 d->Range.Last - d->Range.First + 1, 0x0F);
724 }
725 }
726 break;
727
728 case TGSI_FILE_CONSTANT:
729 case TGSI_FILE_SAMPLER:
730 case TGSI_FILE_SAMPLER_VIEW:
731 case TGSI_FILE_ADDRESS:
732 break;
733
734 case TGSI_FILE_SYSTEM_VALUE:
735 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
736 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
737 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
738 break; /* Already handled from allocate_system_value_inputs */
739 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
740 if (!ctx->native_integers) {
741 struct r600_bytecode_alu alu;
742 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
743
744 alu.op = ALU_OP1_INT_TO_FLT;
745 alu.src[0].sel = 0;
746 alu.src[0].chan = 3;
747
748 alu.dst.sel = 0;
749 alu.dst.chan = 3;
750 alu.dst.write = 1;
751 alu.last = 1;
752
753 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
754 return r;
755 }
756 break;
757 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
758 break;
759 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
760 break;
761 default:
762 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
763 return -EINVAL;
764 }
765 return 0;
766 }
767
768 static int r600_get_temp(struct r600_shader_ctx *ctx)
769 {
770 return ctx->temp_reg + ctx->max_driver_temp_used++;
771 }
772
773 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
774 {
775 struct tgsi_parse_context parse;
776 struct {
777 boolean enabled;
778 int *reg;
779 unsigned name, alternate_name;
780 } inputs[2] = {
781 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
782
783 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
784 };
785 int i, k, num_regs = 0;
786
787 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
788 return 0;
789 }
790
791 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
792 while (!tgsi_parse_end_of_tokens(&parse)) {
793 tgsi_parse_token(&parse);
794
795 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
796 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
797 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
798 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
799 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
800 {
801 int interpolate, location, k;
802
803 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
804 location = TGSI_INTERPOLATE_LOC_CENTER;
805 inputs[1].enabled = true; /* needs SAMPLEID */
806 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
807 location = TGSI_INTERPOLATE_LOC_CENTER;
808 /* Needs sample positions, currently those are always available */
809 } else {
810 location = TGSI_INTERPOLATE_LOC_CENTROID;
811 }
812
813 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
814 k = eg_get_interpolator_index(interpolate, location);
815 ctx->eg_interpolators[k].enabled = true;
816 }
817 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
818 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
819 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
820 for (k = 0; k < Elements(inputs); k++) {
821 if (d->Semantic.Name == inputs[k].name ||
822 d->Semantic.Name == inputs[k].alternate_name) {
823 inputs[k].enabled = true;
824 }
825 }
826 }
827 }
828 }
829
830 tgsi_parse_free(&parse);
831
832 for (i = 0; i < Elements(inputs); i++) {
833 boolean enabled = inputs[i].enabled;
834 int *reg = inputs[i].reg;
835 unsigned name = inputs[i].name;
836
837 if (enabled) {
838 int gpr = gpr_offset + num_regs++;
839
840 // add to inputs, allocate a gpr
841 k = ctx->shader->ninput ++;
842 ctx->shader->input[k].name = name;
843 ctx->shader->input[k].sid = 0;
844 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
845 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
846 *reg = ctx->shader->input[k].gpr = gpr;
847 }
848 }
849
850 return gpr_offset + num_regs;
851 }
852
853 /*
854 * for evergreen we need to scan the shader to find the number of GPRs we need to
855 * reserve for interpolation and system values
856 *
857 * we need to know if we are going to emit
858 * any sample or centroid inputs
859 * if perspective and linear are required
860 */
861 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
862 {
863 int i;
864 int num_baryc;
865 struct tgsi_parse_context parse;
866
867 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
868
869 for (i = 0; i < ctx->info.num_inputs; i++) {
870 int k;
871 /* skip position/face/mask/sampleid */
872 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
873 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
874 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
875 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
876 continue;
877
878 k = eg_get_interpolator_index(
879 ctx->info.input_interpolate[i],
880 ctx->info.input_interpolate_loc[i]);
881 if (k >= 0)
882 ctx->eg_interpolators[k].enabled = TRUE;
883 }
884
885 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
886 return 0;
887 }
888
889 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
890 while (!tgsi_parse_end_of_tokens(&parse)) {
891 tgsi_parse_token(&parse);
892
893 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
894 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
895 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
896 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
897 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
898 {
899 int interpolate, location, k;
900
901 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
902 location = TGSI_INTERPOLATE_LOC_CENTER;
903 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
904 location = TGSI_INTERPOLATE_LOC_CENTER;
905 } else {
906 location = TGSI_INTERPOLATE_LOC_CENTROID;
907 }
908
909 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
910 k = eg_get_interpolator_index(interpolate, location);
911 ctx->eg_interpolators[k].enabled = true;
912 }
913 }
914 }
915
916 tgsi_parse_free(&parse);
917
918 /* assign gpr to each interpolator according to priority */
919 num_baryc = 0;
920 for (i = 0; i < Elements(ctx->eg_interpolators); i++) {
921 if (ctx->eg_interpolators[i].enabled) {
922 ctx->eg_interpolators[i].ij_index = num_baryc;
923 num_baryc ++;
924 }
925 }
926
927 /* XXX PULL MODEL and LINE STIPPLE */
928
929 num_baryc = (num_baryc + 1) >> 1;
930 return allocate_system_value_inputs(ctx, num_baryc);
931 }
932
933 /* sample_id_sel == NULL means fetch for current sample */
934 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
935 {
936 struct r600_bytecode_vtx vtx;
937 int r, t1;
938
939 assert(ctx->fixed_pt_position_gpr != -1);
940
941 t1 = r600_get_temp(ctx);
942
943 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
944 vtx.op = FETCH_OP_VFETCH;
945 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
946 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
947 if (sample_id == NULL) {
948 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
949 vtx.src_sel_x = 3;
950 }
951 else {
952 struct r600_bytecode_alu alu;
953
954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
955 alu.op = ALU_OP1_MOV;
956 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
957 alu.dst.sel = t1;
958 alu.dst.write = 1;
959 alu.last = 1;
960 r = r600_bytecode_add_alu(ctx->bc, &alu);
961 if (r)
962 return r;
963
964 vtx.src_gpr = t1;
965 vtx.src_sel_x = 0;
966 }
967 vtx.mega_fetch_count = 16;
968 vtx.dst_gpr = t1;
969 vtx.dst_sel_x = 0;
970 vtx.dst_sel_y = 1;
971 vtx.dst_sel_z = 2;
972 vtx.dst_sel_w = 3;
973 vtx.data_format = FMT_32_32_32_32_FLOAT;
974 vtx.num_format_all = 2;
975 vtx.format_comp_all = 1;
976 vtx.use_const_fields = 0;
977 vtx.offset = 1; // first element is size of buffer
978 vtx.endian = r600_endian_swap(32);
979 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
980
981 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
982 if (r)
983 return r;
984
985 return t1;
986 }
987
988 static void tgsi_src(struct r600_shader_ctx *ctx,
989 const struct tgsi_full_src_register *tgsi_src,
990 struct r600_shader_src *r600_src)
991 {
992 memset(r600_src, 0, sizeof(*r600_src));
993 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
994 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
995 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
996 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
997 r600_src->neg = tgsi_src->Register.Negate;
998 r600_src->abs = tgsi_src->Register.Absolute;
999
1000 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1001 int index;
1002 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1003 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1004 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1005
1006 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1007 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1008 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1009 return;
1010 }
1011 index = tgsi_src->Register.Index;
1012 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1013 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1014 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1015 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1016 r600_src->swizzle[0] = 2; // Z value
1017 r600_src->swizzle[1] = 2;
1018 r600_src->swizzle[2] = 2;
1019 r600_src->swizzle[3] = 2;
1020 r600_src->sel = ctx->face_gpr;
1021 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1022 r600_src->swizzle[0] = 3; // W value
1023 r600_src->swizzle[1] = 3;
1024 r600_src->swizzle[2] = 3;
1025 r600_src->swizzle[3] = 3;
1026 r600_src->sel = ctx->fixed_pt_position_gpr;
1027 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1028 r600_src->swizzle[0] = 0;
1029 r600_src->swizzle[1] = 1;
1030 r600_src->swizzle[2] = 4;
1031 r600_src->swizzle[3] = 4;
1032 r600_src->sel = load_sample_position(ctx, NULL, -1);
1033 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1034 r600_src->swizzle[0] = 3;
1035 r600_src->swizzle[1] = 3;
1036 r600_src->swizzle[2] = 3;
1037 r600_src->swizzle[3] = 3;
1038 r600_src->sel = 0;
1039 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1040 r600_src->swizzle[0] = 0;
1041 r600_src->swizzle[1] = 0;
1042 r600_src->swizzle[2] = 0;
1043 r600_src->swizzle[3] = 0;
1044 r600_src->sel = 0;
1045 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1046 r600_src->swizzle[0] = 3;
1047 r600_src->swizzle[1] = 3;
1048 r600_src->swizzle[2] = 3;
1049 r600_src->swizzle[3] = 3;
1050 r600_src->sel = 1;
1051 }
1052 } else {
1053 if (tgsi_src->Register.Indirect)
1054 r600_src->rel = V_SQ_REL_RELATIVE;
1055 r600_src->sel = tgsi_src->Register.Index;
1056 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1057 }
1058 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1059 if (tgsi_src->Register.Dimension) {
1060 r600_src->kc_bank = tgsi_src->Dimension.Index;
1061 if (tgsi_src->Dimension.Indirect) {
1062 r600_src->kc_rel = 1;
1063 }
1064 }
1065 }
1066 }
1067
1068 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1069 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1070 unsigned int dst_reg)
1071 {
1072 struct r600_bytecode_vtx vtx;
1073 unsigned int ar_reg;
1074 int r;
1075
1076 if (offset) {
1077 struct r600_bytecode_alu alu;
1078
1079 memset(&alu, 0, sizeof(alu));
1080
1081 alu.op = ALU_OP2_ADD_INT;
1082 alu.src[0].sel = ctx->bc->ar_reg;
1083 alu.src[0].chan = ar_chan;
1084
1085 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1086 alu.src[1].value = offset;
1087
1088 alu.dst.sel = dst_reg;
1089 alu.dst.chan = ar_chan;
1090 alu.dst.write = 1;
1091 alu.last = 1;
1092
1093 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1094 return r;
1095
1096 ar_reg = dst_reg;
1097 } else {
1098 ar_reg = ctx->bc->ar_reg;
1099 }
1100
1101 memset(&vtx, 0, sizeof(vtx));
1102 vtx.buffer_id = cb_idx;
1103 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1104 vtx.src_gpr = ar_reg;
1105 vtx.src_sel_x = ar_chan;
1106 vtx.mega_fetch_count = 16;
1107 vtx.dst_gpr = dst_reg;
1108 vtx.dst_sel_x = 0; /* SEL_X */
1109 vtx.dst_sel_y = 1; /* SEL_Y */
1110 vtx.dst_sel_z = 2; /* SEL_Z */
1111 vtx.dst_sel_w = 3; /* SEL_W */
1112 vtx.data_format = FMT_32_32_32_32_FLOAT;
1113 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1114 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1115 vtx.endian = r600_endian_swap(32);
1116 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1117
1118 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1119 return r;
1120
1121 return 0;
1122 }
1123
1124 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1125 {
1126 struct r600_bytecode_vtx vtx;
1127 int r;
1128 unsigned index = src->Register.Index;
1129 unsigned vtx_id = src->Dimension.Index;
1130 int offset_reg = vtx_id / 3;
1131 int offset_chan = vtx_id % 3;
1132
1133 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1134 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1135
1136 if (offset_reg == 0 && offset_chan == 2)
1137 offset_chan = 3;
1138
1139 if (src->Dimension.Indirect) {
1140 int treg[3];
1141 int t2;
1142 struct r600_bytecode_alu alu;
1143 int r, i;
1144
1145 /* you have got to be shitting me -
1146 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1147 at least this is what fglrx seems to do. */
1148 for (i = 0; i < 3; i++) {
1149 treg[i] = r600_get_temp(ctx);
1150 }
1151 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1152
1153 t2 = r600_get_temp(ctx);
1154 for (i = 0; i < 3; i++) {
1155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1156 alu.op = ALU_OP1_MOV;
1157 alu.src[0].sel = 0;
1158 alu.src[0].chan = i == 2 ? 3 : i;
1159 alu.dst.sel = treg[i];
1160 alu.dst.chan = 0;
1161 alu.dst.write = 1;
1162 alu.last = 1;
1163 r = r600_bytecode_add_alu(ctx->bc, &alu);
1164 if (r)
1165 return r;
1166 }
1167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1168 alu.op = ALU_OP1_MOV;
1169 alu.src[0].sel = treg[0];
1170 alu.src[0].rel = 1;
1171 alu.dst.sel = t2;
1172 alu.dst.write = 1;
1173 alu.last = 1;
1174 r = r600_bytecode_add_alu(ctx->bc, &alu);
1175 if (r)
1176 return r;
1177 offset_reg = t2;
1178 }
1179
1180
1181 memset(&vtx, 0, sizeof(vtx));
1182 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1183 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1184 vtx.src_gpr = offset_reg;
1185 vtx.src_sel_x = offset_chan;
1186 vtx.offset = index * 16; /*bytes*/
1187 vtx.mega_fetch_count = 16;
1188 vtx.dst_gpr = dst_reg;
1189 vtx.dst_sel_x = 0; /* SEL_X */
1190 vtx.dst_sel_y = 1; /* SEL_Y */
1191 vtx.dst_sel_z = 2; /* SEL_Z */
1192 vtx.dst_sel_w = 3; /* SEL_W */
1193 if (ctx->bc->chip_class >= EVERGREEN) {
1194 vtx.use_const_fields = 1;
1195 } else {
1196 vtx.data_format = FMT_32_32_32_32_FLOAT;
1197 }
1198
1199 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1200 return r;
1201
1202 return 0;
1203 }
1204
1205 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1206 {
1207 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1208 int i;
1209
1210 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1211 struct tgsi_full_src_register *src = &inst->Src[i];
1212
1213 if (src->Register.File == TGSI_FILE_INPUT) {
1214 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1215 /* primitive id is in R0.z */
1216 ctx->src[i].sel = 0;
1217 ctx->src[i].swizzle[0] = 2;
1218 }
1219 }
1220 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1221 int treg = r600_get_temp(ctx);
1222
1223 fetch_gs_input(ctx, src, treg);
1224 ctx->src[i].sel = treg;
1225 }
1226 }
1227 return 0;
1228 }
1229
1230 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1231 {
1232 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1233 struct r600_bytecode_alu alu;
1234 int i, j, k, nconst, r;
1235
1236 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1237 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1238 nconst++;
1239 }
1240 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1241 }
1242 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1243 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1244 continue;
1245 }
1246
1247 if (ctx->src[i].rel) {
1248 int chan = inst->Src[i].Indirect.Swizzle;
1249 int treg = r600_get_temp(ctx);
1250 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1251 return r;
1252
1253 ctx->src[i].kc_bank = 0;
1254 ctx->src[i].kc_rel = 0;
1255 ctx->src[i].sel = treg;
1256 ctx->src[i].rel = 0;
1257 j--;
1258 } else if (j > 0) {
1259 int treg = r600_get_temp(ctx);
1260 for (k = 0; k < 4; k++) {
1261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1262 alu.op = ALU_OP1_MOV;
1263 alu.src[0].sel = ctx->src[i].sel;
1264 alu.src[0].chan = k;
1265 alu.src[0].rel = ctx->src[i].rel;
1266 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1267 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1268 alu.dst.sel = treg;
1269 alu.dst.chan = k;
1270 alu.dst.write = 1;
1271 if (k == 3)
1272 alu.last = 1;
1273 r = r600_bytecode_add_alu(ctx->bc, &alu);
1274 if (r)
1275 return r;
1276 }
1277 ctx->src[i].sel = treg;
1278 ctx->src[i].rel =0;
1279 j--;
1280 }
1281 }
1282 return 0;
1283 }
1284
1285 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1286 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1287 {
1288 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1289 struct r600_bytecode_alu alu;
1290 int i, j, k, nliteral, r;
1291
1292 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1293 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1294 nliteral++;
1295 }
1296 }
1297 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1298 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1299 int treg = r600_get_temp(ctx);
1300 for (k = 0; k < 4; k++) {
1301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1302 alu.op = ALU_OP1_MOV;
1303 alu.src[0].sel = ctx->src[i].sel;
1304 alu.src[0].chan = k;
1305 alu.src[0].value = ctx->src[i].value[k];
1306 alu.dst.sel = treg;
1307 alu.dst.chan = k;
1308 alu.dst.write = 1;
1309 if (k == 3)
1310 alu.last = 1;
1311 r = r600_bytecode_add_alu(ctx->bc, &alu);
1312 if (r)
1313 return r;
1314 }
1315 ctx->src[i].sel = treg;
1316 j--;
1317 }
1318 }
1319 return 0;
1320 }
1321
1322 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1323 {
1324 int i, r, count = ctx->shader->ninput;
1325
1326 for (i = 0; i < count; i++) {
1327 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1328 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1329 if (r)
1330 return r;
1331 }
1332 }
1333 return 0;
1334 }
1335
1336 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1337 int stream, unsigned *stream_item_size)
1338 {
1339 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1340 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1341 int i, j, r;
1342
1343 /* Sanity checking. */
1344 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1345 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1346 r = -EINVAL;
1347 goto out_err;
1348 }
1349 for (i = 0; i < so->num_outputs; i++) {
1350 if (so->output[i].output_buffer >= 4) {
1351 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1352 so->output[i].output_buffer);
1353 r = -EINVAL;
1354 goto out_err;
1355 }
1356 }
1357
1358 /* Initialize locations where the outputs are stored. */
1359 for (i = 0; i < so->num_outputs; i++) {
1360
1361 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1362 start_comp[i] = so->output[i].start_component;
1363 /* Lower outputs with dst_offset < start_component.
1364 *
1365 * We can only output 4D vectors with a write mask, e.g. we can
1366 * only output the W component at offset 3, etc. If we want
1367 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1368 * to move it to X and output X. */
1369 if (so->output[i].dst_offset < so->output[i].start_component) {
1370 unsigned tmp = r600_get_temp(ctx);
1371
1372 for (j = 0; j < so->output[i].num_components; j++) {
1373 struct r600_bytecode_alu alu;
1374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1375 alu.op = ALU_OP1_MOV;
1376 alu.src[0].sel = so_gpr[i];
1377 alu.src[0].chan = so->output[i].start_component + j;
1378
1379 alu.dst.sel = tmp;
1380 alu.dst.chan = j;
1381 alu.dst.write = 1;
1382 if (j == so->output[i].num_components - 1)
1383 alu.last = 1;
1384 r = r600_bytecode_add_alu(ctx->bc, &alu);
1385 if (r)
1386 return r;
1387 }
1388 start_comp[i] = 0;
1389 so_gpr[i] = tmp;
1390 }
1391 }
1392
1393 /* Write outputs to buffers. */
1394 for (i = 0; i < so->num_outputs; i++) {
1395 struct r600_bytecode_output output;
1396
1397 if (stream != -1 && stream != so->output[i].output_buffer)
1398 continue;
1399
1400 memset(&output, 0, sizeof(struct r600_bytecode_output));
1401 output.gpr = so_gpr[i];
1402 output.elem_size = so->output[i].num_components - 1;
1403 if (output.elem_size == 2)
1404 output.elem_size = 3; // 3 not supported, write 4 with junk at end
1405 output.array_base = so->output[i].dst_offset - start_comp[i];
1406 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1407 output.burst_count = 1;
1408 /* array_size is an upper limit for the burst_count
1409 * with MEM_STREAM instructions */
1410 output.array_size = 0xFFF;
1411 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
1412
1413 if (ctx->bc->chip_class >= EVERGREEN) {
1414 switch (so->output[i].output_buffer) {
1415 case 0:
1416 output.op = CF_OP_MEM_STREAM0_BUF0;
1417 break;
1418 case 1:
1419 output.op = CF_OP_MEM_STREAM0_BUF1;
1420 break;
1421 case 2:
1422 output.op = CF_OP_MEM_STREAM0_BUF2;
1423 break;
1424 case 3:
1425 output.op = CF_OP_MEM_STREAM0_BUF3;
1426 break;
1427 }
1428 output.op += so->output[i].stream * 4;
1429 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
1430 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
1431 } else {
1432 switch (so->output[i].output_buffer) {
1433 case 0:
1434 output.op = CF_OP_MEM_STREAM0;
1435 break;
1436 case 1:
1437 output.op = CF_OP_MEM_STREAM1;
1438 break;
1439 case 2:
1440 output.op = CF_OP_MEM_STREAM2;
1441 break;
1442 case 3:
1443 output.op = CF_OP_MEM_STREAM3;
1444 break;
1445 }
1446 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
1447 }
1448 r = r600_bytecode_add_output(ctx->bc, &output);
1449 if (r)
1450 goto out_err;
1451 }
1452 return 0;
1453 out_err:
1454 return r;
1455 }
1456
1457 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
1458 {
1459 struct r600_bytecode_alu alu;
1460 unsigned reg;
1461
1462 if (!ctx->shader->vs_out_edgeflag)
1463 return;
1464
1465 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
1466
1467 /* clamp(x, 0, 1) */
1468 memset(&alu, 0, sizeof(alu));
1469 alu.op = ALU_OP1_MOV;
1470 alu.src[0].sel = reg;
1471 alu.dst.sel = reg;
1472 alu.dst.write = 1;
1473 alu.dst.clamp = 1;
1474 alu.last = 1;
1475 r600_bytecode_add_alu(ctx->bc, &alu);
1476
1477 memset(&alu, 0, sizeof(alu));
1478 alu.op = ALU_OP1_FLT_TO_INT;
1479 alu.src[0].sel = reg;
1480 alu.dst.sel = reg;
1481 alu.dst.write = 1;
1482 alu.last = 1;
1483 r600_bytecode_add_alu(ctx->bc, &alu);
1484 }
1485
1486 static int generate_gs_copy_shader(struct r600_context *rctx,
1487 struct r600_pipe_shader *gs,
1488 struct pipe_stream_output_info *so)
1489 {
1490 struct r600_shader_ctx ctx = {};
1491 struct r600_shader *gs_shader = &gs->shader;
1492 struct r600_pipe_shader *cshader;
1493 int ocnt = gs_shader->noutput;
1494 struct r600_bytecode_alu alu;
1495 struct r600_bytecode_vtx vtx;
1496 struct r600_bytecode_output output;
1497 struct r600_bytecode_cf *cf_jump, *cf_pop,
1498 *last_exp_pos = NULL, *last_exp_param = NULL;
1499 int i, j, next_clip_pos = 61, next_param = 0;
1500 int ring;
1501
1502 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1503 if (!cshader)
1504 return 0;
1505
1506 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1507 sizeof(struct r600_shader_io));
1508
1509 cshader->shader.noutput = ocnt;
1510
1511 ctx.shader = &cshader->shader;
1512 ctx.bc = &ctx.shader->bc;
1513 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1514
1515 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1516 rctx->screen->has_compressed_msaa_texturing);
1517
1518 ctx.bc->isa = rctx->isa;
1519
1520 cf_jump = NULL;
1521 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
1522
1523 /* R0.x = R0.x & 0x3fffffff */
1524 memset(&alu, 0, sizeof(alu));
1525 alu.op = ALU_OP2_AND_INT;
1526 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1527 alu.src[1].value = 0x3fffffff;
1528 alu.dst.write = 1;
1529 r600_bytecode_add_alu(ctx.bc, &alu);
1530
1531 /* R0.y = R0.x >> 30 */
1532 memset(&alu, 0, sizeof(alu));
1533 alu.op = ALU_OP2_LSHR_INT;
1534 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1535 alu.src[1].value = 0x1e;
1536 alu.dst.chan = 1;
1537 alu.dst.write = 1;
1538 alu.last = 1;
1539 r600_bytecode_add_alu(ctx.bc, &alu);
1540
1541 /* fetch vertex data from GSVS ring */
1542 for (i = 0; i < ocnt; ++i) {
1543 struct r600_shader_io *out = &ctx.shader->output[i];
1544
1545 out->gpr = i + 1;
1546 out->ring_offset = i * 16;
1547
1548 memset(&vtx, 0, sizeof(vtx));
1549 vtx.op = FETCH_OP_VFETCH;
1550 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1551 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1552 vtx.offset = out->ring_offset;
1553 vtx.dst_gpr = out->gpr;
1554 vtx.src_gpr = 0;
1555 vtx.dst_sel_x = 0;
1556 vtx.dst_sel_y = 1;
1557 vtx.dst_sel_z = 2;
1558 vtx.dst_sel_w = 3;
1559 if (rctx->b.chip_class >= EVERGREEN) {
1560 vtx.use_const_fields = 1;
1561 } else {
1562 vtx.data_format = FMT_32_32_32_32_FLOAT;
1563 }
1564
1565 r600_bytecode_add_vtx(ctx.bc, &vtx);
1566 }
1567 ctx.temp_reg = i + 1;
1568 for (ring = 3; ring >= 0; --ring) {
1569 bool enabled = false;
1570 for (i = 0; i < so->num_outputs; i++) {
1571 if (so->output[i].stream == ring) {
1572 enabled = true;
1573 break;
1574 }
1575 }
1576 if (ring != 0 && !enabled) {
1577 cshader->shader.ring_item_sizes[ring] = 0;
1578 continue;
1579 }
1580
1581 if (cf_jump) {
1582 // Patch up jump label
1583 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1584 cf_pop = ctx.bc->cf_last;
1585
1586 cf_jump->cf_addr = cf_pop->id + 2;
1587 cf_jump->pop_count = 1;
1588 cf_pop->cf_addr = cf_pop->id + 2;
1589 cf_pop->pop_count = 1;
1590 }
1591
1592 /* PRED_SETE_INT __, R0.y, ring */
1593 memset(&alu, 0, sizeof(alu));
1594 alu.op = ALU_OP2_PRED_SETE_INT;
1595 alu.src[0].chan = 1;
1596 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1597 alu.src[1].value = ring;
1598 alu.execute_mask = 1;
1599 alu.update_pred = 1;
1600 alu.last = 1;
1601 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1602
1603 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1604 cf_jump = ctx.bc->cf_last;
1605
1606 if (enabled)
1607 emit_streamout(&ctx, so, ring, &cshader->shader.ring_item_sizes[ring]);
1608 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
1609 }
1610
1611 /* export vertex data */
1612 /* XXX factor out common code with r600_shader_from_tgsi ? */
1613 for (i = 0; i < ocnt; ++i) {
1614 struct r600_shader_io *out = &ctx.shader->output[i];
1615 bool instream0 = true;
1616 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1617 continue;
1618
1619 for (j = 0; j < so->num_outputs; j++) {
1620 if (so->output[j].register_index == i) {
1621 if (so->output[j].stream == 0)
1622 break;
1623 if (so->output[j].stream > 0)
1624 instream0 = false;
1625 }
1626 }
1627 if (!instream0)
1628 continue;
1629 memset(&output, 0, sizeof(output));
1630 output.gpr = out->gpr;
1631 output.elem_size = 3;
1632 output.swizzle_x = 0;
1633 output.swizzle_y = 1;
1634 output.swizzle_z = 2;
1635 output.swizzle_w = 3;
1636 output.burst_count = 1;
1637 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1638 output.op = CF_OP_EXPORT;
1639 switch (out->name) {
1640 case TGSI_SEMANTIC_POSITION:
1641 output.array_base = 60;
1642 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1643 break;
1644
1645 case TGSI_SEMANTIC_PSIZE:
1646 output.array_base = 61;
1647 if (next_clip_pos == 61)
1648 next_clip_pos = 62;
1649 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1650 output.swizzle_y = 7;
1651 output.swizzle_z = 7;
1652 output.swizzle_w = 7;
1653 ctx.shader->vs_out_misc_write = 1;
1654 ctx.shader->vs_out_point_size = 1;
1655 break;
1656 case TGSI_SEMANTIC_LAYER:
1657 if (out->spi_sid) {
1658 /* duplicate it as PARAM to pass to the pixel shader */
1659 output.array_base = next_param++;
1660 r600_bytecode_add_output(ctx.bc, &output);
1661 last_exp_param = ctx.bc->cf_last;
1662 }
1663 output.array_base = 61;
1664 if (next_clip_pos == 61)
1665 next_clip_pos = 62;
1666 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1667 output.swizzle_x = 7;
1668 output.swizzle_y = 7;
1669 output.swizzle_z = 0;
1670 output.swizzle_w = 7;
1671 ctx.shader->vs_out_misc_write = 1;
1672 ctx.shader->vs_out_layer = 1;
1673 break;
1674 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1675 if (out->spi_sid) {
1676 /* duplicate it as PARAM to pass to the pixel shader */
1677 output.array_base = next_param++;
1678 r600_bytecode_add_output(ctx.bc, &output);
1679 last_exp_param = ctx.bc->cf_last;
1680 }
1681 output.array_base = 61;
1682 if (next_clip_pos == 61)
1683 next_clip_pos = 62;
1684 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1685 ctx.shader->vs_out_misc_write = 1;
1686 ctx.shader->vs_out_viewport = 1;
1687 output.swizzle_x = 7;
1688 output.swizzle_y = 7;
1689 output.swizzle_z = 7;
1690 output.swizzle_w = 0;
1691 break;
1692 case TGSI_SEMANTIC_CLIPDIST:
1693 /* spi_sid is 0 for clipdistance outputs that were generated
1694 * for clipvertex - we don't need to pass them to PS */
1695 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
1696 if (out->spi_sid) {
1697 /* duplicate it as PARAM to pass to the pixel shader */
1698 output.array_base = next_param++;
1699 r600_bytecode_add_output(ctx.bc, &output);
1700 last_exp_param = ctx.bc->cf_last;
1701 }
1702 output.array_base = next_clip_pos++;
1703 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1704 break;
1705 case TGSI_SEMANTIC_FOG:
1706 output.swizzle_y = 4; /* 0 */
1707 output.swizzle_z = 4; /* 0 */
1708 output.swizzle_w = 5; /* 1 */
1709 break;
1710 default:
1711 output.array_base = next_param++;
1712 break;
1713 }
1714 r600_bytecode_add_output(ctx.bc, &output);
1715 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1716 last_exp_param = ctx.bc->cf_last;
1717 else
1718 last_exp_pos = ctx.bc->cf_last;
1719 }
1720
1721 if (!last_exp_pos) {
1722 memset(&output, 0, sizeof(output));
1723 output.gpr = 0;
1724 output.elem_size = 3;
1725 output.swizzle_x = 7;
1726 output.swizzle_y = 7;
1727 output.swizzle_z = 7;
1728 output.swizzle_w = 7;
1729 output.burst_count = 1;
1730 output.type = 2;
1731 output.op = CF_OP_EXPORT;
1732 output.array_base = 60;
1733 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1734 r600_bytecode_add_output(ctx.bc, &output);
1735 last_exp_pos = ctx.bc->cf_last;
1736 }
1737
1738 if (!last_exp_param) {
1739 memset(&output, 0, sizeof(output));
1740 output.gpr = 0;
1741 output.elem_size = 3;
1742 output.swizzle_x = 7;
1743 output.swizzle_y = 7;
1744 output.swizzle_z = 7;
1745 output.swizzle_w = 7;
1746 output.burst_count = 1;
1747 output.type = 2;
1748 output.op = CF_OP_EXPORT;
1749 output.array_base = next_param++;
1750 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1751 r600_bytecode_add_output(ctx.bc, &output);
1752 last_exp_param = ctx.bc->cf_last;
1753 }
1754
1755 last_exp_pos->op = CF_OP_EXPORT_DONE;
1756 last_exp_param->op = CF_OP_EXPORT_DONE;
1757
1758 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1759 cf_pop = ctx.bc->cf_last;
1760
1761 cf_jump->cf_addr = cf_pop->id + 2;
1762 cf_jump->pop_count = 1;
1763 cf_pop->cf_addr = cf_pop->id + 2;
1764 cf_pop->pop_count = 1;
1765
1766 if (ctx.bc->chip_class == CAYMAN)
1767 cm_bytecode_add_cf_end(ctx.bc);
1768 else {
1769 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1770 ctx.bc->cf_last->end_of_program = 1;
1771 }
1772
1773 gs->gs_copy_shader = cshader;
1774 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
1775
1776 ctx.bc->nstack = 1;
1777
1778 return r600_bytecode_build(ctx.bc);
1779 }
1780
1781 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
1782 {
1783 struct r600_bytecode_output output;
1784 int i, k, ring_offset;
1785 int effective_stream = stream == -1 ? 0 : stream;
1786 int idx = 0;
1787
1788 for (i = 0; i < ctx->shader->noutput; i++) {
1789 if (ctx->gs_for_vs) {
1790 /* for ES we need to lookup corresponding ring offset expected by GS
1791 * (map this output to GS input by name and sid) */
1792 /* FIXME precompute offsets */
1793 ring_offset = -1;
1794 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1795 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1796 struct r600_shader_io *out = &ctx->shader->output[i];
1797 if (in->name == out->name && in->sid == out->sid)
1798 ring_offset = in->ring_offset;
1799 }
1800
1801 if (ring_offset == -1)
1802 continue;
1803 } else {
1804 ring_offset = idx * 16;
1805 idx++;
1806 }
1807
1808 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
1809 continue;
1810 /* next_ring_offset after parsing input decls contains total size of
1811 * single vertex data, gs_next_vertex - current vertex index */
1812 if (!ind)
1813 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
1814
1815 memset(&output, 0, sizeof(struct r600_bytecode_output));
1816 output.gpr = ctx->shader->output[i].gpr;
1817 output.elem_size = 3;
1818 output.comp_mask = 0xF;
1819 output.burst_count = 1;
1820
1821 if (ind)
1822 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
1823 else
1824 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1825
1826 switch (stream) {
1827 default:
1828 case 0:
1829 output.op = CF_OP_MEM_RING; break;
1830 case 1:
1831 output.op = CF_OP_MEM_RING1; break;
1832 case 2:
1833 output.op = CF_OP_MEM_RING2; break;
1834 case 3:
1835 output.op = CF_OP_MEM_RING3; break;
1836 }
1837
1838 if (ind) {
1839 output.array_base = ring_offset >> 2; /* in dwords */
1840 output.array_size = 0xfff;
1841 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
1842 } else
1843 output.array_base = ring_offset >> 2; /* in dwords */
1844 r600_bytecode_add_output(ctx->bc, &output);
1845 }
1846
1847 if (ind) {
1848 /* get a temp and add the ring offset to the next vertex base in the shader */
1849 struct r600_bytecode_alu alu;
1850 int r;
1851
1852 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1853 alu.op = ALU_OP2_ADD_INT;
1854 alu.src[0].sel = ctx->gs_export_gpr_tregs[effective_stream];
1855 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1856 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
1857 alu.dst.sel = ctx->gs_export_gpr_tregs[effective_stream];
1858 alu.dst.write = 1;
1859 alu.last = 1;
1860 r = r600_bytecode_add_alu(ctx->bc, &alu);
1861 if (r)
1862 return r;
1863 }
1864 ++ctx->gs_next_vertex;
1865 return 0;
1866 }
1867
1868 static int r600_shader_from_tgsi(struct r600_context *rctx,
1869 struct r600_pipe_shader *pipeshader,
1870 union r600_shader_key key)
1871 {
1872 struct r600_screen *rscreen = rctx->screen;
1873 struct r600_shader *shader = &pipeshader->shader;
1874 struct tgsi_token *tokens = pipeshader->selector->tokens;
1875 struct pipe_stream_output_info so = pipeshader->selector->so;
1876 struct tgsi_full_immediate *immediate;
1877 struct r600_shader_ctx ctx;
1878 struct r600_bytecode_output output[32];
1879 unsigned output_done, noutput;
1880 unsigned opcode;
1881 int i, j, k, r = 0;
1882 int next_param_base = 0, next_clip_base;
1883 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
1884 /* Declarations used by llvm code */
1885 bool use_llvm = false;
1886 bool indirect_gprs;
1887 bool ring_outputs = false;
1888 bool pos_emitted = false;
1889
1890 #ifdef R600_USE_LLVM
1891 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
1892 #endif
1893 ctx.bc = &shader->bc;
1894 ctx.shader = shader;
1895 ctx.native_integers = true;
1896
1897
1898 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
1899 rscreen->has_compressed_msaa_texturing);
1900 ctx.tokens = tokens;
1901 tgsi_scan_shader(tokens, &ctx.info);
1902 shader->indirect_files = ctx.info.indirect_files;
1903
1904 shader->uses_doubles = ctx.info.uses_doubles;
1905
1906 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
1907 tgsi_parse_init(&ctx.parse, tokens);
1908 ctx.type = ctx.info.processor;
1909 shader->processor_type = ctx.type;
1910 ctx.bc->type = shader->processor_type;
1911
1912 switch (ctx.type) {
1913 case TGSI_PROCESSOR_VERTEX:
1914 shader->vs_as_gs_a = key.vs.as_gs_a;
1915 shader->vs_as_es = key.vs.as_es;
1916 if (shader->vs_as_es)
1917 ring_outputs = true;
1918 break;
1919 case TGSI_PROCESSOR_GEOMETRY:
1920 ring_outputs = true;
1921 break;
1922 case TGSI_PROCESSOR_FRAGMENT:
1923 shader->two_side = key.ps.color_two_side;
1924 break;
1925 default:
1926 break;
1927 }
1928
1929 if (shader->vs_as_es) {
1930 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
1931 } else {
1932 ctx.gs_for_vs = NULL;
1933 }
1934
1935 ctx.next_ring_offset = 0;
1936 ctx.gs_out_ring_offset = 0;
1937 ctx.gs_next_vertex = 0;
1938 ctx.gs_stream_output_info = &so;
1939
1940 ctx.face_gpr = -1;
1941 ctx.fixed_pt_position_gpr = -1;
1942 ctx.fragcoord_input = -1;
1943 ctx.colors_used = 0;
1944 ctx.clip_vertex_write = 0;
1945
1946 shader->nr_ps_color_exports = 0;
1947 shader->nr_ps_max_color_exports = 0;
1948
1949
1950 /* register allocations */
1951 /* Values [0,127] correspond to GPR[0..127].
1952 * Values [128,159] correspond to constant buffer bank 0
1953 * Values [160,191] correspond to constant buffer bank 1
1954 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1955 * Values [256,287] correspond to constant buffer bank 2 (EG)
1956 * Values [288,319] correspond to constant buffer bank 3 (EG)
1957 * Other special values are shown in the list below.
1958 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1959 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1960 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1961 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1962 * 248 SQ_ALU_SRC_0: special constant 0.0.
1963 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1964 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1965 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1966 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1967 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1968 * 254 SQ_ALU_SRC_PV: previous vector result.
1969 * 255 SQ_ALU_SRC_PS: previous scalar result.
1970 */
1971 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1972 ctx.file_offset[i] = 0;
1973 }
1974
1975 #ifdef R600_USE_LLVM
1976 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1977 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1978 "indirect adressing. Falling back to TGSI "
1979 "backend.\n");
1980 use_llvm = 0;
1981 }
1982 #endif
1983 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1984 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1985 if (!use_llvm) {
1986 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1987 }
1988 }
1989 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
1990 if (ctx.bc->chip_class >= EVERGREEN)
1991 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1992 else
1993 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
1994 }
1995 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1996 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
1997 ctx.file_offset[TGSI_FILE_INPUT] = 2;
1998 }
1999 ctx.use_llvm = use_llvm;
2000
2001 if (use_llvm) {
2002 ctx.file_offset[TGSI_FILE_OUTPUT] =
2003 ctx.file_offset[TGSI_FILE_INPUT];
2004 } else {
2005 ctx.file_offset[TGSI_FILE_OUTPUT] =
2006 ctx.file_offset[TGSI_FILE_INPUT] +
2007 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2008 }
2009 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
2010 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
2011
2012 /* Outside the GPR range. This will be translated to one of the
2013 * kcache banks later. */
2014 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
2015
2016 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
2017 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
2018 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
2019 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
2020 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
2021
2022 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2023 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
2024 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
2025 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
2026 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
2027 ctx.temp_reg = ctx.bc->ar_reg + 7;
2028 } else {
2029 ctx.temp_reg = ctx.bc->ar_reg + 3;
2030 }
2031
2032 shader->max_arrays = 0;
2033 shader->num_arrays = 0;
2034 if (indirect_gprs) {
2035
2036 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
2037 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
2038 ctx.file_offset[TGSI_FILE_OUTPUT] -
2039 ctx.file_offset[TGSI_FILE_INPUT],
2040 0x0F);
2041 }
2042 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
2043 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
2044 ctx.file_offset[TGSI_FILE_TEMPORARY] -
2045 ctx.file_offset[TGSI_FILE_OUTPUT],
2046 0x0F);
2047 }
2048 }
2049
2050 ctx.nliterals = 0;
2051 ctx.literals = NULL;
2052
2053 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS];
2054 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2055 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
2056
2057 if (shader->vs_as_gs_a)
2058 vs_add_primid_output(&ctx, key.vs.prim_id_out);
2059
2060 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2061 tgsi_parse_token(&ctx.parse);
2062 switch (ctx.parse.FullToken.Token.Type) {
2063 case TGSI_TOKEN_TYPE_IMMEDIATE:
2064 immediate = &ctx.parse.FullToken.FullImmediate;
2065 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
2066 if(ctx.literals == NULL) {
2067 r = -ENOMEM;
2068 goto out_err;
2069 }
2070 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
2071 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
2072 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
2073 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
2074 ctx.nliterals++;
2075 break;
2076 case TGSI_TOKEN_TYPE_DECLARATION:
2077 r = tgsi_declaration(&ctx);
2078 if (r)
2079 goto out_err;
2080 break;
2081 case TGSI_TOKEN_TYPE_INSTRUCTION:
2082 case TGSI_TOKEN_TYPE_PROPERTY:
2083 break;
2084 default:
2085 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
2086 r = -EINVAL;
2087 goto out_err;
2088 }
2089 }
2090
2091 shader->ring_item_sizes[0] = ctx.next_ring_offset;
2092 shader->ring_item_sizes[1] = 0;
2093 shader->ring_item_sizes[2] = 0;
2094 shader->ring_item_sizes[3] = 0;
2095
2096 /* Process two side if needed */
2097 if (shader->two_side && ctx.colors_used) {
2098 int i, count = ctx.shader->ninput;
2099 unsigned next_lds_loc = ctx.shader->nlds;
2100
2101 /* additional inputs will be allocated right after the existing inputs,
2102 * we won't need them after the color selection, so we don't need to
2103 * reserve these gprs for the rest of the shader code and to adjust
2104 * output offsets etc. */
2105 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
2106 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2107
2108 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
2109 if (ctx.face_gpr == -1) {
2110 i = ctx.shader->ninput++;
2111 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
2112 ctx.shader->input[i].spi_sid = 0;
2113 ctx.shader->input[i].gpr = gpr++;
2114 ctx.face_gpr = ctx.shader->input[i].gpr;
2115 }
2116
2117 for (i = 0; i < count; i++) {
2118 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2119 int ni = ctx.shader->ninput++;
2120 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
2121 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
2122 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
2123 ctx.shader->input[ni].gpr = gpr++;
2124 // TGSI to LLVM needs to know the lds position of inputs.
2125 // Non LLVM path computes it later (in process_twoside_color)
2126 ctx.shader->input[ni].lds_pos = next_lds_loc++;
2127 ctx.shader->input[i].back_color_input = ni;
2128 if (ctx.bc->chip_class >= EVERGREEN) {
2129 if ((r = evergreen_interp_input(&ctx, ni)))
2130 return r;
2131 }
2132 }
2133 }
2134 }
2135
2136 /* LLVM backend setup */
2137 #ifdef R600_USE_LLVM
2138 if (use_llvm) {
2139 struct radeon_llvm_context radeon_llvm_ctx;
2140 LLVMModuleRef mod;
2141 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
2142 boolean use_kill = false;
2143
2144 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
2145 radeon_llvm_ctx.type = ctx.type;
2146 radeon_llvm_ctx.two_side = shader->two_side;
2147 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
2148 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
2149 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
2150 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
2151 radeon_llvm_ctx.color_buffer_count = max_color_exports;
2152 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
2153 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
2154 radeon_llvm_ctx.stream_outputs = &so;
2155 radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
2156 radeon_llvm_ctx.has_compressed_msaa_texturing =
2157 ctx.bc->has_compressed_msaa_texturing;
2158 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
2159 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
2160 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
2161
2162 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
2163 radeon_llvm_dispose(&radeon_llvm_ctx);
2164 use_llvm = 0;
2165 fprintf(stderr, "R600 LLVM backend failed to compile "
2166 "shader. Falling back to TGSI\n");
2167 } else {
2168 ctx.file_offset[TGSI_FILE_OUTPUT] =
2169 ctx.file_offset[TGSI_FILE_INPUT];
2170 }
2171 if (use_kill)
2172 ctx.shader->uses_kill = use_kill;
2173 radeon_llvm_dispose(&radeon_llvm_ctx);
2174 }
2175 #endif
2176 /* End of LLVM backend setup */
2177
2178 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
2179 shader->nr_ps_max_color_exports = 8;
2180
2181 if (!use_llvm) {
2182 if (ctx.fragcoord_input >= 0) {
2183 if (ctx.bc->chip_class == CAYMAN) {
2184 for (j = 0 ; j < 4; j++) {
2185 struct r600_bytecode_alu alu;
2186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2187 alu.op = ALU_OP1_RECIP_IEEE;
2188 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2189 alu.src[0].chan = 3;
2190
2191 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2192 alu.dst.chan = j;
2193 alu.dst.write = (j == 3);
2194 alu.last = 1;
2195 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2196 return r;
2197 }
2198 } else {
2199 struct r600_bytecode_alu alu;
2200 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2201 alu.op = ALU_OP1_RECIP_IEEE;
2202 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2203 alu.src[0].chan = 3;
2204
2205 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2206 alu.dst.chan = 3;
2207 alu.dst.write = 1;
2208 alu.last = 1;
2209 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2210 return r;
2211 }
2212 }
2213
2214 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2215 struct r600_bytecode_alu alu;
2216 int r;
2217 for (j = 0; j < 4; j++) {
2218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2219 alu.op = ALU_OP1_MOV;
2220 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2221 alu.src[0].value = 0;
2222 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
2223 alu.dst.write = 1;
2224 alu.last = 1;
2225 r = r600_bytecode_add_alu(ctx.bc, &alu);
2226 if (r)
2227 return r;
2228 }
2229 }
2230 if (shader->two_side && ctx.colors_used) {
2231 if ((r = process_twoside_color_inputs(&ctx)))
2232 return r;
2233 }
2234
2235 tgsi_parse_init(&ctx.parse, tokens);
2236 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2237 tgsi_parse_token(&ctx.parse);
2238 switch (ctx.parse.FullToken.Token.Type) {
2239 case TGSI_TOKEN_TYPE_INSTRUCTION:
2240 r = tgsi_is_supported(&ctx);
2241 if (r)
2242 goto out_err;
2243 ctx.max_driver_temp_used = 0;
2244 /* reserve first tmp for everyone */
2245 r600_get_temp(&ctx);
2246
2247 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
2248 if ((r = tgsi_split_constant(&ctx)))
2249 goto out_err;
2250 if ((r = tgsi_split_literal_constant(&ctx)))
2251 goto out_err;
2252 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
2253 if ((r = tgsi_split_gs_inputs(&ctx)))
2254 goto out_err;
2255 if (ctx.bc->chip_class == CAYMAN)
2256 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
2257 else if (ctx.bc->chip_class >= EVERGREEN)
2258 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
2259 else
2260 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
2261 r = ctx.inst_info->process(&ctx);
2262 if (r)
2263 goto out_err;
2264 break;
2265 default:
2266 break;
2267 }
2268 }
2269 }
2270
2271 /* Reset the temporary register counter. */
2272 ctx.max_driver_temp_used = 0;
2273
2274 noutput = shader->noutput;
2275
2276 if (!ring_outputs && ctx.clip_vertex_write) {
2277 unsigned clipdist_temp[2];
2278
2279 clipdist_temp[0] = r600_get_temp(&ctx);
2280 clipdist_temp[1] = r600_get_temp(&ctx);
2281
2282 /* need to convert a clipvertex write into clipdistance writes and not export
2283 the clip vertex anymore */
2284
2285 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
2286 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2287 shader->output[noutput].gpr = clipdist_temp[0];
2288 noutput++;
2289 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2290 shader->output[noutput].gpr = clipdist_temp[1];
2291 noutput++;
2292
2293 /* reset spi_sid for clipvertex output to avoid confusing spi */
2294 shader->output[ctx.cv_output].spi_sid = 0;
2295
2296 shader->clip_dist_write = 0xFF;
2297
2298 for (i = 0; i < 8; i++) {
2299 int oreg = i >> 2;
2300 int ochan = i & 3;
2301
2302 for (j = 0; j < 4; j++) {
2303 struct r600_bytecode_alu alu;
2304 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2305 alu.op = ALU_OP2_DOT4;
2306 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
2307 alu.src[0].chan = j;
2308
2309 alu.src[1].sel = 512 + i;
2310 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
2311 alu.src[1].chan = j;
2312
2313 alu.dst.sel = clipdist_temp[oreg];
2314 alu.dst.chan = j;
2315 alu.dst.write = (j == ochan);
2316 if (j == 3)
2317 alu.last = 1;
2318 if (!use_llvm)
2319 r = r600_bytecode_add_alu(ctx.bc, &alu);
2320 if (r)
2321 return r;
2322 }
2323 }
2324 }
2325
2326 /* Add stream outputs. */
2327 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
2328 so.num_outputs && !use_llvm)
2329 emit_streamout(&ctx, &so, -1, NULL);
2330
2331 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2332 convert_edgeflag_to_int(&ctx);
2333
2334 if (ring_outputs) {
2335 if (shader->vs_as_es) {
2336 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
2337 ctx.gs_export_gpr_tregs[1] = -1;
2338 ctx.gs_export_gpr_tregs[2] = -1;
2339 ctx.gs_export_gpr_tregs[3] = -1;
2340
2341 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
2342 }
2343 } else {
2344 /* Export output */
2345 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
2346
2347 for (i = 0, j = 0; i < noutput; i++, j++) {
2348 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2349 output[j].gpr = shader->output[i].gpr;
2350 output[j].elem_size = 3;
2351 output[j].swizzle_x = 0;
2352 output[j].swizzle_y = 1;
2353 output[j].swizzle_z = 2;
2354 output[j].swizzle_w = 3;
2355 output[j].burst_count = 1;
2356 output[j].type = -1;
2357 output[j].op = CF_OP_EXPORT;
2358 switch (ctx.type) {
2359 case TGSI_PROCESSOR_VERTEX:
2360 switch (shader->output[i].name) {
2361 case TGSI_SEMANTIC_POSITION:
2362 output[j].array_base = 60;
2363 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2364 pos_emitted = true;
2365 break;
2366
2367 case TGSI_SEMANTIC_PSIZE:
2368 output[j].array_base = 61;
2369 output[j].swizzle_y = 7;
2370 output[j].swizzle_z = 7;
2371 output[j].swizzle_w = 7;
2372 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2373 pos_emitted = true;
2374 break;
2375 case TGSI_SEMANTIC_EDGEFLAG:
2376 output[j].array_base = 61;
2377 output[j].swizzle_x = 7;
2378 output[j].swizzle_y = 0;
2379 output[j].swizzle_z = 7;
2380 output[j].swizzle_w = 7;
2381 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2382 pos_emitted = true;
2383 break;
2384 case TGSI_SEMANTIC_LAYER:
2385 /* spi_sid is 0 for outputs that are
2386 * not consumed by PS */
2387 if (shader->output[i].spi_sid) {
2388 output[j].array_base = next_param_base++;
2389 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2390 j++;
2391 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2392 }
2393 output[j].array_base = 61;
2394 output[j].swizzle_x = 7;
2395 output[j].swizzle_y = 7;
2396 output[j].swizzle_z = 0;
2397 output[j].swizzle_w = 7;
2398 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2399 pos_emitted = true;
2400 break;
2401 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2402 /* spi_sid is 0 for outputs that are
2403 * not consumed by PS */
2404 if (shader->output[i].spi_sid) {
2405 output[j].array_base = next_param_base++;
2406 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2407 j++;
2408 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2409 }
2410 output[j].array_base = 61;
2411 output[j].swizzle_x = 7;
2412 output[j].swizzle_y = 7;
2413 output[j].swizzle_z = 7;
2414 output[j].swizzle_w = 0;
2415 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2416 pos_emitted = true;
2417 break;
2418 case TGSI_SEMANTIC_CLIPVERTEX:
2419 j--;
2420 break;
2421 case TGSI_SEMANTIC_CLIPDIST:
2422 output[j].array_base = next_clip_base++;
2423 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2424 pos_emitted = true;
2425 /* spi_sid is 0 for clipdistance outputs that were generated
2426 * for clipvertex - we don't need to pass them to PS */
2427 if (shader->output[i].spi_sid) {
2428 j++;
2429 /* duplicate it as PARAM to pass to the pixel shader */
2430 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2431 output[j].array_base = next_param_base++;
2432 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2433 }
2434 break;
2435 case TGSI_SEMANTIC_FOG:
2436 output[j].swizzle_y = 4; /* 0 */
2437 output[j].swizzle_z = 4; /* 0 */
2438 output[j].swizzle_w = 5; /* 1 */
2439 break;
2440 case TGSI_SEMANTIC_PRIMID:
2441 output[j].swizzle_x = 2;
2442 output[j].swizzle_y = 4; /* 0 */
2443 output[j].swizzle_z = 4; /* 0 */
2444 output[j].swizzle_w = 4; /* 0 */
2445 break;
2446 }
2447
2448 break;
2449 case TGSI_PROCESSOR_FRAGMENT:
2450 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
2451 /* never export more colors than the number of CBs */
2452 if (shader->output[i].sid >= max_color_exports) {
2453 /* skip export */
2454 j--;
2455 continue;
2456 }
2457 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2458 output[j].array_base = shader->output[i].sid;
2459 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2460 shader->nr_ps_color_exports++;
2461 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
2462 for (k = 1; k < max_color_exports; k++) {
2463 j++;
2464 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2465 output[j].gpr = shader->output[i].gpr;
2466 output[j].elem_size = 3;
2467 output[j].swizzle_x = 0;
2468 output[j].swizzle_y = 1;
2469 output[j].swizzle_z = 2;
2470 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2471 output[j].burst_count = 1;
2472 output[j].array_base = k;
2473 output[j].op = CF_OP_EXPORT;
2474 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2475 shader->nr_ps_color_exports++;
2476 }
2477 }
2478 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
2479 output[j].array_base = 61;
2480 output[j].swizzle_x = 2;
2481 output[j].swizzle_y = 7;
2482 output[j].swizzle_z = output[j].swizzle_w = 7;
2483 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2484 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2485 output[j].array_base = 61;
2486 output[j].swizzle_x = 7;
2487 output[j].swizzle_y = 1;
2488 output[j].swizzle_z = output[j].swizzle_w = 7;
2489 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2490 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2491 output[j].array_base = 61;
2492 output[j].swizzle_x = 7;
2493 output[j].swizzle_y = 7;
2494 output[j].swizzle_z = 0;
2495 output[j].swizzle_w = 7;
2496 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2497 } else {
2498 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
2499 r = -EINVAL;
2500 goto out_err;
2501 }
2502 break;
2503 default:
2504 R600_ERR("unsupported processor type %d\n", ctx.type);
2505 r = -EINVAL;
2506 goto out_err;
2507 }
2508
2509 if (output[j].type==-1) {
2510 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2511 output[j].array_base = next_param_base++;
2512 }
2513 }
2514
2515 /* add fake position export */
2516 if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
2517 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2518 output[j].gpr = 0;
2519 output[j].elem_size = 3;
2520 output[j].swizzle_x = 7;
2521 output[j].swizzle_y = 7;
2522 output[j].swizzle_z = 7;
2523 output[j].swizzle_w = 7;
2524 output[j].burst_count = 1;
2525 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2526 output[j].array_base = 60;
2527 output[j].op = CF_OP_EXPORT;
2528 j++;
2529 }
2530
2531 /* add fake param output for vertex shader if no param is exported */
2532 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
2533 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2534 output[j].gpr = 0;
2535 output[j].elem_size = 3;
2536 output[j].swizzle_x = 7;
2537 output[j].swizzle_y = 7;
2538 output[j].swizzle_z = 7;
2539 output[j].swizzle_w = 7;
2540 output[j].burst_count = 1;
2541 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2542 output[j].array_base = 0;
2543 output[j].op = CF_OP_EXPORT;
2544 j++;
2545 }
2546
2547 /* add fake pixel export */
2548 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
2549 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2550 output[j].gpr = 0;
2551 output[j].elem_size = 3;
2552 output[j].swizzle_x = 7;
2553 output[j].swizzle_y = 7;
2554 output[j].swizzle_z = 7;
2555 output[j].swizzle_w = 7;
2556 output[j].burst_count = 1;
2557 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2558 output[j].array_base = 0;
2559 output[j].op = CF_OP_EXPORT;
2560 j++;
2561 shader->nr_ps_color_exports++;
2562 }
2563
2564 noutput = j;
2565
2566 /* set export done on last export of each type */
2567 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
2568 if (!(output_done & (1 << output[i].type))) {
2569 output_done |= (1 << output[i].type);
2570 output[i].op = CF_OP_EXPORT_DONE;
2571 }
2572 }
2573 /* add output to bytecode */
2574 if (!use_llvm) {
2575 for (i = 0; i < noutput; i++) {
2576 r = r600_bytecode_add_output(ctx.bc, &output[i]);
2577 if (r)
2578 goto out_err;
2579 }
2580 }
2581 }
2582
2583 /* add program end */
2584 if (!use_llvm) {
2585 if (ctx.bc->chip_class == CAYMAN)
2586 cm_bytecode_add_cf_end(ctx.bc);
2587 else {
2588 const struct cf_op_info *last = NULL;
2589
2590 if (ctx.bc->cf_last)
2591 last = r600_isa_cf(ctx.bc->cf_last->op);
2592
2593 /* alu clause instructions don't have EOP bit, so add NOP */
2594 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
2595 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2596
2597 ctx.bc->cf_last->end_of_program = 1;
2598 }
2599 }
2600
2601 /* check GPR limit - we have 124 = 128 - 4
2602 * (4 are reserved as alu clause temporary registers) */
2603 if (ctx.bc->ngpr > 124) {
2604 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
2605 r = -ENOMEM;
2606 goto out_err;
2607 }
2608
2609 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2610 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
2611 return r;
2612 }
2613
2614 free(ctx.literals);
2615 tgsi_parse_free(&ctx.parse);
2616 return 0;
2617 out_err:
2618 free(ctx.literals);
2619 tgsi_parse_free(&ctx.parse);
2620 return r;
2621 }
2622
2623 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
2624 {
2625 const unsigned tgsi_opcode =
2626 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
2627 R600_ERR("%s tgsi opcode unsupported\n",
2628 tgsi_get_opcode_name(tgsi_opcode));
2629 return -EINVAL;
2630 }
2631
2632 static int tgsi_end(struct r600_shader_ctx *ctx)
2633 {
2634 return 0;
2635 }
2636
2637 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
2638 const struct r600_shader_src *shader_src,
2639 unsigned chan)
2640 {
2641 bc_src->sel = shader_src->sel;
2642 bc_src->chan = shader_src->swizzle[chan];
2643 bc_src->neg = shader_src->neg;
2644 bc_src->abs = shader_src->abs;
2645 bc_src->rel = shader_src->rel;
2646 bc_src->value = shader_src->value[bc_src->chan];
2647 bc_src->kc_bank = shader_src->kc_bank;
2648 bc_src->kc_rel = shader_src->kc_rel;
2649 }
2650
2651 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
2652 {
2653 bc_src->abs = 1;
2654 bc_src->neg = 0;
2655 }
2656
2657 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2658 {
2659 bc_src->neg = !bc_src->neg;
2660 }
2661
2662 static void tgsi_dst(struct r600_shader_ctx *ctx,
2663 const struct tgsi_full_dst_register *tgsi_dst,
2664 unsigned swizzle,
2665 struct r600_bytecode_alu_dst *r600_dst)
2666 {
2667 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2668
2669 r600_dst->sel = tgsi_dst->Register.Index;
2670 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2671 r600_dst->chan = swizzle;
2672 r600_dst->write = 1;
2673 if (tgsi_dst->Register.Indirect)
2674 r600_dst->rel = V_SQ_REL_RELATIVE;
2675 if (inst->Instruction.Saturate) {
2676 r600_dst->clamp = 1;
2677 }
2678 }
2679
2680 static int tgsi_last_instruction(unsigned writemask)
2681 {
2682 int i, lasti = 0;
2683
2684 for (i = 0; i < 4; i++) {
2685 if (writemask & (1 << i)) {
2686 lasti = i;
2687 }
2688 }
2689 return lasti;
2690 }
2691
2692
2693
2694 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
2695 {
2696 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2697 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2698 struct r600_bytecode_alu alu;
2699 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2700 int use_tmp = 0;
2701
2702 if (singledest) {
2703 switch (write_mask) {
2704 case 0x1:
2705 write_mask = 0x3;
2706 break;
2707 case 0x2:
2708 use_tmp = 1;
2709 write_mask = 0x3;
2710 break;
2711 case 0x4:
2712 write_mask = 0xc;
2713 break;
2714 case 0x8:
2715 write_mask = 0xc;
2716 use_tmp = 3;
2717 break;
2718 }
2719 }
2720
2721 lasti = tgsi_last_instruction(write_mask);
2722 for (i = 0; i <= lasti; i++) {
2723
2724 if (!(write_mask & (1 << i)))
2725 continue;
2726
2727 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2728
2729 if (singledest) {
2730 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2731 if (use_tmp) {
2732 alu.dst.sel = ctx->temp_reg;
2733 alu.dst.chan = i;
2734 alu.dst.write = 1;
2735 }
2736 if (i == 1 || i == 3)
2737 alu.dst.write = 0;
2738 } else
2739 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2740
2741 alu.op = ctx->inst_info->op;
2742 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
2743 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2744 } else if (!swap) {
2745 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2746 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
2747 }
2748 } else {
2749 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
2750 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
2751 }
2752
2753 /* handle some special cases */
2754 if (i == 1 || i == 3) {
2755 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
2756 case TGSI_OPCODE_SUB:
2757 r600_bytecode_src_toggle_neg(&alu.src[1]);
2758 break;
2759 case TGSI_OPCODE_DABS:
2760 r600_bytecode_src_set_abs(&alu.src[0]);
2761 break;
2762 default:
2763 break;
2764 }
2765 }
2766 if (i == lasti) {
2767 alu.last = 1;
2768 }
2769 r = r600_bytecode_add_alu(ctx->bc, &alu);
2770 if (r)
2771 return r;
2772 }
2773
2774 if (use_tmp) {
2775 write_mask = inst->Dst[0].Register.WriteMask;
2776
2777 /* move result from temp to dst */
2778 for (i = 0; i <= lasti; i++) {
2779 if (!(write_mask & (1 << i)))
2780 continue;
2781
2782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2783 alu.op = ALU_OP1_MOV;
2784 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2785 alu.src[0].sel = ctx->temp_reg;
2786 alu.src[0].chan = use_tmp - 1;
2787 alu.last = (i == lasti);
2788
2789 r = r600_bytecode_add_alu(ctx->bc, &alu);
2790 if (r)
2791 return r;
2792 }
2793 }
2794 return 0;
2795 }
2796
2797 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
2798 {
2799 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2800 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2801 /* confirm writemasking */
2802 if ((write_mask & 0x3) != 0x3 &&
2803 (write_mask & 0xc) != 0xc) {
2804 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
2805 return -1;
2806 }
2807 return tgsi_op2_64_params(ctx, false, false);
2808 }
2809
2810 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
2811 {
2812 return tgsi_op2_64_params(ctx, true, false);
2813 }
2814
2815 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
2816 {
2817 return tgsi_op2_64_params(ctx, true, true);
2818 }
2819
2820 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
2821 {
2822 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2823 struct r600_bytecode_alu alu;
2824 int i, j, r;
2825 int lasti = 3;
2826 int tmp = r600_get_temp(ctx);
2827
2828 for (i = 0; i < lasti + 1; i++) {
2829
2830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2831 alu.op = ctx->inst_info->op;
2832 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2833 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
2834 }
2835
2836 if (inst->Dst[0].Register.WriteMask & (1 << i))
2837 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2838 else
2839 alu.dst.sel = tmp;
2840
2841 alu.dst.chan = i;
2842 alu.is_op3 = 1;
2843 if (i == lasti) {
2844 alu.last = 1;
2845 }
2846 r = r600_bytecode_add_alu(ctx->bc, &alu);
2847 if (r)
2848 return r;
2849 }
2850 return 0;
2851 }
2852
2853 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
2854 {
2855 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2856 struct r600_bytecode_alu alu;
2857 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2858 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2859 /* use temp register if trans_only and more than one dst component */
2860 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
2861
2862 for (i = 0; i <= lasti; i++) {
2863 if (!(write_mask & (1 << i)))
2864 continue;
2865
2866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2867 if (use_tmp) {
2868 alu.dst.sel = ctx->temp_reg;
2869 alu.dst.chan = i;
2870 alu.dst.write = 1;
2871 } else
2872 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2873
2874 alu.op = ctx->inst_info->op;
2875 if (!swap) {
2876 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2877 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2878 }
2879 } else {
2880 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2881 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2882 }
2883 /* handle some special cases */
2884 switch (inst->Instruction.Opcode) {
2885 case TGSI_OPCODE_SUB:
2886 r600_bytecode_src_toggle_neg(&alu.src[1]);
2887 break;
2888 case TGSI_OPCODE_ABS:
2889 r600_bytecode_src_set_abs(&alu.src[0]);
2890 break;
2891 default:
2892 break;
2893 }
2894 if (i == lasti || trans_only) {
2895 alu.last = 1;
2896 }
2897 r = r600_bytecode_add_alu(ctx->bc, &alu);
2898 if (r)
2899 return r;
2900 }
2901
2902 if (use_tmp) {
2903 /* move result from temp to dst */
2904 for (i = 0; i <= lasti; i++) {
2905 if (!(write_mask & (1 << i)))
2906 continue;
2907
2908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2909 alu.op = ALU_OP1_MOV;
2910 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2911 alu.src[0].sel = ctx->temp_reg;
2912 alu.src[0].chan = i;
2913 alu.last = (i == lasti);
2914
2915 r = r600_bytecode_add_alu(ctx->bc, &alu);
2916 if (r)
2917 return r;
2918 }
2919 }
2920 return 0;
2921 }
2922
2923 static int tgsi_op2(struct r600_shader_ctx *ctx)
2924 {
2925 return tgsi_op2_s(ctx, 0, 0);
2926 }
2927
2928 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2929 {
2930 return tgsi_op2_s(ctx, 1, 0);
2931 }
2932
2933 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2934 {
2935 return tgsi_op2_s(ctx, 0, 1);
2936 }
2937
2938 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2939 {
2940 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2941 struct r600_bytecode_alu alu;
2942 int i, r;
2943 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2944
2945 for (i = 0; i < lasti + 1; i++) {
2946
2947 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2948 continue;
2949 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2950 alu.op = ctx->inst_info->op;
2951
2952 alu.src[0].sel = V_SQ_ALU_SRC_0;
2953
2954 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2955
2956 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2957
2958 if (i == lasti) {
2959 alu.last = 1;
2960 }
2961 r = r600_bytecode_add_alu(ctx->bc, &alu);
2962 if (r)
2963 return r;
2964 }
2965 return 0;
2966
2967 }
2968
2969 static int tgsi_dneg(struct r600_shader_ctx *ctx)
2970 {
2971 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2972 struct r600_bytecode_alu alu;
2973 int i, r;
2974 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2975
2976 for (i = 0; i < lasti + 1; i++) {
2977
2978 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2979 continue;
2980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2981 alu.op = ALU_OP1_MOV;
2982
2983 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2984
2985 if (i == 1 || i == 3)
2986 r600_bytecode_src_toggle_neg(&alu.src[0]);
2987 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2988
2989 if (i == lasti) {
2990 alu.last = 1;
2991 }
2992 r = r600_bytecode_add_alu(ctx->bc, &alu);
2993 if (r)
2994 return r;
2995 }
2996 return 0;
2997
2998 }
2999
3000 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
3001 {
3002 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3003 struct r600_bytecode_alu alu;
3004 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3005 int i, j, r;
3006 int firsti = write_mask == 0xc ? 2 : 0;
3007
3008 for (i = 0; i <= 3; i++) {
3009 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3010 alu.op = ctx->inst_info->op;
3011
3012 alu.dst.sel = ctx->temp_reg;
3013 alu.dst.chan = i;
3014 alu.dst.write = 1;
3015 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3016 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3017 }
3018
3019 if (i == 3)
3020 alu.last = 1;
3021
3022 r = r600_bytecode_add_alu(ctx->bc, &alu);
3023 if (r)
3024 return r;
3025 }
3026
3027 /* MOV first two channels to writemask dst0 */
3028 for (i = 0; i <= 1; i++) {
3029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3030 alu.op = ALU_OP1_MOV;
3031 alu.src[0].chan = i + 2;
3032 alu.src[0].sel = ctx->temp_reg;
3033
3034 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
3035 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
3036 alu.last = 1;
3037 r = r600_bytecode_add_alu(ctx->bc, &alu);
3038 if (r)
3039 return r;
3040 }
3041
3042 for (i = 0; i <= 3; i++) {
3043 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
3044 /* MOV third channels to writemask dst1 */
3045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3046 alu.op = ALU_OP1_MOV;
3047 alu.src[0].chan = 1;
3048 alu.src[0].sel = ctx->temp_reg;
3049
3050 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
3051 alu.last = 1;
3052 r = r600_bytecode_add_alu(ctx->bc, &alu);
3053 if (r)
3054 return r;
3055 break;
3056 }
3057 }
3058 return 0;
3059 }
3060
3061
3062 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
3063 {
3064 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3065 struct r600_bytecode_alu alu;
3066 int i, r;
3067 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3068
3069 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
3070 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
3071
3072 for (i = 0; i <= (lasti+1)/2; i++) {
3073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3074 alu.op = ctx->inst_info->op;
3075
3076 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3077 alu.dst.sel = ctx->temp_reg;
3078 alu.dst.chan = i;
3079 alu.dst.write = 1;
3080 alu.last = 1;
3081
3082 r = r600_bytecode_add_alu(ctx->bc, &alu);
3083 if (r)
3084 return r;
3085 }
3086
3087 for (i = 0; i <= lasti; i++) {
3088 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3089 alu.op = ALU_OP1_FLT32_TO_FLT64;
3090
3091 alu.src[0].chan = i/2;
3092 if (i%2 == 0)
3093 alu.src[0].sel = ctx->temp_reg;
3094 else {
3095 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3096 alu.src[0].value = 0x0;
3097 }
3098 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3099 alu.last = i == lasti;
3100
3101 r = r600_bytecode_add_alu(ctx->bc, &alu);
3102 if (r)
3103 return r;
3104 }
3105
3106 return 0;
3107 }
3108
3109 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
3110 {
3111 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3112 struct r600_bytecode_alu alu;
3113 int i, r;
3114 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3115
3116 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
3117 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
3118
3119 for (i = 0; i <= lasti; i++) {
3120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3121 alu.op = ALU_OP1_FLT64_TO_FLT32;
3122
3123 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
3124 alu.dst.chan = i;
3125 alu.dst.sel = ctx->temp_reg;
3126 alu.dst.write = i%2 == 0;
3127 alu.last = i == lasti;
3128
3129 r = r600_bytecode_add_alu(ctx->bc, &alu);
3130 if (r)
3131 return r;
3132 }
3133
3134 for (i = 0; i <= (lasti+1)/2; i++) {
3135 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3136 alu.op = ctx->inst_info->op;
3137
3138 alu.src[0].chan = i*2;
3139 alu.src[0].sel = ctx->temp_reg;
3140 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3141 alu.last = 1;
3142
3143 r = r600_bytecode_add_alu(ctx->bc, &alu);
3144 if (r)
3145 return r;
3146 }
3147
3148 return 0;
3149 }
3150
3151 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
3152 {
3153 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3154 int i, r;
3155 struct r600_bytecode_alu alu;
3156 int last_slot = 3;
3157 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3158 int t1 = ctx->temp_reg;
3159
3160 /* these have to write the result to X/Y by the looks of it */
3161 for (i = 0 ; i < last_slot; i++) {
3162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3163 alu.op = ctx->inst_info->op;
3164
3165 /* should only be one src regs */
3166 assert (inst->Instruction.NumSrcRegs == 1);
3167
3168 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3169 r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
3170
3171 /* RSQ should take the absolute value of src */
3172 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
3173 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT) {
3174 r600_bytecode_src_set_abs(&alu.src[1]);
3175 }
3176 alu.dst.sel = t1;
3177 alu.dst.chan = i;
3178 alu.dst.write = (i == 0 || i == 1);
3179
3180 if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
3181 alu.last = 1;
3182 r = r600_bytecode_add_alu(ctx->bc, &alu);
3183 if (r)
3184 return r;
3185 }
3186
3187 for (i = 0 ; i <= lasti; i++) {
3188 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3189 continue;
3190 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3191 alu.op = ALU_OP1_MOV;
3192 alu.src[0].sel = t1;
3193 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
3194 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3195 alu.dst.write = 1;
3196 if (i == lasti)
3197 alu.last = 1;
3198 r = r600_bytecode_add_alu(ctx->bc, &alu);
3199 if (r)
3200 return r;
3201 }
3202 return 0;
3203 }
3204
3205 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
3206 {
3207 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3208 int i, j, r;
3209 struct r600_bytecode_alu alu;
3210 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3211
3212 for (i = 0 ; i < last_slot; i++) {
3213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3214 alu.op = ctx->inst_info->op;
3215 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3216 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
3217
3218 /* RSQ should take the absolute value of src */
3219 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
3220 r600_bytecode_src_set_abs(&alu.src[j]);
3221 }
3222 }
3223 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3224 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3225
3226 if (i == last_slot - 1)
3227 alu.last = 1;
3228 r = r600_bytecode_add_alu(ctx->bc, &alu);
3229 if (r)
3230 return r;
3231 }
3232 return 0;
3233 }
3234
3235 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
3236 {
3237 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3238 int i, j, k, r;
3239 struct r600_bytecode_alu alu;
3240 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3241 int t1 = ctx->temp_reg;
3242
3243 for (k = 0; k <= lasti; k++) {
3244 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
3245 continue;
3246
3247 for (i = 0 ; i < 4; i++) {
3248 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3249 alu.op = ctx->inst_info->op;
3250 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3251 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
3252 }
3253 alu.dst.sel = t1;
3254 alu.dst.chan = i;
3255 alu.dst.write = (i == k);
3256 if (i == 3)
3257 alu.last = 1;
3258 r = r600_bytecode_add_alu(ctx->bc, &alu);
3259 if (r)
3260 return r;
3261 }
3262 }
3263
3264 for (i = 0 ; i <= lasti; i++) {
3265 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3266 continue;
3267 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3268 alu.op = ALU_OP1_MOV;
3269 alu.src[0].sel = t1;
3270 alu.src[0].chan = i;
3271 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3272 alu.dst.write = 1;
3273 if (i == lasti)
3274 alu.last = 1;
3275 r = r600_bytecode_add_alu(ctx->bc, &alu);
3276 if (r)
3277 return r;
3278 }
3279
3280 return 0;
3281 }
3282
3283
3284 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
3285 {
3286 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3287 int i, j, k, r;
3288 struct r600_bytecode_alu alu;
3289 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3290 int t1 = ctx->temp_reg;
3291
3292 for (k = 0; k < 2; k++) {
3293 if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2))))
3294 continue;
3295
3296 for (i = 0; i < 4; i++) {
3297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3298 alu.op = ctx->inst_info->op;
3299 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3300 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));;
3301 }
3302 alu.dst.sel = t1;
3303 alu.dst.chan = i;
3304 alu.dst.write = 1;
3305 if (i == 3)
3306 alu.last = 1;
3307 r = r600_bytecode_add_alu(ctx->bc, &alu);
3308 if (r)
3309 return r;
3310 }
3311 }
3312
3313 for (i = 0; i <= lasti; i++) {
3314 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3315 continue;
3316 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3317 alu.op = ALU_OP1_MOV;
3318 alu.src[0].sel = t1;
3319 alu.src[0].chan = i;
3320 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3321 alu.dst.write = 1;
3322 if (i == lasti)
3323 alu.last = 1;
3324 r = r600_bytecode_add_alu(ctx->bc, &alu);
3325 if (r)
3326 return r;
3327 }
3328
3329 return 0;
3330 }
3331
3332 /*
3333 * r600 - trunc to -PI..PI range
3334 * r700 - normalize by dividing by 2PI
3335 * see fdo bug 27901
3336 */
3337 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
3338 {
3339 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
3340 static float double_pi = 3.1415926535 * 2;
3341 static float neg_pi = -3.1415926535;
3342
3343 int r;
3344 struct r600_bytecode_alu alu;
3345
3346 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3347 alu.op = ALU_OP3_MULADD;
3348 alu.is_op3 = 1;
3349
3350 alu.dst.chan = 0;
3351 alu.dst.sel = ctx->temp_reg;
3352 alu.dst.write = 1;
3353
3354 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3355
3356 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3357 alu.src[1].chan = 0;
3358 alu.src[1].value = *(uint32_t *)&half_inv_pi;
3359 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3360 alu.src[2].chan = 0;
3361 alu.last = 1;
3362 r = r600_bytecode_add_alu(ctx->bc, &alu);
3363 if (r)
3364 return r;
3365
3366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3367 alu.op = ALU_OP1_FRACT;
3368
3369 alu.dst.chan = 0;
3370 alu.dst.sel = ctx->temp_reg;
3371 alu.dst.write = 1;
3372
3373 alu.src[0].sel = ctx->temp_reg;
3374 alu.src[0].chan = 0;
3375 alu.last = 1;
3376 r = r600_bytecode_add_alu(ctx->bc, &alu);
3377 if (r)
3378 return r;
3379
3380 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3381 alu.op = ALU_OP3_MULADD;
3382 alu.is_op3 = 1;
3383
3384 alu.dst.chan = 0;
3385 alu.dst.sel = ctx->temp_reg;
3386 alu.dst.write = 1;
3387
3388 alu.src[0].sel = ctx->temp_reg;
3389 alu.src[0].chan = 0;
3390
3391 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3392 alu.src[1].chan = 0;
3393 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3394 alu.src[2].chan = 0;
3395
3396 if (ctx->bc->chip_class == R600) {
3397 alu.src[1].value = *(uint32_t *)&double_pi;
3398 alu.src[2].value = *(uint32_t *)&neg_pi;
3399 } else {
3400 alu.src[1].sel = V_SQ_ALU_SRC_1;
3401 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3402 alu.src[2].neg = 1;
3403 }
3404
3405 alu.last = 1;
3406 r = r600_bytecode_add_alu(ctx->bc, &alu);
3407 if (r)
3408 return r;
3409 return 0;
3410 }
3411
3412 static int cayman_trig(struct r600_shader_ctx *ctx)
3413 {
3414 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3415 struct r600_bytecode_alu alu;
3416 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3417 int i, r;
3418
3419 r = tgsi_setup_trig(ctx);
3420 if (r)
3421 return r;
3422
3423
3424 for (i = 0; i < last_slot; i++) {
3425 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3426 alu.op = ctx->inst_info->op;
3427 alu.dst.chan = i;
3428
3429 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3430 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3431
3432 alu.src[0].sel = ctx->temp_reg;
3433 alu.src[0].chan = 0;
3434 if (i == last_slot - 1)
3435 alu.last = 1;
3436 r = r600_bytecode_add_alu(ctx->bc, &alu);
3437 if (r)
3438 return r;
3439 }
3440 return 0;
3441 }
3442
3443 static int tgsi_trig(struct r600_shader_ctx *ctx)
3444 {
3445 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3446 struct r600_bytecode_alu alu;
3447 int i, r;
3448 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3449
3450 r = tgsi_setup_trig(ctx);
3451 if (r)
3452 return r;
3453
3454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3455 alu.op = ctx->inst_info->op;
3456 alu.dst.chan = 0;
3457 alu.dst.sel = ctx->temp_reg;
3458 alu.dst.write = 1;
3459
3460 alu.src[0].sel = ctx->temp_reg;
3461 alu.src[0].chan = 0;
3462 alu.last = 1;
3463 r = r600_bytecode_add_alu(ctx->bc, &alu);
3464 if (r)
3465 return r;
3466
3467 /* replicate result */
3468 for (i = 0; i < lasti + 1; i++) {
3469 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3470 continue;
3471
3472 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3473 alu.op = ALU_OP1_MOV;
3474
3475 alu.src[0].sel = ctx->temp_reg;
3476 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3477 if (i == lasti)
3478 alu.last = 1;
3479 r = r600_bytecode_add_alu(ctx->bc, &alu);
3480 if (r)
3481 return r;
3482 }
3483 return 0;
3484 }
3485
3486 static int tgsi_scs(struct r600_shader_ctx *ctx)
3487 {
3488 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3489 struct r600_bytecode_alu alu;
3490 int i, r;
3491
3492 /* We'll only need the trig stuff if we are going to write to the
3493 * X or Y components of the destination vector.
3494 */
3495 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
3496 r = tgsi_setup_trig(ctx);
3497 if (r)
3498 return r;
3499 }
3500
3501 /* dst.x = COS */
3502 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3503 if (ctx->bc->chip_class == CAYMAN) {
3504 for (i = 0 ; i < 3; i++) {
3505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3506 alu.op = ALU_OP1_COS;
3507 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3508
3509 if (i == 0)
3510 alu.dst.write = 1;
3511 else
3512 alu.dst.write = 0;
3513 alu.src[0].sel = ctx->temp_reg;
3514 alu.src[0].chan = 0;
3515 if (i == 2)
3516 alu.last = 1;
3517 r = r600_bytecode_add_alu(ctx->bc, &alu);
3518 if (r)
3519 return r;
3520 }
3521 } else {
3522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3523 alu.op = ALU_OP1_COS;
3524 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3525
3526 alu.src[0].sel = ctx->temp_reg;
3527 alu.src[0].chan = 0;
3528 alu.last = 1;
3529 r = r600_bytecode_add_alu(ctx->bc, &alu);
3530 if (r)
3531 return r;
3532 }
3533 }
3534
3535 /* dst.y = SIN */
3536 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3537 if (ctx->bc->chip_class == CAYMAN) {
3538 for (i = 0 ; i < 3; i++) {
3539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3540 alu.op = ALU_OP1_SIN;
3541 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3542 if (i == 1)
3543 alu.dst.write = 1;
3544 else
3545 alu.dst.write = 0;
3546 alu.src[0].sel = ctx->temp_reg;
3547 alu.src[0].chan = 0;
3548 if (i == 2)
3549 alu.last = 1;
3550 r = r600_bytecode_add_alu(ctx->bc, &alu);
3551 if (r)
3552 return r;
3553 }
3554 } else {
3555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3556 alu.op = ALU_OP1_SIN;
3557 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3558
3559 alu.src[0].sel = ctx->temp_reg;
3560 alu.src[0].chan = 0;
3561 alu.last = 1;
3562 r = r600_bytecode_add_alu(ctx->bc, &alu);
3563 if (r)
3564 return r;
3565 }
3566 }
3567
3568 /* dst.z = 0.0; */
3569 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3570 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3571
3572 alu.op = ALU_OP1_MOV;
3573
3574 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3575
3576 alu.src[0].sel = V_SQ_ALU_SRC_0;
3577 alu.src[0].chan = 0;
3578
3579 alu.last = 1;
3580
3581 r = r600_bytecode_add_alu(ctx->bc, &alu);
3582 if (r)
3583 return r;
3584 }
3585
3586 /* dst.w = 1.0; */
3587 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3588 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3589
3590 alu.op = ALU_OP1_MOV;
3591
3592 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3593
3594 alu.src[0].sel = V_SQ_ALU_SRC_1;
3595 alu.src[0].chan = 0;
3596
3597 alu.last = 1;
3598
3599 r = r600_bytecode_add_alu(ctx->bc, &alu);
3600 if (r)
3601 return r;
3602 }
3603
3604 return 0;
3605 }
3606
3607 static int tgsi_kill(struct r600_shader_ctx *ctx)
3608 {
3609 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3610 struct r600_bytecode_alu alu;
3611 int i, r;
3612
3613 for (i = 0; i < 4; i++) {
3614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3615 alu.op = ctx->inst_info->op;
3616
3617 alu.dst.chan = i;
3618
3619 alu.src[0].sel = V_SQ_ALU_SRC_0;
3620
3621 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
3622 alu.src[1].sel = V_SQ_ALU_SRC_1;
3623 alu.src[1].neg = 1;
3624 } else {
3625 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3626 }
3627 if (i == 3) {
3628 alu.last = 1;
3629 }
3630 r = r600_bytecode_add_alu(ctx->bc, &alu);
3631 if (r)
3632 return r;
3633 }
3634
3635 /* kill must be last in ALU */
3636 ctx->bc->force_add_cf = 1;
3637 ctx->shader->uses_kill = TRUE;
3638 return 0;
3639 }
3640
3641 static int tgsi_lit(struct r600_shader_ctx *ctx)
3642 {
3643 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3644 struct r600_bytecode_alu alu;
3645 int r;
3646
3647 /* tmp.x = max(src.y, 0.0) */
3648 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3649 alu.op = ALU_OP2_MAX;
3650 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3651 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3652 alu.src[1].chan = 1;
3653
3654 alu.dst.sel = ctx->temp_reg;
3655 alu.dst.chan = 0;
3656 alu.dst.write = 1;
3657
3658 alu.last = 1;
3659 r = r600_bytecode_add_alu(ctx->bc, &alu);
3660 if (r)
3661 return r;
3662
3663 if (inst->Dst[0].Register.WriteMask & (1 << 2))
3664 {
3665 int chan;
3666 int sel;
3667 int i;
3668
3669 if (ctx->bc->chip_class == CAYMAN) {
3670 for (i = 0; i < 3; i++) {
3671 /* tmp.z = log(tmp.x) */
3672 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3673 alu.op = ALU_OP1_LOG_CLAMPED;
3674 alu.src[0].sel = ctx->temp_reg;
3675 alu.src[0].chan = 0;
3676 alu.dst.sel = ctx->temp_reg;
3677 alu.dst.chan = i;
3678 if (i == 2) {
3679 alu.dst.write = 1;
3680 alu.last = 1;
3681 } else
3682 alu.dst.write = 0;
3683
3684 r = r600_bytecode_add_alu(ctx->bc, &alu);
3685 if (r)
3686 return r;
3687 }
3688 } else {
3689 /* tmp.z = log(tmp.x) */
3690 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3691 alu.op = ALU_OP1_LOG_CLAMPED;
3692 alu.src[0].sel = ctx->temp_reg;
3693 alu.src[0].chan = 0;
3694 alu.dst.sel = ctx->temp_reg;
3695 alu.dst.chan = 2;
3696 alu.dst.write = 1;
3697 alu.last = 1;
3698 r = r600_bytecode_add_alu(ctx->bc, &alu);
3699 if (r)
3700 return r;
3701 }
3702
3703 chan = alu.dst.chan;
3704 sel = alu.dst.sel;
3705
3706 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
3707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3708 alu.op = ALU_OP3_MUL_LIT;
3709 alu.src[0].sel = sel;
3710 alu.src[0].chan = chan;
3711 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
3712 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
3713 alu.dst.sel = ctx->temp_reg;
3714 alu.dst.chan = 0;
3715 alu.dst.write = 1;
3716 alu.is_op3 = 1;
3717 alu.last = 1;
3718 r = r600_bytecode_add_alu(ctx->bc, &alu);
3719 if (r)
3720 return r;
3721
3722 if (ctx->bc->chip_class == CAYMAN) {
3723 for (i = 0; i < 3; i++) {
3724 /* dst.z = exp(tmp.x) */
3725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3726 alu.op = ALU_OP1_EXP_IEEE;
3727 alu.src[0].sel = ctx->temp_reg;
3728 alu.src[0].chan = 0;
3729 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3730 if (i == 2) {
3731 alu.dst.write = 1;
3732 alu.last = 1;
3733 } else
3734 alu.dst.write = 0;
3735 r = r600_bytecode_add_alu(ctx->bc, &alu);
3736 if (r)
3737 return r;
3738 }
3739 } else {
3740 /* dst.z = exp(tmp.x) */
3741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3742 alu.op = ALU_OP1_EXP_IEEE;
3743 alu.src[0].sel = ctx->temp_reg;
3744 alu.src[0].chan = 0;
3745 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3746 alu.last = 1;
3747 r = r600_bytecode_add_alu(ctx->bc, &alu);
3748 if (r)
3749 return r;
3750 }
3751 }
3752
3753 /* dst.x, <- 1.0 */
3754 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3755 alu.op = ALU_OP1_MOV;
3756 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
3757 alu.src[0].chan = 0;
3758 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3759 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
3760 r = r600_bytecode_add_alu(ctx->bc, &alu);
3761 if (r)
3762 return r;
3763
3764 /* dst.y = max(src.x, 0.0) */
3765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3766 alu.op = ALU_OP2_MAX;
3767 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3768 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3769 alu.src[1].chan = 0;
3770 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3771 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
3772 r = r600_bytecode_add_alu(ctx->bc, &alu);
3773 if (r)
3774 return r;
3775
3776 /* dst.w, <- 1.0 */
3777 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3778 alu.op = ALU_OP1_MOV;
3779 alu.src[0].sel = V_SQ_ALU_SRC_1;
3780 alu.src[0].chan = 0;
3781 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3782 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
3783 alu.last = 1;
3784 r = r600_bytecode_add_alu(ctx->bc, &alu);
3785 if (r)
3786 return r;
3787
3788 return 0;
3789 }
3790
3791 static int tgsi_rsq(struct r600_shader_ctx *ctx)
3792 {
3793 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3794 struct r600_bytecode_alu alu;
3795 int i, r;
3796
3797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3798
3799 /* XXX:
3800 * For state trackers other than OpenGL, we'll want to use
3801 * _RECIPSQRT_IEEE instead.
3802 */
3803 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
3804
3805 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3806 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3807 r600_bytecode_src_set_abs(&alu.src[i]);
3808 }
3809 alu.dst.sel = ctx->temp_reg;
3810 alu.dst.write = 1;
3811 alu.last = 1;
3812 r = r600_bytecode_add_alu(ctx->bc, &alu);
3813 if (r)
3814 return r;
3815 /* replicate result */
3816 return tgsi_helper_tempx_replicate(ctx);
3817 }
3818
3819 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
3820 {
3821 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3822 struct r600_bytecode_alu alu;
3823 int i, r;
3824
3825 for (i = 0; i < 4; i++) {
3826 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3827 alu.src[0].sel = ctx->temp_reg;
3828 alu.op = ALU_OP1_MOV;
3829 alu.dst.chan = i;
3830 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3831 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3832 if (i == 3)
3833 alu.last = 1;
3834 r = r600_bytecode_add_alu(ctx->bc, &alu);
3835 if (r)
3836 return r;
3837 }
3838 return 0;
3839 }
3840
3841 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
3842 {
3843 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3844 struct r600_bytecode_alu alu;
3845 int i, r;
3846
3847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3848 alu.op = ctx->inst_info->op;
3849 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3850 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3851 }
3852 alu.dst.sel = ctx->temp_reg;
3853 alu.dst.write = 1;
3854 alu.last = 1;
3855 r = r600_bytecode_add_alu(ctx->bc, &alu);
3856 if (r)
3857 return r;
3858 /* replicate result */
3859 return tgsi_helper_tempx_replicate(ctx);
3860 }
3861
3862 static int cayman_pow(struct r600_shader_ctx *ctx)
3863 {
3864 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3865 int i, r;
3866 struct r600_bytecode_alu alu;
3867 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3868
3869 for (i = 0; i < 3; i++) {
3870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3871 alu.op = ALU_OP1_LOG_IEEE;
3872 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3873 alu.dst.sel = ctx->temp_reg;
3874 alu.dst.chan = i;
3875 alu.dst.write = 1;
3876 if (i == 2)
3877 alu.last = 1;
3878 r = r600_bytecode_add_alu(ctx->bc, &alu);
3879 if (r)
3880 return r;
3881 }
3882
3883 /* b * LOG2(a) */
3884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3885 alu.op = ALU_OP2_MUL;
3886 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3887 alu.src[1].sel = ctx->temp_reg;
3888 alu.dst.sel = ctx->temp_reg;
3889 alu.dst.write = 1;
3890 alu.last = 1;
3891 r = r600_bytecode_add_alu(ctx->bc, &alu);
3892 if (r)
3893 return r;
3894
3895 for (i = 0; i < last_slot; i++) {
3896 /* POW(a,b) = EXP2(b * LOG2(a))*/
3897 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3898 alu.op = ALU_OP1_EXP_IEEE;
3899 alu.src[0].sel = ctx->temp_reg;
3900
3901 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3902 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3903 if (i == last_slot - 1)
3904 alu.last = 1;
3905 r = r600_bytecode_add_alu(ctx->bc, &alu);
3906 if (r)
3907 return r;
3908 }
3909 return 0;
3910 }
3911
3912 static int tgsi_pow(struct r600_shader_ctx *ctx)
3913 {
3914 struct r600_bytecode_alu alu;
3915 int r;
3916
3917 /* LOG2(a) */
3918 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3919 alu.op = ALU_OP1_LOG_IEEE;
3920 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3921 alu.dst.sel = ctx->temp_reg;
3922 alu.dst.write = 1;
3923 alu.last = 1;
3924 r = r600_bytecode_add_alu(ctx->bc, &alu);
3925 if (r)
3926 return r;
3927 /* b * LOG2(a) */
3928 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3929 alu.op = ALU_OP2_MUL;
3930 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3931 alu.src[1].sel = ctx->temp_reg;
3932 alu.dst.sel = ctx->temp_reg;
3933 alu.dst.write = 1;
3934 alu.last = 1;
3935 r = r600_bytecode_add_alu(ctx->bc, &alu);
3936 if (r)
3937 return r;
3938 /* POW(a,b) = EXP2(b * LOG2(a))*/
3939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3940 alu.op = ALU_OP1_EXP_IEEE;
3941 alu.src[0].sel = ctx->temp_reg;
3942 alu.dst.sel = ctx->temp_reg;
3943 alu.dst.write = 1;
3944 alu.last = 1;
3945 r = r600_bytecode_add_alu(ctx->bc, &alu);
3946 if (r)
3947 return r;
3948 return tgsi_helper_tempx_replicate(ctx);
3949 }
3950
3951 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
3952 {
3953 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3954 struct r600_bytecode_alu alu;
3955 int i, r, j;
3956 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3957 int tmp0 = ctx->temp_reg;
3958 int tmp1 = r600_get_temp(ctx);
3959 int tmp2 = r600_get_temp(ctx);
3960 int tmp3 = r600_get_temp(ctx);
3961 /* Unsigned path:
3962 *
3963 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
3964 *
3965 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
3966 * 2. tmp0.z = lo (tmp0.x * src2)
3967 * 3. tmp0.w = -tmp0.z
3968 * 4. tmp0.y = hi (tmp0.x * src2)
3969 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
3970 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
3971 * 7. tmp1.x = tmp0.x - tmp0.w
3972 * 8. tmp1.y = tmp0.x + tmp0.w
3973 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
3974 * 10. tmp0.z = hi(tmp0.x * src1) = q
3975 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
3976 *
3977 * 12. tmp0.w = src1 - tmp0.y = r
3978 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
3979 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
3980 *
3981 * if DIV
3982 *
3983 * 15. tmp1.z = tmp0.z + 1 = q + 1
3984 * 16. tmp1.w = tmp0.z - 1 = q - 1
3985 *
3986 * else MOD
3987 *
3988 * 15. tmp1.z = tmp0.w - src2 = r - src2
3989 * 16. tmp1.w = tmp0.w + src2 = r + src2
3990 *
3991 * endif
3992 *
3993 * 17. tmp1.x = tmp1.x & tmp1.y
3994 *
3995 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
3996 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
3997 *
3998 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
3999 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
4000 *
4001 * Signed path:
4002 *
4003 * Same as unsigned, using abs values of the operands,
4004 * and fixing the sign of the result in the end.
4005 */
4006
4007 for (i = 0; i < 4; i++) {
4008 if (!(write_mask & (1<<i)))
4009 continue;
4010
4011 if (signed_op) {
4012
4013 /* tmp2.x = -src0 */
4014 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4015 alu.op = ALU_OP2_SUB_INT;
4016
4017 alu.dst.sel = tmp2;
4018 alu.dst.chan = 0;
4019 alu.dst.write = 1;
4020
4021 alu.src[0].sel = V_SQ_ALU_SRC_0;
4022
4023 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4024
4025 alu.last = 1;
4026 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4027 return r;
4028
4029 /* tmp2.y = -src1 */
4030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4031 alu.op = ALU_OP2_SUB_INT;
4032
4033 alu.dst.sel = tmp2;
4034 alu.dst.chan = 1;
4035 alu.dst.write = 1;
4036
4037 alu.src[0].sel = V_SQ_ALU_SRC_0;
4038
4039 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4040
4041 alu.last = 1;
4042 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4043 return r;
4044
4045 /* tmp2.z sign bit is set if src0 and src2 signs are different */
4046 /* it will be a sign of the quotient */
4047 if (!mod) {
4048
4049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4050 alu.op = ALU_OP2_XOR_INT;
4051
4052 alu.dst.sel = tmp2;
4053 alu.dst.chan = 2;
4054 alu.dst.write = 1;
4055
4056 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4057 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4058
4059 alu.last = 1;
4060 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4061 return r;
4062 }
4063
4064 /* tmp2.x = |src0| */
4065 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4066 alu.op = ALU_OP3_CNDGE_INT;
4067 alu.is_op3 = 1;
4068
4069 alu.dst.sel = tmp2;
4070 alu.dst.chan = 0;
4071 alu.dst.write = 1;
4072
4073 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4074 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4075 alu.src[2].sel = tmp2;
4076 alu.src[2].chan = 0;
4077
4078 alu.last = 1;
4079 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4080 return r;
4081
4082 /* tmp2.y = |src1| */
4083 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4084 alu.op = ALU_OP3_CNDGE_INT;
4085 alu.is_op3 = 1;
4086
4087 alu.dst.sel = tmp2;
4088 alu.dst.chan = 1;
4089 alu.dst.write = 1;
4090
4091 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4092 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4093 alu.src[2].sel = tmp2;
4094 alu.src[2].chan = 1;
4095
4096 alu.last = 1;
4097 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4098 return r;
4099
4100 }
4101
4102 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
4103 if (ctx->bc->chip_class == CAYMAN) {
4104 /* tmp3.x = u2f(src2) */
4105 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4106 alu.op = ALU_OP1_UINT_TO_FLT;
4107
4108 alu.dst.sel = tmp3;
4109 alu.dst.chan = 0;
4110 alu.dst.write = 1;
4111
4112 if (signed_op) {
4113 alu.src[0].sel = tmp2;
4114 alu.src[0].chan = 1;
4115 } else {
4116 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4117 }
4118
4119 alu.last = 1;
4120 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4121 return r;
4122
4123 /* tmp0.x = recip(tmp3.x) */
4124 for (j = 0 ; j < 3; j++) {
4125 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4126 alu.op = ALU_OP1_RECIP_IEEE;
4127
4128 alu.dst.sel = tmp0;
4129 alu.dst.chan = j;
4130 alu.dst.write = (j == 0);
4131
4132 alu.src[0].sel = tmp3;
4133 alu.src[0].chan = 0;
4134
4135 if (j == 2)
4136 alu.last = 1;
4137 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4138 return r;
4139 }
4140
4141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4142 alu.op = ALU_OP2_MUL;
4143
4144 alu.src[0].sel = tmp0;
4145 alu.src[0].chan = 0;
4146
4147 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4148 alu.src[1].value = 0x4f800000;
4149
4150 alu.dst.sel = tmp3;
4151 alu.dst.write = 1;
4152 alu.last = 1;
4153 r = r600_bytecode_add_alu(ctx->bc, &alu);
4154 if (r)
4155 return r;
4156
4157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4158 alu.op = ALU_OP1_FLT_TO_UINT;
4159
4160 alu.dst.sel = tmp0;
4161 alu.dst.chan = 0;
4162 alu.dst.write = 1;
4163
4164 alu.src[0].sel = tmp3;
4165 alu.src[0].chan = 0;
4166
4167 alu.last = 1;
4168 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4169 return r;
4170
4171 } else {
4172 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4173 alu.op = ALU_OP1_RECIP_UINT;
4174
4175 alu.dst.sel = tmp0;
4176 alu.dst.chan = 0;
4177 alu.dst.write = 1;
4178
4179 if (signed_op) {
4180 alu.src[0].sel = tmp2;
4181 alu.src[0].chan = 1;
4182 } else {
4183 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4184 }
4185
4186 alu.last = 1;
4187 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4188 return r;
4189 }
4190
4191 /* 2. tmp0.z = lo (tmp0.x * src2) */
4192 if (ctx->bc->chip_class == CAYMAN) {
4193 for (j = 0 ; j < 4; j++) {
4194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4195 alu.op = ALU_OP2_MULLO_UINT;
4196
4197 alu.dst.sel = tmp0;
4198 alu.dst.chan = j;
4199 alu.dst.write = (j == 2);
4200
4201 alu.src[0].sel = tmp0;
4202 alu.src[0].chan = 0;
4203 if (signed_op) {
4204 alu.src[1].sel = tmp2;
4205 alu.src[1].chan = 1;
4206 } else {
4207 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4208 }
4209
4210 alu.last = (j == 3);
4211 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4212 return r;
4213 }
4214 } else {
4215 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4216 alu.op = ALU_OP2_MULLO_UINT;
4217
4218 alu.dst.sel = tmp0;
4219 alu.dst.chan = 2;
4220 alu.dst.write = 1;
4221
4222 alu.src[0].sel = tmp0;
4223 alu.src[0].chan = 0;
4224 if (signed_op) {
4225 alu.src[1].sel = tmp2;
4226 alu.src[1].chan = 1;
4227 } else {
4228 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4229 }
4230
4231 alu.last = 1;
4232 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4233 return r;
4234 }
4235
4236 /* 3. tmp0.w = -tmp0.z */
4237 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4238 alu.op = ALU_OP2_SUB_INT;
4239
4240 alu.dst.sel = tmp0;
4241 alu.dst.chan = 3;
4242 alu.dst.write = 1;
4243
4244 alu.src[0].sel = V_SQ_ALU_SRC_0;
4245 alu.src[1].sel = tmp0;
4246 alu.src[1].chan = 2;
4247
4248 alu.last = 1;
4249 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4250 return r;
4251
4252 /* 4. tmp0.y = hi (tmp0.x * src2) */
4253 if (ctx->bc->chip_class == CAYMAN) {
4254 for (j = 0 ; j < 4; j++) {
4255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4256 alu.op = ALU_OP2_MULHI_UINT;
4257
4258 alu.dst.sel = tmp0;
4259 alu.dst.chan = j;
4260 alu.dst.write = (j == 1);
4261
4262 alu.src[0].sel = tmp0;
4263 alu.src[0].chan = 0;
4264
4265 if (signed_op) {
4266 alu.src[1].sel = tmp2;
4267 alu.src[1].chan = 1;
4268 } else {
4269 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4270 }
4271 alu.last = (j == 3);
4272 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4273 return r;
4274 }
4275 } else {
4276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4277 alu.op = ALU_OP2_MULHI_UINT;
4278
4279 alu.dst.sel = tmp0;
4280 alu.dst.chan = 1;
4281 alu.dst.write = 1;
4282
4283 alu.src[0].sel = tmp0;
4284 alu.src[0].chan = 0;
4285
4286 if (signed_op) {
4287 alu.src[1].sel = tmp2;
4288 alu.src[1].chan = 1;
4289 } else {
4290 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4291 }
4292
4293 alu.last = 1;
4294 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4295 return r;
4296 }
4297
4298 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
4299 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4300 alu.op = ALU_OP3_CNDE_INT;
4301 alu.is_op3 = 1;
4302
4303 alu.dst.sel = tmp0;
4304 alu.dst.chan = 2;
4305 alu.dst.write = 1;
4306
4307 alu.src[0].sel = tmp0;
4308 alu.src[0].chan = 1;
4309 alu.src[1].sel = tmp0;
4310 alu.src[1].chan = 3;
4311 alu.src[2].sel = tmp0;
4312 alu.src[2].chan = 2;
4313
4314 alu.last = 1;
4315 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4316 return r;
4317
4318 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
4319 if (ctx->bc->chip_class == CAYMAN) {
4320 for (j = 0 ; j < 4; j++) {
4321 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4322 alu.op = ALU_OP2_MULHI_UINT;
4323
4324 alu.dst.sel = tmp0;
4325 alu.dst.chan = j;
4326 alu.dst.write = (j == 3);
4327
4328 alu.src[0].sel = tmp0;
4329 alu.src[0].chan = 2;
4330
4331 alu.src[1].sel = tmp0;
4332 alu.src[1].chan = 0;
4333
4334 alu.last = (j == 3);
4335 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4336 return r;
4337 }
4338 } else {
4339 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4340 alu.op = ALU_OP2_MULHI_UINT;
4341
4342 alu.dst.sel = tmp0;
4343 alu.dst.chan = 3;
4344 alu.dst.write = 1;
4345
4346 alu.src[0].sel = tmp0;
4347 alu.src[0].chan = 2;
4348
4349 alu.src[1].sel = tmp0;
4350 alu.src[1].chan = 0;
4351
4352 alu.last = 1;
4353 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4354 return r;
4355 }
4356
4357 /* 7. tmp1.x = tmp0.x - tmp0.w */
4358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4359 alu.op = ALU_OP2_SUB_INT;
4360
4361 alu.dst.sel = tmp1;
4362 alu.dst.chan = 0;
4363 alu.dst.write = 1;
4364
4365 alu.src[0].sel = tmp0;
4366 alu.src[0].chan = 0;
4367 alu.src[1].sel = tmp0;
4368 alu.src[1].chan = 3;
4369
4370 alu.last = 1;
4371 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4372 return r;
4373
4374 /* 8. tmp1.y = tmp0.x + tmp0.w */
4375 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4376 alu.op = ALU_OP2_ADD_INT;
4377
4378 alu.dst.sel = tmp1;
4379 alu.dst.chan = 1;
4380 alu.dst.write = 1;
4381
4382 alu.src[0].sel = tmp0;
4383 alu.src[0].chan = 0;
4384 alu.src[1].sel = tmp0;
4385 alu.src[1].chan = 3;
4386
4387 alu.last = 1;
4388 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4389 return r;
4390
4391 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
4392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4393 alu.op = ALU_OP3_CNDE_INT;
4394 alu.is_op3 = 1;
4395
4396 alu.dst.sel = tmp0;
4397 alu.dst.chan = 0;
4398 alu.dst.write = 1;
4399
4400 alu.src[0].sel = tmp0;
4401 alu.src[0].chan = 1;
4402 alu.src[1].sel = tmp1;
4403 alu.src[1].chan = 1;
4404 alu.src[2].sel = tmp1;
4405 alu.src[2].chan = 0;
4406
4407 alu.last = 1;
4408 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4409 return r;
4410
4411 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
4412 if (ctx->bc->chip_class == CAYMAN) {
4413 for (j = 0 ; j < 4; j++) {
4414 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4415 alu.op = ALU_OP2_MULHI_UINT;
4416
4417 alu.dst.sel = tmp0;
4418 alu.dst.chan = j;
4419 alu.dst.write = (j == 2);
4420
4421 alu.src[0].sel = tmp0;
4422 alu.src[0].chan = 0;
4423
4424 if (signed_op) {
4425 alu.src[1].sel = tmp2;
4426 alu.src[1].chan = 0;
4427 } else {
4428 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4429 }
4430
4431 alu.last = (j == 3);
4432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4433 return r;
4434 }
4435 } else {
4436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4437 alu.op = ALU_OP2_MULHI_UINT;
4438
4439 alu.dst.sel = tmp0;
4440 alu.dst.chan = 2;
4441 alu.dst.write = 1;
4442
4443 alu.src[0].sel = tmp0;
4444 alu.src[0].chan = 0;
4445
4446 if (signed_op) {
4447 alu.src[1].sel = tmp2;
4448 alu.src[1].chan = 0;
4449 } else {
4450 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4451 }
4452
4453 alu.last = 1;
4454 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4455 return r;
4456 }
4457
4458 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
4459 if (ctx->bc->chip_class == CAYMAN) {
4460 for (j = 0 ; j < 4; j++) {
4461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4462 alu.op = ALU_OP2_MULLO_UINT;
4463
4464 alu.dst.sel = tmp0;
4465 alu.dst.chan = j;
4466 alu.dst.write = (j == 1);
4467
4468 if (signed_op) {
4469 alu.src[0].sel = tmp2;
4470 alu.src[0].chan = 1;
4471 } else {
4472 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4473 }
4474
4475 alu.src[1].sel = tmp0;
4476 alu.src[1].chan = 2;
4477
4478 alu.last = (j == 3);
4479 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4480 return r;
4481 }
4482 } else {
4483 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4484 alu.op = ALU_OP2_MULLO_UINT;
4485
4486 alu.dst.sel = tmp0;
4487 alu.dst.chan = 1;
4488 alu.dst.write = 1;
4489
4490 if (signed_op) {
4491 alu.src[0].sel = tmp2;
4492 alu.src[0].chan = 1;
4493 } else {
4494 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4495 }
4496
4497 alu.src[1].sel = tmp0;
4498 alu.src[1].chan = 2;
4499
4500 alu.last = 1;
4501 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4502 return r;
4503 }
4504
4505 /* 12. tmp0.w = src1 - tmp0.y = r */
4506 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4507 alu.op = ALU_OP2_SUB_INT;
4508
4509 alu.dst.sel = tmp0;
4510 alu.dst.chan = 3;
4511 alu.dst.write = 1;
4512
4513 if (signed_op) {
4514 alu.src[0].sel = tmp2;
4515 alu.src[0].chan = 0;
4516 } else {
4517 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4518 }
4519
4520 alu.src[1].sel = tmp0;
4521 alu.src[1].chan = 1;
4522
4523 alu.last = 1;
4524 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4525 return r;
4526
4527 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
4528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4529 alu.op = ALU_OP2_SETGE_UINT;
4530
4531 alu.dst.sel = tmp1;
4532 alu.dst.chan = 0;
4533 alu.dst.write = 1;
4534
4535 alu.src[0].sel = tmp0;
4536 alu.src[0].chan = 3;
4537 if (signed_op) {
4538 alu.src[1].sel = tmp2;
4539 alu.src[1].chan = 1;
4540 } else {
4541 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4542 }
4543
4544 alu.last = 1;
4545 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4546 return r;
4547
4548 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
4549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4550 alu.op = ALU_OP2_SETGE_UINT;
4551
4552 alu.dst.sel = tmp1;
4553 alu.dst.chan = 1;
4554 alu.dst.write = 1;
4555
4556 if (signed_op) {
4557 alu.src[0].sel = tmp2;
4558 alu.src[0].chan = 0;
4559 } else {
4560 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4561 }
4562
4563 alu.src[1].sel = tmp0;
4564 alu.src[1].chan = 1;
4565
4566 alu.last = 1;
4567 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4568 return r;
4569
4570 if (mod) { /* UMOD */
4571
4572 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
4573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4574 alu.op = ALU_OP2_SUB_INT;
4575
4576 alu.dst.sel = tmp1;
4577 alu.dst.chan = 2;
4578 alu.dst.write = 1;
4579
4580 alu.src[0].sel = tmp0;
4581 alu.src[0].chan = 3;
4582
4583 if (signed_op) {
4584 alu.src[1].sel = tmp2;
4585 alu.src[1].chan = 1;
4586 } else {
4587 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4588 }
4589
4590 alu.last = 1;
4591 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4592 return r;
4593
4594 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
4595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4596 alu.op = ALU_OP2_ADD_INT;
4597
4598 alu.dst.sel = tmp1;
4599 alu.dst.chan = 3;
4600 alu.dst.write = 1;
4601
4602 alu.src[0].sel = tmp0;
4603 alu.src[0].chan = 3;
4604 if (signed_op) {
4605 alu.src[1].sel = tmp2;
4606 alu.src[1].chan = 1;
4607 } else {
4608 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4609 }
4610
4611 alu.last = 1;
4612 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4613 return r;
4614
4615 } else { /* UDIV */
4616
4617 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
4618 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4619 alu.op = ALU_OP2_ADD_INT;
4620
4621 alu.dst.sel = tmp1;
4622 alu.dst.chan = 2;
4623 alu.dst.write = 1;
4624
4625 alu.src[0].sel = tmp0;
4626 alu.src[0].chan = 2;
4627 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4628
4629 alu.last = 1;
4630 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4631 return r;
4632
4633 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
4634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4635 alu.op = ALU_OP2_ADD_INT;
4636
4637 alu.dst.sel = tmp1;
4638 alu.dst.chan = 3;
4639 alu.dst.write = 1;
4640
4641 alu.src[0].sel = tmp0;
4642 alu.src[0].chan = 2;
4643 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
4644
4645 alu.last = 1;
4646 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4647 return r;
4648
4649 }
4650
4651 /* 17. tmp1.x = tmp1.x & tmp1.y */
4652 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4653 alu.op = ALU_OP2_AND_INT;
4654
4655 alu.dst.sel = tmp1;
4656 alu.dst.chan = 0;
4657 alu.dst.write = 1;
4658
4659 alu.src[0].sel = tmp1;
4660 alu.src[0].chan = 0;
4661 alu.src[1].sel = tmp1;
4662 alu.src[1].chan = 1;
4663
4664 alu.last = 1;
4665 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4666 return r;
4667
4668 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
4669 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
4670 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4671 alu.op = ALU_OP3_CNDE_INT;
4672 alu.is_op3 = 1;
4673
4674 alu.dst.sel = tmp0;
4675 alu.dst.chan = 2;
4676 alu.dst.write = 1;
4677
4678 alu.src[0].sel = tmp1;
4679 alu.src[0].chan = 0;
4680 alu.src[1].sel = tmp0;
4681 alu.src[1].chan = mod ? 3 : 2;
4682 alu.src[2].sel = tmp1;
4683 alu.src[2].chan = 2;
4684
4685 alu.last = 1;
4686 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4687 return r;
4688
4689 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
4690 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4691 alu.op = ALU_OP3_CNDE_INT;
4692 alu.is_op3 = 1;
4693
4694 if (signed_op) {
4695 alu.dst.sel = tmp0;
4696 alu.dst.chan = 2;
4697 alu.dst.write = 1;
4698 } else {
4699 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4700 }
4701
4702 alu.src[0].sel = tmp1;
4703 alu.src[0].chan = 1;
4704 alu.src[1].sel = tmp1;
4705 alu.src[1].chan = 3;
4706 alu.src[2].sel = tmp0;
4707 alu.src[2].chan = 2;
4708
4709 alu.last = 1;
4710 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4711 return r;
4712
4713 if (signed_op) {
4714
4715 /* fix the sign of the result */
4716
4717 if (mod) {
4718
4719 /* tmp0.x = -tmp0.z */
4720 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4721 alu.op = ALU_OP2_SUB_INT;
4722
4723 alu.dst.sel = tmp0;
4724 alu.dst.chan = 0;
4725 alu.dst.write = 1;
4726
4727 alu.src[0].sel = V_SQ_ALU_SRC_0;
4728 alu.src[1].sel = tmp0;
4729 alu.src[1].chan = 2;
4730
4731 alu.last = 1;
4732 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4733 return r;
4734
4735 /* sign of the remainder is the same as the sign of src0 */
4736 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
4737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4738 alu.op = ALU_OP3_CNDGE_INT;
4739 alu.is_op3 = 1;
4740
4741 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4742
4743 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4744 alu.src[1].sel = tmp0;
4745 alu.src[1].chan = 2;
4746 alu.src[2].sel = tmp0;
4747 alu.src[2].chan = 0;
4748
4749 alu.last = 1;
4750 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4751 return r;
4752
4753 } else {
4754
4755 /* tmp0.x = -tmp0.z */
4756 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4757 alu.op = ALU_OP2_SUB_INT;
4758
4759 alu.dst.sel = tmp0;
4760 alu.dst.chan = 0;
4761 alu.dst.write = 1;
4762
4763 alu.src[0].sel = V_SQ_ALU_SRC_0;
4764 alu.src[1].sel = tmp0;
4765 alu.src[1].chan = 2;
4766
4767 alu.last = 1;
4768 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4769 return r;
4770
4771 /* fix the quotient sign (same as the sign of src0*src1) */
4772 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
4773 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4774 alu.op = ALU_OP3_CNDGE_INT;
4775 alu.is_op3 = 1;
4776
4777 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4778
4779 alu.src[0].sel = tmp2;
4780 alu.src[0].chan = 2;
4781 alu.src[1].sel = tmp0;
4782 alu.src[1].chan = 2;
4783 alu.src[2].sel = tmp0;
4784 alu.src[2].chan = 0;
4785
4786 alu.last = 1;
4787 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4788 return r;
4789 }
4790 }
4791 }
4792 return 0;
4793 }
4794
4795 static int tgsi_udiv(struct r600_shader_ctx *ctx)
4796 {
4797 return tgsi_divmod(ctx, 0, 0);
4798 }
4799
4800 static int tgsi_umod(struct r600_shader_ctx *ctx)
4801 {
4802 return tgsi_divmod(ctx, 1, 0);
4803 }
4804
4805 static int tgsi_idiv(struct r600_shader_ctx *ctx)
4806 {
4807 return tgsi_divmod(ctx, 0, 1);
4808 }
4809
4810 static int tgsi_imod(struct r600_shader_ctx *ctx)
4811 {
4812 return tgsi_divmod(ctx, 1, 1);
4813 }
4814
4815
4816 static int tgsi_f2i(struct r600_shader_ctx *ctx)
4817 {
4818 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4819 struct r600_bytecode_alu alu;
4820 int i, r;
4821 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4822 int last_inst = tgsi_last_instruction(write_mask);
4823
4824 for (i = 0; i < 4; i++) {
4825 if (!(write_mask & (1<<i)))
4826 continue;
4827
4828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4829 alu.op = ALU_OP1_TRUNC;
4830
4831 alu.dst.sel = ctx->temp_reg;
4832 alu.dst.chan = i;
4833 alu.dst.write = 1;
4834
4835 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4836 if (i == last_inst)
4837 alu.last = 1;
4838 r = r600_bytecode_add_alu(ctx->bc, &alu);
4839 if (r)
4840 return r;
4841 }
4842
4843 for (i = 0; i < 4; i++) {
4844 if (!(write_mask & (1<<i)))
4845 continue;
4846
4847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4848 alu.op = ctx->inst_info->op;
4849
4850 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4851
4852 alu.src[0].sel = ctx->temp_reg;
4853 alu.src[0].chan = i;
4854
4855 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
4856 alu.last = 1;
4857 r = r600_bytecode_add_alu(ctx->bc, &alu);
4858 if (r)
4859 return r;
4860 }
4861
4862 return 0;
4863 }
4864
4865 static int tgsi_iabs(struct r600_shader_ctx *ctx)
4866 {
4867 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4868 struct r600_bytecode_alu alu;
4869 int i, r;
4870 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4871 int last_inst = tgsi_last_instruction(write_mask);
4872
4873 /* tmp = -src */
4874 for (i = 0; i < 4; i++) {
4875 if (!(write_mask & (1<<i)))
4876 continue;
4877
4878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4879 alu.op = ALU_OP2_SUB_INT;
4880
4881 alu.dst.sel = ctx->temp_reg;
4882 alu.dst.chan = i;
4883 alu.dst.write = 1;
4884
4885 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4886 alu.src[0].sel = V_SQ_ALU_SRC_0;
4887
4888 if (i == last_inst)
4889 alu.last = 1;
4890 r = r600_bytecode_add_alu(ctx->bc, &alu);
4891 if (r)
4892 return r;
4893 }
4894
4895 /* dst = (src >= 0 ? src : tmp) */
4896 for (i = 0; i < 4; i++) {
4897 if (!(write_mask & (1<<i)))
4898 continue;
4899
4900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4901 alu.op = ALU_OP3_CNDGE_INT;
4902 alu.is_op3 = 1;
4903 alu.dst.write = 1;
4904
4905 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4906
4907 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4908 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4909 alu.src[2].sel = ctx->temp_reg;
4910 alu.src[2].chan = i;
4911
4912 if (i == last_inst)
4913 alu.last = 1;
4914 r = r600_bytecode_add_alu(ctx->bc, &alu);
4915 if (r)
4916 return r;
4917 }
4918 return 0;
4919 }
4920
4921 static int tgsi_issg(struct r600_shader_ctx *ctx)
4922 {
4923 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4924 struct r600_bytecode_alu alu;
4925 int i, r;
4926 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4927 int last_inst = tgsi_last_instruction(write_mask);
4928
4929 /* tmp = (src >= 0 ? src : -1) */
4930 for (i = 0; i < 4; i++) {
4931 if (!(write_mask & (1<<i)))
4932 continue;
4933
4934 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4935 alu.op = ALU_OP3_CNDGE_INT;
4936 alu.is_op3 = 1;
4937
4938 alu.dst.sel = ctx->temp_reg;
4939 alu.dst.chan = i;
4940 alu.dst.write = 1;
4941
4942 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4943 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4944 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
4945
4946 if (i == last_inst)
4947 alu.last = 1;
4948 r = r600_bytecode_add_alu(ctx->bc, &alu);
4949 if (r)
4950 return r;
4951 }
4952
4953 /* dst = (tmp > 0 ? 1 : tmp) */
4954 for (i = 0; i < 4; i++) {
4955 if (!(write_mask & (1<<i)))
4956 continue;
4957
4958 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4959 alu.op = ALU_OP3_CNDGT_INT;
4960 alu.is_op3 = 1;
4961 alu.dst.write = 1;
4962
4963 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4964
4965 alu.src[0].sel = ctx->temp_reg;
4966 alu.src[0].chan = i;
4967
4968 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4969
4970 alu.src[2].sel = ctx->temp_reg;
4971 alu.src[2].chan = i;
4972
4973 if (i == last_inst)
4974 alu.last = 1;
4975 r = r600_bytecode_add_alu(ctx->bc, &alu);
4976 if (r)
4977 return r;
4978 }
4979 return 0;
4980 }
4981
4982
4983
4984 static int tgsi_ssg(struct r600_shader_ctx *ctx)
4985 {
4986 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4987 struct r600_bytecode_alu alu;
4988 int i, r;
4989
4990 /* tmp = (src > 0 ? 1 : src) */
4991 for (i = 0; i < 4; i++) {
4992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4993 alu.op = ALU_OP3_CNDGT;
4994 alu.is_op3 = 1;
4995
4996 alu.dst.sel = ctx->temp_reg;
4997 alu.dst.chan = i;
4998
4999 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5000 alu.src[1].sel = V_SQ_ALU_SRC_1;
5001 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
5002
5003 if (i == 3)
5004 alu.last = 1;
5005 r = r600_bytecode_add_alu(ctx->bc, &alu);
5006 if (r)
5007 return r;
5008 }
5009
5010 /* dst = (-tmp > 0 ? -1 : tmp) */
5011 for (i = 0; i < 4; i++) {
5012 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5013 alu.op = ALU_OP3_CNDGT;
5014 alu.is_op3 = 1;
5015 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5016
5017 alu.src[0].sel = ctx->temp_reg;
5018 alu.src[0].chan = i;
5019 alu.src[0].neg = 1;
5020
5021 alu.src[1].sel = V_SQ_ALU_SRC_1;
5022 alu.src[1].neg = 1;
5023
5024 alu.src[2].sel = ctx->temp_reg;
5025 alu.src[2].chan = i;
5026
5027 if (i == 3)
5028 alu.last = 1;
5029 r = r600_bytecode_add_alu(ctx->bc, &alu);
5030 if (r)
5031 return r;
5032 }
5033 return 0;
5034 }
5035
5036 static int tgsi_bfi(struct r600_shader_ctx *ctx)
5037 {
5038 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5039 struct r600_bytecode_alu alu;
5040 int i, r, t1, t2;
5041
5042 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5043 int last_inst = tgsi_last_instruction(write_mask);
5044
5045 t1 = ctx->temp_reg;
5046
5047 for (i = 0; i < 4; i++) {
5048 if (!(write_mask & (1<<i)))
5049 continue;
5050
5051 /* create mask tmp */
5052 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5053 alu.op = ALU_OP2_BFM_INT;
5054 alu.dst.sel = t1;
5055 alu.dst.chan = i;
5056 alu.dst.write = 1;
5057 alu.last = i == last_inst;
5058
5059 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
5060 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5061
5062 r = r600_bytecode_add_alu(ctx->bc, &alu);
5063 if (r)
5064 return r;
5065 }
5066
5067 t2 = r600_get_temp(ctx);
5068
5069 for (i = 0; i < 4; i++) {
5070 if (!(write_mask & (1<<i)))
5071 continue;
5072
5073 /* shift insert left */
5074 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5075 alu.op = ALU_OP2_LSHL_INT;
5076 alu.dst.sel = t2;
5077 alu.dst.chan = i;
5078 alu.dst.write = 1;
5079 alu.last = i == last_inst;
5080
5081 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5082 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5083
5084 r = r600_bytecode_add_alu(ctx->bc, &alu);
5085 if (r)
5086 return r;
5087 }
5088
5089 for (i = 0; i < 4; i++) {
5090 if (!(write_mask & (1<<i)))
5091 continue;
5092
5093 /* actual bitfield insert */
5094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5095 alu.op = ALU_OP3_BFI_INT;
5096 alu.is_op3 = 1;
5097 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5098 alu.dst.chan = i;
5099 alu.dst.write = 1;
5100 alu.last = i == last_inst;
5101
5102 alu.src[0].sel = t1;
5103 alu.src[0].chan = i;
5104 alu.src[1].sel = t2;
5105 alu.src[1].chan = i;
5106 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
5107
5108 r = r600_bytecode_add_alu(ctx->bc, &alu);
5109 if (r)
5110 return r;
5111 }
5112
5113 return 0;
5114 }
5115
5116 static int tgsi_msb(struct r600_shader_ctx *ctx)
5117 {
5118 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5119 struct r600_bytecode_alu alu;
5120 int i, r, t1, t2;
5121
5122 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5123 int last_inst = tgsi_last_instruction(write_mask);
5124
5125 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
5126 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
5127
5128 t1 = ctx->temp_reg;
5129
5130 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
5131 for (i = 0; i < 4; i++) {
5132 if (!(write_mask & (1<<i)))
5133 continue;
5134
5135 /* t1 = FFBH_INT / FFBH_UINT */
5136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5137 alu.op = ctx->inst_info->op;
5138 alu.dst.sel = t1;
5139 alu.dst.chan = i;
5140 alu.dst.write = 1;
5141 alu.last = i == last_inst;
5142
5143 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5144
5145 r = r600_bytecode_add_alu(ctx->bc, &alu);
5146 if (r)
5147 return r;
5148 }
5149
5150 t2 = r600_get_temp(ctx);
5151
5152 for (i = 0; i < 4; i++) {
5153 if (!(write_mask & (1<<i)))
5154 continue;
5155
5156 /* t2 = 31 - t1 */
5157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5158 alu.op = ALU_OP2_SUB_INT;
5159 alu.dst.sel = t2;
5160 alu.dst.chan = i;
5161 alu.dst.write = 1;
5162 alu.last = i == last_inst;
5163
5164 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
5165 alu.src[0].value = 31;
5166 alu.src[1].sel = t1;
5167 alu.src[1].chan = i;
5168
5169 r = r600_bytecode_add_alu(ctx->bc, &alu);
5170 if (r)
5171 return r;
5172 }
5173
5174 for (i = 0; i < 4; i++) {
5175 if (!(write_mask & (1<<i)))
5176 continue;
5177
5178 /* result = t1 >= 0 ? t2 : t1 */
5179 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5180 alu.op = ALU_OP3_CNDGE_INT;
5181 alu.is_op3 = 1;
5182 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5183 alu.dst.chan = i;
5184 alu.dst.write = 1;
5185 alu.last = i == last_inst;
5186
5187 alu.src[0].sel = t1;
5188 alu.src[0].chan = i;
5189 alu.src[1].sel = t2;
5190 alu.src[1].chan = i;
5191 alu.src[2].sel = t1;
5192 alu.src[2].chan = i;
5193
5194 r = r600_bytecode_add_alu(ctx->bc, &alu);
5195 if (r)
5196 return r;
5197 }
5198
5199 return 0;
5200 }
5201
5202 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
5203 {
5204 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5205 struct r600_bytecode_alu alu;
5206 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
5207 unsigned location;
5208 int input;
5209
5210 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5211
5212 input = inst->Src[0].Register.Index;
5213
5214 /* Interpolators have been marked for use already by allocate_system_value_inputs */
5215 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5216 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5217 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
5218 }
5219 else {
5220 location = TGSI_INTERPOLATE_LOC_CENTROID;
5221 }
5222
5223 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
5224 if (k < 0)
5225 k = 0;
5226 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
5227 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
5228
5229 /* NOTE: currently offset is not perspective correct */
5230 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5231 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5232 int sample_gpr = -1;
5233 int gradientsH, gradientsV;
5234 struct r600_bytecode_tex tex;
5235
5236 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5237 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
5238 }
5239
5240 gradientsH = r600_get_temp(ctx);
5241 gradientsV = r600_get_temp(ctx);
5242 for (i = 0; i < 2; i++) {
5243 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5244 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
5245 tex.src_gpr = interp_gpr;
5246 tex.src_sel_x = interp_base_chan + 0;
5247 tex.src_sel_y = interp_base_chan + 1;
5248 tex.src_sel_z = 0;
5249 tex.src_sel_w = 0;
5250 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
5251 tex.dst_sel_x = 0;
5252 tex.dst_sel_y = 1;
5253 tex.dst_sel_z = 7;
5254 tex.dst_sel_w = 7;
5255 tex.inst_mod = 1; // Use per pixel gradient calculation
5256 tex.sampler_id = 0;
5257 tex.resource_id = tex.sampler_id;
5258 r = r600_bytecode_add_tex(ctx->bc, &tex);
5259 if (r)
5260 return r;
5261 }
5262
5263 for (i = 0; i < 2; i++) {
5264 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5265 alu.op = ALU_OP3_MULADD;
5266 alu.is_op3 = 1;
5267 alu.src[0].sel = gradientsH;
5268 alu.src[0].chan = i;
5269 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5270 alu.src[1].sel = sample_gpr;
5271 alu.src[1].chan = 2;
5272 }
5273 else {
5274 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
5275 }
5276 alu.src[2].sel = interp_gpr;
5277 alu.src[2].chan = interp_base_chan + i;
5278 alu.dst.sel = ctx->temp_reg;
5279 alu.dst.chan = i;
5280 alu.last = i == 1;
5281
5282 r = r600_bytecode_add_alu(ctx->bc, &alu);
5283 if (r)
5284 return r;
5285 }
5286
5287 for (i = 0; i < 2; i++) {
5288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5289 alu.op = ALU_OP3_MULADD;
5290 alu.is_op3 = 1;
5291 alu.src[0].sel = gradientsV;
5292 alu.src[0].chan = i;
5293 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5294 alu.src[1].sel = sample_gpr;
5295 alu.src[1].chan = 3;
5296 }
5297 else {
5298 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
5299 }
5300 alu.src[2].sel = ctx->temp_reg;
5301 alu.src[2].chan = i;
5302 alu.dst.sel = ctx->temp_reg;
5303 alu.dst.chan = i;
5304 alu.last = i == 1;
5305
5306 r = r600_bytecode_add_alu(ctx->bc, &alu);
5307 if (r)
5308 return r;
5309 }
5310 }
5311
5312 tmp = r600_get_temp(ctx);
5313 for (i = 0; i < 8; i++) {
5314 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5315 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
5316
5317 alu.dst.sel = tmp;
5318 if ((i > 1 && i < 6)) {
5319 alu.dst.write = 1;
5320 }
5321 else {
5322 alu.dst.write = 0;
5323 }
5324 alu.dst.chan = i % 4;
5325
5326 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5327 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5328 alu.src[0].sel = ctx->temp_reg;
5329 alu.src[0].chan = 1 - (i % 2);
5330 } else {
5331 alu.src[0].sel = interp_gpr;
5332 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
5333 }
5334 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
5335 alu.src[1].chan = 0;
5336
5337 alu.last = i % 4 == 3;
5338 alu.bank_swizzle_force = SQ_ALU_VEC_210;
5339
5340 r = r600_bytecode_add_alu(ctx->bc, &alu);
5341 if (r)
5342 return r;
5343 }
5344
5345 // INTERP can't swizzle dst
5346 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5347 for (i = 0; i <= lasti; i++) {
5348 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5349 continue;
5350
5351 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5352 alu.op = ALU_OP1_MOV;
5353 alu.src[0].sel = tmp;
5354 alu.src[0].chan = ctx->src[0].swizzle[i];
5355 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5356 alu.dst.write = 1;
5357 alu.last = i == lasti;
5358 r = r600_bytecode_add_alu(ctx->bc, &alu);
5359 if (r)
5360 return r;
5361 }
5362
5363 return 0;
5364 }
5365
5366
5367 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
5368 {
5369 struct r600_bytecode_alu alu;
5370 int i, r;
5371
5372 for (i = 0; i < 4; i++) {
5373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5374 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
5375 alu.op = ALU_OP0_NOP;
5376 alu.dst.chan = i;
5377 } else {
5378 alu.op = ALU_OP1_MOV;
5379 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5380 alu.src[0].sel = ctx->temp_reg;
5381 alu.src[0].chan = i;
5382 }
5383 if (i == 3) {
5384 alu.last = 1;
5385 }
5386 r = r600_bytecode_add_alu(ctx->bc, &alu);
5387 if (r)
5388 return r;
5389 }
5390 return 0;
5391 }
5392
5393 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
5394 unsigned temp, int chan,
5395 struct r600_bytecode_alu_src *bc_src,
5396 const struct r600_shader_src *shader_src)
5397 {
5398 struct r600_bytecode_alu alu;
5399 int r;
5400
5401 r600_bytecode_src(bc_src, shader_src, chan);
5402
5403 /* op3 operands don't support abs modifier */
5404 if (bc_src->abs) {
5405 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
5406 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5407 alu.op = ALU_OP1_MOV;
5408 alu.dst.sel = temp;
5409 alu.dst.chan = chan;
5410 alu.dst.write = 1;
5411
5412 alu.src[0] = *bc_src;
5413 alu.last = true; // sufficient?
5414 r = r600_bytecode_add_alu(ctx->bc, &alu);
5415 if (r)
5416 return r;
5417
5418 memset(bc_src, 0, sizeof(*bc_src));
5419 bc_src->sel = temp;
5420 bc_src->chan = chan;
5421 }
5422 return 0;
5423 }
5424
5425 static int tgsi_op3(struct r600_shader_ctx *ctx)
5426 {
5427 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5428 struct r600_bytecode_alu alu;
5429 int i, j, r;
5430 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5431 int temp_regs[4];
5432
5433 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5434 temp_regs[j] = 0;
5435 if (ctx->src[j].abs)
5436 temp_regs[j] = r600_get_temp(ctx);
5437 }
5438 for (i = 0; i < lasti + 1; i++) {
5439 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5440 continue;
5441
5442 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5443 alu.op = ctx->inst_info->op;
5444 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5445 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
5446 if (r)
5447 return r;
5448 }
5449
5450 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5451 alu.dst.chan = i;
5452 alu.dst.write = 1;
5453 alu.is_op3 = 1;
5454 if (i == lasti) {
5455 alu.last = 1;
5456 }
5457 r = r600_bytecode_add_alu(ctx->bc, &alu);
5458 if (r)
5459 return r;
5460 }
5461 return 0;
5462 }
5463
5464 static int tgsi_dp(struct r600_shader_ctx *ctx)
5465 {
5466 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5467 struct r600_bytecode_alu alu;
5468 int i, j, r;
5469
5470 for (i = 0; i < 4; i++) {
5471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5472 alu.op = ctx->inst_info->op;
5473 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5474 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5475 }
5476
5477 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5478 alu.dst.chan = i;
5479 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5480 /* handle some special cases */
5481 switch (inst->Instruction.Opcode) {
5482 case TGSI_OPCODE_DP2:
5483 if (i > 1) {
5484 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5485 alu.src[0].chan = alu.src[1].chan = 0;
5486 }
5487 break;
5488 case TGSI_OPCODE_DP3:
5489 if (i > 2) {
5490 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5491 alu.src[0].chan = alu.src[1].chan = 0;
5492 }
5493 break;
5494 case TGSI_OPCODE_DPH:
5495 if (i == 3) {
5496 alu.src[0].sel = V_SQ_ALU_SRC_1;
5497 alu.src[0].chan = 0;
5498 alu.src[0].neg = 0;
5499 }
5500 break;
5501 default:
5502 break;
5503 }
5504 if (i == 3) {
5505 alu.last = 1;
5506 }
5507 r = r600_bytecode_add_alu(ctx->bc, &alu);
5508 if (r)
5509 return r;
5510 }
5511 return 0;
5512 }
5513
5514 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
5515 unsigned index)
5516 {
5517 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5518 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
5519 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
5520 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
5521 ctx->src[index].neg || ctx->src[index].abs ||
5522 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
5523 }
5524
5525 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
5526 unsigned index)
5527 {
5528 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5529 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
5530 }
5531
5532 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
5533 {
5534 struct r600_bytecode_vtx vtx;
5535 struct r600_bytecode_alu alu;
5536 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5537 int src_gpr, r, i;
5538 int id = tgsi_tex_get_src_gpr(ctx, 1);
5539
5540 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5541 if (src_requires_loading) {
5542 for (i = 0; i < 4; i++) {
5543 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5544 alu.op = ALU_OP1_MOV;
5545 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5546 alu.dst.sel = ctx->temp_reg;
5547 alu.dst.chan = i;
5548 if (i == 3)
5549 alu.last = 1;
5550 alu.dst.write = 1;
5551 r = r600_bytecode_add_alu(ctx->bc, &alu);
5552 if (r)
5553 return r;
5554 }
5555 src_gpr = ctx->temp_reg;
5556 }
5557
5558 memset(&vtx, 0, sizeof(vtx));
5559 vtx.op = FETCH_OP_VFETCH;
5560 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
5561 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
5562 vtx.src_gpr = src_gpr;
5563 vtx.mega_fetch_count = 16;
5564 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5565 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
5566 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
5567 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
5568 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
5569 vtx.use_const_fields = 1;
5570
5571 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
5572 return r;
5573
5574 if (ctx->bc->chip_class >= EVERGREEN)
5575 return 0;
5576
5577 for (i = 0; i < 4; i++) {
5578 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5579 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5580 continue;
5581
5582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5583 alu.op = ALU_OP2_AND_INT;
5584
5585 alu.dst.chan = i;
5586 alu.dst.sel = vtx.dst_gpr;
5587 alu.dst.write = 1;
5588
5589 alu.src[0].sel = vtx.dst_gpr;
5590 alu.src[0].chan = i;
5591
5592 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
5593 alu.src[1].sel += (id * 2);
5594 alu.src[1].chan = i % 4;
5595 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5596
5597 if (i == lasti)
5598 alu.last = 1;
5599 r = r600_bytecode_add_alu(ctx->bc, &alu);
5600 if (r)
5601 return r;
5602 }
5603
5604 if (inst->Dst[0].Register.WriteMask & 3) {
5605 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5606 alu.op = ALU_OP2_OR_INT;
5607
5608 alu.dst.chan = 3;
5609 alu.dst.sel = vtx.dst_gpr;
5610 alu.dst.write = 1;
5611
5612 alu.src[0].sel = vtx.dst_gpr;
5613 alu.src[0].chan = 3;
5614
5615 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
5616 alu.src[1].chan = 0;
5617 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5618
5619 alu.last = 1;
5620 r = r600_bytecode_add_alu(ctx->bc, &alu);
5621 if (r)
5622 return r;
5623 }
5624 return 0;
5625 }
5626
5627 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
5628 {
5629 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5630 struct r600_bytecode_alu alu;
5631 int r;
5632 int id = tgsi_tex_get_src_gpr(ctx, 1);
5633
5634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5635 alu.op = ALU_OP1_MOV;
5636 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
5637 if (ctx->bc->chip_class >= EVERGREEN) {
5638 /* channel 0 or 2 of each word */
5639 alu.src[0].sel += (id / 2);
5640 alu.src[0].chan = (id % 2) * 2;
5641 } else {
5642 /* r600 we have them at channel 2 of the second dword */
5643 alu.src[0].sel += (id * 2) + 1;
5644 alu.src[0].chan = 1;
5645 }
5646 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5647 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5648 alu.last = 1;
5649 r = r600_bytecode_add_alu(ctx->bc, &alu);
5650 if (r)
5651 return r;
5652 return 0;
5653 }
5654
5655 static int tgsi_tex(struct r600_shader_ctx *ctx)
5656 {
5657 static float one_point_five = 1.5f;
5658 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5659 struct r600_bytecode_tex tex;
5660 struct r600_bytecode_alu alu;
5661 unsigned src_gpr;
5662 int r, i, j;
5663 int opcode;
5664 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
5665 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5666 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
5667 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
5668
5669 bool txf_add_offsets = inst->Texture.NumOffsets &&
5670 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5671 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
5672
5673 /* Texture fetch instructions can only use gprs as source.
5674 * Also they cannot negate the source or take the absolute value */
5675 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
5676 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
5677 tgsi_tex_src_requires_loading(ctx, 0)) ||
5678 read_compressed_msaa || txf_add_offsets;
5679
5680 boolean src_loaded = FALSE;
5681 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
5682 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
5683 boolean has_txq_cube_array_z = false;
5684 unsigned sampler_index_mode;
5685
5686 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
5687 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5688 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
5689 if (inst->Dst[0].Register.WriteMask & 4) {
5690 ctx->shader->has_txq_cube_array_z_comp = true;
5691 has_txq_cube_array_z = true;
5692 }
5693
5694 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
5695 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5696 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
5697 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
5698 sampler_src_reg = 2;
5699
5700 /* TGSI moves the sampler to src reg 3 for TXD */
5701 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
5702 sampler_src_reg = 3;
5703
5704 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
5705
5706 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5707
5708 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
5709 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
5710 ctx->shader->uses_tex_buffers = true;
5711 return r600_do_buffer_txq(ctx);
5712 }
5713 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
5714 if (ctx->bc->chip_class < EVERGREEN)
5715 ctx->shader->uses_tex_buffers = true;
5716 return do_vtx_fetch_inst(ctx, src_requires_loading);
5717 }
5718 }
5719
5720 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
5721 int out_chan;
5722 /* Add perspective divide */
5723 if (ctx->bc->chip_class == CAYMAN) {
5724 out_chan = 2;
5725 for (i = 0; i < 3; i++) {
5726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5727 alu.op = ALU_OP1_RECIP_IEEE;
5728 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5729
5730 alu.dst.sel = ctx->temp_reg;
5731 alu.dst.chan = i;
5732 if (i == 2)
5733 alu.last = 1;
5734 if (out_chan == i)
5735 alu.dst.write = 1;
5736 r = r600_bytecode_add_alu(ctx->bc, &alu);
5737 if (r)
5738 return r;
5739 }
5740
5741 } else {
5742 out_chan = 3;
5743 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5744 alu.op = ALU_OP1_RECIP_IEEE;
5745 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5746
5747 alu.dst.sel = ctx->temp_reg;
5748 alu.dst.chan = out_chan;
5749 alu.last = 1;
5750 alu.dst.write = 1;
5751 r = r600_bytecode_add_alu(ctx->bc, &alu);
5752 if (r)
5753 return r;
5754 }
5755
5756 for (i = 0; i < 3; i++) {
5757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5758 alu.op = ALU_OP2_MUL;
5759 alu.src[0].sel = ctx->temp_reg;
5760 alu.src[0].chan = out_chan;
5761 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5762 alu.dst.sel = ctx->temp_reg;
5763 alu.dst.chan = i;
5764 alu.dst.write = 1;
5765 r = r600_bytecode_add_alu(ctx->bc, &alu);
5766 if (r)
5767 return r;
5768 }
5769 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5770 alu.op = ALU_OP1_MOV;
5771 alu.src[0].sel = V_SQ_ALU_SRC_1;
5772 alu.src[0].chan = 0;
5773 alu.dst.sel = ctx->temp_reg;
5774 alu.dst.chan = 3;
5775 alu.last = 1;
5776 alu.dst.write = 1;
5777 r = r600_bytecode_add_alu(ctx->bc, &alu);
5778 if (r)
5779 return r;
5780 src_loaded = TRUE;
5781 src_gpr = ctx->temp_reg;
5782 }
5783
5784
5785 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
5786 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5787 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5788 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
5789 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
5790 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
5791
5792 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
5793 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
5794
5795 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
5796 for (i = 0; i < 4; i++) {
5797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5798 alu.op = ALU_OP2_CUBE;
5799 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5800 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
5801 alu.dst.sel = ctx->temp_reg;
5802 alu.dst.chan = i;
5803 if (i == 3)
5804 alu.last = 1;
5805 alu.dst.write = 1;
5806 r = r600_bytecode_add_alu(ctx->bc, &alu);
5807 if (r)
5808 return r;
5809 }
5810
5811 /* tmp1.z = RCP_e(|tmp1.z|) */
5812 if (ctx->bc->chip_class == CAYMAN) {
5813 for (i = 0; i < 3; i++) {
5814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5815 alu.op = ALU_OP1_RECIP_IEEE;
5816 alu.src[0].sel = ctx->temp_reg;
5817 alu.src[0].chan = 2;
5818 alu.src[0].abs = 1;
5819 alu.dst.sel = ctx->temp_reg;
5820 alu.dst.chan = i;
5821 if (i == 2)
5822 alu.dst.write = 1;
5823 if (i == 2)
5824 alu.last = 1;
5825 r = r600_bytecode_add_alu(ctx->bc, &alu);
5826 if (r)
5827 return r;
5828 }
5829 } else {
5830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5831 alu.op = ALU_OP1_RECIP_IEEE;
5832 alu.src[0].sel = ctx->temp_reg;
5833 alu.src[0].chan = 2;
5834 alu.src[0].abs = 1;
5835 alu.dst.sel = ctx->temp_reg;
5836 alu.dst.chan = 2;
5837 alu.dst.write = 1;
5838 alu.last = 1;
5839 r = r600_bytecode_add_alu(ctx->bc, &alu);
5840 if (r)
5841 return r;
5842 }
5843
5844 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
5845 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
5846 * muladd has no writemask, have to use another temp
5847 */
5848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5849 alu.op = ALU_OP3_MULADD;
5850 alu.is_op3 = 1;
5851
5852 alu.src[0].sel = ctx->temp_reg;
5853 alu.src[0].chan = 0;
5854 alu.src[1].sel = ctx->temp_reg;
5855 alu.src[1].chan = 2;
5856
5857 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5858 alu.src[2].chan = 0;
5859 alu.src[2].value = *(uint32_t *)&one_point_five;
5860
5861 alu.dst.sel = ctx->temp_reg;
5862 alu.dst.chan = 0;
5863 alu.dst.write = 1;
5864
5865 r = r600_bytecode_add_alu(ctx->bc, &alu);
5866 if (r)
5867 return r;
5868
5869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5870 alu.op = ALU_OP3_MULADD;
5871 alu.is_op3 = 1;
5872
5873 alu.src[0].sel = ctx->temp_reg;
5874 alu.src[0].chan = 1;
5875 alu.src[1].sel = ctx->temp_reg;
5876 alu.src[1].chan = 2;
5877
5878 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5879 alu.src[2].chan = 0;
5880 alu.src[2].value = *(uint32_t *)&one_point_five;
5881
5882 alu.dst.sel = ctx->temp_reg;
5883 alu.dst.chan = 1;
5884 alu.dst.write = 1;
5885
5886 alu.last = 1;
5887 r = r600_bytecode_add_alu(ctx->bc, &alu);
5888 if (r)
5889 return r;
5890 /* write initial compare value into Z component
5891 - W src 0 for shadow cube
5892 - X src 1 for shadow cube array */
5893 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5894 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5896 alu.op = ALU_OP1_MOV;
5897 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
5898 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5899 else
5900 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5901 alu.dst.sel = ctx->temp_reg;
5902 alu.dst.chan = 2;
5903 alu.dst.write = 1;
5904 alu.last = 1;
5905 r = r600_bytecode_add_alu(ctx->bc, &alu);
5906 if (r)
5907 return r;
5908 }
5909
5910 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5911 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5912 if (ctx->bc->chip_class >= EVERGREEN) {
5913 int mytmp = r600_get_temp(ctx);
5914 static const float eight = 8.0f;
5915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5916 alu.op = ALU_OP1_MOV;
5917 alu.src[0].sel = ctx->temp_reg;
5918 alu.src[0].chan = 3;
5919 alu.dst.sel = mytmp;
5920 alu.dst.chan = 0;
5921 alu.dst.write = 1;
5922 alu.last = 1;
5923 r = r600_bytecode_add_alu(ctx->bc, &alu);
5924 if (r)
5925 return r;
5926
5927 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
5928 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5929 alu.op = ALU_OP3_MULADD;
5930 alu.is_op3 = 1;
5931 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5932 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5933 alu.src[1].chan = 0;
5934 alu.src[1].value = *(uint32_t *)&eight;
5935 alu.src[2].sel = mytmp;
5936 alu.src[2].chan = 0;
5937 alu.dst.sel = ctx->temp_reg;
5938 alu.dst.chan = 3;
5939 alu.dst.write = 1;
5940 alu.last = 1;
5941 r = r600_bytecode_add_alu(ctx->bc, &alu);
5942 if (r)
5943 return r;
5944 } else if (ctx->bc->chip_class < EVERGREEN) {
5945 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5946 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
5947 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5948 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5949 tex.src_gpr = r600_get_temp(ctx);
5950 tex.src_sel_x = 0;
5951 tex.src_sel_y = 0;
5952 tex.src_sel_z = 0;
5953 tex.src_sel_w = 0;
5954 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
5955 tex.coord_type_x = 1;
5956 tex.coord_type_y = 1;
5957 tex.coord_type_z = 1;
5958 tex.coord_type_w = 1;
5959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5960 alu.op = ALU_OP1_MOV;
5961 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5962 alu.dst.sel = tex.src_gpr;
5963 alu.dst.chan = 0;
5964 alu.last = 1;
5965 alu.dst.write = 1;
5966 r = r600_bytecode_add_alu(ctx->bc, &alu);
5967 if (r)
5968 return r;
5969
5970 r = r600_bytecode_add_tex(ctx->bc, &tex);
5971 if (r)
5972 return r;
5973 }
5974
5975 }
5976
5977 /* for cube forms of lod and bias we need to route things */
5978 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
5979 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
5980 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5981 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
5982 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5983 alu.op = ALU_OP1_MOV;
5984 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5985 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
5986 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5987 else
5988 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5989 alu.dst.sel = ctx->temp_reg;
5990 alu.dst.chan = 2;
5991 alu.last = 1;
5992 alu.dst.write = 1;
5993 r = r600_bytecode_add_alu(ctx->bc, &alu);
5994 if (r)
5995 return r;
5996 }
5997
5998 src_loaded = TRUE;
5999 src_gpr = ctx->temp_reg;
6000 }
6001
6002 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
6003 int temp_h = 0, temp_v = 0;
6004 int start_val = 0;
6005
6006 /* if we've already loaded the src (i.e. CUBE don't reload it). */
6007 if (src_loaded == TRUE)
6008 start_val = 1;
6009 else
6010 src_loaded = TRUE;
6011 for (i = start_val; i < 3; i++) {
6012 int treg = r600_get_temp(ctx);
6013
6014 if (i == 0)
6015 src_gpr = treg;
6016 else if (i == 1)
6017 temp_h = treg;
6018 else
6019 temp_v = treg;
6020
6021 for (j = 0; j < 4; j++) {
6022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6023 alu.op = ALU_OP1_MOV;
6024 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
6025 alu.dst.sel = treg;
6026 alu.dst.chan = j;
6027 if (j == 3)
6028 alu.last = 1;
6029 alu.dst.write = 1;
6030 r = r600_bytecode_add_alu(ctx->bc, &alu);
6031 if (r)
6032 return r;
6033 }
6034 }
6035 for (i = 1; i < 3; i++) {
6036 /* set gradients h/v */
6037 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6038 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
6039 FETCH_OP_SET_GRADIENTS_V;
6040 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6041 tex.sampler_index_mode = sampler_index_mode;
6042 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6043 tex.resource_index_mode = sampler_index_mode;
6044
6045 tex.src_gpr = (i == 1) ? temp_h : temp_v;
6046 tex.src_sel_x = 0;
6047 tex.src_sel_y = 1;
6048 tex.src_sel_z = 2;
6049 tex.src_sel_w = 3;
6050
6051 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
6052 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
6053 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
6054 tex.coord_type_x = 1;
6055 tex.coord_type_y = 1;
6056 tex.coord_type_z = 1;
6057 tex.coord_type_w = 1;
6058 }
6059 r = r600_bytecode_add_tex(ctx->bc, &tex);
6060 if (r)
6061 return r;
6062 }
6063 }
6064
6065 if (src_requires_loading && !src_loaded) {
6066 for (i = 0; i < 4; i++) {
6067 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6068 alu.op = ALU_OP1_MOV;
6069 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6070 alu.dst.sel = ctx->temp_reg;
6071 alu.dst.chan = i;
6072 if (i == 3)
6073 alu.last = 1;
6074 alu.dst.write = 1;
6075 r = r600_bytecode_add_alu(ctx->bc, &alu);
6076 if (r)
6077 return r;
6078 }
6079 src_loaded = TRUE;
6080 src_gpr = ctx->temp_reg;
6081 }
6082
6083 /* get offset values */
6084 if (inst->Texture.NumOffsets) {
6085 assert(inst->Texture.NumOffsets == 1);
6086
6087 /* The texture offset feature doesn't work with the TXF instruction
6088 * and must be emulated by adding the offset to the texture coordinates. */
6089 if (txf_add_offsets) {
6090 const struct tgsi_texture_offset *off = inst->TexOffsets;
6091
6092 switch (inst->Texture.Texture) {
6093 case TGSI_TEXTURE_3D:
6094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6095 alu.op = ALU_OP2_ADD_INT;
6096 alu.src[0].sel = src_gpr;
6097 alu.src[0].chan = 2;
6098 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6099 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
6100 alu.dst.sel = src_gpr;
6101 alu.dst.chan = 2;
6102 alu.dst.write = 1;
6103 alu.last = 1;
6104 r = r600_bytecode_add_alu(ctx->bc, &alu);
6105 if (r)
6106 return r;
6107 /* fall through */
6108
6109 case TGSI_TEXTURE_2D:
6110 case TGSI_TEXTURE_SHADOW2D:
6111 case TGSI_TEXTURE_RECT:
6112 case TGSI_TEXTURE_SHADOWRECT:
6113 case TGSI_TEXTURE_2D_ARRAY:
6114 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6115 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6116 alu.op = ALU_OP2_ADD_INT;
6117 alu.src[0].sel = src_gpr;
6118 alu.src[0].chan = 1;
6119 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6120 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
6121 alu.dst.sel = src_gpr;
6122 alu.dst.chan = 1;
6123 alu.dst.write = 1;
6124 alu.last = 1;
6125 r = r600_bytecode_add_alu(ctx->bc, &alu);
6126 if (r)
6127 return r;
6128 /* fall through */
6129
6130 case TGSI_TEXTURE_1D:
6131 case TGSI_TEXTURE_SHADOW1D:
6132 case TGSI_TEXTURE_1D_ARRAY:
6133 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6135 alu.op = ALU_OP2_ADD_INT;
6136 alu.src[0].sel = src_gpr;
6137 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6138 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
6139 alu.dst.sel = src_gpr;
6140 alu.dst.write = 1;
6141 alu.last = 1;
6142 r = r600_bytecode_add_alu(ctx->bc, &alu);
6143 if (r)
6144 return r;
6145 break;
6146 /* texture offsets do not apply to other texture targets */
6147 }
6148 } else {
6149 switch (inst->Texture.Texture) {
6150 case TGSI_TEXTURE_3D:
6151 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
6152 /* fallthrough */
6153 case TGSI_TEXTURE_2D:
6154 case TGSI_TEXTURE_SHADOW2D:
6155 case TGSI_TEXTURE_RECT:
6156 case TGSI_TEXTURE_SHADOWRECT:
6157 case TGSI_TEXTURE_2D_ARRAY:
6158 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6159 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
6160 /* fallthrough */
6161 case TGSI_TEXTURE_1D:
6162 case TGSI_TEXTURE_SHADOW1D:
6163 case TGSI_TEXTURE_1D_ARRAY:
6164 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6165 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
6166 }
6167 }
6168 }
6169
6170 /* Obtain the sample index for reading a compressed MSAA color texture.
6171 * To read the FMASK, we use the ldfptr instruction, which tells us
6172 * where the samples are stored.
6173 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
6174 * which is the identity mapping. Each nibble says which physical sample
6175 * should be fetched to get that sample.
6176 *
6177 * Assume src.z contains the sample index. It should be modified like this:
6178 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
6179 * Then fetch the texel with src.
6180 */
6181 if (read_compressed_msaa) {
6182 unsigned sample_chan = 3;
6183 unsigned temp = r600_get_temp(ctx);
6184 assert(src_loaded);
6185
6186 /* temp.w = ldfptr() */
6187 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6188 tex.op = FETCH_OP_LD;
6189 tex.inst_mod = 1; /* to indicate this is ldfptr */
6190 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6191 tex.sampler_index_mode = sampler_index_mode;
6192 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6193 tex.resource_index_mode = sampler_index_mode;
6194 tex.src_gpr = src_gpr;
6195 tex.dst_gpr = temp;
6196 tex.dst_sel_x = 7; /* mask out these components */
6197 tex.dst_sel_y = 7;
6198 tex.dst_sel_z = 7;
6199 tex.dst_sel_w = 0; /* store X */
6200 tex.src_sel_x = 0;
6201 tex.src_sel_y = 1;
6202 tex.src_sel_z = 2;
6203 tex.src_sel_w = 3;
6204 tex.offset_x = offset_x;
6205 tex.offset_y = offset_y;
6206 tex.offset_z = offset_z;
6207 r = r600_bytecode_add_tex(ctx->bc, &tex);
6208 if (r)
6209 return r;
6210
6211 /* temp.x = sample_index*4 */
6212 if (ctx->bc->chip_class == CAYMAN) {
6213 for (i = 0 ; i < 4; i++) {
6214 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6215 alu.op = ALU_OP2_MULLO_INT;
6216 alu.src[0].sel = src_gpr;
6217 alu.src[0].chan = sample_chan;
6218 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6219 alu.src[1].value = 4;
6220 alu.dst.sel = temp;
6221 alu.dst.chan = i;
6222 alu.dst.write = i == 0;
6223 if (i == 3)
6224 alu.last = 1;
6225 r = r600_bytecode_add_alu(ctx->bc, &alu);
6226 if (r)
6227 return r;
6228 }
6229 } else {
6230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6231 alu.op = ALU_OP2_MULLO_INT;
6232 alu.src[0].sel = src_gpr;
6233 alu.src[0].chan = sample_chan;
6234 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6235 alu.src[1].value = 4;
6236 alu.dst.sel = temp;
6237 alu.dst.chan = 0;
6238 alu.dst.write = 1;
6239 alu.last = 1;
6240 r = r600_bytecode_add_alu(ctx->bc, &alu);
6241 if (r)
6242 return r;
6243 }
6244
6245 /* sample_index = temp.w >> temp.x */
6246 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6247 alu.op = ALU_OP2_LSHR_INT;
6248 alu.src[0].sel = temp;
6249 alu.src[0].chan = 3;
6250 alu.src[1].sel = temp;
6251 alu.src[1].chan = 0;
6252 alu.dst.sel = src_gpr;
6253 alu.dst.chan = sample_chan;
6254 alu.dst.write = 1;
6255 alu.last = 1;
6256 r = r600_bytecode_add_alu(ctx->bc, &alu);
6257 if (r)
6258 return r;
6259
6260 /* sample_index & 0xF */
6261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6262 alu.op = ALU_OP2_AND_INT;
6263 alu.src[0].sel = src_gpr;
6264 alu.src[0].chan = sample_chan;
6265 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6266 alu.src[1].value = 0xF;
6267 alu.dst.sel = src_gpr;
6268 alu.dst.chan = sample_chan;
6269 alu.dst.write = 1;
6270 alu.last = 1;
6271 r = r600_bytecode_add_alu(ctx->bc, &alu);
6272 if (r)
6273 return r;
6274 #if 0
6275 /* visualize the FMASK */
6276 for (i = 0; i < 4; i++) {
6277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6278 alu.op = ALU_OP1_INT_TO_FLT;
6279 alu.src[0].sel = src_gpr;
6280 alu.src[0].chan = sample_chan;
6281 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6282 alu.dst.chan = i;
6283 alu.dst.write = 1;
6284 alu.last = 1;
6285 r = r600_bytecode_add_alu(ctx->bc, &alu);
6286 if (r)
6287 return r;
6288 }
6289 return 0;
6290 #endif
6291 }
6292
6293 /* does this shader want a num layers from TXQ for a cube array? */
6294 if (has_txq_cube_array_z) {
6295 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6296
6297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6298 alu.op = ALU_OP1_MOV;
6299
6300 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6301 if (ctx->bc->chip_class >= EVERGREEN) {
6302 /* channel 1 or 3 of each word */
6303 alu.src[0].sel += (id / 2);
6304 alu.src[0].chan = ((id % 2) * 2) + 1;
6305 } else {
6306 /* r600 we have them at channel 2 of the second dword */
6307 alu.src[0].sel += (id * 2) + 1;
6308 alu.src[0].chan = 2;
6309 }
6310 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6311 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
6312 alu.last = 1;
6313 r = r600_bytecode_add_alu(ctx->bc, &alu);
6314 if (r)
6315 return r;
6316 /* disable writemask from texture instruction */
6317 inst->Dst[0].Register.WriteMask &= ~4;
6318 }
6319
6320 opcode = ctx->inst_info->op;
6321 if (opcode == FETCH_OP_GATHER4 &&
6322 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
6323 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
6324 opcode = FETCH_OP_GATHER4_O;
6325
6326 /* GATHER4_O/GATHER4_C_O use offset values loaded by
6327 SET_TEXTURE_OFFSETS instruction. The immediate offset values
6328 encoded in the instruction are ignored. */
6329 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6330 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
6331 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6332 tex.sampler_index_mode = sampler_index_mode;
6333 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6334 tex.resource_index_mode = sampler_index_mode;
6335
6336 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
6337 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
6338 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
6339 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
6340 tex.src_sel_w = 4;
6341
6342 tex.dst_sel_x = 7;
6343 tex.dst_sel_y = 7;
6344 tex.dst_sel_z = 7;
6345 tex.dst_sel_w = 7;
6346
6347 r = r600_bytecode_add_tex(ctx->bc, &tex);
6348 if (r)
6349 return r;
6350 }
6351
6352 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6353 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6354 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6355 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6356 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
6357 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6358 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6359 switch (opcode) {
6360 case FETCH_OP_SAMPLE:
6361 opcode = FETCH_OP_SAMPLE_C;
6362 break;
6363 case FETCH_OP_SAMPLE_L:
6364 opcode = FETCH_OP_SAMPLE_C_L;
6365 break;
6366 case FETCH_OP_SAMPLE_LB:
6367 opcode = FETCH_OP_SAMPLE_C_LB;
6368 break;
6369 case FETCH_OP_SAMPLE_G:
6370 opcode = FETCH_OP_SAMPLE_C_G;
6371 break;
6372 /* Texture gather variants */
6373 case FETCH_OP_GATHER4:
6374 opcode = FETCH_OP_GATHER4_C;
6375 break;
6376 case FETCH_OP_GATHER4_O:
6377 opcode = FETCH_OP_GATHER4_C_O;
6378 break;
6379 }
6380 }
6381
6382 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6383 tex.op = opcode;
6384
6385 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6386 tex.sampler_index_mode = sampler_index_mode;
6387 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6388 tex.resource_index_mode = sampler_index_mode;
6389 tex.src_gpr = src_gpr;
6390 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6391
6392 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
6393 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
6394 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
6395 }
6396
6397 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
6398 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
6399 tex.inst_mod = texture_component_select;
6400
6401 if (ctx->bc->chip_class == CAYMAN) {
6402 /* GATHER4 result order is different from TGSI TG4 */
6403 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
6404 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
6405 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
6406 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6407 } else {
6408 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6409 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6410 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6411 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6412 }
6413 }
6414 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
6415 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6416 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6417 tex.dst_sel_z = 7;
6418 tex.dst_sel_w = 7;
6419 }
6420 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
6421 tex.dst_sel_x = 3;
6422 tex.dst_sel_y = 7;
6423 tex.dst_sel_z = 7;
6424 tex.dst_sel_w = 7;
6425 }
6426 else {
6427 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6428 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6429 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6430 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6431 }
6432
6433
6434 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
6435 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
6436 tex.src_sel_x = 4;
6437 tex.src_sel_y = 4;
6438 tex.src_sel_z = 4;
6439 tex.src_sel_w = 4;
6440 } else if (src_loaded) {
6441 tex.src_sel_x = 0;
6442 tex.src_sel_y = 1;
6443 tex.src_sel_z = 2;
6444 tex.src_sel_w = 3;
6445 } else {
6446 tex.src_sel_x = ctx->src[0].swizzle[0];
6447 tex.src_sel_y = ctx->src[0].swizzle[1];
6448 tex.src_sel_z = ctx->src[0].swizzle[2];
6449 tex.src_sel_w = ctx->src[0].swizzle[3];
6450 tex.src_rel = ctx->src[0].rel;
6451 }
6452
6453 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6454 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6455 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6456 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6457 tex.src_sel_x = 1;
6458 tex.src_sel_y = 0;
6459 tex.src_sel_z = 3;
6460 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
6461 }
6462
6463 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
6464 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
6465 tex.coord_type_x = 1;
6466 tex.coord_type_y = 1;
6467 }
6468 tex.coord_type_z = 1;
6469 tex.coord_type_w = 1;
6470
6471 tex.offset_x = offset_x;
6472 tex.offset_y = offset_y;
6473 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
6474 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6475 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
6476 tex.offset_z = 0;
6477 }
6478 else {
6479 tex.offset_z = offset_z;
6480 }
6481
6482 /* Put the depth for comparison in W.
6483 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
6484 * Some instructions expect the depth in Z. */
6485 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6486 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6487 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6488 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
6489 opcode != FETCH_OP_SAMPLE_C_L &&
6490 opcode != FETCH_OP_SAMPLE_C_LB) {
6491 tex.src_sel_w = tex.src_sel_z;
6492 }
6493
6494 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
6495 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
6496 if (opcode == FETCH_OP_SAMPLE_C_L ||
6497 opcode == FETCH_OP_SAMPLE_C_LB) {
6498 /* the array index is read from Y */
6499 tex.coord_type_y = 0;
6500 } else {
6501 /* the array index is read from Z */
6502 tex.coord_type_z = 0;
6503 tex.src_sel_z = tex.src_sel_y;
6504 }
6505 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6506 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6507 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6508 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6509 (ctx->bc->chip_class >= EVERGREEN)))
6510 /* the array index is read from Z */
6511 tex.coord_type_z = 0;
6512
6513 /* mask unused source components */
6514 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
6515 switch (inst->Texture.Texture) {
6516 case TGSI_TEXTURE_2D:
6517 case TGSI_TEXTURE_RECT:
6518 tex.src_sel_z = 7;
6519 tex.src_sel_w = 7;
6520 break;
6521 case TGSI_TEXTURE_1D_ARRAY:
6522 tex.src_sel_y = 7;
6523 tex.src_sel_w = 7;
6524 break;
6525 case TGSI_TEXTURE_1D:
6526 tex.src_sel_y = 7;
6527 tex.src_sel_z = 7;
6528 tex.src_sel_w = 7;
6529 break;
6530 }
6531 }
6532
6533 r = r600_bytecode_add_tex(ctx->bc, &tex);
6534 if (r)
6535 return r;
6536
6537 /* add shadow ambient support - gallium doesn't do it yet */
6538 return 0;
6539 }
6540
6541 static int tgsi_lrp(struct r600_shader_ctx *ctx)
6542 {
6543 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6544 struct r600_bytecode_alu alu;
6545 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6546 unsigned i, temp_regs[2];
6547 int r;
6548
6549 /* optimize if it's just an equal balance */
6550 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
6551 for (i = 0; i < lasti + 1; i++) {
6552 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6553 continue;
6554
6555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6556 alu.op = ALU_OP2_ADD;
6557 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6558 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6559 alu.omod = 3;
6560 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6561 alu.dst.chan = i;
6562 if (i == lasti) {
6563 alu.last = 1;
6564 }
6565 r = r600_bytecode_add_alu(ctx->bc, &alu);
6566 if (r)
6567 return r;
6568 }
6569 return 0;
6570 }
6571
6572 /* 1 - src0 */
6573 for (i = 0; i < lasti + 1; i++) {
6574 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6575 continue;
6576
6577 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6578 alu.op = ALU_OP2_ADD;
6579 alu.src[0].sel = V_SQ_ALU_SRC_1;
6580 alu.src[0].chan = 0;
6581 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6582 r600_bytecode_src_toggle_neg(&alu.src[1]);
6583 alu.dst.sel = ctx->temp_reg;
6584 alu.dst.chan = i;
6585 if (i == lasti) {
6586 alu.last = 1;
6587 }
6588 alu.dst.write = 1;
6589 r = r600_bytecode_add_alu(ctx->bc, &alu);
6590 if (r)
6591 return r;
6592 }
6593
6594 /* (1 - src0) * src2 */
6595 for (i = 0; i < lasti + 1; i++) {
6596 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6597 continue;
6598
6599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6600 alu.op = ALU_OP2_MUL;
6601 alu.src[0].sel = ctx->temp_reg;
6602 alu.src[0].chan = i;
6603 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6604 alu.dst.sel = ctx->temp_reg;
6605 alu.dst.chan = i;
6606 if (i == lasti) {
6607 alu.last = 1;
6608 }
6609 alu.dst.write = 1;
6610 r = r600_bytecode_add_alu(ctx->bc, &alu);
6611 if (r)
6612 return r;
6613 }
6614
6615 /* src0 * src1 + (1 - src0) * src2 */
6616 if (ctx->src[0].abs)
6617 temp_regs[0] = r600_get_temp(ctx);
6618 else
6619 temp_regs[0] = 0;
6620 if (ctx->src[1].abs)
6621 temp_regs[1] = r600_get_temp(ctx);
6622 else
6623 temp_regs[1] = 0;
6624
6625 for (i = 0; i < lasti + 1; i++) {
6626 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6627 continue;
6628
6629 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6630 alu.op = ALU_OP3_MULADD;
6631 alu.is_op3 = 1;
6632 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6633 if (r)
6634 return r;
6635 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
6636 if (r)
6637 return r;
6638 alu.src[2].sel = ctx->temp_reg;
6639 alu.src[2].chan = i;
6640
6641 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6642 alu.dst.chan = i;
6643 if (i == lasti) {
6644 alu.last = 1;
6645 }
6646 r = r600_bytecode_add_alu(ctx->bc, &alu);
6647 if (r)
6648 return r;
6649 }
6650 return 0;
6651 }
6652
6653 static int tgsi_cmp(struct r600_shader_ctx *ctx)
6654 {
6655 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6656 struct r600_bytecode_alu alu;
6657 int i, r, j;
6658 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6659 int temp_regs[3];
6660
6661 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6662 temp_regs[j] = 0;
6663 if (ctx->src[j].abs)
6664 temp_regs[j] = r600_get_temp(ctx);
6665 }
6666
6667 for (i = 0; i < lasti + 1; i++) {
6668 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6669 continue;
6670
6671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6672 alu.op = ALU_OP3_CNDGE;
6673 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6674 if (r)
6675 return r;
6676 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
6677 if (r)
6678 return r;
6679 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
6680 if (r)
6681 return r;
6682 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6683 alu.dst.chan = i;
6684 alu.dst.write = 1;
6685 alu.is_op3 = 1;
6686 if (i == lasti)
6687 alu.last = 1;
6688 r = r600_bytecode_add_alu(ctx->bc, &alu);
6689 if (r)
6690 return r;
6691 }
6692 return 0;
6693 }
6694
6695 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
6696 {
6697 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6698 struct r600_bytecode_alu alu;
6699 int i, r;
6700 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6701
6702 for (i = 0; i < lasti + 1; i++) {
6703 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6704 continue;
6705
6706 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6707 alu.op = ALU_OP3_CNDE_INT;
6708 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6709 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6710 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6711 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6712 alu.dst.chan = i;
6713 alu.dst.write = 1;
6714 alu.is_op3 = 1;
6715 if (i == lasti)
6716 alu.last = 1;
6717 r = r600_bytecode_add_alu(ctx->bc, &alu);
6718 if (r)
6719 return r;
6720 }
6721 return 0;
6722 }
6723
6724 static int tgsi_xpd(struct r600_shader_ctx *ctx)
6725 {
6726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6727 static const unsigned int src0_swizzle[] = {2, 0, 1};
6728 static const unsigned int src1_swizzle[] = {1, 2, 0};
6729 struct r600_bytecode_alu alu;
6730 uint32_t use_temp = 0;
6731 int i, r;
6732
6733 if (inst->Dst[0].Register.WriteMask != 0xf)
6734 use_temp = 1;
6735
6736 for (i = 0; i < 4; i++) {
6737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6738 alu.op = ALU_OP2_MUL;
6739 if (i < 3) {
6740 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6741 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
6742 } else {
6743 alu.src[0].sel = V_SQ_ALU_SRC_0;
6744 alu.src[0].chan = i;
6745 alu.src[1].sel = V_SQ_ALU_SRC_0;
6746 alu.src[1].chan = i;
6747 }
6748
6749 alu.dst.sel = ctx->temp_reg;
6750 alu.dst.chan = i;
6751 alu.dst.write = 1;
6752
6753 if (i == 3)
6754 alu.last = 1;
6755 r = r600_bytecode_add_alu(ctx->bc, &alu);
6756 if (r)
6757 return r;
6758 }
6759
6760 for (i = 0; i < 4; i++) {
6761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6762 alu.op = ALU_OP3_MULADD;
6763
6764 if (i < 3) {
6765 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
6766 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
6767 } else {
6768 alu.src[0].sel = V_SQ_ALU_SRC_0;
6769 alu.src[0].chan = i;
6770 alu.src[1].sel = V_SQ_ALU_SRC_0;
6771 alu.src[1].chan = i;
6772 }
6773
6774 alu.src[2].sel = ctx->temp_reg;
6775 alu.src[2].neg = 1;
6776 alu.src[2].chan = i;
6777
6778 if (use_temp)
6779 alu.dst.sel = ctx->temp_reg;
6780 else
6781 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6782 alu.dst.chan = i;
6783 alu.dst.write = 1;
6784 alu.is_op3 = 1;
6785 if (i == 3)
6786 alu.last = 1;
6787 r = r600_bytecode_add_alu(ctx->bc, &alu);
6788 if (r)
6789 return r;
6790 }
6791 if (use_temp)
6792 return tgsi_helper_copy(ctx, inst);
6793 return 0;
6794 }
6795
6796 static int tgsi_exp(struct r600_shader_ctx *ctx)
6797 {
6798 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6799 struct r600_bytecode_alu alu;
6800 int r;
6801 int i;
6802
6803 /* result.x = 2^floor(src); */
6804 if (inst->Dst[0].Register.WriteMask & 1) {
6805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6806
6807 alu.op = ALU_OP1_FLOOR;
6808 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6809
6810 alu.dst.sel = ctx->temp_reg;
6811 alu.dst.chan = 0;
6812 alu.dst.write = 1;
6813 alu.last = 1;
6814 r = r600_bytecode_add_alu(ctx->bc, &alu);
6815 if (r)
6816 return r;
6817
6818 if (ctx->bc->chip_class == CAYMAN) {
6819 for (i = 0; i < 3; i++) {
6820 alu.op = ALU_OP1_EXP_IEEE;
6821 alu.src[0].sel = ctx->temp_reg;
6822 alu.src[0].chan = 0;
6823
6824 alu.dst.sel = ctx->temp_reg;
6825 alu.dst.chan = i;
6826 alu.dst.write = i == 0;
6827 alu.last = i == 2;
6828 r = r600_bytecode_add_alu(ctx->bc, &alu);
6829 if (r)
6830 return r;
6831 }
6832 } else {
6833 alu.op = ALU_OP1_EXP_IEEE;
6834 alu.src[0].sel = ctx->temp_reg;
6835 alu.src[0].chan = 0;
6836
6837 alu.dst.sel = ctx->temp_reg;
6838 alu.dst.chan = 0;
6839 alu.dst.write = 1;
6840 alu.last = 1;
6841 r = r600_bytecode_add_alu(ctx->bc, &alu);
6842 if (r)
6843 return r;
6844 }
6845 }
6846
6847 /* result.y = tmp - floor(tmp); */
6848 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
6849 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6850
6851 alu.op = ALU_OP1_FRACT;
6852 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6853
6854 alu.dst.sel = ctx->temp_reg;
6855 #if 0
6856 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6857 if (r)
6858 return r;
6859 #endif
6860 alu.dst.write = 1;
6861 alu.dst.chan = 1;
6862
6863 alu.last = 1;
6864
6865 r = r600_bytecode_add_alu(ctx->bc, &alu);
6866 if (r)
6867 return r;
6868 }
6869
6870 /* result.z = RoughApprox2ToX(tmp);*/
6871 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
6872 if (ctx->bc->chip_class == CAYMAN) {
6873 for (i = 0; i < 3; i++) {
6874 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6875 alu.op = ALU_OP1_EXP_IEEE;
6876 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6877
6878 alu.dst.sel = ctx->temp_reg;
6879 alu.dst.chan = i;
6880 if (i == 2) {
6881 alu.dst.write = 1;
6882 alu.last = 1;
6883 }
6884
6885 r = r600_bytecode_add_alu(ctx->bc, &alu);
6886 if (r)
6887 return r;
6888 }
6889 } else {
6890 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6891 alu.op = ALU_OP1_EXP_IEEE;
6892 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6893
6894 alu.dst.sel = ctx->temp_reg;
6895 alu.dst.write = 1;
6896 alu.dst.chan = 2;
6897
6898 alu.last = 1;
6899
6900 r = r600_bytecode_add_alu(ctx->bc, &alu);
6901 if (r)
6902 return r;
6903 }
6904 }
6905
6906 /* result.w = 1.0;*/
6907 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
6908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6909
6910 alu.op = ALU_OP1_MOV;
6911 alu.src[0].sel = V_SQ_ALU_SRC_1;
6912 alu.src[0].chan = 0;
6913
6914 alu.dst.sel = ctx->temp_reg;
6915 alu.dst.chan = 3;
6916 alu.dst.write = 1;
6917 alu.last = 1;
6918 r = r600_bytecode_add_alu(ctx->bc, &alu);
6919 if (r)
6920 return r;
6921 }
6922 return tgsi_helper_copy(ctx, inst);
6923 }
6924
6925 static int tgsi_log(struct r600_shader_ctx *ctx)
6926 {
6927 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6928 struct r600_bytecode_alu alu;
6929 int r;
6930 int i;
6931
6932 /* result.x = floor(log2(|src|)); */
6933 if (inst->Dst[0].Register.WriteMask & 1) {
6934 if (ctx->bc->chip_class == CAYMAN) {
6935 for (i = 0; i < 3; i++) {
6936 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6937
6938 alu.op = ALU_OP1_LOG_IEEE;
6939 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6940 r600_bytecode_src_set_abs(&alu.src[0]);
6941
6942 alu.dst.sel = ctx->temp_reg;
6943 alu.dst.chan = i;
6944 if (i == 0)
6945 alu.dst.write = 1;
6946 if (i == 2)
6947 alu.last = 1;
6948 r = r600_bytecode_add_alu(ctx->bc, &alu);
6949 if (r)
6950 return r;
6951 }
6952
6953 } else {
6954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6955
6956 alu.op = ALU_OP1_LOG_IEEE;
6957 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6958 r600_bytecode_src_set_abs(&alu.src[0]);
6959
6960 alu.dst.sel = ctx->temp_reg;
6961 alu.dst.chan = 0;
6962 alu.dst.write = 1;
6963 alu.last = 1;
6964 r = r600_bytecode_add_alu(ctx->bc, &alu);
6965 if (r)
6966 return r;
6967 }
6968
6969 alu.op = ALU_OP1_FLOOR;
6970 alu.src[0].sel = ctx->temp_reg;
6971 alu.src[0].chan = 0;
6972
6973 alu.dst.sel = ctx->temp_reg;
6974 alu.dst.chan = 0;
6975 alu.dst.write = 1;
6976 alu.last = 1;
6977
6978 r = r600_bytecode_add_alu(ctx->bc, &alu);
6979 if (r)
6980 return r;
6981 }
6982
6983 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
6984 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
6985
6986 if (ctx->bc->chip_class == CAYMAN) {
6987 for (i = 0; i < 3; i++) {
6988 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6989
6990 alu.op = ALU_OP1_LOG_IEEE;
6991 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6992 r600_bytecode_src_set_abs(&alu.src[0]);
6993
6994 alu.dst.sel = ctx->temp_reg;
6995 alu.dst.chan = i;
6996 if (i == 1)
6997 alu.dst.write = 1;
6998 if (i == 2)
6999 alu.last = 1;
7000
7001 r = r600_bytecode_add_alu(ctx->bc, &alu);
7002 if (r)
7003 return r;
7004 }
7005 } else {
7006 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7007
7008 alu.op = ALU_OP1_LOG_IEEE;
7009 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7010 r600_bytecode_src_set_abs(&alu.src[0]);
7011
7012 alu.dst.sel = ctx->temp_reg;
7013 alu.dst.chan = 1;
7014 alu.dst.write = 1;
7015 alu.last = 1;
7016
7017 r = r600_bytecode_add_alu(ctx->bc, &alu);
7018 if (r)
7019 return r;
7020 }
7021
7022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7023
7024 alu.op = ALU_OP1_FLOOR;
7025 alu.src[0].sel = ctx->temp_reg;
7026 alu.src[0].chan = 1;
7027
7028 alu.dst.sel = ctx->temp_reg;
7029 alu.dst.chan = 1;
7030 alu.dst.write = 1;
7031 alu.last = 1;
7032
7033 r = r600_bytecode_add_alu(ctx->bc, &alu);
7034 if (r)
7035 return r;
7036
7037 if (ctx->bc->chip_class == CAYMAN) {
7038 for (i = 0; i < 3; i++) {
7039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7040 alu.op = ALU_OP1_EXP_IEEE;
7041 alu.src[0].sel = ctx->temp_reg;
7042 alu.src[0].chan = 1;
7043
7044 alu.dst.sel = ctx->temp_reg;
7045 alu.dst.chan = i;
7046 if (i == 1)
7047 alu.dst.write = 1;
7048 if (i == 2)
7049 alu.last = 1;
7050
7051 r = r600_bytecode_add_alu(ctx->bc, &alu);
7052 if (r)
7053 return r;
7054 }
7055 } else {
7056 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7057 alu.op = ALU_OP1_EXP_IEEE;
7058 alu.src[0].sel = ctx->temp_reg;
7059 alu.src[0].chan = 1;
7060
7061 alu.dst.sel = ctx->temp_reg;
7062 alu.dst.chan = 1;
7063 alu.dst.write = 1;
7064 alu.last = 1;
7065
7066 r = r600_bytecode_add_alu(ctx->bc, &alu);
7067 if (r)
7068 return r;
7069 }
7070
7071 if (ctx->bc->chip_class == CAYMAN) {
7072 for (i = 0; i < 3; i++) {
7073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7074 alu.op = ALU_OP1_RECIP_IEEE;
7075 alu.src[0].sel = ctx->temp_reg;
7076 alu.src[0].chan = 1;
7077
7078 alu.dst.sel = ctx->temp_reg;
7079 alu.dst.chan = i;
7080 if (i == 1)
7081 alu.dst.write = 1;
7082 if (i == 2)
7083 alu.last = 1;
7084
7085 r = r600_bytecode_add_alu(ctx->bc, &alu);
7086 if (r)
7087 return r;
7088 }
7089 } else {
7090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7091 alu.op = ALU_OP1_RECIP_IEEE;
7092 alu.src[0].sel = ctx->temp_reg;
7093 alu.src[0].chan = 1;
7094
7095 alu.dst.sel = ctx->temp_reg;
7096 alu.dst.chan = 1;
7097 alu.dst.write = 1;
7098 alu.last = 1;
7099
7100 r = r600_bytecode_add_alu(ctx->bc, &alu);
7101 if (r)
7102 return r;
7103 }
7104
7105 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7106
7107 alu.op = ALU_OP2_MUL;
7108
7109 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7110 r600_bytecode_src_set_abs(&alu.src[0]);
7111
7112 alu.src[1].sel = ctx->temp_reg;
7113 alu.src[1].chan = 1;
7114
7115 alu.dst.sel = ctx->temp_reg;
7116 alu.dst.chan = 1;
7117 alu.dst.write = 1;
7118 alu.last = 1;
7119
7120 r = r600_bytecode_add_alu(ctx->bc, &alu);
7121 if (r)
7122 return r;
7123 }
7124
7125 /* result.z = log2(|src|);*/
7126 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
7127 if (ctx->bc->chip_class == CAYMAN) {
7128 for (i = 0; i < 3; i++) {
7129 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7130
7131 alu.op = ALU_OP1_LOG_IEEE;
7132 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7133 r600_bytecode_src_set_abs(&alu.src[0]);
7134
7135 alu.dst.sel = ctx->temp_reg;
7136 if (i == 2)
7137 alu.dst.write = 1;
7138 alu.dst.chan = i;
7139 if (i == 2)
7140 alu.last = 1;
7141
7142 r = r600_bytecode_add_alu(ctx->bc, &alu);
7143 if (r)
7144 return r;
7145 }
7146 } else {
7147 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7148
7149 alu.op = ALU_OP1_LOG_IEEE;
7150 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7151 r600_bytecode_src_set_abs(&alu.src[0]);
7152
7153 alu.dst.sel = ctx->temp_reg;
7154 alu.dst.write = 1;
7155 alu.dst.chan = 2;
7156 alu.last = 1;
7157
7158 r = r600_bytecode_add_alu(ctx->bc, &alu);
7159 if (r)
7160 return r;
7161 }
7162 }
7163
7164 /* result.w = 1.0; */
7165 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
7166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7167
7168 alu.op = ALU_OP1_MOV;
7169 alu.src[0].sel = V_SQ_ALU_SRC_1;
7170 alu.src[0].chan = 0;
7171
7172 alu.dst.sel = ctx->temp_reg;
7173 alu.dst.chan = 3;
7174 alu.dst.write = 1;
7175 alu.last = 1;
7176
7177 r = r600_bytecode_add_alu(ctx->bc, &alu);
7178 if (r)
7179 return r;
7180 }
7181
7182 return tgsi_helper_copy(ctx, inst);
7183 }
7184
7185 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
7186 {
7187 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7188 struct r600_bytecode_alu alu;
7189 int r;
7190 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7191 unsigned reg = inst->Dst[0].Register.Index > 0 ? ctx->bc->index_reg[inst->Dst[0].Register.Index - 1] : ctx->bc->ar_reg;
7192
7193 assert(inst->Dst[0].Register.Index < 3);
7194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7195
7196 switch (inst->Instruction.Opcode) {
7197 case TGSI_OPCODE_ARL:
7198 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
7199 break;
7200 case TGSI_OPCODE_ARR:
7201 alu.op = ALU_OP1_FLT_TO_INT;
7202 break;
7203 case TGSI_OPCODE_UARL:
7204 alu.op = ALU_OP1_MOV;
7205 break;
7206 default:
7207 assert(0);
7208 return -1;
7209 }
7210
7211 for (i = 0; i <= lasti; ++i) {
7212 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7213 continue;
7214 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7215 alu.last = i == lasti;
7216 alu.dst.sel = reg;
7217 alu.dst.chan = i;
7218 alu.dst.write = 1;
7219 r = r600_bytecode_add_alu(ctx->bc, &alu);
7220 if (r)
7221 return r;
7222 }
7223
7224 if (inst->Dst[0].Register.Index > 0)
7225 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
7226 else
7227 ctx->bc->ar_loaded = 0;
7228
7229 return 0;
7230 }
7231 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
7232 {
7233 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7234 struct r600_bytecode_alu alu;
7235 int r;
7236 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7237
7238 switch (inst->Instruction.Opcode) {
7239 case TGSI_OPCODE_ARL:
7240 memset(&alu, 0, sizeof(alu));
7241 alu.op = ALU_OP1_FLOOR;
7242 alu.dst.sel = ctx->bc->ar_reg;
7243 alu.dst.write = 1;
7244 for (i = 0; i <= lasti; ++i) {
7245 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7246 alu.dst.chan = i;
7247 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7248 alu.last = i == lasti;
7249 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7250 return r;
7251 }
7252 }
7253
7254 memset(&alu, 0, sizeof(alu));
7255 alu.op = ALU_OP1_FLT_TO_INT;
7256 alu.src[0].sel = ctx->bc->ar_reg;
7257 alu.dst.sel = ctx->bc->ar_reg;
7258 alu.dst.write = 1;
7259 /* FLT_TO_INT is trans-only on r600/r700 */
7260 alu.last = TRUE;
7261 for (i = 0; i <= lasti; ++i) {
7262 alu.dst.chan = i;
7263 alu.src[0].chan = i;
7264 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7265 return r;
7266 }
7267 break;
7268 case TGSI_OPCODE_ARR:
7269 memset(&alu, 0, sizeof(alu));
7270 alu.op = ALU_OP1_FLT_TO_INT;
7271 alu.dst.sel = ctx->bc->ar_reg;
7272 alu.dst.write = 1;
7273 /* FLT_TO_INT is trans-only on r600/r700 */
7274 alu.last = TRUE;
7275 for (i = 0; i <= lasti; ++i) {
7276 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7277 alu.dst.chan = i;
7278 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7279 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7280 return r;
7281 }
7282 }
7283 break;
7284 case TGSI_OPCODE_UARL:
7285 memset(&alu, 0, sizeof(alu));
7286 alu.op = ALU_OP1_MOV;
7287 alu.dst.sel = ctx->bc->ar_reg;
7288 alu.dst.write = 1;
7289 for (i = 0; i <= lasti; ++i) {
7290 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7291 alu.dst.chan = i;
7292 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7293 alu.last = i == lasti;
7294 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7295 return r;
7296 }
7297 }
7298 break;
7299 default:
7300 assert(0);
7301 return -1;
7302 }
7303
7304 ctx->bc->ar_loaded = 0;
7305 return 0;
7306 }
7307
7308 static int tgsi_opdst(struct r600_shader_ctx *ctx)
7309 {
7310 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7311 struct r600_bytecode_alu alu;
7312 int i, r = 0;
7313
7314 for (i = 0; i < 4; i++) {
7315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7316
7317 alu.op = ALU_OP2_MUL;
7318 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7319
7320 if (i == 0 || i == 3) {
7321 alu.src[0].sel = V_SQ_ALU_SRC_1;
7322 } else {
7323 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7324 }
7325
7326 if (i == 0 || i == 2) {
7327 alu.src[1].sel = V_SQ_ALU_SRC_1;
7328 } else {
7329 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
7330 }
7331 if (i == 3)
7332 alu.last = 1;
7333 r = r600_bytecode_add_alu(ctx->bc, &alu);
7334 if (r)
7335 return r;
7336 }
7337 return 0;
7338 }
7339
7340 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
7341 {
7342 struct r600_bytecode_alu alu;
7343 int r;
7344
7345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7346 alu.op = opcode;
7347 alu.execute_mask = 1;
7348 alu.update_pred = 1;
7349
7350 alu.dst.sel = ctx->temp_reg;
7351 alu.dst.write = 1;
7352 alu.dst.chan = 0;
7353
7354 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7355 alu.src[1].sel = V_SQ_ALU_SRC_0;
7356 alu.src[1].chan = 0;
7357
7358 alu.last = 1;
7359
7360 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
7361 if (r)
7362 return r;
7363 return 0;
7364 }
7365
7366 static int pops(struct r600_shader_ctx *ctx, int pops)
7367 {
7368 unsigned force_pop = ctx->bc->force_add_cf;
7369
7370 if (!force_pop) {
7371 int alu_pop = 3;
7372 if (ctx->bc->cf_last) {
7373 if (ctx->bc->cf_last->op == CF_OP_ALU)
7374 alu_pop = 0;
7375 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
7376 alu_pop = 1;
7377 }
7378 alu_pop += pops;
7379 if (alu_pop == 1) {
7380 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
7381 ctx->bc->force_add_cf = 1;
7382 } else if (alu_pop == 2) {
7383 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
7384 ctx->bc->force_add_cf = 1;
7385 } else {
7386 force_pop = 1;
7387 }
7388 }
7389
7390 if (force_pop) {
7391 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
7392 ctx->bc->cf_last->pop_count = pops;
7393 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7394 }
7395
7396 return 0;
7397 }
7398
7399 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
7400 unsigned reason)
7401 {
7402 struct r600_stack_info *stack = &ctx->bc->stack;
7403 unsigned elements, entries;
7404
7405 unsigned entry_size = stack->entry_size;
7406
7407 elements = (stack->loop + stack->push_wqm ) * entry_size;
7408 elements += stack->push;
7409
7410 switch (ctx->bc->chip_class) {
7411 case R600:
7412 case R700:
7413 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
7414 * the stack must be reserved to hold the current active/continue
7415 * masks */
7416 if (reason == FC_PUSH_VPM) {
7417 elements += 2;
7418 }
7419 break;
7420
7421 case CAYMAN:
7422 /* r9xx: any stack operation on empty stack consumes 2 additional
7423 * elements */
7424 elements += 2;
7425
7426 /* fallthrough */
7427 /* FIXME: do the two elements added above cover the cases for the
7428 * r8xx+ below? */
7429
7430 case EVERGREEN:
7431 /* r8xx+: 2 extra elements are not always required, but one extra
7432 * element must be added for each of the following cases:
7433 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
7434 * stack usage.
7435 * (Currently we don't use ALU_ELSE_AFTER.)
7436 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
7437 * PUSH instruction executed.
7438 *
7439 * NOTE: it seems we also need to reserve additional element in some
7440 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
7441 * then STACK_SIZE should be 2 instead of 1 */
7442 if (reason == FC_PUSH_VPM) {
7443 elements += 1;
7444 }
7445 break;
7446
7447 default:
7448 assert(0);
7449 break;
7450 }
7451
7452 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
7453 * for all chips, so we use 4 in the final formula, not the real entry_size
7454 * for the chip */
7455 entry_size = 4;
7456
7457 entries = (elements + (entry_size - 1)) / entry_size;
7458
7459 if (entries > stack->max_entries)
7460 stack->max_entries = entries;
7461 }
7462
7463 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
7464 {
7465 switch(reason) {
7466 case FC_PUSH_VPM:
7467 --ctx->bc->stack.push;
7468 assert(ctx->bc->stack.push >= 0);
7469 break;
7470 case FC_PUSH_WQM:
7471 --ctx->bc->stack.push_wqm;
7472 assert(ctx->bc->stack.push_wqm >= 0);
7473 break;
7474 case FC_LOOP:
7475 --ctx->bc->stack.loop;
7476 assert(ctx->bc->stack.loop >= 0);
7477 break;
7478 default:
7479 assert(0);
7480 break;
7481 }
7482 }
7483
7484 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
7485 {
7486 switch (reason) {
7487 case FC_PUSH_VPM:
7488 ++ctx->bc->stack.push;
7489 break;
7490 case FC_PUSH_WQM:
7491 ++ctx->bc->stack.push_wqm;
7492 case FC_LOOP:
7493 ++ctx->bc->stack.loop;
7494 break;
7495 default:
7496 assert(0);
7497 }
7498
7499 callstack_update_max_depth(ctx, reason);
7500 }
7501
7502 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
7503 {
7504 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
7505
7506 sp->mid = realloc((void *)sp->mid,
7507 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
7508 sp->mid[sp->num_mid] = ctx->bc->cf_last;
7509 sp->num_mid++;
7510 }
7511
7512 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
7513 {
7514 ctx->bc->fc_sp++;
7515 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
7516 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
7517 }
7518
7519 static void fc_poplevel(struct r600_shader_ctx *ctx)
7520 {
7521 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
7522 free(sp->mid);
7523 sp->mid = NULL;
7524 sp->num_mid = 0;
7525 sp->start = NULL;
7526 sp->type = 0;
7527 ctx->bc->fc_sp--;
7528 }
7529
7530 #if 0
7531 static int emit_return(struct r600_shader_ctx *ctx)
7532 {
7533 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
7534 return 0;
7535 }
7536
7537 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
7538 {
7539
7540 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
7541 ctx->bc->cf_last->pop_count = pops;
7542 /* XXX work out offset */
7543 return 0;
7544 }
7545
7546 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
7547 {
7548 return 0;
7549 }
7550
7551 static void emit_testflag(struct r600_shader_ctx *ctx)
7552 {
7553
7554 }
7555
7556 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
7557 {
7558 emit_testflag(ctx);
7559 emit_jump_to_offset(ctx, 1, 4);
7560 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
7561 pops(ctx, ifidx + 1);
7562 emit_return(ctx);
7563 }
7564
7565 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
7566 {
7567 emit_testflag(ctx);
7568
7569 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7570 ctx->bc->cf_last->pop_count = 1;
7571
7572 fc_set_mid(ctx, fc_sp);
7573
7574 pops(ctx, 1);
7575 }
7576 #endif
7577
7578 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
7579 {
7580 int alu_type = CF_OP_ALU_PUSH_BEFORE;
7581
7582 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
7583 * LOOP_STARTxxx for nested loops may put the branch stack into a state
7584 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
7585 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
7586 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
7587 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
7588 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7589 alu_type = CF_OP_ALU;
7590 }
7591
7592 emit_logic_pred(ctx, opcode, alu_type);
7593
7594 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
7595
7596 fc_pushlevel(ctx, FC_IF);
7597
7598 callstack_push(ctx, FC_PUSH_VPM);
7599 return 0;
7600 }
7601
7602 static int tgsi_if(struct r600_shader_ctx *ctx)
7603 {
7604 return emit_if(ctx, ALU_OP2_PRED_SETNE);
7605 }
7606
7607 static int tgsi_uif(struct r600_shader_ctx *ctx)
7608 {
7609 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
7610 }
7611
7612 static int tgsi_else(struct r600_shader_ctx *ctx)
7613 {
7614 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
7615 ctx->bc->cf_last->pop_count = 1;
7616
7617 fc_set_mid(ctx, ctx->bc->fc_sp);
7618 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
7619 return 0;
7620 }
7621
7622 static int tgsi_endif(struct r600_shader_ctx *ctx)
7623 {
7624 pops(ctx, 1);
7625 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
7626 R600_ERR("if/endif unbalanced in shader\n");
7627 return -1;
7628 }
7629
7630 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
7631 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7632 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
7633 } else {
7634 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
7635 }
7636 fc_poplevel(ctx);
7637
7638 callstack_pop(ctx, FC_PUSH_VPM);
7639 return 0;
7640 }
7641
7642 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
7643 {
7644 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
7645 * limited to 4096 iterations, like the other LOOP_* instructions. */
7646 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
7647
7648 fc_pushlevel(ctx, FC_LOOP);
7649
7650 /* check stack depth */
7651 callstack_push(ctx, FC_LOOP);
7652 return 0;
7653 }
7654
7655 static int tgsi_endloop(struct r600_shader_ctx *ctx)
7656 {
7657 int i;
7658
7659 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
7660
7661 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
7662 R600_ERR("loop/endloop in shader code are not paired.\n");
7663 return -EINVAL;
7664 }
7665
7666 /* fixup loop pointers - from r600isa
7667 LOOP END points to CF after LOOP START,
7668 LOOP START point to CF after LOOP END
7669 BRK/CONT point to LOOP END CF
7670 */
7671 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
7672
7673 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7674
7675 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
7676 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
7677 }
7678 /* XXX add LOOPRET support */
7679 fc_poplevel(ctx);
7680 callstack_pop(ctx, FC_LOOP);
7681 return 0;
7682 }
7683
7684 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
7685 {
7686 int r;
7687 unsigned int fscp;
7688
7689 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7690 {
7691 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7692 break;
7693 }
7694 if (fscp == 0) {
7695 R600_ERR("BREAKC not inside loop/endloop pair\n");
7696 return -EINVAL;
7697 }
7698
7699 if (ctx->bc->chip_class == EVERGREEN &&
7700 ctx->bc->family != CHIP_CYPRESS &&
7701 ctx->bc->family != CHIP_JUNIPER) {
7702 /* HW bug: ALU_BREAK does not save the active mask correctly */
7703 r = tgsi_uif(ctx);
7704 if (r)
7705 return r;
7706
7707 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
7708 if (r)
7709 return r;
7710 fc_set_mid(ctx, fscp);
7711
7712 return tgsi_endif(ctx);
7713 } else {
7714 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
7715 if (r)
7716 return r;
7717 fc_set_mid(ctx, fscp);
7718 }
7719
7720 return 0;
7721 }
7722
7723 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
7724 {
7725 unsigned int fscp;
7726
7727 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7728 {
7729 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7730 break;
7731 }
7732
7733 if (fscp == 0) {
7734 R600_ERR("Break not inside loop/endloop pair\n");
7735 return -EINVAL;
7736 }
7737
7738 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7739
7740 fc_set_mid(ctx, fscp);
7741
7742 return 0;
7743 }
7744
7745 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
7746 {
7747 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7748 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
7749 int r;
7750
7751 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
7752 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
7753
7754 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7755 if (!r)
7756 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
7757 return r;
7758 }
7759
7760 static int tgsi_umad(struct r600_shader_ctx *ctx)
7761 {
7762 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7763 struct r600_bytecode_alu alu;
7764 int i, j, k, r;
7765 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7766
7767 /* src0 * src1 */
7768 for (i = 0; i < lasti + 1; i++) {
7769 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7770 continue;
7771
7772 if (ctx->bc->chip_class == CAYMAN) {
7773 for (j = 0 ; j < 4; j++) {
7774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7775
7776 alu.op = ALU_OP2_MULLO_UINT;
7777 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
7778 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
7779 }
7780 alu.dst.chan = j;
7781 alu.dst.sel = ctx->temp_reg;
7782 alu.dst.write = (j == i);
7783 if (j == 3)
7784 alu.last = 1;
7785 r = r600_bytecode_add_alu(ctx->bc, &alu);
7786 if (r)
7787 return r;
7788 }
7789 } else {
7790 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7791
7792 alu.dst.chan = i;
7793 alu.dst.sel = ctx->temp_reg;
7794 alu.dst.write = 1;
7795
7796 alu.op = ALU_OP2_MULLO_UINT;
7797 for (j = 0; j < 2; j++) {
7798 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
7799 }
7800
7801 alu.last = 1;
7802 r = r600_bytecode_add_alu(ctx->bc, &alu);
7803 if (r)
7804 return r;
7805 }
7806 }
7807
7808
7809 for (i = 0; i < lasti + 1; i++) {
7810 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7811 continue;
7812
7813 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7814 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7815
7816 alu.op = ALU_OP2_ADD_INT;
7817
7818 alu.src[0].sel = ctx->temp_reg;
7819 alu.src[0].chan = i;
7820
7821 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7822 if (i == lasti) {
7823 alu.last = 1;
7824 }
7825 r = r600_bytecode_add_alu(ctx->bc, &alu);
7826 if (r)
7827 return r;
7828 }
7829 return 0;
7830 }
7831
7832 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
7833 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
7834 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
7835 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
7836
7837 /* XXX:
7838 * For state trackers other than OpenGL, we'll want to use
7839 * _RECIP_IEEE instead.
7840 */
7841 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
7842
7843 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
7844 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
7845 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
7846 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
7847 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
7848 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
7849 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
7850 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
7851 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
7852 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
7853 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
7854 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
7855 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
7856 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
7857 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
7858 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
7859 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
7860 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
7861 [22] = { ALU_OP0_NOP, tgsi_unsupported},
7862 [23] = { ALU_OP0_NOP, tgsi_unsupported},
7863 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
7864 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
7865 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
7866 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
7867 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
7868 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
7869 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
7870 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
7871 [32] = { ALU_OP0_NOP, tgsi_unsupported},
7872 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
7873 [34] = { ALU_OP0_NOP, tgsi_unsupported},
7874 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
7875 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
7876 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7877 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7878 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
7879 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
7880 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
7881 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
7882 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7883 [44] = { ALU_OP0_NOP, tgsi_unsupported},
7884 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
7885 [46] = { ALU_OP0_NOP, tgsi_unsupported},
7886 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
7887 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
7888 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
7889 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
7890 [51] = { ALU_OP0_NOP, tgsi_unsupported},
7891 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
7892 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
7893 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
7894 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
7895 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
7896 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
7897 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7898 [59] = { ALU_OP0_NOP, tgsi_unsupported},
7899 [60] = { ALU_OP0_NOP, tgsi_unsupported},
7900 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
7901 [62] = { ALU_OP0_NOP, tgsi_unsupported},
7902 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
7903 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
7904 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
7905 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
7906 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
7907 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7908 [69] = { ALU_OP0_NOP, tgsi_unsupported},
7909 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
7910 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
7911 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7912 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
7913 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
7914 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
7915 [76] = { ALU_OP0_NOP, tgsi_unsupported},
7916 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
7917 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
7918 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
7919 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
7920 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
7921 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
7922 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
7923 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
7924 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
7925 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
7926 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
7927 [88] = { ALU_OP0_NOP, tgsi_unsupported},
7928 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
7929 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
7930 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
7931 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
7932 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
7933 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
7934 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7935 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
7936 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
7937 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
7938 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
7939 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7940 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
7941 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7942 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7943 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
7944 [105] = { ALU_OP0_NOP, tgsi_unsupported},
7945 [106] = { ALU_OP0_NOP, tgsi_unsupported},
7946 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
7947 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
7948 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
7949 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
7950 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
7951 [112] = { ALU_OP0_NOP, tgsi_unsupported},
7952 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
7953 [114] = { ALU_OP0_NOP, tgsi_unsupported},
7954 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
7955 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
7956 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
7957 [118] = { ALU_OP0_NOP, tgsi_unsupported},
7958 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
7959 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
7960 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
7961 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
7962 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
7963 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
7964 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
7965 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
7966 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
7967 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
7968 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
7969 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
7970 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
7971 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
7972 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
7973 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
7974 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
7975 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
7976 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
7977 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
7978 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
7979 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
7980 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7981 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
7982 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
7983 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7984 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
7985 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
7986 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
7987 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
7988 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
7989 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
7990 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
7991 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
7992 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
7993 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
7994 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
7995 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
7996 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
7997 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
7998 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
7999 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8000 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8001 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8002 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8003 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8004 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8005 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8006 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8007 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8008 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8009 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8010 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8011 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8012 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8013 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8014 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8015 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8016 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8017 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8018 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8019 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
8020 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
8021 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
8022 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
8023 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
8024 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
8025 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
8026 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
8027 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
8028 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
8029 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
8030 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
8031 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
8032 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
8033 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
8034 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8035 };
8036
8037 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
8038 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
8039 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8040 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8041 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
8042 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
8043 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8044 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8045 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8046 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8047 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8048 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8049 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8050 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8051 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8052 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8053 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8054 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8055 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8056 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8057 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8058 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
8059 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8060 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8061 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8062 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8063 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8064 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8065 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8066 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
8067 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
8068 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
8069 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8070 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8071 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8072 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8073 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8074 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
8075 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8076 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8077 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8078 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8079 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8080 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8081 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8082 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8083 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8084 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8085 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8086 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
8087 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8088 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8089 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8090 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8091 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8092 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8093 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8094 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8095 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8096 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8097 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8098 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8099 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
8100 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8101 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8102 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8103 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8104 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8105 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8106 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8107 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8108 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8109 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8110 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8111 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8112 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8113 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8114 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8115 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8116 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8117 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8118 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8119 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8120 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8121 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8122 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
8123 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8124 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8125 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8126 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8127 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8128 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8129 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8130 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8131 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8132 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8133 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8134 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8135 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8136 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8137 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8138 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8139 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8140 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8141 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8142 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8143 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8144 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8145 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8146 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8147 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8148 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8149 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8150 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8151 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8152 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8153 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8154 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8155 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8156 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8157 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
8158 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8159 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8160 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8161 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8162 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8163 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8164 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8165 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
8166 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
8167 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8168 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8169 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8170 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8171 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8172 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8173 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
8174 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8175 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8176 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8177 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8178 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8179 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8180 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8181 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8182 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8183 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8184 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8185 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8186 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8187 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8188 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8189 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8190 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8191 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8192 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8193 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8194 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8195 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8196 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8197 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8198 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8199 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8200 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8201 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8202 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8203 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8204 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8205 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8206 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8207 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8208 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8209 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8210 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8211 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8212 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8213 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8214 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8215 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8216 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8217 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8218 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
8219 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
8220 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8221 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8222 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8223 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8224 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8225 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8226 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8227 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8228 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8229 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8230 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8231 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8232 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8233 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8234 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8235 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8236 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8237 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8238 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8239 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8240 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8241 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8242 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8243 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8244 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8245 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8246 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8247 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8248 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8249 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8250 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8251 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
8252 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
8253 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
8254 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
8255 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8256 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8257 };
8258
8259 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
8260 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
8261 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8262 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8263 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
8264 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
8265 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8266 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8267 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8268 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8269 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8270 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8271 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8272 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8273 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8274 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8275 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8276 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8277 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8278 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8279 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8280 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
8281 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8282 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8283 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8284 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8285 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8286 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8287 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8288 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
8289 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
8290 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
8291 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8292 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8293 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8294 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8295 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8296 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
8297 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8298 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8299 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8300 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8301 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8302 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8303 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8304 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8305 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8306 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8307 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8308 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
8309 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8310 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8311 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8312 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8313 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8314 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8315 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8316 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8317 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8318 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8319 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8320 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8321 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
8322 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8323 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8324 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8325 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8326 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8327 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8328 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8329 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8330 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8331 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8332 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8333 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8334 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8335 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8336 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8337 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8338 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8339 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8340 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8341 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8342 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8343 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8344 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
8345 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8346 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8347 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8348 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8349 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8350 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8351 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8352 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8353 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8354 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8355 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8356 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8357 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8358 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8359 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8360 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8361 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8362 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8363 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8364 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8365 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8366 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8367 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8368 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8369 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8370 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8371 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8372 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8373 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8374 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8375 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8376 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8377 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8378 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8379 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
8380 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8381 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8382 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8383 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8384 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8385 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8386 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8387 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
8388 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
8389 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8390 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8391 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8392 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8393 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8394 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8395 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
8396 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8397 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8398 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8399 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8400 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8401 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8402 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8403 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8404 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8405 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8406 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8407 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8408 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8409 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8410 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8411 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8412 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8413 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8414 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8415 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8416 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8417 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8418 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8419 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8420 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8421 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8422 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8423 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8424 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8425 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8426 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8427 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8428 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8429 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8430 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8431 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8432 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8433 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8434 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8435 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8436 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8437 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8438 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8439 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8440 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
8441 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
8442 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8443 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8444 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8445 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8446 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8447 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8448 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8449 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8450 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8451 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8452 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8453 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8454 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8455 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8456 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8457 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8458 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8459 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8460 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8461 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8462 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8463 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8464 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8465 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8466 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8467 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8468 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8469 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8470 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8471 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8472 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8473 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
8474 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
8475 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
8476 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
8477 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8478 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8479 };