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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
166 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
167 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
168 unsigned export_shader;
169
170 shader->shader.bc.isa = rctx->isa;
171
172 if (dump) {
173 fprintf(stderr, "--------------------------------------------------------------\n");
174 tgsi_dump(sel->tokens, 0);
175
176 if (sel->so.num_outputs) {
177 r600_dump_streamout(&sel->so);
178 }
179 }
180 r = r600_shader_from_tgsi(rctx, shader, key);
181 if (r) {
182 R600_ERR("translation from TGSI failed !\n");
183 goto error;
184 }
185 if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) {
186 /* only disable for vertex shaders in tess paths */
187 if (key.vs.as_ls)
188 use_sb = 0;
189 }
190 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_CTRL);
191 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_EVAL);
192
193 /* disable SB for shaders using doubles */
194 use_sb &= !shader->shader.uses_doubles;
195
196 /* Check if the bytecode has already been built. When using the llvm
197 * backend, r600_shader_from_tgsi() will take care of building the
198 * bytecode.
199 */
200 if (!shader->shader.bc.bytecode) {
201 r = r600_bytecode_build(&shader->shader.bc);
202 if (r) {
203 R600_ERR("building bytecode failed !\n");
204 goto error;
205 }
206 }
207
208 if (dump && !sb_disasm) {
209 fprintf(stderr, "--------------------------------------------------------------\n");
210 r600_bytecode_disasm(&shader->shader.bc);
211 fprintf(stderr, "______________________________________________________________\n");
212 } else if ((dump && sb_disasm) || use_sb) {
213 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
214 dump, use_sb);
215 if (r) {
216 R600_ERR("r600_sb_bytecode_process failed !\n");
217 goto error;
218 }
219 }
220
221 if (shader->gs_copy_shader) {
222 if (dump) {
223 // dump copy shader
224 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
225 &shader->gs_copy_shader->shader, dump, 0);
226 if (r)
227 goto error;
228 }
229
230 if ((r = store_shader(ctx, shader->gs_copy_shader)))
231 goto error;
232 }
233
234 /* Store the shader in a buffer. */
235 if ((r = store_shader(ctx, shader)))
236 goto error;
237
238 /* Build state. */
239 switch (shader->shader.processor_type) {
240 case TGSI_PROCESSOR_TESS_CTRL:
241 evergreen_update_hs_state(ctx, shader);
242 break;
243 case TGSI_PROCESSOR_TESS_EVAL:
244 if (key.tes.as_es)
245 evergreen_update_es_state(ctx, shader);
246 else
247 evergreen_update_vs_state(ctx, shader);
248 break;
249 case TGSI_PROCESSOR_GEOMETRY:
250 if (rctx->b.chip_class >= EVERGREEN) {
251 evergreen_update_gs_state(ctx, shader);
252 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
253 } else {
254 r600_update_gs_state(ctx, shader);
255 r600_update_vs_state(ctx, shader->gs_copy_shader);
256 }
257 break;
258 case TGSI_PROCESSOR_VERTEX:
259 export_shader = key.vs.as_es;
260 if (rctx->b.chip_class >= EVERGREEN) {
261 if (key.vs.as_ls)
262 evergreen_update_ls_state(ctx, shader);
263 else if (key.vs.as_es)
264 evergreen_update_es_state(ctx, shader);
265 else
266 evergreen_update_vs_state(ctx, shader);
267 } else {
268 if (export_shader)
269 r600_update_es_state(ctx, shader);
270 else
271 r600_update_vs_state(ctx, shader);
272 }
273 break;
274 case TGSI_PROCESSOR_FRAGMENT:
275 if (rctx->b.chip_class >= EVERGREEN) {
276 evergreen_update_ps_state(ctx, shader);
277 } else {
278 r600_update_ps_state(ctx, shader);
279 }
280 break;
281 default:
282 r = -EINVAL;
283 goto error;
284 }
285 return 0;
286
287 error:
288 r600_pipe_shader_destroy(ctx, shader);
289 return r;
290 }
291
292 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
293 {
294 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
295 r600_bytecode_clear(&shader->shader.bc);
296 r600_release_command_buffer(&shader->command_buffer);
297 }
298
299 /*
300 * tgsi -> r600 shader
301 */
302 struct r600_shader_tgsi_instruction;
303
304 struct r600_shader_src {
305 unsigned sel;
306 unsigned swizzle[4];
307 unsigned neg;
308 unsigned abs;
309 unsigned rel;
310 unsigned kc_bank;
311 boolean kc_rel; /* true if cache bank is indexed */
312 uint32_t value[4];
313 };
314
315 struct eg_interp {
316 boolean enabled;
317 unsigned ij_index;
318 };
319
320 struct r600_shader_ctx {
321 struct tgsi_shader_info info;
322 struct tgsi_parse_context parse;
323 const struct tgsi_token *tokens;
324 unsigned type;
325 unsigned file_offset[TGSI_FILE_COUNT];
326 unsigned temp_reg;
327 const struct r600_shader_tgsi_instruction *inst_info;
328 struct r600_bytecode *bc;
329 struct r600_shader *shader;
330 struct r600_shader_src src[4];
331 uint32_t *literals;
332 uint32_t nliterals;
333 uint32_t max_driver_temp_used;
334 boolean use_llvm;
335 /* needed for evergreen interpolation */
336 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
337 /* evergreen/cayman also store sample mask in face register */
338 int face_gpr;
339 /* sample id is .w component stored in fixed point position register */
340 int fixed_pt_position_gpr;
341 int colors_used;
342 boolean clip_vertex_write;
343 unsigned cv_output;
344 unsigned edgeflag_output;
345 int fragcoord_input;
346 int native_integers;
347 int next_ring_offset;
348 int gs_out_ring_offset;
349 int gs_next_vertex;
350 struct r600_shader *gs_for_vs;
351 int gs_export_gpr_tregs[4];
352 const struct pipe_stream_output_info *gs_stream_output_info;
353 unsigned enabled_stream_buffers_mask;
354 unsigned tess_input_info; /* temp with tess input offsets */
355 unsigned tess_output_info; /* temp with tess input offsets */
356 };
357
358 struct r600_shader_tgsi_instruction {
359 unsigned op;
360 int (*process)(struct r600_shader_ctx *ctx);
361 };
362
363 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
364 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
365 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
366 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
367 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
368 static int tgsi_else(struct r600_shader_ctx *ctx);
369 static int tgsi_endif(struct r600_shader_ctx *ctx);
370 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
371 static int tgsi_endloop(struct r600_shader_ctx *ctx);
372 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
373 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
374 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
375 unsigned int dst_reg);
376 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
377 const struct r600_shader_src *shader_src,
378 unsigned chan);
379 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
380 unsigned dst_reg);
381
382 static int tgsi_last_instruction(unsigned writemask)
383 {
384 int i, lasti = 0;
385
386 for (i = 0; i < 4; i++) {
387 if (writemask & (1 << i)) {
388 lasti = i;
389 }
390 }
391 return lasti;
392 }
393
394 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
395 {
396 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
397 int j;
398
399 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
400 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
401 return -EINVAL;
402 }
403 if (i->Instruction.Predicate) {
404 R600_ERR("predicate unsupported\n");
405 return -EINVAL;
406 }
407 #if 0
408 if (i->Instruction.Label) {
409 R600_ERR("label unsupported\n");
410 return -EINVAL;
411 }
412 #endif
413 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
414 if (i->Src[j].Register.Dimension) {
415 switch (i->Src[j].Register.File) {
416 case TGSI_FILE_CONSTANT:
417 break;
418 case TGSI_FILE_INPUT:
419 if (ctx->type == TGSI_PROCESSOR_GEOMETRY ||
420 ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
421 ctx->type == TGSI_PROCESSOR_TESS_EVAL)
422 break;
423 case TGSI_FILE_OUTPUT:
424 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
425 break;
426 default:
427 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
428 i->Src[j].Register.File,
429 i->Src[j].Register.Dimension);
430 return -EINVAL;
431 }
432 }
433 }
434 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
435 if (i->Dst[j].Register.Dimension) {
436 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
437 continue;
438 R600_ERR("unsupported dst (dimension)\n");
439 return -EINVAL;
440 }
441 }
442 return 0;
443 }
444
445 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
446 {
447 if (interpolate == TGSI_INTERPOLATE_COLOR ||
448 interpolate == TGSI_INTERPOLATE_LINEAR ||
449 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
450 {
451 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
452 int loc;
453
454 switch(location) {
455 case TGSI_INTERPOLATE_LOC_CENTER:
456 loc = 1;
457 break;
458 case TGSI_INTERPOLATE_LOC_CENTROID:
459 loc = 2;
460 break;
461 case TGSI_INTERPOLATE_LOC_SAMPLE:
462 default:
463 loc = 0; break;
464 }
465
466 return is_linear * 3 + loc;
467 }
468
469 return -1;
470 }
471
472 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
473 int input)
474 {
475 int i = eg_get_interpolator_index(
476 ctx->shader->input[input].interpolate,
477 ctx->shader->input[input].interpolate_location);
478 assert(i >= 0);
479 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
480 }
481
482 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
483 {
484 int i, r;
485 struct r600_bytecode_alu alu;
486 int gpr = 0, base_chan = 0;
487 int ij_index = ctx->shader->input[input].ij_index;
488
489 /* work out gpr and base_chan from index */
490 gpr = ij_index / 2;
491 base_chan = (2 * (ij_index % 2)) + 1;
492
493 for (i = 0; i < 8; i++) {
494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
495
496 if (i < 4)
497 alu.op = ALU_OP2_INTERP_ZW;
498 else
499 alu.op = ALU_OP2_INTERP_XY;
500
501 if ((i > 1) && (i < 6)) {
502 alu.dst.sel = ctx->shader->input[input].gpr;
503 alu.dst.write = 1;
504 }
505
506 alu.dst.chan = i % 4;
507
508 alu.src[0].sel = gpr;
509 alu.src[0].chan = (base_chan - (i % 2));
510
511 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
512
513 alu.bank_swizzle_force = SQ_ALU_VEC_210;
514 if ((i % 4) == 3)
515 alu.last = 1;
516 r = r600_bytecode_add_alu(ctx->bc, &alu);
517 if (r)
518 return r;
519 }
520 return 0;
521 }
522
523 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
524 {
525 int i, r;
526 struct r600_bytecode_alu alu;
527
528 for (i = 0; i < 4; i++) {
529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
530
531 alu.op = ALU_OP1_INTERP_LOAD_P0;
532
533 alu.dst.sel = ctx->shader->input[input].gpr;
534 alu.dst.write = 1;
535
536 alu.dst.chan = i;
537
538 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
539 alu.src[0].chan = i;
540
541 if (i == 3)
542 alu.last = 1;
543 r = r600_bytecode_add_alu(ctx->bc, &alu);
544 if (r)
545 return r;
546 }
547 return 0;
548 }
549
550 /*
551 * Special export handling in shaders
552 *
553 * shader export ARRAY_BASE for EXPORT_POS:
554 * 60 is position
555 * 61 is misc vector
556 * 62, 63 are clip distance vectors
557 *
558 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
559 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
560 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
561 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
562 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
563 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
564 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
565 * exclusive from render target index)
566 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
567 *
568 *
569 * shader export ARRAY_BASE for EXPORT_PIXEL:
570 * 0-7 CB targets
571 * 61 computed Z vector
572 *
573 * The use of the values exported in the computed Z vector are controlled
574 * by DB_SHADER_CONTROL:
575 * Z_EXPORT_ENABLE - Z as a float in RED
576 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
577 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
578 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
579 * DB_SOURCE_FORMAT - export control restrictions
580 *
581 */
582
583
584 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
585 static int r600_spi_sid(struct r600_shader_io * io)
586 {
587 int index, name = io->name;
588
589 /* These params are handled differently, they don't need
590 * semantic indices, so we'll use 0 for them.
591 */
592 if (name == TGSI_SEMANTIC_POSITION ||
593 name == TGSI_SEMANTIC_PSIZE ||
594 name == TGSI_SEMANTIC_EDGEFLAG ||
595 name == TGSI_SEMANTIC_FACE ||
596 name == TGSI_SEMANTIC_SAMPLEMASK)
597 index = 0;
598 else {
599 if (name == TGSI_SEMANTIC_GENERIC) {
600 /* For generic params simply use sid from tgsi */
601 index = io->sid;
602 } else {
603 /* For non-generic params - pack name and sid into 8 bits */
604 index = 0x80 | (name<<3) | (io->sid);
605 }
606
607 /* Make sure that all really used indices have nonzero value, so
608 * we can just compare it to 0 later instead of comparing the name
609 * with different values to detect special cases. */
610 index++;
611 }
612
613 return index;
614 };
615
616 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
617 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
618 {
619 switch (semantic_name) {
620 case TGSI_SEMANTIC_POSITION:
621 return 0;
622 case TGSI_SEMANTIC_PSIZE:
623 return 1;
624 case TGSI_SEMANTIC_CLIPDIST:
625 assert(index <= 1);
626 return 2 + index;
627 case TGSI_SEMANTIC_GENERIC:
628 if (index <= 63-4)
629 return 4 + index - 9;
630 else
631 /* same explanation as in the default statement,
632 * the only user hitting this is st/nine.
633 */
634 return 0;
635
636 /* patch indices are completely separate and thus start from 0 */
637 case TGSI_SEMANTIC_TESSOUTER:
638 return 0;
639 case TGSI_SEMANTIC_TESSINNER:
640 return 1;
641 case TGSI_SEMANTIC_PATCH:
642 return 2 + index;
643
644 default:
645 /* Don't fail here. The result of this function is only used
646 * for LS, TCS, TES, and GS, where legacy GL semantics can't
647 * occur, but this function is called for all vertex shaders
648 * before it's known whether LS will be compiled or not.
649 */
650 return 0;
651 }
652 }
653
654 /* turn input into interpolate on EG */
655 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
656 {
657 int r = 0;
658
659 if (ctx->shader->input[index].spi_sid) {
660 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
661 if (ctx->shader->input[index].interpolate > 0) {
662 evergreen_interp_assign_ij_index(ctx, index);
663 if (!ctx->use_llvm)
664 r = evergreen_interp_alu(ctx, index);
665 } else {
666 if (!ctx->use_llvm)
667 r = evergreen_interp_flat(ctx, index);
668 }
669 }
670 return r;
671 }
672
673 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
674 {
675 struct r600_bytecode_alu alu;
676 int i, r;
677 int gpr_front = ctx->shader->input[front].gpr;
678 int gpr_back = ctx->shader->input[back].gpr;
679
680 for (i = 0; i < 4; i++) {
681 memset(&alu, 0, sizeof(alu));
682 alu.op = ALU_OP3_CNDGT;
683 alu.is_op3 = 1;
684 alu.dst.write = 1;
685 alu.dst.sel = gpr_front;
686 alu.src[0].sel = ctx->face_gpr;
687 alu.src[1].sel = gpr_front;
688 alu.src[2].sel = gpr_back;
689
690 alu.dst.chan = i;
691 alu.src[1].chan = i;
692 alu.src[2].chan = i;
693 alu.last = (i==3);
694
695 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
696 return r;
697 }
698
699 return 0;
700 }
701
702 /* execute a single slot ALU calculation */
703 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
704 int dst_sel, int dst_chan,
705 int src0_sel, unsigned src0_chan_val,
706 int src1_sel, unsigned src1_chan_val)
707 {
708 struct r600_bytecode_alu alu;
709 int r, i;
710
711 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
712 for (i = 0; i < 4; i++) {
713 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
714 alu.op = op;
715 alu.src[0].sel = src0_sel;
716 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
717 alu.src[0].value = src0_chan_val;
718 else
719 alu.src[0].chan = src0_chan_val;
720 alu.src[1].sel = src1_sel;
721 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
722 alu.src[1].value = src1_chan_val;
723 else
724 alu.src[1].chan = src1_chan_val;
725 alu.dst.sel = dst_sel;
726 alu.dst.chan = i;
727 alu.dst.write = i == dst_chan;
728 alu.last = (i == 3);
729 r = r600_bytecode_add_alu(ctx->bc, &alu);
730 if (r)
731 return r;
732 }
733 return 0;
734 }
735
736 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
737 alu.op = op;
738 alu.src[0].sel = src0_sel;
739 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
740 alu.src[0].value = src0_chan_val;
741 else
742 alu.src[0].chan = src0_chan_val;
743 alu.src[1].sel = src1_sel;
744 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
745 alu.src[1].value = src1_chan_val;
746 else
747 alu.src[1].chan = src1_chan_val;
748 alu.dst.sel = dst_sel;
749 alu.dst.chan = dst_chan;
750 alu.dst.write = 1;
751 alu.last = 1;
752 r = r600_bytecode_add_alu(ctx->bc, &alu);
753 if (r)
754 return r;
755 return 0;
756 }
757
758 /* execute a single slot ALU calculation */
759 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
760 int dst_sel, int dst_chan,
761 int src0_sel, unsigned src0_chan_val,
762 int src1_sel, unsigned src1_chan_val,
763 int src2_sel, unsigned src2_chan_val)
764 {
765 struct r600_bytecode_alu alu;
766 int r;
767
768 /* validate this for other ops */
769 assert(op == ALU_OP3_MULADD_UINT24);
770 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
771 alu.op = op;
772 alu.src[0].sel = src0_sel;
773 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
774 alu.src[0].value = src0_chan_val;
775 else
776 alu.src[0].chan = src0_chan_val;
777 alu.src[1].sel = src1_sel;
778 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
779 alu.src[1].value = src1_chan_val;
780 else
781 alu.src[1].chan = src1_chan_val;
782 alu.src[2].sel = src2_sel;
783 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
784 alu.src[2].value = src2_chan_val;
785 else
786 alu.src[2].chan = src2_chan_val;
787 alu.dst.sel = dst_sel;
788 alu.dst.chan = dst_chan;
789 alu.is_op3 = 1;
790 alu.last = 1;
791 r = r600_bytecode_add_alu(ctx->bc, &alu);
792 if (r)
793 return r;
794 return 0;
795 }
796
797 /* put it in temp_reg.x */
798 static int get_lds_offset0(struct r600_shader_ctx *ctx,
799 int rel_patch_chan,
800 int temp_reg, bool is_patch_var)
801 {
802 int r;
803
804 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
805 /* ADD
806 Dimension - patch0_offset (input_vals.z),
807 Non-dim - patch0_data_offset (input_vals.w)
808 */
809 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
810 temp_reg, 0,
811 ctx->tess_output_info, 0,
812 0, rel_patch_chan,
813 ctx->tess_output_info, is_patch_var ? 3 : 2);
814 if (r)
815 return r;
816 return 0;
817 }
818
819 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
820 {
821 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
822 }
823
824 static int r600_get_temp(struct r600_shader_ctx *ctx)
825 {
826 return ctx->temp_reg + ctx->max_driver_temp_used++;
827 }
828
829 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
830 {
831 int i;
832 i = ctx->shader->noutput++;
833 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
834 ctx->shader->output[i].sid = 0;
835 ctx->shader->output[i].gpr = 0;
836 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
837 ctx->shader->output[i].write_mask = 0x4;
838 ctx->shader->output[i].spi_sid = prim_id_sid;
839
840 return 0;
841 }
842
843 static int tgsi_barrier(struct r600_shader_ctx *ctx)
844 {
845 struct r600_bytecode_alu alu;
846 int r;
847
848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
849 alu.op = ctx->inst_info->op;
850 alu.last = 1;
851
852 r = r600_bytecode_add_alu(ctx->bc, &alu);
853 if (r)
854 return r;
855 return 0;
856 }
857
858 static int tgsi_declaration(struct r600_shader_ctx *ctx)
859 {
860 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
861 int r, i, j, count = d->Range.Last - d->Range.First + 1;
862
863 switch (d->Declaration.File) {
864 case TGSI_FILE_INPUT:
865 for (j = 0; j < count; j++) {
866 i = ctx->shader->ninput + j;
867 assert(i < Elements(ctx->shader->input));
868 ctx->shader->input[i].name = d->Semantic.Name;
869 ctx->shader->input[i].sid = d->Semantic.Index + j;
870 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
871 ctx->shader->input[i].interpolate_location = d->Interp.Location;
872 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
873 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
874 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
875 switch (ctx->shader->input[i].name) {
876 case TGSI_SEMANTIC_FACE:
877 if (ctx->face_gpr != -1)
878 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
879 else
880 ctx->face_gpr = ctx->shader->input[i].gpr;
881 break;
882 case TGSI_SEMANTIC_COLOR:
883 ctx->colors_used++;
884 break;
885 case TGSI_SEMANTIC_POSITION:
886 ctx->fragcoord_input = i;
887 break;
888 case TGSI_SEMANTIC_PRIMID:
889 /* set this for now */
890 ctx->shader->gs_prim_id_input = true;
891 ctx->shader->ps_prim_id_input = i;
892 break;
893 }
894 if (ctx->bc->chip_class >= EVERGREEN) {
895 if ((r = evergreen_interp_input(ctx, i)))
896 return r;
897 }
898 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
899 /* FIXME probably skip inputs if they aren't passed in the ring */
900 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
901 ctx->next_ring_offset += 16;
902 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
903 ctx->shader->gs_prim_id_input = true;
904 }
905 }
906 ctx->shader->ninput += count;
907 break;
908 case TGSI_FILE_OUTPUT:
909 for (j = 0; j < count; j++) {
910 i = ctx->shader->noutput + j;
911 assert(i < Elements(ctx->shader->output));
912 ctx->shader->output[i].name = d->Semantic.Name;
913 ctx->shader->output[i].sid = d->Semantic.Index + j;
914 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
915 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
916 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
917 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
918 ctx->type == TGSI_PROCESSOR_GEOMETRY ||
919 ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
920 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
921 switch (d->Semantic.Name) {
922 case TGSI_SEMANTIC_CLIPDIST:
923 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
924 ((d->Semantic.Index + j) << 2);
925 break;
926 case TGSI_SEMANTIC_PSIZE:
927 ctx->shader->vs_out_misc_write = 1;
928 ctx->shader->vs_out_point_size = 1;
929 break;
930 case TGSI_SEMANTIC_EDGEFLAG:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_edgeflag = 1;
933 ctx->edgeflag_output = i;
934 break;
935 case TGSI_SEMANTIC_VIEWPORT_INDEX:
936 ctx->shader->vs_out_misc_write = 1;
937 ctx->shader->vs_out_viewport = 1;
938 break;
939 case TGSI_SEMANTIC_LAYER:
940 ctx->shader->vs_out_misc_write = 1;
941 ctx->shader->vs_out_layer = 1;
942 break;
943 case TGSI_SEMANTIC_CLIPVERTEX:
944 ctx->clip_vertex_write = TRUE;
945 ctx->cv_output = i;
946 break;
947 }
948 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
949 ctx->gs_out_ring_offset += 16;
950 }
951 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
952 switch (d->Semantic.Name) {
953 case TGSI_SEMANTIC_COLOR:
954 ctx->shader->nr_ps_max_color_exports++;
955 break;
956 }
957 }
958 }
959 ctx->shader->noutput += count;
960 break;
961 case TGSI_FILE_TEMPORARY:
962 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
963 if (d->Array.ArrayID) {
964 r600_add_gpr_array(ctx->shader,
965 ctx->file_offset[TGSI_FILE_TEMPORARY] +
966 d->Range.First,
967 d->Range.Last - d->Range.First + 1, 0x0F);
968 }
969 }
970 break;
971
972 case TGSI_FILE_CONSTANT:
973 case TGSI_FILE_SAMPLER:
974 case TGSI_FILE_SAMPLER_VIEW:
975 case TGSI_FILE_ADDRESS:
976 break;
977
978 case TGSI_FILE_SYSTEM_VALUE:
979 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
980 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
981 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
982 break; /* Already handled from allocate_system_value_inputs */
983 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
984 if (!ctx->native_integers) {
985 struct r600_bytecode_alu alu;
986 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
987
988 alu.op = ALU_OP1_INT_TO_FLT;
989 alu.src[0].sel = 0;
990 alu.src[0].chan = 3;
991
992 alu.dst.sel = 0;
993 alu.dst.chan = 3;
994 alu.dst.write = 1;
995 alu.last = 1;
996
997 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
998 return r;
999 }
1000 break;
1001 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1002 break;
1003 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1004 break;
1005 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1006 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1007 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1008 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1009 unsigned temp_reg = r600_get_temp(ctx);
1010
1011 r = get_lds_offset0(ctx, 2, temp_reg, true);
1012 if (r)
1013 return r;
1014
1015 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1016 temp_reg, 0,
1017 temp_reg, 0,
1018 V_SQ_ALU_SRC_LITERAL, param * 16);
1019 if (r)
1020 return r;
1021
1022 do_lds_fetch_values(ctx, temp_reg, dreg);
1023 }
1024 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1025 /* MOV r1.x, r0.x;
1026 MOV r1.y, r0.y;
1027 */
1028 for (i = 0; i < 2; i++) {
1029 struct r600_bytecode_alu alu;
1030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1031 alu.op = ALU_OP1_MOV;
1032 alu.src[0].sel = 0;
1033 alu.src[0].chan = 0 + i;
1034 alu.dst.sel = 1;
1035 alu.dst.chan = 0 + i;
1036 alu.dst.write = 1;
1037 alu.last = (i == 1) ? 1 : 0;
1038 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1039 return r;
1040 }
1041 /* ADD r1.z, 1.0f, -r0.x */
1042 struct r600_bytecode_alu alu;
1043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1044 alu.op = ALU_OP2_ADD;
1045 alu.src[0].sel = V_SQ_ALU_SRC_1;
1046 alu.src[1].sel = 1;
1047 alu.src[1].chan = 0;
1048 alu.src[1].neg = 1;
1049 alu.dst.sel = 1;
1050 alu.dst.chan = 2;
1051 alu.dst.write = 1;
1052 alu.last = 1;
1053 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1054 return r;
1055
1056 /* ADD r1.z, r1.z, -r1.y */
1057 alu.op = ALU_OP2_ADD;
1058 alu.src[0].sel = 1;
1059 alu.src[0].chan = 2;
1060 alu.src[1].sel = 1;
1061 alu.src[1].chan = 1;
1062 alu.src[1].neg = 1;
1063 alu.dst.sel = 1;
1064 alu.dst.chan = 2;
1065 alu.dst.write = 1;
1066 alu.last = 1;
1067 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1068 return r;
1069 break;
1070 }
1071 break;
1072 default:
1073 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1074 return -EINVAL;
1075 }
1076 return 0;
1077 }
1078
1079 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1080 {
1081 struct tgsi_parse_context parse;
1082 struct {
1083 boolean enabled;
1084 int *reg;
1085 unsigned name, alternate_name;
1086 } inputs[2] = {
1087 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1088
1089 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1090 };
1091 int i, k, num_regs = 0;
1092
1093 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1094 return 0;
1095 }
1096
1097 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1098 while (!tgsi_parse_end_of_tokens(&parse)) {
1099 tgsi_parse_token(&parse);
1100
1101 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1102 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1103 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1104 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1105 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1106 {
1107 int interpolate, location, k;
1108
1109 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1110 location = TGSI_INTERPOLATE_LOC_CENTER;
1111 inputs[1].enabled = true; /* needs SAMPLEID */
1112 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1113 location = TGSI_INTERPOLATE_LOC_CENTER;
1114 /* Needs sample positions, currently those are always available */
1115 } else {
1116 location = TGSI_INTERPOLATE_LOC_CENTROID;
1117 }
1118
1119 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1120 k = eg_get_interpolator_index(interpolate, location);
1121 ctx->eg_interpolators[k].enabled = true;
1122 }
1123 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1124 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1125 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1126 for (k = 0; k < Elements(inputs); k++) {
1127 if (d->Semantic.Name == inputs[k].name ||
1128 d->Semantic.Name == inputs[k].alternate_name) {
1129 inputs[k].enabled = true;
1130 }
1131 }
1132 }
1133 }
1134 }
1135
1136 tgsi_parse_free(&parse);
1137
1138 for (i = 0; i < Elements(inputs); i++) {
1139 boolean enabled = inputs[i].enabled;
1140 int *reg = inputs[i].reg;
1141 unsigned name = inputs[i].name;
1142
1143 if (enabled) {
1144 int gpr = gpr_offset + num_regs++;
1145
1146 // add to inputs, allocate a gpr
1147 k = ctx->shader->ninput ++;
1148 ctx->shader->input[k].name = name;
1149 ctx->shader->input[k].sid = 0;
1150 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1151 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1152 *reg = ctx->shader->input[k].gpr = gpr;
1153 }
1154 }
1155
1156 return gpr_offset + num_regs;
1157 }
1158
1159 /*
1160 * for evergreen we need to scan the shader to find the number of GPRs we need to
1161 * reserve for interpolation and system values
1162 *
1163 * we need to know if we are going to emit
1164 * any sample or centroid inputs
1165 * if perspective and linear are required
1166 */
1167 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1168 {
1169 int i;
1170 int num_baryc;
1171 struct tgsi_parse_context parse;
1172
1173 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1174
1175 for (i = 0; i < ctx->info.num_inputs; i++) {
1176 int k;
1177 /* skip position/face/mask/sampleid */
1178 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1179 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1180 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1181 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1182 continue;
1183
1184 k = eg_get_interpolator_index(
1185 ctx->info.input_interpolate[i],
1186 ctx->info.input_interpolate_loc[i]);
1187 if (k >= 0)
1188 ctx->eg_interpolators[k].enabled = TRUE;
1189 }
1190
1191 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1192 return 0;
1193 }
1194
1195 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1196 while (!tgsi_parse_end_of_tokens(&parse)) {
1197 tgsi_parse_token(&parse);
1198
1199 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1200 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1201 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1202 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1203 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1204 {
1205 int interpolate, location, k;
1206
1207 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1208 location = TGSI_INTERPOLATE_LOC_CENTER;
1209 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1210 location = TGSI_INTERPOLATE_LOC_CENTER;
1211 } else {
1212 location = TGSI_INTERPOLATE_LOC_CENTROID;
1213 }
1214
1215 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1216 k = eg_get_interpolator_index(interpolate, location);
1217 ctx->eg_interpolators[k].enabled = true;
1218 }
1219 }
1220 }
1221
1222 tgsi_parse_free(&parse);
1223
1224 /* assign gpr to each interpolator according to priority */
1225 num_baryc = 0;
1226 for (i = 0; i < Elements(ctx->eg_interpolators); i++) {
1227 if (ctx->eg_interpolators[i].enabled) {
1228 ctx->eg_interpolators[i].ij_index = num_baryc;
1229 num_baryc ++;
1230 }
1231 }
1232
1233 /* XXX PULL MODEL and LINE STIPPLE */
1234
1235 num_baryc = (num_baryc + 1) >> 1;
1236 return allocate_system_value_inputs(ctx, num_baryc);
1237 }
1238
1239 /* sample_id_sel == NULL means fetch for current sample */
1240 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1241 {
1242 struct r600_bytecode_vtx vtx;
1243 int r, t1;
1244
1245 assert(ctx->fixed_pt_position_gpr != -1);
1246
1247 t1 = r600_get_temp(ctx);
1248
1249 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1250 vtx.op = FETCH_OP_VFETCH;
1251 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1252 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1253 if (sample_id == NULL) {
1254 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1255 vtx.src_sel_x = 3;
1256 }
1257 else {
1258 struct r600_bytecode_alu alu;
1259
1260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1261 alu.op = ALU_OP1_MOV;
1262 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1263 alu.dst.sel = t1;
1264 alu.dst.write = 1;
1265 alu.last = 1;
1266 r = r600_bytecode_add_alu(ctx->bc, &alu);
1267 if (r)
1268 return r;
1269
1270 vtx.src_gpr = t1;
1271 vtx.src_sel_x = 0;
1272 }
1273 vtx.mega_fetch_count = 16;
1274 vtx.dst_gpr = t1;
1275 vtx.dst_sel_x = 0;
1276 vtx.dst_sel_y = 1;
1277 vtx.dst_sel_z = 2;
1278 vtx.dst_sel_w = 3;
1279 vtx.data_format = FMT_32_32_32_32_FLOAT;
1280 vtx.num_format_all = 2;
1281 vtx.format_comp_all = 1;
1282 vtx.use_const_fields = 0;
1283 vtx.offset = 1; // first element is size of buffer
1284 vtx.endian = r600_endian_swap(32);
1285 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1286
1287 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1288 if (r)
1289 return r;
1290
1291 return t1;
1292 }
1293
1294 static void tgsi_src(struct r600_shader_ctx *ctx,
1295 const struct tgsi_full_src_register *tgsi_src,
1296 struct r600_shader_src *r600_src)
1297 {
1298 memset(r600_src, 0, sizeof(*r600_src));
1299 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1300 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1301 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1302 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1303 r600_src->neg = tgsi_src->Register.Negate;
1304 r600_src->abs = tgsi_src->Register.Absolute;
1305
1306 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1307 int index;
1308 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1309 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1310 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1311
1312 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1313 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1314 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1315 return;
1316 }
1317 index = tgsi_src->Register.Index;
1318 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1319 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1320 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1321 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1322 r600_src->swizzle[0] = 2; // Z value
1323 r600_src->swizzle[1] = 2;
1324 r600_src->swizzle[2] = 2;
1325 r600_src->swizzle[3] = 2;
1326 r600_src->sel = ctx->face_gpr;
1327 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1328 r600_src->swizzle[0] = 3; // W value
1329 r600_src->swizzle[1] = 3;
1330 r600_src->swizzle[2] = 3;
1331 r600_src->swizzle[3] = 3;
1332 r600_src->sel = ctx->fixed_pt_position_gpr;
1333 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1334 r600_src->swizzle[0] = 0;
1335 r600_src->swizzle[1] = 1;
1336 r600_src->swizzle[2] = 4;
1337 r600_src->swizzle[3] = 4;
1338 r600_src->sel = load_sample_position(ctx, NULL, -1);
1339 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1340 r600_src->swizzle[0] = 3;
1341 r600_src->swizzle[1] = 3;
1342 r600_src->swizzle[2] = 3;
1343 r600_src->swizzle[3] = 3;
1344 r600_src->sel = 0;
1345 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1346 r600_src->swizzle[0] = 0;
1347 r600_src->swizzle[1] = 0;
1348 r600_src->swizzle[2] = 0;
1349 r600_src->swizzle[3] = 0;
1350 r600_src->sel = 0;
1351 } else if (ctx->type != TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1352 r600_src->swizzle[0] = 3;
1353 r600_src->swizzle[1] = 3;
1354 r600_src->swizzle[2] = 3;
1355 r600_src->swizzle[3] = 3;
1356 r600_src->sel = 1;
1357 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1358 r600_src->swizzle[0] = 2;
1359 r600_src->swizzle[1] = 2;
1360 r600_src->swizzle[2] = 2;
1361 r600_src->swizzle[3] = 2;
1362 r600_src->sel = 0;
1363 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1364 r600_src->sel = 1;
1365 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1366 r600_src->sel = 3;
1367 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1368 r600_src->sel = 2;
1369 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1370 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
1371 r600_src->sel = ctx->tess_input_info;
1372 r600_src->swizzle[0] = 2;
1373 r600_src->swizzle[1] = 2;
1374 r600_src->swizzle[2] = 2;
1375 r600_src->swizzle[3] = 2;
1376 } else {
1377 r600_src->sel = ctx->tess_input_info;
1378 r600_src->swizzle[0] = 3;
1379 r600_src->swizzle[1] = 3;
1380 r600_src->swizzle[2] = 3;
1381 r600_src->swizzle[3] = 3;
1382 }
1383 } else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1384 r600_src->sel = 0;
1385 r600_src->swizzle[0] = 0;
1386 r600_src->swizzle[1] = 0;
1387 r600_src->swizzle[2] = 0;
1388 r600_src->swizzle[3] = 0;
1389 } else if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1390 r600_src->sel = 0;
1391 r600_src->swizzle[0] = 3;
1392 r600_src->swizzle[1] = 3;
1393 r600_src->swizzle[2] = 3;
1394 r600_src->swizzle[3] = 3;
1395 }
1396 } else {
1397 if (tgsi_src->Register.Indirect)
1398 r600_src->rel = V_SQ_REL_RELATIVE;
1399 r600_src->sel = tgsi_src->Register.Index;
1400 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1401 }
1402 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1403 if (tgsi_src->Register.Dimension) {
1404 r600_src->kc_bank = tgsi_src->Dimension.Index;
1405 if (tgsi_src->Dimension.Indirect) {
1406 r600_src->kc_rel = 1;
1407 }
1408 }
1409 }
1410 }
1411
1412 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1413 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1414 unsigned int dst_reg)
1415 {
1416 struct r600_bytecode_vtx vtx;
1417 unsigned int ar_reg;
1418 int r;
1419
1420 if (offset) {
1421 struct r600_bytecode_alu alu;
1422
1423 memset(&alu, 0, sizeof(alu));
1424
1425 alu.op = ALU_OP2_ADD_INT;
1426 alu.src[0].sel = ctx->bc->ar_reg;
1427 alu.src[0].chan = ar_chan;
1428
1429 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1430 alu.src[1].value = offset;
1431
1432 alu.dst.sel = dst_reg;
1433 alu.dst.chan = ar_chan;
1434 alu.dst.write = 1;
1435 alu.last = 1;
1436
1437 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1438 return r;
1439
1440 ar_reg = dst_reg;
1441 } else {
1442 ar_reg = ctx->bc->ar_reg;
1443 }
1444
1445 memset(&vtx, 0, sizeof(vtx));
1446 vtx.buffer_id = cb_idx;
1447 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1448 vtx.src_gpr = ar_reg;
1449 vtx.src_sel_x = ar_chan;
1450 vtx.mega_fetch_count = 16;
1451 vtx.dst_gpr = dst_reg;
1452 vtx.dst_sel_x = 0; /* SEL_X */
1453 vtx.dst_sel_y = 1; /* SEL_Y */
1454 vtx.dst_sel_z = 2; /* SEL_Z */
1455 vtx.dst_sel_w = 3; /* SEL_W */
1456 vtx.data_format = FMT_32_32_32_32_FLOAT;
1457 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1458 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1459 vtx.endian = r600_endian_swap(32);
1460 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1461
1462 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1463 return r;
1464
1465 return 0;
1466 }
1467
1468 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1469 {
1470 struct r600_bytecode_vtx vtx;
1471 int r;
1472 unsigned index = src->Register.Index;
1473 unsigned vtx_id = src->Dimension.Index;
1474 int offset_reg = vtx_id / 3;
1475 int offset_chan = vtx_id % 3;
1476 int t2 = 0;
1477
1478 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1479 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1480
1481 if (offset_reg == 0 && offset_chan == 2)
1482 offset_chan = 3;
1483
1484 if (src->Dimension.Indirect || src->Register.Indirect)
1485 t2 = r600_get_temp(ctx);
1486
1487 if (src->Dimension.Indirect) {
1488 int treg[3];
1489 struct r600_bytecode_alu alu;
1490 int r, i;
1491
1492 /* you have got to be shitting me -
1493 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1494 at least this is what fglrx seems to do. */
1495 for (i = 0; i < 3; i++) {
1496 treg[i] = r600_get_temp(ctx);
1497 }
1498 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1499
1500 for (i = 0; i < 3; i++) {
1501 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1502 alu.op = ALU_OP1_MOV;
1503 alu.src[0].sel = 0;
1504 alu.src[0].chan = i == 2 ? 3 : i;
1505 alu.dst.sel = treg[i];
1506 alu.dst.chan = 0;
1507 alu.dst.write = 1;
1508 alu.last = 1;
1509 r = r600_bytecode_add_alu(ctx->bc, &alu);
1510 if (r)
1511 return r;
1512 }
1513 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1514 alu.op = ALU_OP1_MOV;
1515 alu.src[0].sel = treg[0];
1516 alu.src[0].rel = 1;
1517 alu.dst.sel = t2;
1518 alu.dst.write = 1;
1519 alu.last = 1;
1520 r = r600_bytecode_add_alu(ctx->bc, &alu);
1521 if (r)
1522 return r;
1523 offset_reg = t2;
1524 offset_chan = 0;
1525 }
1526
1527 if (src->Register.Indirect) {
1528 int addr_reg;
1529 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1530
1531 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1532
1533 /* pull the value from index_reg */
1534 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1535 t2, 1,
1536 addr_reg, 0,
1537 V_SQ_ALU_SRC_LITERAL, first);
1538 if (r)
1539 return r;
1540 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1541 t2, 0,
1542 t2, 1,
1543 V_SQ_ALU_SRC_LITERAL, 4,
1544 offset_reg, offset_chan);
1545 if (r)
1546 return r;
1547 offset_reg = t2;
1548 offset_chan = 0;
1549 index = src->Register.Index - first;
1550 }
1551
1552 memset(&vtx, 0, sizeof(vtx));
1553 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1554 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1555 vtx.src_gpr = offset_reg;
1556 vtx.src_sel_x = offset_chan;
1557 vtx.offset = index * 16; /*bytes*/
1558 vtx.mega_fetch_count = 16;
1559 vtx.dst_gpr = dst_reg;
1560 vtx.dst_sel_x = 0; /* SEL_X */
1561 vtx.dst_sel_y = 1; /* SEL_Y */
1562 vtx.dst_sel_z = 2; /* SEL_Z */
1563 vtx.dst_sel_w = 3; /* SEL_W */
1564 if (ctx->bc->chip_class >= EVERGREEN) {
1565 vtx.use_const_fields = 1;
1566 } else {
1567 vtx.data_format = FMT_32_32_32_32_FLOAT;
1568 }
1569
1570 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1571 return r;
1572
1573 return 0;
1574 }
1575
1576 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1577 {
1578 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1579 int i;
1580
1581 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1582 struct tgsi_full_src_register *src = &inst->Src[i];
1583
1584 if (src->Register.File == TGSI_FILE_INPUT) {
1585 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1586 /* primitive id is in R0.z */
1587 ctx->src[i].sel = 0;
1588 ctx->src[i].swizzle[0] = 2;
1589 }
1590 }
1591 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1592 int treg = r600_get_temp(ctx);
1593
1594 fetch_gs_input(ctx, src, treg);
1595 ctx->src[i].sel = treg;
1596 ctx->src[i].rel = 0;
1597 }
1598 }
1599 return 0;
1600 }
1601
1602
1603 /* Tessellation shaders pass outputs to the next shader using LDS.
1604 *
1605 * LS outputs = TCS(HS) inputs
1606 * TCS(HS) outputs = TES(DS) inputs
1607 *
1608 * The LDS layout is:
1609 * - TCS inputs for patch 0
1610 * - TCS inputs for patch 1
1611 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1612 * - ...
1613 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1614 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1615 * - TCS outputs for patch 1
1616 * - Per-patch TCS outputs for patch 1
1617 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1618 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1619 * - ...
1620 *
1621 * All three shaders VS(LS), TCS, TES share the same LDS space.
1622 */
1623 /* this will return with the dw address in temp_reg.x */
1624 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1625 const struct tgsi_full_dst_register *dst,
1626 const struct tgsi_full_src_register *src,
1627 int stride_bytes_reg, int stride_bytes_chan)
1628 {
1629 struct tgsi_full_dst_register reg;
1630 ubyte *name, *index, *array_first;
1631 int r;
1632 int param;
1633 struct tgsi_shader_info *info = &ctx->info;
1634 /* Set the register description. The address computation is the same
1635 * for sources and destinations. */
1636 if (src) {
1637 reg.Register.File = src->Register.File;
1638 reg.Register.Index = src->Register.Index;
1639 reg.Register.Indirect = src->Register.Indirect;
1640 reg.Register.Dimension = src->Register.Dimension;
1641 reg.Indirect = src->Indirect;
1642 reg.Dimension = src->Dimension;
1643 reg.DimIndirect = src->DimIndirect;
1644 } else
1645 reg = *dst;
1646
1647 /* If the register is 2-dimensional (e.g. an array of vertices
1648 * in a primitive), calculate the base address of the vertex. */
1649 if (reg.Register.Dimension) {
1650 int sel, chan;
1651 if (reg.Dimension.Indirect) {
1652 unsigned addr_reg;
1653 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1654
1655 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1656 /* pull the value from index_reg */
1657 sel = addr_reg;
1658 chan = 0;
1659 } else {
1660 sel = V_SQ_ALU_SRC_LITERAL;
1661 chan = reg.Dimension.Index;
1662 }
1663
1664 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1665 temp_reg, 0,
1666 stride_bytes_reg, stride_bytes_chan,
1667 sel, chan,
1668 temp_reg, 0);
1669 if (r)
1670 return r;
1671 }
1672
1673 if (reg.Register.File == TGSI_FILE_INPUT) {
1674 name = info->input_semantic_name;
1675 index = info->input_semantic_index;
1676 array_first = info->input_array_first;
1677 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1678 name = info->output_semantic_name;
1679 index = info->output_semantic_index;
1680 array_first = info->output_array_first;
1681 } else {
1682 assert(0);
1683 return -1;
1684 }
1685 if (reg.Register.Indirect) {
1686 int addr_reg;
1687 int first;
1688 /* Add the relative address of the element. */
1689 if (reg.Indirect.ArrayID)
1690 first = array_first[reg.Indirect.ArrayID];
1691 else
1692 first = reg.Register.Index;
1693
1694 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1695
1696 /* pull the value from index_reg */
1697 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1698 temp_reg, 0,
1699 V_SQ_ALU_SRC_LITERAL, 16,
1700 addr_reg, 0,
1701 temp_reg, 0);
1702 if (r)
1703 return r;
1704
1705 param = r600_get_lds_unique_index(name[first],
1706 index[first]);
1707
1708 } else {
1709 param = r600_get_lds_unique_index(name[reg.Register.Index],
1710 index[reg.Register.Index]);
1711 }
1712
1713 /* add to base_addr - passed in temp_reg.x */
1714 if (param) {
1715 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1716 temp_reg, 0,
1717 temp_reg, 0,
1718 V_SQ_ALU_SRC_LITERAL, param * 16);
1719 if (r)
1720 return r;
1721
1722 }
1723 return 0;
1724 }
1725
1726 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1727 unsigned dst_reg)
1728 {
1729 struct r600_bytecode_alu alu;
1730 int r, i;
1731
1732 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1733 ctx->bc->force_add_cf = 1;
1734 for (i = 1; i < 4; i++) {
1735 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1736 temp_reg, i,
1737 temp_reg, 0,
1738 V_SQ_ALU_SRC_LITERAL, 4 * i);
1739 }
1740 for (i = 0; i < 4; i++) {
1741 /* emit an LDS_READ_RET */
1742 memset(&alu, 0, sizeof(alu));
1743 alu.op = LDS_OP1_LDS_READ_RET;
1744 alu.src[0].sel = temp_reg;
1745 alu.src[0].chan = i;
1746 alu.src[1].sel = V_SQ_ALU_SRC_0;
1747 alu.src[2].sel = V_SQ_ALU_SRC_0;
1748 alu.dst.chan = 0;
1749 alu.is_lds_idx_op = true;
1750 alu.last = 1;
1751 r = r600_bytecode_add_alu(ctx->bc, &alu);
1752 if (r)
1753 return r;
1754 }
1755 for (i = 0; i < 4; i++) {
1756 /* then read from LDS_OQ_A_POP */
1757 memset(&alu, 0, sizeof(alu));
1758
1759 alu.op = ALU_OP1_MOV;
1760 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1761 alu.src[0].chan = 0;
1762 alu.dst.sel = dst_reg;
1763 alu.dst.chan = i;
1764 alu.dst.write = 1;
1765 alu.last = 1;
1766 r = r600_bytecode_add_alu(ctx->bc, &alu);
1767 if (r)
1768 return r;
1769 }
1770 return 0;
1771 }
1772
1773 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1774 {
1775 int r;
1776 unsigned temp_reg = r600_get_temp(ctx);
1777
1778 r = get_lds_offset0(ctx, 2, temp_reg,
1779 src->Register.Dimension ? false : true);
1780 if (r)
1781 return r;
1782
1783 /* the base address is now in temp.x */
1784 r = r600_get_byte_address(ctx, temp_reg,
1785 NULL, src, ctx->tess_output_info, 1);
1786 if (r)
1787 return r;
1788
1789 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1790 if (r)
1791 return r;
1792 return 0;
1793 }
1794
1795 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1796 {
1797 int r;
1798 unsigned temp_reg = r600_get_temp(ctx);
1799
1800 /* t.x = ips * r0.y */
1801 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1802 temp_reg, 0,
1803 ctx->tess_input_info, 0,
1804 0, 1);
1805
1806 if (r)
1807 return r;
1808
1809 /* the base address is now in temp.x */
1810 r = r600_get_byte_address(ctx, temp_reg,
1811 NULL, src, ctx->tess_input_info, 1);
1812 if (r)
1813 return r;
1814
1815 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1816 if (r)
1817 return r;
1818 return 0;
1819 }
1820
1821 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1822 {
1823 int r;
1824 unsigned temp_reg = r600_get_temp(ctx);
1825
1826 r = get_lds_offset0(ctx, 1, temp_reg,
1827 src->Register.Dimension ? false : true);
1828 if (r)
1829 return r;
1830 /* the base address is now in temp.x */
1831 r = r600_get_byte_address(ctx, temp_reg,
1832 NULL, src,
1833 ctx->tess_output_info, 1);
1834 if (r)
1835 return r;
1836
1837 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1838 if (r)
1839 return r;
1840 return 0;
1841 }
1842
1843 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1844 {
1845 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1846 int i;
1847
1848 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1849 struct tgsi_full_src_register *src = &inst->Src[i];
1850
1851 if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1852 int treg = r600_get_temp(ctx);
1853 fetch_tes_input(ctx, src, treg);
1854 ctx->src[i].sel = treg;
1855 ctx->src[i].rel = 0;
1856 }
1857 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1858 int treg = r600_get_temp(ctx);
1859 fetch_tcs_input(ctx, src, treg);
1860 ctx->src[i].sel = treg;
1861 ctx->src[i].rel = 0;
1862 }
1863 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1864 int treg = r600_get_temp(ctx);
1865 fetch_tcs_output(ctx, src, treg);
1866 ctx->src[i].sel = treg;
1867 ctx->src[i].rel = 0;
1868 }
1869 }
1870 return 0;
1871 }
1872
1873 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1874 {
1875 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1876 struct r600_bytecode_alu alu;
1877 int i, j, k, nconst, r;
1878
1879 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1880 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1881 nconst++;
1882 }
1883 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1884 }
1885 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1886 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1887 continue;
1888 }
1889
1890 if (ctx->src[i].rel) {
1891 int chan = inst->Src[i].Indirect.Swizzle;
1892 int treg = r600_get_temp(ctx);
1893 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1894 return r;
1895
1896 ctx->src[i].kc_bank = 0;
1897 ctx->src[i].kc_rel = 0;
1898 ctx->src[i].sel = treg;
1899 ctx->src[i].rel = 0;
1900 j--;
1901 } else if (j > 0) {
1902 int treg = r600_get_temp(ctx);
1903 for (k = 0; k < 4; k++) {
1904 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1905 alu.op = ALU_OP1_MOV;
1906 alu.src[0].sel = ctx->src[i].sel;
1907 alu.src[0].chan = k;
1908 alu.src[0].rel = ctx->src[i].rel;
1909 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1910 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1911 alu.dst.sel = treg;
1912 alu.dst.chan = k;
1913 alu.dst.write = 1;
1914 if (k == 3)
1915 alu.last = 1;
1916 r = r600_bytecode_add_alu(ctx->bc, &alu);
1917 if (r)
1918 return r;
1919 }
1920 ctx->src[i].sel = treg;
1921 ctx->src[i].rel =0;
1922 j--;
1923 }
1924 }
1925 return 0;
1926 }
1927
1928 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1929 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1930 {
1931 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1932 struct r600_bytecode_alu alu;
1933 int i, j, k, nliteral, r;
1934
1935 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1936 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1937 nliteral++;
1938 }
1939 }
1940 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1941 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1942 int treg = r600_get_temp(ctx);
1943 for (k = 0; k < 4; k++) {
1944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1945 alu.op = ALU_OP1_MOV;
1946 alu.src[0].sel = ctx->src[i].sel;
1947 alu.src[0].chan = k;
1948 alu.src[0].value = ctx->src[i].value[k];
1949 alu.dst.sel = treg;
1950 alu.dst.chan = k;
1951 alu.dst.write = 1;
1952 if (k == 3)
1953 alu.last = 1;
1954 r = r600_bytecode_add_alu(ctx->bc, &alu);
1955 if (r)
1956 return r;
1957 }
1958 ctx->src[i].sel = treg;
1959 j--;
1960 }
1961 }
1962 return 0;
1963 }
1964
1965 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1966 {
1967 int i, r, count = ctx->shader->ninput;
1968
1969 for (i = 0; i < count; i++) {
1970 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1971 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1972 if (r)
1973 return r;
1974 }
1975 }
1976 return 0;
1977 }
1978
1979 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1980 int stream, unsigned *stream_item_size)
1981 {
1982 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1983 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1984 int i, j, r;
1985
1986 /* Sanity checking. */
1987 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1988 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1989 r = -EINVAL;
1990 goto out_err;
1991 }
1992 for (i = 0; i < so->num_outputs; i++) {
1993 if (so->output[i].output_buffer >= 4) {
1994 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1995 so->output[i].output_buffer);
1996 r = -EINVAL;
1997 goto out_err;
1998 }
1999 }
2000
2001 /* Initialize locations where the outputs are stored. */
2002 for (i = 0; i < so->num_outputs; i++) {
2003
2004 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2005 start_comp[i] = so->output[i].start_component;
2006 /* Lower outputs with dst_offset < start_component.
2007 *
2008 * We can only output 4D vectors with a write mask, e.g. we can
2009 * only output the W component at offset 3, etc. If we want
2010 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2011 * to move it to X and output X. */
2012 if (so->output[i].dst_offset < so->output[i].start_component) {
2013 unsigned tmp = r600_get_temp(ctx);
2014
2015 for (j = 0; j < so->output[i].num_components; j++) {
2016 struct r600_bytecode_alu alu;
2017 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2018 alu.op = ALU_OP1_MOV;
2019 alu.src[0].sel = so_gpr[i];
2020 alu.src[0].chan = so->output[i].start_component + j;
2021
2022 alu.dst.sel = tmp;
2023 alu.dst.chan = j;
2024 alu.dst.write = 1;
2025 if (j == so->output[i].num_components - 1)
2026 alu.last = 1;
2027 r = r600_bytecode_add_alu(ctx->bc, &alu);
2028 if (r)
2029 return r;
2030 }
2031 start_comp[i] = 0;
2032 so_gpr[i] = tmp;
2033 }
2034 }
2035
2036 /* Write outputs to buffers. */
2037 for (i = 0; i < so->num_outputs; i++) {
2038 struct r600_bytecode_output output;
2039
2040 if (stream != -1 && stream != so->output[i].output_buffer)
2041 continue;
2042
2043 memset(&output, 0, sizeof(struct r600_bytecode_output));
2044 output.gpr = so_gpr[i];
2045 output.elem_size = so->output[i].num_components - 1;
2046 if (output.elem_size == 2)
2047 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2048 output.array_base = so->output[i].dst_offset - start_comp[i];
2049 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2050 output.burst_count = 1;
2051 /* array_size is an upper limit for the burst_count
2052 * with MEM_STREAM instructions */
2053 output.array_size = 0xFFF;
2054 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2055
2056 if (ctx->bc->chip_class >= EVERGREEN) {
2057 switch (so->output[i].output_buffer) {
2058 case 0:
2059 output.op = CF_OP_MEM_STREAM0_BUF0;
2060 break;
2061 case 1:
2062 output.op = CF_OP_MEM_STREAM0_BUF1;
2063 break;
2064 case 2:
2065 output.op = CF_OP_MEM_STREAM0_BUF2;
2066 break;
2067 case 3:
2068 output.op = CF_OP_MEM_STREAM0_BUF3;
2069 break;
2070 }
2071 output.op += so->output[i].stream * 4;
2072 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2073 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2074 } else {
2075 switch (so->output[i].output_buffer) {
2076 case 0:
2077 output.op = CF_OP_MEM_STREAM0;
2078 break;
2079 case 1:
2080 output.op = CF_OP_MEM_STREAM1;
2081 break;
2082 case 2:
2083 output.op = CF_OP_MEM_STREAM2;
2084 break;
2085 case 3:
2086 output.op = CF_OP_MEM_STREAM3;
2087 break;
2088 }
2089 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2090 }
2091 r = r600_bytecode_add_output(ctx->bc, &output);
2092 if (r)
2093 goto out_err;
2094 }
2095 return 0;
2096 out_err:
2097 return r;
2098 }
2099
2100 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2101 {
2102 struct r600_bytecode_alu alu;
2103 unsigned reg;
2104
2105 if (!ctx->shader->vs_out_edgeflag)
2106 return;
2107
2108 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2109
2110 /* clamp(x, 0, 1) */
2111 memset(&alu, 0, sizeof(alu));
2112 alu.op = ALU_OP1_MOV;
2113 alu.src[0].sel = reg;
2114 alu.dst.sel = reg;
2115 alu.dst.write = 1;
2116 alu.dst.clamp = 1;
2117 alu.last = 1;
2118 r600_bytecode_add_alu(ctx->bc, &alu);
2119
2120 memset(&alu, 0, sizeof(alu));
2121 alu.op = ALU_OP1_FLT_TO_INT;
2122 alu.src[0].sel = reg;
2123 alu.dst.sel = reg;
2124 alu.dst.write = 1;
2125 alu.last = 1;
2126 r600_bytecode_add_alu(ctx->bc, &alu);
2127 }
2128
2129 static int generate_gs_copy_shader(struct r600_context *rctx,
2130 struct r600_pipe_shader *gs,
2131 struct pipe_stream_output_info *so)
2132 {
2133 struct r600_shader_ctx ctx = {};
2134 struct r600_shader *gs_shader = &gs->shader;
2135 struct r600_pipe_shader *cshader;
2136 int ocnt = gs_shader->noutput;
2137 struct r600_bytecode_alu alu;
2138 struct r600_bytecode_vtx vtx;
2139 struct r600_bytecode_output output;
2140 struct r600_bytecode_cf *cf_jump, *cf_pop,
2141 *last_exp_pos = NULL, *last_exp_param = NULL;
2142 int i, j, next_clip_pos = 61, next_param = 0;
2143 int ring;
2144 bool only_ring_0 = true;
2145 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2146 if (!cshader)
2147 return 0;
2148
2149 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2150 sizeof(struct r600_shader_io));
2151
2152 cshader->shader.noutput = ocnt;
2153
2154 ctx.shader = &cshader->shader;
2155 ctx.bc = &ctx.shader->bc;
2156 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
2157
2158 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2159 rctx->screen->has_compressed_msaa_texturing);
2160
2161 ctx.bc->isa = rctx->isa;
2162
2163 cf_jump = NULL;
2164 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2165
2166 /* R0.x = R0.x & 0x3fffffff */
2167 memset(&alu, 0, sizeof(alu));
2168 alu.op = ALU_OP2_AND_INT;
2169 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2170 alu.src[1].value = 0x3fffffff;
2171 alu.dst.write = 1;
2172 r600_bytecode_add_alu(ctx.bc, &alu);
2173
2174 /* R0.y = R0.x >> 30 */
2175 memset(&alu, 0, sizeof(alu));
2176 alu.op = ALU_OP2_LSHR_INT;
2177 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2178 alu.src[1].value = 0x1e;
2179 alu.dst.chan = 1;
2180 alu.dst.write = 1;
2181 alu.last = 1;
2182 r600_bytecode_add_alu(ctx.bc, &alu);
2183
2184 /* fetch vertex data from GSVS ring */
2185 for (i = 0; i < ocnt; ++i) {
2186 struct r600_shader_io *out = &ctx.shader->output[i];
2187
2188 out->gpr = i + 1;
2189 out->ring_offset = i * 16;
2190
2191 memset(&vtx, 0, sizeof(vtx));
2192 vtx.op = FETCH_OP_VFETCH;
2193 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2194 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2195 vtx.mega_fetch_count = 16;
2196 vtx.offset = out->ring_offset;
2197 vtx.dst_gpr = out->gpr;
2198 vtx.src_gpr = 0;
2199 vtx.dst_sel_x = 0;
2200 vtx.dst_sel_y = 1;
2201 vtx.dst_sel_z = 2;
2202 vtx.dst_sel_w = 3;
2203 if (rctx->b.chip_class >= EVERGREEN) {
2204 vtx.use_const_fields = 1;
2205 } else {
2206 vtx.data_format = FMT_32_32_32_32_FLOAT;
2207 }
2208
2209 r600_bytecode_add_vtx(ctx.bc, &vtx);
2210 }
2211 ctx.temp_reg = i + 1;
2212 for (ring = 3; ring >= 0; --ring) {
2213 bool enabled = false;
2214 for (i = 0; i < so->num_outputs; i++) {
2215 if (so->output[i].stream == ring) {
2216 enabled = true;
2217 if (ring > 0)
2218 only_ring_0 = false;
2219 break;
2220 }
2221 }
2222 if (ring != 0 && !enabled) {
2223 cshader->shader.ring_item_sizes[ring] = 0;
2224 continue;
2225 }
2226
2227 if (cf_jump) {
2228 // Patch up jump label
2229 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2230 cf_pop = ctx.bc->cf_last;
2231
2232 cf_jump->cf_addr = cf_pop->id + 2;
2233 cf_jump->pop_count = 1;
2234 cf_pop->cf_addr = cf_pop->id + 2;
2235 cf_pop->pop_count = 1;
2236 }
2237
2238 /* PRED_SETE_INT __, R0.y, ring */
2239 memset(&alu, 0, sizeof(alu));
2240 alu.op = ALU_OP2_PRED_SETE_INT;
2241 alu.src[0].chan = 1;
2242 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2243 alu.src[1].value = ring;
2244 alu.execute_mask = 1;
2245 alu.update_pred = 1;
2246 alu.last = 1;
2247 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2248
2249 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2250 cf_jump = ctx.bc->cf_last;
2251
2252 if (enabled)
2253 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2254 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2255 }
2256
2257 /* bc adds nops - copy it */
2258 if (ctx.bc->chip_class == R600) {
2259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2260 alu.op = ALU_OP0_NOP;
2261 alu.last = 1;
2262 r600_bytecode_add_alu(ctx.bc, &alu);
2263
2264 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2265 }
2266
2267 /* export vertex data */
2268 /* XXX factor out common code with r600_shader_from_tgsi ? */
2269 for (i = 0; i < ocnt; ++i) {
2270 struct r600_shader_io *out = &ctx.shader->output[i];
2271 bool instream0 = true;
2272 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2273 continue;
2274
2275 for (j = 0; j < so->num_outputs; j++) {
2276 if (so->output[j].register_index == i) {
2277 if (so->output[j].stream == 0)
2278 break;
2279 if (so->output[j].stream > 0)
2280 instream0 = false;
2281 }
2282 }
2283 if (!instream0)
2284 continue;
2285 memset(&output, 0, sizeof(output));
2286 output.gpr = out->gpr;
2287 output.elem_size = 3;
2288 output.swizzle_x = 0;
2289 output.swizzle_y = 1;
2290 output.swizzle_z = 2;
2291 output.swizzle_w = 3;
2292 output.burst_count = 1;
2293 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2294 output.op = CF_OP_EXPORT;
2295 switch (out->name) {
2296 case TGSI_SEMANTIC_POSITION:
2297 output.array_base = 60;
2298 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2299 break;
2300
2301 case TGSI_SEMANTIC_PSIZE:
2302 output.array_base = 61;
2303 if (next_clip_pos == 61)
2304 next_clip_pos = 62;
2305 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2306 output.swizzle_y = 7;
2307 output.swizzle_z = 7;
2308 output.swizzle_w = 7;
2309 ctx.shader->vs_out_misc_write = 1;
2310 ctx.shader->vs_out_point_size = 1;
2311 break;
2312 case TGSI_SEMANTIC_LAYER:
2313 if (out->spi_sid) {
2314 /* duplicate it as PARAM to pass to the pixel shader */
2315 output.array_base = next_param++;
2316 r600_bytecode_add_output(ctx.bc, &output);
2317 last_exp_param = ctx.bc->cf_last;
2318 }
2319 output.array_base = 61;
2320 if (next_clip_pos == 61)
2321 next_clip_pos = 62;
2322 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2323 output.swizzle_x = 7;
2324 output.swizzle_y = 7;
2325 output.swizzle_z = 0;
2326 output.swizzle_w = 7;
2327 ctx.shader->vs_out_misc_write = 1;
2328 ctx.shader->vs_out_layer = 1;
2329 break;
2330 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2331 if (out->spi_sid) {
2332 /* duplicate it as PARAM to pass to the pixel shader */
2333 output.array_base = next_param++;
2334 r600_bytecode_add_output(ctx.bc, &output);
2335 last_exp_param = ctx.bc->cf_last;
2336 }
2337 output.array_base = 61;
2338 if (next_clip_pos == 61)
2339 next_clip_pos = 62;
2340 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2341 ctx.shader->vs_out_misc_write = 1;
2342 ctx.shader->vs_out_viewport = 1;
2343 output.swizzle_x = 7;
2344 output.swizzle_y = 7;
2345 output.swizzle_z = 7;
2346 output.swizzle_w = 0;
2347 break;
2348 case TGSI_SEMANTIC_CLIPDIST:
2349 /* spi_sid is 0 for clipdistance outputs that were generated
2350 * for clipvertex - we don't need to pass them to PS */
2351 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2352 if (out->spi_sid) {
2353 /* duplicate it as PARAM to pass to the pixel shader */
2354 output.array_base = next_param++;
2355 r600_bytecode_add_output(ctx.bc, &output);
2356 last_exp_param = ctx.bc->cf_last;
2357 }
2358 output.array_base = next_clip_pos++;
2359 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2360 break;
2361 case TGSI_SEMANTIC_FOG:
2362 output.swizzle_y = 4; /* 0 */
2363 output.swizzle_z = 4; /* 0 */
2364 output.swizzle_w = 5; /* 1 */
2365 break;
2366 default:
2367 output.array_base = next_param++;
2368 break;
2369 }
2370 r600_bytecode_add_output(ctx.bc, &output);
2371 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2372 last_exp_param = ctx.bc->cf_last;
2373 else
2374 last_exp_pos = ctx.bc->cf_last;
2375 }
2376
2377 if (!last_exp_pos) {
2378 memset(&output, 0, sizeof(output));
2379 output.gpr = 0;
2380 output.elem_size = 3;
2381 output.swizzle_x = 7;
2382 output.swizzle_y = 7;
2383 output.swizzle_z = 7;
2384 output.swizzle_w = 7;
2385 output.burst_count = 1;
2386 output.type = 2;
2387 output.op = CF_OP_EXPORT;
2388 output.array_base = 60;
2389 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2390 r600_bytecode_add_output(ctx.bc, &output);
2391 last_exp_pos = ctx.bc->cf_last;
2392 }
2393
2394 if (!last_exp_param) {
2395 memset(&output, 0, sizeof(output));
2396 output.gpr = 0;
2397 output.elem_size = 3;
2398 output.swizzle_x = 7;
2399 output.swizzle_y = 7;
2400 output.swizzle_z = 7;
2401 output.swizzle_w = 7;
2402 output.burst_count = 1;
2403 output.type = 2;
2404 output.op = CF_OP_EXPORT;
2405 output.array_base = next_param++;
2406 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2407 r600_bytecode_add_output(ctx.bc, &output);
2408 last_exp_param = ctx.bc->cf_last;
2409 }
2410
2411 last_exp_pos->op = CF_OP_EXPORT_DONE;
2412 last_exp_param->op = CF_OP_EXPORT_DONE;
2413
2414 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2415 cf_pop = ctx.bc->cf_last;
2416
2417 cf_jump->cf_addr = cf_pop->id + 2;
2418 cf_jump->pop_count = 1;
2419 cf_pop->cf_addr = cf_pop->id + 2;
2420 cf_pop->pop_count = 1;
2421
2422 if (ctx.bc->chip_class == CAYMAN)
2423 cm_bytecode_add_cf_end(ctx.bc);
2424 else {
2425 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2426 ctx.bc->cf_last->end_of_program = 1;
2427 }
2428
2429 gs->gs_copy_shader = cshader;
2430 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2431
2432 ctx.bc->nstack = 1;
2433
2434 return r600_bytecode_build(ctx.bc);
2435 }
2436
2437 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2438 {
2439 if (ind) {
2440 struct r600_bytecode_alu alu;
2441 int r;
2442
2443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2444 alu.op = ALU_OP2_ADD_INT;
2445 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2446 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2447 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2448 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2449 alu.dst.write = 1;
2450 alu.last = 1;
2451 r = r600_bytecode_add_alu(ctx->bc, &alu);
2452 if (r)
2453 return r;
2454 }
2455 return 0;
2456 }
2457
2458 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2459 {
2460 struct r600_bytecode_output output;
2461 int i, k, ring_offset;
2462 int effective_stream = stream == -1 ? 0 : stream;
2463 int idx = 0;
2464
2465 for (i = 0; i < ctx->shader->noutput; i++) {
2466 if (ctx->gs_for_vs) {
2467 /* for ES we need to lookup corresponding ring offset expected by GS
2468 * (map this output to GS input by name and sid) */
2469 /* FIXME precompute offsets */
2470 ring_offset = -1;
2471 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2472 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2473 struct r600_shader_io *out = &ctx->shader->output[i];
2474 if (in->name == out->name && in->sid == out->sid)
2475 ring_offset = in->ring_offset;
2476 }
2477
2478 if (ring_offset == -1)
2479 continue;
2480 } else {
2481 ring_offset = idx * 16;
2482 idx++;
2483 }
2484
2485 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2486 continue;
2487 /* next_ring_offset after parsing input decls contains total size of
2488 * single vertex data, gs_next_vertex - current vertex index */
2489 if (!ind)
2490 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2491
2492 memset(&output, 0, sizeof(struct r600_bytecode_output));
2493 output.gpr = ctx->shader->output[i].gpr;
2494 output.elem_size = 3;
2495 output.comp_mask = 0xF;
2496 output.burst_count = 1;
2497
2498 if (ind)
2499 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2500 else
2501 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2502
2503 switch (stream) {
2504 default:
2505 case 0:
2506 output.op = CF_OP_MEM_RING; break;
2507 case 1:
2508 output.op = CF_OP_MEM_RING1; break;
2509 case 2:
2510 output.op = CF_OP_MEM_RING2; break;
2511 case 3:
2512 output.op = CF_OP_MEM_RING3; break;
2513 }
2514
2515 if (ind) {
2516 output.array_base = ring_offset >> 2; /* in dwords */
2517 output.array_size = 0xfff;
2518 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2519 } else
2520 output.array_base = ring_offset >> 2; /* in dwords */
2521 r600_bytecode_add_output(ctx->bc, &output);
2522 }
2523
2524 ++ctx->gs_next_vertex;
2525 return 0;
2526 }
2527
2528
2529 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2530 {
2531 int r;
2532 struct r600_bytecode_vtx vtx;
2533 int temp_val = ctx->temp_reg;
2534 /* need to store the TCS output somewhere */
2535 r = single_alu_op2(ctx, ALU_OP1_MOV,
2536 temp_val, 0,
2537 V_SQ_ALU_SRC_LITERAL, 0,
2538 0, 0);
2539 if (r)
2540 return r;
2541
2542 /* used by VS/TCS */
2543 if (ctx->tess_input_info) {
2544 /* fetch tcs input values into resv space */
2545 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2546 vtx.op = FETCH_OP_VFETCH;
2547 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2548 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2549 vtx.mega_fetch_count = 16;
2550 vtx.data_format = FMT_32_32_32_32;
2551 vtx.num_format_all = 2;
2552 vtx.format_comp_all = 1;
2553 vtx.use_const_fields = 0;
2554 vtx.endian = r600_endian_swap(32);
2555 vtx.srf_mode_all = 1;
2556 vtx.offset = 0;
2557 vtx.dst_gpr = ctx->tess_input_info;
2558 vtx.dst_sel_x = 0;
2559 vtx.dst_sel_y = 1;
2560 vtx.dst_sel_z = 2;
2561 vtx.dst_sel_w = 3;
2562 vtx.src_gpr = temp_val;
2563 vtx.src_sel_x = 0;
2564
2565 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2566 if (r)
2567 return r;
2568 }
2569
2570 /* used by TCS/TES */
2571 if (ctx->tess_output_info) {
2572 /* fetch tcs output values into resv space */
2573 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2574 vtx.op = FETCH_OP_VFETCH;
2575 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2576 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2577 vtx.mega_fetch_count = 16;
2578 vtx.data_format = FMT_32_32_32_32;
2579 vtx.num_format_all = 2;
2580 vtx.format_comp_all = 1;
2581 vtx.use_const_fields = 0;
2582 vtx.endian = r600_endian_swap(32);
2583 vtx.srf_mode_all = 1;
2584 vtx.offset = 16;
2585 vtx.dst_gpr = ctx->tess_output_info;
2586 vtx.dst_sel_x = 0;
2587 vtx.dst_sel_y = 1;
2588 vtx.dst_sel_z = 2;
2589 vtx.dst_sel_w = 3;
2590 vtx.src_gpr = temp_val;
2591 vtx.src_sel_x = 0;
2592
2593 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2594 if (r)
2595 return r;
2596 }
2597 return 0;
2598 }
2599
2600 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2601 {
2602 int i, j, r;
2603 int temp_reg;
2604
2605 /* fetch tcs input values into input_vals */
2606 ctx->tess_input_info = r600_get_temp(ctx);
2607 ctx->tess_output_info = 0;
2608 r = r600_fetch_tess_io_info(ctx);
2609 if (r)
2610 return r;
2611
2612 temp_reg = r600_get_temp(ctx);
2613 /* dst reg contains LDS address stride * idx */
2614 /* MUL vertexID, vertex_dw_stride */
2615 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2616 temp_reg, 0,
2617 ctx->tess_input_info, 1,
2618 0, 1); /* rel id in r0.y? */
2619 if (r)
2620 return r;
2621
2622 for (i = 0; i < ctx->shader->noutput; i++) {
2623 struct r600_bytecode_alu alu;
2624 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2625
2626 if (param) {
2627 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2628 temp_reg, 1,
2629 temp_reg, 0,
2630 V_SQ_ALU_SRC_LITERAL, param * 16);
2631 if (r)
2632 return r;
2633 }
2634
2635 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2636 temp_reg, 2,
2637 temp_reg, param ? 1 : 0,
2638 V_SQ_ALU_SRC_LITERAL, 8);
2639 if (r)
2640 return r;
2641
2642
2643 for (j = 0; j < 2; j++) {
2644 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2646 alu.op = LDS_OP3_LDS_WRITE_REL;
2647 alu.src[0].sel = temp_reg;
2648 alu.src[0].chan = chan;
2649 alu.src[1].sel = ctx->shader->output[i].gpr;
2650 alu.src[1].chan = j * 2;
2651 alu.src[2].sel = ctx->shader->output[i].gpr;
2652 alu.src[2].chan = (j * 2) + 1;
2653 alu.last = 1;
2654 alu.dst.chan = 0;
2655 alu.lds_idx = 1;
2656 alu.is_lds_idx_op = true;
2657 r = r600_bytecode_add_alu(ctx->bc, &alu);
2658 if (r)
2659 return r;
2660 }
2661 }
2662 return 0;
2663 }
2664
2665 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2666 {
2667 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2668 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2669 int i, r, lasti;
2670 int temp_reg = r600_get_temp(ctx);
2671 struct r600_bytecode_alu alu;
2672 unsigned write_mask = dst->Register.WriteMask;
2673
2674 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2675 return 0;
2676
2677 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2678 if (r)
2679 return r;
2680
2681 /* the base address is now in temp.x */
2682 r = r600_get_byte_address(ctx, temp_reg,
2683 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2684 if (r)
2685 return r;
2686
2687 /* LDS write */
2688 lasti = tgsi_last_instruction(write_mask);
2689 for (i = 1; i <= lasti; i++) {
2690
2691 if (!(write_mask & (1 << i)))
2692 continue;
2693 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2694 temp_reg, i,
2695 temp_reg, 0,
2696 V_SQ_ALU_SRC_LITERAL, 4 * i);
2697 if (r)
2698 return r;
2699 }
2700
2701 for (i = 0; i <= lasti; i++) {
2702 if (!(write_mask & (1 << i)))
2703 continue;
2704
2705 if ((i == 0 && ((write_mask & 3) == 3)) ||
2706 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2708 alu.op = LDS_OP3_LDS_WRITE_REL;
2709 alu.src[0].sel = temp_reg;
2710 alu.src[0].chan = i;
2711
2712 alu.src[1].sel = dst->Register.Index;
2713 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2714 alu.src[1].chan = i;
2715
2716 alu.src[2].sel = dst->Register.Index;
2717 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2718 alu.src[2].chan = i + 1;
2719 alu.lds_idx = 1;
2720 alu.dst.chan = 0;
2721 alu.last = 1;
2722 alu.is_lds_idx_op = true;
2723 r = r600_bytecode_add_alu(ctx->bc, &alu);
2724 if (r)
2725 return r;
2726 i += 1;
2727 continue;
2728 }
2729 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2730 alu.op = LDS_OP2_LDS_WRITE;
2731 alu.src[0].sel = temp_reg;
2732 alu.src[0].chan = i;
2733
2734 alu.src[1].sel = dst->Register.Index;
2735 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2736 alu.src[1].chan = i;
2737
2738 alu.src[2].sel = V_SQ_ALU_SRC_0;
2739 alu.dst.chan = 0;
2740 alu.last = 1;
2741 alu.is_lds_idx_op = true;
2742 r = r600_bytecode_add_alu(ctx->bc, &alu);
2743 if (r)
2744 return r;
2745 }
2746 return 0;
2747 }
2748
2749 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2750 int output_idx)
2751 {
2752 int param;
2753 unsigned temp_reg = r600_get_temp(ctx);
2754 unsigned name = ctx->shader->output[output_idx].name;
2755 int dreg = ctx->shader->output[output_idx].gpr;
2756 int r;
2757
2758 param = r600_get_lds_unique_index(name, 0);
2759 r = get_lds_offset0(ctx, 1, temp_reg, true);
2760 if (r)
2761 return r;
2762
2763 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2764 temp_reg, 0,
2765 temp_reg, 0,
2766 V_SQ_ALU_SRC_LITERAL, param * 16);
2767 if (r)
2768 return r;
2769
2770 do_lds_fetch_values(ctx, temp_reg, dreg);
2771 return 0;
2772 }
2773
2774 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2775 {
2776 int i;
2777 int stride, outer_comps, inner_comps;
2778 int tessinner_idx = -1, tessouter_idx = -1;
2779 int r;
2780 int temp_reg = r600_get_temp(ctx);
2781 int treg[3] = {-1, -1, -1};
2782 struct r600_bytecode_alu alu;
2783 struct r600_bytecode_cf *cf_jump, *cf_pop;
2784
2785 /* only execute factor emission for invocation 0 */
2786 /* PRED_SETE_INT __, R0.x, 0 */
2787 memset(&alu, 0, sizeof(alu));
2788 alu.op = ALU_OP2_PRED_SETE_INT;
2789 alu.src[0].chan = 2;
2790 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2791 alu.execute_mask = 1;
2792 alu.update_pred = 1;
2793 alu.last = 1;
2794 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2795
2796 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2797 cf_jump = ctx->bc->cf_last;
2798
2799 treg[0] = r600_get_temp(ctx);
2800 switch (ctx->shader->tcs_prim_mode) {
2801 case PIPE_PRIM_LINES:
2802 stride = 8; /* 2 dwords, 1 vec2 store */
2803 outer_comps = 2;
2804 inner_comps = 0;
2805 break;
2806 case PIPE_PRIM_TRIANGLES:
2807 stride = 16; /* 4 dwords, 1 vec4 store */
2808 outer_comps = 3;
2809 inner_comps = 1;
2810 treg[1] = r600_get_temp(ctx);
2811 break;
2812 case PIPE_PRIM_QUADS:
2813 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2814 outer_comps = 4;
2815 inner_comps = 2;
2816 treg[1] = r600_get_temp(ctx);
2817 treg[2] = r600_get_temp(ctx);
2818 break;
2819 default:
2820 assert(0);
2821 return -1;
2822 }
2823
2824 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2825 /* TF_WRITE takes index in R.x, value in R.y */
2826 for (i = 0; i < ctx->shader->noutput; i++) {
2827 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2828 tessinner_idx = i;
2829 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2830 tessouter_idx = i;
2831 }
2832
2833 if (tessouter_idx == -1)
2834 return -1;
2835
2836 if (tessinner_idx == -1 && inner_comps)
2837 return -1;
2838
2839 if (tessouter_idx != -1) {
2840 r = r600_tess_factor_read(ctx, tessouter_idx);
2841 if (r)
2842 return r;
2843 }
2844
2845 if (tessinner_idx != -1) {
2846 r = r600_tess_factor_read(ctx, tessinner_idx);
2847 if (r)
2848 return r;
2849 }
2850
2851 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2852 /* r.x = relpatchid(r0.y) * tf_stride */
2853
2854 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2855 /* add incoming r0.w to it: t.x = t.x + r0.w */
2856 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2857 temp_reg, 0,
2858 0, 1,
2859 V_SQ_ALU_SRC_LITERAL, stride,
2860 0, 3);
2861 if (r)
2862 return r;
2863
2864 for (i = 0; i < outer_comps + inner_comps; i++) {
2865 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2866 int out_comp = i >= outer_comps ? i - outer_comps : i;
2867
2868 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2869 treg[i / 2], (2 * (i % 2)),
2870 temp_reg, 0,
2871 V_SQ_ALU_SRC_LITERAL, 4 * i);
2872 if (r)
2873 return r;
2874 r = single_alu_op2(ctx, ALU_OP1_MOV,
2875 treg[i / 2], 1 + (2 * (i%2)),
2876 ctx->shader->output[out_idx].gpr, out_comp,
2877 0, 0);
2878 if (r)
2879 return r;
2880 }
2881 for (i = 0; i < outer_comps + inner_comps; i++) {
2882 struct r600_bytecode_gds gds;
2883
2884 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2885 gds.src_gpr = treg[i / 2];
2886 gds.src_sel_x = 2 * (i % 2);
2887 gds.src_sel_y = 1 + (2 * (i % 2));
2888 gds.src_sel_z = 4;
2889 gds.dst_sel_x = 7;
2890 gds.dst_sel_y = 7;
2891 gds.dst_sel_z = 7;
2892 gds.dst_sel_w = 7;
2893 gds.op = FETCH_OP_TF_WRITE;
2894 r = r600_bytecode_add_gds(ctx->bc, &gds);
2895 if (r)
2896 return r;
2897 }
2898
2899 // Patch up jump label
2900 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2901 cf_pop = ctx->bc->cf_last;
2902
2903 cf_jump->cf_addr = cf_pop->id + 2;
2904 cf_jump->pop_count = 1;
2905 cf_pop->cf_addr = cf_pop->id + 2;
2906 cf_pop->pop_count = 1;
2907
2908 return 0;
2909 }
2910
2911 static int r600_shader_from_tgsi(struct r600_context *rctx,
2912 struct r600_pipe_shader *pipeshader,
2913 union r600_shader_key key)
2914 {
2915 struct r600_screen *rscreen = rctx->screen;
2916 struct r600_shader *shader = &pipeshader->shader;
2917 struct tgsi_token *tokens = pipeshader->selector->tokens;
2918 struct pipe_stream_output_info so = pipeshader->selector->so;
2919 struct tgsi_full_immediate *immediate;
2920 struct r600_shader_ctx ctx;
2921 struct r600_bytecode_output output[32];
2922 unsigned output_done, noutput;
2923 unsigned opcode;
2924 int i, j, k, r = 0;
2925 int next_param_base = 0, next_clip_base;
2926 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2927 /* Declarations used by llvm code */
2928 bool use_llvm = false;
2929 bool indirect_gprs;
2930 bool ring_outputs = false;
2931 bool lds_outputs = false;
2932 bool lds_inputs = false;
2933 bool pos_emitted = false;
2934
2935 #ifdef R600_USE_LLVM
2936 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
2937 #endif
2938 ctx.bc = &shader->bc;
2939 ctx.shader = shader;
2940 ctx.native_integers = true;
2941
2942
2943 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2944 rscreen->has_compressed_msaa_texturing);
2945 ctx.tokens = tokens;
2946 tgsi_scan_shader(tokens, &ctx.info);
2947 shader->indirect_files = ctx.info.indirect_files;
2948
2949 shader->uses_doubles = ctx.info.uses_doubles;
2950
2951 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2952 tgsi_parse_init(&ctx.parse, tokens);
2953 ctx.type = ctx.info.processor;
2954 shader->processor_type = ctx.type;
2955 ctx.bc->type = shader->processor_type;
2956
2957 switch (ctx.type) {
2958 case TGSI_PROCESSOR_VERTEX:
2959 shader->vs_as_gs_a = key.vs.as_gs_a;
2960 shader->vs_as_es = key.vs.as_es;
2961 shader->vs_as_ls = key.vs.as_ls;
2962 if (shader->vs_as_es)
2963 ring_outputs = true;
2964 if (shader->vs_as_ls)
2965 lds_outputs = true;
2966 break;
2967 case TGSI_PROCESSOR_GEOMETRY:
2968 ring_outputs = true;
2969 break;
2970 case TGSI_PROCESSOR_TESS_CTRL:
2971 shader->tcs_prim_mode = key.tcs.prim_mode;
2972 lds_outputs = true;
2973 lds_inputs = true;
2974 break;
2975 case TGSI_PROCESSOR_TESS_EVAL:
2976 shader->tes_as_es = key.tes.as_es;
2977 lds_inputs = true;
2978 if (shader->tes_as_es)
2979 ring_outputs = true;
2980 break;
2981 case TGSI_PROCESSOR_FRAGMENT:
2982 shader->two_side = key.ps.color_two_side;
2983 break;
2984 default:
2985 break;
2986 }
2987
2988 if (shader->vs_as_es || shader->tes_as_es) {
2989 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
2990 } else {
2991 ctx.gs_for_vs = NULL;
2992 }
2993
2994 ctx.next_ring_offset = 0;
2995 ctx.gs_out_ring_offset = 0;
2996 ctx.gs_next_vertex = 0;
2997 ctx.gs_stream_output_info = &so;
2998
2999 ctx.face_gpr = -1;
3000 ctx.fixed_pt_position_gpr = -1;
3001 ctx.fragcoord_input = -1;
3002 ctx.colors_used = 0;
3003 ctx.clip_vertex_write = 0;
3004
3005 shader->nr_ps_color_exports = 0;
3006 shader->nr_ps_max_color_exports = 0;
3007
3008
3009 /* register allocations */
3010 /* Values [0,127] correspond to GPR[0..127].
3011 * Values [128,159] correspond to constant buffer bank 0
3012 * Values [160,191] correspond to constant buffer bank 1
3013 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3014 * Values [256,287] correspond to constant buffer bank 2 (EG)
3015 * Values [288,319] correspond to constant buffer bank 3 (EG)
3016 * Other special values are shown in the list below.
3017 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3018 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3019 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3020 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3021 * 248 SQ_ALU_SRC_0: special constant 0.0.
3022 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3023 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3024 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3025 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3026 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3027 * 254 SQ_ALU_SRC_PV: previous vector result.
3028 * 255 SQ_ALU_SRC_PS: previous scalar result.
3029 */
3030 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3031 ctx.file_offset[i] = 0;
3032 }
3033
3034 #ifdef R600_USE_LLVM
3035 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
3036 fprintf(stderr, "Warning: R600 LLVM backend does not support "
3037 "indirect adressing. Falling back to TGSI "
3038 "backend.\n");
3039 use_llvm = 0;
3040 }
3041 #endif
3042 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
3043 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3044 if (!use_llvm) {
3045 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3046 }
3047 }
3048 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
3049 if (ctx.bc->chip_class >= EVERGREEN)
3050 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3051 else
3052 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3053 }
3054 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3055 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3056 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3057 }
3058 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
3059 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3060 if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) {
3061 bool add_tesscoord = false, add_tess_inout = false;
3062 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3063 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3064 /* if we have tesscoord save one reg */
3065 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3066 add_tesscoord = true;
3067 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3068 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3069 add_tess_inout = true;
3070 }
3071 if (add_tesscoord || add_tess_inout)
3072 ctx.file_offset[TGSI_FILE_INPUT]++;
3073 if (add_tess_inout)
3074 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3075 }
3076 ctx.use_llvm = use_llvm;
3077
3078 if (use_llvm) {
3079 ctx.file_offset[TGSI_FILE_OUTPUT] =
3080 ctx.file_offset[TGSI_FILE_INPUT];
3081 } else {
3082 ctx.file_offset[TGSI_FILE_OUTPUT] =
3083 ctx.file_offset[TGSI_FILE_INPUT] +
3084 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3085 }
3086 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3087 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3088
3089 /* Outside the GPR range. This will be translated to one of the
3090 * kcache banks later. */
3091 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3092
3093 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3094 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3095 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3096 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3097 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3098
3099 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
3100 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3101 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3102 ctx.temp_reg = ctx.bc->ar_reg + 5;
3103 } else if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) {
3104 ctx.tess_input_info = 0;
3105 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3106 ctx.temp_reg = ctx.bc->ar_reg + 4;
3107 } else if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3108 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3109 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3110 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3111 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3112 ctx.temp_reg = ctx.bc->ar_reg + 7;
3113 } else {
3114 ctx.temp_reg = ctx.bc->ar_reg + 3;
3115 }
3116
3117 shader->max_arrays = 0;
3118 shader->num_arrays = 0;
3119 if (indirect_gprs) {
3120
3121 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3122 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3123 ctx.file_offset[TGSI_FILE_OUTPUT] -
3124 ctx.file_offset[TGSI_FILE_INPUT],
3125 0x0F);
3126 }
3127 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3128 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3129 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3130 ctx.file_offset[TGSI_FILE_OUTPUT],
3131 0x0F);
3132 }
3133 }
3134
3135 ctx.nliterals = 0;
3136 ctx.literals = NULL;
3137
3138 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS];
3139 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3140 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3141
3142 if (shader->vs_as_gs_a)
3143 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3144
3145 if (ctx.type == TGSI_PROCESSOR_TESS_EVAL)
3146 r600_fetch_tess_io_info(&ctx);
3147
3148 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3149 tgsi_parse_token(&ctx.parse);
3150 switch (ctx.parse.FullToken.Token.Type) {
3151 case TGSI_TOKEN_TYPE_IMMEDIATE:
3152 immediate = &ctx.parse.FullToken.FullImmediate;
3153 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3154 if(ctx.literals == NULL) {
3155 r = -ENOMEM;
3156 goto out_err;
3157 }
3158 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3159 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3160 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3161 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3162 ctx.nliterals++;
3163 break;
3164 case TGSI_TOKEN_TYPE_DECLARATION:
3165 r = tgsi_declaration(&ctx);
3166 if (r)
3167 goto out_err;
3168 break;
3169 case TGSI_TOKEN_TYPE_INSTRUCTION:
3170 case TGSI_TOKEN_TYPE_PROPERTY:
3171 break;
3172 default:
3173 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3174 r = -EINVAL;
3175 goto out_err;
3176 }
3177 }
3178
3179 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3180 shader->ring_item_sizes[1] = 0;
3181 shader->ring_item_sizes[2] = 0;
3182 shader->ring_item_sizes[3] = 0;
3183
3184 /* Process two side if needed */
3185 if (shader->two_side && ctx.colors_used) {
3186 int i, count = ctx.shader->ninput;
3187 unsigned next_lds_loc = ctx.shader->nlds;
3188
3189 /* additional inputs will be allocated right after the existing inputs,
3190 * we won't need them after the color selection, so we don't need to
3191 * reserve these gprs for the rest of the shader code and to adjust
3192 * output offsets etc. */
3193 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3194 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3195
3196 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3197 if (ctx.face_gpr == -1) {
3198 i = ctx.shader->ninput++;
3199 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3200 ctx.shader->input[i].spi_sid = 0;
3201 ctx.shader->input[i].gpr = gpr++;
3202 ctx.face_gpr = ctx.shader->input[i].gpr;
3203 }
3204
3205 for (i = 0; i < count; i++) {
3206 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3207 int ni = ctx.shader->ninput++;
3208 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3209 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3210 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3211 ctx.shader->input[ni].gpr = gpr++;
3212 // TGSI to LLVM needs to know the lds position of inputs.
3213 // Non LLVM path computes it later (in process_twoside_color)
3214 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3215 ctx.shader->input[i].back_color_input = ni;
3216 if (ctx.bc->chip_class >= EVERGREEN) {
3217 if ((r = evergreen_interp_input(&ctx, ni)))
3218 return r;
3219 }
3220 }
3221 }
3222 }
3223
3224 /* LLVM backend setup */
3225 #ifdef R600_USE_LLVM
3226 if (use_llvm) {
3227 struct radeon_llvm_context radeon_llvm_ctx;
3228 LLVMModuleRef mod;
3229 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
3230 boolean use_kill = false;
3231
3232 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
3233 radeon_llvm_ctx.type = ctx.type;
3234 radeon_llvm_ctx.two_side = shader->two_side;
3235 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
3236 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
3237 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
3238 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
3239 radeon_llvm_ctx.color_buffer_count = max_color_exports;
3240 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
3241 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
3242 radeon_llvm_ctx.stream_outputs = &so;
3243 radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
3244 radeon_llvm_ctx.has_compressed_msaa_texturing =
3245 ctx.bc->has_compressed_msaa_texturing;
3246 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
3247 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
3248 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
3249
3250 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
3251 radeon_llvm_dispose(&radeon_llvm_ctx);
3252 use_llvm = 0;
3253 fprintf(stderr, "R600 LLVM backend failed to compile "
3254 "shader. Falling back to TGSI\n");
3255 } else {
3256 ctx.file_offset[TGSI_FILE_OUTPUT] =
3257 ctx.file_offset[TGSI_FILE_INPUT];
3258 }
3259 if (use_kill)
3260 ctx.shader->uses_kill = use_kill;
3261 radeon_llvm_dispose(&radeon_llvm_ctx);
3262 }
3263 #endif
3264 /* End of LLVM backend setup */
3265
3266 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3267 shader->nr_ps_max_color_exports = 8;
3268
3269 if (!use_llvm) {
3270 if (ctx.fragcoord_input >= 0) {
3271 if (ctx.bc->chip_class == CAYMAN) {
3272 for (j = 0 ; j < 4; j++) {
3273 struct r600_bytecode_alu alu;
3274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3275 alu.op = ALU_OP1_RECIP_IEEE;
3276 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3277 alu.src[0].chan = 3;
3278
3279 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3280 alu.dst.chan = j;
3281 alu.dst.write = (j == 3);
3282 alu.last = 1;
3283 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3284 return r;
3285 }
3286 } else {
3287 struct r600_bytecode_alu alu;
3288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3289 alu.op = ALU_OP1_RECIP_IEEE;
3290 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3291 alu.src[0].chan = 3;
3292
3293 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3294 alu.dst.chan = 3;
3295 alu.dst.write = 1;
3296 alu.last = 1;
3297 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3298 return r;
3299 }
3300 }
3301
3302 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3303 struct r600_bytecode_alu alu;
3304 int r;
3305
3306 /* GS thread with no output workaround - emit a cut at start of GS */
3307 if (ctx.bc->chip_class == R600)
3308 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3309
3310 for (j = 0; j < 4; j++) {
3311 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3312 alu.op = ALU_OP1_MOV;
3313 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3314 alu.src[0].value = 0;
3315 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3316 alu.dst.write = 1;
3317 alu.last = 1;
3318 r = r600_bytecode_add_alu(ctx.bc, &alu);
3319 if (r)
3320 return r;
3321 }
3322 }
3323
3324 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
3325 r600_fetch_tess_io_info(&ctx);
3326
3327 if (shader->two_side && ctx.colors_used) {
3328 if ((r = process_twoside_color_inputs(&ctx)))
3329 return r;
3330 }
3331
3332 tgsi_parse_init(&ctx.parse, tokens);
3333 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3334 tgsi_parse_token(&ctx.parse);
3335 switch (ctx.parse.FullToken.Token.Type) {
3336 case TGSI_TOKEN_TYPE_INSTRUCTION:
3337 r = tgsi_is_supported(&ctx);
3338 if (r)
3339 goto out_err;
3340 ctx.max_driver_temp_used = 0;
3341 /* reserve first tmp for everyone */
3342 r600_get_temp(&ctx);
3343
3344 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3345 if ((r = tgsi_split_constant(&ctx)))
3346 goto out_err;
3347 if ((r = tgsi_split_literal_constant(&ctx)))
3348 goto out_err;
3349 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3350 if ((r = tgsi_split_gs_inputs(&ctx)))
3351 goto out_err;
3352 } else if (lds_inputs) {
3353 if ((r = tgsi_split_lds_inputs(&ctx)))
3354 goto out_err;
3355 }
3356 if (ctx.bc->chip_class == CAYMAN)
3357 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3358 else if (ctx.bc->chip_class >= EVERGREEN)
3359 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3360 else
3361 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3362 r = ctx.inst_info->process(&ctx);
3363 if (r)
3364 goto out_err;
3365
3366 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
3367 r = r600_store_tcs_output(&ctx);
3368 if (r)
3369 goto out_err;
3370 }
3371 break;
3372 default:
3373 break;
3374 }
3375 }
3376 }
3377
3378 /* Reset the temporary register counter. */
3379 ctx.max_driver_temp_used = 0;
3380
3381 noutput = shader->noutput;
3382
3383 if (!ring_outputs && ctx.clip_vertex_write) {
3384 unsigned clipdist_temp[2];
3385
3386 clipdist_temp[0] = r600_get_temp(&ctx);
3387 clipdist_temp[1] = r600_get_temp(&ctx);
3388
3389 /* need to convert a clipvertex write into clipdistance writes and not export
3390 the clip vertex anymore */
3391
3392 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3393 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3394 shader->output[noutput].gpr = clipdist_temp[0];
3395 noutput++;
3396 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3397 shader->output[noutput].gpr = clipdist_temp[1];
3398 noutput++;
3399
3400 /* reset spi_sid for clipvertex output to avoid confusing spi */
3401 shader->output[ctx.cv_output].spi_sid = 0;
3402
3403 shader->clip_dist_write = 0xFF;
3404
3405 for (i = 0; i < 8; i++) {
3406 int oreg = i >> 2;
3407 int ochan = i & 3;
3408
3409 for (j = 0; j < 4; j++) {
3410 struct r600_bytecode_alu alu;
3411 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3412 alu.op = ALU_OP2_DOT4;
3413 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3414 alu.src[0].chan = j;
3415
3416 alu.src[1].sel = 512 + i;
3417 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3418 alu.src[1].chan = j;
3419
3420 alu.dst.sel = clipdist_temp[oreg];
3421 alu.dst.chan = j;
3422 alu.dst.write = (j == ochan);
3423 if (j == 3)
3424 alu.last = 1;
3425 if (!use_llvm)
3426 r = r600_bytecode_add_alu(ctx.bc, &alu);
3427 if (r)
3428 return r;
3429 }
3430 }
3431 }
3432
3433 /* Add stream outputs. */
3434 if (!use_llvm && so.num_outputs) {
3435 bool emit = false;
3436 if (!lds_outputs && !ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX)
3437 emit = true;
3438 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_TESS_EVAL)
3439 emit = true;
3440 if (emit)
3441 emit_streamout(&ctx, &so, -1, NULL);
3442 }
3443 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3444 convert_edgeflag_to_int(&ctx);
3445
3446 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
3447 r600_emit_tess_factor(&ctx);
3448
3449 if (lds_outputs) {
3450 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
3451 if (ctx.shader->noutput)
3452 emit_lds_vs_writes(&ctx);
3453 }
3454 } else if (ring_outputs) {
3455 if (shader->vs_as_es || shader->tes_as_es) {
3456 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3457 ctx.gs_export_gpr_tregs[1] = -1;
3458 ctx.gs_export_gpr_tregs[2] = -1;
3459 ctx.gs_export_gpr_tregs[3] = -1;
3460
3461 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3462 }
3463 } else {
3464 /* Export output */
3465 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3466
3467 for (i = 0, j = 0; i < noutput; i++, j++) {
3468 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3469 output[j].gpr = shader->output[i].gpr;
3470 output[j].elem_size = 3;
3471 output[j].swizzle_x = 0;
3472 output[j].swizzle_y = 1;
3473 output[j].swizzle_z = 2;
3474 output[j].swizzle_w = 3;
3475 output[j].burst_count = 1;
3476 output[j].type = -1;
3477 output[j].op = CF_OP_EXPORT;
3478 switch (ctx.type) {
3479 case TGSI_PROCESSOR_VERTEX:
3480 case TGSI_PROCESSOR_TESS_EVAL:
3481 switch (shader->output[i].name) {
3482 case TGSI_SEMANTIC_POSITION:
3483 output[j].array_base = 60;
3484 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3485 pos_emitted = true;
3486 break;
3487
3488 case TGSI_SEMANTIC_PSIZE:
3489 output[j].array_base = 61;
3490 output[j].swizzle_y = 7;
3491 output[j].swizzle_z = 7;
3492 output[j].swizzle_w = 7;
3493 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3494 pos_emitted = true;
3495 break;
3496 case TGSI_SEMANTIC_EDGEFLAG:
3497 output[j].array_base = 61;
3498 output[j].swizzle_x = 7;
3499 output[j].swizzle_y = 0;
3500 output[j].swizzle_z = 7;
3501 output[j].swizzle_w = 7;
3502 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3503 pos_emitted = true;
3504 break;
3505 case TGSI_SEMANTIC_LAYER:
3506 /* spi_sid is 0 for outputs that are
3507 * not consumed by PS */
3508 if (shader->output[i].spi_sid) {
3509 output[j].array_base = next_param_base++;
3510 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3511 j++;
3512 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3513 }
3514 output[j].array_base = 61;
3515 output[j].swizzle_x = 7;
3516 output[j].swizzle_y = 7;
3517 output[j].swizzle_z = 0;
3518 output[j].swizzle_w = 7;
3519 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3520 pos_emitted = true;
3521 break;
3522 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3523 /* spi_sid is 0 for outputs that are
3524 * not consumed by PS */
3525 if (shader->output[i].spi_sid) {
3526 output[j].array_base = next_param_base++;
3527 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3528 j++;
3529 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3530 }
3531 output[j].array_base = 61;
3532 output[j].swizzle_x = 7;
3533 output[j].swizzle_y = 7;
3534 output[j].swizzle_z = 7;
3535 output[j].swizzle_w = 0;
3536 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3537 pos_emitted = true;
3538 break;
3539 case TGSI_SEMANTIC_CLIPVERTEX:
3540 j--;
3541 break;
3542 case TGSI_SEMANTIC_CLIPDIST:
3543 output[j].array_base = next_clip_base++;
3544 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3545 pos_emitted = true;
3546 /* spi_sid is 0 for clipdistance outputs that were generated
3547 * for clipvertex - we don't need to pass them to PS */
3548 if (shader->output[i].spi_sid) {
3549 j++;
3550 /* duplicate it as PARAM to pass to the pixel shader */
3551 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3552 output[j].array_base = next_param_base++;
3553 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3554 }
3555 break;
3556 case TGSI_SEMANTIC_FOG:
3557 output[j].swizzle_y = 4; /* 0 */
3558 output[j].swizzle_z = 4; /* 0 */
3559 output[j].swizzle_w = 5; /* 1 */
3560 break;
3561 case TGSI_SEMANTIC_PRIMID:
3562 output[j].swizzle_x = 2;
3563 output[j].swizzle_y = 4; /* 0 */
3564 output[j].swizzle_z = 4; /* 0 */
3565 output[j].swizzle_w = 4; /* 0 */
3566 break;
3567 }
3568
3569 break;
3570 case TGSI_PROCESSOR_FRAGMENT:
3571 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3572 /* never export more colors than the number of CBs */
3573 if (shader->output[i].sid >= max_color_exports) {
3574 /* skip export */
3575 j--;
3576 continue;
3577 }
3578 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3579 output[j].array_base = shader->output[i].sid;
3580 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3581 shader->nr_ps_color_exports++;
3582 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3583 for (k = 1; k < max_color_exports; k++) {
3584 j++;
3585 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3586 output[j].gpr = shader->output[i].gpr;
3587 output[j].elem_size = 3;
3588 output[j].swizzle_x = 0;
3589 output[j].swizzle_y = 1;
3590 output[j].swizzle_z = 2;
3591 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3592 output[j].burst_count = 1;
3593 output[j].array_base = k;
3594 output[j].op = CF_OP_EXPORT;
3595 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3596 shader->nr_ps_color_exports++;
3597 }
3598 }
3599 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3600 output[j].array_base = 61;
3601 output[j].swizzle_x = 2;
3602 output[j].swizzle_y = 7;
3603 output[j].swizzle_z = output[j].swizzle_w = 7;
3604 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3605 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3606 output[j].array_base = 61;
3607 output[j].swizzle_x = 7;
3608 output[j].swizzle_y = 1;
3609 output[j].swizzle_z = output[j].swizzle_w = 7;
3610 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3611 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3612 output[j].array_base = 61;
3613 output[j].swizzle_x = 7;
3614 output[j].swizzle_y = 7;
3615 output[j].swizzle_z = 0;
3616 output[j].swizzle_w = 7;
3617 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3618 } else {
3619 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3620 r = -EINVAL;
3621 goto out_err;
3622 }
3623 break;
3624 case TGSI_PROCESSOR_TESS_CTRL:
3625 break;
3626 default:
3627 R600_ERR("unsupported processor type %d\n", ctx.type);
3628 r = -EINVAL;
3629 goto out_err;
3630 }
3631
3632 if (output[j].type==-1) {
3633 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3634 output[j].array_base = next_param_base++;
3635 }
3636 }
3637
3638 /* add fake position export */
3639 if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && pos_emitted == false) {
3640 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3641 output[j].gpr = 0;
3642 output[j].elem_size = 3;
3643 output[j].swizzle_x = 7;
3644 output[j].swizzle_y = 7;
3645 output[j].swizzle_z = 7;
3646 output[j].swizzle_w = 7;
3647 output[j].burst_count = 1;
3648 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3649 output[j].array_base = 60;
3650 output[j].op = CF_OP_EXPORT;
3651 j++;
3652 }
3653
3654 /* add fake param output for vertex shader if no param is exported */
3655 if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && next_param_base == 0) {
3656 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3657 output[j].gpr = 0;
3658 output[j].elem_size = 3;
3659 output[j].swizzle_x = 7;
3660 output[j].swizzle_y = 7;
3661 output[j].swizzle_z = 7;
3662 output[j].swizzle_w = 7;
3663 output[j].burst_count = 1;
3664 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3665 output[j].array_base = 0;
3666 output[j].op = CF_OP_EXPORT;
3667 j++;
3668 }
3669
3670 /* add fake pixel export */
3671 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
3672 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3673 output[j].gpr = 0;
3674 output[j].elem_size = 3;
3675 output[j].swizzle_x = 7;
3676 output[j].swizzle_y = 7;
3677 output[j].swizzle_z = 7;
3678 output[j].swizzle_w = 7;
3679 output[j].burst_count = 1;
3680 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3681 output[j].array_base = 0;
3682 output[j].op = CF_OP_EXPORT;
3683 j++;
3684 shader->nr_ps_color_exports++;
3685 }
3686
3687 noutput = j;
3688
3689 /* set export done on last export of each type */
3690 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3691 if (!(output_done & (1 << output[i].type))) {
3692 output_done |= (1 << output[i].type);
3693 output[i].op = CF_OP_EXPORT_DONE;
3694 }
3695 }
3696 /* add output to bytecode */
3697 if (!use_llvm) {
3698 for (i = 0; i < noutput; i++) {
3699 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3700 if (r)
3701 goto out_err;
3702 }
3703 }
3704 }
3705
3706 /* add program end */
3707 if (!use_llvm) {
3708 if (ctx.bc->chip_class == CAYMAN)
3709 cm_bytecode_add_cf_end(ctx.bc);
3710 else {
3711 const struct cf_op_info *last = NULL;
3712
3713 if (ctx.bc->cf_last)
3714 last = r600_isa_cf(ctx.bc->cf_last->op);
3715
3716 /* alu clause instructions don't have EOP bit, so add NOP */
3717 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3718 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3719
3720 ctx.bc->cf_last->end_of_program = 1;
3721 }
3722 }
3723
3724 /* check GPR limit - we have 124 = 128 - 4
3725 * (4 are reserved as alu clause temporary registers) */
3726 if (ctx.bc->ngpr > 124) {
3727 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3728 r = -ENOMEM;
3729 goto out_err;
3730 }
3731
3732 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3733 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3734 return r;
3735 }
3736
3737 free(ctx.literals);
3738 tgsi_parse_free(&ctx.parse);
3739 return 0;
3740 out_err:
3741 free(ctx.literals);
3742 tgsi_parse_free(&ctx.parse);
3743 return r;
3744 }
3745
3746 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3747 {
3748 const unsigned tgsi_opcode =
3749 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3750 R600_ERR("%s tgsi opcode unsupported\n",
3751 tgsi_get_opcode_name(tgsi_opcode));
3752 return -EINVAL;
3753 }
3754
3755 static int tgsi_end(struct r600_shader_ctx *ctx)
3756 {
3757 return 0;
3758 }
3759
3760 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3761 const struct r600_shader_src *shader_src,
3762 unsigned chan)
3763 {
3764 bc_src->sel = shader_src->sel;
3765 bc_src->chan = shader_src->swizzle[chan];
3766 bc_src->neg = shader_src->neg;
3767 bc_src->abs = shader_src->abs;
3768 bc_src->rel = shader_src->rel;
3769 bc_src->value = shader_src->value[bc_src->chan];
3770 bc_src->kc_bank = shader_src->kc_bank;
3771 bc_src->kc_rel = shader_src->kc_rel;
3772 }
3773
3774 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3775 {
3776 bc_src->abs = 1;
3777 bc_src->neg = 0;
3778 }
3779
3780 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3781 {
3782 bc_src->neg = !bc_src->neg;
3783 }
3784
3785 static void tgsi_dst(struct r600_shader_ctx *ctx,
3786 const struct tgsi_full_dst_register *tgsi_dst,
3787 unsigned swizzle,
3788 struct r600_bytecode_alu_dst *r600_dst)
3789 {
3790 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3791
3792 r600_dst->sel = tgsi_dst->Register.Index;
3793 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3794 r600_dst->chan = swizzle;
3795 r600_dst->write = 1;
3796 if (inst->Instruction.Saturate) {
3797 r600_dst->clamp = 1;
3798 }
3799 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
3800 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3801 return;
3802 }
3803 }
3804 if (tgsi_dst->Register.Indirect)
3805 r600_dst->rel = V_SQ_REL_RELATIVE;
3806
3807 }
3808
3809 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3810 {
3811 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3812 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3813 struct r600_bytecode_alu alu;
3814 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3815 int use_tmp = 0;
3816
3817 if (singledest) {
3818 switch (write_mask) {
3819 case 0x1:
3820 write_mask = 0x3;
3821 break;
3822 case 0x2:
3823 use_tmp = 1;
3824 write_mask = 0x3;
3825 break;
3826 case 0x4:
3827 write_mask = 0xc;
3828 break;
3829 case 0x8:
3830 write_mask = 0xc;
3831 use_tmp = 3;
3832 break;
3833 }
3834 }
3835
3836 lasti = tgsi_last_instruction(write_mask);
3837 for (i = 0; i <= lasti; i++) {
3838
3839 if (!(write_mask & (1 << i)))
3840 continue;
3841
3842 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3843
3844 if (singledest) {
3845 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3846 if (use_tmp) {
3847 alu.dst.sel = ctx->temp_reg;
3848 alu.dst.chan = i;
3849 alu.dst.write = 1;
3850 }
3851 if (i == 1 || i == 3)
3852 alu.dst.write = 0;
3853 } else
3854 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3855
3856 alu.op = ctx->inst_info->op;
3857 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3858 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3859 } else if (!swap) {
3860 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3861 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3862 }
3863 } else {
3864 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3865 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3866 }
3867
3868 /* handle some special cases */
3869 if (i == 1 || i == 3) {
3870 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3871 case TGSI_OPCODE_SUB:
3872 r600_bytecode_src_toggle_neg(&alu.src[1]);
3873 break;
3874 case TGSI_OPCODE_DABS:
3875 r600_bytecode_src_set_abs(&alu.src[0]);
3876 break;
3877 default:
3878 break;
3879 }
3880 }
3881 if (i == lasti) {
3882 alu.last = 1;
3883 }
3884 r = r600_bytecode_add_alu(ctx->bc, &alu);
3885 if (r)
3886 return r;
3887 }
3888
3889 if (use_tmp) {
3890 write_mask = inst->Dst[0].Register.WriteMask;
3891
3892 /* move result from temp to dst */
3893 for (i = 0; i <= lasti; i++) {
3894 if (!(write_mask & (1 << i)))
3895 continue;
3896
3897 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3898 alu.op = ALU_OP1_MOV;
3899 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3900 alu.src[0].sel = ctx->temp_reg;
3901 alu.src[0].chan = use_tmp - 1;
3902 alu.last = (i == lasti);
3903
3904 r = r600_bytecode_add_alu(ctx->bc, &alu);
3905 if (r)
3906 return r;
3907 }
3908 }
3909 return 0;
3910 }
3911
3912 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3913 {
3914 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3915 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3916 /* confirm writemasking */
3917 if ((write_mask & 0x3) != 0x3 &&
3918 (write_mask & 0xc) != 0xc) {
3919 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3920 return -1;
3921 }
3922 return tgsi_op2_64_params(ctx, false, false);
3923 }
3924
3925 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
3926 {
3927 return tgsi_op2_64_params(ctx, true, false);
3928 }
3929
3930 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
3931 {
3932 return tgsi_op2_64_params(ctx, true, true);
3933 }
3934
3935 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3936 {
3937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3938 struct r600_bytecode_alu alu;
3939 int i, j, r;
3940 int lasti = 3;
3941 int tmp = r600_get_temp(ctx);
3942
3943 for (i = 0; i < lasti + 1; i++) {
3944
3945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3946 alu.op = ctx->inst_info->op;
3947 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3948 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3949 }
3950
3951 if (inst->Dst[0].Register.WriteMask & (1 << i))
3952 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3953 else
3954 alu.dst.sel = tmp;
3955
3956 alu.dst.chan = i;
3957 alu.is_op3 = 1;
3958 if (i == lasti) {
3959 alu.last = 1;
3960 }
3961 r = r600_bytecode_add_alu(ctx->bc, &alu);
3962 if (r)
3963 return r;
3964 }
3965 return 0;
3966 }
3967
3968 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3969 {
3970 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3971 struct r600_bytecode_alu alu;
3972 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3973 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3974 /* use temp register if trans_only and more than one dst component */
3975 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3976
3977 for (i = 0; i <= lasti; i++) {
3978 if (!(write_mask & (1 << i)))
3979 continue;
3980
3981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3982 if (use_tmp) {
3983 alu.dst.sel = ctx->temp_reg;
3984 alu.dst.chan = i;
3985 alu.dst.write = 1;
3986 } else
3987 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3988
3989 alu.op = ctx->inst_info->op;
3990 if (!swap) {
3991 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3992 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3993 }
3994 } else {
3995 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3996 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3997 }
3998 /* handle some special cases */
3999 switch (inst->Instruction.Opcode) {
4000 case TGSI_OPCODE_SUB:
4001 r600_bytecode_src_toggle_neg(&alu.src[1]);
4002 break;
4003 case TGSI_OPCODE_ABS:
4004 r600_bytecode_src_set_abs(&alu.src[0]);
4005 break;
4006 default:
4007 break;
4008 }
4009 if (i == lasti || trans_only) {
4010 alu.last = 1;
4011 }
4012 r = r600_bytecode_add_alu(ctx->bc, &alu);
4013 if (r)
4014 return r;
4015 }
4016
4017 if (use_tmp) {
4018 /* move result from temp to dst */
4019 for (i = 0; i <= lasti; i++) {
4020 if (!(write_mask & (1 << i)))
4021 continue;
4022
4023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4024 alu.op = ALU_OP1_MOV;
4025 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4026 alu.src[0].sel = ctx->temp_reg;
4027 alu.src[0].chan = i;
4028 alu.last = (i == lasti);
4029
4030 r = r600_bytecode_add_alu(ctx->bc, &alu);
4031 if (r)
4032 return r;
4033 }
4034 }
4035 return 0;
4036 }
4037
4038 static int tgsi_op2(struct r600_shader_ctx *ctx)
4039 {
4040 return tgsi_op2_s(ctx, 0, 0);
4041 }
4042
4043 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4044 {
4045 return tgsi_op2_s(ctx, 1, 0);
4046 }
4047
4048 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4049 {
4050 return tgsi_op2_s(ctx, 0, 1);
4051 }
4052
4053 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4054 {
4055 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4056 struct r600_bytecode_alu alu;
4057 int i, r;
4058 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4059
4060 for (i = 0; i < lasti + 1; i++) {
4061
4062 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4063 continue;
4064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4065 alu.op = ctx->inst_info->op;
4066
4067 alu.src[0].sel = V_SQ_ALU_SRC_0;
4068
4069 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4070
4071 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4072
4073 if (i == lasti) {
4074 alu.last = 1;
4075 }
4076 r = r600_bytecode_add_alu(ctx->bc, &alu);
4077 if (r)
4078 return r;
4079 }
4080 return 0;
4081
4082 }
4083
4084 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4085 {
4086 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4087 struct r600_bytecode_alu alu;
4088 int i, r;
4089 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4090
4091 for (i = 0; i < lasti + 1; i++) {
4092
4093 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4094 continue;
4095 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4096 alu.op = ALU_OP1_MOV;
4097
4098 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4099
4100 if (i == 1 || i == 3)
4101 r600_bytecode_src_toggle_neg(&alu.src[0]);
4102 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4103
4104 if (i == lasti) {
4105 alu.last = 1;
4106 }
4107 r = r600_bytecode_add_alu(ctx->bc, &alu);
4108 if (r)
4109 return r;
4110 }
4111 return 0;
4112
4113 }
4114
4115 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4116 {
4117 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4118 struct r600_bytecode_alu alu;
4119 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4120 int i, j, r;
4121 int firsti = write_mask == 0xc ? 2 : 0;
4122
4123 for (i = 0; i <= 3; i++) {
4124 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4125 alu.op = ctx->inst_info->op;
4126
4127 alu.dst.sel = ctx->temp_reg;
4128 alu.dst.chan = i;
4129 alu.dst.write = 1;
4130 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4131 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4132 }
4133
4134 if (i == 3)
4135 alu.last = 1;
4136
4137 r = r600_bytecode_add_alu(ctx->bc, &alu);
4138 if (r)
4139 return r;
4140 }
4141
4142 /* MOV first two channels to writemask dst0 */
4143 for (i = 0; i <= 1; i++) {
4144 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4145 alu.op = ALU_OP1_MOV;
4146 alu.src[0].chan = i + 2;
4147 alu.src[0].sel = ctx->temp_reg;
4148
4149 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
4150 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
4151 alu.last = 1;
4152 r = r600_bytecode_add_alu(ctx->bc, &alu);
4153 if (r)
4154 return r;
4155 }
4156
4157 for (i = 0; i <= 3; i++) {
4158 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4159 /* MOV third channels to writemask dst1 */
4160 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4161 alu.op = ALU_OP1_MOV;
4162 alu.src[0].chan = 1;
4163 alu.src[0].sel = ctx->temp_reg;
4164
4165 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4166 alu.last = 1;
4167 r = r600_bytecode_add_alu(ctx->bc, &alu);
4168 if (r)
4169 return r;
4170 break;
4171 }
4172 }
4173 return 0;
4174 }
4175
4176
4177 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4178 {
4179 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4180 struct r600_bytecode_alu alu;
4181 int i, r;
4182 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4183
4184 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4185 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4186
4187 for (i = 0; i <= (lasti+1)/2; i++) {
4188 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4189 alu.op = ctx->inst_info->op;
4190
4191 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4192 alu.dst.sel = ctx->temp_reg;
4193 alu.dst.chan = i;
4194 alu.dst.write = 1;
4195 alu.last = 1;
4196
4197 r = r600_bytecode_add_alu(ctx->bc, &alu);
4198 if (r)
4199 return r;
4200 }
4201
4202 for (i = 0; i <= lasti; i++) {
4203 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4204 alu.op = ALU_OP1_FLT32_TO_FLT64;
4205
4206 alu.src[0].chan = i/2;
4207 if (i%2 == 0)
4208 alu.src[0].sel = ctx->temp_reg;
4209 else {
4210 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4211 alu.src[0].value = 0x0;
4212 }
4213 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4214 alu.last = i == lasti;
4215
4216 r = r600_bytecode_add_alu(ctx->bc, &alu);
4217 if (r)
4218 return r;
4219 }
4220
4221 return 0;
4222 }
4223
4224 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4225 {
4226 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4227 struct r600_bytecode_alu alu;
4228 int i, r;
4229 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4230
4231 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4232 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4233
4234 for (i = 0; i <= lasti; i++) {
4235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4236 alu.op = ALU_OP1_FLT64_TO_FLT32;
4237
4238 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4239 alu.dst.chan = i;
4240 alu.dst.sel = ctx->temp_reg;
4241 alu.dst.write = i%2 == 0;
4242 alu.last = i == lasti;
4243
4244 r = r600_bytecode_add_alu(ctx->bc, &alu);
4245 if (r)
4246 return r;
4247 }
4248
4249 for (i = 0; i <= (lasti+1)/2; i++) {
4250 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4251 alu.op = ctx->inst_info->op;
4252
4253 alu.src[0].chan = i*2;
4254 alu.src[0].sel = ctx->temp_reg;
4255 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4256 alu.last = 1;
4257
4258 r = r600_bytecode_add_alu(ctx->bc, &alu);
4259 if (r)
4260 return r;
4261 }
4262
4263 return 0;
4264 }
4265
4266 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4267 {
4268 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4269 int i, r;
4270 struct r600_bytecode_alu alu;
4271 int last_slot = 3;
4272 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4273 int t1 = ctx->temp_reg;
4274
4275 /* these have to write the result to X/Y by the looks of it */
4276 for (i = 0 ; i < last_slot; i++) {
4277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4278 alu.op = ctx->inst_info->op;
4279
4280 /* should only be one src regs */
4281 assert (inst->Instruction.NumSrcRegs == 1);
4282
4283 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4284 r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
4285
4286 /* RSQ should take the absolute value of src */
4287 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4288 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT) {
4289 r600_bytecode_src_set_abs(&alu.src[1]);
4290 }
4291 alu.dst.sel = t1;
4292 alu.dst.chan = i;
4293 alu.dst.write = (i == 0 || i == 1);
4294
4295 if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
4296 alu.last = 1;
4297 r = r600_bytecode_add_alu(ctx->bc, &alu);
4298 if (r)
4299 return r;
4300 }
4301
4302 for (i = 0 ; i <= lasti; i++) {
4303 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4304 continue;
4305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4306 alu.op = ALU_OP1_MOV;
4307 alu.src[0].sel = t1;
4308 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4309 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4310 alu.dst.write = 1;
4311 if (i == lasti)
4312 alu.last = 1;
4313 r = r600_bytecode_add_alu(ctx->bc, &alu);
4314 if (r)
4315 return r;
4316 }
4317 return 0;
4318 }
4319
4320 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4321 {
4322 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4323 int i, j, r;
4324 struct r600_bytecode_alu alu;
4325 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4326
4327 for (i = 0 ; i < last_slot; i++) {
4328 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4329 alu.op = ctx->inst_info->op;
4330 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4331 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4332
4333 /* RSQ should take the absolute value of src */
4334 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4335 r600_bytecode_src_set_abs(&alu.src[j]);
4336 }
4337 }
4338 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4339 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4340
4341 if (i == last_slot - 1)
4342 alu.last = 1;
4343 r = r600_bytecode_add_alu(ctx->bc, &alu);
4344 if (r)
4345 return r;
4346 }
4347 return 0;
4348 }
4349
4350 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4351 {
4352 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4353 int i, j, k, r;
4354 struct r600_bytecode_alu alu;
4355 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4356 int t1 = ctx->temp_reg;
4357
4358 for (k = 0; k <= lasti; k++) {
4359 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4360 continue;
4361
4362 for (i = 0 ; i < 4; i++) {
4363 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4364 alu.op = ctx->inst_info->op;
4365 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4366 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4367 }
4368 alu.dst.sel = t1;
4369 alu.dst.chan = i;
4370 alu.dst.write = (i == k);
4371 if (i == 3)
4372 alu.last = 1;
4373 r = r600_bytecode_add_alu(ctx->bc, &alu);
4374 if (r)
4375 return r;
4376 }
4377 }
4378
4379 for (i = 0 ; i <= lasti; i++) {
4380 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4381 continue;
4382 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4383 alu.op = ALU_OP1_MOV;
4384 alu.src[0].sel = t1;
4385 alu.src[0].chan = i;
4386 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4387 alu.dst.write = 1;
4388 if (i == lasti)
4389 alu.last = 1;
4390 r = r600_bytecode_add_alu(ctx->bc, &alu);
4391 if (r)
4392 return r;
4393 }
4394
4395 return 0;
4396 }
4397
4398
4399 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4400 {
4401 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4402 int i, j, k, r;
4403 struct r600_bytecode_alu alu;
4404 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4405 int t1 = ctx->temp_reg;
4406
4407 for (k = 0; k < 2; k++) {
4408 if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2))))
4409 continue;
4410
4411 for (i = 0; i < 4; i++) {
4412 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4413 alu.op = ctx->inst_info->op;
4414 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4415 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));;
4416 }
4417 alu.dst.sel = t1;
4418 alu.dst.chan = i;
4419 alu.dst.write = 1;
4420 if (i == 3)
4421 alu.last = 1;
4422 r = r600_bytecode_add_alu(ctx->bc, &alu);
4423 if (r)
4424 return r;
4425 }
4426 }
4427
4428 for (i = 0; i <= lasti; i++) {
4429 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4430 continue;
4431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4432 alu.op = ALU_OP1_MOV;
4433 alu.src[0].sel = t1;
4434 alu.src[0].chan = i;
4435 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4436 alu.dst.write = 1;
4437 if (i == lasti)
4438 alu.last = 1;
4439 r = r600_bytecode_add_alu(ctx->bc, &alu);
4440 if (r)
4441 return r;
4442 }
4443
4444 return 0;
4445 }
4446
4447 /*
4448 * r600 - trunc to -PI..PI range
4449 * r700 - normalize by dividing by 2PI
4450 * see fdo bug 27901
4451 */
4452 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4453 {
4454 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
4455 static float double_pi = 3.1415926535 * 2;
4456 static float neg_pi = -3.1415926535;
4457
4458 int r;
4459 struct r600_bytecode_alu alu;
4460
4461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4462 alu.op = ALU_OP3_MULADD;
4463 alu.is_op3 = 1;
4464
4465 alu.dst.chan = 0;
4466 alu.dst.sel = ctx->temp_reg;
4467 alu.dst.write = 1;
4468
4469 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4470
4471 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4472 alu.src[1].chan = 0;
4473 alu.src[1].value = *(uint32_t *)&half_inv_pi;
4474 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4475 alu.src[2].chan = 0;
4476 alu.last = 1;
4477 r = r600_bytecode_add_alu(ctx->bc, &alu);
4478 if (r)
4479 return r;
4480
4481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4482 alu.op = ALU_OP1_FRACT;
4483
4484 alu.dst.chan = 0;
4485 alu.dst.sel = ctx->temp_reg;
4486 alu.dst.write = 1;
4487
4488 alu.src[0].sel = ctx->temp_reg;
4489 alu.src[0].chan = 0;
4490 alu.last = 1;
4491 r = r600_bytecode_add_alu(ctx->bc, &alu);
4492 if (r)
4493 return r;
4494
4495 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4496 alu.op = ALU_OP3_MULADD;
4497 alu.is_op3 = 1;
4498
4499 alu.dst.chan = 0;
4500 alu.dst.sel = ctx->temp_reg;
4501 alu.dst.write = 1;
4502
4503 alu.src[0].sel = ctx->temp_reg;
4504 alu.src[0].chan = 0;
4505
4506 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4507 alu.src[1].chan = 0;
4508 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4509 alu.src[2].chan = 0;
4510
4511 if (ctx->bc->chip_class == R600) {
4512 alu.src[1].value = *(uint32_t *)&double_pi;
4513 alu.src[2].value = *(uint32_t *)&neg_pi;
4514 } else {
4515 alu.src[1].sel = V_SQ_ALU_SRC_1;
4516 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4517 alu.src[2].neg = 1;
4518 }
4519
4520 alu.last = 1;
4521 r = r600_bytecode_add_alu(ctx->bc, &alu);
4522 if (r)
4523 return r;
4524 return 0;
4525 }
4526
4527 static int cayman_trig(struct r600_shader_ctx *ctx)
4528 {
4529 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4530 struct r600_bytecode_alu alu;
4531 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4532 int i, r;
4533
4534 r = tgsi_setup_trig(ctx);
4535 if (r)
4536 return r;
4537
4538
4539 for (i = 0; i < last_slot; i++) {
4540 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4541 alu.op = ctx->inst_info->op;
4542 alu.dst.chan = i;
4543
4544 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4545 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4546
4547 alu.src[0].sel = ctx->temp_reg;
4548 alu.src[0].chan = 0;
4549 if (i == last_slot - 1)
4550 alu.last = 1;
4551 r = r600_bytecode_add_alu(ctx->bc, &alu);
4552 if (r)
4553 return r;
4554 }
4555 return 0;
4556 }
4557
4558 static int tgsi_trig(struct r600_shader_ctx *ctx)
4559 {
4560 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4561 struct r600_bytecode_alu alu;
4562 int i, r;
4563 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4564
4565 r = tgsi_setup_trig(ctx);
4566 if (r)
4567 return r;
4568
4569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4570 alu.op = ctx->inst_info->op;
4571 alu.dst.chan = 0;
4572 alu.dst.sel = ctx->temp_reg;
4573 alu.dst.write = 1;
4574
4575 alu.src[0].sel = ctx->temp_reg;
4576 alu.src[0].chan = 0;
4577 alu.last = 1;
4578 r = r600_bytecode_add_alu(ctx->bc, &alu);
4579 if (r)
4580 return r;
4581
4582 /* replicate result */
4583 for (i = 0; i < lasti + 1; i++) {
4584 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4585 continue;
4586
4587 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4588 alu.op = ALU_OP1_MOV;
4589
4590 alu.src[0].sel = ctx->temp_reg;
4591 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4592 if (i == lasti)
4593 alu.last = 1;
4594 r = r600_bytecode_add_alu(ctx->bc, &alu);
4595 if (r)
4596 return r;
4597 }
4598 return 0;
4599 }
4600
4601 static int tgsi_scs(struct r600_shader_ctx *ctx)
4602 {
4603 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4604 struct r600_bytecode_alu alu;
4605 int i, r;
4606
4607 /* We'll only need the trig stuff if we are going to write to the
4608 * X or Y components of the destination vector.
4609 */
4610 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
4611 r = tgsi_setup_trig(ctx);
4612 if (r)
4613 return r;
4614 }
4615
4616 /* dst.x = COS */
4617 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4618 if (ctx->bc->chip_class == CAYMAN) {
4619 for (i = 0 ; i < 3; i++) {
4620 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4621 alu.op = ALU_OP1_COS;
4622 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4623
4624 if (i == 0)
4625 alu.dst.write = 1;
4626 else
4627 alu.dst.write = 0;
4628 alu.src[0].sel = ctx->temp_reg;
4629 alu.src[0].chan = 0;
4630 if (i == 2)
4631 alu.last = 1;
4632 r = r600_bytecode_add_alu(ctx->bc, &alu);
4633 if (r)
4634 return r;
4635 }
4636 } else {
4637 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4638 alu.op = ALU_OP1_COS;
4639 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4640
4641 alu.src[0].sel = ctx->temp_reg;
4642 alu.src[0].chan = 0;
4643 alu.last = 1;
4644 r = r600_bytecode_add_alu(ctx->bc, &alu);
4645 if (r)
4646 return r;
4647 }
4648 }
4649
4650 /* dst.y = SIN */
4651 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4652 if (ctx->bc->chip_class == CAYMAN) {
4653 for (i = 0 ; i < 3; i++) {
4654 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4655 alu.op = ALU_OP1_SIN;
4656 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4657 if (i == 1)
4658 alu.dst.write = 1;
4659 else
4660 alu.dst.write = 0;
4661 alu.src[0].sel = ctx->temp_reg;
4662 alu.src[0].chan = 0;
4663 if (i == 2)
4664 alu.last = 1;
4665 r = r600_bytecode_add_alu(ctx->bc, &alu);
4666 if (r)
4667 return r;
4668 }
4669 } else {
4670 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4671 alu.op = ALU_OP1_SIN;
4672 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4673
4674 alu.src[0].sel = ctx->temp_reg;
4675 alu.src[0].chan = 0;
4676 alu.last = 1;
4677 r = r600_bytecode_add_alu(ctx->bc, &alu);
4678 if (r)
4679 return r;
4680 }
4681 }
4682
4683 /* dst.z = 0.0; */
4684 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4685 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4686
4687 alu.op = ALU_OP1_MOV;
4688
4689 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4690
4691 alu.src[0].sel = V_SQ_ALU_SRC_0;
4692 alu.src[0].chan = 0;
4693
4694 alu.last = 1;
4695
4696 r = r600_bytecode_add_alu(ctx->bc, &alu);
4697 if (r)
4698 return r;
4699 }
4700
4701 /* dst.w = 1.0; */
4702 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4704
4705 alu.op = ALU_OP1_MOV;
4706
4707 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4708
4709 alu.src[0].sel = V_SQ_ALU_SRC_1;
4710 alu.src[0].chan = 0;
4711
4712 alu.last = 1;
4713
4714 r = r600_bytecode_add_alu(ctx->bc, &alu);
4715 if (r)
4716 return r;
4717 }
4718
4719 return 0;
4720 }
4721
4722 static int tgsi_kill(struct r600_shader_ctx *ctx)
4723 {
4724 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4725 struct r600_bytecode_alu alu;
4726 int i, r;
4727
4728 for (i = 0; i < 4; i++) {
4729 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4730 alu.op = ctx->inst_info->op;
4731
4732 alu.dst.chan = i;
4733
4734 alu.src[0].sel = V_SQ_ALU_SRC_0;
4735
4736 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4737 alu.src[1].sel = V_SQ_ALU_SRC_1;
4738 alu.src[1].neg = 1;
4739 } else {
4740 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4741 }
4742 if (i == 3) {
4743 alu.last = 1;
4744 }
4745 r = r600_bytecode_add_alu(ctx->bc, &alu);
4746 if (r)
4747 return r;
4748 }
4749
4750 /* kill must be last in ALU */
4751 ctx->bc->force_add_cf = 1;
4752 ctx->shader->uses_kill = TRUE;
4753 return 0;
4754 }
4755
4756 static int tgsi_lit(struct r600_shader_ctx *ctx)
4757 {
4758 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4759 struct r600_bytecode_alu alu;
4760 int r;
4761
4762 /* tmp.x = max(src.y, 0.0) */
4763 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4764 alu.op = ALU_OP2_MAX;
4765 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4766 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4767 alu.src[1].chan = 1;
4768
4769 alu.dst.sel = ctx->temp_reg;
4770 alu.dst.chan = 0;
4771 alu.dst.write = 1;
4772
4773 alu.last = 1;
4774 r = r600_bytecode_add_alu(ctx->bc, &alu);
4775 if (r)
4776 return r;
4777
4778 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4779 {
4780 int chan;
4781 int sel;
4782 int i;
4783
4784 if (ctx->bc->chip_class == CAYMAN) {
4785 for (i = 0; i < 3; i++) {
4786 /* tmp.z = log(tmp.x) */
4787 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4788 alu.op = ALU_OP1_LOG_CLAMPED;
4789 alu.src[0].sel = ctx->temp_reg;
4790 alu.src[0].chan = 0;
4791 alu.dst.sel = ctx->temp_reg;
4792 alu.dst.chan = i;
4793 if (i == 2) {
4794 alu.dst.write = 1;
4795 alu.last = 1;
4796 } else
4797 alu.dst.write = 0;
4798
4799 r = r600_bytecode_add_alu(ctx->bc, &alu);
4800 if (r)
4801 return r;
4802 }
4803 } else {
4804 /* tmp.z = log(tmp.x) */
4805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4806 alu.op = ALU_OP1_LOG_CLAMPED;
4807 alu.src[0].sel = ctx->temp_reg;
4808 alu.src[0].chan = 0;
4809 alu.dst.sel = ctx->temp_reg;
4810 alu.dst.chan = 2;
4811 alu.dst.write = 1;
4812 alu.last = 1;
4813 r = r600_bytecode_add_alu(ctx->bc, &alu);
4814 if (r)
4815 return r;
4816 }
4817
4818 chan = alu.dst.chan;
4819 sel = alu.dst.sel;
4820
4821 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4823 alu.op = ALU_OP3_MUL_LIT;
4824 alu.src[0].sel = sel;
4825 alu.src[0].chan = chan;
4826 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4827 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4828 alu.dst.sel = ctx->temp_reg;
4829 alu.dst.chan = 0;
4830 alu.dst.write = 1;
4831 alu.is_op3 = 1;
4832 alu.last = 1;
4833 r = r600_bytecode_add_alu(ctx->bc, &alu);
4834 if (r)
4835 return r;
4836
4837 if (ctx->bc->chip_class == CAYMAN) {
4838 for (i = 0; i < 3; i++) {
4839 /* dst.z = exp(tmp.x) */
4840 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4841 alu.op = ALU_OP1_EXP_IEEE;
4842 alu.src[0].sel = ctx->temp_reg;
4843 alu.src[0].chan = 0;
4844 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4845 if (i == 2) {
4846 alu.dst.write = 1;
4847 alu.last = 1;
4848 } else
4849 alu.dst.write = 0;
4850 r = r600_bytecode_add_alu(ctx->bc, &alu);
4851 if (r)
4852 return r;
4853 }
4854 } else {
4855 /* dst.z = exp(tmp.x) */
4856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4857 alu.op = ALU_OP1_EXP_IEEE;
4858 alu.src[0].sel = ctx->temp_reg;
4859 alu.src[0].chan = 0;
4860 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4861 alu.last = 1;
4862 r = r600_bytecode_add_alu(ctx->bc, &alu);
4863 if (r)
4864 return r;
4865 }
4866 }
4867
4868 /* dst.x, <- 1.0 */
4869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4870 alu.op = ALU_OP1_MOV;
4871 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4872 alu.src[0].chan = 0;
4873 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4874 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4875 r = r600_bytecode_add_alu(ctx->bc, &alu);
4876 if (r)
4877 return r;
4878
4879 /* dst.y = max(src.x, 0.0) */
4880 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4881 alu.op = ALU_OP2_MAX;
4882 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4883 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4884 alu.src[1].chan = 0;
4885 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4886 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4887 r = r600_bytecode_add_alu(ctx->bc, &alu);
4888 if (r)
4889 return r;
4890
4891 /* dst.w, <- 1.0 */
4892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4893 alu.op = ALU_OP1_MOV;
4894 alu.src[0].sel = V_SQ_ALU_SRC_1;
4895 alu.src[0].chan = 0;
4896 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4897 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4898 alu.last = 1;
4899 r = r600_bytecode_add_alu(ctx->bc, &alu);
4900 if (r)
4901 return r;
4902
4903 return 0;
4904 }
4905
4906 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4907 {
4908 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4909 struct r600_bytecode_alu alu;
4910 int i, r;
4911
4912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4913
4914 /* XXX:
4915 * For state trackers other than OpenGL, we'll want to use
4916 * _RECIPSQRT_IEEE instead.
4917 */
4918 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
4919
4920 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4921 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4922 r600_bytecode_src_set_abs(&alu.src[i]);
4923 }
4924 alu.dst.sel = ctx->temp_reg;
4925 alu.dst.write = 1;
4926 alu.last = 1;
4927 r = r600_bytecode_add_alu(ctx->bc, &alu);
4928 if (r)
4929 return r;
4930 /* replicate result */
4931 return tgsi_helper_tempx_replicate(ctx);
4932 }
4933
4934 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4935 {
4936 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4937 struct r600_bytecode_alu alu;
4938 int i, r;
4939
4940 for (i = 0; i < 4; i++) {
4941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4942 alu.src[0].sel = ctx->temp_reg;
4943 alu.op = ALU_OP1_MOV;
4944 alu.dst.chan = i;
4945 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4946 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4947 if (i == 3)
4948 alu.last = 1;
4949 r = r600_bytecode_add_alu(ctx->bc, &alu);
4950 if (r)
4951 return r;
4952 }
4953 return 0;
4954 }
4955
4956 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4957 {
4958 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4959 struct r600_bytecode_alu alu;
4960 int i, r;
4961
4962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4963 alu.op = ctx->inst_info->op;
4964 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4965 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4966 }
4967 alu.dst.sel = ctx->temp_reg;
4968 alu.dst.write = 1;
4969 alu.last = 1;
4970 r = r600_bytecode_add_alu(ctx->bc, &alu);
4971 if (r)
4972 return r;
4973 /* replicate result */
4974 return tgsi_helper_tempx_replicate(ctx);
4975 }
4976
4977 static int cayman_pow(struct r600_shader_ctx *ctx)
4978 {
4979 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4980 int i, r;
4981 struct r600_bytecode_alu alu;
4982 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4983
4984 for (i = 0; i < 3; i++) {
4985 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4986 alu.op = ALU_OP1_LOG_IEEE;
4987 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4988 alu.dst.sel = ctx->temp_reg;
4989 alu.dst.chan = i;
4990 alu.dst.write = 1;
4991 if (i == 2)
4992 alu.last = 1;
4993 r = r600_bytecode_add_alu(ctx->bc, &alu);
4994 if (r)
4995 return r;
4996 }
4997
4998 /* b * LOG2(a) */
4999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5000 alu.op = ALU_OP2_MUL;
5001 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5002 alu.src[1].sel = ctx->temp_reg;
5003 alu.dst.sel = ctx->temp_reg;
5004 alu.dst.write = 1;
5005 alu.last = 1;
5006 r = r600_bytecode_add_alu(ctx->bc, &alu);
5007 if (r)
5008 return r;
5009
5010 for (i = 0; i < last_slot; i++) {
5011 /* POW(a,b) = EXP2(b * LOG2(a))*/
5012 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5013 alu.op = ALU_OP1_EXP_IEEE;
5014 alu.src[0].sel = ctx->temp_reg;
5015
5016 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5017 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5018 if (i == last_slot - 1)
5019 alu.last = 1;
5020 r = r600_bytecode_add_alu(ctx->bc, &alu);
5021 if (r)
5022 return r;
5023 }
5024 return 0;
5025 }
5026
5027 static int tgsi_pow(struct r600_shader_ctx *ctx)
5028 {
5029 struct r600_bytecode_alu alu;
5030 int r;
5031
5032 /* LOG2(a) */
5033 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5034 alu.op = ALU_OP1_LOG_IEEE;
5035 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5036 alu.dst.sel = ctx->temp_reg;
5037 alu.dst.write = 1;
5038 alu.last = 1;
5039 r = r600_bytecode_add_alu(ctx->bc, &alu);
5040 if (r)
5041 return r;
5042 /* b * LOG2(a) */
5043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5044 alu.op = ALU_OP2_MUL;
5045 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5046 alu.src[1].sel = ctx->temp_reg;
5047 alu.dst.sel = ctx->temp_reg;
5048 alu.dst.write = 1;
5049 alu.last = 1;
5050 r = r600_bytecode_add_alu(ctx->bc, &alu);
5051 if (r)
5052 return r;
5053 /* POW(a,b) = EXP2(b * LOG2(a))*/
5054 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5055 alu.op = ALU_OP1_EXP_IEEE;
5056 alu.src[0].sel = ctx->temp_reg;
5057 alu.dst.sel = ctx->temp_reg;
5058 alu.dst.write = 1;
5059 alu.last = 1;
5060 r = r600_bytecode_add_alu(ctx->bc, &alu);
5061 if (r)
5062 return r;
5063 return tgsi_helper_tempx_replicate(ctx);
5064 }
5065
5066 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5067 {
5068 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5069 struct r600_bytecode_alu alu;
5070 int i, r, j;
5071 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5072 int tmp0 = ctx->temp_reg;
5073 int tmp1 = r600_get_temp(ctx);
5074 int tmp2 = r600_get_temp(ctx);
5075 int tmp3 = r600_get_temp(ctx);
5076 /* Unsigned path:
5077 *
5078 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5079 *
5080 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5081 * 2. tmp0.z = lo (tmp0.x * src2)
5082 * 3. tmp0.w = -tmp0.z
5083 * 4. tmp0.y = hi (tmp0.x * src2)
5084 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5085 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5086 * 7. tmp1.x = tmp0.x - tmp0.w
5087 * 8. tmp1.y = tmp0.x + tmp0.w
5088 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5089 * 10. tmp0.z = hi(tmp0.x * src1) = q
5090 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5091 *
5092 * 12. tmp0.w = src1 - tmp0.y = r
5093 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5094 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5095 *
5096 * if DIV
5097 *
5098 * 15. tmp1.z = tmp0.z + 1 = q + 1
5099 * 16. tmp1.w = tmp0.z - 1 = q - 1
5100 *
5101 * else MOD
5102 *
5103 * 15. tmp1.z = tmp0.w - src2 = r - src2
5104 * 16. tmp1.w = tmp0.w + src2 = r + src2
5105 *
5106 * endif
5107 *
5108 * 17. tmp1.x = tmp1.x & tmp1.y
5109 *
5110 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5111 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5112 *
5113 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5114 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5115 *
5116 * Signed path:
5117 *
5118 * Same as unsigned, using abs values of the operands,
5119 * and fixing the sign of the result in the end.
5120 */
5121
5122 for (i = 0; i < 4; i++) {
5123 if (!(write_mask & (1<<i)))
5124 continue;
5125
5126 if (signed_op) {
5127
5128 /* tmp2.x = -src0 */
5129 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5130 alu.op = ALU_OP2_SUB_INT;
5131
5132 alu.dst.sel = tmp2;
5133 alu.dst.chan = 0;
5134 alu.dst.write = 1;
5135
5136 alu.src[0].sel = V_SQ_ALU_SRC_0;
5137
5138 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5139
5140 alu.last = 1;
5141 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5142 return r;
5143
5144 /* tmp2.y = -src1 */
5145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5146 alu.op = ALU_OP2_SUB_INT;
5147
5148 alu.dst.sel = tmp2;
5149 alu.dst.chan = 1;
5150 alu.dst.write = 1;
5151
5152 alu.src[0].sel = V_SQ_ALU_SRC_0;
5153
5154 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5155
5156 alu.last = 1;
5157 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5158 return r;
5159
5160 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5161 /* it will be a sign of the quotient */
5162 if (!mod) {
5163
5164 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5165 alu.op = ALU_OP2_XOR_INT;
5166
5167 alu.dst.sel = tmp2;
5168 alu.dst.chan = 2;
5169 alu.dst.write = 1;
5170
5171 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5172 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5173
5174 alu.last = 1;
5175 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5176 return r;
5177 }
5178
5179 /* tmp2.x = |src0| */
5180 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5181 alu.op = ALU_OP3_CNDGE_INT;
5182 alu.is_op3 = 1;
5183
5184 alu.dst.sel = tmp2;
5185 alu.dst.chan = 0;
5186 alu.dst.write = 1;
5187
5188 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5189 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5190 alu.src[2].sel = tmp2;
5191 alu.src[2].chan = 0;
5192
5193 alu.last = 1;
5194 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5195 return r;
5196
5197 /* tmp2.y = |src1| */
5198 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5199 alu.op = ALU_OP3_CNDGE_INT;
5200 alu.is_op3 = 1;
5201
5202 alu.dst.sel = tmp2;
5203 alu.dst.chan = 1;
5204 alu.dst.write = 1;
5205
5206 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5207 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5208 alu.src[2].sel = tmp2;
5209 alu.src[2].chan = 1;
5210
5211 alu.last = 1;
5212 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5213 return r;
5214
5215 }
5216
5217 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5218 if (ctx->bc->chip_class == CAYMAN) {
5219 /* tmp3.x = u2f(src2) */
5220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5221 alu.op = ALU_OP1_UINT_TO_FLT;
5222
5223 alu.dst.sel = tmp3;
5224 alu.dst.chan = 0;
5225 alu.dst.write = 1;
5226
5227 if (signed_op) {
5228 alu.src[0].sel = tmp2;
5229 alu.src[0].chan = 1;
5230 } else {
5231 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5232 }
5233
5234 alu.last = 1;
5235 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5236 return r;
5237
5238 /* tmp0.x = recip(tmp3.x) */
5239 for (j = 0 ; j < 3; j++) {
5240 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5241 alu.op = ALU_OP1_RECIP_IEEE;
5242
5243 alu.dst.sel = tmp0;
5244 alu.dst.chan = j;
5245 alu.dst.write = (j == 0);
5246
5247 alu.src[0].sel = tmp3;
5248 alu.src[0].chan = 0;
5249
5250 if (j == 2)
5251 alu.last = 1;
5252 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5253 return r;
5254 }
5255
5256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5257 alu.op = ALU_OP2_MUL;
5258
5259 alu.src[0].sel = tmp0;
5260 alu.src[0].chan = 0;
5261
5262 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5263 alu.src[1].value = 0x4f800000;
5264
5265 alu.dst.sel = tmp3;
5266 alu.dst.write = 1;
5267 alu.last = 1;
5268 r = r600_bytecode_add_alu(ctx->bc, &alu);
5269 if (r)
5270 return r;
5271
5272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5273 alu.op = ALU_OP1_FLT_TO_UINT;
5274
5275 alu.dst.sel = tmp0;
5276 alu.dst.chan = 0;
5277 alu.dst.write = 1;
5278
5279 alu.src[0].sel = tmp3;
5280 alu.src[0].chan = 0;
5281
5282 alu.last = 1;
5283 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5284 return r;
5285
5286 } else {
5287 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5288 alu.op = ALU_OP1_RECIP_UINT;
5289
5290 alu.dst.sel = tmp0;
5291 alu.dst.chan = 0;
5292 alu.dst.write = 1;
5293
5294 if (signed_op) {
5295 alu.src[0].sel = tmp2;
5296 alu.src[0].chan = 1;
5297 } else {
5298 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5299 }
5300
5301 alu.last = 1;
5302 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5303 return r;
5304 }
5305
5306 /* 2. tmp0.z = lo (tmp0.x * src2) */
5307 if (ctx->bc->chip_class == CAYMAN) {
5308 for (j = 0 ; j < 4; j++) {
5309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5310 alu.op = ALU_OP2_MULLO_UINT;
5311
5312 alu.dst.sel = tmp0;
5313 alu.dst.chan = j;
5314 alu.dst.write = (j == 2);
5315
5316 alu.src[0].sel = tmp0;
5317 alu.src[0].chan = 0;
5318 if (signed_op) {
5319 alu.src[1].sel = tmp2;
5320 alu.src[1].chan = 1;
5321 } else {
5322 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5323 }
5324
5325 alu.last = (j == 3);
5326 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5327 return r;
5328 }
5329 } else {
5330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5331 alu.op = ALU_OP2_MULLO_UINT;
5332
5333 alu.dst.sel = tmp0;
5334 alu.dst.chan = 2;
5335 alu.dst.write = 1;
5336
5337 alu.src[0].sel = tmp0;
5338 alu.src[0].chan = 0;
5339 if (signed_op) {
5340 alu.src[1].sel = tmp2;
5341 alu.src[1].chan = 1;
5342 } else {
5343 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5344 }
5345
5346 alu.last = 1;
5347 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5348 return r;
5349 }
5350
5351 /* 3. tmp0.w = -tmp0.z */
5352 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5353 alu.op = ALU_OP2_SUB_INT;
5354
5355 alu.dst.sel = tmp0;
5356 alu.dst.chan = 3;
5357 alu.dst.write = 1;
5358
5359 alu.src[0].sel = V_SQ_ALU_SRC_0;
5360 alu.src[1].sel = tmp0;
5361 alu.src[1].chan = 2;
5362
5363 alu.last = 1;
5364 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5365 return r;
5366
5367 /* 4. tmp0.y = hi (tmp0.x * src2) */
5368 if (ctx->bc->chip_class == CAYMAN) {
5369 for (j = 0 ; j < 4; j++) {
5370 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5371 alu.op = ALU_OP2_MULHI_UINT;
5372
5373 alu.dst.sel = tmp0;
5374 alu.dst.chan = j;
5375 alu.dst.write = (j == 1);
5376
5377 alu.src[0].sel = tmp0;
5378 alu.src[0].chan = 0;
5379
5380 if (signed_op) {
5381 alu.src[1].sel = tmp2;
5382 alu.src[1].chan = 1;
5383 } else {
5384 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5385 }
5386 alu.last = (j == 3);
5387 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5388 return r;
5389 }
5390 } else {
5391 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5392 alu.op = ALU_OP2_MULHI_UINT;
5393
5394 alu.dst.sel = tmp0;
5395 alu.dst.chan = 1;
5396 alu.dst.write = 1;
5397
5398 alu.src[0].sel = tmp0;
5399 alu.src[0].chan = 0;
5400
5401 if (signed_op) {
5402 alu.src[1].sel = tmp2;
5403 alu.src[1].chan = 1;
5404 } else {
5405 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5406 }
5407
5408 alu.last = 1;
5409 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5410 return r;
5411 }
5412
5413 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5414 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5415 alu.op = ALU_OP3_CNDE_INT;
5416 alu.is_op3 = 1;
5417
5418 alu.dst.sel = tmp0;
5419 alu.dst.chan = 2;
5420 alu.dst.write = 1;
5421
5422 alu.src[0].sel = tmp0;
5423 alu.src[0].chan = 1;
5424 alu.src[1].sel = tmp0;
5425 alu.src[1].chan = 3;
5426 alu.src[2].sel = tmp0;
5427 alu.src[2].chan = 2;
5428
5429 alu.last = 1;
5430 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5431 return r;
5432
5433 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5434 if (ctx->bc->chip_class == CAYMAN) {
5435 for (j = 0 ; j < 4; j++) {
5436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5437 alu.op = ALU_OP2_MULHI_UINT;
5438
5439 alu.dst.sel = tmp0;
5440 alu.dst.chan = j;
5441 alu.dst.write = (j == 3);
5442
5443 alu.src[0].sel = tmp0;
5444 alu.src[0].chan = 2;
5445
5446 alu.src[1].sel = tmp0;
5447 alu.src[1].chan = 0;
5448
5449 alu.last = (j == 3);
5450 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5451 return r;
5452 }
5453 } else {
5454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5455 alu.op = ALU_OP2_MULHI_UINT;
5456
5457 alu.dst.sel = tmp0;
5458 alu.dst.chan = 3;
5459 alu.dst.write = 1;
5460
5461 alu.src[0].sel = tmp0;
5462 alu.src[0].chan = 2;
5463
5464 alu.src[1].sel = tmp0;
5465 alu.src[1].chan = 0;
5466
5467 alu.last = 1;
5468 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5469 return r;
5470 }
5471
5472 /* 7. tmp1.x = tmp0.x - tmp0.w */
5473 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5474 alu.op = ALU_OP2_SUB_INT;
5475
5476 alu.dst.sel = tmp1;
5477 alu.dst.chan = 0;
5478 alu.dst.write = 1;
5479
5480 alu.src[0].sel = tmp0;
5481 alu.src[0].chan = 0;
5482 alu.src[1].sel = tmp0;
5483 alu.src[1].chan = 3;
5484
5485 alu.last = 1;
5486 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5487 return r;
5488
5489 /* 8. tmp1.y = tmp0.x + tmp0.w */
5490 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5491 alu.op = ALU_OP2_ADD_INT;
5492
5493 alu.dst.sel = tmp1;
5494 alu.dst.chan = 1;
5495 alu.dst.write = 1;
5496
5497 alu.src[0].sel = tmp0;
5498 alu.src[0].chan = 0;
5499 alu.src[1].sel = tmp0;
5500 alu.src[1].chan = 3;
5501
5502 alu.last = 1;
5503 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5504 return r;
5505
5506 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5507 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5508 alu.op = ALU_OP3_CNDE_INT;
5509 alu.is_op3 = 1;
5510
5511 alu.dst.sel = tmp0;
5512 alu.dst.chan = 0;
5513 alu.dst.write = 1;
5514
5515 alu.src[0].sel = tmp0;
5516 alu.src[0].chan = 1;
5517 alu.src[1].sel = tmp1;
5518 alu.src[1].chan = 1;
5519 alu.src[2].sel = tmp1;
5520 alu.src[2].chan = 0;
5521
5522 alu.last = 1;
5523 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5524 return r;
5525
5526 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5527 if (ctx->bc->chip_class == CAYMAN) {
5528 for (j = 0 ; j < 4; j++) {
5529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5530 alu.op = ALU_OP2_MULHI_UINT;
5531
5532 alu.dst.sel = tmp0;
5533 alu.dst.chan = j;
5534 alu.dst.write = (j == 2);
5535
5536 alu.src[0].sel = tmp0;
5537 alu.src[0].chan = 0;
5538
5539 if (signed_op) {
5540 alu.src[1].sel = tmp2;
5541 alu.src[1].chan = 0;
5542 } else {
5543 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5544 }
5545
5546 alu.last = (j == 3);
5547 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5548 return r;
5549 }
5550 } else {
5551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5552 alu.op = ALU_OP2_MULHI_UINT;
5553
5554 alu.dst.sel = tmp0;
5555 alu.dst.chan = 2;
5556 alu.dst.write = 1;
5557
5558 alu.src[0].sel = tmp0;
5559 alu.src[0].chan = 0;
5560
5561 if (signed_op) {
5562 alu.src[1].sel = tmp2;
5563 alu.src[1].chan = 0;
5564 } else {
5565 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5566 }
5567
5568 alu.last = 1;
5569 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5570 return r;
5571 }
5572
5573 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5574 if (ctx->bc->chip_class == CAYMAN) {
5575 for (j = 0 ; j < 4; j++) {
5576 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5577 alu.op = ALU_OP2_MULLO_UINT;
5578
5579 alu.dst.sel = tmp0;
5580 alu.dst.chan = j;
5581 alu.dst.write = (j == 1);
5582
5583 if (signed_op) {
5584 alu.src[0].sel = tmp2;
5585 alu.src[0].chan = 1;
5586 } else {
5587 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5588 }
5589
5590 alu.src[1].sel = tmp0;
5591 alu.src[1].chan = 2;
5592
5593 alu.last = (j == 3);
5594 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5595 return r;
5596 }
5597 } else {
5598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5599 alu.op = ALU_OP2_MULLO_UINT;
5600
5601 alu.dst.sel = tmp0;
5602 alu.dst.chan = 1;
5603 alu.dst.write = 1;
5604
5605 if (signed_op) {
5606 alu.src[0].sel = tmp2;
5607 alu.src[0].chan = 1;
5608 } else {
5609 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5610 }
5611
5612 alu.src[1].sel = tmp0;
5613 alu.src[1].chan = 2;
5614
5615 alu.last = 1;
5616 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5617 return r;
5618 }
5619
5620 /* 12. tmp0.w = src1 - tmp0.y = r */
5621 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5622 alu.op = ALU_OP2_SUB_INT;
5623
5624 alu.dst.sel = tmp0;
5625 alu.dst.chan = 3;
5626 alu.dst.write = 1;
5627
5628 if (signed_op) {
5629 alu.src[0].sel = tmp2;
5630 alu.src[0].chan = 0;
5631 } else {
5632 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5633 }
5634
5635 alu.src[1].sel = tmp0;
5636 alu.src[1].chan = 1;
5637
5638 alu.last = 1;
5639 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5640 return r;
5641
5642 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5643 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5644 alu.op = ALU_OP2_SETGE_UINT;
5645
5646 alu.dst.sel = tmp1;
5647 alu.dst.chan = 0;
5648 alu.dst.write = 1;
5649
5650 alu.src[0].sel = tmp0;
5651 alu.src[0].chan = 3;
5652 if (signed_op) {
5653 alu.src[1].sel = tmp2;
5654 alu.src[1].chan = 1;
5655 } else {
5656 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5657 }
5658
5659 alu.last = 1;
5660 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5661 return r;
5662
5663 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5665 alu.op = ALU_OP2_SETGE_UINT;
5666
5667 alu.dst.sel = tmp1;
5668 alu.dst.chan = 1;
5669 alu.dst.write = 1;
5670
5671 if (signed_op) {
5672 alu.src[0].sel = tmp2;
5673 alu.src[0].chan = 0;
5674 } else {
5675 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5676 }
5677
5678 alu.src[1].sel = tmp0;
5679 alu.src[1].chan = 1;
5680
5681 alu.last = 1;
5682 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5683 return r;
5684
5685 if (mod) { /* UMOD */
5686
5687 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5688 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5689 alu.op = ALU_OP2_SUB_INT;
5690
5691 alu.dst.sel = tmp1;
5692 alu.dst.chan = 2;
5693 alu.dst.write = 1;
5694
5695 alu.src[0].sel = tmp0;
5696 alu.src[0].chan = 3;
5697
5698 if (signed_op) {
5699 alu.src[1].sel = tmp2;
5700 alu.src[1].chan = 1;
5701 } else {
5702 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5703 }
5704
5705 alu.last = 1;
5706 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5707 return r;
5708
5709 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5711 alu.op = ALU_OP2_ADD_INT;
5712
5713 alu.dst.sel = tmp1;
5714 alu.dst.chan = 3;
5715 alu.dst.write = 1;
5716
5717 alu.src[0].sel = tmp0;
5718 alu.src[0].chan = 3;
5719 if (signed_op) {
5720 alu.src[1].sel = tmp2;
5721 alu.src[1].chan = 1;
5722 } else {
5723 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5724 }
5725
5726 alu.last = 1;
5727 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5728 return r;
5729
5730 } else { /* UDIV */
5731
5732 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5734 alu.op = ALU_OP2_ADD_INT;
5735
5736 alu.dst.sel = tmp1;
5737 alu.dst.chan = 2;
5738 alu.dst.write = 1;
5739
5740 alu.src[0].sel = tmp0;
5741 alu.src[0].chan = 2;
5742 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5743
5744 alu.last = 1;
5745 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5746 return r;
5747
5748 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5750 alu.op = ALU_OP2_ADD_INT;
5751
5752 alu.dst.sel = tmp1;
5753 alu.dst.chan = 3;
5754 alu.dst.write = 1;
5755
5756 alu.src[0].sel = tmp0;
5757 alu.src[0].chan = 2;
5758 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5759
5760 alu.last = 1;
5761 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5762 return r;
5763
5764 }
5765
5766 /* 17. tmp1.x = tmp1.x & tmp1.y */
5767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5768 alu.op = ALU_OP2_AND_INT;
5769
5770 alu.dst.sel = tmp1;
5771 alu.dst.chan = 0;
5772 alu.dst.write = 1;
5773
5774 alu.src[0].sel = tmp1;
5775 alu.src[0].chan = 0;
5776 alu.src[1].sel = tmp1;
5777 alu.src[1].chan = 1;
5778
5779 alu.last = 1;
5780 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5781 return r;
5782
5783 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5784 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5785 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5786 alu.op = ALU_OP3_CNDE_INT;
5787 alu.is_op3 = 1;
5788
5789 alu.dst.sel = tmp0;
5790 alu.dst.chan = 2;
5791 alu.dst.write = 1;
5792
5793 alu.src[0].sel = tmp1;
5794 alu.src[0].chan = 0;
5795 alu.src[1].sel = tmp0;
5796 alu.src[1].chan = mod ? 3 : 2;
5797 alu.src[2].sel = tmp1;
5798 alu.src[2].chan = 2;
5799
5800 alu.last = 1;
5801 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5802 return r;
5803
5804 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5806 alu.op = ALU_OP3_CNDE_INT;
5807 alu.is_op3 = 1;
5808
5809 if (signed_op) {
5810 alu.dst.sel = tmp0;
5811 alu.dst.chan = 2;
5812 alu.dst.write = 1;
5813 } else {
5814 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5815 }
5816
5817 alu.src[0].sel = tmp1;
5818 alu.src[0].chan = 1;
5819 alu.src[1].sel = tmp1;
5820 alu.src[1].chan = 3;
5821 alu.src[2].sel = tmp0;
5822 alu.src[2].chan = 2;
5823
5824 alu.last = 1;
5825 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5826 return r;
5827
5828 if (signed_op) {
5829
5830 /* fix the sign of the result */
5831
5832 if (mod) {
5833
5834 /* tmp0.x = -tmp0.z */
5835 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5836 alu.op = ALU_OP2_SUB_INT;
5837
5838 alu.dst.sel = tmp0;
5839 alu.dst.chan = 0;
5840 alu.dst.write = 1;
5841
5842 alu.src[0].sel = V_SQ_ALU_SRC_0;
5843 alu.src[1].sel = tmp0;
5844 alu.src[1].chan = 2;
5845
5846 alu.last = 1;
5847 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5848 return r;
5849
5850 /* sign of the remainder is the same as the sign of src0 */
5851 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5852 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5853 alu.op = ALU_OP3_CNDGE_INT;
5854 alu.is_op3 = 1;
5855
5856 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5857
5858 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5859 alu.src[1].sel = tmp0;
5860 alu.src[1].chan = 2;
5861 alu.src[2].sel = tmp0;
5862 alu.src[2].chan = 0;
5863
5864 alu.last = 1;
5865 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5866 return r;
5867
5868 } else {
5869
5870 /* tmp0.x = -tmp0.z */
5871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5872 alu.op = ALU_OP2_SUB_INT;
5873
5874 alu.dst.sel = tmp0;
5875 alu.dst.chan = 0;
5876 alu.dst.write = 1;
5877
5878 alu.src[0].sel = V_SQ_ALU_SRC_0;
5879 alu.src[1].sel = tmp0;
5880 alu.src[1].chan = 2;
5881
5882 alu.last = 1;
5883 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5884 return r;
5885
5886 /* fix the quotient sign (same as the sign of src0*src1) */
5887 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5888 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5889 alu.op = ALU_OP3_CNDGE_INT;
5890 alu.is_op3 = 1;
5891
5892 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5893
5894 alu.src[0].sel = tmp2;
5895 alu.src[0].chan = 2;
5896 alu.src[1].sel = tmp0;
5897 alu.src[1].chan = 2;
5898 alu.src[2].sel = tmp0;
5899 alu.src[2].chan = 0;
5900
5901 alu.last = 1;
5902 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5903 return r;
5904 }
5905 }
5906 }
5907 return 0;
5908 }
5909
5910 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5911 {
5912 return tgsi_divmod(ctx, 0, 0);
5913 }
5914
5915 static int tgsi_umod(struct r600_shader_ctx *ctx)
5916 {
5917 return tgsi_divmod(ctx, 1, 0);
5918 }
5919
5920 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5921 {
5922 return tgsi_divmod(ctx, 0, 1);
5923 }
5924
5925 static int tgsi_imod(struct r600_shader_ctx *ctx)
5926 {
5927 return tgsi_divmod(ctx, 1, 1);
5928 }
5929
5930
5931 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5932 {
5933 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5934 struct r600_bytecode_alu alu;
5935 int i, r;
5936 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5937 int last_inst = tgsi_last_instruction(write_mask);
5938
5939 for (i = 0; i < 4; i++) {
5940 if (!(write_mask & (1<<i)))
5941 continue;
5942
5943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5944 alu.op = ALU_OP1_TRUNC;
5945
5946 alu.dst.sel = ctx->temp_reg;
5947 alu.dst.chan = i;
5948 alu.dst.write = 1;
5949
5950 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5951 if (i == last_inst)
5952 alu.last = 1;
5953 r = r600_bytecode_add_alu(ctx->bc, &alu);
5954 if (r)
5955 return r;
5956 }
5957
5958 for (i = 0; i < 4; i++) {
5959 if (!(write_mask & (1<<i)))
5960 continue;
5961
5962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5963 alu.op = ctx->inst_info->op;
5964
5965 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5966
5967 alu.src[0].sel = ctx->temp_reg;
5968 alu.src[0].chan = i;
5969
5970 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5971 alu.last = 1;
5972 r = r600_bytecode_add_alu(ctx->bc, &alu);
5973 if (r)
5974 return r;
5975 }
5976
5977 return 0;
5978 }
5979
5980 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5981 {
5982 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5983 struct r600_bytecode_alu alu;
5984 int i, r;
5985 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5986 int last_inst = tgsi_last_instruction(write_mask);
5987
5988 /* tmp = -src */
5989 for (i = 0; i < 4; i++) {
5990 if (!(write_mask & (1<<i)))
5991 continue;
5992
5993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5994 alu.op = ALU_OP2_SUB_INT;
5995
5996 alu.dst.sel = ctx->temp_reg;
5997 alu.dst.chan = i;
5998 alu.dst.write = 1;
5999
6000 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6001 alu.src[0].sel = V_SQ_ALU_SRC_0;
6002
6003 if (i == last_inst)
6004 alu.last = 1;
6005 r = r600_bytecode_add_alu(ctx->bc, &alu);
6006 if (r)
6007 return r;
6008 }
6009
6010 /* dst = (src >= 0 ? src : tmp) */
6011 for (i = 0; i < 4; i++) {
6012 if (!(write_mask & (1<<i)))
6013 continue;
6014
6015 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6016 alu.op = ALU_OP3_CNDGE_INT;
6017 alu.is_op3 = 1;
6018 alu.dst.write = 1;
6019
6020 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6021
6022 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6023 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6024 alu.src[2].sel = ctx->temp_reg;
6025 alu.src[2].chan = i;
6026
6027 if (i == last_inst)
6028 alu.last = 1;
6029 r = r600_bytecode_add_alu(ctx->bc, &alu);
6030 if (r)
6031 return r;
6032 }
6033 return 0;
6034 }
6035
6036 static int tgsi_issg(struct r600_shader_ctx *ctx)
6037 {
6038 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6039 struct r600_bytecode_alu alu;
6040 int i, r;
6041 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6042 int last_inst = tgsi_last_instruction(write_mask);
6043
6044 /* tmp = (src >= 0 ? src : -1) */
6045 for (i = 0; i < 4; i++) {
6046 if (!(write_mask & (1<<i)))
6047 continue;
6048
6049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6050 alu.op = ALU_OP3_CNDGE_INT;
6051 alu.is_op3 = 1;
6052
6053 alu.dst.sel = ctx->temp_reg;
6054 alu.dst.chan = i;
6055 alu.dst.write = 1;
6056
6057 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6058 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6059 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6060
6061 if (i == last_inst)
6062 alu.last = 1;
6063 r = r600_bytecode_add_alu(ctx->bc, &alu);
6064 if (r)
6065 return r;
6066 }
6067
6068 /* dst = (tmp > 0 ? 1 : tmp) */
6069 for (i = 0; i < 4; i++) {
6070 if (!(write_mask & (1<<i)))
6071 continue;
6072
6073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6074 alu.op = ALU_OP3_CNDGT_INT;
6075 alu.is_op3 = 1;
6076 alu.dst.write = 1;
6077
6078 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6079
6080 alu.src[0].sel = ctx->temp_reg;
6081 alu.src[0].chan = i;
6082
6083 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6084
6085 alu.src[2].sel = ctx->temp_reg;
6086 alu.src[2].chan = i;
6087
6088 if (i == last_inst)
6089 alu.last = 1;
6090 r = r600_bytecode_add_alu(ctx->bc, &alu);
6091 if (r)
6092 return r;
6093 }
6094 return 0;
6095 }
6096
6097
6098
6099 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6100 {
6101 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6102 struct r600_bytecode_alu alu;
6103 int i, r;
6104
6105 /* tmp = (src > 0 ? 1 : src) */
6106 for (i = 0; i < 4; i++) {
6107 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6108 alu.op = ALU_OP3_CNDGT;
6109 alu.is_op3 = 1;
6110
6111 alu.dst.sel = ctx->temp_reg;
6112 alu.dst.chan = i;
6113
6114 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6115 alu.src[1].sel = V_SQ_ALU_SRC_1;
6116 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6117
6118 if (i == 3)
6119 alu.last = 1;
6120 r = r600_bytecode_add_alu(ctx->bc, &alu);
6121 if (r)
6122 return r;
6123 }
6124
6125 /* dst = (-tmp > 0 ? -1 : tmp) */
6126 for (i = 0; i < 4; i++) {
6127 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6128 alu.op = ALU_OP3_CNDGT;
6129 alu.is_op3 = 1;
6130 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6131
6132 alu.src[0].sel = ctx->temp_reg;
6133 alu.src[0].chan = i;
6134 alu.src[0].neg = 1;
6135
6136 alu.src[1].sel = V_SQ_ALU_SRC_1;
6137 alu.src[1].neg = 1;
6138
6139 alu.src[2].sel = ctx->temp_reg;
6140 alu.src[2].chan = i;
6141
6142 if (i == 3)
6143 alu.last = 1;
6144 r = r600_bytecode_add_alu(ctx->bc, &alu);
6145 if (r)
6146 return r;
6147 }
6148 return 0;
6149 }
6150
6151 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6152 {
6153 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6154 struct r600_bytecode_alu alu;
6155 int i, r, t1, t2;
6156
6157 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6158 int last_inst = tgsi_last_instruction(write_mask);
6159
6160 t1 = ctx->temp_reg;
6161
6162 for (i = 0; i < 4; i++) {
6163 if (!(write_mask & (1<<i)))
6164 continue;
6165
6166 /* create mask tmp */
6167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6168 alu.op = ALU_OP2_BFM_INT;
6169 alu.dst.sel = t1;
6170 alu.dst.chan = i;
6171 alu.dst.write = 1;
6172 alu.last = i == last_inst;
6173
6174 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6175 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6176
6177 r = r600_bytecode_add_alu(ctx->bc, &alu);
6178 if (r)
6179 return r;
6180 }
6181
6182 t2 = r600_get_temp(ctx);
6183
6184 for (i = 0; i < 4; i++) {
6185 if (!(write_mask & (1<<i)))
6186 continue;
6187
6188 /* shift insert left */
6189 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6190 alu.op = ALU_OP2_LSHL_INT;
6191 alu.dst.sel = t2;
6192 alu.dst.chan = i;
6193 alu.dst.write = 1;
6194 alu.last = i == last_inst;
6195
6196 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6197 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6198
6199 r = r600_bytecode_add_alu(ctx->bc, &alu);
6200 if (r)
6201 return r;
6202 }
6203
6204 for (i = 0; i < 4; i++) {
6205 if (!(write_mask & (1<<i)))
6206 continue;
6207
6208 /* actual bitfield insert */
6209 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6210 alu.op = ALU_OP3_BFI_INT;
6211 alu.is_op3 = 1;
6212 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6213 alu.dst.chan = i;
6214 alu.dst.write = 1;
6215 alu.last = i == last_inst;
6216
6217 alu.src[0].sel = t1;
6218 alu.src[0].chan = i;
6219 alu.src[1].sel = t2;
6220 alu.src[1].chan = i;
6221 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6222
6223 r = r600_bytecode_add_alu(ctx->bc, &alu);
6224 if (r)
6225 return r;
6226 }
6227
6228 return 0;
6229 }
6230
6231 static int tgsi_msb(struct r600_shader_ctx *ctx)
6232 {
6233 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6234 struct r600_bytecode_alu alu;
6235 int i, r, t1, t2;
6236
6237 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6238 int last_inst = tgsi_last_instruction(write_mask);
6239
6240 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6241 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6242
6243 t1 = ctx->temp_reg;
6244
6245 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6246 for (i = 0; i < 4; i++) {
6247 if (!(write_mask & (1<<i)))
6248 continue;
6249
6250 /* t1 = FFBH_INT / FFBH_UINT */
6251 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6252 alu.op = ctx->inst_info->op;
6253 alu.dst.sel = t1;
6254 alu.dst.chan = i;
6255 alu.dst.write = 1;
6256 alu.last = i == last_inst;
6257
6258 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6259
6260 r = r600_bytecode_add_alu(ctx->bc, &alu);
6261 if (r)
6262 return r;
6263 }
6264
6265 t2 = r600_get_temp(ctx);
6266
6267 for (i = 0; i < 4; i++) {
6268 if (!(write_mask & (1<<i)))
6269 continue;
6270
6271 /* t2 = 31 - t1 */
6272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6273 alu.op = ALU_OP2_SUB_INT;
6274 alu.dst.sel = t2;
6275 alu.dst.chan = i;
6276 alu.dst.write = 1;
6277 alu.last = i == last_inst;
6278
6279 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6280 alu.src[0].value = 31;
6281 alu.src[1].sel = t1;
6282 alu.src[1].chan = i;
6283
6284 r = r600_bytecode_add_alu(ctx->bc, &alu);
6285 if (r)
6286 return r;
6287 }
6288
6289 for (i = 0; i < 4; i++) {
6290 if (!(write_mask & (1<<i)))
6291 continue;
6292
6293 /* result = t1 >= 0 ? t2 : t1 */
6294 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6295 alu.op = ALU_OP3_CNDGE_INT;
6296 alu.is_op3 = 1;
6297 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6298 alu.dst.chan = i;
6299 alu.dst.write = 1;
6300 alu.last = i == last_inst;
6301
6302 alu.src[0].sel = t1;
6303 alu.src[0].chan = i;
6304 alu.src[1].sel = t2;
6305 alu.src[1].chan = i;
6306 alu.src[2].sel = t1;
6307 alu.src[2].chan = i;
6308
6309 r = r600_bytecode_add_alu(ctx->bc, &alu);
6310 if (r)
6311 return r;
6312 }
6313
6314 return 0;
6315 }
6316
6317 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6318 {
6319 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6320 struct r600_bytecode_alu alu;
6321 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6322 unsigned location;
6323 int input;
6324
6325 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6326
6327 input = inst->Src[0].Register.Index;
6328
6329 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6330 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6331 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6332 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6333 }
6334 else {
6335 location = TGSI_INTERPOLATE_LOC_CENTROID;
6336 }
6337
6338 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6339 if (k < 0)
6340 k = 0;
6341 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6342 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6343
6344 /* NOTE: currently offset is not perspective correct */
6345 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6346 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6347 int sample_gpr = -1;
6348 int gradientsH, gradientsV;
6349 struct r600_bytecode_tex tex;
6350
6351 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6352 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6353 }
6354
6355 gradientsH = r600_get_temp(ctx);
6356 gradientsV = r600_get_temp(ctx);
6357 for (i = 0; i < 2; i++) {
6358 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6359 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6360 tex.src_gpr = interp_gpr;
6361 tex.src_sel_x = interp_base_chan + 0;
6362 tex.src_sel_y = interp_base_chan + 1;
6363 tex.src_sel_z = 0;
6364 tex.src_sel_w = 0;
6365 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6366 tex.dst_sel_x = 0;
6367 tex.dst_sel_y = 1;
6368 tex.dst_sel_z = 7;
6369 tex.dst_sel_w = 7;
6370 tex.inst_mod = 1; // Use per pixel gradient calculation
6371 tex.sampler_id = 0;
6372 tex.resource_id = tex.sampler_id;
6373 r = r600_bytecode_add_tex(ctx->bc, &tex);
6374 if (r)
6375 return r;
6376 }
6377
6378 for (i = 0; i < 2; i++) {
6379 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6380 alu.op = ALU_OP3_MULADD;
6381 alu.is_op3 = 1;
6382 alu.src[0].sel = gradientsH;
6383 alu.src[0].chan = i;
6384 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6385 alu.src[1].sel = sample_gpr;
6386 alu.src[1].chan = 2;
6387 }
6388 else {
6389 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6390 }
6391 alu.src[2].sel = interp_gpr;
6392 alu.src[2].chan = interp_base_chan + i;
6393 alu.dst.sel = ctx->temp_reg;
6394 alu.dst.chan = i;
6395 alu.last = i == 1;
6396
6397 r = r600_bytecode_add_alu(ctx->bc, &alu);
6398 if (r)
6399 return r;
6400 }
6401
6402 for (i = 0; i < 2; i++) {
6403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6404 alu.op = ALU_OP3_MULADD;
6405 alu.is_op3 = 1;
6406 alu.src[0].sel = gradientsV;
6407 alu.src[0].chan = i;
6408 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6409 alu.src[1].sel = sample_gpr;
6410 alu.src[1].chan = 3;
6411 }
6412 else {
6413 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6414 }
6415 alu.src[2].sel = ctx->temp_reg;
6416 alu.src[2].chan = i;
6417 alu.dst.sel = ctx->temp_reg;
6418 alu.dst.chan = i;
6419 alu.last = i == 1;
6420
6421 r = r600_bytecode_add_alu(ctx->bc, &alu);
6422 if (r)
6423 return r;
6424 }
6425 }
6426
6427 tmp = r600_get_temp(ctx);
6428 for (i = 0; i < 8; i++) {
6429 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6430 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6431
6432 alu.dst.sel = tmp;
6433 if ((i > 1 && i < 6)) {
6434 alu.dst.write = 1;
6435 }
6436 else {
6437 alu.dst.write = 0;
6438 }
6439 alu.dst.chan = i % 4;
6440
6441 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6442 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6443 alu.src[0].sel = ctx->temp_reg;
6444 alu.src[0].chan = 1 - (i % 2);
6445 } else {
6446 alu.src[0].sel = interp_gpr;
6447 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6448 }
6449 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6450 alu.src[1].chan = 0;
6451
6452 alu.last = i % 4 == 3;
6453 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6454
6455 r = r600_bytecode_add_alu(ctx->bc, &alu);
6456 if (r)
6457 return r;
6458 }
6459
6460 // INTERP can't swizzle dst
6461 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6462 for (i = 0; i <= lasti; i++) {
6463 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6464 continue;
6465
6466 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6467 alu.op = ALU_OP1_MOV;
6468 alu.src[0].sel = tmp;
6469 alu.src[0].chan = ctx->src[0].swizzle[i];
6470 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6471 alu.dst.write = 1;
6472 alu.last = i == lasti;
6473 r = r600_bytecode_add_alu(ctx->bc, &alu);
6474 if (r)
6475 return r;
6476 }
6477
6478 return 0;
6479 }
6480
6481
6482 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6483 {
6484 struct r600_bytecode_alu alu;
6485 int i, r;
6486
6487 for (i = 0; i < 4; i++) {
6488 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6489 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6490 alu.op = ALU_OP0_NOP;
6491 alu.dst.chan = i;
6492 } else {
6493 alu.op = ALU_OP1_MOV;
6494 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6495 alu.src[0].sel = ctx->temp_reg;
6496 alu.src[0].chan = i;
6497 }
6498 if (i == 3) {
6499 alu.last = 1;
6500 }
6501 r = r600_bytecode_add_alu(ctx->bc, &alu);
6502 if (r)
6503 return r;
6504 }
6505 return 0;
6506 }
6507
6508 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6509 unsigned temp, int chan,
6510 struct r600_bytecode_alu_src *bc_src,
6511 const struct r600_shader_src *shader_src)
6512 {
6513 struct r600_bytecode_alu alu;
6514 int r;
6515
6516 r600_bytecode_src(bc_src, shader_src, chan);
6517
6518 /* op3 operands don't support abs modifier */
6519 if (bc_src->abs) {
6520 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6521 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6522 alu.op = ALU_OP1_MOV;
6523 alu.dst.sel = temp;
6524 alu.dst.chan = chan;
6525 alu.dst.write = 1;
6526
6527 alu.src[0] = *bc_src;
6528 alu.last = true; // sufficient?
6529 r = r600_bytecode_add_alu(ctx->bc, &alu);
6530 if (r)
6531 return r;
6532
6533 memset(bc_src, 0, sizeof(*bc_src));
6534 bc_src->sel = temp;
6535 bc_src->chan = chan;
6536 }
6537 return 0;
6538 }
6539
6540 static int tgsi_op3(struct r600_shader_ctx *ctx)
6541 {
6542 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6543 struct r600_bytecode_alu alu;
6544 int i, j, r;
6545 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6546 int temp_regs[4];
6547
6548 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6549 temp_regs[j] = 0;
6550 if (ctx->src[j].abs)
6551 temp_regs[j] = r600_get_temp(ctx);
6552 }
6553 for (i = 0; i < lasti + 1; i++) {
6554 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6555 continue;
6556
6557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6558 alu.op = ctx->inst_info->op;
6559 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6560 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6561 if (r)
6562 return r;
6563 }
6564
6565 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6566 alu.dst.chan = i;
6567 alu.dst.write = 1;
6568 alu.is_op3 = 1;
6569 if (i == lasti) {
6570 alu.last = 1;
6571 }
6572 r = r600_bytecode_add_alu(ctx->bc, &alu);
6573 if (r)
6574 return r;
6575 }
6576 return 0;
6577 }
6578
6579 static int tgsi_dp(struct r600_shader_ctx *ctx)
6580 {
6581 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6582 struct r600_bytecode_alu alu;
6583 int i, j, r;
6584
6585 for (i = 0; i < 4; i++) {
6586 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6587 alu.op = ctx->inst_info->op;
6588 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6589 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6590 }
6591
6592 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6593 alu.dst.chan = i;
6594 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6595 /* handle some special cases */
6596 switch (inst->Instruction.Opcode) {
6597 case TGSI_OPCODE_DP2:
6598 if (i > 1) {
6599 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6600 alu.src[0].chan = alu.src[1].chan = 0;
6601 }
6602 break;
6603 case TGSI_OPCODE_DP3:
6604 if (i > 2) {
6605 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6606 alu.src[0].chan = alu.src[1].chan = 0;
6607 }
6608 break;
6609 case TGSI_OPCODE_DPH:
6610 if (i == 3) {
6611 alu.src[0].sel = V_SQ_ALU_SRC_1;
6612 alu.src[0].chan = 0;
6613 alu.src[0].neg = 0;
6614 }
6615 break;
6616 default:
6617 break;
6618 }
6619 if (i == 3) {
6620 alu.last = 1;
6621 }
6622 r = r600_bytecode_add_alu(ctx->bc, &alu);
6623 if (r)
6624 return r;
6625 }
6626 return 0;
6627 }
6628
6629 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6630 unsigned index)
6631 {
6632 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6633 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6634 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6635 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6636 ctx->src[index].neg || ctx->src[index].abs ||
6637 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
6638 }
6639
6640 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6641 unsigned index)
6642 {
6643 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6644 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6645 }
6646
6647 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6648 {
6649 struct r600_bytecode_vtx vtx;
6650 struct r600_bytecode_alu alu;
6651 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6652 int src_gpr, r, i;
6653 int id = tgsi_tex_get_src_gpr(ctx, 1);
6654
6655 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6656 if (src_requires_loading) {
6657 for (i = 0; i < 4; i++) {
6658 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6659 alu.op = ALU_OP1_MOV;
6660 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6661 alu.dst.sel = ctx->temp_reg;
6662 alu.dst.chan = i;
6663 if (i == 3)
6664 alu.last = 1;
6665 alu.dst.write = 1;
6666 r = r600_bytecode_add_alu(ctx->bc, &alu);
6667 if (r)
6668 return r;
6669 }
6670 src_gpr = ctx->temp_reg;
6671 }
6672
6673 memset(&vtx, 0, sizeof(vtx));
6674 vtx.op = FETCH_OP_VFETCH;
6675 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6676 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6677 vtx.src_gpr = src_gpr;
6678 vtx.mega_fetch_count = 16;
6679 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6680 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6681 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6682 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6683 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6684 vtx.use_const_fields = 1;
6685
6686 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6687 return r;
6688
6689 if (ctx->bc->chip_class >= EVERGREEN)
6690 return 0;
6691
6692 for (i = 0; i < 4; i++) {
6693 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6694 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6695 continue;
6696
6697 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6698 alu.op = ALU_OP2_AND_INT;
6699
6700 alu.dst.chan = i;
6701 alu.dst.sel = vtx.dst_gpr;
6702 alu.dst.write = 1;
6703
6704 alu.src[0].sel = vtx.dst_gpr;
6705 alu.src[0].chan = i;
6706
6707 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6708 alu.src[1].sel += (id * 2);
6709 alu.src[1].chan = i % 4;
6710 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6711
6712 if (i == lasti)
6713 alu.last = 1;
6714 r = r600_bytecode_add_alu(ctx->bc, &alu);
6715 if (r)
6716 return r;
6717 }
6718
6719 if (inst->Dst[0].Register.WriteMask & 3) {
6720 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6721 alu.op = ALU_OP2_OR_INT;
6722
6723 alu.dst.chan = 3;
6724 alu.dst.sel = vtx.dst_gpr;
6725 alu.dst.write = 1;
6726
6727 alu.src[0].sel = vtx.dst_gpr;
6728 alu.src[0].chan = 3;
6729
6730 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6731 alu.src[1].chan = 0;
6732 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6733
6734 alu.last = 1;
6735 r = r600_bytecode_add_alu(ctx->bc, &alu);
6736 if (r)
6737 return r;
6738 }
6739 return 0;
6740 }
6741
6742 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6743 {
6744 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6745 struct r600_bytecode_alu alu;
6746 int r;
6747 int id = tgsi_tex_get_src_gpr(ctx, 1);
6748
6749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6750 alu.op = ALU_OP1_MOV;
6751 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6752 if (ctx->bc->chip_class >= EVERGREEN) {
6753 /* channel 0 or 2 of each word */
6754 alu.src[0].sel += (id / 2);
6755 alu.src[0].chan = (id % 2) * 2;
6756 } else {
6757 /* r600 we have them at channel 2 of the second dword */
6758 alu.src[0].sel += (id * 2) + 1;
6759 alu.src[0].chan = 1;
6760 }
6761 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6762 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6763 alu.last = 1;
6764 r = r600_bytecode_add_alu(ctx->bc, &alu);
6765 if (r)
6766 return r;
6767 return 0;
6768 }
6769
6770 static int tgsi_tex(struct r600_shader_ctx *ctx)
6771 {
6772 static float one_point_five = 1.5f;
6773 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6774 struct r600_bytecode_tex tex;
6775 struct r600_bytecode_alu alu;
6776 unsigned src_gpr;
6777 int r, i, j;
6778 int opcode;
6779 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6780 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6781 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6782 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6783
6784 bool txf_add_offsets = inst->Texture.NumOffsets &&
6785 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6786 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6787
6788 /* Texture fetch instructions can only use gprs as source.
6789 * Also they cannot negate the source or take the absolute value */
6790 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
6791 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6792 tgsi_tex_src_requires_loading(ctx, 0)) ||
6793 read_compressed_msaa || txf_add_offsets;
6794
6795 boolean src_loaded = FALSE;
6796 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
6797 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6798 boolean has_txq_cube_array_z = false;
6799 unsigned sampler_index_mode;
6800
6801 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6802 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6803 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6804 if (inst->Dst[0].Register.WriteMask & 4) {
6805 ctx->shader->has_txq_cube_array_z_comp = true;
6806 has_txq_cube_array_z = true;
6807 }
6808
6809 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6810 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6811 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6812 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6813 sampler_src_reg = 2;
6814
6815 /* TGSI moves the sampler to src reg 3 for TXD */
6816 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6817 sampler_src_reg = 3;
6818
6819 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6820
6821 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6822
6823 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6824 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6825 ctx->shader->uses_tex_buffers = true;
6826 return r600_do_buffer_txq(ctx);
6827 }
6828 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6829 if (ctx->bc->chip_class < EVERGREEN)
6830 ctx->shader->uses_tex_buffers = true;
6831 return do_vtx_fetch_inst(ctx, src_requires_loading);
6832 }
6833 }
6834
6835 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6836 int out_chan;
6837 /* Add perspective divide */
6838 if (ctx->bc->chip_class == CAYMAN) {
6839 out_chan = 2;
6840 for (i = 0; i < 3; i++) {
6841 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6842 alu.op = ALU_OP1_RECIP_IEEE;
6843 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6844
6845 alu.dst.sel = ctx->temp_reg;
6846 alu.dst.chan = i;
6847 if (i == 2)
6848 alu.last = 1;
6849 if (out_chan == i)
6850 alu.dst.write = 1;
6851 r = r600_bytecode_add_alu(ctx->bc, &alu);
6852 if (r)
6853 return r;
6854 }
6855
6856 } else {
6857 out_chan = 3;
6858 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6859 alu.op = ALU_OP1_RECIP_IEEE;
6860 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6861
6862 alu.dst.sel = ctx->temp_reg;
6863 alu.dst.chan = out_chan;
6864 alu.last = 1;
6865 alu.dst.write = 1;
6866 r = r600_bytecode_add_alu(ctx->bc, &alu);
6867 if (r)
6868 return r;
6869 }
6870
6871 for (i = 0; i < 3; i++) {
6872 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6873 alu.op = ALU_OP2_MUL;
6874 alu.src[0].sel = ctx->temp_reg;
6875 alu.src[0].chan = out_chan;
6876 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6877 alu.dst.sel = ctx->temp_reg;
6878 alu.dst.chan = i;
6879 alu.dst.write = 1;
6880 r = r600_bytecode_add_alu(ctx->bc, &alu);
6881 if (r)
6882 return r;
6883 }
6884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6885 alu.op = ALU_OP1_MOV;
6886 alu.src[0].sel = V_SQ_ALU_SRC_1;
6887 alu.src[0].chan = 0;
6888 alu.dst.sel = ctx->temp_reg;
6889 alu.dst.chan = 3;
6890 alu.last = 1;
6891 alu.dst.write = 1;
6892 r = r600_bytecode_add_alu(ctx->bc, &alu);
6893 if (r)
6894 return r;
6895 src_loaded = TRUE;
6896 src_gpr = ctx->temp_reg;
6897 }
6898
6899
6900 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6901 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6902 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6903 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6904 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
6905 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
6906
6907 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6908 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6909
6910 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6911 for (i = 0; i < 4; i++) {
6912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6913 alu.op = ALU_OP2_CUBE;
6914 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6915 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6916 alu.dst.sel = ctx->temp_reg;
6917 alu.dst.chan = i;
6918 if (i == 3)
6919 alu.last = 1;
6920 alu.dst.write = 1;
6921 r = r600_bytecode_add_alu(ctx->bc, &alu);
6922 if (r)
6923 return r;
6924 }
6925
6926 /* tmp1.z = RCP_e(|tmp1.z|) */
6927 if (ctx->bc->chip_class == CAYMAN) {
6928 for (i = 0; i < 3; i++) {
6929 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6930 alu.op = ALU_OP1_RECIP_IEEE;
6931 alu.src[0].sel = ctx->temp_reg;
6932 alu.src[0].chan = 2;
6933 alu.src[0].abs = 1;
6934 alu.dst.sel = ctx->temp_reg;
6935 alu.dst.chan = i;
6936 if (i == 2)
6937 alu.dst.write = 1;
6938 if (i == 2)
6939 alu.last = 1;
6940 r = r600_bytecode_add_alu(ctx->bc, &alu);
6941 if (r)
6942 return r;
6943 }
6944 } else {
6945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6946 alu.op = ALU_OP1_RECIP_IEEE;
6947 alu.src[0].sel = ctx->temp_reg;
6948 alu.src[0].chan = 2;
6949 alu.src[0].abs = 1;
6950 alu.dst.sel = ctx->temp_reg;
6951 alu.dst.chan = 2;
6952 alu.dst.write = 1;
6953 alu.last = 1;
6954 r = r600_bytecode_add_alu(ctx->bc, &alu);
6955 if (r)
6956 return r;
6957 }
6958
6959 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6960 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6961 * muladd has no writemask, have to use another temp
6962 */
6963 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6964 alu.op = ALU_OP3_MULADD;
6965 alu.is_op3 = 1;
6966
6967 alu.src[0].sel = ctx->temp_reg;
6968 alu.src[0].chan = 0;
6969 alu.src[1].sel = ctx->temp_reg;
6970 alu.src[1].chan = 2;
6971
6972 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6973 alu.src[2].chan = 0;
6974 alu.src[2].value = *(uint32_t *)&one_point_five;
6975
6976 alu.dst.sel = ctx->temp_reg;
6977 alu.dst.chan = 0;
6978 alu.dst.write = 1;
6979
6980 r = r600_bytecode_add_alu(ctx->bc, &alu);
6981 if (r)
6982 return r;
6983
6984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6985 alu.op = ALU_OP3_MULADD;
6986 alu.is_op3 = 1;
6987
6988 alu.src[0].sel = ctx->temp_reg;
6989 alu.src[0].chan = 1;
6990 alu.src[1].sel = ctx->temp_reg;
6991 alu.src[1].chan = 2;
6992
6993 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6994 alu.src[2].chan = 0;
6995 alu.src[2].value = *(uint32_t *)&one_point_five;
6996
6997 alu.dst.sel = ctx->temp_reg;
6998 alu.dst.chan = 1;
6999 alu.dst.write = 1;
7000
7001 alu.last = 1;
7002 r = r600_bytecode_add_alu(ctx->bc, &alu);
7003 if (r)
7004 return r;
7005 /* write initial compare value into Z component
7006 - W src 0 for shadow cube
7007 - X src 1 for shadow cube array */
7008 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7009 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7011 alu.op = ALU_OP1_MOV;
7012 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7013 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7014 else
7015 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7016 alu.dst.sel = ctx->temp_reg;
7017 alu.dst.chan = 2;
7018 alu.dst.write = 1;
7019 alu.last = 1;
7020 r = r600_bytecode_add_alu(ctx->bc, &alu);
7021 if (r)
7022 return r;
7023 }
7024
7025 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7026 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7027 if (ctx->bc->chip_class >= EVERGREEN) {
7028 int mytmp = r600_get_temp(ctx);
7029 static const float eight = 8.0f;
7030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7031 alu.op = ALU_OP1_MOV;
7032 alu.src[0].sel = ctx->temp_reg;
7033 alu.src[0].chan = 3;
7034 alu.dst.sel = mytmp;
7035 alu.dst.chan = 0;
7036 alu.dst.write = 1;
7037 alu.last = 1;
7038 r = r600_bytecode_add_alu(ctx->bc, &alu);
7039 if (r)
7040 return r;
7041
7042 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7044 alu.op = ALU_OP3_MULADD;
7045 alu.is_op3 = 1;
7046 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7047 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7048 alu.src[1].chan = 0;
7049 alu.src[1].value = *(uint32_t *)&eight;
7050 alu.src[2].sel = mytmp;
7051 alu.src[2].chan = 0;
7052 alu.dst.sel = ctx->temp_reg;
7053 alu.dst.chan = 3;
7054 alu.dst.write = 1;
7055 alu.last = 1;
7056 r = r600_bytecode_add_alu(ctx->bc, &alu);
7057 if (r)
7058 return r;
7059 } else if (ctx->bc->chip_class < EVERGREEN) {
7060 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7061 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7062 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7063 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7064 tex.src_gpr = r600_get_temp(ctx);
7065 tex.src_sel_x = 0;
7066 tex.src_sel_y = 0;
7067 tex.src_sel_z = 0;
7068 tex.src_sel_w = 0;
7069 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7070 tex.coord_type_x = 1;
7071 tex.coord_type_y = 1;
7072 tex.coord_type_z = 1;
7073 tex.coord_type_w = 1;
7074 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7075 alu.op = ALU_OP1_MOV;
7076 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7077 alu.dst.sel = tex.src_gpr;
7078 alu.dst.chan = 0;
7079 alu.last = 1;
7080 alu.dst.write = 1;
7081 r = r600_bytecode_add_alu(ctx->bc, &alu);
7082 if (r)
7083 return r;
7084
7085 r = r600_bytecode_add_tex(ctx->bc, &tex);
7086 if (r)
7087 return r;
7088 }
7089
7090 }
7091
7092 /* for cube forms of lod and bias we need to route things */
7093 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7094 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7095 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7096 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7098 alu.op = ALU_OP1_MOV;
7099 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7100 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7101 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7102 else
7103 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7104 alu.dst.sel = ctx->temp_reg;
7105 alu.dst.chan = 2;
7106 alu.last = 1;
7107 alu.dst.write = 1;
7108 r = r600_bytecode_add_alu(ctx->bc, &alu);
7109 if (r)
7110 return r;
7111 }
7112
7113 src_loaded = TRUE;
7114 src_gpr = ctx->temp_reg;
7115 }
7116
7117 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7118 int temp_h = 0, temp_v = 0;
7119 int start_val = 0;
7120
7121 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7122 if (src_loaded == TRUE)
7123 start_val = 1;
7124 else
7125 src_loaded = TRUE;
7126 for (i = start_val; i < 3; i++) {
7127 int treg = r600_get_temp(ctx);
7128
7129 if (i == 0)
7130 src_gpr = treg;
7131 else if (i == 1)
7132 temp_h = treg;
7133 else
7134 temp_v = treg;
7135
7136 for (j = 0; j < 4; j++) {
7137 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7138 alu.op = ALU_OP1_MOV;
7139 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7140 alu.dst.sel = treg;
7141 alu.dst.chan = j;
7142 if (j == 3)
7143 alu.last = 1;
7144 alu.dst.write = 1;
7145 r = r600_bytecode_add_alu(ctx->bc, &alu);
7146 if (r)
7147 return r;
7148 }
7149 }
7150 for (i = 1; i < 3; i++) {
7151 /* set gradients h/v */
7152 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7153 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7154 FETCH_OP_SET_GRADIENTS_V;
7155 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7156 tex.sampler_index_mode = sampler_index_mode;
7157 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7158 tex.resource_index_mode = sampler_index_mode;
7159
7160 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7161 tex.src_sel_x = 0;
7162 tex.src_sel_y = 1;
7163 tex.src_sel_z = 2;
7164 tex.src_sel_w = 3;
7165
7166 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7167 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7168 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7169 tex.coord_type_x = 1;
7170 tex.coord_type_y = 1;
7171 tex.coord_type_z = 1;
7172 tex.coord_type_w = 1;
7173 }
7174 r = r600_bytecode_add_tex(ctx->bc, &tex);
7175 if (r)
7176 return r;
7177 }
7178 }
7179
7180 if (src_requires_loading && !src_loaded) {
7181 for (i = 0; i < 4; i++) {
7182 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7183 alu.op = ALU_OP1_MOV;
7184 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7185 alu.dst.sel = ctx->temp_reg;
7186 alu.dst.chan = i;
7187 if (i == 3)
7188 alu.last = 1;
7189 alu.dst.write = 1;
7190 r = r600_bytecode_add_alu(ctx->bc, &alu);
7191 if (r)
7192 return r;
7193 }
7194 src_loaded = TRUE;
7195 src_gpr = ctx->temp_reg;
7196 }
7197
7198 /* get offset values */
7199 if (inst->Texture.NumOffsets) {
7200 assert(inst->Texture.NumOffsets == 1);
7201
7202 /* The texture offset feature doesn't work with the TXF instruction
7203 * and must be emulated by adding the offset to the texture coordinates. */
7204 if (txf_add_offsets) {
7205 const struct tgsi_texture_offset *off = inst->TexOffsets;
7206
7207 switch (inst->Texture.Texture) {
7208 case TGSI_TEXTURE_3D:
7209 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7210 alu.op = ALU_OP2_ADD_INT;
7211 alu.src[0].sel = src_gpr;
7212 alu.src[0].chan = 2;
7213 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7214 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7215 alu.dst.sel = src_gpr;
7216 alu.dst.chan = 2;
7217 alu.dst.write = 1;
7218 alu.last = 1;
7219 r = r600_bytecode_add_alu(ctx->bc, &alu);
7220 if (r)
7221 return r;
7222 /* fall through */
7223
7224 case TGSI_TEXTURE_2D:
7225 case TGSI_TEXTURE_SHADOW2D:
7226 case TGSI_TEXTURE_RECT:
7227 case TGSI_TEXTURE_SHADOWRECT:
7228 case TGSI_TEXTURE_2D_ARRAY:
7229 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7231 alu.op = ALU_OP2_ADD_INT;
7232 alu.src[0].sel = src_gpr;
7233 alu.src[0].chan = 1;
7234 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7235 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7236 alu.dst.sel = src_gpr;
7237 alu.dst.chan = 1;
7238 alu.dst.write = 1;
7239 alu.last = 1;
7240 r = r600_bytecode_add_alu(ctx->bc, &alu);
7241 if (r)
7242 return r;
7243 /* fall through */
7244
7245 case TGSI_TEXTURE_1D:
7246 case TGSI_TEXTURE_SHADOW1D:
7247 case TGSI_TEXTURE_1D_ARRAY:
7248 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7250 alu.op = ALU_OP2_ADD_INT;
7251 alu.src[0].sel = src_gpr;
7252 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7253 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7254 alu.dst.sel = src_gpr;
7255 alu.dst.write = 1;
7256 alu.last = 1;
7257 r = r600_bytecode_add_alu(ctx->bc, &alu);
7258 if (r)
7259 return r;
7260 break;
7261 /* texture offsets do not apply to other texture targets */
7262 }
7263 } else {
7264 switch (inst->Texture.Texture) {
7265 case TGSI_TEXTURE_3D:
7266 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7267 /* fallthrough */
7268 case TGSI_TEXTURE_2D:
7269 case TGSI_TEXTURE_SHADOW2D:
7270 case TGSI_TEXTURE_RECT:
7271 case TGSI_TEXTURE_SHADOWRECT:
7272 case TGSI_TEXTURE_2D_ARRAY:
7273 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7274 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7275 /* fallthrough */
7276 case TGSI_TEXTURE_1D:
7277 case TGSI_TEXTURE_SHADOW1D:
7278 case TGSI_TEXTURE_1D_ARRAY:
7279 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7280 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7281 }
7282 }
7283 }
7284
7285 /* Obtain the sample index for reading a compressed MSAA color texture.
7286 * To read the FMASK, we use the ldfptr instruction, which tells us
7287 * where the samples are stored.
7288 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7289 * which is the identity mapping. Each nibble says which physical sample
7290 * should be fetched to get that sample.
7291 *
7292 * Assume src.z contains the sample index. It should be modified like this:
7293 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7294 * Then fetch the texel with src.
7295 */
7296 if (read_compressed_msaa) {
7297 unsigned sample_chan = 3;
7298 unsigned temp = r600_get_temp(ctx);
7299 assert(src_loaded);
7300
7301 /* temp.w = ldfptr() */
7302 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7303 tex.op = FETCH_OP_LD;
7304 tex.inst_mod = 1; /* to indicate this is ldfptr */
7305 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7306 tex.sampler_index_mode = sampler_index_mode;
7307 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7308 tex.resource_index_mode = sampler_index_mode;
7309 tex.src_gpr = src_gpr;
7310 tex.dst_gpr = temp;
7311 tex.dst_sel_x = 7; /* mask out these components */
7312 tex.dst_sel_y = 7;
7313 tex.dst_sel_z = 7;
7314 tex.dst_sel_w = 0; /* store X */
7315 tex.src_sel_x = 0;
7316 tex.src_sel_y = 1;
7317 tex.src_sel_z = 2;
7318 tex.src_sel_w = 3;
7319 tex.offset_x = offset_x;
7320 tex.offset_y = offset_y;
7321 tex.offset_z = offset_z;
7322 r = r600_bytecode_add_tex(ctx->bc, &tex);
7323 if (r)
7324 return r;
7325
7326 /* temp.x = sample_index*4 */
7327 if (ctx->bc->chip_class == CAYMAN) {
7328 for (i = 0 ; i < 4; i++) {
7329 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7330 alu.op = ALU_OP2_MULLO_INT;
7331 alu.src[0].sel = src_gpr;
7332 alu.src[0].chan = sample_chan;
7333 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7334 alu.src[1].value = 4;
7335 alu.dst.sel = temp;
7336 alu.dst.chan = i;
7337 alu.dst.write = i == 0;
7338 if (i == 3)
7339 alu.last = 1;
7340 r = r600_bytecode_add_alu(ctx->bc, &alu);
7341 if (r)
7342 return r;
7343 }
7344 } else {
7345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7346 alu.op = ALU_OP2_MULLO_INT;
7347 alu.src[0].sel = src_gpr;
7348 alu.src[0].chan = sample_chan;
7349 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7350 alu.src[1].value = 4;
7351 alu.dst.sel = temp;
7352 alu.dst.chan = 0;
7353 alu.dst.write = 1;
7354 alu.last = 1;
7355 r = r600_bytecode_add_alu(ctx->bc, &alu);
7356 if (r)
7357 return r;
7358 }
7359
7360 /* sample_index = temp.w >> temp.x */
7361 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7362 alu.op = ALU_OP2_LSHR_INT;
7363 alu.src[0].sel = temp;
7364 alu.src[0].chan = 3;
7365 alu.src[1].sel = temp;
7366 alu.src[1].chan = 0;
7367 alu.dst.sel = src_gpr;
7368 alu.dst.chan = sample_chan;
7369 alu.dst.write = 1;
7370 alu.last = 1;
7371 r = r600_bytecode_add_alu(ctx->bc, &alu);
7372 if (r)
7373 return r;
7374
7375 /* sample_index & 0xF */
7376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7377 alu.op = ALU_OP2_AND_INT;
7378 alu.src[0].sel = src_gpr;
7379 alu.src[0].chan = sample_chan;
7380 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7381 alu.src[1].value = 0xF;
7382 alu.dst.sel = src_gpr;
7383 alu.dst.chan = sample_chan;
7384 alu.dst.write = 1;
7385 alu.last = 1;
7386 r = r600_bytecode_add_alu(ctx->bc, &alu);
7387 if (r)
7388 return r;
7389 #if 0
7390 /* visualize the FMASK */
7391 for (i = 0; i < 4; i++) {
7392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7393 alu.op = ALU_OP1_INT_TO_FLT;
7394 alu.src[0].sel = src_gpr;
7395 alu.src[0].chan = sample_chan;
7396 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7397 alu.dst.chan = i;
7398 alu.dst.write = 1;
7399 alu.last = 1;
7400 r = r600_bytecode_add_alu(ctx->bc, &alu);
7401 if (r)
7402 return r;
7403 }
7404 return 0;
7405 #endif
7406 }
7407
7408 /* does this shader want a num layers from TXQ for a cube array? */
7409 if (has_txq_cube_array_z) {
7410 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7411
7412 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7413 alu.op = ALU_OP1_MOV;
7414
7415 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7416 if (ctx->bc->chip_class >= EVERGREEN) {
7417 /* channel 1 or 3 of each word */
7418 alu.src[0].sel += (id / 2);
7419 alu.src[0].chan = ((id % 2) * 2) + 1;
7420 } else {
7421 /* r600 we have them at channel 2 of the second dword */
7422 alu.src[0].sel += (id * 2) + 1;
7423 alu.src[0].chan = 2;
7424 }
7425 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7426 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7427 alu.last = 1;
7428 r = r600_bytecode_add_alu(ctx->bc, &alu);
7429 if (r)
7430 return r;
7431 /* disable writemask from texture instruction */
7432 inst->Dst[0].Register.WriteMask &= ~4;
7433 }
7434
7435 opcode = ctx->inst_info->op;
7436 if (opcode == FETCH_OP_GATHER4 &&
7437 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7438 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7439 opcode = FETCH_OP_GATHER4_O;
7440
7441 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7442 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7443 encoded in the instruction are ignored. */
7444 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7445 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7446 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7447 tex.sampler_index_mode = sampler_index_mode;
7448 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7449 tex.resource_index_mode = sampler_index_mode;
7450
7451 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7452 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7453 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7454 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7455 tex.src_sel_w = 4;
7456
7457 tex.dst_sel_x = 7;
7458 tex.dst_sel_y = 7;
7459 tex.dst_sel_z = 7;
7460 tex.dst_sel_w = 7;
7461
7462 r = r600_bytecode_add_tex(ctx->bc, &tex);
7463 if (r)
7464 return r;
7465 }
7466
7467 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7468 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7469 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7470 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7471 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7472 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7473 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7474 switch (opcode) {
7475 case FETCH_OP_SAMPLE:
7476 opcode = FETCH_OP_SAMPLE_C;
7477 break;
7478 case FETCH_OP_SAMPLE_L:
7479 opcode = FETCH_OP_SAMPLE_C_L;
7480 break;
7481 case FETCH_OP_SAMPLE_LB:
7482 opcode = FETCH_OP_SAMPLE_C_LB;
7483 break;
7484 case FETCH_OP_SAMPLE_G:
7485 opcode = FETCH_OP_SAMPLE_C_G;
7486 break;
7487 /* Texture gather variants */
7488 case FETCH_OP_GATHER4:
7489 opcode = FETCH_OP_GATHER4_C;
7490 break;
7491 case FETCH_OP_GATHER4_O:
7492 opcode = FETCH_OP_GATHER4_C_O;
7493 break;
7494 }
7495 }
7496
7497 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7498 tex.op = opcode;
7499
7500 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7501 tex.sampler_index_mode = sampler_index_mode;
7502 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7503 tex.resource_index_mode = sampler_index_mode;
7504 tex.src_gpr = src_gpr;
7505 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7506
7507 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7508 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7509 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7510 }
7511
7512 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7513 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7514 tex.inst_mod = texture_component_select;
7515
7516 if (ctx->bc->chip_class == CAYMAN) {
7517 /* GATHER4 result order is different from TGSI TG4 */
7518 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7519 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7520 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7521 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7522 } else {
7523 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7524 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7525 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7526 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7527 }
7528 }
7529 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7530 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7531 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7532 tex.dst_sel_z = 7;
7533 tex.dst_sel_w = 7;
7534 }
7535 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7536 tex.dst_sel_x = 3;
7537 tex.dst_sel_y = 7;
7538 tex.dst_sel_z = 7;
7539 tex.dst_sel_w = 7;
7540 }
7541 else {
7542 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7543 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7544 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7545 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7546 }
7547
7548
7549 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
7550 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7551 tex.src_sel_x = 4;
7552 tex.src_sel_y = 4;
7553 tex.src_sel_z = 4;
7554 tex.src_sel_w = 4;
7555 } else if (src_loaded) {
7556 tex.src_sel_x = 0;
7557 tex.src_sel_y = 1;
7558 tex.src_sel_z = 2;
7559 tex.src_sel_w = 3;
7560 } else {
7561 tex.src_sel_x = ctx->src[0].swizzle[0];
7562 tex.src_sel_y = ctx->src[0].swizzle[1];
7563 tex.src_sel_z = ctx->src[0].swizzle[2];
7564 tex.src_sel_w = ctx->src[0].swizzle[3];
7565 tex.src_rel = ctx->src[0].rel;
7566 }
7567
7568 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7569 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7570 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7571 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7572 tex.src_sel_x = 1;
7573 tex.src_sel_y = 0;
7574 tex.src_sel_z = 3;
7575 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7576 }
7577
7578 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7579 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7580 tex.coord_type_x = 1;
7581 tex.coord_type_y = 1;
7582 }
7583 tex.coord_type_z = 1;
7584 tex.coord_type_w = 1;
7585
7586 tex.offset_x = offset_x;
7587 tex.offset_y = offset_y;
7588 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7589 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7590 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7591 tex.offset_z = 0;
7592 }
7593 else {
7594 tex.offset_z = offset_z;
7595 }
7596
7597 /* Put the depth for comparison in W.
7598 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7599 * Some instructions expect the depth in Z. */
7600 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7601 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7602 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7603 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7604 opcode != FETCH_OP_SAMPLE_C_L &&
7605 opcode != FETCH_OP_SAMPLE_C_LB) {
7606 tex.src_sel_w = tex.src_sel_z;
7607 }
7608
7609 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7610 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7611 if (opcode == FETCH_OP_SAMPLE_C_L ||
7612 opcode == FETCH_OP_SAMPLE_C_LB) {
7613 /* the array index is read from Y */
7614 tex.coord_type_y = 0;
7615 } else {
7616 /* the array index is read from Z */
7617 tex.coord_type_z = 0;
7618 tex.src_sel_z = tex.src_sel_y;
7619 }
7620 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7621 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7622 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7623 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7624 (ctx->bc->chip_class >= EVERGREEN)))
7625 /* the array index is read from Z */
7626 tex.coord_type_z = 0;
7627
7628 /* mask unused source components */
7629 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7630 switch (inst->Texture.Texture) {
7631 case TGSI_TEXTURE_2D:
7632 case TGSI_TEXTURE_RECT:
7633 tex.src_sel_z = 7;
7634 tex.src_sel_w = 7;
7635 break;
7636 case TGSI_TEXTURE_1D_ARRAY:
7637 tex.src_sel_y = 7;
7638 tex.src_sel_w = 7;
7639 break;
7640 case TGSI_TEXTURE_1D:
7641 tex.src_sel_y = 7;
7642 tex.src_sel_z = 7;
7643 tex.src_sel_w = 7;
7644 break;
7645 }
7646 }
7647
7648 r = r600_bytecode_add_tex(ctx->bc, &tex);
7649 if (r)
7650 return r;
7651
7652 /* add shadow ambient support - gallium doesn't do it yet */
7653 return 0;
7654 }
7655
7656 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7657 {
7658 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7659 struct r600_bytecode_alu alu;
7660 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7661 unsigned i, temp_regs[2];
7662 int r;
7663
7664 /* optimize if it's just an equal balance */
7665 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7666 for (i = 0; i < lasti + 1; i++) {
7667 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7668 continue;
7669
7670 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7671 alu.op = ALU_OP2_ADD;
7672 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7673 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7674 alu.omod = 3;
7675 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7676 alu.dst.chan = i;
7677 if (i == lasti) {
7678 alu.last = 1;
7679 }
7680 r = r600_bytecode_add_alu(ctx->bc, &alu);
7681 if (r)
7682 return r;
7683 }
7684 return 0;
7685 }
7686
7687 /* 1 - src0 */
7688 for (i = 0; i < lasti + 1; i++) {
7689 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7690 continue;
7691
7692 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7693 alu.op = ALU_OP2_ADD;
7694 alu.src[0].sel = V_SQ_ALU_SRC_1;
7695 alu.src[0].chan = 0;
7696 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7697 r600_bytecode_src_toggle_neg(&alu.src[1]);
7698 alu.dst.sel = ctx->temp_reg;
7699 alu.dst.chan = i;
7700 if (i == lasti) {
7701 alu.last = 1;
7702 }
7703 alu.dst.write = 1;
7704 r = r600_bytecode_add_alu(ctx->bc, &alu);
7705 if (r)
7706 return r;
7707 }
7708
7709 /* (1 - src0) * src2 */
7710 for (i = 0; i < lasti + 1; i++) {
7711 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7712 continue;
7713
7714 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7715 alu.op = ALU_OP2_MUL;
7716 alu.src[0].sel = ctx->temp_reg;
7717 alu.src[0].chan = i;
7718 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7719 alu.dst.sel = ctx->temp_reg;
7720 alu.dst.chan = i;
7721 if (i == lasti) {
7722 alu.last = 1;
7723 }
7724 alu.dst.write = 1;
7725 r = r600_bytecode_add_alu(ctx->bc, &alu);
7726 if (r)
7727 return r;
7728 }
7729
7730 /* src0 * src1 + (1 - src0) * src2 */
7731 if (ctx->src[0].abs)
7732 temp_regs[0] = r600_get_temp(ctx);
7733 else
7734 temp_regs[0] = 0;
7735 if (ctx->src[1].abs)
7736 temp_regs[1] = r600_get_temp(ctx);
7737 else
7738 temp_regs[1] = 0;
7739
7740 for (i = 0; i < lasti + 1; i++) {
7741 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7742 continue;
7743
7744 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7745 alu.op = ALU_OP3_MULADD;
7746 alu.is_op3 = 1;
7747 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7748 if (r)
7749 return r;
7750 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7751 if (r)
7752 return r;
7753 alu.src[2].sel = ctx->temp_reg;
7754 alu.src[2].chan = i;
7755
7756 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7757 alu.dst.chan = i;
7758 if (i == lasti) {
7759 alu.last = 1;
7760 }
7761 r = r600_bytecode_add_alu(ctx->bc, &alu);
7762 if (r)
7763 return r;
7764 }
7765 return 0;
7766 }
7767
7768 static int tgsi_cmp(struct r600_shader_ctx *ctx)
7769 {
7770 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7771 struct r600_bytecode_alu alu;
7772 int i, r, j;
7773 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7774 int temp_regs[3];
7775
7776 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7777 temp_regs[j] = 0;
7778 if (ctx->src[j].abs)
7779 temp_regs[j] = r600_get_temp(ctx);
7780 }
7781
7782 for (i = 0; i < lasti + 1; i++) {
7783 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7784 continue;
7785
7786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7787 alu.op = ALU_OP3_CNDGE;
7788 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7789 if (r)
7790 return r;
7791 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
7792 if (r)
7793 return r;
7794 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
7795 if (r)
7796 return r;
7797 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7798 alu.dst.chan = i;
7799 alu.dst.write = 1;
7800 alu.is_op3 = 1;
7801 if (i == lasti)
7802 alu.last = 1;
7803 r = r600_bytecode_add_alu(ctx->bc, &alu);
7804 if (r)
7805 return r;
7806 }
7807 return 0;
7808 }
7809
7810 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
7811 {
7812 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7813 struct r600_bytecode_alu alu;
7814 int i, r;
7815 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7816
7817 for (i = 0; i < lasti + 1; i++) {
7818 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7819 continue;
7820
7821 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7822 alu.op = ALU_OP3_CNDE_INT;
7823 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7824 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7825 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
7826 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7827 alu.dst.chan = i;
7828 alu.dst.write = 1;
7829 alu.is_op3 = 1;
7830 if (i == lasti)
7831 alu.last = 1;
7832 r = r600_bytecode_add_alu(ctx->bc, &alu);
7833 if (r)
7834 return r;
7835 }
7836 return 0;
7837 }
7838
7839 static int tgsi_xpd(struct r600_shader_ctx *ctx)
7840 {
7841 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7842 static const unsigned int src0_swizzle[] = {2, 0, 1};
7843 static const unsigned int src1_swizzle[] = {1, 2, 0};
7844 struct r600_bytecode_alu alu;
7845 uint32_t use_temp = 0;
7846 int i, r;
7847
7848 if (inst->Dst[0].Register.WriteMask != 0xf)
7849 use_temp = 1;
7850
7851 for (i = 0; i < 4; i++) {
7852 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7853 alu.op = ALU_OP2_MUL;
7854 if (i < 3) {
7855 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7856 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
7857 } else {
7858 alu.src[0].sel = V_SQ_ALU_SRC_0;
7859 alu.src[0].chan = i;
7860 alu.src[1].sel = V_SQ_ALU_SRC_0;
7861 alu.src[1].chan = i;
7862 }
7863
7864 alu.dst.sel = ctx->temp_reg;
7865 alu.dst.chan = i;
7866 alu.dst.write = 1;
7867
7868 if (i == 3)
7869 alu.last = 1;
7870 r = r600_bytecode_add_alu(ctx->bc, &alu);
7871 if (r)
7872 return r;
7873 }
7874
7875 for (i = 0; i < 4; i++) {
7876 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7877 alu.op = ALU_OP3_MULADD;
7878
7879 if (i < 3) {
7880 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
7881 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
7882 } else {
7883 alu.src[0].sel = V_SQ_ALU_SRC_0;
7884 alu.src[0].chan = i;
7885 alu.src[1].sel = V_SQ_ALU_SRC_0;
7886 alu.src[1].chan = i;
7887 }
7888
7889 alu.src[2].sel = ctx->temp_reg;
7890 alu.src[2].neg = 1;
7891 alu.src[2].chan = i;
7892
7893 if (use_temp)
7894 alu.dst.sel = ctx->temp_reg;
7895 else
7896 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7897 alu.dst.chan = i;
7898 alu.dst.write = 1;
7899 alu.is_op3 = 1;
7900 if (i == 3)
7901 alu.last = 1;
7902 r = r600_bytecode_add_alu(ctx->bc, &alu);
7903 if (r)
7904 return r;
7905 }
7906 if (use_temp)
7907 return tgsi_helper_copy(ctx, inst);
7908 return 0;
7909 }
7910
7911 static int tgsi_exp(struct r600_shader_ctx *ctx)
7912 {
7913 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7914 struct r600_bytecode_alu alu;
7915 int r;
7916 int i;
7917
7918 /* result.x = 2^floor(src); */
7919 if (inst->Dst[0].Register.WriteMask & 1) {
7920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7921
7922 alu.op = ALU_OP1_FLOOR;
7923 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7924
7925 alu.dst.sel = ctx->temp_reg;
7926 alu.dst.chan = 0;
7927 alu.dst.write = 1;
7928 alu.last = 1;
7929 r = r600_bytecode_add_alu(ctx->bc, &alu);
7930 if (r)
7931 return r;
7932
7933 if (ctx->bc->chip_class == CAYMAN) {
7934 for (i = 0; i < 3; i++) {
7935 alu.op = ALU_OP1_EXP_IEEE;
7936 alu.src[0].sel = ctx->temp_reg;
7937 alu.src[0].chan = 0;
7938
7939 alu.dst.sel = ctx->temp_reg;
7940 alu.dst.chan = i;
7941 alu.dst.write = i == 0;
7942 alu.last = i == 2;
7943 r = r600_bytecode_add_alu(ctx->bc, &alu);
7944 if (r)
7945 return r;
7946 }
7947 } else {
7948 alu.op = ALU_OP1_EXP_IEEE;
7949 alu.src[0].sel = ctx->temp_reg;
7950 alu.src[0].chan = 0;
7951
7952 alu.dst.sel = ctx->temp_reg;
7953 alu.dst.chan = 0;
7954 alu.dst.write = 1;
7955 alu.last = 1;
7956 r = r600_bytecode_add_alu(ctx->bc, &alu);
7957 if (r)
7958 return r;
7959 }
7960 }
7961
7962 /* result.y = tmp - floor(tmp); */
7963 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7964 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7965
7966 alu.op = ALU_OP1_FRACT;
7967 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7968
7969 alu.dst.sel = ctx->temp_reg;
7970 #if 0
7971 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7972 if (r)
7973 return r;
7974 #endif
7975 alu.dst.write = 1;
7976 alu.dst.chan = 1;
7977
7978 alu.last = 1;
7979
7980 r = r600_bytecode_add_alu(ctx->bc, &alu);
7981 if (r)
7982 return r;
7983 }
7984
7985 /* result.z = RoughApprox2ToX(tmp);*/
7986 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
7987 if (ctx->bc->chip_class == CAYMAN) {
7988 for (i = 0; i < 3; i++) {
7989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7990 alu.op = ALU_OP1_EXP_IEEE;
7991 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7992
7993 alu.dst.sel = ctx->temp_reg;
7994 alu.dst.chan = i;
7995 if (i == 2) {
7996 alu.dst.write = 1;
7997 alu.last = 1;
7998 }
7999
8000 r = r600_bytecode_add_alu(ctx->bc, &alu);
8001 if (r)
8002 return r;
8003 }
8004 } else {
8005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8006 alu.op = ALU_OP1_EXP_IEEE;
8007 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8008
8009 alu.dst.sel = ctx->temp_reg;
8010 alu.dst.write = 1;
8011 alu.dst.chan = 2;
8012
8013 alu.last = 1;
8014
8015 r = r600_bytecode_add_alu(ctx->bc, &alu);
8016 if (r)
8017 return r;
8018 }
8019 }
8020
8021 /* result.w = 1.0;*/
8022 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8024
8025 alu.op = ALU_OP1_MOV;
8026 alu.src[0].sel = V_SQ_ALU_SRC_1;
8027 alu.src[0].chan = 0;
8028
8029 alu.dst.sel = ctx->temp_reg;
8030 alu.dst.chan = 3;
8031 alu.dst.write = 1;
8032 alu.last = 1;
8033 r = r600_bytecode_add_alu(ctx->bc, &alu);
8034 if (r)
8035 return r;
8036 }
8037 return tgsi_helper_copy(ctx, inst);
8038 }
8039
8040 static int tgsi_log(struct r600_shader_ctx *ctx)
8041 {
8042 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8043 struct r600_bytecode_alu alu;
8044 int r;
8045 int i;
8046
8047 /* result.x = floor(log2(|src|)); */
8048 if (inst->Dst[0].Register.WriteMask & 1) {
8049 if (ctx->bc->chip_class == CAYMAN) {
8050 for (i = 0; i < 3; i++) {
8051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8052
8053 alu.op = ALU_OP1_LOG_IEEE;
8054 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8055 r600_bytecode_src_set_abs(&alu.src[0]);
8056
8057 alu.dst.sel = ctx->temp_reg;
8058 alu.dst.chan = i;
8059 if (i == 0)
8060 alu.dst.write = 1;
8061 if (i == 2)
8062 alu.last = 1;
8063 r = r600_bytecode_add_alu(ctx->bc, &alu);
8064 if (r)
8065 return r;
8066 }
8067
8068 } else {
8069 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8070
8071 alu.op = ALU_OP1_LOG_IEEE;
8072 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8073 r600_bytecode_src_set_abs(&alu.src[0]);
8074
8075 alu.dst.sel = ctx->temp_reg;
8076 alu.dst.chan = 0;
8077 alu.dst.write = 1;
8078 alu.last = 1;
8079 r = r600_bytecode_add_alu(ctx->bc, &alu);
8080 if (r)
8081 return r;
8082 }
8083
8084 alu.op = ALU_OP1_FLOOR;
8085 alu.src[0].sel = ctx->temp_reg;
8086 alu.src[0].chan = 0;
8087
8088 alu.dst.sel = ctx->temp_reg;
8089 alu.dst.chan = 0;
8090 alu.dst.write = 1;
8091 alu.last = 1;
8092
8093 r = r600_bytecode_add_alu(ctx->bc, &alu);
8094 if (r)
8095 return r;
8096 }
8097
8098 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8099 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8100
8101 if (ctx->bc->chip_class == CAYMAN) {
8102 for (i = 0; i < 3; i++) {
8103 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8104
8105 alu.op = ALU_OP1_LOG_IEEE;
8106 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8107 r600_bytecode_src_set_abs(&alu.src[0]);
8108
8109 alu.dst.sel = ctx->temp_reg;
8110 alu.dst.chan = i;
8111 if (i == 1)
8112 alu.dst.write = 1;
8113 if (i == 2)
8114 alu.last = 1;
8115
8116 r = r600_bytecode_add_alu(ctx->bc, &alu);
8117 if (r)
8118 return r;
8119 }
8120 } else {
8121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8122
8123 alu.op = ALU_OP1_LOG_IEEE;
8124 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8125 r600_bytecode_src_set_abs(&alu.src[0]);
8126
8127 alu.dst.sel = ctx->temp_reg;
8128 alu.dst.chan = 1;
8129 alu.dst.write = 1;
8130 alu.last = 1;
8131
8132 r = r600_bytecode_add_alu(ctx->bc, &alu);
8133 if (r)
8134 return r;
8135 }
8136
8137 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8138
8139 alu.op = ALU_OP1_FLOOR;
8140 alu.src[0].sel = ctx->temp_reg;
8141 alu.src[0].chan = 1;
8142
8143 alu.dst.sel = ctx->temp_reg;
8144 alu.dst.chan = 1;
8145 alu.dst.write = 1;
8146 alu.last = 1;
8147
8148 r = r600_bytecode_add_alu(ctx->bc, &alu);
8149 if (r)
8150 return r;
8151
8152 if (ctx->bc->chip_class == CAYMAN) {
8153 for (i = 0; i < 3; i++) {
8154 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8155 alu.op = ALU_OP1_EXP_IEEE;
8156 alu.src[0].sel = ctx->temp_reg;
8157 alu.src[0].chan = 1;
8158
8159 alu.dst.sel = ctx->temp_reg;
8160 alu.dst.chan = i;
8161 if (i == 1)
8162 alu.dst.write = 1;
8163 if (i == 2)
8164 alu.last = 1;
8165
8166 r = r600_bytecode_add_alu(ctx->bc, &alu);
8167 if (r)
8168 return r;
8169 }
8170 } else {
8171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8172 alu.op = ALU_OP1_EXP_IEEE;
8173 alu.src[0].sel = ctx->temp_reg;
8174 alu.src[0].chan = 1;
8175
8176 alu.dst.sel = ctx->temp_reg;
8177 alu.dst.chan = 1;
8178 alu.dst.write = 1;
8179 alu.last = 1;
8180
8181 r = r600_bytecode_add_alu(ctx->bc, &alu);
8182 if (r)
8183 return r;
8184 }
8185
8186 if (ctx->bc->chip_class == CAYMAN) {
8187 for (i = 0; i < 3; i++) {
8188 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8189 alu.op = ALU_OP1_RECIP_IEEE;
8190 alu.src[0].sel = ctx->temp_reg;
8191 alu.src[0].chan = 1;
8192
8193 alu.dst.sel = ctx->temp_reg;
8194 alu.dst.chan = i;
8195 if (i == 1)
8196 alu.dst.write = 1;
8197 if (i == 2)
8198 alu.last = 1;
8199
8200 r = r600_bytecode_add_alu(ctx->bc, &alu);
8201 if (r)
8202 return r;
8203 }
8204 } else {
8205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8206 alu.op = ALU_OP1_RECIP_IEEE;
8207 alu.src[0].sel = ctx->temp_reg;
8208 alu.src[0].chan = 1;
8209
8210 alu.dst.sel = ctx->temp_reg;
8211 alu.dst.chan = 1;
8212 alu.dst.write = 1;
8213 alu.last = 1;
8214
8215 r = r600_bytecode_add_alu(ctx->bc, &alu);
8216 if (r)
8217 return r;
8218 }
8219
8220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8221
8222 alu.op = ALU_OP2_MUL;
8223
8224 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8225 r600_bytecode_src_set_abs(&alu.src[0]);
8226
8227 alu.src[1].sel = ctx->temp_reg;
8228 alu.src[1].chan = 1;
8229
8230 alu.dst.sel = ctx->temp_reg;
8231 alu.dst.chan = 1;
8232 alu.dst.write = 1;
8233 alu.last = 1;
8234
8235 r = r600_bytecode_add_alu(ctx->bc, &alu);
8236 if (r)
8237 return r;
8238 }
8239
8240 /* result.z = log2(|src|);*/
8241 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8242 if (ctx->bc->chip_class == CAYMAN) {
8243 for (i = 0; i < 3; i++) {
8244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8245
8246 alu.op = ALU_OP1_LOG_IEEE;
8247 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8248 r600_bytecode_src_set_abs(&alu.src[0]);
8249
8250 alu.dst.sel = ctx->temp_reg;
8251 if (i == 2)
8252 alu.dst.write = 1;
8253 alu.dst.chan = i;
8254 if (i == 2)
8255 alu.last = 1;
8256
8257 r = r600_bytecode_add_alu(ctx->bc, &alu);
8258 if (r)
8259 return r;
8260 }
8261 } else {
8262 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8263
8264 alu.op = ALU_OP1_LOG_IEEE;
8265 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8266 r600_bytecode_src_set_abs(&alu.src[0]);
8267
8268 alu.dst.sel = ctx->temp_reg;
8269 alu.dst.write = 1;
8270 alu.dst.chan = 2;
8271 alu.last = 1;
8272
8273 r = r600_bytecode_add_alu(ctx->bc, &alu);
8274 if (r)
8275 return r;
8276 }
8277 }
8278
8279 /* result.w = 1.0; */
8280 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8282
8283 alu.op = ALU_OP1_MOV;
8284 alu.src[0].sel = V_SQ_ALU_SRC_1;
8285 alu.src[0].chan = 0;
8286
8287 alu.dst.sel = ctx->temp_reg;
8288 alu.dst.chan = 3;
8289 alu.dst.write = 1;
8290 alu.last = 1;
8291
8292 r = r600_bytecode_add_alu(ctx->bc, &alu);
8293 if (r)
8294 return r;
8295 }
8296
8297 return tgsi_helper_copy(ctx, inst);
8298 }
8299
8300 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8301 {
8302 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8303 struct r600_bytecode_alu alu;
8304 int r;
8305 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8306 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8307
8308 assert(inst->Dst[0].Register.Index < 3);
8309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8310
8311 switch (inst->Instruction.Opcode) {
8312 case TGSI_OPCODE_ARL:
8313 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8314 break;
8315 case TGSI_OPCODE_ARR:
8316 alu.op = ALU_OP1_FLT_TO_INT;
8317 break;
8318 case TGSI_OPCODE_UARL:
8319 alu.op = ALU_OP1_MOV;
8320 break;
8321 default:
8322 assert(0);
8323 return -1;
8324 }
8325
8326 for (i = 0; i <= lasti; ++i) {
8327 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8328 continue;
8329 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8330 alu.last = i == lasti;
8331 alu.dst.sel = reg;
8332 alu.dst.chan = i;
8333 alu.dst.write = 1;
8334 r = r600_bytecode_add_alu(ctx->bc, &alu);
8335 if (r)
8336 return r;
8337 }
8338
8339 if (inst->Dst[0].Register.Index > 0)
8340 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8341 else
8342 ctx->bc->ar_loaded = 0;
8343
8344 return 0;
8345 }
8346 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8347 {
8348 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8349 struct r600_bytecode_alu alu;
8350 int r;
8351 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8352
8353 switch (inst->Instruction.Opcode) {
8354 case TGSI_OPCODE_ARL:
8355 memset(&alu, 0, sizeof(alu));
8356 alu.op = ALU_OP1_FLOOR;
8357 alu.dst.sel = ctx->bc->ar_reg;
8358 alu.dst.write = 1;
8359 for (i = 0; i <= lasti; ++i) {
8360 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8361 alu.dst.chan = i;
8362 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8363 alu.last = i == lasti;
8364 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8365 return r;
8366 }
8367 }
8368
8369 memset(&alu, 0, sizeof(alu));
8370 alu.op = ALU_OP1_FLT_TO_INT;
8371 alu.src[0].sel = ctx->bc->ar_reg;
8372 alu.dst.sel = ctx->bc->ar_reg;
8373 alu.dst.write = 1;
8374 /* FLT_TO_INT is trans-only on r600/r700 */
8375 alu.last = TRUE;
8376 for (i = 0; i <= lasti; ++i) {
8377 alu.dst.chan = i;
8378 alu.src[0].chan = i;
8379 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8380 return r;
8381 }
8382 break;
8383 case TGSI_OPCODE_ARR:
8384 memset(&alu, 0, sizeof(alu));
8385 alu.op = ALU_OP1_FLT_TO_INT;
8386 alu.dst.sel = ctx->bc->ar_reg;
8387 alu.dst.write = 1;
8388 /* FLT_TO_INT is trans-only on r600/r700 */
8389 alu.last = TRUE;
8390 for (i = 0; i <= lasti; ++i) {
8391 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8392 alu.dst.chan = i;
8393 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8394 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8395 return r;
8396 }
8397 }
8398 break;
8399 case TGSI_OPCODE_UARL:
8400 memset(&alu, 0, sizeof(alu));
8401 alu.op = ALU_OP1_MOV;
8402 alu.dst.sel = ctx->bc->ar_reg;
8403 alu.dst.write = 1;
8404 for (i = 0; i <= lasti; ++i) {
8405 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8406 alu.dst.chan = i;
8407 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8408 alu.last = i == lasti;
8409 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8410 return r;
8411 }
8412 }
8413 break;
8414 default:
8415 assert(0);
8416 return -1;
8417 }
8418
8419 ctx->bc->ar_loaded = 0;
8420 return 0;
8421 }
8422
8423 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8424 {
8425 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8426 struct r600_bytecode_alu alu;
8427 int i, r = 0;
8428
8429 for (i = 0; i < 4; i++) {
8430 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8431
8432 alu.op = ALU_OP2_MUL;
8433 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8434
8435 if (i == 0 || i == 3) {
8436 alu.src[0].sel = V_SQ_ALU_SRC_1;
8437 } else {
8438 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8439 }
8440
8441 if (i == 0 || i == 2) {
8442 alu.src[1].sel = V_SQ_ALU_SRC_1;
8443 } else {
8444 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8445 }
8446 if (i == 3)
8447 alu.last = 1;
8448 r = r600_bytecode_add_alu(ctx->bc, &alu);
8449 if (r)
8450 return r;
8451 }
8452 return 0;
8453 }
8454
8455 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8456 {
8457 struct r600_bytecode_alu alu;
8458 int r;
8459
8460 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8461 alu.op = opcode;
8462 alu.execute_mask = 1;
8463 alu.update_pred = 1;
8464
8465 alu.dst.sel = ctx->temp_reg;
8466 alu.dst.write = 1;
8467 alu.dst.chan = 0;
8468
8469 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8470 alu.src[1].sel = V_SQ_ALU_SRC_0;
8471 alu.src[1].chan = 0;
8472
8473 alu.last = 1;
8474
8475 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8476 if (r)
8477 return r;
8478 return 0;
8479 }
8480
8481 static int pops(struct r600_shader_ctx *ctx, int pops)
8482 {
8483 unsigned force_pop = ctx->bc->force_add_cf;
8484
8485 if (!force_pop) {
8486 int alu_pop = 3;
8487 if (ctx->bc->cf_last) {
8488 if (ctx->bc->cf_last->op == CF_OP_ALU)
8489 alu_pop = 0;
8490 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8491 alu_pop = 1;
8492 }
8493 alu_pop += pops;
8494 if (alu_pop == 1) {
8495 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8496 ctx->bc->force_add_cf = 1;
8497 } else if (alu_pop == 2) {
8498 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8499 ctx->bc->force_add_cf = 1;
8500 } else {
8501 force_pop = 1;
8502 }
8503 }
8504
8505 if (force_pop) {
8506 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8507 ctx->bc->cf_last->pop_count = pops;
8508 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8509 }
8510
8511 return 0;
8512 }
8513
8514 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8515 unsigned reason)
8516 {
8517 struct r600_stack_info *stack = &ctx->bc->stack;
8518 unsigned elements, entries;
8519
8520 unsigned entry_size = stack->entry_size;
8521
8522 elements = (stack->loop + stack->push_wqm ) * entry_size;
8523 elements += stack->push;
8524
8525 switch (ctx->bc->chip_class) {
8526 case R600:
8527 case R700:
8528 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8529 * the stack must be reserved to hold the current active/continue
8530 * masks */
8531 if (reason == FC_PUSH_VPM) {
8532 elements += 2;
8533 }
8534 break;
8535
8536 case CAYMAN:
8537 /* r9xx: any stack operation on empty stack consumes 2 additional
8538 * elements */
8539 elements += 2;
8540
8541 /* fallthrough */
8542 /* FIXME: do the two elements added above cover the cases for the
8543 * r8xx+ below? */
8544
8545 case EVERGREEN:
8546 /* r8xx+: 2 extra elements are not always required, but one extra
8547 * element must be added for each of the following cases:
8548 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8549 * stack usage.
8550 * (Currently we don't use ALU_ELSE_AFTER.)
8551 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8552 * PUSH instruction executed.
8553 *
8554 * NOTE: it seems we also need to reserve additional element in some
8555 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8556 * then STACK_SIZE should be 2 instead of 1 */
8557 if (reason == FC_PUSH_VPM) {
8558 elements += 1;
8559 }
8560 break;
8561
8562 default:
8563 assert(0);
8564 break;
8565 }
8566
8567 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8568 * for all chips, so we use 4 in the final formula, not the real entry_size
8569 * for the chip */
8570 entry_size = 4;
8571
8572 entries = (elements + (entry_size - 1)) / entry_size;
8573
8574 if (entries > stack->max_entries)
8575 stack->max_entries = entries;
8576 }
8577
8578 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8579 {
8580 switch(reason) {
8581 case FC_PUSH_VPM:
8582 --ctx->bc->stack.push;
8583 assert(ctx->bc->stack.push >= 0);
8584 break;
8585 case FC_PUSH_WQM:
8586 --ctx->bc->stack.push_wqm;
8587 assert(ctx->bc->stack.push_wqm >= 0);
8588 break;
8589 case FC_LOOP:
8590 --ctx->bc->stack.loop;
8591 assert(ctx->bc->stack.loop >= 0);
8592 break;
8593 default:
8594 assert(0);
8595 break;
8596 }
8597 }
8598
8599 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8600 {
8601 switch (reason) {
8602 case FC_PUSH_VPM:
8603 ++ctx->bc->stack.push;
8604 break;
8605 case FC_PUSH_WQM:
8606 ++ctx->bc->stack.push_wqm;
8607 case FC_LOOP:
8608 ++ctx->bc->stack.loop;
8609 break;
8610 default:
8611 assert(0);
8612 }
8613
8614 callstack_update_max_depth(ctx, reason);
8615 }
8616
8617 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8618 {
8619 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8620
8621 sp->mid = realloc((void *)sp->mid,
8622 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8623 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8624 sp->num_mid++;
8625 }
8626
8627 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8628 {
8629 ctx->bc->fc_sp++;
8630 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8631 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8632 }
8633
8634 static void fc_poplevel(struct r600_shader_ctx *ctx)
8635 {
8636 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
8637 free(sp->mid);
8638 sp->mid = NULL;
8639 sp->num_mid = 0;
8640 sp->start = NULL;
8641 sp->type = 0;
8642 ctx->bc->fc_sp--;
8643 }
8644
8645 #if 0
8646 static int emit_return(struct r600_shader_ctx *ctx)
8647 {
8648 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8649 return 0;
8650 }
8651
8652 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8653 {
8654
8655 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8656 ctx->bc->cf_last->pop_count = pops;
8657 /* XXX work out offset */
8658 return 0;
8659 }
8660
8661 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8662 {
8663 return 0;
8664 }
8665
8666 static void emit_testflag(struct r600_shader_ctx *ctx)
8667 {
8668
8669 }
8670
8671 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8672 {
8673 emit_testflag(ctx);
8674 emit_jump_to_offset(ctx, 1, 4);
8675 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8676 pops(ctx, ifidx + 1);
8677 emit_return(ctx);
8678 }
8679
8680 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8681 {
8682 emit_testflag(ctx);
8683
8684 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8685 ctx->bc->cf_last->pop_count = 1;
8686
8687 fc_set_mid(ctx, fc_sp);
8688
8689 pops(ctx, 1);
8690 }
8691 #endif
8692
8693 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8694 {
8695 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8696
8697 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8698 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8699 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8700 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8701 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8702 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8703 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8704 alu_type = CF_OP_ALU;
8705 }
8706
8707 emit_logic_pred(ctx, opcode, alu_type);
8708
8709 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8710
8711 fc_pushlevel(ctx, FC_IF);
8712
8713 callstack_push(ctx, FC_PUSH_VPM);
8714 return 0;
8715 }
8716
8717 static int tgsi_if(struct r600_shader_ctx *ctx)
8718 {
8719 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8720 }
8721
8722 static int tgsi_uif(struct r600_shader_ctx *ctx)
8723 {
8724 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8725 }
8726
8727 static int tgsi_else(struct r600_shader_ctx *ctx)
8728 {
8729 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8730 ctx->bc->cf_last->pop_count = 1;
8731
8732 fc_set_mid(ctx, ctx->bc->fc_sp);
8733 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
8734 return 0;
8735 }
8736
8737 static int tgsi_endif(struct r600_shader_ctx *ctx)
8738 {
8739 pops(ctx, 1);
8740 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
8741 R600_ERR("if/endif unbalanced in shader\n");
8742 return -1;
8743 }
8744
8745 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
8746 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8747 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
8748 } else {
8749 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8750 }
8751 fc_poplevel(ctx);
8752
8753 callstack_pop(ctx, FC_PUSH_VPM);
8754 return 0;
8755 }
8756
8757 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8758 {
8759 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8760 * limited to 4096 iterations, like the other LOOP_* instructions. */
8761 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8762
8763 fc_pushlevel(ctx, FC_LOOP);
8764
8765 /* check stack depth */
8766 callstack_push(ctx, FC_LOOP);
8767 return 0;
8768 }
8769
8770 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8771 {
8772 int i;
8773
8774 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8775
8776 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
8777 R600_ERR("loop/endloop in shader code are not paired.\n");
8778 return -EINVAL;
8779 }
8780
8781 /* fixup loop pointers - from r600isa
8782 LOOP END points to CF after LOOP START,
8783 LOOP START point to CF after LOOP END
8784 BRK/CONT point to LOOP END CF
8785 */
8786 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
8787
8788 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8789
8790 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
8791 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
8792 }
8793 /* XXX add LOOPRET support */
8794 fc_poplevel(ctx);
8795 callstack_pop(ctx, FC_LOOP);
8796 return 0;
8797 }
8798
8799 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
8800 {
8801 int r;
8802 unsigned int fscp;
8803
8804 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8805 {
8806 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8807 break;
8808 }
8809 if (fscp == 0) {
8810 R600_ERR("BREAKC not inside loop/endloop pair\n");
8811 return -EINVAL;
8812 }
8813
8814 if (ctx->bc->chip_class == EVERGREEN &&
8815 ctx->bc->family != CHIP_CYPRESS &&
8816 ctx->bc->family != CHIP_JUNIPER) {
8817 /* HW bug: ALU_BREAK does not save the active mask correctly */
8818 r = tgsi_uif(ctx);
8819 if (r)
8820 return r;
8821
8822 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
8823 if (r)
8824 return r;
8825 fc_set_mid(ctx, fscp);
8826
8827 return tgsi_endif(ctx);
8828 } else {
8829 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
8830 if (r)
8831 return r;
8832 fc_set_mid(ctx, fscp);
8833 }
8834
8835 return 0;
8836 }
8837
8838 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8839 {
8840 unsigned int fscp;
8841
8842 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8843 {
8844 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8845 break;
8846 }
8847
8848 if (fscp == 0) {
8849 R600_ERR("Break not inside loop/endloop pair\n");
8850 return -EINVAL;
8851 }
8852
8853 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8854
8855 fc_set_mid(ctx, fscp);
8856
8857 return 0;
8858 }
8859
8860 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8861 {
8862 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8863 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8864 int r;
8865
8866 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8867 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
8868
8869 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8870 if (!r) {
8871 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
8872 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8873 return emit_inc_ring_offset(ctx, stream, TRUE);
8874 }
8875 return r;
8876 }
8877
8878 static int tgsi_umad(struct r600_shader_ctx *ctx)
8879 {
8880 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8881 struct r600_bytecode_alu alu;
8882 int i, j, k, r;
8883 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8884
8885 /* src0 * src1 */
8886 for (i = 0; i < lasti + 1; i++) {
8887 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8888 continue;
8889
8890 if (ctx->bc->chip_class == CAYMAN) {
8891 for (j = 0 ; j < 4; j++) {
8892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8893
8894 alu.op = ALU_OP2_MULLO_UINT;
8895 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
8896 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
8897 }
8898 alu.dst.chan = j;
8899 alu.dst.sel = ctx->temp_reg;
8900 alu.dst.write = (j == i);
8901 if (j == 3)
8902 alu.last = 1;
8903 r = r600_bytecode_add_alu(ctx->bc, &alu);
8904 if (r)
8905 return r;
8906 }
8907 } else {
8908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8909
8910 alu.dst.chan = i;
8911 alu.dst.sel = ctx->temp_reg;
8912 alu.dst.write = 1;
8913
8914 alu.op = ALU_OP2_MULLO_UINT;
8915 for (j = 0; j < 2; j++) {
8916 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
8917 }
8918
8919 alu.last = 1;
8920 r = r600_bytecode_add_alu(ctx->bc, &alu);
8921 if (r)
8922 return r;
8923 }
8924 }
8925
8926
8927 for (i = 0; i < lasti + 1; i++) {
8928 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8929 continue;
8930
8931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8932 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8933
8934 alu.op = ALU_OP2_ADD_INT;
8935
8936 alu.src[0].sel = ctx->temp_reg;
8937 alu.src[0].chan = i;
8938
8939 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8940 if (i == lasti) {
8941 alu.last = 1;
8942 }
8943 r = r600_bytecode_add_alu(ctx->bc, &alu);
8944 if (r)
8945 return r;
8946 }
8947 return 0;
8948 }
8949
8950 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
8951 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
8952 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8953 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8954
8955 /* XXX:
8956 * For state trackers other than OpenGL, we'll want to use
8957 * _RECIP_IEEE instead.
8958 */
8959 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
8960
8961 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
8962 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8963 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8964 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8965 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8966 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8967 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8968 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8969 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8970 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8971 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8972 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8973 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8974 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8975 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8976 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8977 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
8978 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8979 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8980 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8981 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8982 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8983 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8984 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8985 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
8986 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
8987 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
8988 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8989 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8990 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8991 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8992 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8993 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
8994 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8995 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8996 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8997 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8998 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8999 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9000 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9001 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9002 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9003 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9004 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9005 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9006 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9007 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9008 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9009 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9010 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9011 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9012 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9013 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9014 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9015 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9016 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9017 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9018 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9019 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9020 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9021 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9022 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9023 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9024 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9025 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9026 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9027 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9028 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9029 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9030 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9031 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9032 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9033 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9034 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9035 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9036 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9037 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9038 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9039 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9040 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9041 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9042 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9043 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9044 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9045 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9046 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9047 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9048 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9049 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9050 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9051 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9052 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9053 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9054 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9055 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9056 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9057 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9058 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9059 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9060 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9061 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9062 [105] = { ALU_OP0_NOP, tgsi_unsupported},
9063 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9064 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9065 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9066 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9067 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9068 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9069 [112] = { ALU_OP0_NOP, tgsi_unsupported},
9070 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9071 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9072 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
9073 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9074 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9075 [118] = { ALU_OP0_NOP, tgsi_unsupported},
9076 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9077 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9078 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9079 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9080 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9081 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9082 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9083 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9084 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9085 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9086 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9087 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9088 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9089 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9090 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9091 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9092 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9093 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9094 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9095 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9096 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9097 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9098 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9099 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9100 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9101 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9102 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9103 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9104 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9105 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9106 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9107 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9108 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9109 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9110 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9111 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9112 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9113 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9114 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9115 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9116 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9117 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9118 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9119 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9120 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9121 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9122 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9123 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9124 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9125 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9126 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9127 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9128 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9129 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9130 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9131 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9132 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9133 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9134 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9135 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9136 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9137 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9138 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9139 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9140 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9141 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9142 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9143 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9144 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9145 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9146 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9147 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9148 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9149 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9150 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9151 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9152 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9153 };
9154
9155 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9156 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9157 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9158 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9159 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9160 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
9161 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9162 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9163 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9164 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9165 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9166 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9167 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9168 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9169 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9170 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9171 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9172 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9173 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
9174 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9175 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9176 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9177 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9178 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9179 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9180 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9181 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9182 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9183 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9184 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9185 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9186 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9187 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9188 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9189 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
9190 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9191 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9192 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9193 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9194 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9195 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9196 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9197 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9198 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9199 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9200 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9201 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9202 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9203 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9204 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9205 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9206 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9207 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9208 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9209 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9210 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9211 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9212 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9213 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9214 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9215 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9216 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9217 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9218 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9219 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9220 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9221 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9222 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9223 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9224 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9225 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9226 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9227 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9228 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9229 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9230 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9231 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9232 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9233 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9234 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9235 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9236 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9237 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9238 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9239 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9240 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9241 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9242 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9243 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9244 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9245 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9246 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9247 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9248 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9249 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9250 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9251 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9252 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9253 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9254 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9255 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9256 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9257 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9258 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9259 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9260 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9261 [105] = { ALU_OP0_NOP, tgsi_unsupported},
9262 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9263 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9264 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9265 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9266 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9267 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9268 [112] = { ALU_OP0_NOP, tgsi_unsupported},
9269 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9270 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9271 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9272 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9273 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9274 [118] = { ALU_OP0_NOP, tgsi_unsupported},
9275 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9276 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9277 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9278 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9279 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9280 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9281 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9282 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9283 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9284 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9285 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9286 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9287 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9288 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9289 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9290 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9291 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9292 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9293 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9294 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9295 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9296 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9297 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9298 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9299 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9300 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9301 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9302 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9303 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9304 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9305 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9306 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9307 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9308 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9309 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9310 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9311 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9312 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9313 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9314 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9315 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9316 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9317 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9318 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9319 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9320 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9321 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9322 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9323 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9324 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9325 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9326 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9327 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9328 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9329 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9330 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9331 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9332 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9333 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9334 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9335 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9336 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9337 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9338 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9339 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9340 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9341 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9342 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9343 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9344 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9345 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9346 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9347 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9348 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9349 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9350 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9351 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9352 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9353 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9354 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9355 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9356 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9357 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9358 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9359 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9360 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9361 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9362 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9363 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9364 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9365 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9366 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9367 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9368 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9369 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9370 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9371 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9372 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9373 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9374 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9375 };
9376
9377 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9378 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9379 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9380 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9381 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9382 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9383 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9384 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9385 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9386 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9387 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9388 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9389 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9390 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9391 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9392 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9393 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9394 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9395 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
9396 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9397 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9398 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9399 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9400 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9401 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9402 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9403 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9404 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9405 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9406 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9407 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9408 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9409 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9410 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9411 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
9412 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9413 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9414 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9415 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9416 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9417 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9418 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9419 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9420 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9421 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9422 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9423 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9424 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9425 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9426 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9427 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9428 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9429 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9430 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9431 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9432 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9433 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9434 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9435 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9436 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9437 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9438 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9439 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9440 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9441 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9442 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9443 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9444 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9445 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9446 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9447 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9448 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9449 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9450 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9451 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9452 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9453 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9454 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9455 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9456 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9457 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9458 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9459 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9460 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9461 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9462 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9463 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9464 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9465 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9466 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9467 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9468 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9469 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9470 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9471 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9472 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9473 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9474 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9475 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9476 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9477 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9478 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9479 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9480 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9481 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9482 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9483 [105] = { ALU_OP0_NOP, tgsi_unsupported},
9484 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9485 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9486 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9487 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9488 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9489 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9490 [112] = { ALU_OP0_NOP, tgsi_unsupported},
9491 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9492 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9493 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9494 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9495 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9496 [118] = { ALU_OP0_NOP, tgsi_unsupported},
9497 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9498 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9499 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9500 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9501 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9502 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9503 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9504 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9505 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9506 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9507 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9508 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9509 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9510 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9511 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9512 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9513 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9514 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9515 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9516 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9517 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9518 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9519 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9520 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9521 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9522 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9523 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9524 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9525 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9526 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9527 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9528 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9529 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9530 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9531 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9532 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9533 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9534 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9535 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9536 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9537 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9538 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9539 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9540 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9541 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9542 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9543 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9544 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9545 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9546 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9547 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9548 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9549 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9550 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9551 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9552 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9553 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9554 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9555 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9556 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9557 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9558 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9559 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9560 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9561 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9562 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9563 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9564 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9565 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9566 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9567 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9568 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9569 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9570 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9571 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9572 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9573 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9574 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9575 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9576 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9577 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9578 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9579 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9580 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9581 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9582 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9583 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9584 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9585 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9586 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9587 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9588 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9589 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9590 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9591 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9592 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9593 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9594 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9595 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9596 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9597 };