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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 use_sb &= !shader->shader.uses_atomics;
198 use_sb &= !shader->shader.uses_images;
199
200 /* Check if the bytecode has already been built. */
201 if (!shader->shader.bc.bytecode) {
202 r = r600_bytecode_build(&shader->shader.bc);
203 if (r) {
204 R600_ERR("building bytecode failed !\n");
205 goto error;
206 }
207 }
208
209 if (dump && !sb_disasm) {
210 fprintf(stderr, "--------------------------------------------------------------\n");
211 r600_bytecode_disasm(&shader->shader.bc);
212 fprintf(stderr, "______________________________________________________________\n");
213 } else if ((dump && sb_disasm) || use_sb) {
214 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
215 dump, use_sb);
216 if (r) {
217 R600_ERR("r600_sb_bytecode_process failed !\n");
218 goto error;
219 }
220 }
221
222 if (shader->gs_copy_shader) {
223 if (dump) {
224 // dump copy shader
225 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
226 &shader->gs_copy_shader->shader, dump, 0);
227 if (r)
228 goto error;
229 }
230
231 if ((r = store_shader(ctx, shader->gs_copy_shader)))
232 goto error;
233 }
234
235 /* Store the shader in a buffer. */
236 if ((r = store_shader(ctx, shader)))
237 goto error;
238
239 /* Build state. */
240 switch (shader->shader.processor_type) {
241 case PIPE_SHADER_TESS_CTRL:
242 evergreen_update_hs_state(ctx, shader);
243 break;
244 case PIPE_SHADER_TESS_EVAL:
245 if (key.tes.as_es)
246 evergreen_update_es_state(ctx, shader);
247 else
248 evergreen_update_vs_state(ctx, shader);
249 break;
250 case PIPE_SHADER_GEOMETRY:
251 if (rctx->b.chip_class >= EVERGREEN) {
252 evergreen_update_gs_state(ctx, shader);
253 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
254 } else {
255 r600_update_gs_state(ctx, shader);
256 r600_update_vs_state(ctx, shader->gs_copy_shader);
257 }
258 break;
259 case PIPE_SHADER_VERTEX:
260 export_shader = key.vs.as_es;
261 if (rctx->b.chip_class >= EVERGREEN) {
262 if (key.vs.as_ls)
263 evergreen_update_ls_state(ctx, shader);
264 else if (key.vs.as_es)
265 evergreen_update_es_state(ctx, shader);
266 else
267 evergreen_update_vs_state(ctx, shader);
268 } else {
269 if (export_shader)
270 r600_update_es_state(ctx, shader);
271 else
272 r600_update_vs_state(ctx, shader);
273 }
274 break;
275 case PIPE_SHADER_FRAGMENT:
276 if (rctx->b.chip_class >= EVERGREEN) {
277 evergreen_update_ps_state(ctx, shader);
278 } else {
279 r600_update_ps_state(ctx, shader);
280 }
281 break;
282 default:
283 r = -EINVAL;
284 goto error;
285 }
286 return 0;
287
288 error:
289 r600_pipe_shader_destroy(ctx, shader);
290 return r;
291 }
292
293 void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
294 {
295 r600_resource_reference(&shader->bo, NULL);
296 r600_bytecode_clear(&shader->shader.bc);
297 r600_release_command_buffer(&shader->command_buffer);
298 }
299
300 /*
301 * tgsi -> r600 shader
302 */
303 struct r600_shader_tgsi_instruction;
304
305 struct r600_shader_src {
306 unsigned sel;
307 unsigned swizzle[4];
308 unsigned neg;
309 unsigned abs;
310 unsigned rel;
311 unsigned kc_bank;
312 boolean kc_rel; /* true if cache bank is indexed */
313 uint32_t value[4];
314 };
315
316 struct eg_interp {
317 boolean enabled;
318 unsigned ij_index;
319 };
320
321 struct r600_shader_ctx {
322 struct tgsi_shader_info info;
323 struct tgsi_parse_context parse;
324 const struct tgsi_token *tokens;
325 unsigned type;
326 unsigned file_offset[TGSI_FILE_COUNT];
327 unsigned temp_reg;
328 const struct r600_shader_tgsi_instruction *inst_info;
329 struct r600_bytecode *bc;
330 struct r600_shader *shader;
331 struct r600_shader_src src[4];
332 uint32_t *literals;
333 uint32_t nliterals;
334 uint32_t max_driver_temp_used;
335 /* needed for evergreen interpolation */
336 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
337 /* evergreen/cayman also store sample mask in face register */
338 int face_gpr;
339 /* sample id is .w component stored in fixed point position register */
340 int fixed_pt_position_gpr;
341 int colors_used;
342 boolean clip_vertex_write;
343 unsigned cv_output;
344 unsigned edgeflag_output;
345 int fragcoord_input;
346 int native_integers;
347 int next_ring_offset;
348 int gs_out_ring_offset;
349 int gs_next_vertex;
350 struct r600_shader *gs_for_vs;
351 int gs_export_gpr_tregs[4];
352 int gs_rotated_input[2];
353 const struct pipe_stream_output_info *gs_stream_output_info;
354 unsigned enabled_stream_buffers_mask;
355 unsigned tess_input_info; /* temp with tess input offsets */
356 unsigned tess_output_info; /* temp with tess input offsets */
357 unsigned thread_id_gpr; /* temp with thread id calculated for images */
358 bool thread_id_gpr_loaded;
359 };
360
361 struct r600_shader_tgsi_instruction {
362 unsigned op;
363 int (*process)(struct r600_shader_ctx *ctx);
364 };
365
366 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
367 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
368 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
369 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
370 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
371 static int tgsi_else(struct r600_shader_ctx *ctx);
372 static int tgsi_endif(struct r600_shader_ctx *ctx);
373 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
374 static int tgsi_endloop(struct r600_shader_ctx *ctx);
375 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
376 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
377 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
378 unsigned int dst_reg);
379 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
380 const struct r600_shader_src *shader_src,
381 unsigned chan);
382 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
383 unsigned dst_reg, unsigned mask);
384
385 static int tgsi_last_instruction(unsigned writemask)
386 {
387 int i, lasti = 0;
388
389 for (i = 0; i < 4; i++) {
390 if (writemask & (1 << i)) {
391 lasti = i;
392 }
393 }
394 return lasti;
395 }
396
397 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
398 {
399 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
400 unsigned j;
401
402 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
403 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
404 return -EINVAL;
405 }
406 #if 0
407 if (i->Instruction.Label) {
408 R600_ERR("label unsupported\n");
409 return -EINVAL;
410 }
411 #endif
412 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
413 if (i->Src[j].Register.Dimension) {
414 switch (i->Src[j].Register.File) {
415 case TGSI_FILE_CONSTANT:
416 case TGSI_FILE_HW_ATOMIC:
417 break;
418 case TGSI_FILE_INPUT:
419 if (ctx->type == PIPE_SHADER_GEOMETRY ||
420 ctx->type == PIPE_SHADER_TESS_CTRL ||
421 ctx->type == PIPE_SHADER_TESS_EVAL)
422 break;
423 case TGSI_FILE_OUTPUT:
424 if (ctx->type == PIPE_SHADER_TESS_CTRL)
425 break;
426 default:
427 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
428 i->Src[j].Register.File,
429 i->Src[j].Register.Dimension);
430 return -EINVAL;
431 }
432 }
433 }
434 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
435 if (i->Dst[j].Register.Dimension) {
436 if (ctx->type == PIPE_SHADER_TESS_CTRL)
437 continue;
438 R600_ERR("unsupported dst (dimension)\n");
439 return -EINVAL;
440 }
441 }
442 return 0;
443 }
444
445 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
446 {
447 if (interpolate == TGSI_INTERPOLATE_COLOR ||
448 interpolate == TGSI_INTERPOLATE_LINEAR ||
449 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
450 {
451 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
452 int loc;
453
454 switch(location) {
455 case TGSI_INTERPOLATE_LOC_CENTER:
456 loc = 1;
457 break;
458 case TGSI_INTERPOLATE_LOC_CENTROID:
459 loc = 2;
460 break;
461 case TGSI_INTERPOLATE_LOC_SAMPLE:
462 default:
463 loc = 0; break;
464 }
465
466 return is_linear * 3 + loc;
467 }
468
469 return -1;
470 }
471
472 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
473 int input)
474 {
475 int i = eg_get_interpolator_index(
476 ctx->shader->input[input].interpolate,
477 ctx->shader->input[input].interpolate_location);
478 assert(i >= 0);
479 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
480 }
481
482 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
483 {
484 int i, r;
485 struct r600_bytecode_alu alu;
486 int gpr = 0, base_chan = 0;
487 int ij_index = ctx->shader->input[input].ij_index;
488
489 /* work out gpr and base_chan from index */
490 gpr = ij_index / 2;
491 base_chan = (2 * (ij_index % 2)) + 1;
492
493 for (i = 0; i < 8; i++) {
494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
495
496 if (i < 4)
497 alu.op = ALU_OP2_INTERP_ZW;
498 else
499 alu.op = ALU_OP2_INTERP_XY;
500
501 if ((i > 1) && (i < 6)) {
502 alu.dst.sel = ctx->shader->input[input].gpr;
503 alu.dst.write = 1;
504 }
505
506 alu.dst.chan = i % 4;
507
508 alu.src[0].sel = gpr;
509 alu.src[0].chan = (base_chan - (i % 2));
510
511 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
512
513 alu.bank_swizzle_force = SQ_ALU_VEC_210;
514 if ((i % 4) == 3)
515 alu.last = 1;
516 r = r600_bytecode_add_alu(ctx->bc, &alu);
517 if (r)
518 return r;
519 }
520 return 0;
521 }
522
523 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
524 {
525 int i, r;
526 struct r600_bytecode_alu alu;
527
528 for (i = 0; i < 4; i++) {
529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
530
531 alu.op = ALU_OP1_INTERP_LOAD_P0;
532
533 alu.dst.sel = ctx->shader->input[input].gpr;
534 alu.dst.write = 1;
535
536 alu.dst.chan = i;
537
538 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
539 alu.src[0].chan = i;
540
541 if (i == 3)
542 alu.last = 1;
543 r = r600_bytecode_add_alu(ctx->bc, &alu);
544 if (r)
545 return r;
546 }
547 return 0;
548 }
549
550 /*
551 * Special export handling in shaders
552 *
553 * shader export ARRAY_BASE for EXPORT_POS:
554 * 60 is position
555 * 61 is misc vector
556 * 62, 63 are clip distance vectors
557 *
558 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
559 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
560 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
561 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
562 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
563 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
564 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
565 * exclusive from render target index)
566 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
567 *
568 *
569 * shader export ARRAY_BASE for EXPORT_PIXEL:
570 * 0-7 CB targets
571 * 61 computed Z vector
572 *
573 * The use of the values exported in the computed Z vector are controlled
574 * by DB_SHADER_CONTROL:
575 * Z_EXPORT_ENABLE - Z as a float in RED
576 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
577 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
578 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
579 * DB_SOURCE_FORMAT - export control restrictions
580 *
581 */
582
583
584 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
585 static int r600_spi_sid(struct r600_shader_io * io)
586 {
587 int index, name = io->name;
588
589 /* These params are handled differently, they don't need
590 * semantic indices, so we'll use 0 for them.
591 */
592 if (name == TGSI_SEMANTIC_POSITION ||
593 name == TGSI_SEMANTIC_PSIZE ||
594 name == TGSI_SEMANTIC_EDGEFLAG ||
595 name == TGSI_SEMANTIC_FACE ||
596 name == TGSI_SEMANTIC_SAMPLEMASK)
597 index = 0;
598 else {
599 if (name == TGSI_SEMANTIC_GENERIC) {
600 /* For generic params simply use sid from tgsi */
601 index = io->sid;
602 } else {
603 /* For non-generic params - pack name and sid into 8 bits */
604 index = 0x80 | (name<<3) | (io->sid);
605 }
606
607 /* Make sure that all really used indices have nonzero value, so
608 * we can just compare it to 0 later instead of comparing the name
609 * with different values to detect special cases. */
610 index++;
611 }
612
613 return index;
614 };
615
616 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
617 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
618 {
619 switch (semantic_name) {
620 case TGSI_SEMANTIC_POSITION:
621 return 0;
622 case TGSI_SEMANTIC_PSIZE:
623 return 1;
624 case TGSI_SEMANTIC_CLIPDIST:
625 assert(index <= 1);
626 return 2 + index;
627 case TGSI_SEMANTIC_GENERIC:
628 if (index <= 63-4)
629 return 4 + index - 9;
630 else
631 /* same explanation as in the default statement,
632 * the only user hitting this is st/nine.
633 */
634 return 0;
635
636 /* patch indices are completely separate and thus start from 0 */
637 case TGSI_SEMANTIC_TESSOUTER:
638 return 0;
639 case TGSI_SEMANTIC_TESSINNER:
640 return 1;
641 case TGSI_SEMANTIC_PATCH:
642 return 2 + index;
643
644 default:
645 /* Don't fail here. The result of this function is only used
646 * for LS, TCS, TES, and GS, where legacy GL semantics can't
647 * occur, but this function is called for all vertex shaders
648 * before it's known whether LS will be compiled or not.
649 */
650 return 0;
651 }
652 }
653
654 /* turn input into interpolate on EG */
655 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
656 {
657 int r = 0;
658
659 if (ctx->shader->input[index].spi_sid) {
660 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
661 if (ctx->shader->input[index].interpolate > 0) {
662 evergreen_interp_assign_ij_index(ctx, index);
663 r = evergreen_interp_alu(ctx, index);
664 } else {
665 r = evergreen_interp_flat(ctx, index);
666 }
667 }
668 return r;
669 }
670
671 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
672 {
673 struct r600_bytecode_alu alu;
674 int i, r;
675 int gpr_front = ctx->shader->input[front].gpr;
676 int gpr_back = ctx->shader->input[back].gpr;
677
678 for (i = 0; i < 4; i++) {
679 memset(&alu, 0, sizeof(alu));
680 alu.op = ALU_OP3_CNDGT;
681 alu.is_op3 = 1;
682 alu.dst.write = 1;
683 alu.dst.sel = gpr_front;
684 alu.src[0].sel = ctx->face_gpr;
685 alu.src[1].sel = gpr_front;
686 alu.src[2].sel = gpr_back;
687
688 alu.dst.chan = i;
689 alu.src[1].chan = i;
690 alu.src[2].chan = i;
691 alu.last = (i==3);
692
693 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
694 return r;
695 }
696
697 return 0;
698 }
699
700 /* execute a single slot ALU calculation */
701 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
702 int dst_sel, int dst_chan,
703 int src0_sel, unsigned src0_chan_val,
704 int src1_sel, unsigned src1_chan_val)
705 {
706 struct r600_bytecode_alu alu;
707 int r, i;
708
709 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
710 for (i = 0; i < 4; i++) {
711 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
712 alu.op = op;
713 alu.src[0].sel = src0_sel;
714 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
715 alu.src[0].value = src0_chan_val;
716 else
717 alu.src[0].chan = src0_chan_val;
718 alu.src[1].sel = src1_sel;
719 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
720 alu.src[1].value = src1_chan_val;
721 else
722 alu.src[1].chan = src1_chan_val;
723 alu.dst.sel = dst_sel;
724 alu.dst.chan = i;
725 alu.dst.write = i == dst_chan;
726 alu.last = (i == 3);
727 r = r600_bytecode_add_alu(ctx->bc, &alu);
728 if (r)
729 return r;
730 }
731 return 0;
732 }
733
734 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
735 alu.op = op;
736 alu.src[0].sel = src0_sel;
737 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
738 alu.src[0].value = src0_chan_val;
739 else
740 alu.src[0].chan = src0_chan_val;
741 alu.src[1].sel = src1_sel;
742 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
743 alu.src[1].value = src1_chan_val;
744 else
745 alu.src[1].chan = src1_chan_val;
746 alu.dst.sel = dst_sel;
747 alu.dst.chan = dst_chan;
748 alu.dst.write = 1;
749 alu.last = 1;
750 r = r600_bytecode_add_alu(ctx->bc, &alu);
751 if (r)
752 return r;
753 return 0;
754 }
755
756 /* execute a single slot ALU calculation */
757 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
758 int dst_sel, int dst_chan,
759 int src0_sel, unsigned src0_chan_val,
760 int src1_sel, unsigned src1_chan_val,
761 int src2_sel, unsigned src2_chan_val)
762 {
763 struct r600_bytecode_alu alu;
764 int r;
765
766 /* validate this for other ops */
767 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
768 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
769 alu.op = op;
770 alu.src[0].sel = src0_sel;
771 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
772 alu.src[0].value = src0_chan_val;
773 else
774 alu.src[0].chan = src0_chan_val;
775 alu.src[1].sel = src1_sel;
776 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
777 alu.src[1].value = src1_chan_val;
778 else
779 alu.src[1].chan = src1_chan_val;
780 alu.src[2].sel = src2_sel;
781 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
782 alu.src[2].value = src2_chan_val;
783 else
784 alu.src[2].chan = src2_chan_val;
785 alu.dst.sel = dst_sel;
786 alu.dst.chan = dst_chan;
787 alu.is_op3 = 1;
788 alu.last = 1;
789 r = r600_bytecode_add_alu(ctx->bc, &alu);
790 if (r)
791 return r;
792 return 0;
793 }
794
795 /* put it in temp_reg.x */
796 static int get_lds_offset0(struct r600_shader_ctx *ctx,
797 int rel_patch_chan,
798 int temp_reg, bool is_patch_var)
799 {
800 int r;
801
802 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
803 /* ADD
804 Dimension - patch0_offset (input_vals.z),
805 Non-dim - patch0_data_offset (input_vals.w)
806 */
807 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
808 temp_reg, 0,
809 ctx->tess_output_info, 0,
810 0, rel_patch_chan,
811 ctx->tess_output_info, is_patch_var ? 3 : 2);
812 if (r)
813 return r;
814 return 0;
815 }
816
817 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
818 {
819 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
820 }
821
822 static int r600_get_temp(struct r600_shader_ctx *ctx)
823 {
824 return ctx->temp_reg + ctx->max_driver_temp_used++;
825 }
826
827 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
828 {
829 int i;
830 i = ctx->shader->noutput++;
831 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
832 ctx->shader->output[i].sid = 0;
833 ctx->shader->output[i].gpr = 0;
834 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
835 ctx->shader->output[i].write_mask = 0x4;
836 ctx->shader->output[i].spi_sid = prim_id_sid;
837
838 return 0;
839 }
840
841 static int tgsi_barrier(struct r600_shader_ctx *ctx)
842 {
843 struct r600_bytecode_alu alu;
844 int r;
845
846 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
847 alu.op = ctx->inst_info->op;
848 alu.last = 1;
849
850 r = r600_bytecode_add_alu(ctx->bc, &alu);
851 if (r)
852 return r;
853 return 0;
854 }
855
856 static int tgsi_declaration(struct r600_shader_ctx *ctx)
857 {
858 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
859 int r, i, j, count = d->Range.Last - d->Range.First + 1;
860
861 switch (d->Declaration.File) {
862 case TGSI_FILE_INPUT:
863 for (j = 0; j < count; j++) {
864 i = ctx->shader->ninput + j;
865 assert(i < ARRAY_SIZE(ctx->shader->input));
866 ctx->shader->input[i].name = d->Semantic.Name;
867 ctx->shader->input[i].sid = d->Semantic.Index + j;
868 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
869 ctx->shader->input[i].interpolate_location = d->Interp.Location;
870 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
871 if (ctx->type == PIPE_SHADER_FRAGMENT) {
872 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
873 switch (ctx->shader->input[i].name) {
874 case TGSI_SEMANTIC_FACE:
875 if (ctx->face_gpr != -1)
876 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
877 else
878 ctx->face_gpr = ctx->shader->input[i].gpr;
879 break;
880 case TGSI_SEMANTIC_COLOR:
881 ctx->colors_used++;
882 break;
883 case TGSI_SEMANTIC_POSITION:
884 ctx->fragcoord_input = i;
885 break;
886 case TGSI_SEMANTIC_PRIMID:
887 /* set this for now */
888 ctx->shader->gs_prim_id_input = true;
889 ctx->shader->ps_prim_id_input = i;
890 break;
891 }
892 if (ctx->bc->chip_class >= EVERGREEN) {
893 if ((r = evergreen_interp_input(ctx, i)))
894 return r;
895 }
896 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
897 /* FIXME probably skip inputs if they aren't passed in the ring */
898 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
899 ctx->next_ring_offset += 16;
900 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
901 ctx->shader->gs_prim_id_input = true;
902 }
903 }
904 ctx->shader->ninput += count;
905 break;
906 case TGSI_FILE_OUTPUT:
907 for (j = 0; j < count; j++) {
908 i = ctx->shader->noutput + j;
909 assert(i < ARRAY_SIZE(ctx->shader->output));
910 ctx->shader->output[i].name = d->Semantic.Name;
911 ctx->shader->output[i].sid = d->Semantic.Index + j;
912 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
913 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
914 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
915 if (ctx->type == PIPE_SHADER_VERTEX ||
916 ctx->type == PIPE_SHADER_GEOMETRY ||
917 ctx->type == PIPE_SHADER_TESS_EVAL) {
918 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
919 switch (d->Semantic.Name) {
920 case TGSI_SEMANTIC_CLIPDIST:
921 break;
922 case TGSI_SEMANTIC_PSIZE:
923 ctx->shader->vs_out_misc_write = 1;
924 ctx->shader->vs_out_point_size = 1;
925 break;
926 case TGSI_SEMANTIC_EDGEFLAG:
927 ctx->shader->vs_out_misc_write = 1;
928 ctx->shader->vs_out_edgeflag = 1;
929 ctx->edgeflag_output = i;
930 break;
931 case TGSI_SEMANTIC_VIEWPORT_INDEX:
932 ctx->shader->vs_out_misc_write = 1;
933 ctx->shader->vs_out_viewport = 1;
934 break;
935 case TGSI_SEMANTIC_LAYER:
936 ctx->shader->vs_out_misc_write = 1;
937 ctx->shader->vs_out_layer = 1;
938 break;
939 case TGSI_SEMANTIC_CLIPVERTEX:
940 ctx->clip_vertex_write = TRUE;
941 ctx->cv_output = i;
942 break;
943 }
944 if (ctx->type == PIPE_SHADER_GEOMETRY) {
945 ctx->gs_out_ring_offset += 16;
946 }
947 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
948 switch (d->Semantic.Name) {
949 case TGSI_SEMANTIC_COLOR:
950 ctx->shader->nr_ps_max_color_exports++;
951 break;
952 }
953 }
954 }
955 ctx->shader->noutput += count;
956 break;
957 case TGSI_FILE_TEMPORARY:
958 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
959 if (d->Array.ArrayID) {
960 r600_add_gpr_array(ctx->shader,
961 ctx->file_offset[TGSI_FILE_TEMPORARY] +
962 d->Range.First,
963 d->Range.Last - d->Range.First + 1, 0x0F);
964 }
965 }
966 break;
967
968 case TGSI_FILE_CONSTANT:
969 case TGSI_FILE_SAMPLER:
970 case TGSI_FILE_SAMPLER_VIEW:
971 case TGSI_FILE_ADDRESS:
972 case TGSI_FILE_BUFFER:
973 case TGSI_FILE_IMAGE:
974 case TGSI_FILE_MEMORY:
975 break;
976
977 case TGSI_FILE_HW_ATOMIC:
978 i = ctx->shader->nhwatomic_ranges;
979 ctx->shader->atomics[i].start = d->Range.First;
980 ctx->shader->atomics[i].end = d->Range.Last;
981 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
982 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
983 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
984 ctx->shader->nhwatomic_ranges++;
985 ctx->shader->nhwatomic += count;
986 break;
987
988 case TGSI_FILE_SYSTEM_VALUE:
989 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
990 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
991 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
992 break; /* Already handled from allocate_system_value_inputs */
993 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
994 if (!ctx->native_integers) {
995 struct r600_bytecode_alu alu;
996 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
997
998 alu.op = ALU_OP1_INT_TO_FLT;
999 alu.src[0].sel = 0;
1000 alu.src[0].chan = 3;
1001
1002 alu.dst.sel = 0;
1003 alu.dst.chan = 3;
1004 alu.dst.write = 1;
1005 alu.last = 1;
1006
1007 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1008 return r;
1009 }
1010 break;
1011 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1012 break;
1013 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1014 break;
1015 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1016 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1017 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1018 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1019 unsigned temp_reg = r600_get_temp(ctx);
1020
1021 r = get_lds_offset0(ctx, 2, temp_reg, true);
1022 if (r)
1023 return r;
1024
1025 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1026 temp_reg, 0,
1027 temp_reg, 0,
1028 V_SQ_ALU_SRC_LITERAL, param * 16);
1029 if (r)
1030 return r;
1031
1032 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
1033 }
1034 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1035 /* MOV r1.x, r0.x;
1036 MOV r1.y, r0.y;
1037 */
1038 for (i = 0; i < 2; i++) {
1039 struct r600_bytecode_alu alu;
1040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1041 alu.op = ALU_OP1_MOV;
1042 alu.src[0].sel = 0;
1043 alu.src[0].chan = 0 + i;
1044 alu.dst.sel = 1;
1045 alu.dst.chan = 0 + i;
1046 alu.dst.write = 1;
1047 alu.last = (i == 1) ? 1 : 0;
1048 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1049 return r;
1050 }
1051 /* ADD r1.z, 1.0f, -r0.x */
1052 struct r600_bytecode_alu alu;
1053 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1054 alu.op = ALU_OP2_ADD;
1055 alu.src[0].sel = V_SQ_ALU_SRC_1;
1056 alu.src[1].sel = 1;
1057 alu.src[1].chan = 0;
1058 alu.src[1].neg = 1;
1059 alu.dst.sel = 1;
1060 alu.dst.chan = 2;
1061 alu.dst.write = 1;
1062 alu.last = 1;
1063 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1064 return r;
1065
1066 /* ADD r1.z, r1.z, -r1.y */
1067 alu.op = ALU_OP2_ADD;
1068 alu.src[0].sel = 1;
1069 alu.src[0].chan = 2;
1070 alu.src[1].sel = 1;
1071 alu.src[1].chan = 1;
1072 alu.src[1].neg = 1;
1073 alu.dst.sel = 1;
1074 alu.dst.chan = 2;
1075 alu.dst.write = 1;
1076 alu.last = 1;
1077 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1078 return r;
1079 break;
1080 }
1081 break;
1082 default:
1083 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1084 return -EINVAL;
1085 }
1086 return 0;
1087 }
1088
1089 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1090 {
1091 struct tgsi_parse_context parse;
1092 struct {
1093 boolean enabled;
1094 int *reg;
1095 unsigned name, alternate_name;
1096 } inputs[2] = {
1097 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1098
1099 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1100 };
1101 int num_regs = 0;
1102 unsigned k, i;
1103
1104 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1105 return 0;
1106 }
1107
1108 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1109 while (!tgsi_parse_end_of_tokens(&parse)) {
1110 tgsi_parse_token(&parse);
1111
1112 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1113 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1114 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1115 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1116 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1117 {
1118 int interpolate, location, k;
1119
1120 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1121 location = TGSI_INTERPOLATE_LOC_CENTER;
1122 inputs[1].enabled = true; /* needs SAMPLEID */
1123 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1124 location = TGSI_INTERPOLATE_LOC_CENTER;
1125 /* Needs sample positions, currently those are always available */
1126 } else {
1127 location = TGSI_INTERPOLATE_LOC_CENTROID;
1128 }
1129
1130 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1131 k = eg_get_interpolator_index(interpolate, location);
1132 if (k >= 0)
1133 ctx->eg_interpolators[k].enabled = true;
1134 }
1135 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1136 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1137 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1138 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1139 if (d->Semantic.Name == inputs[k].name ||
1140 d->Semantic.Name == inputs[k].alternate_name) {
1141 inputs[k].enabled = true;
1142 }
1143 }
1144 }
1145 }
1146 }
1147
1148 tgsi_parse_free(&parse);
1149
1150 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1151 boolean enabled = inputs[i].enabled;
1152 int *reg = inputs[i].reg;
1153 unsigned name = inputs[i].name;
1154
1155 if (enabled) {
1156 int gpr = gpr_offset + num_regs++;
1157 ctx->shader->nsys_inputs++;
1158
1159 // add to inputs, allocate a gpr
1160 k = ctx->shader->ninput++;
1161 ctx->shader->input[k].name = name;
1162 ctx->shader->input[k].sid = 0;
1163 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1164 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1165 *reg = ctx->shader->input[k].gpr = gpr;
1166 }
1167 }
1168
1169 return gpr_offset + num_regs;
1170 }
1171
1172 /*
1173 * for evergreen we need to scan the shader to find the number of GPRs we need to
1174 * reserve for interpolation and system values
1175 *
1176 * we need to know if we are going to emit
1177 * any sample or centroid inputs
1178 * if perspective and linear are required
1179 */
1180 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1181 {
1182 unsigned i;
1183 int num_baryc;
1184 struct tgsi_parse_context parse;
1185
1186 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1187
1188 for (i = 0; i < ctx->info.num_inputs; i++) {
1189 int k;
1190 /* skip position/face/mask/sampleid */
1191 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1192 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1193 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1194 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1195 continue;
1196
1197 k = eg_get_interpolator_index(
1198 ctx->info.input_interpolate[i],
1199 ctx->info.input_interpolate_loc[i]);
1200 if (k >= 0)
1201 ctx->eg_interpolators[k].enabled = TRUE;
1202 }
1203
1204 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1205 return 0;
1206 }
1207
1208 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1209 while (!tgsi_parse_end_of_tokens(&parse)) {
1210 tgsi_parse_token(&parse);
1211
1212 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1213 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1214 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1215 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1216 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1217 {
1218 int interpolate, location, k;
1219
1220 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1221 location = TGSI_INTERPOLATE_LOC_CENTER;
1222 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1223 location = TGSI_INTERPOLATE_LOC_CENTER;
1224 } else {
1225 location = TGSI_INTERPOLATE_LOC_CENTROID;
1226 }
1227
1228 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1229 k = eg_get_interpolator_index(interpolate, location);
1230 if (k >= 0)
1231 ctx->eg_interpolators[k].enabled = true;
1232 }
1233 }
1234 }
1235
1236 tgsi_parse_free(&parse);
1237
1238 /* assign gpr to each interpolator according to priority */
1239 num_baryc = 0;
1240 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1241 if (ctx->eg_interpolators[i].enabled) {
1242 ctx->eg_interpolators[i].ij_index = num_baryc;
1243 num_baryc ++;
1244 }
1245 }
1246
1247 /* XXX PULL MODEL and LINE STIPPLE */
1248
1249 num_baryc = (num_baryc + 1) >> 1;
1250 return allocate_system_value_inputs(ctx, num_baryc);
1251 }
1252
1253 /* sample_id_sel == NULL means fetch for current sample */
1254 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1255 {
1256 struct r600_bytecode_vtx vtx;
1257 int r, t1;
1258
1259 assert(ctx->fixed_pt_position_gpr != -1);
1260
1261 t1 = r600_get_temp(ctx);
1262
1263 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1264 vtx.op = FETCH_OP_VFETCH;
1265 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1266 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1267 if (sample_id == NULL) {
1268 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1269 vtx.src_sel_x = 3;
1270 }
1271 else {
1272 struct r600_bytecode_alu alu;
1273
1274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1275 alu.op = ALU_OP1_MOV;
1276 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1277 alu.dst.sel = t1;
1278 alu.dst.write = 1;
1279 alu.last = 1;
1280 r = r600_bytecode_add_alu(ctx->bc, &alu);
1281 if (r)
1282 return r;
1283
1284 vtx.src_gpr = t1;
1285 vtx.src_sel_x = 0;
1286 }
1287 vtx.mega_fetch_count = 16;
1288 vtx.dst_gpr = t1;
1289 vtx.dst_sel_x = 0;
1290 vtx.dst_sel_y = 1;
1291 vtx.dst_sel_z = 2;
1292 vtx.dst_sel_w = 3;
1293 vtx.data_format = FMT_32_32_32_32_FLOAT;
1294 vtx.num_format_all = 2;
1295 vtx.format_comp_all = 1;
1296 vtx.use_const_fields = 0;
1297 vtx.offset = 1; // first element is size of buffer
1298 vtx.endian = r600_endian_swap(32);
1299 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1300
1301 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1302 if (r)
1303 return r;
1304
1305 return t1;
1306 }
1307
1308 static void tgsi_src(struct r600_shader_ctx *ctx,
1309 const struct tgsi_full_src_register *tgsi_src,
1310 struct r600_shader_src *r600_src)
1311 {
1312 memset(r600_src, 0, sizeof(*r600_src));
1313 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1314 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1315 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1316 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1317 r600_src->neg = tgsi_src->Register.Negate;
1318 r600_src->abs = tgsi_src->Register.Absolute;
1319
1320 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1321 int index;
1322 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1323 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1324 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1325
1326 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1327 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1328 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1329 return;
1330 }
1331 index = tgsi_src->Register.Index;
1332 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1333 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1334 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1335 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1336 r600_src->swizzle[0] = 2; // Z value
1337 r600_src->swizzle[1] = 2;
1338 r600_src->swizzle[2] = 2;
1339 r600_src->swizzle[3] = 2;
1340 r600_src->sel = ctx->face_gpr;
1341 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1342 r600_src->swizzle[0] = 3; // W value
1343 r600_src->swizzle[1] = 3;
1344 r600_src->swizzle[2] = 3;
1345 r600_src->swizzle[3] = 3;
1346 r600_src->sel = ctx->fixed_pt_position_gpr;
1347 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1348 r600_src->swizzle[0] = 0;
1349 r600_src->swizzle[1] = 1;
1350 r600_src->swizzle[2] = 4;
1351 r600_src->swizzle[3] = 4;
1352 r600_src->sel = load_sample_position(ctx, NULL, -1);
1353 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1354 r600_src->swizzle[0] = 3;
1355 r600_src->swizzle[1] = 3;
1356 r600_src->swizzle[2] = 3;
1357 r600_src->swizzle[3] = 3;
1358 r600_src->sel = 0;
1359 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1360 r600_src->swizzle[0] = 0;
1361 r600_src->swizzle[1] = 0;
1362 r600_src->swizzle[2] = 0;
1363 r600_src->swizzle[3] = 0;
1364 r600_src->sel = 0;
1365 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1366 r600_src->swizzle[0] = 3;
1367 r600_src->swizzle[1] = 3;
1368 r600_src->swizzle[2] = 3;
1369 r600_src->swizzle[3] = 3;
1370 r600_src->sel = 1;
1371 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1372 r600_src->swizzle[0] = 2;
1373 r600_src->swizzle[1] = 2;
1374 r600_src->swizzle[2] = 2;
1375 r600_src->swizzle[3] = 2;
1376 r600_src->sel = 0;
1377 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1378 r600_src->sel = 1;
1379 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1380 r600_src->sel = 3;
1381 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1382 r600_src->sel = 2;
1383 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1384 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1385 r600_src->sel = ctx->tess_input_info;
1386 r600_src->swizzle[0] = 2;
1387 r600_src->swizzle[1] = 2;
1388 r600_src->swizzle[2] = 2;
1389 r600_src->swizzle[3] = 2;
1390 } else {
1391 r600_src->sel = ctx->tess_input_info;
1392 r600_src->swizzle[0] = 3;
1393 r600_src->swizzle[1] = 3;
1394 r600_src->swizzle[2] = 3;
1395 r600_src->swizzle[3] = 3;
1396 }
1397 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1398 r600_src->sel = 0;
1399 r600_src->swizzle[0] = 0;
1400 r600_src->swizzle[1] = 0;
1401 r600_src->swizzle[2] = 0;
1402 r600_src->swizzle[3] = 0;
1403 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1404 r600_src->sel = 0;
1405 r600_src->swizzle[0] = 3;
1406 r600_src->swizzle[1] = 3;
1407 r600_src->swizzle[2] = 3;
1408 r600_src->swizzle[3] = 3;
1409 }
1410 } else {
1411 if (tgsi_src->Register.Indirect)
1412 r600_src->rel = V_SQ_REL_RELATIVE;
1413 r600_src->sel = tgsi_src->Register.Index;
1414 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1415 }
1416 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1417 if (tgsi_src->Register.Dimension) {
1418 r600_src->kc_bank = tgsi_src->Dimension.Index;
1419 if (tgsi_src->Dimension.Indirect) {
1420 r600_src->kc_rel = 1;
1421 }
1422 }
1423 }
1424 }
1425
1426 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1427 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1428 unsigned int dst_reg)
1429 {
1430 struct r600_bytecode_vtx vtx;
1431 unsigned int ar_reg;
1432 int r;
1433
1434 if (offset) {
1435 struct r600_bytecode_alu alu;
1436
1437 memset(&alu, 0, sizeof(alu));
1438
1439 alu.op = ALU_OP2_ADD_INT;
1440 alu.src[0].sel = ctx->bc->ar_reg;
1441 alu.src[0].chan = ar_chan;
1442
1443 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1444 alu.src[1].value = offset;
1445
1446 alu.dst.sel = dst_reg;
1447 alu.dst.chan = ar_chan;
1448 alu.dst.write = 1;
1449 alu.last = 1;
1450
1451 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1452 return r;
1453
1454 ar_reg = dst_reg;
1455 } else {
1456 ar_reg = ctx->bc->ar_reg;
1457 }
1458
1459 memset(&vtx, 0, sizeof(vtx));
1460 vtx.buffer_id = cb_idx;
1461 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1462 vtx.src_gpr = ar_reg;
1463 vtx.src_sel_x = ar_chan;
1464 vtx.mega_fetch_count = 16;
1465 vtx.dst_gpr = dst_reg;
1466 vtx.dst_sel_x = 0; /* SEL_X */
1467 vtx.dst_sel_y = 1; /* SEL_Y */
1468 vtx.dst_sel_z = 2; /* SEL_Z */
1469 vtx.dst_sel_w = 3; /* SEL_W */
1470 vtx.data_format = FMT_32_32_32_32_FLOAT;
1471 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1472 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1473 vtx.endian = r600_endian_swap(32);
1474 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1475
1476 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1477 return r;
1478
1479 return 0;
1480 }
1481
1482 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1483 {
1484 struct r600_bytecode_vtx vtx;
1485 int r;
1486 unsigned index = src->Register.Index;
1487 unsigned vtx_id = src->Dimension.Index;
1488 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1489 int offset_chan = vtx_id % 3;
1490 int t2 = 0;
1491
1492 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1493 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1494
1495 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1496 offset_chan = 3;
1497
1498 if (src->Dimension.Indirect || src->Register.Indirect)
1499 t2 = r600_get_temp(ctx);
1500
1501 if (src->Dimension.Indirect) {
1502 int treg[3];
1503 struct r600_bytecode_alu alu;
1504 int r, i;
1505 unsigned addr_reg;
1506 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1507 if (src->DimIndirect.Index > 0) {
1508 r = single_alu_op2(ctx, ALU_OP1_MOV,
1509 ctx->bc->ar_reg, 0,
1510 addr_reg, 0,
1511 0, 0);
1512 if (r)
1513 return r;
1514 }
1515 /*
1516 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1517 at least this is what fglrx seems to do. */
1518 for (i = 0; i < 3; i++) {
1519 treg[i] = r600_get_temp(ctx);
1520 }
1521 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1522
1523 for (i = 0; i < 3; i++) {
1524 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1525 alu.op = ALU_OP1_MOV;
1526 alu.src[0].sel = ctx->gs_rotated_input[0];
1527 alu.src[0].chan = i == 2 ? 3 : i;
1528 alu.dst.sel = treg[i];
1529 alu.dst.chan = 0;
1530 alu.dst.write = 1;
1531 alu.last = 1;
1532 r = r600_bytecode_add_alu(ctx->bc, &alu);
1533 if (r)
1534 return r;
1535 }
1536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1537 alu.op = ALU_OP1_MOV;
1538 alu.src[0].sel = treg[0];
1539 alu.src[0].rel = 1;
1540 alu.dst.sel = t2;
1541 alu.dst.write = 1;
1542 alu.last = 1;
1543 r = r600_bytecode_add_alu(ctx->bc, &alu);
1544 if (r)
1545 return r;
1546 offset_reg = t2;
1547 offset_chan = 0;
1548 }
1549
1550 if (src->Register.Indirect) {
1551 int addr_reg;
1552 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1553
1554 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1555
1556 /* pull the value from index_reg */
1557 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1558 t2, 1,
1559 addr_reg, 0,
1560 V_SQ_ALU_SRC_LITERAL, first);
1561 if (r)
1562 return r;
1563 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1564 t2, 0,
1565 t2, 1,
1566 V_SQ_ALU_SRC_LITERAL, 4,
1567 offset_reg, offset_chan);
1568 if (r)
1569 return r;
1570 offset_reg = t2;
1571 offset_chan = 0;
1572 index = src->Register.Index - first;
1573 }
1574
1575 memset(&vtx, 0, sizeof(vtx));
1576 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1577 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1578 vtx.src_gpr = offset_reg;
1579 vtx.src_sel_x = offset_chan;
1580 vtx.offset = index * 16; /*bytes*/
1581 vtx.mega_fetch_count = 16;
1582 vtx.dst_gpr = dst_reg;
1583 vtx.dst_sel_x = 0; /* SEL_X */
1584 vtx.dst_sel_y = 1; /* SEL_Y */
1585 vtx.dst_sel_z = 2; /* SEL_Z */
1586 vtx.dst_sel_w = 3; /* SEL_W */
1587 if (ctx->bc->chip_class >= EVERGREEN) {
1588 vtx.use_const_fields = 1;
1589 } else {
1590 vtx.data_format = FMT_32_32_32_32_FLOAT;
1591 }
1592
1593 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1594 return r;
1595
1596 return 0;
1597 }
1598
1599 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1600 {
1601 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1602 unsigned i;
1603
1604 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1605 struct tgsi_full_src_register *src = &inst->Src[i];
1606
1607 if (src->Register.File == TGSI_FILE_INPUT) {
1608 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1609 /* primitive id is in R0.z */
1610 ctx->src[i].sel = 0;
1611 ctx->src[i].swizzle[0] = 2;
1612 }
1613 }
1614 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1615 int treg = r600_get_temp(ctx);
1616
1617 fetch_gs_input(ctx, src, treg);
1618 ctx->src[i].sel = treg;
1619 ctx->src[i].rel = 0;
1620 }
1621 }
1622 return 0;
1623 }
1624
1625
1626 /* Tessellation shaders pass outputs to the next shader using LDS.
1627 *
1628 * LS outputs = TCS(HS) inputs
1629 * TCS(HS) outputs = TES(DS) inputs
1630 *
1631 * The LDS layout is:
1632 * - TCS inputs for patch 0
1633 * - TCS inputs for patch 1
1634 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1635 * - ...
1636 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1637 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1638 * - TCS outputs for patch 1
1639 * - Per-patch TCS outputs for patch 1
1640 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1641 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1642 * - ...
1643 *
1644 * All three shaders VS(LS), TCS, TES share the same LDS space.
1645 */
1646 /* this will return with the dw address in temp_reg.x */
1647 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1648 const struct tgsi_full_dst_register *dst,
1649 const struct tgsi_full_src_register *src,
1650 int stride_bytes_reg, int stride_bytes_chan)
1651 {
1652 struct tgsi_full_dst_register reg;
1653 ubyte *name, *index, *array_first;
1654 int r;
1655 int param;
1656 struct tgsi_shader_info *info = &ctx->info;
1657 /* Set the register description. The address computation is the same
1658 * for sources and destinations. */
1659 if (src) {
1660 reg.Register.File = src->Register.File;
1661 reg.Register.Index = src->Register.Index;
1662 reg.Register.Indirect = src->Register.Indirect;
1663 reg.Register.Dimension = src->Register.Dimension;
1664 reg.Indirect = src->Indirect;
1665 reg.Dimension = src->Dimension;
1666 reg.DimIndirect = src->DimIndirect;
1667 } else
1668 reg = *dst;
1669
1670 /* If the register is 2-dimensional (e.g. an array of vertices
1671 * in a primitive), calculate the base address of the vertex. */
1672 if (reg.Register.Dimension) {
1673 int sel, chan;
1674 if (reg.Dimension.Indirect) {
1675 unsigned addr_reg;
1676 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1677
1678 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1679 /* pull the value from index_reg */
1680 sel = addr_reg;
1681 chan = 0;
1682 } else {
1683 sel = V_SQ_ALU_SRC_LITERAL;
1684 chan = reg.Dimension.Index;
1685 }
1686
1687 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1688 temp_reg, 0,
1689 stride_bytes_reg, stride_bytes_chan,
1690 sel, chan,
1691 temp_reg, 0);
1692 if (r)
1693 return r;
1694 }
1695
1696 if (reg.Register.File == TGSI_FILE_INPUT) {
1697 name = info->input_semantic_name;
1698 index = info->input_semantic_index;
1699 array_first = info->input_array_first;
1700 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1701 name = info->output_semantic_name;
1702 index = info->output_semantic_index;
1703 array_first = info->output_array_first;
1704 } else {
1705 assert(0);
1706 return -1;
1707 }
1708 if (reg.Register.Indirect) {
1709 int addr_reg;
1710 int first;
1711 /* Add the relative address of the element. */
1712 if (reg.Indirect.ArrayID)
1713 first = array_first[reg.Indirect.ArrayID];
1714 else
1715 first = reg.Register.Index;
1716
1717 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1718
1719 /* pull the value from index_reg */
1720 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1721 temp_reg, 0,
1722 V_SQ_ALU_SRC_LITERAL, 16,
1723 addr_reg, 0,
1724 temp_reg, 0);
1725 if (r)
1726 return r;
1727
1728 param = r600_get_lds_unique_index(name[first],
1729 index[first]);
1730
1731 } else {
1732 param = r600_get_lds_unique_index(name[reg.Register.Index],
1733 index[reg.Register.Index]);
1734 }
1735
1736 /* add to base_addr - passed in temp_reg.x */
1737 if (param) {
1738 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1739 temp_reg, 0,
1740 temp_reg, 0,
1741 V_SQ_ALU_SRC_LITERAL, param * 16);
1742 if (r)
1743 return r;
1744
1745 }
1746 return 0;
1747 }
1748
1749 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1750 unsigned dst_reg, unsigned mask)
1751 {
1752 struct r600_bytecode_alu alu;
1753 int r, i, lasti;
1754
1755 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1756 ctx->bc->force_add_cf = 1;
1757
1758 lasti = tgsi_last_instruction(mask);
1759 for (i = 1; i <= lasti; i++) {
1760 if (!(mask & (1 << i)))
1761 continue;
1762
1763 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1764 temp_reg, i,
1765 temp_reg, 0,
1766 V_SQ_ALU_SRC_LITERAL, 4 * i);
1767 if (r)
1768 return r;
1769 }
1770 for (i = 0; i <= lasti; i++) {
1771 if (!(mask & (1 << i)))
1772 continue;
1773
1774 /* emit an LDS_READ_RET */
1775 memset(&alu, 0, sizeof(alu));
1776 alu.op = LDS_OP1_LDS_READ_RET;
1777 alu.src[0].sel = temp_reg;
1778 alu.src[0].chan = i;
1779 alu.src[1].sel = V_SQ_ALU_SRC_0;
1780 alu.src[2].sel = V_SQ_ALU_SRC_0;
1781 alu.dst.chan = 0;
1782 alu.is_lds_idx_op = true;
1783 alu.last = 1;
1784 r = r600_bytecode_add_alu(ctx->bc, &alu);
1785 if (r)
1786 return r;
1787 }
1788 for (i = 0; i <= lasti; i++) {
1789 if (!(mask & (1 << i)))
1790 continue;
1791
1792 /* then read from LDS_OQ_A_POP */
1793 memset(&alu, 0, sizeof(alu));
1794
1795 alu.op = ALU_OP1_MOV;
1796 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1797 alu.src[0].chan = 0;
1798 alu.dst.sel = dst_reg;
1799 alu.dst.chan = i;
1800 alu.dst.write = 1;
1801 alu.last = 1;
1802 r = r600_bytecode_add_alu(ctx->bc, &alu);
1803 if (r)
1804 return r;
1805 }
1806 return 0;
1807 }
1808
1809 static int fetch_mask(struct tgsi_src_register *reg)
1810 {
1811 int mask = 0;
1812 mask |= 1 << reg->SwizzleX;
1813 mask |= 1 << reg->SwizzleY;
1814 mask |= 1 << reg->SwizzleZ;
1815 mask |= 1 << reg->SwizzleW;
1816 return mask;
1817 }
1818
1819 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1820 {
1821 int r;
1822 unsigned temp_reg = r600_get_temp(ctx);
1823
1824 r = get_lds_offset0(ctx, 2, temp_reg,
1825 src->Register.Dimension ? false : true);
1826 if (r)
1827 return r;
1828
1829 /* the base address is now in temp.x */
1830 r = r600_get_byte_address(ctx, temp_reg,
1831 NULL, src, ctx->tess_output_info, 1);
1832 if (r)
1833 return r;
1834
1835 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1836 if (r)
1837 return r;
1838 return 0;
1839 }
1840
1841 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1842 {
1843 int r;
1844 unsigned temp_reg = r600_get_temp(ctx);
1845
1846 /* t.x = ips * r0.y */
1847 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1848 temp_reg, 0,
1849 ctx->tess_input_info, 0,
1850 0, 1);
1851
1852 if (r)
1853 return r;
1854
1855 /* the base address is now in temp.x */
1856 r = r600_get_byte_address(ctx, temp_reg,
1857 NULL, src, ctx->tess_input_info, 1);
1858 if (r)
1859 return r;
1860
1861 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1862 if (r)
1863 return r;
1864 return 0;
1865 }
1866
1867 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1868 {
1869 int r;
1870 unsigned temp_reg = r600_get_temp(ctx);
1871
1872 r = get_lds_offset0(ctx, 1, temp_reg,
1873 src->Register.Dimension ? false : true);
1874 if (r)
1875 return r;
1876 /* the base address is now in temp.x */
1877 r = r600_get_byte_address(ctx, temp_reg,
1878 NULL, src,
1879 ctx->tess_output_info, 1);
1880 if (r)
1881 return r;
1882
1883 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1884 if (r)
1885 return r;
1886 return 0;
1887 }
1888
1889 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1890 {
1891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1892 unsigned i;
1893
1894 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1895 struct tgsi_full_src_register *src = &inst->Src[i];
1896
1897 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1898 int treg = r600_get_temp(ctx);
1899 fetch_tes_input(ctx, src, treg);
1900 ctx->src[i].sel = treg;
1901 ctx->src[i].rel = 0;
1902 }
1903 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1904 int treg = r600_get_temp(ctx);
1905 fetch_tcs_input(ctx, src, treg);
1906 ctx->src[i].sel = treg;
1907 ctx->src[i].rel = 0;
1908 }
1909 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1910 int treg = r600_get_temp(ctx);
1911 fetch_tcs_output(ctx, src, treg);
1912 ctx->src[i].sel = treg;
1913 ctx->src[i].rel = 0;
1914 }
1915 }
1916 return 0;
1917 }
1918
1919 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1920 {
1921 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1922 struct r600_bytecode_alu alu;
1923 int i, j, k, nconst, r;
1924
1925 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1926 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1927 nconst++;
1928 }
1929 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1930 }
1931 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1932 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1933 continue;
1934 }
1935
1936 if (ctx->src[i].rel) {
1937 int chan = inst->Src[i].Indirect.Swizzle;
1938 int treg = r600_get_temp(ctx);
1939 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1940 return r;
1941
1942 ctx->src[i].kc_bank = 0;
1943 ctx->src[i].kc_rel = 0;
1944 ctx->src[i].sel = treg;
1945 ctx->src[i].rel = 0;
1946 j--;
1947 } else if (j > 0) {
1948 int treg = r600_get_temp(ctx);
1949 for (k = 0; k < 4; k++) {
1950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1951 alu.op = ALU_OP1_MOV;
1952 alu.src[0].sel = ctx->src[i].sel;
1953 alu.src[0].chan = k;
1954 alu.src[0].rel = ctx->src[i].rel;
1955 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1956 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1957 alu.dst.sel = treg;
1958 alu.dst.chan = k;
1959 alu.dst.write = 1;
1960 if (k == 3)
1961 alu.last = 1;
1962 r = r600_bytecode_add_alu(ctx->bc, &alu);
1963 if (r)
1964 return r;
1965 }
1966 ctx->src[i].sel = treg;
1967 ctx->src[i].rel =0;
1968 j--;
1969 }
1970 }
1971 return 0;
1972 }
1973
1974 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1975 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1976 {
1977 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1978 struct r600_bytecode_alu alu;
1979 int i, j, k, nliteral, r;
1980
1981 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1982 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1983 nliteral++;
1984 }
1985 }
1986 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1987 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1988 int treg = r600_get_temp(ctx);
1989 for (k = 0; k < 4; k++) {
1990 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1991 alu.op = ALU_OP1_MOV;
1992 alu.src[0].sel = ctx->src[i].sel;
1993 alu.src[0].chan = k;
1994 alu.src[0].value = ctx->src[i].value[k];
1995 alu.dst.sel = treg;
1996 alu.dst.chan = k;
1997 alu.dst.write = 1;
1998 if (k == 3)
1999 alu.last = 1;
2000 r = r600_bytecode_add_alu(ctx->bc, &alu);
2001 if (r)
2002 return r;
2003 }
2004 ctx->src[i].sel = treg;
2005 j--;
2006 }
2007 }
2008 return 0;
2009 }
2010
2011 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
2012 {
2013 int i, r, count = ctx->shader->ninput;
2014
2015 for (i = 0; i < count; i++) {
2016 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2017 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
2018 if (r)
2019 return r;
2020 }
2021 }
2022 return 0;
2023 }
2024
2025 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2026 int stream, unsigned *stream_item_size UNUSED)
2027 {
2028 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2029 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2030 int j, r;
2031 unsigned i;
2032
2033 /* Sanity checking. */
2034 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2035 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2036 r = -EINVAL;
2037 goto out_err;
2038 }
2039 for (i = 0; i < so->num_outputs; i++) {
2040 if (so->output[i].output_buffer >= 4) {
2041 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2042 so->output[i].output_buffer);
2043 r = -EINVAL;
2044 goto out_err;
2045 }
2046 }
2047
2048 /* Initialize locations where the outputs are stored. */
2049 for (i = 0; i < so->num_outputs; i++) {
2050
2051 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2052 start_comp[i] = so->output[i].start_component;
2053 /* Lower outputs with dst_offset < start_component.
2054 *
2055 * We can only output 4D vectors with a write mask, e.g. we can
2056 * only output the W component at offset 3, etc. If we want
2057 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2058 * to move it to X and output X. */
2059 if (so->output[i].dst_offset < so->output[i].start_component) {
2060 unsigned tmp = r600_get_temp(ctx);
2061
2062 for (j = 0; j < so->output[i].num_components; j++) {
2063 struct r600_bytecode_alu alu;
2064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2065 alu.op = ALU_OP1_MOV;
2066 alu.src[0].sel = so_gpr[i];
2067 alu.src[0].chan = so->output[i].start_component + j;
2068
2069 alu.dst.sel = tmp;
2070 alu.dst.chan = j;
2071 alu.dst.write = 1;
2072 if (j == so->output[i].num_components - 1)
2073 alu.last = 1;
2074 r = r600_bytecode_add_alu(ctx->bc, &alu);
2075 if (r)
2076 return r;
2077 }
2078 start_comp[i] = 0;
2079 so_gpr[i] = tmp;
2080 }
2081 }
2082
2083 /* Write outputs to buffers. */
2084 for (i = 0; i < so->num_outputs; i++) {
2085 struct r600_bytecode_output output;
2086
2087 if (stream != -1 && stream != so->output[i].output_buffer)
2088 continue;
2089
2090 memset(&output, 0, sizeof(struct r600_bytecode_output));
2091 output.gpr = so_gpr[i];
2092 output.elem_size = so->output[i].num_components - 1;
2093 if (output.elem_size == 2)
2094 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2095 output.array_base = so->output[i].dst_offset - start_comp[i];
2096 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2097 output.burst_count = 1;
2098 /* array_size is an upper limit for the burst_count
2099 * with MEM_STREAM instructions */
2100 output.array_size = 0xFFF;
2101 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2102
2103 if (ctx->bc->chip_class >= EVERGREEN) {
2104 switch (so->output[i].output_buffer) {
2105 case 0:
2106 output.op = CF_OP_MEM_STREAM0_BUF0;
2107 break;
2108 case 1:
2109 output.op = CF_OP_MEM_STREAM0_BUF1;
2110 break;
2111 case 2:
2112 output.op = CF_OP_MEM_STREAM0_BUF2;
2113 break;
2114 case 3:
2115 output.op = CF_OP_MEM_STREAM0_BUF3;
2116 break;
2117 }
2118 output.op += so->output[i].stream * 4;
2119 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2120 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2121 } else {
2122 switch (so->output[i].output_buffer) {
2123 case 0:
2124 output.op = CF_OP_MEM_STREAM0;
2125 break;
2126 case 1:
2127 output.op = CF_OP_MEM_STREAM1;
2128 break;
2129 case 2:
2130 output.op = CF_OP_MEM_STREAM2;
2131 break;
2132 case 3:
2133 output.op = CF_OP_MEM_STREAM3;
2134 break;
2135 }
2136 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2137 }
2138 r = r600_bytecode_add_output(ctx->bc, &output);
2139 if (r)
2140 goto out_err;
2141 }
2142 return 0;
2143 out_err:
2144 return r;
2145 }
2146
2147 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2148 {
2149 struct r600_bytecode_alu alu;
2150 unsigned reg;
2151
2152 if (!ctx->shader->vs_out_edgeflag)
2153 return;
2154
2155 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2156
2157 /* clamp(x, 0, 1) */
2158 memset(&alu, 0, sizeof(alu));
2159 alu.op = ALU_OP1_MOV;
2160 alu.src[0].sel = reg;
2161 alu.dst.sel = reg;
2162 alu.dst.write = 1;
2163 alu.dst.clamp = 1;
2164 alu.last = 1;
2165 r600_bytecode_add_alu(ctx->bc, &alu);
2166
2167 memset(&alu, 0, sizeof(alu));
2168 alu.op = ALU_OP1_FLT_TO_INT;
2169 alu.src[0].sel = reg;
2170 alu.dst.sel = reg;
2171 alu.dst.write = 1;
2172 alu.last = 1;
2173 r600_bytecode_add_alu(ctx->bc, &alu);
2174 }
2175
2176 static int generate_gs_copy_shader(struct r600_context *rctx,
2177 struct r600_pipe_shader *gs,
2178 struct pipe_stream_output_info *so)
2179 {
2180 struct r600_shader_ctx ctx = {};
2181 struct r600_shader *gs_shader = &gs->shader;
2182 struct r600_pipe_shader *cshader;
2183 unsigned ocnt = gs_shader->noutput;
2184 struct r600_bytecode_alu alu;
2185 struct r600_bytecode_vtx vtx;
2186 struct r600_bytecode_output output;
2187 struct r600_bytecode_cf *cf_jump, *cf_pop,
2188 *last_exp_pos = NULL, *last_exp_param = NULL;
2189 int next_clip_pos = 61, next_param = 0;
2190 unsigned i, j;
2191 int ring;
2192 bool only_ring_0 = true;
2193 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2194 if (!cshader)
2195 return 0;
2196
2197 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2198 sizeof(struct r600_shader_io));
2199
2200 cshader->shader.noutput = ocnt;
2201
2202 ctx.shader = &cshader->shader;
2203 ctx.bc = &ctx.shader->bc;
2204 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2205
2206 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2207 rctx->screen->has_compressed_msaa_texturing);
2208
2209 ctx.bc->isa = rctx->isa;
2210
2211 cf_jump = NULL;
2212 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2213
2214 /* R0.x = R0.x & 0x3fffffff */
2215 memset(&alu, 0, sizeof(alu));
2216 alu.op = ALU_OP2_AND_INT;
2217 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2218 alu.src[1].value = 0x3fffffff;
2219 alu.dst.write = 1;
2220 r600_bytecode_add_alu(ctx.bc, &alu);
2221
2222 /* R0.y = R0.x >> 30 */
2223 memset(&alu, 0, sizeof(alu));
2224 alu.op = ALU_OP2_LSHR_INT;
2225 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2226 alu.src[1].value = 0x1e;
2227 alu.dst.chan = 1;
2228 alu.dst.write = 1;
2229 alu.last = 1;
2230 r600_bytecode_add_alu(ctx.bc, &alu);
2231
2232 /* fetch vertex data from GSVS ring */
2233 for (i = 0; i < ocnt; ++i) {
2234 struct r600_shader_io *out = &ctx.shader->output[i];
2235
2236 out->gpr = i + 1;
2237 out->ring_offset = i * 16;
2238
2239 memset(&vtx, 0, sizeof(vtx));
2240 vtx.op = FETCH_OP_VFETCH;
2241 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2242 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2243 vtx.mega_fetch_count = 16;
2244 vtx.offset = out->ring_offset;
2245 vtx.dst_gpr = out->gpr;
2246 vtx.src_gpr = 0;
2247 vtx.dst_sel_x = 0;
2248 vtx.dst_sel_y = 1;
2249 vtx.dst_sel_z = 2;
2250 vtx.dst_sel_w = 3;
2251 if (rctx->b.chip_class >= EVERGREEN) {
2252 vtx.use_const_fields = 1;
2253 } else {
2254 vtx.data_format = FMT_32_32_32_32_FLOAT;
2255 }
2256
2257 r600_bytecode_add_vtx(ctx.bc, &vtx);
2258 }
2259 ctx.temp_reg = i + 1;
2260 for (ring = 3; ring >= 0; --ring) {
2261 bool enabled = false;
2262 for (i = 0; i < so->num_outputs; i++) {
2263 if (so->output[i].stream == ring) {
2264 enabled = true;
2265 if (ring > 0)
2266 only_ring_0 = false;
2267 break;
2268 }
2269 }
2270 if (ring != 0 && !enabled) {
2271 cshader->shader.ring_item_sizes[ring] = 0;
2272 continue;
2273 }
2274
2275 if (cf_jump) {
2276 // Patch up jump label
2277 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2278 cf_pop = ctx.bc->cf_last;
2279
2280 cf_jump->cf_addr = cf_pop->id + 2;
2281 cf_jump->pop_count = 1;
2282 cf_pop->cf_addr = cf_pop->id + 2;
2283 cf_pop->pop_count = 1;
2284 }
2285
2286 /* PRED_SETE_INT __, R0.y, ring */
2287 memset(&alu, 0, sizeof(alu));
2288 alu.op = ALU_OP2_PRED_SETE_INT;
2289 alu.src[0].chan = 1;
2290 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2291 alu.src[1].value = ring;
2292 alu.execute_mask = 1;
2293 alu.update_pred = 1;
2294 alu.last = 1;
2295 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2296
2297 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2298 cf_jump = ctx.bc->cf_last;
2299
2300 if (enabled)
2301 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2302 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2303 }
2304
2305 /* bc adds nops - copy it */
2306 if (ctx.bc->chip_class == R600) {
2307 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2308 alu.op = ALU_OP0_NOP;
2309 alu.last = 1;
2310 r600_bytecode_add_alu(ctx.bc, &alu);
2311
2312 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2313 }
2314
2315 /* export vertex data */
2316 /* XXX factor out common code with r600_shader_from_tgsi ? */
2317 for (i = 0; i < ocnt; ++i) {
2318 struct r600_shader_io *out = &ctx.shader->output[i];
2319 bool instream0 = true;
2320 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2321 continue;
2322
2323 for (j = 0; j < so->num_outputs; j++) {
2324 if (so->output[j].register_index == i) {
2325 if (so->output[j].stream == 0)
2326 break;
2327 if (so->output[j].stream > 0)
2328 instream0 = false;
2329 }
2330 }
2331 if (!instream0)
2332 continue;
2333 memset(&output, 0, sizeof(output));
2334 output.gpr = out->gpr;
2335 output.elem_size = 3;
2336 output.swizzle_x = 0;
2337 output.swizzle_y = 1;
2338 output.swizzle_z = 2;
2339 output.swizzle_w = 3;
2340 output.burst_count = 1;
2341 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2342 output.op = CF_OP_EXPORT;
2343 switch (out->name) {
2344 case TGSI_SEMANTIC_POSITION:
2345 output.array_base = 60;
2346 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2347 break;
2348
2349 case TGSI_SEMANTIC_PSIZE:
2350 output.array_base = 61;
2351 if (next_clip_pos == 61)
2352 next_clip_pos = 62;
2353 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2354 output.swizzle_y = 7;
2355 output.swizzle_z = 7;
2356 output.swizzle_w = 7;
2357 ctx.shader->vs_out_misc_write = 1;
2358 ctx.shader->vs_out_point_size = 1;
2359 break;
2360 case TGSI_SEMANTIC_LAYER:
2361 if (out->spi_sid) {
2362 /* duplicate it as PARAM to pass to the pixel shader */
2363 output.array_base = next_param++;
2364 r600_bytecode_add_output(ctx.bc, &output);
2365 last_exp_param = ctx.bc->cf_last;
2366 }
2367 output.array_base = 61;
2368 if (next_clip_pos == 61)
2369 next_clip_pos = 62;
2370 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2371 output.swizzle_x = 7;
2372 output.swizzle_y = 7;
2373 output.swizzle_z = 0;
2374 output.swizzle_w = 7;
2375 ctx.shader->vs_out_misc_write = 1;
2376 ctx.shader->vs_out_layer = 1;
2377 break;
2378 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2379 if (out->spi_sid) {
2380 /* duplicate it as PARAM to pass to the pixel shader */
2381 output.array_base = next_param++;
2382 r600_bytecode_add_output(ctx.bc, &output);
2383 last_exp_param = ctx.bc->cf_last;
2384 }
2385 output.array_base = 61;
2386 if (next_clip_pos == 61)
2387 next_clip_pos = 62;
2388 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2389 ctx.shader->vs_out_misc_write = 1;
2390 ctx.shader->vs_out_viewport = 1;
2391 output.swizzle_x = 7;
2392 output.swizzle_y = 7;
2393 output.swizzle_z = 7;
2394 output.swizzle_w = 0;
2395 break;
2396 case TGSI_SEMANTIC_CLIPDIST:
2397 /* spi_sid is 0 for clipdistance outputs that were generated
2398 * for clipvertex - we don't need to pass them to PS */
2399 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2400 ctx.shader->cull_dist_write = gs->shader.cull_dist_write;
2401 ctx.shader->cc_dist_mask = gs->shader.cc_dist_mask;
2402 if (out->spi_sid) {
2403 /* duplicate it as PARAM to pass to the pixel shader */
2404 output.array_base = next_param++;
2405 r600_bytecode_add_output(ctx.bc, &output);
2406 last_exp_param = ctx.bc->cf_last;
2407 }
2408 output.array_base = next_clip_pos++;
2409 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2410 break;
2411 case TGSI_SEMANTIC_FOG:
2412 output.swizzle_y = 4; /* 0 */
2413 output.swizzle_z = 4; /* 0 */
2414 output.swizzle_w = 5; /* 1 */
2415 break;
2416 default:
2417 output.array_base = next_param++;
2418 break;
2419 }
2420 r600_bytecode_add_output(ctx.bc, &output);
2421 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2422 last_exp_param = ctx.bc->cf_last;
2423 else
2424 last_exp_pos = ctx.bc->cf_last;
2425 }
2426
2427 if (!last_exp_pos) {
2428 memset(&output, 0, sizeof(output));
2429 output.gpr = 0;
2430 output.elem_size = 3;
2431 output.swizzle_x = 7;
2432 output.swizzle_y = 7;
2433 output.swizzle_z = 7;
2434 output.swizzle_w = 7;
2435 output.burst_count = 1;
2436 output.type = 2;
2437 output.op = CF_OP_EXPORT;
2438 output.array_base = 60;
2439 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2440 r600_bytecode_add_output(ctx.bc, &output);
2441 last_exp_pos = ctx.bc->cf_last;
2442 }
2443
2444 if (!last_exp_param) {
2445 memset(&output, 0, sizeof(output));
2446 output.gpr = 0;
2447 output.elem_size = 3;
2448 output.swizzle_x = 7;
2449 output.swizzle_y = 7;
2450 output.swizzle_z = 7;
2451 output.swizzle_w = 7;
2452 output.burst_count = 1;
2453 output.type = 2;
2454 output.op = CF_OP_EXPORT;
2455 output.array_base = next_param++;
2456 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2457 r600_bytecode_add_output(ctx.bc, &output);
2458 last_exp_param = ctx.bc->cf_last;
2459 }
2460
2461 last_exp_pos->op = CF_OP_EXPORT_DONE;
2462 last_exp_param->op = CF_OP_EXPORT_DONE;
2463
2464 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2465 cf_pop = ctx.bc->cf_last;
2466
2467 cf_jump->cf_addr = cf_pop->id + 2;
2468 cf_jump->pop_count = 1;
2469 cf_pop->cf_addr = cf_pop->id + 2;
2470 cf_pop->pop_count = 1;
2471
2472 if (ctx.bc->chip_class == CAYMAN)
2473 cm_bytecode_add_cf_end(ctx.bc);
2474 else {
2475 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2476 ctx.bc->cf_last->end_of_program = 1;
2477 }
2478
2479 gs->gs_copy_shader = cshader;
2480 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2481
2482 ctx.bc->nstack = 1;
2483
2484 return r600_bytecode_build(ctx.bc);
2485 }
2486
2487 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2488 {
2489 if (ind) {
2490 struct r600_bytecode_alu alu;
2491 int r;
2492
2493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2494 alu.op = ALU_OP2_ADD_INT;
2495 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2496 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2497 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2498 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2499 alu.dst.write = 1;
2500 alu.last = 1;
2501 r = r600_bytecode_add_alu(ctx->bc, &alu);
2502 if (r)
2503 return r;
2504 }
2505 return 0;
2506 }
2507
2508 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so UNUSED, int stream, bool ind)
2509 {
2510 struct r600_bytecode_output output;
2511 int ring_offset;
2512 unsigned i, k;
2513 int effective_stream = stream == -1 ? 0 : stream;
2514 int idx = 0;
2515
2516 for (i = 0; i < ctx->shader->noutput; i++) {
2517 if (ctx->gs_for_vs) {
2518 /* for ES we need to lookup corresponding ring offset expected by GS
2519 * (map this output to GS input by name and sid) */
2520 /* FIXME precompute offsets */
2521 ring_offset = -1;
2522 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2523 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2524 struct r600_shader_io *out = &ctx->shader->output[i];
2525 if (in->name == out->name && in->sid == out->sid)
2526 ring_offset = in->ring_offset;
2527 }
2528
2529 if (ring_offset == -1)
2530 continue;
2531 } else {
2532 ring_offset = idx * 16;
2533 idx++;
2534 }
2535
2536 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2537 continue;
2538 /* next_ring_offset after parsing input decls contains total size of
2539 * single vertex data, gs_next_vertex - current vertex index */
2540 if (!ind)
2541 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2542
2543 memset(&output, 0, sizeof(struct r600_bytecode_output));
2544 output.gpr = ctx->shader->output[i].gpr;
2545 output.elem_size = 3;
2546 output.comp_mask = 0xF;
2547 output.burst_count = 1;
2548
2549 if (ind)
2550 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2551 else
2552 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2553
2554 switch (stream) {
2555 default:
2556 case 0:
2557 output.op = CF_OP_MEM_RING; break;
2558 case 1:
2559 output.op = CF_OP_MEM_RING1; break;
2560 case 2:
2561 output.op = CF_OP_MEM_RING2; break;
2562 case 3:
2563 output.op = CF_OP_MEM_RING3; break;
2564 }
2565
2566 if (ind) {
2567 output.array_base = ring_offset >> 2; /* in dwords */
2568 output.array_size = 0xfff;
2569 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2570 } else
2571 output.array_base = ring_offset >> 2; /* in dwords */
2572 r600_bytecode_add_output(ctx->bc, &output);
2573 }
2574
2575 ++ctx->gs_next_vertex;
2576 return 0;
2577 }
2578
2579
2580 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2581 {
2582 int r;
2583 struct r600_bytecode_vtx vtx;
2584 int temp_val = ctx->temp_reg;
2585 /* need to store the TCS output somewhere */
2586 r = single_alu_op2(ctx, ALU_OP1_MOV,
2587 temp_val, 0,
2588 V_SQ_ALU_SRC_LITERAL, 0,
2589 0, 0);
2590 if (r)
2591 return r;
2592
2593 /* used by VS/TCS */
2594 if (ctx->tess_input_info) {
2595 /* fetch tcs input values into resv space */
2596 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2597 vtx.op = FETCH_OP_VFETCH;
2598 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2599 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2600 vtx.mega_fetch_count = 16;
2601 vtx.data_format = FMT_32_32_32_32;
2602 vtx.num_format_all = 2;
2603 vtx.format_comp_all = 1;
2604 vtx.use_const_fields = 0;
2605 vtx.endian = r600_endian_swap(32);
2606 vtx.srf_mode_all = 1;
2607 vtx.offset = 0;
2608 vtx.dst_gpr = ctx->tess_input_info;
2609 vtx.dst_sel_x = 0;
2610 vtx.dst_sel_y = 1;
2611 vtx.dst_sel_z = 2;
2612 vtx.dst_sel_w = 3;
2613 vtx.src_gpr = temp_val;
2614 vtx.src_sel_x = 0;
2615
2616 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2617 if (r)
2618 return r;
2619 }
2620
2621 /* used by TCS/TES */
2622 if (ctx->tess_output_info) {
2623 /* fetch tcs output values into resv space */
2624 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2625 vtx.op = FETCH_OP_VFETCH;
2626 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2627 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2628 vtx.mega_fetch_count = 16;
2629 vtx.data_format = FMT_32_32_32_32;
2630 vtx.num_format_all = 2;
2631 vtx.format_comp_all = 1;
2632 vtx.use_const_fields = 0;
2633 vtx.endian = r600_endian_swap(32);
2634 vtx.srf_mode_all = 1;
2635 vtx.offset = 16;
2636 vtx.dst_gpr = ctx->tess_output_info;
2637 vtx.dst_sel_x = 0;
2638 vtx.dst_sel_y = 1;
2639 vtx.dst_sel_z = 2;
2640 vtx.dst_sel_w = 3;
2641 vtx.src_gpr = temp_val;
2642 vtx.src_sel_x = 0;
2643
2644 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2645 if (r)
2646 return r;
2647 }
2648 return 0;
2649 }
2650
2651 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2652 {
2653 int j, r;
2654 int temp_reg;
2655 unsigned i;
2656
2657 /* fetch tcs input values into input_vals */
2658 ctx->tess_input_info = r600_get_temp(ctx);
2659 ctx->tess_output_info = 0;
2660 r = r600_fetch_tess_io_info(ctx);
2661 if (r)
2662 return r;
2663
2664 temp_reg = r600_get_temp(ctx);
2665 /* dst reg contains LDS address stride * idx */
2666 /* MUL vertexID, vertex_dw_stride */
2667 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2668 temp_reg, 0,
2669 ctx->tess_input_info, 1,
2670 0, 1); /* rel id in r0.y? */
2671 if (r)
2672 return r;
2673
2674 for (i = 0; i < ctx->shader->noutput; i++) {
2675 struct r600_bytecode_alu alu;
2676 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2677
2678 if (param) {
2679 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2680 temp_reg, 1,
2681 temp_reg, 0,
2682 V_SQ_ALU_SRC_LITERAL, param * 16);
2683 if (r)
2684 return r;
2685 }
2686
2687 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2688 temp_reg, 2,
2689 temp_reg, param ? 1 : 0,
2690 V_SQ_ALU_SRC_LITERAL, 8);
2691 if (r)
2692 return r;
2693
2694
2695 for (j = 0; j < 2; j++) {
2696 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2697 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2698 alu.op = LDS_OP3_LDS_WRITE_REL;
2699 alu.src[0].sel = temp_reg;
2700 alu.src[0].chan = chan;
2701 alu.src[1].sel = ctx->shader->output[i].gpr;
2702 alu.src[1].chan = j * 2;
2703 alu.src[2].sel = ctx->shader->output[i].gpr;
2704 alu.src[2].chan = (j * 2) + 1;
2705 alu.last = 1;
2706 alu.dst.chan = 0;
2707 alu.lds_idx = 1;
2708 alu.is_lds_idx_op = true;
2709 r = r600_bytecode_add_alu(ctx->bc, &alu);
2710 if (r)
2711 return r;
2712 }
2713 }
2714 return 0;
2715 }
2716
2717 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2718 {
2719 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2720 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2721 int i, r, lasti;
2722 int temp_reg = r600_get_temp(ctx);
2723 struct r600_bytecode_alu alu;
2724 unsigned write_mask = dst->Register.WriteMask;
2725
2726 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2727 return 0;
2728
2729 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2730 if (r)
2731 return r;
2732
2733 /* the base address is now in temp.x */
2734 r = r600_get_byte_address(ctx, temp_reg,
2735 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2736 if (r)
2737 return r;
2738
2739 /* LDS write */
2740 lasti = tgsi_last_instruction(write_mask);
2741 for (i = 1; i <= lasti; i++) {
2742
2743 if (!(write_mask & (1 << i)))
2744 continue;
2745 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2746 temp_reg, i,
2747 temp_reg, 0,
2748 V_SQ_ALU_SRC_LITERAL, 4 * i);
2749 if (r)
2750 return r;
2751 }
2752
2753 for (i = 0; i <= lasti; i++) {
2754 if (!(write_mask & (1 << i)))
2755 continue;
2756
2757 if ((i == 0 && ((write_mask & 3) == 3)) ||
2758 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2760 alu.op = LDS_OP3_LDS_WRITE_REL;
2761 alu.src[0].sel = temp_reg;
2762 alu.src[0].chan = i;
2763
2764 alu.src[1].sel = dst->Register.Index;
2765 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2766 alu.src[1].chan = i;
2767
2768 alu.src[2].sel = dst->Register.Index;
2769 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2770 alu.src[2].chan = i + 1;
2771 alu.lds_idx = 1;
2772 alu.dst.chan = 0;
2773 alu.last = 1;
2774 alu.is_lds_idx_op = true;
2775 r = r600_bytecode_add_alu(ctx->bc, &alu);
2776 if (r)
2777 return r;
2778 i += 1;
2779 continue;
2780 }
2781 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2782 alu.op = LDS_OP2_LDS_WRITE;
2783 alu.src[0].sel = temp_reg;
2784 alu.src[0].chan = i;
2785
2786 alu.src[1].sel = dst->Register.Index;
2787 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2788 alu.src[1].chan = i;
2789
2790 alu.src[2].sel = V_SQ_ALU_SRC_0;
2791 alu.dst.chan = 0;
2792 alu.last = 1;
2793 alu.is_lds_idx_op = true;
2794 r = r600_bytecode_add_alu(ctx->bc, &alu);
2795 if (r)
2796 return r;
2797 }
2798 return 0;
2799 }
2800
2801 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2802 int output_idx)
2803 {
2804 int param;
2805 unsigned temp_reg = r600_get_temp(ctx);
2806 unsigned name = ctx->shader->output[output_idx].name;
2807 int dreg = ctx->shader->output[output_idx].gpr;
2808 int r;
2809
2810 param = r600_get_lds_unique_index(name, 0);
2811 r = get_lds_offset0(ctx, 1, temp_reg, true);
2812 if (r)
2813 return r;
2814
2815 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2816 temp_reg, 0,
2817 temp_reg, 0,
2818 V_SQ_ALU_SRC_LITERAL, param * 16);
2819 if (r)
2820 return r;
2821
2822 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
2823 return 0;
2824 }
2825
2826 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2827 {
2828 int stride, outer_comps, inner_comps;
2829 int tessinner_idx = -1, tessouter_idx = -1;
2830 int i, r;
2831 unsigned j;
2832 int temp_reg = r600_get_temp(ctx);
2833 int treg[3] = {-1, -1, -1};
2834 struct r600_bytecode_alu alu;
2835 struct r600_bytecode_cf *cf_jump, *cf_pop;
2836
2837 /* only execute factor emission for invocation 0 */
2838 /* PRED_SETE_INT __, R0.x, 0 */
2839 memset(&alu, 0, sizeof(alu));
2840 alu.op = ALU_OP2_PRED_SETE_INT;
2841 alu.src[0].chan = 2;
2842 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2843 alu.execute_mask = 1;
2844 alu.update_pred = 1;
2845 alu.last = 1;
2846 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2847
2848 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2849 cf_jump = ctx->bc->cf_last;
2850
2851 treg[0] = r600_get_temp(ctx);
2852 switch (ctx->shader->tcs_prim_mode) {
2853 case PIPE_PRIM_LINES:
2854 stride = 8; /* 2 dwords, 1 vec2 store */
2855 outer_comps = 2;
2856 inner_comps = 0;
2857 break;
2858 case PIPE_PRIM_TRIANGLES:
2859 stride = 16; /* 4 dwords, 1 vec4 store */
2860 outer_comps = 3;
2861 inner_comps = 1;
2862 treg[1] = r600_get_temp(ctx);
2863 break;
2864 case PIPE_PRIM_QUADS:
2865 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2866 outer_comps = 4;
2867 inner_comps = 2;
2868 treg[1] = r600_get_temp(ctx);
2869 treg[2] = r600_get_temp(ctx);
2870 break;
2871 default:
2872 assert(0);
2873 return -1;
2874 }
2875
2876 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2877 /* TF_WRITE takes index in R.x, value in R.y */
2878 for (j = 0; j < ctx->shader->noutput; j++) {
2879 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSINNER)
2880 tessinner_idx = j;
2881 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSOUTER)
2882 tessouter_idx = j;
2883 }
2884
2885 if (tessouter_idx == -1)
2886 return -1;
2887
2888 if (tessinner_idx == -1 && inner_comps)
2889 return -1;
2890
2891 if (tessouter_idx != -1) {
2892 r = r600_tess_factor_read(ctx, tessouter_idx);
2893 if (r)
2894 return r;
2895 }
2896
2897 if (tessinner_idx != -1) {
2898 r = r600_tess_factor_read(ctx, tessinner_idx);
2899 if (r)
2900 return r;
2901 }
2902
2903 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2904 /* r.x = relpatchid(r0.y) * tf_stride */
2905
2906 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2907 /* add incoming r0.w to it: t.x = t.x + r0.w */
2908 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2909 temp_reg, 0,
2910 0, 1,
2911 V_SQ_ALU_SRC_LITERAL, stride,
2912 0, 3);
2913 if (r)
2914 return r;
2915
2916 for (i = 0; i < outer_comps + inner_comps; i++) {
2917 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2918 int out_comp = i >= outer_comps ? i - outer_comps : i;
2919
2920 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2921 if (out_comp == 1)
2922 out_comp = 0;
2923 else if (out_comp == 0)
2924 out_comp = 1;
2925 }
2926
2927 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2928 treg[i / 2], (2 * (i % 2)),
2929 temp_reg, 0,
2930 V_SQ_ALU_SRC_LITERAL, 4 * i);
2931 if (r)
2932 return r;
2933 r = single_alu_op2(ctx, ALU_OP1_MOV,
2934 treg[i / 2], 1 + (2 * (i%2)),
2935 ctx->shader->output[out_idx].gpr, out_comp,
2936 0, 0);
2937 if (r)
2938 return r;
2939 }
2940 for (i = 0; i < outer_comps + inner_comps; i++) {
2941 struct r600_bytecode_gds gds;
2942
2943 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2944 gds.src_gpr = treg[i / 2];
2945 gds.src_sel_x = 2 * (i % 2);
2946 gds.src_sel_y = 1 + (2 * (i % 2));
2947 gds.src_sel_z = 4;
2948 gds.dst_sel_x = 7;
2949 gds.dst_sel_y = 7;
2950 gds.dst_sel_z = 7;
2951 gds.dst_sel_w = 7;
2952 gds.op = FETCH_OP_TF_WRITE;
2953 r = r600_bytecode_add_gds(ctx->bc, &gds);
2954 if (r)
2955 return r;
2956 }
2957
2958 // Patch up jump label
2959 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2960 cf_pop = ctx->bc->cf_last;
2961
2962 cf_jump->cf_addr = cf_pop->id + 2;
2963 cf_jump->pop_count = 1;
2964 cf_pop->cf_addr = cf_pop->id + 2;
2965 cf_pop->pop_count = 1;
2966
2967 return 0;
2968 }
2969
2970 /*
2971 * We have to work out the thread ID for load and atomic
2972 * operations, which store the returned value to an index
2973 * in an intermediate buffer.
2974 * The index is calculated by taking the thread id,
2975 * calculated from the MBCNT instructions.
2976 * Then the shader engine ID is multiplied by 256,
2977 * and the wave id is added.
2978 * Then the result is multipled by 64 and thread id is
2979 * added.
2980 */
2981 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
2982 {
2983 struct r600_bytecode_alu alu;
2984 int r;
2985
2986 if (ctx->thread_id_gpr_loaded)
2987 return 0;
2988
2989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2990 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
2991 alu.dst.sel = ctx->temp_reg;
2992 alu.dst.chan = 0;
2993 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2994 alu.src[0].value = 0xffffffff;
2995 alu.dst.write = 1;
2996 r = r600_bytecode_add_alu(ctx->bc, &alu);
2997 if (r)
2998 return r;
2999
3000 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3001 alu.op = ALU_OP1_MBCNT_32HI_INT;
3002 alu.dst.sel = ctx->temp_reg;
3003 alu.dst.chan = 1;
3004 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3005 alu.src[0].value = 0xffffffff;
3006 alu.dst.write = 1;
3007 r = r600_bytecode_add_alu(ctx->bc, &alu);
3008 if (r)
3009 return r;
3010
3011 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3012 alu.op = ALU_OP3_MULADD_UINT24;
3013 alu.dst.sel = ctx->temp_reg;
3014 alu.dst.chan = 2;
3015 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
3016 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3017 alu.src[1].value = 256;
3018 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
3019 alu.dst.write = 1;
3020 alu.is_op3 = 1;
3021 alu.last = 1;
3022 r = r600_bytecode_add_alu(ctx->bc, &alu);
3023 if (r)
3024 return r;
3025
3026 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3027 ctx->thread_id_gpr, 1,
3028 ctx->temp_reg, 2,
3029 V_SQ_ALU_SRC_LITERAL, 0x40,
3030 ctx->temp_reg, 0);
3031 if (r)
3032 return r;
3033 ctx->thread_id_gpr_loaded = true;
3034 return 0;
3035 }
3036
3037 static int r600_shader_from_tgsi(struct r600_context *rctx,
3038 struct r600_pipe_shader *pipeshader,
3039 union r600_shader_key key)
3040 {
3041 struct r600_screen *rscreen = rctx->screen;
3042 struct r600_shader *shader = &pipeshader->shader;
3043 struct tgsi_token *tokens = pipeshader->selector->tokens;
3044 struct pipe_stream_output_info so = pipeshader->selector->so;
3045 struct tgsi_full_immediate *immediate;
3046 struct r600_shader_ctx ctx;
3047 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3048 unsigned output_done, noutput;
3049 unsigned opcode;
3050 int j, k, r = 0;
3051 unsigned i;
3052 int next_param_base = 0, next_clip_base;
3053 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3054 bool indirect_gprs;
3055 bool ring_outputs = false;
3056 bool lds_outputs = false;
3057 bool lds_inputs = false;
3058 bool pos_emitted = false;
3059
3060 ctx.bc = &shader->bc;
3061 ctx.shader = shader;
3062 ctx.native_integers = true;
3063
3064 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3065 rscreen->has_compressed_msaa_texturing);
3066 ctx.tokens = tokens;
3067 tgsi_scan_shader(tokens, &ctx.info);
3068 shader->indirect_files = ctx.info.indirect_files;
3069
3070 shader->uses_doubles = ctx.info.uses_doubles;
3071 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3072 shader->nsys_inputs = 0;
3073
3074 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0 ||
3075 ctx.info.file_count[TGSI_FILE_BUFFER] > 0;
3076 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3077 tgsi_parse_init(&ctx.parse, tokens);
3078 ctx.type = ctx.info.processor;
3079 shader->processor_type = ctx.type;
3080 ctx.bc->type = shader->processor_type;
3081
3082 switch (ctx.type) {
3083 case PIPE_SHADER_VERTEX:
3084 shader->vs_as_gs_a = key.vs.as_gs_a;
3085 shader->vs_as_es = key.vs.as_es;
3086 shader->vs_as_ls = key.vs.as_ls;
3087 shader->atomic_base = key.vs.first_atomic_counter;
3088 if (shader->vs_as_es)
3089 ring_outputs = true;
3090 if (shader->vs_as_ls)
3091 lds_outputs = true;
3092 break;
3093 case PIPE_SHADER_GEOMETRY:
3094 ring_outputs = true;
3095 shader->atomic_base = key.gs.first_atomic_counter;
3096 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3097 break;
3098 case PIPE_SHADER_TESS_CTRL:
3099 shader->tcs_prim_mode = key.tcs.prim_mode;
3100 shader->atomic_base = key.tcs.first_atomic_counter;
3101 lds_outputs = true;
3102 lds_inputs = true;
3103 break;
3104 case PIPE_SHADER_TESS_EVAL:
3105 shader->tes_as_es = key.tes.as_es;
3106 shader->atomic_base = key.tes.first_atomic_counter;
3107 lds_inputs = true;
3108 if (shader->tes_as_es)
3109 ring_outputs = true;
3110 break;
3111 case PIPE_SHADER_FRAGMENT:
3112 shader->two_side = key.ps.color_two_side;
3113 shader->atomic_base = key.ps.first_atomic_counter;
3114 shader->rat_base = key.ps.nr_cbufs;
3115 shader->image_size_const_offset = key.ps.image_size_const_offset;
3116 break;
3117 default:
3118 break;
3119 }
3120
3121 if (shader->vs_as_es || shader->tes_as_es) {
3122 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3123 } else {
3124 ctx.gs_for_vs = NULL;
3125 }
3126
3127 ctx.next_ring_offset = 0;
3128 ctx.gs_out_ring_offset = 0;
3129 ctx.gs_next_vertex = 0;
3130 ctx.gs_stream_output_info = &so;
3131
3132 ctx.face_gpr = -1;
3133 ctx.fixed_pt_position_gpr = -1;
3134 ctx.fragcoord_input = -1;
3135 ctx.colors_used = 0;
3136 ctx.clip_vertex_write = 0;
3137 ctx.thread_id_gpr_loaded = false;
3138
3139 shader->nr_ps_color_exports = 0;
3140 shader->nr_ps_max_color_exports = 0;
3141
3142
3143 /* register allocations */
3144 /* Values [0,127] correspond to GPR[0..127].
3145 * Values [128,159] correspond to constant buffer bank 0
3146 * Values [160,191] correspond to constant buffer bank 1
3147 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3148 * Values [256,287] correspond to constant buffer bank 2 (EG)
3149 * Values [288,319] correspond to constant buffer bank 3 (EG)
3150 * Other special values are shown in the list below.
3151 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3152 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3153 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3154 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3155 * 248 SQ_ALU_SRC_0: special constant 0.0.
3156 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3157 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3158 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3159 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3160 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3161 * 254 SQ_ALU_SRC_PV: previous vector result.
3162 * 255 SQ_ALU_SRC_PS: previous scalar result.
3163 */
3164 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3165 ctx.file_offset[i] = 0;
3166 }
3167
3168 if (ctx.type == PIPE_SHADER_VERTEX) {
3169
3170 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3171 if (ctx.info.num_inputs)
3172 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3173 }
3174 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3175 if (ctx.bc->chip_class >= EVERGREEN)
3176 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3177 else
3178 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3179 }
3180 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3181 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3182 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3183 }
3184 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3185 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3186 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3187 bool add_tesscoord = false, add_tess_inout = false;
3188 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3189 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3190 /* if we have tesscoord save one reg */
3191 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3192 add_tesscoord = true;
3193 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3194 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3195 add_tess_inout = true;
3196 }
3197 if (add_tesscoord || add_tess_inout)
3198 ctx.file_offset[TGSI_FILE_INPUT]++;
3199 if (add_tess_inout)
3200 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3201 }
3202
3203 ctx.file_offset[TGSI_FILE_OUTPUT] =
3204 ctx.file_offset[TGSI_FILE_INPUT] +
3205 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3206 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3207 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3208
3209 /* Outside the GPR range. This will be translated to one of the
3210 * kcache banks later. */
3211 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3212
3213 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3214 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3215 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3216 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3217 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3218
3219 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3220 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3221 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3222 ctx.temp_reg = ctx.bc->ar_reg + 5;
3223 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3224 ctx.tess_input_info = 0;
3225 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3226 ctx.temp_reg = ctx.bc->ar_reg + 4;
3227 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3228 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3229 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3230 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3231 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3232 ctx.temp_reg = ctx.bc->ar_reg + 7;
3233 if (ctx.shader->gs_tri_strip_adj_fix) {
3234 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3235 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3236 ctx.temp_reg += 2;
3237 } else {
3238 ctx.gs_rotated_input[0] = 0;
3239 ctx.gs_rotated_input[1] = 1;
3240 }
3241 } else {
3242 ctx.temp_reg = ctx.bc->ar_reg + 3;
3243 }
3244
3245 if (shader->uses_images) {
3246 ctx.thread_id_gpr = ctx.temp_reg++;
3247 ctx.thread_id_gpr_loaded = false;
3248 }
3249
3250 shader->max_arrays = 0;
3251 shader->num_arrays = 0;
3252 if (indirect_gprs) {
3253
3254 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3255 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3256 ctx.file_offset[TGSI_FILE_OUTPUT] -
3257 ctx.file_offset[TGSI_FILE_INPUT],
3258 0x0F);
3259 }
3260 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3261 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3262 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3263 ctx.file_offset[TGSI_FILE_OUTPUT],
3264 0x0F);
3265 }
3266 }
3267
3268 ctx.nliterals = 0;
3269 ctx.literals = NULL;
3270
3271 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3272 ctx.info.colors_written == 1;
3273 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3274 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3275
3276 if (ctx.type == PIPE_SHADER_VERTEX ||
3277 ctx.type == PIPE_SHADER_GEOMETRY ||
3278 ctx.type == PIPE_SHADER_TESS_EVAL) {
3279 shader->cc_dist_mask = (1 << (ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED] +
3280 ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED])) - 1;
3281 shader->clip_dist_write = (1 << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED]) - 1;
3282 shader->cull_dist_write = ((1 << ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED]) - 1) << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED];
3283 }
3284
3285 if (shader->vs_as_gs_a)
3286 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3287
3288 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3289 r600_fetch_tess_io_info(&ctx);
3290
3291 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3292 tgsi_parse_token(&ctx.parse);
3293 switch (ctx.parse.FullToken.Token.Type) {
3294 case TGSI_TOKEN_TYPE_IMMEDIATE:
3295 immediate = &ctx.parse.FullToken.FullImmediate;
3296 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3297 if(ctx.literals == NULL) {
3298 r = -ENOMEM;
3299 goto out_err;
3300 }
3301 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3302 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3303 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3304 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3305 ctx.nliterals++;
3306 break;
3307 case TGSI_TOKEN_TYPE_DECLARATION:
3308 r = tgsi_declaration(&ctx);
3309 if (r)
3310 goto out_err;
3311 break;
3312 case TGSI_TOKEN_TYPE_INSTRUCTION:
3313 case TGSI_TOKEN_TYPE_PROPERTY:
3314 break;
3315 default:
3316 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3317 r = -EINVAL;
3318 goto out_err;
3319 }
3320 }
3321
3322 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3323 shader->ring_item_sizes[1] = 0;
3324 shader->ring_item_sizes[2] = 0;
3325 shader->ring_item_sizes[3] = 0;
3326
3327 /* Process two side if needed */
3328 if (shader->two_side && ctx.colors_used) {
3329 int i, count = ctx.shader->ninput;
3330 unsigned next_lds_loc = ctx.shader->nlds;
3331
3332 /* additional inputs will be allocated right after the existing inputs,
3333 * we won't need them after the color selection, so we don't need to
3334 * reserve these gprs for the rest of the shader code and to adjust
3335 * output offsets etc. */
3336 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3337 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3338
3339 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3340 if (ctx.face_gpr == -1) {
3341 i = ctx.shader->ninput++;
3342 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3343 ctx.shader->input[i].spi_sid = 0;
3344 ctx.shader->input[i].gpr = gpr++;
3345 ctx.face_gpr = ctx.shader->input[i].gpr;
3346 }
3347
3348 for (i = 0; i < count; i++) {
3349 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3350 int ni = ctx.shader->ninput++;
3351 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3352 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3353 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3354 ctx.shader->input[ni].gpr = gpr++;
3355 // TGSI to LLVM needs to know the lds position of inputs.
3356 // Non LLVM path computes it later (in process_twoside_color)
3357 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3358 ctx.shader->input[i].back_color_input = ni;
3359 if (ctx.bc->chip_class >= EVERGREEN) {
3360 if ((r = evergreen_interp_input(&ctx, ni)))
3361 return r;
3362 }
3363 }
3364 }
3365 }
3366
3367 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3368 shader->nr_ps_max_color_exports = 8;
3369
3370 if (ctx.fragcoord_input >= 0) {
3371 if (ctx.bc->chip_class == CAYMAN) {
3372 for (j = 0 ; j < 4; j++) {
3373 struct r600_bytecode_alu alu;
3374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3375 alu.op = ALU_OP1_RECIP_IEEE;
3376 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3377 alu.src[0].chan = 3;
3378
3379 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3380 alu.dst.chan = j;
3381 alu.dst.write = (j == 3);
3382 alu.last = 1;
3383 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3384 return r;
3385 }
3386 } else {
3387 struct r600_bytecode_alu alu;
3388 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3389 alu.op = ALU_OP1_RECIP_IEEE;
3390 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3391 alu.src[0].chan = 3;
3392
3393 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3394 alu.dst.chan = 3;
3395 alu.dst.write = 1;
3396 alu.last = 1;
3397 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3398 return r;
3399 }
3400 }
3401
3402 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3403 struct r600_bytecode_alu alu;
3404 int r;
3405
3406 /* GS thread with no output workaround - emit a cut at start of GS */
3407 if (ctx.bc->chip_class == R600)
3408 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3409
3410 for (j = 0; j < 4; j++) {
3411 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3412 alu.op = ALU_OP1_MOV;
3413 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3414 alu.src[0].value = 0;
3415 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3416 alu.dst.write = 1;
3417 alu.last = 1;
3418 r = r600_bytecode_add_alu(ctx.bc, &alu);
3419 if (r)
3420 return r;
3421 }
3422
3423 if (ctx.shader->gs_tri_strip_adj_fix) {
3424 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3425 ctx.gs_rotated_input[0], 2,
3426 0, 2,
3427 V_SQ_ALU_SRC_LITERAL, 1);
3428 if (r)
3429 return r;
3430
3431 for (i = 0; i < 6; i++) {
3432 int rotated = (i + 4) % 6;
3433 int offset_reg = i / 3;
3434 int offset_chan = i % 3;
3435 int rotated_offset_reg = rotated / 3;
3436 int rotated_offset_chan = rotated % 3;
3437
3438 if (offset_reg == 0 && offset_chan == 2)
3439 offset_chan = 3;
3440 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3441 rotated_offset_chan = 3;
3442
3443 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3444 ctx.gs_rotated_input[offset_reg], offset_chan,
3445 ctx.gs_rotated_input[0], 2,
3446 offset_reg, offset_chan,
3447 rotated_offset_reg, rotated_offset_chan);
3448 if (r)
3449 return r;
3450 }
3451 }
3452 }
3453
3454 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3455 r600_fetch_tess_io_info(&ctx);
3456
3457 if (shader->two_side && ctx.colors_used) {
3458 if ((r = process_twoside_color_inputs(&ctx)))
3459 return r;
3460 }
3461
3462 tgsi_parse_init(&ctx.parse, tokens);
3463 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3464 tgsi_parse_token(&ctx.parse);
3465 switch (ctx.parse.FullToken.Token.Type) {
3466 case TGSI_TOKEN_TYPE_INSTRUCTION:
3467 r = tgsi_is_supported(&ctx);
3468 if (r)
3469 goto out_err;
3470 ctx.max_driver_temp_used = 0;
3471 /* reserve first tmp for everyone */
3472 r600_get_temp(&ctx);
3473
3474 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3475 if ((r = tgsi_split_constant(&ctx)))
3476 goto out_err;
3477 if ((r = tgsi_split_literal_constant(&ctx)))
3478 goto out_err;
3479 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3480 if ((r = tgsi_split_gs_inputs(&ctx)))
3481 goto out_err;
3482 } else if (lds_inputs) {
3483 if ((r = tgsi_split_lds_inputs(&ctx)))
3484 goto out_err;
3485 }
3486 if (ctx.bc->chip_class == CAYMAN)
3487 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3488 else if (ctx.bc->chip_class >= EVERGREEN)
3489 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3490 else
3491 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3492 r = ctx.inst_info->process(&ctx);
3493 if (r)
3494 goto out_err;
3495
3496 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3497 r = r600_store_tcs_output(&ctx);
3498 if (r)
3499 goto out_err;
3500 }
3501 break;
3502 default:
3503 break;
3504 }
3505 }
3506
3507 /* Reset the temporary register counter. */
3508 ctx.max_driver_temp_used = 0;
3509
3510 noutput = shader->noutput;
3511
3512 if (!ring_outputs && ctx.clip_vertex_write) {
3513 unsigned clipdist_temp[2];
3514
3515 clipdist_temp[0] = r600_get_temp(&ctx);
3516 clipdist_temp[1] = r600_get_temp(&ctx);
3517
3518 /* need to convert a clipvertex write into clipdistance writes and not export
3519 the clip vertex anymore */
3520
3521 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3522 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3523 shader->output[noutput].gpr = clipdist_temp[0];
3524 noutput++;
3525 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3526 shader->output[noutput].gpr = clipdist_temp[1];
3527 noutput++;
3528
3529 /* reset spi_sid for clipvertex output to avoid confusing spi */
3530 shader->output[ctx.cv_output].spi_sid = 0;
3531
3532 shader->clip_dist_write = 0xFF;
3533 shader->cc_dist_mask = 0xFF;
3534
3535 for (i = 0; i < 8; i++) {
3536 int oreg = i >> 2;
3537 int ochan = i & 3;
3538
3539 for (j = 0; j < 4; j++) {
3540 struct r600_bytecode_alu alu;
3541 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3542 alu.op = ALU_OP2_DOT4;
3543 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3544 alu.src[0].chan = j;
3545
3546 alu.src[1].sel = 512 + i;
3547 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3548 alu.src[1].chan = j;
3549
3550 alu.dst.sel = clipdist_temp[oreg];
3551 alu.dst.chan = j;
3552 alu.dst.write = (j == ochan);
3553 if (j == 3)
3554 alu.last = 1;
3555 r = r600_bytecode_add_alu(ctx.bc, &alu);
3556 if (r)
3557 return r;
3558 }
3559 }
3560 }
3561
3562 /* Add stream outputs. */
3563 if (so.num_outputs) {
3564 bool emit = false;
3565 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3566 emit = true;
3567 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3568 emit = true;
3569 if (emit)
3570 emit_streamout(&ctx, &so, -1, NULL);
3571 }
3572 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3573 convert_edgeflag_to_int(&ctx);
3574
3575 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3576 r600_emit_tess_factor(&ctx);
3577
3578 if (lds_outputs) {
3579 if (ctx.type == PIPE_SHADER_VERTEX) {
3580 if (ctx.shader->noutput)
3581 emit_lds_vs_writes(&ctx);
3582 }
3583 } else if (ring_outputs) {
3584 if (shader->vs_as_es || shader->tes_as_es) {
3585 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3586 ctx.gs_export_gpr_tregs[1] = -1;
3587 ctx.gs_export_gpr_tregs[2] = -1;
3588 ctx.gs_export_gpr_tregs[3] = -1;
3589
3590 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3591 }
3592 } else {
3593 /* Export output */
3594 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3595
3596 for (i = 0, j = 0; i < noutput; i++, j++) {
3597 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3598 output[j].gpr = shader->output[i].gpr;
3599 output[j].elem_size = 3;
3600 output[j].swizzle_x = 0;
3601 output[j].swizzle_y = 1;
3602 output[j].swizzle_z = 2;
3603 output[j].swizzle_w = 3;
3604 output[j].burst_count = 1;
3605 output[j].type = 0xffffffff;
3606 output[j].op = CF_OP_EXPORT;
3607 switch (ctx.type) {
3608 case PIPE_SHADER_VERTEX:
3609 case PIPE_SHADER_TESS_EVAL:
3610 switch (shader->output[i].name) {
3611 case TGSI_SEMANTIC_POSITION:
3612 output[j].array_base = 60;
3613 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3614 pos_emitted = true;
3615 break;
3616
3617 case TGSI_SEMANTIC_PSIZE:
3618 output[j].array_base = 61;
3619 output[j].swizzle_y = 7;
3620 output[j].swizzle_z = 7;
3621 output[j].swizzle_w = 7;
3622 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3623 pos_emitted = true;
3624 break;
3625 case TGSI_SEMANTIC_EDGEFLAG:
3626 output[j].array_base = 61;
3627 output[j].swizzle_x = 7;
3628 output[j].swizzle_y = 0;
3629 output[j].swizzle_z = 7;
3630 output[j].swizzle_w = 7;
3631 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3632 pos_emitted = true;
3633 break;
3634 case TGSI_SEMANTIC_LAYER:
3635 /* spi_sid is 0 for outputs that are
3636 * not consumed by PS */
3637 if (shader->output[i].spi_sid) {
3638 output[j].array_base = next_param_base++;
3639 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3640 j++;
3641 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3642 }
3643 output[j].array_base = 61;
3644 output[j].swizzle_x = 7;
3645 output[j].swizzle_y = 7;
3646 output[j].swizzle_z = 0;
3647 output[j].swizzle_w = 7;
3648 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3649 pos_emitted = true;
3650 break;
3651 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3652 /* spi_sid is 0 for outputs that are
3653 * not consumed by PS */
3654 if (shader->output[i].spi_sid) {
3655 output[j].array_base = next_param_base++;
3656 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3657 j++;
3658 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3659 }
3660 output[j].array_base = 61;
3661 output[j].swizzle_x = 7;
3662 output[j].swizzle_y = 7;
3663 output[j].swizzle_z = 7;
3664 output[j].swizzle_w = 0;
3665 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3666 pos_emitted = true;
3667 break;
3668 case TGSI_SEMANTIC_CLIPVERTEX:
3669 j--;
3670 break;
3671 case TGSI_SEMANTIC_CLIPDIST:
3672 output[j].array_base = next_clip_base++;
3673 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3674 pos_emitted = true;
3675 /* spi_sid is 0 for clipdistance outputs that were generated
3676 * for clipvertex - we don't need to pass them to PS */
3677 if (shader->output[i].spi_sid) {
3678 j++;
3679 /* duplicate it as PARAM to pass to the pixel shader */
3680 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3681 output[j].array_base = next_param_base++;
3682 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3683 }
3684 break;
3685 case TGSI_SEMANTIC_FOG:
3686 output[j].swizzle_y = 4; /* 0 */
3687 output[j].swizzle_z = 4; /* 0 */
3688 output[j].swizzle_w = 5; /* 1 */
3689 break;
3690 case TGSI_SEMANTIC_PRIMID:
3691 output[j].swizzle_x = 2;
3692 output[j].swizzle_y = 4; /* 0 */
3693 output[j].swizzle_z = 4; /* 0 */
3694 output[j].swizzle_w = 4; /* 0 */
3695 break;
3696 }
3697
3698 break;
3699 case PIPE_SHADER_FRAGMENT:
3700 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3701 /* never export more colors than the number of CBs */
3702 if (shader->output[i].sid >= max_color_exports) {
3703 /* skip export */
3704 j--;
3705 continue;
3706 }
3707 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3708 output[j].array_base = shader->output[i].sid;
3709 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3710 shader->nr_ps_color_exports++;
3711 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3712 for (k = 1; k < max_color_exports; k++) {
3713 j++;
3714 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3715 output[j].gpr = shader->output[i].gpr;
3716 output[j].elem_size = 3;
3717 output[j].swizzle_x = 0;
3718 output[j].swizzle_y = 1;
3719 output[j].swizzle_z = 2;
3720 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3721 output[j].burst_count = 1;
3722 output[j].array_base = k;
3723 output[j].op = CF_OP_EXPORT;
3724 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3725 shader->nr_ps_color_exports++;
3726 }
3727 }
3728 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3729 output[j].array_base = 61;
3730 output[j].swizzle_x = 2;
3731 output[j].swizzle_y = 7;
3732 output[j].swizzle_z = output[j].swizzle_w = 7;
3733 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3734 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3735 output[j].array_base = 61;
3736 output[j].swizzle_x = 7;
3737 output[j].swizzle_y = 1;
3738 output[j].swizzle_z = output[j].swizzle_w = 7;
3739 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3740 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3741 output[j].array_base = 61;
3742 output[j].swizzle_x = 7;
3743 output[j].swizzle_y = 7;
3744 output[j].swizzle_z = 0;
3745 output[j].swizzle_w = 7;
3746 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3747 } else {
3748 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3749 r = -EINVAL;
3750 goto out_err;
3751 }
3752 break;
3753 case PIPE_SHADER_TESS_CTRL:
3754 break;
3755 default:
3756 R600_ERR("unsupported processor type %d\n", ctx.type);
3757 r = -EINVAL;
3758 goto out_err;
3759 }
3760
3761 if (output[j].type == 0xffffffff) {
3762 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3763 output[j].array_base = next_param_base++;
3764 }
3765 }
3766
3767 /* add fake position export */
3768 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3769 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3770 output[j].gpr = 0;
3771 output[j].elem_size = 3;
3772 output[j].swizzle_x = 7;
3773 output[j].swizzle_y = 7;
3774 output[j].swizzle_z = 7;
3775 output[j].swizzle_w = 7;
3776 output[j].burst_count = 1;
3777 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3778 output[j].array_base = 60;
3779 output[j].op = CF_OP_EXPORT;
3780 j++;
3781 }
3782
3783 /* add fake param output for vertex shader if no param is exported */
3784 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3785 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3786 output[j].gpr = 0;
3787 output[j].elem_size = 3;
3788 output[j].swizzle_x = 7;
3789 output[j].swizzle_y = 7;
3790 output[j].swizzle_z = 7;
3791 output[j].swizzle_w = 7;
3792 output[j].burst_count = 1;
3793 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3794 output[j].array_base = 0;
3795 output[j].op = CF_OP_EXPORT;
3796 j++;
3797 }
3798
3799 /* add fake pixel export */
3800 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3801 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3802 output[j].gpr = 0;
3803 output[j].elem_size = 3;
3804 output[j].swizzle_x = 7;
3805 output[j].swizzle_y = 7;
3806 output[j].swizzle_z = 7;
3807 output[j].swizzle_w = 7;
3808 output[j].burst_count = 1;
3809 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3810 output[j].array_base = 0;
3811 output[j].op = CF_OP_EXPORT;
3812 j++;
3813 shader->nr_ps_color_exports++;
3814 }
3815
3816 noutput = j;
3817
3818 /* set export done on last export of each type */
3819 for (k = noutput - 1, output_done = 0; k >= 0; k--) {
3820 if (!(output_done & (1 << output[k].type))) {
3821 output_done |= (1 << output[k].type);
3822 output[k].op = CF_OP_EXPORT_DONE;
3823 }
3824 }
3825 /* add output to bytecode */
3826 for (i = 0; i < noutput; i++) {
3827 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3828 if (r)
3829 goto out_err;
3830 }
3831 }
3832
3833 /* add program end */
3834 if (ctx.bc->chip_class == CAYMAN)
3835 cm_bytecode_add_cf_end(ctx.bc);
3836 else {
3837 const struct cf_op_info *last = NULL;
3838
3839 if (ctx.bc->cf_last)
3840 last = r600_isa_cf(ctx.bc->cf_last->op);
3841
3842 /* alu clause instructions don't have EOP bit, so add NOP */
3843 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_POP)
3844 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3845
3846 ctx.bc->cf_last->end_of_program = 1;
3847 }
3848
3849 /* check GPR limit - we have 124 = 128 - 4
3850 * (4 are reserved as alu clause temporary registers) */
3851 if (ctx.bc->ngpr > 124) {
3852 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3853 r = -ENOMEM;
3854 goto out_err;
3855 }
3856
3857 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3858 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3859 return r;
3860 }
3861
3862 free(ctx.literals);
3863 tgsi_parse_free(&ctx.parse);
3864 return 0;
3865 out_err:
3866 free(ctx.literals);
3867 tgsi_parse_free(&ctx.parse);
3868 return r;
3869 }
3870
3871 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3872 {
3873 const unsigned tgsi_opcode =
3874 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3875 R600_ERR("%s tgsi opcode unsupported\n",
3876 tgsi_get_opcode_name(tgsi_opcode));
3877 return -EINVAL;
3878 }
3879
3880 static int tgsi_end(struct r600_shader_ctx *ctx UNUSED)
3881 {
3882 return 0;
3883 }
3884
3885 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3886 const struct r600_shader_src *shader_src,
3887 unsigned chan)
3888 {
3889 bc_src->sel = shader_src->sel;
3890 bc_src->chan = shader_src->swizzle[chan];
3891 bc_src->neg = shader_src->neg;
3892 bc_src->abs = shader_src->abs;
3893 bc_src->rel = shader_src->rel;
3894 bc_src->value = shader_src->value[bc_src->chan];
3895 bc_src->kc_bank = shader_src->kc_bank;
3896 bc_src->kc_rel = shader_src->kc_rel;
3897 }
3898
3899 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3900 {
3901 bc_src->abs = 1;
3902 bc_src->neg = 0;
3903 }
3904
3905 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3906 {
3907 bc_src->neg = !bc_src->neg;
3908 }
3909
3910 static void tgsi_dst(struct r600_shader_ctx *ctx,
3911 const struct tgsi_full_dst_register *tgsi_dst,
3912 unsigned swizzle,
3913 struct r600_bytecode_alu_dst *r600_dst)
3914 {
3915 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3916
3917 r600_dst->sel = tgsi_dst->Register.Index;
3918 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3919 r600_dst->chan = swizzle;
3920 r600_dst->write = 1;
3921 if (inst->Instruction.Saturate) {
3922 r600_dst->clamp = 1;
3923 }
3924 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3925 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3926 return;
3927 }
3928 }
3929 if (tgsi_dst->Register.Indirect)
3930 r600_dst->rel = V_SQ_REL_RELATIVE;
3931
3932 }
3933
3934 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap, int dest_temp, int op_override)
3935 {
3936 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3937 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3938 struct r600_bytecode_alu alu;
3939 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3940 int use_tmp = 0;
3941 int swizzle_x = inst->Src[0].Register.SwizzleX;
3942
3943 if (singledest) {
3944 switch (write_mask) {
3945 case 0x1:
3946 if (swizzle_x == 2) {
3947 write_mask = 0xc;
3948 use_tmp = 3;
3949 } else
3950 write_mask = 0x3;
3951 break;
3952 case 0x2:
3953 if (swizzle_x == 2) {
3954 write_mask = 0xc;
3955 use_tmp = 3;
3956 } else {
3957 write_mask = 0x3;
3958 use_tmp = 1;
3959 }
3960 break;
3961 case 0x4:
3962 if (swizzle_x == 0) {
3963 write_mask = 0x3;
3964 use_tmp = 1;
3965 } else
3966 write_mask = 0xc;
3967 break;
3968 case 0x8:
3969 if (swizzle_x == 0) {
3970 write_mask = 0x3;
3971 use_tmp = 1;
3972 } else {
3973 write_mask = 0xc;
3974 use_tmp = 3;
3975 }
3976 break;
3977 }
3978 }
3979
3980 lasti = tgsi_last_instruction(write_mask);
3981 for (i = 0; i <= lasti; i++) {
3982
3983 if (!(write_mask & (1 << i)))
3984 continue;
3985
3986 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3987
3988 if (singledest) {
3989 if (use_tmp || dest_temp) {
3990 alu.dst.sel = use_tmp ? ctx->temp_reg : dest_temp;
3991 alu.dst.chan = i;
3992 alu.dst.write = 1;
3993 } else {
3994 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3995 }
3996 if (i == 1 || i == 3)
3997 alu.dst.write = 0;
3998 } else
3999 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4000
4001 alu.op = op_override ? op_override : ctx->inst_info->op;
4002 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
4003 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4004 } else if (!swap) {
4005 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4006 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4007 }
4008 } else {
4009 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
4010 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
4011 }
4012
4013 /* handle some special cases */
4014 if (i == 1 || i == 3) {
4015 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
4016 case TGSI_OPCODE_DABS:
4017 r600_bytecode_src_set_abs(&alu.src[0]);
4018 break;
4019 default:
4020 break;
4021 }
4022 }
4023 if (i == lasti) {
4024 alu.last = 1;
4025 }
4026 r = r600_bytecode_add_alu(ctx->bc, &alu);
4027 if (r)
4028 return r;
4029 }
4030
4031 if (use_tmp) {
4032 write_mask = inst->Dst[0].Register.WriteMask;
4033
4034 lasti = tgsi_last_instruction(write_mask);
4035 /* move result from temp to dst */
4036 for (i = 0; i <= lasti; i++) {
4037 if (!(write_mask & (1 << i)))
4038 continue;
4039
4040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4041 alu.op = ALU_OP1_MOV;
4042
4043 if (dest_temp) {
4044 alu.dst.sel = dest_temp;
4045 alu.dst.chan = i;
4046 alu.dst.write = 1;
4047 } else
4048 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4049 alu.src[0].sel = ctx->temp_reg;
4050 alu.src[0].chan = use_tmp - 1;
4051 alu.last = (i == lasti);
4052
4053 r = r600_bytecode_add_alu(ctx->bc, &alu);
4054 if (r)
4055 return r;
4056 }
4057 }
4058 return 0;
4059 }
4060
4061 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
4062 {
4063 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4064 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4065 /* confirm writemasking */
4066 if ((write_mask & 0x3) != 0x3 &&
4067 (write_mask & 0xc) != 0xc) {
4068 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4069 return -1;
4070 }
4071 return tgsi_op2_64_params(ctx, false, false, 0, 0);
4072 }
4073
4074 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4075 {
4076 return tgsi_op2_64_params(ctx, true, false, 0, 0);
4077 }
4078
4079 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4080 {
4081 return tgsi_op2_64_params(ctx, true, true, 0, 0);
4082 }
4083
4084 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4085 {
4086 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4087 struct r600_bytecode_alu alu;
4088 int i, j, r;
4089 int lasti = 3;
4090 int tmp = r600_get_temp(ctx);
4091
4092 for (i = 0; i < lasti + 1; i++) {
4093
4094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4095 alu.op = ctx->inst_info->op;
4096 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4097 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4098 }
4099
4100 if (inst->Dst[0].Register.WriteMask & (1 << i))
4101 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4102 else
4103 alu.dst.sel = tmp;
4104
4105 alu.dst.chan = i;
4106 alu.is_op3 = 1;
4107 if (i == lasti) {
4108 alu.last = 1;
4109 }
4110 r = r600_bytecode_add_alu(ctx->bc, &alu);
4111 if (r)
4112 return r;
4113 }
4114 return 0;
4115 }
4116
4117 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4118 {
4119 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4120 struct r600_bytecode_alu alu;
4121 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4122 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4123 /* use temp register if trans_only and more than one dst component */
4124 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4125 unsigned op = ctx->inst_info->op;
4126
4127 if (op == ALU_OP2_MUL_IEEE &&
4128 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4129 op = ALU_OP2_MUL;
4130
4131 for (i = 0; i <= lasti; i++) {
4132 if (!(write_mask & (1 << i)))
4133 continue;
4134
4135 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4136 if (use_tmp) {
4137 alu.dst.sel = ctx->temp_reg;
4138 alu.dst.chan = i;
4139 alu.dst.write = 1;
4140 } else
4141 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4142
4143 alu.op = op;
4144 if (!swap) {
4145 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4146 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4147 }
4148 } else {
4149 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4150 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4151 }
4152 if (i == lasti || trans_only) {
4153 alu.last = 1;
4154 }
4155 r = r600_bytecode_add_alu(ctx->bc, &alu);
4156 if (r)
4157 return r;
4158 }
4159
4160 if (use_tmp) {
4161 /* move result from temp to dst */
4162 for (i = 0; i <= lasti; i++) {
4163 if (!(write_mask & (1 << i)))
4164 continue;
4165
4166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4167 alu.op = ALU_OP1_MOV;
4168 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4169 alu.src[0].sel = ctx->temp_reg;
4170 alu.src[0].chan = i;
4171 alu.last = (i == lasti);
4172
4173 r = r600_bytecode_add_alu(ctx->bc, &alu);
4174 if (r)
4175 return r;
4176 }
4177 }
4178 return 0;
4179 }
4180
4181 static int tgsi_op2(struct r600_shader_ctx *ctx)
4182 {
4183 return tgsi_op2_s(ctx, 0, 0);
4184 }
4185
4186 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4187 {
4188 return tgsi_op2_s(ctx, 1, 0);
4189 }
4190
4191 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4192 {
4193 return tgsi_op2_s(ctx, 0, 1);
4194 }
4195
4196 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4197 {
4198 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4199 struct r600_bytecode_alu alu;
4200 int i, r;
4201 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4202
4203 for (i = 0; i < lasti + 1; i++) {
4204
4205 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4206 continue;
4207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4208 alu.op = ctx->inst_info->op;
4209
4210 alu.src[0].sel = V_SQ_ALU_SRC_0;
4211
4212 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4213
4214 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4215
4216 if (i == lasti) {
4217 alu.last = 1;
4218 }
4219 r = r600_bytecode_add_alu(ctx->bc, &alu);
4220 if (r)
4221 return r;
4222 }
4223 return 0;
4224
4225 }
4226
4227 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4228 {
4229 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4230 struct r600_bytecode_alu alu;
4231 int i, r;
4232 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4233
4234 for (i = 0; i < lasti + 1; i++) {
4235
4236 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4237 continue;
4238 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4239 alu.op = ALU_OP1_MOV;
4240
4241 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4242
4243 if (i == 1 || i == 3)
4244 r600_bytecode_src_toggle_neg(&alu.src[0]);
4245 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4246
4247 if (i == lasti) {
4248 alu.last = 1;
4249 }
4250 r = r600_bytecode_add_alu(ctx->bc, &alu);
4251 if (r)
4252 return r;
4253 }
4254 return 0;
4255
4256 }
4257
4258 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4259 {
4260 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4261 struct r600_bytecode_alu alu;
4262 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4263 int i, j, r;
4264
4265 for (i = 0; i <= 3; i++) {
4266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4267 alu.op = ctx->inst_info->op;
4268
4269 alu.dst.sel = ctx->temp_reg;
4270 alu.dst.chan = i;
4271 alu.dst.write = 1;
4272 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4273 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4274 }
4275
4276 if (i == 3)
4277 alu.last = 1;
4278
4279 r = r600_bytecode_add_alu(ctx->bc, &alu);
4280 if (r)
4281 return r;
4282 }
4283
4284 /* Replicate significand result across channels. */
4285 for (i = 0; i <= 3; i++) {
4286 if (!(write_mask & (1 << i)))
4287 continue;
4288
4289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4290 alu.op = ALU_OP1_MOV;
4291 alu.src[0].chan = (i & 1) + 2;
4292 alu.src[0].sel = ctx->temp_reg;
4293
4294 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4295 alu.dst.write = 1;
4296 alu.last = 1;
4297 r = r600_bytecode_add_alu(ctx->bc, &alu);
4298 if (r)
4299 return r;
4300 }
4301
4302 for (i = 0; i <= 3; i++) {
4303 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4304 /* MOV third channels to writemask dst1 */
4305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4306 alu.op = ALU_OP1_MOV;
4307 alu.src[0].chan = 1;
4308 alu.src[0].sel = ctx->temp_reg;
4309
4310 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4311 alu.last = 1;
4312 r = r600_bytecode_add_alu(ctx->bc, &alu);
4313 if (r)
4314 return r;
4315 break;
4316 }
4317 }
4318 return 0;
4319 }
4320
4321
4322 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4323 {
4324 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4325 struct r600_bytecode_alu alu;
4326 int i, r;
4327 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4328
4329 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4330 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4331
4332 for (i = 0; i <= (lasti+1)/2; i++) {
4333 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4334 alu.op = ctx->inst_info->op;
4335
4336 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4337 alu.dst.sel = ctx->temp_reg;
4338 alu.dst.chan = i;
4339 alu.dst.write = 1;
4340 alu.last = 1;
4341
4342 r = r600_bytecode_add_alu(ctx->bc, &alu);
4343 if (r)
4344 return r;
4345 }
4346
4347 for (i = 0; i <= lasti; i++) {
4348 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4349 alu.op = ALU_OP1_FLT32_TO_FLT64;
4350
4351 alu.src[0].chan = i/2;
4352 if (i%2 == 0)
4353 alu.src[0].sel = ctx->temp_reg;
4354 else {
4355 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4356 alu.src[0].value = 0x0;
4357 }
4358 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4359 alu.last = i == lasti;
4360
4361 r = r600_bytecode_add_alu(ctx->bc, &alu);
4362 if (r)
4363 return r;
4364 }
4365
4366 return 0;
4367 }
4368
4369 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4370 {
4371 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4372 struct r600_bytecode_alu alu;
4373 int i, r;
4374 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4375 int treg = r600_get_temp(ctx);
4376 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4377 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4378
4379 /* do a 64->32 into a temp register */
4380 r = tgsi_op2_64_params(ctx, true, false, treg, ALU_OP1_FLT64_TO_FLT32);
4381 if (r)
4382 return r;
4383
4384 for (i = 0; i <= lasti; i++) {
4385 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4386 continue;
4387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4388 alu.op = ctx->inst_info->op;
4389
4390 alu.src[0].chan = i;
4391 alu.src[0].sel = treg;
4392 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4393 alu.last = (i == lasti);
4394
4395 r = r600_bytecode_add_alu(ctx->bc, &alu);
4396 if (r)
4397 return r;
4398 }
4399
4400 return 0;
4401 }
4402
4403 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4404 unsigned op,
4405 int dst_reg,
4406 struct r600_shader_src *src,
4407 bool abs)
4408 {
4409 struct r600_bytecode_alu alu;
4410 const int last_slot = 3;
4411 int r;
4412
4413 /* these have to write the result to X/Y by the looks of it */
4414 for (int i = 0 ; i < last_slot; i++) {
4415 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4416 alu.op = op;
4417
4418 r600_bytecode_src(&alu.src[0], src, 1);
4419 r600_bytecode_src(&alu.src[1], src, 0);
4420
4421 if (abs)
4422 r600_bytecode_src_set_abs(&alu.src[1]);
4423
4424 alu.dst.sel = dst_reg;
4425 alu.dst.chan = i;
4426 alu.dst.write = (i == 0 || i == 1);
4427
4428 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4429 alu.last = 1;
4430 r = r600_bytecode_add_alu(bc, &alu);
4431 if (r)
4432 return r;
4433 }
4434
4435 return 0;
4436 }
4437
4438 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4439 {
4440 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4441 int i, r;
4442 struct r600_bytecode_alu alu;
4443 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4444 int t1 = ctx->temp_reg;
4445
4446 /* should only be one src regs */
4447 assert(inst->Instruction.NumSrcRegs == 1);
4448
4449 /* only support one double at a time */
4450 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4451 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4452
4453 r = cayman_emit_unary_double_raw(
4454 ctx->bc, ctx->inst_info->op, t1,
4455 &ctx->src[0],
4456 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4457 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4458 if (r)
4459 return r;
4460
4461 for (i = 0 ; i <= lasti; i++) {
4462 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4463 continue;
4464 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4465 alu.op = ALU_OP1_MOV;
4466 alu.src[0].sel = t1;
4467 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4468 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4469 alu.dst.write = 1;
4470 if (i == lasti)
4471 alu.last = 1;
4472 r = r600_bytecode_add_alu(ctx->bc, &alu);
4473 if (r)
4474 return r;
4475 }
4476 return 0;
4477 }
4478
4479 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4480 {
4481 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4482 int i, j, r;
4483 struct r600_bytecode_alu alu;
4484 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4485
4486 for (i = 0 ; i < last_slot; i++) {
4487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4488 alu.op = ctx->inst_info->op;
4489 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4490 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4491
4492 /* RSQ should take the absolute value of src */
4493 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4494 r600_bytecode_src_set_abs(&alu.src[j]);
4495 }
4496 }
4497 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4498 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4499
4500 if (i == last_slot - 1)
4501 alu.last = 1;
4502 r = r600_bytecode_add_alu(ctx->bc, &alu);
4503 if (r)
4504 return r;
4505 }
4506 return 0;
4507 }
4508
4509 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4510 {
4511 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4512 int i, j, k, r;
4513 struct r600_bytecode_alu alu;
4514 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4515 int t1 = ctx->temp_reg;
4516
4517 for (k = 0; k <= lasti; k++) {
4518 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4519 continue;
4520
4521 for (i = 0 ; i < 4; i++) {
4522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4523 alu.op = ctx->inst_info->op;
4524 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4525 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4526 }
4527 alu.dst.sel = t1;
4528 alu.dst.chan = i;
4529 alu.dst.write = (i == k);
4530 if (i == 3)
4531 alu.last = 1;
4532 r = r600_bytecode_add_alu(ctx->bc, &alu);
4533 if (r)
4534 return r;
4535 }
4536 }
4537
4538 for (i = 0 ; i <= lasti; i++) {
4539 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4540 continue;
4541 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4542 alu.op = ALU_OP1_MOV;
4543 alu.src[0].sel = t1;
4544 alu.src[0].chan = i;
4545 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4546 alu.dst.write = 1;
4547 if (i == lasti)
4548 alu.last = 1;
4549 r = r600_bytecode_add_alu(ctx->bc, &alu);
4550 if (r)
4551 return r;
4552 }
4553
4554 return 0;
4555 }
4556
4557
4558 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4559 {
4560 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4561 int i, j, k, r;
4562 struct r600_bytecode_alu alu;
4563 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4564 int t1 = ctx->temp_reg;
4565
4566 /* t1 would get overwritten below if we actually tried to
4567 * multiply two pairs of doubles at a time. */
4568 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4569 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4570
4571 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4572
4573 for (i = 0; i < 4; i++) {
4574 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4575 alu.op = ctx->inst_info->op;
4576 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4577 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4578 }
4579 alu.dst.sel = t1;
4580 alu.dst.chan = i;
4581 alu.dst.write = 1;
4582 if (i == 3)
4583 alu.last = 1;
4584 r = r600_bytecode_add_alu(ctx->bc, &alu);
4585 if (r)
4586 return r;
4587 }
4588
4589 for (i = 0; i <= lasti; i++) {
4590 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4591 continue;
4592 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4593 alu.op = ALU_OP1_MOV;
4594 alu.src[0].sel = t1;
4595 alu.src[0].chan = i;
4596 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4597 alu.dst.write = 1;
4598 if (i == lasti)
4599 alu.last = 1;
4600 r = r600_bytecode_add_alu(ctx->bc, &alu);
4601 if (r)
4602 return r;
4603 }
4604
4605 return 0;
4606 }
4607
4608 /*
4609 * Emit RECIP_64 + MUL_64 to implement division.
4610 */
4611 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4612 {
4613 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4614 int r;
4615 struct r600_bytecode_alu alu;
4616 int t1 = ctx->temp_reg;
4617 int k;
4618
4619 /* Only support one double at a time. This is the same constraint as
4620 * in DMUL lowering. */
4621 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4622 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4623
4624 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4625
4626 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4627 if (r)
4628 return r;
4629
4630 for (int i = 0; i < 4; i++) {
4631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4632 alu.op = ALU_OP2_MUL_64;
4633
4634 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4635
4636 alu.src[1].sel = t1;
4637 alu.src[1].chan = (i == 3) ? 0 : 1;
4638
4639 alu.dst.sel = t1;
4640 alu.dst.chan = i;
4641 alu.dst.write = 1;
4642 if (i == 3)
4643 alu.last = 1;
4644 r = r600_bytecode_add_alu(ctx->bc, &alu);
4645 if (r)
4646 return r;
4647 }
4648
4649 for (int i = 0; i < 2; i++) {
4650 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4651 alu.op = ALU_OP1_MOV;
4652 alu.src[0].sel = t1;
4653 alu.src[0].chan = i;
4654 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4655 alu.dst.write = 1;
4656 if (i == 1)
4657 alu.last = 1;
4658 r = r600_bytecode_add_alu(ctx->bc, &alu);
4659 if (r)
4660 return r;
4661 }
4662 return 0;
4663 }
4664
4665 /*
4666 * r600 - trunc to -PI..PI range
4667 * r700 - normalize by dividing by 2PI
4668 * see fdo bug 27901
4669 */
4670 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4671 {
4672 int r;
4673 struct r600_bytecode_alu alu;
4674
4675 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4676 alu.op = ALU_OP3_MULADD;
4677 alu.is_op3 = 1;
4678
4679 alu.dst.chan = 0;
4680 alu.dst.sel = ctx->temp_reg;
4681 alu.dst.write = 1;
4682
4683 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4684
4685 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4686 alu.src[1].chan = 0;
4687 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4688 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4689 alu.src[2].chan = 0;
4690 alu.last = 1;
4691 r = r600_bytecode_add_alu(ctx->bc, &alu);
4692 if (r)
4693 return r;
4694
4695 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4696 alu.op = ALU_OP1_FRACT;
4697
4698 alu.dst.chan = 0;
4699 alu.dst.sel = ctx->temp_reg;
4700 alu.dst.write = 1;
4701
4702 alu.src[0].sel = ctx->temp_reg;
4703 alu.src[0].chan = 0;
4704 alu.last = 1;
4705 r = r600_bytecode_add_alu(ctx->bc, &alu);
4706 if (r)
4707 return r;
4708
4709 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4710 alu.op = ALU_OP3_MULADD;
4711 alu.is_op3 = 1;
4712
4713 alu.dst.chan = 0;
4714 alu.dst.sel = ctx->temp_reg;
4715 alu.dst.write = 1;
4716
4717 alu.src[0].sel = ctx->temp_reg;
4718 alu.src[0].chan = 0;
4719
4720 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4721 alu.src[1].chan = 0;
4722 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4723 alu.src[2].chan = 0;
4724
4725 if (ctx->bc->chip_class == R600) {
4726 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4727 alu.src[2].value = u_bitcast_f2u(-M_PI);
4728 } else {
4729 alu.src[1].sel = V_SQ_ALU_SRC_1;
4730 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4731 alu.src[2].neg = 1;
4732 }
4733
4734 alu.last = 1;
4735 r = r600_bytecode_add_alu(ctx->bc, &alu);
4736 if (r)
4737 return r;
4738 return 0;
4739 }
4740
4741 static int cayman_trig(struct r600_shader_ctx *ctx)
4742 {
4743 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4744 struct r600_bytecode_alu alu;
4745 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4746 int i, r;
4747
4748 r = tgsi_setup_trig(ctx);
4749 if (r)
4750 return r;
4751
4752
4753 for (i = 0; i < last_slot; i++) {
4754 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4755 alu.op = ctx->inst_info->op;
4756 alu.dst.chan = i;
4757
4758 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4759 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4760
4761 alu.src[0].sel = ctx->temp_reg;
4762 alu.src[0].chan = 0;
4763 if (i == last_slot - 1)
4764 alu.last = 1;
4765 r = r600_bytecode_add_alu(ctx->bc, &alu);
4766 if (r)
4767 return r;
4768 }
4769 return 0;
4770 }
4771
4772 static int tgsi_trig(struct r600_shader_ctx *ctx)
4773 {
4774 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4775 struct r600_bytecode_alu alu;
4776 int i, r;
4777 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4778
4779 r = tgsi_setup_trig(ctx);
4780 if (r)
4781 return r;
4782
4783 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4784 alu.op = ctx->inst_info->op;
4785 alu.dst.chan = 0;
4786 alu.dst.sel = ctx->temp_reg;
4787 alu.dst.write = 1;
4788
4789 alu.src[0].sel = ctx->temp_reg;
4790 alu.src[0].chan = 0;
4791 alu.last = 1;
4792 r = r600_bytecode_add_alu(ctx->bc, &alu);
4793 if (r)
4794 return r;
4795
4796 /* replicate result */
4797 for (i = 0; i < lasti + 1; i++) {
4798 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4799 continue;
4800
4801 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4802 alu.op = ALU_OP1_MOV;
4803
4804 alu.src[0].sel = ctx->temp_reg;
4805 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4806 if (i == lasti)
4807 alu.last = 1;
4808 r = r600_bytecode_add_alu(ctx->bc, &alu);
4809 if (r)
4810 return r;
4811 }
4812 return 0;
4813 }
4814
4815 static int tgsi_kill(struct r600_shader_ctx *ctx)
4816 {
4817 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4818 struct r600_bytecode_alu alu;
4819 int i, r;
4820
4821 for (i = 0; i < 4; i++) {
4822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4823 alu.op = ctx->inst_info->op;
4824
4825 alu.dst.chan = i;
4826
4827 alu.src[0].sel = V_SQ_ALU_SRC_0;
4828
4829 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4830 alu.src[1].sel = V_SQ_ALU_SRC_1;
4831 alu.src[1].neg = 1;
4832 } else {
4833 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4834 }
4835 if (i == 3) {
4836 alu.last = 1;
4837 }
4838 r = r600_bytecode_add_alu(ctx->bc, &alu);
4839 if (r)
4840 return r;
4841 }
4842
4843 /* kill must be last in ALU */
4844 ctx->bc->force_add_cf = 1;
4845 ctx->shader->uses_kill = TRUE;
4846 return 0;
4847 }
4848
4849 static int tgsi_lit(struct r600_shader_ctx *ctx)
4850 {
4851 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4852 struct r600_bytecode_alu alu;
4853 int r;
4854
4855 /* tmp.x = max(src.y, 0.0) */
4856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4857 alu.op = ALU_OP2_MAX;
4858 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4859 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4860 alu.src[1].chan = 1;
4861
4862 alu.dst.sel = ctx->temp_reg;
4863 alu.dst.chan = 0;
4864 alu.dst.write = 1;
4865
4866 alu.last = 1;
4867 r = r600_bytecode_add_alu(ctx->bc, &alu);
4868 if (r)
4869 return r;
4870
4871 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4872 {
4873 int chan;
4874 int sel;
4875 unsigned i;
4876
4877 if (ctx->bc->chip_class == CAYMAN) {
4878 for (i = 0; i < 3; i++) {
4879 /* tmp.z = log(tmp.x) */
4880 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4881 alu.op = ALU_OP1_LOG_CLAMPED;
4882 alu.src[0].sel = ctx->temp_reg;
4883 alu.src[0].chan = 0;
4884 alu.dst.sel = ctx->temp_reg;
4885 alu.dst.chan = i;
4886 if (i == 2) {
4887 alu.dst.write = 1;
4888 alu.last = 1;
4889 } else
4890 alu.dst.write = 0;
4891
4892 r = r600_bytecode_add_alu(ctx->bc, &alu);
4893 if (r)
4894 return r;
4895 }
4896 } else {
4897 /* tmp.z = log(tmp.x) */
4898 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4899 alu.op = ALU_OP1_LOG_CLAMPED;
4900 alu.src[0].sel = ctx->temp_reg;
4901 alu.src[0].chan = 0;
4902 alu.dst.sel = ctx->temp_reg;
4903 alu.dst.chan = 2;
4904 alu.dst.write = 1;
4905 alu.last = 1;
4906 r = r600_bytecode_add_alu(ctx->bc, &alu);
4907 if (r)
4908 return r;
4909 }
4910
4911 chan = alu.dst.chan;
4912 sel = alu.dst.sel;
4913
4914 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4916 alu.op = ALU_OP3_MUL_LIT;
4917 alu.src[0].sel = sel;
4918 alu.src[0].chan = chan;
4919 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4920 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4921 alu.dst.sel = ctx->temp_reg;
4922 alu.dst.chan = 0;
4923 alu.dst.write = 1;
4924 alu.is_op3 = 1;
4925 alu.last = 1;
4926 r = r600_bytecode_add_alu(ctx->bc, &alu);
4927 if (r)
4928 return r;
4929
4930 if (ctx->bc->chip_class == CAYMAN) {
4931 for (i = 0; i < 3; i++) {
4932 /* dst.z = exp(tmp.x) */
4933 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4934 alu.op = ALU_OP1_EXP_IEEE;
4935 alu.src[0].sel = ctx->temp_reg;
4936 alu.src[0].chan = 0;
4937 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4938 if (i == 2) {
4939 alu.dst.write = 1;
4940 alu.last = 1;
4941 } else
4942 alu.dst.write = 0;
4943 r = r600_bytecode_add_alu(ctx->bc, &alu);
4944 if (r)
4945 return r;
4946 }
4947 } else {
4948 /* dst.z = exp(tmp.x) */
4949 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4950 alu.op = ALU_OP1_EXP_IEEE;
4951 alu.src[0].sel = ctx->temp_reg;
4952 alu.src[0].chan = 0;
4953 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4954 alu.last = 1;
4955 r = r600_bytecode_add_alu(ctx->bc, &alu);
4956 if (r)
4957 return r;
4958 }
4959 }
4960
4961 /* dst.x, <- 1.0 */
4962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4963 alu.op = ALU_OP1_MOV;
4964 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4965 alu.src[0].chan = 0;
4966 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4967 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4968 r = r600_bytecode_add_alu(ctx->bc, &alu);
4969 if (r)
4970 return r;
4971
4972 /* dst.y = max(src.x, 0.0) */
4973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4974 alu.op = ALU_OP2_MAX;
4975 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4976 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4977 alu.src[1].chan = 0;
4978 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4979 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4980 r = r600_bytecode_add_alu(ctx->bc, &alu);
4981 if (r)
4982 return r;
4983
4984 /* dst.w, <- 1.0 */
4985 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4986 alu.op = ALU_OP1_MOV;
4987 alu.src[0].sel = V_SQ_ALU_SRC_1;
4988 alu.src[0].chan = 0;
4989 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4990 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4991 alu.last = 1;
4992 r = r600_bytecode_add_alu(ctx->bc, &alu);
4993 if (r)
4994 return r;
4995
4996 return 0;
4997 }
4998
4999 static int tgsi_rsq(struct r600_shader_ctx *ctx)
5000 {
5001 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5002 struct r600_bytecode_alu alu;
5003 int i, r;
5004
5005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5006
5007 alu.op = ALU_OP1_RECIPSQRT_IEEE;
5008
5009 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5010 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5011 r600_bytecode_src_set_abs(&alu.src[i]);
5012 }
5013 alu.dst.sel = ctx->temp_reg;
5014 alu.dst.write = 1;
5015 alu.last = 1;
5016 r = r600_bytecode_add_alu(ctx->bc, &alu);
5017 if (r)
5018 return r;
5019 /* replicate result */
5020 return tgsi_helper_tempx_replicate(ctx);
5021 }
5022
5023 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
5024 {
5025 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5026 struct r600_bytecode_alu alu;
5027 int i, r;
5028
5029 for (i = 0; i < 4; i++) {
5030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5031 alu.src[0].sel = ctx->temp_reg;
5032 alu.op = ALU_OP1_MOV;
5033 alu.dst.chan = i;
5034 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5035 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5036 if (i == 3)
5037 alu.last = 1;
5038 r = r600_bytecode_add_alu(ctx->bc, &alu);
5039 if (r)
5040 return r;
5041 }
5042 return 0;
5043 }
5044
5045 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
5046 {
5047 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5048 struct r600_bytecode_alu alu;
5049 int i, r;
5050
5051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5052 alu.op = ctx->inst_info->op;
5053 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5054 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5055 }
5056 alu.dst.sel = ctx->temp_reg;
5057 alu.dst.write = 1;
5058 alu.last = 1;
5059 r = r600_bytecode_add_alu(ctx->bc, &alu);
5060 if (r)
5061 return r;
5062 /* replicate result */
5063 return tgsi_helper_tempx_replicate(ctx);
5064 }
5065
5066 static int cayman_pow(struct r600_shader_ctx *ctx)
5067 {
5068 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5069 int i, r;
5070 struct r600_bytecode_alu alu;
5071 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5072
5073 for (i = 0; i < 3; i++) {
5074 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5075 alu.op = ALU_OP1_LOG_IEEE;
5076 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5077 alu.dst.sel = ctx->temp_reg;
5078 alu.dst.chan = i;
5079 alu.dst.write = 1;
5080 if (i == 2)
5081 alu.last = 1;
5082 r = r600_bytecode_add_alu(ctx->bc, &alu);
5083 if (r)
5084 return r;
5085 }
5086
5087 /* b * LOG2(a) */
5088 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5089 alu.op = ALU_OP2_MUL;
5090 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5091 alu.src[1].sel = ctx->temp_reg;
5092 alu.dst.sel = ctx->temp_reg;
5093 alu.dst.write = 1;
5094 alu.last = 1;
5095 r = r600_bytecode_add_alu(ctx->bc, &alu);
5096 if (r)
5097 return r;
5098
5099 for (i = 0; i < last_slot; i++) {
5100 /* POW(a,b) = EXP2(b * LOG2(a))*/
5101 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5102 alu.op = ALU_OP1_EXP_IEEE;
5103 alu.src[0].sel = ctx->temp_reg;
5104
5105 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5106 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5107 if (i == last_slot - 1)
5108 alu.last = 1;
5109 r = r600_bytecode_add_alu(ctx->bc, &alu);
5110 if (r)
5111 return r;
5112 }
5113 return 0;
5114 }
5115
5116 static int tgsi_pow(struct r600_shader_ctx *ctx)
5117 {
5118 struct r600_bytecode_alu alu;
5119 int r;
5120
5121 /* LOG2(a) */
5122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5123 alu.op = ALU_OP1_LOG_IEEE;
5124 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5125 alu.dst.sel = ctx->temp_reg;
5126 alu.dst.write = 1;
5127 alu.last = 1;
5128 r = r600_bytecode_add_alu(ctx->bc, &alu);
5129 if (r)
5130 return r;
5131 /* b * LOG2(a) */
5132 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5133 alu.op = ALU_OP2_MUL;
5134 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5135 alu.src[1].sel = ctx->temp_reg;
5136 alu.dst.sel = ctx->temp_reg;
5137 alu.dst.write = 1;
5138 alu.last = 1;
5139 r = r600_bytecode_add_alu(ctx->bc, &alu);
5140 if (r)
5141 return r;
5142 /* POW(a,b) = EXP2(b * LOG2(a))*/
5143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5144 alu.op = ALU_OP1_EXP_IEEE;
5145 alu.src[0].sel = ctx->temp_reg;
5146 alu.dst.sel = ctx->temp_reg;
5147 alu.dst.write = 1;
5148 alu.last = 1;
5149 r = r600_bytecode_add_alu(ctx->bc, &alu);
5150 if (r)
5151 return r;
5152 return tgsi_helper_tempx_replicate(ctx);
5153 }
5154
5155 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5156 {
5157 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5158 struct r600_bytecode_alu alu;
5159 int i, r, j;
5160 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5161 int tmp0 = ctx->temp_reg;
5162 int tmp1 = r600_get_temp(ctx);
5163 int tmp2 = r600_get_temp(ctx);
5164 int tmp3 = r600_get_temp(ctx);
5165 /* Unsigned path:
5166 *
5167 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5168 *
5169 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5170 * 2. tmp0.z = lo (tmp0.x * src2)
5171 * 3. tmp0.w = -tmp0.z
5172 * 4. tmp0.y = hi (tmp0.x * src2)
5173 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5174 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5175 * 7. tmp1.x = tmp0.x - tmp0.w
5176 * 8. tmp1.y = tmp0.x + tmp0.w
5177 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5178 * 10. tmp0.z = hi(tmp0.x * src1) = q
5179 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5180 *
5181 * 12. tmp0.w = src1 - tmp0.y = r
5182 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5183 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5184 *
5185 * if DIV
5186 *
5187 * 15. tmp1.z = tmp0.z + 1 = q + 1
5188 * 16. tmp1.w = tmp0.z - 1 = q - 1
5189 *
5190 * else MOD
5191 *
5192 * 15. tmp1.z = tmp0.w - src2 = r - src2
5193 * 16. tmp1.w = tmp0.w + src2 = r + src2
5194 *
5195 * endif
5196 *
5197 * 17. tmp1.x = tmp1.x & tmp1.y
5198 *
5199 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5200 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5201 *
5202 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5203 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5204 *
5205 * Signed path:
5206 *
5207 * Same as unsigned, using abs values of the operands,
5208 * and fixing the sign of the result in the end.
5209 */
5210
5211 for (i = 0; i < 4; i++) {
5212 if (!(write_mask & (1<<i)))
5213 continue;
5214
5215 if (signed_op) {
5216
5217 /* tmp2.x = -src0 */
5218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5219 alu.op = ALU_OP2_SUB_INT;
5220
5221 alu.dst.sel = tmp2;
5222 alu.dst.chan = 0;
5223 alu.dst.write = 1;
5224
5225 alu.src[0].sel = V_SQ_ALU_SRC_0;
5226
5227 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5228
5229 alu.last = 1;
5230 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5231 return r;
5232
5233 /* tmp2.y = -src1 */
5234 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5235 alu.op = ALU_OP2_SUB_INT;
5236
5237 alu.dst.sel = tmp2;
5238 alu.dst.chan = 1;
5239 alu.dst.write = 1;
5240
5241 alu.src[0].sel = V_SQ_ALU_SRC_0;
5242
5243 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5244
5245 alu.last = 1;
5246 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5247 return r;
5248
5249 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5250 /* it will be a sign of the quotient */
5251 if (!mod) {
5252
5253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5254 alu.op = ALU_OP2_XOR_INT;
5255
5256 alu.dst.sel = tmp2;
5257 alu.dst.chan = 2;
5258 alu.dst.write = 1;
5259
5260 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5261 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5262
5263 alu.last = 1;
5264 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5265 return r;
5266 }
5267
5268 /* tmp2.x = |src0| */
5269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5270 alu.op = ALU_OP3_CNDGE_INT;
5271 alu.is_op3 = 1;
5272
5273 alu.dst.sel = tmp2;
5274 alu.dst.chan = 0;
5275 alu.dst.write = 1;
5276
5277 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5278 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5279 alu.src[2].sel = tmp2;
5280 alu.src[2].chan = 0;
5281
5282 alu.last = 1;
5283 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5284 return r;
5285
5286 /* tmp2.y = |src1| */
5287 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5288 alu.op = ALU_OP3_CNDGE_INT;
5289 alu.is_op3 = 1;
5290
5291 alu.dst.sel = tmp2;
5292 alu.dst.chan = 1;
5293 alu.dst.write = 1;
5294
5295 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5296 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5297 alu.src[2].sel = tmp2;
5298 alu.src[2].chan = 1;
5299
5300 alu.last = 1;
5301 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5302 return r;
5303
5304 }
5305
5306 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5307 if (ctx->bc->chip_class == CAYMAN) {
5308 /* tmp3.x = u2f(src2) */
5309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5310 alu.op = ALU_OP1_UINT_TO_FLT;
5311
5312 alu.dst.sel = tmp3;
5313 alu.dst.chan = 0;
5314 alu.dst.write = 1;
5315
5316 if (signed_op) {
5317 alu.src[0].sel = tmp2;
5318 alu.src[0].chan = 1;
5319 } else {
5320 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5321 }
5322
5323 alu.last = 1;
5324 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5325 return r;
5326
5327 /* tmp0.x = recip(tmp3.x) */
5328 for (j = 0 ; j < 3; j++) {
5329 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5330 alu.op = ALU_OP1_RECIP_IEEE;
5331
5332 alu.dst.sel = tmp0;
5333 alu.dst.chan = j;
5334 alu.dst.write = (j == 0);
5335
5336 alu.src[0].sel = tmp3;
5337 alu.src[0].chan = 0;
5338
5339 if (j == 2)
5340 alu.last = 1;
5341 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5342 return r;
5343 }
5344
5345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5346 alu.op = ALU_OP2_MUL;
5347
5348 alu.src[0].sel = tmp0;
5349 alu.src[0].chan = 0;
5350
5351 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5352 alu.src[1].value = 0x4f800000;
5353
5354 alu.dst.sel = tmp3;
5355 alu.dst.write = 1;
5356 alu.last = 1;
5357 r = r600_bytecode_add_alu(ctx->bc, &alu);
5358 if (r)
5359 return r;
5360
5361 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5362 alu.op = ALU_OP1_FLT_TO_UINT;
5363
5364 alu.dst.sel = tmp0;
5365 alu.dst.chan = 0;
5366 alu.dst.write = 1;
5367
5368 alu.src[0].sel = tmp3;
5369 alu.src[0].chan = 0;
5370
5371 alu.last = 1;
5372 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5373 return r;
5374
5375 } else {
5376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5377 alu.op = ALU_OP1_RECIP_UINT;
5378
5379 alu.dst.sel = tmp0;
5380 alu.dst.chan = 0;
5381 alu.dst.write = 1;
5382
5383 if (signed_op) {
5384 alu.src[0].sel = tmp2;
5385 alu.src[0].chan = 1;
5386 } else {
5387 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5388 }
5389
5390 alu.last = 1;
5391 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5392 return r;
5393 }
5394
5395 /* 2. tmp0.z = lo (tmp0.x * src2) */
5396 if (ctx->bc->chip_class == CAYMAN) {
5397 for (j = 0 ; j < 4; j++) {
5398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5399 alu.op = ALU_OP2_MULLO_UINT;
5400
5401 alu.dst.sel = tmp0;
5402 alu.dst.chan = j;
5403 alu.dst.write = (j == 2);
5404
5405 alu.src[0].sel = tmp0;
5406 alu.src[0].chan = 0;
5407 if (signed_op) {
5408 alu.src[1].sel = tmp2;
5409 alu.src[1].chan = 1;
5410 } else {
5411 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5412 }
5413
5414 alu.last = (j == 3);
5415 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5416 return r;
5417 }
5418 } else {
5419 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5420 alu.op = ALU_OP2_MULLO_UINT;
5421
5422 alu.dst.sel = tmp0;
5423 alu.dst.chan = 2;
5424 alu.dst.write = 1;
5425
5426 alu.src[0].sel = tmp0;
5427 alu.src[0].chan = 0;
5428 if (signed_op) {
5429 alu.src[1].sel = tmp2;
5430 alu.src[1].chan = 1;
5431 } else {
5432 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5433 }
5434
5435 alu.last = 1;
5436 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5437 return r;
5438 }
5439
5440 /* 3. tmp0.w = -tmp0.z */
5441 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5442 alu.op = ALU_OP2_SUB_INT;
5443
5444 alu.dst.sel = tmp0;
5445 alu.dst.chan = 3;
5446 alu.dst.write = 1;
5447
5448 alu.src[0].sel = V_SQ_ALU_SRC_0;
5449 alu.src[1].sel = tmp0;
5450 alu.src[1].chan = 2;
5451
5452 alu.last = 1;
5453 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5454 return r;
5455
5456 /* 4. tmp0.y = hi (tmp0.x * src2) */
5457 if (ctx->bc->chip_class == CAYMAN) {
5458 for (j = 0 ; j < 4; j++) {
5459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5460 alu.op = ALU_OP2_MULHI_UINT;
5461
5462 alu.dst.sel = tmp0;
5463 alu.dst.chan = j;
5464 alu.dst.write = (j == 1);
5465
5466 alu.src[0].sel = tmp0;
5467 alu.src[0].chan = 0;
5468
5469 if (signed_op) {
5470 alu.src[1].sel = tmp2;
5471 alu.src[1].chan = 1;
5472 } else {
5473 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5474 }
5475 alu.last = (j == 3);
5476 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5477 return r;
5478 }
5479 } else {
5480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5481 alu.op = ALU_OP2_MULHI_UINT;
5482
5483 alu.dst.sel = tmp0;
5484 alu.dst.chan = 1;
5485 alu.dst.write = 1;
5486
5487 alu.src[0].sel = tmp0;
5488 alu.src[0].chan = 0;
5489
5490 if (signed_op) {
5491 alu.src[1].sel = tmp2;
5492 alu.src[1].chan = 1;
5493 } else {
5494 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5495 }
5496
5497 alu.last = 1;
5498 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5499 return r;
5500 }
5501
5502 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5503 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5504 alu.op = ALU_OP3_CNDE_INT;
5505 alu.is_op3 = 1;
5506
5507 alu.dst.sel = tmp0;
5508 alu.dst.chan = 2;
5509 alu.dst.write = 1;
5510
5511 alu.src[0].sel = tmp0;
5512 alu.src[0].chan = 1;
5513 alu.src[1].sel = tmp0;
5514 alu.src[1].chan = 3;
5515 alu.src[2].sel = tmp0;
5516 alu.src[2].chan = 2;
5517
5518 alu.last = 1;
5519 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5520 return r;
5521
5522 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5523 if (ctx->bc->chip_class == CAYMAN) {
5524 for (j = 0 ; j < 4; j++) {
5525 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5526 alu.op = ALU_OP2_MULHI_UINT;
5527
5528 alu.dst.sel = tmp0;
5529 alu.dst.chan = j;
5530 alu.dst.write = (j == 3);
5531
5532 alu.src[0].sel = tmp0;
5533 alu.src[0].chan = 2;
5534
5535 alu.src[1].sel = tmp0;
5536 alu.src[1].chan = 0;
5537
5538 alu.last = (j == 3);
5539 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5540 return r;
5541 }
5542 } else {
5543 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5544 alu.op = ALU_OP2_MULHI_UINT;
5545
5546 alu.dst.sel = tmp0;
5547 alu.dst.chan = 3;
5548 alu.dst.write = 1;
5549
5550 alu.src[0].sel = tmp0;
5551 alu.src[0].chan = 2;
5552
5553 alu.src[1].sel = tmp0;
5554 alu.src[1].chan = 0;
5555
5556 alu.last = 1;
5557 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5558 return r;
5559 }
5560
5561 /* 7. tmp1.x = tmp0.x - tmp0.w */
5562 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5563 alu.op = ALU_OP2_SUB_INT;
5564
5565 alu.dst.sel = tmp1;
5566 alu.dst.chan = 0;
5567 alu.dst.write = 1;
5568
5569 alu.src[0].sel = tmp0;
5570 alu.src[0].chan = 0;
5571 alu.src[1].sel = tmp0;
5572 alu.src[1].chan = 3;
5573
5574 alu.last = 1;
5575 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5576 return r;
5577
5578 /* 8. tmp1.y = tmp0.x + tmp0.w */
5579 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5580 alu.op = ALU_OP2_ADD_INT;
5581
5582 alu.dst.sel = tmp1;
5583 alu.dst.chan = 1;
5584 alu.dst.write = 1;
5585
5586 alu.src[0].sel = tmp0;
5587 alu.src[0].chan = 0;
5588 alu.src[1].sel = tmp0;
5589 alu.src[1].chan = 3;
5590
5591 alu.last = 1;
5592 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5593 return r;
5594
5595 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5596 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5597 alu.op = ALU_OP3_CNDE_INT;
5598 alu.is_op3 = 1;
5599
5600 alu.dst.sel = tmp0;
5601 alu.dst.chan = 0;
5602 alu.dst.write = 1;
5603
5604 alu.src[0].sel = tmp0;
5605 alu.src[0].chan = 1;
5606 alu.src[1].sel = tmp1;
5607 alu.src[1].chan = 1;
5608 alu.src[2].sel = tmp1;
5609 alu.src[2].chan = 0;
5610
5611 alu.last = 1;
5612 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5613 return r;
5614
5615 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5616 if (ctx->bc->chip_class == CAYMAN) {
5617 for (j = 0 ; j < 4; j++) {
5618 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5619 alu.op = ALU_OP2_MULHI_UINT;
5620
5621 alu.dst.sel = tmp0;
5622 alu.dst.chan = j;
5623 alu.dst.write = (j == 2);
5624
5625 alu.src[0].sel = tmp0;
5626 alu.src[0].chan = 0;
5627
5628 if (signed_op) {
5629 alu.src[1].sel = tmp2;
5630 alu.src[1].chan = 0;
5631 } else {
5632 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5633 }
5634
5635 alu.last = (j == 3);
5636 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5637 return r;
5638 }
5639 } else {
5640 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5641 alu.op = ALU_OP2_MULHI_UINT;
5642
5643 alu.dst.sel = tmp0;
5644 alu.dst.chan = 2;
5645 alu.dst.write = 1;
5646
5647 alu.src[0].sel = tmp0;
5648 alu.src[0].chan = 0;
5649
5650 if (signed_op) {
5651 alu.src[1].sel = tmp2;
5652 alu.src[1].chan = 0;
5653 } else {
5654 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5655 }
5656
5657 alu.last = 1;
5658 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5659 return r;
5660 }
5661
5662 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5663 if (ctx->bc->chip_class == CAYMAN) {
5664 for (j = 0 ; j < 4; j++) {
5665 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5666 alu.op = ALU_OP2_MULLO_UINT;
5667
5668 alu.dst.sel = tmp0;
5669 alu.dst.chan = j;
5670 alu.dst.write = (j == 1);
5671
5672 if (signed_op) {
5673 alu.src[0].sel = tmp2;
5674 alu.src[0].chan = 1;
5675 } else {
5676 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5677 }
5678
5679 alu.src[1].sel = tmp0;
5680 alu.src[1].chan = 2;
5681
5682 alu.last = (j == 3);
5683 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5684 return r;
5685 }
5686 } else {
5687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5688 alu.op = ALU_OP2_MULLO_UINT;
5689
5690 alu.dst.sel = tmp0;
5691 alu.dst.chan = 1;
5692 alu.dst.write = 1;
5693
5694 if (signed_op) {
5695 alu.src[0].sel = tmp2;
5696 alu.src[0].chan = 1;
5697 } else {
5698 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5699 }
5700
5701 alu.src[1].sel = tmp0;
5702 alu.src[1].chan = 2;
5703
5704 alu.last = 1;
5705 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5706 return r;
5707 }
5708
5709 /* 12. tmp0.w = src1 - tmp0.y = r */
5710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5711 alu.op = ALU_OP2_SUB_INT;
5712
5713 alu.dst.sel = tmp0;
5714 alu.dst.chan = 3;
5715 alu.dst.write = 1;
5716
5717 if (signed_op) {
5718 alu.src[0].sel = tmp2;
5719 alu.src[0].chan = 0;
5720 } else {
5721 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5722 }
5723
5724 alu.src[1].sel = tmp0;
5725 alu.src[1].chan = 1;
5726
5727 alu.last = 1;
5728 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5729 return r;
5730
5731 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5732 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5733 alu.op = ALU_OP2_SETGE_UINT;
5734
5735 alu.dst.sel = tmp1;
5736 alu.dst.chan = 0;
5737 alu.dst.write = 1;
5738
5739 alu.src[0].sel = tmp0;
5740 alu.src[0].chan = 3;
5741 if (signed_op) {
5742 alu.src[1].sel = tmp2;
5743 alu.src[1].chan = 1;
5744 } else {
5745 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5746 }
5747
5748 alu.last = 1;
5749 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5750 return r;
5751
5752 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5754 alu.op = ALU_OP2_SETGE_UINT;
5755
5756 alu.dst.sel = tmp1;
5757 alu.dst.chan = 1;
5758 alu.dst.write = 1;
5759
5760 if (signed_op) {
5761 alu.src[0].sel = tmp2;
5762 alu.src[0].chan = 0;
5763 } else {
5764 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5765 }
5766
5767 alu.src[1].sel = tmp0;
5768 alu.src[1].chan = 1;
5769
5770 alu.last = 1;
5771 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5772 return r;
5773
5774 if (mod) { /* UMOD */
5775
5776 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5777 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5778 alu.op = ALU_OP2_SUB_INT;
5779
5780 alu.dst.sel = tmp1;
5781 alu.dst.chan = 2;
5782 alu.dst.write = 1;
5783
5784 alu.src[0].sel = tmp0;
5785 alu.src[0].chan = 3;
5786
5787 if (signed_op) {
5788 alu.src[1].sel = tmp2;
5789 alu.src[1].chan = 1;
5790 } else {
5791 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5792 }
5793
5794 alu.last = 1;
5795 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5796 return r;
5797
5798 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5799 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5800 alu.op = ALU_OP2_ADD_INT;
5801
5802 alu.dst.sel = tmp1;
5803 alu.dst.chan = 3;
5804 alu.dst.write = 1;
5805
5806 alu.src[0].sel = tmp0;
5807 alu.src[0].chan = 3;
5808 if (signed_op) {
5809 alu.src[1].sel = tmp2;
5810 alu.src[1].chan = 1;
5811 } else {
5812 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5813 }
5814
5815 alu.last = 1;
5816 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5817 return r;
5818
5819 } else { /* UDIV */
5820
5821 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5823 alu.op = ALU_OP2_ADD_INT;
5824
5825 alu.dst.sel = tmp1;
5826 alu.dst.chan = 2;
5827 alu.dst.write = 1;
5828
5829 alu.src[0].sel = tmp0;
5830 alu.src[0].chan = 2;
5831 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5832
5833 alu.last = 1;
5834 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5835 return r;
5836
5837 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5839 alu.op = ALU_OP2_ADD_INT;
5840
5841 alu.dst.sel = tmp1;
5842 alu.dst.chan = 3;
5843 alu.dst.write = 1;
5844
5845 alu.src[0].sel = tmp0;
5846 alu.src[0].chan = 2;
5847 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5848
5849 alu.last = 1;
5850 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5851 return r;
5852
5853 }
5854
5855 /* 17. tmp1.x = tmp1.x & tmp1.y */
5856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5857 alu.op = ALU_OP2_AND_INT;
5858
5859 alu.dst.sel = tmp1;
5860 alu.dst.chan = 0;
5861 alu.dst.write = 1;
5862
5863 alu.src[0].sel = tmp1;
5864 alu.src[0].chan = 0;
5865 alu.src[1].sel = tmp1;
5866 alu.src[1].chan = 1;
5867
5868 alu.last = 1;
5869 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5870 return r;
5871
5872 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5873 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5874 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5875 alu.op = ALU_OP3_CNDE_INT;
5876 alu.is_op3 = 1;
5877
5878 alu.dst.sel = tmp0;
5879 alu.dst.chan = 2;
5880 alu.dst.write = 1;
5881
5882 alu.src[0].sel = tmp1;
5883 alu.src[0].chan = 0;
5884 alu.src[1].sel = tmp0;
5885 alu.src[1].chan = mod ? 3 : 2;
5886 alu.src[2].sel = tmp1;
5887 alu.src[2].chan = 2;
5888
5889 alu.last = 1;
5890 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5891 return r;
5892
5893 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5894 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5895 alu.op = ALU_OP3_CNDE_INT;
5896 alu.is_op3 = 1;
5897
5898 if (signed_op) {
5899 alu.dst.sel = tmp0;
5900 alu.dst.chan = 2;
5901 alu.dst.write = 1;
5902 } else {
5903 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5904 }
5905
5906 alu.src[0].sel = tmp1;
5907 alu.src[0].chan = 1;
5908 alu.src[1].sel = tmp1;
5909 alu.src[1].chan = 3;
5910 alu.src[2].sel = tmp0;
5911 alu.src[2].chan = 2;
5912
5913 alu.last = 1;
5914 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5915 return r;
5916
5917 if (signed_op) {
5918
5919 /* fix the sign of the result */
5920
5921 if (mod) {
5922
5923 /* tmp0.x = -tmp0.z */
5924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5925 alu.op = ALU_OP2_SUB_INT;
5926
5927 alu.dst.sel = tmp0;
5928 alu.dst.chan = 0;
5929 alu.dst.write = 1;
5930
5931 alu.src[0].sel = V_SQ_ALU_SRC_0;
5932 alu.src[1].sel = tmp0;
5933 alu.src[1].chan = 2;
5934
5935 alu.last = 1;
5936 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5937 return r;
5938
5939 /* sign of the remainder is the same as the sign of src0 */
5940 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5942 alu.op = ALU_OP3_CNDGE_INT;
5943 alu.is_op3 = 1;
5944
5945 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5946
5947 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5948 alu.src[1].sel = tmp0;
5949 alu.src[1].chan = 2;
5950 alu.src[2].sel = tmp0;
5951 alu.src[2].chan = 0;
5952
5953 alu.last = 1;
5954 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5955 return r;
5956
5957 } else {
5958
5959 /* tmp0.x = -tmp0.z */
5960 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5961 alu.op = ALU_OP2_SUB_INT;
5962
5963 alu.dst.sel = tmp0;
5964 alu.dst.chan = 0;
5965 alu.dst.write = 1;
5966
5967 alu.src[0].sel = V_SQ_ALU_SRC_0;
5968 alu.src[1].sel = tmp0;
5969 alu.src[1].chan = 2;
5970
5971 alu.last = 1;
5972 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5973 return r;
5974
5975 /* fix the quotient sign (same as the sign of src0*src1) */
5976 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5978 alu.op = ALU_OP3_CNDGE_INT;
5979 alu.is_op3 = 1;
5980
5981 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5982
5983 alu.src[0].sel = tmp2;
5984 alu.src[0].chan = 2;
5985 alu.src[1].sel = tmp0;
5986 alu.src[1].chan = 2;
5987 alu.src[2].sel = tmp0;
5988 alu.src[2].chan = 0;
5989
5990 alu.last = 1;
5991 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5992 return r;
5993 }
5994 }
5995 }
5996 return 0;
5997 }
5998
5999 static int tgsi_udiv(struct r600_shader_ctx *ctx)
6000 {
6001 return tgsi_divmod(ctx, 0, 0);
6002 }
6003
6004 static int tgsi_umod(struct r600_shader_ctx *ctx)
6005 {
6006 return tgsi_divmod(ctx, 1, 0);
6007 }
6008
6009 static int tgsi_idiv(struct r600_shader_ctx *ctx)
6010 {
6011 return tgsi_divmod(ctx, 0, 1);
6012 }
6013
6014 static int tgsi_imod(struct r600_shader_ctx *ctx)
6015 {
6016 return tgsi_divmod(ctx, 1, 1);
6017 }
6018
6019
6020 static int tgsi_f2i(struct r600_shader_ctx *ctx)
6021 {
6022 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6023 struct r600_bytecode_alu alu;
6024 int i, r;
6025 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6026 int last_inst = tgsi_last_instruction(write_mask);
6027
6028 for (i = 0; i < 4; i++) {
6029 if (!(write_mask & (1<<i)))
6030 continue;
6031
6032 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6033 alu.op = ALU_OP1_TRUNC;
6034
6035 alu.dst.sel = ctx->temp_reg;
6036 alu.dst.chan = i;
6037 alu.dst.write = 1;
6038
6039 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6040 if (i == last_inst)
6041 alu.last = 1;
6042 r = r600_bytecode_add_alu(ctx->bc, &alu);
6043 if (r)
6044 return r;
6045 }
6046
6047 for (i = 0; i < 4; i++) {
6048 if (!(write_mask & (1<<i)))
6049 continue;
6050
6051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6052 alu.op = ctx->inst_info->op;
6053
6054 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6055
6056 alu.src[0].sel = ctx->temp_reg;
6057 alu.src[0].chan = i;
6058
6059 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6060 alu.last = 1;
6061 r = r600_bytecode_add_alu(ctx->bc, &alu);
6062 if (r)
6063 return r;
6064 }
6065
6066 return 0;
6067 }
6068
6069 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6070 {
6071 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6072 struct r600_bytecode_alu alu;
6073 int i, r;
6074 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6075 int last_inst = tgsi_last_instruction(write_mask);
6076
6077 /* tmp = -src */
6078 for (i = 0; i < 4; i++) {
6079 if (!(write_mask & (1<<i)))
6080 continue;
6081
6082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6083 alu.op = ALU_OP2_SUB_INT;
6084
6085 alu.dst.sel = ctx->temp_reg;
6086 alu.dst.chan = i;
6087 alu.dst.write = 1;
6088
6089 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6090 alu.src[0].sel = V_SQ_ALU_SRC_0;
6091
6092 if (i == last_inst)
6093 alu.last = 1;
6094 r = r600_bytecode_add_alu(ctx->bc, &alu);
6095 if (r)
6096 return r;
6097 }
6098
6099 /* dst = (src >= 0 ? src : tmp) */
6100 for (i = 0; i < 4; i++) {
6101 if (!(write_mask & (1<<i)))
6102 continue;
6103
6104 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6105 alu.op = ALU_OP3_CNDGE_INT;
6106 alu.is_op3 = 1;
6107 alu.dst.write = 1;
6108
6109 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6110
6111 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6112 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6113 alu.src[2].sel = ctx->temp_reg;
6114 alu.src[2].chan = i;
6115
6116 if (i == last_inst)
6117 alu.last = 1;
6118 r = r600_bytecode_add_alu(ctx->bc, &alu);
6119 if (r)
6120 return r;
6121 }
6122 return 0;
6123 }
6124
6125 static int tgsi_issg(struct r600_shader_ctx *ctx)
6126 {
6127 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6128 struct r600_bytecode_alu alu;
6129 int i, r;
6130 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6131 int last_inst = tgsi_last_instruction(write_mask);
6132
6133 /* tmp = (src >= 0 ? src : -1) */
6134 for (i = 0; i < 4; i++) {
6135 if (!(write_mask & (1<<i)))
6136 continue;
6137
6138 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6139 alu.op = ALU_OP3_CNDGE_INT;
6140 alu.is_op3 = 1;
6141
6142 alu.dst.sel = ctx->temp_reg;
6143 alu.dst.chan = i;
6144 alu.dst.write = 1;
6145
6146 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6147 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6148 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6149
6150 if (i == last_inst)
6151 alu.last = 1;
6152 r = r600_bytecode_add_alu(ctx->bc, &alu);
6153 if (r)
6154 return r;
6155 }
6156
6157 /* dst = (tmp > 0 ? 1 : tmp) */
6158 for (i = 0; i < 4; i++) {
6159 if (!(write_mask & (1<<i)))
6160 continue;
6161
6162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6163 alu.op = ALU_OP3_CNDGT_INT;
6164 alu.is_op3 = 1;
6165 alu.dst.write = 1;
6166
6167 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6168
6169 alu.src[0].sel = ctx->temp_reg;
6170 alu.src[0].chan = i;
6171
6172 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6173
6174 alu.src[2].sel = ctx->temp_reg;
6175 alu.src[2].chan = i;
6176
6177 if (i == last_inst)
6178 alu.last = 1;
6179 r = r600_bytecode_add_alu(ctx->bc, &alu);
6180 if (r)
6181 return r;
6182 }
6183 return 0;
6184 }
6185
6186
6187
6188 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6189 {
6190 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6191 struct r600_bytecode_alu alu;
6192 int i, r;
6193
6194 /* tmp = (src > 0 ? 1 : src) */
6195 for (i = 0; i < 4; i++) {
6196 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6197 alu.op = ALU_OP3_CNDGT;
6198 alu.is_op3 = 1;
6199
6200 alu.dst.sel = ctx->temp_reg;
6201 alu.dst.chan = i;
6202
6203 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6204 alu.src[1].sel = V_SQ_ALU_SRC_1;
6205 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6206
6207 if (i == 3)
6208 alu.last = 1;
6209 r = r600_bytecode_add_alu(ctx->bc, &alu);
6210 if (r)
6211 return r;
6212 }
6213
6214 /* dst = (-tmp > 0 ? -1 : tmp) */
6215 for (i = 0; i < 4; i++) {
6216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6217 alu.op = ALU_OP3_CNDGT;
6218 alu.is_op3 = 1;
6219 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6220
6221 alu.src[0].sel = ctx->temp_reg;
6222 alu.src[0].chan = i;
6223 alu.src[0].neg = 1;
6224
6225 alu.src[1].sel = V_SQ_ALU_SRC_1;
6226 alu.src[1].neg = 1;
6227
6228 alu.src[2].sel = ctx->temp_reg;
6229 alu.src[2].chan = i;
6230
6231 if (i == 3)
6232 alu.last = 1;
6233 r = r600_bytecode_add_alu(ctx->bc, &alu);
6234 if (r)
6235 return r;
6236 }
6237 return 0;
6238 }
6239
6240 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6241 {
6242 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6243 struct r600_bytecode_alu alu;
6244 int i, r, t1, t2;
6245
6246 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6247 int last_inst = tgsi_last_instruction(write_mask);
6248
6249 t1 = r600_get_temp(ctx);
6250
6251 for (i = 0; i < 4; i++) {
6252 if (!(write_mask & (1<<i)))
6253 continue;
6254
6255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6256 alu.op = ALU_OP2_SETGE_INT;
6257 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6258 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6259 alu.src[1].value = 32;
6260 alu.dst.sel = ctx->temp_reg;
6261 alu.dst.chan = i;
6262 alu.dst.write = 1;
6263 alu.last = i == last_inst;
6264 r = r600_bytecode_add_alu(ctx->bc, &alu);
6265 if (r)
6266 return r;
6267 }
6268
6269 for (i = 0; i < 4; i++) {
6270 if (!(write_mask & (1<<i)))
6271 continue;
6272
6273 /* create mask tmp */
6274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6275 alu.op = ALU_OP2_BFM_INT;
6276 alu.dst.sel = t1;
6277 alu.dst.chan = i;
6278 alu.dst.write = 1;
6279 alu.last = i == last_inst;
6280
6281 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6282 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6283
6284 r = r600_bytecode_add_alu(ctx->bc, &alu);
6285 if (r)
6286 return r;
6287 }
6288
6289 t2 = r600_get_temp(ctx);
6290
6291 for (i = 0; i < 4; i++) {
6292 if (!(write_mask & (1<<i)))
6293 continue;
6294
6295 /* shift insert left */
6296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6297 alu.op = ALU_OP2_LSHL_INT;
6298 alu.dst.sel = t2;
6299 alu.dst.chan = i;
6300 alu.dst.write = 1;
6301 alu.last = i == last_inst;
6302
6303 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6304 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6305
6306 r = r600_bytecode_add_alu(ctx->bc, &alu);
6307 if (r)
6308 return r;
6309 }
6310
6311 for (i = 0; i < 4; i++) {
6312 if (!(write_mask & (1<<i)))
6313 continue;
6314
6315 /* actual bitfield insert */
6316 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6317 alu.op = ALU_OP3_BFI_INT;
6318 alu.is_op3 = 1;
6319 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6320 alu.dst.chan = i;
6321 alu.dst.write = 1;
6322 alu.last = i == last_inst;
6323
6324 alu.src[0].sel = t1;
6325 alu.src[0].chan = i;
6326 alu.src[1].sel = t2;
6327 alu.src[1].chan = i;
6328 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6329
6330 r = r600_bytecode_add_alu(ctx->bc, &alu);
6331 if (r)
6332 return r;
6333 }
6334
6335 for (i = 0; i < 4; i++) {
6336 if (!(write_mask & (1<<i)))
6337 continue;
6338 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6339 alu.op = ALU_OP3_CNDE_INT;
6340 alu.is_op3 = 1;
6341 alu.src[0].sel = ctx->temp_reg;
6342 alu.src[0].chan = i;
6343 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6344
6345 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6346
6347 alu.src[1].sel = alu.dst.sel;
6348 alu.src[1].chan = i;
6349
6350 alu.last = i == last_inst;
6351 r = r600_bytecode_add_alu(ctx->bc, &alu);
6352 if (r)
6353 return r;
6354 }
6355 return 0;
6356 }
6357
6358 static int tgsi_msb(struct r600_shader_ctx *ctx)
6359 {
6360 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6361 struct r600_bytecode_alu alu;
6362 int i, r, t1, t2;
6363
6364 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6365 int last_inst = tgsi_last_instruction(write_mask);
6366
6367 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6368 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6369
6370 t1 = ctx->temp_reg;
6371
6372 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6373 for (i = 0; i < 4; i++) {
6374 if (!(write_mask & (1<<i)))
6375 continue;
6376
6377 /* t1 = FFBH_INT / FFBH_UINT */
6378 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6379 alu.op = ctx->inst_info->op;
6380 alu.dst.sel = t1;
6381 alu.dst.chan = i;
6382 alu.dst.write = 1;
6383 alu.last = i == last_inst;
6384
6385 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6386
6387 r = r600_bytecode_add_alu(ctx->bc, &alu);
6388 if (r)
6389 return r;
6390 }
6391
6392 t2 = r600_get_temp(ctx);
6393
6394 for (i = 0; i < 4; i++) {
6395 if (!(write_mask & (1<<i)))
6396 continue;
6397
6398 /* t2 = 31 - t1 */
6399 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6400 alu.op = ALU_OP2_SUB_INT;
6401 alu.dst.sel = t2;
6402 alu.dst.chan = i;
6403 alu.dst.write = 1;
6404 alu.last = i == last_inst;
6405
6406 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6407 alu.src[0].value = 31;
6408 alu.src[1].sel = t1;
6409 alu.src[1].chan = i;
6410
6411 r = r600_bytecode_add_alu(ctx->bc, &alu);
6412 if (r)
6413 return r;
6414 }
6415
6416 for (i = 0; i < 4; i++) {
6417 if (!(write_mask & (1<<i)))
6418 continue;
6419
6420 /* result = t1 >= 0 ? t2 : t1 */
6421 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6422 alu.op = ALU_OP3_CNDGE_INT;
6423 alu.is_op3 = 1;
6424 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6425 alu.dst.chan = i;
6426 alu.dst.write = 1;
6427 alu.last = i == last_inst;
6428
6429 alu.src[0].sel = t1;
6430 alu.src[0].chan = i;
6431 alu.src[1].sel = t2;
6432 alu.src[1].chan = i;
6433 alu.src[2].sel = t1;
6434 alu.src[2].chan = i;
6435
6436 r = r600_bytecode_add_alu(ctx->bc, &alu);
6437 if (r)
6438 return r;
6439 }
6440
6441 return 0;
6442 }
6443
6444 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6445 {
6446 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6447 struct r600_bytecode_alu alu;
6448 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6449 unsigned location;
6450 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6451
6452 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6453
6454 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6455 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6456 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6457 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6458 }
6459 else {
6460 location = TGSI_INTERPOLATE_LOC_CENTROID;
6461 }
6462
6463 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6464 if (k < 0)
6465 k = 0;
6466 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6467 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6468
6469 /* NOTE: currently offset is not perspective correct */
6470 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6471 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6472 int sample_gpr = -1;
6473 int gradientsH, gradientsV;
6474 struct r600_bytecode_tex tex;
6475
6476 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6477 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6478 }
6479
6480 gradientsH = r600_get_temp(ctx);
6481 gradientsV = r600_get_temp(ctx);
6482 for (i = 0; i < 2; i++) {
6483 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6484 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6485 tex.src_gpr = interp_gpr;
6486 tex.src_sel_x = interp_base_chan + 0;
6487 tex.src_sel_y = interp_base_chan + 1;
6488 tex.src_sel_z = 0;
6489 tex.src_sel_w = 0;
6490 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6491 tex.dst_sel_x = 0;
6492 tex.dst_sel_y = 1;
6493 tex.dst_sel_z = 7;
6494 tex.dst_sel_w = 7;
6495 tex.inst_mod = 1; // Use per pixel gradient calculation
6496 tex.sampler_id = 0;
6497 tex.resource_id = tex.sampler_id;
6498 r = r600_bytecode_add_tex(ctx->bc, &tex);
6499 if (r)
6500 return r;
6501 }
6502
6503 for (i = 0; i < 2; i++) {
6504 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6505 alu.op = ALU_OP3_MULADD;
6506 alu.is_op3 = 1;
6507 alu.src[0].sel = gradientsH;
6508 alu.src[0].chan = i;
6509 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6510 alu.src[1].sel = sample_gpr;
6511 alu.src[1].chan = 2;
6512 }
6513 else {
6514 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6515 }
6516 alu.src[2].sel = interp_gpr;
6517 alu.src[2].chan = interp_base_chan + i;
6518 alu.dst.sel = ctx->temp_reg;
6519 alu.dst.chan = i;
6520 alu.last = i == 1;
6521
6522 r = r600_bytecode_add_alu(ctx->bc, &alu);
6523 if (r)
6524 return r;
6525 }
6526
6527 for (i = 0; i < 2; i++) {
6528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6529 alu.op = ALU_OP3_MULADD;
6530 alu.is_op3 = 1;
6531 alu.src[0].sel = gradientsV;
6532 alu.src[0].chan = i;
6533 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6534 alu.src[1].sel = sample_gpr;
6535 alu.src[1].chan = 3;
6536 }
6537 else {
6538 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6539 }
6540 alu.src[2].sel = ctx->temp_reg;
6541 alu.src[2].chan = i;
6542 alu.dst.sel = ctx->temp_reg;
6543 alu.dst.chan = i;
6544 alu.last = i == 1;
6545
6546 r = r600_bytecode_add_alu(ctx->bc, &alu);
6547 if (r)
6548 return r;
6549 }
6550 }
6551
6552 tmp = r600_get_temp(ctx);
6553 for (i = 0; i < 8; i++) {
6554 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6555 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6556
6557 alu.dst.sel = tmp;
6558 if ((i > 1 && i < 6)) {
6559 alu.dst.write = 1;
6560 }
6561 else {
6562 alu.dst.write = 0;
6563 }
6564 alu.dst.chan = i % 4;
6565
6566 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6567 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6568 alu.src[0].sel = ctx->temp_reg;
6569 alu.src[0].chan = 1 - (i % 2);
6570 } else {
6571 alu.src[0].sel = interp_gpr;
6572 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6573 }
6574 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6575 alu.src[1].chan = 0;
6576
6577 alu.last = i % 4 == 3;
6578 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6579
6580 r = r600_bytecode_add_alu(ctx->bc, &alu);
6581 if (r)
6582 return r;
6583 }
6584
6585 // INTERP can't swizzle dst
6586 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6587 for (i = 0; i <= lasti; i++) {
6588 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6589 continue;
6590
6591 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6592 alu.op = ALU_OP1_MOV;
6593 alu.src[0].sel = tmp;
6594 alu.src[0].chan = ctx->src[0].swizzle[i];
6595 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6596 alu.dst.write = 1;
6597 alu.last = i == lasti;
6598 r = r600_bytecode_add_alu(ctx->bc, &alu);
6599 if (r)
6600 return r;
6601 }
6602
6603 return 0;
6604 }
6605
6606
6607 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6608 {
6609 struct r600_bytecode_alu alu;
6610 int i, r;
6611
6612 for (i = 0; i < 4; i++) {
6613 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6614 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6615 alu.op = ALU_OP0_NOP;
6616 alu.dst.chan = i;
6617 } else {
6618 alu.op = ALU_OP1_MOV;
6619 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6620 alu.src[0].sel = ctx->temp_reg;
6621 alu.src[0].chan = i;
6622 }
6623 if (i == 3) {
6624 alu.last = 1;
6625 }
6626 r = r600_bytecode_add_alu(ctx->bc, &alu);
6627 if (r)
6628 return r;
6629 }
6630 return 0;
6631 }
6632
6633 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6634 unsigned temp, int chan,
6635 struct r600_bytecode_alu_src *bc_src,
6636 const struct r600_shader_src *shader_src)
6637 {
6638 struct r600_bytecode_alu alu;
6639 int r;
6640
6641 r600_bytecode_src(bc_src, shader_src, chan);
6642
6643 /* op3 operands don't support abs modifier */
6644 if (bc_src->abs) {
6645 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6646 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6647 alu.op = ALU_OP1_MOV;
6648 alu.dst.sel = temp;
6649 alu.dst.chan = chan;
6650 alu.dst.write = 1;
6651
6652 alu.src[0] = *bc_src;
6653 alu.last = true; // sufficient?
6654 r = r600_bytecode_add_alu(ctx->bc, &alu);
6655 if (r)
6656 return r;
6657
6658 memset(bc_src, 0, sizeof(*bc_src));
6659 bc_src->sel = temp;
6660 bc_src->chan = chan;
6661 }
6662 return 0;
6663 }
6664
6665 static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
6666 {
6667 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6668 struct r600_bytecode_alu alu;
6669 int i, j, r;
6670 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6671 int temp_regs[4];
6672 unsigned op = ctx->inst_info->op;
6673
6674 if (op == ALU_OP3_MULADD_IEEE &&
6675 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6676 op = ALU_OP3_MULADD;
6677
6678 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6679 temp_regs[j] = 0;
6680 if (ctx->src[j].abs)
6681 temp_regs[j] = r600_get_temp(ctx);
6682 }
6683 for (i = 0; i < lasti + 1; i++) {
6684 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6685 continue;
6686
6687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6688 alu.op = op;
6689 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6690 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6691 if (r)
6692 return r;
6693 }
6694
6695 if (dst == -1) {
6696 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6697 } else {
6698 alu.dst.sel = dst;
6699 }
6700 alu.dst.chan = i;
6701 alu.dst.write = 1;
6702 alu.is_op3 = 1;
6703 if (i == lasti) {
6704 alu.last = 1;
6705 }
6706 r = r600_bytecode_add_alu(ctx->bc, &alu);
6707 if (r)
6708 return r;
6709 }
6710 return 0;
6711 }
6712
6713 static int tgsi_op3(struct r600_shader_ctx *ctx)
6714 {
6715 return tgsi_op3_dst(ctx, -1);
6716 }
6717
6718 static int tgsi_dp(struct r600_shader_ctx *ctx)
6719 {
6720 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6721 struct r600_bytecode_alu alu;
6722 int i, j, r;
6723 unsigned op = ctx->inst_info->op;
6724 if (op == ALU_OP2_DOT4_IEEE &&
6725 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6726 op = ALU_OP2_DOT4;
6727
6728 for (i = 0; i < 4; i++) {
6729 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6730 alu.op = op;
6731 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6732 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6733 }
6734
6735 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6736 alu.dst.chan = i;
6737 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6738 /* handle some special cases */
6739 switch (inst->Instruction.Opcode) {
6740 case TGSI_OPCODE_DP2:
6741 if (i > 1) {
6742 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6743 alu.src[0].chan = alu.src[1].chan = 0;
6744 }
6745 break;
6746 case TGSI_OPCODE_DP3:
6747 if (i > 2) {
6748 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6749 alu.src[0].chan = alu.src[1].chan = 0;
6750 }
6751 break;
6752 default:
6753 break;
6754 }
6755 if (i == 3) {
6756 alu.last = 1;
6757 }
6758 r = r600_bytecode_add_alu(ctx->bc, &alu);
6759 if (r)
6760 return r;
6761 }
6762 return 0;
6763 }
6764
6765 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6766 unsigned index)
6767 {
6768 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6769 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6770 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6771 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6772 ctx->src[index].neg || ctx->src[index].abs ||
6773 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6774 }
6775
6776 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6777 unsigned index)
6778 {
6779 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6780 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6781 }
6782
6783 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6784 {
6785 struct r600_bytecode_vtx vtx;
6786 struct r600_bytecode_alu alu;
6787 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6788 int src_gpr, r, i;
6789 int id = tgsi_tex_get_src_gpr(ctx, 1);
6790
6791 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6792 if (src_requires_loading) {
6793 for (i = 0; i < 4; i++) {
6794 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6795 alu.op = ALU_OP1_MOV;
6796 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6797 alu.dst.sel = ctx->temp_reg;
6798 alu.dst.chan = i;
6799 if (i == 3)
6800 alu.last = 1;
6801 alu.dst.write = 1;
6802 r = r600_bytecode_add_alu(ctx->bc, &alu);
6803 if (r)
6804 return r;
6805 }
6806 src_gpr = ctx->temp_reg;
6807 }
6808
6809 memset(&vtx, 0, sizeof(vtx));
6810 vtx.op = FETCH_OP_VFETCH;
6811 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6812 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6813 vtx.src_gpr = src_gpr;
6814 vtx.mega_fetch_count = 16;
6815 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6816 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6817 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6818 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6819 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6820 vtx.use_const_fields = 1;
6821
6822 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6823 return r;
6824
6825 if (ctx->bc->chip_class >= EVERGREEN)
6826 return 0;
6827
6828 for (i = 0; i < 4; i++) {
6829 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6830 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6831 continue;
6832
6833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6834 alu.op = ALU_OP2_AND_INT;
6835
6836 alu.dst.chan = i;
6837 alu.dst.sel = vtx.dst_gpr;
6838 alu.dst.write = 1;
6839
6840 alu.src[0].sel = vtx.dst_gpr;
6841 alu.src[0].chan = i;
6842
6843 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6844 alu.src[1].sel += (id * 2);
6845 alu.src[1].chan = i % 4;
6846 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6847
6848 if (i == lasti)
6849 alu.last = 1;
6850 r = r600_bytecode_add_alu(ctx->bc, &alu);
6851 if (r)
6852 return r;
6853 }
6854
6855 if (inst->Dst[0].Register.WriteMask & 3) {
6856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6857 alu.op = ALU_OP2_OR_INT;
6858
6859 alu.dst.chan = 3;
6860 alu.dst.sel = vtx.dst_gpr;
6861 alu.dst.write = 1;
6862
6863 alu.src[0].sel = vtx.dst_gpr;
6864 alu.src[0].chan = 3;
6865
6866 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6867 alu.src[1].chan = 0;
6868 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6869
6870 alu.last = 1;
6871 r = r600_bytecode_add_alu(ctx->bc, &alu);
6872 if (r)
6873 return r;
6874 }
6875 return 0;
6876 }
6877
6878 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset)
6879 {
6880 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6881 struct r600_bytecode_alu alu;
6882 int r;
6883 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
6884
6885 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6886 alu.op = ALU_OP1_MOV;
6887 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6888 if (ctx->bc->chip_class >= EVERGREEN) {
6889 /* channel 0 or 2 of each word */
6890 alu.src[0].sel += (id / 2);
6891 alu.src[0].chan = (id % 2) * 2;
6892 } else {
6893 /* r600 we have them at channel 2 of the second dword */
6894 alu.src[0].sel += (id * 2) + 1;
6895 alu.src[0].chan = 1;
6896 }
6897 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6898 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6899 alu.last = 1;
6900 r = r600_bytecode_add_alu(ctx->bc, &alu);
6901 if (r)
6902 return r;
6903 return 0;
6904 }
6905
6906 static int tgsi_tex(struct r600_shader_ctx *ctx)
6907 {
6908 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6909 struct r600_bytecode_tex tex;
6910 struct r600_bytecode_alu alu;
6911 unsigned src_gpr;
6912 int r, i, j;
6913 int opcode;
6914 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6915 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6916 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6917 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6918
6919 bool txf_add_offsets = inst->Texture.NumOffsets &&
6920 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6921 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6922
6923 /* Texture fetch instructions can only use gprs as source.
6924 * Also they cannot negate the source or take the absolute value */
6925 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6926 tgsi_tex_src_requires_loading(ctx, 0)) ||
6927 read_compressed_msaa || txf_add_offsets;
6928
6929 boolean src_loaded = FALSE;
6930 unsigned sampler_src_reg = 1;
6931 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6932 boolean has_txq_cube_array_z = false;
6933 unsigned sampler_index_mode;
6934
6935 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6936 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6937 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6938 if (inst->Dst[0].Register.WriteMask & 4) {
6939 ctx->shader->has_txq_cube_array_z_comp = true;
6940 has_txq_cube_array_z = true;
6941 }
6942
6943 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6944 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6945 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6946 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6947 sampler_src_reg = 2;
6948
6949 /* TGSI moves the sampler to src reg 3 for TXD */
6950 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6951 sampler_src_reg = 3;
6952
6953 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6954
6955 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6956
6957 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6958 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6959 ctx->shader->uses_tex_buffers = true;
6960 return r600_do_buffer_txq(ctx, 1, 0);
6961 }
6962 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6963 if (ctx->bc->chip_class < EVERGREEN)
6964 ctx->shader->uses_tex_buffers = true;
6965 return do_vtx_fetch_inst(ctx, src_requires_loading);
6966 }
6967 }
6968
6969 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6970 int out_chan;
6971 /* Add perspective divide */
6972 if (ctx->bc->chip_class == CAYMAN) {
6973 out_chan = 2;
6974 for (i = 0; i < 3; i++) {
6975 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6976 alu.op = ALU_OP1_RECIP_IEEE;
6977 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6978
6979 alu.dst.sel = ctx->temp_reg;
6980 alu.dst.chan = i;
6981 if (i == 2)
6982 alu.last = 1;
6983 if (out_chan == i)
6984 alu.dst.write = 1;
6985 r = r600_bytecode_add_alu(ctx->bc, &alu);
6986 if (r)
6987 return r;
6988 }
6989
6990 } else {
6991 out_chan = 3;
6992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6993 alu.op = ALU_OP1_RECIP_IEEE;
6994 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6995
6996 alu.dst.sel = ctx->temp_reg;
6997 alu.dst.chan = out_chan;
6998 alu.last = 1;
6999 alu.dst.write = 1;
7000 r = r600_bytecode_add_alu(ctx->bc, &alu);
7001 if (r)
7002 return r;
7003 }
7004
7005 for (i = 0; i < 3; i++) {
7006 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7007 alu.op = ALU_OP2_MUL;
7008 alu.src[0].sel = ctx->temp_reg;
7009 alu.src[0].chan = out_chan;
7010 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7011 alu.dst.sel = ctx->temp_reg;
7012 alu.dst.chan = i;
7013 alu.dst.write = 1;
7014 r = r600_bytecode_add_alu(ctx->bc, &alu);
7015 if (r)
7016 return r;
7017 }
7018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7019 alu.op = ALU_OP1_MOV;
7020 alu.src[0].sel = V_SQ_ALU_SRC_1;
7021 alu.src[0].chan = 0;
7022 alu.dst.sel = ctx->temp_reg;
7023 alu.dst.chan = 3;
7024 alu.last = 1;
7025 alu.dst.write = 1;
7026 r = r600_bytecode_add_alu(ctx->bc, &alu);
7027 if (r)
7028 return r;
7029 src_loaded = TRUE;
7030 src_gpr = ctx->temp_reg;
7031 }
7032
7033
7034 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7035 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7036 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7037 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7038 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
7039
7040 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
7041 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
7042
7043 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7044 for (i = 0; i < 4; i++) {
7045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7046 alu.op = ALU_OP2_CUBE;
7047 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7048 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
7049 alu.dst.sel = ctx->temp_reg;
7050 alu.dst.chan = i;
7051 if (i == 3)
7052 alu.last = 1;
7053 alu.dst.write = 1;
7054 r = r600_bytecode_add_alu(ctx->bc, &alu);
7055 if (r)
7056 return r;
7057 }
7058
7059 /* tmp1.z = RCP_e(|tmp1.z|) */
7060 if (ctx->bc->chip_class == CAYMAN) {
7061 for (i = 0; i < 3; i++) {
7062 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7063 alu.op = ALU_OP1_RECIP_IEEE;
7064 alu.src[0].sel = ctx->temp_reg;
7065 alu.src[0].chan = 2;
7066 alu.src[0].abs = 1;
7067 alu.dst.sel = ctx->temp_reg;
7068 alu.dst.chan = i;
7069 if (i == 2)
7070 alu.dst.write = 1;
7071 if (i == 2)
7072 alu.last = 1;
7073 r = r600_bytecode_add_alu(ctx->bc, &alu);
7074 if (r)
7075 return r;
7076 }
7077 } else {
7078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7079 alu.op = ALU_OP1_RECIP_IEEE;
7080 alu.src[0].sel = ctx->temp_reg;
7081 alu.src[0].chan = 2;
7082 alu.src[0].abs = 1;
7083 alu.dst.sel = ctx->temp_reg;
7084 alu.dst.chan = 2;
7085 alu.dst.write = 1;
7086 alu.last = 1;
7087 r = r600_bytecode_add_alu(ctx->bc, &alu);
7088 if (r)
7089 return r;
7090 }
7091
7092 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7093 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7094 * muladd has no writemask, have to use another temp
7095 */
7096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7097 alu.op = ALU_OP3_MULADD;
7098 alu.is_op3 = 1;
7099
7100 alu.src[0].sel = ctx->temp_reg;
7101 alu.src[0].chan = 0;
7102 alu.src[1].sel = ctx->temp_reg;
7103 alu.src[1].chan = 2;
7104
7105 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7106 alu.src[2].chan = 0;
7107 alu.src[2].value = u_bitcast_f2u(1.5f);
7108
7109 alu.dst.sel = ctx->temp_reg;
7110 alu.dst.chan = 0;
7111 alu.dst.write = 1;
7112
7113 r = r600_bytecode_add_alu(ctx->bc, &alu);
7114 if (r)
7115 return r;
7116
7117 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7118 alu.op = ALU_OP3_MULADD;
7119 alu.is_op3 = 1;
7120
7121 alu.src[0].sel = ctx->temp_reg;
7122 alu.src[0].chan = 1;
7123 alu.src[1].sel = ctx->temp_reg;
7124 alu.src[1].chan = 2;
7125
7126 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7127 alu.src[2].chan = 0;
7128 alu.src[2].value = u_bitcast_f2u(1.5f);
7129
7130 alu.dst.sel = ctx->temp_reg;
7131 alu.dst.chan = 1;
7132 alu.dst.write = 1;
7133
7134 alu.last = 1;
7135 r = r600_bytecode_add_alu(ctx->bc, &alu);
7136 if (r)
7137 return r;
7138 /* write initial compare value into Z component
7139 - W src 0 for shadow cube
7140 - X src 1 for shadow cube array */
7141 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7142 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7144 alu.op = ALU_OP1_MOV;
7145 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7146 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7147 else
7148 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7149 alu.dst.sel = ctx->temp_reg;
7150 alu.dst.chan = 2;
7151 alu.dst.write = 1;
7152 alu.last = 1;
7153 r = r600_bytecode_add_alu(ctx->bc, &alu);
7154 if (r)
7155 return r;
7156 }
7157
7158 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7159 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7160 if (ctx->bc->chip_class >= EVERGREEN) {
7161 int mytmp = r600_get_temp(ctx);
7162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7163 alu.op = ALU_OP1_MOV;
7164 alu.src[0].sel = ctx->temp_reg;
7165 alu.src[0].chan = 3;
7166 alu.dst.sel = mytmp;
7167 alu.dst.chan = 0;
7168 alu.dst.write = 1;
7169 alu.last = 1;
7170 r = r600_bytecode_add_alu(ctx->bc, &alu);
7171 if (r)
7172 return r;
7173
7174 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7176 alu.op = ALU_OP3_MULADD;
7177 alu.is_op3 = 1;
7178 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7179 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7180 alu.src[1].chan = 0;
7181 alu.src[1].value = u_bitcast_f2u(8.0f);
7182 alu.src[2].sel = mytmp;
7183 alu.src[2].chan = 0;
7184 alu.dst.sel = ctx->temp_reg;
7185 alu.dst.chan = 3;
7186 alu.dst.write = 1;
7187 alu.last = 1;
7188 r = r600_bytecode_add_alu(ctx->bc, &alu);
7189 if (r)
7190 return r;
7191 } else if (ctx->bc->chip_class < EVERGREEN) {
7192 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7193 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7194 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7195 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7196 tex.src_gpr = r600_get_temp(ctx);
7197 tex.src_sel_x = 0;
7198 tex.src_sel_y = 0;
7199 tex.src_sel_z = 0;
7200 tex.src_sel_w = 0;
7201 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7202 tex.coord_type_x = 1;
7203 tex.coord_type_y = 1;
7204 tex.coord_type_z = 1;
7205 tex.coord_type_w = 1;
7206 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7207 alu.op = ALU_OP1_MOV;
7208 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7209 alu.dst.sel = tex.src_gpr;
7210 alu.dst.chan = 0;
7211 alu.last = 1;
7212 alu.dst.write = 1;
7213 r = r600_bytecode_add_alu(ctx->bc, &alu);
7214 if (r)
7215 return r;
7216
7217 r = r600_bytecode_add_tex(ctx->bc, &tex);
7218 if (r)
7219 return r;
7220 }
7221
7222 }
7223
7224 /* for cube forms of lod and bias we need to route things */
7225 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7226 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7227 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7228 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7229 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7230 alu.op = ALU_OP1_MOV;
7231 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7232 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7233 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7234 else
7235 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7236 alu.dst.sel = ctx->temp_reg;
7237 alu.dst.chan = 2;
7238 alu.last = 1;
7239 alu.dst.write = 1;
7240 r = r600_bytecode_add_alu(ctx->bc, &alu);
7241 if (r)
7242 return r;
7243 }
7244
7245 src_loaded = TRUE;
7246 src_gpr = ctx->temp_reg;
7247 }
7248
7249 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7250 int temp_h = 0, temp_v = 0;
7251 int start_val = 0;
7252
7253 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7254 if (src_loaded == TRUE)
7255 start_val = 1;
7256 else
7257 src_loaded = TRUE;
7258 for (i = start_val; i < 3; i++) {
7259 int treg = r600_get_temp(ctx);
7260
7261 if (i == 0)
7262 src_gpr = treg;
7263 else if (i == 1)
7264 temp_h = treg;
7265 else
7266 temp_v = treg;
7267
7268 for (j = 0; j < 4; j++) {
7269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7270 alu.op = ALU_OP1_MOV;
7271 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7272 alu.dst.sel = treg;
7273 alu.dst.chan = j;
7274 if (j == 3)
7275 alu.last = 1;
7276 alu.dst.write = 1;
7277 r = r600_bytecode_add_alu(ctx->bc, &alu);
7278 if (r)
7279 return r;
7280 }
7281 }
7282 for (i = 1; i < 3; i++) {
7283 /* set gradients h/v */
7284 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7285 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7286 FETCH_OP_SET_GRADIENTS_V;
7287 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7288 tex.sampler_index_mode = sampler_index_mode;
7289 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7290 tex.resource_index_mode = sampler_index_mode;
7291
7292 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7293 tex.src_sel_x = 0;
7294 tex.src_sel_y = 1;
7295 tex.src_sel_z = 2;
7296 tex.src_sel_w = 3;
7297
7298 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7299 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7300 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7301 tex.coord_type_x = 1;
7302 tex.coord_type_y = 1;
7303 tex.coord_type_z = 1;
7304 tex.coord_type_w = 1;
7305 }
7306 r = r600_bytecode_add_tex(ctx->bc, &tex);
7307 if (r)
7308 return r;
7309 }
7310 }
7311
7312 if (src_requires_loading && !src_loaded) {
7313 for (i = 0; i < 4; i++) {
7314 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7315 alu.op = ALU_OP1_MOV;
7316 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7317 alu.dst.sel = ctx->temp_reg;
7318 alu.dst.chan = i;
7319 if (i == 3)
7320 alu.last = 1;
7321 alu.dst.write = 1;
7322 r = r600_bytecode_add_alu(ctx->bc, &alu);
7323 if (r)
7324 return r;
7325 }
7326 src_loaded = TRUE;
7327 src_gpr = ctx->temp_reg;
7328 }
7329
7330 /* get offset values */
7331 if (inst->Texture.NumOffsets) {
7332 assert(inst->Texture.NumOffsets == 1);
7333
7334 /* The texture offset feature doesn't work with the TXF instruction
7335 * and must be emulated by adding the offset to the texture coordinates. */
7336 if (txf_add_offsets) {
7337 const struct tgsi_texture_offset *off = inst->TexOffsets;
7338
7339 switch (inst->Texture.Texture) {
7340 case TGSI_TEXTURE_3D:
7341 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7342 alu.op = ALU_OP2_ADD_INT;
7343 alu.src[0].sel = src_gpr;
7344 alu.src[0].chan = 2;
7345 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7346 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7347 alu.dst.sel = src_gpr;
7348 alu.dst.chan = 2;
7349 alu.dst.write = 1;
7350 alu.last = 1;
7351 r = r600_bytecode_add_alu(ctx->bc, &alu);
7352 if (r)
7353 return r;
7354 /* fall through */
7355
7356 case TGSI_TEXTURE_2D:
7357 case TGSI_TEXTURE_SHADOW2D:
7358 case TGSI_TEXTURE_RECT:
7359 case TGSI_TEXTURE_SHADOWRECT:
7360 case TGSI_TEXTURE_2D_ARRAY:
7361 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7363 alu.op = ALU_OP2_ADD_INT;
7364 alu.src[0].sel = src_gpr;
7365 alu.src[0].chan = 1;
7366 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7367 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7368 alu.dst.sel = src_gpr;
7369 alu.dst.chan = 1;
7370 alu.dst.write = 1;
7371 alu.last = 1;
7372 r = r600_bytecode_add_alu(ctx->bc, &alu);
7373 if (r)
7374 return r;
7375 /* fall through */
7376
7377 case TGSI_TEXTURE_1D:
7378 case TGSI_TEXTURE_SHADOW1D:
7379 case TGSI_TEXTURE_1D_ARRAY:
7380 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7381 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7382 alu.op = ALU_OP2_ADD_INT;
7383 alu.src[0].sel = src_gpr;
7384 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7385 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7386 alu.dst.sel = src_gpr;
7387 alu.dst.write = 1;
7388 alu.last = 1;
7389 r = r600_bytecode_add_alu(ctx->bc, &alu);
7390 if (r)
7391 return r;
7392 break;
7393 /* texture offsets do not apply to other texture targets */
7394 }
7395 } else {
7396 switch (inst->Texture.Texture) {
7397 case TGSI_TEXTURE_3D:
7398 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7399 /* fallthrough */
7400 case TGSI_TEXTURE_2D:
7401 case TGSI_TEXTURE_SHADOW2D:
7402 case TGSI_TEXTURE_RECT:
7403 case TGSI_TEXTURE_SHADOWRECT:
7404 case TGSI_TEXTURE_2D_ARRAY:
7405 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7406 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7407 /* fallthrough */
7408 case TGSI_TEXTURE_1D:
7409 case TGSI_TEXTURE_SHADOW1D:
7410 case TGSI_TEXTURE_1D_ARRAY:
7411 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7412 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7413 }
7414 }
7415 }
7416
7417 /* Obtain the sample index for reading a compressed MSAA color texture.
7418 * To read the FMASK, we use the ldfptr instruction, which tells us
7419 * where the samples are stored.
7420 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7421 * which is the identity mapping. Each nibble says which physical sample
7422 * should be fetched to get that sample.
7423 *
7424 * Assume src.z contains the sample index. It should be modified like this:
7425 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7426 * Then fetch the texel with src.
7427 */
7428 if (read_compressed_msaa) {
7429 unsigned sample_chan = 3;
7430 unsigned temp = r600_get_temp(ctx);
7431 assert(src_loaded);
7432
7433 /* temp.w = ldfptr() */
7434 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7435 tex.op = FETCH_OP_LD;
7436 tex.inst_mod = 1; /* to indicate this is ldfptr */
7437 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7438 tex.sampler_index_mode = sampler_index_mode;
7439 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7440 tex.resource_index_mode = sampler_index_mode;
7441 tex.src_gpr = src_gpr;
7442 tex.dst_gpr = temp;
7443 tex.dst_sel_x = 7; /* mask out these components */
7444 tex.dst_sel_y = 7;
7445 tex.dst_sel_z = 7;
7446 tex.dst_sel_w = 0; /* store X */
7447 tex.src_sel_x = 0;
7448 tex.src_sel_y = 1;
7449 tex.src_sel_z = 2;
7450 tex.src_sel_w = 3;
7451 tex.offset_x = offset_x;
7452 tex.offset_y = offset_y;
7453 tex.offset_z = offset_z;
7454 r = r600_bytecode_add_tex(ctx->bc, &tex);
7455 if (r)
7456 return r;
7457
7458 /* temp.x = sample_index*4 */
7459 if (ctx->bc->chip_class == CAYMAN) {
7460 for (i = 0 ; i < 4; i++) {
7461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7462 alu.op = ALU_OP2_MULLO_INT;
7463 alu.src[0].sel = src_gpr;
7464 alu.src[0].chan = sample_chan;
7465 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7466 alu.src[1].value = 4;
7467 alu.dst.sel = temp;
7468 alu.dst.chan = i;
7469 alu.dst.write = i == 0;
7470 if (i == 3)
7471 alu.last = 1;
7472 r = r600_bytecode_add_alu(ctx->bc, &alu);
7473 if (r)
7474 return r;
7475 }
7476 } else {
7477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7478 alu.op = ALU_OP2_MULLO_INT;
7479 alu.src[0].sel = src_gpr;
7480 alu.src[0].chan = sample_chan;
7481 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7482 alu.src[1].value = 4;
7483 alu.dst.sel = temp;
7484 alu.dst.chan = 0;
7485 alu.dst.write = 1;
7486 alu.last = 1;
7487 r = r600_bytecode_add_alu(ctx->bc, &alu);
7488 if (r)
7489 return r;
7490 }
7491
7492 /* sample_index = temp.w >> temp.x */
7493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7494 alu.op = ALU_OP2_LSHR_INT;
7495 alu.src[0].sel = temp;
7496 alu.src[0].chan = 3;
7497 alu.src[1].sel = temp;
7498 alu.src[1].chan = 0;
7499 alu.dst.sel = src_gpr;
7500 alu.dst.chan = sample_chan;
7501 alu.dst.write = 1;
7502 alu.last = 1;
7503 r = r600_bytecode_add_alu(ctx->bc, &alu);
7504 if (r)
7505 return r;
7506
7507 /* sample_index & 0xF */
7508 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7509 alu.op = ALU_OP2_AND_INT;
7510 alu.src[0].sel = src_gpr;
7511 alu.src[0].chan = sample_chan;
7512 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7513 alu.src[1].value = 0xF;
7514 alu.dst.sel = src_gpr;
7515 alu.dst.chan = sample_chan;
7516 alu.dst.write = 1;
7517 alu.last = 1;
7518 r = r600_bytecode_add_alu(ctx->bc, &alu);
7519 if (r)
7520 return r;
7521 #if 0
7522 /* visualize the FMASK */
7523 for (i = 0; i < 4; i++) {
7524 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7525 alu.op = ALU_OP1_INT_TO_FLT;
7526 alu.src[0].sel = src_gpr;
7527 alu.src[0].chan = sample_chan;
7528 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7529 alu.dst.chan = i;
7530 alu.dst.write = 1;
7531 alu.last = 1;
7532 r = r600_bytecode_add_alu(ctx->bc, &alu);
7533 if (r)
7534 return r;
7535 }
7536 return 0;
7537 #endif
7538 }
7539
7540 /* does this shader want a num layers from TXQ for a cube array? */
7541 if (has_txq_cube_array_z) {
7542 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7543
7544 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7545 alu.op = ALU_OP1_MOV;
7546
7547 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7548 if (ctx->bc->chip_class >= EVERGREEN) {
7549 /* channel 1 or 3 of each word */
7550 alu.src[0].sel += (id / 2);
7551 alu.src[0].chan = ((id % 2) * 2) + 1;
7552 } else {
7553 /* r600 we have them at channel 2 of the second dword */
7554 alu.src[0].sel += (id * 2) + 1;
7555 alu.src[0].chan = 2;
7556 }
7557 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7558 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7559 alu.last = 1;
7560 r = r600_bytecode_add_alu(ctx->bc, &alu);
7561 if (r)
7562 return r;
7563 /* disable writemask from texture instruction */
7564 inst->Dst[0].Register.WriteMask &= ~4;
7565 }
7566
7567 opcode = ctx->inst_info->op;
7568 if (opcode == FETCH_OP_GATHER4 &&
7569 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7570 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7571 opcode = FETCH_OP_GATHER4_O;
7572
7573 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7574 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7575 encoded in the instruction are ignored. */
7576 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7577 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7578 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7579 tex.sampler_index_mode = sampler_index_mode;
7580 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7581 tex.resource_index_mode = sampler_index_mode;
7582
7583 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7584 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7585 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7586 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7587 tex.src_sel_w = 4;
7588
7589 tex.dst_sel_x = 7;
7590 tex.dst_sel_y = 7;
7591 tex.dst_sel_z = 7;
7592 tex.dst_sel_w = 7;
7593
7594 r = r600_bytecode_add_tex(ctx->bc, &tex);
7595 if (r)
7596 return r;
7597 }
7598
7599 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7600 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7601 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7602 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7603 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7604 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7605 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7606 switch (opcode) {
7607 case FETCH_OP_SAMPLE:
7608 opcode = FETCH_OP_SAMPLE_C;
7609 break;
7610 case FETCH_OP_SAMPLE_L:
7611 opcode = FETCH_OP_SAMPLE_C_L;
7612 break;
7613 case FETCH_OP_SAMPLE_LB:
7614 opcode = FETCH_OP_SAMPLE_C_LB;
7615 break;
7616 case FETCH_OP_SAMPLE_G:
7617 opcode = FETCH_OP_SAMPLE_C_G;
7618 break;
7619 /* Texture gather variants */
7620 case FETCH_OP_GATHER4:
7621 opcode = FETCH_OP_GATHER4_C;
7622 break;
7623 case FETCH_OP_GATHER4_O:
7624 opcode = FETCH_OP_GATHER4_C_O;
7625 break;
7626 }
7627 }
7628
7629 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7630 tex.op = opcode;
7631
7632 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7633 tex.sampler_index_mode = sampler_index_mode;
7634 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7635 tex.resource_index_mode = sampler_index_mode;
7636 tex.src_gpr = src_gpr;
7637 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7638
7639 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7640 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7641 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7642 }
7643
7644 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7645 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7646 tex.inst_mod = texture_component_select;
7647
7648 if (ctx->bc->chip_class == CAYMAN) {
7649 /* GATHER4 result order is different from TGSI TG4 */
7650 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7651 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7652 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7653 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7654 } else {
7655 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7656 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7657 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7658 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7659 }
7660 }
7661 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7662 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7663 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7664 tex.dst_sel_z = 7;
7665 tex.dst_sel_w = 7;
7666 }
7667 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7668 tex.dst_sel_x = 3;
7669 tex.dst_sel_y = 7;
7670 tex.dst_sel_z = 7;
7671 tex.dst_sel_w = 7;
7672 }
7673 else {
7674 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7675 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7676 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7677 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7678 }
7679
7680
7681 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7682 tex.src_sel_x = 4;
7683 tex.src_sel_y = 4;
7684 tex.src_sel_z = 4;
7685 tex.src_sel_w = 4;
7686 } else if (src_loaded) {
7687 tex.src_sel_x = 0;
7688 tex.src_sel_y = 1;
7689 tex.src_sel_z = 2;
7690 tex.src_sel_w = 3;
7691 } else {
7692 tex.src_sel_x = ctx->src[0].swizzle[0];
7693 tex.src_sel_y = ctx->src[0].swizzle[1];
7694 tex.src_sel_z = ctx->src[0].swizzle[2];
7695 tex.src_sel_w = ctx->src[0].swizzle[3];
7696 tex.src_rel = ctx->src[0].rel;
7697 }
7698
7699 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7700 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7701 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7702 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7703 tex.src_sel_x = 1;
7704 tex.src_sel_y = 0;
7705 tex.src_sel_z = 3;
7706 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7707 }
7708
7709 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7710 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7711 tex.coord_type_x = 1;
7712 tex.coord_type_y = 1;
7713 }
7714 tex.coord_type_z = 1;
7715 tex.coord_type_w = 1;
7716
7717 tex.offset_x = offset_x;
7718 tex.offset_y = offset_y;
7719 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7720 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7721 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7722 tex.offset_z = 0;
7723 }
7724 else {
7725 tex.offset_z = offset_z;
7726 }
7727
7728 /* Put the depth for comparison in W.
7729 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7730 * Some instructions expect the depth in Z. */
7731 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7732 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7733 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7734 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7735 opcode != FETCH_OP_SAMPLE_C_L &&
7736 opcode != FETCH_OP_SAMPLE_C_LB) {
7737 tex.src_sel_w = tex.src_sel_z;
7738 }
7739
7740 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7741 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7742 if (opcode == FETCH_OP_SAMPLE_C_L ||
7743 opcode == FETCH_OP_SAMPLE_C_LB) {
7744 /* the array index is read from Y */
7745 tex.coord_type_y = 0;
7746 } else {
7747 /* the array index is read from Z */
7748 tex.coord_type_z = 0;
7749 tex.src_sel_z = tex.src_sel_y;
7750 }
7751 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7752 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7753 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7754 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7755 (ctx->bc->chip_class >= EVERGREEN)))
7756 /* the array index is read from Z */
7757 tex.coord_type_z = 0;
7758
7759 /* mask unused source components */
7760 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7761 switch (inst->Texture.Texture) {
7762 case TGSI_TEXTURE_2D:
7763 case TGSI_TEXTURE_RECT:
7764 tex.src_sel_z = 7;
7765 tex.src_sel_w = 7;
7766 break;
7767 case TGSI_TEXTURE_1D_ARRAY:
7768 tex.src_sel_y = 7;
7769 tex.src_sel_w = 7;
7770 break;
7771 case TGSI_TEXTURE_1D:
7772 tex.src_sel_y = 7;
7773 tex.src_sel_z = 7;
7774 tex.src_sel_w = 7;
7775 break;
7776 }
7777 }
7778
7779 r = r600_bytecode_add_tex(ctx->bc, &tex);
7780 if (r)
7781 return r;
7782
7783 /* add shadow ambient support - gallium doesn't do it yet */
7784 return 0;
7785 }
7786
7787 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7788 struct tgsi_full_src_register *src)
7789 {
7790 unsigned i;
7791
7792 if (src->Register.Indirect) {
7793 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7794 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7795 return ctx->shader->atomics[i].hw_idx;
7796 }
7797 } else {
7798 uint32_t index = src->Register.Index;
7799 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7800 if (ctx->shader->atomics[i].buffer_id != (unsigned)src->Dimension.Index)
7801 continue;
7802 if (index > ctx->shader->atomics[i].end)
7803 continue;
7804 if (index < ctx->shader->atomics[i].start)
7805 continue;
7806 uint32_t offset = (index - ctx->shader->atomics[i].start);
7807 return ctx->shader->atomics[i].hw_idx + offset;
7808 }
7809 }
7810 assert(0);
7811 return -1;
7812 }
7813
7814 static int tgsi_set_gds_temp(struct r600_shader_ctx *ctx,
7815 int *uav_id_p, int *uav_index_mode_p)
7816 {
7817 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7818 int uav_id, uav_index_mode;
7819 int r;
7820 bool is_cm = (ctx->bc->chip_class == CAYMAN);
7821
7822 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7823
7824 if (inst->Src[0].Register.Indirect) {
7825 if (is_cm) {
7826 struct r600_bytecode_alu alu;
7827 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7828 alu.op = ALU_OP2_LSHL_INT;
7829 alu.src[0].sel = get_address_file_reg(ctx, inst->Src[0].Indirect.Index);
7830 alu.src[0].chan = 0;
7831 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7832 alu.src[1].value = 2;
7833 alu.dst.sel = ctx->temp_reg;
7834 alu.dst.chan = 0;
7835 alu.dst.write = 1;
7836 alu.last = 1;
7837 r = r600_bytecode_add_alu(ctx->bc, &alu);
7838 if (r)
7839 return r;
7840
7841 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
7842 ctx->temp_reg, 0,
7843 ctx->temp_reg, 0,
7844 V_SQ_ALU_SRC_LITERAL, uav_id * 4);
7845 if (r)
7846 return r;
7847 } else
7848 uav_index_mode = 2;
7849 } else if (is_cm) {
7850 r = single_alu_op2(ctx, ALU_OP1_MOV,
7851 ctx->temp_reg, 0,
7852 V_SQ_ALU_SRC_LITERAL, uav_id * 4,
7853 0, 0);
7854 if (r)
7855 return r;
7856 }
7857 *uav_id_p = uav_id;
7858 *uav_index_mode_p = uav_index_mode;
7859 return 0;
7860 }
7861
7862 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7863 {
7864 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7865 int r;
7866 struct r600_bytecode_gds gds;
7867 int uav_id = 0;
7868 int uav_index_mode = 0;
7869 bool is_cm = (ctx->bc->chip_class == CAYMAN);
7870
7871 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
7872 if (r)
7873 return r;
7874
7875 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7876 gds.op = FETCH_OP_GDS_READ_RET;
7877 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7878 gds.uav_id = is_cm ? 0 : uav_id;
7879 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
7880 gds.src_gpr = ctx->temp_reg;
7881 gds.src_sel_x = (is_cm) ? 0 : 4;
7882 gds.src_sel_y = 4;
7883 gds.src_sel_z = 4;
7884 gds.dst_sel_x = 0;
7885 gds.dst_sel_y = 7;
7886 gds.dst_sel_z = 7;
7887 gds.dst_sel_w = 7;
7888 gds.src_gpr2 = 0;
7889 gds.alloc_consume = !is_cm;
7890 r = r600_bytecode_add_gds(ctx->bc, &gds);
7891 if (r)
7892 return r;
7893
7894 ctx->bc->cf_last->vpm = 1;
7895 return 0;
7896 }
7897
7898 /* this fixes up 1D arrays properly */
7899 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
7900 {
7901 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7902 int r, i;
7903 struct r600_bytecode_alu alu;
7904 int temp_reg = r600_get_temp(ctx);
7905
7906 for (i = 0; i < 4; i++) {
7907 bool def_val = true, write_zero = false;
7908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7909 alu.op = ALU_OP1_MOV;
7910 alu.dst.sel = temp_reg;
7911 alu.dst.chan = i;
7912
7913 switch (inst->Memory.Texture) {
7914 case TGSI_TEXTURE_BUFFER:
7915 case TGSI_TEXTURE_1D:
7916 if (i == 1 || i == 2 || i == 3) {
7917 write_zero = true;
7918 }
7919 break;
7920 case TGSI_TEXTURE_1D_ARRAY:
7921 if (i == 1 || i == 3)
7922 write_zero = true;
7923 else if (i == 2) {
7924 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
7925 def_val = false;
7926 }
7927 break;
7928 case TGSI_TEXTURE_2D:
7929 if (i == 2 || i == 3)
7930 write_zero = true;
7931 break;
7932 default:
7933 if (i == 3)
7934 write_zero = true;
7935 break;
7936 }
7937
7938 if (write_zero) {
7939 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
7940 alu.src[0].value = 0;
7941 } else if (def_val) {
7942 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
7943 }
7944
7945 if (i == 3)
7946 alu.last = 1;
7947 alu.dst.write = 1;
7948 r = r600_bytecode_add_alu(ctx->bc, &alu);
7949 if (r)
7950 return r;
7951 }
7952 *idx_gpr = temp_reg;
7953 return 0;
7954 }
7955
7956 static int load_buffer_coord(struct r600_shader_ctx *ctx, int src_idx,
7957 int temp_reg)
7958 {
7959 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7960 int r;
7961 if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
7962 int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
7963 r = single_alu_op2(ctx, ALU_OP1_MOV,
7964 temp_reg, 0,
7965 V_SQ_ALU_SRC_LITERAL, value >> 2,
7966 0, 0);
7967 if (r)
7968 return r;
7969 } else {
7970 struct r600_bytecode_alu alu;
7971 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7972 alu.op = ALU_OP2_LSHR_INT;
7973 r600_bytecode_src(&alu.src[0], &ctx->src[src_idx], 0);
7974 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7975 alu.src[1].value = 2;
7976 alu.dst.sel = temp_reg;
7977 alu.dst.write = 1;
7978 alu.last = 1;
7979 r = r600_bytecode_add_alu(ctx->bc, &alu);
7980 if (r)
7981 return r;
7982 }
7983 return 0;
7984 }
7985
7986 static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
7987 {
7988 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7989 /* have to work out the offset into the RAT immediate return buffer */
7990 struct r600_bytecode_vtx vtx;
7991 struct r600_bytecode_cf *cf;
7992 int r;
7993 int temp_reg = r600_get_temp(ctx);
7994 unsigned rat_index_mode;
7995 unsigned base;
7996
7997 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7998 base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
7999
8000 r = load_buffer_coord(ctx, 1, temp_reg);
8001 if (r)
8002 return r;
8003 ctx->bc->cf_last->barrier = 1;
8004 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8005 vtx.op = FETCH_OP_VFETCH;
8006 vtx.buffer_id = inst->Src[0].Register.Index + base;
8007 vtx.buffer_index_mode = rat_index_mode;
8008 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8009 vtx.src_gpr = temp_reg;
8010 vtx.src_sel_x = 0;
8011 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8012 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
8013 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
8014 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
8015 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
8016 vtx.num_format_all = 1;
8017 vtx.format_comp_all = 1;
8018 vtx.srf_mode_all = 0;
8019
8020 if (inst->Dst[0].Register.WriteMask & 8) {
8021 vtx.data_format = FMT_32_32_32_32;
8022 vtx.use_const_fields = 0;
8023 } else if (inst->Dst[0].Register.WriteMask & 4) {
8024 vtx.data_format = FMT_32_32_32;
8025 vtx.use_const_fields = 0;
8026 } else if (inst->Dst[0].Register.WriteMask & 2) {
8027 vtx.data_format = FMT_32_32;
8028 vtx.use_const_fields = 0;
8029 } else {
8030 vtx.data_format = FMT_32;
8031 vtx.use_const_fields = 0;
8032 }
8033
8034 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8035 if (r)
8036 return r;
8037 cf = ctx->bc->cf_last;
8038 cf->barrier = 1;
8039 return 0;
8040 }
8041
8042 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
8043 {
8044 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8045 /* have to work out the offset into the RAT immediate return buffer */
8046 struct r600_bytecode_vtx vtx;
8047 struct r600_bytecode_cf *cf;
8048 int r;
8049 int idx_gpr;
8050 unsigned format, num_format, format_comp, endian;
8051 const struct util_format_description *desc;
8052 unsigned rat_index_mode;
8053 unsigned immed_base;
8054
8055 r = load_thread_id_gpr(ctx);
8056 if (r)
8057 return r;
8058
8059 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8060
8061 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8062 r = load_index_src(ctx, 1, &idx_gpr);
8063 if (r)
8064 return r;
8065
8066 if (rat_index_mode)
8067 egcm_load_index_reg(ctx->bc, 1, false);
8068
8069 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8070 cf = ctx->bc->cf_last;
8071
8072 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8073 cf->rat.inst = V_RAT_INST_NOP_RTN;
8074 cf->rat.index_mode = rat_index_mode;
8075 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8076 cf->output.gpr = ctx->thread_id_gpr;
8077 cf->output.index_gpr = idx_gpr;
8078 cf->output.comp_mask = 0xf;
8079 cf->output.burst_count = 1;
8080 cf->vpm = 1;
8081 cf->barrier = 1;
8082 cf->mark = 1;
8083 cf->output.elem_size = 0;
8084
8085 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8086 cf = ctx->bc->cf_last;
8087 cf->barrier = 1;
8088
8089 desc = util_format_description(inst->Memory.Format);
8090 r600_vertex_data_type(inst->Memory.Format,
8091 &format, &num_format, &format_comp, &endian);
8092 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8093 vtx.op = FETCH_OP_VFETCH;
8094 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8095 vtx.buffer_index_mode = rat_index_mode;
8096 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8097 vtx.src_gpr = ctx->thread_id_gpr;
8098 vtx.src_sel_x = 1;
8099 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8100 vtx.dst_sel_x = desc->swizzle[0];
8101 vtx.dst_sel_y = desc->swizzle[1];
8102 vtx.dst_sel_z = desc->swizzle[2];
8103 vtx.dst_sel_w = desc->swizzle[3];
8104 vtx.srf_mode_all = 1;
8105 vtx.data_format = format;
8106 vtx.num_format_all = num_format;
8107 vtx.format_comp_all = format_comp;
8108 vtx.endian = endian;
8109 vtx.offset = 0;
8110 vtx.mega_fetch_count = 3;
8111 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8112 if (r)
8113 return r;
8114 cf = ctx->bc->cf_last;
8115 cf->barrier = 1;
8116 return 0;
8117 }
8118
8119 static int tgsi_load_lds(struct r600_shader_ctx *ctx)
8120 {
8121 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8122 struct r600_bytecode_alu alu;
8123 int r;
8124 int temp_reg = r600_get_temp(ctx);
8125
8126 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8127 alu.op = ALU_OP1_MOV;
8128 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8129 alu.dst.sel = temp_reg;
8130 alu.dst.write = 1;
8131 alu.last = 1;
8132 r = r600_bytecode_add_alu(ctx->bc, &alu);
8133 if (r)
8134 return r;
8135
8136 r = do_lds_fetch_values(ctx, temp_reg,
8137 ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
8138 if (r)
8139 return r;
8140 return 0;
8141 }
8142
8143 static int tgsi_load(struct r600_shader_ctx *ctx)
8144 {
8145 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8146 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8147 return tgsi_load_rat(ctx);
8148 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8149 return tgsi_load_gds(ctx);
8150 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8151 return tgsi_load_buffer(ctx);
8152 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8153 return tgsi_load_lds(ctx);
8154 return 0;
8155 }
8156
8157 static int tgsi_store_buffer_rat(struct r600_shader_ctx *ctx)
8158 {
8159 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8160 struct r600_bytecode_cf *cf;
8161 int r, i;
8162 unsigned rat_index_mode;
8163 int lasti;
8164 int temp_reg = r600_get_temp(ctx), treg2 = r600_get_temp(ctx);
8165
8166 r = load_buffer_coord(ctx, 0, treg2);
8167 if (r)
8168 return r;
8169
8170 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8171 if (rat_index_mode)
8172 egcm_load_index_reg(ctx->bc, 1, false);
8173
8174 for (i = 0; i <= 3; i++) {
8175 struct r600_bytecode_alu alu;
8176 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8177 alu.op = ALU_OP1_MOV;
8178 alu.dst.sel = temp_reg;
8179 alu.dst.chan = i;
8180 alu.src[0].sel = V_SQ_ALU_SRC_0;
8181 alu.last = (i == 3);
8182 alu.dst.write = 1;
8183 r = r600_bytecode_add_alu(ctx->bc, &alu);
8184 if (r)
8185 return r;
8186 }
8187
8188 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8189 for (i = 0; i <= lasti; i++) {
8190 struct r600_bytecode_alu alu;
8191 if (!((1 << i) & inst->Dst[0].Register.WriteMask))
8192 continue;
8193
8194 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8195 temp_reg, 0,
8196 treg2, 0,
8197 V_SQ_ALU_SRC_LITERAL, i);
8198 if (r)
8199 return r;
8200
8201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8202 alu.op = ALU_OP1_MOV;
8203 alu.dst.sel = ctx->temp_reg;
8204 alu.dst.chan = 0;
8205
8206 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8207 alu.last = 1;
8208 alu.dst.write = 1;
8209 r = r600_bytecode_add_alu(ctx->bc, &alu);
8210 if (r)
8211 return r;
8212
8213 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8214 cf = ctx->bc->cf_last;
8215
8216 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index + ctx->info.file_count[TGSI_FILE_IMAGE];
8217 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8218 cf->rat.index_mode = rat_index_mode;
8219 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8220 cf->output.gpr = ctx->temp_reg;
8221 cf->output.index_gpr = temp_reg;
8222 cf->output.comp_mask = 1;
8223 cf->output.burst_count = 1;
8224 cf->vpm = 1;
8225 cf->barrier = 1;
8226 cf->output.elem_size = 0;
8227 }
8228 return 0;
8229 }
8230
8231 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
8232 {
8233 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8234 struct r600_bytecode_cf *cf;
8235 bool src_requires_loading = false;
8236 int val_gpr, idx_gpr;
8237 int r, i;
8238 unsigned rat_index_mode;
8239
8240 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8241
8242 r = load_index_src(ctx, 0, &idx_gpr);
8243 if (r)
8244 return r;
8245
8246 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
8247 src_requires_loading = true;
8248
8249 if (src_requires_loading) {
8250 struct r600_bytecode_alu alu;
8251 for (i = 0; i < 4; i++) {
8252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8253 alu.op = ALU_OP1_MOV;
8254 alu.dst.sel = ctx->temp_reg;
8255 alu.dst.chan = i;
8256
8257 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8258 if (i == 3)
8259 alu.last = 1;
8260 alu.dst.write = 1;
8261 r = r600_bytecode_add_alu(ctx->bc, &alu);
8262 if (r)
8263 return r;
8264 }
8265 val_gpr = ctx->temp_reg;
8266 } else
8267 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
8268 if (rat_index_mode)
8269 egcm_load_index_reg(ctx->bc, 1, false);
8270
8271 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8272 cf = ctx->bc->cf_last;
8273
8274 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
8275 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8276 cf->rat.index_mode = rat_index_mode;
8277 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8278 cf->output.gpr = val_gpr;
8279 cf->output.index_gpr = idx_gpr;
8280 cf->output.comp_mask = 0xf;
8281 cf->output.burst_count = 1;
8282 cf->vpm = 1;
8283 cf->barrier = 1;
8284 cf->output.elem_size = 0;
8285 return 0;
8286 }
8287
8288 static int tgsi_store_lds(struct r600_shader_ctx *ctx)
8289 {
8290 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8291 struct r600_bytecode_alu alu;
8292 int r, i, lasti;
8293 int write_mask = inst->Dst[0].Register.WriteMask;
8294 int temp_reg = r600_get_temp(ctx);
8295
8296 /* LDS write */
8297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8298 alu.op = ALU_OP1_MOV;
8299 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8300 alu.dst.sel = temp_reg;
8301 alu.dst.write = 1;
8302 alu.last = 1;
8303 r = r600_bytecode_add_alu(ctx->bc, &alu);
8304 if (r)
8305 return r;
8306
8307 lasti = tgsi_last_instruction(write_mask);
8308 for (i = 1; i <= lasti; i++) {
8309 if (!(write_mask & (1 << i)))
8310 continue;
8311 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8312 temp_reg, i,
8313 temp_reg, 0,
8314 V_SQ_ALU_SRC_LITERAL, 4 * i);
8315 if (r)
8316 return r;
8317 }
8318 for (i = 0; i <= lasti; i++) {
8319 if (!(write_mask & (1 << i)))
8320 continue;
8321
8322 if ((i == 0 && ((write_mask & 3) == 3)) ||
8323 (i == 2 && ((write_mask & 0xc) == 0xc))) {
8324 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8325 alu.op = LDS_OP3_LDS_WRITE_REL;
8326
8327 alu.src[0].sel = temp_reg;
8328 alu.src[0].chan = i;
8329 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8330 r600_bytecode_src(&alu.src[2], &ctx->src[1], i + 1);
8331 alu.last = 1;
8332 alu.is_lds_idx_op = true;
8333 alu.lds_idx = 1;
8334 r = r600_bytecode_add_alu(ctx->bc, &alu);
8335 if (r)
8336 return r;
8337 i += 1;
8338 continue;
8339 }
8340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8341 alu.op = LDS_OP2_LDS_WRITE;
8342
8343 alu.src[0].sel = temp_reg;
8344 alu.src[0].chan = i;
8345 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8346
8347 alu.last = 1;
8348 alu.is_lds_idx_op = true;
8349
8350 r = r600_bytecode_add_alu(ctx->bc, &alu);
8351 if (r)
8352 return r;
8353 }
8354 return 0;
8355 }
8356
8357 static int tgsi_store(struct r600_shader_ctx *ctx)
8358 {
8359 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8360 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
8361 return tgsi_store_buffer_rat(ctx);
8362 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
8363 return tgsi_store_lds(ctx);
8364 else
8365 return tgsi_store_rat(ctx);
8366 }
8367
8368 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
8369 {
8370 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8371 /* have to work out the offset into the RAT immediate return buffer */
8372 struct r600_bytecode_alu alu;
8373 struct r600_bytecode_vtx vtx;
8374 struct r600_bytecode_cf *cf;
8375 int r;
8376 int idx_gpr;
8377 unsigned format, num_format, format_comp, endian;
8378 const struct util_format_description *desc;
8379 unsigned rat_index_mode;
8380 unsigned immed_base;
8381 unsigned rat_base;
8382
8383 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8384 rat_base = ctx->shader->rat_base;
8385
8386 r = load_thread_id_gpr(ctx);
8387 if (r)
8388 return r;
8389
8390 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
8391 immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8392 rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8393
8394 r = load_buffer_coord(ctx, 1, ctx->temp_reg);
8395 if (r)
8396 return r;
8397 idx_gpr = ctx->temp_reg;
8398 } else {
8399 r = load_index_src(ctx, 1, &idx_gpr);
8400 if (r)
8401 return r;
8402 }
8403
8404 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8405
8406 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
8407 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8408 alu.op = ALU_OP1_MOV;
8409 alu.dst.sel = ctx->thread_id_gpr;
8410 alu.dst.chan = 0;
8411 alu.dst.write = 1;
8412 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8413 alu.last = 1;
8414 r = r600_bytecode_add_alu(ctx->bc, &alu);
8415 if (r)
8416 return r;
8417
8418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8419 alu.op = ALU_OP1_MOV;
8420 alu.dst.sel = ctx->thread_id_gpr;
8421 if (ctx->bc->chip_class == CAYMAN)
8422 alu.dst.chan = 2;
8423 else
8424 alu.dst.chan = 3;
8425 alu.dst.write = 1;
8426 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8427 alu.last = 1;
8428 r = r600_bytecode_add_alu(ctx->bc, &alu);
8429 if (r)
8430 return r;
8431 } else {
8432 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8433 alu.op = ALU_OP1_MOV;
8434 alu.dst.sel = ctx->thread_id_gpr;
8435 alu.dst.chan = 0;
8436 alu.dst.write = 1;
8437 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8438 alu.last = 1;
8439 r = r600_bytecode_add_alu(ctx->bc, &alu);
8440 if (r)
8441 return r;
8442 }
8443
8444 if (rat_index_mode)
8445 egcm_load_index_reg(ctx->bc, 1, false);
8446 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8447 cf = ctx->bc->cf_last;
8448
8449 cf->rat.id = rat_base + inst->Src[0].Register.Index;
8450 cf->rat.inst = ctx->inst_info->op;
8451 cf->rat.index_mode = rat_index_mode;
8452 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8453 cf->output.gpr = ctx->thread_id_gpr;
8454 cf->output.index_gpr = idx_gpr;
8455 cf->output.comp_mask = 0xf;
8456 cf->output.burst_count = 1;
8457 cf->vpm = 1;
8458 cf->barrier = 1;
8459 cf->mark = 1;
8460 cf->output.elem_size = 0;
8461 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8462 cf = ctx->bc->cf_last;
8463 cf->barrier = 1;
8464 cf->cf_addr = 1;
8465
8466 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8467 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
8468 desc = util_format_description(inst->Memory.Format);
8469 r600_vertex_data_type(inst->Memory.Format,
8470 &format, &num_format, &format_comp, &endian);
8471 vtx.dst_sel_x = desc->swizzle[0];
8472 } else {
8473 format = FMT_32;
8474 num_format = 1;
8475 format_comp = 0;
8476 endian = 0;
8477 vtx.dst_sel_x = 0;
8478 }
8479 vtx.op = FETCH_OP_VFETCH;
8480 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8481 vtx.buffer_index_mode = rat_index_mode;
8482 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8483 vtx.src_gpr = ctx->thread_id_gpr;
8484 vtx.src_sel_x = 1;
8485 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8486 vtx.dst_sel_y = 7;
8487 vtx.dst_sel_z = 7;
8488 vtx.dst_sel_w = 7;
8489 vtx.use_const_fields = 0;
8490 vtx.srf_mode_all = 1;
8491 vtx.data_format = format;
8492 vtx.num_format_all = num_format;
8493 vtx.format_comp_all = format_comp;
8494 vtx.endian = endian;
8495 vtx.offset = 0;
8496 vtx.mega_fetch_count = 0xf;
8497 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8498 if (r)
8499 return r;
8500 cf = ctx->bc->cf_last;
8501 cf->vpm = 1;
8502 cf->barrier = 1;
8503 return 0;
8504 }
8505
8506 static int get_gds_op(int opcode)
8507 {
8508 switch (opcode) {
8509 case TGSI_OPCODE_ATOMUADD:
8510 return FETCH_OP_GDS_ADD_RET;
8511 case TGSI_OPCODE_ATOMAND:
8512 return FETCH_OP_GDS_AND_RET;
8513 case TGSI_OPCODE_ATOMOR:
8514 return FETCH_OP_GDS_OR_RET;
8515 case TGSI_OPCODE_ATOMXOR:
8516 return FETCH_OP_GDS_XOR_RET;
8517 case TGSI_OPCODE_ATOMUMIN:
8518 return FETCH_OP_GDS_MIN_UINT_RET;
8519 case TGSI_OPCODE_ATOMUMAX:
8520 return FETCH_OP_GDS_MAX_UINT_RET;
8521 case TGSI_OPCODE_ATOMXCHG:
8522 return FETCH_OP_GDS_XCHG_RET;
8523 case TGSI_OPCODE_ATOMCAS:
8524 return FETCH_OP_GDS_CMP_XCHG_RET;
8525 default:
8526 return -1;
8527 }
8528 }
8529
8530 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
8531 {
8532 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8533 struct r600_bytecode_gds gds;
8534 struct r600_bytecode_alu alu;
8535 int gds_op = get_gds_op(inst->Instruction.Opcode);
8536 int r;
8537 int uav_id = 0;
8538 int uav_index_mode = 0;
8539 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8540
8541 if (gds_op == -1) {
8542 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
8543 return -1;
8544 }
8545
8546 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8547 if (r)
8548 return r;
8549
8550 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
8551 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
8552 int abs_value = abs(value);
8553 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
8554 gds_op = FETCH_OP_GDS_SUB_RET;
8555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8556 alu.op = ALU_OP1_MOV;
8557 alu.dst.sel = ctx->temp_reg;
8558 alu.dst.chan = is_cm ? 1 : 0;
8559 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8560 alu.src[0].value = abs_value;
8561 alu.last = 1;
8562 alu.dst.write = 1;
8563 r = r600_bytecode_add_alu(ctx->bc, &alu);
8564 if (r)
8565 return r;
8566 } else {
8567 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8568 alu.op = ALU_OP1_MOV;
8569 alu.dst.sel = ctx->temp_reg;
8570 alu.dst.chan = is_cm ? 1 : 0;
8571 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8572 alu.last = 1;
8573 alu.dst.write = 1;
8574 r = r600_bytecode_add_alu(ctx->bc, &alu);
8575 if (r)
8576 return r;
8577 }
8578
8579
8580 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8581 gds.op = gds_op;
8582 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8583 gds.uav_id = is_cm ? 0 : uav_id;
8584 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8585 gds.src_gpr = ctx->temp_reg;
8586 gds.src_gpr2 = 0;
8587 gds.src_sel_x = is_cm ? 0 : 4;
8588 gds.src_sel_y = is_cm ? 1 : 0;
8589 gds.src_sel_z = 7;
8590 gds.dst_sel_x = 0;
8591 gds.dst_sel_y = 7;
8592 gds.dst_sel_z = 7;
8593 gds.dst_sel_w = 7;
8594 gds.alloc_consume = !is_cm;
8595
8596 r = r600_bytecode_add_gds(ctx->bc, &gds);
8597 if (r)
8598 return r;
8599 ctx->bc->cf_last->vpm = 1;
8600 return 0;
8601 }
8602
8603 static int get_lds_op(int opcode)
8604 {
8605 switch (opcode) {
8606 case TGSI_OPCODE_ATOMUADD:
8607 return LDS_OP2_LDS_ADD_RET;
8608 case TGSI_OPCODE_ATOMAND:
8609 return LDS_OP2_LDS_AND_RET;
8610 case TGSI_OPCODE_ATOMOR:
8611 return LDS_OP2_LDS_OR_RET;
8612 case TGSI_OPCODE_ATOMXOR:
8613 return LDS_OP2_LDS_XOR_RET;
8614 case TGSI_OPCODE_ATOMUMIN:
8615 return LDS_OP2_LDS_MIN_UINT_RET;
8616 case TGSI_OPCODE_ATOMUMAX:
8617 return LDS_OP2_LDS_MAX_UINT_RET;
8618 case TGSI_OPCODE_ATOMIMIN:
8619 return LDS_OP2_LDS_MIN_INT_RET;
8620 case TGSI_OPCODE_ATOMIMAX:
8621 return LDS_OP2_LDS_MAX_INT_RET;
8622 case TGSI_OPCODE_ATOMXCHG:
8623 return LDS_OP2_LDS_XCHG_RET;
8624 case TGSI_OPCODE_ATOMCAS:
8625 return LDS_OP3_LDS_CMP_XCHG_RET;
8626 default:
8627 return -1;
8628 }
8629 }
8630
8631 static int tgsi_atomic_op_lds(struct r600_shader_ctx *ctx)
8632 {
8633 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8634 int lds_op = get_lds_op(inst->Instruction.Opcode);
8635 int r;
8636
8637 struct r600_bytecode_alu alu;
8638 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8639 alu.op = lds_op;
8640 alu.is_lds_idx_op = true;
8641 alu.last = 1;
8642 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8643 r600_bytecode_src(&alu.src[1], &ctx->src[2], 0);
8644 if (lds_op == LDS_OP3_LDS_CMP_XCHG_RET)
8645 r600_bytecode_src(&alu.src[2], &ctx->src[3], 0);
8646 else
8647 alu.src[2].sel = V_SQ_ALU_SRC_0;
8648 r = r600_bytecode_add_alu(ctx->bc, &alu);
8649 if (r)
8650 return r;
8651
8652 /* then read from LDS_OQ_A_POP */
8653 memset(&alu, 0, sizeof(alu));
8654
8655 alu.op = ALU_OP1_MOV;
8656 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
8657 alu.src[0].chan = 0;
8658 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
8659 alu.dst.write = 1;
8660 alu.last = 1;
8661 r = r600_bytecode_add_alu(ctx->bc, &alu);
8662 if (r)
8663 return r;
8664
8665 return 0;
8666 }
8667
8668 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
8669 {
8670 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8671 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8672 return tgsi_atomic_op_rat(ctx);
8673 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8674 return tgsi_atomic_op_gds(ctx);
8675 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8676 return tgsi_atomic_op_rat(ctx);
8677 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8678 return tgsi_atomic_op_lds(ctx);
8679 return 0;
8680 }
8681
8682 static int tgsi_resq(struct r600_shader_ctx *ctx)
8683 {
8684 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8685 unsigned sampler_index_mode;
8686 struct r600_bytecode_tex tex;
8687 int r;
8688 boolean has_txq_cube_array_z = false;
8689
8690 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
8691 (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
8692 ctx->shader->uses_tex_buffers = true;
8693 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset);
8694 }
8695
8696 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
8697 inst->Dst[0].Register.WriteMask & 4) {
8698 ctx->shader->has_txq_cube_array_z_comp = true;
8699 has_txq_cube_array_z = true;
8700 }
8701
8702 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8703 if (sampler_index_mode)
8704 egcm_load_index_reg(ctx->bc, 1, false);
8705
8706
8707 /* does this shader want a num layers from TXQ for a cube array? */
8708 if (has_txq_cube_array_z) {
8709 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
8710 struct r600_bytecode_alu alu;
8711
8712 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8713 alu.op = ALU_OP1_MOV;
8714
8715 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8716 /* channel 1 or 3 of each word */
8717 alu.src[0].sel += (id / 2);
8718 alu.src[0].chan = ((id % 2) * 2) + 1;
8719 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8720 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8721 alu.last = 1;
8722 r = r600_bytecode_add_alu(ctx->bc, &alu);
8723 if (r)
8724 return r;
8725 /* disable writemask from texture instruction */
8726 inst->Dst[0].Register.WriteMask &= ~4;
8727 }
8728 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8729 tex.op = ctx->inst_info->op;
8730 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
8731 tex.sampler_index_mode = sampler_index_mode;
8732 tex.resource_id = tex.sampler_id;
8733 tex.resource_index_mode = sampler_index_mode;
8734 tex.src_sel_x = 4;
8735 tex.src_sel_y = 4;
8736 tex.src_sel_z = 4;
8737 tex.src_sel_w = 4;
8738 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8739 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8740 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8741 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8742 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8743 r = r600_bytecode_add_tex(ctx->bc, &tex);
8744 if (r)
8745 return r;
8746
8747 return 0;
8748 }
8749
8750 static int tgsi_lrp(struct r600_shader_ctx *ctx)
8751 {
8752 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8753 struct r600_bytecode_alu alu;
8754 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8755 unsigned i, temp_regs[2];
8756 int r;
8757
8758 /* optimize if it's just an equal balance */
8759 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
8760 for (i = 0; i < lasti + 1; i++) {
8761 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8762 continue;
8763
8764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8765 alu.op = ALU_OP2_ADD;
8766 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8767 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8768 alu.omod = 3;
8769 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8770 alu.dst.chan = i;
8771 if (i == lasti) {
8772 alu.last = 1;
8773 }
8774 r = r600_bytecode_add_alu(ctx->bc, &alu);
8775 if (r)
8776 return r;
8777 }
8778 return 0;
8779 }
8780
8781 /* 1 - src0 */
8782 for (i = 0; i < lasti + 1; i++) {
8783 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8784 continue;
8785
8786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8787 alu.op = ALU_OP2_ADD;
8788 alu.src[0].sel = V_SQ_ALU_SRC_1;
8789 alu.src[0].chan = 0;
8790 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
8791 r600_bytecode_src_toggle_neg(&alu.src[1]);
8792 alu.dst.sel = ctx->temp_reg;
8793 alu.dst.chan = i;
8794 if (i == lasti) {
8795 alu.last = 1;
8796 }
8797 alu.dst.write = 1;
8798 r = r600_bytecode_add_alu(ctx->bc, &alu);
8799 if (r)
8800 return r;
8801 }
8802
8803 /* (1 - src0) * src2 */
8804 for (i = 0; i < lasti + 1; i++) {
8805 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8806 continue;
8807
8808 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8809 alu.op = ALU_OP2_MUL;
8810 alu.src[0].sel = ctx->temp_reg;
8811 alu.src[0].chan = i;
8812 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8813 alu.dst.sel = ctx->temp_reg;
8814 alu.dst.chan = i;
8815 if (i == lasti) {
8816 alu.last = 1;
8817 }
8818 alu.dst.write = 1;
8819 r = r600_bytecode_add_alu(ctx->bc, &alu);
8820 if (r)
8821 return r;
8822 }
8823
8824 /* src0 * src1 + (1 - src0) * src2 */
8825 if (ctx->src[0].abs)
8826 temp_regs[0] = r600_get_temp(ctx);
8827 else
8828 temp_regs[0] = 0;
8829 if (ctx->src[1].abs)
8830 temp_regs[1] = r600_get_temp(ctx);
8831 else
8832 temp_regs[1] = 0;
8833
8834 for (i = 0; i < lasti + 1; i++) {
8835 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8836 continue;
8837
8838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8839 alu.op = ALU_OP3_MULADD;
8840 alu.is_op3 = 1;
8841 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8842 if (r)
8843 return r;
8844 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
8845 if (r)
8846 return r;
8847 alu.src[2].sel = ctx->temp_reg;
8848 alu.src[2].chan = i;
8849
8850 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8851 alu.dst.chan = i;
8852 if (i == lasti) {
8853 alu.last = 1;
8854 }
8855 r = r600_bytecode_add_alu(ctx->bc, &alu);
8856 if (r)
8857 return r;
8858 }
8859 return 0;
8860 }
8861
8862 static int tgsi_cmp(struct r600_shader_ctx *ctx)
8863 {
8864 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8865 struct r600_bytecode_alu alu;
8866 int i, r, j;
8867 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8868 int temp_regs[3];
8869 unsigned op;
8870
8871 if (ctx->src[0].abs && ctx->src[0].neg) {
8872 op = ALU_OP3_CNDE;
8873 ctx->src[0].abs = 0;
8874 ctx->src[0].neg = 0;
8875 } else {
8876 op = ALU_OP3_CNDGE;
8877 }
8878
8879 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
8880 temp_regs[j] = 0;
8881 if (ctx->src[j].abs)
8882 temp_regs[j] = r600_get_temp(ctx);
8883 }
8884
8885 for (i = 0; i < lasti + 1; i++) {
8886 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8887 continue;
8888
8889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8890 alu.op = op;
8891 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8892 if (r)
8893 return r;
8894 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
8895 if (r)
8896 return r;
8897 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
8898 if (r)
8899 return r;
8900 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8901 alu.dst.chan = i;
8902 alu.dst.write = 1;
8903 alu.is_op3 = 1;
8904 if (i == lasti)
8905 alu.last = 1;
8906 r = r600_bytecode_add_alu(ctx->bc, &alu);
8907 if (r)
8908 return r;
8909 }
8910 return 0;
8911 }
8912
8913 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
8914 {
8915 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8916 struct r600_bytecode_alu alu;
8917 int i, r;
8918 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8919
8920 for (i = 0; i < lasti + 1; i++) {
8921 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8922 continue;
8923
8924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8925 alu.op = ALU_OP3_CNDE_INT;
8926 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8927 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8928 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
8929 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8930 alu.dst.chan = i;
8931 alu.dst.write = 1;
8932 alu.is_op3 = 1;
8933 if (i == lasti)
8934 alu.last = 1;
8935 r = r600_bytecode_add_alu(ctx->bc, &alu);
8936 if (r)
8937 return r;
8938 }
8939 return 0;
8940 }
8941
8942 static int tgsi_exp(struct r600_shader_ctx *ctx)
8943 {
8944 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8945 struct r600_bytecode_alu alu;
8946 int r;
8947 unsigned i;
8948
8949 /* result.x = 2^floor(src); */
8950 if (inst->Dst[0].Register.WriteMask & 1) {
8951 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8952
8953 alu.op = ALU_OP1_FLOOR;
8954 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8955
8956 alu.dst.sel = ctx->temp_reg;
8957 alu.dst.chan = 0;
8958 alu.dst.write = 1;
8959 alu.last = 1;
8960 r = r600_bytecode_add_alu(ctx->bc, &alu);
8961 if (r)
8962 return r;
8963
8964 if (ctx->bc->chip_class == CAYMAN) {
8965 for (i = 0; i < 3; i++) {
8966 alu.op = ALU_OP1_EXP_IEEE;
8967 alu.src[0].sel = ctx->temp_reg;
8968 alu.src[0].chan = 0;
8969
8970 alu.dst.sel = ctx->temp_reg;
8971 alu.dst.chan = i;
8972 alu.dst.write = i == 0;
8973 alu.last = i == 2;
8974 r = r600_bytecode_add_alu(ctx->bc, &alu);
8975 if (r)
8976 return r;
8977 }
8978 } else {
8979 alu.op = ALU_OP1_EXP_IEEE;
8980 alu.src[0].sel = ctx->temp_reg;
8981 alu.src[0].chan = 0;
8982
8983 alu.dst.sel = ctx->temp_reg;
8984 alu.dst.chan = 0;
8985 alu.dst.write = 1;
8986 alu.last = 1;
8987 r = r600_bytecode_add_alu(ctx->bc, &alu);
8988 if (r)
8989 return r;
8990 }
8991 }
8992
8993 /* result.y = tmp - floor(tmp); */
8994 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8995 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8996
8997 alu.op = ALU_OP1_FRACT;
8998 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8999
9000 alu.dst.sel = ctx->temp_reg;
9001 #if 0
9002 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9003 if (r)
9004 return r;
9005 #endif
9006 alu.dst.write = 1;
9007 alu.dst.chan = 1;
9008
9009 alu.last = 1;
9010
9011 r = r600_bytecode_add_alu(ctx->bc, &alu);
9012 if (r)
9013 return r;
9014 }
9015
9016 /* result.z = RoughApprox2ToX(tmp);*/
9017 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
9018 if (ctx->bc->chip_class == CAYMAN) {
9019 for (i = 0; i < 3; i++) {
9020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9021 alu.op = ALU_OP1_EXP_IEEE;
9022 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9023
9024 alu.dst.sel = ctx->temp_reg;
9025 alu.dst.chan = i;
9026 if (i == 2) {
9027 alu.dst.write = 1;
9028 alu.last = 1;
9029 }
9030
9031 r = r600_bytecode_add_alu(ctx->bc, &alu);
9032 if (r)
9033 return r;
9034 }
9035 } else {
9036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9037 alu.op = ALU_OP1_EXP_IEEE;
9038 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9039
9040 alu.dst.sel = ctx->temp_reg;
9041 alu.dst.write = 1;
9042 alu.dst.chan = 2;
9043
9044 alu.last = 1;
9045
9046 r = r600_bytecode_add_alu(ctx->bc, &alu);
9047 if (r)
9048 return r;
9049 }
9050 }
9051
9052 /* result.w = 1.0;*/
9053 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
9054 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9055
9056 alu.op = ALU_OP1_MOV;
9057 alu.src[0].sel = V_SQ_ALU_SRC_1;
9058 alu.src[0].chan = 0;
9059
9060 alu.dst.sel = ctx->temp_reg;
9061 alu.dst.chan = 3;
9062 alu.dst.write = 1;
9063 alu.last = 1;
9064 r = r600_bytecode_add_alu(ctx->bc, &alu);
9065 if (r)
9066 return r;
9067 }
9068 return tgsi_helper_copy(ctx, inst);
9069 }
9070
9071 static int tgsi_log(struct r600_shader_ctx *ctx)
9072 {
9073 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9074 struct r600_bytecode_alu alu;
9075 int r;
9076 unsigned i;
9077
9078 /* result.x = floor(log2(|src|)); */
9079 if (inst->Dst[0].Register.WriteMask & 1) {
9080 if (ctx->bc->chip_class == CAYMAN) {
9081 for (i = 0; i < 3; i++) {
9082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9083
9084 alu.op = ALU_OP1_LOG_IEEE;
9085 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9086 r600_bytecode_src_set_abs(&alu.src[0]);
9087
9088 alu.dst.sel = ctx->temp_reg;
9089 alu.dst.chan = i;
9090 if (i == 0)
9091 alu.dst.write = 1;
9092 if (i == 2)
9093 alu.last = 1;
9094 r = r600_bytecode_add_alu(ctx->bc, &alu);
9095 if (r)
9096 return r;
9097 }
9098
9099 } else {
9100 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9101
9102 alu.op = ALU_OP1_LOG_IEEE;
9103 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9104 r600_bytecode_src_set_abs(&alu.src[0]);
9105
9106 alu.dst.sel = ctx->temp_reg;
9107 alu.dst.chan = 0;
9108 alu.dst.write = 1;
9109 alu.last = 1;
9110 r = r600_bytecode_add_alu(ctx->bc, &alu);
9111 if (r)
9112 return r;
9113 }
9114
9115 alu.op = ALU_OP1_FLOOR;
9116 alu.src[0].sel = ctx->temp_reg;
9117 alu.src[0].chan = 0;
9118
9119 alu.dst.sel = ctx->temp_reg;
9120 alu.dst.chan = 0;
9121 alu.dst.write = 1;
9122 alu.last = 1;
9123
9124 r = r600_bytecode_add_alu(ctx->bc, &alu);
9125 if (r)
9126 return r;
9127 }
9128
9129 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
9130 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9131
9132 if (ctx->bc->chip_class == CAYMAN) {
9133 for (i = 0; i < 3; i++) {
9134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9135
9136 alu.op = ALU_OP1_LOG_IEEE;
9137 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9138 r600_bytecode_src_set_abs(&alu.src[0]);
9139
9140 alu.dst.sel = ctx->temp_reg;
9141 alu.dst.chan = i;
9142 if (i == 1)
9143 alu.dst.write = 1;
9144 if (i == 2)
9145 alu.last = 1;
9146
9147 r = r600_bytecode_add_alu(ctx->bc, &alu);
9148 if (r)
9149 return r;
9150 }
9151 } else {
9152 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9153
9154 alu.op = ALU_OP1_LOG_IEEE;
9155 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9156 r600_bytecode_src_set_abs(&alu.src[0]);
9157
9158 alu.dst.sel = ctx->temp_reg;
9159 alu.dst.chan = 1;
9160 alu.dst.write = 1;
9161 alu.last = 1;
9162
9163 r = r600_bytecode_add_alu(ctx->bc, &alu);
9164 if (r)
9165 return r;
9166 }
9167
9168 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9169
9170 alu.op = ALU_OP1_FLOOR;
9171 alu.src[0].sel = ctx->temp_reg;
9172 alu.src[0].chan = 1;
9173
9174 alu.dst.sel = ctx->temp_reg;
9175 alu.dst.chan = 1;
9176 alu.dst.write = 1;
9177 alu.last = 1;
9178
9179 r = r600_bytecode_add_alu(ctx->bc, &alu);
9180 if (r)
9181 return r;
9182
9183 if (ctx->bc->chip_class == CAYMAN) {
9184 for (i = 0; i < 3; i++) {
9185 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9186 alu.op = ALU_OP1_EXP_IEEE;
9187 alu.src[0].sel = ctx->temp_reg;
9188 alu.src[0].chan = 1;
9189
9190 alu.dst.sel = ctx->temp_reg;
9191 alu.dst.chan = i;
9192 if (i == 1)
9193 alu.dst.write = 1;
9194 if (i == 2)
9195 alu.last = 1;
9196
9197 r = r600_bytecode_add_alu(ctx->bc, &alu);
9198 if (r)
9199 return r;
9200 }
9201 } else {
9202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9203 alu.op = ALU_OP1_EXP_IEEE;
9204 alu.src[0].sel = ctx->temp_reg;
9205 alu.src[0].chan = 1;
9206
9207 alu.dst.sel = ctx->temp_reg;
9208 alu.dst.chan = 1;
9209 alu.dst.write = 1;
9210 alu.last = 1;
9211
9212 r = r600_bytecode_add_alu(ctx->bc, &alu);
9213 if (r)
9214 return r;
9215 }
9216
9217 if (ctx->bc->chip_class == CAYMAN) {
9218 for (i = 0; i < 3; i++) {
9219 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9220 alu.op = ALU_OP1_RECIP_IEEE;
9221 alu.src[0].sel = ctx->temp_reg;
9222 alu.src[0].chan = 1;
9223
9224 alu.dst.sel = ctx->temp_reg;
9225 alu.dst.chan = i;
9226 if (i == 1)
9227 alu.dst.write = 1;
9228 if (i == 2)
9229 alu.last = 1;
9230
9231 r = r600_bytecode_add_alu(ctx->bc, &alu);
9232 if (r)
9233 return r;
9234 }
9235 } else {
9236 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9237 alu.op = ALU_OP1_RECIP_IEEE;
9238 alu.src[0].sel = ctx->temp_reg;
9239 alu.src[0].chan = 1;
9240
9241 alu.dst.sel = ctx->temp_reg;
9242 alu.dst.chan = 1;
9243 alu.dst.write = 1;
9244 alu.last = 1;
9245
9246 r = r600_bytecode_add_alu(ctx->bc, &alu);
9247 if (r)
9248 return r;
9249 }
9250
9251 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9252
9253 alu.op = ALU_OP2_MUL;
9254
9255 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9256 r600_bytecode_src_set_abs(&alu.src[0]);
9257
9258 alu.src[1].sel = ctx->temp_reg;
9259 alu.src[1].chan = 1;
9260
9261 alu.dst.sel = ctx->temp_reg;
9262 alu.dst.chan = 1;
9263 alu.dst.write = 1;
9264 alu.last = 1;
9265
9266 r = r600_bytecode_add_alu(ctx->bc, &alu);
9267 if (r)
9268 return r;
9269 }
9270
9271 /* result.z = log2(|src|);*/
9272 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
9273 if (ctx->bc->chip_class == CAYMAN) {
9274 for (i = 0; i < 3; i++) {
9275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9276
9277 alu.op = ALU_OP1_LOG_IEEE;
9278 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9279 r600_bytecode_src_set_abs(&alu.src[0]);
9280
9281 alu.dst.sel = ctx->temp_reg;
9282 if (i == 2)
9283 alu.dst.write = 1;
9284 alu.dst.chan = i;
9285 if (i == 2)
9286 alu.last = 1;
9287
9288 r = r600_bytecode_add_alu(ctx->bc, &alu);
9289 if (r)
9290 return r;
9291 }
9292 } else {
9293 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9294
9295 alu.op = ALU_OP1_LOG_IEEE;
9296 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9297 r600_bytecode_src_set_abs(&alu.src[0]);
9298
9299 alu.dst.sel = ctx->temp_reg;
9300 alu.dst.write = 1;
9301 alu.dst.chan = 2;
9302 alu.last = 1;
9303
9304 r = r600_bytecode_add_alu(ctx->bc, &alu);
9305 if (r)
9306 return r;
9307 }
9308 }
9309
9310 /* result.w = 1.0; */
9311 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
9312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9313
9314 alu.op = ALU_OP1_MOV;
9315 alu.src[0].sel = V_SQ_ALU_SRC_1;
9316 alu.src[0].chan = 0;
9317
9318 alu.dst.sel = ctx->temp_reg;
9319 alu.dst.chan = 3;
9320 alu.dst.write = 1;
9321 alu.last = 1;
9322
9323 r = r600_bytecode_add_alu(ctx->bc, &alu);
9324 if (r)
9325 return r;
9326 }
9327
9328 return tgsi_helper_copy(ctx, inst);
9329 }
9330
9331 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
9332 {
9333 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9334 struct r600_bytecode_alu alu;
9335 int r;
9336 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9337 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
9338
9339 assert(inst->Dst[0].Register.Index < 3);
9340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9341
9342 switch (inst->Instruction.Opcode) {
9343 case TGSI_OPCODE_ARL:
9344 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
9345 break;
9346 case TGSI_OPCODE_ARR:
9347 alu.op = ALU_OP1_FLT_TO_INT;
9348 break;
9349 case TGSI_OPCODE_UARL:
9350 alu.op = ALU_OP1_MOV;
9351 break;
9352 default:
9353 assert(0);
9354 return -1;
9355 }
9356
9357 for (i = 0; i <= lasti; ++i) {
9358 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9359 continue;
9360 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9361 alu.last = i == lasti;
9362 alu.dst.sel = reg;
9363 alu.dst.chan = i;
9364 alu.dst.write = 1;
9365 r = r600_bytecode_add_alu(ctx->bc, &alu);
9366 if (r)
9367 return r;
9368 }
9369
9370 if (inst->Dst[0].Register.Index > 0)
9371 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
9372 else
9373 ctx->bc->ar_loaded = 0;
9374
9375 return 0;
9376 }
9377 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
9378 {
9379 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9380 struct r600_bytecode_alu alu;
9381 int r;
9382 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9383
9384 switch (inst->Instruction.Opcode) {
9385 case TGSI_OPCODE_ARL:
9386 memset(&alu, 0, sizeof(alu));
9387 alu.op = ALU_OP1_FLOOR;
9388 alu.dst.sel = ctx->bc->ar_reg;
9389 alu.dst.write = 1;
9390 for (i = 0; i <= lasti; ++i) {
9391 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9392 alu.dst.chan = i;
9393 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9394 alu.last = i == lasti;
9395 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9396 return r;
9397 }
9398 }
9399
9400 memset(&alu, 0, sizeof(alu));
9401 alu.op = ALU_OP1_FLT_TO_INT;
9402 alu.src[0].sel = ctx->bc->ar_reg;
9403 alu.dst.sel = ctx->bc->ar_reg;
9404 alu.dst.write = 1;
9405 /* FLT_TO_INT is trans-only on r600/r700 */
9406 alu.last = TRUE;
9407 for (i = 0; i <= lasti; ++i) {
9408 alu.dst.chan = i;
9409 alu.src[0].chan = i;
9410 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9411 return r;
9412 }
9413 break;
9414 case TGSI_OPCODE_ARR:
9415 memset(&alu, 0, sizeof(alu));
9416 alu.op = ALU_OP1_FLT_TO_INT;
9417 alu.dst.sel = ctx->bc->ar_reg;
9418 alu.dst.write = 1;
9419 /* FLT_TO_INT is trans-only on r600/r700 */
9420 alu.last = TRUE;
9421 for (i = 0; i <= lasti; ++i) {
9422 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9423 alu.dst.chan = i;
9424 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9425 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9426 return r;
9427 }
9428 }
9429 break;
9430 case TGSI_OPCODE_UARL:
9431 memset(&alu, 0, sizeof(alu));
9432 alu.op = ALU_OP1_MOV;
9433 alu.dst.sel = ctx->bc->ar_reg;
9434 alu.dst.write = 1;
9435 for (i = 0; i <= lasti; ++i) {
9436 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9437 alu.dst.chan = i;
9438 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9439 alu.last = i == lasti;
9440 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9441 return r;
9442 }
9443 }
9444 break;
9445 default:
9446 assert(0);
9447 return -1;
9448 }
9449
9450 ctx->bc->ar_loaded = 0;
9451 return 0;
9452 }
9453
9454 static int tgsi_opdst(struct r600_shader_ctx *ctx)
9455 {
9456 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9457 struct r600_bytecode_alu alu;
9458 int i, r = 0;
9459
9460 for (i = 0; i < 4; i++) {
9461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9462
9463 alu.op = ALU_OP2_MUL;
9464 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9465
9466 if (i == 0 || i == 3) {
9467 alu.src[0].sel = V_SQ_ALU_SRC_1;
9468 } else {
9469 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9470 }
9471
9472 if (i == 0 || i == 2) {
9473 alu.src[1].sel = V_SQ_ALU_SRC_1;
9474 } else {
9475 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
9476 }
9477 if (i == 3)
9478 alu.last = 1;
9479 r = r600_bytecode_add_alu(ctx->bc, &alu);
9480 if (r)
9481 return r;
9482 }
9483 return 0;
9484 }
9485
9486 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
9487 {
9488 struct r600_bytecode_alu alu;
9489 int r;
9490
9491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9492 alu.op = opcode;
9493 alu.execute_mask = 1;
9494 alu.update_pred = 1;
9495
9496 alu.dst.sel = ctx->temp_reg;
9497 alu.dst.write = 1;
9498 alu.dst.chan = 0;
9499
9500 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9501 alu.src[1].sel = V_SQ_ALU_SRC_0;
9502 alu.src[1].chan = 0;
9503
9504 alu.last = 1;
9505
9506 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
9507 if (r)
9508 return r;
9509 return 0;
9510 }
9511
9512 static int pops(struct r600_shader_ctx *ctx, int pops)
9513 {
9514 unsigned force_pop = ctx->bc->force_add_cf;
9515
9516 if (!force_pop) {
9517 int alu_pop = 3;
9518 if (ctx->bc->cf_last) {
9519 if (ctx->bc->cf_last->op == CF_OP_ALU)
9520 alu_pop = 0;
9521 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
9522 alu_pop = 1;
9523 }
9524 alu_pop += pops;
9525 if (alu_pop == 1) {
9526 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
9527 ctx->bc->force_add_cf = 1;
9528 } else if (alu_pop == 2) {
9529 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
9530 ctx->bc->force_add_cf = 1;
9531 } else {
9532 force_pop = 1;
9533 }
9534 }
9535
9536 if (force_pop) {
9537 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
9538 ctx->bc->cf_last->pop_count = pops;
9539 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9540 }
9541
9542 return 0;
9543 }
9544
9545 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
9546 unsigned reason)
9547 {
9548 struct r600_stack_info *stack = &ctx->bc->stack;
9549 unsigned elements;
9550 int entries;
9551
9552 unsigned entry_size = stack->entry_size;
9553
9554 elements = (stack->loop + stack->push_wqm ) * entry_size;
9555 elements += stack->push;
9556
9557 switch (ctx->bc->chip_class) {
9558 case R600:
9559 case R700:
9560 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9561 * the stack must be reserved to hold the current active/continue
9562 * masks */
9563 if (reason == FC_PUSH_VPM) {
9564 elements += 2;
9565 }
9566 break;
9567
9568 case CAYMAN:
9569 /* r9xx: any stack operation on empty stack consumes 2 additional
9570 * elements */
9571 elements += 2;
9572
9573 /* fallthrough */
9574 /* FIXME: do the two elements added above cover the cases for the
9575 * r8xx+ below? */
9576
9577 case EVERGREEN:
9578 /* r8xx+: 2 extra elements are not always required, but one extra
9579 * element must be added for each of the following cases:
9580 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9581 * stack usage.
9582 * (Currently we don't use ALU_ELSE_AFTER.)
9583 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9584 * PUSH instruction executed.
9585 *
9586 * NOTE: it seems we also need to reserve additional element in some
9587 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9588 * then STACK_SIZE should be 2 instead of 1 */
9589 if (reason == FC_PUSH_VPM) {
9590 elements += 1;
9591 }
9592 break;
9593
9594 default:
9595 assert(0);
9596 break;
9597 }
9598
9599 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9600 * for all chips, so we use 4 in the final formula, not the real entry_size
9601 * for the chip */
9602 entry_size = 4;
9603
9604 entries = (elements + (entry_size - 1)) / entry_size;
9605
9606 if (entries > stack->max_entries)
9607 stack->max_entries = entries;
9608 }
9609
9610 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
9611 {
9612 switch(reason) {
9613 case FC_PUSH_VPM:
9614 --ctx->bc->stack.push;
9615 assert(ctx->bc->stack.push >= 0);
9616 break;
9617 case FC_PUSH_WQM:
9618 --ctx->bc->stack.push_wqm;
9619 assert(ctx->bc->stack.push_wqm >= 0);
9620 break;
9621 case FC_LOOP:
9622 --ctx->bc->stack.loop;
9623 assert(ctx->bc->stack.loop >= 0);
9624 break;
9625 default:
9626 assert(0);
9627 break;
9628 }
9629 }
9630
9631 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
9632 {
9633 switch (reason) {
9634 case FC_PUSH_VPM:
9635 ++ctx->bc->stack.push;
9636 break;
9637 case FC_PUSH_WQM:
9638 ++ctx->bc->stack.push_wqm;
9639 case FC_LOOP:
9640 ++ctx->bc->stack.loop;
9641 break;
9642 default:
9643 assert(0);
9644 }
9645
9646 callstack_update_max_depth(ctx, reason);
9647 }
9648
9649 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
9650 {
9651 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
9652
9653 sp->mid = realloc((void *)sp->mid,
9654 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
9655 sp->mid[sp->num_mid] = ctx->bc->cf_last;
9656 sp->num_mid++;
9657 }
9658
9659 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
9660 {
9661 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
9662 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
9663 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
9664 ctx->bc->fc_sp++;
9665 }
9666
9667 static void fc_poplevel(struct r600_shader_ctx *ctx)
9668 {
9669 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
9670 free(sp->mid);
9671 sp->mid = NULL;
9672 sp->num_mid = 0;
9673 sp->start = NULL;
9674 sp->type = 0;
9675 ctx->bc->fc_sp--;
9676 }
9677
9678 #if 0
9679 static int emit_return(struct r600_shader_ctx *ctx)
9680 {
9681 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
9682 return 0;
9683 }
9684
9685 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
9686 {
9687
9688 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
9689 ctx->bc->cf_last->pop_count = pops;
9690 /* XXX work out offset */
9691 return 0;
9692 }
9693
9694 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
9695 {
9696 return 0;
9697 }
9698
9699 static void emit_testflag(struct r600_shader_ctx *ctx)
9700 {
9701
9702 }
9703
9704 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
9705 {
9706 emit_testflag(ctx);
9707 emit_jump_to_offset(ctx, 1, 4);
9708 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
9709 pops(ctx, ifidx + 1);
9710 emit_return(ctx);
9711 }
9712
9713 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
9714 {
9715 emit_testflag(ctx);
9716
9717 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9718 ctx->bc->cf_last->pop_count = 1;
9719
9720 fc_set_mid(ctx, fc_sp);
9721
9722 pops(ctx, 1);
9723 }
9724 #endif
9725
9726 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
9727 {
9728 int alu_type = CF_OP_ALU_PUSH_BEFORE;
9729
9730 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9731 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9732 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9733 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9734 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
9735 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
9736 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9737 alu_type = CF_OP_ALU;
9738 }
9739
9740 emit_logic_pred(ctx, opcode, alu_type);
9741
9742 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
9743
9744 fc_pushlevel(ctx, FC_IF);
9745
9746 callstack_push(ctx, FC_PUSH_VPM);
9747 return 0;
9748 }
9749
9750 static int tgsi_if(struct r600_shader_ctx *ctx)
9751 {
9752 return emit_if(ctx, ALU_OP2_PRED_SETNE);
9753 }
9754
9755 static int tgsi_uif(struct r600_shader_ctx *ctx)
9756 {
9757 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
9758 }
9759
9760 static int tgsi_else(struct r600_shader_ctx *ctx)
9761 {
9762 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
9763 ctx->bc->cf_last->pop_count = 1;
9764
9765 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
9766 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
9767 return 0;
9768 }
9769
9770 static int tgsi_endif(struct r600_shader_ctx *ctx)
9771 {
9772 pops(ctx, 1);
9773 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
9774 R600_ERR("if/endif unbalanced in shader\n");
9775 return -1;
9776 }
9777
9778 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
9779 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9780 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
9781 } else {
9782 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
9783 }
9784 fc_poplevel(ctx);
9785
9786 callstack_pop(ctx, FC_PUSH_VPM);
9787 return 0;
9788 }
9789
9790 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
9791 {
9792 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9793 * limited to 4096 iterations, like the other LOOP_* instructions. */
9794 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
9795
9796 fc_pushlevel(ctx, FC_LOOP);
9797
9798 /* check stack depth */
9799 callstack_push(ctx, FC_LOOP);
9800 return 0;
9801 }
9802
9803 static int tgsi_endloop(struct r600_shader_ctx *ctx)
9804 {
9805 int i;
9806
9807 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
9808
9809 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
9810 R600_ERR("loop/endloop in shader code are not paired.\n");
9811 return -EINVAL;
9812 }
9813
9814 /* fixup loop pointers - from r600isa
9815 LOOP END points to CF after LOOP START,
9816 LOOP START point to CF after LOOP END
9817 BRK/CONT point to LOOP END CF
9818 */
9819 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
9820
9821 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9822
9823 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
9824 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
9825 }
9826 /* XXX add LOOPRET support */
9827 fc_poplevel(ctx);
9828 callstack_pop(ctx, FC_LOOP);
9829 return 0;
9830 }
9831
9832 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
9833 {
9834 unsigned int fscp;
9835
9836 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
9837 {
9838 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
9839 break;
9840 }
9841
9842 if (fscp == 0) {
9843 R600_ERR("Break not inside loop/endloop pair\n");
9844 return -EINVAL;
9845 }
9846
9847 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9848
9849 fc_set_mid(ctx, fscp - 1);
9850
9851 return 0;
9852 }
9853
9854 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
9855 {
9856 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9857 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
9858 int r;
9859
9860 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9861 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
9862
9863 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9864 if (!r) {
9865 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
9866 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9867 return emit_inc_ring_offset(ctx, stream, TRUE);
9868 }
9869 return r;
9870 }
9871
9872 static int tgsi_umad(struct r600_shader_ctx *ctx)
9873 {
9874 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9875 struct r600_bytecode_alu alu;
9876 int i, j, k, r;
9877 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9878
9879 /* src0 * src1 */
9880 for (i = 0; i < lasti + 1; i++) {
9881 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9882 continue;
9883
9884 if (ctx->bc->chip_class == CAYMAN) {
9885 for (j = 0 ; j < 4; j++) {
9886 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9887
9888 alu.op = ALU_OP2_MULLO_UINT;
9889 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
9890 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
9891 }
9892 alu.dst.chan = j;
9893 alu.dst.sel = ctx->temp_reg;
9894 alu.dst.write = (j == i);
9895 if (j == 3)
9896 alu.last = 1;
9897 r = r600_bytecode_add_alu(ctx->bc, &alu);
9898 if (r)
9899 return r;
9900 }
9901 } else {
9902 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9903
9904 alu.dst.chan = i;
9905 alu.dst.sel = ctx->temp_reg;
9906 alu.dst.write = 1;
9907
9908 alu.op = ALU_OP2_MULLO_UINT;
9909 for (j = 0; j < 2; j++) {
9910 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
9911 }
9912
9913 alu.last = 1;
9914 r = r600_bytecode_add_alu(ctx->bc, &alu);
9915 if (r)
9916 return r;
9917 }
9918 }
9919
9920
9921 for (i = 0; i < lasti + 1; i++) {
9922 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9923 continue;
9924
9925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9926 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9927
9928 alu.op = ALU_OP2_ADD_INT;
9929
9930 alu.src[0].sel = ctx->temp_reg;
9931 alu.src[0].chan = i;
9932
9933 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9934 if (i == lasti) {
9935 alu.last = 1;
9936 }
9937 r = r600_bytecode_add_alu(ctx->bc, &alu);
9938 if (r)
9939 return r;
9940 }
9941 return 0;
9942 }
9943
9944 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
9945 {
9946 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9947 struct r600_bytecode_alu alu;
9948 int r, i;
9949 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9950
9951 /* temp.xy = f32_to_f16(src) */
9952 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9953 alu.op = ALU_OP1_FLT32_TO_FLT16;
9954 alu.dst.chan = 0;
9955 alu.dst.sel = ctx->temp_reg;
9956 alu.dst.write = 1;
9957 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9958 r = r600_bytecode_add_alu(ctx->bc, &alu);
9959 if (r)
9960 return r;
9961 alu.dst.chan = 1;
9962 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
9963 alu.last = 1;
9964 r = r600_bytecode_add_alu(ctx->bc, &alu);
9965 if (r)
9966 return r;
9967
9968 /* dst.x = temp.y * 0x10000 + temp.x */
9969 for (i = 0; i < lasti + 1; i++) {
9970 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9971 continue;
9972
9973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9974 alu.op = ALU_OP3_MULADD_UINT24;
9975 alu.is_op3 = 1;
9976 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9977 alu.last = i == lasti;
9978 alu.src[0].sel = ctx->temp_reg;
9979 alu.src[0].chan = 1;
9980 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9981 alu.src[1].value = 0x10000;
9982 alu.src[2].sel = ctx->temp_reg;
9983 alu.src[2].chan = 0;
9984 r = r600_bytecode_add_alu(ctx->bc, &alu);
9985 if (r)
9986 return r;
9987 }
9988
9989 return 0;
9990 }
9991
9992 static int tgsi_up2h(struct r600_shader_ctx *ctx)
9993 {
9994 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9995 struct r600_bytecode_alu alu;
9996 int r, i;
9997 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9998
9999 /* temp.x = src.x */
10000 /* note: no need to mask out the high bits */
10001 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10002 alu.op = ALU_OP1_MOV;
10003 alu.dst.chan = 0;
10004 alu.dst.sel = ctx->temp_reg;
10005 alu.dst.write = 1;
10006 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10007 r = r600_bytecode_add_alu(ctx->bc, &alu);
10008 if (r)
10009 return r;
10010
10011 /* temp.y = src.x >> 16 */
10012 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10013 alu.op = ALU_OP2_LSHR_INT;
10014 alu.dst.chan = 1;
10015 alu.dst.sel = ctx->temp_reg;
10016 alu.dst.write = 1;
10017 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10018 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10019 alu.src[1].value = 16;
10020 alu.last = 1;
10021 r = r600_bytecode_add_alu(ctx->bc, &alu);
10022 if (r)
10023 return r;
10024
10025 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
10026 for (i = 0; i < lasti + 1; i++) {
10027 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10028 continue;
10029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10030 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10031 alu.op = ALU_OP1_FLT16_TO_FLT32;
10032 alu.src[0].sel = ctx->temp_reg;
10033 alu.src[0].chan = i % 2;
10034 alu.last = i == lasti;
10035 r = r600_bytecode_add_alu(ctx->bc, &alu);
10036 if (r)
10037 return r;
10038 }
10039
10040 return 0;
10041 }
10042
10043 static int tgsi_bfe(struct r600_shader_ctx *ctx)
10044 {
10045 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10046 struct r600_bytecode_alu alu;
10047 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10048 int r, i;
10049 int dst = -1;
10050
10051 if ((inst->Src[0].Register.File == inst->Dst[0].Register.File &&
10052 inst->Src[0].Register.Index == inst->Dst[0].Register.Index) ||
10053 (inst->Src[2].Register.File == inst->Dst[0].Register.File &&
10054 inst->Src[2].Register.Index == inst->Dst[0].Register.Index))
10055 dst = r600_get_temp(ctx);
10056
10057 r = tgsi_op3_dst(ctx, dst);
10058 if (r)
10059 return r;
10060
10061 for (i = 0; i < lasti + 1; i++) {
10062 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10063 alu.op = ALU_OP2_SETGE_INT;
10064 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
10065 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10066 alu.src[1].value = 32;
10067 alu.dst.sel = ctx->temp_reg;
10068 alu.dst.chan = i;
10069 alu.dst.write = 1;
10070 if (i == lasti)
10071 alu.last = 1;
10072 r = r600_bytecode_add_alu(ctx->bc, &alu);
10073 if (r)
10074 return r;
10075 }
10076
10077 for (i = 0; i < lasti + 1; i++) {
10078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10079 alu.op = ALU_OP3_CNDE_INT;
10080 alu.is_op3 = 1;
10081 alu.src[0].sel = ctx->temp_reg;
10082 alu.src[0].chan = i;
10083
10084 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10085 if (dst != -1)
10086 alu.src[1].sel = dst;
10087 else
10088 alu.src[1].sel = alu.dst.sel;
10089 alu.src[1].chan = i;
10090 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
10091 alu.dst.write = 1;
10092 if (i == lasti)
10093 alu.last = 1;
10094 r = r600_bytecode_add_alu(ctx->bc, &alu);
10095 if (r)
10096 return r;
10097 }
10098
10099 return 0;
10100 }
10101
10102 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
10103 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
10104 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10105 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10106
10107 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
10108
10109 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
10110 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10111 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10112 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10113 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10114 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10115 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10116 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10117 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
10118 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10119 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10120 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10121 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10122 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10123 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10124 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
10125 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
10126 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10127 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10128 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10129 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10130 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10131 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10132 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10133 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
10134 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
10135 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
10136 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10137 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10138 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10139 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10140 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10141 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
10142 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10143 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10144 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10145 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
10146 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10147 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10148 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10149 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10150 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10151 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10152 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10153 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
10154 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10155 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10156 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10157 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10158 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10159 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10160 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
10161 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10162 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10163 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10164 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10165 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10166 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
10167 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10168 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10169 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10170 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10171 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10172 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10173 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10174 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10175 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10176 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10177 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10178 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10179 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10180 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10181 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10182 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10183 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10184 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
10185 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
10186 [81] = { ALU_OP0_NOP, tgsi_unsupported},
10187 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10188 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10189 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
10190 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10191 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10192 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
10193 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10194 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10195 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10196 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10197 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10198 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10199 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10200 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10201 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10202 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10203 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10204 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10205 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10206 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10207 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10208 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10209 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10210 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
10211 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10212 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10213 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10214 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10215 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10216 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10217 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
10218 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10219 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10220 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10221 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10222 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10223 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
10224 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
10225 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10226 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10227 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10228 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10229 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10230 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
10231 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10232 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
10233 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
10234 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10235 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10236 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10237 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10238 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10239 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10240 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
10241 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10242 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10243 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
10244 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10245 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
10246 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10247 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10248 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10249 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10250 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10251 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10252 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10253 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10254 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10255 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10256 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10257 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10258 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10259 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10260 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10261 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10262 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
10263 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10264 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10265 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10266 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
10267 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
10268 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10269 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10270 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10271 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
10272 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
10273 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
10274 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
10275 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
10276 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
10277 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
10278 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
10279 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
10280 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
10281 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
10282 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10283 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10284 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10285 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
10286 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
10287 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
10288 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
10289 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
10290 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
10291 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
10292 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
10293 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
10294 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
10295 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
10296 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
10297 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
10298 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
10299 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
10300 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10301 };
10302
10303 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
10304 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
10305 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10306 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10307 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
10308 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
10309 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10310 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10311 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10312 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10313 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10314 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10315 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10316 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10317 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10318 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10319 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10320 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10321 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10322 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
10323 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
10324 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10325 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10326 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10327 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10328 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10329 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10330 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10331 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
10332 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
10333 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
10334 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10335 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10336 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10337 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10338 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10339 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
10340 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10341 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10342 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10343 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
10344 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10345 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10346 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10347 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10348 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10349 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10350 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10351 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
10352 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10353 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10354 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10355 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10356 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10357 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10358 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
10359 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10360 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10361 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10362 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10363 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10364 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
10365 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10366 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10367 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10368 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10369 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10370 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10371 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10372 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10373 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10374 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10375 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10376 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10377 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10378 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10379 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10380 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10381 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10382 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10383 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10384 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10385 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10386 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
10387 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10388 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10389 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
10390 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10391 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10392 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10393 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10394 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10395 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10396 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10397 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10398 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10399 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10400 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10401 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10402 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10403 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10404 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10405 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10406 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10407 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
10408 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10409 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10410 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10411 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10412 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10413 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10414 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10415 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10416 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10417 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10418 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10419 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10420 /* Refer below for TGSI_OPCODE_DFMA */
10421 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
10422 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10423 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10424 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10425 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10426 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10427 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
10428 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10429 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
10430 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
10431 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10432 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10433 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10434 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10435 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10436 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10437 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
10438 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10439 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10440 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
10441 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10442 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
10443 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10444 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10445 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10446 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10447 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10448 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10449 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10450 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10451 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10452 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10453 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10454 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10455 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10456 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10457 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10458 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10459 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
10460 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10461 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10462 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10463 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
10464 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
10465 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10466 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10467 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10468 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10469 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
10470 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
10471 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
10472 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
10473 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
10474 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10475 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10476 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10477 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10478 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10479 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10480 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10481 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10482 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
10483 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
10484 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10485 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10486 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10487 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10488 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10489 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10490 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10491 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10492 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10493 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10494 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10495 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10496 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10497 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10498 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10499 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10500 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10501 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10502 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10503 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10504 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10505 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10506 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10507 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10508 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10509 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10510 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10511 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10512 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10513 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10514 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10515 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10516 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10517 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10518 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10519 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10520 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10521 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10522 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10523 };
10524
10525 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
10526 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
10527 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10528 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10529 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
10530 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
10531 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10532 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10533 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10534 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10535 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10536 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10537 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10538 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10539 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10540 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10541 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10542 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10543 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10544 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
10545 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
10546 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10547 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10548 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10549 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10550 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10551 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10552 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10553 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
10554 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
10555 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
10556 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10557 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10558 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10559 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10560 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10561 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
10562 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10563 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10564 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10565 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
10566 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10567 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10568 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10569 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10570 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10571 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10572 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10573 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
10574 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10575 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10576 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10577 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10578 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10579 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10580 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
10581 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10582 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10583 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10584 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10585 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10586 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
10587 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10588 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10589 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10590 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10591 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10592 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10593 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10594 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10595 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10596 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10597 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10598 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10599 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10600 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10601 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10602 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10603 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10604 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10605 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10606 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10607 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10608 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
10609 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10610 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10611 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
10612 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10613 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10614 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10615 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10616 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10617 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10618 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10619 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10620 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10621 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10622 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10623 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10624 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10625 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10626 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10627 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10628 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10629 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
10630 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10631 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10632 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10633 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10634 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10635 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10636 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10637 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10638 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10639 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10640 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10641 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10642 /* Refer below for TGSI_OPCODE_DFMA */
10643 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
10644 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10645 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10646 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10647 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10648 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10649 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
10650 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10651 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
10652 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
10653 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10654 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10655 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10656 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10657 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10658 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10659 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
10660 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10661 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10662 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
10663 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10664 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
10665 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10666 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10667 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10668 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10669 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10670 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10671 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10672 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10673 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10674 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10675 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10676 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10677 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10678 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10679 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10680 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10681 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
10682 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10683 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10684 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10685 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
10686 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
10687 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10688 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10689 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10690 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10691 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
10692 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
10693 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
10694 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
10695 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
10696 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10697 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10698 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10699 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10700 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10701 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10702 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10703 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10704 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
10705 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
10706 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10707 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10708 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10709 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10710 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10711 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10712 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10713 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10714 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10715 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10716 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10717 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10718 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10719 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10720 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10721 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10722 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10723 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10724 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10725 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10726 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10727 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10728 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10729 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10730 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10731 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10732 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10733 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10734 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10735 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10736 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10737 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10738 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10739 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10740 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10741 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10742 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10743 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10744 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10745 };