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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
88 {
89 struct tgsi_parse_context parse;
90
91 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
92 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
93 return ~0;
94 }
95 return parse.FullHeader.Processor.Processor;
96 }
97
98 static bool r600_can_dump_shader(struct r600_screen *rscreen, unsigned processor_type)
99 {
100 switch (processor_type) {
101 case TGSI_PROCESSOR_VERTEX:
102 return (rscreen->debug_flags & DBG_VS) != 0;
103 case TGSI_PROCESSOR_GEOMETRY:
104 return (rscreen->debug_flags & DBG_GS) != 0;
105 case TGSI_PROCESSOR_FRAGMENT:
106 return (rscreen->debug_flags & DBG_PS) != 0;
107 case TGSI_PROCESSOR_COMPUTE:
108 return (rscreen->debug_flags & DBG_CS) != 0;
109 default:
110 return false;
111 }
112 }
113
114 static void r600_dump_streamout(struct pipe_stream_output_info *so)
115 {
116 unsigned i;
117
118 fprintf(stderr, "STREAMOUT\n");
119 for (i = 0; i < so->num_outputs; i++) {
120 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
121 so->output[i].start_component;
122 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
123 i, so->output[i].output_buffer,
124 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
125 so->output[i].register_index,
126 mask & 1 ? "x" : "",
127 mask & 2 ? "y" : "",
128 mask & 4 ? "z" : "",
129 mask & 8 ? "w" : "",
130 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
131 }
132 }
133
134 int r600_pipe_shader_create(struct pipe_context *ctx,
135 struct r600_pipe_shader *shader,
136 struct r600_shader_key key)
137 {
138 struct r600_context *rctx = (struct r600_context *)ctx;
139 struct r600_pipe_shader_selector *sel = shader->selector;
140 int r, i;
141 uint32_t *ptr;
142 bool dump = r600_can_dump_shader(rctx->screen, tgsi_get_processor_type(sel->tokens));
143 unsigned use_sb = rctx->screen->debug_flags & DBG_SB;
144 unsigned sb_disasm = use_sb || (rctx->screen->debug_flags & DBG_SB_DISASM);
145
146 shader->shader.bc.isa = rctx->isa;
147
148 if (dump) {
149 fprintf(stderr, "--------------------------------------------------------------\n");
150 tgsi_dump(sel->tokens, 0);
151
152 if (sel->so.num_outputs) {
153 r600_dump_streamout(&sel->so);
154 }
155 }
156 r = r600_shader_from_tgsi(rctx->screen, shader, key);
157 if (r) {
158 R600_ERR("translation from TGSI failed !\n");
159 return r;
160 }
161
162 /* Check if the bytecode has already been built. When using the llvm
163 * backend, r600_shader_from_tgsi() will take care of building the
164 * bytecode.
165 */
166 if (!shader->shader.bc.bytecode) {
167 r = r600_bytecode_build(&shader->shader.bc);
168 if (r) {
169 R600_ERR("building bytecode failed !\n");
170 return r;
171 }
172 }
173
174 if (dump && !sb_disasm) {
175 fprintf(stderr, "--------------------------------------------------------------\n");
176 r600_bytecode_disasm(&shader->shader.bc);
177 fprintf(stderr, "______________________________________________________________\n");
178 } else if ((dump && sb_disasm) || use_sb) {
179 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
180 dump, use_sb);
181 if (r) {
182 R600_ERR("r600_sb_bytecode_process failed !\n");
183 return r;
184 }
185 }
186
187 /* Store the shader in a buffer. */
188 if (shader->bo == NULL) {
189 shader->bo = (struct r600_resource*)
190 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
191 if (shader->bo == NULL) {
192 return -ENOMEM;
193 }
194 ptr = r600_buffer_mmap_sync_with_rings(rctx, shader->bo, PIPE_TRANSFER_WRITE);
195 if (R600_BIG_ENDIAN) {
196 for (i = 0; i < shader->shader.bc.ndw; ++i) {
197 ptr[i] = util_bswap32(shader->shader.bc.bytecode[i]);
198 }
199 } else {
200 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
201 }
202 rctx->ws->buffer_unmap(shader->bo->cs_buf);
203 }
204
205 /* Build state. */
206 switch (shader->shader.processor_type) {
207 case TGSI_PROCESSOR_VERTEX:
208 if (rctx->chip_class >= EVERGREEN) {
209 evergreen_update_vs_state(ctx, shader);
210 } else {
211 r600_update_vs_state(ctx, shader);
212 }
213 break;
214 case TGSI_PROCESSOR_FRAGMENT:
215 if (rctx->chip_class >= EVERGREEN) {
216 evergreen_update_ps_state(ctx, shader);
217 } else {
218 r600_update_ps_state(ctx, shader);
219 }
220 break;
221 default:
222 return -EINVAL;
223 }
224 return 0;
225 }
226
227 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
228 {
229 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
230 r600_bytecode_clear(&shader->shader.bc);
231 r600_release_command_buffer(&shader->command_buffer);
232 }
233
234 /*
235 * tgsi -> r600 shader
236 */
237 struct r600_shader_tgsi_instruction;
238
239 struct r600_shader_src {
240 unsigned sel;
241 unsigned swizzle[4];
242 unsigned neg;
243 unsigned abs;
244 unsigned rel;
245 unsigned kc_bank;
246 uint32_t value[4];
247 };
248
249 struct r600_shader_ctx {
250 struct tgsi_shader_info info;
251 struct tgsi_parse_context parse;
252 const struct tgsi_token *tokens;
253 unsigned type;
254 unsigned file_offset[TGSI_FILE_COUNT];
255 unsigned temp_reg;
256 struct r600_shader_tgsi_instruction *inst_info;
257 struct r600_bytecode *bc;
258 struct r600_shader *shader;
259 struct r600_shader_src src[4];
260 uint32_t *literals;
261 uint32_t nliterals;
262 uint32_t max_driver_temp_used;
263 boolean use_llvm;
264 /* needed for evergreen interpolation */
265 boolean input_centroid;
266 boolean input_linear;
267 boolean input_perspective;
268 int num_interp_gpr;
269 int face_gpr;
270 int colors_used;
271 boolean clip_vertex_write;
272 unsigned cv_output;
273 int fragcoord_input;
274 int native_integers;
275 };
276
277 struct r600_shader_tgsi_instruction {
278 unsigned tgsi_opcode;
279 unsigned is_op3;
280 unsigned op;
281 int (*process)(struct r600_shader_ctx *ctx);
282 };
283
284 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
285 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
286 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
287 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
288 static int tgsi_else(struct r600_shader_ctx *ctx);
289 static int tgsi_endif(struct r600_shader_ctx *ctx);
290 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
291 static int tgsi_endloop(struct r600_shader_ctx *ctx);
292 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
293
294 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
295 {
296 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
297 int j;
298
299 if (i->Instruction.NumDstRegs > 1) {
300 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
301 return -EINVAL;
302 }
303 if (i->Instruction.Predicate) {
304 R600_ERR("predicate unsupported\n");
305 return -EINVAL;
306 }
307 #if 0
308 if (i->Instruction.Label) {
309 R600_ERR("label unsupported\n");
310 return -EINVAL;
311 }
312 #endif
313 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
314 if (i->Src[j].Register.Dimension) {
315 if (i->Src[j].Register.File != TGSI_FILE_CONSTANT) {
316 R600_ERR("unsupported src %d (dimension %d)\n", j,
317 i->Src[j].Register.Dimension);
318 return -EINVAL;
319 }
320 }
321 }
322 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
323 if (i->Dst[j].Register.Dimension) {
324 R600_ERR("unsupported dst (dimension)\n");
325 return -EINVAL;
326 }
327 }
328 return 0;
329 }
330
331 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
332 int input)
333 {
334 int ij_index = 0;
335
336 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
337 if (ctx->shader->input[input].centroid)
338 ij_index++;
339 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
340 /* if we have perspective add one */
341 if (ctx->input_perspective) {
342 ij_index++;
343 /* if we have perspective centroid */
344 if (ctx->input_centroid)
345 ij_index++;
346 }
347 if (ctx->shader->input[input].centroid)
348 ij_index++;
349 }
350
351 ctx->shader->input[input].ij_index = ij_index;
352 }
353
354 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
355 {
356 int i, r;
357 struct r600_bytecode_alu alu;
358 int gpr = 0, base_chan = 0;
359 int ij_index = ctx->shader->input[input].ij_index;
360
361 /* work out gpr and base_chan from index */
362 gpr = ij_index / 2;
363 base_chan = (2 * (ij_index % 2)) + 1;
364
365 for (i = 0; i < 8; i++) {
366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
367
368 if (i < 4)
369 alu.op = ALU_OP2_INTERP_ZW;
370 else
371 alu.op = ALU_OP2_INTERP_XY;
372
373 if ((i > 1) && (i < 6)) {
374 alu.dst.sel = ctx->shader->input[input].gpr;
375 alu.dst.write = 1;
376 }
377
378 alu.dst.chan = i % 4;
379
380 alu.src[0].sel = gpr;
381 alu.src[0].chan = (base_chan - (i % 2));
382
383 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
384
385 alu.bank_swizzle_force = SQ_ALU_VEC_210;
386 if ((i % 4) == 3)
387 alu.last = 1;
388 r = r600_bytecode_add_alu(ctx->bc, &alu);
389 if (r)
390 return r;
391 }
392 return 0;
393 }
394
395 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
396 {
397 int i, r;
398 struct r600_bytecode_alu alu;
399
400 for (i = 0; i < 4; i++) {
401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
402
403 alu.op = ALU_OP1_INTERP_LOAD_P0;
404
405 alu.dst.sel = ctx->shader->input[input].gpr;
406 alu.dst.write = 1;
407
408 alu.dst.chan = i;
409
410 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
411 alu.src[0].chan = i;
412
413 if (i == 3)
414 alu.last = 1;
415 r = r600_bytecode_add_alu(ctx->bc, &alu);
416 if (r)
417 return r;
418 }
419 return 0;
420 }
421
422 /*
423 * Special export handling in shaders
424 *
425 * shader export ARRAY_BASE for EXPORT_POS:
426 * 60 is position
427 * 61 is misc vector
428 * 62, 63 are clip distance vectors
429 *
430 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
431 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
432 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
433 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
434 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
435 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
436 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
437 * exclusive from render target index)
438 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
439 *
440 *
441 * shader export ARRAY_BASE for EXPORT_PIXEL:
442 * 0-7 CB targets
443 * 61 computed Z vector
444 *
445 * The use of the values exported in the computed Z vector are controlled
446 * by DB_SHADER_CONTROL:
447 * Z_EXPORT_ENABLE - Z as a float in RED
448 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
449 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
450 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
451 * DB_SOURCE_FORMAT - export control restrictions
452 *
453 */
454
455
456 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
457 static int r600_spi_sid(struct r600_shader_io * io)
458 {
459 int index, name = io->name;
460
461 /* These params are handled differently, they don't need
462 * semantic indices, so we'll use 0 for them.
463 */
464 if (name == TGSI_SEMANTIC_POSITION ||
465 name == TGSI_SEMANTIC_PSIZE ||
466 name == TGSI_SEMANTIC_FACE)
467 index = 0;
468 else {
469 if (name == TGSI_SEMANTIC_GENERIC) {
470 /* For generic params simply use sid from tgsi */
471 index = io->sid;
472 } else {
473 /* For non-generic params - pack name and sid into 8 bits */
474 index = 0x80 | (name<<3) | (io->sid);
475 }
476
477 /* Make sure that all really used indices have nonzero value, so
478 * we can just compare it to 0 later instead of comparing the name
479 * with different values to detect special cases. */
480 index++;
481 }
482
483 return index;
484 };
485
486 /* turn input into interpolate on EG */
487 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
488 {
489 int r = 0;
490
491 if (ctx->shader->input[index].spi_sid) {
492 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
493 if (ctx->shader->input[index].interpolate > 0) {
494 evergreen_interp_assign_ij_index(ctx, index);
495 if (!ctx->use_llvm)
496 r = evergreen_interp_alu(ctx, index);
497 } else {
498 if (!ctx->use_llvm)
499 r = evergreen_interp_flat(ctx, index);
500 }
501 }
502 return r;
503 }
504
505 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
506 {
507 struct r600_bytecode_alu alu;
508 int i, r;
509 int gpr_front = ctx->shader->input[front].gpr;
510 int gpr_back = ctx->shader->input[back].gpr;
511
512 for (i = 0; i < 4; i++) {
513 memset(&alu, 0, sizeof(alu));
514 alu.op = ALU_OP3_CNDGT;
515 alu.is_op3 = 1;
516 alu.dst.write = 1;
517 alu.dst.sel = gpr_front;
518 alu.src[0].sel = ctx->face_gpr;
519 alu.src[1].sel = gpr_front;
520 alu.src[2].sel = gpr_back;
521
522 alu.dst.chan = i;
523 alu.src[1].chan = i;
524 alu.src[2].chan = i;
525 alu.last = (i==3);
526
527 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
528 return r;
529 }
530
531 return 0;
532 }
533
534 static int tgsi_declaration(struct r600_shader_ctx *ctx)
535 {
536 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
537 int r, i, j, count = d->Range.Last - d->Range.First + 1;
538
539 switch (d->Declaration.File) {
540 case TGSI_FILE_INPUT:
541 i = ctx->shader->ninput;
542 assert(i < Elements(ctx->shader->input));
543 ctx->shader->ninput += count;
544 ctx->shader->input[i].name = d->Semantic.Name;
545 ctx->shader->input[i].sid = d->Semantic.Index;
546 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
547 ctx->shader->input[i].centroid = d->Interp.Centroid;
548 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
549 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
550 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
551 switch (ctx->shader->input[i].name) {
552 case TGSI_SEMANTIC_FACE:
553 ctx->face_gpr = ctx->shader->input[i].gpr;
554 break;
555 case TGSI_SEMANTIC_COLOR:
556 ctx->colors_used++;
557 break;
558 case TGSI_SEMANTIC_POSITION:
559 ctx->fragcoord_input = i;
560 break;
561 }
562 if (ctx->bc->chip_class >= EVERGREEN) {
563 if ((r = evergreen_interp_input(ctx, i)))
564 return r;
565 }
566 }
567 for (j = 1; j < count; ++j) {
568 ctx->shader->input[i + j] = ctx->shader->input[i];
569 ctx->shader->input[i + j].gpr += j;
570 }
571 break;
572 case TGSI_FILE_OUTPUT:
573 i = ctx->shader->noutput++;
574 assert(i < Elements(ctx->shader->output));
575 ctx->shader->output[i].name = d->Semantic.Name;
576 ctx->shader->output[i].sid = d->Semantic.Index;
577 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
578 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
579 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
580 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
581 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
582 switch (d->Semantic.Name) {
583 case TGSI_SEMANTIC_CLIPDIST:
584 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
585 break;
586 case TGSI_SEMANTIC_PSIZE:
587 ctx->shader->vs_out_misc_write = 1;
588 ctx->shader->vs_out_point_size = 1;
589 break;
590 case TGSI_SEMANTIC_CLIPVERTEX:
591 ctx->clip_vertex_write = TRUE;
592 ctx->cv_output = i;
593 break;
594 }
595 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
596 switch (d->Semantic.Name) {
597 case TGSI_SEMANTIC_COLOR:
598 ctx->shader->nr_ps_max_color_exports++;
599 break;
600 }
601 }
602 break;
603 case TGSI_FILE_TEMPORARY:
604 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
605 if (d->Array.ArrayID) {
606 r600_add_gpr_array(ctx->shader,
607 ctx->file_offset[TGSI_FILE_TEMPORARY] +
608 d->Range.First,
609 d->Range.Last - d->Range.First + 1, 0x0F);
610 }
611 }
612 break;
613
614 case TGSI_FILE_CONSTANT:
615 case TGSI_FILE_SAMPLER:
616 case TGSI_FILE_ADDRESS:
617 break;
618
619 case TGSI_FILE_SYSTEM_VALUE:
620 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
621 if (!ctx->native_integers) {
622 struct r600_bytecode_alu alu;
623 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
624
625 alu.op = ALU_OP1_INT_TO_FLT;
626 alu.src[0].sel = 0;
627 alu.src[0].chan = 3;
628
629 alu.dst.sel = 0;
630 alu.dst.chan = 3;
631 alu.dst.write = 1;
632 alu.last = 1;
633
634 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
635 return r;
636 }
637 break;
638 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
639 break;
640 default:
641 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
642 return -EINVAL;
643 }
644 return 0;
645 }
646
647 static int r600_get_temp(struct r600_shader_ctx *ctx)
648 {
649 return ctx->temp_reg + ctx->max_driver_temp_used++;
650 }
651
652 /*
653 * for evergreen we need to scan the shader to find the number of GPRs we need to
654 * reserve for interpolation.
655 *
656 * we need to know if we are going to emit
657 * any centroid inputs
658 * if perspective and linear are required
659 */
660 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
661 {
662 int i;
663 int num_baryc;
664
665 ctx->input_linear = FALSE;
666 ctx->input_perspective = FALSE;
667 ctx->input_centroid = FALSE;
668 ctx->num_interp_gpr = 1;
669
670 /* any centroid inputs */
671 for (i = 0; i < ctx->info.num_inputs; i++) {
672 /* skip position/face */
673 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
674 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
675 continue;
676 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
677 ctx->input_linear = TRUE;
678 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
679 ctx->input_perspective = TRUE;
680 if (ctx->info.input_centroid[i])
681 ctx->input_centroid = TRUE;
682 }
683
684 num_baryc = 0;
685 /* ignoring sample for now */
686 if (ctx->input_perspective)
687 num_baryc++;
688 if (ctx->input_linear)
689 num_baryc++;
690 if (ctx->input_centroid)
691 num_baryc *= 2;
692
693 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
694
695 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
696 return ctx->num_interp_gpr;
697 }
698
699 static void tgsi_src(struct r600_shader_ctx *ctx,
700 const struct tgsi_full_src_register *tgsi_src,
701 struct r600_shader_src *r600_src)
702 {
703 memset(r600_src, 0, sizeof(*r600_src));
704 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
705 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
706 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
707 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
708 r600_src->neg = tgsi_src->Register.Negate;
709 r600_src->abs = tgsi_src->Register.Absolute;
710
711 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
712 int index;
713 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
714 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
715 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
716
717 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
718 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
719 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
720 return;
721 }
722 index = tgsi_src->Register.Index;
723 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
724 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
725 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
726 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
727 r600_src->swizzle[0] = 3;
728 r600_src->swizzle[1] = 3;
729 r600_src->swizzle[2] = 3;
730 r600_src->swizzle[3] = 3;
731 r600_src->sel = 0;
732 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
733 r600_src->swizzle[0] = 0;
734 r600_src->swizzle[1] = 0;
735 r600_src->swizzle[2] = 0;
736 r600_src->swizzle[3] = 0;
737 r600_src->sel = 0;
738 }
739 } else {
740 if (tgsi_src->Register.Indirect)
741 r600_src->rel = V_SQ_REL_RELATIVE;
742 r600_src->sel = tgsi_src->Register.Index;
743 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
744 }
745 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
746 if (tgsi_src->Register.Dimension) {
747 r600_src->kc_bank = tgsi_src->Dimension.Index;
748 }
749 }
750 }
751
752 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
753 {
754 struct r600_bytecode_vtx vtx;
755 unsigned int ar_reg;
756 int r;
757
758 if (offset) {
759 struct r600_bytecode_alu alu;
760
761 memset(&alu, 0, sizeof(alu));
762
763 alu.op = ALU_OP2_ADD_INT;
764 alu.src[0].sel = ctx->bc->ar_reg;
765
766 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
767 alu.src[1].value = offset;
768
769 alu.dst.sel = dst_reg;
770 alu.dst.write = 1;
771 alu.last = 1;
772
773 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
774 return r;
775
776 ar_reg = dst_reg;
777 } else {
778 ar_reg = ctx->bc->ar_reg;
779 }
780
781 memset(&vtx, 0, sizeof(vtx));
782 vtx.buffer_id = cb_idx;
783 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
784 vtx.src_gpr = ar_reg;
785 vtx.mega_fetch_count = 16;
786 vtx.dst_gpr = dst_reg;
787 vtx.dst_sel_x = 0; /* SEL_X */
788 vtx.dst_sel_y = 1; /* SEL_Y */
789 vtx.dst_sel_z = 2; /* SEL_Z */
790 vtx.dst_sel_w = 3; /* SEL_W */
791 vtx.data_format = FMT_32_32_32_32_FLOAT;
792 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
793 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
794 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
795 vtx.endian = r600_endian_swap(32);
796
797 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
798 return r;
799
800 return 0;
801 }
802
803 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
804 {
805 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
806 struct r600_bytecode_alu alu;
807 int i, j, k, nconst, r;
808
809 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
810 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
811 nconst++;
812 }
813 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
814 }
815 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
816 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
817 continue;
818 }
819
820 if (ctx->src[i].rel) {
821 int treg = r600_get_temp(ctx);
822 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
823 return r;
824
825 ctx->src[i].kc_bank = 0;
826 ctx->src[i].sel = treg;
827 ctx->src[i].rel = 0;
828 j--;
829 } else if (j > 0) {
830 int treg = r600_get_temp(ctx);
831 for (k = 0; k < 4; k++) {
832 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
833 alu.op = ALU_OP1_MOV;
834 alu.src[0].sel = ctx->src[i].sel;
835 alu.src[0].chan = k;
836 alu.src[0].rel = ctx->src[i].rel;
837 alu.dst.sel = treg;
838 alu.dst.chan = k;
839 alu.dst.write = 1;
840 if (k == 3)
841 alu.last = 1;
842 r = r600_bytecode_add_alu(ctx->bc, &alu);
843 if (r)
844 return r;
845 }
846 ctx->src[i].sel = treg;
847 ctx->src[i].rel =0;
848 j--;
849 }
850 }
851 return 0;
852 }
853
854 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
855 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
856 {
857 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
858 struct r600_bytecode_alu alu;
859 int i, j, k, nliteral, r;
860
861 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
862 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
863 nliteral++;
864 }
865 }
866 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
867 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
868 int treg = r600_get_temp(ctx);
869 for (k = 0; k < 4; k++) {
870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
871 alu.op = ALU_OP1_MOV;
872 alu.src[0].sel = ctx->src[i].sel;
873 alu.src[0].chan = k;
874 alu.src[0].value = ctx->src[i].value[k];
875 alu.dst.sel = treg;
876 alu.dst.chan = k;
877 alu.dst.write = 1;
878 if (k == 3)
879 alu.last = 1;
880 r = r600_bytecode_add_alu(ctx->bc, &alu);
881 if (r)
882 return r;
883 }
884 ctx->src[i].sel = treg;
885 j--;
886 }
887 }
888 return 0;
889 }
890
891 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
892 {
893 int i, r, count = ctx->shader->ninput;
894
895 for (i = 0; i < count; i++) {
896 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
897 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
898 if (r)
899 return r;
900 }
901 }
902 return 0;
903 }
904
905
906 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
907 struct r600_pipe_shader *pipeshader,
908 struct r600_shader_key key)
909 {
910 struct r600_shader *shader = &pipeshader->shader;
911 struct tgsi_token *tokens = pipeshader->selector->tokens;
912 struct pipe_stream_output_info so = pipeshader->selector->so;
913 struct tgsi_full_immediate *immediate;
914 struct tgsi_full_property *property;
915 struct r600_shader_ctx ctx;
916 struct r600_bytecode_output output[32];
917 unsigned output_done, noutput;
918 unsigned opcode;
919 int i, j, k, r = 0;
920 int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
921 /* Declarations used by llvm code */
922 bool use_llvm = false;
923 bool indirect_gprs;
924
925 #ifdef R600_USE_LLVM
926 use_llvm = !(rscreen->debug_flags & DBG_NO_LLVM);
927 #endif
928 ctx.bc = &shader->bc;
929 ctx.shader = shader;
930 ctx.native_integers = true;
931
932 r600_bytecode_init(ctx.bc, rscreen->chip_class, rscreen->family,
933 rscreen->has_compressed_msaa_texturing);
934 ctx.tokens = tokens;
935 tgsi_scan_shader(tokens, &ctx.info);
936 shader->indirect_files = ctx.info.indirect_files;
937 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
938 tgsi_parse_init(&ctx.parse, tokens);
939 ctx.type = ctx.parse.FullHeader.Processor.Processor;
940 shader->processor_type = ctx.type;
941 ctx.bc->type = shader->processor_type;
942
943 ctx.face_gpr = -1;
944 ctx.fragcoord_input = -1;
945 ctx.colors_used = 0;
946 ctx.clip_vertex_write = 0;
947
948 shader->nr_ps_color_exports = 0;
949 shader->nr_ps_max_color_exports = 0;
950
951 shader->two_side = key.color_two_side;
952
953 /* register allocations */
954 /* Values [0,127] correspond to GPR[0..127].
955 * Values [128,159] correspond to constant buffer bank 0
956 * Values [160,191] correspond to constant buffer bank 1
957 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
958 * Values [256,287] correspond to constant buffer bank 2 (EG)
959 * Values [288,319] correspond to constant buffer bank 3 (EG)
960 * Other special values are shown in the list below.
961 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
962 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
963 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
964 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
965 * 248 SQ_ALU_SRC_0: special constant 0.0.
966 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
967 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
968 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
969 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
970 * 253 SQ_ALU_SRC_LITERAL: literal constant.
971 * 254 SQ_ALU_SRC_PV: previous vector result.
972 * 255 SQ_ALU_SRC_PS: previous scalar result.
973 */
974 for (i = 0; i < TGSI_FILE_COUNT; i++) {
975 ctx.file_offset[i] = 0;
976 }
977
978 #ifdef R600_USE_LLVM
979 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
980 fprintf(stderr, "Warning: R600 LLVM backend does not support "
981 "indirect adressing. Falling back to TGSI "
982 "backend.\n");
983 use_llvm = 0;
984 }
985 #endif
986 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
987 ctx.file_offset[TGSI_FILE_INPUT] = 1;
988 if (!use_llvm) {
989 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
990 }
991 }
992 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
993 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
994 }
995 ctx.use_llvm = use_llvm;
996
997 if (use_llvm) {
998 ctx.file_offset[TGSI_FILE_OUTPUT] =
999 ctx.file_offset[TGSI_FILE_INPUT];
1000 } else {
1001 ctx.file_offset[TGSI_FILE_OUTPUT] =
1002 ctx.file_offset[TGSI_FILE_INPUT] +
1003 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1004 }
1005 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1006 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1007
1008 /* Outside the GPR range. This will be translated to one of the
1009 * kcache banks later. */
1010 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1011
1012 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1013 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1014 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1015 ctx.temp_reg = ctx.bc->ar_reg + 1;
1016
1017 if (indirect_gprs) {
1018 shader->max_arrays = 0;
1019 shader->num_arrays = 0;
1020
1021 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1022 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1023 ctx.file_offset[TGSI_FILE_OUTPUT] -
1024 ctx.file_offset[TGSI_FILE_INPUT],
1025 0x0F);
1026 }
1027 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1028 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1029 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1030 ctx.file_offset[TGSI_FILE_OUTPUT],
1031 0x0F);
1032 }
1033 }
1034
1035 ctx.nliterals = 0;
1036 ctx.literals = NULL;
1037 shader->fs_write_all = FALSE;
1038 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1039 tgsi_parse_token(&ctx.parse);
1040 switch (ctx.parse.FullToken.Token.Type) {
1041 case TGSI_TOKEN_TYPE_IMMEDIATE:
1042 immediate = &ctx.parse.FullToken.FullImmediate;
1043 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1044 if(ctx.literals == NULL) {
1045 r = -ENOMEM;
1046 goto out_err;
1047 }
1048 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1049 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1050 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1051 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1052 ctx.nliterals++;
1053 break;
1054 case TGSI_TOKEN_TYPE_DECLARATION:
1055 r = tgsi_declaration(&ctx);
1056 if (r)
1057 goto out_err;
1058 break;
1059 case TGSI_TOKEN_TYPE_INSTRUCTION:
1060 break;
1061 case TGSI_TOKEN_TYPE_PROPERTY:
1062 property = &ctx.parse.FullToken.FullProperty;
1063 switch (property->Property.PropertyName) {
1064 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1065 if (property->u[0].Data == 1)
1066 shader->fs_write_all = TRUE;
1067 break;
1068 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1069 /* we don't need this one */
1070 break;
1071 }
1072 break;
1073 default:
1074 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1075 r = -EINVAL;
1076 goto out_err;
1077 }
1078 }
1079
1080 /* Process two side if needed */
1081 if (shader->two_side && ctx.colors_used) {
1082 int i, count = ctx.shader->ninput;
1083 unsigned next_lds_loc = ctx.shader->nlds;
1084
1085 /* additional inputs will be allocated right after the existing inputs,
1086 * we won't need them after the color selection, so we don't need to
1087 * reserve these gprs for the rest of the shader code and to adjust
1088 * output offsets etc. */
1089 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1090 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1091
1092 if (ctx.face_gpr == -1) {
1093 i = ctx.shader->ninput++;
1094 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1095 ctx.shader->input[i].spi_sid = 0;
1096 ctx.shader->input[i].gpr = gpr++;
1097 ctx.face_gpr = ctx.shader->input[i].gpr;
1098 }
1099
1100 for (i = 0; i < count; i++) {
1101 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1102 int ni = ctx.shader->ninput++;
1103 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1104 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1105 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1106 ctx.shader->input[ni].gpr = gpr++;
1107 // TGSI to LLVM needs to know the lds position of inputs.
1108 // Non LLVM path computes it later (in process_twoside_color)
1109 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1110 ctx.shader->input[i].back_color_input = ni;
1111 if (ctx.bc->chip_class >= EVERGREEN) {
1112 if ((r = evergreen_interp_input(&ctx, ni)))
1113 return r;
1114 }
1115 }
1116 }
1117 }
1118
1119 /* LLVM backend setup */
1120 #ifdef R600_USE_LLVM
1121 if (use_llvm) {
1122 struct radeon_llvm_context radeon_llvm_ctx;
1123 LLVMModuleRef mod;
1124 bool dump = r600_can_dump_shader(rscreen, ctx.type);
1125 boolean use_kill = false;
1126
1127 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1128 radeon_llvm_ctx.type = ctx.type;
1129 radeon_llvm_ctx.two_side = shader->two_side;
1130 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1131 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1132 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1133 radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
1134 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1135 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
1136 radeon_llvm_ctx.stream_outputs = &so;
1137 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1138 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1139 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1140 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
1141
1142 if (r600_llvm_compile(mod, rscreen->family, ctx.bc, &use_kill, dump)) {
1143 radeon_llvm_dispose(&radeon_llvm_ctx);
1144 use_llvm = 0;
1145 fprintf(stderr, "R600 LLVM backend failed to compile "
1146 "shader. Falling back to TGSI\n");
1147 } else {
1148 ctx.file_offset[TGSI_FILE_OUTPUT] =
1149 ctx.file_offset[TGSI_FILE_INPUT];
1150 }
1151 if (use_kill)
1152 ctx.shader->uses_kill = use_kill;
1153 radeon_llvm_dispose(&radeon_llvm_ctx);
1154 }
1155 #endif
1156 /* End of LLVM backend setup */
1157
1158 if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
1159 shader->nr_ps_max_color_exports = 8;
1160
1161 if (!use_llvm) {
1162 if (ctx.fragcoord_input >= 0) {
1163 if (ctx.bc->chip_class == CAYMAN) {
1164 for (j = 0 ; j < 4; j++) {
1165 struct r600_bytecode_alu alu;
1166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1167 alu.op = ALU_OP1_RECIP_IEEE;
1168 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1169 alu.src[0].chan = 3;
1170
1171 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1172 alu.dst.chan = j;
1173 alu.dst.write = (j == 3);
1174 alu.last = 1;
1175 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1176 return r;
1177 }
1178 } else {
1179 struct r600_bytecode_alu alu;
1180 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1181 alu.op = ALU_OP1_RECIP_IEEE;
1182 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1183 alu.src[0].chan = 3;
1184
1185 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1186 alu.dst.chan = 3;
1187 alu.dst.write = 1;
1188 alu.last = 1;
1189 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1190 return r;
1191 }
1192 }
1193
1194 if (shader->two_side && ctx.colors_used) {
1195 if ((r = process_twoside_color_inputs(&ctx)))
1196 return r;
1197 }
1198
1199 tgsi_parse_init(&ctx.parse, tokens);
1200 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1201 tgsi_parse_token(&ctx.parse);
1202 switch (ctx.parse.FullToken.Token.Type) {
1203 case TGSI_TOKEN_TYPE_INSTRUCTION:
1204 r = tgsi_is_supported(&ctx);
1205 if (r)
1206 goto out_err;
1207 ctx.max_driver_temp_used = 0;
1208 /* reserve first tmp for everyone */
1209 r600_get_temp(&ctx);
1210
1211 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1212 if ((r = tgsi_split_constant(&ctx)))
1213 goto out_err;
1214 if ((r = tgsi_split_literal_constant(&ctx)))
1215 goto out_err;
1216 if (ctx.bc->chip_class == CAYMAN)
1217 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1218 else if (ctx.bc->chip_class >= EVERGREEN)
1219 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1220 else
1221 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1222 r = ctx.inst_info->process(&ctx);
1223 if (r)
1224 goto out_err;
1225 break;
1226 default:
1227 break;
1228 }
1229 }
1230 }
1231
1232 /* Reset the temporary register counter. */
1233 ctx.max_driver_temp_used = 0;
1234
1235 noutput = shader->noutput;
1236
1237 if (ctx.clip_vertex_write) {
1238 unsigned clipdist_temp[2];
1239
1240 clipdist_temp[0] = r600_get_temp(&ctx);
1241 clipdist_temp[1] = r600_get_temp(&ctx);
1242
1243 /* need to convert a clipvertex write into clipdistance writes and not export
1244 the clip vertex anymore */
1245
1246 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1247 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1248 shader->output[noutput].gpr = clipdist_temp[0];
1249 noutput++;
1250 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1251 shader->output[noutput].gpr = clipdist_temp[1];
1252 noutput++;
1253
1254 /* reset spi_sid for clipvertex output to avoid confusing spi */
1255 shader->output[ctx.cv_output].spi_sid = 0;
1256
1257 shader->clip_dist_write = 0xFF;
1258
1259 for (i = 0; i < 8; i++) {
1260 int oreg = i >> 2;
1261 int ochan = i & 3;
1262
1263 for (j = 0; j < 4; j++) {
1264 struct r600_bytecode_alu alu;
1265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1266 alu.op = ALU_OP2_DOT4;
1267 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1268 alu.src[0].chan = j;
1269
1270 alu.src[1].sel = 512 + i;
1271 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1272 alu.src[1].chan = j;
1273
1274 alu.dst.sel = clipdist_temp[oreg];
1275 alu.dst.chan = j;
1276 alu.dst.write = (j == ochan);
1277 if (j == 3)
1278 alu.last = 1;
1279 if (!use_llvm)
1280 r = r600_bytecode_add_alu(ctx.bc, &alu);
1281 if (r)
1282 return r;
1283 }
1284 }
1285 }
1286
1287 /* Add stream outputs. */
1288 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
1289 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1290
1291 /* Sanity checking. */
1292 if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1293 R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
1294 r = -EINVAL;
1295 goto out_err;
1296 }
1297 for (i = 0; i < so.num_outputs; i++) {
1298 if (so.output[i].output_buffer >= 4) {
1299 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1300 so.output[i].output_buffer);
1301 r = -EINVAL;
1302 goto out_err;
1303 }
1304 }
1305
1306 /* Initialize locations where the outputs are stored. */
1307 for (i = 0; i < so.num_outputs; i++) {
1308 so_gpr[i] = shader->output[so.output[i].register_index].gpr;
1309
1310 /* Lower outputs with dst_offset < start_component.
1311 *
1312 * We can only output 4D vectors with a write mask, e.g. we can
1313 * only output the W component at offset 3, etc. If we want
1314 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1315 * to move it to X and output X. */
1316 if (so.output[i].dst_offset < so.output[i].start_component) {
1317 unsigned tmp = r600_get_temp(&ctx);
1318
1319 for (j = 0; j < so.output[i].num_components; j++) {
1320 struct r600_bytecode_alu alu;
1321 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1322 alu.op = ALU_OP1_MOV;
1323 alu.src[0].sel = so_gpr[i];
1324 alu.src[0].chan = so.output[i].start_component + j;
1325
1326 alu.dst.sel = tmp;
1327 alu.dst.chan = j;
1328 alu.dst.write = 1;
1329 if (j == so.output[i].num_components - 1)
1330 alu.last = 1;
1331 r = r600_bytecode_add_alu(ctx.bc, &alu);
1332 if (r)
1333 return r;
1334 }
1335 so.output[i].start_component = 0;
1336 so_gpr[i] = tmp;
1337 }
1338 }
1339
1340 /* Write outputs to buffers. */
1341 for (i = 0; i < so.num_outputs; i++) {
1342 struct r600_bytecode_output output;
1343
1344 memset(&output, 0, sizeof(struct r600_bytecode_output));
1345 output.gpr = so_gpr[i];
1346 output.elem_size = so.output[i].num_components;
1347 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1348 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1349 output.burst_count = 1;
1350 output.barrier = 1;
1351 /* array_size is an upper limit for the burst_count
1352 * with MEM_STREAM instructions */
1353 output.array_size = 0xFFF;
1354 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1355 if (ctx.bc->chip_class >= EVERGREEN) {
1356 switch (so.output[i].output_buffer) {
1357 case 0:
1358 output.op = CF_OP_MEM_STREAM0_BUF0;
1359 break;
1360 case 1:
1361 output.op = CF_OP_MEM_STREAM0_BUF1;
1362 break;
1363 case 2:
1364 output.op = CF_OP_MEM_STREAM0_BUF2;
1365 break;
1366 case 3:
1367 output.op = CF_OP_MEM_STREAM0_BUF3;
1368 break;
1369 }
1370 } else {
1371 switch (so.output[i].output_buffer) {
1372 case 0:
1373 output.op = CF_OP_MEM_STREAM0;
1374 break;
1375 case 1:
1376 output.op = CF_OP_MEM_STREAM1;
1377 break;
1378 case 2:
1379 output.op = CF_OP_MEM_STREAM2;
1380 break;
1381 case 3:
1382 output.op = CF_OP_MEM_STREAM3;
1383 break;
1384 }
1385 }
1386 r = r600_bytecode_add_output(ctx.bc, &output);
1387 if (r)
1388 goto out_err;
1389 }
1390 }
1391
1392 /* export output */
1393 for (i = 0, j = 0; i < noutput; i++, j++) {
1394 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1395 output[j].gpr = shader->output[i].gpr;
1396 output[j].elem_size = 3;
1397 output[j].swizzle_x = 0;
1398 output[j].swizzle_y = 1;
1399 output[j].swizzle_z = 2;
1400 output[j].swizzle_w = 3;
1401 output[j].burst_count = 1;
1402 output[j].barrier = 1;
1403 output[j].type = -1;
1404 output[j].op = CF_OP_EXPORT;
1405 switch (ctx.type) {
1406 case TGSI_PROCESSOR_VERTEX:
1407 switch (shader->output[i].name) {
1408 case TGSI_SEMANTIC_POSITION:
1409 output[j].array_base = next_pos_base++;
1410 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1411 break;
1412
1413 case TGSI_SEMANTIC_PSIZE:
1414 output[j].array_base = next_pos_base++;
1415 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1416 break;
1417 case TGSI_SEMANTIC_CLIPVERTEX:
1418 j--;
1419 break;
1420 case TGSI_SEMANTIC_CLIPDIST:
1421 output[j].array_base = next_pos_base++;
1422 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1423 /* spi_sid is 0 for clipdistance outputs that were generated
1424 * for clipvertex - we don't need to pass them to PS */
1425 if (shader->output[i].spi_sid) {
1426 j++;
1427 /* duplicate it as PARAM to pass to the pixel shader */
1428 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1429 output[j].array_base = next_param_base++;
1430 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1431 }
1432 break;
1433 case TGSI_SEMANTIC_FOG:
1434 output[j].swizzle_y = 4; /* 0 */
1435 output[j].swizzle_z = 4; /* 0 */
1436 output[j].swizzle_w = 5; /* 1 */
1437 break;
1438 }
1439 break;
1440 case TGSI_PROCESSOR_FRAGMENT:
1441 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1442 /* never export more colors than the number of CBs */
1443 if (next_pixel_base && next_pixel_base >= key.nr_cbufs) {
1444 /* skip export */
1445 j--;
1446 continue;
1447 }
1448 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1449 output[j].array_base = next_pixel_base++;
1450 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1451 shader->nr_ps_color_exports++;
1452 if (shader->fs_write_all && (rscreen->chip_class >= EVERGREEN)) {
1453 for (k = 1; k < key.nr_cbufs; k++) {
1454 j++;
1455 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1456 output[j].gpr = shader->output[i].gpr;
1457 output[j].elem_size = 3;
1458 output[j].swizzle_x = 0;
1459 output[j].swizzle_y = 1;
1460 output[j].swizzle_z = 2;
1461 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1462 output[j].burst_count = 1;
1463 output[j].barrier = 1;
1464 output[j].array_base = next_pixel_base++;
1465 output[j].op = CF_OP_EXPORT;
1466 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1467 shader->nr_ps_color_exports++;
1468 }
1469 }
1470 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1471 output[j].array_base = 61;
1472 output[j].swizzle_x = 2;
1473 output[j].swizzle_y = 7;
1474 output[j].swizzle_z = output[j].swizzle_w = 7;
1475 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1476 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1477 output[j].array_base = 61;
1478 output[j].swizzle_x = 7;
1479 output[j].swizzle_y = 1;
1480 output[j].swizzle_z = output[j].swizzle_w = 7;
1481 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1482 } else {
1483 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1484 r = -EINVAL;
1485 goto out_err;
1486 }
1487 break;
1488 default:
1489 R600_ERR("unsupported processor type %d\n", ctx.type);
1490 r = -EINVAL;
1491 goto out_err;
1492 }
1493
1494 if (output[j].type==-1) {
1495 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1496 output[j].array_base = next_param_base++;
1497 }
1498 }
1499
1500 /* add fake position export */
1501 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1502 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1503 output[j].gpr = 0;
1504 output[j].elem_size = 3;
1505 output[j].swizzle_x = 7;
1506 output[j].swizzle_y = 7;
1507 output[j].swizzle_z = 7;
1508 output[j].swizzle_w = 7;
1509 output[j].burst_count = 1;
1510 output[j].barrier = 1;
1511 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1512 output[j].array_base = next_pos_base;
1513 output[j].op = CF_OP_EXPORT;
1514 j++;
1515 }
1516
1517 /* add fake param output for vertex shader if no param is exported */
1518 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1519 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1520 output[j].gpr = 0;
1521 output[j].elem_size = 3;
1522 output[j].swizzle_x = 7;
1523 output[j].swizzle_y = 7;
1524 output[j].swizzle_z = 7;
1525 output[j].swizzle_w = 7;
1526 output[j].burst_count = 1;
1527 output[j].barrier = 1;
1528 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1529 output[j].array_base = 0;
1530 output[j].op = CF_OP_EXPORT;
1531 j++;
1532 }
1533
1534 /* add fake pixel export */
1535 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && next_pixel_base == 0) {
1536 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1537 output[j].gpr = 0;
1538 output[j].elem_size = 3;
1539 output[j].swizzle_x = 7;
1540 output[j].swizzle_y = 7;
1541 output[j].swizzle_z = 7;
1542 output[j].swizzle_w = 7;
1543 output[j].burst_count = 1;
1544 output[j].barrier = 1;
1545 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1546 output[j].array_base = 0;
1547 output[j].op = CF_OP_EXPORT;
1548 j++;
1549 }
1550
1551 noutput = j;
1552
1553 /* set export done on last export of each type */
1554 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1555 if (ctx.bc->chip_class < CAYMAN) {
1556 if (i == (noutput - 1)) {
1557 output[i].end_of_program = 1;
1558 }
1559 }
1560 if (!(output_done & (1 << output[i].type))) {
1561 output_done |= (1 << output[i].type);
1562 output[i].op = CF_OP_EXPORT_DONE;
1563 }
1564 }
1565 /* add output to bytecode */
1566 if (!use_llvm) {
1567 for (i = 0; i < noutput; i++) {
1568 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1569 if (r)
1570 goto out_err;
1571 }
1572 }
1573 /* add program end */
1574 if (!use_llvm && ctx.bc->chip_class == CAYMAN)
1575 cm_bytecode_add_cf_end(ctx.bc);
1576
1577 /* check GPR limit - we have 124 = 128 - 4
1578 * (4 are reserved as alu clause temporary registers) */
1579 if (ctx.bc->ngpr > 124) {
1580 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1581 r = -ENOMEM;
1582 goto out_err;
1583 }
1584
1585 free(ctx.literals);
1586 tgsi_parse_free(&ctx.parse);
1587 return 0;
1588 out_err:
1589 free(ctx.literals);
1590 tgsi_parse_free(&ctx.parse);
1591 return r;
1592 }
1593
1594 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1595 {
1596 R600_ERR("%s tgsi opcode unsupported\n",
1597 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1598 return -EINVAL;
1599 }
1600
1601 static int tgsi_end(struct r600_shader_ctx *ctx)
1602 {
1603 return 0;
1604 }
1605
1606 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1607 const struct r600_shader_src *shader_src,
1608 unsigned chan)
1609 {
1610 bc_src->sel = shader_src->sel;
1611 bc_src->chan = shader_src->swizzle[chan];
1612 bc_src->neg = shader_src->neg;
1613 bc_src->abs = shader_src->abs;
1614 bc_src->rel = shader_src->rel;
1615 bc_src->value = shader_src->value[bc_src->chan];
1616 bc_src->kc_bank = shader_src->kc_bank;
1617 }
1618
1619 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1620 {
1621 bc_src->abs = 1;
1622 bc_src->neg = 0;
1623 }
1624
1625 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1626 {
1627 bc_src->neg = !bc_src->neg;
1628 }
1629
1630 static void tgsi_dst(struct r600_shader_ctx *ctx,
1631 const struct tgsi_full_dst_register *tgsi_dst,
1632 unsigned swizzle,
1633 struct r600_bytecode_alu_dst *r600_dst)
1634 {
1635 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1636
1637 r600_dst->sel = tgsi_dst->Register.Index;
1638 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1639 r600_dst->chan = swizzle;
1640 r600_dst->write = 1;
1641 if (tgsi_dst->Register.Indirect)
1642 r600_dst->rel = V_SQ_REL_RELATIVE;
1643 if (inst->Instruction.Saturate) {
1644 r600_dst->clamp = 1;
1645 }
1646 }
1647
1648 static int tgsi_last_instruction(unsigned writemask)
1649 {
1650 int i, lasti = 0;
1651
1652 for (i = 0; i < 4; i++) {
1653 if (writemask & (1 << i)) {
1654 lasti = i;
1655 }
1656 }
1657 return lasti;
1658 }
1659
1660 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1661 {
1662 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1663 struct r600_bytecode_alu alu;
1664 int i, j, r;
1665 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1666
1667 for (i = 0; i < lasti + 1; i++) {
1668 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1669 continue;
1670
1671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1672 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1673
1674 alu.op = ctx->inst_info->op;
1675 if (!swap) {
1676 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1677 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1678 }
1679 } else {
1680 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1681 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1682 }
1683 /* handle some special cases */
1684 switch (ctx->inst_info->tgsi_opcode) {
1685 case TGSI_OPCODE_SUB:
1686 r600_bytecode_src_toggle_neg(&alu.src[1]);
1687 break;
1688 case TGSI_OPCODE_ABS:
1689 r600_bytecode_src_set_abs(&alu.src[0]);
1690 break;
1691 default:
1692 break;
1693 }
1694 if (i == lasti || trans_only) {
1695 alu.last = 1;
1696 }
1697 r = r600_bytecode_add_alu(ctx->bc, &alu);
1698 if (r)
1699 return r;
1700 }
1701 return 0;
1702 }
1703
1704 static int tgsi_op2(struct r600_shader_ctx *ctx)
1705 {
1706 return tgsi_op2_s(ctx, 0, 0);
1707 }
1708
1709 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1710 {
1711 return tgsi_op2_s(ctx, 1, 0);
1712 }
1713
1714 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1715 {
1716 return tgsi_op2_s(ctx, 0, 1);
1717 }
1718
1719 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1720 {
1721 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1722 struct r600_bytecode_alu alu;
1723 int i, r;
1724 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1725
1726 for (i = 0; i < lasti + 1; i++) {
1727
1728 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1729 continue;
1730 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1731 alu.op = ctx->inst_info->op;
1732
1733 alu.src[0].sel = V_SQ_ALU_SRC_0;
1734
1735 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1736
1737 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1738
1739 if (i == lasti) {
1740 alu.last = 1;
1741 }
1742 r = r600_bytecode_add_alu(ctx->bc, &alu);
1743 if (r)
1744 return r;
1745 }
1746 return 0;
1747
1748 }
1749
1750 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1751 {
1752 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1753 int i, j, r;
1754 struct r600_bytecode_alu alu;
1755 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1756
1757 for (i = 0 ; i < last_slot; i++) {
1758 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1759 alu.op = ctx->inst_info->op;
1760 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1761 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1762
1763 /* RSQ should take the absolute value of src */
1764 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
1765 r600_bytecode_src_set_abs(&alu.src[j]);
1766 }
1767 }
1768 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1769 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1770
1771 if (i == last_slot - 1)
1772 alu.last = 1;
1773 r = r600_bytecode_add_alu(ctx->bc, &alu);
1774 if (r)
1775 return r;
1776 }
1777 return 0;
1778 }
1779
1780 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
1781 {
1782 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1783 int i, j, k, r;
1784 struct r600_bytecode_alu alu;
1785 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1786 for (k = 0; k < last_slot; k++) {
1787 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
1788 continue;
1789
1790 for (i = 0 ; i < 4; i++) {
1791 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1792 alu.op = ctx->inst_info->op;
1793 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1794 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
1795 }
1796 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1797 alu.dst.write = (i == k);
1798 if (i == 3)
1799 alu.last = 1;
1800 r = r600_bytecode_add_alu(ctx->bc, &alu);
1801 if (r)
1802 return r;
1803 }
1804 }
1805 return 0;
1806 }
1807
1808 /*
1809 * r600 - trunc to -PI..PI range
1810 * r700 - normalize by dividing by 2PI
1811 * see fdo bug 27901
1812 */
1813 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1814 {
1815 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1816 static float double_pi = 3.1415926535 * 2;
1817 static float neg_pi = -3.1415926535;
1818
1819 int r;
1820 struct r600_bytecode_alu alu;
1821
1822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1823 alu.op = ALU_OP3_MULADD;
1824 alu.is_op3 = 1;
1825
1826 alu.dst.chan = 0;
1827 alu.dst.sel = ctx->temp_reg;
1828 alu.dst.write = 1;
1829
1830 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1831
1832 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1833 alu.src[1].chan = 0;
1834 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1835 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1836 alu.src[2].chan = 0;
1837 alu.last = 1;
1838 r = r600_bytecode_add_alu(ctx->bc, &alu);
1839 if (r)
1840 return r;
1841
1842 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1843 alu.op = ALU_OP1_FRACT;
1844
1845 alu.dst.chan = 0;
1846 alu.dst.sel = ctx->temp_reg;
1847 alu.dst.write = 1;
1848
1849 alu.src[0].sel = ctx->temp_reg;
1850 alu.src[0].chan = 0;
1851 alu.last = 1;
1852 r = r600_bytecode_add_alu(ctx->bc, &alu);
1853 if (r)
1854 return r;
1855
1856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1857 alu.op = ALU_OP3_MULADD;
1858 alu.is_op3 = 1;
1859
1860 alu.dst.chan = 0;
1861 alu.dst.sel = ctx->temp_reg;
1862 alu.dst.write = 1;
1863
1864 alu.src[0].sel = ctx->temp_reg;
1865 alu.src[0].chan = 0;
1866
1867 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1868 alu.src[1].chan = 0;
1869 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1870 alu.src[2].chan = 0;
1871
1872 if (ctx->bc->chip_class == R600) {
1873 alu.src[1].value = *(uint32_t *)&double_pi;
1874 alu.src[2].value = *(uint32_t *)&neg_pi;
1875 } else {
1876 alu.src[1].sel = V_SQ_ALU_SRC_1;
1877 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1878 alu.src[2].neg = 1;
1879 }
1880
1881 alu.last = 1;
1882 r = r600_bytecode_add_alu(ctx->bc, &alu);
1883 if (r)
1884 return r;
1885 return 0;
1886 }
1887
1888 static int cayman_trig(struct r600_shader_ctx *ctx)
1889 {
1890 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1891 struct r600_bytecode_alu alu;
1892 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1893 int i, r;
1894
1895 r = tgsi_setup_trig(ctx);
1896 if (r)
1897 return r;
1898
1899
1900 for (i = 0; i < last_slot; i++) {
1901 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1902 alu.op = ctx->inst_info->op;
1903 alu.dst.chan = i;
1904
1905 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1906 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1907
1908 alu.src[0].sel = ctx->temp_reg;
1909 alu.src[0].chan = 0;
1910 if (i == last_slot - 1)
1911 alu.last = 1;
1912 r = r600_bytecode_add_alu(ctx->bc, &alu);
1913 if (r)
1914 return r;
1915 }
1916 return 0;
1917 }
1918
1919 static int tgsi_trig(struct r600_shader_ctx *ctx)
1920 {
1921 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1922 struct r600_bytecode_alu alu;
1923 int i, r;
1924 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1925
1926 r = tgsi_setup_trig(ctx);
1927 if (r)
1928 return r;
1929
1930 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1931 alu.op = ctx->inst_info->op;
1932 alu.dst.chan = 0;
1933 alu.dst.sel = ctx->temp_reg;
1934 alu.dst.write = 1;
1935
1936 alu.src[0].sel = ctx->temp_reg;
1937 alu.src[0].chan = 0;
1938 alu.last = 1;
1939 r = r600_bytecode_add_alu(ctx->bc, &alu);
1940 if (r)
1941 return r;
1942
1943 /* replicate result */
1944 for (i = 0; i < lasti + 1; i++) {
1945 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1946 continue;
1947
1948 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1949 alu.op = ALU_OP1_MOV;
1950
1951 alu.src[0].sel = ctx->temp_reg;
1952 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1953 if (i == lasti)
1954 alu.last = 1;
1955 r = r600_bytecode_add_alu(ctx->bc, &alu);
1956 if (r)
1957 return r;
1958 }
1959 return 0;
1960 }
1961
1962 static int tgsi_scs(struct r600_shader_ctx *ctx)
1963 {
1964 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1965 struct r600_bytecode_alu alu;
1966 int i, r;
1967
1968 /* We'll only need the trig stuff if we are going to write to the
1969 * X or Y components of the destination vector.
1970 */
1971 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1972 r = tgsi_setup_trig(ctx);
1973 if (r)
1974 return r;
1975 }
1976
1977 /* dst.x = COS */
1978 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1979 if (ctx->bc->chip_class == CAYMAN) {
1980 for (i = 0 ; i < 3; i++) {
1981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1982 alu.op = ALU_OP1_COS;
1983 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1984
1985 if (i == 0)
1986 alu.dst.write = 1;
1987 else
1988 alu.dst.write = 0;
1989 alu.src[0].sel = ctx->temp_reg;
1990 alu.src[0].chan = 0;
1991 if (i == 2)
1992 alu.last = 1;
1993 r = r600_bytecode_add_alu(ctx->bc, &alu);
1994 if (r)
1995 return r;
1996 }
1997 } else {
1998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1999 alu.op = ALU_OP1_COS;
2000 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2001
2002 alu.src[0].sel = ctx->temp_reg;
2003 alu.src[0].chan = 0;
2004 alu.last = 1;
2005 r = r600_bytecode_add_alu(ctx->bc, &alu);
2006 if (r)
2007 return r;
2008 }
2009 }
2010
2011 /* dst.y = SIN */
2012 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2013 if (ctx->bc->chip_class == CAYMAN) {
2014 for (i = 0 ; i < 3; i++) {
2015 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2016 alu.op = ALU_OP1_SIN;
2017 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2018 if (i == 1)
2019 alu.dst.write = 1;
2020 else
2021 alu.dst.write = 0;
2022 alu.src[0].sel = ctx->temp_reg;
2023 alu.src[0].chan = 0;
2024 if (i == 2)
2025 alu.last = 1;
2026 r = r600_bytecode_add_alu(ctx->bc, &alu);
2027 if (r)
2028 return r;
2029 }
2030 } else {
2031 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2032 alu.op = ALU_OP1_SIN;
2033 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2034
2035 alu.src[0].sel = ctx->temp_reg;
2036 alu.src[0].chan = 0;
2037 alu.last = 1;
2038 r = r600_bytecode_add_alu(ctx->bc, &alu);
2039 if (r)
2040 return r;
2041 }
2042 }
2043
2044 /* dst.z = 0.0; */
2045 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2046 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2047
2048 alu.op = ALU_OP1_MOV;
2049
2050 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2051
2052 alu.src[0].sel = V_SQ_ALU_SRC_0;
2053 alu.src[0].chan = 0;
2054
2055 alu.last = 1;
2056
2057 r = r600_bytecode_add_alu(ctx->bc, &alu);
2058 if (r)
2059 return r;
2060 }
2061
2062 /* dst.w = 1.0; */
2063 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2065
2066 alu.op = ALU_OP1_MOV;
2067
2068 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2069
2070 alu.src[0].sel = V_SQ_ALU_SRC_1;
2071 alu.src[0].chan = 0;
2072
2073 alu.last = 1;
2074
2075 r = r600_bytecode_add_alu(ctx->bc, &alu);
2076 if (r)
2077 return r;
2078 }
2079
2080 return 0;
2081 }
2082
2083 static int tgsi_kill(struct r600_shader_ctx *ctx)
2084 {
2085 struct r600_bytecode_alu alu;
2086 int i, r;
2087
2088 for (i = 0; i < 4; i++) {
2089 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2090 alu.op = ctx->inst_info->op;
2091
2092 alu.dst.chan = i;
2093
2094 alu.src[0].sel = V_SQ_ALU_SRC_0;
2095
2096 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILL) {
2097 alu.src[1].sel = V_SQ_ALU_SRC_1;
2098 alu.src[1].neg = 1;
2099 } else {
2100 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2101 }
2102 if (i == 3) {
2103 alu.last = 1;
2104 }
2105 r = r600_bytecode_add_alu(ctx->bc, &alu);
2106 if (r)
2107 return r;
2108 }
2109
2110 /* kill must be last in ALU */
2111 ctx->bc->force_add_cf = 1;
2112 ctx->shader->uses_kill = TRUE;
2113 return 0;
2114 }
2115
2116 static int tgsi_lit(struct r600_shader_ctx *ctx)
2117 {
2118 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2119 struct r600_bytecode_alu alu;
2120 int r;
2121
2122 /* tmp.x = max(src.y, 0.0) */
2123 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2124 alu.op = ALU_OP2_MAX;
2125 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2126 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2127 alu.src[1].chan = 1;
2128
2129 alu.dst.sel = ctx->temp_reg;
2130 alu.dst.chan = 0;
2131 alu.dst.write = 1;
2132
2133 alu.last = 1;
2134 r = r600_bytecode_add_alu(ctx->bc, &alu);
2135 if (r)
2136 return r;
2137
2138 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2139 {
2140 int chan;
2141 int sel;
2142 int i;
2143
2144 if (ctx->bc->chip_class == CAYMAN) {
2145 for (i = 0; i < 3; i++) {
2146 /* tmp.z = log(tmp.x) */
2147 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2148 alu.op = ALU_OP1_LOG_CLAMPED;
2149 alu.src[0].sel = ctx->temp_reg;
2150 alu.src[0].chan = 0;
2151 alu.dst.sel = ctx->temp_reg;
2152 alu.dst.chan = i;
2153 if (i == 2) {
2154 alu.dst.write = 1;
2155 alu.last = 1;
2156 } else
2157 alu.dst.write = 0;
2158
2159 r = r600_bytecode_add_alu(ctx->bc, &alu);
2160 if (r)
2161 return r;
2162 }
2163 } else {
2164 /* tmp.z = log(tmp.x) */
2165 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2166 alu.op = ALU_OP1_LOG_CLAMPED;
2167 alu.src[0].sel = ctx->temp_reg;
2168 alu.src[0].chan = 0;
2169 alu.dst.sel = ctx->temp_reg;
2170 alu.dst.chan = 2;
2171 alu.dst.write = 1;
2172 alu.last = 1;
2173 r = r600_bytecode_add_alu(ctx->bc, &alu);
2174 if (r)
2175 return r;
2176 }
2177
2178 chan = alu.dst.chan;
2179 sel = alu.dst.sel;
2180
2181 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2182 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2183 alu.op = ALU_OP3_MUL_LIT;
2184 alu.src[0].sel = sel;
2185 alu.src[0].chan = chan;
2186 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2187 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2188 alu.dst.sel = ctx->temp_reg;
2189 alu.dst.chan = 0;
2190 alu.dst.write = 1;
2191 alu.is_op3 = 1;
2192 alu.last = 1;
2193 r = r600_bytecode_add_alu(ctx->bc, &alu);
2194 if (r)
2195 return r;
2196
2197 if (ctx->bc->chip_class == CAYMAN) {
2198 for (i = 0; i < 3; i++) {
2199 /* dst.z = exp(tmp.x) */
2200 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2201 alu.op = ALU_OP1_EXP_IEEE;
2202 alu.src[0].sel = ctx->temp_reg;
2203 alu.src[0].chan = 0;
2204 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2205 if (i == 2) {
2206 alu.dst.write = 1;
2207 alu.last = 1;
2208 } else
2209 alu.dst.write = 0;
2210 r = r600_bytecode_add_alu(ctx->bc, &alu);
2211 if (r)
2212 return r;
2213 }
2214 } else {
2215 /* dst.z = exp(tmp.x) */
2216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2217 alu.op = ALU_OP1_EXP_IEEE;
2218 alu.src[0].sel = ctx->temp_reg;
2219 alu.src[0].chan = 0;
2220 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2221 alu.last = 1;
2222 r = r600_bytecode_add_alu(ctx->bc, &alu);
2223 if (r)
2224 return r;
2225 }
2226 }
2227
2228 /* dst.x, <- 1.0 */
2229 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2230 alu.op = ALU_OP1_MOV;
2231 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2232 alu.src[0].chan = 0;
2233 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2234 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2235 r = r600_bytecode_add_alu(ctx->bc, &alu);
2236 if (r)
2237 return r;
2238
2239 /* dst.y = max(src.x, 0.0) */
2240 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2241 alu.op = ALU_OP2_MAX;
2242 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2243 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2244 alu.src[1].chan = 0;
2245 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2246 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2247 r = r600_bytecode_add_alu(ctx->bc, &alu);
2248 if (r)
2249 return r;
2250
2251 /* dst.w, <- 1.0 */
2252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2253 alu.op = ALU_OP1_MOV;
2254 alu.src[0].sel = V_SQ_ALU_SRC_1;
2255 alu.src[0].chan = 0;
2256 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2257 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2258 alu.last = 1;
2259 r = r600_bytecode_add_alu(ctx->bc, &alu);
2260 if (r)
2261 return r;
2262
2263 return 0;
2264 }
2265
2266 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2267 {
2268 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2269 struct r600_bytecode_alu alu;
2270 int i, r;
2271
2272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2273
2274 /* XXX:
2275 * For state trackers other than OpenGL, we'll want to use
2276 * _RECIPSQRT_IEEE instead.
2277 */
2278 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2279
2280 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2281 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2282 r600_bytecode_src_set_abs(&alu.src[i]);
2283 }
2284 alu.dst.sel = ctx->temp_reg;
2285 alu.dst.write = 1;
2286 alu.last = 1;
2287 r = r600_bytecode_add_alu(ctx->bc, &alu);
2288 if (r)
2289 return r;
2290 /* replicate result */
2291 return tgsi_helper_tempx_replicate(ctx);
2292 }
2293
2294 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2295 {
2296 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2297 struct r600_bytecode_alu alu;
2298 int i, r;
2299
2300 for (i = 0; i < 4; i++) {
2301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2302 alu.src[0].sel = ctx->temp_reg;
2303 alu.op = ALU_OP1_MOV;
2304 alu.dst.chan = i;
2305 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2306 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2307 if (i == 3)
2308 alu.last = 1;
2309 r = r600_bytecode_add_alu(ctx->bc, &alu);
2310 if (r)
2311 return r;
2312 }
2313 return 0;
2314 }
2315
2316 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2317 {
2318 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2319 struct r600_bytecode_alu alu;
2320 int i, r;
2321
2322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2323 alu.op = ctx->inst_info->op;
2324 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2325 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2326 }
2327 alu.dst.sel = ctx->temp_reg;
2328 alu.dst.write = 1;
2329 alu.last = 1;
2330 r = r600_bytecode_add_alu(ctx->bc, &alu);
2331 if (r)
2332 return r;
2333 /* replicate result */
2334 return tgsi_helper_tempx_replicate(ctx);
2335 }
2336
2337 static int cayman_pow(struct r600_shader_ctx *ctx)
2338 {
2339 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2340 int i, r;
2341 struct r600_bytecode_alu alu;
2342 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2343
2344 for (i = 0; i < 3; i++) {
2345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2346 alu.op = ALU_OP1_LOG_IEEE;
2347 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2348 alu.dst.sel = ctx->temp_reg;
2349 alu.dst.chan = i;
2350 alu.dst.write = 1;
2351 if (i == 2)
2352 alu.last = 1;
2353 r = r600_bytecode_add_alu(ctx->bc, &alu);
2354 if (r)
2355 return r;
2356 }
2357
2358 /* b * LOG2(a) */
2359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2360 alu.op = ALU_OP2_MUL;
2361 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2362 alu.src[1].sel = ctx->temp_reg;
2363 alu.dst.sel = ctx->temp_reg;
2364 alu.dst.write = 1;
2365 alu.last = 1;
2366 r = r600_bytecode_add_alu(ctx->bc, &alu);
2367 if (r)
2368 return r;
2369
2370 for (i = 0; i < last_slot; i++) {
2371 /* POW(a,b) = EXP2(b * LOG2(a))*/
2372 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2373 alu.op = ALU_OP1_EXP_IEEE;
2374 alu.src[0].sel = ctx->temp_reg;
2375
2376 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2377 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2378 if (i == last_slot - 1)
2379 alu.last = 1;
2380 r = r600_bytecode_add_alu(ctx->bc, &alu);
2381 if (r)
2382 return r;
2383 }
2384 return 0;
2385 }
2386
2387 static int tgsi_pow(struct r600_shader_ctx *ctx)
2388 {
2389 struct r600_bytecode_alu alu;
2390 int r;
2391
2392 /* LOG2(a) */
2393 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2394 alu.op = ALU_OP1_LOG_IEEE;
2395 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2396 alu.dst.sel = ctx->temp_reg;
2397 alu.dst.write = 1;
2398 alu.last = 1;
2399 r = r600_bytecode_add_alu(ctx->bc, &alu);
2400 if (r)
2401 return r;
2402 /* b * LOG2(a) */
2403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2404 alu.op = ALU_OP2_MUL;
2405 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2406 alu.src[1].sel = ctx->temp_reg;
2407 alu.dst.sel = ctx->temp_reg;
2408 alu.dst.write = 1;
2409 alu.last = 1;
2410 r = r600_bytecode_add_alu(ctx->bc, &alu);
2411 if (r)
2412 return r;
2413 /* POW(a,b) = EXP2(b * LOG2(a))*/
2414 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2415 alu.op = ALU_OP1_EXP_IEEE;
2416 alu.src[0].sel = ctx->temp_reg;
2417 alu.dst.sel = ctx->temp_reg;
2418 alu.dst.write = 1;
2419 alu.last = 1;
2420 r = r600_bytecode_add_alu(ctx->bc, &alu);
2421 if (r)
2422 return r;
2423 return tgsi_helper_tempx_replicate(ctx);
2424 }
2425
2426 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2427 {
2428 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2429 struct r600_bytecode_alu alu;
2430 int i, r, j;
2431 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2432 int tmp0 = ctx->temp_reg;
2433 int tmp1 = r600_get_temp(ctx);
2434 int tmp2 = r600_get_temp(ctx);
2435 int tmp3 = r600_get_temp(ctx);
2436 /* Unsigned path:
2437 *
2438 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2439 *
2440 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2441 * 2. tmp0.z = lo (tmp0.x * src2)
2442 * 3. tmp0.w = -tmp0.z
2443 * 4. tmp0.y = hi (tmp0.x * src2)
2444 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2445 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2446 * 7. tmp1.x = tmp0.x - tmp0.w
2447 * 8. tmp1.y = tmp0.x + tmp0.w
2448 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2449 * 10. tmp0.z = hi(tmp0.x * src1) = q
2450 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2451 *
2452 * 12. tmp0.w = src1 - tmp0.y = r
2453 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2454 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2455 *
2456 * if DIV
2457 *
2458 * 15. tmp1.z = tmp0.z + 1 = q + 1
2459 * 16. tmp1.w = tmp0.z - 1 = q - 1
2460 *
2461 * else MOD
2462 *
2463 * 15. tmp1.z = tmp0.w - src2 = r - src2
2464 * 16. tmp1.w = tmp0.w + src2 = r + src2
2465 *
2466 * endif
2467 *
2468 * 17. tmp1.x = tmp1.x & tmp1.y
2469 *
2470 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2471 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2472 *
2473 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2474 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2475 *
2476 * Signed path:
2477 *
2478 * Same as unsigned, using abs values of the operands,
2479 * and fixing the sign of the result in the end.
2480 */
2481
2482 for (i = 0; i < 4; i++) {
2483 if (!(write_mask & (1<<i)))
2484 continue;
2485
2486 if (signed_op) {
2487
2488 /* tmp2.x = -src0 */
2489 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2490 alu.op = ALU_OP2_SUB_INT;
2491
2492 alu.dst.sel = tmp2;
2493 alu.dst.chan = 0;
2494 alu.dst.write = 1;
2495
2496 alu.src[0].sel = V_SQ_ALU_SRC_0;
2497
2498 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2499
2500 alu.last = 1;
2501 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2502 return r;
2503
2504 /* tmp2.y = -src1 */
2505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2506 alu.op = ALU_OP2_SUB_INT;
2507
2508 alu.dst.sel = tmp2;
2509 alu.dst.chan = 1;
2510 alu.dst.write = 1;
2511
2512 alu.src[0].sel = V_SQ_ALU_SRC_0;
2513
2514 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2515
2516 alu.last = 1;
2517 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2518 return r;
2519
2520 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2521 /* it will be a sign of the quotient */
2522 if (!mod) {
2523
2524 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2525 alu.op = ALU_OP2_XOR_INT;
2526
2527 alu.dst.sel = tmp2;
2528 alu.dst.chan = 2;
2529 alu.dst.write = 1;
2530
2531 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2532 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2533
2534 alu.last = 1;
2535 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2536 return r;
2537 }
2538
2539 /* tmp2.x = |src0| */
2540 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2541 alu.op = ALU_OP3_CNDGE_INT;
2542 alu.is_op3 = 1;
2543
2544 alu.dst.sel = tmp2;
2545 alu.dst.chan = 0;
2546 alu.dst.write = 1;
2547
2548 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2549 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2550 alu.src[2].sel = tmp2;
2551 alu.src[2].chan = 0;
2552
2553 alu.last = 1;
2554 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2555 return r;
2556
2557 /* tmp2.y = |src1| */
2558 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2559 alu.op = ALU_OP3_CNDGE_INT;
2560 alu.is_op3 = 1;
2561
2562 alu.dst.sel = tmp2;
2563 alu.dst.chan = 1;
2564 alu.dst.write = 1;
2565
2566 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2567 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2568 alu.src[2].sel = tmp2;
2569 alu.src[2].chan = 1;
2570
2571 alu.last = 1;
2572 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2573 return r;
2574
2575 }
2576
2577 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2578 if (ctx->bc->chip_class == CAYMAN) {
2579 /* tmp3.x = u2f(src2) */
2580 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2581 alu.op = ALU_OP1_UINT_TO_FLT;
2582
2583 alu.dst.sel = tmp3;
2584 alu.dst.chan = 0;
2585 alu.dst.write = 1;
2586
2587 if (signed_op) {
2588 alu.src[0].sel = tmp2;
2589 alu.src[0].chan = 1;
2590 } else {
2591 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2592 }
2593
2594 alu.last = 1;
2595 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2596 return r;
2597
2598 /* tmp0.x = recip(tmp3.x) */
2599 for (j = 0 ; j < 3; j++) {
2600 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2601 alu.op = ALU_OP1_RECIP_IEEE;
2602
2603 alu.dst.sel = tmp0;
2604 alu.dst.chan = j;
2605 alu.dst.write = (j == 0);
2606
2607 alu.src[0].sel = tmp3;
2608 alu.src[0].chan = 0;
2609
2610 if (j == 2)
2611 alu.last = 1;
2612 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2613 return r;
2614 }
2615
2616 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2617 alu.op = ALU_OP2_MUL;
2618
2619 alu.src[0].sel = tmp0;
2620 alu.src[0].chan = 0;
2621
2622 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2623 alu.src[1].value = 0x4f800000;
2624
2625 alu.dst.sel = tmp3;
2626 alu.dst.write = 1;
2627 alu.last = 1;
2628 r = r600_bytecode_add_alu(ctx->bc, &alu);
2629 if (r)
2630 return r;
2631
2632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2633 alu.op = ALU_OP1_FLT_TO_UINT;
2634
2635 alu.dst.sel = tmp0;
2636 alu.dst.chan = 0;
2637 alu.dst.write = 1;
2638
2639 alu.src[0].sel = tmp3;
2640 alu.src[0].chan = 0;
2641
2642 alu.last = 1;
2643 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2644 return r;
2645
2646 } else {
2647 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2648 alu.op = ALU_OP1_RECIP_UINT;
2649
2650 alu.dst.sel = tmp0;
2651 alu.dst.chan = 0;
2652 alu.dst.write = 1;
2653
2654 if (signed_op) {
2655 alu.src[0].sel = tmp2;
2656 alu.src[0].chan = 1;
2657 } else {
2658 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2659 }
2660
2661 alu.last = 1;
2662 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2663 return r;
2664 }
2665
2666 /* 2. tmp0.z = lo (tmp0.x * src2) */
2667 if (ctx->bc->chip_class == CAYMAN) {
2668 for (j = 0 ; j < 4; j++) {
2669 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2670 alu.op = ALU_OP2_MULLO_UINT;
2671
2672 alu.dst.sel = tmp0;
2673 alu.dst.chan = j;
2674 alu.dst.write = (j == 2);
2675
2676 alu.src[0].sel = tmp0;
2677 alu.src[0].chan = 0;
2678 if (signed_op) {
2679 alu.src[1].sel = tmp2;
2680 alu.src[1].chan = 1;
2681 } else {
2682 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2683 }
2684
2685 alu.last = (j == 3);
2686 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2687 return r;
2688 }
2689 } else {
2690 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2691 alu.op = ALU_OP2_MULLO_UINT;
2692
2693 alu.dst.sel = tmp0;
2694 alu.dst.chan = 2;
2695 alu.dst.write = 1;
2696
2697 alu.src[0].sel = tmp0;
2698 alu.src[0].chan = 0;
2699 if (signed_op) {
2700 alu.src[1].sel = tmp2;
2701 alu.src[1].chan = 1;
2702 } else {
2703 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2704 }
2705
2706 alu.last = 1;
2707 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2708 return r;
2709 }
2710
2711 /* 3. tmp0.w = -tmp0.z */
2712 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2713 alu.op = ALU_OP2_SUB_INT;
2714
2715 alu.dst.sel = tmp0;
2716 alu.dst.chan = 3;
2717 alu.dst.write = 1;
2718
2719 alu.src[0].sel = V_SQ_ALU_SRC_0;
2720 alu.src[1].sel = tmp0;
2721 alu.src[1].chan = 2;
2722
2723 alu.last = 1;
2724 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2725 return r;
2726
2727 /* 4. tmp0.y = hi (tmp0.x * src2) */
2728 if (ctx->bc->chip_class == CAYMAN) {
2729 for (j = 0 ; j < 4; j++) {
2730 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2731 alu.op = ALU_OP2_MULHI_UINT;
2732
2733 alu.dst.sel = tmp0;
2734 alu.dst.chan = j;
2735 alu.dst.write = (j == 1);
2736
2737 alu.src[0].sel = tmp0;
2738 alu.src[0].chan = 0;
2739
2740 if (signed_op) {
2741 alu.src[1].sel = tmp2;
2742 alu.src[1].chan = 1;
2743 } else {
2744 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2745 }
2746 alu.last = (j == 3);
2747 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2748 return r;
2749 }
2750 } else {
2751 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2752 alu.op = ALU_OP2_MULHI_UINT;
2753
2754 alu.dst.sel = tmp0;
2755 alu.dst.chan = 1;
2756 alu.dst.write = 1;
2757
2758 alu.src[0].sel = tmp0;
2759 alu.src[0].chan = 0;
2760
2761 if (signed_op) {
2762 alu.src[1].sel = tmp2;
2763 alu.src[1].chan = 1;
2764 } else {
2765 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2766 }
2767
2768 alu.last = 1;
2769 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2770 return r;
2771 }
2772
2773 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2775 alu.op = ALU_OP3_CNDE_INT;
2776 alu.is_op3 = 1;
2777
2778 alu.dst.sel = tmp0;
2779 alu.dst.chan = 2;
2780 alu.dst.write = 1;
2781
2782 alu.src[0].sel = tmp0;
2783 alu.src[0].chan = 1;
2784 alu.src[1].sel = tmp0;
2785 alu.src[1].chan = 3;
2786 alu.src[2].sel = tmp0;
2787 alu.src[2].chan = 2;
2788
2789 alu.last = 1;
2790 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2791 return r;
2792
2793 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2794 if (ctx->bc->chip_class == CAYMAN) {
2795 for (j = 0 ; j < 4; j++) {
2796 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2797 alu.op = ALU_OP2_MULHI_UINT;
2798
2799 alu.dst.sel = tmp0;
2800 alu.dst.chan = j;
2801 alu.dst.write = (j == 3);
2802
2803 alu.src[0].sel = tmp0;
2804 alu.src[0].chan = 2;
2805
2806 alu.src[1].sel = tmp0;
2807 alu.src[1].chan = 0;
2808
2809 alu.last = (j == 3);
2810 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2811 return r;
2812 }
2813 } else {
2814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2815 alu.op = ALU_OP2_MULHI_UINT;
2816
2817 alu.dst.sel = tmp0;
2818 alu.dst.chan = 3;
2819 alu.dst.write = 1;
2820
2821 alu.src[0].sel = tmp0;
2822 alu.src[0].chan = 2;
2823
2824 alu.src[1].sel = tmp0;
2825 alu.src[1].chan = 0;
2826
2827 alu.last = 1;
2828 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2829 return r;
2830 }
2831
2832 /* 7. tmp1.x = tmp0.x - tmp0.w */
2833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2834 alu.op = ALU_OP2_SUB_INT;
2835
2836 alu.dst.sel = tmp1;
2837 alu.dst.chan = 0;
2838 alu.dst.write = 1;
2839
2840 alu.src[0].sel = tmp0;
2841 alu.src[0].chan = 0;
2842 alu.src[1].sel = tmp0;
2843 alu.src[1].chan = 3;
2844
2845 alu.last = 1;
2846 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2847 return r;
2848
2849 /* 8. tmp1.y = tmp0.x + tmp0.w */
2850 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2851 alu.op = ALU_OP2_ADD_INT;
2852
2853 alu.dst.sel = tmp1;
2854 alu.dst.chan = 1;
2855 alu.dst.write = 1;
2856
2857 alu.src[0].sel = tmp0;
2858 alu.src[0].chan = 0;
2859 alu.src[1].sel = tmp0;
2860 alu.src[1].chan = 3;
2861
2862 alu.last = 1;
2863 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2864 return r;
2865
2866 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2867 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2868 alu.op = ALU_OP3_CNDE_INT;
2869 alu.is_op3 = 1;
2870
2871 alu.dst.sel = tmp0;
2872 alu.dst.chan = 0;
2873 alu.dst.write = 1;
2874
2875 alu.src[0].sel = tmp0;
2876 alu.src[0].chan = 1;
2877 alu.src[1].sel = tmp1;
2878 alu.src[1].chan = 1;
2879 alu.src[2].sel = tmp1;
2880 alu.src[2].chan = 0;
2881
2882 alu.last = 1;
2883 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2884 return r;
2885
2886 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2887 if (ctx->bc->chip_class == CAYMAN) {
2888 for (j = 0 ; j < 4; j++) {
2889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2890 alu.op = ALU_OP2_MULHI_UINT;
2891
2892 alu.dst.sel = tmp0;
2893 alu.dst.chan = j;
2894 alu.dst.write = (j == 2);
2895
2896 alu.src[0].sel = tmp0;
2897 alu.src[0].chan = 0;
2898
2899 if (signed_op) {
2900 alu.src[1].sel = tmp2;
2901 alu.src[1].chan = 0;
2902 } else {
2903 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2904 }
2905
2906 alu.last = (j == 3);
2907 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2908 return r;
2909 }
2910 } else {
2911 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2912 alu.op = ALU_OP2_MULHI_UINT;
2913
2914 alu.dst.sel = tmp0;
2915 alu.dst.chan = 2;
2916 alu.dst.write = 1;
2917
2918 alu.src[0].sel = tmp0;
2919 alu.src[0].chan = 0;
2920
2921 if (signed_op) {
2922 alu.src[1].sel = tmp2;
2923 alu.src[1].chan = 0;
2924 } else {
2925 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2926 }
2927
2928 alu.last = 1;
2929 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2930 return r;
2931 }
2932
2933 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
2934 if (ctx->bc->chip_class == CAYMAN) {
2935 for (j = 0 ; j < 4; j++) {
2936 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2937 alu.op = ALU_OP2_MULLO_UINT;
2938
2939 alu.dst.sel = tmp0;
2940 alu.dst.chan = j;
2941 alu.dst.write = (j == 1);
2942
2943 if (signed_op) {
2944 alu.src[0].sel = tmp2;
2945 alu.src[0].chan = 1;
2946 } else {
2947 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2948 }
2949
2950 alu.src[1].sel = tmp0;
2951 alu.src[1].chan = 2;
2952
2953 alu.last = (j == 3);
2954 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2955 return r;
2956 }
2957 } else {
2958 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2959 alu.op = ALU_OP2_MULLO_UINT;
2960
2961 alu.dst.sel = tmp0;
2962 alu.dst.chan = 1;
2963 alu.dst.write = 1;
2964
2965 if (signed_op) {
2966 alu.src[0].sel = tmp2;
2967 alu.src[0].chan = 1;
2968 } else {
2969 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2970 }
2971
2972 alu.src[1].sel = tmp0;
2973 alu.src[1].chan = 2;
2974
2975 alu.last = 1;
2976 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2977 return r;
2978 }
2979
2980 /* 12. tmp0.w = src1 - tmp0.y = r */
2981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2982 alu.op = ALU_OP2_SUB_INT;
2983
2984 alu.dst.sel = tmp0;
2985 alu.dst.chan = 3;
2986 alu.dst.write = 1;
2987
2988 if (signed_op) {
2989 alu.src[0].sel = tmp2;
2990 alu.src[0].chan = 0;
2991 } else {
2992 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2993 }
2994
2995 alu.src[1].sel = tmp0;
2996 alu.src[1].chan = 1;
2997
2998 alu.last = 1;
2999 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3000 return r;
3001
3002 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3003 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3004 alu.op = ALU_OP2_SETGE_UINT;
3005
3006 alu.dst.sel = tmp1;
3007 alu.dst.chan = 0;
3008 alu.dst.write = 1;
3009
3010 alu.src[0].sel = tmp0;
3011 alu.src[0].chan = 3;
3012 if (signed_op) {
3013 alu.src[1].sel = tmp2;
3014 alu.src[1].chan = 1;
3015 } else {
3016 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3017 }
3018
3019 alu.last = 1;
3020 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3021 return r;
3022
3023 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3025 alu.op = ALU_OP2_SETGE_UINT;
3026
3027 alu.dst.sel = tmp1;
3028 alu.dst.chan = 1;
3029 alu.dst.write = 1;
3030
3031 if (signed_op) {
3032 alu.src[0].sel = tmp2;
3033 alu.src[0].chan = 0;
3034 } else {
3035 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3036 }
3037
3038 alu.src[1].sel = tmp0;
3039 alu.src[1].chan = 1;
3040
3041 alu.last = 1;
3042 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3043 return r;
3044
3045 if (mod) { /* UMOD */
3046
3047 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3048 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3049 alu.op = ALU_OP2_SUB_INT;
3050
3051 alu.dst.sel = tmp1;
3052 alu.dst.chan = 2;
3053 alu.dst.write = 1;
3054
3055 alu.src[0].sel = tmp0;
3056 alu.src[0].chan = 3;
3057
3058 if (signed_op) {
3059 alu.src[1].sel = tmp2;
3060 alu.src[1].chan = 1;
3061 } else {
3062 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3063 }
3064
3065 alu.last = 1;
3066 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3067 return r;
3068
3069 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3070 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3071 alu.op = ALU_OP2_ADD_INT;
3072
3073 alu.dst.sel = tmp1;
3074 alu.dst.chan = 3;
3075 alu.dst.write = 1;
3076
3077 alu.src[0].sel = tmp0;
3078 alu.src[0].chan = 3;
3079 if (signed_op) {
3080 alu.src[1].sel = tmp2;
3081 alu.src[1].chan = 1;
3082 } else {
3083 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3084 }
3085
3086 alu.last = 1;
3087 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3088 return r;
3089
3090 } else { /* UDIV */
3091
3092 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3094 alu.op = ALU_OP2_ADD_INT;
3095
3096 alu.dst.sel = tmp1;
3097 alu.dst.chan = 2;
3098 alu.dst.write = 1;
3099
3100 alu.src[0].sel = tmp0;
3101 alu.src[0].chan = 2;
3102 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3103
3104 alu.last = 1;
3105 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3106 return r;
3107
3108 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3109 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3110 alu.op = ALU_OP2_ADD_INT;
3111
3112 alu.dst.sel = tmp1;
3113 alu.dst.chan = 3;
3114 alu.dst.write = 1;
3115
3116 alu.src[0].sel = tmp0;
3117 alu.src[0].chan = 2;
3118 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3119
3120 alu.last = 1;
3121 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3122 return r;
3123
3124 }
3125
3126 /* 17. tmp1.x = tmp1.x & tmp1.y */
3127 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3128 alu.op = ALU_OP2_AND_INT;
3129
3130 alu.dst.sel = tmp1;
3131 alu.dst.chan = 0;
3132 alu.dst.write = 1;
3133
3134 alu.src[0].sel = tmp1;
3135 alu.src[0].chan = 0;
3136 alu.src[1].sel = tmp1;
3137 alu.src[1].chan = 1;
3138
3139 alu.last = 1;
3140 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3141 return r;
3142
3143 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3144 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3146 alu.op = ALU_OP3_CNDE_INT;
3147 alu.is_op3 = 1;
3148
3149 alu.dst.sel = tmp0;
3150 alu.dst.chan = 2;
3151 alu.dst.write = 1;
3152
3153 alu.src[0].sel = tmp1;
3154 alu.src[0].chan = 0;
3155 alu.src[1].sel = tmp0;
3156 alu.src[1].chan = mod ? 3 : 2;
3157 alu.src[2].sel = tmp1;
3158 alu.src[2].chan = 2;
3159
3160 alu.last = 1;
3161 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3162 return r;
3163
3164 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3165 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3166 alu.op = ALU_OP3_CNDE_INT;
3167 alu.is_op3 = 1;
3168
3169 if (signed_op) {
3170 alu.dst.sel = tmp0;
3171 alu.dst.chan = 2;
3172 alu.dst.write = 1;
3173 } else {
3174 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3175 }
3176
3177 alu.src[0].sel = tmp1;
3178 alu.src[0].chan = 1;
3179 alu.src[1].sel = tmp1;
3180 alu.src[1].chan = 3;
3181 alu.src[2].sel = tmp0;
3182 alu.src[2].chan = 2;
3183
3184 alu.last = 1;
3185 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3186 return r;
3187
3188 if (signed_op) {
3189
3190 /* fix the sign of the result */
3191
3192 if (mod) {
3193
3194 /* tmp0.x = -tmp0.z */
3195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3196 alu.op = ALU_OP2_SUB_INT;
3197
3198 alu.dst.sel = tmp0;
3199 alu.dst.chan = 0;
3200 alu.dst.write = 1;
3201
3202 alu.src[0].sel = V_SQ_ALU_SRC_0;
3203 alu.src[1].sel = tmp0;
3204 alu.src[1].chan = 2;
3205
3206 alu.last = 1;
3207 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3208 return r;
3209
3210 /* sign of the remainder is the same as the sign of src0 */
3211 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3212 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3213 alu.op = ALU_OP3_CNDGE_INT;
3214 alu.is_op3 = 1;
3215
3216 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3217
3218 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3219 alu.src[1].sel = tmp0;
3220 alu.src[1].chan = 2;
3221 alu.src[2].sel = tmp0;
3222 alu.src[2].chan = 0;
3223
3224 alu.last = 1;
3225 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3226 return r;
3227
3228 } else {
3229
3230 /* tmp0.x = -tmp0.z */
3231 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3232 alu.op = ALU_OP2_SUB_INT;
3233
3234 alu.dst.sel = tmp0;
3235 alu.dst.chan = 0;
3236 alu.dst.write = 1;
3237
3238 alu.src[0].sel = V_SQ_ALU_SRC_0;
3239 alu.src[1].sel = tmp0;
3240 alu.src[1].chan = 2;
3241
3242 alu.last = 1;
3243 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3244 return r;
3245
3246 /* fix the quotient sign (same as the sign of src0*src1) */
3247 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3248 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3249 alu.op = ALU_OP3_CNDGE_INT;
3250 alu.is_op3 = 1;
3251
3252 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3253
3254 alu.src[0].sel = tmp2;
3255 alu.src[0].chan = 2;
3256 alu.src[1].sel = tmp0;
3257 alu.src[1].chan = 2;
3258 alu.src[2].sel = tmp0;
3259 alu.src[2].chan = 0;
3260
3261 alu.last = 1;
3262 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3263 return r;
3264 }
3265 }
3266 }
3267 return 0;
3268 }
3269
3270 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3271 {
3272 return tgsi_divmod(ctx, 0, 0);
3273 }
3274
3275 static int tgsi_umod(struct r600_shader_ctx *ctx)
3276 {
3277 return tgsi_divmod(ctx, 1, 0);
3278 }
3279
3280 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3281 {
3282 return tgsi_divmod(ctx, 0, 1);
3283 }
3284
3285 static int tgsi_imod(struct r600_shader_ctx *ctx)
3286 {
3287 return tgsi_divmod(ctx, 1, 1);
3288 }
3289
3290
3291 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3292 {
3293 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3294 struct r600_bytecode_alu alu;
3295 int i, r;
3296 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3297 int last_inst = tgsi_last_instruction(write_mask);
3298
3299 for (i = 0; i < 4; i++) {
3300 if (!(write_mask & (1<<i)))
3301 continue;
3302
3303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3304 alu.op = ALU_OP1_TRUNC;
3305
3306 alu.dst.sel = ctx->temp_reg;
3307 alu.dst.chan = i;
3308 alu.dst.write = 1;
3309
3310 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3311 if (i == last_inst)
3312 alu.last = 1;
3313 r = r600_bytecode_add_alu(ctx->bc, &alu);
3314 if (r)
3315 return r;
3316 }
3317
3318 for (i = 0; i < 4; i++) {
3319 if (!(write_mask & (1<<i)))
3320 continue;
3321
3322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3323 alu.op = ctx->inst_info->op;
3324
3325 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3326
3327 alu.src[0].sel = ctx->temp_reg;
3328 alu.src[0].chan = i;
3329
3330 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3331 alu.last = 1;
3332 r = r600_bytecode_add_alu(ctx->bc, &alu);
3333 if (r)
3334 return r;
3335 }
3336
3337 return 0;
3338 }
3339
3340 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3341 {
3342 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3343 struct r600_bytecode_alu alu;
3344 int i, r;
3345 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3346 int last_inst = tgsi_last_instruction(write_mask);
3347
3348 /* tmp = -src */
3349 for (i = 0; i < 4; i++) {
3350 if (!(write_mask & (1<<i)))
3351 continue;
3352
3353 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3354 alu.op = ALU_OP2_SUB_INT;
3355
3356 alu.dst.sel = ctx->temp_reg;
3357 alu.dst.chan = i;
3358 alu.dst.write = 1;
3359
3360 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3361 alu.src[0].sel = V_SQ_ALU_SRC_0;
3362
3363 if (i == last_inst)
3364 alu.last = 1;
3365 r = r600_bytecode_add_alu(ctx->bc, &alu);
3366 if (r)
3367 return r;
3368 }
3369
3370 /* dst = (src >= 0 ? src : tmp) */
3371 for (i = 0; i < 4; i++) {
3372 if (!(write_mask & (1<<i)))
3373 continue;
3374
3375 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3376 alu.op = ALU_OP3_CNDGE_INT;
3377 alu.is_op3 = 1;
3378 alu.dst.write = 1;
3379
3380 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3381
3382 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3383 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3384 alu.src[2].sel = ctx->temp_reg;
3385 alu.src[2].chan = i;
3386
3387 if (i == last_inst)
3388 alu.last = 1;
3389 r = r600_bytecode_add_alu(ctx->bc, &alu);
3390 if (r)
3391 return r;
3392 }
3393 return 0;
3394 }
3395
3396 static int tgsi_issg(struct r600_shader_ctx *ctx)
3397 {
3398 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3399 struct r600_bytecode_alu alu;
3400 int i, r;
3401 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3402 int last_inst = tgsi_last_instruction(write_mask);
3403
3404 /* tmp = (src >= 0 ? src : -1) */
3405 for (i = 0; i < 4; i++) {
3406 if (!(write_mask & (1<<i)))
3407 continue;
3408
3409 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3410 alu.op = ALU_OP3_CNDGE_INT;
3411 alu.is_op3 = 1;
3412
3413 alu.dst.sel = ctx->temp_reg;
3414 alu.dst.chan = i;
3415 alu.dst.write = 1;
3416
3417 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3418 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3419 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3420
3421 if (i == last_inst)
3422 alu.last = 1;
3423 r = r600_bytecode_add_alu(ctx->bc, &alu);
3424 if (r)
3425 return r;
3426 }
3427
3428 /* dst = (tmp > 0 ? 1 : tmp) */
3429 for (i = 0; i < 4; i++) {
3430 if (!(write_mask & (1<<i)))
3431 continue;
3432
3433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3434 alu.op = ALU_OP3_CNDGT_INT;
3435 alu.is_op3 = 1;
3436 alu.dst.write = 1;
3437
3438 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3439
3440 alu.src[0].sel = ctx->temp_reg;
3441 alu.src[0].chan = i;
3442
3443 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3444
3445 alu.src[2].sel = ctx->temp_reg;
3446 alu.src[2].chan = i;
3447
3448 if (i == last_inst)
3449 alu.last = 1;
3450 r = r600_bytecode_add_alu(ctx->bc, &alu);
3451 if (r)
3452 return r;
3453 }
3454 return 0;
3455 }
3456
3457
3458
3459 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3460 {
3461 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3462 struct r600_bytecode_alu alu;
3463 int i, r;
3464
3465 /* tmp = (src > 0 ? 1 : src) */
3466 for (i = 0; i < 4; i++) {
3467 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3468 alu.op = ALU_OP3_CNDGT;
3469 alu.is_op3 = 1;
3470
3471 alu.dst.sel = ctx->temp_reg;
3472 alu.dst.chan = i;
3473
3474 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3475 alu.src[1].sel = V_SQ_ALU_SRC_1;
3476 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3477
3478 if (i == 3)
3479 alu.last = 1;
3480 r = r600_bytecode_add_alu(ctx->bc, &alu);
3481 if (r)
3482 return r;
3483 }
3484
3485 /* dst = (-tmp > 0 ? -1 : tmp) */
3486 for (i = 0; i < 4; i++) {
3487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3488 alu.op = ALU_OP3_CNDGT;
3489 alu.is_op3 = 1;
3490 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3491
3492 alu.src[0].sel = ctx->temp_reg;
3493 alu.src[0].chan = i;
3494 alu.src[0].neg = 1;
3495
3496 alu.src[1].sel = V_SQ_ALU_SRC_1;
3497 alu.src[1].neg = 1;
3498
3499 alu.src[2].sel = ctx->temp_reg;
3500 alu.src[2].chan = i;
3501
3502 if (i == 3)
3503 alu.last = 1;
3504 r = r600_bytecode_add_alu(ctx->bc, &alu);
3505 if (r)
3506 return r;
3507 }
3508 return 0;
3509 }
3510
3511 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3512 {
3513 struct r600_bytecode_alu alu;
3514 int i, r;
3515
3516 for (i = 0; i < 4; i++) {
3517 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3518 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3519 alu.op = ALU_OP0_NOP;
3520 alu.dst.chan = i;
3521 } else {
3522 alu.op = ALU_OP1_MOV;
3523 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3524 alu.src[0].sel = ctx->temp_reg;
3525 alu.src[0].chan = i;
3526 }
3527 if (i == 3) {
3528 alu.last = 1;
3529 }
3530 r = r600_bytecode_add_alu(ctx->bc, &alu);
3531 if (r)
3532 return r;
3533 }
3534 return 0;
3535 }
3536
3537 static int tgsi_op3(struct r600_shader_ctx *ctx)
3538 {
3539 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3540 struct r600_bytecode_alu alu;
3541 int i, j, r;
3542 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3543
3544 for (i = 0; i < lasti + 1; i++) {
3545 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3546 continue;
3547
3548 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3549 alu.op = ctx->inst_info->op;
3550 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3551 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3552 }
3553
3554 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3555 alu.dst.chan = i;
3556 alu.dst.write = 1;
3557 alu.is_op3 = 1;
3558 if (i == lasti) {
3559 alu.last = 1;
3560 }
3561 r = r600_bytecode_add_alu(ctx->bc, &alu);
3562 if (r)
3563 return r;
3564 }
3565 return 0;
3566 }
3567
3568 static int tgsi_dp(struct r600_shader_ctx *ctx)
3569 {
3570 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3571 struct r600_bytecode_alu alu;
3572 int i, j, r;
3573
3574 for (i = 0; i < 4; i++) {
3575 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3576 alu.op = ctx->inst_info->op;
3577 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3578 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3579 }
3580
3581 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3582 alu.dst.chan = i;
3583 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3584 /* handle some special cases */
3585 switch (ctx->inst_info->tgsi_opcode) {
3586 case TGSI_OPCODE_DP2:
3587 if (i > 1) {
3588 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3589 alu.src[0].chan = alu.src[1].chan = 0;
3590 }
3591 break;
3592 case TGSI_OPCODE_DP3:
3593 if (i > 2) {
3594 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3595 alu.src[0].chan = alu.src[1].chan = 0;
3596 }
3597 break;
3598 case TGSI_OPCODE_DPH:
3599 if (i == 3) {
3600 alu.src[0].sel = V_SQ_ALU_SRC_1;
3601 alu.src[0].chan = 0;
3602 alu.src[0].neg = 0;
3603 }
3604 break;
3605 default:
3606 break;
3607 }
3608 if (i == 3) {
3609 alu.last = 1;
3610 }
3611 r = r600_bytecode_add_alu(ctx->bc, &alu);
3612 if (r)
3613 return r;
3614 }
3615 return 0;
3616 }
3617
3618 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3619 unsigned index)
3620 {
3621 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3622 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3623 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3624 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3625 ctx->src[index].neg || ctx->src[index].abs;
3626 }
3627
3628 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3629 unsigned index)
3630 {
3631 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3632 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3633 }
3634
3635 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
3636 {
3637 struct r600_bytecode_vtx vtx;
3638 struct r600_bytecode_alu alu;
3639 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3640 int src_gpr, r, i;
3641 int id = tgsi_tex_get_src_gpr(ctx, 1);
3642
3643 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3644 if (src_requires_loading) {
3645 for (i = 0; i < 4; i++) {
3646 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3647 alu.op = ALU_OP1_MOV;
3648 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3649 alu.dst.sel = ctx->temp_reg;
3650 alu.dst.chan = i;
3651 if (i == 3)
3652 alu.last = 1;
3653 alu.dst.write = 1;
3654 r = r600_bytecode_add_alu(ctx->bc, &alu);
3655 if (r)
3656 return r;
3657 }
3658 src_gpr = ctx->temp_reg;
3659 }
3660
3661 memset(&vtx, 0, sizeof(vtx));
3662 vtx.op = FETCH_OP_VFETCH;
3663 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
3664 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
3665 vtx.src_gpr = src_gpr;
3666 vtx.mega_fetch_count = 16;
3667 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3668 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
3669 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
3670 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
3671 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
3672 vtx.use_const_fields = 1;
3673 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
3674
3675 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
3676 return r;
3677
3678 if (ctx->bc->chip_class >= EVERGREEN)
3679 return 0;
3680
3681 for (i = 0; i < 4; i++) {
3682 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3683 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3684 continue;
3685
3686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3687 alu.op = ALU_OP2_AND_INT;
3688
3689 alu.dst.chan = i;
3690 alu.dst.sel = vtx.dst_gpr;
3691 alu.dst.write = 1;
3692
3693 alu.src[0].sel = vtx.dst_gpr;
3694 alu.src[0].chan = i;
3695
3696 alu.src[1].sel = 512 + (id * 2);
3697 alu.src[1].chan = i % 4;
3698 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3699
3700 if (i == lasti)
3701 alu.last = 1;
3702 r = r600_bytecode_add_alu(ctx->bc, &alu);
3703 if (r)
3704 return r;
3705 }
3706
3707 if (inst->Dst[0].Register.WriteMask & 3) {
3708 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3709 alu.op = ALU_OP2_OR_INT;
3710
3711 alu.dst.chan = 3;
3712 alu.dst.sel = vtx.dst_gpr;
3713 alu.dst.write = 1;
3714
3715 alu.src[0].sel = vtx.dst_gpr;
3716 alu.src[0].chan = 3;
3717
3718 alu.src[1].sel = 512 + (id * 2) + 1;
3719 alu.src[1].chan = 0;
3720 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3721
3722 alu.last = 1;
3723 r = r600_bytecode_add_alu(ctx->bc, &alu);
3724 if (r)
3725 return r;
3726 }
3727 return 0;
3728 }
3729
3730 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
3731 {
3732 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3733 struct r600_bytecode_alu alu;
3734 int r;
3735 int id = tgsi_tex_get_src_gpr(ctx, 1);
3736
3737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3738 alu.op = ALU_OP1_MOV;
3739
3740 if (ctx->bc->chip_class >= EVERGREEN) {
3741 alu.src[0].sel = 512 + (id / 4);
3742 alu.src[0].chan = id % 4;
3743 } else {
3744 /* r600 we have them at channel 2 of the second dword */
3745 alu.src[0].sel = 512 + (id * 2) + 1;
3746 alu.src[0].chan = 1;
3747 }
3748 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3749 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3750 alu.last = 1;
3751 r = r600_bytecode_add_alu(ctx->bc, &alu);
3752 if (r)
3753 return r;
3754 return 0;
3755 }
3756
3757 static int tgsi_tex(struct r600_shader_ctx *ctx)
3758 {
3759 static float one_point_five = 1.5f;
3760 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3761 struct r600_bytecode_tex tex;
3762 struct r600_bytecode_alu alu;
3763 unsigned src_gpr;
3764 int r, i, j;
3765 int opcode;
3766 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
3767 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
3768 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
3769 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
3770
3771 /* Texture fetch instructions can only use gprs as source.
3772 * Also they cannot negate the source or take the absolute value */
3773 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
3774 tgsi_tex_src_requires_loading(ctx, 0)) ||
3775 read_compressed_msaa;
3776 boolean src_loaded = FALSE;
3777 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
3778 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
3779 boolean has_txq_cube_array_z = false;
3780
3781 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
3782 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3783 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
3784 if (inst->Dst[0].Register.WriteMask & 4) {
3785 ctx->shader->has_txq_cube_array_z_comp = true;
3786 has_txq_cube_array_z = true;
3787 }
3788
3789 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
3790 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
3791 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
3792 sampler_src_reg = 2;
3793
3794 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3795
3796 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
3797 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
3798 ctx->shader->uses_tex_buffers = true;
3799 return r600_do_buffer_txq(ctx);
3800 }
3801 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3802 if (ctx->bc->chip_class < EVERGREEN)
3803 ctx->shader->uses_tex_buffers = true;
3804 return do_vtx_fetch_inst(ctx, src_requires_loading);
3805 }
3806 }
3807
3808 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3809 /* get offset values */
3810 if (inst->Texture.NumOffsets) {
3811 assert(inst->Texture.NumOffsets == 1);
3812
3813 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
3814 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
3815 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
3816 }
3817 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3818 /* TGSI moves the sampler to src reg 3 for TXD */
3819 sampler_src_reg = 3;
3820
3821 for (i = 1; i < 3; i++) {
3822 /* set gradients h/v */
3823 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3824 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
3825 FETCH_OP_SET_GRADIENTS_V;
3826 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3827 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3828
3829 if (tgsi_tex_src_requires_loading(ctx, i)) {
3830 tex.src_gpr = r600_get_temp(ctx);
3831 tex.src_sel_x = 0;
3832 tex.src_sel_y = 1;
3833 tex.src_sel_z = 2;
3834 tex.src_sel_w = 3;
3835
3836 for (j = 0; j < 4; j++) {
3837 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3838 alu.op = ALU_OP1_MOV;
3839 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
3840 alu.dst.sel = tex.src_gpr;
3841 alu.dst.chan = j;
3842 if (j == 3)
3843 alu.last = 1;
3844 alu.dst.write = 1;
3845 r = r600_bytecode_add_alu(ctx->bc, &alu);
3846 if (r)
3847 return r;
3848 }
3849
3850 } else {
3851 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
3852 tex.src_sel_x = ctx->src[i].swizzle[0];
3853 tex.src_sel_y = ctx->src[i].swizzle[1];
3854 tex.src_sel_z = ctx->src[i].swizzle[2];
3855 tex.src_sel_w = ctx->src[i].swizzle[3];
3856 tex.src_rel = ctx->src[i].rel;
3857 }
3858 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
3859 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
3860 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
3861 tex.coord_type_x = 1;
3862 tex.coord_type_y = 1;
3863 tex.coord_type_z = 1;
3864 tex.coord_type_w = 1;
3865 }
3866 r = r600_bytecode_add_tex(ctx->bc, &tex);
3867 if (r)
3868 return r;
3869 }
3870 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3871 int out_chan;
3872 /* Add perspective divide */
3873 if (ctx->bc->chip_class == CAYMAN) {
3874 out_chan = 2;
3875 for (i = 0; i < 3; i++) {
3876 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3877 alu.op = ALU_OP1_RECIP_IEEE;
3878 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3879
3880 alu.dst.sel = ctx->temp_reg;
3881 alu.dst.chan = i;
3882 if (i == 2)
3883 alu.last = 1;
3884 if (out_chan == i)
3885 alu.dst.write = 1;
3886 r = r600_bytecode_add_alu(ctx->bc, &alu);
3887 if (r)
3888 return r;
3889 }
3890
3891 } else {
3892 out_chan = 3;
3893 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3894 alu.op = ALU_OP1_RECIP_IEEE;
3895 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3896
3897 alu.dst.sel = ctx->temp_reg;
3898 alu.dst.chan = out_chan;
3899 alu.last = 1;
3900 alu.dst.write = 1;
3901 r = r600_bytecode_add_alu(ctx->bc, &alu);
3902 if (r)
3903 return r;
3904 }
3905
3906 for (i = 0; i < 3; i++) {
3907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3908 alu.op = ALU_OP2_MUL;
3909 alu.src[0].sel = ctx->temp_reg;
3910 alu.src[0].chan = out_chan;
3911 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3912 alu.dst.sel = ctx->temp_reg;
3913 alu.dst.chan = i;
3914 alu.dst.write = 1;
3915 r = r600_bytecode_add_alu(ctx->bc, &alu);
3916 if (r)
3917 return r;
3918 }
3919 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3920 alu.op = ALU_OP1_MOV;
3921 alu.src[0].sel = V_SQ_ALU_SRC_1;
3922 alu.src[0].chan = 0;
3923 alu.dst.sel = ctx->temp_reg;
3924 alu.dst.chan = 3;
3925 alu.last = 1;
3926 alu.dst.write = 1;
3927 r = r600_bytecode_add_alu(ctx->bc, &alu);
3928 if (r)
3929 return r;
3930 src_loaded = TRUE;
3931 src_gpr = ctx->temp_reg;
3932 }
3933
3934 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
3935 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3936 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
3937 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
3938 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
3939 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
3940
3941 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
3942 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
3943
3944 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3945 for (i = 0; i < 4; i++) {
3946 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3947 alu.op = ALU_OP2_CUBE;
3948 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3949 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
3950 alu.dst.sel = ctx->temp_reg;
3951 alu.dst.chan = i;
3952 if (i == 3)
3953 alu.last = 1;
3954 alu.dst.write = 1;
3955 r = r600_bytecode_add_alu(ctx->bc, &alu);
3956 if (r)
3957 return r;
3958 }
3959
3960 /* tmp1.z = RCP_e(|tmp1.z|) */
3961 if (ctx->bc->chip_class == CAYMAN) {
3962 for (i = 0; i < 3; i++) {
3963 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3964 alu.op = ALU_OP1_RECIP_IEEE;
3965 alu.src[0].sel = ctx->temp_reg;
3966 alu.src[0].chan = 2;
3967 alu.src[0].abs = 1;
3968 alu.dst.sel = ctx->temp_reg;
3969 alu.dst.chan = i;
3970 if (i == 2)
3971 alu.dst.write = 1;
3972 if (i == 2)
3973 alu.last = 1;
3974 r = r600_bytecode_add_alu(ctx->bc, &alu);
3975 if (r)
3976 return r;
3977 }
3978 } else {
3979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3980 alu.op = ALU_OP1_RECIP_IEEE;
3981 alu.src[0].sel = ctx->temp_reg;
3982 alu.src[0].chan = 2;
3983 alu.src[0].abs = 1;
3984 alu.dst.sel = ctx->temp_reg;
3985 alu.dst.chan = 2;
3986 alu.dst.write = 1;
3987 alu.last = 1;
3988 r = r600_bytecode_add_alu(ctx->bc, &alu);
3989 if (r)
3990 return r;
3991 }
3992
3993 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
3994 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
3995 * muladd has no writemask, have to use another temp
3996 */
3997 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3998 alu.op = ALU_OP3_MULADD;
3999 alu.is_op3 = 1;
4000
4001 alu.src[0].sel = ctx->temp_reg;
4002 alu.src[0].chan = 0;
4003 alu.src[1].sel = ctx->temp_reg;
4004 alu.src[1].chan = 2;
4005
4006 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4007 alu.src[2].chan = 0;
4008 alu.src[2].value = *(uint32_t *)&one_point_five;
4009
4010 alu.dst.sel = ctx->temp_reg;
4011 alu.dst.chan = 0;
4012 alu.dst.write = 1;
4013
4014 r = r600_bytecode_add_alu(ctx->bc, &alu);
4015 if (r)
4016 return r;
4017
4018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4019 alu.op = ALU_OP3_MULADD;
4020 alu.is_op3 = 1;
4021
4022 alu.src[0].sel = ctx->temp_reg;
4023 alu.src[0].chan = 1;
4024 alu.src[1].sel = ctx->temp_reg;
4025 alu.src[1].chan = 2;
4026
4027 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4028 alu.src[2].chan = 0;
4029 alu.src[2].value = *(uint32_t *)&one_point_five;
4030
4031 alu.dst.sel = ctx->temp_reg;
4032 alu.dst.chan = 1;
4033 alu.dst.write = 1;
4034
4035 alu.last = 1;
4036 r = r600_bytecode_add_alu(ctx->bc, &alu);
4037 if (r)
4038 return r;
4039 /* write initial compare value into Z component
4040 - W src 0 for shadow cube
4041 - X src 1 for shadow cube array */
4042 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4043 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4045 alu.op = ALU_OP1_MOV;
4046 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4047 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4048 else
4049 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4050 alu.dst.sel = ctx->temp_reg;
4051 alu.dst.chan = 2;
4052 alu.dst.write = 1;
4053 alu.last = 1;
4054 r = r600_bytecode_add_alu(ctx->bc, &alu);
4055 if (r)
4056 return r;
4057 }
4058
4059 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4060 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4061 if (ctx->bc->chip_class >= EVERGREEN) {
4062 int mytmp = r600_get_temp(ctx);
4063 static const float eight = 8.0f;
4064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4065 alu.op = ALU_OP1_MOV;
4066 alu.src[0].sel = ctx->temp_reg;
4067 alu.src[0].chan = 3;
4068 alu.dst.sel = mytmp;
4069 alu.dst.chan = 0;
4070 alu.dst.write = 1;
4071 alu.last = 1;
4072 r = r600_bytecode_add_alu(ctx->bc, &alu);
4073 if (r)
4074 return r;
4075
4076 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4078 alu.op = ALU_OP3_MULADD;
4079 alu.is_op3 = 1;
4080 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4081 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4082 alu.src[1].chan = 0;
4083 alu.src[1].value = *(uint32_t *)&eight;
4084 alu.src[2].sel = mytmp;
4085 alu.src[2].chan = 0;
4086 alu.dst.sel = ctx->temp_reg;
4087 alu.dst.chan = 3;
4088 alu.dst.write = 1;
4089 alu.last = 1;
4090 r = r600_bytecode_add_alu(ctx->bc, &alu);
4091 if (r)
4092 return r;
4093 } else if (ctx->bc->chip_class < EVERGREEN) {
4094 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4095 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4096 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4097 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4098 tex.src_gpr = r600_get_temp(ctx);
4099 tex.src_sel_x = 0;
4100 tex.src_sel_y = 0;
4101 tex.src_sel_z = 0;
4102 tex.src_sel_w = 0;
4103 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4104 tex.coord_type_x = 1;
4105 tex.coord_type_y = 1;
4106 tex.coord_type_z = 1;
4107 tex.coord_type_w = 1;
4108 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4109 alu.op = ALU_OP1_MOV;
4110 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4111 alu.dst.sel = tex.src_gpr;
4112 alu.dst.chan = 0;
4113 alu.last = 1;
4114 alu.dst.write = 1;
4115 r = r600_bytecode_add_alu(ctx->bc, &alu);
4116 if (r)
4117 return r;
4118
4119 r = r600_bytecode_add_tex(ctx->bc, &tex);
4120 if (r)
4121 return r;
4122 }
4123
4124 }
4125
4126 /* for cube forms of lod and bias we need to route things */
4127 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4128 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4129 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4130 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4131 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4132 alu.op = ALU_OP1_MOV;
4133 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4134 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4135 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4136 else
4137 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4138 alu.dst.sel = ctx->temp_reg;
4139 alu.dst.chan = 2;
4140 alu.last = 1;
4141 alu.dst.write = 1;
4142 r = r600_bytecode_add_alu(ctx->bc, &alu);
4143 if (r)
4144 return r;
4145 }
4146
4147 src_loaded = TRUE;
4148 src_gpr = ctx->temp_reg;
4149 }
4150
4151 if (src_requires_loading && !src_loaded) {
4152 for (i = 0; i < 4; i++) {
4153 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4154 alu.op = ALU_OP1_MOV;
4155 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4156 alu.dst.sel = ctx->temp_reg;
4157 alu.dst.chan = i;
4158 if (i == 3)
4159 alu.last = 1;
4160 alu.dst.write = 1;
4161 r = r600_bytecode_add_alu(ctx->bc, &alu);
4162 if (r)
4163 return r;
4164 }
4165 src_loaded = TRUE;
4166 src_gpr = ctx->temp_reg;
4167 }
4168
4169 /* Obtain the sample index for reading a compressed MSAA color texture.
4170 * To read the FMASK, we use the ldfptr instruction, which tells us
4171 * where the samples are stored.
4172 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4173 * which is the identity mapping. Each nibble says which physical sample
4174 * should be fetched to get that sample.
4175 *
4176 * Assume src.z contains the sample index. It should be modified like this:
4177 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4178 * Then fetch the texel with src.
4179 */
4180 if (read_compressed_msaa) {
4181 unsigned sample_chan = 3;
4182 unsigned temp = r600_get_temp(ctx);
4183 assert(src_loaded);
4184
4185 /* temp.w = ldfptr() */
4186 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4187 tex.op = FETCH_OP_LD;
4188 tex.inst_mod = 1; /* to indicate this is ldfptr */
4189 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4190 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4191 tex.src_gpr = src_gpr;
4192 tex.dst_gpr = temp;
4193 tex.dst_sel_x = 7; /* mask out these components */
4194 tex.dst_sel_y = 7;
4195 tex.dst_sel_z = 7;
4196 tex.dst_sel_w = 0; /* store X */
4197 tex.src_sel_x = 0;
4198 tex.src_sel_y = 1;
4199 tex.src_sel_z = 2;
4200 tex.src_sel_w = 3;
4201 tex.offset_x = offset_x;
4202 tex.offset_y = offset_y;
4203 tex.offset_z = offset_z;
4204 r = r600_bytecode_add_tex(ctx->bc, &tex);
4205 if (r)
4206 return r;
4207
4208 /* temp.x = sample_index*4 */
4209 if (ctx->bc->chip_class == CAYMAN) {
4210 for (i = 0 ; i < 4; i++) {
4211 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4212 alu.op = ALU_OP2_MULLO_INT;
4213 alu.src[0].sel = src_gpr;
4214 alu.src[0].chan = sample_chan;
4215 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4216 alu.src[1].value = 4;
4217 alu.dst.sel = temp;
4218 alu.dst.chan = i;
4219 alu.dst.write = i == 0;
4220 if (i == 3)
4221 alu.last = 1;
4222 r = r600_bytecode_add_alu(ctx->bc, &alu);
4223 if (r)
4224 return r;
4225 }
4226 } else {
4227 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4228 alu.op = ALU_OP2_MULLO_INT;
4229 alu.src[0].sel = src_gpr;
4230 alu.src[0].chan = sample_chan;
4231 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4232 alu.src[1].value = 4;
4233 alu.dst.sel = temp;
4234 alu.dst.chan = 0;
4235 alu.dst.write = 1;
4236 alu.last = 1;
4237 r = r600_bytecode_add_alu(ctx->bc, &alu);
4238 if (r)
4239 return r;
4240 }
4241
4242 /* sample_index = temp.w >> temp.x */
4243 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4244 alu.op = ALU_OP2_LSHR_INT;
4245 alu.src[0].sel = temp;
4246 alu.src[0].chan = 3;
4247 alu.src[1].sel = temp;
4248 alu.src[1].chan = 0;
4249 alu.dst.sel = src_gpr;
4250 alu.dst.chan = sample_chan;
4251 alu.dst.write = 1;
4252 alu.last = 1;
4253 r = r600_bytecode_add_alu(ctx->bc, &alu);
4254 if (r)
4255 return r;
4256
4257 /* sample_index & 0xF */
4258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4259 alu.op = ALU_OP2_AND_INT;
4260 alu.src[0].sel = src_gpr;
4261 alu.src[0].chan = sample_chan;
4262 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4263 alu.src[1].value = 0xF;
4264 alu.dst.sel = src_gpr;
4265 alu.dst.chan = sample_chan;
4266 alu.dst.write = 1;
4267 alu.last = 1;
4268 r = r600_bytecode_add_alu(ctx->bc, &alu);
4269 if (r)
4270 return r;
4271 #if 0
4272 /* visualize the FMASK */
4273 for (i = 0; i < 4; i++) {
4274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4275 alu.op = ALU_OP1_INT_TO_FLT;
4276 alu.src[0].sel = src_gpr;
4277 alu.src[0].chan = sample_chan;
4278 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4279 alu.dst.chan = i;
4280 alu.dst.write = 1;
4281 alu.last = 1;
4282 r = r600_bytecode_add_alu(ctx->bc, &alu);
4283 if (r)
4284 return r;
4285 }
4286 return 0;
4287 #endif
4288 }
4289
4290 /* does this shader want a num layers from TXQ for a cube array? */
4291 if (has_txq_cube_array_z) {
4292 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4293
4294 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4295 alu.op = ALU_OP1_MOV;
4296
4297 alu.src[0].sel = 512 + (id / 4);
4298 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4299 alu.src[0].chan = id % 4;
4300 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4301 alu.last = 1;
4302 r = r600_bytecode_add_alu(ctx->bc, &alu);
4303 if (r)
4304 return r;
4305 /* disable writemask from texture instruction */
4306 inst->Dst[0].Register.WriteMask &= ~4;
4307 }
4308
4309 opcode = ctx->inst_info->op;
4310 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4311 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4312 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4313 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4314 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4315 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4316 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4317 switch (opcode) {
4318 case FETCH_OP_SAMPLE:
4319 opcode = FETCH_OP_SAMPLE_C;
4320 break;
4321 case FETCH_OP_SAMPLE_L:
4322 opcode = FETCH_OP_SAMPLE_C_L;
4323 break;
4324 case FETCH_OP_SAMPLE_LB:
4325 opcode = FETCH_OP_SAMPLE_C_LB;
4326 break;
4327 case FETCH_OP_SAMPLE_G:
4328 opcode = FETCH_OP_SAMPLE_C_G;
4329 break;
4330 }
4331 }
4332
4333 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4334 tex.op = opcode;
4335
4336 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4337 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4338 tex.src_gpr = src_gpr;
4339 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4340 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4341 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4342 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4343 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4344
4345 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4346 tex.src_sel_x = 4;
4347 tex.src_sel_y = 4;
4348 tex.src_sel_z = 4;
4349 tex.src_sel_w = 4;
4350 } else if (src_loaded) {
4351 tex.src_sel_x = 0;
4352 tex.src_sel_y = 1;
4353 tex.src_sel_z = 2;
4354 tex.src_sel_w = 3;
4355 } else {
4356 tex.src_sel_x = ctx->src[0].swizzle[0];
4357 tex.src_sel_y = ctx->src[0].swizzle[1];
4358 tex.src_sel_z = ctx->src[0].swizzle[2];
4359 tex.src_sel_w = ctx->src[0].swizzle[3];
4360 tex.src_rel = ctx->src[0].rel;
4361 }
4362
4363 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4364 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4365 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4366 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4367 tex.src_sel_x = 1;
4368 tex.src_sel_y = 0;
4369 tex.src_sel_z = 3;
4370 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4371 }
4372
4373 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4374 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4375 tex.coord_type_x = 1;
4376 tex.coord_type_y = 1;
4377 }
4378 tex.coord_type_z = 1;
4379 tex.coord_type_w = 1;
4380
4381 tex.offset_x = offset_x;
4382 tex.offset_y = offset_y;
4383 tex.offset_z = offset_z;
4384
4385 /* Put the depth for comparison in W.
4386 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4387 * Some instructions expect the depth in Z. */
4388 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4389 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4390 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4391 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4392 opcode != FETCH_OP_SAMPLE_C_L &&
4393 opcode != FETCH_OP_SAMPLE_C_LB) {
4394 tex.src_sel_w = tex.src_sel_z;
4395 }
4396
4397 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4398 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4399 if (opcode == FETCH_OP_SAMPLE_C_L ||
4400 opcode == FETCH_OP_SAMPLE_C_LB) {
4401 /* the array index is read from Y */
4402 tex.coord_type_y = 0;
4403 } else {
4404 /* the array index is read from Z */
4405 tex.coord_type_z = 0;
4406 tex.src_sel_z = tex.src_sel_y;
4407 }
4408 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4409 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4410 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4411 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4412 (ctx->bc->chip_class >= EVERGREEN)))
4413 /* the array index is read from Z */
4414 tex.coord_type_z = 0;
4415
4416 /* mask unused source components */
4417 if (opcode == FETCH_OP_SAMPLE) {
4418 switch (inst->Texture.Texture) {
4419 case TGSI_TEXTURE_2D:
4420 case TGSI_TEXTURE_RECT:
4421 tex.src_sel_z = 7;
4422 tex.src_sel_w = 7;
4423 break;
4424 case TGSI_TEXTURE_1D_ARRAY:
4425 tex.src_sel_y = 7;
4426 tex.src_sel_w = 7;
4427 break;
4428 case TGSI_TEXTURE_1D:
4429 tex.src_sel_y = 7;
4430 tex.src_sel_z = 7;
4431 tex.src_sel_w = 7;
4432 break;
4433 }
4434 }
4435
4436 r = r600_bytecode_add_tex(ctx->bc, &tex);
4437 if (r)
4438 return r;
4439
4440 /* add shadow ambient support - gallium doesn't do it yet */
4441 return 0;
4442 }
4443
4444 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4445 {
4446 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4447 struct r600_bytecode_alu alu;
4448 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4449 unsigned i;
4450 int r;
4451
4452 /* optimize if it's just an equal balance */
4453 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4454 for (i = 0; i < lasti + 1; i++) {
4455 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4456 continue;
4457
4458 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4459 alu.op = ALU_OP2_ADD;
4460 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4461 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4462 alu.omod = 3;
4463 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4464 alu.dst.chan = i;
4465 if (i == lasti) {
4466 alu.last = 1;
4467 }
4468 r = r600_bytecode_add_alu(ctx->bc, &alu);
4469 if (r)
4470 return r;
4471 }
4472 return 0;
4473 }
4474
4475 /* 1 - src0 */
4476 for (i = 0; i < lasti + 1; i++) {
4477 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4478 continue;
4479
4480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4481 alu.op = ALU_OP2_ADD;
4482 alu.src[0].sel = V_SQ_ALU_SRC_1;
4483 alu.src[0].chan = 0;
4484 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4485 r600_bytecode_src_toggle_neg(&alu.src[1]);
4486 alu.dst.sel = ctx->temp_reg;
4487 alu.dst.chan = i;
4488 if (i == lasti) {
4489 alu.last = 1;
4490 }
4491 alu.dst.write = 1;
4492 r = r600_bytecode_add_alu(ctx->bc, &alu);
4493 if (r)
4494 return r;
4495 }
4496
4497 /* (1 - src0) * src2 */
4498 for (i = 0; i < lasti + 1; i++) {
4499 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4500 continue;
4501
4502 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4503 alu.op = ALU_OP2_MUL;
4504 alu.src[0].sel = ctx->temp_reg;
4505 alu.src[0].chan = i;
4506 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4507 alu.dst.sel = ctx->temp_reg;
4508 alu.dst.chan = i;
4509 if (i == lasti) {
4510 alu.last = 1;
4511 }
4512 alu.dst.write = 1;
4513 r = r600_bytecode_add_alu(ctx->bc, &alu);
4514 if (r)
4515 return r;
4516 }
4517
4518 /* src0 * src1 + (1 - src0) * src2 */
4519 for (i = 0; i < lasti + 1; i++) {
4520 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4521 continue;
4522
4523 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4524 alu.op = ALU_OP3_MULADD;
4525 alu.is_op3 = 1;
4526 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4527 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4528 alu.src[2].sel = ctx->temp_reg;
4529 alu.src[2].chan = i;
4530
4531 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4532 alu.dst.chan = i;
4533 if (i == lasti) {
4534 alu.last = 1;
4535 }
4536 r = r600_bytecode_add_alu(ctx->bc, &alu);
4537 if (r)
4538 return r;
4539 }
4540 return 0;
4541 }
4542
4543 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4544 {
4545 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4546 struct r600_bytecode_alu alu;
4547 int i, r;
4548 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4549
4550 for (i = 0; i < lasti + 1; i++) {
4551 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4552 continue;
4553
4554 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4555 alu.op = ALU_OP3_CNDGE;
4556 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4557 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4558 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4559 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4560 alu.dst.chan = i;
4561 alu.dst.write = 1;
4562 alu.is_op3 = 1;
4563 if (i == lasti)
4564 alu.last = 1;
4565 r = r600_bytecode_add_alu(ctx->bc, &alu);
4566 if (r)
4567 return r;
4568 }
4569 return 0;
4570 }
4571
4572 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4573 {
4574 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4575 struct r600_bytecode_alu alu;
4576 int i, r;
4577 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4578
4579 for (i = 0; i < lasti + 1; i++) {
4580 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4581 continue;
4582
4583 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4584 alu.op = ALU_OP3_CNDGE_INT;
4585 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4586 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4587 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4588 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4589 alu.dst.chan = i;
4590 alu.dst.write = 1;
4591 alu.is_op3 = 1;
4592 if (i == lasti)
4593 alu.last = 1;
4594 r = r600_bytecode_add_alu(ctx->bc, &alu);
4595 if (r)
4596 return r;
4597 }
4598 return 0;
4599 }
4600
4601 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4602 {
4603 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4604 static const unsigned int src0_swizzle[] = {2, 0, 1};
4605 static const unsigned int src1_swizzle[] = {1, 2, 0};
4606 struct r600_bytecode_alu alu;
4607 uint32_t use_temp = 0;
4608 int i, r;
4609
4610 if (inst->Dst[0].Register.WriteMask != 0xf)
4611 use_temp = 1;
4612
4613 for (i = 0; i < 4; i++) {
4614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4615 alu.op = ALU_OP2_MUL;
4616 if (i < 3) {
4617 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4618 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4619 } else {
4620 alu.src[0].sel = V_SQ_ALU_SRC_0;
4621 alu.src[0].chan = i;
4622 alu.src[1].sel = V_SQ_ALU_SRC_0;
4623 alu.src[1].chan = i;
4624 }
4625
4626 alu.dst.sel = ctx->temp_reg;
4627 alu.dst.chan = i;
4628 alu.dst.write = 1;
4629
4630 if (i == 3)
4631 alu.last = 1;
4632 r = r600_bytecode_add_alu(ctx->bc, &alu);
4633 if (r)
4634 return r;
4635 }
4636
4637 for (i = 0; i < 4; i++) {
4638 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4639 alu.op = ALU_OP3_MULADD;
4640
4641 if (i < 3) {
4642 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4643 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4644 } else {
4645 alu.src[0].sel = V_SQ_ALU_SRC_0;
4646 alu.src[0].chan = i;
4647 alu.src[1].sel = V_SQ_ALU_SRC_0;
4648 alu.src[1].chan = i;
4649 }
4650
4651 alu.src[2].sel = ctx->temp_reg;
4652 alu.src[2].neg = 1;
4653 alu.src[2].chan = i;
4654
4655 if (use_temp)
4656 alu.dst.sel = ctx->temp_reg;
4657 else
4658 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4659 alu.dst.chan = i;
4660 alu.dst.write = 1;
4661 alu.is_op3 = 1;
4662 if (i == 3)
4663 alu.last = 1;
4664 r = r600_bytecode_add_alu(ctx->bc, &alu);
4665 if (r)
4666 return r;
4667 }
4668 if (use_temp)
4669 return tgsi_helper_copy(ctx, inst);
4670 return 0;
4671 }
4672
4673 static int tgsi_exp(struct r600_shader_ctx *ctx)
4674 {
4675 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4676 struct r600_bytecode_alu alu;
4677 int r;
4678 int i;
4679
4680 /* result.x = 2^floor(src); */
4681 if (inst->Dst[0].Register.WriteMask & 1) {
4682 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4683
4684 alu.op = ALU_OP1_FLOOR;
4685 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4686
4687 alu.dst.sel = ctx->temp_reg;
4688 alu.dst.chan = 0;
4689 alu.dst.write = 1;
4690 alu.last = 1;
4691 r = r600_bytecode_add_alu(ctx->bc, &alu);
4692 if (r)
4693 return r;
4694
4695 if (ctx->bc->chip_class == CAYMAN) {
4696 for (i = 0; i < 3; i++) {
4697 alu.op = ALU_OP1_EXP_IEEE;
4698 alu.src[0].sel = ctx->temp_reg;
4699 alu.src[0].chan = 0;
4700
4701 alu.dst.sel = ctx->temp_reg;
4702 alu.dst.chan = i;
4703 alu.dst.write = i == 0;
4704 alu.last = i == 2;
4705 r = r600_bytecode_add_alu(ctx->bc, &alu);
4706 if (r)
4707 return r;
4708 }
4709 } else {
4710 alu.op = ALU_OP1_EXP_IEEE;
4711 alu.src[0].sel = ctx->temp_reg;
4712 alu.src[0].chan = 0;
4713
4714 alu.dst.sel = ctx->temp_reg;
4715 alu.dst.chan = 0;
4716 alu.dst.write = 1;
4717 alu.last = 1;
4718 r = r600_bytecode_add_alu(ctx->bc, &alu);
4719 if (r)
4720 return r;
4721 }
4722 }
4723
4724 /* result.y = tmp - floor(tmp); */
4725 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4727
4728 alu.op = ALU_OP1_FRACT;
4729 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4730
4731 alu.dst.sel = ctx->temp_reg;
4732 #if 0
4733 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4734 if (r)
4735 return r;
4736 #endif
4737 alu.dst.write = 1;
4738 alu.dst.chan = 1;
4739
4740 alu.last = 1;
4741
4742 r = r600_bytecode_add_alu(ctx->bc, &alu);
4743 if (r)
4744 return r;
4745 }
4746
4747 /* result.z = RoughApprox2ToX(tmp);*/
4748 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
4749 if (ctx->bc->chip_class == CAYMAN) {
4750 for (i = 0; i < 3; i++) {
4751 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4752 alu.op = ALU_OP1_EXP_IEEE;
4753 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4754
4755 alu.dst.sel = ctx->temp_reg;
4756 alu.dst.chan = i;
4757 if (i == 2) {
4758 alu.dst.write = 1;
4759 alu.last = 1;
4760 }
4761
4762 r = r600_bytecode_add_alu(ctx->bc, &alu);
4763 if (r)
4764 return r;
4765 }
4766 } else {
4767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4768 alu.op = ALU_OP1_EXP_IEEE;
4769 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4770
4771 alu.dst.sel = ctx->temp_reg;
4772 alu.dst.write = 1;
4773 alu.dst.chan = 2;
4774
4775 alu.last = 1;
4776
4777 r = r600_bytecode_add_alu(ctx->bc, &alu);
4778 if (r)
4779 return r;
4780 }
4781 }
4782
4783 /* result.w = 1.0;*/
4784 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
4785 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4786
4787 alu.op = ALU_OP1_MOV;
4788 alu.src[0].sel = V_SQ_ALU_SRC_1;
4789 alu.src[0].chan = 0;
4790
4791 alu.dst.sel = ctx->temp_reg;
4792 alu.dst.chan = 3;
4793 alu.dst.write = 1;
4794 alu.last = 1;
4795 r = r600_bytecode_add_alu(ctx->bc, &alu);
4796 if (r)
4797 return r;
4798 }
4799 return tgsi_helper_copy(ctx, inst);
4800 }
4801
4802 static int tgsi_log(struct r600_shader_ctx *ctx)
4803 {
4804 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4805 struct r600_bytecode_alu alu;
4806 int r;
4807 int i;
4808
4809 /* result.x = floor(log2(|src|)); */
4810 if (inst->Dst[0].Register.WriteMask & 1) {
4811 if (ctx->bc->chip_class == CAYMAN) {
4812 for (i = 0; i < 3; i++) {
4813 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4814
4815 alu.op = ALU_OP1_LOG_IEEE;
4816 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4817 r600_bytecode_src_set_abs(&alu.src[0]);
4818
4819 alu.dst.sel = ctx->temp_reg;
4820 alu.dst.chan = i;
4821 if (i == 0)
4822 alu.dst.write = 1;
4823 if (i == 2)
4824 alu.last = 1;
4825 r = r600_bytecode_add_alu(ctx->bc, &alu);
4826 if (r)
4827 return r;
4828 }
4829
4830 } else {
4831 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4832
4833 alu.op = ALU_OP1_LOG_IEEE;
4834 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4835 r600_bytecode_src_set_abs(&alu.src[0]);
4836
4837 alu.dst.sel = ctx->temp_reg;
4838 alu.dst.chan = 0;
4839 alu.dst.write = 1;
4840 alu.last = 1;
4841 r = r600_bytecode_add_alu(ctx->bc, &alu);
4842 if (r)
4843 return r;
4844 }
4845
4846 alu.op = ALU_OP1_FLOOR;
4847 alu.src[0].sel = ctx->temp_reg;
4848 alu.src[0].chan = 0;
4849
4850 alu.dst.sel = ctx->temp_reg;
4851 alu.dst.chan = 0;
4852 alu.dst.write = 1;
4853 alu.last = 1;
4854
4855 r = r600_bytecode_add_alu(ctx->bc, &alu);
4856 if (r)
4857 return r;
4858 }
4859
4860 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4861 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4862
4863 if (ctx->bc->chip_class == CAYMAN) {
4864 for (i = 0; i < 3; i++) {
4865 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4866
4867 alu.op = ALU_OP1_LOG_IEEE;
4868 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4869 r600_bytecode_src_set_abs(&alu.src[0]);
4870
4871 alu.dst.sel = ctx->temp_reg;
4872 alu.dst.chan = i;
4873 if (i == 1)
4874 alu.dst.write = 1;
4875 if (i == 2)
4876 alu.last = 1;
4877
4878 r = r600_bytecode_add_alu(ctx->bc, &alu);
4879 if (r)
4880 return r;
4881 }
4882 } else {
4883 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4884
4885 alu.op = ALU_OP1_LOG_IEEE;
4886 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4887 r600_bytecode_src_set_abs(&alu.src[0]);
4888
4889 alu.dst.sel = ctx->temp_reg;
4890 alu.dst.chan = 1;
4891 alu.dst.write = 1;
4892 alu.last = 1;
4893
4894 r = r600_bytecode_add_alu(ctx->bc, &alu);
4895 if (r)
4896 return r;
4897 }
4898
4899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4900
4901 alu.op = ALU_OP1_FLOOR;
4902 alu.src[0].sel = ctx->temp_reg;
4903 alu.src[0].chan = 1;
4904
4905 alu.dst.sel = ctx->temp_reg;
4906 alu.dst.chan = 1;
4907 alu.dst.write = 1;
4908 alu.last = 1;
4909
4910 r = r600_bytecode_add_alu(ctx->bc, &alu);
4911 if (r)
4912 return r;
4913
4914 if (ctx->bc->chip_class == CAYMAN) {
4915 for (i = 0; i < 3; i++) {
4916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4917 alu.op = ALU_OP1_EXP_IEEE;
4918 alu.src[0].sel = ctx->temp_reg;
4919 alu.src[0].chan = 1;
4920
4921 alu.dst.sel = ctx->temp_reg;
4922 alu.dst.chan = i;
4923 if (i == 1)
4924 alu.dst.write = 1;
4925 if (i == 2)
4926 alu.last = 1;
4927
4928 r = r600_bytecode_add_alu(ctx->bc, &alu);
4929 if (r)
4930 return r;
4931 }
4932 } else {
4933 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4934 alu.op = ALU_OP1_EXP_IEEE;
4935 alu.src[0].sel = ctx->temp_reg;
4936 alu.src[0].chan = 1;
4937
4938 alu.dst.sel = ctx->temp_reg;
4939 alu.dst.chan = 1;
4940 alu.dst.write = 1;
4941 alu.last = 1;
4942
4943 r = r600_bytecode_add_alu(ctx->bc, &alu);
4944 if (r)
4945 return r;
4946 }
4947
4948 if (ctx->bc->chip_class == CAYMAN) {
4949 for (i = 0; i < 3; i++) {
4950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4951 alu.op = ALU_OP1_RECIP_IEEE;
4952 alu.src[0].sel = ctx->temp_reg;
4953 alu.src[0].chan = 1;
4954
4955 alu.dst.sel = ctx->temp_reg;
4956 alu.dst.chan = i;
4957 if (i == 1)
4958 alu.dst.write = 1;
4959 if (i == 2)
4960 alu.last = 1;
4961
4962 r = r600_bytecode_add_alu(ctx->bc, &alu);
4963 if (r)
4964 return r;
4965 }
4966 } else {
4967 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4968 alu.op = ALU_OP1_RECIP_IEEE;
4969 alu.src[0].sel = ctx->temp_reg;
4970 alu.src[0].chan = 1;
4971
4972 alu.dst.sel = ctx->temp_reg;
4973 alu.dst.chan = 1;
4974 alu.dst.write = 1;
4975 alu.last = 1;
4976
4977 r = r600_bytecode_add_alu(ctx->bc, &alu);
4978 if (r)
4979 return r;
4980 }
4981
4982 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4983
4984 alu.op = ALU_OP2_MUL;
4985
4986 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4987 r600_bytecode_src_set_abs(&alu.src[0]);
4988
4989 alu.src[1].sel = ctx->temp_reg;
4990 alu.src[1].chan = 1;
4991
4992 alu.dst.sel = ctx->temp_reg;
4993 alu.dst.chan = 1;
4994 alu.dst.write = 1;
4995 alu.last = 1;
4996
4997 r = r600_bytecode_add_alu(ctx->bc, &alu);
4998 if (r)
4999 return r;
5000 }
5001
5002 /* result.z = log2(|src|);*/
5003 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5004 if (ctx->bc->chip_class == CAYMAN) {
5005 for (i = 0; i < 3; i++) {
5006 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5007
5008 alu.op = ALU_OP1_LOG_IEEE;
5009 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5010 r600_bytecode_src_set_abs(&alu.src[0]);
5011
5012 alu.dst.sel = ctx->temp_reg;
5013 if (i == 2)
5014 alu.dst.write = 1;
5015 alu.dst.chan = i;
5016 if (i == 2)
5017 alu.last = 1;
5018
5019 r = r600_bytecode_add_alu(ctx->bc, &alu);
5020 if (r)
5021 return r;
5022 }
5023 } else {
5024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5025
5026 alu.op = ALU_OP1_LOG_IEEE;
5027 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5028 r600_bytecode_src_set_abs(&alu.src[0]);
5029
5030 alu.dst.sel = ctx->temp_reg;
5031 alu.dst.write = 1;
5032 alu.dst.chan = 2;
5033 alu.last = 1;
5034
5035 r = r600_bytecode_add_alu(ctx->bc, &alu);
5036 if (r)
5037 return r;
5038 }
5039 }
5040
5041 /* result.w = 1.0; */
5042 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5044
5045 alu.op = ALU_OP1_MOV;
5046 alu.src[0].sel = V_SQ_ALU_SRC_1;
5047 alu.src[0].chan = 0;
5048
5049 alu.dst.sel = ctx->temp_reg;
5050 alu.dst.chan = 3;
5051 alu.dst.write = 1;
5052 alu.last = 1;
5053
5054 r = r600_bytecode_add_alu(ctx->bc, &alu);
5055 if (r)
5056 return r;
5057 }
5058
5059 return tgsi_helper_copy(ctx, inst);
5060 }
5061
5062 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5063 {
5064 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5065 struct r600_bytecode_alu alu;
5066 int r;
5067
5068 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5069
5070 switch (inst->Instruction.Opcode) {
5071 case TGSI_OPCODE_ARL:
5072 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5073 break;
5074 case TGSI_OPCODE_ARR:
5075 alu.op = ALU_OP1_FLT_TO_INT;
5076 break;
5077 case TGSI_OPCODE_UARL:
5078 alu.op = ALU_OP1_MOV;
5079 break;
5080 default:
5081 assert(0);
5082 return -1;
5083 }
5084
5085 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5086 alu.last = 1;
5087 alu.dst.sel = ctx->bc->ar_reg;
5088 alu.dst.write = 1;
5089 r = r600_bytecode_add_alu(ctx->bc, &alu);
5090 if (r)
5091 return r;
5092
5093 ctx->bc->ar_loaded = 0;
5094 return 0;
5095 }
5096 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5097 {
5098 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5099 struct r600_bytecode_alu alu;
5100 int r;
5101
5102 switch (inst->Instruction.Opcode) {
5103 case TGSI_OPCODE_ARL:
5104 memset(&alu, 0, sizeof(alu));
5105 alu.op = ALU_OP1_FLOOR;
5106 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5107 alu.dst.sel = ctx->bc->ar_reg;
5108 alu.dst.write = 1;
5109 alu.last = 1;
5110
5111 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5112 return r;
5113
5114 memset(&alu, 0, sizeof(alu));
5115 alu.op = ALU_OP1_FLT_TO_INT;
5116 alu.src[0].sel = ctx->bc->ar_reg;
5117 alu.dst.sel = ctx->bc->ar_reg;
5118 alu.dst.write = 1;
5119 alu.last = 1;
5120
5121 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5122 return r;
5123 break;
5124 case TGSI_OPCODE_ARR:
5125 memset(&alu, 0, sizeof(alu));
5126 alu.op = ALU_OP1_FLT_TO_INT;
5127 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5128 alu.dst.sel = ctx->bc->ar_reg;
5129 alu.dst.write = 1;
5130 alu.last = 1;
5131
5132 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5133 return r;
5134 break;
5135 case TGSI_OPCODE_UARL:
5136 memset(&alu, 0, sizeof(alu));
5137 alu.op = ALU_OP1_MOV;
5138 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5139 alu.dst.sel = ctx->bc->ar_reg;
5140 alu.dst.write = 1;
5141 alu.last = 1;
5142
5143 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5144 return r;
5145 break;
5146 default:
5147 assert(0);
5148 return -1;
5149 }
5150
5151 ctx->bc->ar_loaded = 0;
5152 return 0;
5153 }
5154
5155 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5156 {
5157 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5158 struct r600_bytecode_alu alu;
5159 int i, r = 0;
5160
5161 for (i = 0; i < 4; i++) {
5162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5163
5164 alu.op = ALU_OP2_MUL;
5165 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5166
5167 if (i == 0 || i == 3) {
5168 alu.src[0].sel = V_SQ_ALU_SRC_1;
5169 } else {
5170 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5171 }
5172
5173 if (i == 0 || i == 2) {
5174 alu.src[1].sel = V_SQ_ALU_SRC_1;
5175 } else {
5176 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5177 }
5178 if (i == 3)
5179 alu.last = 1;
5180 r = r600_bytecode_add_alu(ctx->bc, &alu);
5181 if (r)
5182 return r;
5183 }
5184 return 0;
5185 }
5186
5187 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5188 {
5189 struct r600_bytecode_alu alu;
5190 int r;
5191
5192 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5193 alu.op = opcode;
5194 alu.execute_mask = 1;
5195 alu.update_pred = 1;
5196
5197 alu.dst.sel = ctx->temp_reg;
5198 alu.dst.write = 1;
5199 alu.dst.chan = 0;
5200
5201 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5202 alu.src[1].sel = V_SQ_ALU_SRC_0;
5203 alu.src[1].chan = 0;
5204
5205 alu.last = 1;
5206
5207 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5208 if (r)
5209 return r;
5210 return 0;
5211 }
5212
5213 static int pops(struct r600_shader_ctx *ctx, int pops)
5214 {
5215 unsigned force_pop = ctx->bc->force_add_cf;
5216
5217 if (!force_pop) {
5218 int alu_pop = 3;
5219 if (ctx->bc->cf_last) {
5220 if (ctx->bc->cf_last->op == CF_OP_ALU)
5221 alu_pop = 0;
5222 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5223 alu_pop = 1;
5224 }
5225 alu_pop += pops;
5226 if (alu_pop == 1) {
5227 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5228 ctx->bc->force_add_cf = 1;
5229 } else if (alu_pop == 2) {
5230 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5231 ctx->bc->force_add_cf = 1;
5232 } else {
5233 force_pop = 1;
5234 }
5235 }
5236
5237 if (force_pop) {
5238 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5239 ctx->bc->cf_last->pop_count = pops;
5240 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5241 }
5242
5243 return 0;
5244 }
5245
5246 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5247 unsigned reason)
5248 {
5249 struct r600_stack_info *stack = &ctx->bc->stack;
5250 unsigned elements, entries;
5251
5252 unsigned entry_size = stack->entry_size;
5253
5254 elements = (stack->loop + stack->push_wqm ) * entry_size;
5255 elements += stack->push;
5256
5257 switch (ctx->bc->chip_class) {
5258 case R600:
5259 case R700:
5260 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5261 * the stack must be reserved to hold the current active/continue
5262 * masks */
5263 if (reason == FC_PUSH_VPM) {
5264 elements += 2;
5265 }
5266 break;
5267
5268 case CAYMAN:
5269 /* r9xx: any stack operation on empty stack consumes 2 additional
5270 * elements */
5271 elements += 2;
5272
5273 /* fallthrough */
5274 /* FIXME: do the two elements added above cover the cases for the
5275 * r8xx+ below? */
5276
5277 case EVERGREEN:
5278 /* r8xx+: 2 extra elements are not always required, but one extra
5279 * element must be added for each of the following cases:
5280 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5281 * stack usage.
5282 * (Currently we don't use ALU_ELSE_AFTER.)
5283 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5284 * PUSH instruction executed.
5285 *
5286 * NOTE: it seems we also need to reserve additional element in some
5287 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5288 * then STACK_SIZE should be 2 instead of 1 */
5289 if (reason == FC_PUSH_VPM) {
5290 elements += 1;
5291 }
5292 break;
5293
5294 default:
5295 assert(0);
5296 break;
5297 }
5298
5299 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5300 * for all chips, so we use 4 in the final formula, not the real entry_size
5301 * for the chip */
5302 entry_size = 4;
5303
5304 entries = (elements + (entry_size - 1)) / entry_size;
5305
5306 if (entries > stack->max_entries)
5307 stack->max_entries = entries;
5308 }
5309
5310 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5311 {
5312 switch(reason) {
5313 case FC_PUSH_VPM:
5314 --ctx->bc->stack.push;
5315 assert(ctx->bc->stack.push >= 0);
5316 break;
5317 case FC_PUSH_WQM:
5318 --ctx->bc->stack.push_wqm;
5319 assert(ctx->bc->stack.push_wqm >= 0);
5320 break;
5321 case FC_LOOP:
5322 --ctx->bc->stack.loop;
5323 assert(ctx->bc->stack.loop >= 0);
5324 break;
5325 default:
5326 assert(0);
5327 break;
5328 }
5329 }
5330
5331 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5332 {
5333 switch (reason) {
5334 case FC_PUSH_VPM:
5335 ++ctx->bc->stack.push;
5336 break;
5337 case FC_PUSH_WQM:
5338 ++ctx->bc->stack.push_wqm;
5339 case FC_LOOP:
5340 ++ctx->bc->stack.loop;
5341 break;
5342 default:
5343 assert(0);
5344 }
5345
5346 callstack_update_max_depth(ctx, reason);
5347 }
5348
5349 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5350 {
5351 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5352
5353 sp->mid = realloc((void *)sp->mid,
5354 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5355 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5356 sp->num_mid++;
5357 }
5358
5359 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5360 {
5361 ctx->bc->fc_sp++;
5362 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5363 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5364 }
5365
5366 static void fc_poplevel(struct r600_shader_ctx *ctx)
5367 {
5368 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5369 free(sp->mid);
5370 sp->mid = NULL;
5371 sp->num_mid = 0;
5372 sp->start = NULL;
5373 sp->type = 0;
5374 ctx->bc->fc_sp--;
5375 }
5376
5377 #if 0
5378 static int emit_return(struct r600_shader_ctx *ctx)
5379 {
5380 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5381 return 0;
5382 }
5383
5384 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5385 {
5386
5387 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5388 ctx->bc->cf_last->pop_count = pops;
5389 /* XXX work out offset */
5390 return 0;
5391 }
5392
5393 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5394 {
5395 return 0;
5396 }
5397
5398 static void emit_testflag(struct r600_shader_ctx *ctx)
5399 {
5400
5401 }
5402
5403 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5404 {
5405 emit_testflag(ctx);
5406 emit_jump_to_offset(ctx, 1, 4);
5407 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5408 pops(ctx, ifidx + 1);
5409 emit_return(ctx);
5410 }
5411
5412 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5413 {
5414 emit_testflag(ctx);
5415
5416 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5417 ctx->bc->cf_last->pop_count = 1;
5418
5419 fc_set_mid(ctx, fc_sp);
5420
5421 pops(ctx, 1);
5422 }
5423 #endif
5424
5425 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
5426 {
5427 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5428
5429 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
5430 * LOOP_STARTxxx for nested loops may put the branch stack into a state
5431 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
5432 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
5433 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
5434 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
5435 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5436 alu_type = CF_OP_ALU;
5437 }
5438
5439 emit_logic_pred(ctx, opcode, alu_type);
5440
5441 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5442
5443 fc_pushlevel(ctx, FC_IF);
5444
5445 callstack_push(ctx, FC_PUSH_VPM);
5446 return 0;
5447 }
5448
5449 static int tgsi_if(struct r600_shader_ctx *ctx)
5450 {
5451 return emit_if(ctx, ALU_OP2_PRED_SETNE);
5452 }
5453
5454 static int tgsi_uif(struct r600_shader_ctx *ctx)
5455 {
5456 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
5457 }
5458
5459 static int tgsi_else(struct r600_shader_ctx *ctx)
5460 {
5461 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5462 ctx->bc->cf_last->pop_count = 1;
5463
5464 fc_set_mid(ctx, ctx->bc->fc_sp);
5465 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5466 return 0;
5467 }
5468
5469 static int tgsi_endif(struct r600_shader_ctx *ctx)
5470 {
5471 pops(ctx, 1);
5472 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5473 R600_ERR("if/endif unbalanced in shader\n");
5474 return -1;
5475 }
5476
5477 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5478 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5479 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5480 } else {
5481 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5482 }
5483 fc_poplevel(ctx);
5484
5485 callstack_pop(ctx, FC_PUSH_VPM);
5486 return 0;
5487 }
5488
5489 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5490 {
5491 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5492 * limited to 4096 iterations, like the other LOOP_* instructions. */
5493 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5494
5495 fc_pushlevel(ctx, FC_LOOP);
5496
5497 /* check stack depth */
5498 callstack_push(ctx, FC_LOOP);
5499 return 0;
5500 }
5501
5502 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5503 {
5504 int i;
5505
5506 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5507
5508 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5509 R600_ERR("loop/endloop in shader code are not paired.\n");
5510 return -EINVAL;
5511 }
5512
5513 /* fixup loop pointers - from r600isa
5514 LOOP END points to CF after LOOP START,
5515 LOOP START point to CF after LOOP END
5516 BRK/CONT point to LOOP END CF
5517 */
5518 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5519
5520 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5521
5522 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5523 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5524 }
5525 /* XXX add LOOPRET support */
5526 fc_poplevel(ctx);
5527 callstack_pop(ctx, FC_LOOP);
5528 return 0;
5529 }
5530
5531 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5532 {
5533 unsigned int fscp;
5534
5535 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5536 {
5537 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5538 break;
5539 }
5540
5541 if (fscp == 0) {
5542 R600_ERR("Break not inside loop/endloop pair\n");
5543 return -EINVAL;
5544 }
5545
5546 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5547
5548 fc_set_mid(ctx, fscp);
5549
5550 return 0;
5551 }
5552
5553 static int tgsi_umad(struct r600_shader_ctx *ctx)
5554 {
5555 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5556 struct r600_bytecode_alu alu;
5557 int i, j, k, r;
5558 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5559
5560 /* src0 * src1 */
5561 for (i = 0; i < lasti + 1; i++) {
5562 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5563 continue;
5564
5565 if (ctx->bc->chip_class == CAYMAN) {
5566 for (j = 0 ; j < 4; j++) {
5567 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5568
5569 alu.op = ALU_OP2_MULLO_UINT;
5570 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
5571 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
5572 }
5573 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
5574 alu.dst.sel = ctx->temp_reg;
5575 alu.dst.write = (j == i);
5576 if (j == 3)
5577 alu.last = 1;
5578 r = r600_bytecode_add_alu(ctx->bc, &alu);
5579 if (r)
5580 return r;
5581 }
5582 } else {
5583 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5584
5585 alu.dst.chan = i;
5586 alu.dst.sel = ctx->temp_reg;
5587 alu.dst.write = 1;
5588
5589 alu.op = ALU_OP2_MULLO_UINT;
5590 for (j = 0; j < 2; j++) {
5591 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5592 }
5593
5594 alu.last = 1;
5595 r = r600_bytecode_add_alu(ctx->bc, &alu);
5596 if (r)
5597 return r;
5598 }
5599 }
5600
5601
5602 for (i = 0; i < lasti + 1; i++) {
5603 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5604 continue;
5605
5606 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5607 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5608
5609 alu.op = ALU_OP2_ADD_INT;
5610
5611 alu.src[0].sel = ctx->temp_reg;
5612 alu.src[0].chan = i;
5613
5614 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5615 if (i == lasti) {
5616 alu.last = 1;
5617 }
5618 r = r600_bytecode_add_alu(ctx->bc, &alu);
5619 if (r)
5620 return r;
5621 }
5622 return 0;
5623 }
5624
5625 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5626 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
5627 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5628 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5629
5630 /* XXX:
5631 * For state trackers other than OpenGL, we'll want to use
5632 * _RECIP_IEEE instead.
5633 */
5634 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5635
5636 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
5637 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5638 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5639 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5640 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5641 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5642 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5643 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5644 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5645 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5646 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5647 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5648 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5649 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5650 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5651 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5652 /* gap */
5653 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5654 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5655 /* gap */
5656 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5657 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5658 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5659 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5660 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5661 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5662 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5663 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5664 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5665 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5666 /* gap */
5667 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5668 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5669 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5670 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5671 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5672 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5673 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5674 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
5675 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5676 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5677 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5678 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5679 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5680 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5681 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5682 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5683 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5684 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5685 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5686 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5687 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5688 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5689 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5690 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5691 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5692 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5693 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5694 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5695 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5696 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
5697 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5698 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5699 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5700 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5701 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5702 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5703 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5704 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5705 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5706 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5707 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5708 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5709 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5710 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5711 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5712 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5713 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5714 /* gap */
5715 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5716 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5717 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5718 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5719 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5720 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5721 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5722 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5723 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
5724 /* gap */
5725 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5726 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5727 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5728 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5729 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5730 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5731 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5732 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5733 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5734 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5735 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5736 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5737 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5738 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5739 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5740 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5741 /* gap */
5742 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5743 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5744 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5745 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5746 /* gap */
5747 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
5748 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
5749 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
5750 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
5751 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5752 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5753 /* gap */
5754 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5755 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5756 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5757 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5758 /* gap */
5759 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5760 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
5761 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5762 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5763 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5764 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5765 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5766 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
5767 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5768 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
5769 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5770 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5771 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5772 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5773 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5774 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5775 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5776 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5777 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5778 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
5779 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
5780 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
5781 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
5782 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5783 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
5784 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
5785 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5786 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5787 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5788 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5789 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5790 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5791 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5792 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5793 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5794 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5795 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5796 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5797 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5798 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
5799 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
5800 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5801 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5802 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5803 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
5804 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5805 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5806 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5807 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
5808 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
5809 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
5810 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
5811 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
5812 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5813 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5814 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5815 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5816 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5817 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5818 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
5819 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5820 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5821 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
5822 };
5823
5824 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
5825 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
5826 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5827 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5828 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
5829 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
5830 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5831 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5832 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5833 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5834 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5835 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5836 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5837 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5838 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5839 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5840 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5841 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5842 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5843 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5844 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5845 /* gap */
5846 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5847 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5848 /* gap */
5849 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5850 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5851 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5852 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5853 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5854 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5855 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5856 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5857 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5858 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5859 /* gap */
5860 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5861 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5862 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5863 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5864 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5865 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5866 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5867 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
5868 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5869 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5870 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5871 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5872 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5873 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5874 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5875 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5876 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5877 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5878 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5879 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5880 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5881 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5882 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5883 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5884 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5885 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5886 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5887 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5888 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5889 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
5890 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5891 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5892 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5893 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5894 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5895 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5896 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5897 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5898 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5899 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5900 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5901 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5902 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5903 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5904 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5905 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5906 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5907 /* gap */
5908 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5909 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5910 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5911 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5912 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5913 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5914 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5915 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5916 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
5917 /* gap */
5918 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5919 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5920 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5921 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5922 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5923 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5924 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5925 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5926 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5927 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5928 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5929 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5930 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5931 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5932 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5933 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5934 /* gap */
5935 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5936 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5937 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5938 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5939 /* gap */
5940 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
5941 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
5942 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
5943 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
5944 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5945 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5946 /* gap */
5947 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5948 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5949 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5950 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5951 /* gap */
5952 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5953 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
5954 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5955 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5956 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5957 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5958 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5959 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
5960 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5961 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
5962 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5963 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5964 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5965 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5966 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5967 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5968 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5969 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5970 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5971 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
5972 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
5973 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
5974 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
5975 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5976 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
5977 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
5978 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5979 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5980 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5981 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5982 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5983 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5984 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5985 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5986 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5987 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5988 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5989 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5990 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5991 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
5992 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
5993 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5994 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5995 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5996 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
5997 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5998 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5999 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6000 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6001 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6002 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6003 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6004 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6005 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6006 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6007 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6008 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6009 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6010 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6011 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6012 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6013 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6014 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6015 };
6016
6017 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6018 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6019 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6020 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6021 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6022 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6023 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6024 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6025 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6026 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6027 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6028 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6029 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6030 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6031 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6032 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6033 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6034 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6035 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6036 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6037 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6038 /* gap */
6039 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6040 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6041 /* gap */
6042 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6043 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6044 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6045 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6046 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6047 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6048 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6049 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6050 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6051 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6052 /* gap */
6053 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6054 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6055 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6056 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6057 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6058 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6059 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6060 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6061 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6062 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6063 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6064 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6065 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6066 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6067 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6068 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6069 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6070 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6071 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6072 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6073 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6074 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6075 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6076 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6077 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6078 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6079 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6080 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6081 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6082 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6083 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6084 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6085 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6086 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6087 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6088 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6089 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6090 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6091 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6092 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6093 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6094 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6095 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6096 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6097 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6098 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6099 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6100 /* gap */
6101 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6102 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6103 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6104 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6105 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6106 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6107 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6108 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6109 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6110 /* gap */
6111 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6112 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6113 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6114 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6115 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6116 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6117 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6118 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6119 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6120 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6121 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6122 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6123 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6124 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6125 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6126 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6127 /* gap */
6128 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6129 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6130 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6131 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6132 /* gap */
6133 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6134 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6135 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6136 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6137 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6138 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6139 /* gap */
6140 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6141 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6142 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6143 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6144 /* gap */
6145 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6146 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6147 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6148 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6149 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6150 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6151 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6152 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6153 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6154 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6155 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6156 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6157 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6158 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6159 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6160 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6161 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6162 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6163 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6164 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6165 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6166 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6167 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6168 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6169 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6170 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6171 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6172 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6173 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6174 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6175 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6176 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6177 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6178 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6179 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6180 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6181 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6182 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6183 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6184 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6185 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6186 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6187 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6188 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6189 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6190 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6191 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6192 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6193 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6194 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6195 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6196 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6197 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6198 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6199 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6200 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6201 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6202 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6203 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6204 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6205 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6206 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6207 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6208 };