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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "pipe/p_shader_tokens.h"
31 #include "tgsi/tgsi_info.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "util/u_memory.h"
36 #include <stdio.h>
37 #include <errno.h>
38 #include <byteswap.h>
39
40 /* CAYMAN notes
41 Why CAYMAN got loops for lots of instructions is explained here.
42
43 -These 8xx t-slot only ops are implemented in all vector slots.
44 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
45 These 8xx t-slot only opcodes become vector ops, with all four
46 slots expecting the arguments on sources a and b. Result is
47 broadcast to all channels.
48 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
49 These 8xx t-slot only opcodes become vector ops in the z, y, and
50 x slots.
51 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
52 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
53 SQRT_IEEE/_64
54 SIN/COS
55 The w slot may have an independent co-issued operation, or if the
56 result is required to be in the w slot, the opcode above may be
57 issued in the w slot as well.
58 The compiler must issue the source argument to slots z, y, and x
59 */
60
61 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
62 struct r600_pipe_shader *pipeshader,
63 struct r600_shader_key key);
64
65 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
66 {
67 struct tgsi_parse_context parse;
68
69 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
70 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
71 return ~0;
72 }
73 return parse.FullHeader.Processor.Processor;
74 }
75
76 static bool r600_can_dump_shader(struct r600_screen *rscreen, unsigned processor_type)
77 {
78 switch (processor_type) {
79 case TGSI_PROCESSOR_VERTEX:
80 return (rscreen->debug_flags & DBG_VS) != 0;
81 case TGSI_PROCESSOR_GEOMETRY:
82 return (rscreen->debug_flags & DBG_GS) != 0;
83 case TGSI_PROCESSOR_FRAGMENT:
84 return (rscreen->debug_flags & DBG_PS) != 0;
85 case TGSI_PROCESSOR_COMPUTE:
86 return (rscreen->debug_flags & DBG_CS) != 0;
87 default:
88 return false;
89 }
90 }
91
92 static void r600_dump_streamout(struct pipe_stream_output_info *so)
93 {
94 unsigned i;
95
96 fprintf(stderr, "STREAMOUT\n");
97 for (i = 0; i < so->num_outputs; i++) {
98 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
99 so->output[i].start_component;
100 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
101 i, so->output[i].output_buffer,
102 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
103 so->output[i].register_index,
104 mask & 1 ? "x" : "",
105 mask & 2 ? "y" : "",
106 mask & 4 ? "z" : "",
107 mask & 8 ? "w" : "",
108 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
109 }
110 }
111
112 int r600_pipe_shader_create(struct pipe_context *ctx,
113 struct r600_pipe_shader *shader,
114 struct r600_shader_key key)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117 struct r600_pipe_shader_selector *sel = shader->selector;
118 int r, i;
119 uint32_t *ptr;
120 bool dump = r600_can_dump_shader(rctx->screen, tgsi_get_processor_type(sel->tokens));
121
122 shader->shader.bc.isa = rctx->isa;
123
124 if (dump) {
125 fprintf(stderr, "--------------------------------------------------------------\n");
126 tgsi_dump(sel->tokens, 0);
127
128 if (sel->so.num_outputs) {
129 r600_dump_streamout(&sel->so);
130 }
131 }
132 r = r600_shader_from_tgsi(rctx->screen, shader, key);
133 if (r) {
134 R600_ERR("translation from TGSI failed !\n");
135 return r;
136 }
137 r = r600_bytecode_build(&shader->shader.bc);
138 if (r) {
139 R600_ERR("building bytecode failed !\n");
140 return r;
141 }
142 if (dump) {
143 fprintf(stderr, "--------------------------------------------------------------\n");
144 r600_bytecode_disasm(&shader->shader.bc);
145 fprintf(stderr, "______________________________________________________________\n");
146 }
147
148
149 /* Store the shader in a buffer. */
150 if (shader->bo == NULL) {
151 shader->bo = (struct r600_resource*)
152 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
153 if (shader->bo == NULL) {
154 return -ENOMEM;
155 }
156 ptr = r600_buffer_mmap_sync_with_rings(rctx, shader->bo, PIPE_TRANSFER_WRITE);
157 if (R600_BIG_ENDIAN) {
158 for (i = 0; i < shader->shader.bc.ndw; ++i) {
159 ptr[i] = bswap_32(shader->shader.bc.bytecode[i]);
160 }
161 } else {
162 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
163 }
164 rctx->ws->buffer_unmap(shader->bo->cs_buf);
165 }
166
167 /* Build state. */
168 switch (shader->shader.processor_type) {
169 case TGSI_PROCESSOR_VERTEX:
170 if (rctx->chip_class >= EVERGREEN) {
171 evergreen_update_vs_state(ctx, shader);
172 } else {
173 r600_update_vs_state(ctx, shader);
174 }
175 break;
176 case TGSI_PROCESSOR_FRAGMENT:
177 if (rctx->chip_class >= EVERGREEN) {
178 evergreen_update_ps_state(ctx, shader);
179 } else {
180 r600_update_ps_state(ctx, shader);
181 }
182 break;
183 default:
184 return -EINVAL;
185 }
186 return 0;
187 }
188
189 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
190 {
191 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
192 r600_bytecode_clear(&shader->shader.bc);
193 r600_release_command_buffer(&shader->command_buffer);
194 }
195
196 /*
197 * tgsi -> r600 shader
198 */
199 struct r600_shader_tgsi_instruction;
200
201 struct r600_shader_src {
202 unsigned sel;
203 unsigned swizzle[4];
204 unsigned neg;
205 unsigned abs;
206 unsigned rel;
207 unsigned kc_bank;
208 uint32_t value[4];
209 };
210
211 struct r600_shader_ctx {
212 struct tgsi_shader_info info;
213 struct tgsi_parse_context parse;
214 const struct tgsi_token *tokens;
215 unsigned type;
216 unsigned file_offset[TGSI_FILE_COUNT];
217 unsigned temp_reg;
218 struct r600_shader_tgsi_instruction *inst_info;
219 struct r600_bytecode *bc;
220 struct r600_shader *shader;
221 struct r600_shader_src src[4];
222 uint32_t *literals;
223 uint32_t nliterals;
224 uint32_t max_driver_temp_used;
225 boolean use_llvm;
226 /* needed for evergreen interpolation */
227 boolean input_centroid;
228 boolean input_linear;
229 boolean input_perspective;
230 int num_interp_gpr;
231 int face_gpr;
232 int colors_used;
233 boolean clip_vertex_write;
234 unsigned cv_output;
235 int fragcoord_input;
236 int native_integers;
237 };
238
239 struct r600_shader_tgsi_instruction {
240 unsigned tgsi_opcode;
241 unsigned is_op3;
242 unsigned op;
243 int (*process)(struct r600_shader_ctx *ctx);
244 };
245
246 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
247 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
248 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only);
249 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
250 static int tgsi_else(struct r600_shader_ctx *ctx);
251 static int tgsi_endif(struct r600_shader_ctx *ctx);
252 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
253 static int tgsi_endloop(struct r600_shader_ctx *ctx);
254 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
255
256 /*
257 * bytestream -> r600 shader
258 *
259 * These functions are used to transform the output of the LLVM backend into
260 * struct r600_bytecode.
261 */
262
263 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
264 unsigned char * bytes, unsigned num_bytes);
265
266 #ifdef HAVE_OPENCL
267 int r600_compute_shader_create(struct pipe_context * ctx,
268 LLVMModuleRef mod, struct r600_bytecode * bytecode)
269 {
270 struct r600_context *r600_ctx = (struct r600_context *)ctx;
271 unsigned char * bytes;
272 unsigned byte_count;
273 struct r600_shader_ctx shader_ctx;
274 bool dump = (r600_ctx->screen->debug_flags & DBG_CS) != 0;
275
276 r600_llvm_compile(mod, &bytes, &byte_count, r600_ctx->family , dump);
277 shader_ctx.bc = bytecode;
278 r600_bytecode_init(shader_ctx.bc, r600_ctx->chip_class, r600_ctx->family,
279 r600_ctx->screen->msaa_texture_support);
280 shader_ctx.bc->type = TGSI_PROCESSOR_COMPUTE;
281 shader_ctx.bc->isa = r600_ctx->isa;
282 r600_bytecode_from_byte_stream(&shader_ctx, bytes, byte_count);
283 if (shader_ctx.bc->chip_class == CAYMAN) {
284 cm_bytecode_add_cf_end(shader_ctx.bc);
285 }
286 r600_bytecode_build(shader_ctx.bc);
287 if (dump) {
288 r600_bytecode_disasm(shader_ctx.bc);
289 }
290 free(bytes);
291 return 1;
292 }
293
294 #endif /* HAVE_OPENCL */
295
296 static uint32_t i32_from_byte_stream(unsigned char * bytes,
297 unsigned * bytes_read)
298 {
299 unsigned i;
300 uint32_t out = 0;
301 for (i = 0; i < 4; i++) {
302 out |= bytes[(*bytes_read)++] << (8 * i);
303 }
304 return out;
305 }
306
307 static unsigned r600_src_from_byte_stream(unsigned char * bytes,
308 unsigned bytes_read, struct r600_bytecode_alu * alu, unsigned src_idx)
309 {
310 unsigned i;
311 unsigned sel0, sel1;
312 sel0 = bytes[bytes_read++];
313 sel1 = bytes[bytes_read++];
314 alu->src[src_idx].sel = sel0 | (sel1 << 8);
315 alu->src[src_idx].chan = bytes[bytes_read++];
316 alu->src[src_idx].neg = bytes[bytes_read++];
317 alu->src[src_idx].abs = bytes[bytes_read++];
318 alu->src[src_idx].rel = bytes[bytes_read++];
319 alu->src[src_idx].kc_bank = bytes[bytes_read++];
320 for (i = 0; i < 4; i++) {
321 alu->src[src_idx].value |= bytes[bytes_read++] << (i * 8);
322 }
323 return bytes_read;
324 }
325
326 static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
327 unsigned char * bytes, unsigned bytes_read)
328 {
329 unsigned src_idx, src_num;
330 struct r600_bytecode_alu alu;
331 unsigned src_use_sel[3];
332 const struct alu_op_info *alu_op;
333 unsigned src_sel[3] = {};
334 uint32_t word0, word1;
335
336 src_num = bytes[bytes_read++];
337
338 memset(&alu, 0, sizeof(alu));
339 for(src_idx = 0; src_idx < src_num; src_idx++) {
340 unsigned i;
341 src_use_sel[src_idx] = bytes[bytes_read++];
342 for (i = 0; i < 4; i++) {
343 src_sel[src_idx] |= bytes[bytes_read++] << (i * 8);
344 }
345 for (i = 0; i < 4; i++) {
346 alu.src[src_idx].value |= bytes[bytes_read++] << (i * 8);
347 }
348 }
349
350 word0 = i32_from_byte_stream(bytes, &bytes_read);
351 word1 = i32_from_byte_stream(bytes, &bytes_read);
352
353 switch(ctx->bc->chip_class) {
354 default:
355 case R600:
356 r600_bytecode_alu_read(ctx->bc, &alu, word0, word1);
357 break;
358 case R700:
359 case EVERGREEN:
360 case CAYMAN:
361 r700_bytecode_alu_read(ctx->bc, &alu, word0, word1);
362 break;
363 }
364
365 for(src_idx = 0; src_idx < src_num; src_idx++) {
366 if (src_use_sel[src_idx]) {
367 unsigned sel = src_sel[src_idx];
368
369 alu.src[src_idx].chan = sel & 3;
370 sel >>= 2;
371
372 if (sel>=512) { /* constant */
373 sel -= 512;
374 alu.src[src_idx].kc_bank = sel >> 12;
375 alu.src[src_idx].sel = (sel & 4095) + 512;
376 }
377 else {
378 alu.src[src_idx].sel = sel;
379 }
380 }
381 }
382
383 alu_op = r600_isa_alu(alu.op);
384
385 #if HAVE_LLVM < 0x0302
386 if ((alu_op->flags & AF_PRED) && alu_op->src_count == 2) {
387 alu.update_pred = 1;
388 alu.dst.write = 0;
389 alu.src[1].sel = V_SQ_ALU_SRC_0;
390 alu.src[1].chan = 0;
391 alu.last = 1;
392 }
393 #endif
394
395 if (alu_op->flags & AF_MOVA) {
396 ctx->bc->ar_reg = alu.src[0].sel;
397 ctx->bc->ar_chan = alu.src[0].chan;
398 ctx->bc->ar_loaded = 0;
399 return bytes_read;
400 }
401
402 if (alu.execute_mask) {
403 alu.pred_sel = 0;
404 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
405 } else {
406 r600_bytecode_add_alu(ctx->bc, &alu);
407 }
408
409 /* XXX: Handle other KILL instructions */
410 if (alu_op->flags & AF_KILL) {
411 ctx->shader->uses_kill = 1;
412 /* XXX: This should be enforced in the LLVM backend. */
413 ctx->bc->force_add_cf = 1;
414 }
415 return bytes_read;
416 }
417
418 static void llvm_if(struct r600_shader_ctx *ctx)
419 {
420 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
421 fc_pushlevel(ctx, FC_IF);
422 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
423 }
424
425 static void r600_break_from_byte_stream(struct r600_shader_ctx *ctx)
426 {
427 unsigned opcode = TGSI_OPCODE_BRK;
428 if (ctx->bc->chip_class == CAYMAN)
429 ctx->inst_info = &cm_shader_tgsi_instruction[opcode];
430 else if (ctx->bc->chip_class >= EVERGREEN)
431 ctx->inst_info = &eg_shader_tgsi_instruction[opcode];
432 else
433 ctx->inst_info = &r600_shader_tgsi_instruction[opcode];
434 llvm_if(ctx);
435 tgsi_loop_brk_cont(ctx);
436 tgsi_endif(ctx);
437 }
438
439 static unsigned r600_fc_from_byte_stream(struct r600_shader_ctx *ctx,
440 unsigned char * bytes, unsigned bytes_read)
441 {
442 struct r600_bytecode_alu alu;
443 unsigned inst;
444 memset(&alu, 0, sizeof(alu));
445 bytes_read = r600_src_from_byte_stream(bytes, bytes_read, &alu, 0);
446 inst = bytes[bytes_read++];
447 switch (inst) {
448 case 0: /* IF_PREDICATED */
449 llvm_if(ctx);
450 break;
451 case 1: /* ELSE */
452 tgsi_else(ctx);
453 break;
454 case 2: /* ENDIF */
455 tgsi_endif(ctx);
456 break;
457 case 3: /* BGNLOOP */
458 tgsi_bgnloop(ctx);
459 break;
460 case 4: /* ENDLOOP */
461 tgsi_endloop(ctx);
462 break;
463 case 5: /* PREDICATED_BREAK */
464 r600_break_from_byte_stream(ctx);
465 break;
466 case 6: /* CONTINUE */
467 {
468 unsigned opcode = TGSI_OPCODE_CONT;
469 if (ctx->bc->chip_class == CAYMAN) {
470 ctx->inst_info =
471 &cm_shader_tgsi_instruction[opcode];
472 } else if (ctx->bc->chip_class >= EVERGREEN) {
473 ctx->inst_info =
474 &eg_shader_tgsi_instruction[opcode];
475 } else {
476 ctx->inst_info =
477 &r600_shader_tgsi_instruction[opcode];
478 }
479 tgsi_loop_brk_cont(ctx);
480 }
481 break;
482 }
483
484 return bytes_read;
485 }
486
487 static unsigned r600_tex_from_byte_stream(struct r600_shader_ctx *ctx,
488 unsigned char * bytes, unsigned bytes_read)
489 {
490 struct r600_bytecode_tex tex;
491
492 uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
493 uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
494 uint32_t word2 = i32_from_byte_stream(bytes, &bytes_read);
495
496 tex.op = r600_isa_fetch_by_opcode(ctx->bc->isa, G_SQ_TEX_WORD0_TEX_INST(word0));
497 tex.resource_id = G_SQ_TEX_WORD0_RESOURCE_ID(word0);
498 tex.src_gpr = G_SQ_TEX_WORD0_SRC_GPR(word0);
499 tex.src_rel = G_SQ_TEX_WORD0_SRC_REL(word0);
500 tex.dst_gpr = G_SQ_TEX_WORD1_DST_GPR(word1);
501 tex.dst_rel = G_SQ_TEX_WORD1_DST_REL(word1);
502 tex.dst_sel_x = G_SQ_TEX_WORD1_DST_SEL_X(word1);
503 tex.dst_sel_y = G_SQ_TEX_WORD1_DST_SEL_Y(word1);
504 tex.dst_sel_z = G_SQ_TEX_WORD1_DST_SEL_Z(word1);
505 tex.dst_sel_w = G_SQ_TEX_WORD1_DST_SEL_W(word1);
506 tex.lod_bias = G_SQ_TEX_WORD1_LOD_BIAS(word1);
507 tex.coord_type_x = G_SQ_TEX_WORD1_COORD_TYPE_X(word1);
508 tex.coord_type_y = G_SQ_TEX_WORD1_COORD_TYPE_Y(word1);
509 tex.coord_type_z = G_SQ_TEX_WORD1_COORD_TYPE_Z(word1);
510 tex.coord_type_w = G_SQ_TEX_WORD1_COORD_TYPE_W(word1);
511 tex.offset_x = G_SQ_TEX_WORD2_OFFSET_X(word2);
512 tex.offset_y = G_SQ_TEX_WORD2_OFFSET_Y(word2);
513 tex.offset_z = G_SQ_TEX_WORD2_OFFSET_Z(word2);
514 tex.sampler_id = G_SQ_TEX_WORD2_SAMPLER_ID(word2);
515 tex.src_sel_x = G_SQ_TEX_WORD2_SRC_SEL_X(word2);
516 tex.src_sel_y = G_SQ_TEX_WORD2_SRC_SEL_Y(word2);
517 tex.src_sel_z = G_SQ_TEX_WORD2_SRC_SEL_Z(word2);
518 tex.src_sel_w = G_SQ_TEX_WORD2_SRC_SEL_W(word2);
519
520 tex.inst_mod = 0;
521
522 r600_bytecode_add_tex(ctx->bc, &tex);
523
524 return bytes_read;
525 }
526
527 static int r600_vtx_from_byte_stream(struct r600_shader_ctx *ctx,
528 unsigned char * bytes, unsigned bytes_read)
529 {
530 struct r600_bytecode_vtx vtx;
531
532 uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
533 uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
534 uint32_t word2 = i32_from_byte_stream(bytes, &bytes_read);
535
536 memset(&vtx, 0, sizeof(vtx));
537
538 /* WORD0 */
539 vtx.op = r600_isa_fetch_by_opcode(ctx->bc->isa,
540 G_SQ_VTX_WORD0_VTX_INST(word0));
541 vtx.fetch_type = G_SQ_VTX_WORD0_FETCH_TYPE(word0);
542 vtx.buffer_id = G_SQ_VTX_WORD0_BUFFER_ID(word0);
543 vtx.src_gpr = G_SQ_VTX_WORD0_SRC_GPR(word0);
544 vtx.src_sel_x = G_SQ_VTX_WORD0_SRC_SEL_X(word0);
545 vtx.mega_fetch_count = G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(word0);
546
547 /* WORD1 */
548 vtx.dst_gpr = G_SQ_VTX_WORD1_GPR_DST_GPR(word1);
549 vtx.dst_sel_x = G_SQ_VTX_WORD1_DST_SEL_X(word1);
550 vtx.dst_sel_y = G_SQ_VTX_WORD1_DST_SEL_Y(word1);
551 vtx.dst_sel_z = G_SQ_VTX_WORD1_DST_SEL_Z(word1);
552 vtx.dst_sel_w = G_SQ_VTX_WORD1_DST_SEL_W(word1);
553 vtx.use_const_fields = G_SQ_VTX_WORD1_USE_CONST_FIELDS(word1);
554 vtx.data_format = G_SQ_VTX_WORD1_DATA_FORMAT(word1);
555 vtx.num_format_all = G_SQ_VTX_WORD1_NUM_FORMAT_ALL(word1);
556 vtx.format_comp_all = G_SQ_VTX_WORD1_FORMAT_COMP_ALL(word1);
557 vtx.srf_mode_all = G_SQ_VTX_WORD1_SRF_MODE_ALL(word1);
558
559 /* WORD 2*/
560 vtx.offset = G_SQ_VTX_WORD2_OFFSET(word2);
561 vtx.endian = G_SQ_VTX_WORD2_ENDIAN_SWAP(word2);
562
563 if (r600_bytecode_add_vtx(ctx->bc, &vtx)) {
564 fprintf(stderr, "Error adding vtx\n");
565 }
566
567 /* Use the Texture Cache for compute shaders*/
568 if (ctx->bc->chip_class >= EVERGREEN &&
569 ctx->bc->type == TGSI_PROCESSOR_COMPUTE) {
570 ctx->bc->cf_last->op = CF_OP_TEX;
571 }
572 return bytes_read;
573 }
574
575 static int r600_export_from_byte_stream(struct r600_shader_ctx *ctx,
576 unsigned char * bytes, unsigned bytes_read)
577 {
578 uint32_t word0 = 0, word1 = 0;
579 struct r600_bytecode_output output;
580 memset(&output, 0, sizeof(struct r600_bytecode_output));
581 word0 = i32_from_byte_stream(bytes, &bytes_read);
582 word1 = i32_from_byte_stream(bytes, &bytes_read);
583 if (ctx->bc->chip_class >= EVERGREEN)
584 eg_bytecode_export_read(ctx->bc, &output, word0,word1);
585 else
586 r600_bytecode_export_read(ctx->bc, &output, word0,word1);
587 r600_bytecode_add_output(ctx->bc, &output);
588 return bytes_read;
589 }
590
591 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
592 unsigned char * bytes, unsigned num_bytes)
593 {
594 unsigned bytes_read = 0;
595 ctx->bc->nstack = bytes[bytes_read++];
596 unsigned i, byte;
597 while (bytes_read < num_bytes) {
598 char inst_type = bytes[bytes_read++];
599 switch (inst_type) {
600 case 0:
601 bytes_read = r600_alu_from_byte_stream(ctx, bytes,
602 bytes_read);
603 break;
604 case 1:
605 bytes_read = r600_tex_from_byte_stream(ctx, bytes,
606 bytes_read);
607 break;
608 case 2:
609 bytes_read = r600_fc_from_byte_stream(ctx, bytes,
610 bytes_read);
611 break;
612 case 3:
613 r600_bytecode_add_cfinst(ctx->bc, CF_NATIVE);
614 for (i = 0; i < 2; i++) {
615 for (byte = 0 ; byte < 4; byte++) {
616 ctx->bc->cf_last->isa[i] |=
617 (bytes[bytes_read++] << (byte * 8));
618 }
619 }
620 break;
621
622 case 4:
623 bytes_read = r600_vtx_from_byte_stream(ctx, bytes,
624 bytes_read);
625 break;
626 case 5:
627 bytes_read = r600_export_from_byte_stream(ctx, bytes,
628 bytes_read);
629 break;
630 case 6: {
631 int32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
632 int32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
633
634 r600_bytecode_add_cf(ctx->bc);
635 ctx->bc->cf_last->op = r600_isa_cf_by_opcode(ctx->bc->isa, 8/* CF_ALU*/, 1);
636 ctx->bc->cf_last->kcache[0].bank = G_SQ_CF_ALU_WORD0_KCACHE_BANK0(word0);
637 ctx->bc->cf_last->kcache[0].addr = G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(word1);
638 ctx->bc->cf_last->kcache[0].mode = G_SQ_CF_ALU_WORD0_KCACHE_MODE0(word0);
639 ctx->bc->cf_last->kcache[1].bank = G_SQ_CF_ALU_WORD0_KCACHE_BANK1(word0);
640 ctx->bc->cf_last->kcache[1].addr = G_SQ_CF_ALU_WORD1_KCACHE_ADDR1(word1);
641 ctx->bc->cf_last->kcache[1].mode = G_SQ_CF_ALU_WORD1_KCACHE_MODE1(word1);
642 break;
643 }
644 default:
645 /* XXX: Error here */
646 break;
647 }
648 }
649 }
650
651 /* End bytestream -> r600 shader functions*/
652
653 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
654 {
655 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
656 int j;
657
658 if (i->Instruction.NumDstRegs > 1) {
659 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
660 return -EINVAL;
661 }
662 if (i->Instruction.Predicate) {
663 R600_ERR("predicate unsupported\n");
664 return -EINVAL;
665 }
666 #if 0
667 if (i->Instruction.Label) {
668 R600_ERR("label unsupported\n");
669 return -EINVAL;
670 }
671 #endif
672 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
673 if (i->Src[j].Register.Dimension) {
674 if (i->Src[j].Register.File != TGSI_FILE_CONSTANT) {
675 R600_ERR("unsupported src %d (dimension %d)\n", j,
676 i->Src[j].Register.Dimension);
677 return -EINVAL;
678 }
679 }
680 }
681 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
682 if (i->Dst[j].Register.Dimension) {
683 R600_ERR("unsupported dst (dimension)\n");
684 return -EINVAL;
685 }
686 }
687 return 0;
688 }
689
690 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
691 int input)
692 {
693 int ij_index = 0;
694
695 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
696 if (ctx->shader->input[input].centroid)
697 ij_index++;
698 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
699 /* if we have perspective add one */
700 if (ctx->input_perspective) {
701 ij_index++;
702 /* if we have perspective centroid */
703 if (ctx->input_centroid)
704 ij_index++;
705 }
706 if (ctx->shader->input[input].centroid)
707 ij_index++;
708 }
709
710 ctx->shader->input[input].ij_index = ij_index;
711 }
712
713 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
714 {
715 int i, r;
716 struct r600_bytecode_alu alu;
717 int gpr = 0, base_chan = 0;
718 int ij_index = ctx->shader->input[input].ij_index;
719
720 /* work out gpr and base_chan from index */
721 gpr = ij_index / 2;
722 base_chan = (2 * (ij_index % 2)) + 1;
723
724 for (i = 0; i < 8; i++) {
725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
726
727 if (i < 4)
728 alu.op = ALU_OP2_INTERP_ZW;
729 else
730 alu.op = ALU_OP2_INTERP_XY;
731
732 if ((i > 1) && (i < 6)) {
733 alu.dst.sel = ctx->shader->input[input].gpr;
734 alu.dst.write = 1;
735 }
736
737 alu.dst.chan = i % 4;
738
739 alu.src[0].sel = gpr;
740 alu.src[0].chan = (base_chan - (i % 2));
741
742 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
743
744 alu.bank_swizzle_force = SQ_ALU_VEC_210;
745 if ((i % 4) == 3)
746 alu.last = 1;
747 r = r600_bytecode_add_alu(ctx->bc, &alu);
748 if (r)
749 return r;
750 }
751 return 0;
752 }
753
754 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
755 {
756 int i, r;
757 struct r600_bytecode_alu alu;
758
759 for (i = 0; i < 4; i++) {
760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
761
762 alu.op = ALU_OP1_INTERP_LOAD_P0;
763
764 alu.dst.sel = ctx->shader->input[input].gpr;
765 alu.dst.write = 1;
766
767 alu.dst.chan = i;
768
769 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
770 alu.src[0].chan = i;
771
772 if (i == 3)
773 alu.last = 1;
774 r = r600_bytecode_add_alu(ctx->bc, &alu);
775 if (r)
776 return r;
777 }
778 return 0;
779 }
780
781 /*
782 * Special export handling in shaders
783 *
784 * shader export ARRAY_BASE for EXPORT_POS:
785 * 60 is position
786 * 61 is misc vector
787 * 62, 63 are clip distance vectors
788 *
789 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
790 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
791 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
792 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
793 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
794 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
795 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
796 * exclusive from render target index)
797 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
798 *
799 *
800 * shader export ARRAY_BASE for EXPORT_PIXEL:
801 * 0-7 CB targets
802 * 61 computed Z vector
803 *
804 * The use of the values exported in the computed Z vector are controlled
805 * by DB_SHADER_CONTROL:
806 * Z_EXPORT_ENABLE - Z as a float in RED
807 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
808 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
809 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
810 * DB_SOURCE_FORMAT - export control restrictions
811 *
812 */
813
814
815 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
816 static int r600_spi_sid(struct r600_shader_io * io)
817 {
818 int index, name = io->name;
819
820 /* These params are handled differently, they don't need
821 * semantic indices, so we'll use 0 for them.
822 */
823 if (name == TGSI_SEMANTIC_POSITION ||
824 name == TGSI_SEMANTIC_PSIZE ||
825 name == TGSI_SEMANTIC_FACE)
826 index = 0;
827 else {
828 if (name == TGSI_SEMANTIC_GENERIC) {
829 /* For generic params simply use sid from tgsi */
830 index = io->sid;
831 } else {
832 /* For non-generic params - pack name and sid into 8 bits */
833 index = 0x80 | (name<<3) | (io->sid);
834 }
835
836 /* Make sure that all really used indices have nonzero value, so
837 * we can just compare it to 0 later instead of comparing the name
838 * with different values to detect special cases. */
839 index++;
840 }
841
842 return index;
843 };
844
845 /* turn input into interpolate on EG */
846 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
847 {
848 int r = 0;
849
850 if (ctx->shader->input[index].spi_sid) {
851 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
852 if (ctx->shader->input[index].interpolate > 0) {
853 evergreen_interp_assign_ij_index(ctx, index);
854 if (!ctx->use_llvm)
855 r = evergreen_interp_alu(ctx, index);
856 } else {
857 if (!ctx->use_llvm)
858 r = evergreen_interp_flat(ctx, index);
859 }
860 }
861 return r;
862 }
863
864 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
865 {
866 struct r600_bytecode_alu alu;
867 int i, r;
868 int gpr_front = ctx->shader->input[front].gpr;
869 int gpr_back = ctx->shader->input[back].gpr;
870
871 for (i = 0; i < 4; i++) {
872 memset(&alu, 0, sizeof(alu));
873 alu.op = ALU_OP3_CNDGT;
874 alu.is_op3 = 1;
875 alu.dst.write = 1;
876 alu.dst.sel = gpr_front;
877 alu.src[0].sel = ctx->face_gpr;
878 alu.src[1].sel = gpr_front;
879 alu.src[2].sel = gpr_back;
880
881 alu.dst.chan = i;
882 alu.src[1].chan = i;
883 alu.src[2].chan = i;
884 alu.last = (i==3);
885
886 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
887 return r;
888 }
889
890 return 0;
891 }
892
893 static int tgsi_declaration(struct r600_shader_ctx *ctx)
894 {
895 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
896 int r, i, j, count = d->Range.Last - d->Range.First + 1;
897
898 switch (d->Declaration.File) {
899 case TGSI_FILE_INPUT:
900 i = ctx->shader->ninput;
901 ctx->shader->ninput += count;
902 ctx->shader->input[i].name = d->Semantic.Name;
903 ctx->shader->input[i].sid = d->Semantic.Index;
904 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
905 ctx->shader->input[i].centroid = d->Interp.Centroid;
906 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
907 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
908 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
909 switch (ctx->shader->input[i].name) {
910 case TGSI_SEMANTIC_FACE:
911 ctx->face_gpr = ctx->shader->input[i].gpr;
912 break;
913 case TGSI_SEMANTIC_COLOR:
914 ctx->colors_used++;
915 break;
916 case TGSI_SEMANTIC_POSITION:
917 ctx->fragcoord_input = i;
918 break;
919 }
920 if (ctx->bc->chip_class >= EVERGREEN) {
921 if ((r = evergreen_interp_input(ctx, i)))
922 return r;
923 }
924 }
925 for (j = 1; j < count; ++j) {
926 ctx->shader->input[i + j] = ctx->shader->input[i];
927 ctx->shader->input[i + j].gpr += j;
928 }
929 break;
930 case TGSI_FILE_OUTPUT:
931 i = ctx->shader->noutput++;
932 ctx->shader->output[i].name = d->Semantic.Name;
933 ctx->shader->output[i].sid = d->Semantic.Index;
934 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
935 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
936 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
937 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
938 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
939 switch (d->Semantic.Name) {
940 case TGSI_SEMANTIC_CLIPDIST:
941 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
942 break;
943 case TGSI_SEMANTIC_PSIZE:
944 ctx->shader->vs_out_misc_write = 1;
945 ctx->shader->vs_out_point_size = 1;
946 break;
947 case TGSI_SEMANTIC_CLIPVERTEX:
948 ctx->clip_vertex_write = TRUE;
949 ctx->cv_output = i;
950 break;
951 }
952 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
953 switch (d->Semantic.Name) {
954 case TGSI_SEMANTIC_COLOR:
955 ctx->shader->nr_ps_max_color_exports++;
956 break;
957 }
958 }
959 break;
960 case TGSI_FILE_CONSTANT:
961 case TGSI_FILE_TEMPORARY:
962 case TGSI_FILE_SAMPLER:
963 case TGSI_FILE_ADDRESS:
964 break;
965
966 case TGSI_FILE_SYSTEM_VALUE:
967 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
968 if (!ctx->native_integers) {
969 struct r600_bytecode_alu alu;
970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
971
972 alu.op = ALU_OP1_INT_TO_FLT;
973 alu.src[0].sel = 0;
974 alu.src[0].chan = 3;
975
976 alu.dst.sel = 0;
977 alu.dst.chan = 3;
978 alu.dst.write = 1;
979 alu.last = 1;
980
981 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
982 return r;
983 }
984 break;
985 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
986 break;
987 default:
988 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
989 return -EINVAL;
990 }
991 return 0;
992 }
993
994 static int r600_get_temp(struct r600_shader_ctx *ctx)
995 {
996 return ctx->temp_reg + ctx->max_driver_temp_used++;
997 }
998
999 /*
1000 * for evergreen we need to scan the shader to find the number of GPRs we need to
1001 * reserve for interpolation.
1002 *
1003 * we need to know if we are going to emit
1004 * any centroid inputs
1005 * if perspective and linear are required
1006 */
1007 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1008 {
1009 int i;
1010 int num_baryc;
1011
1012 ctx->input_linear = FALSE;
1013 ctx->input_perspective = FALSE;
1014 ctx->input_centroid = FALSE;
1015 ctx->num_interp_gpr = 1;
1016
1017 /* any centroid inputs */
1018 for (i = 0; i < ctx->info.num_inputs; i++) {
1019 /* skip position/face */
1020 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1021 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
1022 continue;
1023 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
1024 ctx->input_linear = TRUE;
1025 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
1026 ctx->input_perspective = TRUE;
1027 if (ctx->info.input_centroid[i])
1028 ctx->input_centroid = TRUE;
1029 }
1030
1031 num_baryc = 0;
1032 /* ignoring sample for now */
1033 if (ctx->input_perspective)
1034 num_baryc++;
1035 if (ctx->input_linear)
1036 num_baryc++;
1037 if (ctx->input_centroid)
1038 num_baryc *= 2;
1039
1040 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
1041
1042 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
1043 return ctx->num_interp_gpr;
1044 }
1045
1046 static void tgsi_src(struct r600_shader_ctx *ctx,
1047 const struct tgsi_full_src_register *tgsi_src,
1048 struct r600_shader_src *r600_src)
1049 {
1050 memset(r600_src, 0, sizeof(*r600_src));
1051 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1052 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1053 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1054 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1055 r600_src->neg = tgsi_src->Register.Negate;
1056 r600_src->abs = tgsi_src->Register.Absolute;
1057
1058 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1059 int index;
1060 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1061 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1062 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1063
1064 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1065 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
1066 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1067 return;
1068 }
1069 index = tgsi_src->Register.Index;
1070 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1071 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1072 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1073 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1074 r600_src->swizzle[0] = 3;
1075 r600_src->swizzle[1] = 3;
1076 r600_src->swizzle[2] = 3;
1077 r600_src->swizzle[3] = 3;
1078 r600_src->sel = 0;
1079 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1080 r600_src->swizzle[0] = 0;
1081 r600_src->swizzle[1] = 0;
1082 r600_src->swizzle[2] = 0;
1083 r600_src->swizzle[3] = 0;
1084 r600_src->sel = 0;
1085 }
1086 } else {
1087 if (tgsi_src->Register.Indirect)
1088 r600_src->rel = V_SQ_REL_RELATIVE;
1089 r600_src->sel = tgsi_src->Register.Index;
1090 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1091 }
1092 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1093 if (tgsi_src->Register.Dimension) {
1094 r600_src->kc_bank = tgsi_src->Dimension.Index;
1095 }
1096 }
1097 }
1098
1099 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
1100 {
1101 struct r600_bytecode_vtx vtx;
1102 unsigned int ar_reg;
1103 int r;
1104
1105 if (offset) {
1106 struct r600_bytecode_alu alu;
1107
1108 memset(&alu, 0, sizeof(alu));
1109
1110 alu.op = ALU_OP2_ADD_INT;
1111 alu.src[0].sel = ctx->bc->ar_reg;
1112
1113 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1114 alu.src[1].value = offset;
1115
1116 alu.dst.sel = dst_reg;
1117 alu.dst.write = 1;
1118 alu.last = 1;
1119
1120 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1121 return r;
1122
1123 ar_reg = dst_reg;
1124 } else {
1125 ar_reg = ctx->bc->ar_reg;
1126 }
1127
1128 memset(&vtx, 0, sizeof(vtx));
1129 vtx.buffer_id = cb_idx;
1130 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
1131 vtx.src_gpr = ar_reg;
1132 vtx.mega_fetch_count = 16;
1133 vtx.dst_gpr = dst_reg;
1134 vtx.dst_sel_x = 0; /* SEL_X */
1135 vtx.dst_sel_y = 1; /* SEL_Y */
1136 vtx.dst_sel_z = 2; /* SEL_Z */
1137 vtx.dst_sel_w = 3; /* SEL_W */
1138 vtx.data_format = FMT_32_32_32_32_FLOAT;
1139 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1140 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1141 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1142 vtx.endian = r600_endian_swap(32);
1143
1144 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1145 return r;
1146
1147 return 0;
1148 }
1149
1150 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1151 {
1152 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1153 struct r600_bytecode_alu alu;
1154 int i, j, k, nconst, r;
1155
1156 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1157 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1158 nconst++;
1159 }
1160 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1161 }
1162 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1163 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1164 continue;
1165 }
1166
1167 if (ctx->src[i].rel) {
1168 int treg = r600_get_temp(ctx);
1169 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
1170 return r;
1171
1172 ctx->src[i].kc_bank = 0;
1173 ctx->src[i].sel = treg;
1174 ctx->src[i].rel = 0;
1175 j--;
1176 } else if (j > 0) {
1177 int treg = r600_get_temp(ctx);
1178 for (k = 0; k < 4; k++) {
1179 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1180 alu.op = ALU_OP1_MOV;
1181 alu.src[0].sel = ctx->src[i].sel;
1182 alu.src[0].chan = k;
1183 alu.src[0].rel = ctx->src[i].rel;
1184 alu.dst.sel = treg;
1185 alu.dst.chan = k;
1186 alu.dst.write = 1;
1187 if (k == 3)
1188 alu.last = 1;
1189 r = r600_bytecode_add_alu(ctx->bc, &alu);
1190 if (r)
1191 return r;
1192 }
1193 ctx->src[i].sel = treg;
1194 ctx->src[i].rel =0;
1195 j--;
1196 }
1197 }
1198 return 0;
1199 }
1200
1201 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1202 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1203 {
1204 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1205 struct r600_bytecode_alu alu;
1206 int i, j, k, nliteral, r;
1207
1208 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1209 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1210 nliteral++;
1211 }
1212 }
1213 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1214 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1215 int treg = r600_get_temp(ctx);
1216 for (k = 0; k < 4; k++) {
1217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1218 alu.op = ALU_OP1_MOV;
1219 alu.src[0].sel = ctx->src[i].sel;
1220 alu.src[0].chan = k;
1221 alu.src[0].value = ctx->src[i].value[k];
1222 alu.dst.sel = treg;
1223 alu.dst.chan = k;
1224 alu.dst.write = 1;
1225 if (k == 3)
1226 alu.last = 1;
1227 r = r600_bytecode_add_alu(ctx->bc, &alu);
1228 if (r)
1229 return r;
1230 }
1231 ctx->src[i].sel = treg;
1232 j--;
1233 }
1234 }
1235 return 0;
1236 }
1237
1238 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1239 {
1240 int i, r, count = ctx->shader->ninput;
1241
1242 for (i = 0; i < count; i++) {
1243 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1244 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1245 if (r)
1246 return r;
1247 }
1248 }
1249 return 0;
1250 }
1251
1252 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
1253 struct r600_pipe_shader *pipeshader,
1254 struct r600_shader_key key)
1255 {
1256 struct r600_shader *shader = &pipeshader->shader;
1257 struct tgsi_token *tokens = pipeshader->selector->tokens;
1258 struct pipe_stream_output_info so = pipeshader->selector->so;
1259 struct tgsi_full_immediate *immediate;
1260 struct tgsi_full_property *property;
1261 struct r600_shader_ctx ctx;
1262 struct r600_bytecode_output output[32];
1263 unsigned output_done, noutput;
1264 unsigned opcode;
1265 int i, j, k, r = 0;
1266 int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
1267 /* Declarations used by llvm code */
1268 bool use_llvm = false;
1269 unsigned char * inst_bytes = NULL;
1270 unsigned inst_byte_count = 0;
1271
1272 #ifdef R600_USE_LLVM
1273 use_llvm = !(rscreen->debug_flags & DBG_NO_LLVM);
1274 #endif
1275 ctx.bc = &shader->bc;
1276 ctx.shader = shader;
1277 ctx.native_integers = true;
1278
1279 r600_bytecode_init(ctx.bc, rscreen->chip_class, rscreen->family,
1280 rscreen->msaa_texture_support);
1281 ctx.tokens = tokens;
1282 tgsi_scan_shader(tokens, &ctx.info);
1283 tgsi_parse_init(&ctx.parse, tokens);
1284 ctx.type = ctx.parse.FullHeader.Processor.Processor;
1285 shader->processor_type = ctx.type;
1286 ctx.bc->type = shader->processor_type;
1287
1288 ctx.face_gpr = -1;
1289 ctx.fragcoord_input = -1;
1290 ctx.colors_used = 0;
1291 ctx.clip_vertex_write = 0;
1292
1293 shader->nr_ps_color_exports = 0;
1294 shader->nr_ps_max_color_exports = 0;
1295
1296 shader->two_side = key.color_two_side;
1297
1298 /* register allocations */
1299 /* Values [0,127] correspond to GPR[0..127].
1300 * Values [128,159] correspond to constant buffer bank 0
1301 * Values [160,191] correspond to constant buffer bank 1
1302 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1303 * Values [256,287] correspond to constant buffer bank 2 (EG)
1304 * Values [288,319] correspond to constant buffer bank 3 (EG)
1305 * Other special values are shown in the list below.
1306 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1307 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1308 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1309 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1310 * 248 SQ_ALU_SRC_0: special constant 0.0.
1311 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1312 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1313 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1314 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1315 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1316 * 254 SQ_ALU_SRC_PV: previous vector result.
1317 * 255 SQ_ALU_SRC_PS: previous scalar result.
1318 */
1319 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1320 ctx.file_offset[i] = 0;
1321 }
1322 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1323 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1324 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1325 }
1326 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1327 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1328 }
1329
1330 #ifdef R600_USE_LLVM
1331 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1332 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1333 "indirect adressing. Falling back to TGSI "
1334 "backend.\n");
1335 use_llvm = 0;
1336 }
1337 #endif
1338 ctx.use_llvm = use_llvm;
1339
1340 if (use_llvm) {
1341 ctx.file_offset[TGSI_FILE_OUTPUT] =
1342 ctx.file_offset[TGSI_FILE_INPUT];
1343 } else {
1344 ctx.file_offset[TGSI_FILE_OUTPUT] =
1345 ctx.file_offset[TGSI_FILE_INPUT] +
1346 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1347 }
1348 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1349 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1350
1351 /* Outside the GPR range. This will be translated to one of the
1352 * kcache banks later. */
1353 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1354
1355 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1356 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1357 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1358 ctx.temp_reg = ctx.bc->ar_reg + 1;
1359
1360 ctx.nliterals = 0;
1361 ctx.literals = NULL;
1362 shader->fs_write_all = FALSE;
1363 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1364 tgsi_parse_token(&ctx.parse);
1365 switch (ctx.parse.FullToken.Token.Type) {
1366 case TGSI_TOKEN_TYPE_IMMEDIATE:
1367 immediate = &ctx.parse.FullToken.FullImmediate;
1368 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1369 if(ctx.literals == NULL) {
1370 r = -ENOMEM;
1371 goto out_err;
1372 }
1373 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1374 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1375 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1376 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1377 ctx.nliterals++;
1378 break;
1379 case TGSI_TOKEN_TYPE_DECLARATION:
1380 r = tgsi_declaration(&ctx);
1381 if (r)
1382 goto out_err;
1383 break;
1384 case TGSI_TOKEN_TYPE_INSTRUCTION:
1385 break;
1386 case TGSI_TOKEN_TYPE_PROPERTY:
1387 property = &ctx.parse.FullToken.FullProperty;
1388 switch (property->Property.PropertyName) {
1389 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1390 if (property->u[0].Data == 1)
1391 shader->fs_write_all = TRUE;
1392 break;
1393 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1394 /* we don't need this one */
1395 break;
1396 }
1397 break;
1398 default:
1399 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1400 r = -EINVAL;
1401 goto out_err;
1402 }
1403 }
1404
1405 /* Process two side if needed */
1406 if (shader->two_side && ctx.colors_used) {
1407 int i, count = ctx.shader->ninput;
1408 unsigned next_lds_loc = ctx.shader->nlds;
1409
1410 /* additional inputs will be allocated right after the existing inputs,
1411 * we won't need them after the color selection, so we don't need to
1412 * reserve these gprs for the rest of the shader code and to adjust
1413 * output offsets etc. */
1414 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1415 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1416
1417 if (ctx.face_gpr == -1) {
1418 i = ctx.shader->ninput++;
1419 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1420 ctx.shader->input[i].spi_sid = 0;
1421 ctx.shader->input[i].gpr = gpr++;
1422 ctx.face_gpr = ctx.shader->input[i].gpr;
1423 }
1424
1425 for (i = 0; i < count; i++) {
1426 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1427 int ni = ctx.shader->ninput++;
1428 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1429 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1430 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1431 ctx.shader->input[ni].gpr = gpr++;
1432 // TGSI to LLVM needs to know the lds position of inputs.
1433 // Non LLVM path computes it later (in process_twoside_color)
1434 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1435 ctx.shader->input[i].back_color_input = ni;
1436 if (ctx.bc->chip_class >= EVERGREEN) {
1437 if ((r = evergreen_interp_input(&ctx, ni)))
1438 return r;
1439 }
1440 }
1441 }
1442 }
1443
1444 /* LLVM backend setup */
1445 #ifdef R600_USE_LLVM
1446 if (use_llvm) {
1447 struct radeon_llvm_context radeon_llvm_ctx;
1448 LLVMModuleRef mod;
1449 bool dump = r600_can_dump_shader(rscreen, ctx.type);
1450
1451 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1452 radeon_llvm_ctx.type = ctx.type;
1453 radeon_llvm_ctx.two_side = shader->two_side;
1454 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1455 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1456 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1457 radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
1458 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1459 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
1460 radeon_llvm_ctx.stream_outputs = &so;
1461 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1462 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1463 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1464
1465 if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
1466 rscreen->family, dump)) {
1467 FREE(inst_bytes);
1468 radeon_llvm_dispose(&radeon_llvm_ctx);
1469 use_llvm = 0;
1470 fprintf(stderr, "R600 LLVM backend failed to compile "
1471 "shader. Falling back to TGSI\n");
1472 } else {
1473 ctx.file_offset[TGSI_FILE_OUTPUT] =
1474 ctx.file_offset[TGSI_FILE_INPUT];
1475 }
1476 radeon_llvm_dispose(&radeon_llvm_ctx);
1477 }
1478 #endif
1479 /* End of LLVM backend setup */
1480
1481 if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
1482 shader->nr_ps_max_color_exports = 8;
1483
1484 if (!use_llvm) {
1485 if (ctx.fragcoord_input >= 0) {
1486 if (ctx.bc->chip_class == CAYMAN) {
1487 for (j = 0 ; j < 4; j++) {
1488 struct r600_bytecode_alu alu;
1489 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1490 alu.op = ALU_OP1_RECIP_IEEE;
1491 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1492 alu.src[0].chan = 3;
1493
1494 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1495 alu.dst.chan = j;
1496 alu.dst.write = (j == 3);
1497 alu.last = 1;
1498 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1499 return r;
1500 }
1501 } else {
1502 struct r600_bytecode_alu alu;
1503 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1504 alu.op = ALU_OP1_RECIP_IEEE;
1505 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1506 alu.src[0].chan = 3;
1507
1508 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1509 alu.dst.chan = 3;
1510 alu.dst.write = 1;
1511 alu.last = 1;
1512 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1513 return r;
1514 }
1515 }
1516
1517 if (shader->two_side && ctx.colors_used) {
1518 if ((r = process_twoside_color_inputs(&ctx)))
1519 return r;
1520 }
1521
1522 tgsi_parse_init(&ctx.parse, tokens);
1523 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1524 tgsi_parse_token(&ctx.parse);
1525 switch (ctx.parse.FullToken.Token.Type) {
1526 case TGSI_TOKEN_TYPE_INSTRUCTION:
1527 r = tgsi_is_supported(&ctx);
1528 if (r)
1529 goto out_err;
1530 ctx.max_driver_temp_used = 0;
1531 /* reserve first tmp for everyone */
1532 r600_get_temp(&ctx);
1533
1534 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1535 if ((r = tgsi_split_constant(&ctx)))
1536 goto out_err;
1537 if ((r = tgsi_split_literal_constant(&ctx)))
1538 goto out_err;
1539 if (ctx.bc->chip_class == CAYMAN)
1540 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1541 else if (ctx.bc->chip_class >= EVERGREEN)
1542 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1543 else
1544 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1545 r = ctx.inst_info->process(&ctx);
1546 if (r)
1547 goto out_err;
1548 break;
1549 default:
1550 break;
1551 }
1552 }
1553 }
1554
1555 /* Reset the temporary register counter. */
1556 ctx.max_driver_temp_used = 0;
1557
1558 /* Get instructions if we are using the LLVM backend. */
1559 if (use_llvm) {
1560 r600_bytecode_from_byte_stream(&ctx, inst_bytes, inst_byte_count);
1561 FREE(inst_bytes);
1562 }
1563
1564 noutput = shader->noutput;
1565
1566 if (ctx.clip_vertex_write) {
1567 unsigned clipdist_temp[2];
1568
1569 clipdist_temp[0] = r600_get_temp(&ctx);
1570 clipdist_temp[1] = r600_get_temp(&ctx);
1571
1572 /* need to convert a clipvertex write into clipdistance writes and not export
1573 the clip vertex anymore */
1574
1575 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1576 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1577 shader->output[noutput].gpr = clipdist_temp[0];
1578 noutput++;
1579 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1580 shader->output[noutput].gpr = clipdist_temp[1];
1581 noutput++;
1582
1583 /* reset spi_sid for clipvertex output to avoid confusing spi */
1584 shader->output[ctx.cv_output].spi_sid = 0;
1585
1586 shader->clip_dist_write = 0xFF;
1587
1588 for (i = 0; i < 8; i++) {
1589 int oreg = i >> 2;
1590 int ochan = i & 3;
1591
1592 for (j = 0; j < 4; j++) {
1593 struct r600_bytecode_alu alu;
1594 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1595 alu.op = ALU_OP2_DOT4;
1596 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1597 alu.src[0].chan = j;
1598
1599 alu.src[1].sel = 512 + i;
1600 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1601 alu.src[1].chan = j;
1602
1603 alu.dst.sel = clipdist_temp[oreg];
1604 alu.dst.chan = j;
1605 alu.dst.write = (j == ochan);
1606 if (j == 3)
1607 alu.last = 1;
1608 if (!use_llvm)
1609 r = r600_bytecode_add_alu(ctx.bc, &alu);
1610 if (r)
1611 return r;
1612 }
1613 }
1614 }
1615
1616 /* Add stream outputs. */
1617 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
1618 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1619
1620 /* Sanity checking. */
1621 if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1622 R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
1623 r = -EINVAL;
1624 goto out_err;
1625 }
1626 for (i = 0; i < so.num_outputs; i++) {
1627 if (so.output[i].output_buffer >= 4) {
1628 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1629 so.output[i].output_buffer);
1630 r = -EINVAL;
1631 goto out_err;
1632 }
1633 }
1634
1635 /* Initialize locations where the outputs are stored. */
1636 for (i = 0; i < so.num_outputs; i++) {
1637 so_gpr[i] = shader->output[so.output[i].register_index].gpr;
1638
1639 /* Lower outputs with dst_offset < start_component.
1640 *
1641 * We can only output 4D vectors with a write mask, e.g. we can
1642 * only output the W component at offset 3, etc. If we want
1643 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1644 * to move it to X and output X. */
1645 if (so.output[i].dst_offset < so.output[i].start_component) {
1646 unsigned tmp = r600_get_temp(&ctx);
1647
1648 for (j = 0; j < so.output[i].num_components; j++) {
1649 struct r600_bytecode_alu alu;
1650 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1651 alu.op = ALU_OP1_MOV;
1652 alu.src[0].sel = so_gpr[i];
1653 alu.src[0].chan = so.output[i].start_component + j;
1654
1655 alu.dst.sel = tmp;
1656 alu.dst.chan = j;
1657 alu.dst.write = 1;
1658 if (j == so.output[i].num_components - 1)
1659 alu.last = 1;
1660 r = r600_bytecode_add_alu(ctx.bc, &alu);
1661 if (r)
1662 return r;
1663 }
1664 so.output[i].start_component = 0;
1665 so_gpr[i] = tmp;
1666 }
1667 }
1668
1669 /* Write outputs to buffers. */
1670 for (i = 0; i < so.num_outputs; i++) {
1671 struct r600_bytecode_output output;
1672
1673 memset(&output, 0, sizeof(struct r600_bytecode_output));
1674 output.gpr = so_gpr[i];
1675 output.elem_size = so.output[i].num_components;
1676 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1677 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1678 output.burst_count = 1;
1679 output.barrier = 1;
1680 /* array_size is an upper limit for the burst_count
1681 * with MEM_STREAM instructions */
1682 output.array_size = 0xFFF;
1683 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1684 if (ctx.bc->chip_class >= EVERGREEN) {
1685 switch (so.output[i].output_buffer) {
1686 case 0:
1687 output.op = CF_OP_MEM_STREAM0_BUF0;
1688 break;
1689 case 1:
1690 output.op = CF_OP_MEM_STREAM0_BUF1;
1691 break;
1692 case 2:
1693 output.op = CF_OP_MEM_STREAM0_BUF2;
1694 break;
1695 case 3:
1696 output.op = CF_OP_MEM_STREAM0_BUF3;
1697 break;
1698 }
1699 } else {
1700 switch (so.output[i].output_buffer) {
1701 case 0:
1702 output.op = CF_OP_MEM_STREAM0;
1703 break;
1704 case 1:
1705 output.op = CF_OP_MEM_STREAM1;
1706 break;
1707 case 2:
1708 output.op = CF_OP_MEM_STREAM2;
1709 break;
1710 case 3:
1711 output.op = CF_OP_MEM_STREAM3;
1712 break;
1713 }
1714 }
1715 r = r600_bytecode_add_output(ctx.bc, &output);
1716 if (r)
1717 goto out_err;
1718 }
1719 }
1720
1721 /* export output */
1722 for (i = 0, j = 0; i < noutput; i++, j++) {
1723 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1724 output[j].gpr = shader->output[i].gpr;
1725 output[j].elem_size = 3;
1726 output[j].swizzle_x = 0;
1727 output[j].swizzle_y = 1;
1728 output[j].swizzle_z = 2;
1729 output[j].swizzle_w = 3;
1730 output[j].burst_count = 1;
1731 output[j].barrier = 1;
1732 output[j].type = -1;
1733 output[j].op = CF_OP_EXPORT;
1734 switch (ctx.type) {
1735 case TGSI_PROCESSOR_VERTEX:
1736 switch (shader->output[i].name) {
1737 case TGSI_SEMANTIC_POSITION:
1738 output[j].array_base = next_pos_base++;
1739 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1740 break;
1741
1742 case TGSI_SEMANTIC_PSIZE:
1743 output[j].array_base = next_pos_base++;
1744 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1745 break;
1746 case TGSI_SEMANTIC_CLIPVERTEX:
1747 j--;
1748 break;
1749 case TGSI_SEMANTIC_CLIPDIST:
1750 output[j].array_base = next_pos_base++;
1751 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1752 /* spi_sid is 0 for clipdistance outputs that were generated
1753 * for clipvertex - we don't need to pass them to PS */
1754 if (shader->output[i].spi_sid) {
1755 j++;
1756 /* duplicate it as PARAM to pass to the pixel shader */
1757 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1758 output[j].array_base = next_param_base++;
1759 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1760 }
1761 break;
1762 case TGSI_SEMANTIC_FOG:
1763 output[j].swizzle_y = 4; /* 0 */
1764 output[j].swizzle_z = 4; /* 0 */
1765 output[j].swizzle_w = 5; /* 1 */
1766 break;
1767 }
1768 break;
1769 case TGSI_PROCESSOR_FRAGMENT:
1770 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1771 /* never export more colors than the number of CBs */
1772 if (next_pixel_base && next_pixel_base >= key.nr_cbufs) {
1773 /* skip export */
1774 j--;
1775 continue;
1776 }
1777 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1778 output[j].array_base = next_pixel_base++;
1779 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1780 shader->nr_ps_color_exports++;
1781 if (shader->fs_write_all && (rscreen->chip_class >= EVERGREEN)) {
1782 for (k = 1; k < key.nr_cbufs; k++) {
1783 j++;
1784 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1785 output[j].gpr = shader->output[i].gpr;
1786 output[j].elem_size = 3;
1787 output[j].swizzle_x = 0;
1788 output[j].swizzle_y = 1;
1789 output[j].swizzle_z = 2;
1790 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1791 output[j].burst_count = 1;
1792 output[j].barrier = 1;
1793 output[j].array_base = next_pixel_base++;
1794 output[j].op = CF_OP_EXPORT;
1795 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1796 shader->nr_ps_color_exports++;
1797 }
1798 }
1799 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1800 output[j].array_base = 61;
1801 output[j].swizzle_x = 2;
1802 output[j].swizzle_y = 7;
1803 output[j].swizzle_z = output[j].swizzle_w = 7;
1804 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1805 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1806 output[j].array_base = 61;
1807 output[j].swizzle_x = 7;
1808 output[j].swizzle_y = 1;
1809 output[j].swizzle_z = output[j].swizzle_w = 7;
1810 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1811 } else {
1812 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1813 r = -EINVAL;
1814 goto out_err;
1815 }
1816 break;
1817 default:
1818 R600_ERR("unsupported processor type %d\n", ctx.type);
1819 r = -EINVAL;
1820 goto out_err;
1821 }
1822
1823 if (output[j].type==-1) {
1824 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1825 output[j].array_base = next_param_base++;
1826 }
1827 }
1828
1829 /* add fake position export */
1830 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1831 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1832 output[j].gpr = 0;
1833 output[j].elem_size = 3;
1834 output[j].swizzle_x = 7;
1835 output[j].swizzle_y = 7;
1836 output[j].swizzle_z = 7;
1837 output[j].swizzle_w = 7;
1838 output[j].burst_count = 1;
1839 output[j].barrier = 1;
1840 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1841 output[j].array_base = next_pos_base;
1842 output[j].op = CF_OP_EXPORT;
1843 j++;
1844 }
1845
1846 /* add fake param output for vertex shader if no param is exported */
1847 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1848 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1849 output[j].gpr = 0;
1850 output[j].elem_size = 3;
1851 output[j].swizzle_x = 7;
1852 output[j].swizzle_y = 7;
1853 output[j].swizzle_z = 7;
1854 output[j].swizzle_w = 7;
1855 output[j].burst_count = 1;
1856 output[j].barrier = 1;
1857 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1858 output[j].array_base = 0;
1859 output[j].op = CF_OP_EXPORT;
1860 j++;
1861 }
1862
1863 /* add fake pixel export */
1864 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && next_pixel_base == 0) {
1865 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1866 output[j].gpr = 0;
1867 output[j].elem_size = 3;
1868 output[j].swizzle_x = 7;
1869 output[j].swizzle_y = 7;
1870 output[j].swizzle_z = 7;
1871 output[j].swizzle_w = 7;
1872 output[j].burst_count = 1;
1873 output[j].barrier = 1;
1874 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1875 output[j].array_base = 0;
1876 output[j].op = CF_OP_EXPORT;
1877 j++;
1878 }
1879
1880 noutput = j;
1881
1882 /* set export done on last export of each type */
1883 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1884 if (ctx.bc->chip_class < CAYMAN) {
1885 if (i == (noutput - 1)) {
1886 output[i].end_of_program = 1;
1887 }
1888 }
1889 if (!(output_done & (1 << output[i].type))) {
1890 output_done |= (1 << output[i].type);
1891 output[i].op = CF_OP_EXPORT_DONE;
1892 }
1893 }
1894 /* add output to bytecode */
1895 if (!use_llvm) {
1896 for (i = 0; i < noutput; i++) {
1897 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1898 if (r)
1899 goto out_err;
1900 }
1901 }
1902 /* add program end */
1903 if (ctx.bc->chip_class == CAYMAN)
1904 cm_bytecode_add_cf_end(ctx.bc);
1905
1906 /* check GPR limit - we have 124 = 128 - 4
1907 * (4 are reserved as alu clause temporary registers) */
1908 if (ctx.bc->ngpr > 124) {
1909 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1910 r = -ENOMEM;
1911 goto out_err;
1912 }
1913
1914 free(ctx.literals);
1915 tgsi_parse_free(&ctx.parse);
1916 return 0;
1917 out_err:
1918 free(ctx.literals);
1919 tgsi_parse_free(&ctx.parse);
1920 return r;
1921 }
1922
1923 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1924 {
1925 R600_ERR("%s tgsi opcode unsupported\n",
1926 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1927 return -EINVAL;
1928 }
1929
1930 static int tgsi_end(struct r600_shader_ctx *ctx)
1931 {
1932 return 0;
1933 }
1934
1935 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1936 const struct r600_shader_src *shader_src,
1937 unsigned chan)
1938 {
1939 bc_src->sel = shader_src->sel;
1940 bc_src->chan = shader_src->swizzle[chan];
1941 bc_src->neg = shader_src->neg;
1942 bc_src->abs = shader_src->abs;
1943 bc_src->rel = shader_src->rel;
1944 bc_src->value = shader_src->value[bc_src->chan];
1945 bc_src->kc_bank = shader_src->kc_bank;
1946 }
1947
1948 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1949 {
1950 bc_src->abs = 1;
1951 bc_src->neg = 0;
1952 }
1953
1954 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1955 {
1956 bc_src->neg = !bc_src->neg;
1957 }
1958
1959 static void tgsi_dst(struct r600_shader_ctx *ctx,
1960 const struct tgsi_full_dst_register *tgsi_dst,
1961 unsigned swizzle,
1962 struct r600_bytecode_alu_dst *r600_dst)
1963 {
1964 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1965
1966 r600_dst->sel = tgsi_dst->Register.Index;
1967 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1968 r600_dst->chan = swizzle;
1969 r600_dst->write = 1;
1970 if (tgsi_dst->Register.Indirect)
1971 r600_dst->rel = V_SQ_REL_RELATIVE;
1972 if (inst->Instruction.Saturate) {
1973 r600_dst->clamp = 1;
1974 }
1975 }
1976
1977 static int tgsi_last_instruction(unsigned writemask)
1978 {
1979 int i, lasti = 0;
1980
1981 for (i = 0; i < 4; i++) {
1982 if (writemask & (1 << i)) {
1983 lasti = i;
1984 }
1985 }
1986 return lasti;
1987 }
1988
1989 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1990 {
1991 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1992 struct r600_bytecode_alu alu;
1993 int i, j, r;
1994 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1995
1996 for (i = 0; i < lasti + 1; i++) {
1997 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1998 continue;
1999
2000 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2001 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2002
2003 alu.op = ctx->inst_info->op;
2004 if (!swap) {
2005 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2006 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2007 }
2008 } else {
2009 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2010 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2011 }
2012 /* handle some special cases */
2013 switch (ctx->inst_info->tgsi_opcode) {
2014 case TGSI_OPCODE_SUB:
2015 r600_bytecode_src_toggle_neg(&alu.src[1]);
2016 break;
2017 case TGSI_OPCODE_ABS:
2018 r600_bytecode_src_set_abs(&alu.src[0]);
2019 break;
2020 default:
2021 break;
2022 }
2023 if (i == lasti || trans_only) {
2024 alu.last = 1;
2025 }
2026 r = r600_bytecode_add_alu(ctx->bc, &alu);
2027 if (r)
2028 return r;
2029 }
2030 return 0;
2031 }
2032
2033 static int tgsi_op2(struct r600_shader_ctx *ctx)
2034 {
2035 return tgsi_op2_s(ctx, 0, 0);
2036 }
2037
2038 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2039 {
2040 return tgsi_op2_s(ctx, 1, 0);
2041 }
2042
2043 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2044 {
2045 return tgsi_op2_s(ctx, 0, 1);
2046 }
2047
2048 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2049 {
2050 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2051 struct r600_bytecode_alu alu;
2052 int i, r;
2053 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2054
2055 for (i = 0; i < lasti + 1; i++) {
2056
2057 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2058 continue;
2059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2060 alu.op = ctx->inst_info->op;
2061
2062 alu.src[0].sel = V_SQ_ALU_SRC_0;
2063
2064 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2065
2066 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2067
2068 if (i == lasti) {
2069 alu.last = 1;
2070 }
2071 r = r600_bytecode_add_alu(ctx->bc, &alu);
2072 if (r)
2073 return r;
2074 }
2075 return 0;
2076
2077 }
2078
2079 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
2080 {
2081 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2082 int i, j, r;
2083 struct r600_bytecode_alu alu;
2084 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2085
2086 for (i = 0 ; i < last_slot; i++) {
2087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2088 alu.op = ctx->inst_info->op;
2089 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2090 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
2091
2092 /* RSQ should take the absolute value of src */
2093 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
2094 r600_bytecode_src_set_abs(&alu.src[j]);
2095 }
2096 }
2097 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2098 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2099
2100 if (i == last_slot - 1)
2101 alu.last = 1;
2102 r = r600_bytecode_add_alu(ctx->bc, &alu);
2103 if (r)
2104 return r;
2105 }
2106 return 0;
2107 }
2108
2109 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
2110 {
2111 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2112 int i, j, k, r;
2113 struct r600_bytecode_alu alu;
2114 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2115 for (k = 0; k < last_slot; k++) {
2116 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
2117 continue;
2118
2119 for (i = 0 ; i < 4; i++) {
2120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2121 alu.op = ctx->inst_info->op;
2122 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2123 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
2124 }
2125 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2126 alu.dst.write = (i == k);
2127 if (i == 3)
2128 alu.last = 1;
2129 r = r600_bytecode_add_alu(ctx->bc, &alu);
2130 if (r)
2131 return r;
2132 }
2133 }
2134 return 0;
2135 }
2136
2137 /*
2138 * r600 - trunc to -PI..PI range
2139 * r700 - normalize by dividing by 2PI
2140 * see fdo bug 27901
2141 */
2142 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
2143 {
2144 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
2145 static float double_pi = 3.1415926535 * 2;
2146 static float neg_pi = -3.1415926535;
2147
2148 int r;
2149 struct r600_bytecode_alu alu;
2150
2151 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2152 alu.op = ALU_OP3_MULADD;
2153 alu.is_op3 = 1;
2154
2155 alu.dst.chan = 0;
2156 alu.dst.sel = ctx->temp_reg;
2157 alu.dst.write = 1;
2158
2159 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2160
2161 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2162 alu.src[1].chan = 0;
2163 alu.src[1].value = *(uint32_t *)&half_inv_pi;
2164 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2165 alu.src[2].chan = 0;
2166 alu.last = 1;
2167 r = r600_bytecode_add_alu(ctx->bc, &alu);
2168 if (r)
2169 return r;
2170
2171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2172 alu.op = ALU_OP1_FRACT;
2173
2174 alu.dst.chan = 0;
2175 alu.dst.sel = ctx->temp_reg;
2176 alu.dst.write = 1;
2177
2178 alu.src[0].sel = ctx->temp_reg;
2179 alu.src[0].chan = 0;
2180 alu.last = 1;
2181 r = r600_bytecode_add_alu(ctx->bc, &alu);
2182 if (r)
2183 return r;
2184
2185 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2186 alu.op = ALU_OP3_MULADD;
2187 alu.is_op3 = 1;
2188
2189 alu.dst.chan = 0;
2190 alu.dst.sel = ctx->temp_reg;
2191 alu.dst.write = 1;
2192
2193 alu.src[0].sel = ctx->temp_reg;
2194 alu.src[0].chan = 0;
2195
2196 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2197 alu.src[1].chan = 0;
2198 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2199 alu.src[2].chan = 0;
2200
2201 if (ctx->bc->chip_class == R600) {
2202 alu.src[1].value = *(uint32_t *)&double_pi;
2203 alu.src[2].value = *(uint32_t *)&neg_pi;
2204 } else {
2205 alu.src[1].sel = V_SQ_ALU_SRC_1;
2206 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2207 alu.src[2].neg = 1;
2208 }
2209
2210 alu.last = 1;
2211 r = r600_bytecode_add_alu(ctx->bc, &alu);
2212 if (r)
2213 return r;
2214 return 0;
2215 }
2216
2217 static int cayman_trig(struct r600_shader_ctx *ctx)
2218 {
2219 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2220 struct r600_bytecode_alu alu;
2221 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2222 int i, r;
2223
2224 r = tgsi_setup_trig(ctx);
2225 if (r)
2226 return r;
2227
2228
2229 for (i = 0; i < last_slot; i++) {
2230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2231 alu.op = ctx->inst_info->op;
2232 alu.dst.chan = i;
2233
2234 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2235 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2236
2237 alu.src[0].sel = ctx->temp_reg;
2238 alu.src[0].chan = 0;
2239 if (i == last_slot - 1)
2240 alu.last = 1;
2241 r = r600_bytecode_add_alu(ctx->bc, &alu);
2242 if (r)
2243 return r;
2244 }
2245 return 0;
2246 }
2247
2248 static int tgsi_trig(struct r600_shader_ctx *ctx)
2249 {
2250 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2251 struct r600_bytecode_alu alu;
2252 int i, r;
2253 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2254
2255 r = tgsi_setup_trig(ctx);
2256 if (r)
2257 return r;
2258
2259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2260 alu.op = ctx->inst_info->op;
2261 alu.dst.chan = 0;
2262 alu.dst.sel = ctx->temp_reg;
2263 alu.dst.write = 1;
2264
2265 alu.src[0].sel = ctx->temp_reg;
2266 alu.src[0].chan = 0;
2267 alu.last = 1;
2268 r = r600_bytecode_add_alu(ctx->bc, &alu);
2269 if (r)
2270 return r;
2271
2272 /* replicate result */
2273 for (i = 0; i < lasti + 1; i++) {
2274 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2275 continue;
2276
2277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2278 alu.op = ALU_OP1_MOV;
2279
2280 alu.src[0].sel = ctx->temp_reg;
2281 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2282 if (i == lasti)
2283 alu.last = 1;
2284 r = r600_bytecode_add_alu(ctx->bc, &alu);
2285 if (r)
2286 return r;
2287 }
2288 return 0;
2289 }
2290
2291 static int tgsi_scs(struct r600_shader_ctx *ctx)
2292 {
2293 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2294 struct r600_bytecode_alu alu;
2295 int i, r;
2296
2297 /* We'll only need the trig stuff if we are going to write to the
2298 * X or Y components of the destination vector.
2299 */
2300 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2301 r = tgsi_setup_trig(ctx);
2302 if (r)
2303 return r;
2304 }
2305
2306 /* dst.x = COS */
2307 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2308 if (ctx->bc->chip_class == CAYMAN) {
2309 for (i = 0 ; i < 3; i++) {
2310 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2311 alu.op = ALU_OP1_COS;
2312 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2313
2314 if (i == 0)
2315 alu.dst.write = 1;
2316 else
2317 alu.dst.write = 0;
2318 alu.src[0].sel = ctx->temp_reg;
2319 alu.src[0].chan = 0;
2320 if (i == 2)
2321 alu.last = 1;
2322 r = r600_bytecode_add_alu(ctx->bc, &alu);
2323 if (r)
2324 return r;
2325 }
2326 } else {
2327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2328 alu.op = ALU_OP1_COS;
2329 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2330
2331 alu.src[0].sel = ctx->temp_reg;
2332 alu.src[0].chan = 0;
2333 alu.last = 1;
2334 r = r600_bytecode_add_alu(ctx->bc, &alu);
2335 if (r)
2336 return r;
2337 }
2338 }
2339
2340 /* dst.y = SIN */
2341 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2342 if (ctx->bc->chip_class == CAYMAN) {
2343 for (i = 0 ; i < 3; i++) {
2344 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2345 alu.op = ALU_OP1_SIN;
2346 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2347 if (i == 1)
2348 alu.dst.write = 1;
2349 else
2350 alu.dst.write = 0;
2351 alu.src[0].sel = ctx->temp_reg;
2352 alu.src[0].chan = 0;
2353 if (i == 2)
2354 alu.last = 1;
2355 r = r600_bytecode_add_alu(ctx->bc, &alu);
2356 if (r)
2357 return r;
2358 }
2359 } else {
2360 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2361 alu.op = ALU_OP1_SIN;
2362 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2363
2364 alu.src[0].sel = ctx->temp_reg;
2365 alu.src[0].chan = 0;
2366 alu.last = 1;
2367 r = r600_bytecode_add_alu(ctx->bc, &alu);
2368 if (r)
2369 return r;
2370 }
2371 }
2372
2373 /* dst.z = 0.0; */
2374 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2375 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2376
2377 alu.op = ALU_OP1_MOV;
2378
2379 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2380
2381 alu.src[0].sel = V_SQ_ALU_SRC_0;
2382 alu.src[0].chan = 0;
2383
2384 alu.last = 1;
2385
2386 r = r600_bytecode_add_alu(ctx->bc, &alu);
2387 if (r)
2388 return r;
2389 }
2390
2391 /* dst.w = 1.0; */
2392 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2393 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2394
2395 alu.op = ALU_OP1_MOV;
2396
2397 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2398
2399 alu.src[0].sel = V_SQ_ALU_SRC_1;
2400 alu.src[0].chan = 0;
2401
2402 alu.last = 1;
2403
2404 r = r600_bytecode_add_alu(ctx->bc, &alu);
2405 if (r)
2406 return r;
2407 }
2408
2409 return 0;
2410 }
2411
2412 static int tgsi_kill(struct r600_shader_ctx *ctx)
2413 {
2414 struct r600_bytecode_alu alu;
2415 int i, r;
2416
2417 for (i = 0; i < 4; i++) {
2418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2419 alu.op = ctx->inst_info->op;
2420
2421 alu.dst.chan = i;
2422
2423 alu.src[0].sel = V_SQ_ALU_SRC_0;
2424
2425 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
2426 alu.src[1].sel = V_SQ_ALU_SRC_1;
2427 alu.src[1].neg = 1;
2428 } else {
2429 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2430 }
2431 if (i == 3) {
2432 alu.last = 1;
2433 }
2434 r = r600_bytecode_add_alu(ctx->bc, &alu);
2435 if (r)
2436 return r;
2437 }
2438
2439 /* kill must be last in ALU */
2440 ctx->bc->force_add_cf = 1;
2441 ctx->shader->uses_kill = TRUE;
2442 return 0;
2443 }
2444
2445 static int tgsi_lit(struct r600_shader_ctx *ctx)
2446 {
2447 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2448 struct r600_bytecode_alu alu;
2449 int r;
2450
2451 /* tmp.x = max(src.y, 0.0) */
2452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2453 alu.op = ALU_OP2_MAX;
2454 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2455 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2456 alu.src[1].chan = 1;
2457
2458 alu.dst.sel = ctx->temp_reg;
2459 alu.dst.chan = 0;
2460 alu.dst.write = 1;
2461
2462 alu.last = 1;
2463 r = r600_bytecode_add_alu(ctx->bc, &alu);
2464 if (r)
2465 return r;
2466
2467 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2468 {
2469 int chan;
2470 int sel;
2471 int i;
2472
2473 if (ctx->bc->chip_class == CAYMAN) {
2474 for (i = 0; i < 3; i++) {
2475 /* tmp.z = log(tmp.x) */
2476 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2477 alu.op = ALU_OP1_LOG_CLAMPED;
2478 alu.src[0].sel = ctx->temp_reg;
2479 alu.src[0].chan = 0;
2480 alu.dst.sel = ctx->temp_reg;
2481 alu.dst.chan = i;
2482 if (i == 2) {
2483 alu.dst.write = 1;
2484 alu.last = 1;
2485 } else
2486 alu.dst.write = 0;
2487
2488 r = r600_bytecode_add_alu(ctx->bc, &alu);
2489 if (r)
2490 return r;
2491 }
2492 } else {
2493 /* tmp.z = log(tmp.x) */
2494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2495 alu.op = ALU_OP1_LOG_CLAMPED;
2496 alu.src[0].sel = ctx->temp_reg;
2497 alu.src[0].chan = 0;
2498 alu.dst.sel = ctx->temp_reg;
2499 alu.dst.chan = 2;
2500 alu.dst.write = 1;
2501 alu.last = 1;
2502 r = r600_bytecode_add_alu(ctx->bc, &alu);
2503 if (r)
2504 return r;
2505 }
2506
2507 chan = alu.dst.chan;
2508 sel = alu.dst.sel;
2509
2510 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2512 alu.op = ALU_OP3_MUL_LIT;
2513 alu.src[0].sel = sel;
2514 alu.src[0].chan = chan;
2515 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2516 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2517 alu.dst.sel = ctx->temp_reg;
2518 alu.dst.chan = 0;
2519 alu.dst.write = 1;
2520 alu.is_op3 = 1;
2521 alu.last = 1;
2522 r = r600_bytecode_add_alu(ctx->bc, &alu);
2523 if (r)
2524 return r;
2525
2526 if (ctx->bc->chip_class == CAYMAN) {
2527 for (i = 0; i < 3; i++) {
2528 /* dst.z = exp(tmp.x) */
2529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2530 alu.op = ALU_OP1_EXP_IEEE;
2531 alu.src[0].sel = ctx->temp_reg;
2532 alu.src[0].chan = 0;
2533 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2534 if (i == 2) {
2535 alu.dst.write = 1;
2536 alu.last = 1;
2537 } else
2538 alu.dst.write = 0;
2539 r = r600_bytecode_add_alu(ctx->bc, &alu);
2540 if (r)
2541 return r;
2542 }
2543 } else {
2544 /* dst.z = exp(tmp.x) */
2545 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2546 alu.op = ALU_OP1_EXP_IEEE;
2547 alu.src[0].sel = ctx->temp_reg;
2548 alu.src[0].chan = 0;
2549 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2550 alu.last = 1;
2551 r = r600_bytecode_add_alu(ctx->bc, &alu);
2552 if (r)
2553 return r;
2554 }
2555 }
2556
2557 /* dst.x, <- 1.0 */
2558 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2559 alu.op = ALU_OP1_MOV;
2560 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2561 alu.src[0].chan = 0;
2562 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2563 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2564 r = r600_bytecode_add_alu(ctx->bc, &alu);
2565 if (r)
2566 return r;
2567
2568 /* dst.y = max(src.x, 0.0) */
2569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2570 alu.op = ALU_OP2_MAX;
2571 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2572 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2573 alu.src[1].chan = 0;
2574 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2575 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2576 r = r600_bytecode_add_alu(ctx->bc, &alu);
2577 if (r)
2578 return r;
2579
2580 /* dst.w, <- 1.0 */
2581 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2582 alu.op = ALU_OP1_MOV;
2583 alu.src[0].sel = V_SQ_ALU_SRC_1;
2584 alu.src[0].chan = 0;
2585 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2586 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2587 alu.last = 1;
2588 r = r600_bytecode_add_alu(ctx->bc, &alu);
2589 if (r)
2590 return r;
2591
2592 return 0;
2593 }
2594
2595 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2596 {
2597 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2598 struct r600_bytecode_alu alu;
2599 int i, r;
2600
2601 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2602
2603 /* XXX:
2604 * For state trackers other than OpenGL, we'll want to use
2605 * _RECIPSQRT_IEEE instead.
2606 */
2607 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2608
2609 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2610 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2611 r600_bytecode_src_set_abs(&alu.src[i]);
2612 }
2613 alu.dst.sel = ctx->temp_reg;
2614 alu.dst.write = 1;
2615 alu.last = 1;
2616 r = r600_bytecode_add_alu(ctx->bc, &alu);
2617 if (r)
2618 return r;
2619 /* replicate result */
2620 return tgsi_helper_tempx_replicate(ctx);
2621 }
2622
2623 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2624 {
2625 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2626 struct r600_bytecode_alu alu;
2627 int i, r;
2628
2629 for (i = 0; i < 4; i++) {
2630 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2631 alu.src[0].sel = ctx->temp_reg;
2632 alu.op = ALU_OP1_MOV;
2633 alu.dst.chan = i;
2634 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2635 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2636 if (i == 3)
2637 alu.last = 1;
2638 r = r600_bytecode_add_alu(ctx->bc, &alu);
2639 if (r)
2640 return r;
2641 }
2642 return 0;
2643 }
2644
2645 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2646 {
2647 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2648 struct r600_bytecode_alu alu;
2649 int i, r;
2650
2651 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2652 alu.op = ctx->inst_info->op;
2653 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2654 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2655 }
2656 alu.dst.sel = ctx->temp_reg;
2657 alu.dst.write = 1;
2658 alu.last = 1;
2659 r = r600_bytecode_add_alu(ctx->bc, &alu);
2660 if (r)
2661 return r;
2662 /* replicate result */
2663 return tgsi_helper_tempx_replicate(ctx);
2664 }
2665
2666 static int cayman_pow(struct r600_shader_ctx *ctx)
2667 {
2668 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2669 int i, r;
2670 struct r600_bytecode_alu alu;
2671 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2672
2673 for (i = 0; i < 3; i++) {
2674 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2675 alu.op = ALU_OP1_LOG_IEEE;
2676 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2677 alu.dst.sel = ctx->temp_reg;
2678 alu.dst.chan = i;
2679 alu.dst.write = 1;
2680 if (i == 2)
2681 alu.last = 1;
2682 r = r600_bytecode_add_alu(ctx->bc, &alu);
2683 if (r)
2684 return r;
2685 }
2686
2687 /* b * LOG2(a) */
2688 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2689 alu.op = ALU_OP2_MUL;
2690 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2691 alu.src[1].sel = ctx->temp_reg;
2692 alu.dst.sel = ctx->temp_reg;
2693 alu.dst.write = 1;
2694 alu.last = 1;
2695 r = r600_bytecode_add_alu(ctx->bc, &alu);
2696 if (r)
2697 return r;
2698
2699 for (i = 0; i < last_slot; i++) {
2700 /* POW(a,b) = EXP2(b * LOG2(a))*/
2701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2702 alu.op = ALU_OP1_EXP_IEEE;
2703 alu.src[0].sel = ctx->temp_reg;
2704
2705 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2706 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2707 if (i == last_slot - 1)
2708 alu.last = 1;
2709 r = r600_bytecode_add_alu(ctx->bc, &alu);
2710 if (r)
2711 return r;
2712 }
2713 return 0;
2714 }
2715
2716 static int tgsi_pow(struct r600_shader_ctx *ctx)
2717 {
2718 struct r600_bytecode_alu alu;
2719 int r;
2720
2721 /* LOG2(a) */
2722 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2723 alu.op = ALU_OP1_LOG_IEEE;
2724 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2725 alu.dst.sel = ctx->temp_reg;
2726 alu.dst.write = 1;
2727 alu.last = 1;
2728 r = r600_bytecode_add_alu(ctx->bc, &alu);
2729 if (r)
2730 return r;
2731 /* b * LOG2(a) */
2732 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2733 alu.op = ALU_OP2_MUL;
2734 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2735 alu.src[1].sel = ctx->temp_reg;
2736 alu.dst.sel = ctx->temp_reg;
2737 alu.dst.write = 1;
2738 alu.last = 1;
2739 r = r600_bytecode_add_alu(ctx->bc, &alu);
2740 if (r)
2741 return r;
2742 /* POW(a,b) = EXP2(b * LOG2(a))*/
2743 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2744 alu.op = ALU_OP1_EXP_IEEE;
2745 alu.src[0].sel = ctx->temp_reg;
2746 alu.dst.sel = ctx->temp_reg;
2747 alu.dst.write = 1;
2748 alu.last = 1;
2749 r = r600_bytecode_add_alu(ctx->bc, &alu);
2750 if (r)
2751 return r;
2752 return tgsi_helper_tempx_replicate(ctx);
2753 }
2754
2755 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2756 {
2757 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2758 struct r600_bytecode_alu alu;
2759 int i, r, j;
2760 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2761 int tmp0 = ctx->temp_reg;
2762 int tmp1 = r600_get_temp(ctx);
2763 int tmp2 = r600_get_temp(ctx);
2764 int tmp3 = r600_get_temp(ctx);
2765 /* Unsigned path:
2766 *
2767 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2768 *
2769 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2770 * 2. tmp0.z = lo (tmp0.x * src2)
2771 * 3. tmp0.w = -tmp0.z
2772 * 4. tmp0.y = hi (tmp0.x * src2)
2773 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2774 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2775 * 7. tmp1.x = tmp0.x - tmp0.w
2776 * 8. tmp1.y = tmp0.x + tmp0.w
2777 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2778 * 10. tmp0.z = hi(tmp0.x * src1) = q
2779 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2780 *
2781 * 12. tmp0.w = src1 - tmp0.y = r
2782 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2783 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2784 *
2785 * if DIV
2786 *
2787 * 15. tmp1.z = tmp0.z + 1 = q + 1
2788 * 16. tmp1.w = tmp0.z - 1 = q - 1
2789 *
2790 * else MOD
2791 *
2792 * 15. tmp1.z = tmp0.w - src2 = r - src2
2793 * 16. tmp1.w = tmp0.w + src2 = r + src2
2794 *
2795 * endif
2796 *
2797 * 17. tmp1.x = tmp1.x & tmp1.y
2798 *
2799 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2800 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2801 *
2802 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2803 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2804 *
2805 * Signed path:
2806 *
2807 * Same as unsigned, using abs values of the operands,
2808 * and fixing the sign of the result in the end.
2809 */
2810
2811 for (i = 0; i < 4; i++) {
2812 if (!(write_mask & (1<<i)))
2813 continue;
2814
2815 if (signed_op) {
2816
2817 /* tmp2.x = -src0 */
2818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2819 alu.op = ALU_OP2_SUB_INT;
2820
2821 alu.dst.sel = tmp2;
2822 alu.dst.chan = 0;
2823 alu.dst.write = 1;
2824
2825 alu.src[0].sel = V_SQ_ALU_SRC_0;
2826
2827 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2828
2829 alu.last = 1;
2830 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2831 return r;
2832
2833 /* tmp2.y = -src1 */
2834 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2835 alu.op = ALU_OP2_SUB_INT;
2836
2837 alu.dst.sel = tmp2;
2838 alu.dst.chan = 1;
2839 alu.dst.write = 1;
2840
2841 alu.src[0].sel = V_SQ_ALU_SRC_0;
2842
2843 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2844
2845 alu.last = 1;
2846 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2847 return r;
2848
2849 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2850 /* it will be a sign of the quotient */
2851 if (!mod) {
2852
2853 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2854 alu.op = ALU_OP2_XOR_INT;
2855
2856 alu.dst.sel = tmp2;
2857 alu.dst.chan = 2;
2858 alu.dst.write = 1;
2859
2860 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2861 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2862
2863 alu.last = 1;
2864 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2865 return r;
2866 }
2867
2868 /* tmp2.x = |src0| */
2869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2870 alu.op = ALU_OP3_CNDGE_INT;
2871 alu.is_op3 = 1;
2872
2873 alu.dst.sel = tmp2;
2874 alu.dst.chan = 0;
2875 alu.dst.write = 1;
2876
2877 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2878 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2879 alu.src[2].sel = tmp2;
2880 alu.src[2].chan = 0;
2881
2882 alu.last = 1;
2883 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2884 return r;
2885
2886 /* tmp2.y = |src1| */
2887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2888 alu.op = ALU_OP3_CNDGE_INT;
2889 alu.is_op3 = 1;
2890
2891 alu.dst.sel = tmp2;
2892 alu.dst.chan = 1;
2893 alu.dst.write = 1;
2894
2895 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2896 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2897 alu.src[2].sel = tmp2;
2898 alu.src[2].chan = 1;
2899
2900 alu.last = 1;
2901 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2902 return r;
2903
2904 }
2905
2906 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2907 if (ctx->bc->chip_class == CAYMAN) {
2908 /* tmp3.x = u2f(src2) */
2909 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2910 alu.op = ALU_OP1_UINT_TO_FLT;
2911
2912 alu.dst.sel = tmp3;
2913 alu.dst.chan = 0;
2914 alu.dst.write = 1;
2915
2916 if (signed_op) {
2917 alu.src[0].sel = tmp2;
2918 alu.src[0].chan = 1;
2919 } else {
2920 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2921 }
2922
2923 alu.last = 1;
2924 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2925 return r;
2926
2927 /* tmp0.x = recip(tmp3.x) */
2928 for (j = 0 ; j < 3; j++) {
2929 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2930 alu.op = ALU_OP1_RECIP_IEEE;
2931
2932 alu.dst.sel = tmp0;
2933 alu.dst.chan = j;
2934 alu.dst.write = (j == 0);
2935
2936 alu.src[0].sel = tmp3;
2937 alu.src[0].chan = 0;
2938
2939 if (j == 2)
2940 alu.last = 1;
2941 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2942 return r;
2943 }
2944
2945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2946 alu.op = ALU_OP2_MUL;
2947
2948 alu.src[0].sel = tmp0;
2949 alu.src[0].chan = 0;
2950
2951 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2952 alu.src[1].value = 0x4f800000;
2953
2954 alu.dst.sel = tmp3;
2955 alu.dst.write = 1;
2956 alu.last = 1;
2957 r = r600_bytecode_add_alu(ctx->bc, &alu);
2958 if (r)
2959 return r;
2960
2961 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2962 alu.op = ALU_OP1_FLT_TO_UINT;
2963
2964 alu.dst.sel = tmp0;
2965 alu.dst.chan = 0;
2966 alu.dst.write = 1;
2967
2968 alu.src[0].sel = tmp3;
2969 alu.src[0].chan = 0;
2970
2971 alu.last = 1;
2972 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2973 return r;
2974
2975 } else {
2976 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2977 alu.op = ALU_OP1_RECIP_UINT;
2978
2979 alu.dst.sel = tmp0;
2980 alu.dst.chan = 0;
2981 alu.dst.write = 1;
2982
2983 if (signed_op) {
2984 alu.src[0].sel = tmp2;
2985 alu.src[0].chan = 1;
2986 } else {
2987 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2988 }
2989
2990 alu.last = 1;
2991 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2992 return r;
2993 }
2994
2995 /* 2. tmp0.z = lo (tmp0.x * src2) */
2996 if (ctx->bc->chip_class == CAYMAN) {
2997 for (j = 0 ; j < 4; j++) {
2998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2999 alu.op = ALU_OP2_MULLO_UINT;
3000
3001 alu.dst.sel = tmp0;
3002 alu.dst.chan = j;
3003 alu.dst.write = (j == 2);
3004
3005 alu.src[0].sel = tmp0;
3006 alu.src[0].chan = 0;
3007 if (signed_op) {
3008 alu.src[1].sel = tmp2;
3009 alu.src[1].chan = 1;
3010 } else {
3011 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3012 }
3013
3014 alu.last = (j == 3);
3015 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3016 return r;
3017 }
3018 } else {
3019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3020 alu.op = ALU_OP2_MULLO_UINT;
3021
3022 alu.dst.sel = tmp0;
3023 alu.dst.chan = 2;
3024 alu.dst.write = 1;
3025
3026 alu.src[0].sel = tmp0;
3027 alu.src[0].chan = 0;
3028 if (signed_op) {
3029 alu.src[1].sel = tmp2;
3030 alu.src[1].chan = 1;
3031 } else {
3032 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3033 }
3034
3035 alu.last = 1;
3036 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3037 return r;
3038 }
3039
3040 /* 3. tmp0.w = -tmp0.z */
3041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3042 alu.op = ALU_OP2_SUB_INT;
3043
3044 alu.dst.sel = tmp0;
3045 alu.dst.chan = 3;
3046 alu.dst.write = 1;
3047
3048 alu.src[0].sel = V_SQ_ALU_SRC_0;
3049 alu.src[1].sel = tmp0;
3050 alu.src[1].chan = 2;
3051
3052 alu.last = 1;
3053 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3054 return r;
3055
3056 /* 4. tmp0.y = hi (tmp0.x * src2) */
3057 if (ctx->bc->chip_class == CAYMAN) {
3058 for (j = 0 ; j < 4; j++) {
3059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3060 alu.op = ALU_OP2_MULHI_UINT;
3061
3062 alu.dst.sel = tmp0;
3063 alu.dst.chan = j;
3064 alu.dst.write = (j == 1);
3065
3066 alu.src[0].sel = tmp0;
3067 alu.src[0].chan = 0;
3068
3069 if (signed_op) {
3070 alu.src[1].sel = tmp2;
3071 alu.src[1].chan = 1;
3072 } else {
3073 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3074 }
3075 alu.last = (j == 3);
3076 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3077 return r;
3078 }
3079 } else {
3080 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3081 alu.op = ALU_OP2_MULHI_UINT;
3082
3083 alu.dst.sel = tmp0;
3084 alu.dst.chan = 1;
3085 alu.dst.write = 1;
3086
3087 alu.src[0].sel = tmp0;
3088 alu.src[0].chan = 0;
3089
3090 if (signed_op) {
3091 alu.src[1].sel = tmp2;
3092 alu.src[1].chan = 1;
3093 } else {
3094 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3095 }
3096
3097 alu.last = 1;
3098 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3099 return r;
3100 }
3101
3102 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
3103 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3104 alu.op = ALU_OP3_CNDE_INT;
3105 alu.is_op3 = 1;
3106
3107 alu.dst.sel = tmp0;
3108 alu.dst.chan = 2;
3109 alu.dst.write = 1;
3110
3111 alu.src[0].sel = tmp0;
3112 alu.src[0].chan = 1;
3113 alu.src[1].sel = tmp0;
3114 alu.src[1].chan = 3;
3115 alu.src[2].sel = tmp0;
3116 alu.src[2].chan = 2;
3117
3118 alu.last = 1;
3119 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3120 return r;
3121
3122 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
3123 if (ctx->bc->chip_class == CAYMAN) {
3124 for (j = 0 ; j < 4; j++) {
3125 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3126 alu.op = ALU_OP2_MULHI_UINT;
3127
3128 alu.dst.sel = tmp0;
3129 alu.dst.chan = j;
3130 alu.dst.write = (j == 3);
3131
3132 alu.src[0].sel = tmp0;
3133 alu.src[0].chan = 2;
3134
3135 alu.src[1].sel = tmp0;
3136 alu.src[1].chan = 0;
3137
3138 alu.last = (j == 3);
3139 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3140 return r;
3141 }
3142 } else {
3143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3144 alu.op = ALU_OP2_MULHI_UINT;
3145
3146 alu.dst.sel = tmp0;
3147 alu.dst.chan = 3;
3148 alu.dst.write = 1;
3149
3150 alu.src[0].sel = tmp0;
3151 alu.src[0].chan = 2;
3152
3153 alu.src[1].sel = tmp0;
3154 alu.src[1].chan = 0;
3155
3156 alu.last = 1;
3157 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3158 return r;
3159 }
3160
3161 /* 7. tmp1.x = tmp0.x - tmp0.w */
3162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3163 alu.op = ALU_OP2_SUB_INT;
3164
3165 alu.dst.sel = tmp1;
3166 alu.dst.chan = 0;
3167 alu.dst.write = 1;
3168
3169 alu.src[0].sel = tmp0;
3170 alu.src[0].chan = 0;
3171 alu.src[1].sel = tmp0;
3172 alu.src[1].chan = 3;
3173
3174 alu.last = 1;
3175 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3176 return r;
3177
3178 /* 8. tmp1.y = tmp0.x + tmp0.w */
3179 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3180 alu.op = ALU_OP2_ADD_INT;
3181
3182 alu.dst.sel = tmp1;
3183 alu.dst.chan = 1;
3184 alu.dst.write = 1;
3185
3186 alu.src[0].sel = tmp0;
3187 alu.src[0].chan = 0;
3188 alu.src[1].sel = tmp0;
3189 alu.src[1].chan = 3;
3190
3191 alu.last = 1;
3192 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3193 return r;
3194
3195 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3196 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3197 alu.op = ALU_OP3_CNDE_INT;
3198 alu.is_op3 = 1;
3199
3200 alu.dst.sel = tmp0;
3201 alu.dst.chan = 0;
3202 alu.dst.write = 1;
3203
3204 alu.src[0].sel = tmp0;
3205 alu.src[0].chan = 1;
3206 alu.src[1].sel = tmp1;
3207 alu.src[1].chan = 1;
3208 alu.src[2].sel = tmp1;
3209 alu.src[2].chan = 0;
3210
3211 alu.last = 1;
3212 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3213 return r;
3214
3215 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3216 if (ctx->bc->chip_class == CAYMAN) {
3217 for (j = 0 ; j < 4; j++) {
3218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3219 alu.op = ALU_OP2_MULHI_UINT;
3220
3221 alu.dst.sel = tmp0;
3222 alu.dst.chan = j;
3223 alu.dst.write = (j == 2);
3224
3225 alu.src[0].sel = tmp0;
3226 alu.src[0].chan = 0;
3227
3228 if (signed_op) {
3229 alu.src[1].sel = tmp2;
3230 alu.src[1].chan = 0;
3231 } else {
3232 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3233 }
3234
3235 alu.last = (j == 3);
3236 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3237 return r;
3238 }
3239 } else {
3240 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3241 alu.op = ALU_OP2_MULHI_UINT;
3242
3243 alu.dst.sel = tmp0;
3244 alu.dst.chan = 2;
3245 alu.dst.write = 1;
3246
3247 alu.src[0].sel = tmp0;
3248 alu.src[0].chan = 0;
3249
3250 if (signed_op) {
3251 alu.src[1].sel = tmp2;
3252 alu.src[1].chan = 0;
3253 } else {
3254 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3255 }
3256
3257 alu.last = 1;
3258 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3259 return r;
3260 }
3261
3262 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3263 if (ctx->bc->chip_class == CAYMAN) {
3264 for (j = 0 ; j < 4; j++) {
3265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3266 alu.op = ALU_OP2_MULLO_UINT;
3267
3268 alu.dst.sel = tmp0;
3269 alu.dst.chan = j;
3270 alu.dst.write = (j == 1);
3271
3272 if (signed_op) {
3273 alu.src[0].sel = tmp2;
3274 alu.src[0].chan = 1;
3275 } else {
3276 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3277 }
3278
3279 alu.src[1].sel = tmp0;
3280 alu.src[1].chan = 2;
3281
3282 alu.last = (j == 3);
3283 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3284 return r;
3285 }
3286 } else {
3287 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3288 alu.op = ALU_OP2_MULLO_UINT;
3289
3290 alu.dst.sel = tmp0;
3291 alu.dst.chan = 1;
3292 alu.dst.write = 1;
3293
3294 if (signed_op) {
3295 alu.src[0].sel = tmp2;
3296 alu.src[0].chan = 1;
3297 } else {
3298 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3299 }
3300
3301 alu.src[1].sel = tmp0;
3302 alu.src[1].chan = 2;
3303
3304 alu.last = 1;
3305 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3306 return r;
3307 }
3308
3309 /* 12. tmp0.w = src1 - tmp0.y = r */
3310 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3311 alu.op = ALU_OP2_SUB_INT;
3312
3313 alu.dst.sel = tmp0;
3314 alu.dst.chan = 3;
3315 alu.dst.write = 1;
3316
3317 if (signed_op) {
3318 alu.src[0].sel = tmp2;
3319 alu.src[0].chan = 0;
3320 } else {
3321 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3322 }
3323
3324 alu.src[1].sel = tmp0;
3325 alu.src[1].chan = 1;
3326
3327 alu.last = 1;
3328 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3329 return r;
3330
3331 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3332 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3333 alu.op = ALU_OP2_SETGE_UINT;
3334
3335 alu.dst.sel = tmp1;
3336 alu.dst.chan = 0;
3337 alu.dst.write = 1;
3338
3339 alu.src[0].sel = tmp0;
3340 alu.src[0].chan = 3;
3341 if (signed_op) {
3342 alu.src[1].sel = tmp2;
3343 alu.src[1].chan = 1;
3344 } else {
3345 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3346 }
3347
3348 alu.last = 1;
3349 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3350 return r;
3351
3352 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3353 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3354 alu.op = ALU_OP2_SETGE_UINT;
3355
3356 alu.dst.sel = tmp1;
3357 alu.dst.chan = 1;
3358 alu.dst.write = 1;
3359
3360 if (signed_op) {
3361 alu.src[0].sel = tmp2;
3362 alu.src[0].chan = 0;
3363 } else {
3364 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3365 }
3366
3367 alu.src[1].sel = tmp0;
3368 alu.src[1].chan = 1;
3369
3370 alu.last = 1;
3371 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3372 return r;
3373
3374 if (mod) { /* UMOD */
3375
3376 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3378 alu.op = ALU_OP2_SUB_INT;
3379
3380 alu.dst.sel = tmp1;
3381 alu.dst.chan = 2;
3382 alu.dst.write = 1;
3383
3384 alu.src[0].sel = tmp0;
3385 alu.src[0].chan = 3;
3386
3387 if (signed_op) {
3388 alu.src[1].sel = tmp2;
3389 alu.src[1].chan = 1;
3390 } else {
3391 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3392 }
3393
3394 alu.last = 1;
3395 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3396 return r;
3397
3398 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3399 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3400 alu.op = ALU_OP2_ADD_INT;
3401
3402 alu.dst.sel = tmp1;
3403 alu.dst.chan = 3;
3404 alu.dst.write = 1;
3405
3406 alu.src[0].sel = tmp0;
3407 alu.src[0].chan = 3;
3408 if (signed_op) {
3409 alu.src[1].sel = tmp2;
3410 alu.src[1].chan = 1;
3411 } else {
3412 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3413 }
3414
3415 alu.last = 1;
3416 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3417 return r;
3418
3419 } else { /* UDIV */
3420
3421 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3422 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3423 alu.op = ALU_OP2_ADD_INT;
3424
3425 alu.dst.sel = tmp1;
3426 alu.dst.chan = 2;
3427 alu.dst.write = 1;
3428
3429 alu.src[0].sel = tmp0;
3430 alu.src[0].chan = 2;
3431 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3432
3433 alu.last = 1;
3434 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3435 return r;
3436
3437 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3438 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3439 alu.op = ALU_OP2_ADD_INT;
3440
3441 alu.dst.sel = tmp1;
3442 alu.dst.chan = 3;
3443 alu.dst.write = 1;
3444
3445 alu.src[0].sel = tmp0;
3446 alu.src[0].chan = 2;
3447 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3448
3449 alu.last = 1;
3450 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3451 return r;
3452
3453 }
3454
3455 /* 17. tmp1.x = tmp1.x & tmp1.y */
3456 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3457 alu.op = ALU_OP2_AND_INT;
3458
3459 alu.dst.sel = tmp1;
3460 alu.dst.chan = 0;
3461 alu.dst.write = 1;
3462
3463 alu.src[0].sel = tmp1;
3464 alu.src[0].chan = 0;
3465 alu.src[1].sel = tmp1;
3466 alu.src[1].chan = 1;
3467
3468 alu.last = 1;
3469 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3470 return r;
3471
3472 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3473 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3475 alu.op = ALU_OP3_CNDE_INT;
3476 alu.is_op3 = 1;
3477
3478 alu.dst.sel = tmp0;
3479 alu.dst.chan = 2;
3480 alu.dst.write = 1;
3481
3482 alu.src[0].sel = tmp1;
3483 alu.src[0].chan = 0;
3484 alu.src[1].sel = tmp0;
3485 alu.src[1].chan = mod ? 3 : 2;
3486 alu.src[2].sel = tmp1;
3487 alu.src[2].chan = 2;
3488
3489 alu.last = 1;
3490 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3491 return r;
3492
3493 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3495 alu.op = ALU_OP3_CNDE_INT;
3496 alu.is_op3 = 1;
3497
3498 if (signed_op) {
3499 alu.dst.sel = tmp0;
3500 alu.dst.chan = 2;
3501 alu.dst.write = 1;
3502 } else {
3503 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3504 }
3505
3506 alu.src[0].sel = tmp1;
3507 alu.src[0].chan = 1;
3508 alu.src[1].sel = tmp1;
3509 alu.src[1].chan = 3;
3510 alu.src[2].sel = tmp0;
3511 alu.src[2].chan = 2;
3512
3513 alu.last = 1;
3514 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3515 return r;
3516
3517 if (signed_op) {
3518
3519 /* fix the sign of the result */
3520
3521 if (mod) {
3522
3523 /* tmp0.x = -tmp0.z */
3524 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3525 alu.op = ALU_OP2_SUB_INT;
3526
3527 alu.dst.sel = tmp0;
3528 alu.dst.chan = 0;
3529 alu.dst.write = 1;
3530
3531 alu.src[0].sel = V_SQ_ALU_SRC_0;
3532 alu.src[1].sel = tmp0;
3533 alu.src[1].chan = 2;
3534
3535 alu.last = 1;
3536 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3537 return r;
3538
3539 /* sign of the remainder is the same as the sign of src0 */
3540 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3541 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3542 alu.op = ALU_OP3_CNDGE_INT;
3543 alu.is_op3 = 1;
3544
3545 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3546
3547 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3548 alu.src[1].sel = tmp0;
3549 alu.src[1].chan = 2;
3550 alu.src[2].sel = tmp0;
3551 alu.src[2].chan = 0;
3552
3553 alu.last = 1;
3554 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3555 return r;
3556
3557 } else {
3558
3559 /* tmp0.x = -tmp0.z */
3560 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3561 alu.op = ALU_OP2_SUB_INT;
3562
3563 alu.dst.sel = tmp0;
3564 alu.dst.chan = 0;
3565 alu.dst.write = 1;
3566
3567 alu.src[0].sel = V_SQ_ALU_SRC_0;
3568 alu.src[1].sel = tmp0;
3569 alu.src[1].chan = 2;
3570
3571 alu.last = 1;
3572 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3573 return r;
3574
3575 /* fix the quotient sign (same as the sign of src0*src1) */
3576 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3577 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3578 alu.op = ALU_OP3_CNDGE_INT;
3579 alu.is_op3 = 1;
3580
3581 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3582
3583 alu.src[0].sel = tmp2;
3584 alu.src[0].chan = 2;
3585 alu.src[1].sel = tmp0;
3586 alu.src[1].chan = 2;
3587 alu.src[2].sel = tmp0;
3588 alu.src[2].chan = 0;
3589
3590 alu.last = 1;
3591 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3592 return r;
3593 }
3594 }
3595 }
3596 return 0;
3597 }
3598
3599 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3600 {
3601 return tgsi_divmod(ctx, 0, 0);
3602 }
3603
3604 static int tgsi_umod(struct r600_shader_ctx *ctx)
3605 {
3606 return tgsi_divmod(ctx, 1, 0);
3607 }
3608
3609 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3610 {
3611 return tgsi_divmod(ctx, 0, 1);
3612 }
3613
3614 static int tgsi_imod(struct r600_shader_ctx *ctx)
3615 {
3616 return tgsi_divmod(ctx, 1, 1);
3617 }
3618
3619
3620 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3621 {
3622 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3623 struct r600_bytecode_alu alu;
3624 int i, r;
3625 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3626 int last_inst = tgsi_last_instruction(write_mask);
3627
3628 for (i = 0; i < 4; i++) {
3629 if (!(write_mask & (1<<i)))
3630 continue;
3631
3632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3633 alu.op = ALU_OP1_TRUNC;
3634
3635 alu.dst.sel = ctx->temp_reg;
3636 alu.dst.chan = i;
3637 alu.dst.write = 1;
3638
3639 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3640 if (i == last_inst)
3641 alu.last = 1;
3642 r = r600_bytecode_add_alu(ctx->bc, &alu);
3643 if (r)
3644 return r;
3645 }
3646
3647 for (i = 0; i < 4; i++) {
3648 if (!(write_mask & (1<<i)))
3649 continue;
3650
3651 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3652 alu.op = ctx->inst_info->op;
3653
3654 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3655
3656 alu.src[0].sel = ctx->temp_reg;
3657 alu.src[0].chan = i;
3658
3659 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3660 alu.last = 1;
3661 r = r600_bytecode_add_alu(ctx->bc, &alu);
3662 if (r)
3663 return r;
3664 }
3665
3666 return 0;
3667 }
3668
3669 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3670 {
3671 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3672 struct r600_bytecode_alu alu;
3673 int i, r;
3674 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3675 int last_inst = tgsi_last_instruction(write_mask);
3676
3677 /* tmp = -src */
3678 for (i = 0; i < 4; i++) {
3679 if (!(write_mask & (1<<i)))
3680 continue;
3681
3682 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3683 alu.op = ALU_OP2_SUB_INT;
3684
3685 alu.dst.sel = ctx->temp_reg;
3686 alu.dst.chan = i;
3687 alu.dst.write = 1;
3688
3689 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3690 alu.src[0].sel = V_SQ_ALU_SRC_0;
3691
3692 if (i == last_inst)
3693 alu.last = 1;
3694 r = r600_bytecode_add_alu(ctx->bc, &alu);
3695 if (r)
3696 return r;
3697 }
3698
3699 /* dst = (src >= 0 ? src : tmp) */
3700 for (i = 0; i < 4; i++) {
3701 if (!(write_mask & (1<<i)))
3702 continue;
3703
3704 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3705 alu.op = ALU_OP3_CNDGE_INT;
3706 alu.is_op3 = 1;
3707 alu.dst.write = 1;
3708
3709 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3710
3711 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3712 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3713 alu.src[2].sel = ctx->temp_reg;
3714 alu.src[2].chan = i;
3715
3716 if (i == last_inst)
3717 alu.last = 1;
3718 r = r600_bytecode_add_alu(ctx->bc, &alu);
3719 if (r)
3720 return r;
3721 }
3722 return 0;
3723 }
3724
3725 static int tgsi_issg(struct r600_shader_ctx *ctx)
3726 {
3727 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3728 struct r600_bytecode_alu alu;
3729 int i, r;
3730 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3731 int last_inst = tgsi_last_instruction(write_mask);
3732
3733 /* tmp = (src >= 0 ? src : -1) */
3734 for (i = 0; i < 4; i++) {
3735 if (!(write_mask & (1<<i)))
3736 continue;
3737
3738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3739 alu.op = ALU_OP3_CNDGE_INT;
3740 alu.is_op3 = 1;
3741
3742 alu.dst.sel = ctx->temp_reg;
3743 alu.dst.chan = i;
3744 alu.dst.write = 1;
3745
3746 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3747 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3748 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3749
3750 if (i == last_inst)
3751 alu.last = 1;
3752 r = r600_bytecode_add_alu(ctx->bc, &alu);
3753 if (r)
3754 return r;
3755 }
3756
3757 /* dst = (tmp > 0 ? 1 : tmp) */
3758 for (i = 0; i < 4; i++) {
3759 if (!(write_mask & (1<<i)))
3760 continue;
3761
3762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3763 alu.op = ALU_OP3_CNDGT_INT;
3764 alu.is_op3 = 1;
3765 alu.dst.write = 1;
3766
3767 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3768
3769 alu.src[0].sel = ctx->temp_reg;
3770 alu.src[0].chan = i;
3771
3772 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3773
3774 alu.src[2].sel = ctx->temp_reg;
3775 alu.src[2].chan = i;
3776
3777 if (i == last_inst)
3778 alu.last = 1;
3779 r = r600_bytecode_add_alu(ctx->bc, &alu);
3780 if (r)
3781 return r;
3782 }
3783 return 0;
3784 }
3785
3786
3787
3788 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3789 {
3790 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3791 struct r600_bytecode_alu alu;
3792 int i, r;
3793
3794 /* tmp = (src > 0 ? 1 : src) */
3795 for (i = 0; i < 4; i++) {
3796 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3797 alu.op = ALU_OP3_CNDGT;
3798 alu.is_op3 = 1;
3799
3800 alu.dst.sel = ctx->temp_reg;
3801 alu.dst.chan = i;
3802
3803 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3804 alu.src[1].sel = V_SQ_ALU_SRC_1;
3805 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3806
3807 if (i == 3)
3808 alu.last = 1;
3809 r = r600_bytecode_add_alu(ctx->bc, &alu);
3810 if (r)
3811 return r;
3812 }
3813
3814 /* dst = (-tmp > 0 ? -1 : tmp) */
3815 for (i = 0; i < 4; i++) {
3816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3817 alu.op = ALU_OP3_CNDGT;
3818 alu.is_op3 = 1;
3819 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3820
3821 alu.src[0].sel = ctx->temp_reg;
3822 alu.src[0].chan = i;
3823 alu.src[0].neg = 1;
3824
3825 alu.src[1].sel = V_SQ_ALU_SRC_1;
3826 alu.src[1].neg = 1;
3827
3828 alu.src[2].sel = ctx->temp_reg;
3829 alu.src[2].chan = i;
3830
3831 if (i == 3)
3832 alu.last = 1;
3833 r = r600_bytecode_add_alu(ctx->bc, &alu);
3834 if (r)
3835 return r;
3836 }
3837 return 0;
3838 }
3839
3840 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3841 {
3842 struct r600_bytecode_alu alu;
3843 int i, r;
3844
3845 for (i = 0; i < 4; i++) {
3846 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3847 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3848 alu.op = ALU_OP0_NOP;
3849 alu.dst.chan = i;
3850 } else {
3851 alu.op = ALU_OP1_MOV;
3852 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3853 alu.src[0].sel = ctx->temp_reg;
3854 alu.src[0].chan = i;
3855 }
3856 if (i == 3) {
3857 alu.last = 1;
3858 }
3859 r = r600_bytecode_add_alu(ctx->bc, &alu);
3860 if (r)
3861 return r;
3862 }
3863 return 0;
3864 }
3865
3866 static int tgsi_op3(struct r600_shader_ctx *ctx)
3867 {
3868 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3869 struct r600_bytecode_alu alu;
3870 int i, j, r;
3871 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3872
3873 for (i = 0; i < lasti + 1; i++) {
3874 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3875 continue;
3876
3877 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3878 alu.op = ctx->inst_info->op;
3879 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3880 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3881 }
3882
3883 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3884 alu.dst.chan = i;
3885 alu.dst.write = 1;
3886 alu.is_op3 = 1;
3887 if (i == lasti) {
3888 alu.last = 1;
3889 }
3890 r = r600_bytecode_add_alu(ctx->bc, &alu);
3891 if (r)
3892 return r;
3893 }
3894 return 0;
3895 }
3896
3897 static int tgsi_dp(struct r600_shader_ctx *ctx)
3898 {
3899 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3900 struct r600_bytecode_alu alu;
3901 int i, j, r;
3902
3903 for (i = 0; i < 4; i++) {
3904 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3905 alu.op = ctx->inst_info->op;
3906 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3907 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3908 }
3909
3910 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3911 alu.dst.chan = i;
3912 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3913 /* handle some special cases */
3914 switch (ctx->inst_info->tgsi_opcode) {
3915 case TGSI_OPCODE_DP2:
3916 if (i > 1) {
3917 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3918 alu.src[0].chan = alu.src[1].chan = 0;
3919 }
3920 break;
3921 case TGSI_OPCODE_DP3:
3922 if (i > 2) {
3923 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3924 alu.src[0].chan = alu.src[1].chan = 0;
3925 }
3926 break;
3927 case TGSI_OPCODE_DPH:
3928 if (i == 3) {
3929 alu.src[0].sel = V_SQ_ALU_SRC_1;
3930 alu.src[0].chan = 0;
3931 alu.src[0].neg = 0;
3932 }
3933 break;
3934 default:
3935 break;
3936 }
3937 if (i == 3) {
3938 alu.last = 1;
3939 }
3940 r = r600_bytecode_add_alu(ctx->bc, &alu);
3941 if (r)
3942 return r;
3943 }
3944 return 0;
3945 }
3946
3947 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3948 unsigned index)
3949 {
3950 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3951 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3952 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3953 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3954 ctx->src[index].neg || ctx->src[index].abs;
3955 }
3956
3957 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3958 unsigned index)
3959 {
3960 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3961 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3962 }
3963
3964 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
3965 {
3966 struct r600_bytecode_vtx vtx;
3967 struct r600_bytecode_alu alu;
3968 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3969 int src_gpr, r, i;
3970 int id = tgsi_tex_get_src_gpr(ctx, 1);
3971
3972 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3973 if (src_requires_loading) {
3974 for (i = 0; i < 4; i++) {
3975 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3976 alu.op = ALU_OP1_MOV;
3977 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3978 alu.dst.sel = ctx->temp_reg;
3979 alu.dst.chan = i;
3980 if (i == 3)
3981 alu.last = 1;
3982 alu.dst.write = 1;
3983 r = r600_bytecode_add_alu(ctx->bc, &alu);
3984 if (r)
3985 return r;
3986 }
3987 src_gpr = ctx->temp_reg;
3988 }
3989
3990 memset(&vtx, 0, sizeof(vtx));
3991 vtx.op = FETCH_OP_VFETCH;
3992 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
3993 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
3994 vtx.src_gpr = src_gpr;
3995 vtx.mega_fetch_count = 16;
3996 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3997 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
3998 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
3999 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
4000 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
4001 vtx.use_const_fields = 1;
4002 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
4003
4004 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
4005 return r;
4006
4007 if (ctx->bc->chip_class >= EVERGREEN)
4008 return 0;
4009
4010 for (i = 0; i < 4; i++) {
4011 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4012 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4013 continue;
4014
4015 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4016 alu.op = ALU_OP2_AND_INT;
4017
4018 alu.dst.chan = i;
4019 alu.dst.sel = vtx.dst_gpr;
4020 alu.dst.write = 1;
4021
4022 alu.src[0].sel = vtx.dst_gpr;
4023 alu.src[0].chan = i;
4024
4025 alu.src[1].sel = 512 + (id * 2);
4026 alu.src[1].chan = i % 4;
4027 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4028
4029 if (i == lasti)
4030 alu.last = 1;
4031 r = r600_bytecode_add_alu(ctx->bc, &alu);
4032 if (r)
4033 return r;
4034 }
4035
4036 if (inst->Dst[0].Register.WriteMask & 3) {
4037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4038 alu.op = ALU_OP2_OR_INT;
4039
4040 alu.dst.chan = 3;
4041 alu.dst.sel = vtx.dst_gpr;
4042 alu.dst.write = 1;
4043
4044 alu.src[0].sel = vtx.dst_gpr;
4045 alu.src[0].chan = 3;
4046
4047 alu.src[1].sel = 512 + (id * 2) + 1;
4048 alu.src[1].chan = 0;
4049 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4050
4051 alu.last = 1;
4052 r = r600_bytecode_add_alu(ctx->bc, &alu);
4053 if (r)
4054 return r;
4055 }
4056 return 0;
4057 }
4058
4059 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
4060 {
4061 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4062 struct r600_bytecode_alu alu;
4063 int r;
4064 int id = tgsi_tex_get_src_gpr(ctx, 1);
4065
4066 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4067 alu.op = ALU_OP1_MOV;
4068
4069 if (ctx->bc->chip_class >= EVERGREEN) {
4070 alu.src[0].sel = 512 + (id / 4);
4071 alu.src[0].chan = id % 4;
4072 } else {
4073 /* r600 we have them at channel 2 of the second dword */
4074 alu.src[0].sel = 512 + (id * 2) + 1;
4075 alu.src[0].chan = 1;
4076 }
4077 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4078 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4079 alu.last = 1;
4080 r = r600_bytecode_add_alu(ctx->bc, &alu);
4081 if (r)
4082 return r;
4083 return 0;
4084 }
4085
4086 static int tgsi_tex(struct r600_shader_ctx *ctx)
4087 {
4088 static float one_point_five = 1.5f;
4089 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4090 struct r600_bytecode_tex tex;
4091 struct r600_bytecode_alu alu;
4092 unsigned src_gpr;
4093 int r, i, j;
4094 int opcode;
4095 bool read_compressed_msaa = ctx->bc->msaa_texture_mode == MSAA_TEXTURE_COMPRESSED &&
4096 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
4097 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
4098 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
4099 /* Texture fetch instructions can only use gprs as source.
4100 * Also they cannot negate the source or take the absolute value */
4101 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
4102 tgsi_tex_src_requires_loading(ctx, 0)) ||
4103 read_compressed_msaa;
4104 boolean src_loaded = FALSE;
4105 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
4106 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
4107 boolean has_txq_cube_array_z = false;
4108
4109 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
4110 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4111 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
4112 if (inst->Dst[0].Register.WriteMask & 4) {
4113 ctx->shader->has_txq_cube_array_z_comp = true;
4114 has_txq_cube_array_z = true;
4115 }
4116
4117 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
4118 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4119 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4120 sampler_src_reg = 2;
4121
4122 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4123
4124 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
4125 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
4126 ctx->shader->uses_tex_buffers = true;
4127 return r600_do_buffer_txq(ctx);
4128 }
4129 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4130 if (ctx->bc->chip_class < EVERGREEN)
4131 ctx->shader->uses_tex_buffers = true;
4132 return do_vtx_fetch_inst(ctx, src_requires_loading);
4133 }
4134 }
4135
4136 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4137 /* get offset values */
4138 if (inst->Texture.NumOffsets) {
4139 assert(inst->Texture.NumOffsets == 1);
4140
4141 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
4142 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
4143 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
4144 }
4145 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
4146 /* TGSI moves the sampler to src reg 3 for TXD */
4147 sampler_src_reg = 3;
4148
4149 for (i = 1; i < 3; i++) {
4150 /* set gradients h/v */
4151 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4152 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
4153 FETCH_OP_SET_GRADIENTS_V;
4154 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4155 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4156
4157 if (tgsi_tex_src_requires_loading(ctx, i)) {
4158 tex.src_gpr = r600_get_temp(ctx);
4159 tex.src_sel_x = 0;
4160 tex.src_sel_y = 1;
4161 tex.src_sel_z = 2;
4162 tex.src_sel_w = 3;
4163
4164 for (j = 0; j < 4; j++) {
4165 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4166 alu.op = ALU_OP1_MOV;
4167 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
4168 alu.dst.sel = tex.src_gpr;
4169 alu.dst.chan = j;
4170 if (j == 3)
4171 alu.last = 1;
4172 alu.dst.write = 1;
4173 r = r600_bytecode_add_alu(ctx->bc, &alu);
4174 if (r)
4175 return r;
4176 }
4177
4178 } else {
4179 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
4180 tex.src_sel_x = ctx->src[i].swizzle[0];
4181 tex.src_sel_y = ctx->src[i].swizzle[1];
4182 tex.src_sel_z = ctx->src[i].swizzle[2];
4183 tex.src_sel_w = ctx->src[i].swizzle[3];
4184 tex.src_rel = ctx->src[i].rel;
4185 }
4186 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
4187 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4188 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
4189 tex.coord_type_x = 1;
4190 tex.coord_type_y = 1;
4191 tex.coord_type_z = 1;
4192 tex.coord_type_w = 1;
4193 }
4194 r = r600_bytecode_add_tex(ctx->bc, &tex);
4195 if (r)
4196 return r;
4197 }
4198 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
4199 int out_chan;
4200 /* Add perspective divide */
4201 if (ctx->bc->chip_class == CAYMAN) {
4202 out_chan = 2;
4203 for (i = 0; i < 3; i++) {
4204 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4205 alu.op = ALU_OP1_RECIP_IEEE;
4206 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4207
4208 alu.dst.sel = ctx->temp_reg;
4209 alu.dst.chan = i;
4210 if (i == 2)
4211 alu.last = 1;
4212 if (out_chan == i)
4213 alu.dst.write = 1;
4214 r = r600_bytecode_add_alu(ctx->bc, &alu);
4215 if (r)
4216 return r;
4217 }
4218
4219 } else {
4220 out_chan = 3;
4221 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4222 alu.op = ALU_OP1_RECIP_IEEE;
4223 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4224
4225 alu.dst.sel = ctx->temp_reg;
4226 alu.dst.chan = out_chan;
4227 alu.last = 1;
4228 alu.dst.write = 1;
4229 r = r600_bytecode_add_alu(ctx->bc, &alu);
4230 if (r)
4231 return r;
4232 }
4233
4234 for (i = 0; i < 3; i++) {
4235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4236 alu.op = ALU_OP2_MUL;
4237 alu.src[0].sel = ctx->temp_reg;
4238 alu.src[0].chan = out_chan;
4239 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4240 alu.dst.sel = ctx->temp_reg;
4241 alu.dst.chan = i;
4242 alu.dst.write = 1;
4243 r = r600_bytecode_add_alu(ctx->bc, &alu);
4244 if (r)
4245 return r;
4246 }
4247 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4248 alu.op = ALU_OP1_MOV;
4249 alu.src[0].sel = V_SQ_ALU_SRC_1;
4250 alu.src[0].chan = 0;
4251 alu.dst.sel = ctx->temp_reg;
4252 alu.dst.chan = 3;
4253 alu.last = 1;
4254 alu.dst.write = 1;
4255 r = r600_bytecode_add_alu(ctx->bc, &alu);
4256 if (r)
4257 return r;
4258 src_loaded = TRUE;
4259 src_gpr = ctx->temp_reg;
4260 }
4261
4262 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4263 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4264 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4265 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4266 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
4267 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
4268
4269 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
4270 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
4271
4272 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
4273 for (i = 0; i < 4; i++) {
4274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4275 alu.op = ALU_OP2_CUBE;
4276 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4277 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
4278 alu.dst.sel = ctx->temp_reg;
4279 alu.dst.chan = i;
4280 if (i == 3)
4281 alu.last = 1;
4282 alu.dst.write = 1;
4283 r = r600_bytecode_add_alu(ctx->bc, &alu);
4284 if (r)
4285 return r;
4286 }
4287
4288 /* tmp1.z = RCP_e(|tmp1.z|) */
4289 if (ctx->bc->chip_class == CAYMAN) {
4290 for (i = 0; i < 3; i++) {
4291 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4292 alu.op = ALU_OP1_RECIP_IEEE;
4293 alu.src[0].sel = ctx->temp_reg;
4294 alu.src[0].chan = 2;
4295 alu.src[0].abs = 1;
4296 alu.dst.sel = ctx->temp_reg;
4297 alu.dst.chan = i;
4298 if (i == 2)
4299 alu.dst.write = 1;
4300 if (i == 2)
4301 alu.last = 1;
4302 r = r600_bytecode_add_alu(ctx->bc, &alu);
4303 if (r)
4304 return r;
4305 }
4306 } else {
4307 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4308 alu.op = ALU_OP1_RECIP_IEEE;
4309 alu.src[0].sel = ctx->temp_reg;
4310 alu.src[0].chan = 2;
4311 alu.src[0].abs = 1;
4312 alu.dst.sel = ctx->temp_reg;
4313 alu.dst.chan = 2;
4314 alu.dst.write = 1;
4315 alu.last = 1;
4316 r = r600_bytecode_add_alu(ctx->bc, &alu);
4317 if (r)
4318 return r;
4319 }
4320
4321 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4322 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4323 * muladd has no writemask, have to use another temp
4324 */
4325 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4326 alu.op = ALU_OP3_MULADD;
4327 alu.is_op3 = 1;
4328
4329 alu.src[0].sel = ctx->temp_reg;
4330 alu.src[0].chan = 0;
4331 alu.src[1].sel = ctx->temp_reg;
4332 alu.src[1].chan = 2;
4333
4334 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4335 alu.src[2].chan = 0;
4336 alu.src[2].value = *(uint32_t *)&one_point_five;
4337
4338 alu.dst.sel = ctx->temp_reg;
4339 alu.dst.chan = 0;
4340 alu.dst.write = 1;
4341
4342 r = r600_bytecode_add_alu(ctx->bc, &alu);
4343 if (r)
4344 return r;
4345
4346 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4347 alu.op = ALU_OP3_MULADD;
4348 alu.is_op3 = 1;
4349
4350 alu.src[0].sel = ctx->temp_reg;
4351 alu.src[0].chan = 1;
4352 alu.src[1].sel = ctx->temp_reg;
4353 alu.src[1].chan = 2;
4354
4355 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4356 alu.src[2].chan = 0;
4357 alu.src[2].value = *(uint32_t *)&one_point_five;
4358
4359 alu.dst.sel = ctx->temp_reg;
4360 alu.dst.chan = 1;
4361 alu.dst.write = 1;
4362
4363 alu.last = 1;
4364 r = r600_bytecode_add_alu(ctx->bc, &alu);
4365 if (r)
4366 return r;
4367 /* write initial compare value into Z component
4368 - W src 0 for shadow cube
4369 - X src 1 for shadow cube array */
4370 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4371 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4372 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4373 alu.op = ALU_OP1_MOV;
4374 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4375 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4376 else
4377 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4378 alu.dst.sel = ctx->temp_reg;
4379 alu.dst.chan = 2;
4380 alu.dst.write = 1;
4381 alu.last = 1;
4382 r = r600_bytecode_add_alu(ctx->bc, &alu);
4383 if (r)
4384 return r;
4385 }
4386
4387 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4388 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4389 if (ctx->bc->chip_class >= EVERGREEN) {
4390 int mytmp = r600_get_temp(ctx);
4391 static const float eight = 8.0f;
4392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4393 alu.op = ALU_OP1_MOV;
4394 alu.src[0].sel = ctx->temp_reg;
4395 alu.src[0].chan = 3;
4396 alu.dst.sel = mytmp;
4397 alu.dst.chan = 0;
4398 alu.dst.write = 1;
4399 alu.last = 1;
4400 r = r600_bytecode_add_alu(ctx->bc, &alu);
4401 if (r)
4402 return r;
4403
4404 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4405 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4406 alu.op = ALU_OP3_MULADD;
4407 alu.is_op3 = 1;
4408 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4409 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4410 alu.src[1].chan = 0;
4411 alu.src[1].value = *(uint32_t *)&eight;
4412 alu.src[2].sel = mytmp;
4413 alu.src[2].chan = 0;
4414 alu.dst.sel = ctx->temp_reg;
4415 alu.dst.chan = 3;
4416 alu.dst.write = 1;
4417 alu.last = 1;
4418 r = r600_bytecode_add_alu(ctx->bc, &alu);
4419 if (r)
4420 return r;
4421 } else if (ctx->bc->chip_class < EVERGREEN) {
4422 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4423 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4424 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4425 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4426 tex.src_gpr = r600_get_temp(ctx);
4427 tex.src_sel_x = 0;
4428 tex.src_sel_y = 0;
4429 tex.src_sel_z = 0;
4430 tex.src_sel_w = 0;
4431 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4432 tex.coord_type_x = 1;
4433 tex.coord_type_y = 1;
4434 tex.coord_type_z = 1;
4435 tex.coord_type_w = 1;
4436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4437 alu.op = ALU_OP1_MOV;
4438 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4439 alu.dst.sel = tex.src_gpr;
4440 alu.dst.chan = 0;
4441 alu.last = 1;
4442 alu.dst.write = 1;
4443 r = r600_bytecode_add_alu(ctx->bc, &alu);
4444 if (r)
4445 return r;
4446
4447 r = r600_bytecode_add_tex(ctx->bc, &tex);
4448 if (r)
4449 return r;
4450 }
4451
4452 }
4453
4454 /* for cube forms of lod and bias we need to route things */
4455 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4456 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4457 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4458 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4460 alu.op = ALU_OP1_MOV;
4461 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4462 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4463 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4464 else
4465 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4466 alu.dst.sel = ctx->temp_reg;
4467 alu.dst.chan = 2;
4468 alu.last = 1;
4469 alu.dst.write = 1;
4470 r = r600_bytecode_add_alu(ctx->bc, &alu);
4471 if (r)
4472 return r;
4473 }
4474
4475 src_loaded = TRUE;
4476 src_gpr = ctx->temp_reg;
4477 }
4478
4479 if (src_requires_loading && !src_loaded) {
4480 for (i = 0; i < 4; i++) {
4481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4482 alu.op = ALU_OP1_MOV;
4483 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4484 alu.dst.sel = ctx->temp_reg;
4485 alu.dst.chan = i;
4486 if (i == 3)
4487 alu.last = 1;
4488 alu.dst.write = 1;
4489 r = r600_bytecode_add_alu(ctx->bc, &alu);
4490 if (r)
4491 return r;
4492 }
4493 src_loaded = TRUE;
4494 src_gpr = ctx->temp_reg;
4495 }
4496
4497 /* Obtain the sample index for reading a compressed MSAA color texture.
4498 * To read the FMASK, we use the ldfptr instruction, which tells us
4499 * where the samples are stored.
4500 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4501 * which is the identity mapping. Each nibble says which physical sample
4502 * should be fetched to get that sample.
4503 *
4504 * Assume src.z contains the sample index. It should be modified like this:
4505 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4506 * Then fetch the texel with src.
4507 */
4508 if (read_compressed_msaa) {
4509 unsigned sample_chan = inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ? 3 : 4;
4510 unsigned temp = r600_get_temp(ctx);
4511 assert(src_loaded);
4512
4513 /* temp.w = ldfptr() */
4514 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4515 tex.op = FETCH_OP_LD;
4516 tex.inst_mod = 1; /* to indicate this is ldfptr */
4517 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4518 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4519 tex.src_gpr = src_gpr;
4520 tex.dst_gpr = temp;
4521 tex.dst_sel_x = 7; /* mask out these components */
4522 tex.dst_sel_y = 7;
4523 tex.dst_sel_z = 7;
4524 tex.dst_sel_w = 0; /* store X */
4525 tex.src_sel_x = 0;
4526 tex.src_sel_y = 1;
4527 tex.src_sel_z = 2;
4528 tex.src_sel_w = 3;
4529 tex.offset_x = offset_x;
4530 tex.offset_y = offset_y;
4531 tex.offset_z = offset_z;
4532 r = r600_bytecode_add_tex(ctx->bc, &tex);
4533 if (r)
4534 return r;
4535
4536 /* temp.x = sample_index*4 */
4537 if (ctx->bc->chip_class == CAYMAN) {
4538 for (i = 0 ; i < 4; i++) {
4539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4540 alu.op = ctx->inst_info->op;
4541 alu.src[0].sel = src_gpr;
4542 alu.src[0].chan = sample_chan;
4543 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4544 alu.src[1].value = 4;
4545 alu.dst.sel = temp;
4546 alu.dst.chan = i;
4547 alu.dst.write = i == 0;
4548 if (i == 3)
4549 alu.last = 1;
4550 r = r600_bytecode_add_alu(ctx->bc, &alu);
4551 if (r)
4552 return r;
4553 }
4554 } else {
4555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4556 alu.op = ALU_OP2_MULLO_INT;
4557 alu.src[0].sel = src_gpr;
4558 alu.src[0].chan = sample_chan;
4559 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4560 alu.src[1].value = 4;
4561 alu.dst.sel = temp;
4562 alu.dst.chan = 0;
4563 alu.dst.write = 1;
4564 alu.last = 1;
4565 r = r600_bytecode_add_alu(ctx->bc, &alu);
4566 if (r)
4567 return r;
4568 }
4569
4570 /* sample_index = temp.w >> temp.x */
4571 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4572 alu.op = ALU_OP2_LSHR_INT;
4573 alu.src[0].sel = temp;
4574 alu.src[0].chan = 3;
4575 alu.src[1].sel = temp;
4576 alu.src[1].chan = 0;
4577 alu.dst.sel = src_gpr;
4578 alu.dst.chan = sample_chan;
4579 alu.dst.write = 1;
4580 alu.last = 1;
4581 r = r600_bytecode_add_alu(ctx->bc, &alu);
4582 if (r)
4583 return r;
4584
4585 /* sample_index & 0xF */
4586 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4587 alu.op = ALU_OP2_AND_INT;
4588 alu.src[0].sel = src_gpr;
4589 alu.src[0].chan = sample_chan;
4590 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4591 alu.src[1].value = 0xF;
4592 alu.dst.sel = src_gpr;
4593 alu.dst.chan = sample_chan;
4594 alu.dst.write = 1;
4595 alu.last = 1;
4596 r = r600_bytecode_add_alu(ctx->bc, &alu);
4597 if (r)
4598 return r;
4599 #if 0
4600 /* visualize the FMASK */
4601 for (i = 0; i < 4; i++) {
4602 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4603 alu.op = ALU_OP1_INT_TO_FLT;
4604 alu.src[0].sel = src_gpr;
4605 alu.src[0].chan = sample_chan;
4606 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4607 alu.dst.chan = i;
4608 alu.dst.write = 1;
4609 alu.last = 1;
4610 r = r600_bytecode_add_alu(ctx->bc, &alu);
4611 if (r)
4612 return r;
4613 }
4614 return 0;
4615 #endif
4616 }
4617
4618 /* does this shader want a num layers from TXQ for a cube array? */
4619 if (has_txq_cube_array_z) {
4620 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4621
4622 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4623 alu.op = ALU_OP1_MOV;
4624
4625 alu.src[0].sel = 512 + (id / 4);
4626 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4627 alu.src[0].chan = id % 4;
4628 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4629 alu.last = 1;
4630 r = r600_bytecode_add_alu(ctx->bc, &alu);
4631 if (r)
4632 return r;
4633 /* disable writemask from texture instruction */
4634 inst->Dst[0].Register.WriteMask &= ~4;
4635 }
4636
4637 opcode = ctx->inst_info->op;
4638 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4639 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4640 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4641 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4642 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4643 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4644 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4645 switch (opcode) {
4646 case FETCH_OP_SAMPLE:
4647 opcode = FETCH_OP_SAMPLE_C;
4648 break;
4649 case FETCH_OP_SAMPLE_L:
4650 opcode = FETCH_OP_SAMPLE_C_L;
4651 break;
4652 case FETCH_OP_SAMPLE_LB:
4653 opcode = FETCH_OP_SAMPLE_C_LB;
4654 break;
4655 case FETCH_OP_SAMPLE_G:
4656 opcode = FETCH_OP_SAMPLE_C_G;
4657 break;
4658 }
4659 }
4660
4661 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4662 tex.op = opcode;
4663
4664 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4665 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4666 tex.src_gpr = src_gpr;
4667 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4668 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4669 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4670 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4671 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4672
4673 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4674 tex.src_sel_x = 4;
4675 tex.src_sel_y = 4;
4676 tex.src_sel_z = 4;
4677 tex.src_sel_w = 4;
4678 } else if (src_loaded) {
4679 tex.src_sel_x = 0;
4680 tex.src_sel_y = 1;
4681 tex.src_sel_z = 2;
4682 tex.src_sel_w = 3;
4683 } else {
4684 tex.src_sel_x = ctx->src[0].swizzle[0];
4685 tex.src_sel_y = ctx->src[0].swizzle[1];
4686 tex.src_sel_z = ctx->src[0].swizzle[2];
4687 tex.src_sel_w = ctx->src[0].swizzle[3];
4688 tex.src_rel = ctx->src[0].rel;
4689 }
4690
4691 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4692 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4693 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4694 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4695 tex.src_sel_x = 1;
4696 tex.src_sel_y = 0;
4697 tex.src_sel_z = 3;
4698 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4699 }
4700
4701 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4702 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4703 tex.coord_type_x = 1;
4704 tex.coord_type_y = 1;
4705 }
4706 tex.coord_type_z = 1;
4707 tex.coord_type_w = 1;
4708
4709 tex.offset_x = offset_x;
4710 tex.offset_y = offset_y;
4711 tex.offset_z = offset_z;
4712
4713 /* Put the depth for comparison in W.
4714 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4715 * Some instructions expect the depth in Z. */
4716 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4717 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4718 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4719 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4720 opcode != FETCH_OP_SAMPLE_C_L &&
4721 opcode != FETCH_OP_SAMPLE_C_LB) {
4722 tex.src_sel_w = tex.src_sel_z;
4723 }
4724
4725 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4726 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4727 if (opcode == FETCH_OP_SAMPLE_C_L ||
4728 opcode == FETCH_OP_SAMPLE_C_LB) {
4729 /* the array index is read from Y */
4730 tex.coord_type_y = 0;
4731 } else {
4732 /* the array index is read from Z */
4733 tex.coord_type_z = 0;
4734 tex.src_sel_z = tex.src_sel_y;
4735 }
4736 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4737 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4738 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4739 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4740 (ctx->bc->chip_class >= EVERGREEN)))
4741 /* the array index is read from Z */
4742 tex.coord_type_z = 0;
4743
4744 r = r600_bytecode_add_tex(ctx->bc, &tex);
4745 if (r)
4746 return r;
4747
4748 /* add shadow ambient support - gallium doesn't do it yet */
4749 return 0;
4750 }
4751
4752 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4753 {
4754 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4755 struct r600_bytecode_alu alu;
4756 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4757 unsigned i;
4758 int r;
4759
4760 /* optimize if it's just an equal balance */
4761 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4762 for (i = 0; i < lasti + 1; i++) {
4763 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4764 continue;
4765
4766 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4767 alu.op = ALU_OP2_ADD;
4768 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4769 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4770 alu.omod = 3;
4771 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4772 alu.dst.chan = i;
4773 if (i == lasti) {
4774 alu.last = 1;
4775 }
4776 r = r600_bytecode_add_alu(ctx->bc, &alu);
4777 if (r)
4778 return r;
4779 }
4780 return 0;
4781 }
4782
4783 /* 1 - src0 */
4784 for (i = 0; i < lasti + 1; i++) {
4785 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4786 continue;
4787
4788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4789 alu.op = ALU_OP2_ADD;
4790 alu.src[0].sel = V_SQ_ALU_SRC_1;
4791 alu.src[0].chan = 0;
4792 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4793 r600_bytecode_src_toggle_neg(&alu.src[1]);
4794 alu.dst.sel = ctx->temp_reg;
4795 alu.dst.chan = i;
4796 if (i == lasti) {
4797 alu.last = 1;
4798 }
4799 alu.dst.write = 1;
4800 r = r600_bytecode_add_alu(ctx->bc, &alu);
4801 if (r)
4802 return r;
4803 }
4804
4805 /* (1 - src0) * src2 */
4806 for (i = 0; i < lasti + 1; i++) {
4807 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4808 continue;
4809
4810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4811 alu.op = ALU_OP2_MUL;
4812 alu.src[0].sel = ctx->temp_reg;
4813 alu.src[0].chan = i;
4814 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4815 alu.dst.sel = ctx->temp_reg;
4816 alu.dst.chan = i;
4817 if (i == lasti) {
4818 alu.last = 1;
4819 }
4820 alu.dst.write = 1;
4821 r = r600_bytecode_add_alu(ctx->bc, &alu);
4822 if (r)
4823 return r;
4824 }
4825
4826 /* src0 * src1 + (1 - src0) * src2 */
4827 for (i = 0; i < lasti + 1; i++) {
4828 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4829 continue;
4830
4831 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4832 alu.op = ALU_OP3_MULADD;
4833 alu.is_op3 = 1;
4834 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4835 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4836 alu.src[2].sel = ctx->temp_reg;
4837 alu.src[2].chan = i;
4838
4839 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4840 alu.dst.chan = i;
4841 if (i == lasti) {
4842 alu.last = 1;
4843 }
4844 r = r600_bytecode_add_alu(ctx->bc, &alu);
4845 if (r)
4846 return r;
4847 }
4848 return 0;
4849 }
4850
4851 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4852 {
4853 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4854 struct r600_bytecode_alu alu;
4855 int i, r;
4856 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4857
4858 for (i = 0; i < lasti + 1; i++) {
4859 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4860 continue;
4861
4862 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4863 alu.op = ALU_OP3_CNDGE;
4864 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4865 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4866 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4867 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4868 alu.dst.chan = i;
4869 alu.dst.write = 1;
4870 alu.is_op3 = 1;
4871 if (i == lasti)
4872 alu.last = 1;
4873 r = r600_bytecode_add_alu(ctx->bc, &alu);
4874 if (r)
4875 return r;
4876 }
4877 return 0;
4878 }
4879
4880 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4881 {
4882 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4883 struct r600_bytecode_alu alu;
4884 int i, r;
4885 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4886
4887 for (i = 0; i < lasti + 1; i++) {
4888 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4889 continue;
4890
4891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4892 alu.op = ALU_OP3_CNDGE_INT;
4893 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4894 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4895 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4896 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4897 alu.dst.chan = i;
4898 alu.dst.write = 1;
4899 alu.is_op3 = 1;
4900 if (i == lasti)
4901 alu.last = 1;
4902 r = r600_bytecode_add_alu(ctx->bc, &alu);
4903 if (r)
4904 return r;
4905 }
4906 return 0;
4907 }
4908
4909 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4910 {
4911 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4912 static const unsigned int src0_swizzle[] = {2, 0, 1};
4913 static const unsigned int src1_swizzle[] = {1, 2, 0};
4914 struct r600_bytecode_alu alu;
4915 uint32_t use_temp = 0;
4916 int i, r;
4917
4918 if (inst->Dst[0].Register.WriteMask != 0xf)
4919 use_temp = 1;
4920
4921 for (i = 0; i < 4; i++) {
4922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4923 alu.op = ALU_OP2_MUL;
4924 if (i < 3) {
4925 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4926 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4927 } else {
4928 alu.src[0].sel = V_SQ_ALU_SRC_0;
4929 alu.src[0].chan = i;
4930 alu.src[1].sel = V_SQ_ALU_SRC_0;
4931 alu.src[1].chan = i;
4932 }
4933
4934 alu.dst.sel = ctx->temp_reg;
4935 alu.dst.chan = i;
4936 alu.dst.write = 1;
4937
4938 if (i == 3)
4939 alu.last = 1;
4940 r = r600_bytecode_add_alu(ctx->bc, &alu);
4941 if (r)
4942 return r;
4943 }
4944
4945 for (i = 0; i < 4; i++) {
4946 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4947 alu.op = ALU_OP3_MULADD;
4948
4949 if (i < 3) {
4950 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4951 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4952 } else {
4953 alu.src[0].sel = V_SQ_ALU_SRC_0;
4954 alu.src[0].chan = i;
4955 alu.src[1].sel = V_SQ_ALU_SRC_0;
4956 alu.src[1].chan = i;
4957 }
4958
4959 alu.src[2].sel = ctx->temp_reg;
4960 alu.src[2].neg = 1;
4961 alu.src[2].chan = i;
4962
4963 if (use_temp)
4964 alu.dst.sel = ctx->temp_reg;
4965 else
4966 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4967 alu.dst.chan = i;
4968 alu.dst.write = 1;
4969 alu.is_op3 = 1;
4970 if (i == 3)
4971 alu.last = 1;
4972 r = r600_bytecode_add_alu(ctx->bc, &alu);
4973 if (r)
4974 return r;
4975 }
4976 if (use_temp)
4977 return tgsi_helper_copy(ctx, inst);
4978 return 0;
4979 }
4980
4981 static int tgsi_exp(struct r600_shader_ctx *ctx)
4982 {
4983 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4984 struct r600_bytecode_alu alu;
4985 int r;
4986 int i;
4987
4988 /* result.x = 2^floor(src); */
4989 if (inst->Dst[0].Register.WriteMask & 1) {
4990 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4991
4992 alu.op = ALU_OP1_FLOOR;
4993 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4994
4995 alu.dst.sel = ctx->temp_reg;
4996 alu.dst.chan = 0;
4997 alu.dst.write = 1;
4998 alu.last = 1;
4999 r = r600_bytecode_add_alu(ctx->bc, &alu);
5000 if (r)
5001 return r;
5002
5003 if (ctx->bc->chip_class == CAYMAN) {
5004 for (i = 0; i < 3; i++) {
5005 alu.op = ALU_OP1_EXP_IEEE;
5006 alu.src[0].sel = ctx->temp_reg;
5007 alu.src[0].chan = 0;
5008
5009 alu.dst.sel = ctx->temp_reg;
5010 alu.dst.chan = i;
5011 alu.dst.write = i == 0;
5012 alu.last = i == 2;
5013 r = r600_bytecode_add_alu(ctx->bc, &alu);
5014 if (r)
5015 return r;
5016 }
5017 } else {
5018 alu.op = ALU_OP1_EXP_IEEE;
5019 alu.src[0].sel = ctx->temp_reg;
5020 alu.src[0].chan = 0;
5021
5022 alu.dst.sel = ctx->temp_reg;
5023 alu.dst.chan = 0;
5024 alu.dst.write = 1;
5025 alu.last = 1;
5026 r = r600_bytecode_add_alu(ctx->bc, &alu);
5027 if (r)
5028 return r;
5029 }
5030 }
5031
5032 /* result.y = tmp - floor(tmp); */
5033 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5034 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5035
5036 alu.op = ALU_OP1_FRACT;
5037 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5038
5039 alu.dst.sel = ctx->temp_reg;
5040 #if 0
5041 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5042 if (r)
5043 return r;
5044 #endif
5045 alu.dst.write = 1;
5046 alu.dst.chan = 1;
5047
5048 alu.last = 1;
5049
5050 r = r600_bytecode_add_alu(ctx->bc, &alu);
5051 if (r)
5052 return r;
5053 }
5054
5055 /* result.z = RoughApprox2ToX(tmp);*/
5056 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
5057 if (ctx->bc->chip_class == CAYMAN) {
5058 for (i = 0; i < 3; i++) {
5059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5060 alu.op = ALU_OP1_EXP_IEEE;
5061 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5062
5063 alu.dst.sel = ctx->temp_reg;
5064 alu.dst.chan = i;
5065 if (i == 2) {
5066 alu.dst.write = 1;
5067 alu.last = 1;
5068 }
5069
5070 r = r600_bytecode_add_alu(ctx->bc, &alu);
5071 if (r)
5072 return r;
5073 }
5074 } else {
5075 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5076 alu.op = ALU_OP1_EXP_IEEE;
5077 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5078
5079 alu.dst.sel = ctx->temp_reg;
5080 alu.dst.write = 1;
5081 alu.dst.chan = 2;
5082
5083 alu.last = 1;
5084
5085 r = r600_bytecode_add_alu(ctx->bc, &alu);
5086 if (r)
5087 return r;
5088 }
5089 }
5090
5091 /* result.w = 1.0;*/
5092 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
5093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5094
5095 alu.op = ALU_OP1_MOV;
5096 alu.src[0].sel = V_SQ_ALU_SRC_1;
5097 alu.src[0].chan = 0;
5098
5099 alu.dst.sel = ctx->temp_reg;
5100 alu.dst.chan = 3;
5101 alu.dst.write = 1;
5102 alu.last = 1;
5103 r = r600_bytecode_add_alu(ctx->bc, &alu);
5104 if (r)
5105 return r;
5106 }
5107 return tgsi_helper_copy(ctx, inst);
5108 }
5109
5110 static int tgsi_log(struct r600_shader_ctx *ctx)
5111 {
5112 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5113 struct r600_bytecode_alu alu;
5114 int r;
5115 int i;
5116
5117 /* result.x = floor(log2(|src|)); */
5118 if (inst->Dst[0].Register.WriteMask & 1) {
5119 if (ctx->bc->chip_class == CAYMAN) {
5120 for (i = 0; i < 3; i++) {
5121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5122
5123 alu.op = ALU_OP1_LOG_IEEE;
5124 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5125 r600_bytecode_src_set_abs(&alu.src[0]);
5126
5127 alu.dst.sel = ctx->temp_reg;
5128 alu.dst.chan = i;
5129 if (i == 0)
5130 alu.dst.write = 1;
5131 if (i == 2)
5132 alu.last = 1;
5133 r = r600_bytecode_add_alu(ctx->bc, &alu);
5134 if (r)
5135 return r;
5136 }
5137
5138 } else {
5139 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5140
5141 alu.op = ALU_OP1_LOG_IEEE;
5142 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5143 r600_bytecode_src_set_abs(&alu.src[0]);
5144
5145 alu.dst.sel = ctx->temp_reg;
5146 alu.dst.chan = 0;
5147 alu.dst.write = 1;
5148 alu.last = 1;
5149 r = r600_bytecode_add_alu(ctx->bc, &alu);
5150 if (r)
5151 return r;
5152 }
5153
5154 alu.op = ALU_OP1_FLOOR;
5155 alu.src[0].sel = ctx->temp_reg;
5156 alu.src[0].chan = 0;
5157
5158 alu.dst.sel = ctx->temp_reg;
5159 alu.dst.chan = 0;
5160 alu.dst.write = 1;
5161 alu.last = 1;
5162
5163 r = r600_bytecode_add_alu(ctx->bc, &alu);
5164 if (r)
5165 return r;
5166 }
5167
5168 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
5169 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5170
5171 if (ctx->bc->chip_class == CAYMAN) {
5172 for (i = 0; i < 3; i++) {
5173 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5174
5175 alu.op = ALU_OP1_LOG_IEEE;
5176 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5177 r600_bytecode_src_set_abs(&alu.src[0]);
5178
5179 alu.dst.sel = ctx->temp_reg;
5180 alu.dst.chan = i;
5181 if (i == 1)
5182 alu.dst.write = 1;
5183 if (i == 2)
5184 alu.last = 1;
5185
5186 r = r600_bytecode_add_alu(ctx->bc, &alu);
5187 if (r)
5188 return r;
5189 }
5190 } else {
5191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5192
5193 alu.op = ALU_OP1_LOG_IEEE;
5194 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5195 r600_bytecode_src_set_abs(&alu.src[0]);
5196
5197 alu.dst.sel = ctx->temp_reg;
5198 alu.dst.chan = 1;
5199 alu.dst.write = 1;
5200 alu.last = 1;
5201
5202 r = r600_bytecode_add_alu(ctx->bc, &alu);
5203 if (r)
5204 return r;
5205 }
5206
5207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5208
5209 alu.op = ALU_OP1_FLOOR;
5210 alu.src[0].sel = ctx->temp_reg;
5211 alu.src[0].chan = 1;
5212
5213 alu.dst.sel = ctx->temp_reg;
5214 alu.dst.chan = 1;
5215 alu.dst.write = 1;
5216 alu.last = 1;
5217
5218 r = r600_bytecode_add_alu(ctx->bc, &alu);
5219 if (r)
5220 return r;
5221
5222 if (ctx->bc->chip_class == CAYMAN) {
5223 for (i = 0; i < 3; i++) {
5224 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5225 alu.op = ALU_OP1_EXP_IEEE;
5226 alu.src[0].sel = ctx->temp_reg;
5227 alu.src[0].chan = 1;
5228
5229 alu.dst.sel = ctx->temp_reg;
5230 alu.dst.chan = i;
5231 if (i == 1)
5232 alu.dst.write = 1;
5233 if (i == 2)
5234 alu.last = 1;
5235
5236 r = r600_bytecode_add_alu(ctx->bc, &alu);
5237 if (r)
5238 return r;
5239 }
5240 } else {
5241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5242 alu.op = ALU_OP1_EXP_IEEE;
5243 alu.src[0].sel = ctx->temp_reg;
5244 alu.src[0].chan = 1;
5245
5246 alu.dst.sel = ctx->temp_reg;
5247 alu.dst.chan = 1;
5248 alu.dst.write = 1;
5249 alu.last = 1;
5250
5251 r = r600_bytecode_add_alu(ctx->bc, &alu);
5252 if (r)
5253 return r;
5254 }
5255
5256 if (ctx->bc->chip_class == CAYMAN) {
5257 for (i = 0; i < 3; i++) {
5258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5259 alu.op = ALU_OP1_RECIP_IEEE;
5260 alu.src[0].sel = ctx->temp_reg;
5261 alu.src[0].chan = 1;
5262
5263 alu.dst.sel = ctx->temp_reg;
5264 alu.dst.chan = i;
5265 if (i == 1)
5266 alu.dst.write = 1;
5267 if (i == 2)
5268 alu.last = 1;
5269
5270 r = r600_bytecode_add_alu(ctx->bc, &alu);
5271 if (r)
5272 return r;
5273 }
5274 } else {
5275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5276 alu.op = ALU_OP1_RECIP_IEEE;
5277 alu.src[0].sel = ctx->temp_reg;
5278 alu.src[0].chan = 1;
5279
5280 alu.dst.sel = ctx->temp_reg;
5281 alu.dst.chan = 1;
5282 alu.dst.write = 1;
5283 alu.last = 1;
5284
5285 r = r600_bytecode_add_alu(ctx->bc, &alu);
5286 if (r)
5287 return r;
5288 }
5289
5290 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5291
5292 alu.op = ALU_OP2_MUL;
5293
5294 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5295 r600_bytecode_src_set_abs(&alu.src[0]);
5296
5297 alu.src[1].sel = ctx->temp_reg;
5298 alu.src[1].chan = 1;
5299
5300 alu.dst.sel = ctx->temp_reg;
5301 alu.dst.chan = 1;
5302 alu.dst.write = 1;
5303 alu.last = 1;
5304
5305 r = r600_bytecode_add_alu(ctx->bc, &alu);
5306 if (r)
5307 return r;
5308 }
5309
5310 /* result.z = log2(|src|);*/
5311 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5312 if (ctx->bc->chip_class == CAYMAN) {
5313 for (i = 0; i < 3; i++) {
5314 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5315
5316 alu.op = ALU_OP1_LOG_IEEE;
5317 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5318 r600_bytecode_src_set_abs(&alu.src[0]);
5319
5320 alu.dst.sel = ctx->temp_reg;
5321 if (i == 2)
5322 alu.dst.write = 1;
5323 alu.dst.chan = i;
5324 if (i == 2)
5325 alu.last = 1;
5326
5327 r = r600_bytecode_add_alu(ctx->bc, &alu);
5328 if (r)
5329 return r;
5330 }
5331 } else {
5332 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5333
5334 alu.op = ALU_OP1_LOG_IEEE;
5335 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5336 r600_bytecode_src_set_abs(&alu.src[0]);
5337
5338 alu.dst.sel = ctx->temp_reg;
5339 alu.dst.write = 1;
5340 alu.dst.chan = 2;
5341 alu.last = 1;
5342
5343 r = r600_bytecode_add_alu(ctx->bc, &alu);
5344 if (r)
5345 return r;
5346 }
5347 }
5348
5349 /* result.w = 1.0; */
5350 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5351 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5352
5353 alu.op = ALU_OP1_MOV;
5354 alu.src[0].sel = V_SQ_ALU_SRC_1;
5355 alu.src[0].chan = 0;
5356
5357 alu.dst.sel = ctx->temp_reg;
5358 alu.dst.chan = 3;
5359 alu.dst.write = 1;
5360 alu.last = 1;
5361
5362 r = r600_bytecode_add_alu(ctx->bc, &alu);
5363 if (r)
5364 return r;
5365 }
5366
5367 return tgsi_helper_copy(ctx, inst);
5368 }
5369
5370 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5371 {
5372 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5373 struct r600_bytecode_alu alu;
5374 int r;
5375
5376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5377
5378 switch (inst->Instruction.Opcode) {
5379 case TGSI_OPCODE_ARL:
5380 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5381 break;
5382 case TGSI_OPCODE_ARR:
5383 alu.op = ALU_OP1_FLT_TO_INT;
5384 break;
5385 case TGSI_OPCODE_UARL:
5386 alu.op = ALU_OP1_MOV;
5387 break;
5388 default:
5389 assert(0);
5390 return -1;
5391 }
5392
5393 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5394 alu.last = 1;
5395 alu.dst.sel = ctx->bc->ar_reg;
5396 alu.dst.write = 1;
5397 r = r600_bytecode_add_alu(ctx->bc, &alu);
5398 if (r)
5399 return r;
5400
5401 ctx->bc->ar_loaded = 0;
5402 return 0;
5403 }
5404 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5405 {
5406 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5407 struct r600_bytecode_alu alu;
5408 int r;
5409
5410 switch (inst->Instruction.Opcode) {
5411 case TGSI_OPCODE_ARL:
5412 memset(&alu, 0, sizeof(alu));
5413 alu.op = ALU_OP1_FLOOR;
5414 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5415 alu.dst.sel = ctx->bc->ar_reg;
5416 alu.dst.write = 1;
5417 alu.last = 1;
5418
5419 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5420 return r;
5421
5422 memset(&alu, 0, sizeof(alu));
5423 alu.op = ALU_OP1_FLT_TO_INT;
5424 alu.src[0].sel = ctx->bc->ar_reg;
5425 alu.dst.sel = ctx->bc->ar_reg;
5426 alu.dst.write = 1;
5427 alu.last = 1;
5428
5429 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5430 return r;
5431 break;
5432 case TGSI_OPCODE_ARR:
5433 memset(&alu, 0, sizeof(alu));
5434 alu.op = ALU_OP1_FLT_TO_INT;
5435 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5436 alu.dst.sel = ctx->bc->ar_reg;
5437 alu.dst.write = 1;
5438 alu.last = 1;
5439
5440 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5441 return r;
5442 break;
5443 case TGSI_OPCODE_UARL:
5444 memset(&alu, 0, sizeof(alu));
5445 alu.op = ALU_OP1_MOV;
5446 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5447 alu.dst.sel = ctx->bc->ar_reg;
5448 alu.dst.write = 1;
5449 alu.last = 1;
5450
5451 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5452 return r;
5453 break;
5454 default:
5455 assert(0);
5456 return -1;
5457 }
5458
5459 ctx->bc->ar_loaded = 0;
5460 return 0;
5461 }
5462
5463 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5464 {
5465 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5466 struct r600_bytecode_alu alu;
5467 int i, r = 0;
5468
5469 for (i = 0; i < 4; i++) {
5470 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5471
5472 alu.op = ALU_OP2_MUL;
5473 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5474
5475 if (i == 0 || i == 3) {
5476 alu.src[0].sel = V_SQ_ALU_SRC_1;
5477 } else {
5478 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5479 }
5480
5481 if (i == 0 || i == 2) {
5482 alu.src[1].sel = V_SQ_ALU_SRC_1;
5483 } else {
5484 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5485 }
5486 if (i == 3)
5487 alu.last = 1;
5488 r = r600_bytecode_add_alu(ctx->bc, &alu);
5489 if (r)
5490 return r;
5491 }
5492 return 0;
5493 }
5494
5495 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
5496 {
5497 struct r600_bytecode_alu alu;
5498 int r;
5499
5500 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5501 alu.op = opcode;
5502 alu.execute_mask = 1;
5503 alu.update_pred = 1;
5504
5505 alu.dst.sel = ctx->temp_reg;
5506 alu.dst.write = 1;
5507 alu.dst.chan = 0;
5508
5509 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5510 alu.src[1].sel = V_SQ_ALU_SRC_0;
5511 alu.src[1].chan = 0;
5512
5513 alu.last = 1;
5514
5515 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
5516 if (r)
5517 return r;
5518 return 0;
5519 }
5520
5521 static int pops(struct r600_shader_ctx *ctx, int pops)
5522 {
5523 unsigned force_pop = ctx->bc->force_add_cf;
5524
5525 if (!force_pop) {
5526 int alu_pop = 3;
5527 if (ctx->bc->cf_last) {
5528 if (ctx->bc->cf_last->op == CF_OP_ALU)
5529 alu_pop = 0;
5530 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5531 alu_pop = 1;
5532 }
5533 alu_pop += pops;
5534 if (alu_pop == 1) {
5535 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5536 ctx->bc->force_add_cf = 1;
5537 } else if (alu_pop == 2) {
5538 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5539 ctx->bc->force_add_cf = 1;
5540 } else {
5541 force_pop = 1;
5542 }
5543 }
5544
5545 if (force_pop) {
5546 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5547 ctx->bc->cf_last->pop_count = pops;
5548 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5549 }
5550
5551 return 0;
5552 }
5553
5554 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
5555 {
5556 switch(reason) {
5557 case FC_PUSH_VPM:
5558 ctx->bc->callstack[ctx->bc->call_sp].current--;
5559 break;
5560 case FC_PUSH_WQM:
5561 case FC_LOOP:
5562 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
5563 break;
5564 case FC_REP:
5565 /* TOODO : for 16 vp asic should -= 2; */
5566 ctx->bc->callstack[ctx->bc->call_sp].current --;
5567 break;
5568 }
5569 }
5570
5571 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
5572 {
5573 if (check_max_only) {
5574 int diff;
5575 switch (reason) {
5576 case FC_PUSH_VPM:
5577 diff = 1;
5578 break;
5579 case FC_PUSH_WQM:
5580 diff = 4;
5581 break;
5582 default:
5583 assert(0);
5584 diff = 0;
5585 }
5586 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
5587 ctx->bc->callstack[ctx->bc->call_sp].max) {
5588 ctx->bc->callstack[ctx->bc->call_sp].max =
5589 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
5590 }
5591 return;
5592 }
5593 switch (reason) {
5594 case FC_PUSH_VPM:
5595 ctx->bc->callstack[ctx->bc->call_sp].current++;
5596 break;
5597 case FC_PUSH_WQM:
5598 case FC_LOOP:
5599 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
5600 break;
5601 case FC_REP:
5602 ctx->bc->callstack[ctx->bc->call_sp].current++;
5603 break;
5604 }
5605
5606 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
5607 ctx->bc->callstack[ctx->bc->call_sp].max) {
5608 ctx->bc->callstack[ctx->bc->call_sp].max =
5609 ctx->bc->callstack[ctx->bc->call_sp].current;
5610 }
5611 }
5612
5613 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5614 {
5615 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5616
5617 sp->mid = realloc((void *)sp->mid,
5618 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5619 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5620 sp->num_mid++;
5621 }
5622
5623 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5624 {
5625 ctx->bc->fc_sp++;
5626 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5627 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5628 }
5629
5630 static void fc_poplevel(struct r600_shader_ctx *ctx)
5631 {
5632 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5633 free(sp->mid);
5634 sp->mid = NULL;
5635 sp->num_mid = 0;
5636 sp->start = NULL;
5637 sp->type = 0;
5638 ctx->bc->fc_sp--;
5639 }
5640
5641 #if 0
5642 static int emit_return(struct r600_shader_ctx *ctx)
5643 {
5644 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5645 return 0;
5646 }
5647
5648 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5649 {
5650
5651 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5652 ctx->bc->cf_last->pop_count = pops;
5653 /* XXX work out offset */
5654 return 0;
5655 }
5656
5657 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5658 {
5659 return 0;
5660 }
5661
5662 static void emit_testflag(struct r600_shader_ctx *ctx)
5663 {
5664
5665 }
5666
5667 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5668 {
5669 emit_testflag(ctx);
5670 emit_jump_to_offset(ctx, 1, 4);
5671 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5672 pops(ctx, ifidx + 1);
5673 emit_return(ctx);
5674 }
5675
5676 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5677 {
5678 emit_testflag(ctx);
5679
5680 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5681 ctx->bc->cf_last->pop_count = 1;
5682
5683 fc_set_mid(ctx, fc_sp);
5684
5685 pops(ctx, 1);
5686 }
5687 #endif
5688
5689 static int tgsi_if(struct r600_shader_ctx *ctx)
5690 {
5691 emit_logic_pred(ctx, ALU_OP2_PRED_SETNE_INT);
5692
5693 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5694
5695 fc_pushlevel(ctx, FC_IF);
5696
5697 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
5698 return 0;
5699 }
5700
5701 static int tgsi_else(struct r600_shader_ctx *ctx)
5702 {
5703 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5704 ctx->bc->cf_last->pop_count = 1;
5705
5706 fc_set_mid(ctx, ctx->bc->fc_sp);
5707 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5708 return 0;
5709 }
5710
5711 static int tgsi_endif(struct r600_shader_ctx *ctx)
5712 {
5713 pops(ctx, 1);
5714 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5715 R600_ERR("if/endif unbalanced in shader\n");
5716 return -1;
5717 }
5718
5719 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5720 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5721 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5722 } else {
5723 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5724 }
5725 fc_poplevel(ctx);
5726
5727 callstack_decrease_current(ctx, FC_PUSH_VPM);
5728 return 0;
5729 }
5730
5731 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5732 {
5733 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5734 * limited to 4096 iterations, like the other LOOP_* instructions. */
5735 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5736
5737 fc_pushlevel(ctx, FC_LOOP);
5738
5739 /* check stack depth */
5740 callstack_check_depth(ctx, FC_LOOP, 0);
5741 return 0;
5742 }
5743
5744 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5745 {
5746 int i;
5747
5748 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5749
5750 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5751 R600_ERR("loop/endloop in shader code are not paired.\n");
5752 return -EINVAL;
5753 }
5754
5755 /* fixup loop pointers - from r600isa
5756 LOOP END points to CF after LOOP START,
5757 LOOP START point to CF after LOOP END
5758 BRK/CONT point to LOOP END CF
5759 */
5760 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5761
5762 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5763
5764 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5765 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5766 }
5767 /* XXX add LOOPRET support */
5768 fc_poplevel(ctx);
5769 callstack_decrease_current(ctx, FC_LOOP);
5770 return 0;
5771 }
5772
5773 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5774 {
5775 unsigned int fscp;
5776
5777 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5778 {
5779 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5780 break;
5781 }
5782
5783 if (fscp == 0) {
5784 R600_ERR("Break not inside loop/endloop pair\n");
5785 return -EINVAL;
5786 }
5787
5788 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5789
5790 fc_set_mid(ctx, fscp);
5791
5792 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
5793 return 0;
5794 }
5795
5796 static int tgsi_umad(struct r600_shader_ctx *ctx)
5797 {
5798 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5799 struct r600_bytecode_alu alu;
5800 int i, j, r;
5801 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5802
5803 /* src0 * src1 */
5804 for (i = 0; i < lasti + 1; i++) {
5805 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5806 continue;
5807
5808 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5809
5810 alu.dst.chan = i;
5811 alu.dst.sel = ctx->temp_reg;
5812 alu.dst.write = 1;
5813
5814 alu.op = ALU_OP2_MULLO_UINT;
5815 for (j = 0; j < 2; j++) {
5816 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5817 }
5818
5819 alu.last = 1;
5820 r = r600_bytecode_add_alu(ctx->bc, &alu);
5821 if (r)
5822 return r;
5823 }
5824
5825
5826 for (i = 0; i < lasti + 1; i++) {
5827 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5828 continue;
5829
5830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5831 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5832
5833 alu.op = ALU_OP2_ADD_INT;
5834
5835 alu.src[0].sel = ctx->temp_reg;
5836 alu.src[0].chan = i;
5837
5838 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5839 if (i == lasti) {
5840 alu.last = 1;
5841 }
5842 r = r600_bytecode_add_alu(ctx->bc, &alu);
5843 if (r)
5844 return r;
5845 }
5846 return 0;
5847 }
5848
5849 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5850 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
5851 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5852 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5853
5854 /* XXX:
5855 * For state trackers other than OpenGL, we'll want to use
5856 * _RECIP_IEEE instead.
5857 */
5858 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5859
5860 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
5861 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5862 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5863 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5864 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5865 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5866 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5867 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5868 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5869 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5870 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5871 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5872 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5873 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5874 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5875 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5876 /* gap */
5877 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5878 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5879 /* gap */
5880 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5881 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5882 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5883 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5884 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5885 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5886 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5887 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5888 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5889 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5890 /* gap */
5891 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5892 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5893 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5894 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5895 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5896 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5897 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5898 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
5899 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5900 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5901 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5902 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5903 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5904 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5905 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5906 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5907 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5908 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5909 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5910 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5911 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5912 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5913 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5914 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5915 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5916 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5917 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5918 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5919 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5920 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
5921 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5922 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5923 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5924 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5925 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5926 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5927 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5928 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5929 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5930 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5931 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5932 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5933 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5934 /* gap */
5935 {75, 0, ALU_OP0_NOP, tgsi_unsupported},
5936 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5937 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5938 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5939 /* gap */
5940 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5941 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5942 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5943 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5944 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5945 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5946 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5947 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5948 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
5949 /* gap */
5950 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5951 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5952 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5953 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5954 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5955 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5956 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5957 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5958 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5959 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5960 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5961 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5962 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5963 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5964 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5965 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5966 /* gap */
5967 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5968 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5969 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5970 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5971 /* gap */
5972 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
5973 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
5974 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
5975 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
5976 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5977 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5978 {TGSI_OPCODE_IFC, 0, ALU_OP0_NOP, tgsi_unsupported},
5979 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5980 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5981 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5982 /* gap */
5983 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5984 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
5985 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5986 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5987 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5988 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5989 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5990 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
5991 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5992 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
5993 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5994 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5995 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5996 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5997 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5998 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5999 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6000 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6001 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6002 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6003 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
6004 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6005 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
6006 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6007 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6008 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6009 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6010 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6011 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6012 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6013 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6014 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6015 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6016 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6017 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6018 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6019 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6020 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6021 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6022 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
6023 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6024 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6025 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6026 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6027 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6028 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6029 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6030 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6031 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6032 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6033 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6034 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6035 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6036 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6037 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6038 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6039 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6040 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6041 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6042 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6043 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6044 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6045 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6046 };
6047
6048 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
6049 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6050 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6051 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6052 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
6053 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
6054 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6055 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6056 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6057 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6058 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6059 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6060 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6061 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6062 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6063 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6064 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6065 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6066 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6067 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6068 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6069 /* gap */
6070 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6071 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6072 /* gap */
6073 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6074 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6075 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6076 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6077 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6078 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6079 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6080 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6081 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6082 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6083 /* gap */
6084 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6085 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6086 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6087 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6088 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6089 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6090 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6091 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6092 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6093 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6094 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6095 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6096 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6097 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6098 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6099 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6100 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6101 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6102 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6103 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6104 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6105 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6106 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6107 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6108 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6109 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6110 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6111 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6112 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6113 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6114 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6115 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6116 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6117 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6118 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6119 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6120 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6121 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6122 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6123 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6124 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6125 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6126 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6127 /* gap */
6128 {75, 0, ALU_OP0_NOP, tgsi_unsupported},
6129 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6130 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6131 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6132 /* gap */
6133 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6134 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6135 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6136 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6137 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6138 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6139 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6140 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6141 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6142 /* gap */
6143 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6144 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6145 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6146 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6147 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6148 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6149 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6150 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6151 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6152 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6153 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6154 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6155 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6156 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6157 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6158 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6159 /* gap */
6160 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6161 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6162 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6163 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6164 /* gap */
6165 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6166 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6167 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6168 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6169 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6170 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6171 {TGSI_OPCODE_IFC, 0, ALU_OP0_NOP, tgsi_unsupported},
6172 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6173 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6174 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6175 /* gap */
6176 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6177 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
6178 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6179 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6180 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6181 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6182 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6183 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6184 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6185 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
6186 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6187 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6188 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6189 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6190 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6191 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6192 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6193 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6194 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6195 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6196 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6197 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6198 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6199 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6200 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6201 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6202 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6203 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6204 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6205 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6206 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6207 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6208 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6209 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6210 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6211 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6212 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6213 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6214 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6215 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6216 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6217 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6218 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6219 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6220 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6221 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6222 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6223 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6224 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6225 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6226 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6227 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6228 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6229 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6230 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6231 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6232 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6233 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6234 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6235 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6236 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6237 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6238 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6239 };
6240
6241 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6242 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6243 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6244 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6245 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6246 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6247 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6248 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6249 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6250 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6251 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6252 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6253 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6254 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6255 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6256 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6257 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6258 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6259 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6260 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6261 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6262 /* gap */
6263 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6264 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6265 /* gap */
6266 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6267 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6268 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6269 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6270 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6271 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6272 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6273 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6274 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6275 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6276 /* gap */
6277 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6278 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6279 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6280 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6281 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6282 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6283 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6284 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6285 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6286 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6287 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6288 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6289 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6290 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6291 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6292 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6293 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6294 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6295 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6296 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6297 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6298 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6299 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6300 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6301 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6302 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6303 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6304 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6305 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6306 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6307 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6308 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6309 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6310 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6311 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6312 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6313 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6314 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6315 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6316 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6317 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6318 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6319 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6320 /* gap */
6321 {75, 0, ALU_OP0_NOP, tgsi_unsupported},
6322 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6323 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6324 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6325 /* gap */
6326 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6327 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6328 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6329 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6330 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6331 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6332 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6333 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6334 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6335 /* gap */
6336 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6337 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6338 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6339 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6340 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6341 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6342 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6343 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6344 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6345 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6346 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6347 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6348 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6349 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6350 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6351 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6352 /* gap */
6353 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6354 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6355 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6356 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6357 /* gap */
6358 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6359 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6360 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6361 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6362 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6363 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6364 {TGSI_OPCODE_IFC, 0, ALU_OP0_NOP, tgsi_unsupported},
6365 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6366 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6367 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6368 /* gap */
6369 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6370 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6371 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6372 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6373 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6374 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6375 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6376 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6377 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6378 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6379 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6380 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6381 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6382 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6383 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6384 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6385 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6386 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6387 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6388 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6389 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6390 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6391 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6392 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6393 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6394 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6395 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6396 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6397 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6398 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6399 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6400 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6401 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6402 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6403 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6404 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6405 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6406 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6407 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6408 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6409 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6410 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6411 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6412 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6413 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6414 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6415 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6416 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6417 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6418 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6419 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6420 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6421 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6422 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6423 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6424 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6425 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6426 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6427 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6428 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6429 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6430 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6431 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6432 };