2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
29 #include "pipe/p_shader_tokens.h"
30 #include "tgsi/tgsi_info.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "util/u_memory.h"
40 Why CAYMAN got loops for lots of instructions is explained here.
42 -These 8xx t-slot only ops are implemented in all vector slots.
43 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
44 These 8xx t-slot only opcodes become vector ops, with all four
45 slots expecting the arguments on sources a and b. Result is
46 broadcast to all channels.
47 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
48 These 8xx t-slot only opcodes become vector ops in the z, y, and
50 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
51 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
54 The w slot may have an independent co-issued operation, or if the
55 result is required to be in the w slot, the opcode above may be
56 issued in the w slot as well.
57 The compiler must issue the source argument to slots z, y, and x
60 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
62 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
63 struct r600_shader
*rshader
= &shader
->shader
;
68 if (shader
->bo
== NULL
) {
69 shader
->bo
= (struct r600_resource
*)
70 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_IMMUTABLE
, rshader
->bc
.ndw
* 4);
71 if (shader
->bo
== NULL
) {
74 ptr
= (uint32_t*)rctx
->ws
->buffer_map(shader
->bo
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
75 if (R600_BIG_ENDIAN
) {
76 for (i
= 0; i
< rshader
->bc
.ndw
; ++i
) {
77 ptr
[i
] = bswap_32(rshader
->bc
.bytecode
[i
]);
80 memcpy(ptr
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* sizeof(*ptr
));
82 rctx
->ws
->buffer_unmap(shader
->bo
->cs_buf
);
85 switch (rshader
->processor_type
) {
86 case TGSI_PROCESSOR_VERTEX
:
87 if (rctx
->chip_class
>= EVERGREEN
) {
88 evergreen_pipe_shader_vs(ctx
, shader
);
90 r600_pipe_shader_vs(ctx
, shader
);
93 case TGSI_PROCESSOR_FRAGMENT
:
94 if (rctx
->chip_class
>= EVERGREEN
) {
95 evergreen_pipe_shader_ps(ctx
, shader
);
97 r600_pipe_shader_ps(ctx
, shader
);
106 static int r600_shader_from_tgsi(struct r600_context
* rctx
, struct r600_pipe_shader
*pipeshader
);
108 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
110 static int dump_shaders
= -1;
111 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
112 struct r600_pipe_shader_selector
*sel
= shader
->selector
;
115 /* Would like some magic "get_bool_option_once" routine.
117 if (dump_shaders
== -1)
118 dump_shaders
= debug_get_bool_option("R600_DUMP_SHADERS", FALSE
);
121 fprintf(stderr
, "--------------------------------------------------------------\n");
122 tgsi_dump(sel
->tokens
, 0);
124 if (sel
->so
.num_outputs
) {
126 fprintf(stderr
, "STREAMOUT\n");
127 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
128 unsigned mask
= ((1 << sel
->so
.output
[i
].num_components
) - 1) <<
129 sel
->so
.output
[i
].start_component
;
130 fprintf(stderr
, " %i: MEM_STREAM0_BUF%i OUT[%i].%s%s%s%s\n", i
,
131 sel
->so
.output
[i
].output_buffer
, sel
->so
.output
[i
].register_index
,
132 mask
& 1 ? "x" : "_",
133 (mask
>> 1) & 1 ? "y" : "_",
134 (mask
>> 2) & 1 ? "z" : "_",
135 (mask
>> 3) & 1 ? "w" : "_");
139 r
= r600_shader_from_tgsi(rctx
, shader
);
141 R600_ERR("translation from TGSI failed !\n");
144 r
= r600_bytecode_build(&shader
->shader
.bc
);
146 R600_ERR("building bytecode failed !\n");
150 r600_bytecode_dump(&shader
->shader
.bc
);
151 fprintf(stderr
, "______________________________________________________________\n");
153 return r600_pipe_shader(ctx
, shader
);
156 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
158 pipe_resource_reference((struct pipe_resource
**)&shader
->bo
, NULL
);
159 r600_bytecode_clear(&shader
->shader
.bc
);
163 * tgsi -> r600 shader
165 struct r600_shader_tgsi_instruction
;
167 struct r600_shader_src
{
176 struct r600_shader_ctx
{
177 struct tgsi_shader_info info
;
178 struct tgsi_parse_context parse
;
179 const struct tgsi_token
*tokens
;
181 unsigned file_offset
[TGSI_FILE_COUNT
];
183 struct r600_shader_tgsi_instruction
*inst_info
;
184 struct r600_bytecode
*bc
;
185 struct r600_shader
*shader
;
186 struct r600_shader_src src
[4];
189 uint32_t max_driver_temp_used
;
190 /* needed for evergreen interpolation */
191 boolean input_centroid
;
192 boolean input_linear
;
193 boolean input_perspective
;
197 boolean clip_vertex_write
;
203 struct r600_shader_tgsi_instruction
{
204 unsigned tgsi_opcode
;
206 unsigned r600_opcode
;
207 int (*process
)(struct r600_shader_ctx
*ctx
);
210 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
211 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
212 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
);
213 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
);
214 static int tgsi_else(struct r600_shader_ctx
*ctx
);
215 static int tgsi_endif(struct r600_shader_ctx
*ctx
);
216 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
);
217 static int tgsi_endloop(struct r600_shader_ctx
*ctx
);
218 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
);
221 * bytestream -> r600 shader
223 * These functions are used to transform the output of the LLVM backend into
224 * struct r600_bytecode.
227 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx
*ctx
,
228 unsigned char * bytes
, unsigned num_bytes
);
231 int r600_compute_shader_create(struct pipe_context
* ctx
,
232 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
)
234 struct r600_context
*r600_ctx
= (struct r600_context
*)ctx
;
235 unsigned char * bytes
;
237 struct r600_shader_ctx shader_ctx
;
240 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE
)) {
244 r600_llvm_compile(mod
, &bytes
, &byte_count
, r600_ctx
->family
, dump
);
245 shader_ctx
.bc
= bytecode
;
246 r600_bytecode_init(shader_ctx
.bc
, r600_ctx
->chip_class
, r600_ctx
->family
);
247 shader_ctx
.bc
->type
= TGSI_PROCESSOR_COMPUTE
;
248 r600_bytecode_from_byte_stream(&shader_ctx
, bytes
, byte_count
);
249 if (shader_ctx
.bc
->chip_class
== CAYMAN
) {
250 cm_bytecode_add_cf_end(shader_ctx
.bc
);
252 r600_bytecode_build(shader_ctx
.bc
);
254 r600_bytecode_dump(shader_ctx
.bc
);
259 #endif /* HAVE_OPENCL */
261 static uint32_t i32_from_byte_stream(unsigned char * bytes
,
262 unsigned * bytes_read
)
266 for (i
= 0; i
< 4; i
++) {
267 out
|= bytes
[(*bytes_read
)++] << (8 * i
);
272 static unsigned r600_src_from_byte_stream(unsigned char * bytes
,
273 unsigned bytes_read
, struct r600_bytecode_alu
* alu
, unsigned src_idx
)
277 sel0
= bytes
[bytes_read
++];
278 sel1
= bytes
[bytes_read
++];
279 alu
->src
[src_idx
].sel
= sel0
| (sel1
<< 8);
280 alu
->src
[src_idx
].chan
= bytes
[bytes_read
++];
281 alu
->src
[src_idx
].neg
= bytes
[bytes_read
++];
282 alu
->src
[src_idx
].abs
= bytes
[bytes_read
++];
283 alu
->src
[src_idx
].rel
= bytes
[bytes_read
++];
284 alu
->src
[src_idx
].kc_bank
= bytes
[bytes_read
++];
285 for (i
= 0; i
< 4; i
++) {
286 alu
->src
[src_idx
].value
|= bytes
[bytes_read
++] << (i
* 8);
291 static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx
*ctx
,
292 unsigned char * bytes
, unsigned bytes_read
)
295 unsigned inst0
, inst1
;
296 struct r600_bytecode_alu alu
;
297 memset(&alu
, 0, sizeof(alu
));
298 for(src_idx
= 0; src_idx
< 3; src_idx
++) {
299 bytes_read
= r600_src_from_byte_stream(bytes
, bytes_read
,
303 alu
.dst
.sel
= bytes
[bytes_read
++];
304 alu
.dst
.chan
= bytes
[bytes_read
++];
305 alu
.dst
.clamp
= bytes
[bytes_read
++];
306 alu
.dst
.write
= bytes
[bytes_read
++];
307 alu
.dst
.rel
= bytes
[bytes_read
++];
308 inst0
= bytes
[bytes_read
++];
309 inst1
= bytes
[bytes_read
++];
310 alu
.inst
= inst0
| (inst1
<< 8);
311 alu
.last
= bytes
[bytes_read
++];
312 alu
.is_op3
= bytes
[bytes_read
++];
313 alu
.predicate
= bytes
[bytes_read
++];
314 alu
.bank_swizzle
= bytes
[bytes_read
++];
315 alu
.bank_swizzle_force
= bytes
[bytes_read
++];
316 alu
.omod
= bytes
[bytes_read
++];
317 alu
.index_mode
= bytes
[bytes_read
++];
318 r600_bytecode_add_alu(ctx
->bc
, &alu
);
320 /* XXX: Handle other KILL instructions */
321 if (alu
.inst
== CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
)) {
322 ctx
->shader
->uses_kill
= 1;
323 /* XXX: This should be enforced in the LLVM backend. */
324 ctx
->bc
->force_add_cf
= 1;
329 static void llvm_if(struct r600_shader_ctx
*ctx
, struct r600_bytecode_alu
* alu
,
332 alu
->inst
= pred_inst
;
335 alu
->src
[1].sel
= V_SQ_ALU_SRC_0
;
336 alu
->src
[1].chan
= 0;
338 r600_bytecode_add_alu_type(ctx
->bc
, alu
,
339 CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
341 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
342 fc_pushlevel(ctx
, FC_IF
);
343 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
346 static void r600_break_from_byte_stream(struct r600_shader_ctx
*ctx
,
347 struct r600_bytecode_alu
*alu
, unsigned compare_opcode
)
349 unsigned opcode
= TGSI_OPCODE_BRK
;
350 if (ctx
->bc
->chip_class
== CAYMAN
)
351 ctx
->inst_info
= &cm_shader_tgsi_instruction
[opcode
];
352 else if (ctx
->bc
->chip_class
>= EVERGREEN
)
353 ctx
->inst_info
= &eg_shader_tgsi_instruction
[opcode
];
355 ctx
->inst_info
= &r600_shader_tgsi_instruction
[opcode
];
356 llvm_if(ctx
, alu
, compare_opcode
);
357 tgsi_loop_brk_cont(ctx
);
361 static unsigned r600_fc_from_byte_stream(struct r600_shader_ctx
*ctx
,
362 unsigned char * bytes
, unsigned bytes_read
)
364 struct r600_bytecode_alu alu
;
366 memset(&alu
, 0, sizeof(alu
));
367 bytes_read
= r600_src_from_byte_stream(bytes
, bytes_read
, &alu
, 0);
368 inst
= bytes
[bytes_read
++];
372 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
));
374 case 1: /* FC_IF_INT */
376 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
));
378 case 2: /* FC_ELSE */
381 case 3: /* FC_ENDIF */
384 case 4: /* FC_BGNLOOP */
387 case 5: /* FC_ENDLOOP */
390 case 6: /* FC_BREAK */
391 r600_break_from_byte_stream(ctx
, &alu
,
392 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
));
394 case 7: /* FC_BREAK_NZ_INT */
395 r600_break_from_byte_stream(ctx
, &alu
,
396 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
));
398 case 8: /* FC_CONTINUE */
400 unsigned opcode
= TGSI_OPCODE_CONT
;
401 if (ctx
->bc
->chip_class
== CAYMAN
) {
403 &cm_shader_tgsi_instruction
[opcode
];
404 } else if (ctx
->bc
->chip_class
>= EVERGREEN
) {
406 &eg_shader_tgsi_instruction
[opcode
];
409 &r600_shader_tgsi_instruction
[opcode
];
411 tgsi_loop_brk_cont(ctx
);
414 case 9: /* FC_BREAK_Z_INT */
415 r600_break_from_byte_stream(ctx
, &alu
,
416 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
));
418 case 10: /* FC_BREAK_NZ */
419 r600_break_from_byte_stream(ctx
, &alu
,
420 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
));
427 static unsigned r600_tex_from_byte_stream(struct r600_shader_ctx
*ctx
,
428 unsigned char * bytes
, unsigned bytes_read
)
430 struct r600_bytecode_tex tex
;
432 tex
.inst
= bytes
[bytes_read
++];
433 tex
.resource_id
= bytes
[bytes_read
++];
434 tex
.src_gpr
= bytes
[bytes_read
++];
435 tex
.src_rel
= bytes
[bytes_read
++];
436 tex
.dst_gpr
= bytes
[bytes_read
++];
437 tex
.dst_rel
= bytes
[bytes_read
++];
438 tex
.dst_sel_x
= bytes
[bytes_read
++];
439 tex
.dst_sel_y
= bytes
[bytes_read
++];
440 tex
.dst_sel_z
= bytes
[bytes_read
++];
441 tex
.dst_sel_w
= bytes
[bytes_read
++];
442 tex
.lod_bias
= bytes
[bytes_read
++];
443 tex
.coord_type_x
= bytes
[bytes_read
++];
444 tex
.coord_type_y
= bytes
[bytes_read
++];
445 tex
.coord_type_z
= bytes
[bytes_read
++];
446 tex
.coord_type_w
= bytes
[bytes_read
++];
447 tex
.offset_x
= bytes
[bytes_read
++];
448 tex
.offset_y
= bytes
[bytes_read
++];
449 tex
.offset_z
= bytes
[bytes_read
++];
450 tex
.sampler_id
= bytes
[bytes_read
++];
451 tex
.src_sel_x
= bytes
[bytes_read
++];
452 tex
.src_sel_y
= bytes
[bytes_read
++];
453 tex
.src_sel_z
= bytes
[bytes_read
++];
454 tex
.src_sel_w
= bytes
[bytes_read
++];
456 r600_bytecode_add_tex(ctx
->bc
, &tex
);
461 static int r600_vtx_from_byte_stream(struct r600_shader_ctx
*ctx
,
462 unsigned char * bytes
, unsigned bytes_read
)
464 struct r600_bytecode_vtx vtx
;
466 uint32_t word0
= i32_from_byte_stream(bytes
, &bytes_read
);
467 uint32_t word1
= i32_from_byte_stream(bytes
, &bytes_read
);
468 uint32_t word2
= i32_from_byte_stream(bytes
, &bytes_read
);
470 memset(&vtx
, 0, sizeof(vtx
));
473 vtx
.inst
= G_SQ_VTX_WORD0_VTX_INST(word0
);
474 vtx
.fetch_type
= G_SQ_VTX_WORD0_FETCH_TYPE(word0
);
475 vtx
.buffer_id
= G_SQ_VTX_WORD0_BUFFER_ID(word0
);
476 vtx
.src_gpr
= G_SQ_VTX_WORD0_SRC_GPR(word0
);
477 vtx
.src_sel_x
= G_SQ_VTX_WORD0_SRC_SEL_X(word0
);
478 vtx
.mega_fetch_count
= G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(word0
);
481 vtx
.dst_gpr
= G_SQ_VTX_WORD1_GPR_DST_GPR(word1
);
482 vtx
.dst_sel_x
= G_SQ_VTX_WORD1_DST_SEL_X(word1
);
483 vtx
.dst_sel_y
= G_SQ_VTX_WORD1_DST_SEL_Y(word1
);
484 vtx
.dst_sel_z
= G_SQ_VTX_WORD1_DST_SEL_Z(word1
);
485 vtx
.dst_sel_w
= G_SQ_VTX_WORD1_DST_SEL_W(word1
);
486 vtx
.use_const_fields
= G_SQ_VTX_WORD1_USE_CONST_FIELDS(word1
);
487 vtx
.data_format
= G_SQ_VTX_WORD1_DATA_FORMAT(word1
);
488 vtx
.num_format_all
= G_SQ_VTX_WORD1_NUM_FORMAT_ALL(word1
);
489 vtx
.format_comp_all
= G_SQ_VTX_WORD1_FORMAT_COMP_ALL(word1
);
490 vtx
.srf_mode_all
= G_SQ_VTX_WORD1_SRF_MODE_ALL(word1
);
493 vtx
.offset
= G_SQ_VTX_WORD2_OFFSET(word2
);
494 vtx
.endian
= G_SQ_VTX_WORD2_ENDIAN_SWAP(word2
);
496 if (r600_bytecode_add_vtx(ctx
->bc
, &vtx
)) {
497 fprintf(stderr
, "Error adding vtx\n");
499 /* Use the Texture Cache */
500 ctx
->bc
->cf_last
->inst
= EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
;
504 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx
*ctx
,
505 unsigned char * bytes
, unsigned num_bytes
)
507 unsigned bytes_read
= 0;
509 while (bytes_read
< num_bytes
) {
510 char inst_type
= bytes
[bytes_read
++];
513 bytes_read
= r600_alu_from_byte_stream(ctx
, bytes
,
517 bytes_read
= r600_tex_from_byte_stream(ctx
, bytes
,
521 bytes_read
= r600_fc_from_byte_stream(ctx
, bytes
,
525 r600_bytecode_add_cfinst(ctx
->bc
, CF_NATIVE
);
526 for (i
= 0; i
< 2; i
++) {
527 for (byte
= 0 ; byte
< 4; byte
++) {
528 ctx
->bc
->cf_last
->isa
[i
] |=
529 (bytes
[bytes_read
++] << (byte
* 8));
535 bytes_read
= r600_vtx_from_byte_stream(ctx
, bytes
,
539 /* XXX: Error here */
545 /* End bytestream -> r600 shader functions*/
547 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
549 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
552 if (i
->Instruction
.NumDstRegs
> 1) {
553 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
556 if (i
->Instruction
.Predicate
) {
557 R600_ERR("predicate unsupported\n");
561 if (i
->Instruction
.Label
) {
562 R600_ERR("label unsupported\n");
566 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
567 if (i
->Src
[j
].Register
.Dimension
) {
568 R600_ERR("unsupported src %d (dimension %d)\n", j
,
569 i
->Src
[j
].Register
.Dimension
);
573 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
574 if (i
->Dst
[j
].Register
.Dimension
) {
575 R600_ERR("unsupported dst (dimension)\n");
582 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
585 struct r600_bytecode_alu alu
;
586 int gpr
= 0, base_chan
= 0;
589 if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
) {
591 if (ctx
->shader
->input
[input
].centroid
)
593 } else if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
595 /* if we have perspective add one */
596 if (ctx
->input_perspective
) {
598 /* if we have perspective centroid */
599 if (ctx
->input_centroid
)
602 if (ctx
->shader
->input
[input
].centroid
)
606 /* work out gpr and base_chan from index */
608 base_chan
= (2 * (ij_index
% 2)) + 1;
610 for (i
= 0; i
< 8; i
++) {
611 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
614 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW
;
616 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY
;
618 if ((i
> 1) && (i
< 6)) {
619 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
623 alu
.dst
.chan
= i
% 4;
625 alu
.src
[0].sel
= gpr
;
626 alu
.src
[0].chan
= (base_chan
- (i
% 2));
628 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
630 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
633 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
640 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
643 struct r600_bytecode_alu alu
;
645 for (i
= 0; i
< 4; i
++) {
646 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
648 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0
;
650 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
655 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
660 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
668 * Special export handling in shaders
670 * shader export ARRAY_BASE for EXPORT_POS:
673 * 62, 63 are clip distance vectors
675 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
676 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
677 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
678 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
679 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
680 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
681 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
682 * exclusive from render target index)
683 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
686 * shader export ARRAY_BASE for EXPORT_PIXEL:
688 * 61 computed Z vector
690 * The use of the values exported in the computed Z vector are controlled
691 * by DB_SHADER_CONTROL:
692 * Z_EXPORT_ENABLE - Z as a float in RED
693 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
694 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
695 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
696 * DB_SOURCE_FORMAT - export control restrictions
701 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
702 static int r600_spi_sid(struct r600_shader_io
* io
)
704 int index
, name
= io
->name
;
706 /* These params are handled differently, they don't need
707 * semantic indices, so we'll use 0 for them.
709 if (name
== TGSI_SEMANTIC_POSITION
||
710 name
== TGSI_SEMANTIC_PSIZE
||
711 name
== TGSI_SEMANTIC_FACE
)
714 if (name
== TGSI_SEMANTIC_GENERIC
) {
715 /* For generic params simply use sid from tgsi */
718 /* For non-generic params - pack name and sid into 8 bits */
719 index
= 0x80 | (name
<<3) | (io
->sid
);
722 /* Make sure that all really used indices have nonzero value, so
723 * we can just compare it to 0 later instead of comparing the name
724 * with different values to detect special cases. */
731 /* turn input into interpolate on EG */
732 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
736 if (ctx
->shader
->input
[index
].spi_sid
) {
737 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
738 if (ctx
->shader
->input
[index
].interpolate
> 0) {
739 r
= evergreen_interp_alu(ctx
, index
);
741 r
= evergreen_interp_flat(ctx
, index
);
747 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
749 struct r600_bytecode_alu alu
;
751 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
752 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
754 for (i
= 0; i
< 4; i
++) {
755 memset(&alu
, 0, sizeof(alu
));
756 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
759 alu
.dst
.sel
= gpr_front
;
760 alu
.src
[0].sel
= ctx
->face_gpr
;
761 alu
.src
[1].sel
= gpr_front
;
762 alu
.src
[2].sel
= gpr_back
;
769 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
776 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
778 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
782 switch (d
->Declaration
.File
) {
783 case TGSI_FILE_INPUT
:
784 i
= ctx
->shader
->ninput
++;
785 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
786 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
787 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
788 ctx
->shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
789 ctx
->shader
->input
[i
].centroid
= d
->Interp
.Centroid
;
790 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
;
791 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
792 switch (ctx
->shader
->input
[i
].name
) {
793 case TGSI_SEMANTIC_FACE
:
794 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
796 case TGSI_SEMANTIC_COLOR
:
799 case TGSI_SEMANTIC_POSITION
:
800 ctx
->fragcoord_input
= i
;
803 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
804 if ((r
= evergreen_interp_input(ctx
, i
)))
809 case TGSI_FILE_OUTPUT
:
810 i
= ctx
->shader
->noutput
++;
811 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
812 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
813 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
814 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
;
815 ctx
->shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
816 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
817 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
818 switch (d
->Semantic
.Name
) {
819 case TGSI_SEMANTIC_CLIPDIST
:
820 ctx
->shader
->clip_dist_write
|= d
->Declaration
.UsageMask
<< (d
->Semantic
.Index
<< 2);
822 case TGSI_SEMANTIC_PSIZE
:
823 ctx
->shader
->vs_out_misc_write
= 1;
824 ctx
->shader
->vs_out_point_size
= 1;
826 case TGSI_SEMANTIC_CLIPVERTEX
:
827 ctx
->clip_vertex_write
= TRUE
;
831 } else if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
832 switch (d
->Semantic
.Name
) {
833 case TGSI_SEMANTIC_COLOR
:
834 ctx
->shader
->nr_ps_max_color_exports
++;
839 case TGSI_FILE_CONSTANT
:
840 case TGSI_FILE_TEMPORARY
:
841 case TGSI_FILE_SAMPLER
:
842 case TGSI_FILE_ADDRESS
:
845 case TGSI_FILE_SYSTEM_VALUE
:
846 if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
847 if (!ctx
->native_integers
) {
848 struct r600_bytecode_alu alu
;
849 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
851 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
);
860 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
864 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
867 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
873 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
875 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
879 * for evergreen we need to scan the shader to find the number of GPRs we need to
880 * reserve for interpolation.
882 * we need to know if we are going to emit
883 * any centroid inputs
884 * if perspective and linear are required
886 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
891 ctx
->input_linear
= FALSE
;
892 ctx
->input_perspective
= FALSE
;
893 ctx
->input_centroid
= FALSE
;
894 ctx
->num_interp_gpr
= 1;
896 /* any centroid inputs */
897 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
898 /* skip position/face */
899 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
900 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
)
902 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_LINEAR
)
903 ctx
->input_linear
= TRUE
;
904 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_PERSPECTIVE
)
905 ctx
->input_perspective
= TRUE
;
906 if (ctx
->info
.input_centroid
[i
])
907 ctx
->input_centroid
= TRUE
;
911 /* ignoring sample for now */
912 if (ctx
->input_perspective
)
914 if (ctx
->input_linear
)
916 if (ctx
->input_centroid
)
919 ctx
->num_interp_gpr
+= (num_baryc
+ 1) >> 1;
921 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
922 return ctx
->num_interp_gpr
;
925 static void tgsi_src(struct r600_shader_ctx
*ctx
,
926 const struct tgsi_full_src_register
*tgsi_src
,
927 struct r600_shader_src
*r600_src
)
929 memset(r600_src
, 0, sizeof(*r600_src
));
930 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
931 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
932 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
933 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
934 r600_src
->neg
= tgsi_src
->Register
.Negate
;
935 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
937 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
939 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
940 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
941 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
943 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
944 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
);
945 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
948 index
= tgsi_src
->Register
.Index
;
949 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
950 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
951 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
952 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
953 r600_src
->swizzle
[0] = 3;
954 r600_src
->swizzle
[1] = 3;
955 r600_src
->swizzle
[2] = 3;
956 r600_src
->swizzle
[3] = 3;
958 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
959 r600_src
->swizzle
[0] = 0;
960 r600_src
->swizzle
[1] = 0;
961 r600_src
->swizzle
[2] = 0;
962 r600_src
->swizzle
[3] = 0;
966 if (tgsi_src
->Register
.Indirect
)
967 r600_src
->rel
= V_SQ_REL_RELATIVE
;
968 r600_src
->sel
= tgsi_src
->Register
.Index
;
969 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
973 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
, unsigned int offset
, unsigned int dst_reg
)
975 struct r600_bytecode_vtx vtx
;
980 struct r600_bytecode_alu alu
;
982 memset(&alu
, 0, sizeof(alu
));
984 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
985 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
987 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
988 alu
.src
[1].value
= offset
;
990 alu
.dst
.sel
= dst_reg
;
994 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
999 ar_reg
= ctx
->bc
->ar_reg
;
1002 memset(&vtx
, 0, sizeof(vtx
));
1003 vtx
.fetch_type
= 2; /* VTX_FETCH_NO_INDEX_OFFSET */
1004 vtx
.src_gpr
= ar_reg
;
1005 vtx
.mega_fetch_count
= 16;
1006 vtx
.dst_gpr
= dst_reg
;
1007 vtx
.dst_sel_x
= 0; /* SEL_X */
1008 vtx
.dst_sel_y
= 1; /* SEL_Y */
1009 vtx
.dst_sel_z
= 2; /* SEL_Z */
1010 vtx
.dst_sel_w
= 3; /* SEL_W */
1011 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1012 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
1013 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
1014 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
1015 vtx
.endian
= r600_endian_swap(32);
1017 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1023 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
1025 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1026 struct r600_bytecode_alu alu
;
1027 int i
, j
, k
, nconst
, r
;
1029 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1030 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
1033 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
1035 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1036 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
1040 if (ctx
->src
[i
].rel
) {
1041 int treg
= r600_get_temp(ctx
);
1042 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].sel
- 512, treg
)))
1045 ctx
->src
[i
].sel
= treg
;
1046 ctx
->src
[i
].rel
= 0;
1049 int treg
= r600_get_temp(ctx
);
1050 for (k
= 0; k
< 4; k
++) {
1051 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1052 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1053 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1054 alu
.src
[0].chan
= k
;
1055 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
1061 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1065 ctx
->src
[i
].sel
= treg
;
1073 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1074 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
1076 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1077 struct r600_bytecode_alu alu
;
1078 int i
, j
, k
, nliteral
, r
;
1080 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1081 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1085 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1086 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1087 int treg
= r600_get_temp(ctx
);
1088 for (k
= 0; k
< 4; k
++) {
1089 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1090 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1091 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1092 alu
.src
[0].chan
= k
;
1093 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
1099 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1103 ctx
->src
[i
].sel
= treg
;
1110 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
1112 int i
, r
, count
= ctx
->shader
->ninput
;
1114 /* additional inputs will be allocated right after the existing inputs,
1115 * we won't need them after the color selection, so we don't need to
1116 * reserve these gprs for the rest of the shader code and to adjust
1117 * output offsets etc. */
1118 int gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] +
1119 ctx
->info
.file_max
[TGSI_FILE_INPUT
] + 1;
1121 if (ctx
->face_gpr
== -1) {
1122 i
= ctx
->shader
->ninput
++;
1123 ctx
->shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
1124 ctx
->shader
->input
[i
].spi_sid
= 0;
1125 ctx
->shader
->input
[i
].gpr
= gpr
++;
1126 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
1129 for (i
= 0; i
< count
; i
++) {
1130 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1131 int ni
= ctx
->shader
->ninput
++;
1132 memcpy(&ctx
->shader
->input
[ni
],&ctx
->shader
->input
[i
], sizeof(struct r600_shader_io
));
1133 ctx
->shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
1134 ctx
->shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[ni
]);
1135 ctx
->shader
->input
[ni
].gpr
= gpr
++;
1137 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1138 r
= evergreen_interp_input(ctx
, ni
);
1143 r
= select_twoside_color(ctx
, i
, ni
);
1151 static int r600_shader_from_tgsi(struct r600_context
* rctx
, struct r600_pipe_shader
*pipeshader
)
1153 struct r600_shader
*shader
= &pipeshader
->shader
;
1154 struct tgsi_token
*tokens
= pipeshader
->selector
->tokens
;
1155 struct pipe_stream_output_info so
= pipeshader
->selector
->so
;
1156 struct tgsi_full_immediate
*immediate
;
1157 struct tgsi_full_property
*property
;
1158 struct r600_shader_ctx ctx
;
1159 struct r600_bytecode_output output
[32];
1160 unsigned output_done
, noutput
;
1163 int next_pixel_base
= 0, next_pos_base
= 60, next_param_base
= 0;
1164 /* Declarations used by llvm code */
1165 bool use_llvm
= false;
1166 unsigned char * inst_bytes
= NULL
;
1167 unsigned inst_byte_count
= 0;
1169 #ifdef R600_USE_LLVM
1170 use_llvm
= debug_get_bool_option("R600_LLVM", TRUE
);
1172 ctx
.bc
= &shader
->bc
;
1173 ctx
.shader
= shader
;
1174 ctx
.native_integers
= true;
1176 r600_bytecode_init(ctx
.bc
, rctx
->chip_class
, rctx
->family
);
1177 ctx
.tokens
= tokens
;
1178 tgsi_scan_shader(tokens
, &ctx
.info
);
1179 tgsi_parse_init(&ctx
.parse
, tokens
);
1180 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
1181 shader
->processor_type
= ctx
.type
;
1182 ctx
.bc
->type
= shader
->processor_type
;
1185 ctx
.fragcoord_input
= -1;
1186 ctx
.colors_used
= 0;
1187 ctx
.clip_vertex_write
= 0;
1189 shader
->nr_ps_color_exports
= 0;
1190 shader
->nr_ps_max_color_exports
= 0;
1192 shader
->two_side
= (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
) && rctx
->two_side
;
1194 /* register allocations */
1195 /* Values [0,127] correspond to GPR[0..127].
1196 * Values [128,159] correspond to constant buffer bank 0
1197 * Values [160,191] correspond to constant buffer bank 1
1198 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1199 * Values [256,287] correspond to constant buffer bank 2 (EG)
1200 * Values [288,319] correspond to constant buffer bank 3 (EG)
1201 * Other special values are shown in the list below.
1202 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1203 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1204 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1205 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1206 * 248 SQ_ALU_SRC_0: special constant 0.0.
1207 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1208 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1209 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1210 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1211 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1212 * 254 SQ_ALU_SRC_PV: previous vector result.
1213 * 255 SQ_ALU_SRC_PS: previous scalar result.
1215 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
1216 ctx
.file_offset
[i
] = 0;
1218 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
1219 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
1220 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
1221 r600_bytecode_add_cfinst(ctx
.bc
, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
1223 r600_bytecode_add_cfinst(ctx
.bc
, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
1226 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
.bc
->chip_class
>= EVERGREEN
) {
1227 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
1230 /* LLVM backend setup */
1231 #ifdef R600_USE_LLVM
1232 if (use_llvm
&& ctx
.info
.indirect_files
) {
1233 fprintf(stderr
, "Warning: R600 LLVM backend does not support "
1234 "indirect adressing. Falling back to TGSI "
1239 struct radeon_llvm_context radeon_llvm_ctx
;
1242 memset(&radeon_llvm_ctx
, 0, sizeof(radeon_llvm_ctx
));
1243 radeon_llvm_ctx
.reserved_reg_count
= ctx
.file_offset
[TGSI_FILE_INPUT
];
1244 mod
= r600_tgsi_llvm(&radeon_llvm_ctx
, tokens
);
1245 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE
)) {
1248 if (r600_llvm_compile(mod
, &inst_bytes
, &inst_byte_count
,
1249 rctx
->family
, dump
)) {
1251 radeon_llvm_dispose(&radeon_llvm_ctx
);
1253 fprintf(stderr
, "R600 LLVM backend failed to compile "
1254 "shader. Falling back to TGSI\n");
1256 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
1257 ctx
.file_offset
[TGSI_FILE_INPUT
];
1259 radeon_llvm_dispose(&radeon_llvm_ctx
);
1262 /* End of LLVM backend setup */
1265 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
1266 ctx
.file_offset
[TGSI_FILE_INPUT
] +
1267 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
1269 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
1270 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
1272 /* Outside the GPR range. This will be translated to one of the
1273 * kcache banks later. */
1274 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
1276 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
1277 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
1278 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
1279 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 1;
1282 ctx
.literals
= NULL
;
1283 shader
->fs_write_all
= FALSE
;
1284 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
1285 tgsi_parse_token(&ctx
.parse
);
1286 switch (ctx
.parse
.FullToken
.Token
.Type
) {
1287 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1288 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
1289 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
1290 if(ctx
.literals
== NULL
) {
1294 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
1295 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
1296 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
1297 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
1300 case TGSI_TOKEN_TYPE_DECLARATION
:
1301 r
= tgsi_declaration(&ctx
);
1305 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1307 case TGSI_TOKEN_TYPE_PROPERTY
:
1308 property
= &ctx
.parse
.FullToken
.FullProperty
;
1309 switch (property
->Property
.PropertyName
) {
1310 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
:
1311 if (property
->u
[0].Data
== 1)
1312 shader
->fs_write_all
= TRUE
;
1314 case TGSI_PROPERTY_VS_PROHIBIT_UCPS
:
1315 if (property
->u
[0].Data
== 1)
1316 shader
->vs_prohibit_ucps
= TRUE
;
1321 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
1327 if (shader
->fs_write_all
&& rctx
->chip_class
>= EVERGREEN
)
1328 shader
->nr_ps_max_color_exports
= 8;
1330 if (ctx
.fragcoord_input
>= 0) {
1331 if (ctx
.bc
->chip_class
== CAYMAN
) {
1332 for (j
= 0 ; j
< 4; j
++) {
1333 struct r600_bytecode_alu alu
;
1334 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1335 alu
.inst
= BC_INST(ctx
.bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1336 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
1337 alu
.src
[0].chan
= 3;
1339 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
1341 alu
.dst
.write
= (j
== 3);
1343 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
1347 struct r600_bytecode_alu alu
;
1348 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1349 alu
.inst
= BC_INST(ctx
.bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1350 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
1351 alu
.src
[0].chan
= 3;
1353 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
1357 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
1362 if (shader
->two_side
&& ctx
.colors_used
) {
1363 if ((r
= process_twoside_color_inputs(&ctx
)))
1367 tgsi_parse_init(&ctx
.parse
, tokens
);
1368 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
1369 tgsi_parse_token(&ctx
.parse
);
1370 switch (ctx
.parse
.FullToken
.Token
.Type
) {
1371 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1375 r
= tgsi_is_supported(&ctx
);
1378 ctx
.max_driver_temp_used
= 0;
1379 /* reserve first tmp for everyone */
1380 r600_get_temp(&ctx
);
1382 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
1383 if ((r
= tgsi_split_constant(&ctx
)))
1385 if ((r
= tgsi_split_literal_constant(&ctx
)))
1387 if (ctx
.bc
->chip_class
== CAYMAN
)
1388 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
1389 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
1390 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
1392 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
1393 r
= ctx
.inst_info
->process(&ctx
);
1402 /* Get instructions if we are using the LLVM backend. */
1404 r600_bytecode_from_byte_stream(&ctx
, inst_bytes
, inst_byte_count
);
1408 noutput
= shader
->noutput
;
1410 if (ctx
.clip_vertex_write
) {
1411 /* need to convert a clipvertex write into clipdistance writes and not export
1412 the clip vertex anymore */
1414 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
1415 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
1416 shader
->output
[noutput
].gpr
= ctx
.temp_reg
;
1418 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
1419 shader
->output
[noutput
].gpr
= ctx
.temp_reg
+1;
1422 /* reset spi_sid for clipvertex output to avoid confusing spi */
1423 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
1425 shader
->clip_dist_write
= 0xFF;
1427 for (i
= 0; i
< 8; i
++) {
1431 for (j
= 0; j
< 4; j
++) {
1432 struct r600_bytecode_alu alu
;
1433 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1434 alu
.inst
= BC_INST(ctx
.bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
);
1435 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
1436 alu
.src
[0].chan
= j
;
1438 alu
.src
[1].sel
= 512 + i
;
1439 alu
.src
[1].kc_bank
= 1;
1440 alu
.src
[1].chan
= j
;
1442 alu
.dst
.sel
= ctx
.temp_reg
+ oreg
;
1444 alu
.dst
.write
= (j
== ochan
);
1447 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
1454 /* Add stream outputs. */
1455 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
&& so
.num_outputs
) {
1456 for (i
= 0; i
< so
.num_outputs
; i
++) {
1457 struct r600_bytecode_output output
;
1459 if (so
.output
[i
].output_buffer
>= 4) {
1460 R600_ERR("exceeded the max number of stream output buffers, got: %d\n",
1461 so
.output
[i
].output_buffer
);
1465 if (so
.output
[i
].dst_offset
< so
.output
[i
].start_component
) {
1466 R600_ERR("stream_output - dst_offset cannot be less than start_component\n");
1471 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
1472 output
.gpr
= shader
->output
[so
.output
[i
].register_index
].gpr
;
1473 output
.elem_size
= 0;
1474 output
.array_base
= so
.output
[i
].dst_offset
- so
.output
[i
].start_component
;
1475 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
1476 output
.burst_count
= 1;
1478 /* array_size is an upper limit for the burst_count
1479 * with MEM_STREAM instructions */
1480 output
.array_size
= 0xFFF;
1481 output
.comp_mask
= ((1 << so
.output
[i
].num_components
) - 1) << so
.output
[i
].start_component
;
1482 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
1483 switch (so
.output
[i
].output_buffer
) {
1485 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
;
1488 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
;
1491 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
;
1494 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
;
1498 switch (so
.output
[i
].output_buffer
) {
1500 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
;
1503 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
;
1506 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
;
1509 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
;
1513 r
= r600_bytecode_add_output(ctx
.bc
, &output
);
1520 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
1521 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1522 output
[j
].gpr
= shader
->output
[i
].gpr
;
1523 output
[j
].elem_size
= 3;
1524 output
[j
].swizzle_x
= 0;
1525 output
[j
].swizzle_y
= 1;
1526 output
[j
].swizzle_z
= 2;
1527 output
[j
].swizzle_w
= 3;
1528 output
[j
].burst_count
= 1;
1529 output
[j
].barrier
= 1;
1530 output
[j
].type
= -1;
1531 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1533 case TGSI_PROCESSOR_VERTEX
:
1534 switch (shader
->output
[i
].name
) {
1535 case TGSI_SEMANTIC_POSITION
:
1536 output
[j
].array_base
= next_pos_base
++;
1537 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1540 case TGSI_SEMANTIC_PSIZE
:
1541 output
[j
].array_base
= next_pos_base
++;
1542 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1544 case TGSI_SEMANTIC_CLIPVERTEX
:
1547 case TGSI_SEMANTIC_CLIPDIST
:
1548 output
[j
].array_base
= next_pos_base
++;
1549 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1550 /* spi_sid is 0 for clipdistance outputs that were generated
1551 * for clipvertex - we don't need to pass them to PS */
1552 if (shader
->output
[i
].spi_sid
) {
1554 /* duplicate it as PARAM to pass to the pixel shader */
1555 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
1556 output
[j
].array_base
= next_param_base
++;
1557 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1560 case TGSI_SEMANTIC_FOG
:
1561 output
[j
].swizzle_y
= 4; /* 0 */
1562 output
[j
].swizzle_z
= 4; /* 0 */
1563 output
[j
].swizzle_w
= 5; /* 1 */
1567 case TGSI_PROCESSOR_FRAGMENT
:
1568 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1569 /* never export more colors than the number of CBs */
1570 if (next_pixel_base
&& next_pixel_base
>= (rctx
->nr_cbufs
+ rctx
->dual_src_blend
* 1)) {
1575 output
[j
].swizzle_w
= rctx
->alpha_to_one
&& rctx
->multisample_enable
&& !rctx
->cb0_is_integer
? 5 : 3;
1576 output
[j
].array_base
= next_pixel_base
++;
1577 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1578 shader
->nr_ps_color_exports
++;
1579 if (shader
->fs_write_all
&& (rctx
->chip_class
>= EVERGREEN
)) {
1580 for (k
= 1; k
< rctx
->nr_cbufs
; k
++) {
1582 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1583 output
[j
].gpr
= shader
->output
[i
].gpr
;
1584 output
[j
].elem_size
= 3;
1585 output
[j
].swizzle_x
= 0;
1586 output
[j
].swizzle_y
= 1;
1587 output
[j
].swizzle_z
= 2;
1588 output
[j
].swizzle_w
= rctx
->alpha_to_one
&& rctx
->multisample_enable
&& !rctx
->cb0_is_integer
? 5 : 3;
1589 output
[j
].burst_count
= 1;
1590 output
[j
].barrier
= 1;
1591 output
[j
].array_base
= next_pixel_base
++;
1592 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1593 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1594 shader
->nr_ps_color_exports
++;
1597 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
1598 output
[j
].array_base
= 61;
1599 output
[j
].swizzle_x
= 2;
1600 output
[j
].swizzle_y
= 7;
1601 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
1602 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1603 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
1604 output
[j
].array_base
= 61;
1605 output
[j
].swizzle_x
= 7;
1606 output
[j
].swizzle_y
= 1;
1607 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
1608 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1610 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
1616 R600_ERR("unsupported processor type %d\n", ctx
.type
);
1621 if (output
[j
].type
==-1) {
1622 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1623 output
[j
].array_base
= next_param_base
++;
1627 /* add fake param output for vertex shader if no param is exported */
1628 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
&& next_param_base
== 0) {
1629 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1631 output
[j
].elem_size
= 3;
1632 output
[j
].swizzle_x
= 7;
1633 output
[j
].swizzle_y
= 7;
1634 output
[j
].swizzle_z
= 7;
1635 output
[j
].swizzle_w
= 7;
1636 output
[j
].burst_count
= 1;
1637 output
[j
].barrier
= 1;
1638 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1639 output
[j
].array_base
= 0;
1640 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1644 /* add fake pixel export */
1645 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& next_pixel_base
== 0) {
1646 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1648 output
[j
].elem_size
= 3;
1649 output
[j
].swizzle_x
= 7;
1650 output
[j
].swizzle_y
= 7;
1651 output
[j
].swizzle_z
= 7;
1652 output
[j
].swizzle_w
= 7;
1653 output
[j
].burst_count
= 1;
1654 output
[j
].barrier
= 1;
1655 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1656 output
[j
].array_base
= 0;
1657 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1663 /* set export done on last export of each type */
1664 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
1665 if (ctx
.bc
->chip_class
< CAYMAN
) {
1666 if (i
== (noutput
- 1)) {
1667 output
[i
].end_of_program
= 1;
1670 if (!(output_done
& (1 << output
[i
].type
))) {
1671 output_done
|= (1 << output
[i
].type
);
1672 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
);
1675 /* add output to bytecode */
1676 for (i
= 0; i
< noutput
; i
++) {
1677 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
1681 /* add program end */
1682 if (ctx
.bc
->chip_class
== CAYMAN
)
1683 cm_bytecode_add_cf_end(ctx
.bc
);
1685 /* check GPR limit - we have 124 = 128 - 4
1686 * (4 are reserved as alu clause temporary registers) */
1687 if (ctx
.bc
->ngpr
> 124) {
1688 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx
.bc
->ngpr
);
1694 tgsi_parse_free(&ctx
.parse
);
1698 tgsi_parse_free(&ctx
.parse
);
1702 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
1704 R600_ERR("%s tgsi opcode unsupported\n",
1705 tgsi_get_opcode_name(ctx
->inst_info
->tgsi_opcode
));
1709 static int tgsi_end(struct r600_shader_ctx
*ctx
)
1714 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
1715 const struct r600_shader_src
*shader_src
,
1718 bc_src
->sel
= shader_src
->sel
;
1719 bc_src
->chan
= shader_src
->swizzle
[chan
];
1720 bc_src
->neg
= shader_src
->neg
;
1721 bc_src
->abs
= shader_src
->abs
;
1722 bc_src
->rel
= shader_src
->rel
;
1723 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
1726 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
1732 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
1734 bc_src
->neg
= !bc_src
->neg
;
1737 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
1738 const struct tgsi_full_dst_register
*tgsi_dst
,
1740 struct r600_bytecode_alu_dst
*r600_dst
)
1742 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1744 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
1745 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
1746 r600_dst
->chan
= swizzle
;
1747 r600_dst
->write
= 1;
1748 if (tgsi_dst
->Register
.Indirect
)
1749 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
1750 if (inst
->Instruction
.Saturate
) {
1751 r600_dst
->clamp
= 1;
1755 static int tgsi_last_instruction(unsigned writemask
)
1759 for (i
= 0; i
< 4; i
++) {
1760 if (writemask
& (1 << i
)) {
1767 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
1769 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1770 struct r600_bytecode_alu alu
;
1772 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1774 for (i
= 0; i
< lasti
+ 1; i
++) {
1775 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1778 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1779 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1781 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1783 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1784 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
1787 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
1788 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
1790 /* handle some special cases */
1791 switch (ctx
->inst_info
->tgsi_opcode
) {
1792 case TGSI_OPCODE_SUB
:
1793 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
1795 case TGSI_OPCODE_ABS
:
1796 r600_bytecode_src_set_abs(&alu
.src
[0]);
1801 if (i
== lasti
|| trans_only
) {
1804 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1811 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
1813 return tgsi_op2_s(ctx
, 0, 0);
1816 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
1818 return tgsi_op2_s(ctx
, 1, 0);
1821 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
1823 return tgsi_op2_s(ctx
, 0, 1);
1826 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
1828 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1829 struct r600_bytecode_alu alu
;
1831 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1833 for (i
= 0; i
< lasti
+ 1; i
++) {
1835 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1837 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1838 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1840 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1842 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
1844 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1849 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1857 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
1859 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1861 struct r600_bytecode_alu alu
;
1862 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
1864 for (i
= 0 ; i
< last_slot
; i
++) {
1865 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1866 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1867 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1868 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
1870 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1871 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1873 if (i
== last_slot
- 1)
1875 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1882 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
1884 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1886 struct r600_bytecode_alu alu
;
1887 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
1888 for (k
= 0; k
< last_slot
; k
++) {
1889 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
1892 for (i
= 0 ; i
< 4; i
++) {
1893 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1894 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1895 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1896 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
1898 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1899 alu
.dst
.write
= (i
== k
);
1902 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1911 * r600 - trunc to -PI..PI range
1912 * r700 - normalize by dividing by 2PI
1915 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
1917 static float half_inv_pi
= 1.0 /(3.1415926535 * 2);
1918 static float double_pi
= 3.1415926535 * 2;
1919 static float neg_pi
= -3.1415926535;
1922 struct r600_bytecode_alu alu
;
1924 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1925 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1929 alu
.dst
.sel
= ctx
->temp_reg
;
1932 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
1934 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1935 alu
.src
[1].chan
= 0;
1936 alu
.src
[1].value
= *(uint32_t *)&half_inv_pi
;
1937 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
1938 alu
.src
[2].chan
= 0;
1940 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1944 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1945 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
1948 alu
.dst
.sel
= ctx
->temp_reg
;
1951 alu
.src
[0].sel
= ctx
->temp_reg
;
1952 alu
.src
[0].chan
= 0;
1954 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1958 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1959 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1963 alu
.dst
.sel
= ctx
->temp_reg
;
1966 alu
.src
[0].sel
= ctx
->temp_reg
;
1967 alu
.src
[0].chan
= 0;
1969 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1970 alu
.src
[1].chan
= 0;
1971 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1972 alu
.src
[2].chan
= 0;
1974 if (ctx
->bc
->chip_class
== R600
) {
1975 alu
.src
[1].value
= *(uint32_t *)&double_pi
;
1976 alu
.src
[2].value
= *(uint32_t *)&neg_pi
;
1978 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1979 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
1984 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1990 static int cayman_trig(struct r600_shader_ctx
*ctx
)
1992 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1993 struct r600_bytecode_alu alu
;
1994 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
1997 r
= tgsi_setup_trig(ctx
);
2002 for (i
= 0; i
< last_slot
; i
++) {
2003 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2004 alu
.inst
= ctx
->inst_info
->r600_opcode
;
2007 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2008 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
2010 alu
.src
[0].sel
= ctx
->temp_reg
;
2011 alu
.src
[0].chan
= 0;
2012 if (i
== last_slot
- 1)
2014 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2021 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
2023 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2024 struct r600_bytecode_alu alu
;
2026 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
2028 r
= tgsi_setup_trig(ctx
);
2032 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2033 alu
.inst
= ctx
->inst_info
->r600_opcode
;
2035 alu
.dst
.sel
= ctx
->temp_reg
;
2038 alu
.src
[0].sel
= ctx
->temp_reg
;
2039 alu
.src
[0].chan
= 0;
2041 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2045 /* replicate result */
2046 for (i
= 0; i
< lasti
+ 1; i
++) {
2047 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
2050 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2051 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2053 alu
.src
[0].sel
= ctx
->temp_reg
;
2054 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2057 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2064 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
2066 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2067 struct r600_bytecode_alu alu
;
2070 /* We'll only need the trig stuff if we are going to write to the
2071 * X or Y components of the destination vector.
2073 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
2074 r
= tgsi_setup_trig(ctx
);
2080 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2081 if (ctx
->bc
->chip_class
== CAYMAN
) {
2082 for (i
= 0 ; i
< 3; i
++) {
2083 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2084 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
2085 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2091 alu
.src
[0].sel
= ctx
->temp_reg
;
2092 alu
.src
[0].chan
= 0;
2095 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2100 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2101 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
2102 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
2104 alu
.src
[0].sel
= ctx
->temp_reg
;
2105 alu
.src
[0].chan
= 0;
2107 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2114 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2115 if (ctx
->bc
->chip_class
== CAYMAN
) {
2116 for (i
= 0 ; i
< 3; i
++) {
2117 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2118 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
2119 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2124 alu
.src
[0].sel
= ctx
->temp_reg
;
2125 alu
.src
[0].chan
= 0;
2128 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2133 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2134 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
2135 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
2137 alu
.src
[0].sel
= ctx
->temp_reg
;
2138 alu
.src
[0].chan
= 0;
2140 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2147 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2148 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2150 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2152 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
2154 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2155 alu
.src
[0].chan
= 0;
2159 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2165 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2166 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2168 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2170 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
2172 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2173 alu
.src
[0].chan
= 0;
2177 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2185 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
2187 struct r600_bytecode_alu alu
;
2190 for (i
= 0; i
< 4; i
++) {
2191 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2192 alu
.inst
= ctx
->inst_info
->r600_opcode
;
2196 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2198 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILP
) {
2199 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
2202 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2207 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2212 /* kill must be last in ALU */
2213 ctx
->bc
->force_add_cf
= 1;
2214 ctx
->shader
->uses_kill
= TRUE
;
2218 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
2220 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2221 struct r600_bytecode_alu alu
;
2224 /* tmp.x = max(src.y, 0.0) */
2225 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2226 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
2227 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
2228 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
2229 alu
.src
[1].chan
= 1;
2231 alu
.dst
.sel
= ctx
->temp_reg
;
2236 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2240 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
2246 if (ctx
->bc
->chip_class
== CAYMAN
) {
2247 for (i
= 0; i
< 3; i
++) {
2248 /* tmp.z = log(tmp.x) */
2249 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2250 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
2251 alu
.src
[0].sel
= ctx
->temp_reg
;
2252 alu
.src
[0].chan
= 0;
2253 alu
.dst
.sel
= ctx
->temp_reg
;
2261 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2266 /* tmp.z = log(tmp.x) */
2267 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2268 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
2269 alu
.src
[0].sel
= ctx
->temp_reg
;
2270 alu
.src
[0].chan
= 0;
2271 alu
.dst
.sel
= ctx
->temp_reg
;
2275 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2280 chan
= alu
.dst
.chan
;
2283 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2284 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2285 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
);
2286 alu
.src
[0].sel
= sel
;
2287 alu
.src
[0].chan
= chan
;
2288 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
2289 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
2290 alu
.dst
.sel
= ctx
->temp_reg
;
2295 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2299 if (ctx
->bc
->chip_class
== CAYMAN
) {
2300 for (i
= 0; i
< 3; i
++) {
2301 /* dst.z = exp(tmp.x) */
2302 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2303 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2304 alu
.src
[0].sel
= ctx
->temp_reg
;
2305 alu
.src
[0].chan
= 0;
2306 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2312 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2317 /* dst.z = exp(tmp.x) */
2318 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2319 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2320 alu
.src
[0].sel
= ctx
->temp_reg
;
2321 alu
.src
[0].chan
= 0;
2322 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
2324 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2331 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2332 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2333 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
2334 alu
.src
[0].chan
= 0;
2335 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
2336 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
2337 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2341 /* dst.y = max(src.x, 0.0) */
2342 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2343 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
2344 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
2345 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
2346 alu
.src
[1].chan
= 0;
2347 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
2348 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
2349 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2354 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2355 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2356 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2357 alu
.src
[0].chan
= 0;
2358 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
2359 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
2361 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2368 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
2370 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2371 struct r600_bytecode_alu alu
;
2374 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2377 * For state trackers other than OpenGL, we'll want to use
2378 * _RECIPSQRT_IEEE instead.
2380 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
);
2382 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2383 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
2384 r600_bytecode_src_set_abs(&alu
.src
[i
]);
2386 alu
.dst
.sel
= ctx
->temp_reg
;
2389 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2392 /* replicate result */
2393 return tgsi_helper_tempx_replicate(ctx
);
2396 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
2398 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2399 struct r600_bytecode_alu alu
;
2402 for (i
= 0; i
< 4; i
++) {
2403 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2404 alu
.src
[0].sel
= ctx
->temp_reg
;
2405 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2407 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2408 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
2411 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2418 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
2420 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2421 struct r600_bytecode_alu alu
;
2424 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2425 alu
.inst
= ctx
->inst_info
->r600_opcode
;
2426 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2427 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
2429 alu
.dst
.sel
= ctx
->temp_reg
;
2432 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2435 /* replicate result */
2436 return tgsi_helper_tempx_replicate(ctx
);
2439 static int cayman_pow(struct r600_shader_ctx
*ctx
)
2441 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2443 struct r600_bytecode_alu alu
;
2444 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
2446 for (i
= 0; i
< 3; i
++) {
2447 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2448 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2449 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
2450 alu
.dst
.sel
= ctx
->temp_reg
;
2455 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2461 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2462 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2463 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
2464 alu
.src
[1].sel
= ctx
->temp_reg
;
2465 alu
.dst
.sel
= ctx
->temp_reg
;
2468 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2472 for (i
= 0; i
< last_slot
; i
++) {
2473 /* POW(a,b) = EXP2(b * LOG2(a))*/
2474 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2475 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2476 alu
.src
[0].sel
= ctx
->temp_reg
;
2478 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2479 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
2480 if (i
== last_slot
- 1)
2482 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2489 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
2491 struct r600_bytecode_alu alu
;
2495 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2496 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2497 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
2498 alu
.dst
.sel
= ctx
->temp_reg
;
2501 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2505 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2506 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2507 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
2508 alu
.src
[1].sel
= ctx
->temp_reg
;
2509 alu
.dst
.sel
= ctx
->temp_reg
;
2512 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2515 /* POW(a,b) = EXP2(b * LOG2(a))*/
2516 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2517 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2518 alu
.src
[0].sel
= ctx
->temp_reg
;
2519 alu
.dst
.sel
= ctx
->temp_reg
;
2522 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2525 return tgsi_helper_tempx_replicate(ctx
);
2528 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
2530 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2531 struct r600_bytecode_alu alu
;
2533 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
2534 int tmp0
= ctx
->temp_reg
;
2535 int tmp1
= r600_get_temp(ctx
);
2536 int tmp2
= r600_get_temp(ctx
);
2537 int tmp3
= r600_get_temp(ctx
);
2540 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2542 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2543 * 2. tmp0.z = lo (tmp0.x * src2)
2544 * 3. tmp0.w = -tmp0.z
2545 * 4. tmp0.y = hi (tmp0.x * src2)
2546 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2547 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2548 * 7. tmp1.x = tmp0.x - tmp0.w
2549 * 8. tmp1.y = tmp0.x + tmp0.w
2550 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2551 * 10. tmp0.z = hi(tmp0.x * src1) = q
2552 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2554 * 12. tmp0.w = src1 - tmp0.y = r
2555 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2556 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2560 * 15. tmp1.z = tmp0.z + 1 = q + 1
2561 * 16. tmp1.w = tmp0.z - 1 = q - 1
2565 * 15. tmp1.z = tmp0.w - src2 = r - src2
2566 * 16. tmp1.w = tmp0.w + src2 = r + src2
2570 * 17. tmp1.x = tmp1.x & tmp1.y
2572 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2573 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2575 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2576 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2580 * Same as unsigned, using abs values of the operands,
2581 * and fixing the sign of the result in the end.
2584 for (i
= 0; i
< 4; i
++) {
2585 if (!(write_mask
& (1<<i
)))
2590 /* tmp2.x = -src0 */
2591 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2592 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2598 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2600 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2603 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2606 /* tmp2.y = -src1 */
2607 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2608 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2614 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2616 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2619 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2622 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2623 /* it will be a sign of the quotient */
2626 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2627 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
);
2633 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
2634 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2637 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2641 /* tmp2.x = |src0| */
2642 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2643 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
2650 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
2651 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2652 alu
.src
[2].sel
= tmp2
;
2653 alu
.src
[2].chan
= 0;
2656 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2659 /* tmp2.y = |src1| */
2660 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2661 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
2668 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2669 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2670 alu
.src
[2].sel
= tmp2
;
2671 alu
.src
[2].chan
= 1;
2674 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2679 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2680 if (ctx
->bc
->chip_class
== CAYMAN
) {
2681 /* tmp3.x = u2f(src2) */
2682 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2683 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
);
2690 alu
.src
[0].sel
= tmp2
;
2691 alu
.src
[0].chan
= 1;
2693 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2697 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2700 /* tmp0.x = recip(tmp3.x) */
2701 for (j
= 0 ; j
< 3; j
++) {
2702 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2703 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
2707 alu
.dst
.write
= (j
== 0);
2709 alu
.src
[0].sel
= tmp3
;
2710 alu
.src
[0].chan
= 0;
2714 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2718 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2719 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2721 alu
.src
[0].sel
= tmp0
;
2722 alu
.src
[0].chan
= 0;
2724 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2725 alu
.src
[1].value
= 0x4f800000;
2730 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2734 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2735 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
);
2741 alu
.src
[0].sel
= tmp3
;
2742 alu
.src
[0].chan
= 0;
2745 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2749 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2750 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
);
2757 alu
.src
[0].sel
= tmp2
;
2758 alu
.src
[0].chan
= 1;
2760 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2764 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2768 /* 2. tmp0.z = lo (tmp0.x * src2) */
2769 if (ctx
->bc
->chip_class
== CAYMAN
) {
2770 for (j
= 0 ; j
< 4; j
++) {
2771 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2772 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2776 alu
.dst
.write
= (j
== 2);
2778 alu
.src
[0].sel
= tmp0
;
2779 alu
.src
[0].chan
= 0;
2781 alu
.src
[1].sel
= tmp2
;
2782 alu
.src
[1].chan
= 1;
2784 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2787 alu
.last
= (j
== 3);
2788 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2792 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2793 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2799 alu
.src
[0].sel
= tmp0
;
2800 alu
.src
[0].chan
= 0;
2802 alu
.src
[1].sel
= tmp2
;
2803 alu
.src
[1].chan
= 1;
2805 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2809 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2813 /* 3. tmp0.w = -tmp0.z */
2814 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2815 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2821 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2822 alu
.src
[1].sel
= tmp0
;
2823 alu
.src
[1].chan
= 2;
2826 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2829 /* 4. tmp0.y = hi (tmp0.x * src2) */
2830 if (ctx
->bc
->chip_class
== CAYMAN
) {
2831 for (j
= 0 ; j
< 4; j
++) {
2832 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2833 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2837 alu
.dst
.write
= (j
== 1);
2839 alu
.src
[0].sel
= tmp0
;
2840 alu
.src
[0].chan
= 0;
2843 alu
.src
[1].sel
= tmp2
;
2844 alu
.src
[1].chan
= 1;
2846 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2848 alu
.last
= (j
== 3);
2849 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2853 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2854 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2860 alu
.src
[0].sel
= tmp0
;
2861 alu
.src
[0].chan
= 0;
2864 alu
.src
[1].sel
= tmp2
;
2865 alu
.src
[1].chan
= 1;
2867 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2871 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2875 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2876 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2877 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
2884 alu
.src
[0].sel
= tmp0
;
2885 alu
.src
[0].chan
= 1;
2886 alu
.src
[1].sel
= tmp0
;
2887 alu
.src
[1].chan
= 3;
2888 alu
.src
[2].sel
= tmp0
;
2889 alu
.src
[2].chan
= 2;
2892 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2895 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2896 if (ctx
->bc
->chip_class
== CAYMAN
) {
2897 for (j
= 0 ; j
< 4; j
++) {
2898 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2899 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2903 alu
.dst
.write
= (j
== 3);
2905 alu
.src
[0].sel
= tmp0
;
2906 alu
.src
[0].chan
= 2;
2908 alu
.src
[1].sel
= tmp0
;
2909 alu
.src
[1].chan
= 0;
2911 alu
.last
= (j
== 3);
2912 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2916 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2917 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2923 alu
.src
[0].sel
= tmp0
;
2924 alu
.src
[0].chan
= 2;
2926 alu
.src
[1].sel
= tmp0
;
2927 alu
.src
[1].chan
= 0;
2930 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2934 /* 7. tmp1.x = tmp0.x - tmp0.w */
2935 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2936 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2942 alu
.src
[0].sel
= tmp0
;
2943 alu
.src
[0].chan
= 0;
2944 alu
.src
[1].sel
= tmp0
;
2945 alu
.src
[1].chan
= 3;
2948 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2951 /* 8. tmp1.y = tmp0.x + tmp0.w */
2952 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2953 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
2959 alu
.src
[0].sel
= tmp0
;
2960 alu
.src
[0].chan
= 0;
2961 alu
.src
[1].sel
= tmp0
;
2962 alu
.src
[1].chan
= 3;
2965 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2968 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2969 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2970 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
2977 alu
.src
[0].sel
= tmp0
;
2978 alu
.src
[0].chan
= 1;
2979 alu
.src
[1].sel
= tmp1
;
2980 alu
.src
[1].chan
= 1;
2981 alu
.src
[2].sel
= tmp1
;
2982 alu
.src
[2].chan
= 0;
2985 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2988 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2989 if (ctx
->bc
->chip_class
== CAYMAN
) {
2990 for (j
= 0 ; j
< 4; j
++) {
2991 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2992 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2996 alu
.dst
.write
= (j
== 2);
2998 alu
.src
[0].sel
= tmp0
;
2999 alu
.src
[0].chan
= 0;
3002 alu
.src
[1].sel
= tmp2
;
3003 alu
.src
[1].chan
= 0;
3005 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3008 alu
.last
= (j
== 3);
3009 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3013 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3014 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
3020 alu
.src
[0].sel
= tmp0
;
3021 alu
.src
[0].chan
= 0;
3024 alu
.src
[1].sel
= tmp2
;
3025 alu
.src
[1].chan
= 0;
3027 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3031 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3035 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3036 if (ctx
->bc
->chip_class
== CAYMAN
) {
3037 for (j
= 0 ; j
< 4; j
++) {
3038 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3039 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
3043 alu
.dst
.write
= (j
== 1);
3046 alu
.src
[0].sel
= tmp2
;
3047 alu
.src
[0].chan
= 1;
3049 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
3052 alu
.src
[1].sel
= tmp0
;
3053 alu
.src
[1].chan
= 2;
3055 alu
.last
= (j
== 3);
3056 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3060 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3061 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
3068 alu
.src
[0].sel
= tmp2
;
3069 alu
.src
[0].chan
= 1;
3071 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
3074 alu
.src
[1].sel
= tmp0
;
3075 alu
.src
[1].chan
= 2;
3078 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3082 /* 12. tmp0.w = src1 - tmp0.y = r */
3083 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3084 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3091 alu
.src
[0].sel
= tmp2
;
3092 alu
.src
[0].chan
= 0;
3094 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3097 alu
.src
[1].sel
= tmp0
;
3098 alu
.src
[1].chan
= 1;
3101 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3104 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3105 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3106 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
);
3112 alu
.src
[0].sel
= tmp0
;
3113 alu
.src
[0].chan
= 3;
3115 alu
.src
[1].sel
= tmp2
;
3116 alu
.src
[1].chan
= 1;
3118 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3122 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3125 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3126 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3127 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
);
3134 alu
.src
[0].sel
= tmp2
;
3135 alu
.src
[0].chan
= 0;
3137 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3140 alu
.src
[1].sel
= tmp0
;
3141 alu
.src
[1].chan
= 1;
3144 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3147 if (mod
) { /* UMOD */
3149 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3150 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3151 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3157 alu
.src
[0].sel
= tmp0
;
3158 alu
.src
[0].chan
= 3;
3161 alu
.src
[1].sel
= tmp2
;
3162 alu
.src
[1].chan
= 1;
3164 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3168 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3171 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3172 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3173 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
3179 alu
.src
[0].sel
= tmp0
;
3180 alu
.src
[0].chan
= 3;
3182 alu
.src
[1].sel
= tmp2
;
3183 alu
.src
[1].chan
= 1;
3185 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3189 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3194 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3195 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3196 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
3202 alu
.src
[0].sel
= tmp0
;
3203 alu
.src
[0].chan
= 2;
3204 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
3207 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3210 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3211 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3212 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
3218 alu
.src
[0].sel
= tmp0
;
3219 alu
.src
[0].chan
= 2;
3220 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
3223 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3228 /* 17. tmp1.x = tmp1.x & tmp1.y */
3229 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3230 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
);
3236 alu
.src
[0].sel
= tmp1
;
3237 alu
.src
[0].chan
= 0;
3238 alu
.src
[1].sel
= tmp1
;
3239 alu
.src
[1].chan
= 1;
3242 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3245 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3246 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3247 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3248 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
3255 alu
.src
[0].sel
= tmp1
;
3256 alu
.src
[0].chan
= 0;
3257 alu
.src
[1].sel
= tmp0
;
3258 alu
.src
[1].chan
= mod
? 3 : 2;
3259 alu
.src
[2].sel
= tmp1
;
3260 alu
.src
[2].chan
= 2;
3263 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3266 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3267 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3268 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
3276 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3279 alu
.src
[0].sel
= tmp1
;
3280 alu
.src
[0].chan
= 1;
3281 alu
.src
[1].sel
= tmp1
;
3282 alu
.src
[1].chan
= 3;
3283 alu
.src
[2].sel
= tmp0
;
3284 alu
.src
[2].chan
= 2;
3287 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3292 /* fix the sign of the result */
3296 /* tmp0.x = -tmp0.z */
3297 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3298 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3304 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3305 alu
.src
[1].sel
= tmp0
;
3306 alu
.src
[1].chan
= 2;
3309 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3312 /* sign of the remainder is the same as the sign of src0 */
3313 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3314 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3315 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3318 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3320 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3321 alu
.src
[1].sel
= tmp0
;
3322 alu
.src
[1].chan
= 2;
3323 alu
.src
[2].sel
= tmp0
;
3324 alu
.src
[2].chan
= 0;
3327 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3332 /* tmp0.x = -tmp0.z */
3333 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3334 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3340 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3341 alu
.src
[1].sel
= tmp0
;
3342 alu
.src
[1].chan
= 2;
3345 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3348 /* fix the quotient sign (same as the sign of src0*src1) */
3349 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3350 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3351 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3354 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3356 alu
.src
[0].sel
= tmp2
;
3357 alu
.src
[0].chan
= 2;
3358 alu
.src
[1].sel
= tmp0
;
3359 alu
.src
[1].chan
= 2;
3360 alu
.src
[2].sel
= tmp0
;
3361 alu
.src
[2].chan
= 0;
3364 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3372 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
3374 return tgsi_divmod(ctx
, 0, 0);
3377 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
3379 return tgsi_divmod(ctx
, 1, 0);
3382 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
3384 return tgsi_divmod(ctx
, 0, 1);
3387 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
3389 return tgsi_divmod(ctx
, 1, 1);
3393 static int tgsi_f2i(struct r600_shader_ctx
*ctx
)
3395 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3396 struct r600_bytecode_alu alu
;
3398 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3399 int last_inst
= tgsi_last_instruction(write_mask
);
3401 for (i
= 0; i
< 4; i
++) {
3402 if (!(write_mask
& (1<<i
)))
3405 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3406 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
);
3408 alu
.dst
.sel
= ctx
->temp_reg
;
3412 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3415 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3420 for (i
= 0; i
< 4; i
++) {
3421 if (!(write_mask
& (1<<i
)))
3424 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3425 alu
.inst
= ctx
->inst_info
->r600_opcode
;
3427 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3429 alu
.src
[0].sel
= ctx
->temp_reg
;
3430 alu
.src
[0].chan
= i
;
3432 if (i
== last_inst
|| alu
.inst
== EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
)
3434 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3442 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
3444 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3445 struct r600_bytecode_alu alu
;
3447 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3448 int last_inst
= tgsi_last_instruction(write_mask
);
3451 for (i
= 0; i
< 4; i
++) {
3452 if (!(write_mask
& (1<<i
)))
3455 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3456 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3458 alu
.dst
.sel
= ctx
->temp_reg
;
3462 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3463 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3467 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3472 /* dst = (src >= 0 ? src : tmp) */
3473 for (i
= 0; i
< 4; i
++) {
3474 if (!(write_mask
& (1<<i
)))
3477 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3478 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3482 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3484 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3485 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3486 alu
.src
[2].sel
= ctx
->temp_reg
;
3487 alu
.src
[2].chan
= i
;
3491 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3498 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
3500 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3501 struct r600_bytecode_alu alu
;
3503 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3504 int last_inst
= tgsi_last_instruction(write_mask
);
3506 /* tmp = (src >= 0 ? src : -1) */
3507 for (i
= 0; i
< 4; i
++) {
3508 if (!(write_mask
& (1<<i
)))
3511 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3512 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3515 alu
.dst
.sel
= ctx
->temp_reg
;
3519 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3520 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3521 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
3525 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3530 /* dst = (tmp > 0 ? 1 : tmp) */
3531 for (i
= 0; i
< 4; i
++) {
3532 if (!(write_mask
& (1<<i
)))
3535 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3536 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT
);
3540 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3542 alu
.src
[0].sel
= ctx
->temp_reg
;
3543 alu
.src
[0].chan
= i
;
3545 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
3547 alu
.src
[2].sel
= ctx
->temp_reg
;
3548 alu
.src
[2].chan
= i
;
3552 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3561 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
3563 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3564 struct r600_bytecode_alu alu
;
3567 /* tmp = (src > 0 ? 1 : src) */
3568 for (i
= 0; i
< 4; i
++) {
3569 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3570 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
3573 alu
.dst
.sel
= ctx
->temp_reg
;
3576 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3577 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
3578 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
3582 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3587 /* dst = (-tmp > 0 ? -1 : tmp) */
3588 for (i
= 0; i
< 4; i
++) {
3589 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3590 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
3592 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3594 alu
.src
[0].sel
= ctx
->temp_reg
;
3595 alu
.src
[0].chan
= i
;
3598 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
3601 alu
.src
[2].sel
= ctx
->temp_reg
;
3602 alu
.src
[2].chan
= i
;
3606 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3613 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
3615 struct r600_bytecode_alu alu
;
3618 for (i
= 0; i
< 4; i
++) {
3619 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3620 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
3621 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
3624 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3625 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3626 alu
.src
[0].sel
= ctx
->temp_reg
;
3627 alu
.src
[0].chan
= i
;
3632 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3639 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
3641 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3642 struct r600_bytecode_alu alu
;
3644 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
3646 for (i
= 0; i
< lasti
+ 1; i
++) {
3647 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
3650 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3651 alu
.inst
= ctx
->inst_info
->r600_opcode
;
3652 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3653 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
3656 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3663 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3670 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
3672 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3673 struct r600_bytecode_alu alu
;
3676 for (i
= 0; i
< 4; i
++) {
3677 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3678 alu
.inst
= ctx
->inst_info
->r600_opcode
;
3679 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3680 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
3683 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3685 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
3686 /* handle some special cases */
3687 switch (ctx
->inst_info
->tgsi_opcode
) {
3688 case TGSI_OPCODE_DP2
:
3690 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
3691 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
3694 case TGSI_OPCODE_DP3
:
3696 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
3697 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
3700 case TGSI_OPCODE_DPH
:
3702 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3703 alu
.src
[0].chan
= 0;
3713 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3720 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
3723 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3724 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
3725 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
&&
3726 inst
->Src
[index
].Register
.File
!= TGSI_FILE_OUTPUT
) ||
3727 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
;
3730 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
3733 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3734 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
3737 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
3739 static float one_point_five
= 1.5f
;
3740 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3741 struct r600_bytecode_tex tex
;
3742 struct r600_bytecode_alu alu
;
3746 /* Texture fetch instructions can only use gprs as source.
3747 * Also they cannot negate the source or take the absolute value */
3748 const boolean src_requires_loading
= inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
&&
3749 tgsi_tex_src_requires_loading(ctx
, 0);
3750 boolean src_loaded
= FALSE
;
3751 unsigned sampler_src_reg
= inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ_LZ
? 0 : 1;
3752 uint8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
3754 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
3756 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
3757 /* get offset values */
3758 if (inst
->Texture
.NumOffsets
) {
3759 assert(inst
->Texture
.NumOffsets
== 1);
3761 offset_x
= ctx
->literals
[inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
3762 offset_y
= ctx
->literals
[inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
3763 offset_z
= ctx
->literals
[inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
3765 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
3766 /* TGSI moves the sampler to src reg 3 for TXD */
3767 sampler_src_reg
= 3;
3769 for (i
= 1; i
< 3; i
++) {
3770 /* set gradients h/v */
3771 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
3772 tex
.inst
= (i
== 1) ? SQ_TEX_INST_SET_GRADIENTS_H
:
3773 SQ_TEX_INST_SET_GRADIENTS_V
;
3774 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
3775 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
3777 if (tgsi_tex_src_requires_loading(ctx
, i
)) {
3778 tex
.src_gpr
= r600_get_temp(ctx
);
3784 for (j
= 0; j
< 4; j
++) {
3785 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3786 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3787 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
3788 alu
.dst
.sel
= tex
.src_gpr
;
3793 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3799 tex
.src_gpr
= tgsi_tex_get_src_gpr(ctx
, i
);
3800 tex
.src_sel_x
= ctx
->src
[i
].swizzle
[0];
3801 tex
.src_sel_y
= ctx
->src
[i
].swizzle
[1];
3802 tex
.src_sel_z
= ctx
->src
[i
].swizzle
[2];
3803 tex
.src_sel_w
= ctx
->src
[i
].swizzle
[3];
3804 tex
.src_rel
= ctx
->src
[i
].rel
;
3806 tex
.dst_gpr
= ctx
->temp_reg
; /* just to avoid confusing the asm scheduler */
3807 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
3808 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
3809 tex
.coord_type_x
= 1;
3810 tex
.coord_type_y
= 1;
3811 tex
.coord_type_z
= 1;
3812 tex
.coord_type_w
= 1;
3814 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
3818 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
3820 /* Add perspective divide */
3821 if (ctx
->bc
->chip_class
== CAYMAN
) {
3823 for (i
= 0; i
< 3; i
++) {
3824 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3825 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3826 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
3828 alu
.dst
.sel
= ctx
->temp_reg
;
3834 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3841 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3842 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3843 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
3845 alu
.dst
.sel
= ctx
->temp_reg
;
3846 alu
.dst
.chan
= out_chan
;
3849 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3854 for (i
= 0; i
< 3; i
++) {
3855 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3856 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
3857 alu
.src
[0].sel
= ctx
->temp_reg
;
3858 alu
.src
[0].chan
= out_chan
;
3859 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3860 alu
.dst
.sel
= ctx
->temp_reg
;
3863 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3867 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3868 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3869 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3870 alu
.src
[0].chan
= 0;
3871 alu
.dst
.sel
= ctx
->temp_reg
;
3875 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3879 src_gpr
= ctx
->temp_reg
;
3882 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
3883 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) &&
3884 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
&&
3885 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ_LZ
) {
3887 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
3888 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
3890 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3891 for (i
= 0; i
< 4; i
++) {
3892 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3893 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
);
3894 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
3895 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
3896 alu
.dst
.sel
= ctx
->temp_reg
;
3901 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3906 /* tmp1.z = RCP_e(|tmp1.z|) */
3907 if (ctx
->bc
->chip_class
== CAYMAN
) {
3908 for (i
= 0; i
< 3; i
++) {
3909 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3910 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3911 alu
.src
[0].sel
= ctx
->temp_reg
;
3912 alu
.src
[0].chan
= 2;
3914 alu
.dst
.sel
= ctx
->temp_reg
;
3920 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3925 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3926 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3927 alu
.src
[0].sel
= ctx
->temp_reg
;
3928 alu
.src
[0].chan
= 2;
3930 alu
.dst
.sel
= ctx
->temp_reg
;
3934 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3939 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
3940 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
3941 * muladd has no writemask, have to use another temp
3943 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3944 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
3947 alu
.src
[0].sel
= ctx
->temp_reg
;
3948 alu
.src
[0].chan
= 0;
3949 alu
.src
[1].sel
= ctx
->temp_reg
;
3950 alu
.src
[1].chan
= 2;
3952 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
3953 alu
.src
[2].chan
= 0;
3954 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
3956 alu
.dst
.sel
= ctx
->temp_reg
;
3960 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3964 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3965 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
3968 alu
.src
[0].sel
= ctx
->temp_reg
;
3969 alu
.src
[0].chan
= 1;
3970 alu
.src
[1].sel
= ctx
->temp_reg
;
3971 alu
.src
[1].chan
= 2;
3973 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
3974 alu
.src
[2].chan
= 0;
3975 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
3977 alu
.dst
.sel
= ctx
->temp_reg
;
3982 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3985 /* write initial W value into Z component */
3986 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) {
3987 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3988 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3989 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
3990 alu
.dst
.sel
= ctx
->temp_reg
;
3994 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3999 src_gpr
= ctx
->temp_reg
;
4002 if (src_requires_loading
&& !src_loaded
) {
4003 for (i
= 0; i
< 4; i
++) {
4004 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4005 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
4006 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4007 alu
.dst
.sel
= ctx
->temp_reg
;
4012 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4017 src_gpr
= ctx
->temp_reg
;
4020 opcode
= ctx
->inst_info
->r600_opcode
;
4021 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
4022 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
4023 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
4024 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
4025 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
4026 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
) {
4028 case SQ_TEX_INST_SAMPLE
:
4029 opcode
= SQ_TEX_INST_SAMPLE_C
;
4031 case SQ_TEX_INST_SAMPLE_L
:
4032 opcode
= SQ_TEX_INST_SAMPLE_C_L
;
4034 case SQ_TEX_INST_SAMPLE_LB
:
4035 opcode
= SQ_TEX_INST_SAMPLE_C_LB
;
4037 case SQ_TEX_INST_SAMPLE_G
:
4038 opcode
= SQ_TEX_INST_SAMPLE_C_G
;
4043 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
4046 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
4047 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
4048 tex
.src_gpr
= src_gpr
;
4049 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
4050 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
4051 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
4052 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
4053 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
4055 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ_LZ
) {
4060 } else if (src_loaded
) {
4066 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
4067 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
4068 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
4069 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
4070 tex
.src_rel
= ctx
->src
[0].rel
;
4073 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
4079 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) {
4083 tex
.src_sel_w
= 2; /* route Z compare value into W */
4086 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
4087 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
4088 tex
.coord_type_x
= 1;
4089 tex
.coord_type_y
= 1;
4091 tex
.coord_type_z
= 1;
4092 tex
.coord_type_w
= 1;
4094 tex
.offset_x
= offset_x
;
4095 tex
.offset_y
= offset_y
;
4096 tex
.offset_z
= offset_z
;
4098 /* Put the depth for comparison in W.
4099 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4100 * Some instructions expect the depth in Z. */
4101 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
4102 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
4103 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
4104 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
4105 opcode
!= SQ_TEX_INST_SAMPLE_C_L
&&
4106 opcode
!= SQ_TEX_INST_SAMPLE_C_LB
) {
4107 tex
.src_sel_w
= tex
.src_sel_z
;
4110 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
4111 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
4112 if (opcode
== SQ_TEX_INST_SAMPLE_C_L
||
4113 opcode
== SQ_TEX_INST_SAMPLE_C_LB
) {
4114 /* the array index is read from Y */
4115 tex
.coord_type_y
= 0;
4117 /* the array index is read from Z */
4118 tex
.coord_type_z
= 0;
4119 tex
.src_sel_z
= tex
.src_sel_y
;
4121 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
4122 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)
4123 /* the array index is read from Z */
4124 tex
.coord_type_z
= 0;
4126 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
4130 /* add shadow ambient support - gallium doesn't do it yet */
4134 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
4136 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4137 struct r600_bytecode_alu alu
;
4138 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4142 /* optimize if it's just an equal balance */
4143 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
4144 for (i
= 0; i
< lasti
+ 1; i
++) {
4145 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4148 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4149 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
4150 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
4151 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
4153 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4158 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4166 for (i
= 0; i
< lasti
+ 1; i
++) {
4167 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4170 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4171 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
4172 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4173 alu
.src
[0].chan
= 0;
4174 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4175 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
4176 alu
.dst
.sel
= ctx
->temp_reg
;
4182 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4187 /* (1 - src0) * src2 */
4188 for (i
= 0; i
< lasti
+ 1; i
++) {
4189 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4192 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4193 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4194 alu
.src
[0].sel
= ctx
->temp_reg
;
4195 alu
.src
[0].chan
= i
;
4196 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
4197 alu
.dst
.sel
= ctx
->temp_reg
;
4203 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4208 /* src0 * src1 + (1 - src0) * src2 */
4209 for (i
= 0; i
< lasti
+ 1; i
++) {
4210 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4213 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4214 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
4216 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4217 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
4218 alu
.src
[2].sel
= ctx
->temp_reg
;
4219 alu
.src
[2].chan
= i
;
4221 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4226 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4233 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
4235 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4236 struct r600_bytecode_alu alu
;
4238 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4240 for (i
= 0; i
< lasti
+ 1; i
++) {
4241 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4244 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4245 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
);
4246 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4247 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
4248 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
4249 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4255 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4262 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
4264 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4265 static const unsigned int src0_swizzle
[] = {2, 0, 1};
4266 static const unsigned int src1_swizzle
[] = {1, 2, 0};
4267 struct r600_bytecode_alu alu
;
4268 uint32_t use_temp
= 0;
4271 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
4274 for (i
= 0; i
< 4; i
++) {
4275 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4276 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4278 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
4279 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src1_swizzle
[i
]);
4281 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4282 alu
.src
[0].chan
= i
;
4283 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
4284 alu
.src
[1].chan
= i
;
4287 alu
.dst
.sel
= ctx
->temp_reg
;
4293 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4298 for (i
= 0; i
< 4; i
++) {
4299 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4300 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
4303 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src1_swizzle
[i
]);
4304 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src0_swizzle
[i
]);
4306 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4307 alu
.src
[0].chan
= i
;
4308 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
4309 alu
.src
[1].chan
= i
;
4312 alu
.src
[2].sel
= ctx
->temp_reg
;
4314 alu
.src
[2].chan
= i
;
4317 alu
.dst
.sel
= ctx
->temp_reg
;
4319 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4325 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4330 return tgsi_helper_copy(ctx
, inst
);
4334 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
4336 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4337 struct r600_bytecode_alu alu
;
4341 /* result.x = 2^floor(src); */
4342 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
4343 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4345 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
4346 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4348 alu
.dst
.sel
= ctx
->temp_reg
;
4352 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4356 if (ctx
->bc
->chip_class
== CAYMAN
) {
4357 for (i
= 0; i
< 3; i
++) {
4358 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4359 alu
.src
[0].sel
= ctx
->temp_reg
;
4360 alu
.src
[0].chan
= 0;
4362 alu
.dst
.sel
= ctx
->temp_reg
;
4368 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4373 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4374 alu
.src
[0].sel
= ctx
->temp_reg
;
4375 alu
.src
[0].chan
= 0;
4377 alu
.dst
.sel
= ctx
->temp_reg
;
4381 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4387 /* result.y = tmp - floor(tmp); */
4388 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
4389 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4391 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
4392 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4394 alu
.dst
.sel
= ctx
->temp_reg
;
4396 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4405 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4410 /* result.z = RoughApprox2ToX(tmp);*/
4411 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
4412 if (ctx
->bc
->chip_class
== CAYMAN
) {
4413 for (i
= 0; i
< 3; i
++) {
4414 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4415 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4416 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4418 alu
.dst
.sel
= ctx
->temp_reg
;
4425 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4430 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4431 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4432 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4434 alu
.dst
.sel
= ctx
->temp_reg
;
4440 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4446 /* result.w = 1.0;*/
4447 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
4448 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4450 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
4451 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4452 alu
.src
[0].chan
= 0;
4454 alu
.dst
.sel
= ctx
->temp_reg
;
4458 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4462 return tgsi_helper_copy(ctx
, inst
);
4465 static int tgsi_log(struct r600_shader_ctx
*ctx
)
4467 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4468 struct r600_bytecode_alu alu
;
4472 /* result.x = floor(log2(|src|)); */
4473 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
4474 if (ctx
->bc
->chip_class
== CAYMAN
) {
4475 for (i
= 0; i
< 3; i
++) {
4476 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4478 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4479 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4480 r600_bytecode_src_set_abs(&alu
.src
[0]);
4482 alu
.dst
.sel
= ctx
->temp_reg
;
4488 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4494 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4496 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4497 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4498 r600_bytecode_src_set_abs(&alu
.src
[0]);
4500 alu
.dst
.sel
= ctx
->temp_reg
;
4504 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4509 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
4510 alu
.src
[0].sel
= ctx
->temp_reg
;
4511 alu
.src
[0].chan
= 0;
4513 alu
.dst
.sel
= ctx
->temp_reg
;
4518 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4523 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4524 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
4526 if (ctx
->bc
->chip_class
== CAYMAN
) {
4527 for (i
= 0; i
< 3; i
++) {
4528 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4530 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4531 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4532 r600_bytecode_src_set_abs(&alu
.src
[0]);
4534 alu
.dst
.sel
= ctx
->temp_reg
;
4541 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4546 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4548 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4549 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4550 r600_bytecode_src_set_abs(&alu
.src
[0]);
4552 alu
.dst
.sel
= ctx
->temp_reg
;
4557 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4562 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4564 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
4565 alu
.src
[0].sel
= ctx
->temp_reg
;
4566 alu
.src
[0].chan
= 1;
4568 alu
.dst
.sel
= ctx
->temp_reg
;
4573 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4577 if (ctx
->bc
->chip_class
== CAYMAN
) {
4578 for (i
= 0; i
< 3; i
++) {
4579 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4580 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4581 alu
.src
[0].sel
= ctx
->temp_reg
;
4582 alu
.src
[0].chan
= 1;
4584 alu
.dst
.sel
= ctx
->temp_reg
;
4591 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4596 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4597 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4598 alu
.src
[0].sel
= ctx
->temp_reg
;
4599 alu
.src
[0].chan
= 1;
4601 alu
.dst
.sel
= ctx
->temp_reg
;
4606 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4611 if (ctx
->bc
->chip_class
== CAYMAN
) {
4612 for (i
= 0; i
< 3; i
++) {
4613 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4614 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
4615 alu
.src
[0].sel
= ctx
->temp_reg
;
4616 alu
.src
[0].chan
= 1;
4618 alu
.dst
.sel
= ctx
->temp_reg
;
4625 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4630 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4631 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
4632 alu
.src
[0].sel
= ctx
->temp_reg
;
4633 alu
.src
[0].chan
= 1;
4635 alu
.dst
.sel
= ctx
->temp_reg
;
4640 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4645 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4647 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4649 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4650 r600_bytecode_src_set_abs(&alu
.src
[0]);
4652 alu
.src
[1].sel
= ctx
->temp_reg
;
4653 alu
.src
[1].chan
= 1;
4655 alu
.dst
.sel
= ctx
->temp_reg
;
4660 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4665 /* result.z = log2(|src|);*/
4666 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
4667 if (ctx
->bc
->chip_class
== CAYMAN
) {
4668 for (i
= 0; i
< 3; i
++) {
4669 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4671 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4672 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4673 r600_bytecode_src_set_abs(&alu
.src
[0]);
4675 alu
.dst
.sel
= ctx
->temp_reg
;
4682 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4687 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4689 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4690 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4691 r600_bytecode_src_set_abs(&alu
.src
[0]);
4693 alu
.dst
.sel
= ctx
->temp_reg
;
4698 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4704 /* result.w = 1.0; */
4705 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
4706 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4708 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
4709 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4710 alu
.src
[0].chan
= 0;
4712 alu
.dst
.sel
= ctx
->temp_reg
;
4717 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4722 return tgsi_helper_copy(ctx
, inst
);
4725 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
4727 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4728 struct r600_bytecode_alu alu
;
4731 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4733 switch (inst
->Instruction
.Opcode
) {
4734 case TGSI_OPCODE_ARL
:
4735 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
;
4737 case TGSI_OPCODE_ARR
:
4738 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
4740 case TGSI_OPCODE_UARL
:
4741 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
4748 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4750 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4752 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4756 ctx
->bc
->ar_loaded
= 0;
4759 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
4761 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4762 struct r600_bytecode_alu alu
;
4765 switch (inst
->Instruction
.Opcode
) {
4766 case TGSI_OPCODE_ARL
:
4767 memset(&alu
, 0, sizeof(alu
));
4768 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
;
4769 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4770 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4774 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4777 memset(&alu
, 0, sizeof(alu
));
4778 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
4779 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
4780 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4784 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4787 case TGSI_OPCODE_ARR
:
4788 memset(&alu
, 0, sizeof(alu
));
4789 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
4790 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4791 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4795 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4798 case TGSI_OPCODE_UARL
:
4799 memset(&alu
, 0, sizeof(alu
));
4800 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
4801 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4802 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4806 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4814 ctx
->bc
->ar_loaded
= 0;
4818 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
4820 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4821 struct r600_bytecode_alu alu
;
4824 for (i
= 0; i
< 4; i
++) {
4825 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4827 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4828 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4830 if (i
== 0 || i
== 3) {
4831 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4833 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4836 if (i
== 0 || i
== 2) {
4837 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4839 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
4843 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4850 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
4852 struct r600_bytecode_alu alu
;
4855 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4859 alu
.dst
.sel
= ctx
->temp_reg
;
4863 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4864 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
4865 alu
.src
[1].chan
= 0;
4869 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
4875 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
4877 unsigned force_pop
= ctx
->bc
->force_add_cf
;
4881 if (ctx
->bc
->cf_last
) {
4882 if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
))
4884 else if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
))
4889 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
);
4890 ctx
->bc
->force_add_cf
= 1;
4891 } else if (alu_pop
== 2) {
4892 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
);
4893 ctx
->bc
->force_add_cf
= 1;
4900 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP
));
4901 ctx
->bc
->cf_last
->pop_count
= pops
;
4902 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
4908 static inline void callstack_decrease_current(struct r600_shader_ctx
*ctx
, unsigned reason
)
4912 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
4916 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
-= 4;
4919 /* TOODO : for 16 vp asic should -= 2; */
4920 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
4925 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
)
4927 if (check_max_only
) {
4940 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
) >
4941 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
4942 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
4943 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
;
4949 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
4953 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+= 4;
4956 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
4960 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
) >
4961 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
4962 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
4963 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
;
4967 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
4969 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
4971 sp
->mid
= (struct r600_bytecode_cf
**)realloc((void *)sp
->mid
,
4972 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
4973 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
4977 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
4980 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
4981 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
4984 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
4986 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
4998 static int emit_return(struct r600_shader_ctx
*ctx
)
5000 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN
));
5004 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
5007 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
5008 ctx
->bc
->cf_last
->pop_count
= pops
;
5009 /* XXX work out offset */
5013 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
5018 static void emit_testflag(struct r600_shader_ctx
*ctx
)
5023 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
5026 emit_jump_to_offset(ctx
, 1, 4);
5027 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
5028 pops(ctx
, ifidx
+ 1);
5032 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
5036 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
5037 ctx
->bc
->cf_last
->pop_count
= 1;
5039 fc_set_mid(ctx
, fc_sp
);
5045 static int tgsi_if(struct r600_shader_ctx
*ctx
)
5047 emit_logic_pred(ctx
, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
));
5049 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
5051 fc_pushlevel(ctx
, FC_IF
);
5053 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
5057 static int tgsi_else(struct r600_shader_ctx
*ctx
)
5059 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE
));
5060 ctx
->bc
->cf_last
->pop_count
= 1;
5062 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
5063 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
5067 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
5070 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
5071 R600_ERR("if/endif unbalanced in shader\n");
5075 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
5076 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
5077 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
5079 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
5083 callstack_decrease_current(ctx
, FC_PUSH_VPM
);
5087 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
5089 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
));
5091 fc_pushlevel(ctx
, FC_LOOP
);
5093 /* check stack depth */
5094 callstack_check_depth(ctx
, FC_LOOP
, 0);
5098 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
5102 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
));
5104 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
5105 R600_ERR("loop/endloop in shader code are not paired.\n");
5109 /* fixup loop pointers - from r600isa
5110 LOOP END points to CF after LOOP START,
5111 LOOP START point to CF after LOOP END
5112 BRK/CONT point to LOOP END CF
5114 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
5116 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
5118 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
5119 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
5121 /* XXX add LOOPRET support */
5123 callstack_decrease_current(ctx
, FC_LOOP
);
5127 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
5131 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
5133 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
5138 R600_ERR("Break not inside loop/endloop pair\n");
5142 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
5144 fc_set_mid(ctx
, fscp
);
5146 callstack_check_depth(ctx
, FC_PUSH_VPM
, 1);
5150 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
5152 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5153 struct r600_bytecode_alu alu
;
5155 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
5158 for (i
= 0; i
< lasti
+ 1; i
++) {
5159 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
5162 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5165 alu
.dst
.sel
= ctx
->temp_reg
;
5168 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
5169 for (j
= 0; j
< 2; j
++) {
5170 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
5174 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5180 for (i
= 0; i
< lasti
+ 1; i
++) {
5181 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
5184 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5185 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5187 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
5189 alu
.src
[0].sel
= ctx
->temp_reg
;
5190 alu
.src
[0].chan
= i
;
5192 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
5196 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5203 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
5204 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
5205 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5206 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
5209 * For state trackers other than OpenGL, we'll want to use
5210 * _RECIP_IEEE instead.
5212 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
5214 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_rsq
},
5215 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
5216 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
5217 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
5218 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5219 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5220 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5221 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
5222 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
5223 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
5224 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
5225 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
5226 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
5227 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5228 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
5229 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5231 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5232 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5234 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5235 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5236 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
5237 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5238 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
5239 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
, tgsi_op2
},
5240 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
5241 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
5242 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
5243 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
5245 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5246 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5247 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5248 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5249 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
5250 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
5251 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
5252 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
5253 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5254 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5255 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5256 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5257 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5258 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
5259 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5260 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
5261 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
5262 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
5263 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
5264 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5265 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5266 {TGSI_OPCODE_TXD
, 0, SQ_TEX_INST_SAMPLE_G
, tgsi_tex
},
5267 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5268 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5269 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5270 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5271 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5272 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5273 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5274 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
5275 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5276 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5277 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5278 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
5279 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
5280 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
5281 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_LB
, tgsi_tex
},
5282 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5283 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5284 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5285 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
5286 {TGSI_OPCODE_BRK
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
5287 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
5289 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5290 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5291 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
5292 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
5294 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5295 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5296 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5297 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5298 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL
, tgsi_op2
},
5299 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
, tgsi_op2_trans
},
5300 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
, tgsi_op2
},
5301 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
5302 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
, tgsi_op2_trans
},
5304 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5305 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
, tgsi_op2
},
5306 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
, tgsi_op2
},
5307 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_imod
},
5308 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
, tgsi_op2
},
5309 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5310 {TGSI_OPCODE_TXF
, 0, SQ_TEX_INST_LD
, tgsi_tex
},
5311 {TGSI_OPCODE_TXQ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5312 {TGSI_OPCODE_CONT
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
5313 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5314 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5315 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
5316 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5317 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
5318 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5319 {TGSI_OPCODE_TXQ_LZ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5321 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5322 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5323 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5324 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5326 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5327 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5328 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5329 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5330 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5331 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5332 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5333 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5334 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
5335 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
5337 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5338 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
, tgsi_op2_trans
},
5339 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_idiv
},
5340 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
, tgsi_op2
},
5341 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
, tgsi_op2
},
5342 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
, tgsi_ineg
},
5343 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
, tgsi_op2
},
5344 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
, tgsi_op2_trans
},
5345 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
, tgsi_op2_swap
},
5346 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
, tgsi_op2
},
5347 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
, tgsi_op2_trans
},
5348 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
, tgsi_op2
},
5349 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_udiv
},
5350 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umad
},
5351 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
, tgsi_op2
},
5352 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
, tgsi_op2
},
5353 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umod
},
5354 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
, tgsi_op2_trans
},
5355 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
, tgsi_op2
},
5356 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
, tgsi_op2
},
5357 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
, tgsi_op2_trans
},
5358 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
, tgsi_op2_swap
},
5359 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
, tgsi_op2_swap
},
5360 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5361 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5362 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5363 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5364 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
5365 {TGSI_OPCODE_SAMPLE_I
, 0, 0, tgsi_unsupported
},
5366 {TGSI_OPCODE_SAMPLE_I_MS
, 0, 0, tgsi_unsupported
},
5367 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
5368 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
5369 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
5370 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
5371 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
5372 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
5373 {TGSI_OPCODE_SVIEWINFO
, 0, 0, tgsi_unsupported
},
5374 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
5375 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
5376 {TGSI_OPCODE_UARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
, tgsi_r600_arl
},
5377 {TGSI_OPCODE_UCMP
, 0, 0, tgsi_unsupported
},
5378 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
5379 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
5380 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5383 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
5384 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5385 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5386 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
5387 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
5388 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_rsq
},
5389 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
5390 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
5391 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
5392 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5393 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5394 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5395 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
5396 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
5397 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
5398 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
5399 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
5400 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
5401 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5402 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
5403 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5405 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5406 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5408 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5409 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5410 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
5411 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5412 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
5413 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
, tgsi_op2
},
5414 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
5415 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
5416 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
5417 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
5419 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5420 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5421 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5422 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5423 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
5424 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
5425 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
5426 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
5427 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5428 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5429 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5430 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5431 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5432 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
5433 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5434 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
5435 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
5436 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
5437 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
5438 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5439 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5440 {TGSI_OPCODE_TXD
, 0, SQ_TEX_INST_SAMPLE_G
, tgsi_tex
},
5441 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5442 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5443 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5444 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5445 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5446 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5447 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5448 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5449 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5450 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5451 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5452 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
5453 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
5454 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
5455 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_LB
, tgsi_tex
},
5456 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5457 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5458 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5459 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
5460 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
5461 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
5463 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5464 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5465 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
5466 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
5468 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5469 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5470 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5471 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5472 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL
, tgsi_op2
},
5473 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
, tgsi_op2_trans
},
5474 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
, tgsi_op2
},
5475 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
5476 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
, tgsi_op2
},
5478 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5479 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
, tgsi_op2
},
5480 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
, tgsi_op2
},
5481 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_imod
},
5482 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
, tgsi_op2
},
5483 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5484 {TGSI_OPCODE_TXF
, 0, SQ_TEX_INST_LD
, tgsi_tex
},
5485 {TGSI_OPCODE_TXQ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5486 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
5487 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5488 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5489 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
5490 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5491 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
5492 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5493 {TGSI_OPCODE_TXQ_LZ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5495 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5496 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5497 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5498 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5500 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5501 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5502 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5503 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5504 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5505 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5506 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5507 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5508 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
5509 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
5511 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5512 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
, tgsi_f2i
},
5513 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_idiv
},
5514 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
, tgsi_op2
},
5515 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
, tgsi_op2
},
5516 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
, tgsi_ineg
},
5517 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
, tgsi_op2
},
5518 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
, tgsi_op2
},
5519 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
, tgsi_op2_swap
},
5520 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
, tgsi_f2i
},
5521 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
, tgsi_op2_trans
},
5522 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
, tgsi_op2
},
5523 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_udiv
},
5524 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umad
},
5525 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
, tgsi_op2
},
5526 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
, tgsi_op2
},
5527 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umod
},
5528 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
, tgsi_op2_trans
},
5529 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
, tgsi_op2
},
5530 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
, tgsi_op2
},
5531 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
, tgsi_op2
},
5532 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
, tgsi_op2_swap
},
5533 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
, tgsi_op2
},
5534 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5535 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5536 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5537 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5538 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
5539 {TGSI_OPCODE_SAMPLE_I
, 0, 0, tgsi_unsupported
},
5540 {TGSI_OPCODE_SAMPLE_I_MS
, 0, 0, tgsi_unsupported
},
5541 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
5542 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
5543 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
5544 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
5545 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
5546 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
5547 {TGSI_OPCODE_SVIEWINFO
, 0, 0, tgsi_unsupported
},
5548 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
5549 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
5550 {TGSI_OPCODE_UARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
, tgsi_eg_arl
},
5551 {TGSI_OPCODE_UCMP
, 0, 0, tgsi_unsupported
},
5552 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
5553 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
5554 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5557 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
5558 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5559 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5560 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
5561 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, cayman_emit_float_instr
},
5562 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
5563 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
5564 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
5565 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
5566 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5567 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5568 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5569 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
5570 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
5571 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
5572 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
5573 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
5574 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
5575 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5576 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
5577 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5579 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5580 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5582 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5583 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5584 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
5585 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5586 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
5587 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
, tgsi_op2
},
5588 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, cayman_emit_float_instr
},
5589 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, cayman_emit_float_instr
},
5590 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, cayman_pow
},
5591 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
5593 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5594 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5595 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5596 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5597 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, cayman_trig
},
5598 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
5599 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
5600 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
5601 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5602 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5603 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5604 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5605 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5606 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
5607 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5608 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
5609 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, cayman_trig
},
5610 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
5611 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
5612 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5613 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5614 {TGSI_OPCODE_TXD
, 0, SQ_TEX_INST_SAMPLE_G
, tgsi_tex
},
5615 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5616 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5617 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5618 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5619 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5620 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5621 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5622 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5623 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5624 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5625 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5626 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
5627 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
5628 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
5629 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_LB
, tgsi_tex
},
5630 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5631 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5632 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5633 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
5634 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
5635 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
5637 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5638 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5639 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
5640 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
5642 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5643 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5644 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5645 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5646 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL
, tgsi_op2
},
5647 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
, tgsi_op2
},
5648 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
, tgsi_op2
},
5649 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
5650 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
, tgsi_op2
},
5652 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5653 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
, tgsi_op2
},
5654 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
, tgsi_op2
},
5655 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_imod
},
5656 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
, tgsi_op2
},
5657 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5658 {TGSI_OPCODE_TXF
, 0, SQ_TEX_INST_LD
, tgsi_tex
},
5659 {TGSI_OPCODE_TXQ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5660 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
5661 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5662 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5663 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
5664 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5665 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
5666 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5667 {TGSI_OPCODE_TXQ_LZ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5669 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5670 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5671 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5672 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5674 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5675 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5676 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5677 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5678 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5679 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5680 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5681 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5682 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
5683 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
5685 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5686 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
, tgsi_op2
},
5687 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_idiv
},
5688 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
, tgsi_op2
},
5689 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
, tgsi_op2
},
5690 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
, tgsi_ineg
},
5691 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
, tgsi_op2
},
5692 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
, tgsi_op2
},
5693 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
, tgsi_op2_swap
},
5694 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
, tgsi_op2
},
5695 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
, tgsi_op2
},
5696 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
, tgsi_op2
},
5697 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_udiv
},
5698 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umad
},
5699 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
, tgsi_op2
},
5700 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
, tgsi_op2
},
5701 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umod
},
5702 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
, cayman_mul_int_instr
},
5703 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
, tgsi_op2
},
5704 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
, tgsi_op2
},
5705 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
, tgsi_op2
},
5706 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
, tgsi_op2_swap
},
5707 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
, tgsi_op2
},
5708 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5709 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5710 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5711 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5712 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
5713 {TGSI_OPCODE_SAMPLE_I
, 0, 0, tgsi_unsupported
},
5714 {TGSI_OPCODE_SAMPLE_I_MS
, 0, 0, tgsi_unsupported
},
5715 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
5716 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
5717 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
5718 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
5719 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
5720 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
5721 {TGSI_OPCODE_SVIEWINFO
, 0, 0, tgsi_unsupported
},
5722 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
5723 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
5724 {TGSI_OPCODE_UARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
, tgsi_eg_arl
},
5725 {TGSI_OPCODE_UCMP
, 0, 0, tgsi_unsupported
},
5726 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
5727 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
5728 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},