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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "pipe/p_shader_tokens.h"
31 #include "tgsi/tgsi_info.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "util/u_memory.h"
36 #include <stdio.h>
37 #include <errno.h>
38 #include <byteswap.h>
39
40 /* CAYMAN notes
41 Why CAYMAN got loops for lots of instructions is explained here.
42
43 -These 8xx t-slot only ops are implemented in all vector slots.
44 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
45 These 8xx t-slot only opcodes become vector ops, with all four
46 slots expecting the arguments on sources a and b. Result is
47 broadcast to all channels.
48 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
49 These 8xx t-slot only opcodes become vector ops in the z, y, and
50 x slots.
51 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
52 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
53 SQRT_IEEE/_64
54 SIN/COS
55 The w slot may have an independent co-issued operation, or if the
56 result is required to be in the w slot, the opcode above may be
57 issued in the w slot as well.
58 The compiler must issue the source argument to slots z, y, and x
59 */
60
61 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
62 struct r600_pipe_shader *pipeshader,
63 struct r600_shader_key key);
64
65 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
66 {
67 struct tgsi_parse_context parse;
68
69 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
70 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
71 return ~0;
72 }
73 return parse.FullHeader.Processor.Processor;
74 }
75
76 static bool r600_can_dump_shader(struct r600_screen *rscreen, unsigned processor_type)
77 {
78 switch (processor_type) {
79 case TGSI_PROCESSOR_VERTEX:
80 return (rscreen->debug_flags & DBG_VS) != 0;
81 case TGSI_PROCESSOR_GEOMETRY:
82 return (rscreen->debug_flags & DBG_GS) != 0;
83 case TGSI_PROCESSOR_FRAGMENT:
84 return (rscreen->debug_flags & DBG_PS) != 0;
85 case TGSI_PROCESSOR_COMPUTE:
86 return (rscreen->debug_flags & DBG_CS) != 0;
87 default:
88 return false;
89 }
90 }
91
92 static void r600_dump_streamout(struct pipe_stream_output_info *so)
93 {
94 unsigned i;
95
96 fprintf(stderr, "STREAMOUT\n");
97 for (i = 0; i < so->num_outputs; i++) {
98 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
99 so->output[i].start_component;
100 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
101 i, so->output[i].output_buffer,
102 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
103 so->output[i].register_index,
104 mask & 1 ? "x" : "",
105 mask & 2 ? "y" : "",
106 mask & 4 ? "z" : "",
107 mask & 8 ? "w" : "",
108 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
109 }
110 }
111
112 int r600_pipe_shader_create(struct pipe_context *ctx,
113 struct r600_pipe_shader *shader,
114 struct r600_shader_key key)
115 {
116 struct r600_context *rctx = (struct r600_context *)ctx;
117 struct r600_pipe_shader_selector *sel = shader->selector;
118 int r, i;
119 uint32_t *ptr;
120 bool dump = r600_can_dump_shader(rctx->screen, tgsi_get_processor_type(sel->tokens));
121
122 shader->shader.bc.isa = rctx->isa;
123
124 if (dump) {
125 fprintf(stderr, "--------------------------------------------------------------\n");
126 tgsi_dump(sel->tokens, 0);
127
128 if (sel->so.num_outputs) {
129 r600_dump_streamout(&sel->so);
130 }
131 }
132 r = r600_shader_from_tgsi(rctx->screen, shader, key);
133 if (r) {
134 R600_ERR("translation from TGSI failed !\n");
135 return r;
136 }
137 r = r600_bytecode_build(&shader->shader.bc);
138 if (r) {
139 R600_ERR("building bytecode failed !\n");
140 return r;
141 }
142 if (dump) {
143 fprintf(stderr, "--------------------------------------------------------------\n");
144 r600_bytecode_disasm(&shader->shader.bc);
145 fprintf(stderr, "______________________________________________________________\n");
146 }
147
148
149 /* Store the shader in a buffer. */
150 if (shader->bo == NULL) {
151 shader->bo = (struct r600_resource*)
152 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
153 if (shader->bo == NULL) {
154 return -ENOMEM;
155 }
156 ptr = r600_buffer_mmap_sync_with_rings(rctx, shader->bo, PIPE_TRANSFER_WRITE);
157 if (R600_BIG_ENDIAN) {
158 for (i = 0; i < shader->shader.bc.ndw; ++i) {
159 ptr[i] = bswap_32(shader->shader.bc.bytecode[i]);
160 }
161 } else {
162 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
163 }
164 rctx->ws->buffer_unmap(shader->bo->cs_buf);
165 }
166
167 /* Build state. */
168 switch (shader->shader.processor_type) {
169 case TGSI_PROCESSOR_VERTEX:
170 if (rctx->chip_class >= EVERGREEN) {
171 evergreen_update_vs_state(ctx, shader);
172 } else {
173 r600_update_vs_state(ctx, shader);
174 }
175 break;
176 case TGSI_PROCESSOR_FRAGMENT:
177 if (rctx->chip_class >= EVERGREEN) {
178 evergreen_update_ps_state(ctx, shader);
179 } else {
180 r600_update_ps_state(ctx, shader);
181 }
182 break;
183 default:
184 return -EINVAL;
185 }
186 return 0;
187 }
188
189 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
190 {
191 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
192 r600_bytecode_clear(&shader->shader.bc);
193 r600_release_command_buffer(&shader->command_buffer);
194 }
195
196 /*
197 * tgsi -> r600 shader
198 */
199 struct r600_shader_tgsi_instruction;
200
201 struct r600_shader_src {
202 unsigned sel;
203 unsigned swizzle[4];
204 unsigned neg;
205 unsigned abs;
206 unsigned rel;
207 unsigned kc_bank;
208 uint32_t value[4];
209 };
210
211 struct r600_shader_ctx {
212 struct tgsi_shader_info info;
213 struct tgsi_parse_context parse;
214 const struct tgsi_token *tokens;
215 unsigned type;
216 unsigned file_offset[TGSI_FILE_COUNT];
217 unsigned temp_reg;
218 struct r600_shader_tgsi_instruction *inst_info;
219 struct r600_bytecode *bc;
220 struct r600_shader *shader;
221 struct r600_shader_src src[4];
222 uint32_t *literals;
223 uint32_t nliterals;
224 uint32_t max_driver_temp_used;
225 boolean use_llvm;
226 /* needed for evergreen interpolation */
227 boolean input_centroid;
228 boolean input_linear;
229 boolean input_perspective;
230 int num_interp_gpr;
231 int face_gpr;
232 int colors_used;
233 boolean clip_vertex_write;
234 unsigned cv_output;
235 int fragcoord_input;
236 int native_integers;
237 };
238
239 struct r600_shader_tgsi_instruction {
240 unsigned tgsi_opcode;
241 unsigned is_op3;
242 unsigned op;
243 int (*process)(struct r600_shader_ctx *ctx);
244 };
245
246 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
247 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
248 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
249 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
250 static int tgsi_else(struct r600_shader_ctx *ctx);
251 static int tgsi_endif(struct r600_shader_ctx *ctx);
252 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
253 static int tgsi_endloop(struct r600_shader_ctx *ctx);
254 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
255
256 /*
257 * bytestream -> r600 shader
258 *
259 * These functions are used to transform the output of the LLVM backend into
260 * struct r600_bytecode.
261 */
262
263 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
264 unsigned char * bytes, unsigned num_bytes);
265
266 #ifdef HAVE_OPENCL
267 int r600_compute_shader_create(struct pipe_context * ctx,
268 LLVMModuleRef mod, struct r600_bytecode * bytecode)
269 {
270 struct r600_context *r600_ctx = (struct r600_context *)ctx;
271 unsigned char * bytes;
272 unsigned byte_count;
273 struct r600_shader_ctx shader_ctx;
274 boolean use_kill = false;
275 bool dump = (r600_ctx->screen->debug_flags & DBG_CS) != 0;
276
277 shader_ctx.bc = bytecode;
278 r600_bytecode_init(shader_ctx.bc, r600_ctx->chip_class, r600_ctx->family,
279 r600_ctx->screen->msaa_texture_support);
280 shader_ctx.bc->type = TGSI_PROCESSOR_COMPUTE;
281 shader_ctx.bc->isa = r600_ctx->isa;
282 r600_llvm_compile(mod, &bytes, &byte_count, r600_ctx->family,
283 shader_ctx.bc, &use_kill, dump);
284 r600_bytecode_from_byte_stream(&shader_ctx, bytes, byte_count);
285 if (shader_ctx.bc->chip_class == CAYMAN) {
286 cm_bytecode_add_cf_end(shader_ctx.bc);
287 }
288 r600_bytecode_build(shader_ctx.bc);
289 if (dump) {
290 r600_bytecode_disasm(shader_ctx.bc);
291 }
292 free(bytes);
293 return 1;
294 }
295
296 #endif /* HAVE_OPENCL */
297
298 static uint32_t i32_from_byte_stream(unsigned char * bytes,
299 unsigned * bytes_read)
300 {
301 unsigned i;
302 uint32_t out = 0;
303 for (i = 0; i < 4; i++) {
304 out |= bytes[(*bytes_read)++] << (8 * i);
305 }
306 return out;
307 }
308
309 static unsigned r600_src_from_byte_stream(unsigned char * bytes,
310 unsigned bytes_read, struct r600_bytecode_alu * alu, unsigned src_idx)
311 {
312 unsigned i;
313 unsigned sel0, sel1;
314 sel0 = bytes[bytes_read++];
315 sel1 = bytes[bytes_read++];
316 alu->src[src_idx].sel = sel0 | (sel1 << 8);
317 alu->src[src_idx].chan = bytes[bytes_read++];
318 alu->src[src_idx].neg = bytes[bytes_read++];
319 alu->src[src_idx].abs = bytes[bytes_read++];
320 alu->src[src_idx].rel = bytes[bytes_read++];
321 alu->src[src_idx].kc_bank = bytes[bytes_read++];
322 for (i = 0; i < 4; i++) {
323 alu->src[src_idx].value |= bytes[bytes_read++] << (i * 8);
324 }
325 return bytes_read;
326 }
327
328 static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
329 unsigned char * bytes, unsigned bytes_read)
330 {
331 unsigned src_idx, src_num;
332 struct r600_bytecode_alu alu;
333 unsigned src_use_sel[3];
334 const struct alu_op_info *alu_op;
335 unsigned src_sel[3] = {};
336 uint32_t word0, word1;
337
338 src_num = bytes[bytes_read++];
339
340 memset(&alu, 0, sizeof(alu));
341 for(src_idx = 0; src_idx < src_num; src_idx++) {
342 unsigned i;
343 src_use_sel[src_idx] = bytes[bytes_read++];
344 for (i = 0; i < 4; i++) {
345 src_sel[src_idx] |= bytes[bytes_read++] << (i * 8);
346 }
347 for (i = 0; i < 4; i++) {
348 alu.src[src_idx].value |= bytes[bytes_read++] << (i * 8);
349 }
350 }
351
352 word0 = i32_from_byte_stream(bytes, &bytes_read);
353 word1 = i32_from_byte_stream(bytes, &bytes_read);
354
355 switch(ctx->bc->chip_class) {
356 default:
357 case R600:
358 r600_bytecode_alu_read(ctx->bc, &alu, word0, word1);
359 break;
360 case R700:
361 case EVERGREEN:
362 case CAYMAN:
363 r700_bytecode_alu_read(ctx->bc, &alu, word0, word1);
364 break;
365 }
366
367 for(src_idx = 0; src_idx < src_num; src_idx++) {
368 if (src_use_sel[src_idx]) {
369 unsigned sel = src_sel[src_idx];
370
371 alu.src[src_idx].chan = sel & 3;
372 sel >>= 2;
373
374 if (sel>=512) { /* constant */
375 sel -= 512;
376 alu.src[src_idx].kc_bank = sel >> 12;
377 alu.src[src_idx].sel = (sel & 4095) + 512;
378 }
379 else {
380 alu.src[src_idx].sel = sel;
381 }
382 }
383 }
384
385 alu_op = r600_isa_alu(alu.op);
386
387 #if HAVE_LLVM < 0x0302
388 if ((alu_op->flags & AF_PRED) && alu_op->src_count == 2) {
389 alu.update_pred = 1;
390 alu.dst.write = 0;
391 alu.src[1].sel = V_SQ_ALU_SRC_0;
392 alu.src[1].chan = 0;
393 alu.last = 1;
394 }
395 #endif
396
397 if (alu_op->flags & AF_MOVA) {
398 ctx->bc->ar_reg = alu.src[0].sel;
399 ctx->bc->ar_chan = alu.src[0].chan;
400 ctx->bc->ar_loaded = 0;
401 return bytes_read;
402 }
403
404 r600_bytecode_add_alu_type(ctx->bc, &alu, ctx->bc->cf_last->op);
405
406 /* XXX: Handle other KILL instructions */
407 if (alu_op->flags & AF_KILL) {
408 ctx->shader->uses_kill = 1;
409 /* XXX: This should be enforced in the LLVM backend. */
410 ctx->bc->force_add_cf = 1;
411 }
412 return bytes_read;
413 }
414
415 static void llvm_if(struct r600_shader_ctx *ctx)
416 {
417 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
418 fc_pushlevel(ctx, FC_IF);
419 callstack_push(ctx, FC_PUSH_VPM);
420 }
421
422 static void r600_break_from_byte_stream(struct r600_shader_ctx *ctx)
423 {
424 unsigned opcode = TGSI_OPCODE_BRK;
425 if (ctx->bc->chip_class == CAYMAN)
426 ctx->inst_info = &cm_shader_tgsi_instruction[opcode];
427 else if (ctx->bc->chip_class >= EVERGREEN)
428 ctx->inst_info = &eg_shader_tgsi_instruction[opcode];
429 else
430 ctx->inst_info = &r600_shader_tgsi_instruction[opcode];
431 llvm_if(ctx);
432 tgsi_loop_brk_cont(ctx);
433 tgsi_endif(ctx);
434 }
435
436 static unsigned r600_fc_from_byte_stream(struct r600_shader_ctx *ctx,
437 unsigned char * bytes, unsigned bytes_read)
438 {
439 struct r600_bytecode_alu alu;
440 unsigned inst;
441 memset(&alu, 0, sizeof(alu));
442 bytes_read = r600_src_from_byte_stream(bytes, bytes_read, &alu, 0);
443 inst = bytes[bytes_read++];
444 switch (inst) {
445 case 0: /* IF_PREDICATED */
446 llvm_if(ctx);
447 break;
448 case 1: /* ELSE */
449 tgsi_else(ctx);
450 break;
451 case 2: /* ENDIF */
452 tgsi_endif(ctx);
453 break;
454 case 3: /* BGNLOOP */
455 tgsi_bgnloop(ctx);
456 break;
457 case 4: /* ENDLOOP */
458 tgsi_endloop(ctx);
459 break;
460 case 5: /* PREDICATED_BREAK */
461 r600_break_from_byte_stream(ctx);
462 break;
463 case 6: /* CONTINUE */
464 {
465 unsigned opcode = TGSI_OPCODE_CONT;
466 if (ctx->bc->chip_class == CAYMAN) {
467 ctx->inst_info =
468 &cm_shader_tgsi_instruction[opcode];
469 } else if (ctx->bc->chip_class >= EVERGREEN) {
470 ctx->inst_info =
471 &eg_shader_tgsi_instruction[opcode];
472 } else {
473 ctx->inst_info =
474 &r600_shader_tgsi_instruction[opcode];
475 }
476 tgsi_loop_brk_cont(ctx);
477 }
478 break;
479 }
480
481 return bytes_read;
482 }
483
484 static unsigned r600_tex_from_byte_stream(struct r600_shader_ctx *ctx,
485 unsigned char * bytes, unsigned bytes_read)
486 {
487 struct r600_bytecode_tex tex;
488
489 uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
490 uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
491 uint32_t word2 = i32_from_byte_stream(bytes, &bytes_read);
492
493 tex.op = r600_isa_fetch_by_opcode(ctx->bc->isa, G_SQ_TEX_WORD0_TEX_INST(word0));
494 tex.resource_id = G_SQ_TEX_WORD0_RESOURCE_ID(word0);
495 tex.src_gpr = G_SQ_TEX_WORD0_SRC_GPR(word0);
496 tex.src_rel = G_SQ_TEX_WORD0_SRC_REL(word0);
497 tex.dst_gpr = G_SQ_TEX_WORD1_DST_GPR(word1);
498 tex.dst_rel = G_SQ_TEX_WORD1_DST_REL(word1);
499 tex.dst_sel_x = G_SQ_TEX_WORD1_DST_SEL_X(word1);
500 tex.dst_sel_y = G_SQ_TEX_WORD1_DST_SEL_Y(word1);
501 tex.dst_sel_z = G_SQ_TEX_WORD1_DST_SEL_Z(word1);
502 tex.dst_sel_w = G_SQ_TEX_WORD1_DST_SEL_W(word1);
503 tex.lod_bias = G_SQ_TEX_WORD1_LOD_BIAS(word1);
504 tex.coord_type_x = G_SQ_TEX_WORD1_COORD_TYPE_X(word1);
505 tex.coord_type_y = G_SQ_TEX_WORD1_COORD_TYPE_Y(word1);
506 tex.coord_type_z = G_SQ_TEX_WORD1_COORD_TYPE_Z(word1);
507 tex.coord_type_w = G_SQ_TEX_WORD1_COORD_TYPE_W(word1);
508 tex.offset_x = G_SQ_TEX_WORD2_OFFSET_X(word2);
509 tex.offset_y = G_SQ_TEX_WORD2_OFFSET_Y(word2);
510 tex.offset_z = G_SQ_TEX_WORD2_OFFSET_Z(word2);
511 tex.sampler_id = G_SQ_TEX_WORD2_SAMPLER_ID(word2);
512 tex.src_sel_x = G_SQ_TEX_WORD2_SRC_SEL_X(word2);
513 tex.src_sel_y = G_SQ_TEX_WORD2_SRC_SEL_Y(word2);
514 tex.src_sel_z = G_SQ_TEX_WORD2_SRC_SEL_Z(word2);
515 tex.src_sel_w = G_SQ_TEX_WORD2_SRC_SEL_W(word2);
516 tex.offset_x <<= 1;
517 tex.offset_y <<= 1;
518 tex.offset_z <<= 1;
519
520 tex.inst_mod = 0;
521
522 r600_bytecode_add_tex(ctx->bc, &tex);
523
524 return bytes_read;
525 }
526
527 static int r600_vtx_from_byte_stream(struct r600_shader_ctx *ctx,
528 unsigned char * bytes, unsigned bytes_read)
529 {
530 struct r600_bytecode_vtx vtx;
531
532 uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
533 uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
534 uint32_t word2 = i32_from_byte_stream(bytes, &bytes_read);
535
536 memset(&vtx, 0, sizeof(vtx));
537
538 /* WORD0 */
539 vtx.op = r600_isa_fetch_by_opcode(ctx->bc->isa,
540 G_SQ_VTX_WORD0_VTX_INST(word0));
541 vtx.fetch_type = G_SQ_VTX_WORD0_FETCH_TYPE(word0);
542 vtx.buffer_id = G_SQ_VTX_WORD0_BUFFER_ID(word0);
543 vtx.src_gpr = G_SQ_VTX_WORD0_SRC_GPR(word0);
544 vtx.src_sel_x = G_SQ_VTX_WORD0_SRC_SEL_X(word0);
545 vtx.mega_fetch_count = G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(word0);
546
547 /* WORD1 */
548 vtx.dst_gpr = G_SQ_VTX_WORD1_GPR_DST_GPR(word1);
549 vtx.dst_sel_x = G_SQ_VTX_WORD1_DST_SEL_X(word1);
550 vtx.dst_sel_y = G_SQ_VTX_WORD1_DST_SEL_Y(word1);
551 vtx.dst_sel_z = G_SQ_VTX_WORD1_DST_SEL_Z(word1);
552 vtx.dst_sel_w = G_SQ_VTX_WORD1_DST_SEL_W(word1);
553 vtx.use_const_fields = G_SQ_VTX_WORD1_USE_CONST_FIELDS(word1);
554 vtx.data_format = G_SQ_VTX_WORD1_DATA_FORMAT(word1);
555 vtx.num_format_all = G_SQ_VTX_WORD1_NUM_FORMAT_ALL(word1);
556 vtx.format_comp_all = G_SQ_VTX_WORD1_FORMAT_COMP_ALL(word1);
557 vtx.srf_mode_all = G_SQ_VTX_WORD1_SRF_MODE_ALL(word1);
558
559 /* WORD 2*/
560 vtx.offset = G_SQ_VTX_WORD2_OFFSET(word2);
561 vtx.endian = G_SQ_VTX_WORD2_ENDIAN_SWAP(word2);
562
563 if (r600_bytecode_add_vtx(ctx->bc, &vtx)) {
564 fprintf(stderr, "Error adding vtx\n");
565 }
566
567 /* Use the Texture Cache for compute shaders*/
568 if (ctx->bc->chip_class >= EVERGREEN &&
569 ctx->bc->type == TGSI_PROCESSOR_COMPUTE) {
570 ctx->bc->cf_last->op = CF_OP_TEX;
571 }
572 return bytes_read;
573 }
574
575 static int r600_export_from_byte_stream(struct r600_shader_ctx *ctx,
576 unsigned char * bytes, unsigned bytes_read)
577 {
578 uint32_t word0 = 0, word1 = 0;
579 struct r600_bytecode_output output;
580 memset(&output, 0, sizeof(struct r600_bytecode_output));
581 word0 = i32_from_byte_stream(bytes, &bytes_read);
582 word1 = i32_from_byte_stream(bytes, &bytes_read);
583 if (ctx->bc->chip_class >= EVERGREEN)
584 eg_bytecode_export_read(ctx->bc, &output, word0,word1);
585 else
586 r600_bytecode_export_read(ctx->bc, &output, word0,word1);
587 r600_bytecode_add_output(ctx->bc, &output);
588 return bytes_read;
589 }
590
591 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
592 unsigned char * bytes, unsigned num_bytes)
593 {
594 unsigned bytes_read = 0;
595 unsigned i, byte;
596 while (bytes_read < num_bytes) {
597 char inst_type = bytes[bytes_read++];
598 switch (inst_type) {
599 case 0:
600 bytes_read = r600_alu_from_byte_stream(ctx, bytes,
601 bytes_read);
602 break;
603 case 1:
604 bytes_read = r600_tex_from_byte_stream(ctx, bytes,
605 bytes_read);
606 break;
607 case 2:
608 bytes_read = r600_fc_from_byte_stream(ctx, bytes,
609 bytes_read);
610 break;
611 case 3:
612 r600_bytecode_add_cfinst(ctx->bc, CF_NATIVE);
613 for (i = 0; i < 2; i++) {
614 for (byte = 0 ; byte < 4; byte++) {
615 ctx->bc->cf_last->isa[i] |=
616 (bytes[bytes_read++] << (byte * 8));
617 }
618 }
619 break;
620
621 case 4:
622 bytes_read = r600_vtx_from_byte_stream(ctx, bytes,
623 bytes_read);
624 break;
625 case 5:
626 bytes_read = r600_export_from_byte_stream(ctx, bytes,
627 bytes_read);
628 break;
629 case 6: {
630 int32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
631 int32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
632
633 r600_bytecode_add_cf(ctx->bc);
634 ctx->bc->cf_last->op = r600_isa_cf_by_opcode(ctx->bc->isa, G_SQ_CF_ALU_WORD1_CF_INST(word1), 1);
635 ctx->bc->cf_last->kcache[0].bank = G_SQ_CF_ALU_WORD0_KCACHE_BANK0(word0);
636 ctx->bc->cf_last->kcache[0].addr = G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(word1);
637 ctx->bc->cf_last->kcache[0].mode = G_SQ_CF_ALU_WORD0_KCACHE_MODE0(word0);
638 ctx->bc->cf_last->kcache[1].bank = G_SQ_CF_ALU_WORD0_KCACHE_BANK1(word0);
639 ctx->bc->cf_last->kcache[1].addr = G_SQ_CF_ALU_WORD1_KCACHE_ADDR1(word1);
640 ctx->bc->cf_last->kcache[1].mode = G_SQ_CF_ALU_WORD1_KCACHE_MODE1(word1);
641 break;
642 }
643 default:
644 /* XXX: Error here */
645 break;
646 }
647 }
648 }
649
650 /* End bytestream -> r600 shader functions*/
651
652 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
653 {
654 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
655 int j;
656
657 if (i->Instruction.NumDstRegs > 1) {
658 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
659 return -EINVAL;
660 }
661 if (i->Instruction.Predicate) {
662 R600_ERR("predicate unsupported\n");
663 return -EINVAL;
664 }
665 #if 0
666 if (i->Instruction.Label) {
667 R600_ERR("label unsupported\n");
668 return -EINVAL;
669 }
670 #endif
671 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
672 if (i->Src[j].Register.Dimension) {
673 if (i->Src[j].Register.File != TGSI_FILE_CONSTANT) {
674 R600_ERR("unsupported src %d (dimension %d)\n", j,
675 i->Src[j].Register.Dimension);
676 return -EINVAL;
677 }
678 }
679 }
680 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
681 if (i->Dst[j].Register.Dimension) {
682 R600_ERR("unsupported dst (dimension)\n");
683 return -EINVAL;
684 }
685 }
686 return 0;
687 }
688
689 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
690 int input)
691 {
692 int ij_index = 0;
693
694 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
695 if (ctx->shader->input[input].centroid)
696 ij_index++;
697 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
698 /* if we have perspective add one */
699 if (ctx->input_perspective) {
700 ij_index++;
701 /* if we have perspective centroid */
702 if (ctx->input_centroid)
703 ij_index++;
704 }
705 if (ctx->shader->input[input].centroid)
706 ij_index++;
707 }
708
709 ctx->shader->input[input].ij_index = ij_index;
710 }
711
712 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
713 {
714 int i, r;
715 struct r600_bytecode_alu alu;
716 int gpr = 0, base_chan = 0;
717 int ij_index = ctx->shader->input[input].ij_index;
718
719 /* work out gpr and base_chan from index */
720 gpr = ij_index / 2;
721 base_chan = (2 * (ij_index % 2)) + 1;
722
723 for (i = 0; i < 8; i++) {
724 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
725
726 if (i < 4)
727 alu.op = ALU_OP2_INTERP_ZW;
728 else
729 alu.op = ALU_OP2_INTERP_XY;
730
731 if ((i > 1) && (i < 6)) {
732 alu.dst.sel = ctx->shader->input[input].gpr;
733 alu.dst.write = 1;
734 }
735
736 alu.dst.chan = i % 4;
737
738 alu.src[0].sel = gpr;
739 alu.src[0].chan = (base_chan - (i % 2));
740
741 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
742
743 alu.bank_swizzle_force = SQ_ALU_VEC_210;
744 if ((i % 4) == 3)
745 alu.last = 1;
746 r = r600_bytecode_add_alu(ctx->bc, &alu);
747 if (r)
748 return r;
749 }
750 return 0;
751 }
752
753 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
754 {
755 int i, r;
756 struct r600_bytecode_alu alu;
757
758 for (i = 0; i < 4; i++) {
759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
760
761 alu.op = ALU_OP1_INTERP_LOAD_P0;
762
763 alu.dst.sel = ctx->shader->input[input].gpr;
764 alu.dst.write = 1;
765
766 alu.dst.chan = i;
767
768 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
769 alu.src[0].chan = i;
770
771 if (i == 3)
772 alu.last = 1;
773 r = r600_bytecode_add_alu(ctx->bc, &alu);
774 if (r)
775 return r;
776 }
777 return 0;
778 }
779
780 /*
781 * Special export handling in shaders
782 *
783 * shader export ARRAY_BASE for EXPORT_POS:
784 * 60 is position
785 * 61 is misc vector
786 * 62, 63 are clip distance vectors
787 *
788 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
789 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
790 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
791 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
792 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
793 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
794 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
795 * exclusive from render target index)
796 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
797 *
798 *
799 * shader export ARRAY_BASE for EXPORT_PIXEL:
800 * 0-7 CB targets
801 * 61 computed Z vector
802 *
803 * The use of the values exported in the computed Z vector are controlled
804 * by DB_SHADER_CONTROL:
805 * Z_EXPORT_ENABLE - Z as a float in RED
806 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
807 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
808 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
809 * DB_SOURCE_FORMAT - export control restrictions
810 *
811 */
812
813
814 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
815 static int r600_spi_sid(struct r600_shader_io * io)
816 {
817 int index, name = io->name;
818
819 /* These params are handled differently, they don't need
820 * semantic indices, so we'll use 0 for them.
821 */
822 if (name == TGSI_SEMANTIC_POSITION ||
823 name == TGSI_SEMANTIC_PSIZE ||
824 name == TGSI_SEMANTIC_FACE)
825 index = 0;
826 else {
827 if (name == TGSI_SEMANTIC_GENERIC) {
828 /* For generic params simply use sid from tgsi */
829 index = io->sid;
830 } else {
831 /* For non-generic params - pack name and sid into 8 bits */
832 index = 0x80 | (name<<3) | (io->sid);
833 }
834
835 /* Make sure that all really used indices have nonzero value, so
836 * we can just compare it to 0 later instead of comparing the name
837 * with different values to detect special cases. */
838 index++;
839 }
840
841 return index;
842 };
843
844 /* turn input into interpolate on EG */
845 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
846 {
847 int r = 0;
848
849 if (ctx->shader->input[index].spi_sid) {
850 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
851 if (ctx->shader->input[index].interpolate > 0) {
852 evergreen_interp_assign_ij_index(ctx, index);
853 if (!ctx->use_llvm)
854 r = evergreen_interp_alu(ctx, index);
855 } else {
856 if (!ctx->use_llvm)
857 r = evergreen_interp_flat(ctx, index);
858 }
859 }
860 return r;
861 }
862
863 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
864 {
865 struct r600_bytecode_alu alu;
866 int i, r;
867 int gpr_front = ctx->shader->input[front].gpr;
868 int gpr_back = ctx->shader->input[back].gpr;
869
870 for (i = 0; i < 4; i++) {
871 memset(&alu, 0, sizeof(alu));
872 alu.op = ALU_OP3_CNDGT;
873 alu.is_op3 = 1;
874 alu.dst.write = 1;
875 alu.dst.sel = gpr_front;
876 alu.src[0].sel = ctx->face_gpr;
877 alu.src[1].sel = gpr_front;
878 alu.src[2].sel = gpr_back;
879
880 alu.dst.chan = i;
881 alu.src[1].chan = i;
882 alu.src[2].chan = i;
883 alu.last = (i==3);
884
885 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
886 return r;
887 }
888
889 return 0;
890 }
891
892 static int tgsi_declaration(struct r600_shader_ctx *ctx)
893 {
894 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
895 int r, i, j, count = d->Range.Last - d->Range.First + 1;
896
897 switch (d->Declaration.File) {
898 case TGSI_FILE_INPUT:
899 i = ctx->shader->ninput;
900 ctx->shader->ninput += count;
901 ctx->shader->input[i].name = d->Semantic.Name;
902 ctx->shader->input[i].sid = d->Semantic.Index;
903 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
904 ctx->shader->input[i].centroid = d->Interp.Centroid;
905 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
906 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
907 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
908 switch (ctx->shader->input[i].name) {
909 case TGSI_SEMANTIC_FACE:
910 ctx->face_gpr = ctx->shader->input[i].gpr;
911 break;
912 case TGSI_SEMANTIC_COLOR:
913 ctx->colors_used++;
914 break;
915 case TGSI_SEMANTIC_POSITION:
916 ctx->fragcoord_input = i;
917 break;
918 }
919 if (ctx->bc->chip_class >= EVERGREEN) {
920 if ((r = evergreen_interp_input(ctx, i)))
921 return r;
922 }
923 }
924 for (j = 1; j < count; ++j) {
925 ctx->shader->input[i + j] = ctx->shader->input[i];
926 ctx->shader->input[i + j].gpr += j;
927 }
928 break;
929 case TGSI_FILE_OUTPUT:
930 i = ctx->shader->noutput++;
931 ctx->shader->output[i].name = d->Semantic.Name;
932 ctx->shader->output[i].sid = d->Semantic.Index;
933 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
934 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
935 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
936 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
937 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
938 switch (d->Semantic.Name) {
939 case TGSI_SEMANTIC_CLIPDIST:
940 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
941 break;
942 case TGSI_SEMANTIC_PSIZE:
943 ctx->shader->vs_out_misc_write = 1;
944 ctx->shader->vs_out_point_size = 1;
945 break;
946 case TGSI_SEMANTIC_CLIPVERTEX:
947 ctx->clip_vertex_write = TRUE;
948 ctx->cv_output = i;
949 break;
950 }
951 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
952 switch (d->Semantic.Name) {
953 case TGSI_SEMANTIC_COLOR:
954 ctx->shader->nr_ps_max_color_exports++;
955 break;
956 }
957 }
958 break;
959 case TGSI_FILE_CONSTANT:
960 case TGSI_FILE_TEMPORARY:
961 case TGSI_FILE_SAMPLER:
962 case TGSI_FILE_ADDRESS:
963 break;
964
965 case TGSI_FILE_SYSTEM_VALUE:
966 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
967 if (!ctx->native_integers) {
968 struct r600_bytecode_alu alu;
969 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
970
971 alu.op = ALU_OP1_INT_TO_FLT;
972 alu.src[0].sel = 0;
973 alu.src[0].chan = 3;
974
975 alu.dst.sel = 0;
976 alu.dst.chan = 3;
977 alu.dst.write = 1;
978 alu.last = 1;
979
980 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
981 return r;
982 }
983 break;
984 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
985 break;
986 default:
987 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
988 return -EINVAL;
989 }
990 return 0;
991 }
992
993 static int r600_get_temp(struct r600_shader_ctx *ctx)
994 {
995 return ctx->temp_reg + ctx->max_driver_temp_used++;
996 }
997
998 /*
999 * for evergreen we need to scan the shader to find the number of GPRs we need to
1000 * reserve for interpolation.
1001 *
1002 * we need to know if we are going to emit
1003 * any centroid inputs
1004 * if perspective and linear are required
1005 */
1006 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1007 {
1008 int i;
1009 int num_baryc;
1010
1011 ctx->input_linear = FALSE;
1012 ctx->input_perspective = FALSE;
1013 ctx->input_centroid = FALSE;
1014 ctx->num_interp_gpr = 1;
1015
1016 /* any centroid inputs */
1017 for (i = 0; i < ctx->info.num_inputs; i++) {
1018 /* skip position/face */
1019 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1020 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
1021 continue;
1022 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
1023 ctx->input_linear = TRUE;
1024 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
1025 ctx->input_perspective = TRUE;
1026 if (ctx->info.input_centroid[i])
1027 ctx->input_centroid = TRUE;
1028 }
1029
1030 num_baryc = 0;
1031 /* ignoring sample for now */
1032 if (ctx->input_perspective)
1033 num_baryc++;
1034 if (ctx->input_linear)
1035 num_baryc++;
1036 if (ctx->input_centroid)
1037 num_baryc *= 2;
1038
1039 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
1040
1041 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
1042 return ctx->num_interp_gpr;
1043 }
1044
1045 static void tgsi_src(struct r600_shader_ctx *ctx,
1046 const struct tgsi_full_src_register *tgsi_src,
1047 struct r600_shader_src *r600_src)
1048 {
1049 memset(r600_src, 0, sizeof(*r600_src));
1050 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1051 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1052 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1053 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1054 r600_src->neg = tgsi_src->Register.Negate;
1055 r600_src->abs = tgsi_src->Register.Absolute;
1056
1057 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1058 int index;
1059 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1060 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1061 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1062
1063 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1064 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
1065 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1066 return;
1067 }
1068 index = tgsi_src->Register.Index;
1069 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1070 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1071 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1072 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1073 r600_src->swizzle[0] = 3;
1074 r600_src->swizzle[1] = 3;
1075 r600_src->swizzle[2] = 3;
1076 r600_src->swizzle[3] = 3;
1077 r600_src->sel = 0;
1078 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1079 r600_src->swizzle[0] = 0;
1080 r600_src->swizzle[1] = 0;
1081 r600_src->swizzle[2] = 0;
1082 r600_src->swizzle[3] = 0;
1083 r600_src->sel = 0;
1084 }
1085 } else {
1086 if (tgsi_src->Register.Indirect)
1087 r600_src->rel = V_SQ_REL_RELATIVE;
1088 r600_src->sel = tgsi_src->Register.Index;
1089 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1090 }
1091 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1092 if (tgsi_src->Register.Dimension) {
1093 r600_src->kc_bank = tgsi_src->Dimension.Index;
1094 }
1095 }
1096 }
1097
1098 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
1099 {
1100 struct r600_bytecode_vtx vtx;
1101 unsigned int ar_reg;
1102 int r;
1103
1104 if (offset) {
1105 struct r600_bytecode_alu alu;
1106
1107 memset(&alu, 0, sizeof(alu));
1108
1109 alu.op = ALU_OP2_ADD_INT;
1110 alu.src[0].sel = ctx->bc->ar_reg;
1111
1112 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1113 alu.src[1].value = offset;
1114
1115 alu.dst.sel = dst_reg;
1116 alu.dst.write = 1;
1117 alu.last = 1;
1118
1119 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1120 return r;
1121
1122 ar_reg = dst_reg;
1123 } else {
1124 ar_reg = ctx->bc->ar_reg;
1125 }
1126
1127 memset(&vtx, 0, sizeof(vtx));
1128 vtx.buffer_id = cb_idx;
1129 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
1130 vtx.src_gpr = ar_reg;
1131 vtx.mega_fetch_count = 16;
1132 vtx.dst_gpr = dst_reg;
1133 vtx.dst_sel_x = 0; /* SEL_X */
1134 vtx.dst_sel_y = 1; /* SEL_Y */
1135 vtx.dst_sel_z = 2; /* SEL_Z */
1136 vtx.dst_sel_w = 3; /* SEL_W */
1137 vtx.data_format = FMT_32_32_32_32_FLOAT;
1138 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1139 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1140 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1141 vtx.endian = r600_endian_swap(32);
1142
1143 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1144 return r;
1145
1146 return 0;
1147 }
1148
1149 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1150 {
1151 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1152 struct r600_bytecode_alu alu;
1153 int i, j, k, nconst, r;
1154
1155 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1156 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1157 nconst++;
1158 }
1159 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1160 }
1161 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1162 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1163 continue;
1164 }
1165
1166 if (ctx->src[i].rel) {
1167 int treg = r600_get_temp(ctx);
1168 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
1169 return r;
1170
1171 ctx->src[i].kc_bank = 0;
1172 ctx->src[i].sel = treg;
1173 ctx->src[i].rel = 0;
1174 j--;
1175 } else if (j > 0) {
1176 int treg = r600_get_temp(ctx);
1177 for (k = 0; k < 4; k++) {
1178 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1179 alu.op = ALU_OP1_MOV;
1180 alu.src[0].sel = ctx->src[i].sel;
1181 alu.src[0].chan = k;
1182 alu.src[0].rel = ctx->src[i].rel;
1183 alu.dst.sel = treg;
1184 alu.dst.chan = k;
1185 alu.dst.write = 1;
1186 if (k == 3)
1187 alu.last = 1;
1188 r = r600_bytecode_add_alu(ctx->bc, &alu);
1189 if (r)
1190 return r;
1191 }
1192 ctx->src[i].sel = treg;
1193 ctx->src[i].rel =0;
1194 j--;
1195 }
1196 }
1197 return 0;
1198 }
1199
1200 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1201 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1202 {
1203 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1204 struct r600_bytecode_alu alu;
1205 int i, j, k, nliteral, r;
1206
1207 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1208 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1209 nliteral++;
1210 }
1211 }
1212 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1213 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1214 int treg = r600_get_temp(ctx);
1215 for (k = 0; k < 4; k++) {
1216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1217 alu.op = ALU_OP1_MOV;
1218 alu.src[0].sel = ctx->src[i].sel;
1219 alu.src[0].chan = k;
1220 alu.src[0].value = ctx->src[i].value[k];
1221 alu.dst.sel = treg;
1222 alu.dst.chan = k;
1223 alu.dst.write = 1;
1224 if (k == 3)
1225 alu.last = 1;
1226 r = r600_bytecode_add_alu(ctx->bc, &alu);
1227 if (r)
1228 return r;
1229 }
1230 ctx->src[i].sel = treg;
1231 j--;
1232 }
1233 }
1234 return 0;
1235 }
1236
1237 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1238 {
1239 int i, r, count = ctx->shader->ninput;
1240
1241 for (i = 0; i < count; i++) {
1242 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1243 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1244 if (r)
1245 return r;
1246 }
1247 }
1248 return 0;
1249 }
1250
1251 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
1252 struct r600_pipe_shader *pipeshader,
1253 struct r600_shader_key key)
1254 {
1255 struct r600_shader *shader = &pipeshader->shader;
1256 struct tgsi_token *tokens = pipeshader->selector->tokens;
1257 struct pipe_stream_output_info so = pipeshader->selector->so;
1258 struct tgsi_full_immediate *immediate;
1259 struct tgsi_full_property *property;
1260 struct r600_shader_ctx ctx;
1261 struct r600_bytecode_output output[32];
1262 unsigned output_done, noutput;
1263 unsigned opcode;
1264 int i, j, k, r = 0;
1265 int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
1266 /* Declarations used by llvm code */
1267 bool use_llvm = false;
1268 unsigned char * inst_bytes = NULL;
1269 unsigned inst_byte_count = 0;
1270
1271 #ifdef R600_USE_LLVM
1272 use_llvm = !(rscreen->debug_flags & DBG_NO_LLVM);
1273 #endif
1274 ctx.bc = &shader->bc;
1275 ctx.shader = shader;
1276 ctx.native_integers = true;
1277
1278 r600_bytecode_init(ctx.bc, rscreen->chip_class, rscreen->family,
1279 rscreen->msaa_texture_support);
1280 ctx.tokens = tokens;
1281 tgsi_scan_shader(tokens, &ctx.info);
1282 tgsi_parse_init(&ctx.parse, tokens);
1283 ctx.type = ctx.parse.FullHeader.Processor.Processor;
1284 shader->processor_type = ctx.type;
1285 ctx.bc->type = shader->processor_type;
1286
1287 ctx.face_gpr = -1;
1288 ctx.fragcoord_input = -1;
1289 ctx.colors_used = 0;
1290 ctx.clip_vertex_write = 0;
1291
1292 shader->nr_ps_color_exports = 0;
1293 shader->nr_ps_max_color_exports = 0;
1294
1295 shader->two_side = key.color_two_side;
1296
1297 /* register allocations */
1298 /* Values [0,127] correspond to GPR[0..127].
1299 * Values [128,159] correspond to constant buffer bank 0
1300 * Values [160,191] correspond to constant buffer bank 1
1301 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1302 * Values [256,287] correspond to constant buffer bank 2 (EG)
1303 * Values [288,319] correspond to constant buffer bank 3 (EG)
1304 * Other special values are shown in the list below.
1305 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1306 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1307 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1308 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1309 * 248 SQ_ALU_SRC_0: special constant 0.0.
1310 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1311 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1312 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1313 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1314 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1315 * 254 SQ_ALU_SRC_PV: previous vector result.
1316 * 255 SQ_ALU_SRC_PS: previous scalar result.
1317 */
1318 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1319 ctx.file_offset[i] = 0;
1320 }
1321 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1322 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1323 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1324 }
1325 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1326 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1327 }
1328
1329 #ifdef R600_USE_LLVM
1330 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1331 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1332 "indirect adressing. Falling back to TGSI "
1333 "backend.\n");
1334 use_llvm = 0;
1335 }
1336 #endif
1337 ctx.use_llvm = use_llvm;
1338
1339 if (use_llvm) {
1340 ctx.file_offset[TGSI_FILE_OUTPUT] =
1341 ctx.file_offset[TGSI_FILE_INPUT];
1342 } else {
1343 ctx.file_offset[TGSI_FILE_OUTPUT] =
1344 ctx.file_offset[TGSI_FILE_INPUT] +
1345 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1346 }
1347 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1348 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1349
1350 /* Outside the GPR range. This will be translated to one of the
1351 * kcache banks later. */
1352 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1353
1354 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1355 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1356 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1357 ctx.temp_reg = ctx.bc->ar_reg + 1;
1358
1359 ctx.nliterals = 0;
1360 ctx.literals = NULL;
1361 shader->fs_write_all = FALSE;
1362 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1363 tgsi_parse_token(&ctx.parse);
1364 switch (ctx.parse.FullToken.Token.Type) {
1365 case TGSI_TOKEN_TYPE_IMMEDIATE:
1366 immediate = &ctx.parse.FullToken.FullImmediate;
1367 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1368 if(ctx.literals == NULL) {
1369 r = -ENOMEM;
1370 goto out_err;
1371 }
1372 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1373 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1374 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1375 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1376 ctx.nliterals++;
1377 break;
1378 case TGSI_TOKEN_TYPE_DECLARATION:
1379 r = tgsi_declaration(&ctx);
1380 if (r)
1381 goto out_err;
1382 break;
1383 case TGSI_TOKEN_TYPE_INSTRUCTION:
1384 break;
1385 case TGSI_TOKEN_TYPE_PROPERTY:
1386 property = &ctx.parse.FullToken.FullProperty;
1387 switch (property->Property.PropertyName) {
1388 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1389 if (property->u[0].Data == 1)
1390 shader->fs_write_all = TRUE;
1391 break;
1392 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1393 /* we don't need this one */
1394 break;
1395 }
1396 break;
1397 default:
1398 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1399 r = -EINVAL;
1400 goto out_err;
1401 }
1402 }
1403
1404 /* Process two side if needed */
1405 if (shader->two_side && ctx.colors_used) {
1406 int i, count = ctx.shader->ninput;
1407 unsigned next_lds_loc = ctx.shader->nlds;
1408
1409 /* additional inputs will be allocated right after the existing inputs,
1410 * we won't need them after the color selection, so we don't need to
1411 * reserve these gprs for the rest of the shader code and to adjust
1412 * output offsets etc. */
1413 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1414 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1415
1416 if (ctx.face_gpr == -1) {
1417 i = ctx.shader->ninput++;
1418 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1419 ctx.shader->input[i].spi_sid = 0;
1420 ctx.shader->input[i].gpr = gpr++;
1421 ctx.face_gpr = ctx.shader->input[i].gpr;
1422 }
1423
1424 for (i = 0; i < count; i++) {
1425 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1426 int ni = ctx.shader->ninput++;
1427 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1428 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1429 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1430 ctx.shader->input[ni].gpr = gpr++;
1431 // TGSI to LLVM needs to know the lds position of inputs.
1432 // Non LLVM path computes it later (in process_twoside_color)
1433 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1434 ctx.shader->input[i].back_color_input = ni;
1435 if (ctx.bc->chip_class >= EVERGREEN) {
1436 if ((r = evergreen_interp_input(&ctx, ni)))
1437 return r;
1438 }
1439 }
1440 }
1441 }
1442
1443 /* LLVM backend setup */
1444 #ifdef R600_USE_LLVM
1445 if (use_llvm) {
1446 struct radeon_llvm_context radeon_llvm_ctx;
1447 LLVMModuleRef mod;
1448 bool dump = r600_can_dump_shader(rscreen, ctx.type);
1449 boolean use_kill = false;
1450
1451 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1452 radeon_llvm_ctx.type = ctx.type;
1453 radeon_llvm_ctx.two_side = shader->two_side;
1454 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1455 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1456 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1457 radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
1458 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1459 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
1460 radeon_llvm_ctx.stream_outputs = &so;
1461 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1462 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1463 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1464
1465 if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
1466 rscreen->family, ctx.bc, &use_kill, dump)) {
1467 FREE(inst_bytes);
1468 radeon_llvm_dispose(&radeon_llvm_ctx);
1469 use_llvm = 0;
1470 fprintf(stderr, "R600 LLVM backend failed to compile "
1471 "shader. Falling back to TGSI\n");
1472 } else {
1473 ctx.file_offset[TGSI_FILE_OUTPUT] =
1474 ctx.file_offset[TGSI_FILE_INPUT];
1475 }
1476 if (use_kill)
1477 ctx.shader->uses_kill = use_kill;
1478 radeon_llvm_dispose(&radeon_llvm_ctx);
1479 }
1480 #endif
1481 /* End of LLVM backend setup */
1482
1483 if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
1484 shader->nr_ps_max_color_exports = 8;
1485
1486 if (!use_llvm) {
1487 if (ctx.fragcoord_input >= 0) {
1488 if (ctx.bc->chip_class == CAYMAN) {
1489 for (j = 0 ; j < 4; j++) {
1490 struct r600_bytecode_alu alu;
1491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1492 alu.op = ALU_OP1_RECIP_IEEE;
1493 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1494 alu.src[0].chan = 3;
1495
1496 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1497 alu.dst.chan = j;
1498 alu.dst.write = (j == 3);
1499 alu.last = 1;
1500 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1501 return r;
1502 }
1503 } else {
1504 struct r600_bytecode_alu alu;
1505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1506 alu.op = ALU_OP1_RECIP_IEEE;
1507 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1508 alu.src[0].chan = 3;
1509
1510 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1511 alu.dst.chan = 3;
1512 alu.dst.write = 1;
1513 alu.last = 1;
1514 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1515 return r;
1516 }
1517 }
1518
1519 if (shader->two_side && ctx.colors_used) {
1520 if ((r = process_twoside_color_inputs(&ctx)))
1521 return r;
1522 }
1523
1524 tgsi_parse_init(&ctx.parse, tokens);
1525 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1526 tgsi_parse_token(&ctx.parse);
1527 switch (ctx.parse.FullToken.Token.Type) {
1528 case TGSI_TOKEN_TYPE_INSTRUCTION:
1529 r = tgsi_is_supported(&ctx);
1530 if (r)
1531 goto out_err;
1532 ctx.max_driver_temp_used = 0;
1533 /* reserve first tmp for everyone */
1534 r600_get_temp(&ctx);
1535
1536 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1537 if ((r = tgsi_split_constant(&ctx)))
1538 goto out_err;
1539 if ((r = tgsi_split_literal_constant(&ctx)))
1540 goto out_err;
1541 if (ctx.bc->chip_class == CAYMAN)
1542 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1543 else if (ctx.bc->chip_class >= EVERGREEN)
1544 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1545 else
1546 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1547 r = ctx.inst_info->process(&ctx);
1548 if (r)
1549 goto out_err;
1550 break;
1551 default:
1552 break;
1553 }
1554 }
1555 }
1556
1557 /* Reset the temporary register counter. */
1558 ctx.max_driver_temp_used = 0;
1559
1560 /* Get instructions if we are using the LLVM backend. */
1561 if (use_llvm) {
1562 r600_bytecode_from_byte_stream(&ctx, inst_bytes, inst_byte_count);
1563 FREE(inst_bytes);
1564 }
1565
1566 noutput = shader->noutput;
1567
1568 if (ctx.clip_vertex_write) {
1569 unsigned clipdist_temp[2];
1570
1571 clipdist_temp[0] = r600_get_temp(&ctx);
1572 clipdist_temp[1] = r600_get_temp(&ctx);
1573
1574 /* need to convert a clipvertex write into clipdistance writes and not export
1575 the clip vertex anymore */
1576
1577 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1578 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1579 shader->output[noutput].gpr = clipdist_temp[0];
1580 noutput++;
1581 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1582 shader->output[noutput].gpr = clipdist_temp[1];
1583 noutput++;
1584
1585 /* reset spi_sid for clipvertex output to avoid confusing spi */
1586 shader->output[ctx.cv_output].spi_sid = 0;
1587
1588 shader->clip_dist_write = 0xFF;
1589
1590 for (i = 0; i < 8; i++) {
1591 int oreg = i >> 2;
1592 int ochan = i & 3;
1593
1594 for (j = 0; j < 4; j++) {
1595 struct r600_bytecode_alu alu;
1596 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1597 alu.op = ALU_OP2_DOT4;
1598 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1599 alu.src[0].chan = j;
1600
1601 alu.src[1].sel = 512 + i;
1602 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1603 alu.src[1].chan = j;
1604
1605 alu.dst.sel = clipdist_temp[oreg];
1606 alu.dst.chan = j;
1607 alu.dst.write = (j == ochan);
1608 if (j == 3)
1609 alu.last = 1;
1610 if (!use_llvm)
1611 r = r600_bytecode_add_alu(ctx.bc, &alu);
1612 if (r)
1613 return r;
1614 }
1615 }
1616 }
1617
1618 /* Add stream outputs. */
1619 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
1620 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1621
1622 /* Sanity checking. */
1623 if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1624 R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
1625 r = -EINVAL;
1626 goto out_err;
1627 }
1628 for (i = 0; i < so.num_outputs; i++) {
1629 if (so.output[i].output_buffer >= 4) {
1630 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1631 so.output[i].output_buffer);
1632 r = -EINVAL;
1633 goto out_err;
1634 }
1635 }
1636
1637 /* Initialize locations where the outputs are stored. */
1638 for (i = 0; i < so.num_outputs; i++) {
1639 so_gpr[i] = shader->output[so.output[i].register_index].gpr;
1640
1641 /* Lower outputs with dst_offset < start_component.
1642 *
1643 * We can only output 4D vectors with a write mask, e.g. we can
1644 * only output the W component at offset 3, etc. If we want
1645 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1646 * to move it to X and output X. */
1647 if (so.output[i].dst_offset < so.output[i].start_component) {
1648 unsigned tmp = r600_get_temp(&ctx);
1649
1650 for (j = 0; j < so.output[i].num_components; j++) {
1651 struct r600_bytecode_alu alu;
1652 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1653 alu.op = ALU_OP1_MOV;
1654 alu.src[0].sel = so_gpr[i];
1655 alu.src[0].chan = so.output[i].start_component + j;
1656
1657 alu.dst.sel = tmp;
1658 alu.dst.chan = j;
1659 alu.dst.write = 1;
1660 if (j == so.output[i].num_components - 1)
1661 alu.last = 1;
1662 r = r600_bytecode_add_alu(ctx.bc, &alu);
1663 if (r)
1664 return r;
1665 }
1666 so.output[i].start_component = 0;
1667 so_gpr[i] = tmp;
1668 }
1669 }
1670
1671 /* Write outputs to buffers. */
1672 for (i = 0; i < so.num_outputs; i++) {
1673 struct r600_bytecode_output output;
1674
1675 memset(&output, 0, sizeof(struct r600_bytecode_output));
1676 output.gpr = so_gpr[i];
1677 output.elem_size = so.output[i].num_components;
1678 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1679 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1680 output.burst_count = 1;
1681 output.barrier = 1;
1682 /* array_size is an upper limit for the burst_count
1683 * with MEM_STREAM instructions */
1684 output.array_size = 0xFFF;
1685 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1686 if (ctx.bc->chip_class >= EVERGREEN) {
1687 switch (so.output[i].output_buffer) {
1688 case 0:
1689 output.op = CF_OP_MEM_STREAM0_BUF0;
1690 break;
1691 case 1:
1692 output.op = CF_OP_MEM_STREAM0_BUF1;
1693 break;
1694 case 2:
1695 output.op = CF_OP_MEM_STREAM0_BUF2;
1696 break;
1697 case 3:
1698 output.op = CF_OP_MEM_STREAM0_BUF3;
1699 break;
1700 }
1701 } else {
1702 switch (so.output[i].output_buffer) {
1703 case 0:
1704 output.op = CF_OP_MEM_STREAM0;
1705 break;
1706 case 1:
1707 output.op = CF_OP_MEM_STREAM1;
1708 break;
1709 case 2:
1710 output.op = CF_OP_MEM_STREAM2;
1711 break;
1712 case 3:
1713 output.op = CF_OP_MEM_STREAM3;
1714 break;
1715 }
1716 }
1717 r = r600_bytecode_add_output(ctx.bc, &output);
1718 if (r)
1719 goto out_err;
1720 }
1721 }
1722
1723 /* export output */
1724 for (i = 0, j = 0; i < noutput; i++, j++) {
1725 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1726 output[j].gpr = shader->output[i].gpr;
1727 output[j].elem_size = 3;
1728 output[j].swizzle_x = 0;
1729 output[j].swizzle_y = 1;
1730 output[j].swizzle_z = 2;
1731 output[j].swizzle_w = 3;
1732 output[j].burst_count = 1;
1733 output[j].barrier = 1;
1734 output[j].type = -1;
1735 output[j].op = CF_OP_EXPORT;
1736 switch (ctx.type) {
1737 case TGSI_PROCESSOR_VERTEX:
1738 switch (shader->output[i].name) {
1739 case TGSI_SEMANTIC_POSITION:
1740 output[j].array_base = next_pos_base++;
1741 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1742 break;
1743
1744 case TGSI_SEMANTIC_PSIZE:
1745 output[j].array_base = next_pos_base++;
1746 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1747 break;
1748 case TGSI_SEMANTIC_CLIPVERTEX:
1749 j--;
1750 break;
1751 case TGSI_SEMANTIC_CLIPDIST:
1752 output[j].array_base = next_pos_base++;
1753 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1754 /* spi_sid is 0 for clipdistance outputs that were generated
1755 * for clipvertex - we don't need to pass them to PS */
1756 if (shader->output[i].spi_sid) {
1757 j++;
1758 /* duplicate it as PARAM to pass to the pixel shader */
1759 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1760 output[j].array_base = next_param_base++;
1761 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1762 }
1763 break;
1764 case TGSI_SEMANTIC_FOG:
1765 output[j].swizzle_y = 4; /* 0 */
1766 output[j].swizzle_z = 4; /* 0 */
1767 output[j].swizzle_w = 5; /* 1 */
1768 break;
1769 }
1770 break;
1771 case TGSI_PROCESSOR_FRAGMENT:
1772 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1773 /* never export more colors than the number of CBs */
1774 if (next_pixel_base && next_pixel_base >= key.nr_cbufs) {
1775 /* skip export */
1776 j--;
1777 continue;
1778 }
1779 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1780 output[j].array_base = next_pixel_base++;
1781 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1782 shader->nr_ps_color_exports++;
1783 if (shader->fs_write_all && (rscreen->chip_class >= EVERGREEN)) {
1784 for (k = 1; k < key.nr_cbufs; k++) {
1785 j++;
1786 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1787 output[j].gpr = shader->output[i].gpr;
1788 output[j].elem_size = 3;
1789 output[j].swizzle_x = 0;
1790 output[j].swizzle_y = 1;
1791 output[j].swizzle_z = 2;
1792 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1793 output[j].burst_count = 1;
1794 output[j].barrier = 1;
1795 output[j].array_base = next_pixel_base++;
1796 output[j].op = CF_OP_EXPORT;
1797 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1798 shader->nr_ps_color_exports++;
1799 }
1800 }
1801 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1802 output[j].array_base = 61;
1803 output[j].swizzle_x = 2;
1804 output[j].swizzle_y = 7;
1805 output[j].swizzle_z = output[j].swizzle_w = 7;
1806 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1807 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1808 output[j].array_base = 61;
1809 output[j].swizzle_x = 7;
1810 output[j].swizzle_y = 1;
1811 output[j].swizzle_z = output[j].swizzle_w = 7;
1812 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1813 } else {
1814 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1815 r = -EINVAL;
1816 goto out_err;
1817 }
1818 break;
1819 default:
1820 R600_ERR("unsupported processor type %d\n", ctx.type);
1821 r = -EINVAL;
1822 goto out_err;
1823 }
1824
1825 if (output[j].type==-1) {
1826 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1827 output[j].array_base = next_param_base++;
1828 }
1829 }
1830
1831 /* add fake position export */
1832 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1833 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1834 output[j].gpr = 0;
1835 output[j].elem_size = 3;
1836 output[j].swizzle_x = 7;
1837 output[j].swizzle_y = 7;
1838 output[j].swizzle_z = 7;
1839 output[j].swizzle_w = 7;
1840 output[j].burst_count = 1;
1841 output[j].barrier = 1;
1842 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1843 output[j].array_base = next_pos_base;
1844 output[j].op = CF_OP_EXPORT;
1845 j++;
1846 }
1847
1848 /* add fake param output for vertex shader if no param is exported */
1849 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1850 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1851 output[j].gpr = 0;
1852 output[j].elem_size = 3;
1853 output[j].swizzle_x = 7;
1854 output[j].swizzle_y = 7;
1855 output[j].swizzle_z = 7;
1856 output[j].swizzle_w = 7;
1857 output[j].burst_count = 1;
1858 output[j].barrier = 1;
1859 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1860 output[j].array_base = 0;
1861 output[j].op = CF_OP_EXPORT;
1862 j++;
1863 }
1864
1865 /* add fake pixel export */
1866 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && next_pixel_base == 0) {
1867 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1868 output[j].gpr = 0;
1869 output[j].elem_size = 3;
1870 output[j].swizzle_x = 7;
1871 output[j].swizzle_y = 7;
1872 output[j].swizzle_z = 7;
1873 output[j].swizzle_w = 7;
1874 output[j].burst_count = 1;
1875 output[j].barrier = 1;
1876 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1877 output[j].array_base = 0;
1878 output[j].op = CF_OP_EXPORT;
1879 j++;
1880 }
1881
1882 noutput = j;
1883
1884 /* set export done on last export of each type */
1885 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1886 if (ctx.bc->chip_class < CAYMAN) {
1887 if (i == (noutput - 1)) {
1888 output[i].end_of_program = 1;
1889 }
1890 }
1891 if (!(output_done & (1 << output[i].type))) {
1892 output_done |= (1 << output[i].type);
1893 output[i].op = CF_OP_EXPORT_DONE;
1894 }
1895 }
1896 /* add output to bytecode */
1897 if (!use_llvm) {
1898 for (i = 0; i < noutput; i++) {
1899 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1900 if (r)
1901 goto out_err;
1902 }
1903 }
1904 /* add program end */
1905 if (!use_llvm && ctx.bc->chip_class == CAYMAN)
1906 cm_bytecode_add_cf_end(ctx.bc);
1907
1908 /* check GPR limit - we have 124 = 128 - 4
1909 * (4 are reserved as alu clause temporary registers) */
1910 if (ctx.bc->ngpr > 124) {
1911 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1912 r = -ENOMEM;
1913 goto out_err;
1914 }
1915
1916 free(ctx.literals);
1917 tgsi_parse_free(&ctx.parse);
1918 return 0;
1919 out_err:
1920 free(ctx.literals);
1921 tgsi_parse_free(&ctx.parse);
1922 return r;
1923 }
1924
1925 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1926 {
1927 R600_ERR("%s tgsi opcode unsupported\n",
1928 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1929 return -EINVAL;
1930 }
1931
1932 static int tgsi_end(struct r600_shader_ctx *ctx)
1933 {
1934 return 0;
1935 }
1936
1937 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1938 const struct r600_shader_src *shader_src,
1939 unsigned chan)
1940 {
1941 bc_src->sel = shader_src->sel;
1942 bc_src->chan = shader_src->swizzle[chan];
1943 bc_src->neg = shader_src->neg;
1944 bc_src->abs = shader_src->abs;
1945 bc_src->rel = shader_src->rel;
1946 bc_src->value = shader_src->value[bc_src->chan];
1947 bc_src->kc_bank = shader_src->kc_bank;
1948 }
1949
1950 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1951 {
1952 bc_src->abs = 1;
1953 bc_src->neg = 0;
1954 }
1955
1956 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1957 {
1958 bc_src->neg = !bc_src->neg;
1959 }
1960
1961 static void tgsi_dst(struct r600_shader_ctx *ctx,
1962 const struct tgsi_full_dst_register *tgsi_dst,
1963 unsigned swizzle,
1964 struct r600_bytecode_alu_dst *r600_dst)
1965 {
1966 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1967
1968 r600_dst->sel = tgsi_dst->Register.Index;
1969 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1970 r600_dst->chan = swizzle;
1971 r600_dst->write = 1;
1972 if (tgsi_dst->Register.Indirect)
1973 r600_dst->rel = V_SQ_REL_RELATIVE;
1974 if (inst->Instruction.Saturate) {
1975 r600_dst->clamp = 1;
1976 }
1977 }
1978
1979 static int tgsi_last_instruction(unsigned writemask)
1980 {
1981 int i, lasti = 0;
1982
1983 for (i = 0; i < 4; i++) {
1984 if (writemask & (1 << i)) {
1985 lasti = i;
1986 }
1987 }
1988 return lasti;
1989 }
1990
1991 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1992 {
1993 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1994 struct r600_bytecode_alu alu;
1995 int i, j, r;
1996 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1997
1998 for (i = 0; i < lasti + 1; i++) {
1999 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2000 continue;
2001
2002 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2003 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2004
2005 alu.op = ctx->inst_info->op;
2006 if (!swap) {
2007 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2008 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2009 }
2010 } else {
2011 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2012 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2013 }
2014 /* handle some special cases */
2015 switch (ctx->inst_info->tgsi_opcode) {
2016 case TGSI_OPCODE_SUB:
2017 r600_bytecode_src_toggle_neg(&alu.src[1]);
2018 break;
2019 case TGSI_OPCODE_ABS:
2020 r600_bytecode_src_set_abs(&alu.src[0]);
2021 break;
2022 default:
2023 break;
2024 }
2025 if (i == lasti || trans_only) {
2026 alu.last = 1;
2027 }
2028 r = r600_bytecode_add_alu(ctx->bc, &alu);
2029 if (r)
2030 return r;
2031 }
2032 return 0;
2033 }
2034
2035 static int tgsi_op2(struct r600_shader_ctx *ctx)
2036 {
2037 return tgsi_op2_s(ctx, 0, 0);
2038 }
2039
2040 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2041 {
2042 return tgsi_op2_s(ctx, 1, 0);
2043 }
2044
2045 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2046 {
2047 return tgsi_op2_s(ctx, 0, 1);
2048 }
2049
2050 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2051 {
2052 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2053 struct r600_bytecode_alu alu;
2054 int i, r;
2055 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2056
2057 for (i = 0; i < lasti + 1; i++) {
2058
2059 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2060 continue;
2061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2062 alu.op = ctx->inst_info->op;
2063
2064 alu.src[0].sel = V_SQ_ALU_SRC_0;
2065
2066 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2067
2068 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2069
2070 if (i == lasti) {
2071 alu.last = 1;
2072 }
2073 r = r600_bytecode_add_alu(ctx->bc, &alu);
2074 if (r)
2075 return r;
2076 }
2077 return 0;
2078
2079 }
2080
2081 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
2082 {
2083 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2084 int i, j, r;
2085 struct r600_bytecode_alu alu;
2086 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2087
2088 for (i = 0 ; i < last_slot; i++) {
2089 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2090 alu.op = ctx->inst_info->op;
2091 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2092 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
2093
2094 /* RSQ should take the absolute value of src */
2095 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
2096 r600_bytecode_src_set_abs(&alu.src[j]);
2097 }
2098 }
2099 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2100 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2101
2102 if (i == last_slot - 1)
2103 alu.last = 1;
2104 r = r600_bytecode_add_alu(ctx->bc, &alu);
2105 if (r)
2106 return r;
2107 }
2108 return 0;
2109 }
2110
2111 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
2112 {
2113 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2114 int i, j, k, r;
2115 struct r600_bytecode_alu alu;
2116 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2117 for (k = 0; k < last_slot; k++) {
2118 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
2119 continue;
2120
2121 for (i = 0 ; i < 4; i++) {
2122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2123 alu.op = ctx->inst_info->op;
2124 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2125 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
2126 }
2127 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2128 alu.dst.write = (i == k);
2129 if (i == 3)
2130 alu.last = 1;
2131 r = r600_bytecode_add_alu(ctx->bc, &alu);
2132 if (r)
2133 return r;
2134 }
2135 }
2136 return 0;
2137 }
2138
2139 /*
2140 * r600 - trunc to -PI..PI range
2141 * r700 - normalize by dividing by 2PI
2142 * see fdo bug 27901
2143 */
2144 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
2145 {
2146 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
2147 static float double_pi = 3.1415926535 * 2;
2148 static float neg_pi = -3.1415926535;
2149
2150 int r;
2151 struct r600_bytecode_alu alu;
2152
2153 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2154 alu.op = ALU_OP3_MULADD;
2155 alu.is_op3 = 1;
2156
2157 alu.dst.chan = 0;
2158 alu.dst.sel = ctx->temp_reg;
2159 alu.dst.write = 1;
2160
2161 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2162
2163 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2164 alu.src[1].chan = 0;
2165 alu.src[1].value = *(uint32_t *)&half_inv_pi;
2166 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2167 alu.src[2].chan = 0;
2168 alu.last = 1;
2169 r = r600_bytecode_add_alu(ctx->bc, &alu);
2170 if (r)
2171 return r;
2172
2173 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2174 alu.op = ALU_OP1_FRACT;
2175
2176 alu.dst.chan = 0;
2177 alu.dst.sel = ctx->temp_reg;
2178 alu.dst.write = 1;
2179
2180 alu.src[0].sel = ctx->temp_reg;
2181 alu.src[0].chan = 0;
2182 alu.last = 1;
2183 r = r600_bytecode_add_alu(ctx->bc, &alu);
2184 if (r)
2185 return r;
2186
2187 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2188 alu.op = ALU_OP3_MULADD;
2189 alu.is_op3 = 1;
2190
2191 alu.dst.chan = 0;
2192 alu.dst.sel = ctx->temp_reg;
2193 alu.dst.write = 1;
2194
2195 alu.src[0].sel = ctx->temp_reg;
2196 alu.src[0].chan = 0;
2197
2198 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2199 alu.src[1].chan = 0;
2200 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2201 alu.src[2].chan = 0;
2202
2203 if (ctx->bc->chip_class == R600) {
2204 alu.src[1].value = *(uint32_t *)&double_pi;
2205 alu.src[2].value = *(uint32_t *)&neg_pi;
2206 } else {
2207 alu.src[1].sel = V_SQ_ALU_SRC_1;
2208 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2209 alu.src[2].neg = 1;
2210 }
2211
2212 alu.last = 1;
2213 r = r600_bytecode_add_alu(ctx->bc, &alu);
2214 if (r)
2215 return r;
2216 return 0;
2217 }
2218
2219 static int cayman_trig(struct r600_shader_ctx *ctx)
2220 {
2221 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2222 struct r600_bytecode_alu alu;
2223 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2224 int i, r;
2225
2226 r = tgsi_setup_trig(ctx);
2227 if (r)
2228 return r;
2229
2230
2231 for (i = 0; i < last_slot; i++) {
2232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2233 alu.op = ctx->inst_info->op;
2234 alu.dst.chan = i;
2235
2236 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2237 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2238
2239 alu.src[0].sel = ctx->temp_reg;
2240 alu.src[0].chan = 0;
2241 if (i == last_slot - 1)
2242 alu.last = 1;
2243 r = r600_bytecode_add_alu(ctx->bc, &alu);
2244 if (r)
2245 return r;
2246 }
2247 return 0;
2248 }
2249
2250 static int tgsi_trig(struct r600_shader_ctx *ctx)
2251 {
2252 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2253 struct r600_bytecode_alu alu;
2254 int i, r;
2255 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2256
2257 r = tgsi_setup_trig(ctx);
2258 if (r)
2259 return r;
2260
2261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2262 alu.op = ctx->inst_info->op;
2263 alu.dst.chan = 0;
2264 alu.dst.sel = ctx->temp_reg;
2265 alu.dst.write = 1;
2266
2267 alu.src[0].sel = ctx->temp_reg;
2268 alu.src[0].chan = 0;
2269 alu.last = 1;
2270 r = r600_bytecode_add_alu(ctx->bc, &alu);
2271 if (r)
2272 return r;
2273
2274 /* replicate result */
2275 for (i = 0; i < lasti + 1; i++) {
2276 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2277 continue;
2278
2279 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2280 alu.op = ALU_OP1_MOV;
2281
2282 alu.src[0].sel = ctx->temp_reg;
2283 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2284 if (i == lasti)
2285 alu.last = 1;
2286 r = r600_bytecode_add_alu(ctx->bc, &alu);
2287 if (r)
2288 return r;
2289 }
2290 return 0;
2291 }
2292
2293 static int tgsi_scs(struct r600_shader_ctx *ctx)
2294 {
2295 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2296 struct r600_bytecode_alu alu;
2297 int i, r;
2298
2299 /* We'll only need the trig stuff if we are going to write to the
2300 * X or Y components of the destination vector.
2301 */
2302 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2303 r = tgsi_setup_trig(ctx);
2304 if (r)
2305 return r;
2306 }
2307
2308 /* dst.x = COS */
2309 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2310 if (ctx->bc->chip_class == CAYMAN) {
2311 for (i = 0 ; i < 3; i++) {
2312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2313 alu.op = ALU_OP1_COS;
2314 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2315
2316 if (i == 0)
2317 alu.dst.write = 1;
2318 else
2319 alu.dst.write = 0;
2320 alu.src[0].sel = ctx->temp_reg;
2321 alu.src[0].chan = 0;
2322 if (i == 2)
2323 alu.last = 1;
2324 r = r600_bytecode_add_alu(ctx->bc, &alu);
2325 if (r)
2326 return r;
2327 }
2328 } else {
2329 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2330 alu.op = ALU_OP1_COS;
2331 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2332
2333 alu.src[0].sel = ctx->temp_reg;
2334 alu.src[0].chan = 0;
2335 alu.last = 1;
2336 r = r600_bytecode_add_alu(ctx->bc, &alu);
2337 if (r)
2338 return r;
2339 }
2340 }
2341
2342 /* dst.y = SIN */
2343 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2344 if (ctx->bc->chip_class == CAYMAN) {
2345 for (i = 0 ; i < 3; i++) {
2346 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2347 alu.op = ALU_OP1_SIN;
2348 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2349 if (i == 1)
2350 alu.dst.write = 1;
2351 else
2352 alu.dst.write = 0;
2353 alu.src[0].sel = ctx->temp_reg;
2354 alu.src[0].chan = 0;
2355 if (i == 2)
2356 alu.last = 1;
2357 r = r600_bytecode_add_alu(ctx->bc, &alu);
2358 if (r)
2359 return r;
2360 }
2361 } else {
2362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2363 alu.op = ALU_OP1_SIN;
2364 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2365
2366 alu.src[0].sel = ctx->temp_reg;
2367 alu.src[0].chan = 0;
2368 alu.last = 1;
2369 r = r600_bytecode_add_alu(ctx->bc, &alu);
2370 if (r)
2371 return r;
2372 }
2373 }
2374
2375 /* dst.z = 0.0; */
2376 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2378
2379 alu.op = ALU_OP1_MOV;
2380
2381 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2382
2383 alu.src[0].sel = V_SQ_ALU_SRC_0;
2384 alu.src[0].chan = 0;
2385
2386 alu.last = 1;
2387
2388 r = r600_bytecode_add_alu(ctx->bc, &alu);
2389 if (r)
2390 return r;
2391 }
2392
2393 /* dst.w = 1.0; */
2394 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2396
2397 alu.op = ALU_OP1_MOV;
2398
2399 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2400
2401 alu.src[0].sel = V_SQ_ALU_SRC_1;
2402 alu.src[0].chan = 0;
2403
2404 alu.last = 1;
2405
2406 r = r600_bytecode_add_alu(ctx->bc, &alu);
2407 if (r)
2408 return r;
2409 }
2410
2411 return 0;
2412 }
2413
2414 static int tgsi_kill(struct r600_shader_ctx *ctx)
2415 {
2416 struct r600_bytecode_alu alu;
2417 int i, r;
2418
2419 for (i = 0; i < 4; i++) {
2420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2421 alu.op = ctx->inst_info->op;
2422
2423 alu.dst.chan = i;
2424
2425 alu.src[0].sel = V_SQ_ALU_SRC_0;
2426
2427 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
2428 alu.src[1].sel = V_SQ_ALU_SRC_1;
2429 alu.src[1].neg = 1;
2430 } else {
2431 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2432 }
2433 if (i == 3) {
2434 alu.last = 1;
2435 }
2436 r = r600_bytecode_add_alu(ctx->bc, &alu);
2437 if (r)
2438 return r;
2439 }
2440
2441 /* kill must be last in ALU */
2442 ctx->bc->force_add_cf = 1;
2443 ctx->shader->uses_kill = TRUE;
2444 return 0;
2445 }
2446
2447 static int tgsi_lit(struct r600_shader_ctx *ctx)
2448 {
2449 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2450 struct r600_bytecode_alu alu;
2451 int r;
2452
2453 /* tmp.x = max(src.y, 0.0) */
2454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2455 alu.op = ALU_OP2_MAX;
2456 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2457 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2458 alu.src[1].chan = 1;
2459
2460 alu.dst.sel = ctx->temp_reg;
2461 alu.dst.chan = 0;
2462 alu.dst.write = 1;
2463
2464 alu.last = 1;
2465 r = r600_bytecode_add_alu(ctx->bc, &alu);
2466 if (r)
2467 return r;
2468
2469 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2470 {
2471 int chan;
2472 int sel;
2473 int i;
2474
2475 if (ctx->bc->chip_class == CAYMAN) {
2476 for (i = 0; i < 3; i++) {
2477 /* tmp.z = log(tmp.x) */
2478 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2479 alu.op = ALU_OP1_LOG_CLAMPED;
2480 alu.src[0].sel = ctx->temp_reg;
2481 alu.src[0].chan = 0;
2482 alu.dst.sel = ctx->temp_reg;
2483 alu.dst.chan = i;
2484 if (i == 2) {
2485 alu.dst.write = 1;
2486 alu.last = 1;
2487 } else
2488 alu.dst.write = 0;
2489
2490 r = r600_bytecode_add_alu(ctx->bc, &alu);
2491 if (r)
2492 return r;
2493 }
2494 } else {
2495 /* tmp.z = log(tmp.x) */
2496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2497 alu.op = ALU_OP1_LOG_CLAMPED;
2498 alu.src[0].sel = ctx->temp_reg;
2499 alu.src[0].chan = 0;
2500 alu.dst.sel = ctx->temp_reg;
2501 alu.dst.chan = 2;
2502 alu.dst.write = 1;
2503 alu.last = 1;
2504 r = r600_bytecode_add_alu(ctx->bc, &alu);
2505 if (r)
2506 return r;
2507 }
2508
2509 chan = alu.dst.chan;
2510 sel = alu.dst.sel;
2511
2512 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2513 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2514 alu.op = ALU_OP3_MUL_LIT;
2515 alu.src[0].sel = sel;
2516 alu.src[0].chan = chan;
2517 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2518 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2519 alu.dst.sel = ctx->temp_reg;
2520 alu.dst.chan = 0;
2521 alu.dst.write = 1;
2522 alu.is_op3 = 1;
2523 alu.last = 1;
2524 r = r600_bytecode_add_alu(ctx->bc, &alu);
2525 if (r)
2526 return r;
2527
2528 if (ctx->bc->chip_class == CAYMAN) {
2529 for (i = 0; i < 3; i++) {
2530 /* dst.z = exp(tmp.x) */
2531 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2532 alu.op = ALU_OP1_EXP_IEEE;
2533 alu.src[0].sel = ctx->temp_reg;
2534 alu.src[0].chan = 0;
2535 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2536 if (i == 2) {
2537 alu.dst.write = 1;
2538 alu.last = 1;
2539 } else
2540 alu.dst.write = 0;
2541 r = r600_bytecode_add_alu(ctx->bc, &alu);
2542 if (r)
2543 return r;
2544 }
2545 } else {
2546 /* dst.z = exp(tmp.x) */
2547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2548 alu.op = ALU_OP1_EXP_IEEE;
2549 alu.src[0].sel = ctx->temp_reg;
2550 alu.src[0].chan = 0;
2551 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2552 alu.last = 1;
2553 r = r600_bytecode_add_alu(ctx->bc, &alu);
2554 if (r)
2555 return r;
2556 }
2557 }
2558
2559 /* dst.x, <- 1.0 */
2560 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2561 alu.op = ALU_OP1_MOV;
2562 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2563 alu.src[0].chan = 0;
2564 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2565 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2566 r = r600_bytecode_add_alu(ctx->bc, &alu);
2567 if (r)
2568 return r;
2569
2570 /* dst.y = max(src.x, 0.0) */
2571 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2572 alu.op = ALU_OP2_MAX;
2573 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2574 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2575 alu.src[1].chan = 0;
2576 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2577 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2578 r = r600_bytecode_add_alu(ctx->bc, &alu);
2579 if (r)
2580 return r;
2581
2582 /* dst.w, <- 1.0 */
2583 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2584 alu.op = ALU_OP1_MOV;
2585 alu.src[0].sel = V_SQ_ALU_SRC_1;
2586 alu.src[0].chan = 0;
2587 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2588 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2589 alu.last = 1;
2590 r = r600_bytecode_add_alu(ctx->bc, &alu);
2591 if (r)
2592 return r;
2593
2594 return 0;
2595 }
2596
2597 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2598 {
2599 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2600 struct r600_bytecode_alu alu;
2601 int i, r;
2602
2603 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2604
2605 /* XXX:
2606 * For state trackers other than OpenGL, we'll want to use
2607 * _RECIPSQRT_IEEE instead.
2608 */
2609 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2610
2611 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2612 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2613 r600_bytecode_src_set_abs(&alu.src[i]);
2614 }
2615 alu.dst.sel = ctx->temp_reg;
2616 alu.dst.write = 1;
2617 alu.last = 1;
2618 r = r600_bytecode_add_alu(ctx->bc, &alu);
2619 if (r)
2620 return r;
2621 /* replicate result */
2622 return tgsi_helper_tempx_replicate(ctx);
2623 }
2624
2625 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2626 {
2627 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2628 struct r600_bytecode_alu alu;
2629 int i, r;
2630
2631 for (i = 0; i < 4; i++) {
2632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2633 alu.src[0].sel = ctx->temp_reg;
2634 alu.op = ALU_OP1_MOV;
2635 alu.dst.chan = i;
2636 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2637 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2638 if (i == 3)
2639 alu.last = 1;
2640 r = r600_bytecode_add_alu(ctx->bc, &alu);
2641 if (r)
2642 return r;
2643 }
2644 return 0;
2645 }
2646
2647 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2648 {
2649 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2650 struct r600_bytecode_alu alu;
2651 int i, r;
2652
2653 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2654 alu.op = ctx->inst_info->op;
2655 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2656 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2657 }
2658 alu.dst.sel = ctx->temp_reg;
2659 alu.dst.write = 1;
2660 alu.last = 1;
2661 r = r600_bytecode_add_alu(ctx->bc, &alu);
2662 if (r)
2663 return r;
2664 /* replicate result */
2665 return tgsi_helper_tempx_replicate(ctx);
2666 }
2667
2668 static int cayman_pow(struct r600_shader_ctx *ctx)
2669 {
2670 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2671 int i, r;
2672 struct r600_bytecode_alu alu;
2673 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2674
2675 for (i = 0; i < 3; i++) {
2676 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2677 alu.op = ALU_OP1_LOG_IEEE;
2678 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2679 alu.dst.sel = ctx->temp_reg;
2680 alu.dst.chan = i;
2681 alu.dst.write = 1;
2682 if (i == 2)
2683 alu.last = 1;
2684 r = r600_bytecode_add_alu(ctx->bc, &alu);
2685 if (r)
2686 return r;
2687 }
2688
2689 /* b * LOG2(a) */
2690 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2691 alu.op = ALU_OP2_MUL;
2692 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2693 alu.src[1].sel = ctx->temp_reg;
2694 alu.dst.sel = ctx->temp_reg;
2695 alu.dst.write = 1;
2696 alu.last = 1;
2697 r = r600_bytecode_add_alu(ctx->bc, &alu);
2698 if (r)
2699 return r;
2700
2701 for (i = 0; i < last_slot; i++) {
2702 /* POW(a,b) = EXP2(b * LOG2(a))*/
2703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2704 alu.op = ALU_OP1_EXP_IEEE;
2705 alu.src[0].sel = ctx->temp_reg;
2706
2707 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2708 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2709 if (i == last_slot - 1)
2710 alu.last = 1;
2711 r = r600_bytecode_add_alu(ctx->bc, &alu);
2712 if (r)
2713 return r;
2714 }
2715 return 0;
2716 }
2717
2718 static int tgsi_pow(struct r600_shader_ctx *ctx)
2719 {
2720 struct r600_bytecode_alu alu;
2721 int r;
2722
2723 /* LOG2(a) */
2724 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2725 alu.op = ALU_OP1_LOG_IEEE;
2726 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2727 alu.dst.sel = ctx->temp_reg;
2728 alu.dst.write = 1;
2729 alu.last = 1;
2730 r = r600_bytecode_add_alu(ctx->bc, &alu);
2731 if (r)
2732 return r;
2733 /* b * LOG2(a) */
2734 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2735 alu.op = ALU_OP2_MUL;
2736 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2737 alu.src[1].sel = ctx->temp_reg;
2738 alu.dst.sel = ctx->temp_reg;
2739 alu.dst.write = 1;
2740 alu.last = 1;
2741 r = r600_bytecode_add_alu(ctx->bc, &alu);
2742 if (r)
2743 return r;
2744 /* POW(a,b) = EXP2(b * LOG2(a))*/
2745 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2746 alu.op = ALU_OP1_EXP_IEEE;
2747 alu.src[0].sel = ctx->temp_reg;
2748 alu.dst.sel = ctx->temp_reg;
2749 alu.dst.write = 1;
2750 alu.last = 1;
2751 r = r600_bytecode_add_alu(ctx->bc, &alu);
2752 if (r)
2753 return r;
2754 return tgsi_helper_tempx_replicate(ctx);
2755 }
2756
2757 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2758 {
2759 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2760 struct r600_bytecode_alu alu;
2761 int i, r, j;
2762 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2763 int tmp0 = ctx->temp_reg;
2764 int tmp1 = r600_get_temp(ctx);
2765 int tmp2 = r600_get_temp(ctx);
2766 int tmp3 = r600_get_temp(ctx);
2767 /* Unsigned path:
2768 *
2769 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2770 *
2771 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2772 * 2. tmp0.z = lo (tmp0.x * src2)
2773 * 3. tmp0.w = -tmp0.z
2774 * 4. tmp0.y = hi (tmp0.x * src2)
2775 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2776 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2777 * 7. tmp1.x = tmp0.x - tmp0.w
2778 * 8. tmp1.y = tmp0.x + tmp0.w
2779 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2780 * 10. tmp0.z = hi(tmp0.x * src1) = q
2781 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2782 *
2783 * 12. tmp0.w = src1 - tmp0.y = r
2784 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2785 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2786 *
2787 * if DIV
2788 *
2789 * 15. tmp1.z = tmp0.z + 1 = q + 1
2790 * 16. tmp1.w = tmp0.z - 1 = q - 1
2791 *
2792 * else MOD
2793 *
2794 * 15. tmp1.z = tmp0.w - src2 = r - src2
2795 * 16. tmp1.w = tmp0.w + src2 = r + src2
2796 *
2797 * endif
2798 *
2799 * 17. tmp1.x = tmp1.x & tmp1.y
2800 *
2801 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2802 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2803 *
2804 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2805 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2806 *
2807 * Signed path:
2808 *
2809 * Same as unsigned, using abs values of the operands,
2810 * and fixing the sign of the result in the end.
2811 */
2812
2813 for (i = 0; i < 4; i++) {
2814 if (!(write_mask & (1<<i)))
2815 continue;
2816
2817 if (signed_op) {
2818
2819 /* tmp2.x = -src0 */
2820 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2821 alu.op = ALU_OP2_SUB_INT;
2822
2823 alu.dst.sel = tmp2;
2824 alu.dst.chan = 0;
2825 alu.dst.write = 1;
2826
2827 alu.src[0].sel = V_SQ_ALU_SRC_0;
2828
2829 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2830
2831 alu.last = 1;
2832 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2833 return r;
2834
2835 /* tmp2.y = -src1 */
2836 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2837 alu.op = ALU_OP2_SUB_INT;
2838
2839 alu.dst.sel = tmp2;
2840 alu.dst.chan = 1;
2841 alu.dst.write = 1;
2842
2843 alu.src[0].sel = V_SQ_ALU_SRC_0;
2844
2845 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2846
2847 alu.last = 1;
2848 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2849 return r;
2850
2851 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2852 /* it will be a sign of the quotient */
2853 if (!mod) {
2854
2855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2856 alu.op = ALU_OP2_XOR_INT;
2857
2858 alu.dst.sel = tmp2;
2859 alu.dst.chan = 2;
2860 alu.dst.write = 1;
2861
2862 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2863 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2864
2865 alu.last = 1;
2866 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2867 return r;
2868 }
2869
2870 /* tmp2.x = |src0| */
2871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2872 alu.op = ALU_OP3_CNDGE_INT;
2873 alu.is_op3 = 1;
2874
2875 alu.dst.sel = tmp2;
2876 alu.dst.chan = 0;
2877 alu.dst.write = 1;
2878
2879 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2880 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2881 alu.src[2].sel = tmp2;
2882 alu.src[2].chan = 0;
2883
2884 alu.last = 1;
2885 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2886 return r;
2887
2888 /* tmp2.y = |src1| */
2889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2890 alu.op = ALU_OP3_CNDGE_INT;
2891 alu.is_op3 = 1;
2892
2893 alu.dst.sel = tmp2;
2894 alu.dst.chan = 1;
2895 alu.dst.write = 1;
2896
2897 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2898 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2899 alu.src[2].sel = tmp2;
2900 alu.src[2].chan = 1;
2901
2902 alu.last = 1;
2903 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2904 return r;
2905
2906 }
2907
2908 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2909 if (ctx->bc->chip_class == CAYMAN) {
2910 /* tmp3.x = u2f(src2) */
2911 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2912 alu.op = ALU_OP1_UINT_TO_FLT;
2913
2914 alu.dst.sel = tmp3;
2915 alu.dst.chan = 0;
2916 alu.dst.write = 1;
2917
2918 if (signed_op) {
2919 alu.src[0].sel = tmp2;
2920 alu.src[0].chan = 1;
2921 } else {
2922 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2923 }
2924
2925 alu.last = 1;
2926 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2927 return r;
2928
2929 /* tmp0.x = recip(tmp3.x) */
2930 for (j = 0 ; j < 3; j++) {
2931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2932 alu.op = ALU_OP1_RECIP_IEEE;
2933
2934 alu.dst.sel = tmp0;
2935 alu.dst.chan = j;
2936 alu.dst.write = (j == 0);
2937
2938 alu.src[0].sel = tmp3;
2939 alu.src[0].chan = 0;
2940
2941 if (j == 2)
2942 alu.last = 1;
2943 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2944 return r;
2945 }
2946
2947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2948 alu.op = ALU_OP2_MUL;
2949
2950 alu.src[0].sel = tmp0;
2951 alu.src[0].chan = 0;
2952
2953 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2954 alu.src[1].value = 0x4f800000;
2955
2956 alu.dst.sel = tmp3;
2957 alu.dst.write = 1;
2958 alu.last = 1;
2959 r = r600_bytecode_add_alu(ctx->bc, &alu);
2960 if (r)
2961 return r;
2962
2963 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2964 alu.op = ALU_OP1_FLT_TO_UINT;
2965
2966 alu.dst.sel = tmp0;
2967 alu.dst.chan = 0;
2968 alu.dst.write = 1;
2969
2970 alu.src[0].sel = tmp3;
2971 alu.src[0].chan = 0;
2972
2973 alu.last = 1;
2974 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2975 return r;
2976
2977 } else {
2978 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2979 alu.op = ALU_OP1_RECIP_UINT;
2980
2981 alu.dst.sel = tmp0;
2982 alu.dst.chan = 0;
2983 alu.dst.write = 1;
2984
2985 if (signed_op) {
2986 alu.src[0].sel = tmp2;
2987 alu.src[0].chan = 1;
2988 } else {
2989 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2990 }
2991
2992 alu.last = 1;
2993 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2994 return r;
2995 }
2996
2997 /* 2. tmp0.z = lo (tmp0.x * src2) */
2998 if (ctx->bc->chip_class == CAYMAN) {
2999 for (j = 0 ; j < 4; j++) {
3000 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3001 alu.op = ALU_OP2_MULLO_UINT;
3002
3003 alu.dst.sel = tmp0;
3004 alu.dst.chan = j;
3005 alu.dst.write = (j == 2);
3006
3007 alu.src[0].sel = tmp0;
3008 alu.src[0].chan = 0;
3009 if (signed_op) {
3010 alu.src[1].sel = tmp2;
3011 alu.src[1].chan = 1;
3012 } else {
3013 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3014 }
3015
3016 alu.last = (j == 3);
3017 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3018 return r;
3019 }
3020 } else {
3021 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3022 alu.op = ALU_OP2_MULLO_UINT;
3023
3024 alu.dst.sel = tmp0;
3025 alu.dst.chan = 2;
3026 alu.dst.write = 1;
3027
3028 alu.src[0].sel = tmp0;
3029 alu.src[0].chan = 0;
3030 if (signed_op) {
3031 alu.src[1].sel = tmp2;
3032 alu.src[1].chan = 1;
3033 } else {
3034 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3035 }
3036
3037 alu.last = 1;
3038 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3039 return r;
3040 }
3041
3042 /* 3. tmp0.w = -tmp0.z */
3043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3044 alu.op = ALU_OP2_SUB_INT;
3045
3046 alu.dst.sel = tmp0;
3047 alu.dst.chan = 3;
3048 alu.dst.write = 1;
3049
3050 alu.src[0].sel = V_SQ_ALU_SRC_0;
3051 alu.src[1].sel = tmp0;
3052 alu.src[1].chan = 2;
3053
3054 alu.last = 1;
3055 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3056 return r;
3057
3058 /* 4. tmp0.y = hi (tmp0.x * src2) */
3059 if (ctx->bc->chip_class == CAYMAN) {
3060 for (j = 0 ; j < 4; j++) {
3061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3062 alu.op = ALU_OP2_MULHI_UINT;
3063
3064 alu.dst.sel = tmp0;
3065 alu.dst.chan = j;
3066 alu.dst.write = (j == 1);
3067
3068 alu.src[0].sel = tmp0;
3069 alu.src[0].chan = 0;
3070
3071 if (signed_op) {
3072 alu.src[1].sel = tmp2;
3073 alu.src[1].chan = 1;
3074 } else {
3075 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3076 }
3077 alu.last = (j == 3);
3078 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3079 return r;
3080 }
3081 } else {
3082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3083 alu.op = ALU_OP2_MULHI_UINT;
3084
3085 alu.dst.sel = tmp0;
3086 alu.dst.chan = 1;
3087 alu.dst.write = 1;
3088
3089 alu.src[0].sel = tmp0;
3090 alu.src[0].chan = 0;
3091
3092 if (signed_op) {
3093 alu.src[1].sel = tmp2;
3094 alu.src[1].chan = 1;
3095 } else {
3096 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3097 }
3098
3099 alu.last = 1;
3100 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3101 return r;
3102 }
3103
3104 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
3105 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3106 alu.op = ALU_OP3_CNDE_INT;
3107 alu.is_op3 = 1;
3108
3109 alu.dst.sel = tmp0;
3110 alu.dst.chan = 2;
3111 alu.dst.write = 1;
3112
3113 alu.src[0].sel = tmp0;
3114 alu.src[0].chan = 1;
3115 alu.src[1].sel = tmp0;
3116 alu.src[1].chan = 3;
3117 alu.src[2].sel = tmp0;
3118 alu.src[2].chan = 2;
3119
3120 alu.last = 1;
3121 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3122 return r;
3123
3124 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
3125 if (ctx->bc->chip_class == CAYMAN) {
3126 for (j = 0 ; j < 4; j++) {
3127 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3128 alu.op = ALU_OP2_MULHI_UINT;
3129
3130 alu.dst.sel = tmp0;
3131 alu.dst.chan = j;
3132 alu.dst.write = (j == 3);
3133
3134 alu.src[0].sel = tmp0;
3135 alu.src[0].chan = 2;
3136
3137 alu.src[1].sel = tmp0;
3138 alu.src[1].chan = 0;
3139
3140 alu.last = (j == 3);
3141 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3142 return r;
3143 }
3144 } else {
3145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3146 alu.op = ALU_OP2_MULHI_UINT;
3147
3148 alu.dst.sel = tmp0;
3149 alu.dst.chan = 3;
3150 alu.dst.write = 1;
3151
3152 alu.src[0].sel = tmp0;
3153 alu.src[0].chan = 2;
3154
3155 alu.src[1].sel = tmp0;
3156 alu.src[1].chan = 0;
3157
3158 alu.last = 1;
3159 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3160 return r;
3161 }
3162
3163 /* 7. tmp1.x = tmp0.x - tmp0.w */
3164 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3165 alu.op = ALU_OP2_SUB_INT;
3166
3167 alu.dst.sel = tmp1;
3168 alu.dst.chan = 0;
3169 alu.dst.write = 1;
3170
3171 alu.src[0].sel = tmp0;
3172 alu.src[0].chan = 0;
3173 alu.src[1].sel = tmp0;
3174 alu.src[1].chan = 3;
3175
3176 alu.last = 1;
3177 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3178 return r;
3179
3180 /* 8. tmp1.y = tmp0.x + tmp0.w */
3181 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3182 alu.op = ALU_OP2_ADD_INT;
3183
3184 alu.dst.sel = tmp1;
3185 alu.dst.chan = 1;
3186 alu.dst.write = 1;
3187
3188 alu.src[0].sel = tmp0;
3189 alu.src[0].chan = 0;
3190 alu.src[1].sel = tmp0;
3191 alu.src[1].chan = 3;
3192
3193 alu.last = 1;
3194 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3195 return r;
3196
3197 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3198 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3199 alu.op = ALU_OP3_CNDE_INT;
3200 alu.is_op3 = 1;
3201
3202 alu.dst.sel = tmp0;
3203 alu.dst.chan = 0;
3204 alu.dst.write = 1;
3205
3206 alu.src[0].sel = tmp0;
3207 alu.src[0].chan = 1;
3208 alu.src[1].sel = tmp1;
3209 alu.src[1].chan = 1;
3210 alu.src[2].sel = tmp1;
3211 alu.src[2].chan = 0;
3212
3213 alu.last = 1;
3214 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3215 return r;
3216
3217 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3218 if (ctx->bc->chip_class == CAYMAN) {
3219 for (j = 0 ; j < 4; j++) {
3220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3221 alu.op = ALU_OP2_MULHI_UINT;
3222
3223 alu.dst.sel = tmp0;
3224 alu.dst.chan = j;
3225 alu.dst.write = (j == 2);
3226
3227 alu.src[0].sel = tmp0;
3228 alu.src[0].chan = 0;
3229
3230 if (signed_op) {
3231 alu.src[1].sel = tmp2;
3232 alu.src[1].chan = 0;
3233 } else {
3234 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3235 }
3236
3237 alu.last = (j == 3);
3238 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3239 return r;
3240 }
3241 } else {
3242 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3243 alu.op = ALU_OP2_MULHI_UINT;
3244
3245 alu.dst.sel = tmp0;
3246 alu.dst.chan = 2;
3247 alu.dst.write = 1;
3248
3249 alu.src[0].sel = tmp0;
3250 alu.src[0].chan = 0;
3251
3252 if (signed_op) {
3253 alu.src[1].sel = tmp2;
3254 alu.src[1].chan = 0;
3255 } else {
3256 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3257 }
3258
3259 alu.last = 1;
3260 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3261 return r;
3262 }
3263
3264 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3265 if (ctx->bc->chip_class == CAYMAN) {
3266 for (j = 0 ; j < 4; j++) {
3267 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3268 alu.op = ALU_OP2_MULLO_UINT;
3269
3270 alu.dst.sel = tmp0;
3271 alu.dst.chan = j;
3272 alu.dst.write = (j == 1);
3273
3274 if (signed_op) {
3275 alu.src[0].sel = tmp2;
3276 alu.src[0].chan = 1;
3277 } else {
3278 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3279 }
3280
3281 alu.src[1].sel = tmp0;
3282 alu.src[1].chan = 2;
3283
3284 alu.last = (j == 3);
3285 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3286 return r;
3287 }
3288 } else {
3289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3290 alu.op = ALU_OP2_MULLO_UINT;
3291
3292 alu.dst.sel = tmp0;
3293 alu.dst.chan = 1;
3294 alu.dst.write = 1;
3295
3296 if (signed_op) {
3297 alu.src[0].sel = tmp2;
3298 alu.src[0].chan = 1;
3299 } else {
3300 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3301 }
3302
3303 alu.src[1].sel = tmp0;
3304 alu.src[1].chan = 2;
3305
3306 alu.last = 1;
3307 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3308 return r;
3309 }
3310
3311 /* 12. tmp0.w = src1 - tmp0.y = r */
3312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3313 alu.op = ALU_OP2_SUB_INT;
3314
3315 alu.dst.sel = tmp0;
3316 alu.dst.chan = 3;
3317 alu.dst.write = 1;
3318
3319 if (signed_op) {
3320 alu.src[0].sel = tmp2;
3321 alu.src[0].chan = 0;
3322 } else {
3323 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3324 }
3325
3326 alu.src[1].sel = tmp0;
3327 alu.src[1].chan = 1;
3328
3329 alu.last = 1;
3330 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3331 return r;
3332
3333 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3335 alu.op = ALU_OP2_SETGE_UINT;
3336
3337 alu.dst.sel = tmp1;
3338 alu.dst.chan = 0;
3339 alu.dst.write = 1;
3340
3341 alu.src[0].sel = tmp0;
3342 alu.src[0].chan = 3;
3343 if (signed_op) {
3344 alu.src[1].sel = tmp2;
3345 alu.src[1].chan = 1;
3346 } else {
3347 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3348 }
3349
3350 alu.last = 1;
3351 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3352 return r;
3353
3354 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3355 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3356 alu.op = ALU_OP2_SETGE_UINT;
3357
3358 alu.dst.sel = tmp1;
3359 alu.dst.chan = 1;
3360 alu.dst.write = 1;
3361
3362 if (signed_op) {
3363 alu.src[0].sel = tmp2;
3364 alu.src[0].chan = 0;
3365 } else {
3366 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3367 }
3368
3369 alu.src[1].sel = tmp0;
3370 alu.src[1].chan = 1;
3371
3372 alu.last = 1;
3373 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3374 return r;
3375
3376 if (mod) { /* UMOD */
3377
3378 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3379 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3380 alu.op = ALU_OP2_SUB_INT;
3381
3382 alu.dst.sel = tmp1;
3383 alu.dst.chan = 2;
3384 alu.dst.write = 1;
3385
3386 alu.src[0].sel = tmp0;
3387 alu.src[0].chan = 3;
3388
3389 if (signed_op) {
3390 alu.src[1].sel = tmp2;
3391 alu.src[1].chan = 1;
3392 } else {
3393 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3394 }
3395
3396 alu.last = 1;
3397 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3398 return r;
3399
3400 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3402 alu.op = ALU_OP2_ADD_INT;
3403
3404 alu.dst.sel = tmp1;
3405 alu.dst.chan = 3;
3406 alu.dst.write = 1;
3407
3408 alu.src[0].sel = tmp0;
3409 alu.src[0].chan = 3;
3410 if (signed_op) {
3411 alu.src[1].sel = tmp2;
3412 alu.src[1].chan = 1;
3413 } else {
3414 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3415 }
3416
3417 alu.last = 1;
3418 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3419 return r;
3420
3421 } else { /* UDIV */
3422
3423 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3425 alu.op = ALU_OP2_ADD_INT;
3426
3427 alu.dst.sel = tmp1;
3428 alu.dst.chan = 2;
3429 alu.dst.write = 1;
3430
3431 alu.src[0].sel = tmp0;
3432 alu.src[0].chan = 2;
3433 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3434
3435 alu.last = 1;
3436 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3437 return r;
3438
3439 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3441 alu.op = ALU_OP2_ADD_INT;
3442
3443 alu.dst.sel = tmp1;
3444 alu.dst.chan = 3;
3445 alu.dst.write = 1;
3446
3447 alu.src[0].sel = tmp0;
3448 alu.src[0].chan = 2;
3449 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3450
3451 alu.last = 1;
3452 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3453 return r;
3454
3455 }
3456
3457 /* 17. tmp1.x = tmp1.x & tmp1.y */
3458 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3459 alu.op = ALU_OP2_AND_INT;
3460
3461 alu.dst.sel = tmp1;
3462 alu.dst.chan = 0;
3463 alu.dst.write = 1;
3464
3465 alu.src[0].sel = tmp1;
3466 alu.src[0].chan = 0;
3467 alu.src[1].sel = tmp1;
3468 alu.src[1].chan = 1;
3469
3470 alu.last = 1;
3471 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3472 return r;
3473
3474 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3475 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3476 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3477 alu.op = ALU_OP3_CNDE_INT;
3478 alu.is_op3 = 1;
3479
3480 alu.dst.sel = tmp0;
3481 alu.dst.chan = 2;
3482 alu.dst.write = 1;
3483
3484 alu.src[0].sel = tmp1;
3485 alu.src[0].chan = 0;
3486 alu.src[1].sel = tmp0;
3487 alu.src[1].chan = mod ? 3 : 2;
3488 alu.src[2].sel = tmp1;
3489 alu.src[2].chan = 2;
3490
3491 alu.last = 1;
3492 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3493 return r;
3494
3495 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3497 alu.op = ALU_OP3_CNDE_INT;
3498 alu.is_op3 = 1;
3499
3500 if (signed_op) {
3501 alu.dst.sel = tmp0;
3502 alu.dst.chan = 2;
3503 alu.dst.write = 1;
3504 } else {
3505 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3506 }
3507
3508 alu.src[0].sel = tmp1;
3509 alu.src[0].chan = 1;
3510 alu.src[1].sel = tmp1;
3511 alu.src[1].chan = 3;
3512 alu.src[2].sel = tmp0;
3513 alu.src[2].chan = 2;
3514
3515 alu.last = 1;
3516 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3517 return r;
3518
3519 if (signed_op) {
3520
3521 /* fix the sign of the result */
3522
3523 if (mod) {
3524
3525 /* tmp0.x = -tmp0.z */
3526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3527 alu.op = ALU_OP2_SUB_INT;
3528
3529 alu.dst.sel = tmp0;
3530 alu.dst.chan = 0;
3531 alu.dst.write = 1;
3532
3533 alu.src[0].sel = V_SQ_ALU_SRC_0;
3534 alu.src[1].sel = tmp0;
3535 alu.src[1].chan = 2;
3536
3537 alu.last = 1;
3538 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3539 return r;
3540
3541 /* sign of the remainder is the same as the sign of src0 */
3542 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3543 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3544 alu.op = ALU_OP3_CNDGE_INT;
3545 alu.is_op3 = 1;
3546
3547 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3548
3549 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3550 alu.src[1].sel = tmp0;
3551 alu.src[1].chan = 2;
3552 alu.src[2].sel = tmp0;
3553 alu.src[2].chan = 0;
3554
3555 alu.last = 1;
3556 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3557 return r;
3558
3559 } else {
3560
3561 /* tmp0.x = -tmp0.z */
3562 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3563 alu.op = ALU_OP2_SUB_INT;
3564
3565 alu.dst.sel = tmp0;
3566 alu.dst.chan = 0;
3567 alu.dst.write = 1;
3568
3569 alu.src[0].sel = V_SQ_ALU_SRC_0;
3570 alu.src[1].sel = tmp0;
3571 alu.src[1].chan = 2;
3572
3573 alu.last = 1;
3574 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3575 return r;
3576
3577 /* fix the quotient sign (same as the sign of src0*src1) */
3578 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3579 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3580 alu.op = ALU_OP3_CNDGE_INT;
3581 alu.is_op3 = 1;
3582
3583 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3584
3585 alu.src[0].sel = tmp2;
3586 alu.src[0].chan = 2;
3587 alu.src[1].sel = tmp0;
3588 alu.src[1].chan = 2;
3589 alu.src[2].sel = tmp0;
3590 alu.src[2].chan = 0;
3591
3592 alu.last = 1;
3593 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3594 return r;
3595 }
3596 }
3597 }
3598 return 0;
3599 }
3600
3601 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3602 {
3603 return tgsi_divmod(ctx, 0, 0);
3604 }
3605
3606 static int tgsi_umod(struct r600_shader_ctx *ctx)
3607 {
3608 return tgsi_divmod(ctx, 1, 0);
3609 }
3610
3611 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3612 {
3613 return tgsi_divmod(ctx, 0, 1);
3614 }
3615
3616 static int tgsi_imod(struct r600_shader_ctx *ctx)
3617 {
3618 return tgsi_divmod(ctx, 1, 1);
3619 }
3620
3621
3622 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3623 {
3624 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3625 struct r600_bytecode_alu alu;
3626 int i, r;
3627 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3628 int last_inst = tgsi_last_instruction(write_mask);
3629
3630 for (i = 0; i < 4; i++) {
3631 if (!(write_mask & (1<<i)))
3632 continue;
3633
3634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3635 alu.op = ALU_OP1_TRUNC;
3636
3637 alu.dst.sel = ctx->temp_reg;
3638 alu.dst.chan = i;
3639 alu.dst.write = 1;
3640
3641 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3642 if (i == last_inst)
3643 alu.last = 1;
3644 r = r600_bytecode_add_alu(ctx->bc, &alu);
3645 if (r)
3646 return r;
3647 }
3648
3649 for (i = 0; i < 4; i++) {
3650 if (!(write_mask & (1<<i)))
3651 continue;
3652
3653 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3654 alu.op = ctx->inst_info->op;
3655
3656 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3657
3658 alu.src[0].sel = ctx->temp_reg;
3659 alu.src[0].chan = i;
3660
3661 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3662 alu.last = 1;
3663 r = r600_bytecode_add_alu(ctx->bc, &alu);
3664 if (r)
3665 return r;
3666 }
3667
3668 return 0;
3669 }
3670
3671 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3672 {
3673 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3674 struct r600_bytecode_alu alu;
3675 int i, r;
3676 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3677 int last_inst = tgsi_last_instruction(write_mask);
3678
3679 /* tmp = -src */
3680 for (i = 0; i < 4; i++) {
3681 if (!(write_mask & (1<<i)))
3682 continue;
3683
3684 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3685 alu.op = ALU_OP2_SUB_INT;
3686
3687 alu.dst.sel = ctx->temp_reg;
3688 alu.dst.chan = i;
3689 alu.dst.write = 1;
3690
3691 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3692 alu.src[0].sel = V_SQ_ALU_SRC_0;
3693
3694 if (i == last_inst)
3695 alu.last = 1;
3696 r = r600_bytecode_add_alu(ctx->bc, &alu);
3697 if (r)
3698 return r;
3699 }
3700
3701 /* dst = (src >= 0 ? src : tmp) */
3702 for (i = 0; i < 4; i++) {
3703 if (!(write_mask & (1<<i)))
3704 continue;
3705
3706 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3707 alu.op = ALU_OP3_CNDGE_INT;
3708 alu.is_op3 = 1;
3709 alu.dst.write = 1;
3710
3711 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3712
3713 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3714 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3715 alu.src[2].sel = ctx->temp_reg;
3716 alu.src[2].chan = i;
3717
3718 if (i == last_inst)
3719 alu.last = 1;
3720 r = r600_bytecode_add_alu(ctx->bc, &alu);
3721 if (r)
3722 return r;
3723 }
3724 return 0;
3725 }
3726
3727 static int tgsi_issg(struct r600_shader_ctx *ctx)
3728 {
3729 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3730 struct r600_bytecode_alu alu;
3731 int i, r;
3732 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3733 int last_inst = tgsi_last_instruction(write_mask);
3734
3735 /* tmp = (src >= 0 ? src : -1) */
3736 for (i = 0; i < 4; i++) {
3737 if (!(write_mask & (1<<i)))
3738 continue;
3739
3740 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3741 alu.op = ALU_OP3_CNDGE_INT;
3742 alu.is_op3 = 1;
3743
3744 alu.dst.sel = ctx->temp_reg;
3745 alu.dst.chan = i;
3746 alu.dst.write = 1;
3747
3748 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3749 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3750 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3751
3752 if (i == last_inst)
3753 alu.last = 1;
3754 r = r600_bytecode_add_alu(ctx->bc, &alu);
3755 if (r)
3756 return r;
3757 }
3758
3759 /* dst = (tmp > 0 ? 1 : tmp) */
3760 for (i = 0; i < 4; i++) {
3761 if (!(write_mask & (1<<i)))
3762 continue;
3763
3764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3765 alu.op = ALU_OP3_CNDGT_INT;
3766 alu.is_op3 = 1;
3767 alu.dst.write = 1;
3768
3769 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3770
3771 alu.src[0].sel = ctx->temp_reg;
3772 alu.src[0].chan = i;
3773
3774 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3775
3776 alu.src[2].sel = ctx->temp_reg;
3777 alu.src[2].chan = i;
3778
3779 if (i == last_inst)
3780 alu.last = 1;
3781 r = r600_bytecode_add_alu(ctx->bc, &alu);
3782 if (r)
3783 return r;
3784 }
3785 return 0;
3786 }
3787
3788
3789
3790 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3791 {
3792 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3793 struct r600_bytecode_alu alu;
3794 int i, r;
3795
3796 /* tmp = (src > 0 ? 1 : src) */
3797 for (i = 0; i < 4; i++) {
3798 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3799 alu.op = ALU_OP3_CNDGT;
3800 alu.is_op3 = 1;
3801
3802 alu.dst.sel = ctx->temp_reg;
3803 alu.dst.chan = i;
3804
3805 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3806 alu.src[1].sel = V_SQ_ALU_SRC_1;
3807 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3808
3809 if (i == 3)
3810 alu.last = 1;
3811 r = r600_bytecode_add_alu(ctx->bc, &alu);
3812 if (r)
3813 return r;
3814 }
3815
3816 /* dst = (-tmp > 0 ? -1 : tmp) */
3817 for (i = 0; i < 4; i++) {
3818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3819 alu.op = ALU_OP3_CNDGT;
3820 alu.is_op3 = 1;
3821 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3822
3823 alu.src[0].sel = ctx->temp_reg;
3824 alu.src[0].chan = i;
3825 alu.src[0].neg = 1;
3826
3827 alu.src[1].sel = V_SQ_ALU_SRC_1;
3828 alu.src[1].neg = 1;
3829
3830 alu.src[2].sel = ctx->temp_reg;
3831 alu.src[2].chan = i;
3832
3833 if (i == 3)
3834 alu.last = 1;
3835 r = r600_bytecode_add_alu(ctx->bc, &alu);
3836 if (r)
3837 return r;
3838 }
3839 return 0;
3840 }
3841
3842 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3843 {
3844 struct r600_bytecode_alu alu;
3845 int i, r;
3846
3847 for (i = 0; i < 4; i++) {
3848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3849 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3850 alu.op = ALU_OP0_NOP;
3851 alu.dst.chan = i;
3852 } else {
3853 alu.op = ALU_OP1_MOV;
3854 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3855 alu.src[0].sel = ctx->temp_reg;
3856 alu.src[0].chan = i;
3857 }
3858 if (i == 3) {
3859 alu.last = 1;
3860 }
3861 r = r600_bytecode_add_alu(ctx->bc, &alu);
3862 if (r)
3863 return r;
3864 }
3865 return 0;
3866 }
3867
3868 static int tgsi_op3(struct r600_shader_ctx *ctx)
3869 {
3870 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3871 struct r600_bytecode_alu alu;
3872 int i, j, r;
3873 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3874
3875 for (i = 0; i < lasti + 1; i++) {
3876 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3877 continue;
3878
3879 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3880 alu.op = ctx->inst_info->op;
3881 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3882 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3883 }
3884
3885 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3886 alu.dst.chan = i;
3887 alu.dst.write = 1;
3888 alu.is_op3 = 1;
3889 if (i == lasti) {
3890 alu.last = 1;
3891 }
3892 r = r600_bytecode_add_alu(ctx->bc, &alu);
3893 if (r)
3894 return r;
3895 }
3896 return 0;
3897 }
3898
3899 static int tgsi_dp(struct r600_shader_ctx *ctx)
3900 {
3901 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3902 struct r600_bytecode_alu alu;
3903 int i, j, r;
3904
3905 for (i = 0; i < 4; i++) {
3906 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3907 alu.op = ctx->inst_info->op;
3908 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3909 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3910 }
3911
3912 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3913 alu.dst.chan = i;
3914 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3915 /* handle some special cases */
3916 switch (ctx->inst_info->tgsi_opcode) {
3917 case TGSI_OPCODE_DP2:
3918 if (i > 1) {
3919 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3920 alu.src[0].chan = alu.src[1].chan = 0;
3921 }
3922 break;
3923 case TGSI_OPCODE_DP3:
3924 if (i > 2) {
3925 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3926 alu.src[0].chan = alu.src[1].chan = 0;
3927 }
3928 break;
3929 case TGSI_OPCODE_DPH:
3930 if (i == 3) {
3931 alu.src[0].sel = V_SQ_ALU_SRC_1;
3932 alu.src[0].chan = 0;
3933 alu.src[0].neg = 0;
3934 }
3935 break;
3936 default:
3937 break;
3938 }
3939 if (i == 3) {
3940 alu.last = 1;
3941 }
3942 r = r600_bytecode_add_alu(ctx->bc, &alu);
3943 if (r)
3944 return r;
3945 }
3946 return 0;
3947 }
3948
3949 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3950 unsigned index)
3951 {
3952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3953 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3954 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3955 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3956 ctx->src[index].neg || ctx->src[index].abs;
3957 }
3958
3959 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3960 unsigned index)
3961 {
3962 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3963 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3964 }
3965
3966 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
3967 {
3968 struct r600_bytecode_vtx vtx;
3969 struct r600_bytecode_alu alu;
3970 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3971 int src_gpr, r, i;
3972 int id = tgsi_tex_get_src_gpr(ctx, 1);
3973
3974 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3975 if (src_requires_loading) {
3976 for (i = 0; i < 4; i++) {
3977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3978 alu.op = ALU_OP1_MOV;
3979 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3980 alu.dst.sel = ctx->temp_reg;
3981 alu.dst.chan = i;
3982 if (i == 3)
3983 alu.last = 1;
3984 alu.dst.write = 1;
3985 r = r600_bytecode_add_alu(ctx->bc, &alu);
3986 if (r)
3987 return r;
3988 }
3989 src_gpr = ctx->temp_reg;
3990 }
3991
3992 memset(&vtx, 0, sizeof(vtx));
3993 vtx.op = FETCH_OP_VFETCH;
3994 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
3995 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
3996 vtx.src_gpr = src_gpr;
3997 vtx.mega_fetch_count = 16;
3998 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3999 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
4000 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
4001 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
4002 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
4003 vtx.use_const_fields = 1;
4004 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
4005
4006 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
4007 return r;
4008
4009 if (ctx->bc->chip_class >= EVERGREEN)
4010 return 0;
4011
4012 for (i = 0; i < 4; i++) {
4013 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4014 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4015 continue;
4016
4017 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4018 alu.op = ALU_OP2_AND_INT;
4019
4020 alu.dst.chan = i;
4021 alu.dst.sel = vtx.dst_gpr;
4022 alu.dst.write = 1;
4023
4024 alu.src[0].sel = vtx.dst_gpr;
4025 alu.src[0].chan = i;
4026
4027 alu.src[1].sel = 512 + (id * 2);
4028 alu.src[1].chan = i % 4;
4029 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4030
4031 if (i == lasti)
4032 alu.last = 1;
4033 r = r600_bytecode_add_alu(ctx->bc, &alu);
4034 if (r)
4035 return r;
4036 }
4037
4038 if (inst->Dst[0].Register.WriteMask & 3) {
4039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4040 alu.op = ALU_OP2_OR_INT;
4041
4042 alu.dst.chan = 3;
4043 alu.dst.sel = vtx.dst_gpr;
4044 alu.dst.write = 1;
4045
4046 alu.src[0].sel = vtx.dst_gpr;
4047 alu.src[0].chan = 3;
4048
4049 alu.src[1].sel = 512 + (id * 2) + 1;
4050 alu.src[1].chan = 0;
4051 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4052
4053 alu.last = 1;
4054 r = r600_bytecode_add_alu(ctx->bc, &alu);
4055 if (r)
4056 return r;
4057 }
4058 return 0;
4059 }
4060
4061 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
4062 {
4063 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4064 struct r600_bytecode_alu alu;
4065 int r;
4066 int id = tgsi_tex_get_src_gpr(ctx, 1);
4067
4068 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4069 alu.op = ALU_OP1_MOV;
4070
4071 if (ctx->bc->chip_class >= EVERGREEN) {
4072 alu.src[0].sel = 512 + (id / 4);
4073 alu.src[0].chan = id % 4;
4074 } else {
4075 /* r600 we have them at channel 2 of the second dword */
4076 alu.src[0].sel = 512 + (id * 2) + 1;
4077 alu.src[0].chan = 1;
4078 }
4079 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4080 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4081 alu.last = 1;
4082 r = r600_bytecode_add_alu(ctx->bc, &alu);
4083 if (r)
4084 return r;
4085 return 0;
4086 }
4087
4088 static int tgsi_tex(struct r600_shader_ctx *ctx)
4089 {
4090 static float one_point_five = 1.5f;
4091 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4092 struct r600_bytecode_tex tex;
4093 struct r600_bytecode_alu alu;
4094 unsigned src_gpr;
4095 int r, i, j;
4096 int opcode;
4097 bool read_compressed_msaa = ctx->bc->msaa_texture_mode == MSAA_TEXTURE_COMPRESSED &&
4098 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
4099 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
4100 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
4101 /* Texture fetch instructions can only use gprs as source.
4102 * Also they cannot negate the source or take the absolute value */
4103 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
4104 tgsi_tex_src_requires_loading(ctx, 0)) ||
4105 read_compressed_msaa;
4106 boolean src_loaded = FALSE;
4107 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
4108 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
4109 boolean has_txq_cube_array_z = false;
4110
4111 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
4112 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4113 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
4114 if (inst->Dst[0].Register.WriteMask & 4) {
4115 ctx->shader->has_txq_cube_array_z_comp = true;
4116 has_txq_cube_array_z = true;
4117 }
4118
4119 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
4120 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4121 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4122 sampler_src_reg = 2;
4123
4124 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4125
4126 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
4127 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
4128 ctx->shader->uses_tex_buffers = true;
4129 return r600_do_buffer_txq(ctx);
4130 }
4131 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4132 if (ctx->bc->chip_class < EVERGREEN)
4133 ctx->shader->uses_tex_buffers = true;
4134 return do_vtx_fetch_inst(ctx, src_requires_loading);
4135 }
4136 }
4137
4138 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4139 /* get offset values */
4140 if (inst->Texture.NumOffsets) {
4141 assert(inst->Texture.NumOffsets == 1);
4142
4143 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
4144 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
4145 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
4146 }
4147 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
4148 /* TGSI moves the sampler to src reg 3 for TXD */
4149 sampler_src_reg = 3;
4150
4151 for (i = 1; i < 3; i++) {
4152 /* set gradients h/v */
4153 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4154 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
4155 FETCH_OP_SET_GRADIENTS_V;
4156 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4157 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4158
4159 if (tgsi_tex_src_requires_loading(ctx, i)) {
4160 tex.src_gpr = r600_get_temp(ctx);
4161 tex.src_sel_x = 0;
4162 tex.src_sel_y = 1;
4163 tex.src_sel_z = 2;
4164 tex.src_sel_w = 3;
4165
4166 for (j = 0; j < 4; j++) {
4167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4168 alu.op = ALU_OP1_MOV;
4169 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
4170 alu.dst.sel = tex.src_gpr;
4171 alu.dst.chan = j;
4172 if (j == 3)
4173 alu.last = 1;
4174 alu.dst.write = 1;
4175 r = r600_bytecode_add_alu(ctx->bc, &alu);
4176 if (r)
4177 return r;
4178 }
4179
4180 } else {
4181 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
4182 tex.src_sel_x = ctx->src[i].swizzle[0];
4183 tex.src_sel_y = ctx->src[i].swizzle[1];
4184 tex.src_sel_z = ctx->src[i].swizzle[2];
4185 tex.src_sel_w = ctx->src[i].swizzle[3];
4186 tex.src_rel = ctx->src[i].rel;
4187 }
4188 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
4189 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4190 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
4191 tex.coord_type_x = 1;
4192 tex.coord_type_y = 1;
4193 tex.coord_type_z = 1;
4194 tex.coord_type_w = 1;
4195 }
4196 r = r600_bytecode_add_tex(ctx->bc, &tex);
4197 if (r)
4198 return r;
4199 }
4200 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
4201 int out_chan;
4202 /* Add perspective divide */
4203 if (ctx->bc->chip_class == CAYMAN) {
4204 out_chan = 2;
4205 for (i = 0; i < 3; i++) {
4206 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4207 alu.op = ALU_OP1_RECIP_IEEE;
4208 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4209
4210 alu.dst.sel = ctx->temp_reg;
4211 alu.dst.chan = i;
4212 if (i == 2)
4213 alu.last = 1;
4214 if (out_chan == i)
4215 alu.dst.write = 1;
4216 r = r600_bytecode_add_alu(ctx->bc, &alu);
4217 if (r)
4218 return r;
4219 }
4220
4221 } else {
4222 out_chan = 3;
4223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4224 alu.op = ALU_OP1_RECIP_IEEE;
4225 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4226
4227 alu.dst.sel = ctx->temp_reg;
4228 alu.dst.chan = out_chan;
4229 alu.last = 1;
4230 alu.dst.write = 1;
4231 r = r600_bytecode_add_alu(ctx->bc, &alu);
4232 if (r)
4233 return r;
4234 }
4235
4236 for (i = 0; i < 3; i++) {
4237 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4238 alu.op = ALU_OP2_MUL;
4239 alu.src[0].sel = ctx->temp_reg;
4240 alu.src[0].chan = out_chan;
4241 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4242 alu.dst.sel = ctx->temp_reg;
4243 alu.dst.chan = i;
4244 alu.dst.write = 1;
4245 r = r600_bytecode_add_alu(ctx->bc, &alu);
4246 if (r)
4247 return r;
4248 }
4249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4250 alu.op = ALU_OP1_MOV;
4251 alu.src[0].sel = V_SQ_ALU_SRC_1;
4252 alu.src[0].chan = 0;
4253 alu.dst.sel = ctx->temp_reg;
4254 alu.dst.chan = 3;
4255 alu.last = 1;
4256 alu.dst.write = 1;
4257 r = r600_bytecode_add_alu(ctx->bc, &alu);
4258 if (r)
4259 return r;
4260 src_loaded = TRUE;
4261 src_gpr = ctx->temp_reg;
4262 }
4263
4264 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4265 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4266 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4267 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4268 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
4269 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
4270
4271 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
4272 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
4273
4274 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
4275 for (i = 0; i < 4; i++) {
4276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4277 alu.op = ALU_OP2_CUBE;
4278 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4279 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
4280 alu.dst.sel = ctx->temp_reg;
4281 alu.dst.chan = i;
4282 if (i == 3)
4283 alu.last = 1;
4284 alu.dst.write = 1;
4285 r = r600_bytecode_add_alu(ctx->bc, &alu);
4286 if (r)
4287 return r;
4288 }
4289
4290 /* tmp1.z = RCP_e(|tmp1.z|) */
4291 if (ctx->bc->chip_class == CAYMAN) {
4292 for (i = 0; i < 3; i++) {
4293 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4294 alu.op = ALU_OP1_RECIP_IEEE;
4295 alu.src[0].sel = ctx->temp_reg;
4296 alu.src[0].chan = 2;
4297 alu.src[0].abs = 1;
4298 alu.dst.sel = ctx->temp_reg;
4299 alu.dst.chan = i;
4300 if (i == 2)
4301 alu.dst.write = 1;
4302 if (i == 2)
4303 alu.last = 1;
4304 r = r600_bytecode_add_alu(ctx->bc, &alu);
4305 if (r)
4306 return r;
4307 }
4308 } else {
4309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4310 alu.op = ALU_OP1_RECIP_IEEE;
4311 alu.src[0].sel = ctx->temp_reg;
4312 alu.src[0].chan = 2;
4313 alu.src[0].abs = 1;
4314 alu.dst.sel = ctx->temp_reg;
4315 alu.dst.chan = 2;
4316 alu.dst.write = 1;
4317 alu.last = 1;
4318 r = r600_bytecode_add_alu(ctx->bc, &alu);
4319 if (r)
4320 return r;
4321 }
4322
4323 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4324 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4325 * muladd has no writemask, have to use another temp
4326 */
4327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4328 alu.op = ALU_OP3_MULADD;
4329 alu.is_op3 = 1;
4330
4331 alu.src[0].sel = ctx->temp_reg;
4332 alu.src[0].chan = 0;
4333 alu.src[1].sel = ctx->temp_reg;
4334 alu.src[1].chan = 2;
4335
4336 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4337 alu.src[2].chan = 0;
4338 alu.src[2].value = *(uint32_t *)&one_point_five;
4339
4340 alu.dst.sel = ctx->temp_reg;
4341 alu.dst.chan = 0;
4342 alu.dst.write = 1;
4343
4344 r = r600_bytecode_add_alu(ctx->bc, &alu);
4345 if (r)
4346 return r;
4347
4348 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4349 alu.op = ALU_OP3_MULADD;
4350 alu.is_op3 = 1;
4351
4352 alu.src[0].sel = ctx->temp_reg;
4353 alu.src[0].chan = 1;
4354 alu.src[1].sel = ctx->temp_reg;
4355 alu.src[1].chan = 2;
4356
4357 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4358 alu.src[2].chan = 0;
4359 alu.src[2].value = *(uint32_t *)&one_point_five;
4360
4361 alu.dst.sel = ctx->temp_reg;
4362 alu.dst.chan = 1;
4363 alu.dst.write = 1;
4364
4365 alu.last = 1;
4366 r = r600_bytecode_add_alu(ctx->bc, &alu);
4367 if (r)
4368 return r;
4369 /* write initial compare value into Z component
4370 - W src 0 for shadow cube
4371 - X src 1 for shadow cube array */
4372 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4373 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4375 alu.op = ALU_OP1_MOV;
4376 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4377 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4378 else
4379 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4380 alu.dst.sel = ctx->temp_reg;
4381 alu.dst.chan = 2;
4382 alu.dst.write = 1;
4383 alu.last = 1;
4384 r = r600_bytecode_add_alu(ctx->bc, &alu);
4385 if (r)
4386 return r;
4387 }
4388
4389 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4390 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4391 if (ctx->bc->chip_class >= EVERGREEN) {
4392 int mytmp = r600_get_temp(ctx);
4393 static const float eight = 8.0f;
4394 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4395 alu.op = ALU_OP1_MOV;
4396 alu.src[0].sel = ctx->temp_reg;
4397 alu.src[0].chan = 3;
4398 alu.dst.sel = mytmp;
4399 alu.dst.chan = 0;
4400 alu.dst.write = 1;
4401 alu.last = 1;
4402 r = r600_bytecode_add_alu(ctx->bc, &alu);
4403 if (r)
4404 return r;
4405
4406 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4407 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4408 alu.op = ALU_OP3_MULADD;
4409 alu.is_op3 = 1;
4410 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4411 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4412 alu.src[1].chan = 0;
4413 alu.src[1].value = *(uint32_t *)&eight;
4414 alu.src[2].sel = mytmp;
4415 alu.src[2].chan = 0;
4416 alu.dst.sel = ctx->temp_reg;
4417 alu.dst.chan = 3;
4418 alu.dst.write = 1;
4419 alu.last = 1;
4420 r = r600_bytecode_add_alu(ctx->bc, &alu);
4421 if (r)
4422 return r;
4423 } else if (ctx->bc->chip_class < EVERGREEN) {
4424 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4425 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4426 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4427 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4428 tex.src_gpr = r600_get_temp(ctx);
4429 tex.src_sel_x = 0;
4430 tex.src_sel_y = 0;
4431 tex.src_sel_z = 0;
4432 tex.src_sel_w = 0;
4433 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4434 tex.coord_type_x = 1;
4435 tex.coord_type_y = 1;
4436 tex.coord_type_z = 1;
4437 tex.coord_type_w = 1;
4438 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4439 alu.op = ALU_OP1_MOV;
4440 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4441 alu.dst.sel = tex.src_gpr;
4442 alu.dst.chan = 0;
4443 alu.last = 1;
4444 alu.dst.write = 1;
4445 r = r600_bytecode_add_alu(ctx->bc, &alu);
4446 if (r)
4447 return r;
4448
4449 r = r600_bytecode_add_tex(ctx->bc, &tex);
4450 if (r)
4451 return r;
4452 }
4453
4454 }
4455
4456 /* for cube forms of lod and bias we need to route things */
4457 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4458 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4459 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4460 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4462 alu.op = ALU_OP1_MOV;
4463 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4464 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4465 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4466 else
4467 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4468 alu.dst.sel = ctx->temp_reg;
4469 alu.dst.chan = 2;
4470 alu.last = 1;
4471 alu.dst.write = 1;
4472 r = r600_bytecode_add_alu(ctx->bc, &alu);
4473 if (r)
4474 return r;
4475 }
4476
4477 src_loaded = TRUE;
4478 src_gpr = ctx->temp_reg;
4479 }
4480
4481 if (src_requires_loading && !src_loaded) {
4482 for (i = 0; i < 4; i++) {
4483 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4484 alu.op = ALU_OP1_MOV;
4485 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4486 alu.dst.sel = ctx->temp_reg;
4487 alu.dst.chan = i;
4488 if (i == 3)
4489 alu.last = 1;
4490 alu.dst.write = 1;
4491 r = r600_bytecode_add_alu(ctx->bc, &alu);
4492 if (r)
4493 return r;
4494 }
4495 src_loaded = TRUE;
4496 src_gpr = ctx->temp_reg;
4497 }
4498
4499 /* Obtain the sample index for reading a compressed MSAA color texture.
4500 * To read the FMASK, we use the ldfptr instruction, which tells us
4501 * where the samples are stored.
4502 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4503 * which is the identity mapping. Each nibble says which physical sample
4504 * should be fetched to get that sample.
4505 *
4506 * Assume src.z contains the sample index. It should be modified like this:
4507 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4508 * Then fetch the texel with src.
4509 */
4510 if (read_compressed_msaa) {
4511 unsigned sample_chan = 3;
4512 unsigned temp = r600_get_temp(ctx);
4513 assert(src_loaded);
4514
4515 /* temp.w = ldfptr() */
4516 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4517 tex.op = FETCH_OP_LD;
4518 tex.inst_mod = 1; /* to indicate this is ldfptr */
4519 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4520 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4521 tex.src_gpr = src_gpr;
4522 tex.dst_gpr = temp;
4523 tex.dst_sel_x = 7; /* mask out these components */
4524 tex.dst_sel_y = 7;
4525 tex.dst_sel_z = 7;
4526 tex.dst_sel_w = 0; /* store X */
4527 tex.src_sel_x = 0;
4528 tex.src_sel_y = 1;
4529 tex.src_sel_z = 2;
4530 tex.src_sel_w = 3;
4531 tex.offset_x = offset_x;
4532 tex.offset_y = offset_y;
4533 tex.offset_z = offset_z;
4534 r = r600_bytecode_add_tex(ctx->bc, &tex);
4535 if (r)
4536 return r;
4537
4538 /* temp.x = sample_index*4 */
4539 if (ctx->bc->chip_class == CAYMAN) {
4540 for (i = 0 ; i < 4; i++) {
4541 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4542 alu.op = ALU_OP2_MULLO_INT;
4543 alu.src[0].sel = src_gpr;
4544 alu.src[0].chan = sample_chan;
4545 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4546 alu.src[1].value = 4;
4547 alu.dst.sel = temp;
4548 alu.dst.chan = i;
4549 alu.dst.write = i == 0;
4550 if (i == 3)
4551 alu.last = 1;
4552 r = r600_bytecode_add_alu(ctx->bc, &alu);
4553 if (r)
4554 return r;
4555 }
4556 } else {
4557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4558 alu.op = ALU_OP2_MULLO_INT;
4559 alu.src[0].sel = src_gpr;
4560 alu.src[0].chan = sample_chan;
4561 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4562 alu.src[1].value = 4;
4563 alu.dst.sel = temp;
4564 alu.dst.chan = 0;
4565 alu.dst.write = 1;
4566 alu.last = 1;
4567 r = r600_bytecode_add_alu(ctx->bc, &alu);
4568 if (r)
4569 return r;
4570 }
4571
4572 /* sample_index = temp.w >> temp.x */
4573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4574 alu.op = ALU_OP2_LSHR_INT;
4575 alu.src[0].sel = temp;
4576 alu.src[0].chan = 3;
4577 alu.src[1].sel = temp;
4578 alu.src[1].chan = 0;
4579 alu.dst.sel = src_gpr;
4580 alu.dst.chan = sample_chan;
4581 alu.dst.write = 1;
4582 alu.last = 1;
4583 r = r600_bytecode_add_alu(ctx->bc, &alu);
4584 if (r)
4585 return r;
4586
4587 /* sample_index & 0xF */
4588 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4589 alu.op = ALU_OP2_AND_INT;
4590 alu.src[0].sel = src_gpr;
4591 alu.src[0].chan = sample_chan;
4592 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4593 alu.src[1].value = 0xF;
4594 alu.dst.sel = src_gpr;
4595 alu.dst.chan = sample_chan;
4596 alu.dst.write = 1;
4597 alu.last = 1;
4598 r = r600_bytecode_add_alu(ctx->bc, &alu);
4599 if (r)
4600 return r;
4601 #if 0
4602 /* visualize the FMASK */
4603 for (i = 0; i < 4; i++) {
4604 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4605 alu.op = ALU_OP1_INT_TO_FLT;
4606 alu.src[0].sel = src_gpr;
4607 alu.src[0].chan = sample_chan;
4608 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4609 alu.dst.chan = i;
4610 alu.dst.write = 1;
4611 alu.last = 1;
4612 r = r600_bytecode_add_alu(ctx->bc, &alu);
4613 if (r)
4614 return r;
4615 }
4616 return 0;
4617 #endif
4618 }
4619
4620 /* does this shader want a num layers from TXQ for a cube array? */
4621 if (has_txq_cube_array_z) {
4622 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4623
4624 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4625 alu.op = ALU_OP1_MOV;
4626
4627 alu.src[0].sel = 512 + (id / 4);
4628 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4629 alu.src[0].chan = id % 4;
4630 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4631 alu.last = 1;
4632 r = r600_bytecode_add_alu(ctx->bc, &alu);
4633 if (r)
4634 return r;
4635 /* disable writemask from texture instruction */
4636 inst->Dst[0].Register.WriteMask &= ~4;
4637 }
4638
4639 opcode = ctx->inst_info->op;
4640 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4641 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4642 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4643 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4644 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4645 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4646 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4647 switch (opcode) {
4648 case FETCH_OP_SAMPLE:
4649 opcode = FETCH_OP_SAMPLE_C;
4650 break;
4651 case FETCH_OP_SAMPLE_L:
4652 opcode = FETCH_OP_SAMPLE_C_L;
4653 break;
4654 case FETCH_OP_SAMPLE_LB:
4655 opcode = FETCH_OP_SAMPLE_C_LB;
4656 break;
4657 case FETCH_OP_SAMPLE_G:
4658 opcode = FETCH_OP_SAMPLE_C_G;
4659 break;
4660 }
4661 }
4662
4663 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4664 tex.op = opcode;
4665
4666 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4667 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4668 tex.src_gpr = src_gpr;
4669 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4670 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4671 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4672 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4673 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4674
4675 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4676 tex.src_sel_x = 4;
4677 tex.src_sel_y = 4;
4678 tex.src_sel_z = 4;
4679 tex.src_sel_w = 4;
4680 } else if (src_loaded) {
4681 tex.src_sel_x = 0;
4682 tex.src_sel_y = 1;
4683 tex.src_sel_z = 2;
4684 tex.src_sel_w = 3;
4685 } else {
4686 tex.src_sel_x = ctx->src[0].swizzle[0];
4687 tex.src_sel_y = ctx->src[0].swizzle[1];
4688 tex.src_sel_z = ctx->src[0].swizzle[2];
4689 tex.src_sel_w = ctx->src[0].swizzle[3];
4690 tex.src_rel = ctx->src[0].rel;
4691 }
4692
4693 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4694 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4695 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4696 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4697 tex.src_sel_x = 1;
4698 tex.src_sel_y = 0;
4699 tex.src_sel_z = 3;
4700 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4701 }
4702
4703 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4704 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4705 tex.coord_type_x = 1;
4706 tex.coord_type_y = 1;
4707 }
4708 tex.coord_type_z = 1;
4709 tex.coord_type_w = 1;
4710
4711 tex.offset_x = offset_x;
4712 tex.offset_y = offset_y;
4713 tex.offset_z = offset_z;
4714
4715 /* Put the depth for comparison in W.
4716 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4717 * Some instructions expect the depth in Z. */
4718 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4719 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4720 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4721 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4722 opcode != FETCH_OP_SAMPLE_C_L &&
4723 opcode != FETCH_OP_SAMPLE_C_LB) {
4724 tex.src_sel_w = tex.src_sel_z;
4725 }
4726
4727 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4728 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4729 if (opcode == FETCH_OP_SAMPLE_C_L ||
4730 opcode == FETCH_OP_SAMPLE_C_LB) {
4731 /* the array index is read from Y */
4732 tex.coord_type_y = 0;
4733 } else {
4734 /* the array index is read from Z */
4735 tex.coord_type_z = 0;
4736 tex.src_sel_z = tex.src_sel_y;
4737 }
4738 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4739 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4740 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4741 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4742 (ctx->bc->chip_class >= EVERGREEN)))
4743 /* the array index is read from Z */
4744 tex.coord_type_z = 0;
4745
4746 /* mask unused source components */
4747 if (opcode == FETCH_OP_SAMPLE) {
4748 switch (inst->Texture.Texture) {
4749 case TGSI_TEXTURE_2D:
4750 case TGSI_TEXTURE_RECT:
4751 tex.src_sel_z = 7;
4752 tex.src_sel_w = 7;
4753 break;
4754 case TGSI_TEXTURE_1D_ARRAY:
4755 tex.src_sel_y = 7;
4756 tex.src_sel_w = 7;
4757 break;
4758 case TGSI_TEXTURE_1D:
4759 tex.src_sel_y = 7;
4760 tex.src_sel_z = 7;
4761 tex.src_sel_w = 7;
4762 break;
4763 }
4764 }
4765
4766 r = r600_bytecode_add_tex(ctx->bc, &tex);
4767 if (r)
4768 return r;
4769
4770 /* add shadow ambient support - gallium doesn't do it yet */
4771 return 0;
4772 }
4773
4774 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4775 {
4776 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4777 struct r600_bytecode_alu alu;
4778 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4779 unsigned i;
4780 int r;
4781
4782 /* optimize if it's just an equal balance */
4783 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4784 for (i = 0; i < lasti + 1; i++) {
4785 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4786 continue;
4787
4788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4789 alu.op = ALU_OP2_ADD;
4790 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4791 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4792 alu.omod = 3;
4793 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4794 alu.dst.chan = i;
4795 if (i == lasti) {
4796 alu.last = 1;
4797 }
4798 r = r600_bytecode_add_alu(ctx->bc, &alu);
4799 if (r)
4800 return r;
4801 }
4802 return 0;
4803 }
4804
4805 /* 1 - src0 */
4806 for (i = 0; i < lasti + 1; i++) {
4807 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4808 continue;
4809
4810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4811 alu.op = ALU_OP2_ADD;
4812 alu.src[0].sel = V_SQ_ALU_SRC_1;
4813 alu.src[0].chan = 0;
4814 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4815 r600_bytecode_src_toggle_neg(&alu.src[1]);
4816 alu.dst.sel = ctx->temp_reg;
4817 alu.dst.chan = i;
4818 if (i == lasti) {
4819 alu.last = 1;
4820 }
4821 alu.dst.write = 1;
4822 r = r600_bytecode_add_alu(ctx->bc, &alu);
4823 if (r)
4824 return r;
4825 }
4826
4827 /* (1 - src0) * src2 */
4828 for (i = 0; i < lasti + 1; i++) {
4829 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4830 continue;
4831
4832 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4833 alu.op = ALU_OP2_MUL;
4834 alu.src[0].sel = ctx->temp_reg;
4835 alu.src[0].chan = i;
4836 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4837 alu.dst.sel = ctx->temp_reg;
4838 alu.dst.chan = i;
4839 if (i == lasti) {
4840 alu.last = 1;
4841 }
4842 alu.dst.write = 1;
4843 r = r600_bytecode_add_alu(ctx->bc, &alu);
4844 if (r)
4845 return r;
4846 }
4847
4848 /* src0 * src1 + (1 - src0) * src2 */
4849 for (i = 0; i < lasti + 1; i++) {
4850 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4851 continue;
4852
4853 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4854 alu.op = ALU_OP3_MULADD;
4855 alu.is_op3 = 1;
4856 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4857 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4858 alu.src[2].sel = ctx->temp_reg;
4859 alu.src[2].chan = i;
4860
4861 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4862 alu.dst.chan = i;
4863 if (i == lasti) {
4864 alu.last = 1;
4865 }
4866 r = r600_bytecode_add_alu(ctx->bc, &alu);
4867 if (r)
4868 return r;
4869 }
4870 return 0;
4871 }
4872
4873 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4874 {
4875 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4876 struct r600_bytecode_alu alu;
4877 int i, r;
4878 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4879
4880 for (i = 0; i < lasti + 1; i++) {
4881 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4882 continue;
4883
4884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4885 alu.op = ALU_OP3_CNDGE;
4886 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4887 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4888 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4889 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4890 alu.dst.chan = i;
4891 alu.dst.write = 1;
4892 alu.is_op3 = 1;
4893 if (i == lasti)
4894 alu.last = 1;
4895 r = r600_bytecode_add_alu(ctx->bc, &alu);
4896 if (r)
4897 return r;
4898 }
4899 return 0;
4900 }
4901
4902 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4903 {
4904 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4905 struct r600_bytecode_alu alu;
4906 int i, r;
4907 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4908
4909 for (i = 0; i < lasti + 1; i++) {
4910 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4911 continue;
4912
4913 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4914 alu.op = ALU_OP3_CNDGE_INT;
4915 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4916 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4917 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4918 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4919 alu.dst.chan = i;
4920 alu.dst.write = 1;
4921 alu.is_op3 = 1;
4922 if (i == lasti)
4923 alu.last = 1;
4924 r = r600_bytecode_add_alu(ctx->bc, &alu);
4925 if (r)
4926 return r;
4927 }
4928 return 0;
4929 }
4930
4931 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4932 {
4933 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4934 static const unsigned int src0_swizzle[] = {2, 0, 1};
4935 static const unsigned int src1_swizzle[] = {1, 2, 0};
4936 struct r600_bytecode_alu alu;
4937 uint32_t use_temp = 0;
4938 int i, r;
4939
4940 if (inst->Dst[0].Register.WriteMask != 0xf)
4941 use_temp = 1;
4942
4943 for (i = 0; i < 4; i++) {
4944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4945 alu.op = ALU_OP2_MUL;
4946 if (i < 3) {
4947 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4948 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4949 } else {
4950 alu.src[0].sel = V_SQ_ALU_SRC_0;
4951 alu.src[0].chan = i;
4952 alu.src[1].sel = V_SQ_ALU_SRC_0;
4953 alu.src[1].chan = i;
4954 }
4955
4956 alu.dst.sel = ctx->temp_reg;
4957 alu.dst.chan = i;
4958 alu.dst.write = 1;
4959
4960 if (i == 3)
4961 alu.last = 1;
4962 r = r600_bytecode_add_alu(ctx->bc, &alu);
4963 if (r)
4964 return r;
4965 }
4966
4967 for (i = 0; i < 4; i++) {
4968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4969 alu.op = ALU_OP3_MULADD;
4970
4971 if (i < 3) {
4972 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4973 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4974 } else {
4975 alu.src[0].sel = V_SQ_ALU_SRC_0;
4976 alu.src[0].chan = i;
4977 alu.src[1].sel = V_SQ_ALU_SRC_0;
4978 alu.src[1].chan = i;
4979 }
4980
4981 alu.src[2].sel = ctx->temp_reg;
4982 alu.src[2].neg = 1;
4983 alu.src[2].chan = i;
4984
4985 if (use_temp)
4986 alu.dst.sel = ctx->temp_reg;
4987 else
4988 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4989 alu.dst.chan = i;
4990 alu.dst.write = 1;
4991 alu.is_op3 = 1;
4992 if (i == 3)
4993 alu.last = 1;
4994 r = r600_bytecode_add_alu(ctx->bc, &alu);
4995 if (r)
4996 return r;
4997 }
4998 if (use_temp)
4999 return tgsi_helper_copy(ctx, inst);
5000 return 0;
5001 }
5002
5003 static int tgsi_exp(struct r600_shader_ctx *ctx)
5004 {
5005 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5006 struct r600_bytecode_alu alu;
5007 int r;
5008 int i;
5009
5010 /* result.x = 2^floor(src); */
5011 if (inst->Dst[0].Register.WriteMask & 1) {
5012 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5013
5014 alu.op = ALU_OP1_FLOOR;
5015 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5016
5017 alu.dst.sel = ctx->temp_reg;
5018 alu.dst.chan = 0;
5019 alu.dst.write = 1;
5020 alu.last = 1;
5021 r = r600_bytecode_add_alu(ctx->bc, &alu);
5022 if (r)
5023 return r;
5024
5025 if (ctx->bc->chip_class == CAYMAN) {
5026 for (i = 0; i < 3; i++) {
5027 alu.op = ALU_OP1_EXP_IEEE;
5028 alu.src[0].sel = ctx->temp_reg;
5029 alu.src[0].chan = 0;
5030
5031 alu.dst.sel = ctx->temp_reg;
5032 alu.dst.chan = i;
5033 alu.dst.write = i == 0;
5034 alu.last = i == 2;
5035 r = r600_bytecode_add_alu(ctx->bc, &alu);
5036 if (r)
5037 return r;
5038 }
5039 } else {
5040 alu.op = ALU_OP1_EXP_IEEE;
5041 alu.src[0].sel = ctx->temp_reg;
5042 alu.src[0].chan = 0;
5043
5044 alu.dst.sel = ctx->temp_reg;
5045 alu.dst.chan = 0;
5046 alu.dst.write = 1;
5047 alu.last = 1;
5048 r = r600_bytecode_add_alu(ctx->bc, &alu);
5049 if (r)
5050 return r;
5051 }
5052 }
5053
5054 /* result.y = tmp - floor(tmp); */
5055 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5056 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5057
5058 alu.op = ALU_OP1_FRACT;
5059 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5060
5061 alu.dst.sel = ctx->temp_reg;
5062 #if 0
5063 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5064 if (r)
5065 return r;
5066 #endif
5067 alu.dst.write = 1;
5068 alu.dst.chan = 1;
5069
5070 alu.last = 1;
5071
5072 r = r600_bytecode_add_alu(ctx->bc, &alu);
5073 if (r)
5074 return r;
5075 }
5076
5077 /* result.z = RoughApprox2ToX(tmp);*/
5078 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
5079 if (ctx->bc->chip_class == CAYMAN) {
5080 for (i = 0; i < 3; i++) {
5081 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5082 alu.op = ALU_OP1_EXP_IEEE;
5083 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5084
5085 alu.dst.sel = ctx->temp_reg;
5086 alu.dst.chan = i;
5087 if (i == 2) {
5088 alu.dst.write = 1;
5089 alu.last = 1;
5090 }
5091
5092 r = r600_bytecode_add_alu(ctx->bc, &alu);
5093 if (r)
5094 return r;
5095 }
5096 } else {
5097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5098 alu.op = ALU_OP1_EXP_IEEE;
5099 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5100
5101 alu.dst.sel = ctx->temp_reg;
5102 alu.dst.write = 1;
5103 alu.dst.chan = 2;
5104
5105 alu.last = 1;
5106
5107 r = r600_bytecode_add_alu(ctx->bc, &alu);
5108 if (r)
5109 return r;
5110 }
5111 }
5112
5113 /* result.w = 1.0;*/
5114 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
5115 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5116
5117 alu.op = ALU_OP1_MOV;
5118 alu.src[0].sel = V_SQ_ALU_SRC_1;
5119 alu.src[0].chan = 0;
5120
5121 alu.dst.sel = ctx->temp_reg;
5122 alu.dst.chan = 3;
5123 alu.dst.write = 1;
5124 alu.last = 1;
5125 r = r600_bytecode_add_alu(ctx->bc, &alu);
5126 if (r)
5127 return r;
5128 }
5129 return tgsi_helper_copy(ctx, inst);
5130 }
5131
5132 static int tgsi_log(struct r600_shader_ctx *ctx)
5133 {
5134 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5135 struct r600_bytecode_alu alu;
5136 int r;
5137 int i;
5138
5139 /* result.x = floor(log2(|src|)); */
5140 if (inst->Dst[0].Register.WriteMask & 1) {
5141 if (ctx->bc->chip_class == CAYMAN) {
5142 for (i = 0; i < 3; i++) {
5143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5144
5145 alu.op = ALU_OP1_LOG_IEEE;
5146 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5147 r600_bytecode_src_set_abs(&alu.src[0]);
5148
5149 alu.dst.sel = ctx->temp_reg;
5150 alu.dst.chan = i;
5151 if (i == 0)
5152 alu.dst.write = 1;
5153 if (i == 2)
5154 alu.last = 1;
5155 r = r600_bytecode_add_alu(ctx->bc, &alu);
5156 if (r)
5157 return r;
5158 }
5159
5160 } else {
5161 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5162
5163 alu.op = ALU_OP1_LOG_IEEE;
5164 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5165 r600_bytecode_src_set_abs(&alu.src[0]);
5166
5167 alu.dst.sel = ctx->temp_reg;
5168 alu.dst.chan = 0;
5169 alu.dst.write = 1;
5170 alu.last = 1;
5171 r = r600_bytecode_add_alu(ctx->bc, &alu);
5172 if (r)
5173 return r;
5174 }
5175
5176 alu.op = ALU_OP1_FLOOR;
5177 alu.src[0].sel = ctx->temp_reg;
5178 alu.src[0].chan = 0;
5179
5180 alu.dst.sel = ctx->temp_reg;
5181 alu.dst.chan = 0;
5182 alu.dst.write = 1;
5183 alu.last = 1;
5184
5185 r = r600_bytecode_add_alu(ctx->bc, &alu);
5186 if (r)
5187 return r;
5188 }
5189
5190 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
5191 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5192
5193 if (ctx->bc->chip_class == CAYMAN) {
5194 for (i = 0; i < 3; i++) {
5195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5196
5197 alu.op = ALU_OP1_LOG_IEEE;
5198 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5199 r600_bytecode_src_set_abs(&alu.src[0]);
5200
5201 alu.dst.sel = ctx->temp_reg;
5202 alu.dst.chan = i;
5203 if (i == 1)
5204 alu.dst.write = 1;
5205 if (i == 2)
5206 alu.last = 1;
5207
5208 r = r600_bytecode_add_alu(ctx->bc, &alu);
5209 if (r)
5210 return r;
5211 }
5212 } else {
5213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5214
5215 alu.op = ALU_OP1_LOG_IEEE;
5216 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5217 r600_bytecode_src_set_abs(&alu.src[0]);
5218
5219 alu.dst.sel = ctx->temp_reg;
5220 alu.dst.chan = 1;
5221 alu.dst.write = 1;
5222 alu.last = 1;
5223
5224 r = r600_bytecode_add_alu(ctx->bc, &alu);
5225 if (r)
5226 return r;
5227 }
5228
5229 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5230
5231 alu.op = ALU_OP1_FLOOR;
5232 alu.src[0].sel = ctx->temp_reg;
5233 alu.src[0].chan = 1;
5234
5235 alu.dst.sel = ctx->temp_reg;
5236 alu.dst.chan = 1;
5237 alu.dst.write = 1;
5238 alu.last = 1;
5239
5240 r = r600_bytecode_add_alu(ctx->bc, &alu);
5241 if (r)
5242 return r;
5243
5244 if (ctx->bc->chip_class == CAYMAN) {
5245 for (i = 0; i < 3; i++) {
5246 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5247 alu.op = ALU_OP1_EXP_IEEE;
5248 alu.src[0].sel = ctx->temp_reg;
5249 alu.src[0].chan = 1;
5250
5251 alu.dst.sel = ctx->temp_reg;
5252 alu.dst.chan = i;
5253 if (i == 1)
5254 alu.dst.write = 1;
5255 if (i == 2)
5256 alu.last = 1;
5257
5258 r = r600_bytecode_add_alu(ctx->bc, &alu);
5259 if (r)
5260 return r;
5261 }
5262 } else {
5263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5264 alu.op = ALU_OP1_EXP_IEEE;
5265 alu.src[0].sel = ctx->temp_reg;
5266 alu.src[0].chan = 1;
5267
5268 alu.dst.sel = ctx->temp_reg;
5269 alu.dst.chan = 1;
5270 alu.dst.write = 1;
5271 alu.last = 1;
5272
5273 r = r600_bytecode_add_alu(ctx->bc, &alu);
5274 if (r)
5275 return r;
5276 }
5277
5278 if (ctx->bc->chip_class == CAYMAN) {
5279 for (i = 0; i < 3; i++) {
5280 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5281 alu.op = ALU_OP1_RECIP_IEEE;
5282 alu.src[0].sel = ctx->temp_reg;
5283 alu.src[0].chan = 1;
5284
5285 alu.dst.sel = ctx->temp_reg;
5286 alu.dst.chan = i;
5287 if (i == 1)
5288 alu.dst.write = 1;
5289 if (i == 2)
5290 alu.last = 1;
5291
5292 r = r600_bytecode_add_alu(ctx->bc, &alu);
5293 if (r)
5294 return r;
5295 }
5296 } else {
5297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5298 alu.op = ALU_OP1_RECIP_IEEE;
5299 alu.src[0].sel = ctx->temp_reg;
5300 alu.src[0].chan = 1;
5301
5302 alu.dst.sel = ctx->temp_reg;
5303 alu.dst.chan = 1;
5304 alu.dst.write = 1;
5305 alu.last = 1;
5306
5307 r = r600_bytecode_add_alu(ctx->bc, &alu);
5308 if (r)
5309 return r;
5310 }
5311
5312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5313
5314 alu.op = ALU_OP2_MUL;
5315
5316 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5317 r600_bytecode_src_set_abs(&alu.src[0]);
5318
5319 alu.src[1].sel = ctx->temp_reg;
5320 alu.src[1].chan = 1;
5321
5322 alu.dst.sel = ctx->temp_reg;
5323 alu.dst.chan = 1;
5324 alu.dst.write = 1;
5325 alu.last = 1;
5326
5327 r = r600_bytecode_add_alu(ctx->bc, &alu);
5328 if (r)
5329 return r;
5330 }
5331
5332 /* result.z = log2(|src|);*/
5333 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5334 if (ctx->bc->chip_class == CAYMAN) {
5335 for (i = 0; i < 3; i++) {
5336 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5337
5338 alu.op = ALU_OP1_LOG_IEEE;
5339 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5340 r600_bytecode_src_set_abs(&alu.src[0]);
5341
5342 alu.dst.sel = ctx->temp_reg;
5343 if (i == 2)
5344 alu.dst.write = 1;
5345 alu.dst.chan = i;
5346 if (i == 2)
5347 alu.last = 1;
5348
5349 r = r600_bytecode_add_alu(ctx->bc, &alu);
5350 if (r)
5351 return r;
5352 }
5353 } else {
5354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5355
5356 alu.op = ALU_OP1_LOG_IEEE;
5357 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5358 r600_bytecode_src_set_abs(&alu.src[0]);
5359
5360 alu.dst.sel = ctx->temp_reg;
5361 alu.dst.write = 1;
5362 alu.dst.chan = 2;
5363 alu.last = 1;
5364
5365 r = r600_bytecode_add_alu(ctx->bc, &alu);
5366 if (r)
5367 return r;
5368 }
5369 }
5370
5371 /* result.w = 1.0; */
5372 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5374
5375 alu.op = ALU_OP1_MOV;
5376 alu.src[0].sel = V_SQ_ALU_SRC_1;
5377 alu.src[0].chan = 0;
5378
5379 alu.dst.sel = ctx->temp_reg;
5380 alu.dst.chan = 3;
5381 alu.dst.write = 1;
5382 alu.last = 1;
5383
5384 r = r600_bytecode_add_alu(ctx->bc, &alu);
5385 if (r)
5386 return r;
5387 }
5388
5389 return tgsi_helper_copy(ctx, inst);
5390 }
5391
5392 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5393 {
5394 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5395 struct r600_bytecode_alu alu;
5396 int r;
5397
5398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5399
5400 switch (inst->Instruction.Opcode) {
5401 case TGSI_OPCODE_ARL:
5402 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5403 break;
5404 case TGSI_OPCODE_ARR:
5405 alu.op = ALU_OP1_FLT_TO_INT;
5406 break;
5407 case TGSI_OPCODE_UARL:
5408 alu.op = ALU_OP1_MOV;
5409 break;
5410 default:
5411 assert(0);
5412 return -1;
5413 }
5414
5415 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5416 alu.last = 1;
5417 alu.dst.sel = ctx->bc->ar_reg;
5418 alu.dst.write = 1;
5419 r = r600_bytecode_add_alu(ctx->bc, &alu);
5420 if (r)
5421 return r;
5422
5423 ctx->bc->ar_loaded = 0;
5424 return 0;
5425 }
5426 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5427 {
5428 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5429 struct r600_bytecode_alu alu;
5430 int r;
5431
5432 switch (inst->Instruction.Opcode) {
5433 case TGSI_OPCODE_ARL:
5434 memset(&alu, 0, sizeof(alu));
5435 alu.op = ALU_OP1_FLOOR;
5436 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5437 alu.dst.sel = ctx->bc->ar_reg;
5438 alu.dst.write = 1;
5439 alu.last = 1;
5440
5441 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5442 return r;
5443
5444 memset(&alu, 0, sizeof(alu));
5445 alu.op = ALU_OP1_FLT_TO_INT;
5446 alu.src[0].sel = ctx->bc->ar_reg;
5447 alu.dst.sel = ctx->bc->ar_reg;
5448 alu.dst.write = 1;
5449 alu.last = 1;
5450
5451 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5452 return r;
5453 break;
5454 case TGSI_OPCODE_ARR:
5455 memset(&alu, 0, sizeof(alu));
5456 alu.op = ALU_OP1_FLT_TO_INT;
5457 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5458 alu.dst.sel = ctx->bc->ar_reg;
5459 alu.dst.write = 1;
5460 alu.last = 1;
5461
5462 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5463 return r;
5464 break;
5465 case TGSI_OPCODE_UARL:
5466 memset(&alu, 0, sizeof(alu));
5467 alu.op = ALU_OP1_MOV;
5468 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5469 alu.dst.sel = ctx->bc->ar_reg;
5470 alu.dst.write = 1;
5471 alu.last = 1;
5472
5473 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5474 return r;
5475 break;
5476 default:
5477 assert(0);
5478 return -1;
5479 }
5480
5481 ctx->bc->ar_loaded = 0;
5482 return 0;
5483 }
5484
5485 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5486 {
5487 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5488 struct r600_bytecode_alu alu;
5489 int i, r = 0;
5490
5491 for (i = 0; i < 4; i++) {
5492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5493
5494 alu.op = ALU_OP2_MUL;
5495 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5496
5497 if (i == 0 || i == 3) {
5498 alu.src[0].sel = V_SQ_ALU_SRC_1;
5499 } else {
5500 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5501 }
5502
5503 if (i == 0 || i == 2) {
5504 alu.src[1].sel = V_SQ_ALU_SRC_1;
5505 } else {
5506 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5507 }
5508 if (i == 3)
5509 alu.last = 1;
5510 r = r600_bytecode_add_alu(ctx->bc, &alu);
5511 if (r)
5512 return r;
5513 }
5514 return 0;
5515 }
5516
5517 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5518 {
5519 struct r600_bytecode_alu alu;
5520 int r;
5521
5522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5523 alu.op = opcode;
5524 alu.execute_mask = 1;
5525 alu.update_pred = 1;
5526
5527 alu.dst.sel = ctx->temp_reg;
5528 alu.dst.write = 1;
5529 alu.dst.chan = 0;
5530
5531 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5532 alu.src[1].sel = V_SQ_ALU_SRC_0;
5533 alu.src[1].chan = 0;
5534
5535 alu.last = 1;
5536
5537 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5538 if (r)
5539 return r;
5540 return 0;
5541 }
5542
5543 static int pops(struct r600_shader_ctx *ctx, int pops)
5544 {
5545 unsigned force_pop = ctx->bc->force_add_cf;
5546
5547 if (!force_pop) {
5548 int alu_pop = 3;
5549 if (ctx->bc->cf_last) {
5550 if (ctx->bc->cf_last->op == CF_OP_ALU)
5551 alu_pop = 0;
5552 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5553 alu_pop = 1;
5554 }
5555 alu_pop += pops;
5556 if (alu_pop == 1) {
5557 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5558 ctx->bc->force_add_cf = 1;
5559 } else if (alu_pop == 2) {
5560 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5561 ctx->bc->force_add_cf = 1;
5562 } else {
5563 force_pop = 1;
5564 }
5565 }
5566
5567 if (force_pop) {
5568 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5569 ctx->bc->cf_last->pop_count = pops;
5570 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5571 }
5572
5573 return 0;
5574 }
5575
5576 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5577 unsigned reason)
5578 {
5579 struct r600_stack_info *stack = &ctx->bc->stack;
5580 unsigned elements, entries;
5581
5582 unsigned entry_size = stack->entry_size;
5583
5584 elements = (stack->loop + stack->push_wqm ) * entry_size;
5585 elements += stack->push;
5586
5587 switch (ctx->bc->chip_class) {
5588 case R600:
5589 case R700:
5590 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5591 * the stack must be reserved to hold the current active/continue
5592 * masks */
5593 if (reason == FC_PUSH_VPM) {
5594 elements += 2;
5595 }
5596 break;
5597
5598 case CAYMAN:
5599 /* r9xx: any stack operation on empty stack consumes 2 additional
5600 * elements */
5601 elements += 2;
5602
5603 /* fallthrough */
5604 /* FIXME: do the two elements added above cover the cases for the
5605 * r8xx+ below? */
5606
5607 case EVERGREEN:
5608 /* r8xx+: 2 extra elements are not always required, but one extra
5609 * element must be added for each of the following cases:
5610 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5611 * stack usage.
5612 * (Currently we don't use ALU_ELSE_AFTER.)
5613 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5614 * PUSH instruction executed.
5615 *
5616 * NOTE: it seems we also need to reserve additional element in some
5617 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5618 * then STACK_SIZE should be 2 instead of 1 */
5619 if (reason == FC_PUSH_VPM) {
5620 elements += 1;
5621 }
5622 break;
5623
5624 default:
5625 assert(0);
5626 break;
5627 }
5628
5629 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5630 * for all chips, so we use 4 in the final formula, not the real entry_size
5631 * for the chip */
5632 entry_size = 4;
5633
5634 entries = (elements + (entry_size - 1)) / entry_size;
5635
5636 if (entries > stack->max_entries)
5637 stack->max_entries = entries;
5638 }
5639
5640 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5641 {
5642 switch(reason) {
5643 case FC_PUSH_VPM:
5644 --ctx->bc->stack.push;
5645 assert(ctx->bc->stack.push >= 0);
5646 break;
5647 case FC_PUSH_WQM:
5648 --ctx->bc->stack.push_wqm;
5649 assert(ctx->bc->stack.push_wqm >= 0);
5650 break;
5651 case FC_LOOP:
5652 --ctx->bc->stack.loop;
5653 assert(ctx->bc->stack.loop >= 0);
5654 break;
5655 default:
5656 assert(0);
5657 break;
5658 }
5659 }
5660
5661 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5662 {
5663 switch (reason) {
5664 case FC_PUSH_VPM:
5665 ++ctx->bc->stack.push;
5666 break;
5667 case FC_PUSH_WQM:
5668 ++ctx->bc->stack.push_wqm;
5669 case FC_LOOP:
5670 ++ctx->bc->stack.loop;
5671 break;
5672 default:
5673 assert(0);
5674 }
5675
5676 callstack_update_max_depth(ctx, reason);
5677 }
5678
5679 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5680 {
5681 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5682
5683 sp->mid = realloc((void *)sp->mid,
5684 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5685 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5686 sp->num_mid++;
5687 }
5688
5689 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5690 {
5691 ctx->bc->fc_sp++;
5692 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5693 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5694 }
5695
5696 static void fc_poplevel(struct r600_shader_ctx *ctx)
5697 {
5698 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5699 free(sp->mid);
5700 sp->mid = NULL;
5701 sp->num_mid = 0;
5702 sp->start = NULL;
5703 sp->type = 0;
5704 ctx->bc->fc_sp--;
5705 }
5706
5707 #if 0
5708 static int emit_return(struct r600_shader_ctx *ctx)
5709 {
5710 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5711 return 0;
5712 }
5713
5714 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5715 {
5716
5717 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5718 ctx->bc->cf_last->pop_count = pops;
5719 /* XXX work out offset */
5720 return 0;
5721 }
5722
5723 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5724 {
5725 return 0;
5726 }
5727
5728 static void emit_testflag(struct r600_shader_ctx *ctx)
5729 {
5730
5731 }
5732
5733 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5734 {
5735 emit_testflag(ctx);
5736 emit_jump_to_offset(ctx, 1, 4);
5737 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5738 pops(ctx, ifidx + 1);
5739 emit_return(ctx);
5740 }
5741
5742 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5743 {
5744 emit_testflag(ctx);
5745
5746 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5747 ctx->bc->cf_last->pop_count = 1;
5748
5749 fc_set_mid(ctx, fc_sp);
5750
5751 pops(ctx, 1);
5752 }
5753 #endif
5754
5755 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
5756 {
5757 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5758
5759 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
5760 * LOOP_STARTxxx for nested loops may put the branch stack into a state
5761 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
5762 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
5763 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
5764 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
5765 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5766 alu_type = CF_OP_ALU;
5767 }
5768
5769 emit_logic_pred(ctx, opcode, alu_type);
5770
5771 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5772
5773 fc_pushlevel(ctx, FC_IF);
5774
5775 callstack_push(ctx, FC_PUSH_VPM);
5776 return 0;
5777 }
5778
5779 static int tgsi_if(struct r600_shader_ctx *ctx)
5780 {
5781 return emit_if(ctx, ALU_OP2_PRED_SETNE);
5782 }
5783
5784 static int tgsi_uif(struct r600_shader_ctx *ctx)
5785 {
5786 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
5787 }
5788
5789 static int tgsi_else(struct r600_shader_ctx *ctx)
5790 {
5791 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5792 ctx->bc->cf_last->pop_count = 1;
5793
5794 fc_set_mid(ctx, ctx->bc->fc_sp);
5795 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5796 return 0;
5797 }
5798
5799 static int tgsi_endif(struct r600_shader_ctx *ctx)
5800 {
5801 pops(ctx, 1);
5802 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5803 R600_ERR("if/endif unbalanced in shader\n");
5804 return -1;
5805 }
5806
5807 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5808 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5809 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5810 } else {
5811 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5812 }
5813 fc_poplevel(ctx);
5814
5815 callstack_pop(ctx, FC_PUSH_VPM);
5816 return 0;
5817 }
5818
5819 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5820 {
5821 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5822 * limited to 4096 iterations, like the other LOOP_* instructions. */
5823 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5824
5825 fc_pushlevel(ctx, FC_LOOP);
5826
5827 /* check stack depth */
5828 callstack_push(ctx, FC_LOOP);
5829 return 0;
5830 }
5831
5832 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5833 {
5834 int i;
5835
5836 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5837
5838 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5839 R600_ERR("loop/endloop in shader code are not paired.\n");
5840 return -EINVAL;
5841 }
5842
5843 /* fixup loop pointers - from r600isa
5844 LOOP END points to CF after LOOP START,
5845 LOOP START point to CF after LOOP END
5846 BRK/CONT point to LOOP END CF
5847 */
5848 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5849
5850 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5851
5852 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5853 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5854 }
5855 /* XXX add LOOPRET support */
5856 fc_poplevel(ctx);
5857 callstack_pop(ctx, FC_LOOP);
5858 return 0;
5859 }
5860
5861 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5862 {
5863 unsigned int fscp;
5864
5865 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5866 {
5867 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5868 break;
5869 }
5870
5871 if (fscp == 0) {
5872 R600_ERR("Break not inside loop/endloop pair\n");
5873 return -EINVAL;
5874 }
5875
5876 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5877
5878 fc_set_mid(ctx, fscp);
5879
5880 return 0;
5881 }
5882
5883 static int tgsi_umad(struct r600_shader_ctx *ctx)
5884 {
5885 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5886 struct r600_bytecode_alu alu;
5887 int i, j, k, r;
5888 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5889
5890 /* src0 * src1 */
5891 for (i = 0; i < lasti + 1; i++) {
5892 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5893 continue;
5894
5895 if (ctx->bc->chip_class == CAYMAN) {
5896 for (j = 0 ; j < 4; j++) {
5897 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5898
5899 alu.op = ALU_OP2_MULLO_UINT;
5900 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
5901 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
5902 }
5903 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
5904 alu.dst.sel = ctx->temp_reg;
5905 alu.dst.write = (j == i);
5906 if (j == 3)
5907 alu.last = 1;
5908 r = r600_bytecode_add_alu(ctx->bc, &alu);
5909 if (r)
5910 return r;
5911 }
5912 } else {
5913 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5914
5915 alu.dst.chan = i;
5916 alu.dst.sel = ctx->temp_reg;
5917 alu.dst.write = 1;
5918
5919 alu.op = ALU_OP2_MULLO_UINT;
5920 for (j = 0; j < 2; j++) {
5921 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5922 }
5923
5924 alu.last = 1;
5925 r = r600_bytecode_add_alu(ctx->bc, &alu);
5926 if (r)
5927 return r;
5928 }
5929 }
5930
5931
5932 for (i = 0; i < lasti + 1; i++) {
5933 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5934 continue;
5935
5936 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5937 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5938
5939 alu.op = ALU_OP2_ADD_INT;
5940
5941 alu.src[0].sel = ctx->temp_reg;
5942 alu.src[0].chan = i;
5943
5944 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5945 if (i == lasti) {
5946 alu.last = 1;
5947 }
5948 r = r600_bytecode_add_alu(ctx->bc, &alu);
5949 if (r)
5950 return r;
5951 }
5952 return 0;
5953 }
5954
5955 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5956 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
5957 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5958 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5959
5960 /* XXX:
5961 * For state trackers other than OpenGL, we'll want to use
5962 * _RECIP_IEEE instead.
5963 */
5964 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5965
5966 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
5967 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5968 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5969 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5970 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5971 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5972 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5973 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5974 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5975 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5976 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5977 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5978 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5979 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5980 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5981 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5982 /* gap */
5983 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5984 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5985 /* gap */
5986 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5987 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5988 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5989 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5990 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5991 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5992 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5993 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5994 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5995 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5996 /* gap */
5997 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5998 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5999 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6000 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6001 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6002 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6003 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6004 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6005 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6006 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6007 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6008 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6009 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6010 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6011 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6012 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6013 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6014 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6015 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6016 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6017 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6018 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6019 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6020 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6021 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6022 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6023 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6024 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6025 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6026 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
6027 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6028 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6029 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6030 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6031 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6032 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6033 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6034 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6035 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6036 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6037 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6038 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6039 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6040 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6041 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6042 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6043 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6044 /* gap */
6045 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6046 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6047 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6048 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6049 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6050 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6051 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6052 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6053 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
6054 /* gap */
6055 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6056 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6057 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6058 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6059 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6060 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6061 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6062 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6063 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6064 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6065 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6066 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6067 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6068 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6069 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6070 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6071 /* gap */
6072 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6073 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6074 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6075 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6076 /* gap */
6077 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6078 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6079 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6080 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6081 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6082 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6083 /* gap */
6084 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6085 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6086 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6087 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6088 /* gap */
6089 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6090 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
6091 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6092 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6093 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6094 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6095 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6096 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
6097 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6098 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
6099 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6100 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6101 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6102 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6103 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6104 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6105 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6106 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6107 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6108 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6109 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
6110 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6111 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
6112 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6113 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6114 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6115 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6116 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6117 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6118 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6119 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6120 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6121 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6122 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6123 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6124 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6125 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6126 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6127 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6128 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
6129 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6130 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6131 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6132 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6133 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6134 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6135 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6136 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6137 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6138 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6139 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6140 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6141 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6142 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6143 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6144 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6145 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6146 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6147 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6148 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6149 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6150 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6151 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6152 };
6153
6154 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
6155 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6156 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6157 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6158 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
6159 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
6160 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6161 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6162 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6163 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6164 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6165 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6166 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6167 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6168 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6169 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6170 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6171 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6172 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6173 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6174 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6175 /* gap */
6176 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6177 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6178 /* gap */
6179 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6180 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6181 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6182 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6183 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6184 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6185 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6186 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6187 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6188 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6189 /* gap */
6190 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6191 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6192 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6193 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6194 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6195 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6196 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6197 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6198 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6199 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6200 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6201 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6202 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6203 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6204 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6205 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6206 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6207 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6208 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6209 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6210 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6211 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6212 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6213 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6214 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6215 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6216 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6217 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6218 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6219 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6220 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6221 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6222 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6223 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6224 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6225 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6226 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6227 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6228 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6229 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6230 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6231 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6232 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6233 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6234 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6235 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6236 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6237 /* gap */
6238 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6239 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6240 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6241 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6242 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6243 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6244 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6245 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6246 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6247 /* gap */
6248 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6249 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6250 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6251 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6252 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6253 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6254 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6255 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6256 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6257 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6258 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6259 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6260 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6261 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6262 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6263 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6264 /* gap */
6265 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6266 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6267 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6268 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6269 /* gap */
6270 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6271 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6272 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6273 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6274 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6275 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6276 /* gap */
6277 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6278 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6279 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6280 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6281 /* gap */
6282 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6283 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
6284 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6285 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6286 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6287 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6288 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6289 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6290 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6291 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
6292 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6293 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6294 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6295 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6296 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6297 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6298 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6299 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6300 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6301 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6302 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6303 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6304 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6305 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6306 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6307 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6308 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6309 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6310 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6311 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6312 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6313 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6314 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6315 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6316 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6317 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6318 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6319 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6320 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6321 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6322 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6323 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6324 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6325 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6326 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6327 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6328 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6329 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6330 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6331 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6332 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6333 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6334 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6335 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6336 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6337 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6338 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6339 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6340 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6341 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6342 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6343 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6344 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6345 };
6346
6347 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6348 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6349 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6350 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6351 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6352 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6353 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6354 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6355 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6356 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6357 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6358 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6359 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6360 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6361 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6362 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6363 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6364 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6365 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6366 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6367 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6368 /* gap */
6369 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6370 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6371 /* gap */
6372 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6373 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6374 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6375 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6376 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6377 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6378 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6379 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6380 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6381 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6382 /* gap */
6383 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6384 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6385 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6386 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6387 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6388 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6389 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6390 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6391 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6392 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6393 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6394 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6395 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6396 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6397 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6398 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6399 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6400 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6401 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6402 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6403 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6404 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6405 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6406 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6407 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6408 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6409 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6410 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6411 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6412 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6413 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6414 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6415 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6416 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6417 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6418 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6419 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6420 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6421 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6422 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6423 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6424 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6425 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6426 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6427 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6428 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6429 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6430 /* gap */
6431 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6432 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6433 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6434 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6435 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6436 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6437 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6438 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6439 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6440 /* gap */
6441 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6442 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6443 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6444 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6445 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6446 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6447 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6448 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6449 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6450 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6451 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6452 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6453 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6454 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6455 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6456 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6457 /* gap */
6458 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6459 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6460 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6461 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6462 /* gap */
6463 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6464 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6465 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6466 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6467 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6468 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6469 /* gap */
6470 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6471 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6472 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6473 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6474 /* gap */
6475 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6476 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6477 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6478 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6479 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6480 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6481 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6482 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6483 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6484 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6485 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6486 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6487 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6488 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6489 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6490 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6491 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6492 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6493 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6494 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6495 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6496 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6497 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6498 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6499 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6500 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6501 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6502 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6503 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6504 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6505 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6506 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6507 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6508 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6509 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6510 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6511 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6512 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6513 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6514 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6515 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6516 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6517 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6518 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6519 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6520 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6521 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6522 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6523 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6524 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6525 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6526 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6527 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6528 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6529 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6530 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6531 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6532 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6533 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6534 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6535 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6536 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6537 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6538 };