2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
29 #include "sb/sb_public.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
43 Why CAYMAN got loops for lots of instructions is explained here.
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
63 /* Contents of r0 on entry to various shaders
69 GS - r0.xyw, r1.xyz = per-vertex offsets
75 .w = tess factor base.
77 TES - .x = TessCoord.x
79 - .z = RelPatchID (??)
82 PS - face_gpr.z = SampleMask
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
87 struct r600_pipe_shader
*pipeshader
,
88 union r600_shader_key key
);
90 static void r600_add_gpr_array(struct r600_shader
*ps
, int start_gpr
,
91 int size
, unsigned comp_mask
) {
96 if (ps
->num_arrays
== ps
->max_arrays
) {
98 ps
->arrays
= realloc(ps
->arrays
, ps
->max_arrays
*
99 sizeof(struct r600_shader_array
));
102 int n
= ps
->num_arrays
;
105 ps
->arrays
[n
].comp_mask
= comp_mask
;
106 ps
->arrays
[n
].gpr_start
= start_gpr
;
107 ps
->arrays
[n
].gpr_count
= size
;
110 static void r600_dump_streamout(struct pipe_stream_output_info
*so
)
114 fprintf(stderr
, "STREAMOUT\n");
115 for (i
= 0; i
< so
->num_outputs
; i
++) {
116 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
117 so
->output
[i
].start_component
;
118 fprintf(stderr
, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
120 so
->output
[i
].stream
,
121 so
->output
[i
].output_buffer
,
122 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
123 so
->output
[i
].register_index
,
128 so
->output
[i
].dst_offset
< so
->output
[i
].start_component
? " (will lower)" : "");
132 static int store_shader(struct pipe_context
*ctx
,
133 struct r600_pipe_shader
*shader
)
135 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
138 if (shader
->bo
== NULL
) {
139 shader
->bo
= (struct r600_resource
*)
140 pipe_buffer_create(ctx
->screen
, 0, PIPE_USAGE_IMMUTABLE
, shader
->shader
.bc
.ndw
* 4);
141 if (shader
->bo
== NULL
) {
144 ptr
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->bo
, PIPE_TRANSFER_WRITE
);
145 if (R600_BIG_ENDIAN
) {
146 for (i
= 0; i
< shader
->shader
.bc
.ndw
; ++i
) {
147 ptr
[i
] = util_cpu_to_le32(shader
->shader
.bc
.bytecode
[i
]);
150 memcpy(ptr
, shader
->shader
.bc
.bytecode
, shader
->shader
.bc
.ndw
* sizeof(*ptr
));
152 rctx
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
158 int r600_pipe_shader_create(struct pipe_context
*ctx
,
159 struct r600_pipe_shader
*shader
,
160 union r600_shader_key key
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_shader_selector
*sel
= shader
->selector
;
165 bool dump
= r600_can_dump_shader(&rctx
->screen
->b
,
166 tgsi_get_processor_type(sel
->tokens
));
167 unsigned use_sb
= !(rctx
->screen
->b
.debug_flags
& DBG_NO_SB
);
168 unsigned sb_disasm
= use_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
169 unsigned export_shader
;
171 shader
->shader
.bc
.isa
= rctx
->isa
;
174 fprintf(stderr
, "--------------------------------------------------------------\n");
175 tgsi_dump(sel
->tokens
, 0);
177 if (sel
->so
.num_outputs
) {
178 r600_dump_streamout(&sel
->so
);
181 r
= r600_shader_from_tgsi(rctx
, shader
, key
);
183 R600_ERR("translation from TGSI failed !\n");
186 if (shader
->shader
.processor_type
== PIPE_SHADER_VERTEX
) {
187 /* only disable for vertex shaders in tess paths */
191 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_CTRL
);
192 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_EVAL
);
193 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_COMPUTE
);
195 /* disable SB for shaders using doubles */
196 use_sb
&= !shader
->shader
.uses_doubles
;
198 use_sb
&= !shader
->shader
.uses_atomics
;
199 use_sb
&= !shader
->shader
.uses_images
;
201 /* Check if the bytecode has already been built. */
202 if (!shader
->shader
.bc
.bytecode
) {
203 r
= r600_bytecode_build(&shader
->shader
.bc
);
205 R600_ERR("building bytecode failed !\n");
210 if (dump
&& !sb_disasm
) {
211 fprintf(stderr
, "--------------------------------------------------------------\n");
212 r600_bytecode_disasm(&shader
->shader
.bc
);
213 fprintf(stderr
, "______________________________________________________________\n");
214 } else if ((dump
&& sb_disasm
) || use_sb
) {
215 r
= r600_sb_bytecode_process(rctx
, &shader
->shader
.bc
, &shader
->shader
,
218 R600_ERR("r600_sb_bytecode_process failed !\n");
223 if (shader
->gs_copy_shader
) {
226 r
= r600_sb_bytecode_process(rctx
, &shader
->gs_copy_shader
->shader
.bc
,
227 &shader
->gs_copy_shader
->shader
, dump
, 0);
232 if ((r
= store_shader(ctx
, shader
->gs_copy_shader
)))
236 /* Store the shader in a buffer. */
237 if ((r
= store_shader(ctx
, shader
)))
241 switch (shader
->shader
.processor_type
) {
242 case PIPE_SHADER_TESS_CTRL
:
243 evergreen_update_hs_state(ctx
, shader
);
245 case PIPE_SHADER_TESS_EVAL
:
247 evergreen_update_es_state(ctx
, shader
);
249 evergreen_update_vs_state(ctx
, shader
);
251 case PIPE_SHADER_GEOMETRY
:
252 if (rctx
->b
.chip_class
>= EVERGREEN
) {
253 evergreen_update_gs_state(ctx
, shader
);
254 evergreen_update_vs_state(ctx
, shader
->gs_copy_shader
);
256 r600_update_gs_state(ctx
, shader
);
257 r600_update_vs_state(ctx
, shader
->gs_copy_shader
);
260 case PIPE_SHADER_VERTEX
:
261 export_shader
= key
.vs
.as_es
;
262 if (rctx
->b
.chip_class
>= EVERGREEN
) {
264 evergreen_update_ls_state(ctx
, shader
);
265 else if (key
.vs
.as_es
)
266 evergreen_update_es_state(ctx
, shader
);
268 evergreen_update_vs_state(ctx
, shader
);
271 r600_update_es_state(ctx
, shader
);
273 r600_update_vs_state(ctx
, shader
);
276 case PIPE_SHADER_FRAGMENT
:
277 if (rctx
->b
.chip_class
>= EVERGREEN
) {
278 evergreen_update_ps_state(ctx
, shader
);
280 r600_update_ps_state(ctx
, shader
);
283 case PIPE_SHADER_COMPUTE
:
284 evergreen_update_ls_state(ctx
, shader
);
293 r600_pipe_shader_destroy(ctx
, shader
);
297 void r600_pipe_shader_destroy(struct pipe_context
*ctx UNUSED
, struct r600_pipe_shader
*shader
)
299 r600_resource_reference(&shader
->bo
, NULL
);
300 r600_bytecode_clear(&shader
->shader
.bc
);
301 r600_release_command_buffer(&shader
->command_buffer
);
305 * tgsi -> r600 shader
307 struct r600_shader_tgsi_instruction
;
309 struct r600_shader_src
{
316 boolean kc_rel
; /* true if cache bank is indexed */
325 struct r600_shader_ctx
{
326 struct tgsi_shader_info info
;
327 struct tgsi_parse_context parse
;
328 const struct tgsi_token
*tokens
;
330 unsigned file_offset
[TGSI_FILE_COUNT
];
332 const struct r600_shader_tgsi_instruction
*inst_info
;
333 struct r600_bytecode
*bc
;
334 struct r600_shader
*shader
;
335 struct r600_shader_src src
[4];
338 uint32_t max_driver_temp_used
;
339 /* needed for evergreen interpolation */
340 struct eg_interp eg_interpolators
[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
341 /* evergreen/cayman also store sample mask in face register */
343 /* sample id is .w component stored in fixed point position register */
344 int fixed_pt_position_gpr
;
346 boolean clip_vertex_write
;
348 unsigned edgeflag_output
;
349 int cs_block_size_reg
;
350 int cs_grid_size_reg
;
351 bool cs_block_size_loaded
, cs_grid_size_loaded
;
353 int next_ring_offset
;
354 int gs_out_ring_offset
;
356 struct r600_shader
*gs_for_vs
;
357 int gs_export_gpr_tregs
[4];
358 int gs_rotated_input
[2];
359 const struct pipe_stream_output_info
*gs_stream_output_info
;
360 unsigned enabled_stream_buffers_mask
;
361 unsigned tess_input_info
; /* temp with tess input offsets */
362 unsigned tess_output_info
; /* temp with tess input offsets */
363 unsigned thread_id_gpr
; /* temp with thread id calculated for images */
364 bool thread_id_gpr_loaded
;
367 struct r600_shader_tgsi_instruction
{
369 int (*process
)(struct r600_shader_ctx
*ctx
);
372 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
);
373 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
374 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
375 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
);
376 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
);
377 static int tgsi_else(struct r600_shader_ctx
*ctx
);
378 static int tgsi_endif(struct r600_shader_ctx
*ctx
);
379 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
);
380 static int tgsi_endloop(struct r600_shader_ctx
*ctx
);
381 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
);
382 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
383 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
384 unsigned int dst_reg
);
385 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
386 const struct r600_shader_src
*shader_src
,
388 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
389 unsigned dst_reg
, unsigned mask
);
391 static int tgsi_last_instruction(unsigned writemask
)
395 for (i
= 0; i
< 4; i
++) {
396 if (writemask
& (1 << i
)) {
403 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
405 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
408 if (i
->Instruction
.NumDstRegs
> 1 && i
->Instruction
.Opcode
!= TGSI_OPCODE_DFRACEXP
) {
409 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
413 if (i
->Instruction
.Label
) {
414 R600_ERR("label unsupported\n");
418 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
419 if (i
->Src
[j
].Register
.Dimension
) {
420 switch (i
->Src
[j
].Register
.File
) {
421 case TGSI_FILE_CONSTANT
:
422 case TGSI_FILE_HW_ATOMIC
:
424 case TGSI_FILE_INPUT
:
425 if (ctx
->type
== PIPE_SHADER_GEOMETRY
||
426 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
427 ctx
->type
== PIPE_SHADER_TESS_EVAL
)
429 case TGSI_FILE_OUTPUT
:
430 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
433 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j
,
434 i
->Src
[j
].Register
.File
,
435 i
->Src
[j
].Register
.Dimension
);
440 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
441 if (i
->Dst
[j
].Register
.Dimension
) {
442 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
444 R600_ERR("unsupported dst (dimension)\n");
451 int eg_get_interpolator_index(unsigned interpolate
, unsigned location
)
453 if (interpolate
== TGSI_INTERPOLATE_COLOR
||
454 interpolate
== TGSI_INTERPOLATE_LINEAR
||
455 interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
457 int is_linear
= interpolate
== TGSI_INTERPOLATE_LINEAR
;
461 case TGSI_INTERPOLATE_LOC_CENTER
:
464 case TGSI_INTERPOLATE_LOC_CENTROID
:
467 case TGSI_INTERPOLATE_LOC_SAMPLE
:
472 return is_linear
* 3 + loc
;
478 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx
*ctx
,
481 int i
= eg_get_interpolator_index(
482 ctx
->shader
->input
[input
].interpolate
,
483 ctx
->shader
->input
[input
].interpolate_location
);
485 ctx
->shader
->input
[input
].ij_index
= ctx
->eg_interpolators
[i
].ij_index
;
488 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
491 struct r600_bytecode_alu alu
;
492 int gpr
= 0, base_chan
= 0;
493 int ij_index
= ctx
->shader
->input
[input
].ij_index
;
495 /* work out gpr and base_chan from index */
497 base_chan
= (2 * (ij_index
% 2)) + 1;
499 for (i
= 0; i
< 8; i
++) {
500 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
503 alu
.op
= ALU_OP2_INTERP_ZW
;
505 alu
.op
= ALU_OP2_INTERP_XY
;
507 if ((i
> 1) && (i
< 6)) {
508 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
512 alu
.dst
.chan
= i
% 4;
514 alu
.src
[0].sel
= gpr
;
515 alu
.src
[0].chan
= (base_chan
- (i
% 2));
517 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
519 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
522 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
529 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
532 struct r600_bytecode_alu alu
;
534 for (i
= 0; i
< 4; i
++) {
535 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
537 alu
.op
= ALU_OP1_INTERP_LOAD_P0
;
539 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
544 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
549 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
557 * Special export handling in shaders
559 * shader export ARRAY_BASE for EXPORT_POS:
562 * 62, 63 are clip distance vectors
564 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
565 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
566 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
567 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
568 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
569 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
570 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
571 * exclusive from render target index)
572 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
575 * shader export ARRAY_BASE for EXPORT_PIXEL:
577 * 61 computed Z vector
579 * The use of the values exported in the computed Z vector are controlled
580 * by DB_SHADER_CONTROL:
581 * Z_EXPORT_ENABLE - Z as a float in RED
582 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
583 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
584 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
585 * DB_SOURCE_FORMAT - export control restrictions
590 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
591 static int r600_spi_sid(struct r600_shader_io
* io
)
593 int index
, name
= io
->name
;
595 /* These params are handled differently, they don't need
596 * semantic indices, so we'll use 0 for them.
598 if (name
== TGSI_SEMANTIC_POSITION
||
599 name
== TGSI_SEMANTIC_PSIZE
||
600 name
== TGSI_SEMANTIC_EDGEFLAG
||
601 name
== TGSI_SEMANTIC_FACE
||
602 name
== TGSI_SEMANTIC_SAMPLEMASK
)
605 if (name
== TGSI_SEMANTIC_GENERIC
) {
606 /* For generic params simply use sid from tgsi */
609 /* For non-generic params - pack name and sid into 8 bits */
610 index
= 0x80 | (name
<<3) | (io
->sid
);
613 /* Make sure that all really used indices have nonzero value, so
614 * we can just compare it to 0 later instead of comparing the name
615 * with different values to detect special cases. */
622 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
623 int r600_get_lds_unique_index(unsigned semantic_name
, unsigned index
)
625 switch (semantic_name
) {
626 case TGSI_SEMANTIC_POSITION
:
628 case TGSI_SEMANTIC_PSIZE
:
630 case TGSI_SEMANTIC_CLIPDIST
:
633 case TGSI_SEMANTIC_GENERIC
:
635 return 4 + index
- 9;
637 /* same explanation as in the default statement,
638 * the only user hitting this is st/nine.
642 /* patch indices are completely separate and thus start from 0 */
643 case TGSI_SEMANTIC_TESSOUTER
:
645 case TGSI_SEMANTIC_TESSINNER
:
647 case TGSI_SEMANTIC_PATCH
:
651 /* Don't fail here. The result of this function is only used
652 * for LS, TCS, TES, and GS, where legacy GL semantics can't
653 * occur, but this function is called for all vertex shaders
654 * before it's known whether LS will be compiled or not.
660 /* turn input into interpolate on EG */
661 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
665 if (ctx
->shader
->input
[index
].spi_sid
) {
666 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
667 if (ctx
->shader
->input
[index
].interpolate
> 0) {
668 evergreen_interp_assign_ij_index(ctx
, index
);
669 r
= evergreen_interp_alu(ctx
, index
);
671 r
= evergreen_interp_flat(ctx
, index
);
677 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
679 struct r600_bytecode_alu alu
;
681 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
682 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
684 for (i
= 0; i
< 4; i
++) {
685 memset(&alu
, 0, sizeof(alu
));
686 alu
.op
= ALU_OP3_CNDGT
;
689 alu
.dst
.sel
= gpr_front
;
690 alu
.src
[0].sel
= ctx
->face_gpr
;
691 alu
.src
[1].sel
= gpr_front
;
692 alu
.src
[2].sel
= gpr_back
;
699 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
706 /* execute a single slot ALU calculation */
707 static int single_alu_op2(struct r600_shader_ctx
*ctx
, int op
,
708 int dst_sel
, int dst_chan
,
709 int src0_sel
, unsigned src0_chan_val
,
710 int src1_sel
, unsigned src1_chan_val
)
712 struct r600_bytecode_alu alu
;
715 if (ctx
->bc
->chip_class
== CAYMAN
&& op
== ALU_OP2_MULLO_INT
) {
716 for (i
= 0; i
< 4; i
++) {
717 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
719 alu
.src
[0].sel
= src0_sel
;
720 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
721 alu
.src
[0].value
= src0_chan_val
;
723 alu
.src
[0].chan
= src0_chan_val
;
724 alu
.src
[1].sel
= src1_sel
;
725 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
726 alu
.src
[1].value
= src1_chan_val
;
728 alu
.src
[1].chan
= src1_chan_val
;
729 alu
.dst
.sel
= dst_sel
;
731 alu
.dst
.write
= i
== dst_chan
;
733 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
740 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
742 alu
.src
[0].sel
= src0_sel
;
743 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
744 alu
.src
[0].value
= src0_chan_val
;
746 alu
.src
[0].chan
= src0_chan_val
;
747 alu
.src
[1].sel
= src1_sel
;
748 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
749 alu
.src
[1].value
= src1_chan_val
;
751 alu
.src
[1].chan
= src1_chan_val
;
752 alu
.dst
.sel
= dst_sel
;
753 alu
.dst
.chan
= dst_chan
;
756 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
762 /* execute a single slot ALU calculation */
763 static int single_alu_op3(struct r600_shader_ctx
*ctx
, int op
,
764 int dst_sel
, int dst_chan
,
765 int src0_sel
, unsigned src0_chan_val
,
766 int src1_sel
, unsigned src1_chan_val
,
767 int src2_sel
, unsigned src2_chan_val
)
769 struct r600_bytecode_alu alu
;
772 /* validate this for other ops */
773 assert(op
== ALU_OP3_MULADD_UINT24
|| op
== ALU_OP3_CNDE_INT
);
774 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
776 alu
.src
[0].sel
= src0_sel
;
777 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
778 alu
.src
[0].value
= src0_chan_val
;
780 alu
.src
[0].chan
= src0_chan_val
;
781 alu
.src
[1].sel
= src1_sel
;
782 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
783 alu
.src
[1].value
= src1_chan_val
;
785 alu
.src
[1].chan
= src1_chan_val
;
786 alu
.src
[2].sel
= src2_sel
;
787 if (src2_sel
== V_SQ_ALU_SRC_LITERAL
)
788 alu
.src
[2].value
= src2_chan_val
;
790 alu
.src
[2].chan
= src2_chan_val
;
791 alu
.dst
.sel
= dst_sel
;
792 alu
.dst
.chan
= dst_chan
;
795 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
801 /* put it in temp_reg.x */
802 static int get_lds_offset0(struct r600_shader_ctx
*ctx
,
804 int temp_reg
, bool is_patch_var
)
808 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
810 Dimension - patch0_offset (input_vals.z),
811 Non-dim - patch0_data_offset (input_vals.w)
813 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
815 ctx
->tess_output_info
, 0,
817 ctx
->tess_output_info
, is_patch_var
? 3 : 2);
823 static inline int get_address_file_reg(struct r600_shader_ctx
*ctx
, int index
)
825 return index
> 0 ? ctx
->bc
->index_reg
[index
- 1] : ctx
->bc
->ar_reg
;
828 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
830 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
833 static int vs_add_primid_output(struct r600_shader_ctx
*ctx
, int prim_id_sid
)
836 i
= ctx
->shader
->noutput
++;
837 ctx
->shader
->output
[i
].name
= TGSI_SEMANTIC_PRIMID
;
838 ctx
->shader
->output
[i
].sid
= 0;
839 ctx
->shader
->output
[i
].gpr
= 0;
840 ctx
->shader
->output
[i
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
841 ctx
->shader
->output
[i
].write_mask
= 0x4;
842 ctx
->shader
->output
[i
].spi_sid
= prim_id_sid
;
847 static int tgsi_barrier(struct r600_shader_ctx
*ctx
)
849 struct r600_bytecode_alu alu
;
852 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
853 alu
.op
= ctx
->inst_info
->op
;
856 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
862 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
864 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
865 int r
, i
, j
, count
= d
->Range
.Last
- d
->Range
.First
+ 1;
867 switch (d
->Declaration
.File
) {
868 case TGSI_FILE_INPUT
:
869 for (j
= 0; j
< count
; j
++) {
870 i
= ctx
->shader
->ninput
+ j
;
871 assert(i
< ARRAY_SIZE(ctx
->shader
->input
));
872 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
873 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
+ j
;
874 ctx
->shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
875 ctx
->shader
->input
[i
].interpolate_location
= d
->Interp
.Location
;
876 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
+ j
;
877 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
878 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
879 switch (ctx
->shader
->input
[i
].name
) {
880 case TGSI_SEMANTIC_FACE
:
881 if (ctx
->face_gpr
!= -1)
882 ctx
->shader
->input
[i
].gpr
= ctx
->face_gpr
; /* already allocated by allocate_system_value_inputs */
884 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
886 case TGSI_SEMANTIC_COLOR
:
889 case TGSI_SEMANTIC_POSITION
:
890 ctx
->fragcoord_input
= i
;
892 case TGSI_SEMANTIC_PRIMID
:
893 /* set this for now */
894 ctx
->shader
->gs_prim_id_input
= true;
895 ctx
->shader
->ps_prim_id_input
= i
;
898 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
899 if ((r
= evergreen_interp_input(ctx
, i
)))
902 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
903 /* FIXME probably skip inputs if they aren't passed in the ring */
904 ctx
->shader
->input
[i
].ring_offset
= ctx
->next_ring_offset
;
905 ctx
->next_ring_offset
+= 16;
906 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_PRIMID
)
907 ctx
->shader
->gs_prim_id_input
= true;
910 ctx
->shader
->ninput
+= count
;
912 case TGSI_FILE_OUTPUT
:
913 for (j
= 0; j
< count
; j
++) {
914 i
= ctx
->shader
->noutput
+ j
;
915 assert(i
< ARRAY_SIZE(ctx
->shader
->output
));
916 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
917 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
+ j
;
918 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
+ j
;
919 ctx
->shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
920 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
921 if (ctx
->type
== PIPE_SHADER_VERTEX
||
922 ctx
->type
== PIPE_SHADER_GEOMETRY
||
923 ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
924 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
925 switch (d
->Semantic
.Name
) {
926 case TGSI_SEMANTIC_CLIPDIST
:
928 case TGSI_SEMANTIC_PSIZE
:
929 ctx
->shader
->vs_out_misc_write
= 1;
930 ctx
->shader
->vs_out_point_size
= 1;
932 case TGSI_SEMANTIC_EDGEFLAG
:
933 ctx
->shader
->vs_out_misc_write
= 1;
934 ctx
->shader
->vs_out_edgeflag
= 1;
935 ctx
->edgeflag_output
= i
;
937 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
938 ctx
->shader
->vs_out_misc_write
= 1;
939 ctx
->shader
->vs_out_viewport
= 1;
941 case TGSI_SEMANTIC_LAYER
:
942 ctx
->shader
->vs_out_misc_write
= 1;
943 ctx
->shader
->vs_out_layer
= 1;
945 case TGSI_SEMANTIC_CLIPVERTEX
:
946 ctx
->clip_vertex_write
= TRUE
;
950 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
951 ctx
->gs_out_ring_offset
+= 16;
953 } else if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
954 switch (d
->Semantic
.Name
) {
955 case TGSI_SEMANTIC_COLOR
:
956 ctx
->shader
->nr_ps_max_color_exports
++;
961 ctx
->shader
->noutput
+= count
;
963 case TGSI_FILE_TEMPORARY
:
964 if (ctx
->info
.indirect_files
& (1 << TGSI_FILE_TEMPORARY
)) {
965 if (d
->Array
.ArrayID
) {
966 r600_add_gpr_array(ctx
->shader
,
967 ctx
->file_offset
[TGSI_FILE_TEMPORARY
] +
969 d
->Range
.Last
- d
->Range
.First
+ 1, 0x0F);
974 case TGSI_FILE_CONSTANT
:
975 case TGSI_FILE_SAMPLER
:
976 case TGSI_FILE_SAMPLER_VIEW
:
977 case TGSI_FILE_ADDRESS
:
978 case TGSI_FILE_BUFFER
:
979 case TGSI_FILE_IMAGE
:
980 case TGSI_FILE_MEMORY
:
983 case TGSI_FILE_HW_ATOMIC
:
984 i
= ctx
->shader
->nhwatomic_ranges
;
985 ctx
->shader
->atomics
[i
].start
= d
->Range
.First
;
986 ctx
->shader
->atomics
[i
].end
= d
->Range
.Last
;
987 ctx
->shader
->atomics
[i
].hw_idx
= ctx
->shader
->atomic_base
+ ctx
->shader
->nhwatomic
;
988 ctx
->shader
->atomics
[i
].array_id
= d
->Array
.ArrayID
;
989 ctx
->shader
->atomics
[i
].buffer_id
= d
->Dim
.Index2D
;
990 ctx
->shader
->nhwatomic_ranges
++;
991 ctx
->shader
->nhwatomic
+= count
;
994 case TGSI_FILE_SYSTEM_VALUE
:
995 if (d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEMASK
||
996 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEID
||
997 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEPOS
) {
998 break; /* Already handled from allocate_system_value_inputs */
999 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
1001 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
1003 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INVOCATIONID
)
1005 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
||
1006 d
->Semantic
.Name
== TGSI_SEMANTIC_TESSOUTER
) {
1007 int param
= r600_get_lds_unique_index(d
->Semantic
.Name
, 0);
1008 int dreg
= d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
? 3 : 2;
1009 unsigned temp_reg
= r600_get_temp(ctx
);
1011 r
= get_lds_offset0(ctx
, 2, temp_reg
, true);
1015 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1018 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1022 do_lds_fetch_values(ctx
, temp_reg
, dreg
, 0xf);
1024 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSCOORD
) {
1028 for (i
= 0; i
< 2; i
++) {
1029 struct r600_bytecode_alu alu
;
1030 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1031 alu
.op
= ALU_OP1_MOV
;
1033 alu
.src
[0].chan
= 0 + i
;
1035 alu
.dst
.chan
= 0 + i
;
1037 alu
.last
= (i
== 1) ? 1 : 0;
1038 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1041 /* ADD r1.z, 1.0f, -r0.x */
1042 struct r600_bytecode_alu alu
;
1043 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1044 alu
.op
= ALU_OP2_ADD
;
1045 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1047 alu
.src
[1].chan
= 0;
1053 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1056 /* ADD r1.z, r1.z, -r1.y */
1057 alu
.op
= ALU_OP2_ADD
;
1059 alu
.src
[0].chan
= 2;
1061 alu
.src
[1].chan
= 1;
1067 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1073 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
1079 static int allocate_system_value_inputs(struct r600_shader_ctx
*ctx
, int gpr_offset
)
1081 struct tgsi_parse_context parse
;
1085 unsigned name
, alternate_name
;
1087 { false, &ctx
->face_gpr
, TGSI_SEMANTIC_SAMPLEMASK
, ~0u }, /* lives in Front Face GPR.z */
1089 { false, &ctx
->fixed_pt_position_gpr
, TGSI_SEMANTIC_SAMPLEID
, TGSI_SEMANTIC_SAMPLEPOS
} /* SAMPLEID is in Fixed Point Position GPR.w */
1094 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1098 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1099 while (!tgsi_parse_end_of_tokens(&parse
)) {
1100 tgsi_parse_token(&parse
);
1102 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1103 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1104 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1105 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1106 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1108 int interpolate
, location
, k
;
1110 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1111 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1112 inputs
[1].enabled
= true; /* needs SAMPLEID */
1113 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1114 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1115 /* Needs sample positions, currently those are always available */
1117 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1120 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1121 k
= eg_get_interpolator_index(interpolate
, location
);
1123 ctx
->eg_interpolators
[k
].enabled
= true;
1125 } else if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_DECLARATION
) {
1126 struct tgsi_full_declaration
*d
= &parse
.FullToken
.FullDeclaration
;
1127 if (d
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1128 for (k
= 0; k
< ARRAY_SIZE(inputs
); k
++) {
1129 if (d
->Semantic
.Name
== inputs
[k
].name
||
1130 d
->Semantic
.Name
== inputs
[k
].alternate_name
) {
1131 inputs
[k
].enabled
= true;
1138 tgsi_parse_free(&parse
);
1140 for (i
= 0; i
< ARRAY_SIZE(inputs
); i
++) {
1141 boolean enabled
= inputs
[i
].enabled
;
1142 int *reg
= inputs
[i
].reg
;
1143 unsigned name
= inputs
[i
].name
;
1146 int gpr
= gpr_offset
+ num_regs
++;
1147 ctx
->shader
->nsys_inputs
++;
1149 // add to inputs, allocate a gpr
1150 k
= ctx
->shader
->ninput
++;
1151 ctx
->shader
->input
[k
].name
= name
;
1152 ctx
->shader
->input
[k
].sid
= 0;
1153 ctx
->shader
->input
[k
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1154 ctx
->shader
->input
[k
].interpolate_location
= TGSI_INTERPOLATE_LOC_CENTER
;
1155 *reg
= ctx
->shader
->input
[k
].gpr
= gpr
;
1159 return gpr_offset
+ num_regs
;
1163 * for evergreen we need to scan the shader to find the number of GPRs we need to
1164 * reserve for interpolation and system values
1166 * we need to know if we are going to emit
1167 * any sample or centroid inputs
1168 * if perspective and linear are required
1170 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
1174 struct tgsi_parse_context parse
;
1176 memset(&ctx
->eg_interpolators
, 0, sizeof(ctx
->eg_interpolators
));
1178 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
1180 /* skip position/face/mask/sampleid */
1181 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
1182 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
||
1183 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEMASK
||
1184 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEID
)
1187 k
= eg_get_interpolator_index(
1188 ctx
->info
.input_interpolate
[i
],
1189 ctx
->info
.input_interpolate_loc
[i
]);
1191 ctx
->eg_interpolators
[k
].enabled
= TRUE
;
1194 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1198 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1199 while (!tgsi_parse_end_of_tokens(&parse
)) {
1200 tgsi_parse_token(&parse
);
1202 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1203 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1204 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1205 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1206 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1208 int interpolate
, location
, k
;
1210 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1211 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1212 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1213 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1215 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1218 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1219 k
= eg_get_interpolator_index(interpolate
, location
);
1221 ctx
->eg_interpolators
[k
].enabled
= true;
1226 tgsi_parse_free(&parse
);
1228 /* assign gpr to each interpolator according to priority */
1230 for (i
= 0; i
< ARRAY_SIZE(ctx
->eg_interpolators
); i
++) {
1231 if (ctx
->eg_interpolators
[i
].enabled
) {
1232 ctx
->eg_interpolators
[i
].ij_index
= num_baryc
;
1237 /* XXX PULL MODEL and LINE STIPPLE */
1239 num_baryc
= (num_baryc
+ 1) >> 1;
1240 return allocate_system_value_inputs(ctx
, num_baryc
);
1243 /* sample_id_sel == NULL means fetch for current sample */
1244 static int load_sample_position(struct r600_shader_ctx
*ctx
, struct r600_shader_src
*sample_id
, int chan_sel
)
1246 struct r600_bytecode_vtx vtx
;
1249 assert(ctx
->fixed_pt_position_gpr
!= -1);
1251 t1
= r600_get_temp(ctx
);
1253 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
1254 vtx
.op
= FETCH_OP_VFETCH
;
1255 vtx
.buffer_id
= R600_BUFFER_INFO_CONST_BUFFER
;
1256 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1257 if (sample_id
== NULL
) {
1258 vtx
.src_gpr
= ctx
->fixed_pt_position_gpr
; // SAMPLEID is in .w;
1262 struct r600_bytecode_alu alu
;
1264 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1265 alu
.op
= ALU_OP1_MOV
;
1266 r600_bytecode_src(&alu
.src
[0], sample_id
, chan_sel
);
1270 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1277 vtx
.mega_fetch_count
= 16;
1283 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1284 vtx
.num_format_all
= 2;
1285 vtx
.format_comp_all
= 1;
1286 vtx
.use_const_fields
= 0;
1288 vtx
.endian
= r600_endian_swap(32);
1289 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
1291 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
1298 static int load_block_grid_size(struct r600_shader_ctx
*ctx
, bool load_block
)
1300 struct r600_bytecode_vtx vtx
;
1303 if (ctx
->cs_block_size_loaded
)
1304 return ctx
->cs_block_size_reg
;
1305 if (ctx
->cs_grid_size_loaded
)
1306 return ctx
->cs_grid_size_reg
;
1308 t1
= load_block
? ctx
->cs_block_size_reg
: ctx
->cs_grid_size_reg
;
1309 struct r600_bytecode_alu alu
;
1310 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1311 alu
.op
= ALU_OP1_MOV
;
1312 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1316 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1320 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
1321 vtx
.op
= FETCH_OP_VFETCH
;
1322 vtx
.buffer_id
= R600_BUFFER_INFO_CONST_BUFFER
;
1323 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1327 vtx
.mega_fetch_count
= 16;
1333 vtx
.data_format
= FMT_32_32_32_32
;
1334 vtx
.num_format_all
= 1;
1335 vtx
.format_comp_all
= 0;
1336 vtx
.use_const_fields
= 0;
1337 vtx
.offset
= load_block
? 0 : 16; // first element is size of buffer
1338 vtx
.endian
= r600_endian_swap(32);
1339 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
1341 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
1346 ctx
->cs_block_size_loaded
= true;
1348 ctx
->cs_grid_size_loaded
= true;
1352 static void tgsi_src(struct r600_shader_ctx
*ctx
,
1353 const struct tgsi_full_src_register
*tgsi_src
,
1354 struct r600_shader_src
*r600_src
)
1356 memset(r600_src
, 0, sizeof(*r600_src
));
1357 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
1358 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
1359 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
1360 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
1361 r600_src
->neg
= tgsi_src
->Register
.Negate
;
1362 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
1364 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
1366 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
1367 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
1368 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
1370 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
1371 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
, r600_src
->abs
);
1372 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
1375 index
= tgsi_src
->Register
.Index
;
1376 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
1377 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
1378 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1379 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEMASK
) {
1380 r600_src
->swizzle
[0] = 2; // Z value
1381 r600_src
->swizzle
[1] = 2;
1382 r600_src
->swizzle
[2] = 2;
1383 r600_src
->swizzle
[3] = 2;
1384 r600_src
->sel
= ctx
->face_gpr
;
1385 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEID
) {
1386 r600_src
->swizzle
[0] = 3; // W value
1387 r600_src
->swizzle
[1] = 3;
1388 r600_src
->swizzle
[2] = 3;
1389 r600_src
->swizzle
[3] = 3;
1390 r600_src
->sel
= ctx
->fixed_pt_position_gpr
;
1391 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEPOS
) {
1392 r600_src
->swizzle
[0] = 0;
1393 r600_src
->swizzle
[1] = 1;
1394 r600_src
->swizzle
[2] = 4;
1395 r600_src
->swizzle
[3] = 4;
1396 r600_src
->sel
= load_sample_position(ctx
, NULL
, -1);
1397 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
1398 r600_src
->swizzle
[0] = 3;
1399 r600_src
->swizzle
[1] = 3;
1400 r600_src
->swizzle
[2] = 3;
1401 r600_src
->swizzle
[3] = 3;
1403 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
1404 r600_src
->swizzle
[0] = 0;
1405 r600_src
->swizzle
[1] = 0;
1406 r600_src
->swizzle
[2] = 0;
1407 r600_src
->swizzle
[3] = 0;
1409 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_THREAD_ID
) {
1411 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_BLOCK_ID
) {
1413 } else if (ctx
->type
!= PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1414 r600_src
->swizzle
[0] = 3;
1415 r600_src
->swizzle
[1] = 3;
1416 r600_src
->swizzle
[2] = 3;
1417 r600_src
->swizzle
[3] = 3;
1419 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1420 r600_src
->swizzle
[0] = 2;
1421 r600_src
->swizzle
[1] = 2;
1422 r600_src
->swizzle
[2] = 2;
1423 r600_src
->swizzle
[3] = 2;
1425 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSCOORD
) {
1427 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSINNER
) {
1429 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSOUTER
) {
1431 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTICESIN
) {
1432 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
1433 r600_src
->sel
= ctx
->tess_input_info
;
1434 r600_src
->swizzle
[0] = 2;
1435 r600_src
->swizzle
[1] = 2;
1436 r600_src
->swizzle
[2] = 2;
1437 r600_src
->swizzle
[3] = 2;
1439 r600_src
->sel
= ctx
->tess_input_info
;
1440 r600_src
->swizzle
[0] = 3;
1441 r600_src
->swizzle
[1] = 3;
1442 r600_src
->swizzle
[2] = 3;
1443 r600_src
->swizzle
[3] = 3;
1445 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1447 r600_src
->swizzle
[0] = 0;
1448 r600_src
->swizzle
[1] = 0;
1449 r600_src
->swizzle
[2] = 0;
1450 r600_src
->swizzle
[3] = 0;
1451 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1453 r600_src
->swizzle
[0] = 3;
1454 r600_src
->swizzle
[1] = 3;
1455 r600_src
->swizzle
[2] = 3;
1456 r600_src
->swizzle
[3] = 3;
1457 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_GRID_SIZE
) {
1458 r600_src
->sel
= load_block_grid_size(ctx
, false);
1459 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_BLOCK_SIZE
) {
1460 r600_src
->sel
= load_block_grid_size(ctx
, true);
1463 if (tgsi_src
->Register
.Indirect
)
1464 r600_src
->rel
= V_SQ_REL_RELATIVE
;
1465 r600_src
->sel
= tgsi_src
->Register
.Index
;
1466 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
1468 if (tgsi_src
->Register
.File
== TGSI_FILE_CONSTANT
) {
1469 if (tgsi_src
->Register
.Dimension
) {
1470 r600_src
->kc_bank
= tgsi_src
->Dimension
.Index
;
1471 if (tgsi_src
->Dimension
.Indirect
) {
1472 r600_src
->kc_rel
= 1;
1478 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
1479 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
1480 unsigned int dst_reg
)
1482 struct r600_bytecode_vtx vtx
;
1483 unsigned int ar_reg
;
1487 struct r600_bytecode_alu alu
;
1489 memset(&alu
, 0, sizeof(alu
));
1491 alu
.op
= ALU_OP2_ADD_INT
;
1492 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
1493 alu
.src
[0].chan
= ar_chan
;
1495 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1496 alu
.src
[1].value
= offset
;
1498 alu
.dst
.sel
= dst_reg
;
1499 alu
.dst
.chan
= ar_chan
;
1503 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1508 ar_reg
= ctx
->bc
->ar_reg
;
1511 memset(&vtx
, 0, sizeof(vtx
));
1512 vtx
.buffer_id
= cb_idx
;
1513 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1514 vtx
.src_gpr
= ar_reg
;
1515 vtx
.src_sel_x
= ar_chan
;
1516 vtx
.mega_fetch_count
= 16;
1517 vtx
.dst_gpr
= dst_reg
;
1518 vtx
.dst_sel_x
= 0; /* SEL_X */
1519 vtx
.dst_sel_y
= 1; /* SEL_Y */
1520 vtx
.dst_sel_z
= 2; /* SEL_Z */
1521 vtx
.dst_sel_w
= 3; /* SEL_W */
1522 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1523 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
1524 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
1525 vtx
.endian
= r600_endian_swap(32);
1526 vtx
.buffer_index_mode
= cb_rel
; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1528 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1534 static int fetch_gs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1536 struct r600_bytecode_vtx vtx
;
1538 unsigned index
= src
->Register
.Index
;
1539 unsigned vtx_id
= src
->Dimension
.Index
;
1540 int offset_reg
= ctx
->gs_rotated_input
[vtx_id
/ 3];
1541 int offset_chan
= vtx_id
% 3;
1544 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1545 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1547 if (offset_reg
== ctx
->gs_rotated_input
[0] && offset_chan
== 2)
1550 if (src
->Dimension
.Indirect
|| src
->Register
.Indirect
)
1551 t2
= r600_get_temp(ctx
);
1553 if (src
->Dimension
.Indirect
) {
1555 struct r600_bytecode_alu alu
;
1558 addr_reg
= get_address_file_reg(ctx
, src
->DimIndirect
.Index
);
1559 if (src
->DimIndirect
.Index
> 0) {
1560 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
1568 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1569 at least this is what fglrx seems to do. */
1570 for (i
= 0; i
< 3; i
++) {
1571 treg
[i
] = r600_get_temp(ctx
);
1573 r600_add_gpr_array(ctx
->shader
, treg
[0], 3, 0x0F);
1575 for (i
= 0; i
< 3; i
++) {
1576 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1577 alu
.op
= ALU_OP1_MOV
;
1578 alu
.src
[0].sel
= ctx
->gs_rotated_input
[0];
1579 alu
.src
[0].chan
= i
== 2 ? 3 : i
;
1580 alu
.dst
.sel
= treg
[i
];
1584 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1588 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1589 alu
.op
= ALU_OP1_MOV
;
1590 alu
.src
[0].sel
= treg
[0];
1595 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1602 if (src
->Register
.Indirect
) {
1604 unsigned first
= ctx
->info
.input_array_first
[src
->Indirect
.ArrayID
];
1606 addr_reg
= get_address_file_reg(ctx
, src
->Indirect
.Index
);
1608 /* pull the value from index_reg */
1609 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1612 V_SQ_ALU_SRC_LITERAL
, first
);
1615 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1618 V_SQ_ALU_SRC_LITERAL
, 4,
1619 offset_reg
, offset_chan
);
1624 index
= src
->Register
.Index
- first
;
1627 memset(&vtx
, 0, sizeof(vtx
));
1628 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
1629 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1630 vtx
.src_gpr
= offset_reg
;
1631 vtx
.src_sel_x
= offset_chan
;
1632 vtx
.offset
= index
* 16; /*bytes*/
1633 vtx
.mega_fetch_count
= 16;
1634 vtx
.dst_gpr
= dst_reg
;
1635 vtx
.dst_sel_x
= 0; /* SEL_X */
1636 vtx
.dst_sel_y
= 1; /* SEL_Y */
1637 vtx
.dst_sel_z
= 2; /* SEL_Z */
1638 vtx
.dst_sel_w
= 3; /* SEL_W */
1639 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1640 vtx
.use_const_fields
= 1;
1642 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1645 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1651 static int tgsi_split_gs_inputs(struct r600_shader_ctx
*ctx
)
1653 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1656 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1657 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1659 if (src
->Register
.File
== TGSI_FILE_INPUT
) {
1660 if (ctx
->shader
->input
[src
->Register
.Index
].name
== TGSI_SEMANTIC_PRIMID
) {
1661 /* primitive id is in R0.z */
1662 ctx
->src
[i
].sel
= 0;
1663 ctx
->src
[i
].swizzle
[0] = 2;
1666 if (src
->Register
.File
== TGSI_FILE_INPUT
&& src
->Register
.Dimension
) {
1667 int treg
= r600_get_temp(ctx
);
1669 fetch_gs_input(ctx
, src
, treg
);
1670 ctx
->src
[i
].sel
= treg
;
1671 ctx
->src
[i
].rel
= 0;
1678 /* Tessellation shaders pass outputs to the next shader using LDS.
1680 * LS outputs = TCS(HS) inputs
1681 * TCS(HS) outputs = TES(DS) inputs
1683 * The LDS layout is:
1684 * - TCS inputs for patch 0
1685 * - TCS inputs for patch 1
1686 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1688 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1689 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1690 * - TCS outputs for patch 1
1691 * - Per-patch TCS outputs for patch 1
1692 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1693 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1696 * All three shaders VS(LS), TCS, TES share the same LDS space.
1698 /* this will return with the dw address in temp_reg.x */
1699 static int r600_get_byte_address(struct r600_shader_ctx
*ctx
, int temp_reg
,
1700 const struct tgsi_full_dst_register
*dst
,
1701 const struct tgsi_full_src_register
*src
,
1702 int stride_bytes_reg
, int stride_bytes_chan
)
1704 struct tgsi_full_dst_register reg
;
1705 ubyte
*name
, *index
, *array_first
;
1708 struct tgsi_shader_info
*info
= &ctx
->info
;
1709 /* Set the register description. The address computation is the same
1710 * for sources and destinations. */
1712 reg
.Register
.File
= src
->Register
.File
;
1713 reg
.Register
.Index
= src
->Register
.Index
;
1714 reg
.Register
.Indirect
= src
->Register
.Indirect
;
1715 reg
.Register
.Dimension
= src
->Register
.Dimension
;
1716 reg
.Indirect
= src
->Indirect
;
1717 reg
.Dimension
= src
->Dimension
;
1718 reg
.DimIndirect
= src
->DimIndirect
;
1722 /* If the register is 2-dimensional (e.g. an array of vertices
1723 * in a primitive), calculate the base address of the vertex. */
1724 if (reg
.Register
.Dimension
) {
1726 if (reg
.Dimension
.Indirect
) {
1728 assert (reg
.DimIndirect
.File
== TGSI_FILE_ADDRESS
);
1730 addr_reg
= get_address_file_reg(ctx
, reg
.DimIndirect
.Index
);
1731 /* pull the value from index_reg */
1735 sel
= V_SQ_ALU_SRC_LITERAL
;
1736 chan
= reg
.Dimension
.Index
;
1739 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1741 stride_bytes_reg
, stride_bytes_chan
,
1748 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1749 name
= info
->input_semantic_name
;
1750 index
= info
->input_semantic_index
;
1751 array_first
= info
->input_array_first
;
1752 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1753 name
= info
->output_semantic_name
;
1754 index
= info
->output_semantic_index
;
1755 array_first
= info
->output_array_first
;
1760 if (reg
.Register
.Indirect
) {
1763 /* Add the relative address of the element. */
1764 if (reg
.Indirect
.ArrayID
)
1765 first
= array_first
[reg
.Indirect
.ArrayID
];
1767 first
= reg
.Register
.Index
;
1769 addr_reg
= get_address_file_reg(ctx
, reg
.Indirect
.Index
);
1771 /* pull the value from index_reg */
1772 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1774 V_SQ_ALU_SRC_LITERAL
, 16,
1780 param
= r600_get_lds_unique_index(name
[first
],
1784 param
= r600_get_lds_unique_index(name
[reg
.Register
.Index
],
1785 index
[reg
.Register
.Index
]);
1788 /* add to base_addr - passed in temp_reg.x */
1790 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1793 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1801 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
1802 unsigned dst_reg
, unsigned mask
)
1804 struct r600_bytecode_alu alu
;
1807 if ((ctx
->bc
->cf_last
->ndw
>>1) >= 0x60)
1808 ctx
->bc
->force_add_cf
= 1;
1810 lasti
= tgsi_last_instruction(mask
);
1811 for (i
= 1; i
<= lasti
; i
++) {
1812 if (!(mask
& (1 << i
)))
1815 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1818 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
1822 for (i
= 0; i
<= lasti
; i
++) {
1823 if (!(mask
& (1 << i
)))
1826 /* emit an LDS_READ_RET */
1827 memset(&alu
, 0, sizeof(alu
));
1828 alu
.op
= LDS_OP1_LDS_READ_RET
;
1829 alu
.src
[0].sel
= temp_reg
;
1830 alu
.src
[0].chan
= i
;
1831 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1832 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
1834 alu
.is_lds_idx_op
= true;
1836 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1840 for (i
= 0; i
<= lasti
; i
++) {
1841 if (!(mask
& (1 << i
)))
1844 /* then read from LDS_OQ_A_POP */
1845 memset(&alu
, 0, sizeof(alu
));
1847 alu
.op
= ALU_OP1_MOV
;
1848 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
;
1849 alu
.src
[0].chan
= 0;
1850 alu
.dst
.sel
= dst_reg
;
1854 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1861 static int fetch_mask(struct tgsi_src_register
*reg
)
1864 mask
|= 1 << reg
->SwizzleX
;
1865 mask
|= 1 << reg
->SwizzleY
;
1866 mask
|= 1 << reg
->SwizzleZ
;
1867 mask
|= 1 << reg
->SwizzleW
;
1871 static int fetch_tes_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1874 unsigned temp_reg
= r600_get_temp(ctx
);
1876 r
= get_lds_offset0(ctx
, 2, temp_reg
,
1877 src
->Register
.Dimension
? false : true);
1881 /* the base address is now in temp.x */
1882 r
= r600_get_byte_address(ctx
, temp_reg
,
1883 NULL
, src
, ctx
->tess_output_info
, 1);
1887 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
, fetch_mask(&src
->Register
));
1893 static int fetch_tcs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1896 unsigned temp_reg
= r600_get_temp(ctx
);
1898 /* t.x = ips * r0.y */
1899 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
1901 ctx
->tess_input_info
, 0,
1907 /* the base address is now in temp.x */
1908 r
= r600_get_byte_address(ctx
, temp_reg
,
1909 NULL
, src
, ctx
->tess_input_info
, 1);
1913 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
, fetch_mask(&src
->Register
));
1919 static int fetch_tcs_output(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1922 unsigned temp_reg
= r600_get_temp(ctx
);
1924 r
= get_lds_offset0(ctx
, 1, temp_reg
,
1925 src
->Register
.Dimension
? false : true);
1928 /* the base address is now in temp.x */
1929 r
= r600_get_byte_address(ctx
, temp_reg
,
1931 ctx
->tess_output_info
, 1);
1935 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
, fetch_mask(&src
->Register
));
1941 static int tgsi_split_lds_inputs(struct r600_shader_ctx
*ctx
)
1943 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1946 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1947 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1949 if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1950 int treg
= r600_get_temp(ctx
);
1951 fetch_tes_input(ctx
, src
, treg
);
1952 ctx
->src
[i
].sel
= treg
;
1953 ctx
->src
[i
].rel
= 0;
1955 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1956 int treg
= r600_get_temp(ctx
);
1957 fetch_tcs_input(ctx
, src
, treg
);
1958 ctx
->src
[i
].sel
= treg
;
1959 ctx
->src
[i
].rel
= 0;
1961 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_OUTPUT
) {
1962 int treg
= r600_get_temp(ctx
);
1963 fetch_tcs_output(ctx
, src
, treg
);
1964 ctx
->src
[i
].sel
= treg
;
1965 ctx
->src
[i
].rel
= 0;
1971 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
1973 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1974 struct r600_bytecode_alu alu
;
1975 int i
, j
, k
, nconst
, r
;
1977 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1978 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
1981 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
1983 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1984 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
1988 if (ctx
->src
[i
].rel
) {
1989 int chan
= inst
->Src
[i
].Indirect
.Swizzle
;
1990 int treg
= r600_get_temp(ctx
);
1991 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].kc_bank
, ctx
->src
[i
].kc_rel
, ctx
->src
[i
].sel
- 512, chan
, treg
)))
1994 ctx
->src
[i
].kc_bank
= 0;
1995 ctx
->src
[i
].kc_rel
= 0;
1996 ctx
->src
[i
].sel
= treg
;
1997 ctx
->src
[i
].rel
= 0;
2000 int treg
= r600_get_temp(ctx
);
2001 for (k
= 0; k
< 4; k
++) {
2002 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2003 alu
.op
= ALU_OP1_MOV
;
2004 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
2005 alu
.src
[0].chan
= k
;
2006 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
2007 alu
.src
[0].kc_bank
= ctx
->src
[i
].kc_bank
;
2008 alu
.src
[0].kc_rel
= ctx
->src
[i
].kc_rel
;
2014 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2018 ctx
->src
[i
].sel
= treg
;
2026 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
2027 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
2029 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2030 struct r600_bytecode_alu alu
;
2031 int i
, j
, k
, nliteral
, r
;
2033 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2034 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
2038 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2039 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
2040 int treg
= r600_get_temp(ctx
);
2041 for (k
= 0; k
< 4; k
++) {
2042 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2043 alu
.op
= ALU_OP1_MOV
;
2044 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
2045 alu
.src
[0].chan
= k
;
2046 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
2052 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2056 ctx
->src
[i
].sel
= treg
;
2063 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
2065 int i
, r
, count
= ctx
->shader
->ninput
;
2067 for (i
= 0; i
< count
; i
++) {
2068 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
2069 r
= select_twoside_color(ctx
, i
, ctx
->shader
->input
[i
].back_color_input
);
2077 static int emit_streamout(struct r600_shader_ctx
*ctx
, struct pipe_stream_output_info
*so
,
2078 int stream
, unsigned *stream_item_size UNUSED
)
2080 unsigned so_gpr
[PIPE_MAX_SHADER_OUTPUTS
];
2081 unsigned start_comp
[PIPE_MAX_SHADER_OUTPUTS
];
2085 /* Sanity checking. */
2086 if (so
->num_outputs
> PIPE_MAX_SO_OUTPUTS
) {
2087 R600_ERR("Too many stream outputs: %d\n", so
->num_outputs
);
2091 for (i
= 0; i
< so
->num_outputs
; i
++) {
2092 if (so
->output
[i
].output_buffer
>= 4) {
2093 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2094 so
->output
[i
].output_buffer
);
2100 /* Initialize locations where the outputs are stored. */
2101 for (i
= 0; i
< so
->num_outputs
; i
++) {
2103 so_gpr
[i
] = ctx
->shader
->output
[so
->output
[i
].register_index
].gpr
;
2104 start_comp
[i
] = so
->output
[i
].start_component
;
2105 /* Lower outputs with dst_offset < start_component.
2107 * We can only output 4D vectors with a write mask, e.g. we can
2108 * only output the W component at offset 3, etc. If we want
2109 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2110 * to move it to X and output X. */
2111 if (so
->output
[i
].dst_offset
< so
->output
[i
].start_component
) {
2112 unsigned tmp
= r600_get_temp(ctx
);
2114 for (j
= 0; j
< so
->output
[i
].num_components
; j
++) {
2115 struct r600_bytecode_alu alu
;
2116 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2117 alu
.op
= ALU_OP1_MOV
;
2118 alu
.src
[0].sel
= so_gpr
[i
];
2119 alu
.src
[0].chan
= so
->output
[i
].start_component
+ j
;
2124 if (j
== so
->output
[i
].num_components
- 1)
2126 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2135 /* Write outputs to buffers. */
2136 for (i
= 0; i
< so
->num_outputs
; i
++) {
2137 struct r600_bytecode_output output
;
2139 if (stream
!= -1 && stream
!= so
->output
[i
].output_buffer
)
2142 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2143 output
.gpr
= so_gpr
[i
];
2144 output
.elem_size
= so
->output
[i
].num_components
- 1;
2145 if (output
.elem_size
== 2)
2146 output
.elem_size
= 3; // 3 not supported, write 4 with junk at end
2147 output
.array_base
= so
->output
[i
].dst_offset
- start_comp
[i
];
2148 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2149 output
.burst_count
= 1;
2150 /* array_size is an upper limit for the burst_count
2151 * with MEM_STREAM instructions */
2152 output
.array_size
= 0xFFF;
2153 output
.comp_mask
= ((1 << so
->output
[i
].num_components
) - 1) << start_comp
[i
];
2155 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
2156 switch (so
->output
[i
].output_buffer
) {
2158 output
.op
= CF_OP_MEM_STREAM0_BUF0
;
2161 output
.op
= CF_OP_MEM_STREAM0_BUF1
;
2164 output
.op
= CF_OP_MEM_STREAM0_BUF2
;
2167 output
.op
= CF_OP_MEM_STREAM0_BUF3
;
2170 output
.op
+= so
->output
[i
].stream
* 4;
2171 assert(output
.op
>= CF_OP_MEM_STREAM0_BUF0
&& output
.op
<= CF_OP_MEM_STREAM3_BUF3
);
2172 ctx
->enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << so
->output
[i
].stream
* 4;
2174 switch (so
->output
[i
].output_buffer
) {
2176 output
.op
= CF_OP_MEM_STREAM0
;
2179 output
.op
= CF_OP_MEM_STREAM1
;
2182 output
.op
= CF_OP_MEM_STREAM2
;
2185 output
.op
= CF_OP_MEM_STREAM3
;
2188 ctx
->enabled_stream_buffers_mask
|= 1 << so
->output
[i
].output_buffer
;
2190 r
= r600_bytecode_add_output(ctx
->bc
, &output
);
2199 static void convert_edgeflag_to_int(struct r600_shader_ctx
*ctx
)
2201 struct r600_bytecode_alu alu
;
2204 if (!ctx
->shader
->vs_out_edgeflag
)
2207 reg
= ctx
->shader
->output
[ctx
->edgeflag_output
].gpr
;
2209 /* clamp(x, 0, 1) */
2210 memset(&alu
, 0, sizeof(alu
));
2211 alu
.op
= ALU_OP1_MOV
;
2212 alu
.src
[0].sel
= reg
;
2217 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2219 memset(&alu
, 0, sizeof(alu
));
2220 alu
.op
= ALU_OP1_FLT_TO_INT
;
2221 alu
.src
[0].sel
= reg
;
2225 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2228 static int generate_gs_copy_shader(struct r600_context
*rctx
,
2229 struct r600_pipe_shader
*gs
,
2230 struct pipe_stream_output_info
*so
)
2232 struct r600_shader_ctx ctx
= {};
2233 struct r600_shader
*gs_shader
= &gs
->shader
;
2234 struct r600_pipe_shader
*cshader
;
2235 unsigned ocnt
= gs_shader
->noutput
;
2236 struct r600_bytecode_alu alu
;
2237 struct r600_bytecode_vtx vtx
;
2238 struct r600_bytecode_output output
;
2239 struct r600_bytecode_cf
*cf_jump
, *cf_pop
,
2240 *last_exp_pos
= NULL
, *last_exp_param
= NULL
;
2241 int next_clip_pos
= 61, next_param
= 0;
2244 bool only_ring_0
= true;
2245 cshader
= calloc(1, sizeof(struct r600_pipe_shader
));
2249 memcpy(cshader
->shader
.output
, gs_shader
->output
, ocnt
*
2250 sizeof(struct r600_shader_io
));
2252 cshader
->shader
.noutput
= ocnt
;
2254 ctx
.shader
= &cshader
->shader
;
2255 ctx
.bc
= &ctx
.shader
->bc
;
2256 ctx
.type
= ctx
.bc
->type
= PIPE_SHADER_VERTEX
;
2258 r600_bytecode_init(ctx
.bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2259 rctx
->screen
->has_compressed_msaa_texturing
);
2261 ctx
.bc
->isa
= rctx
->isa
;
2264 memset(cshader
->shader
.ring_item_sizes
, 0, sizeof(cshader
->shader
.ring_item_sizes
));
2266 /* R0.x = R0.x & 0x3fffffff */
2267 memset(&alu
, 0, sizeof(alu
));
2268 alu
.op
= ALU_OP2_AND_INT
;
2269 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2270 alu
.src
[1].value
= 0x3fffffff;
2272 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2274 /* R0.y = R0.x >> 30 */
2275 memset(&alu
, 0, sizeof(alu
));
2276 alu
.op
= ALU_OP2_LSHR_INT
;
2277 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2278 alu
.src
[1].value
= 0x1e;
2282 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2284 /* fetch vertex data from GSVS ring */
2285 for (i
= 0; i
< ocnt
; ++i
) {
2286 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2289 out
->ring_offset
= i
* 16;
2291 memset(&vtx
, 0, sizeof(vtx
));
2292 vtx
.op
= FETCH_OP_VFETCH
;
2293 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
2294 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2295 vtx
.mega_fetch_count
= 16;
2296 vtx
.offset
= out
->ring_offset
;
2297 vtx
.dst_gpr
= out
->gpr
;
2303 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2304 vtx
.use_const_fields
= 1;
2306 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
2309 r600_bytecode_add_vtx(ctx
.bc
, &vtx
);
2311 ctx
.temp_reg
= i
+ 1;
2312 for (ring
= 3; ring
>= 0; --ring
) {
2313 bool enabled
= false;
2314 for (i
= 0; i
< so
->num_outputs
; i
++) {
2315 if (so
->output
[i
].stream
== ring
) {
2318 only_ring_0
= false;
2322 if (ring
!= 0 && !enabled
) {
2323 cshader
->shader
.ring_item_sizes
[ring
] = 0;
2328 // Patch up jump label
2329 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2330 cf_pop
= ctx
.bc
->cf_last
;
2332 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2333 cf_jump
->pop_count
= 1;
2334 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2335 cf_pop
->pop_count
= 1;
2338 /* PRED_SETE_INT __, R0.y, ring */
2339 memset(&alu
, 0, sizeof(alu
));
2340 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2341 alu
.src
[0].chan
= 1;
2342 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2343 alu
.src
[1].value
= ring
;
2344 alu
.execute_mask
= 1;
2345 alu
.update_pred
= 1;
2347 r600_bytecode_add_alu_type(ctx
.bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2349 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_JUMP
);
2350 cf_jump
= ctx
.bc
->cf_last
;
2353 emit_streamout(&ctx
, so
, only_ring_0
? -1 : ring
, &cshader
->shader
.ring_item_sizes
[ring
]);
2354 cshader
->shader
.ring_item_sizes
[ring
] = ocnt
* 16;
2357 /* bc adds nops - copy it */
2358 if (ctx
.bc
->chip_class
== R600
) {
2359 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2360 alu
.op
= ALU_OP0_NOP
;
2362 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2364 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2367 /* export vertex data */
2368 /* XXX factor out common code with r600_shader_from_tgsi ? */
2369 for (i
= 0; i
< ocnt
; ++i
) {
2370 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2371 bool instream0
= true;
2372 if (out
->name
== TGSI_SEMANTIC_CLIPVERTEX
)
2375 for (j
= 0; j
< so
->num_outputs
; j
++) {
2376 if (so
->output
[j
].register_index
== i
) {
2377 if (so
->output
[j
].stream
== 0)
2379 if (so
->output
[j
].stream
> 0)
2385 memset(&output
, 0, sizeof(output
));
2386 output
.gpr
= out
->gpr
;
2387 output
.elem_size
= 3;
2388 output
.swizzle_x
= 0;
2389 output
.swizzle_y
= 1;
2390 output
.swizzle_z
= 2;
2391 output
.swizzle_w
= 3;
2392 output
.burst_count
= 1;
2393 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2394 output
.op
= CF_OP_EXPORT
;
2395 switch (out
->name
) {
2396 case TGSI_SEMANTIC_POSITION
:
2397 output
.array_base
= 60;
2398 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2401 case TGSI_SEMANTIC_PSIZE
:
2402 output
.array_base
= 61;
2403 if (next_clip_pos
== 61)
2405 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2406 output
.swizzle_y
= 7;
2407 output
.swizzle_z
= 7;
2408 output
.swizzle_w
= 7;
2409 ctx
.shader
->vs_out_misc_write
= 1;
2410 ctx
.shader
->vs_out_point_size
= 1;
2412 case TGSI_SEMANTIC_LAYER
:
2414 /* duplicate it as PARAM to pass to the pixel shader */
2415 output
.array_base
= next_param
++;
2416 r600_bytecode_add_output(ctx
.bc
, &output
);
2417 last_exp_param
= ctx
.bc
->cf_last
;
2419 output
.array_base
= 61;
2420 if (next_clip_pos
== 61)
2422 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2423 output
.swizzle_x
= 7;
2424 output
.swizzle_y
= 7;
2425 output
.swizzle_z
= 0;
2426 output
.swizzle_w
= 7;
2427 ctx
.shader
->vs_out_misc_write
= 1;
2428 ctx
.shader
->vs_out_layer
= 1;
2430 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2432 /* duplicate it as PARAM to pass to the pixel shader */
2433 output
.array_base
= next_param
++;
2434 r600_bytecode_add_output(ctx
.bc
, &output
);
2435 last_exp_param
= ctx
.bc
->cf_last
;
2437 output
.array_base
= 61;
2438 if (next_clip_pos
== 61)
2440 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2441 ctx
.shader
->vs_out_misc_write
= 1;
2442 ctx
.shader
->vs_out_viewport
= 1;
2443 output
.swizzle_x
= 7;
2444 output
.swizzle_y
= 7;
2445 output
.swizzle_z
= 7;
2446 output
.swizzle_w
= 0;
2448 case TGSI_SEMANTIC_CLIPDIST
:
2449 /* spi_sid is 0 for clipdistance outputs that were generated
2450 * for clipvertex - we don't need to pass them to PS */
2451 ctx
.shader
->clip_dist_write
= gs
->shader
.clip_dist_write
;
2452 ctx
.shader
->cull_dist_write
= gs
->shader
.cull_dist_write
;
2453 ctx
.shader
->cc_dist_mask
= gs
->shader
.cc_dist_mask
;
2455 /* duplicate it as PARAM to pass to the pixel shader */
2456 output
.array_base
= next_param
++;
2457 r600_bytecode_add_output(ctx
.bc
, &output
);
2458 last_exp_param
= ctx
.bc
->cf_last
;
2460 output
.array_base
= next_clip_pos
++;
2461 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2463 case TGSI_SEMANTIC_FOG
:
2464 output
.swizzle_y
= 4; /* 0 */
2465 output
.swizzle_z
= 4; /* 0 */
2466 output
.swizzle_w
= 5; /* 1 */
2469 output
.array_base
= next_param
++;
2472 r600_bytecode_add_output(ctx
.bc
, &output
);
2473 if (output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
)
2474 last_exp_param
= ctx
.bc
->cf_last
;
2476 last_exp_pos
= ctx
.bc
->cf_last
;
2479 if (!last_exp_pos
) {
2480 memset(&output
, 0, sizeof(output
));
2482 output
.elem_size
= 3;
2483 output
.swizzle_x
= 7;
2484 output
.swizzle_y
= 7;
2485 output
.swizzle_z
= 7;
2486 output
.swizzle_w
= 7;
2487 output
.burst_count
= 1;
2489 output
.op
= CF_OP_EXPORT
;
2490 output
.array_base
= 60;
2491 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2492 r600_bytecode_add_output(ctx
.bc
, &output
);
2493 last_exp_pos
= ctx
.bc
->cf_last
;
2496 if (!last_exp_param
) {
2497 memset(&output
, 0, sizeof(output
));
2499 output
.elem_size
= 3;
2500 output
.swizzle_x
= 7;
2501 output
.swizzle_y
= 7;
2502 output
.swizzle_z
= 7;
2503 output
.swizzle_w
= 7;
2504 output
.burst_count
= 1;
2506 output
.op
= CF_OP_EXPORT
;
2507 output
.array_base
= next_param
++;
2508 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2509 r600_bytecode_add_output(ctx
.bc
, &output
);
2510 last_exp_param
= ctx
.bc
->cf_last
;
2513 last_exp_pos
->op
= CF_OP_EXPORT_DONE
;
2514 last_exp_param
->op
= CF_OP_EXPORT_DONE
;
2516 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2517 cf_pop
= ctx
.bc
->cf_last
;
2519 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2520 cf_jump
->pop_count
= 1;
2521 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2522 cf_pop
->pop_count
= 1;
2524 if (ctx
.bc
->chip_class
== CAYMAN
)
2525 cm_bytecode_add_cf_end(ctx
.bc
);
2527 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2528 ctx
.bc
->cf_last
->end_of_program
= 1;
2531 gs
->gs_copy_shader
= cshader
;
2532 cshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
2536 return r600_bytecode_build(ctx
.bc
);
2539 static int emit_inc_ring_offset(struct r600_shader_ctx
*ctx
, int idx
, bool ind
)
2542 struct r600_bytecode_alu alu
;
2545 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2546 alu
.op
= ALU_OP2_ADD_INT
;
2547 alu
.src
[0].sel
= ctx
->gs_export_gpr_tregs
[idx
];
2548 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2549 alu
.src
[1].value
= ctx
->gs_out_ring_offset
>> 4;
2550 alu
.dst
.sel
= ctx
->gs_export_gpr_tregs
[idx
];
2553 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2560 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so UNUSED
, int stream
, bool ind
)
2562 struct r600_bytecode_output output
;
2565 int effective_stream
= stream
== -1 ? 0 : stream
;
2568 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2569 if (ctx
->gs_for_vs
) {
2570 /* for ES we need to lookup corresponding ring offset expected by GS
2571 * (map this output to GS input by name and sid) */
2572 /* FIXME precompute offsets */
2574 for(k
= 0; k
< ctx
->gs_for_vs
->ninput
; ++k
) {
2575 struct r600_shader_io
*in
= &ctx
->gs_for_vs
->input
[k
];
2576 struct r600_shader_io
*out
= &ctx
->shader
->output
[i
];
2577 if (in
->name
== out
->name
&& in
->sid
== out
->sid
)
2578 ring_offset
= in
->ring_offset
;
2581 if (ring_offset
== -1)
2584 ring_offset
= idx
* 16;
2588 if (stream
> 0 && ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2590 /* next_ring_offset after parsing input decls contains total size of
2591 * single vertex data, gs_next_vertex - current vertex index */
2593 ring_offset
+= ctx
->gs_out_ring_offset
* ctx
->gs_next_vertex
;
2595 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2596 output
.gpr
= ctx
->shader
->output
[i
].gpr
;
2597 output
.elem_size
= 3;
2598 output
.comp_mask
= 0xF;
2599 output
.burst_count
= 1;
2602 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
2604 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2609 output
.op
= CF_OP_MEM_RING
; break;
2611 output
.op
= CF_OP_MEM_RING1
; break;
2613 output
.op
= CF_OP_MEM_RING2
; break;
2615 output
.op
= CF_OP_MEM_RING3
; break;
2619 output
.array_base
= ring_offset
>> 2; /* in dwords */
2620 output
.array_size
= 0xfff;
2621 output
.index_gpr
= ctx
->gs_export_gpr_tregs
[effective_stream
];
2623 output
.array_base
= ring_offset
>> 2; /* in dwords */
2624 r600_bytecode_add_output(ctx
->bc
, &output
);
2627 ++ctx
->gs_next_vertex
;
2632 static int r600_fetch_tess_io_info(struct r600_shader_ctx
*ctx
)
2635 struct r600_bytecode_vtx vtx
;
2636 int temp_val
= ctx
->temp_reg
;
2637 /* need to store the TCS output somewhere */
2638 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2640 V_SQ_ALU_SRC_LITERAL
, 0,
2645 /* used by VS/TCS */
2646 if (ctx
->tess_input_info
) {
2647 /* fetch tcs input values into resv space */
2648 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2649 vtx
.op
= FETCH_OP_VFETCH
;
2650 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2651 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2652 vtx
.mega_fetch_count
= 16;
2653 vtx
.data_format
= FMT_32_32_32_32
;
2654 vtx
.num_format_all
= 2;
2655 vtx
.format_comp_all
= 1;
2656 vtx
.use_const_fields
= 0;
2657 vtx
.endian
= r600_endian_swap(32);
2658 vtx
.srf_mode_all
= 1;
2660 vtx
.dst_gpr
= ctx
->tess_input_info
;
2665 vtx
.src_gpr
= temp_val
;
2668 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2673 /* used by TCS/TES */
2674 if (ctx
->tess_output_info
) {
2675 /* fetch tcs output values into resv space */
2676 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2677 vtx
.op
= FETCH_OP_VFETCH
;
2678 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2679 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2680 vtx
.mega_fetch_count
= 16;
2681 vtx
.data_format
= FMT_32_32_32_32
;
2682 vtx
.num_format_all
= 2;
2683 vtx
.format_comp_all
= 1;
2684 vtx
.use_const_fields
= 0;
2685 vtx
.endian
= r600_endian_swap(32);
2686 vtx
.srf_mode_all
= 1;
2688 vtx
.dst_gpr
= ctx
->tess_output_info
;
2693 vtx
.src_gpr
= temp_val
;
2696 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2703 static int emit_lds_vs_writes(struct r600_shader_ctx
*ctx
)
2709 /* fetch tcs input values into input_vals */
2710 ctx
->tess_input_info
= r600_get_temp(ctx
);
2711 ctx
->tess_output_info
= 0;
2712 r
= r600_fetch_tess_io_info(ctx
);
2716 temp_reg
= r600_get_temp(ctx
);
2717 /* dst reg contains LDS address stride * idx */
2718 /* MUL vertexID, vertex_dw_stride */
2719 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
2721 ctx
->tess_input_info
, 1,
2722 0, 1); /* rel id in r0.y? */
2726 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2727 struct r600_bytecode_alu alu
;
2728 int param
= r600_get_lds_unique_index(ctx
->shader
->output
[i
].name
, ctx
->shader
->output
[i
].sid
);
2731 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2734 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2739 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2741 temp_reg
, param
? 1 : 0,
2742 V_SQ_ALU_SRC_LITERAL
, 8);
2747 for (j
= 0; j
< 2; j
++) {
2748 int chan
= (j
== 1) ? 2 : (param
? 1 : 0);
2749 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2750 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2751 alu
.src
[0].sel
= temp_reg
;
2752 alu
.src
[0].chan
= chan
;
2753 alu
.src
[1].sel
= ctx
->shader
->output
[i
].gpr
;
2754 alu
.src
[1].chan
= j
* 2;
2755 alu
.src
[2].sel
= ctx
->shader
->output
[i
].gpr
;
2756 alu
.src
[2].chan
= (j
* 2) + 1;
2760 alu
.is_lds_idx_op
= true;
2761 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2769 static int r600_store_tcs_output(struct r600_shader_ctx
*ctx
)
2771 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2772 const struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
2774 int temp_reg
= r600_get_temp(ctx
);
2775 struct r600_bytecode_alu alu
;
2776 unsigned write_mask
= dst
->Register
.WriteMask
;
2778 if (inst
->Dst
[0].Register
.File
!= TGSI_FILE_OUTPUT
)
2781 r
= get_lds_offset0(ctx
, 1, temp_reg
, dst
->Register
.Dimension
? false : true);
2785 /* the base address is now in temp.x */
2786 r
= r600_get_byte_address(ctx
, temp_reg
,
2787 &inst
->Dst
[0], NULL
, ctx
->tess_output_info
, 1);
2792 lasti
= tgsi_last_instruction(write_mask
);
2793 for (i
= 1; i
<= lasti
; i
++) {
2795 if (!(write_mask
& (1 << i
)))
2797 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2800 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2805 for (i
= 0; i
<= lasti
; i
++) {
2806 if (!(write_mask
& (1 << i
)))
2809 if ((i
== 0 && ((write_mask
& 3) == 3)) ||
2810 (i
== 2 && ((write_mask
& 0xc) == 0xc))) {
2811 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2812 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2813 alu
.src
[0].sel
= temp_reg
;
2814 alu
.src
[0].chan
= i
;
2816 alu
.src
[1].sel
= dst
->Register
.Index
;
2817 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2818 alu
.src
[1].chan
= i
;
2820 alu
.src
[2].sel
= dst
->Register
.Index
;
2821 alu
.src
[2].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2822 alu
.src
[2].chan
= i
+ 1;
2826 alu
.is_lds_idx_op
= true;
2827 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2833 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2834 alu
.op
= LDS_OP2_LDS_WRITE
;
2835 alu
.src
[0].sel
= temp_reg
;
2836 alu
.src
[0].chan
= i
;
2838 alu
.src
[1].sel
= dst
->Register
.Index
;
2839 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2840 alu
.src
[1].chan
= i
;
2842 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
2845 alu
.is_lds_idx_op
= true;
2846 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2853 static int r600_tess_factor_read(struct r600_shader_ctx
*ctx
,
2854 int output_idx
, int nc
)
2857 unsigned temp_reg
= r600_get_temp(ctx
);
2858 unsigned name
= ctx
->shader
->output
[output_idx
].name
;
2859 int dreg
= ctx
->shader
->output
[output_idx
].gpr
;
2862 param
= r600_get_lds_unique_index(name
, 0);
2863 r
= get_lds_offset0(ctx
, 1, temp_reg
, true);
2867 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2870 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2874 do_lds_fetch_values(ctx
, temp_reg
, dreg
, ((1u << nc
) - 1));
2878 static int r600_emit_tess_factor(struct r600_shader_ctx
*ctx
)
2880 int stride
, outer_comps
, inner_comps
;
2881 int tessinner_idx
= -1, tessouter_idx
= -1;
2884 int temp_reg
= r600_get_temp(ctx
);
2885 int treg
[3] = {-1, -1, -1};
2886 struct r600_bytecode_alu alu
;
2887 struct r600_bytecode_cf
*cf_jump
, *cf_pop
;
2889 /* only execute factor emission for invocation 0 */
2890 /* PRED_SETE_INT __, R0.x, 0 */
2891 memset(&alu
, 0, sizeof(alu
));
2892 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2893 alu
.src
[0].chan
= 2;
2894 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2895 alu
.execute_mask
= 1;
2896 alu
.update_pred
= 1;
2898 r600_bytecode_add_alu_type(ctx
->bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2900 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
2901 cf_jump
= ctx
->bc
->cf_last
;
2903 treg
[0] = r600_get_temp(ctx
);
2904 switch (ctx
->shader
->tcs_prim_mode
) {
2905 case PIPE_PRIM_LINES
:
2906 stride
= 8; /* 2 dwords, 1 vec2 store */
2910 case PIPE_PRIM_TRIANGLES
:
2911 stride
= 16; /* 4 dwords, 1 vec4 store */
2914 treg
[1] = r600_get_temp(ctx
);
2916 case PIPE_PRIM_QUADS
:
2917 stride
= 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2920 treg
[1] = r600_get_temp(ctx
);
2921 treg
[2] = r600_get_temp(ctx
);
2928 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2929 /* TF_WRITE takes index in R.x, value in R.y */
2930 for (j
= 0; j
< ctx
->shader
->noutput
; j
++) {
2931 if (ctx
->shader
->output
[j
].name
== TGSI_SEMANTIC_TESSINNER
)
2933 if (ctx
->shader
->output
[j
].name
== TGSI_SEMANTIC_TESSOUTER
)
2937 if (tessouter_idx
== -1)
2940 if (tessinner_idx
== -1 && inner_comps
)
2943 if (tessouter_idx
!= -1) {
2944 r
= r600_tess_factor_read(ctx
, tessouter_idx
, outer_comps
);
2949 if (tessinner_idx
!= -1) {
2950 r
= r600_tess_factor_read(ctx
, tessinner_idx
, inner_comps
);
2955 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2956 /* r.x = relpatchid(r0.y) * tf_stride */
2958 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2959 /* add incoming r0.w to it: t.x = t.x + r0.w */
2960 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
2963 V_SQ_ALU_SRC_LITERAL
, stride
,
2968 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2969 int out_idx
= i
>= outer_comps
? tessinner_idx
: tessouter_idx
;
2970 int out_comp
= i
>= outer_comps
? i
- outer_comps
: i
;
2972 if (ctx
->shader
->tcs_prim_mode
== PIPE_PRIM_LINES
) {
2975 else if (out_comp
== 0)
2979 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2980 treg
[i
/ 2], (2 * (i
% 2)),
2982 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2985 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2986 treg
[i
/ 2], 1 + (2 * (i
%2)),
2987 ctx
->shader
->output
[out_idx
].gpr
, out_comp
,
2992 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2993 struct r600_bytecode_gds gds
;
2995 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
2996 gds
.src_gpr
= treg
[i
/ 2];
2997 gds
.src_sel_x
= 2 * (i
% 2);
2998 gds
.src_sel_y
= 1 + (2 * (i
% 2));
3004 gds
.op
= FETCH_OP_TF_WRITE
;
3005 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
3010 // Patch up jump label
3011 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
3012 cf_pop
= ctx
->bc
->cf_last
;
3014 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
3015 cf_jump
->pop_count
= 1;
3016 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
3017 cf_pop
->pop_count
= 1;
3023 * We have to work out the thread ID for load and atomic
3024 * operations, which store the returned value to an index
3025 * in an intermediate buffer.
3026 * The index is calculated by taking the thread id,
3027 * calculated from the MBCNT instructions.
3028 * Then the shader engine ID is multiplied by 256,
3029 * and the wave id is added.
3030 * Then the result is multipled by 64 and thread id is
3033 static int load_thread_id_gpr(struct r600_shader_ctx
*ctx
)
3035 struct r600_bytecode_alu alu
;
3038 if (ctx
->thread_id_gpr_loaded
)
3041 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3042 alu
.op
= ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT
;
3043 alu
.dst
.sel
= ctx
->temp_reg
;
3045 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
3046 alu
.src
[0].value
= 0xffffffff;
3048 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3052 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3053 alu
.op
= ALU_OP1_MBCNT_32HI_INT
;
3054 alu
.dst
.sel
= ctx
->temp_reg
;
3056 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
3057 alu
.src
[0].value
= 0xffffffff;
3059 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3063 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3064 alu
.op
= ALU_OP3_MULADD_UINT24
;
3065 alu
.dst
.sel
= ctx
->temp_reg
;
3067 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_SE_ID
;
3068 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
3069 alu
.src
[1].value
= 256;
3070 alu
.src
[2].sel
= EG_V_SQ_ALU_SRC_HW_WAVE_ID
;
3074 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3078 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
3079 ctx
->thread_id_gpr
, 1,
3081 V_SQ_ALU_SRC_LITERAL
, 0x40,
3085 ctx
->thread_id_gpr_loaded
= true;
3089 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
3090 struct r600_pipe_shader
*pipeshader
,
3091 union r600_shader_key key
)
3093 struct r600_screen
*rscreen
= rctx
->screen
;
3094 struct r600_shader
*shader
= &pipeshader
->shader
;
3095 struct tgsi_token
*tokens
= pipeshader
->selector
->tokens
;
3096 struct pipe_stream_output_info so
= pipeshader
->selector
->so
;
3097 struct tgsi_full_immediate
*immediate
;
3098 struct r600_shader_ctx ctx
;
3099 struct r600_bytecode_output output
[ARRAY_SIZE(shader
->output
)];
3100 unsigned output_done
, noutput
;
3104 int next_param_base
= 0, next_clip_base
;
3105 int max_color_exports
= MAX2(key
.ps
.nr_cbufs
, 1);
3107 bool ring_outputs
= false;
3108 bool lds_outputs
= false;
3109 bool lds_inputs
= false;
3110 bool pos_emitted
= false;
3112 ctx
.bc
= &shader
->bc
;
3113 ctx
.shader
= shader
;
3115 r600_bytecode_init(ctx
.bc
, rscreen
->b
.chip_class
, rscreen
->b
.family
,
3116 rscreen
->has_compressed_msaa_texturing
);
3117 ctx
.tokens
= tokens
;
3118 tgsi_scan_shader(tokens
, &ctx
.info
);
3119 shader
->indirect_files
= ctx
.info
.indirect_files
;
3121 shader
->uses_doubles
= ctx
.info
.uses_doubles
;
3122 shader
->uses_atomics
= ctx
.info
.file_mask
[TGSI_FILE_HW_ATOMIC
];
3123 shader
->nsys_inputs
= 0;
3125 shader
->uses_images
= ctx
.info
.file_count
[TGSI_FILE_IMAGE
] > 0 ||
3126 ctx
.info
.file_count
[TGSI_FILE_BUFFER
] > 0;
3127 indirect_gprs
= ctx
.info
.indirect_files
& ~((1 << TGSI_FILE_CONSTANT
) | (1 << TGSI_FILE_SAMPLER
));
3128 tgsi_parse_init(&ctx
.parse
, tokens
);
3129 ctx
.type
= ctx
.info
.processor
;
3130 shader
->processor_type
= ctx
.type
;
3131 ctx
.bc
->type
= shader
->processor_type
;
3134 case PIPE_SHADER_VERTEX
:
3135 shader
->vs_as_gs_a
= key
.vs
.as_gs_a
;
3136 shader
->vs_as_es
= key
.vs
.as_es
;
3137 shader
->vs_as_ls
= key
.vs
.as_ls
;
3138 shader
->atomic_base
= key
.vs
.first_atomic_counter
;
3139 if (shader
->vs_as_es
)
3140 ring_outputs
= true;
3141 if (shader
->vs_as_ls
)
3144 case PIPE_SHADER_GEOMETRY
:
3145 ring_outputs
= true;
3146 shader
->atomic_base
= key
.gs
.first_atomic_counter
;
3147 shader
->gs_tri_strip_adj_fix
= key
.gs
.tri_strip_adj_fix
;
3149 case PIPE_SHADER_TESS_CTRL
:
3150 shader
->tcs_prim_mode
= key
.tcs
.prim_mode
;
3151 shader
->atomic_base
= key
.tcs
.first_atomic_counter
;
3155 case PIPE_SHADER_TESS_EVAL
:
3156 shader
->tes_as_es
= key
.tes
.as_es
;
3157 shader
->atomic_base
= key
.tes
.first_atomic_counter
;
3159 if (shader
->tes_as_es
)
3160 ring_outputs
= true;
3162 case PIPE_SHADER_FRAGMENT
:
3163 shader
->two_side
= key
.ps
.color_two_side
;
3164 shader
->atomic_base
= key
.ps
.first_atomic_counter
;
3165 shader
->rat_base
= key
.ps
.nr_cbufs
;
3166 shader
->image_size_const_offset
= key
.ps
.image_size_const_offset
;
3168 case PIPE_SHADER_COMPUTE
:
3169 shader
->rat_base
= 0;
3170 shader
->image_size_const_offset
= 0;
3176 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3177 ctx
.gs_for_vs
= &rctx
->gs_shader
->current
->shader
;
3179 ctx
.gs_for_vs
= NULL
;
3182 ctx
.next_ring_offset
= 0;
3183 ctx
.gs_out_ring_offset
= 0;
3184 ctx
.gs_next_vertex
= 0;
3185 ctx
.gs_stream_output_info
= &so
;
3188 ctx
.fixed_pt_position_gpr
= -1;
3189 ctx
.fragcoord_input
= -1;
3190 ctx
.colors_used
= 0;
3191 ctx
.clip_vertex_write
= 0;
3192 ctx
.thread_id_gpr_loaded
= false;
3194 ctx
.cs_block_size_reg
= -1;
3195 ctx
.cs_grid_size_reg
= -1;
3196 ctx
.cs_block_size_loaded
= false;
3197 ctx
.cs_grid_size_loaded
= false;
3199 shader
->nr_ps_color_exports
= 0;
3200 shader
->nr_ps_max_color_exports
= 0;
3203 /* register allocations */
3204 /* Values [0,127] correspond to GPR[0..127].
3205 * Values [128,159] correspond to constant buffer bank 0
3206 * Values [160,191] correspond to constant buffer bank 1
3207 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3208 * Values [256,287] correspond to constant buffer bank 2 (EG)
3209 * Values [288,319] correspond to constant buffer bank 3 (EG)
3210 * Other special values are shown in the list below.
3211 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3212 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3213 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3214 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3215 * 248 SQ_ALU_SRC_0: special constant 0.0.
3216 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3217 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3218 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3219 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3220 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3221 * 254 SQ_ALU_SRC_PV: previous vector result.
3222 * 255 SQ_ALU_SRC_PS: previous scalar result.
3224 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
3225 ctx
.file_offset
[i
] = 0;
3228 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3230 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3231 if (ctx
.info
.num_inputs
)
3232 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CALL_FS
);
3234 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
3235 if (ctx
.bc
->chip_class
>= EVERGREEN
)
3236 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
3238 ctx
.file_offset
[TGSI_FILE_INPUT
] = allocate_system_value_inputs(&ctx
, ctx
.file_offset
[TGSI_FILE_INPUT
]);
3240 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3241 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3242 ctx
.file_offset
[TGSI_FILE_INPUT
] = 2;
3244 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3245 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3246 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3247 bool add_tesscoord
= false, add_tess_inout
= false;
3248 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3249 for (i
= 0; i
< PIPE_MAX_SHADER_INPUTS
; i
++) {
3250 /* if we have tesscoord save one reg */
3251 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSCOORD
)
3252 add_tesscoord
= true;
3253 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSINNER
||
3254 ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSOUTER
)
3255 add_tess_inout
= true;
3257 if (add_tesscoord
|| add_tess_inout
)
3258 ctx
.file_offset
[TGSI_FILE_INPUT
]++;
3260 ctx
.file_offset
[TGSI_FILE_INPUT
]+=2;
3262 if (ctx
.type
== PIPE_SHADER_COMPUTE
) {
3263 ctx
.file_offset
[TGSI_FILE_INPUT
] = 2;
3264 for (i
= 0; i
< PIPE_MAX_SHADER_INPUTS
; i
++) {
3265 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_GRID_SIZE
)
3266 ctx
.cs_grid_size_reg
= ctx
.file_offset
[TGSI_FILE_INPUT
]++;
3267 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_BLOCK_SIZE
)
3268 ctx
.cs_block_size_reg
= ctx
.file_offset
[TGSI_FILE_INPUT
]++;
3272 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
3273 ctx
.file_offset
[TGSI_FILE_INPUT
] +
3274 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3275 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
3276 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
3278 /* Outside the GPR range. This will be translated to one of the
3279 * kcache banks later. */
3280 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
3282 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
3283 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
3284 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
3285 ctx
.bc
->index_reg
[0] = ctx
.bc
->ar_reg
+ 1;
3286 ctx
.bc
->index_reg
[1] = ctx
.bc
->ar_reg
+ 2;
3288 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3289 ctx
.tess_input_info
= ctx
.bc
->ar_reg
+ 3;
3290 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 4;
3291 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 5;
3292 } else if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3293 ctx
.tess_input_info
= 0;
3294 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 3;
3295 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 4;
3296 } else if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3297 ctx
.gs_export_gpr_tregs
[0] = ctx
.bc
->ar_reg
+ 3;
3298 ctx
.gs_export_gpr_tregs
[1] = ctx
.bc
->ar_reg
+ 4;
3299 ctx
.gs_export_gpr_tregs
[2] = ctx
.bc
->ar_reg
+ 5;
3300 ctx
.gs_export_gpr_tregs
[3] = ctx
.bc
->ar_reg
+ 6;
3301 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 7;
3302 if (ctx
.shader
->gs_tri_strip_adj_fix
) {
3303 ctx
.gs_rotated_input
[0] = ctx
.bc
->ar_reg
+ 7;
3304 ctx
.gs_rotated_input
[1] = ctx
.bc
->ar_reg
+ 8;
3307 ctx
.gs_rotated_input
[0] = 0;
3308 ctx
.gs_rotated_input
[1] = 1;
3311 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 3;
3314 if (shader
->uses_images
) {
3315 ctx
.thread_id_gpr
= ctx
.temp_reg
++;
3316 ctx
.thread_id_gpr_loaded
= false;
3319 shader
->max_arrays
= 0;
3320 shader
->num_arrays
= 0;
3321 if (indirect_gprs
) {
3323 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_INPUT
)) {
3324 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_INPUT
],
3325 ctx
.file_offset
[TGSI_FILE_OUTPUT
] -
3326 ctx
.file_offset
[TGSI_FILE_INPUT
],
3329 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_OUTPUT
)) {
3330 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3331 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] -
3332 ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3338 ctx
.literals
= NULL
;
3340 shader
->fs_write_all
= ctx
.info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
3341 ctx
.info
.colors_written
== 1;
3342 shader
->vs_position_window_space
= ctx
.info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
3343 shader
->ps_conservative_z
= (uint8_t)ctx
.info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
];
3345 if (ctx
.type
== PIPE_SHADER_VERTEX
||
3346 ctx
.type
== PIPE_SHADER_GEOMETRY
||
3347 ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3348 shader
->cc_dist_mask
= (1 << (ctx
.info
.properties
[TGSI_PROPERTY_NUM_CULLDIST_ENABLED
] +
3349 ctx
.info
.properties
[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED
])) - 1;
3350 shader
->clip_dist_write
= (1 << ctx
.info
.properties
[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED
]) - 1;
3351 shader
->cull_dist_write
= ((1 << ctx
.info
.properties
[TGSI_PROPERTY_NUM_CULLDIST_ENABLED
]) - 1) << ctx
.info
.properties
[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED
];
3354 if (shader
->vs_as_gs_a
)
3355 vs_add_primid_output(&ctx
, key
.vs
.prim_id_out
);
3357 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3358 r600_fetch_tess_io_info(&ctx
);
3360 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3361 tgsi_parse_token(&ctx
.parse
);
3362 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3363 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3364 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
3365 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
3366 if(ctx
.literals
== NULL
) {
3370 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
3371 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
3372 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
3373 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
3376 case TGSI_TOKEN_TYPE_DECLARATION
:
3377 r
= tgsi_declaration(&ctx
);
3381 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3382 case TGSI_TOKEN_TYPE_PROPERTY
:
3385 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
3391 shader
->ring_item_sizes
[0] = ctx
.next_ring_offset
;
3392 shader
->ring_item_sizes
[1] = 0;
3393 shader
->ring_item_sizes
[2] = 0;
3394 shader
->ring_item_sizes
[3] = 0;
3396 /* Process two side if needed */
3397 if (shader
->two_side
&& ctx
.colors_used
) {
3398 int i
, count
= ctx
.shader
->ninput
;
3399 unsigned next_lds_loc
= ctx
.shader
->nlds
;
3401 /* additional inputs will be allocated right after the existing inputs,
3402 * we won't need them after the color selection, so we don't need to
3403 * reserve these gprs for the rest of the shader code and to adjust
3404 * output offsets etc. */
3405 int gpr
= ctx
.file_offset
[TGSI_FILE_INPUT
] +
3406 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3408 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3409 if (ctx
.face_gpr
== -1) {
3410 i
= ctx
.shader
->ninput
++;
3411 ctx
.shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
3412 ctx
.shader
->input
[i
].spi_sid
= 0;
3413 ctx
.shader
->input
[i
].gpr
= gpr
++;
3414 ctx
.face_gpr
= ctx
.shader
->input
[i
].gpr
;
3417 for (i
= 0; i
< count
; i
++) {
3418 if (ctx
.shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3419 int ni
= ctx
.shader
->ninput
++;
3420 memcpy(&ctx
.shader
->input
[ni
],&ctx
.shader
->input
[i
], sizeof(struct r600_shader_io
));
3421 ctx
.shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
3422 ctx
.shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
.shader
->input
[ni
]);
3423 ctx
.shader
->input
[ni
].gpr
= gpr
++;
3424 // TGSI to LLVM needs to know the lds position of inputs.
3425 // Non LLVM path computes it later (in process_twoside_color)
3426 ctx
.shader
->input
[ni
].lds_pos
= next_lds_loc
++;
3427 ctx
.shader
->input
[i
].back_color_input
= ni
;
3428 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
3429 if ((r
= evergreen_interp_input(&ctx
, ni
)))
3436 if (shader
->fs_write_all
&& rscreen
->b
.chip_class
>= EVERGREEN
)
3437 shader
->nr_ps_max_color_exports
= 8;
3439 if (ctx
.fragcoord_input
>= 0) {
3440 if (ctx
.bc
->chip_class
== CAYMAN
) {
3441 for (j
= 0 ; j
< 4; j
++) {
3442 struct r600_bytecode_alu alu
;
3443 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3444 alu
.op
= ALU_OP1_RECIP_IEEE
;
3445 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3446 alu
.src
[0].chan
= 3;
3448 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3450 alu
.dst
.write
= (j
== 3);
3452 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3456 struct r600_bytecode_alu alu
;
3457 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3458 alu
.op
= ALU_OP1_RECIP_IEEE
;
3459 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3460 alu
.src
[0].chan
= 3;
3462 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3466 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3471 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3472 struct r600_bytecode_alu alu
;
3475 /* GS thread with no output workaround - emit a cut at start of GS */
3476 if (ctx
.bc
->chip_class
== R600
)
3477 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CUT_VERTEX
);
3479 for (j
= 0; j
< 4; j
++) {
3480 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3481 alu
.op
= ALU_OP1_MOV
;
3482 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
3483 alu
.src
[0].value
= 0;
3484 alu
.dst
.sel
= ctx
.gs_export_gpr_tregs
[j
];
3487 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3492 if (ctx
.shader
->gs_tri_strip_adj_fix
) {
3493 r
= single_alu_op2(&ctx
, ALU_OP2_AND_INT
,
3494 ctx
.gs_rotated_input
[0], 2,
3496 V_SQ_ALU_SRC_LITERAL
, 1);
3500 for (i
= 0; i
< 6; i
++) {
3501 int rotated
= (i
+ 4) % 6;
3502 int offset_reg
= i
/ 3;
3503 int offset_chan
= i
% 3;
3504 int rotated_offset_reg
= rotated
/ 3;
3505 int rotated_offset_chan
= rotated
% 3;
3507 if (offset_reg
== 0 && offset_chan
== 2)
3509 if (rotated_offset_reg
== 0 && rotated_offset_chan
== 2)
3510 rotated_offset_chan
= 3;
3512 r
= single_alu_op3(&ctx
, ALU_OP3_CNDE_INT
,
3513 ctx
.gs_rotated_input
[offset_reg
], offset_chan
,
3514 ctx
.gs_rotated_input
[0], 2,
3515 offset_reg
, offset_chan
,
3516 rotated_offset_reg
, rotated_offset_chan
);
3523 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3524 r600_fetch_tess_io_info(&ctx
);
3526 if (shader
->two_side
&& ctx
.colors_used
) {
3527 if ((r
= process_twoside_color_inputs(&ctx
)))
3531 tgsi_parse_init(&ctx
.parse
, tokens
);
3532 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3533 tgsi_parse_token(&ctx
.parse
);
3534 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3535 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3536 r
= tgsi_is_supported(&ctx
);
3539 ctx
.max_driver_temp_used
= 0;
3540 /* reserve first tmp for everyone */
3541 r600_get_temp(&ctx
);
3543 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3544 if ((r
= tgsi_split_constant(&ctx
)))
3546 if ((r
= tgsi_split_literal_constant(&ctx
)))
3548 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3549 if ((r
= tgsi_split_gs_inputs(&ctx
)))
3551 } else if (lds_inputs
) {
3552 if ((r
= tgsi_split_lds_inputs(&ctx
)))
3555 if (ctx
.bc
->chip_class
== CAYMAN
)
3556 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
3557 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
3558 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
3560 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
3561 r
= ctx
.inst_info
->process(&ctx
);
3565 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3566 r
= r600_store_tcs_output(&ctx
);
3576 /* Reset the temporary register counter. */
3577 ctx
.max_driver_temp_used
= 0;
3579 noutput
= shader
->noutput
;
3581 if (!ring_outputs
&& ctx
.clip_vertex_write
) {
3582 unsigned clipdist_temp
[2];
3584 clipdist_temp
[0] = r600_get_temp(&ctx
);
3585 clipdist_temp
[1] = r600_get_temp(&ctx
);
3587 /* need to convert a clipvertex write into clipdistance writes and not export
3588 the clip vertex anymore */
3590 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
3591 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3592 shader
->output
[noutput
].gpr
= clipdist_temp
[0];
3594 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3595 shader
->output
[noutput
].gpr
= clipdist_temp
[1];
3598 /* reset spi_sid for clipvertex output to avoid confusing spi */
3599 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
3601 shader
->clip_dist_write
= 0xFF;
3602 shader
->cc_dist_mask
= 0xFF;
3604 for (i
= 0; i
< 8; i
++) {
3608 for (j
= 0; j
< 4; j
++) {
3609 struct r600_bytecode_alu alu
;
3610 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3611 alu
.op
= ALU_OP2_DOT4
;
3612 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
3613 alu
.src
[0].chan
= j
;
3615 alu
.src
[1].sel
= 512 + i
;
3616 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
3617 alu
.src
[1].chan
= j
;
3619 alu
.dst
.sel
= clipdist_temp
[oreg
];
3621 alu
.dst
.write
= (j
== ochan
);
3624 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3631 /* Add stream outputs. */
3632 if (so
.num_outputs
) {
3634 if (!lds_outputs
&& !ring_outputs
&& ctx
.type
== PIPE_SHADER_VERTEX
)
3636 if (!ring_outputs
&& ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3639 emit_streamout(&ctx
, &so
, -1, NULL
);
3641 pipeshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
3642 convert_edgeflag_to_int(&ctx
);
3644 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3645 r600_emit_tess_factor(&ctx
);
3648 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3649 if (ctx
.shader
->noutput
)
3650 emit_lds_vs_writes(&ctx
);
3652 } else if (ring_outputs
) {
3653 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3654 ctx
.gs_export_gpr_tregs
[0] = r600_get_temp(&ctx
);
3655 ctx
.gs_export_gpr_tregs
[1] = -1;
3656 ctx
.gs_export_gpr_tregs
[2] = -1;
3657 ctx
.gs_export_gpr_tregs
[3] = -1;
3659 emit_gs_ring_writes(&ctx
, &so
, -1, FALSE
);
3663 next_clip_base
= shader
->vs_out_misc_write
? 62 : 61;
3665 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
3666 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3667 output
[j
].gpr
= shader
->output
[i
].gpr
;
3668 output
[j
].elem_size
= 3;
3669 output
[j
].swizzle_x
= 0;
3670 output
[j
].swizzle_y
= 1;
3671 output
[j
].swizzle_z
= 2;
3672 output
[j
].swizzle_w
= 3;
3673 output
[j
].burst_count
= 1;
3674 output
[j
].type
= 0xffffffff;
3675 output
[j
].op
= CF_OP_EXPORT
;
3677 case PIPE_SHADER_VERTEX
:
3678 case PIPE_SHADER_TESS_EVAL
:
3679 switch (shader
->output
[i
].name
) {
3680 case TGSI_SEMANTIC_POSITION
:
3681 output
[j
].array_base
= 60;
3682 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3686 case TGSI_SEMANTIC_PSIZE
:
3687 output
[j
].array_base
= 61;
3688 output
[j
].swizzle_y
= 7;
3689 output
[j
].swizzle_z
= 7;
3690 output
[j
].swizzle_w
= 7;
3691 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3694 case TGSI_SEMANTIC_EDGEFLAG
:
3695 output
[j
].array_base
= 61;
3696 output
[j
].swizzle_x
= 7;
3697 output
[j
].swizzle_y
= 0;
3698 output
[j
].swizzle_z
= 7;
3699 output
[j
].swizzle_w
= 7;
3700 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3703 case TGSI_SEMANTIC_LAYER
:
3704 /* spi_sid is 0 for outputs that are
3705 * not consumed by PS */
3706 if (shader
->output
[i
].spi_sid
) {
3707 output
[j
].array_base
= next_param_base
++;
3708 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3710 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3712 output
[j
].array_base
= 61;
3713 output
[j
].swizzle_x
= 7;
3714 output
[j
].swizzle_y
= 7;
3715 output
[j
].swizzle_z
= 0;
3716 output
[j
].swizzle_w
= 7;
3717 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3720 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
3721 /* spi_sid is 0 for outputs that are
3722 * not consumed by PS */
3723 if (shader
->output
[i
].spi_sid
) {
3724 output
[j
].array_base
= next_param_base
++;
3725 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3727 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3729 output
[j
].array_base
= 61;
3730 output
[j
].swizzle_x
= 7;
3731 output
[j
].swizzle_y
= 7;
3732 output
[j
].swizzle_z
= 7;
3733 output
[j
].swizzle_w
= 0;
3734 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3737 case TGSI_SEMANTIC_CLIPVERTEX
:
3740 case TGSI_SEMANTIC_CLIPDIST
:
3741 output
[j
].array_base
= next_clip_base
++;
3742 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3744 /* spi_sid is 0 for clipdistance outputs that were generated
3745 * for clipvertex - we don't need to pass them to PS */
3746 if (shader
->output
[i
].spi_sid
) {
3748 /* duplicate it as PARAM to pass to the pixel shader */
3749 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3750 output
[j
].array_base
= next_param_base
++;
3751 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3754 case TGSI_SEMANTIC_FOG
:
3755 output
[j
].swizzle_y
= 4; /* 0 */
3756 output
[j
].swizzle_z
= 4; /* 0 */
3757 output
[j
].swizzle_w
= 5; /* 1 */
3759 case TGSI_SEMANTIC_PRIMID
:
3760 output
[j
].swizzle_x
= 2;
3761 output
[j
].swizzle_y
= 4; /* 0 */
3762 output
[j
].swizzle_z
= 4; /* 0 */
3763 output
[j
].swizzle_w
= 4; /* 0 */
3768 case PIPE_SHADER_FRAGMENT
:
3769 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3770 /* never export more colors than the number of CBs */
3771 if (shader
->output
[i
].sid
>= max_color_exports
) {
3776 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3777 output
[j
].array_base
= shader
->output
[i
].sid
;
3778 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3779 shader
->nr_ps_color_exports
++;
3780 if (shader
->fs_write_all
&& (rscreen
->b
.chip_class
>= EVERGREEN
)) {
3781 for (k
= 1; k
< max_color_exports
; k
++) {
3783 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3784 output
[j
].gpr
= shader
->output
[i
].gpr
;
3785 output
[j
].elem_size
= 3;
3786 output
[j
].swizzle_x
= 0;
3787 output
[j
].swizzle_y
= 1;
3788 output
[j
].swizzle_z
= 2;
3789 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3790 output
[j
].burst_count
= 1;
3791 output
[j
].array_base
= k
;
3792 output
[j
].op
= CF_OP_EXPORT
;
3793 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3794 shader
->nr_ps_color_exports
++;
3797 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
3798 output
[j
].array_base
= 61;
3799 output
[j
].swizzle_x
= 2;
3800 output
[j
].swizzle_y
= 7;
3801 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3802 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3803 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
3804 output
[j
].array_base
= 61;
3805 output
[j
].swizzle_x
= 7;
3806 output
[j
].swizzle_y
= 1;
3807 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3808 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3809 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
3810 output
[j
].array_base
= 61;
3811 output
[j
].swizzle_x
= 7;
3812 output
[j
].swizzle_y
= 7;
3813 output
[j
].swizzle_z
= 0;
3814 output
[j
].swizzle_w
= 7;
3815 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3817 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
3822 case PIPE_SHADER_TESS_CTRL
:
3825 R600_ERR("unsupported processor type %d\n", ctx
.type
);
3830 if (output
[j
].type
== 0xffffffff) {
3831 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3832 output
[j
].array_base
= next_param_base
++;
3836 /* add fake position export */
3837 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && pos_emitted
== false) {
3838 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3840 output
[j
].elem_size
= 3;
3841 output
[j
].swizzle_x
= 7;
3842 output
[j
].swizzle_y
= 7;
3843 output
[j
].swizzle_z
= 7;
3844 output
[j
].swizzle_w
= 7;
3845 output
[j
].burst_count
= 1;
3846 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3847 output
[j
].array_base
= 60;
3848 output
[j
].op
= CF_OP_EXPORT
;
3852 /* add fake param output for vertex shader if no param is exported */
3853 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && next_param_base
== 0) {
3854 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3856 output
[j
].elem_size
= 3;
3857 output
[j
].swizzle_x
= 7;
3858 output
[j
].swizzle_y
= 7;
3859 output
[j
].swizzle_z
= 7;
3860 output
[j
].swizzle_w
= 7;
3861 output
[j
].burst_count
= 1;
3862 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3863 output
[j
].array_base
= 0;
3864 output
[j
].op
= CF_OP_EXPORT
;
3868 /* add fake pixel export */
3869 if (ctx
.type
== PIPE_SHADER_FRAGMENT
&& shader
->nr_ps_color_exports
== 0) {
3870 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3872 output
[j
].elem_size
= 3;
3873 output
[j
].swizzle_x
= 7;
3874 output
[j
].swizzle_y
= 7;
3875 output
[j
].swizzle_z
= 7;
3876 output
[j
].swizzle_w
= 7;
3877 output
[j
].burst_count
= 1;
3878 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3879 output
[j
].array_base
= 0;
3880 output
[j
].op
= CF_OP_EXPORT
;
3882 shader
->nr_ps_color_exports
++;
3887 /* set export done on last export of each type */
3888 for (k
= noutput
- 1, output_done
= 0; k
>= 0; k
--) {
3889 if (!(output_done
& (1 << output
[k
].type
))) {
3890 output_done
|= (1 << output
[k
].type
);
3891 output
[k
].op
= CF_OP_EXPORT_DONE
;
3894 /* add output to bytecode */
3895 for (i
= 0; i
< noutput
; i
++) {
3896 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
3902 /* add program end */
3903 if (ctx
.bc
->chip_class
== CAYMAN
)
3904 cm_bytecode_add_cf_end(ctx
.bc
);
3906 const struct cf_op_info
*last
= NULL
;
3908 if (ctx
.bc
->cf_last
)
3909 last
= r600_isa_cf(ctx
.bc
->cf_last
->op
);
3911 /* alu clause instructions don't have EOP bit, so add NOP */
3912 if (!last
|| last
->flags
& CF_ALU
|| ctx
.bc
->cf_last
->op
== CF_OP_LOOP_END
|| ctx
.bc
->cf_last
->op
== CF_OP_POP
)
3913 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
3915 ctx
.bc
->cf_last
->end_of_program
= 1;
3918 /* check GPR limit - we have 124 = 128 - 4
3919 * (4 are reserved as alu clause temporary registers) */
3920 if (ctx
.bc
->ngpr
> 124) {
3921 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx
.bc
->ngpr
);
3926 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3927 if ((r
= generate_gs_copy_shader(rctx
, pipeshader
, &so
)))
3932 tgsi_parse_free(&ctx
.parse
);
3936 tgsi_parse_free(&ctx
.parse
);
3940 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
3942 const unsigned tgsi_opcode
=
3943 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3944 R600_ERR("%s tgsi opcode unsupported\n",
3945 tgsi_get_opcode_name(tgsi_opcode
));
3949 static int tgsi_end(struct r600_shader_ctx
*ctx UNUSED
)
3954 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
3955 const struct r600_shader_src
*shader_src
,
3958 bc_src
->sel
= shader_src
->sel
;
3959 bc_src
->chan
= shader_src
->swizzle
[chan
];
3960 bc_src
->neg
= shader_src
->neg
;
3961 bc_src
->abs
= shader_src
->abs
;
3962 bc_src
->rel
= shader_src
->rel
;
3963 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
3964 bc_src
->kc_bank
= shader_src
->kc_bank
;
3965 bc_src
->kc_rel
= shader_src
->kc_rel
;
3968 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
3974 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
3976 bc_src
->neg
= !bc_src
->neg
;
3979 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
3980 const struct tgsi_full_dst_register
*tgsi_dst
,
3982 struct r600_bytecode_alu_dst
*r600_dst
)
3984 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3986 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
3987 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
3988 r600_dst
->chan
= swizzle
;
3989 r600_dst
->write
= 1;
3990 if (inst
->Instruction
.Saturate
) {
3991 r600_dst
->clamp
= 1;
3993 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
3994 if (tgsi_dst
->Register
.File
== TGSI_FILE_OUTPUT
) {
3998 if (tgsi_dst
->Register
.Indirect
)
3999 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
4003 static int tgsi_op2_64_params(struct r600_shader_ctx
*ctx
, bool singledest
, bool swap
, int dest_temp
, int op_override
)
4005 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4006 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4007 struct r600_bytecode_alu alu
;
4008 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
4010 int swizzle_x
= inst
->Src
[0].Register
.SwizzleX
;
4013 switch (write_mask
) {
4015 if (swizzle_x
== 2) {
4022 if (swizzle_x
== 2) {
4031 if (swizzle_x
== 0) {
4038 if (swizzle_x
== 0) {
4049 lasti
= tgsi_last_instruction(write_mask
);
4050 for (i
= 0; i
<= lasti
; i
++) {
4052 if (!(write_mask
& (1 << i
)))
4055 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4058 if (use_tmp
|| dest_temp
) {
4059 alu
.dst
.sel
= use_tmp
? ctx
->temp_reg
: dest_temp
;
4063 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4065 if (i
== 1 || i
== 3)
4068 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4070 alu
.op
= op_override
? op_override
: ctx
->inst_info
->op
;
4071 if (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DABS
) {
4072 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4074 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4075 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
4078 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], fp64_switch(i
));
4079 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], fp64_switch(i
));
4082 /* handle some special cases */
4083 if (i
== 1 || i
== 3) {
4084 switch (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
) {
4085 case TGSI_OPCODE_DABS
:
4086 r600_bytecode_src_set_abs(&alu
.src
[0]);
4095 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4101 write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4103 lasti
= tgsi_last_instruction(write_mask
);
4104 /* move result from temp to dst */
4105 for (i
= 0; i
<= lasti
; i
++) {
4106 if (!(write_mask
& (1 << i
)))
4109 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4110 alu
.op
= ALU_OP1_MOV
;
4113 alu
.dst
.sel
= dest_temp
;
4117 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4118 alu
.src
[0].sel
= ctx
->temp_reg
;
4119 alu
.src
[0].chan
= use_tmp
- 1;
4120 alu
.last
= (i
== lasti
);
4122 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4130 static int tgsi_op2_64(struct r600_shader_ctx
*ctx
)
4132 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4133 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4134 /* confirm writemasking */
4135 if ((write_mask
& 0x3) != 0x3 &&
4136 (write_mask
& 0xc) != 0xc) {
4137 fprintf(stderr
, "illegal writemask for 64-bit: 0x%x\n", write_mask
);
4140 return tgsi_op2_64_params(ctx
, false, false, 0, 0);
4143 static int tgsi_op2_64_single_dest(struct r600_shader_ctx
*ctx
)
4145 return tgsi_op2_64_params(ctx
, true, false, 0, 0);
4148 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx
*ctx
)
4150 return tgsi_op2_64_params(ctx
, true, true, 0, 0);
4153 static int tgsi_op3_64(struct r600_shader_ctx
*ctx
)
4155 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4156 struct r600_bytecode_alu alu
;
4159 int tmp
= r600_get_temp(ctx
);
4161 for (i
= 0; i
< lasti
+ 1; i
++) {
4163 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4164 alu
.op
= ctx
->inst_info
->op
;
4165 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4166 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
== 3 ? 0 : 1);
4169 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
))
4170 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4179 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4186 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
4188 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4189 struct r600_bytecode_alu alu
;
4190 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4191 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
4192 /* use temp register if trans_only and more than one dst component */
4193 int use_tmp
= trans_only
&& (write_mask
^ (1 << lasti
));
4194 unsigned op
= ctx
->inst_info
->op
;
4196 if (op
== ALU_OP2_MUL_IEEE
&&
4197 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
4200 for (i
= 0; i
<= lasti
; i
++) {
4201 if (!(write_mask
& (1 << i
)))
4204 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4206 alu
.dst
.sel
= ctx
->temp_reg
;
4210 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4214 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4215 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
4218 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
4219 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4221 if (i
== lasti
|| trans_only
) {
4224 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4230 /* move result from temp to dst */
4231 for (i
= 0; i
<= lasti
; i
++) {
4232 if (!(write_mask
& (1 << i
)))
4235 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4236 alu
.op
= ALU_OP1_MOV
;
4237 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4238 alu
.src
[0].sel
= ctx
->temp_reg
;
4239 alu
.src
[0].chan
= i
;
4240 alu
.last
= (i
== lasti
);
4242 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4250 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
4252 return tgsi_op2_s(ctx
, 0, 0);
4255 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
4257 return tgsi_op2_s(ctx
, 1, 0);
4260 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
4262 return tgsi_op2_s(ctx
, 0, 1);
4265 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
4267 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4268 struct r600_bytecode_alu alu
;
4270 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4272 for (i
= 0; i
< lasti
+ 1; i
++) {
4274 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4276 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4277 alu
.op
= ctx
->inst_info
->op
;
4279 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4281 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4283 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4288 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4296 static int tgsi_dneg(struct r600_shader_ctx
*ctx
)
4298 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4299 struct r600_bytecode_alu alu
;
4301 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4303 for (i
= 0; i
< lasti
+ 1; i
++) {
4305 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4307 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4308 alu
.op
= ALU_OP1_MOV
;
4310 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4312 if (i
== 1 || i
== 3)
4313 r600_bytecode_src_toggle_neg(&alu
.src
[0]);
4314 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4319 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4327 static int tgsi_dfracexp(struct r600_shader_ctx
*ctx
)
4329 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4330 struct r600_bytecode_alu alu
;
4331 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4334 for (i
= 0; i
<= 3; i
++) {
4335 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4336 alu
.op
= ctx
->inst_info
->op
;
4338 alu
.dst
.sel
= ctx
->temp_reg
;
4341 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4342 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
4348 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4353 /* Replicate significand result across channels. */
4354 for (i
= 0; i
<= 3; i
++) {
4355 if (!(write_mask
& (1 << i
)))
4358 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4359 alu
.op
= ALU_OP1_MOV
;
4360 alu
.src
[0].chan
= (i
& 1) + 2;
4361 alu
.src
[0].sel
= ctx
->temp_reg
;
4363 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4366 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4371 for (i
= 0; i
<= 3; i
++) {
4372 if (inst
->Dst
[1].Register
.WriteMask
& (1 << i
)) {
4373 /* MOV third channels to writemask dst1 */
4374 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4375 alu
.op
= ALU_OP1_MOV
;
4376 alu
.src
[0].chan
= 1;
4377 alu
.src
[0].sel
= ctx
->temp_reg
;
4379 tgsi_dst(ctx
, &inst
->Dst
[1], i
, &alu
.dst
);
4381 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4391 static int egcm_int_to_double(struct r600_shader_ctx
*ctx
)
4393 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4394 struct r600_bytecode_alu alu
;
4396 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4398 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_I2D
||
4399 inst
->Instruction
.Opcode
== TGSI_OPCODE_U2D
);
4401 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4402 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4403 alu
.op
= ctx
->inst_info
->op
;
4405 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4406 alu
.dst
.sel
= ctx
->temp_reg
;
4411 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4416 for (i
= 0; i
<= lasti
; i
++) {
4417 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4418 alu
.op
= ALU_OP1_FLT32_TO_FLT64
;
4420 alu
.src
[0].chan
= i
/2;
4422 alu
.src
[0].sel
= ctx
->temp_reg
;
4424 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
4425 alu
.src
[0].value
= 0x0;
4427 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4428 alu
.last
= i
== lasti
;
4430 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4438 static int egcm_double_to_int(struct r600_shader_ctx
*ctx
)
4440 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4441 struct r600_bytecode_alu alu
;
4443 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4444 int treg
= r600_get_temp(ctx
);
4445 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_D2I
||
4446 inst
->Instruction
.Opcode
== TGSI_OPCODE_D2U
);
4448 /* do a 64->32 into a temp register */
4449 r
= tgsi_op2_64_params(ctx
, true, false, treg
, ALU_OP1_FLT64_TO_FLT32
);
4453 for (i
= 0; i
<= lasti
; i
++) {
4454 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4456 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4457 alu
.op
= ctx
->inst_info
->op
;
4459 alu
.src
[0].chan
= i
;
4460 alu
.src
[0].sel
= treg
;
4461 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4462 alu
.last
= (i
== lasti
);
4464 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4472 static int cayman_emit_unary_double_raw(struct r600_bytecode
*bc
,
4475 struct r600_shader_src
*src
,
4478 struct r600_bytecode_alu alu
;
4479 const int last_slot
= 3;
4482 /* these have to write the result to X/Y by the looks of it */
4483 for (int i
= 0 ; i
< last_slot
; i
++) {
4484 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4487 r600_bytecode_src(&alu
.src
[0], src
, 1);
4488 r600_bytecode_src(&alu
.src
[1], src
, 0);
4491 r600_bytecode_src_set_abs(&alu
.src
[1]);
4493 alu
.dst
.sel
= dst_reg
;
4495 alu
.dst
.write
= (i
== 0 || i
== 1);
4497 if (bc
->chip_class
!= CAYMAN
|| i
== last_slot
- 1)
4499 r
= r600_bytecode_add_alu(bc
, &alu
);
4507 static int cayman_emit_double_instr(struct r600_shader_ctx
*ctx
)
4509 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4511 struct r600_bytecode_alu alu
;
4512 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4513 int t1
= ctx
->temp_reg
;
4515 /* should only be one src regs */
4516 assert(inst
->Instruction
.NumSrcRegs
== 1);
4518 /* only support one double at a time */
4519 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4520 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4522 r
= cayman_emit_unary_double_raw(
4523 ctx
->bc
, ctx
->inst_info
->op
, t1
,
4525 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DRSQ
||
4526 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DSQRT
);
4530 for (i
= 0 ; i
<= lasti
; i
++) {
4531 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4533 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4534 alu
.op
= ALU_OP1_MOV
;
4535 alu
.src
[0].sel
= t1
;
4536 alu
.src
[0].chan
= (i
== 0 || i
== 2) ? 0 : 1;
4537 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4541 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4548 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
4550 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4552 struct r600_bytecode_alu alu
;
4553 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4555 for (i
= 0 ; i
< last_slot
; i
++) {
4556 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4557 alu
.op
= ctx
->inst_info
->op
;
4558 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4559 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
4561 /* RSQ should take the absolute value of src */
4562 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_RSQ
) {
4563 r600_bytecode_src_set_abs(&alu
.src
[j
]);
4566 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4567 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4569 if (i
== last_slot
- 1)
4571 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4578 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
4580 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4582 struct r600_bytecode_alu alu
;
4583 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4584 int t1
= ctx
->temp_reg
;
4586 for (k
= 0; k
<= lasti
; k
++) {
4587 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
4590 for (i
= 0 ; i
< 4; i
++) {
4591 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4592 alu
.op
= ctx
->inst_info
->op
;
4593 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4594 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
4598 alu
.dst
.write
= (i
== k
);
4601 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4607 for (i
= 0 ; i
<= lasti
; i
++) {
4608 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4610 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4611 alu
.op
= ALU_OP1_MOV
;
4612 alu
.src
[0].sel
= t1
;
4613 alu
.src
[0].chan
= i
;
4614 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4618 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4627 static int cayman_mul_double_instr(struct r600_shader_ctx
*ctx
)
4629 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4631 struct r600_bytecode_alu alu
;
4632 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4633 int t1
= ctx
->temp_reg
;
4635 /* t1 would get overwritten below if we actually tried to
4636 * multiply two pairs of doubles at a time. */
4637 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4638 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4640 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4642 for (i
= 0; i
< 4; i
++) {
4643 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4644 alu
.op
= ctx
->inst_info
->op
;
4645 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4646 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
* 2 + ((i
== 3) ? 0 : 1));
4653 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4658 for (i
= 0; i
<= lasti
; i
++) {
4659 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4661 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4662 alu
.op
= ALU_OP1_MOV
;
4663 alu
.src
[0].sel
= t1
;
4664 alu
.src
[0].chan
= i
;
4665 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4669 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4678 * Emit RECIP_64 + MUL_64 to implement division.
4680 static int cayman_ddiv_instr(struct r600_shader_ctx
*ctx
)
4682 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4684 struct r600_bytecode_alu alu
;
4685 int t1
= ctx
->temp_reg
;
4688 /* Only support one double at a time. This is the same constraint as
4689 * in DMUL lowering. */
4690 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4691 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4693 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4695 r
= cayman_emit_unary_double_raw(ctx
->bc
, ALU_OP2_RECIP_64
, t1
, &ctx
->src
[1], false);
4699 for (int i
= 0; i
< 4; i
++) {
4700 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4701 alu
.op
= ALU_OP2_MUL_64
;
4703 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], k
* 2 + ((i
== 3) ? 0 : 1));
4705 alu
.src
[1].sel
= t1
;
4706 alu
.src
[1].chan
= (i
== 3) ? 0 : 1;
4713 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4718 for (int i
= 0; i
< 2; i
++) {
4719 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4720 alu
.op
= ALU_OP1_MOV
;
4721 alu
.src
[0].sel
= t1
;
4722 alu
.src
[0].chan
= i
;
4723 tgsi_dst(ctx
, &inst
->Dst
[0], k
* 2 + i
, &alu
.dst
);
4727 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4735 * r600 - trunc to -PI..PI range
4736 * r700 - normalize by dividing by 2PI
4739 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
4742 struct r600_bytecode_alu alu
;
4744 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4745 alu
.op
= ALU_OP3_MULADD
;
4749 alu
.dst
.sel
= ctx
->temp_reg
;
4752 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4754 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4755 alu
.src
[1].chan
= 0;
4756 alu
.src
[1].value
= u_bitcast_f2u(0.5f
* M_1_PI
);
4757 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4758 alu
.src
[2].chan
= 0;
4760 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4764 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4765 alu
.op
= ALU_OP1_FRACT
;
4768 alu
.dst
.sel
= ctx
->temp_reg
;
4771 alu
.src
[0].sel
= ctx
->temp_reg
;
4772 alu
.src
[0].chan
= 0;
4774 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4778 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4779 alu
.op
= ALU_OP3_MULADD
;
4783 alu
.dst
.sel
= ctx
->temp_reg
;
4786 alu
.src
[0].sel
= ctx
->temp_reg
;
4787 alu
.src
[0].chan
= 0;
4789 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4790 alu
.src
[1].chan
= 0;
4791 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
4792 alu
.src
[2].chan
= 0;
4794 if (ctx
->bc
->chip_class
== R600
) {
4795 alu
.src
[1].value
= u_bitcast_f2u(2.0f
* M_PI
);
4796 alu
.src
[2].value
= u_bitcast_f2u(-M_PI
);
4798 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4799 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4804 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4810 static int cayman_trig(struct r600_shader_ctx
*ctx
)
4812 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4813 struct r600_bytecode_alu alu
;
4814 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4817 r
= tgsi_setup_trig(ctx
);
4822 for (i
= 0; i
< last_slot
; i
++) {
4823 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4824 alu
.op
= ctx
->inst_info
->op
;
4827 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4828 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4830 alu
.src
[0].sel
= ctx
->temp_reg
;
4831 alu
.src
[0].chan
= 0;
4832 if (i
== last_slot
- 1)
4834 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4841 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
4843 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4844 struct r600_bytecode_alu alu
;
4846 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4848 r
= tgsi_setup_trig(ctx
);
4852 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4853 alu
.op
= ctx
->inst_info
->op
;
4855 alu
.dst
.sel
= ctx
->temp_reg
;
4858 alu
.src
[0].sel
= ctx
->temp_reg
;
4859 alu
.src
[0].chan
= 0;
4861 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4865 /* replicate result */
4866 for (i
= 0; i
< lasti
+ 1; i
++) {
4867 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4870 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4871 alu
.op
= ALU_OP1_MOV
;
4873 alu
.src
[0].sel
= ctx
->temp_reg
;
4874 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4877 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4884 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
4886 const struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4887 struct r600_bytecode_alu alu
;
4890 for (i
= 0; i
< 4; i
++) {
4891 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4892 alu
.op
= ctx
->inst_info
->op
;
4896 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4898 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_KILL
) {
4899 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4902 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4907 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4912 /* kill must be last in ALU */
4913 ctx
->bc
->force_add_cf
= 1;
4914 ctx
->shader
->uses_kill
= TRUE
;
4918 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
4920 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4921 struct r600_bytecode_alu alu
;
4924 /* tmp.x = max(src.y, 0.0) */
4925 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4926 alu
.op
= ALU_OP2_MAX
;
4927 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
4928 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4929 alu
.src
[1].chan
= 1;
4931 alu
.dst
.sel
= ctx
->temp_reg
;
4936 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4940 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
4946 if (ctx
->bc
->chip_class
== CAYMAN
) {
4947 for (i
= 0; i
< 3; i
++) {
4948 /* tmp.z = log(tmp.x) */
4949 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4950 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4951 alu
.src
[0].sel
= ctx
->temp_reg
;
4952 alu
.src
[0].chan
= 0;
4953 alu
.dst
.sel
= ctx
->temp_reg
;
4961 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4966 /* tmp.z = log(tmp.x) */
4967 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4968 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4969 alu
.src
[0].sel
= ctx
->temp_reg
;
4970 alu
.src
[0].chan
= 0;
4971 alu
.dst
.sel
= ctx
->temp_reg
;
4975 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4980 chan
= alu
.dst
.chan
;
4983 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4984 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4985 alu
.op
= ALU_OP3_MUL_LIT
;
4986 alu
.src
[0].sel
= sel
;
4987 alu
.src
[0].chan
= chan
;
4988 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
4989 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
4990 alu
.dst
.sel
= ctx
->temp_reg
;
4995 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4999 if (ctx
->bc
->chip_class
== CAYMAN
) {
5000 for (i
= 0; i
< 3; i
++) {
5001 /* dst.z = exp(tmp.x) */
5002 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5003 alu
.op
= ALU_OP1_EXP_IEEE
;
5004 alu
.src
[0].sel
= ctx
->temp_reg
;
5005 alu
.src
[0].chan
= 0;
5006 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5012 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5017 /* dst.z = exp(tmp.x) */
5018 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5019 alu
.op
= ALU_OP1_EXP_IEEE
;
5020 alu
.src
[0].sel
= ctx
->temp_reg
;
5021 alu
.src
[0].chan
= 0;
5022 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
5024 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5031 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5032 alu
.op
= ALU_OP1_MOV
;
5033 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
5034 alu
.src
[0].chan
= 0;
5035 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
5036 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
5037 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5041 /* dst.y = max(src.x, 0.0) */
5042 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5043 alu
.op
= ALU_OP2_MAX
;
5044 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5045 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
5046 alu
.src
[1].chan
= 0;
5047 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
5048 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
5049 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5054 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5055 alu
.op
= ALU_OP1_MOV
;
5056 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
5057 alu
.src
[0].chan
= 0;
5058 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
5059 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
5061 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5068 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
5070 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5071 struct r600_bytecode_alu alu
;
5074 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5076 alu
.op
= ALU_OP1_RECIPSQRT_IEEE
;
5078 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
5079 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
5080 r600_bytecode_src_set_abs(&alu
.src
[i
]);
5082 alu
.dst
.sel
= ctx
->temp_reg
;
5085 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5088 /* replicate result */
5089 return tgsi_helper_tempx_replicate(ctx
);
5092 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
5094 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5095 struct r600_bytecode_alu alu
;
5098 for (i
= 0; i
< 4; i
++) {
5099 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5100 alu
.src
[0].sel
= ctx
->temp_reg
;
5101 alu
.op
= ALU_OP1_MOV
;
5103 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5104 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
5107 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5114 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
5116 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5117 struct r600_bytecode_alu alu
;
5120 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5121 alu
.op
= ctx
->inst_info
->op
;
5122 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
5123 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
5125 alu
.dst
.sel
= ctx
->temp_reg
;
5128 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5131 /* replicate result */
5132 return tgsi_helper_tempx_replicate(ctx
);
5135 static int cayman_pow(struct r600_shader_ctx
*ctx
)
5137 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5139 struct r600_bytecode_alu alu
;
5140 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
5142 for (i
= 0; i
< 3; i
++) {
5143 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5144 alu
.op
= ALU_OP1_LOG_IEEE
;
5145 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5146 alu
.dst
.sel
= ctx
->temp_reg
;
5151 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5157 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5158 alu
.op
= ALU_OP2_MUL
;
5159 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5160 alu
.src
[1].sel
= ctx
->temp_reg
;
5161 alu
.dst
.sel
= ctx
->temp_reg
;
5164 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5168 for (i
= 0; i
< last_slot
; i
++) {
5169 /* POW(a,b) = EXP2(b * LOG2(a))*/
5170 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5171 alu
.op
= ALU_OP1_EXP_IEEE
;
5172 alu
.src
[0].sel
= ctx
->temp_reg
;
5174 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5175 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
5176 if (i
== last_slot
- 1)
5178 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5185 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
5187 struct r600_bytecode_alu alu
;
5191 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5192 alu
.op
= ALU_OP1_LOG_IEEE
;
5193 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5194 alu
.dst
.sel
= ctx
->temp_reg
;
5197 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5201 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5202 alu
.op
= ALU_OP2_MUL
;
5203 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5204 alu
.src
[1].sel
= ctx
->temp_reg
;
5205 alu
.dst
.sel
= ctx
->temp_reg
;
5208 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5211 /* POW(a,b) = EXP2(b * LOG2(a))*/
5212 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5213 alu
.op
= ALU_OP1_EXP_IEEE
;
5214 alu
.src
[0].sel
= ctx
->temp_reg
;
5215 alu
.dst
.sel
= ctx
->temp_reg
;
5218 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5221 return tgsi_helper_tempx_replicate(ctx
);
5224 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
5226 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5227 struct r600_bytecode_alu alu
;
5229 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5230 int tmp0
= ctx
->temp_reg
;
5231 int tmp1
= r600_get_temp(ctx
);
5232 int tmp2
= r600_get_temp(ctx
);
5233 int tmp3
= r600_get_temp(ctx
);
5236 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5238 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5239 * 2. tmp0.z = lo (tmp0.x * src2)
5240 * 3. tmp0.w = -tmp0.z
5241 * 4. tmp0.y = hi (tmp0.x * src2)
5242 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5243 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5244 * 7. tmp1.x = tmp0.x - tmp0.w
5245 * 8. tmp1.y = tmp0.x + tmp0.w
5246 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5247 * 10. tmp0.z = hi(tmp0.x * src1) = q
5248 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5250 * 12. tmp0.w = src1 - tmp0.y = r
5251 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5252 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5256 * 15. tmp1.z = tmp0.z + 1 = q + 1
5257 * 16. tmp1.w = tmp0.z - 1 = q - 1
5261 * 15. tmp1.z = tmp0.w - src2 = r - src2
5262 * 16. tmp1.w = tmp0.w + src2 = r + src2
5266 * 17. tmp1.x = tmp1.x & tmp1.y
5268 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5269 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5271 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5272 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5276 * Same as unsigned, using abs values of the operands,
5277 * and fixing the sign of the result in the end.
5280 for (i
= 0; i
< 4; i
++) {
5281 if (!(write_mask
& (1<<i
)))
5286 /* tmp2.x = -src0 */
5287 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5288 alu
.op
= ALU_OP2_SUB_INT
;
5294 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5296 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5299 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5302 /* tmp2.y = -src1 */
5303 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5304 alu
.op
= ALU_OP2_SUB_INT
;
5310 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5312 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5315 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5318 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5319 /* it will be a sign of the quotient */
5322 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5323 alu
.op
= ALU_OP2_XOR_INT
;
5329 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5330 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5333 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5337 /* tmp2.x = |src0| */
5338 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5339 alu
.op
= ALU_OP3_CNDGE_INT
;
5346 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5347 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5348 alu
.src
[2].sel
= tmp2
;
5349 alu
.src
[2].chan
= 0;
5352 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5355 /* tmp2.y = |src1| */
5356 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5357 alu
.op
= ALU_OP3_CNDGE_INT
;
5364 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5365 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5366 alu
.src
[2].sel
= tmp2
;
5367 alu
.src
[2].chan
= 1;
5370 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5375 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5376 if (ctx
->bc
->chip_class
== CAYMAN
) {
5377 /* tmp3.x = u2f(src2) */
5378 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5379 alu
.op
= ALU_OP1_UINT_TO_FLT
;
5386 alu
.src
[0].sel
= tmp2
;
5387 alu
.src
[0].chan
= 1;
5389 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5393 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5396 /* tmp0.x = recip(tmp3.x) */
5397 for (j
= 0 ; j
< 3; j
++) {
5398 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5399 alu
.op
= ALU_OP1_RECIP_IEEE
;
5403 alu
.dst
.write
= (j
== 0);
5405 alu
.src
[0].sel
= tmp3
;
5406 alu
.src
[0].chan
= 0;
5410 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5414 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5415 alu
.op
= ALU_OP2_MUL
;
5417 alu
.src
[0].sel
= tmp0
;
5418 alu
.src
[0].chan
= 0;
5420 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5421 alu
.src
[1].value
= 0x4f800000;
5426 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5430 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5431 alu
.op
= ALU_OP1_FLT_TO_UINT
;
5437 alu
.src
[0].sel
= tmp3
;
5438 alu
.src
[0].chan
= 0;
5441 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5445 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5446 alu
.op
= ALU_OP1_RECIP_UINT
;
5453 alu
.src
[0].sel
= tmp2
;
5454 alu
.src
[0].chan
= 1;
5456 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5460 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5464 /* 2. tmp0.z = lo (tmp0.x * src2) */
5465 if (ctx
->bc
->chip_class
== CAYMAN
) {
5466 for (j
= 0 ; j
< 4; j
++) {
5467 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5468 alu
.op
= ALU_OP2_MULLO_UINT
;
5472 alu
.dst
.write
= (j
== 2);
5474 alu
.src
[0].sel
= tmp0
;
5475 alu
.src
[0].chan
= 0;
5477 alu
.src
[1].sel
= tmp2
;
5478 alu
.src
[1].chan
= 1;
5480 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5483 alu
.last
= (j
== 3);
5484 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5488 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5489 alu
.op
= ALU_OP2_MULLO_UINT
;
5495 alu
.src
[0].sel
= tmp0
;
5496 alu
.src
[0].chan
= 0;
5498 alu
.src
[1].sel
= tmp2
;
5499 alu
.src
[1].chan
= 1;
5501 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5505 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5509 /* 3. tmp0.w = -tmp0.z */
5510 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5511 alu
.op
= ALU_OP2_SUB_INT
;
5517 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5518 alu
.src
[1].sel
= tmp0
;
5519 alu
.src
[1].chan
= 2;
5522 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5525 /* 4. tmp0.y = hi (tmp0.x * src2) */
5526 if (ctx
->bc
->chip_class
== CAYMAN
) {
5527 for (j
= 0 ; j
< 4; j
++) {
5528 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5529 alu
.op
= ALU_OP2_MULHI_UINT
;
5533 alu
.dst
.write
= (j
== 1);
5535 alu
.src
[0].sel
= tmp0
;
5536 alu
.src
[0].chan
= 0;
5539 alu
.src
[1].sel
= tmp2
;
5540 alu
.src
[1].chan
= 1;
5542 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5544 alu
.last
= (j
== 3);
5545 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5549 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5550 alu
.op
= ALU_OP2_MULHI_UINT
;
5556 alu
.src
[0].sel
= tmp0
;
5557 alu
.src
[0].chan
= 0;
5560 alu
.src
[1].sel
= tmp2
;
5561 alu
.src
[1].chan
= 1;
5563 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5567 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5571 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5572 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5573 alu
.op
= ALU_OP3_CNDE_INT
;
5580 alu
.src
[0].sel
= tmp0
;
5581 alu
.src
[0].chan
= 1;
5582 alu
.src
[1].sel
= tmp0
;
5583 alu
.src
[1].chan
= 3;
5584 alu
.src
[2].sel
= tmp0
;
5585 alu
.src
[2].chan
= 2;
5588 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5591 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5592 if (ctx
->bc
->chip_class
== CAYMAN
) {
5593 for (j
= 0 ; j
< 4; j
++) {
5594 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5595 alu
.op
= ALU_OP2_MULHI_UINT
;
5599 alu
.dst
.write
= (j
== 3);
5601 alu
.src
[0].sel
= tmp0
;
5602 alu
.src
[0].chan
= 2;
5604 alu
.src
[1].sel
= tmp0
;
5605 alu
.src
[1].chan
= 0;
5607 alu
.last
= (j
== 3);
5608 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5612 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5613 alu
.op
= ALU_OP2_MULHI_UINT
;
5619 alu
.src
[0].sel
= tmp0
;
5620 alu
.src
[0].chan
= 2;
5622 alu
.src
[1].sel
= tmp0
;
5623 alu
.src
[1].chan
= 0;
5626 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5630 /* 7. tmp1.x = tmp0.x - tmp0.w */
5631 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5632 alu
.op
= ALU_OP2_SUB_INT
;
5638 alu
.src
[0].sel
= tmp0
;
5639 alu
.src
[0].chan
= 0;
5640 alu
.src
[1].sel
= tmp0
;
5641 alu
.src
[1].chan
= 3;
5644 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5647 /* 8. tmp1.y = tmp0.x + tmp0.w */
5648 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5649 alu
.op
= ALU_OP2_ADD_INT
;
5655 alu
.src
[0].sel
= tmp0
;
5656 alu
.src
[0].chan
= 0;
5657 alu
.src
[1].sel
= tmp0
;
5658 alu
.src
[1].chan
= 3;
5661 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5664 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5665 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5666 alu
.op
= ALU_OP3_CNDE_INT
;
5673 alu
.src
[0].sel
= tmp0
;
5674 alu
.src
[0].chan
= 1;
5675 alu
.src
[1].sel
= tmp1
;
5676 alu
.src
[1].chan
= 1;
5677 alu
.src
[2].sel
= tmp1
;
5678 alu
.src
[2].chan
= 0;
5681 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5684 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5685 if (ctx
->bc
->chip_class
== CAYMAN
) {
5686 for (j
= 0 ; j
< 4; j
++) {
5687 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5688 alu
.op
= ALU_OP2_MULHI_UINT
;
5692 alu
.dst
.write
= (j
== 2);
5694 alu
.src
[0].sel
= tmp0
;
5695 alu
.src
[0].chan
= 0;
5698 alu
.src
[1].sel
= tmp2
;
5699 alu
.src
[1].chan
= 0;
5701 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5704 alu
.last
= (j
== 3);
5705 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5709 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5710 alu
.op
= ALU_OP2_MULHI_UINT
;
5716 alu
.src
[0].sel
= tmp0
;
5717 alu
.src
[0].chan
= 0;
5720 alu
.src
[1].sel
= tmp2
;
5721 alu
.src
[1].chan
= 0;
5723 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5727 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5731 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5732 if (ctx
->bc
->chip_class
== CAYMAN
) {
5733 for (j
= 0 ; j
< 4; j
++) {
5734 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5735 alu
.op
= ALU_OP2_MULLO_UINT
;
5739 alu
.dst
.write
= (j
== 1);
5742 alu
.src
[0].sel
= tmp2
;
5743 alu
.src
[0].chan
= 1;
5745 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5748 alu
.src
[1].sel
= tmp0
;
5749 alu
.src
[1].chan
= 2;
5751 alu
.last
= (j
== 3);
5752 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5756 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5757 alu
.op
= ALU_OP2_MULLO_UINT
;
5764 alu
.src
[0].sel
= tmp2
;
5765 alu
.src
[0].chan
= 1;
5767 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5770 alu
.src
[1].sel
= tmp0
;
5771 alu
.src
[1].chan
= 2;
5774 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5778 /* 12. tmp0.w = src1 - tmp0.y = r */
5779 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5780 alu
.op
= ALU_OP2_SUB_INT
;
5787 alu
.src
[0].sel
= tmp2
;
5788 alu
.src
[0].chan
= 0;
5790 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5793 alu
.src
[1].sel
= tmp0
;
5794 alu
.src
[1].chan
= 1;
5797 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5800 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5801 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5802 alu
.op
= ALU_OP2_SETGE_UINT
;
5808 alu
.src
[0].sel
= tmp0
;
5809 alu
.src
[0].chan
= 3;
5811 alu
.src
[1].sel
= tmp2
;
5812 alu
.src
[1].chan
= 1;
5814 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5818 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5821 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5822 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5823 alu
.op
= ALU_OP2_SETGE_UINT
;
5830 alu
.src
[0].sel
= tmp2
;
5831 alu
.src
[0].chan
= 0;
5833 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5836 alu
.src
[1].sel
= tmp0
;
5837 alu
.src
[1].chan
= 1;
5840 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5843 if (mod
) { /* UMOD */
5845 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5846 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5847 alu
.op
= ALU_OP2_SUB_INT
;
5853 alu
.src
[0].sel
= tmp0
;
5854 alu
.src
[0].chan
= 3;
5857 alu
.src
[1].sel
= tmp2
;
5858 alu
.src
[1].chan
= 1;
5860 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5864 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5867 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5868 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5869 alu
.op
= ALU_OP2_ADD_INT
;
5875 alu
.src
[0].sel
= tmp0
;
5876 alu
.src
[0].chan
= 3;
5878 alu
.src
[1].sel
= tmp2
;
5879 alu
.src
[1].chan
= 1;
5881 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5885 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5890 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5891 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5892 alu
.op
= ALU_OP2_ADD_INT
;
5898 alu
.src
[0].sel
= tmp0
;
5899 alu
.src
[0].chan
= 2;
5900 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
5903 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5906 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5907 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5908 alu
.op
= ALU_OP2_ADD_INT
;
5914 alu
.src
[0].sel
= tmp0
;
5915 alu
.src
[0].chan
= 2;
5916 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
5919 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5924 /* 17. tmp1.x = tmp1.x & tmp1.y */
5925 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5926 alu
.op
= ALU_OP2_AND_INT
;
5932 alu
.src
[0].sel
= tmp1
;
5933 alu
.src
[0].chan
= 0;
5934 alu
.src
[1].sel
= tmp1
;
5935 alu
.src
[1].chan
= 1;
5938 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5941 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5942 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5943 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5944 alu
.op
= ALU_OP3_CNDE_INT
;
5951 alu
.src
[0].sel
= tmp1
;
5952 alu
.src
[0].chan
= 0;
5953 alu
.src
[1].sel
= tmp0
;
5954 alu
.src
[1].chan
= mod
? 3 : 2;
5955 alu
.src
[2].sel
= tmp1
;
5956 alu
.src
[2].chan
= 2;
5959 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5962 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5963 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5964 alu
.op
= ALU_OP3_CNDE_INT
;
5972 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5975 alu
.src
[0].sel
= tmp1
;
5976 alu
.src
[0].chan
= 1;
5977 alu
.src
[1].sel
= tmp1
;
5978 alu
.src
[1].chan
= 3;
5979 alu
.src
[2].sel
= tmp0
;
5980 alu
.src
[2].chan
= 2;
5983 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5988 /* fix the sign of the result */
5992 /* tmp0.x = -tmp0.z */
5993 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5994 alu
.op
= ALU_OP2_SUB_INT
;
6000 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
6001 alu
.src
[1].sel
= tmp0
;
6002 alu
.src
[1].chan
= 2;
6005 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
6008 /* sign of the remainder is the same as the sign of src0 */
6009 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
6010 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6011 alu
.op
= ALU_OP3_CNDGE_INT
;
6014 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6016 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6017 alu
.src
[1].sel
= tmp0
;
6018 alu
.src
[1].chan
= 2;
6019 alu
.src
[2].sel
= tmp0
;
6020 alu
.src
[2].chan
= 0;
6023 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
6028 /* tmp0.x = -tmp0.z */
6029 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6030 alu
.op
= ALU_OP2_SUB_INT
;
6036 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
6037 alu
.src
[1].sel
= tmp0
;
6038 alu
.src
[1].chan
= 2;
6041 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
6044 /* fix the quotient sign (same as the sign of src0*src1) */
6045 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
6046 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6047 alu
.op
= ALU_OP3_CNDGE_INT
;
6050 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6052 alu
.src
[0].sel
= tmp2
;
6053 alu
.src
[0].chan
= 2;
6054 alu
.src
[1].sel
= tmp0
;
6055 alu
.src
[1].chan
= 2;
6056 alu
.src
[2].sel
= tmp0
;
6057 alu
.src
[2].chan
= 0;
6060 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
6068 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
6070 return tgsi_divmod(ctx
, 0, 0);
6073 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
6075 return tgsi_divmod(ctx
, 1, 0);
6078 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
6080 return tgsi_divmod(ctx
, 0, 1);
6083 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
6085 return tgsi_divmod(ctx
, 1, 1);
6089 static int tgsi_f2i(struct r600_shader_ctx
*ctx
)
6091 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6092 struct r600_bytecode_alu alu
;
6094 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6095 int last_inst
= tgsi_last_instruction(write_mask
);
6097 for (i
= 0; i
< 4; i
++) {
6098 if (!(write_mask
& (1<<i
)))
6101 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6102 alu
.op
= ALU_OP1_TRUNC
;
6104 alu
.dst
.sel
= ctx
->temp_reg
;
6108 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6111 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6116 for (i
= 0; i
< 4; i
++) {
6117 if (!(write_mask
& (1<<i
)))
6120 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6121 alu
.op
= ctx
->inst_info
->op
;
6123 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6125 alu
.src
[0].sel
= ctx
->temp_reg
;
6126 alu
.src
[0].chan
= i
;
6128 if (i
== last_inst
|| alu
.op
== ALU_OP1_FLT_TO_UINT
)
6130 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6138 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
6140 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6141 struct r600_bytecode_alu alu
;
6143 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6144 int last_inst
= tgsi_last_instruction(write_mask
);
6147 for (i
= 0; i
< 4; i
++) {
6148 if (!(write_mask
& (1<<i
)))
6151 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6152 alu
.op
= ALU_OP2_SUB_INT
;
6154 alu
.dst
.sel
= ctx
->temp_reg
;
6158 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6159 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
6163 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6168 /* dst = (src >= 0 ? src : tmp) */
6169 for (i
= 0; i
< 4; i
++) {
6170 if (!(write_mask
& (1<<i
)))
6173 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6174 alu
.op
= ALU_OP3_CNDGE_INT
;
6178 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6180 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6181 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6182 alu
.src
[2].sel
= ctx
->temp_reg
;
6183 alu
.src
[2].chan
= i
;
6187 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6194 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
6196 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6197 struct r600_bytecode_alu alu
;
6199 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6200 int last_inst
= tgsi_last_instruction(write_mask
);
6202 /* tmp = (src >= 0 ? src : -1) */
6203 for (i
= 0; i
< 4; i
++) {
6204 if (!(write_mask
& (1<<i
)))
6207 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6208 alu
.op
= ALU_OP3_CNDGE_INT
;
6211 alu
.dst
.sel
= ctx
->temp_reg
;
6215 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6216 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6217 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
6221 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6226 /* dst = (tmp > 0 ? 1 : tmp) */
6227 for (i
= 0; i
< 4; i
++) {
6228 if (!(write_mask
& (1<<i
)))
6231 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6232 alu
.op
= ALU_OP3_CNDGT_INT
;
6236 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6238 alu
.src
[0].sel
= ctx
->temp_reg
;
6239 alu
.src
[0].chan
= i
;
6241 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
6243 alu
.src
[2].sel
= ctx
->temp_reg
;
6244 alu
.src
[2].chan
= i
;
6248 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6257 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
6259 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6260 struct r600_bytecode_alu alu
;
6263 /* tmp = (src > 0 ? 1 : src) */
6264 for (i
= 0; i
< 4; i
++) {
6265 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6266 alu
.op
= ALU_OP3_CNDGT
;
6269 alu
.dst
.sel
= ctx
->temp_reg
;
6272 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6273 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6274 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6278 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6283 /* dst = (-tmp > 0 ? -1 : tmp) */
6284 for (i
= 0; i
< 4; i
++) {
6285 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6286 alu
.op
= ALU_OP3_CNDGT
;
6288 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6290 alu
.src
[0].sel
= ctx
->temp_reg
;
6291 alu
.src
[0].chan
= i
;
6294 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6297 alu
.src
[2].sel
= ctx
->temp_reg
;
6298 alu
.src
[2].chan
= i
;
6302 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6309 static int tgsi_bfi(struct r600_shader_ctx
*ctx
)
6311 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6312 struct r600_bytecode_alu alu
;
6315 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6316 int last_inst
= tgsi_last_instruction(write_mask
);
6318 t1
= r600_get_temp(ctx
);
6320 for (i
= 0; i
< 4; i
++) {
6321 if (!(write_mask
& (1<<i
)))
6324 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6325 alu
.op
= ALU_OP2_SETGE_INT
;
6326 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6327 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
6328 alu
.src
[1].value
= 32;
6329 alu
.dst
.sel
= ctx
->temp_reg
;
6332 alu
.last
= i
== last_inst
;
6333 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6338 for (i
= 0; i
< 4; i
++) {
6339 if (!(write_mask
& (1<<i
)))
6342 /* create mask tmp */
6343 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6344 alu
.op
= ALU_OP2_BFM_INT
;
6348 alu
.last
= i
== last_inst
;
6350 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6351 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6353 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6358 t2
= r600_get_temp(ctx
);
6360 for (i
= 0; i
< 4; i
++) {
6361 if (!(write_mask
& (1<<i
)))
6364 /* shift insert left */
6365 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6366 alu
.op
= ALU_OP2_LSHL_INT
;
6370 alu
.last
= i
== last_inst
;
6372 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
6373 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6375 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6380 for (i
= 0; i
< 4; i
++) {
6381 if (!(write_mask
& (1<<i
)))
6384 /* actual bitfield insert */
6385 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6386 alu
.op
= ALU_OP3_BFI_INT
;
6388 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6391 alu
.last
= i
== last_inst
;
6393 alu
.src
[0].sel
= t1
;
6394 alu
.src
[0].chan
= i
;
6395 alu
.src
[1].sel
= t2
;
6396 alu
.src
[1].chan
= i
;
6397 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6399 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6404 for (i
= 0; i
< 4; i
++) {
6405 if (!(write_mask
& (1<<i
)))
6407 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6408 alu
.op
= ALU_OP3_CNDE_INT
;
6410 alu
.src
[0].sel
= ctx
->temp_reg
;
6411 alu
.src
[0].chan
= i
;
6412 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
6414 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6416 alu
.src
[1].sel
= alu
.dst
.sel
;
6417 alu
.src
[1].chan
= i
;
6419 alu
.last
= i
== last_inst
;
6420 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6427 static int tgsi_msb(struct r600_shader_ctx
*ctx
)
6429 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6430 struct r600_bytecode_alu alu
;
6433 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6434 int last_inst
= tgsi_last_instruction(write_mask
);
6436 assert(ctx
->inst_info
->op
== ALU_OP1_FFBH_INT
||
6437 ctx
->inst_info
->op
== ALU_OP1_FFBH_UINT
);
6441 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6442 for (i
= 0; i
< 4; i
++) {
6443 if (!(write_mask
& (1<<i
)))
6446 /* t1 = FFBH_INT / FFBH_UINT */
6447 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6448 alu
.op
= ctx
->inst_info
->op
;
6452 alu
.last
= i
== last_inst
;
6454 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6456 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6461 t2
= r600_get_temp(ctx
);
6463 for (i
= 0; i
< 4; i
++) {
6464 if (!(write_mask
& (1<<i
)))
6468 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6469 alu
.op
= ALU_OP2_SUB_INT
;
6473 alu
.last
= i
== last_inst
;
6475 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
6476 alu
.src
[0].value
= 31;
6477 alu
.src
[1].sel
= t1
;
6478 alu
.src
[1].chan
= i
;
6480 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6485 for (i
= 0; i
< 4; i
++) {
6486 if (!(write_mask
& (1<<i
)))
6489 /* result = t1 >= 0 ? t2 : t1 */
6490 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6491 alu
.op
= ALU_OP3_CNDGE_INT
;
6493 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6496 alu
.last
= i
== last_inst
;
6498 alu
.src
[0].sel
= t1
;
6499 alu
.src
[0].chan
= i
;
6500 alu
.src
[1].sel
= t2
;
6501 alu
.src
[1].chan
= i
;
6502 alu
.src
[2].sel
= t1
;
6503 alu
.src
[2].chan
= i
;
6505 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6513 static int tgsi_interp_egcm(struct r600_shader_ctx
*ctx
)
6515 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6516 struct r600_bytecode_alu alu
;
6517 int r
, i
= 0, k
, interp_gpr
, interp_base_chan
, tmp
, lasti
;
6519 const int input
= inst
->Src
[0].Register
.Index
+ ctx
->shader
->nsys_inputs
;
6521 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
6523 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6524 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6525 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6526 location
= TGSI_INTERPOLATE_LOC_CENTER
; /* sample offset will be added explicitly */
6529 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
6532 k
= eg_get_interpolator_index(ctx
->shader
->input
[input
].interpolate
, location
);
6535 interp_gpr
= ctx
->eg_interpolators
[k
].ij_index
/ 2;
6536 interp_base_chan
= 2 * (ctx
->eg_interpolators
[k
].ij_index
% 2);
6538 /* NOTE: currently offset is not perspective correct */
6539 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6540 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6541 int sample_gpr
= -1;
6542 int gradientsH
, gradientsV
;
6543 struct r600_bytecode_tex tex
;
6545 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6546 sample_gpr
= load_sample_position(ctx
, &ctx
->src
[1], ctx
->src
[1].swizzle
[0]);
6549 gradientsH
= r600_get_temp(ctx
);
6550 gradientsV
= r600_get_temp(ctx
);
6551 for (i
= 0; i
< 2; i
++) {
6552 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
6553 tex
.op
= i
== 0 ? FETCH_OP_GET_GRADIENTS_H
: FETCH_OP_GET_GRADIENTS_V
;
6554 tex
.src_gpr
= interp_gpr
;
6555 tex
.src_sel_x
= interp_base_chan
+ 0;
6556 tex
.src_sel_y
= interp_base_chan
+ 1;
6559 tex
.dst_gpr
= i
== 0 ? gradientsH
: gradientsV
;
6564 tex
.inst_mod
= 1; // Use per pixel gradient calculation
6566 tex
.resource_id
= tex
.sampler_id
;
6567 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
6572 for (i
= 0; i
< 2; i
++) {
6573 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6574 alu
.op
= ALU_OP3_MULADD
;
6576 alu
.src
[0].sel
= gradientsH
;
6577 alu
.src
[0].chan
= i
;
6578 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6579 alu
.src
[1].sel
= sample_gpr
;
6580 alu
.src
[1].chan
= 2;
6583 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 0);
6585 alu
.src
[2].sel
= interp_gpr
;
6586 alu
.src
[2].chan
= interp_base_chan
+ i
;
6587 alu
.dst
.sel
= ctx
->temp_reg
;
6591 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6596 for (i
= 0; i
< 2; i
++) {
6597 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6598 alu
.op
= ALU_OP3_MULADD
;
6600 alu
.src
[0].sel
= gradientsV
;
6601 alu
.src
[0].chan
= i
;
6602 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6603 alu
.src
[1].sel
= sample_gpr
;
6604 alu
.src
[1].chan
= 3;
6607 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 1);
6609 alu
.src
[2].sel
= ctx
->temp_reg
;
6610 alu
.src
[2].chan
= i
;
6611 alu
.dst
.sel
= ctx
->temp_reg
;
6615 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6621 tmp
= r600_get_temp(ctx
);
6622 for (i
= 0; i
< 8; i
++) {
6623 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6624 alu
.op
= i
< 4 ? ALU_OP2_INTERP_ZW
: ALU_OP2_INTERP_XY
;
6627 if ((i
> 1 && i
< 6)) {
6633 alu
.dst
.chan
= i
% 4;
6635 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6636 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6637 alu
.src
[0].sel
= ctx
->temp_reg
;
6638 alu
.src
[0].chan
= 1 - (i
% 2);
6640 alu
.src
[0].sel
= interp_gpr
;
6641 alu
.src
[0].chan
= interp_base_chan
+ 1 - (i
% 2);
6643 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
6644 alu
.src
[1].chan
= 0;
6646 alu
.last
= i
% 4 == 3;
6647 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
6649 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6654 // INTERP can't swizzle dst
6655 lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6656 for (i
= 0; i
<= lasti
; i
++) {
6657 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6660 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6661 alu
.op
= ALU_OP1_MOV
;
6662 alu
.src
[0].sel
= tmp
;
6663 alu
.src
[0].chan
= ctx
->src
[0].swizzle
[i
];
6664 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6666 alu
.last
= i
== lasti
;
6667 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6676 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
6678 struct r600_bytecode_alu alu
;
6681 for (i
= 0; i
< 4; i
++) {
6682 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6683 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
6684 alu
.op
= ALU_OP0_NOP
;
6687 alu
.op
= ALU_OP1_MOV
;
6688 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6689 alu
.src
[0].sel
= ctx
->temp_reg
;
6690 alu
.src
[0].chan
= i
;
6695 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6702 static int tgsi_make_src_for_op3(struct r600_shader_ctx
*ctx
,
6703 unsigned temp
, int chan
,
6704 struct r600_bytecode_alu_src
*bc_src
,
6705 const struct r600_shader_src
*shader_src
)
6707 struct r600_bytecode_alu alu
;
6710 r600_bytecode_src(bc_src
, shader_src
, chan
);
6712 /* op3 operands don't support abs modifier */
6714 assert(temp
!=0); /* we actually need the extra register, make sure it is allocated. */
6715 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6716 alu
.op
= ALU_OP1_MOV
;
6718 alu
.dst
.chan
= chan
;
6721 alu
.src
[0] = *bc_src
;
6722 alu
.last
= true; // sufficient?
6723 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6727 memset(bc_src
, 0, sizeof(*bc_src
));
6729 bc_src
->chan
= chan
;
6734 static int tgsi_op3_dst(struct r600_shader_ctx
*ctx
, int dst
)
6736 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6737 struct r600_bytecode_alu alu
;
6739 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6741 unsigned op
= ctx
->inst_info
->op
;
6743 if (op
== ALU_OP3_MULADD_IEEE
&&
6744 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6745 op
= ALU_OP3_MULADD
;
6747 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6749 if (ctx
->src
[j
].abs
)
6750 temp_regs
[j
] = r600_get_temp(ctx
);
6752 for (i
= 0; i
< lasti
+ 1; i
++) {
6753 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6756 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6758 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6759 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[j
], i
, &alu
.src
[j
], &ctx
->src
[j
]);
6765 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6775 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6782 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
6784 return tgsi_op3_dst(ctx
, -1);
6787 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
6789 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6790 struct r600_bytecode_alu alu
;
6792 unsigned op
= ctx
->inst_info
->op
;
6793 if (op
== ALU_OP2_DOT4_IEEE
&&
6794 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6797 for (i
= 0; i
< 4; i
++) {
6798 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6800 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6801 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
6804 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6806 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
6807 /* handle some special cases */
6808 switch (inst
->Instruction
.Opcode
) {
6809 case TGSI_OPCODE_DP2
:
6811 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6812 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6815 case TGSI_OPCODE_DP3
:
6817 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6818 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6827 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6834 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
6837 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6838 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
6839 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
&&
6840 inst
->Src
[index
].Register
.File
!= TGSI_FILE_OUTPUT
) ||
6841 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
||
6842 (inst
->Src
[index
].Register
.File
== TGSI_FILE_INPUT
&& ctx
->type
== PIPE_SHADER_GEOMETRY
);
6845 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
6848 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6849 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
6852 static int do_vtx_fetch_inst(struct r600_shader_ctx
*ctx
, boolean src_requires_loading
)
6854 struct r600_bytecode_vtx vtx
;
6855 struct r600_bytecode_alu alu
;
6856 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6858 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6859 int sampler_index_mode
= inst
->Src
[1].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6861 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6862 if (src_requires_loading
) {
6863 for (i
= 0; i
< 4; i
++) {
6864 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6865 alu
.op
= ALU_OP1_MOV
;
6866 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6867 alu
.dst
.sel
= ctx
->temp_reg
;
6872 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6876 src_gpr
= ctx
->temp_reg
;
6879 memset(&vtx
, 0, sizeof(vtx
));
6880 vtx
.op
= FETCH_OP_VFETCH
;
6881 vtx
.buffer_id
= id
+ R600_MAX_CONST_BUFFERS
;
6882 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
6883 vtx
.src_gpr
= src_gpr
;
6884 vtx
.mega_fetch_count
= 16;
6885 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
6886 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
6887 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7; /* SEL_Y */
6888 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7; /* SEL_Z */
6889 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7; /* SEL_W */
6890 vtx
.use_const_fields
= 1;
6891 vtx
.buffer_index_mode
= sampler_index_mode
;
6893 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
6896 if (ctx
->bc
->chip_class
>= EVERGREEN
)
6899 for (i
= 0; i
< 4; i
++) {
6900 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6901 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6904 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6905 alu
.op
= ALU_OP2_AND_INT
;
6908 alu
.dst
.sel
= vtx
.dst_gpr
;
6911 alu
.src
[0].sel
= vtx
.dst_gpr
;
6912 alu
.src
[0].chan
= i
;
6914 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6915 alu
.src
[1].sel
+= (id
* 2);
6916 alu
.src
[1].chan
= i
% 4;
6917 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6921 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6926 if (inst
->Dst
[0].Register
.WriteMask
& 3) {
6927 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6928 alu
.op
= ALU_OP2_OR_INT
;
6931 alu
.dst
.sel
= vtx
.dst_gpr
;
6934 alu
.src
[0].sel
= vtx
.dst_gpr
;
6935 alu
.src
[0].chan
= 3;
6937 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
+ (id
* 2) + 1;
6938 alu
.src
[1].chan
= 0;
6939 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6942 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6949 static int r600_do_buffer_txq(struct r600_shader_ctx
*ctx
, int reg_idx
, int offset
)
6951 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6953 int id
= tgsi_tex_get_src_gpr(ctx
, reg_idx
) + offset
;
6954 int sampler_index_mode
= inst
->Src
[reg_idx
].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6956 if (ctx
->bc
->chip_class
< EVERGREEN
) {
6957 struct r600_bytecode_alu alu
;
6958 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6959 alu
.op
= ALU_OP1_MOV
;
6960 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6961 /* r600 we have them at channel 2 of the second dword */
6962 alu
.src
[0].sel
+= (id
* 2) + 1;
6963 alu
.src
[0].chan
= 1;
6964 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6965 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
6967 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6972 struct r600_bytecode_vtx vtx
;
6973 memset(&vtx
, 0, sizeof(vtx
));
6974 vtx
.op
= FETCH_OP_GDS_MIN_UINT
; /* aka GET_BUFFER_RESINFO */
6975 vtx
.buffer_id
= id
+ R600_MAX_CONST_BUFFERS
;
6976 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
6978 vtx
.mega_fetch_count
= 16; /* no idea here really... */
6979 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
6980 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
6981 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 4 : 7; /* SEL_Y */
6982 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 4 : 7; /* SEL_Z */
6983 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 4 : 7; /* SEL_W */
6984 vtx
.data_format
= FMT_32_32_32_32
;
6985 vtx
.buffer_index_mode
= sampler_index_mode
;
6987 if ((r
= r600_bytecode_add_vtx_tc(ctx
->bc
, &vtx
)))
6994 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
6996 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6997 struct r600_bytecode_tex tex
;
6998 struct r600_bytecode_alu alu
;
7002 bool read_compressed_msaa
= ctx
->bc
->has_compressed_msaa_texturing
&&
7003 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
7004 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
7005 inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
7007 bool txf_add_offsets
= inst
->Texture
.NumOffsets
&&
7008 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
7009 inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
;
7011 /* Texture fetch instructions can only use gprs as source.
7012 * Also they cannot negate the source or take the absolute value */
7013 const boolean src_requires_loading
= (inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQS
&&
7014 tgsi_tex_src_requires_loading(ctx
, 0)) ||
7015 read_compressed_msaa
|| txf_add_offsets
;
7017 boolean src_loaded
= FALSE
;
7018 unsigned sampler_src_reg
= 1;
7019 int8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
7020 boolean has_txq_cube_array_z
= false;
7021 unsigned sampler_index_mode
;
7023 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
7024 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7025 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)))
7026 if (inst
->Dst
[0].Register
.WriteMask
& 4) {
7027 ctx
->shader
->has_txq_cube_array_z_comp
= true;
7028 has_txq_cube_array_z
= true;
7031 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
7032 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7033 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
||
7034 inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
)
7035 sampler_src_reg
= 2;
7037 /* TGSI moves the sampler to src reg 3 for TXD */
7038 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
)
7039 sampler_src_reg
= 3;
7041 sampler_index_mode
= inst
->Src
[sampler_src_reg
].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7043 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
7045 if (inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
7046 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
7047 if (ctx
->bc
->chip_class
< EVERGREEN
)
7048 ctx
->shader
->uses_tex_buffers
= true;
7049 return r600_do_buffer_txq(ctx
, 1, 0);
7051 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
7052 if (ctx
->bc
->chip_class
< EVERGREEN
)
7053 ctx
->shader
->uses_tex_buffers
= true;
7054 return do_vtx_fetch_inst(ctx
, src_requires_loading
);
7058 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
7060 /* Add perspective divide */
7061 if (ctx
->bc
->chip_class
== CAYMAN
) {
7063 for (i
= 0; i
< 3; i
++) {
7064 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7065 alu
.op
= ALU_OP1_RECIP_IEEE
;
7066 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7068 alu
.dst
.sel
= ctx
->temp_reg
;
7074 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7081 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7082 alu
.op
= ALU_OP1_RECIP_IEEE
;
7083 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7085 alu
.dst
.sel
= ctx
->temp_reg
;
7086 alu
.dst
.chan
= out_chan
;
7089 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7094 for (i
= 0; i
< 3; i
++) {
7095 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7096 alu
.op
= ALU_OP2_MUL
;
7097 alu
.src
[0].sel
= ctx
->temp_reg
;
7098 alu
.src
[0].chan
= out_chan
;
7099 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
7100 alu
.dst
.sel
= ctx
->temp_reg
;
7103 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7107 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7108 alu
.op
= ALU_OP1_MOV
;
7109 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
7110 alu
.src
[0].chan
= 0;
7111 alu
.dst
.sel
= ctx
->temp_reg
;
7115 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7119 src_gpr
= ctx
->temp_reg
;
7123 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
7124 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7125 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7126 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
7127 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
) {
7129 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
7130 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
7132 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7133 for (i
= 0; i
< 4; i
++) {
7134 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7135 alu
.op
= ALU_OP2_CUBE
;
7136 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
7137 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
7138 alu
.dst
.sel
= ctx
->temp_reg
;
7143 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7148 /* tmp1.z = RCP_e(|tmp1.z|) */
7149 if (ctx
->bc
->chip_class
== CAYMAN
) {
7150 for (i
= 0; i
< 3; i
++) {
7151 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7152 alu
.op
= ALU_OP1_RECIP_IEEE
;
7153 alu
.src
[0].sel
= ctx
->temp_reg
;
7154 alu
.src
[0].chan
= 2;
7156 alu
.dst
.sel
= ctx
->temp_reg
;
7162 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7167 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7168 alu
.op
= ALU_OP1_RECIP_IEEE
;
7169 alu
.src
[0].sel
= ctx
->temp_reg
;
7170 alu
.src
[0].chan
= 2;
7172 alu
.dst
.sel
= ctx
->temp_reg
;
7176 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7181 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7182 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7183 * muladd has no writemask, have to use another temp
7185 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7186 alu
.op
= ALU_OP3_MULADD
;
7189 alu
.src
[0].sel
= ctx
->temp_reg
;
7190 alu
.src
[0].chan
= 0;
7191 alu
.src
[1].sel
= ctx
->temp_reg
;
7192 alu
.src
[1].chan
= 2;
7194 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
7195 alu
.src
[2].chan
= 0;
7196 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
7198 alu
.dst
.sel
= ctx
->temp_reg
;
7202 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7206 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7207 alu
.op
= ALU_OP3_MULADD
;
7210 alu
.src
[0].sel
= ctx
->temp_reg
;
7211 alu
.src
[0].chan
= 1;
7212 alu
.src
[1].sel
= ctx
->temp_reg
;
7213 alu
.src
[1].chan
= 2;
7215 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
7216 alu
.src
[2].chan
= 0;
7217 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
7219 alu
.dst
.sel
= ctx
->temp_reg
;
7224 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7227 /* write initial compare value into Z component
7228 - W src 0 for shadow cube
7229 - X src 1 for shadow cube array */
7230 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7231 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7232 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7233 alu
.op
= ALU_OP1_MOV
;
7234 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
7235 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7237 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7238 alu
.dst
.sel
= ctx
->temp_reg
;
7242 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7247 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7248 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7249 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7250 int mytmp
= r600_get_temp(ctx
);
7251 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7252 alu
.op
= ALU_OP1_MOV
;
7253 alu
.src
[0].sel
= ctx
->temp_reg
;
7254 alu
.src
[0].chan
= 3;
7255 alu
.dst
.sel
= mytmp
;
7259 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7263 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7264 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7265 alu
.op
= ALU_OP3_MULADD
;
7267 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7268 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7269 alu
.src
[1].chan
= 0;
7270 alu
.src
[1].value
= u_bitcast_f2u(8.0f
);
7271 alu
.src
[2].sel
= mytmp
;
7272 alu
.src
[2].chan
= 0;
7273 alu
.dst
.sel
= ctx
->temp_reg
;
7277 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7280 } else if (ctx
->bc
->chip_class
< EVERGREEN
) {
7281 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7282 tex
.op
= FETCH_OP_SET_CUBEMAP_INDEX
;
7283 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7284 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7285 tex
.src_gpr
= r600_get_temp(ctx
);
7290 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7291 tex
.coord_type_x
= 1;
7292 tex
.coord_type_y
= 1;
7293 tex
.coord_type_z
= 1;
7294 tex
.coord_type_w
= 1;
7295 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7296 alu
.op
= ALU_OP1_MOV
;
7297 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7298 alu
.dst
.sel
= tex
.src_gpr
;
7302 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7306 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7313 /* for cube forms of lod and bias we need to route things */
7314 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
||
7315 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
||
7316 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7317 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
7318 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7319 alu
.op
= ALU_OP1_MOV
;
7320 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7321 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
)
7322 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7324 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7325 alu
.dst
.sel
= ctx
->temp_reg
;
7329 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7335 src_gpr
= ctx
->temp_reg
;
7338 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
7339 int temp_h
= 0, temp_v
= 0;
7342 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7343 if (src_loaded
== TRUE
)
7347 for (i
= start_val
; i
< 3; i
++) {
7348 int treg
= r600_get_temp(ctx
);
7357 for (j
= 0; j
< 4; j
++) {
7358 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7359 alu
.op
= ALU_OP1_MOV
;
7360 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
7366 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7371 for (i
= 1; i
< 3; i
++) {
7372 /* set gradients h/v */
7373 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7374 tex
.op
= (i
== 1) ? FETCH_OP_SET_GRADIENTS_H
:
7375 FETCH_OP_SET_GRADIENTS_V
;
7376 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7377 tex
.sampler_index_mode
= sampler_index_mode
;
7378 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7379 tex
.resource_index_mode
= sampler_index_mode
;
7381 tex
.src_gpr
= (i
== 1) ? temp_h
: temp_v
;
7387 tex
.dst_gpr
= r600_get_temp(ctx
); /* just to avoid confusing the asm scheduler */
7388 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7389 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
7390 tex
.coord_type_x
= 1;
7391 tex
.coord_type_y
= 1;
7392 tex
.coord_type_z
= 1;
7393 tex
.coord_type_w
= 1;
7395 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7401 if (src_requires_loading
&& !src_loaded
) {
7402 for (i
= 0; i
< 4; i
++) {
7403 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7404 alu
.op
= ALU_OP1_MOV
;
7405 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
7406 alu
.dst
.sel
= ctx
->temp_reg
;
7411 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7416 src_gpr
= ctx
->temp_reg
;
7419 /* get offset values */
7420 if (inst
->Texture
.NumOffsets
) {
7421 assert(inst
->Texture
.NumOffsets
== 1);
7423 /* The texture offset feature doesn't work with the TXF instruction
7424 * and must be emulated by adding the offset to the texture coordinates. */
7425 if (txf_add_offsets
) {
7426 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
7428 switch (inst
->Texture
.Texture
) {
7429 case TGSI_TEXTURE_3D
:
7430 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7431 alu
.op
= ALU_OP2_ADD_INT
;
7432 alu
.src
[0].sel
= src_gpr
;
7433 alu
.src
[0].chan
= 2;
7434 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7435 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleZ
];
7436 alu
.dst
.sel
= src_gpr
;
7440 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7445 case TGSI_TEXTURE_2D
:
7446 case TGSI_TEXTURE_SHADOW2D
:
7447 case TGSI_TEXTURE_RECT
:
7448 case TGSI_TEXTURE_SHADOWRECT
:
7449 case TGSI_TEXTURE_2D_ARRAY
:
7450 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7451 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7452 alu
.op
= ALU_OP2_ADD_INT
;
7453 alu
.src
[0].sel
= src_gpr
;
7454 alu
.src
[0].chan
= 1;
7455 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7456 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleY
];
7457 alu
.dst
.sel
= src_gpr
;
7461 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7466 case TGSI_TEXTURE_1D
:
7467 case TGSI_TEXTURE_SHADOW1D
:
7468 case TGSI_TEXTURE_1D_ARRAY
:
7469 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7470 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7471 alu
.op
= ALU_OP2_ADD_INT
;
7472 alu
.src
[0].sel
= src_gpr
;
7473 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7474 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleX
];
7475 alu
.dst
.sel
= src_gpr
;
7478 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7482 /* texture offsets do not apply to other texture targets */
7485 switch (inst
->Texture
.Texture
) {
7486 case TGSI_TEXTURE_3D
:
7487 offset_z
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
7489 case TGSI_TEXTURE_2D
:
7490 case TGSI_TEXTURE_SHADOW2D
:
7491 case TGSI_TEXTURE_RECT
:
7492 case TGSI_TEXTURE_SHADOWRECT
:
7493 case TGSI_TEXTURE_2D_ARRAY
:
7494 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7495 offset_y
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
7497 case TGSI_TEXTURE_1D
:
7498 case TGSI_TEXTURE_SHADOW1D
:
7499 case TGSI_TEXTURE_1D_ARRAY
:
7500 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7501 offset_x
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
7506 /* Obtain the sample index for reading a compressed MSAA color texture.
7507 * To read the FMASK, we use the ldfptr instruction, which tells us
7508 * where the samples are stored.
7509 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7510 * which is the identity mapping. Each nibble says which physical sample
7511 * should be fetched to get that sample.
7513 * Assume src.z contains the sample index. It should be modified like this:
7514 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7515 * Then fetch the texel with src.
7517 if (read_compressed_msaa
) {
7518 unsigned sample_chan
= 3;
7519 unsigned temp
= r600_get_temp(ctx
);
7522 /* temp.w = ldfptr() */
7523 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7524 tex
.op
= FETCH_OP_LD
;
7525 tex
.inst_mod
= 1; /* to indicate this is ldfptr */
7526 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7527 tex
.sampler_index_mode
= sampler_index_mode
;
7528 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7529 tex
.resource_index_mode
= sampler_index_mode
;
7530 tex
.src_gpr
= src_gpr
;
7532 tex
.dst_sel_x
= 7; /* mask out these components */
7535 tex
.dst_sel_w
= 0; /* store X */
7540 tex
.offset_x
= offset_x
;
7541 tex
.offset_y
= offset_y
;
7542 tex
.offset_z
= offset_z
;
7543 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7547 /* temp.x = sample_index*4 */
7548 if (ctx
->bc
->chip_class
== CAYMAN
) {
7549 for (i
= 0 ; i
< 4; i
++) {
7550 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7551 alu
.op
= ALU_OP2_MULLO_INT
;
7552 alu
.src
[0].sel
= src_gpr
;
7553 alu
.src
[0].chan
= sample_chan
;
7554 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7555 alu
.src
[1].value
= 4;
7558 alu
.dst
.write
= i
== 0;
7561 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7566 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7567 alu
.op
= ALU_OP2_MULLO_INT
;
7568 alu
.src
[0].sel
= src_gpr
;
7569 alu
.src
[0].chan
= sample_chan
;
7570 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7571 alu
.src
[1].value
= 4;
7576 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7581 /* sample_index = temp.w >> temp.x */
7582 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7583 alu
.op
= ALU_OP2_LSHR_INT
;
7584 alu
.src
[0].sel
= temp
;
7585 alu
.src
[0].chan
= 3;
7586 alu
.src
[1].sel
= temp
;
7587 alu
.src
[1].chan
= 0;
7588 alu
.dst
.sel
= src_gpr
;
7589 alu
.dst
.chan
= sample_chan
;
7592 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7596 /* sample_index & 0xF */
7597 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7598 alu
.op
= ALU_OP2_AND_INT
;
7599 alu
.src
[0].sel
= src_gpr
;
7600 alu
.src
[0].chan
= sample_chan
;
7601 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7602 alu
.src
[1].value
= 0xF;
7603 alu
.dst
.sel
= src_gpr
;
7604 alu
.dst
.chan
= sample_chan
;
7607 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7611 /* visualize the FMASK */
7612 for (i
= 0; i
< 4; i
++) {
7613 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7614 alu
.op
= ALU_OP1_INT_TO_FLT
;
7615 alu
.src
[0].sel
= src_gpr
;
7616 alu
.src
[0].chan
= sample_chan
;
7617 alu
.dst
.sel
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7621 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7629 /* does this shader want a num layers from TXQ for a cube array? */
7630 if (has_txq_cube_array_z
) {
7631 int id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7633 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7634 alu
.op
= ALU_OP1_MOV
;
7636 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
7637 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7638 /* with eg each dword is number of cubes */
7639 alu
.src
[0].sel
+= id
/ 4;
7640 alu
.src
[0].chan
= id
% 4;
7642 /* r600 we have them at channel 2 of the second dword */
7643 alu
.src
[0].sel
+= (id
* 2) + 1;
7644 alu
.src
[0].chan
= 2;
7646 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
7647 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
7649 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7652 /* disable writemask from texture instruction */
7653 inst
->Dst
[0].Register
.WriteMask
&= ~4;
7656 opcode
= ctx
->inst_info
->op
;
7657 if (opcode
== FETCH_OP_GATHER4
&&
7658 inst
->TexOffsets
[0].File
!= TGSI_FILE_NULL
&&
7659 inst
->TexOffsets
[0].File
!= TGSI_FILE_IMMEDIATE
) {
7660 opcode
= FETCH_OP_GATHER4_O
;
7662 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7663 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7664 encoded in the instruction are ignored. */
7665 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7666 tex
.op
= FETCH_OP_SET_TEXTURE_OFFSETS
;
7667 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7668 tex
.sampler_index_mode
= sampler_index_mode
;
7669 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7670 tex
.resource_index_mode
= sampler_index_mode
;
7672 tex
.src_gpr
= ctx
->file_offset
[inst
->TexOffsets
[0].File
] + inst
->TexOffsets
[0].Index
;
7673 tex
.src_sel_x
= inst
->TexOffsets
[0].SwizzleX
;
7674 tex
.src_sel_y
= inst
->TexOffsets
[0].SwizzleY
;
7675 tex
.src_sel_z
= inst
->TexOffsets
[0].SwizzleZ
;
7683 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7688 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7689 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7690 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7691 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7692 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
7693 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7694 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7696 case FETCH_OP_SAMPLE
:
7697 opcode
= FETCH_OP_SAMPLE_C
;
7699 case FETCH_OP_SAMPLE_L
:
7700 opcode
= FETCH_OP_SAMPLE_C_L
;
7702 case FETCH_OP_SAMPLE_LB
:
7703 opcode
= FETCH_OP_SAMPLE_C_LB
;
7705 case FETCH_OP_SAMPLE_G
:
7706 opcode
= FETCH_OP_SAMPLE_C_G
;
7708 /* Texture gather variants */
7709 case FETCH_OP_GATHER4
:
7710 opcode
= FETCH_OP_GATHER4_C
;
7712 case FETCH_OP_GATHER4_O
:
7713 opcode
= FETCH_OP_GATHER4_C_O
;
7718 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7721 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7722 tex
.sampler_index_mode
= sampler_index_mode
;
7723 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7724 tex
.resource_index_mode
= sampler_index_mode
;
7725 tex
.src_gpr
= src_gpr
;
7726 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7728 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_DDX_FINE
||
7729 inst
->Instruction
.Opcode
== TGSI_OPCODE_DDY_FINE
) {
7730 tex
.inst_mod
= 1; /* per pixel gradient calculation instead of per 2x2 quad */
7733 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
) {
7734 int8_t texture_component_select
= ctx
->literals
[4 * inst
->Src
[1].Register
.Index
+ inst
->Src
[1].Register
.SwizzleX
];
7735 tex
.inst_mod
= texture_component_select
;
7737 if (ctx
->bc
->chip_class
== CAYMAN
) {
7738 /* GATHER4 result order is different from TGSI TG4 */
7739 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 0 : 7;
7740 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 1 : 7;
7741 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 2 : 7;
7742 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7744 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7745 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7746 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7747 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7750 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LODQ
) {
7751 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7752 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7756 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7763 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7764 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7765 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7766 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7770 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7775 } else if (src_loaded
) {
7781 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
7782 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
7783 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
7784 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
7785 tex
.src_rel
= ctx
->src
[0].rel
;
7788 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
7789 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7790 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7791 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7795 tex
.src_sel_w
= 2; /* route Z compare or Lod value into W */
7798 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
7799 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
7800 tex
.coord_type_x
= 1;
7801 tex
.coord_type_y
= 1;
7803 tex
.coord_type_z
= 1;
7804 tex
.coord_type_w
= 1;
7806 tex
.offset_x
= offset_x
;
7807 tex
.offset_y
= offset_y
;
7808 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
&&
7809 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7810 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)) {
7814 tex
.offset_z
= offset_z
;
7817 /* Put the depth for comparison in W.
7818 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7819 * Some instructions expect the depth in Z. */
7820 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7821 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7822 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7823 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
7824 opcode
!= FETCH_OP_SAMPLE_C_L
&&
7825 opcode
!= FETCH_OP_SAMPLE_C_LB
) {
7826 tex
.src_sel_w
= tex
.src_sel_z
;
7829 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
7830 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
7831 if (opcode
== FETCH_OP_SAMPLE_C_L
||
7832 opcode
== FETCH_OP_SAMPLE_C_LB
) {
7833 /* the array index is read from Y */
7834 tex
.coord_type_y
= 0;
7836 /* the array index is read from Z */
7837 tex
.coord_type_z
= 0;
7838 tex
.src_sel_z
= tex
.src_sel_y
;
7840 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7841 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7842 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7843 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
7844 (ctx
->bc
->chip_class
>= EVERGREEN
)))
7845 /* the array index is read from Z */
7846 tex
.coord_type_z
= 0;
7848 /* mask unused source components */
7849 if (opcode
== FETCH_OP_SAMPLE
|| opcode
== FETCH_OP_GATHER4
) {
7850 switch (inst
->Texture
.Texture
) {
7851 case TGSI_TEXTURE_2D
:
7852 case TGSI_TEXTURE_RECT
:
7856 case TGSI_TEXTURE_1D_ARRAY
:
7860 case TGSI_TEXTURE_1D
:
7868 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7872 /* add shadow ambient support - gallium doesn't do it yet */
7876 static int find_hw_atomic_counter(struct r600_shader_ctx
*ctx
,
7877 struct tgsi_full_src_register
*src
)
7881 if (src
->Register
.Indirect
) {
7882 for (i
= 0; i
< ctx
->shader
->nhwatomic_ranges
; i
++) {
7883 if (src
->Indirect
.ArrayID
== ctx
->shader
->atomics
[i
].array_id
)
7884 return ctx
->shader
->atomics
[i
].hw_idx
;
7887 uint32_t index
= src
->Register
.Index
;
7888 for (i
= 0; i
< ctx
->shader
->nhwatomic_ranges
; i
++) {
7889 if (ctx
->shader
->atomics
[i
].buffer_id
!= (unsigned)src
->Dimension
.Index
)
7891 if (index
> ctx
->shader
->atomics
[i
].end
)
7893 if (index
< ctx
->shader
->atomics
[i
].start
)
7895 uint32_t offset
= (index
- ctx
->shader
->atomics
[i
].start
);
7896 return ctx
->shader
->atomics
[i
].hw_idx
+ offset
;
7903 static int tgsi_set_gds_temp(struct r600_shader_ctx
*ctx
,
7904 int *uav_id_p
, int *uav_index_mode_p
)
7906 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7907 int uav_id
, uav_index_mode
= 0;
7909 bool is_cm
= (ctx
->bc
->chip_class
== CAYMAN
);
7911 uav_id
= find_hw_atomic_counter(ctx
, &inst
->Src
[0]);
7913 if (inst
->Src
[0].Register
.Indirect
) {
7915 struct r600_bytecode_alu alu
;
7916 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7917 alu
.op
= ALU_OP2_LSHL_INT
;
7918 alu
.src
[0].sel
= get_address_file_reg(ctx
, inst
->Src
[0].Indirect
.Index
);
7919 alu
.src
[0].chan
= 0;
7920 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7921 alu
.src
[1].value
= 2;
7922 alu
.dst
.sel
= ctx
->temp_reg
;
7926 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7930 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
7933 V_SQ_ALU_SRC_LITERAL
, uav_id
* 4);
7939 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
7941 V_SQ_ALU_SRC_LITERAL
, uav_id
* 4,
7947 *uav_index_mode_p
= uav_index_mode
;
7951 static int tgsi_load_gds(struct r600_shader_ctx
*ctx
)
7953 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7955 struct r600_bytecode_gds gds
;
7957 int uav_index_mode
= 0;
7958 bool is_cm
= (ctx
->bc
->chip_class
== CAYMAN
);
7960 r
= tgsi_set_gds_temp(ctx
, &uav_id
, &uav_index_mode
);
7964 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
7965 gds
.op
= FETCH_OP_GDS_READ_RET
;
7966 gds
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7967 gds
.uav_id
= is_cm
? 0 : uav_id
;
7968 gds
.uav_index_mode
= is_cm
? 0 : uav_index_mode
;
7969 gds
.src_gpr
= ctx
->temp_reg
;
7970 gds
.src_sel_x
= (is_cm
) ? 0 : 4;
7978 gds
.alloc_consume
= !is_cm
;
7979 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
7983 ctx
->bc
->cf_last
->vpm
= 1;
7987 /* this fixes up 1D arrays properly */
7988 static int load_index_src(struct r600_shader_ctx
*ctx
, int src_index
, int *idx_gpr
)
7990 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7992 struct r600_bytecode_alu alu
;
7993 int temp_reg
= r600_get_temp(ctx
);
7995 for (i
= 0; i
< 4; i
++) {
7996 bool def_val
= true, write_zero
= false;
7997 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7998 alu
.op
= ALU_OP1_MOV
;
7999 alu
.dst
.sel
= temp_reg
;
8002 switch (inst
->Memory
.Texture
) {
8003 case TGSI_TEXTURE_BUFFER
:
8004 case TGSI_TEXTURE_1D
:
8005 if (i
== 1 || i
== 2 || i
== 3) {
8009 case TGSI_TEXTURE_1D_ARRAY
:
8010 if (i
== 1 || i
== 3)
8013 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[src_index
], 1);
8017 case TGSI_TEXTURE_2D
:
8018 if (i
== 2 || i
== 3)
8028 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
8029 alu
.src
[0].value
= 0;
8030 } else if (def_val
) {
8031 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[src_index
], i
);
8037 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8041 *idx_gpr
= temp_reg
;
8045 static int load_buffer_coord(struct r600_shader_ctx
*ctx
, int src_idx
,
8048 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8050 if (inst
->Src
[src_idx
].Register
.File
== TGSI_FILE_IMMEDIATE
) {
8051 int value
= (ctx
->literals
[4 * inst
->Src
[src_idx
].Register
.Index
+ inst
->Src
[src_idx
].Register
.SwizzleX
]);
8052 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
8054 V_SQ_ALU_SRC_LITERAL
, value
>> 2,
8059 struct r600_bytecode_alu alu
;
8060 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8061 alu
.op
= ALU_OP2_LSHR_INT
;
8062 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[src_idx
], 0);
8063 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
8064 alu
.src
[1].value
= 2;
8065 alu
.dst
.sel
= temp_reg
;
8068 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8075 static int tgsi_load_buffer(struct r600_shader_ctx
*ctx
)
8077 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8078 /* have to work out the offset into the RAT immediate return buffer */
8079 struct r600_bytecode_vtx vtx
;
8080 struct r600_bytecode_cf
*cf
;
8082 int temp_reg
= r600_get_temp(ctx
);
8083 unsigned rat_index_mode
;
8086 rat_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8087 base
= R600_IMAGE_REAL_RESOURCE_OFFSET
+ ctx
->info
.file_count
[TGSI_FILE_IMAGE
];
8089 r
= load_buffer_coord(ctx
, 1, temp_reg
);
8092 ctx
->bc
->cf_last
->barrier
= 1;
8093 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
8094 vtx
.op
= FETCH_OP_VFETCH
;
8095 vtx
.buffer_id
= inst
->Src
[0].Register
.Index
+ base
;
8096 vtx
.buffer_index_mode
= rat_index_mode
;
8097 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
8098 vtx
.src_gpr
= temp_reg
;
8100 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8101 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
8102 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7; /* SEL_Y */
8103 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7; /* SEL_Z */
8104 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7; /* SEL_W */
8105 vtx
.num_format_all
= 1;
8106 vtx
.format_comp_all
= 1;
8107 vtx
.srf_mode_all
= 0;
8109 if (inst
->Dst
[0].Register
.WriteMask
& 8) {
8110 vtx
.data_format
= FMT_32_32_32_32
;
8111 vtx
.use_const_fields
= 0;
8112 } else if (inst
->Dst
[0].Register
.WriteMask
& 4) {
8113 vtx
.data_format
= FMT_32_32_32
;
8114 vtx
.use_const_fields
= 0;
8115 } else if (inst
->Dst
[0].Register
.WriteMask
& 2) {
8116 vtx
.data_format
= FMT_32_32
;
8117 vtx
.use_const_fields
= 0;
8119 vtx
.data_format
= FMT_32
;
8120 vtx
.use_const_fields
= 0;
8123 r
= r600_bytecode_add_vtx_tc(ctx
->bc
, &vtx
);
8126 cf
= ctx
->bc
->cf_last
;
8131 static int tgsi_load_rat(struct r600_shader_ctx
*ctx
)
8133 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8134 /* have to work out the offset into the RAT immediate return buffer */
8135 struct r600_bytecode_vtx vtx
;
8136 struct r600_bytecode_cf
*cf
;
8139 unsigned format
, num_format
, format_comp
, endian
;
8140 const struct util_format_description
*desc
;
8141 unsigned rat_index_mode
;
8142 unsigned immed_base
;
8144 r
= load_thread_id_gpr(ctx
);
8148 rat_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8150 immed_base
= R600_IMAGE_IMMED_RESOURCE_OFFSET
;
8151 r
= load_index_src(ctx
, 1, &idx_gpr
);
8156 egcm_load_index_reg(ctx
->bc
, 1, false);
8158 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
8159 cf
= ctx
->bc
->cf_last
;
8161 cf
->rat
.id
= ctx
->shader
->rat_base
+ inst
->Src
[0].Register
.Index
;
8162 cf
->rat
.inst
= V_RAT_INST_NOP_RTN
;
8163 cf
->rat
.index_mode
= rat_index_mode
;
8164 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND
;
8165 cf
->output
.gpr
= ctx
->thread_id_gpr
;
8166 cf
->output
.index_gpr
= idx_gpr
;
8167 cf
->output
.comp_mask
= 0xf;
8168 cf
->output
.burst_count
= 1;
8172 cf
->output
.elem_size
= 0;
8174 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_WAIT_ACK
);
8175 cf
= ctx
->bc
->cf_last
;
8178 desc
= util_format_description(inst
->Memory
.Format
);
8179 r600_vertex_data_type(inst
->Memory
.Format
,
8180 &format
, &num_format
, &format_comp
, &endian
);
8181 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
8182 vtx
.op
= FETCH_OP_VFETCH
;
8183 vtx
.buffer_id
= immed_base
+ inst
->Src
[0].Register
.Index
;
8184 vtx
.buffer_index_mode
= rat_index_mode
;
8185 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
8186 vtx
.src_gpr
= ctx
->thread_id_gpr
;
8188 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8189 vtx
.dst_sel_x
= desc
->swizzle
[0];
8190 vtx
.dst_sel_y
= desc
->swizzle
[1];
8191 vtx
.dst_sel_z
= desc
->swizzle
[2];
8192 vtx
.dst_sel_w
= desc
->swizzle
[3];
8193 vtx
.srf_mode_all
= 1;
8194 vtx
.data_format
= format
;
8195 vtx
.num_format_all
= num_format
;
8196 vtx
.format_comp_all
= format_comp
;
8197 vtx
.endian
= endian
;
8199 vtx
.mega_fetch_count
= 3;
8200 r
= r600_bytecode_add_vtx_tc(ctx
->bc
, &vtx
);
8203 cf
= ctx
->bc
->cf_last
;
8208 static int tgsi_load_lds(struct r600_shader_ctx
*ctx
)
8210 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8211 struct r600_bytecode_alu alu
;
8213 int temp_reg
= r600_get_temp(ctx
);
8215 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8216 alu
.op
= ALU_OP1_MOV
;
8217 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
8218 alu
.dst
.sel
= temp_reg
;
8221 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8225 r
= do_lds_fetch_values(ctx
, temp_reg
,
8226 ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
, inst
->Dst
[0].Register
.WriteMask
);
8232 static int tgsi_load(struct r600_shader_ctx
*ctx
)
8234 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8235 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
8236 return tgsi_load_rat(ctx
);
8237 if (inst
->Src
[0].Register
.File
== TGSI_FILE_HW_ATOMIC
)
8238 return tgsi_load_gds(ctx
);
8239 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
8240 return tgsi_load_buffer(ctx
);
8241 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
8242 return tgsi_load_lds(ctx
);
8246 static int tgsi_store_buffer_rat(struct r600_shader_ctx
*ctx
)
8248 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8249 struct r600_bytecode_cf
*cf
;
8251 unsigned rat_index_mode
;
8253 int temp_reg
= r600_get_temp(ctx
), treg2
= r600_get_temp(ctx
);
8255 r
= load_buffer_coord(ctx
, 0, treg2
);
8259 rat_index_mode
= inst
->Dst
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8261 egcm_load_index_reg(ctx
->bc
, 1, false);
8263 for (i
= 0; i
<= 3; i
++) {
8264 struct r600_bytecode_alu alu
;
8265 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8266 alu
.op
= ALU_OP1_MOV
;
8267 alu
.dst
.sel
= temp_reg
;
8269 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
8270 alu
.last
= (i
== 3);
8272 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8277 lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8278 for (i
= 0; i
<= lasti
; i
++) {
8279 struct r600_bytecode_alu alu
;
8280 if (!((1 << i
) & inst
->Dst
[0].Register
.WriteMask
))
8283 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
8286 V_SQ_ALU_SRC_LITERAL
, i
);
8290 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8291 alu
.op
= ALU_OP1_MOV
;
8292 alu
.dst
.sel
= ctx
->temp_reg
;
8295 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
8298 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8302 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
8303 cf
= ctx
->bc
->cf_last
;
8305 cf
->rat
.id
= ctx
->shader
->rat_base
+ inst
->Dst
[0].Register
.Index
+ ctx
->info
.file_count
[TGSI_FILE_IMAGE
];
8306 cf
->rat
.inst
= V_RAT_INST_STORE_TYPED
;
8307 cf
->rat
.index_mode
= rat_index_mode
;
8308 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
8309 cf
->output
.gpr
= ctx
->temp_reg
;
8310 cf
->output
.index_gpr
= temp_reg
;
8311 cf
->output
.comp_mask
= 1;
8312 cf
->output
.burst_count
= 1;
8315 cf
->output
.elem_size
= 0;
8320 static int tgsi_store_rat(struct r600_shader_ctx
*ctx
)
8322 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8323 struct r600_bytecode_cf
*cf
;
8324 bool src_requires_loading
= false;
8325 int val_gpr
, idx_gpr
;
8327 unsigned rat_index_mode
;
8329 rat_index_mode
= inst
->Dst
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8331 r
= load_index_src(ctx
, 0, &idx_gpr
);
8335 if (inst
->Src
[1].Register
.File
!= TGSI_FILE_TEMPORARY
)
8336 src_requires_loading
= true;
8338 if (src_requires_loading
) {
8339 struct r600_bytecode_alu alu
;
8340 for (i
= 0; i
< 4; i
++) {
8341 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8342 alu
.op
= ALU_OP1_MOV
;
8343 alu
.dst
.sel
= ctx
->temp_reg
;
8346 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
8350 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8354 val_gpr
= ctx
->temp_reg
;
8356 val_gpr
= tgsi_tex_get_src_gpr(ctx
, 1);
8358 egcm_load_index_reg(ctx
->bc
, 1, false);
8360 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
8361 cf
= ctx
->bc
->cf_last
;
8363 cf
->rat
.id
= ctx
->shader
->rat_base
+ inst
->Dst
[0].Register
.Index
;
8364 cf
->rat
.inst
= V_RAT_INST_STORE_TYPED
;
8365 cf
->rat
.index_mode
= rat_index_mode
;
8366 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
8367 cf
->output
.gpr
= val_gpr
;
8368 cf
->output
.index_gpr
= idx_gpr
;
8369 cf
->output
.comp_mask
= 0xf;
8370 cf
->output
.burst_count
= 1;
8373 cf
->output
.elem_size
= 0;
8377 static int tgsi_store_lds(struct r600_shader_ctx
*ctx
)
8379 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8380 struct r600_bytecode_alu alu
;
8382 int write_mask
= inst
->Dst
[0].Register
.WriteMask
;
8383 int temp_reg
= r600_get_temp(ctx
);
8386 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8387 alu
.op
= ALU_OP1_MOV
;
8388 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8389 alu
.dst
.sel
= temp_reg
;
8392 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8396 lasti
= tgsi_last_instruction(write_mask
);
8397 for (i
= 1; i
<= lasti
; i
++) {
8398 if (!(write_mask
& (1 << i
)))
8400 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
8403 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
8407 for (i
= 0; i
<= lasti
; i
++) {
8408 if (!(write_mask
& (1 << i
)))
8411 if ((i
== 0 && ((write_mask
& 3) == 3)) ||
8412 (i
== 2 && ((write_mask
& 0xc) == 0xc))) {
8413 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8414 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
8416 alu
.src
[0].sel
= temp_reg
;
8417 alu
.src
[0].chan
= i
;
8418 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
8419 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
+ 1);
8421 alu
.is_lds_idx_op
= true;
8423 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8429 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8430 alu
.op
= LDS_OP2_LDS_WRITE
;
8432 alu
.src
[0].sel
= temp_reg
;
8433 alu
.src
[0].chan
= i
;
8434 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
8437 alu
.is_lds_idx_op
= true;
8439 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8446 static int tgsi_store(struct r600_shader_ctx
*ctx
)
8448 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8449 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
8450 return tgsi_store_buffer_rat(ctx
);
8451 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
8452 return tgsi_store_lds(ctx
);
8454 return tgsi_store_rat(ctx
);
8457 static int tgsi_atomic_op_rat(struct r600_shader_ctx
*ctx
)
8459 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8460 /* have to work out the offset into the RAT immediate return buffer */
8461 struct r600_bytecode_alu alu
;
8462 struct r600_bytecode_vtx vtx
;
8463 struct r600_bytecode_cf
*cf
;
8466 unsigned format
, num_format
, format_comp
, endian
;
8467 const struct util_format_description
*desc
;
8468 unsigned rat_index_mode
;
8469 unsigned immed_base
;
8472 immed_base
= R600_IMAGE_IMMED_RESOURCE_OFFSET
;
8473 rat_base
= ctx
->shader
->rat_base
;
8475 r
= load_thread_id_gpr(ctx
);
8479 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
8480 immed_base
+= ctx
->info
.file_count
[TGSI_FILE_IMAGE
];
8481 rat_base
+= ctx
->info
.file_count
[TGSI_FILE_IMAGE
];
8483 r
= load_buffer_coord(ctx
, 1, ctx
->temp_reg
);
8486 idx_gpr
= ctx
->temp_reg
;
8488 r
= load_index_src(ctx
, 1, &idx_gpr
);
8493 rat_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8495 if (ctx
->inst_info
->op
== V_RAT_INST_CMPXCHG_INT_RTN
) {
8496 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8497 alu
.op
= ALU_OP1_MOV
;
8498 alu
.dst
.sel
= ctx
->thread_id_gpr
;
8501 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], 0);
8503 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8507 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8508 alu
.op
= ALU_OP1_MOV
;
8509 alu
.dst
.sel
= ctx
->thread_id_gpr
;
8510 if (ctx
->bc
->chip_class
== CAYMAN
)
8515 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
8517 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8521 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8522 alu
.op
= ALU_OP1_MOV
;
8523 alu
.dst
.sel
= ctx
->thread_id_gpr
;
8526 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
8528 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8534 egcm_load_index_reg(ctx
->bc
, 1, false);
8535 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
8536 cf
= ctx
->bc
->cf_last
;
8538 cf
->rat
.id
= rat_base
+ inst
->Src
[0].Register
.Index
;
8539 cf
->rat
.inst
= ctx
->inst_info
->op
;
8540 cf
->rat
.index_mode
= rat_index_mode
;
8541 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND
;
8542 cf
->output
.gpr
= ctx
->thread_id_gpr
;
8543 cf
->output
.index_gpr
= idx_gpr
;
8544 cf
->output
.comp_mask
= 0xf;
8545 cf
->output
.burst_count
= 1;
8549 cf
->output
.elem_size
= 0;
8550 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_WAIT_ACK
);
8551 cf
= ctx
->bc
->cf_last
;
8555 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
8556 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
) {
8557 desc
= util_format_description(inst
->Memory
.Format
);
8558 r600_vertex_data_type(inst
->Memory
.Format
,
8559 &format
, &num_format
, &format_comp
, &endian
);
8560 vtx
.dst_sel_x
= desc
->swizzle
[0];
8568 vtx
.op
= FETCH_OP_VFETCH
;
8569 vtx
.buffer_id
= immed_base
+ inst
->Src
[0].Register
.Index
;
8570 vtx
.buffer_index_mode
= rat_index_mode
;
8571 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
8572 vtx
.src_gpr
= ctx
->thread_id_gpr
;
8574 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8578 vtx
.use_const_fields
= 0;
8579 vtx
.srf_mode_all
= 1;
8580 vtx
.data_format
= format
;
8581 vtx
.num_format_all
= num_format
;
8582 vtx
.format_comp_all
= format_comp
;
8583 vtx
.endian
= endian
;
8585 vtx
.mega_fetch_count
= 0xf;
8586 r
= r600_bytecode_add_vtx_tc(ctx
->bc
, &vtx
);
8589 cf
= ctx
->bc
->cf_last
;
8595 static int get_gds_op(int opcode
)
8598 case TGSI_OPCODE_ATOMUADD
:
8599 return FETCH_OP_GDS_ADD_RET
;
8600 case TGSI_OPCODE_ATOMAND
:
8601 return FETCH_OP_GDS_AND_RET
;
8602 case TGSI_OPCODE_ATOMOR
:
8603 return FETCH_OP_GDS_OR_RET
;
8604 case TGSI_OPCODE_ATOMXOR
:
8605 return FETCH_OP_GDS_XOR_RET
;
8606 case TGSI_OPCODE_ATOMUMIN
:
8607 return FETCH_OP_GDS_MIN_UINT_RET
;
8608 case TGSI_OPCODE_ATOMUMAX
:
8609 return FETCH_OP_GDS_MAX_UINT_RET
;
8610 case TGSI_OPCODE_ATOMXCHG
:
8611 return FETCH_OP_GDS_XCHG_RET
;
8612 case TGSI_OPCODE_ATOMCAS
:
8613 return FETCH_OP_GDS_CMP_XCHG_RET
;
8619 static int tgsi_atomic_op_gds(struct r600_shader_ctx
*ctx
)
8621 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8622 struct r600_bytecode_gds gds
;
8623 struct r600_bytecode_alu alu
;
8624 int gds_op
= get_gds_op(inst
->Instruction
.Opcode
);
8627 int uav_index_mode
= 0;
8628 bool is_cm
= (ctx
->bc
->chip_class
== CAYMAN
);
8631 fprintf(stderr
, "unknown GDS op for opcode %d\n", inst
->Instruction
.Opcode
);
8635 r
= tgsi_set_gds_temp(ctx
, &uav_id
, &uav_index_mode
);
8639 if (inst
->Src
[2].Register
.File
== TGSI_FILE_IMMEDIATE
) {
8640 int value
= (ctx
->literals
[4 * inst
->Src
[2].Register
.Index
+ inst
->Src
[2].Register
.SwizzleX
]);
8641 int abs_value
= abs(value
);
8642 if (abs_value
!= value
&& gds_op
== FETCH_OP_GDS_ADD_RET
)
8643 gds_op
= FETCH_OP_GDS_SUB_RET
;
8644 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8645 alu
.op
= ALU_OP1_MOV
;
8646 alu
.dst
.sel
= ctx
->temp_reg
;
8647 alu
.dst
.chan
= is_cm
? 1 : 0;
8648 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
8649 alu
.src
[0].value
= abs_value
;
8652 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8656 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8657 alu
.op
= ALU_OP1_MOV
;
8658 alu
.dst
.sel
= ctx
->temp_reg
;
8659 alu
.dst
.chan
= is_cm
? 1 : 0;
8660 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
8663 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8669 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
8671 gds
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8672 gds
.uav_id
= is_cm
? 0 : uav_id
;
8673 gds
.uav_index_mode
= is_cm
? 0 : uav_index_mode
;
8674 gds
.src_gpr
= ctx
->temp_reg
;
8676 gds
.src_sel_x
= is_cm
? 0 : 4;
8677 gds
.src_sel_y
= is_cm
? 1 : 0;
8683 gds
.alloc_consume
= !is_cm
;
8685 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
8688 ctx
->bc
->cf_last
->vpm
= 1;
8692 static int get_lds_op(int opcode
)
8695 case TGSI_OPCODE_ATOMUADD
:
8696 return LDS_OP2_LDS_ADD_RET
;
8697 case TGSI_OPCODE_ATOMAND
:
8698 return LDS_OP2_LDS_AND_RET
;
8699 case TGSI_OPCODE_ATOMOR
:
8700 return LDS_OP2_LDS_OR_RET
;
8701 case TGSI_OPCODE_ATOMXOR
:
8702 return LDS_OP2_LDS_XOR_RET
;
8703 case TGSI_OPCODE_ATOMUMIN
:
8704 return LDS_OP2_LDS_MIN_UINT_RET
;
8705 case TGSI_OPCODE_ATOMUMAX
:
8706 return LDS_OP2_LDS_MAX_UINT_RET
;
8707 case TGSI_OPCODE_ATOMIMIN
:
8708 return LDS_OP2_LDS_MIN_INT_RET
;
8709 case TGSI_OPCODE_ATOMIMAX
:
8710 return LDS_OP2_LDS_MAX_INT_RET
;
8711 case TGSI_OPCODE_ATOMXCHG
:
8712 return LDS_OP2_LDS_XCHG_RET
;
8713 case TGSI_OPCODE_ATOMCAS
:
8714 return LDS_OP3_LDS_CMP_XCHG_RET
;
8720 static int tgsi_atomic_op_lds(struct r600_shader_ctx
*ctx
)
8722 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8723 int lds_op
= get_lds_op(inst
->Instruction
.Opcode
);
8726 struct r600_bytecode_alu alu
;
8727 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8729 alu
.is_lds_idx_op
= true;
8731 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
8732 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], 0);
8733 if (lds_op
== LDS_OP3_LDS_CMP_XCHG_RET
)
8734 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[3], 0);
8736 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
8737 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8741 /* then read from LDS_OQ_A_POP */
8742 memset(&alu
, 0, sizeof(alu
));
8744 alu
.op
= ALU_OP1_MOV
;
8745 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
;
8746 alu
.src
[0].chan
= 0;
8747 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
8750 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8757 static int tgsi_atomic_op(struct r600_shader_ctx
*ctx
)
8759 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8760 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
8761 return tgsi_atomic_op_rat(ctx
);
8762 if (inst
->Src
[0].Register
.File
== TGSI_FILE_HW_ATOMIC
)
8763 return tgsi_atomic_op_gds(ctx
);
8764 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
8765 return tgsi_atomic_op_rat(ctx
);
8766 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
8767 return tgsi_atomic_op_lds(ctx
);
8771 static int tgsi_resq(struct r600_shader_ctx
*ctx
)
8773 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8774 unsigned sampler_index_mode
;
8775 struct r600_bytecode_tex tex
;
8777 boolean has_txq_cube_array_z
= false;
8779 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
8780 (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
&& inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
)) {
8781 if (ctx
->bc
->chip_class
< EVERGREEN
)
8782 ctx
->shader
->uses_tex_buffers
= true;
8783 return r600_do_buffer_txq(ctx
, 0, ctx
->shader
->image_size_const_offset
);
8786 if (inst
->Memory
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
&&
8787 inst
->Dst
[0].Register
.WriteMask
& 4) {
8788 ctx
->shader
->has_txq_cube_array_z_comp
= true;
8789 has_txq_cube_array_z
= true;
8792 sampler_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8793 if (sampler_index_mode
)
8794 egcm_load_index_reg(ctx
->bc
, 1, false);
8797 /* does this shader want a num layers from TXQ for a cube array? */
8798 if (has_txq_cube_array_z
) {
8799 int id
= tgsi_tex_get_src_gpr(ctx
, 0) + ctx
->shader
->image_size_const_offset
;
8800 struct r600_bytecode_alu alu
;
8802 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8803 alu
.op
= ALU_OP1_MOV
;
8805 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
8806 /* with eg each dword is either number of cubes */
8807 alu
.src
[0].sel
+= id
/ 4;
8808 alu
.src
[0].chan
= id
% 4;
8809 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
8810 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
8812 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8815 /* disable writemask from texture instruction */
8816 inst
->Dst
[0].Register
.WriteMask
&= ~4;
8818 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
8819 tex
.op
= ctx
->inst_info
->op
;
8820 tex
.sampler_id
= R600_IMAGE_REAL_RESOURCE_OFFSET
+ inst
->Src
[0].Register
.Index
;
8821 tex
.sampler_index_mode
= sampler_index_mode
;
8822 tex
.resource_id
= tex
.sampler_id
;
8823 tex
.resource_index_mode
= sampler_index_mode
;
8828 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
8829 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
8830 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
8831 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
8832 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8833 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
8840 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
8842 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8843 struct r600_bytecode_alu alu
;
8844 unsigned lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8845 unsigned i
, temp_regs
[2];
8848 /* optimize if it's just an equal balance */
8849 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
8850 for (i
= 0; i
< lasti
+ 1; i
++) {
8851 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8854 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8855 alu
.op
= ALU_OP2_ADD
;
8856 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
8857 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8859 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8864 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8872 for (i
= 0; i
< lasti
+ 1; i
++) {
8873 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8876 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8877 alu
.op
= ALU_OP2_ADD
;
8878 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8879 alu
.src
[0].chan
= 0;
8880 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
8881 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
8882 alu
.dst
.sel
= ctx
->temp_reg
;
8888 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8893 /* (1 - src0) * src2 */
8894 for (i
= 0; i
< lasti
+ 1; i
++) {
8895 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8898 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8899 alu
.op
= ALU_OP2_MUL
;
8900 alu
.src
[0].sel
= ctx
->temp_reg
;
8901 alu
.src
[0].chan
= i
;
8902 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8903 alu
.dst
.sel
= ctx
->temp_reg
;
8909 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8914 /* src0 * src1 + (1 - src0) * src2 */
8915 if (ctx
->src
[0].abs
)
8916 temp_regs
[0] = r600_get_temp(ctx
);
8919 if (ctx
->src
[1].abs
)
8920 temp_regs
[1] = r600_get_temp(ctx
);
8924 for (i
= 0; i
< lasti
+ 1; i
++) {
8925 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8928 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8929 alu
.op
= ALU_OP3_MULADD
;
8931 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
8934 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[1], &ctx
->src
[1]);
8937 alu
.src
[2].sel
= ctx
->temp_reg
;
8938 alu
.src
[2].chan
= i
;
8940 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8945 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8952 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
8954 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8955 struct r600_bytecode_alu alu
;
8957 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8961 if (ctx
->src
[0].abs
&& ctx
->src
[0].neg
) {
8963 ctx
->src
[0].abs
= 0;
8964 ctx
->src
[0].neg
= 0;
8969 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
8971 if (ctx
->src
[j
].abs
)
8972 temp_regs
[j
] = r600_get_temp(ctx
);
8975 for (i
= 0; i
< lasti
+ 1; i
++) {
8976 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8979 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8981 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
8984 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[2], i
, &alu
.src
[1], &ctx
->src
[2]);
8987 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[2], &ctx
->src
[1]);
8990 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8996 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9003 static int tgsi_ucmp(struct r600_shader_ctx
*ctx
)
9005 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9006 struct r600_bytecode_alu alu
;
9008 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9010 for (i
= 0; i
< lasti
+ 1; i
++) {
9011 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9014 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9015 alu
.op
= ALU_OP3_CNDE_INT
;
9016 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9017 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
9018 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
9019 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9025 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9032 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
9034 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9035 struct r600_bytecode_alu alu
;
9039 /* result.x = 2^floor(src); */
9040 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
9041 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9043 alu
.op
= ALU_OP1_FLOOR
;
9044 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9046 alu
.dst
.sel
= ctx
->temp_reg
;
9050 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9054 if (ctx
->bc
->chip_class
== CAYMAN
) {
9055 for (i
= 0; i
< 3; i
++) {
9056 alu
.op
= ALU_OP1_EXP_IEEE
;
9057 alu
.src
[0].sel
= ctx
->temp_reg
;
9058 alu
.src
[0].chan
= 0;
9060 alu
.dst
.sel
= ctx
->temp_reg
;
9062 alu
.dst
.write
= i
== 0;
9064 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9069 alu
.op
= ALU_OP1_EXP_IEEE
;
9070 alu
.src
[0].sel
= ctx
->temp_reg
;
9071 alu
.src
[0].chan
= 0;
9073 alu
.dst
.sel
= ctx
->temp_reg
;
9077 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9083 /* result.y = tmp - floor(tmp); */
9084 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
9085 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9087 alu
.op
= ALU_OP1_FRACT
;
9088 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9090 alu
.dst
.sel
= ctx
->temp_reg
;
9092 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9101 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9106 /* result.z = RoughApprox2ToX(tmp);*/
9107 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
9108 if (ctx
->bc
->chip_class
== CAYMAN
) {
9109 for (i
= 0; i
< 3; i
++) {
9110 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9111 alu
.op
= ALU_OP1_EXP_IEEE
;
9112 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9114 alu
.dst
.sel
= ctx
->temp_reg
;
9121 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9126 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9127 alu
.op
= ALU_OP1_EXP_IEEE
;
9128 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9130 alu
.dst
.sel
= ctx
->temp_reg
;
9136 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9142 /* result.w = 1.0;*/
9143 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
9144 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9146 alu
.op
= ALU_OP1_MOV
;
9147 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
9148 alu
.src
[0].chan
= 0;
9150 alu
.dst
.sel
= ctx
->temp_reg
;
9154 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9158 return tgsi_helper_copy(ctx
, inst
);
9161 static int tgsi_log(struct r600_shader_ctx
*ctx
)
9163 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9164 struct r600_bytecode_alu alu
;
9168 /* result.x = floor(log2(|src|)); */
9169 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
9170 if (ctx
->bc
->chip_class
== CAYMAN
) {
9171 for (i
= 0; i
< 3; i
++) {
9172 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9174 alu
.op
= ALU_OP1_LOG_IEEE
;
9175 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9176 r600_bytecode_src_set_abs(&alu
.src
[0]);
9178 alu
.dst
.sel
= ctx
->temp_reg
;
9184 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9190 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9192 alu
.op
= ALU_OP1_LOG_IEEE
;
9193 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9194 r600_bytecode_src_set_abs(&alu
.src
[0]);
9196 alu
.dst
.sel
= ctx
->temp_reg
;
9200 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9205 alu
.op
= ALU_OP1_FLOOR
;
9206 alu
.src
[0].sel
= ctx
->temp_reg
;
9207 alu
.src
[0].chan
= 0;
9209 alu
.dst
.sel
= ctx
->temp_reg
;
9214 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9219 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
9220 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
9222 if (ctx
->bc
->chip_class
== CAYMAN
) {
9223 for (i
= 0; i
< 3; i
++) {
9224 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9226 alu
.op
= ALU_OP1_LOG_IEEE
;
9227 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9228 r600_bytecode_src_set_abs(&alu
.src
[0]);
9230 alu
.dst
.sel
= ctx
->temp_reg
;
9237 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9242 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9244 alu
.op
= ALU_OP1_LOG_IEEE
;
9245 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9246 r600_bytecode_src_set_abs(&alu
.src
[0]);
9248 alu
.dst
.sel
= ctx
->temp_reg
;
9253 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9258 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9260 alu
.op
= ALU_OP1_FLOOR
;
9261 alu
.src
[0].sel
= ctx
->temp_reg
;
9262 alu
.src
[0].chan
= 1;
9264 alu
.dst
.sel
= ctx
->temp_reg
;
9269 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9273 if (ctx
->bc
->chip_class
== CAYMAN
) {
9274 for (i
= 0; i
< 3; i
++) {
9275 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9276 alu
.op
= ALU_OP1_EXP_IEEE
;
9277 alu
.src
[0].sel
= ctx
->temp_reg
;
9278 alu
.src
[0].chan
= 1;
9280 alu
.dst
.sel
= ctx
->temp_reg
;
9287 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9292 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9293 alu
.op
= ALU_OP1_EXP_IEEE
;
9294 alu
.src
[0].sel
= ctx
->temp_reg
;
9295 alu
.src
[0].chan
= 1;
9297 alu
.dst
.sel
= ctx
->temp_reg
;
9302 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9307 if (ctx
->bc
->chip_class
== CAYMAN
) {
9308 for (i
= 0; i
< 3; i
++) {
9309 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9310 alu
.op
= ALU_OP1_RECIP_IEEE
;
9311 alu
.src
[0].sel
= ctx
->temp_reg
;
9312 alu
.src
[0].chan
= 1;
9314 alu
.dst
.sel
= ctx
->temp_reg
;
9321 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9326 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9327 alu
.op
= ALU_OP1_RECIP_IEEE
;
9328 alu
.src
[0].sel
= ctx
->temp_reg
;
9329 alu
.src
[0].chan
= 1;
9331 alu
.dst
.sel
= ctx
->temp_reg
;
9336 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9341 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9343 alu
.op
= ALU_OP2_MUL
;
9345 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9346 r600_bytecode_src_set_abs(&alu
.src
[0]);
9348 alu
.src
[1].sel
= ctx
->temp_reg
;
9349 alu
.src
[1].chan
= 1;
9351 alu
.dst
.sel
= ctx
->temp_reg
;
9356 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9361 /* result.z = log2(|src|);*/
9362 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
9363 if (ctx
->bc
->chip_class
== CAYMAN
) {
9364 for (i
= 0; i
< 3; i
++) {
9365 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9367 alu
.op
= ALU_OP1_LOG_IEEE
;
9368 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9369 r600_bytecode_src_set_abs(&alu
.src
[0]);
9371 alu
.dst
.sel
= ctx
->temp_reg
;
9378 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9383 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9385 alu
.op
= ALU_OP1_LOG_IEEE
;
9386 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9387 r600_bytecode_src_set_abs(&alu
.src
[0]);
9389 alu
.dst
.sel
= ctx
->temp_reg
;
9394 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9400 /* result.w = 1.0; */
9401 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
9402 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9404 alu
.op
= ALU_OP1_MOV
;
9405 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
9406 alu
.src
[0].chan
= 0;
9408 alu
.dst
.sel
= ctx
->temp_reg
;
9413 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9418 return tgsi_helper_copy(ctx
, inst
);
9421 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
9423 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9424 struct r600_bytecode_alu alu
;
9426 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9427 unsigned reg
= get_address_file_reg(ctx
, inst
->Dst
[0].Register
.Index
);
9429 assert(inst
->Dst
[0].Register
.Index
< 3);
9430 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9432 switch (inst
->Instruction
.Opcode
) {
9433 case TGSI_OPCODE_ARL
:
9434 alu
.op
= ALU_OP1_FLT_TO_INT_FLOOR
;
9436 case TGSI_OPCODE_ARR
:
9437 alu
.op
= ALU_OP1_FLT_TO_INT
;
9439 case TGSI_OPCODE_UARL
:
9440 alu
.op
= ALU_OP1_MOV
;
9447 for (i
= 0; i
<= lasti
; ++i
) {
9448 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9450 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9451 alu
.last
= i
== lasti
;
9455 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9460 if (inst
->Dst
[0].Register
.Index
> 0)
9461 ctx
->bc
->index_loaded
[inst
->Dst
[0].Register
.Index
- 1] = 0;
9463 ctx
->bc
->ar_loaded
= 0;
9467 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
9469 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9470 struct r600_bytecode_alu alu
;
9472 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9474 switch (inst
->Instruction
.Opcode
) {
9475 case TGSI_OPCODE_ARL
:
9476 memset(&alu
, 0, sizeof(alu
));
9477 alu
.op
= ALU_OP1_FLOOR
;
9478 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
9480 for (i
= 0; i
<= lasti
; ++i
) {
9481 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
9483 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9484 alu
.last
= i
== lasti
;
9485 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
9490 memset(&alu
, 0, sizeof(alu
));
9491 alu
.op
= ALU_OP1_FLT_TO_INT
;
9492 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
9493 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
9495 /* FLT_TO_INT is trans-only on r600/r700 */
9497 for (i
= 0; i
<= lasti
; ++i
) {
9499 alu
.src
[0].chan
= i
;
9500 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
9504 case TGSI_OPCODE_ARR
:
9505 memset(&alu
, 0, sizeof(alu
));
9506 alu
.op
= ALU_OP1_FLT_TO_INT
;
9507 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
9509 /* FLT_TO_INT is trans-only on r600/r700 */
9511 for (i
= 0; i
<= lasti
; ++i
) {
9512 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
9514 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9515 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
9520 case TGSI_OPCODE_UARL
:
9521 memset(&alu
, 0, sizeof(alu
));
9522 alu
.op
= ALU_OP1_MOV
;
9523 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
9525 for (i
= 0; i
<= lasti
; ++i
) {
9526 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
9528 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9529 alu
.last
= i
== lasti
;
9530 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
9540 ctx
->bc
->ar_loaded
= 0;
9544 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
9546 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9547 struct r600_bytecode_alu alu
;
9550 for (i
= 0; i
< 4; i
++) {
9551 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9553 alu
.op
= ALU_OP2_MUL
;
9554 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9556 if (i
== 0 || i
== 3) {
9557 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
9559 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9562 if (i
== 0 || i
== 2) {
9563 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
9565 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
9569 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9576 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
, int alu_type
)
9578 struct r600_bytecode_alu alu
;
9581 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9583 alu
.execute_mask
= 1;
9584 alu
.update_pred
= 1;
9586 alu
.dst
.sel
= ctx
->temp_reg
;
9590 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9591 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
9592 alu
.src
[1].chan
= 0;
9596 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, alu_type
);
9602 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
9604 unsigned force_pop
= ctx
->bc
->force_add_cf
;
9608 if (ctx
->bc
->cf_last
) {
9609 if (ctx
->bc
->cf_last
->op
== CF_OP_ALU
)
9611 else if (ctx
->bc
->cf_last
->op
== CF_OP_ALU_POP_AFTER
)
9616 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP_AFTER
;
9617 ctx
->bc
->force_add_cf
= 1;
9618 } else if (alu_pop
== 2) {
9619 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP2_AFTER
;
9620 ctx
->bc
->force_add_cf
= 1;
9627 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
9628 ctx
->bc
->cf_last
->pop_count
= pops
;
9629 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9635 static inline void callstack_update_max_depth(struct r600_shader_ctx
*ctx
,
9638 struct r600_stack_info
*stack
= &ctx
->bc
->stack
;
9642 unsigned entry_size
= stack
->entry_size
;
9644 elements
= (stack
->loop
+ stack
->push_wqm
) * entry_size
;
9645 elements
+= stack
->push
;
9647 switch (ctx
->bc
->chip_class
) {
9650 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9651 * the stack must be reserved to hold the current active/continue
9653 if (reason
== FC_PUSH_VPM
) {
9659 /* r9xx: any stack operation on empty stack consumes 2 additional
9664 /* FIXME: do the two elements added above cover the cases for the
9668 /* r8xx+: 2 extra elements are not always required, but one extra
9669 * element must be added for each of the following cases:
9670 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9672 * (Currently we don't use ALU_ELSE_AFTER.)
9673 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9674 * PUSH instruction executed.
9676 * NOTE: it seems we also need to reserve additional element in some
9677 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9678 * then STACK_SIZE should be 2 instead of 1 */
9679 if (reason
== FC_PUSH_VPM
) {
9689 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9690 * for all chips, so we use 4 in the final formula, not the real entry_size
9694 entries
= (elements
+ (entry_size
- 1)) / entry_size
;
9696 if (entries
> stack
->max_entries
)
9697 stack
->max_entries
= entries
;
9700 static inline void callstack_pop(struct r600_shader_ctx
*ctx
, unsigned reason
)
9704 --ctx
->bc
->stack
.push
;
9705 assert(ctx
->bc
->stack
.push
>= 0);
9708 --ctx
->bc
->stack
.push_wqm
;
9709 assert(ctx
->bc
->stack
.push_wqm
>= 0);
9712 --ctx
->bc
->stack
.loop
;
9713 assert(ctx
->bc
->stack
.loop
>= 0);
9721 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
)
9725 ++ctx
->bc
->stack
.push
;
9728 ++ctx
->bc
->stack
.push_wqm
;
9730 ++ctx
->bc
->stack
.loop
;
9736 callstack_update_max_depth(ctx
, reason
);
9739 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
9741 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
9743 sp
->mid
= realloc((void *)sp
->mid
,
9744 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
9745 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
9749 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
9751 assert(ctx
->bc
->fc_sp
< ARRAY_SIZE(ctx
->bc
->fc_stack
));
9752 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
9753 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
9757 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
9759 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1];
9769 static int emit_return(struct r600_shader_ctx
*ctx
)
9771 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_RETURN
));
9775 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
9778 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
));
9779 ctx
->bc
->cf_last
->pop_count
= pops
;
9780 /* XXX work out offset */
9784 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
9789 static void emit_testflag(struct r600_shader_ctx
*ctx
)
9794 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
9797 emit_jump_to_offset(ctx
, 1, 4);
9798 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
9799 pops(ctx
, ifidx
+ 1);
9803 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
9807 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
9808 ctx
->bc
->cf_last
->pop_count
= 1;
9810 fc_set_mid(ctx
, fc_sp
);
9816 static int emit_if(struct r600_shader_ctx
*ctx
, int opcode
)
9818 int alu_type
= CF_OP_ALU_PUSH_BEFORE
;
9820 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9821 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9822 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9823 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9824 if (ctx
->bc
->chip_class
== CAYMAN
&& ctx
->bc
->stack
.loop
> 1) {
9825 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_PUSH
);
9826 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9827 alu_type
= CF_OP_ALU
;
9830 emit_logic_pred(ctx
, opcode
, alu_type
);
9832 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
9834 fc_pushlevel(ctx
, FC_IF
);
9836 callstack_push(ctx
, FC_PUSH_VPM
);
9840 static int tgsi_if(struct r600_shader_ctx
*ctx
)
9842 return emit_if(ctx
, ALU_OP2_PRED_SETNE
);
9845 static int tgsi_uif(struct r600_shader_ctx
*ctx
)
9847 return emit_if(ctx
, ALU_OP2_PRED_SETNE_INT
);
9850 static int tgsi_else(struct r600_shader_ctx
*ctx
)
9852 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_ELSE
);
9853 ctx
->bc
->cf_last
->pop_count
= 1;
9855 fc_set_mid(ctx
, ctx
->bc
->fc_sp
- 1);
9856 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
9860 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
9863 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_IF
) {
9864 R600_ERR("if/endif unbalanced in shader\n");
9868 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
== NULL
) {
9869 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9870 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->pop_count
= 1;
9872 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9876 callstack_pop(ctx
, FC_PUSH_VPM
);
9880 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
9882 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9883 * limited to 4096 iterations, like the other LOOP_* instructions. */
9884 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_START_DX10
);
9886 fc_pushlevel(ctx
, FC_LOOP
);
9888 /* check stack depth */
9889 callstack_push(ctx
, FC_LOOP
);
9893 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
9897 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_END
);
9899 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_LOOP
) {
9900 R600_ERR("loop/endloop in shader code are not paired.\n");
9904 /* fixup loop pointers - from r600isa
9905 LOOP END points to CF after LOOP START,
9906 LOOP START point to CF after LOOP END
9907 BRK/CONT point to LOOP END CF
9909 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->id
+ 2;
9911 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9913 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].num_mid
; i
++) {
9914 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
9916 /* XXX add LOOPRET support */
9918 callstack_pop(ctx
, FC_LOOP
);
9922 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
9926 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
9928 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
- 1].type
)
9933 R600_ERR("Break not inside loop/endloop pair\n");
9937 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
9939 fc_set_mid(ctx
, fscp
- 1);
9944 static int tgsi_gs_emit(struct r600_shader_ctx
*ctx
)
9946 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9947 int stream
= ctx
->literals
[inst
->Src
[0].Register
.Index
* 4 + inst
->Src
[0].Register
.SwizzleX
];
9950 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
9951 emit_gs_ring_writes(ctx
, ctx
->gs_stream_output_info
, stream
, TRUE
);
9953 r
= r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
9955 ctx
->bc
->cf_last
->count
= stream
; // Count field for CUT/EMIT_VERTEX indicates which stream
9956 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
9957 return emit_inc_ring_offset(ctx
, stream
, TRUE
);
9962 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
9964 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9965 struct r600_bytecode_alu alu
;
9967 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9970 for (i
= 0; i
< lasti
+ 1; i
++) {
9971 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9974 if (ctx
->bc
->chip_class
== CAYMAN
) {
9975 for (j
= 0 ; j
< 4; j
++) {
9976 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9978 alu
.op
= ALU_OP2_MULLO_UINT
;
9979 for (k
= 0; k
< inst
->Instruction
.NumSrcRegs
; k
++) {
9980 r600_bytecode_src(&alu
.src
[k
], &ctx
->src
[k
], i
);
9983 alu
.dst
.sel
= ctx
->temp_reg
;
9984 alu
.dst
.write
= (j
== i
);
9987 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9992 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9995 alu
.dst
.sel
= ctx
->temp_reg
;
9998 alu
.op
= ALU_OP2_MULLO_UINT
;
9999 for (j
= 0; j
< 2; j
++) {
10000 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
10004 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10011 for (i
= 0; i
< lasti
+ 1; i
++) {
10012 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
10015 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
10016 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
10018 alu
.op
= ALU_OP2_ADD_INT
;
10020 alu
.src
[0].sel
= ctx
->temp_reg
;
10021 alu
.src
[0].chan
= i
;
10023 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
10027 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10034 static int tgsi_pk2h(struct r600_shader_ctx
*ctx
)
10036 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
10037 struct r600_bytecode_alu alu
;
10039 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
10041 /* temp.xy = f32_to_f16(src) */
10042 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
10043 alu
.op
= ALU_OP1_FLT32_TO_FLT16
;
10045 alu
.dst
.sel
= ctx
->temp_reg
;
10047 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
10048 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10052 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
10054 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10058 /* dst.x = temp.y * 0x10000 + temp.x */
10059 for (i
= 0; i
< lasti
+ 1; i
++) {
10060 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
10063 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
10064 alu
.op
= ALU_OP3_MULADD_UINT24
;
10066 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
10067 alu
.last
= i
== lasti
;
10068 alu
.src
[0].sel
= ctx
->temp_reg
;
10069 alu
.src
[0].chan
= 1;
10070 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
10071 alu
.src
[1].value
= 0x10000;
10072 alu
.src
[2].sel
= ctx
->temp_reg
;
10073 alu
.src
[2].chan
= 0;
10074 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10082 static int tgsi_up2h(struct r600_shader_ctx
*ctx
)
10084 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
10085 struct r600_bytecode_alu alu
;
10087 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
10089 /* temp.x = src.x */
10090 /* note: no need to mask out the high bits */
10091 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
10092 alu
.op
= ALU_OP1_MOV
;
10094 alu
.dst
.sel
= ctx
->temp_reg
;
10096 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
10097 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10101 /* temp.y = src.x >> 16 */
10102 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
10103 alu
.op
= ALU_OP2_LSHR_INT
;
10105 alu
.dst
.sel
= ctx
->temp_reg
;
10107 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
10108 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
10109 alu
.src
[1].value
= 16;
10111 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10115 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
10116 for (i
= 0; i
< lasti
+ 1; i
++) {
10117 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
10119 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
10120 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
10121 alu
.op
= ALU_OP1_FLT16_TO_FLT32
;
10122 alu
.src
[0].sel
= ctx
->temp_reg
;
10123 alu
.src
[0].chan
= i
% 2;
10124 alu
.last
= i
== lasti
;
10125 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10133 static int tgsi_bfe(struct r600_shader_ctx
*ctx
)
10135 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
10136 struct r600_bytecode_alu alu
;
10137 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
10141 if ((inst
->Src
[0].Register
.File
== inst
->Dst
[0].Register
.File
&&
10142 inst
->Src
[0].Register
.Index
== inst
->Dst
[0].Register
.Index
) ||
10143 (inst
->Src
[2].Register
.File
== inst
->Dst
[0].Register
.File
&&
10144 inst
->Src
[2].Register
.Index
== inst
->Dst
[0].Register
.Index
))
10145 dst
= r600_get_temp(ctx
);
10147 r
= tgsi_op3_dst(ctx
, dst
);
10151 for (i
= 0; i
< lasti
+ 1; i
++) {
10152 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
10153 alu
.op
= ALU_OP2_SETGE_INT
;
10154 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], i
);
10155 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
10156 alu
.src
[1].value
= 32;
10157 alu
.dst
.sel
= ctx
->temp_reg
;
10162 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10167 for (i
= 0; i
< lasti
+ 1; i
++) {
10168 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
10169 alu
.op
= ALU_OP3_CNDE_INT
;
10171 alu
.src
[0].sel
= ctx
->temp_reg
;
10172 alu
.src
[0].chan
= i
;
10174 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
10176 alu
.src
[1].sel
= dst
;
10178 alu
.src
[1].sel
= alu
.dst
.sel
;
10179 alu
.src
[1].chan
= i
;
10180 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
10184 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
10192 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
10193 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
10194 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
10195 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
10197 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
10199 [TGSI_OPCODE_RSQ
] = { ALU_OP0_NOP
, tgsi_rsq
},
10200 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
10201 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
10202 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
10203 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
10204 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10205 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10206 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
10207 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
10208 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN_DX10
, tgsi_op2
},
10209 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX_DX10
, tgsi_op2
},
10210 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
10211 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
10212 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
10213 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
10214 [TGSI_OPCODE_FMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10215 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
10216 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
10217 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
10218 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
10219 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
10220 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
10221 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
10222 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
10223 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
10224 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
10225 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
10226 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
10227 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
10228 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
10229 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
10230 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
10231 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
10232 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10233 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10234 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
10235 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10236 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10237 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10238 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10239 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
10240 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
10241 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
10242 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
10243 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
10244 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
10245 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
10246 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
10247 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10248 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
10249 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10250 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10251 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10252 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10253 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10254 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
10255 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
10256 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
10257 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
10258 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10259 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10260 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
10261 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
10262 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
10263 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10264 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
10265 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10266 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10267 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10268 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
10269 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
10270 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
10271 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
10272 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
10273 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
10274 [TGSI_OPCODE_DDX_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10275 [TGSI_OPCODE_DDY_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10276 [81] = { ALU_OP0_NOP
, tgsi_unsupported
},
10277 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
10278 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
10279 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
10280 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
10281 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
10282 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2_trans
},
10283 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
10284 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
10285 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
10286 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
10287 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
10288 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
10289 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
10290 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10291 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
10292 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
10293 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
10294 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
10295 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10296 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
10297 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10298 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10299 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
10300 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10301 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
10302 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10303 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
10304 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
10305 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
10306 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
10307 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10308 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
10309 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
10310 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
10311 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
10312 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
10313 [TGSI_OPCODE_DFMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10314 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2_trans
},
10315 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
10316 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
10317 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
10318 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
10319 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
10320 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2_trans
},
10321 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
10322 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2_trans
},
10323 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
10324 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
10325 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
10326 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
10327 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
10328 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
10329 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
10330 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
10331 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
10332 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
10333 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2_trans
},
10334 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
10335 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2_swap
},
10336 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10337 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10338 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10339 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10340 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
10341 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
10342 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
10343 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
10344 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
10345 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
10346 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
10347 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
10348 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
10349 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
10350 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
10351 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
10352 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_r600_arl
},
10353 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
10354 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
10355 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
10356 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10357 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10358 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
10359 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
10360 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
10361 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10362 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10363 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10364 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10365 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10366 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10367 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10368 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10369 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10370 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10371 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10372 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10373 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10374 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10375 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
10376 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
10377 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_unsupported
},
10378 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_unsupported
},
10379 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_unsupported
},
10380 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_unsupported
},
10381 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10382 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_unsupported
},
10383 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_unsupported
},
10384 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_unsupported
},
10385 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_unsupported
},
10386 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_unsupported
},
10387 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10388 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10389 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10390 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10393 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
10394 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
10395 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
10396 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
10397 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
10398 [TGSI_OPCODE_RSQ
] = { ALU_OP0_NOP
, tgsi_rsq
},
10399 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
10400 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
10401 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
10402 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
10403 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10404 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10405 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
10406 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN_DX10
, tgsi_op2
},
10407 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX_DX10
, tgsi_op2
},
10408 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
10409 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
10410 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
10411 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
10412 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
10413 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
10414 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
10415 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
10416 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
10417 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
10418 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
10419 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
10420 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
10421 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
10422 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
10423 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
10424 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
10425 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
10426 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
10427 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
10428 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
10429 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
10430 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10431 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10432 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
10433 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
10434 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10435 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10436 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10437 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
10438 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
10439 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
10440 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
10441 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
10442 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
10443 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
10444 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
10445 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10446 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
10447 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10448 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
10449 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10450 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10451 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10452 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
10453 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
10454 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
10455 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
10456 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10457 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10458 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
10459 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
10460 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
10461 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10462 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
10463 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10464 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10465 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10466 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
10467 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
10468 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
10469 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
10470 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
10471 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
10472 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10473 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10474 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
10475 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
10476 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
10477 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
10478 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
10479 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
10480 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
10481 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
10482 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
10483 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
10484 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
10485 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
10486 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
10487 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10488 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
10489 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
10490 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
10491 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
10492 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10493 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
10494 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10495 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10496 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
10497 [TGSI_OPCODE_RESQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_resq
},
10498 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
10499 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10500 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
10501 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
10502 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
10503 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
10504 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10505 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
10506 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
10507 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
10508 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
10509 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
10510 /* Refer below for TGSI_OPCODE_DFMA */
10511 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_f2i
},
10512 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
10513 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
10514 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
10515 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
10516 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
10517 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
10518 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
10519 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_f2i
},
10520 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
10521 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
10522 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
10523 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
10524 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
10525 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
10526 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
10527 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
10528 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
10529 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
10530 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
10531 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
10532 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
10533 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10534 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10535 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10536 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10537 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
10538 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
10539 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
10540 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
10541 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
10542 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
10543 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
10544 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
10545 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
10546 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
10547 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
10548 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
10549 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
10550 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
10551 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
10552 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
10553 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_load
},
10554 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_store
},
10555 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
10556 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
10557 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
10558 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10559 [TGSI_OPCODE_ATOMUADD
] = { V_RAT_INST_ADD_RTN
, tgsi_atomic_op
},
10560 [TGSI_OPCODE_ATOMXCHG
] = { V_RAT_INST_XCHG_RTN
, tgsi_atomic_op
},
10561 [TGSI_OPCODE_ATOMCAS
] = { V_RAT_INST_CMPXCHG_INT_RTN
, tgsi_atomic_op
},
10562 [TGSI_OPCODE_ATOMAND
] = { V_RAT_INST_AND_RTN
, tgsi_atomic_op
},
10563 [TGSI_OPCODE_ATOMOR
] = { V_RAT_INST_OR_RTN
, tgsi_atomic_op
},
10564 [TGSI_OPCODE_ATOMXOR
] = { V_RAT_INST_XOR_RTN
, tgsi_atomic_op
},
10565 [TGSI_OPCODE_ATOMUMIN
] = { V_RAT_INST_MIN_UINT_RTN
, tgsi_atomic_op
},
10566 [TGSI_OPCODE_ATOMUMAX
] = { V_RAT_INST_MAX_UINT_RTN
, tgsi_atomic_op
},
10567 [TGSI_OPCODE_ATOMIMIN
] = { V_RAT_INST_MIN_INT_RTN
, tgsi_atomic_op
},
10568 [TGSI_OPCODE_ATOMIMAX
] = { V_RAT_INST_MAX_INT_RTN
, tgsi_atomic_op
},
10569 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10570 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10571 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10572 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
10573 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
10574 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
10575 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
10576 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_bfe
},
10577 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_bfe
},
10578 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
10579 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
10580 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
10581 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
10582 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
10583 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
10584 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10585 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10586 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10587 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
10588 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
10589 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
10590 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
10591 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
10592 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
10593 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
10594 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
10595 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
10596 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
10597 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
10598 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
10599 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
10600 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
10601 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
10602 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10603 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10604 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
10605 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
10606 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
10607 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
10608 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
10609 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
10610 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
10611 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
10612 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10615 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
10616 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
10617 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
10618 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
10619 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, cayman_emit_float_instr
},
10620 [TGSI_OPCODE_RSQ
] = { ALU_OP1_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
10621 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
10622 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
10623 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
10624 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
10625 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10626 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10627 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
10628 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN_DX10
, tgsi_op2
},
10629 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX_DX10
, tgsi_op2
},
10630 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
10631 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
10632 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
10633 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
10634 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
10635 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, cayman_emit_float_instr
},
10636 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
10637 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
10638 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
10639 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
10640 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
10641 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
10642 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
10643 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, cayman_emit_float_instr
},
10644 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, cayman_emit_float_instr
},
10645 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, cayman_pow
},
10646 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
10647 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
10648 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
10649 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
10650 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
10651 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, cayman_trig
},
10652 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10653 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10654 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
10655 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
10656 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10657 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10658 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10659 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
10660 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
10661 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
10662 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
10663 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, cayman_trig
},
10664 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
10665 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
10666 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
10667 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10668 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
10669 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10670 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
10671 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10672 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10673 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10674 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
10675 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
10676 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
10677 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
10678 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10679 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10680 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
10681 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
10682 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
10683 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10684 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
10685 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10686 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10687 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10688 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
10689 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
10690 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
10691 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
10692 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
10693 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
10694 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10695 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10696 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
10697 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
10698 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2
},
10699 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
10700 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
10701 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
10702 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
10703 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
10704 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
10705 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
10706 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
10707 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
10708 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
10709 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10710 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
10711 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
10712 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
10713 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
10714 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10715 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
10716 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10717 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10718 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
10719 [TGSI_OPCODE_RESQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_resq
},
10720 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
10721 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10722 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
10723 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
10724 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
10725 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
10726 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10727 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
10728 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
10729 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
10730 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
10731 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
10732 /* Refer below for TGSI_OPCODE_DFMA */
10733 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2
},
10734 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
10735 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
10736 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
10737 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
10738 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
10739 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
10740 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
10741 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2
},
10742 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2
},
10743 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
10744 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
10745 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
10746 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
10747 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
10748 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
10749 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_INT
, cayman_mul_int_instr
},
10750 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
10751 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
10752 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
10753 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
10754 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
10755 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10756 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10757 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10758 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10759 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
10760 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
10761 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
10762 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
10763 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
10764 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
10765 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
10766 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
10767 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
10768 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
10769 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
10770 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
10771 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
10772 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
10773 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
10774 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
10775 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_load
},
10776 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_store
},
10777 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
10778 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
10779 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
10780 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10781 [TGSI_OPCODE_ATOMUADD
] = { V_RAT_INST_ADD_RTN
, tgsi_atomic_op
},
10782 [TGSI_OPCODE_ATOMXCHG
] = { V_RAT_INST_XCHG_RTN
, tgsi_atomic_op
},
10783 [TGSI_OPCODE_ATOMCAS
] = { V_RAT_INST_CMPXCHG_INT_RTN
, tgsi_atomic_op
},
10784 [TGSI_OPCODE_ATOMAND
] = { V_RAT_INST_AND_RTN
, tgsi_atomic_op
},
10785 [TGSI_OPCODE_ATOMOR
] = { V_RAT_INST_OR_RTN
, tgsi_atomic_op
},
10786 [TGSI_OPCODE_ATOMXOR
] = { V_RAT_INST_XOR_RTN
, tgsi_atomic_op
},
10787 [TGSI_OPCODE_ATOMUMIN
] = { V_RAT_INST_MIN_UINT_RTN
, tgsi_atomic_op
},
10788 [TGSI_OPCODE_ATOMUMAX
] = { V_RAT_INST_MAX_UINT_RTN
, tgsi_atomic_op
},
10789 [TGSI_OPCODE_ATOMIMIN
] = { V_RAT_INST_MIN_INT_RTN
, tgsi_atomic_op
},
10790 [TGSI_OPCODE_ATOMIMAX
] = { V_RAT_INST_MAX_INT_RTN
, tgsi_atomic_op
},
10791 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10792 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10793 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10794 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, cayman_mul_int_instr
},
10795 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, cayman_mul_int_instr
},
10796 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
10797 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
10798 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_bfe
},
10799 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_bfe
},
10800 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
10801 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
10802 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
10803 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
10804 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
10805 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
10806 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10807 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10808 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10809 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
10810 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
10811 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
10812 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
10813 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
10814 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
10815 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
10816 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
10817 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
10818 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
10819 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
10820 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
10821 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
10822 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
10823 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
10824 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10825 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10826 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
10827 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
10828 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
10829 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
10830 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
10831 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
10832 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
10833 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
10834 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},