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r600g: increase array base for exported parameters
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_context *rctx,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static void r600_dump_streamout(struct pipe_stream_output_info *so)
88 {
89 unsigned i;
90
91 fprintf(stderr, "STREAMOUT\n");
92 for (i = 0; i < so->num_outputs; i++) {
93 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
94 so->output[i].start_component;
95 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
96 i, so->output[i].output_buffer,
97 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
98 so->output[i].register_index,
99 mask & 1 ? "x" : "",
100 mask & 2 ? "y" : "",
101 mask & 4 ? "z" : "",
102 mask & 8 ? "w" : "",
103 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
104 }
105 }
106
107 static int store_shader(struct pipe_context *ctx,
108 struct r600_pipe_shader *shader)
109 {
110 struct r600_context *rctx = (struct r600_context *)ctx;
111 uint32_t *ptr, i;
112
113 if (shader->bo == NULL) {
114 shader->bo = (struct r600_resource*)
115 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
116 if (shader->bo == NULL) {
117 return -ENOMEM;
118 }
119 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
120 if (R600_BIG_ENDIAN) {
121 for (i = 0; i < shader->shader.bc.ndw; ++i) {
122 ptr[i] = util_bswap32(shader->shader.bc.bytecode[i]);
123 }
124 } else {
125 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
126 }
127 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
128 }
129
130 return 0;
131 }
132
133 int r600_pipe_shader_create(struct pipe_context *ctx,
134 struct r600_pipe_shader *shader,
135 struct r600_shader_key key)
136 {
137 struct r600_context *rctx = (struct r600_context *)ctx;
138 struct r600_pipe_shader_selector *sel = shader->selector;
139 int r;
140 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
141 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
142 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
143 unsigned export_shader = key.vs_as_es;
144
145 shader->shader.bc.isa = rctx->isa;
146
147 if (dump) {
148 fprintf(stderr, "--------------------------------------------------------------\n");
149 tgsi_dump(sel->tokens, 0);
150
151 if (sel->so.num_outputs) {
152 r600_dump_streamout(&sel->so);
153 }
154 }
155 r = r600_shader_from_tgsi(rctx, shader, key);
156 if (r) {
157 R600_ERR("translation from TGSI failed !\n");
158 return r;
159 }
160
161 /* disable SB for geom shaders - it can't handle the CF_EMIT instructions */
162 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_GEOMETRY);
163
164 /* Check if the bytecode has already been built. When using the llvm
165 * backend, r600_shader_from_tgsi() will take care of building the
166 * bytecode.
167 */
168 if (!shader->shader.bc.bytecode) {
169 r = r600_bytecode_build(&shader->shader.bc);
170 if (r) {
171 R600_ERR("building bytecode failed !\n");
172 return r;
173 }
174 }
175
176 if (dump && !sb_disasm) {
177 fprintf(stderr, "--------------------------------------------------------------\n");
178 r600_bytecode_disasm(&shader->shader.bc);
179 fprintf(stderr, "______________________________________________________________\n");
180 } else if ((dump && sb_disasm) || use_sb) {
181 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
182 dump, use_sb);
183 if (r) {
184 R600_ERR("r600_sb_bytecode_process failed !\n");
185 return r;
186 }
187 }
188
189 if (shader->gs_copy_shader) {
190 if (dump) {
191 // dump copy shader
192 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
193 &shader->gs_copy_shader->shader, dump, 0);
194 if (r)
195 return r;
196 }
197
198 if ((r = store_shader(ctx, shader->gs_copy_shader)))
199 return r;
200 }
201
202 /* Store the shader in a buffer. */
203 if ((r = store_shader(ctx, shader)))
204 return r;
205
206 /* Build state. */
207 switch (shader->shader.processor_type) {
208 case TGSI_PROCESSOR_GEOMETRY:
209 if (rctx->b.chip_class >= EVERGREEN) {
210 evergreen_update_gs_state(ctx, shader);
211 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
212 } else {
213 assert(!"not suported yet");
214 }
215 break;
216 case TGSI_PROCESSOR_VERTEX:
217 if (rctx->b.chip_class >= EVERGREEN) {
218 if (export_shader)
219 evergreen_update_es_state(ctx, shader);
220 else
221 evergreen_update_vs_state(ctx, shader);
222 } else {
223 r600_update_vs_state(ctx, shader);
224 }
225 break;
226 case TGSI_PROCESSOR_FRAGMENT:
227 if (rctx->b.chip_class >= EVERGREEN) {
228 evergreen_update_ps_state(ctx, shader);
229 } else {
230 r600_update_ps_state(ctx, shader);
231 }
232 break;
233 default:
234 return -EINVAL;
235 }
236 return 0;
237 }
238
239 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
240 {
241 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
242 r600_bytecode_clear(&shader->shader.bc);
243 r600_release_command_buffer(&shader->command_buffer);
244 }
245
246 /*
247 * tgsi -> r600 shader
248 */
249 struct r600_shader_tgsi_instruction;
250
251 struct r600_shader_src {
252 unsigned sel;
253 unsigned swizzle[4];
254 unsigned neg;
255 unsigned abs;
256 unsigned rel;
257 unsigned kc_bank;
258 uint32_t value[4];
259 };
260
261 struct r600_shader_ctx {
262 struct tgsi_shader_info info;
263 struct tgsi_parse_context parse;
264 const struct tgsi_token *tokens;
265 unsigned type;
266 unsigned file_offset[TGSI_FILE_COUNT];
267 unsigned temp_reg;
268 struct r600_shader_tgsi_instruction *inst_info;
269 struct r600_bytecode *bc;
270 struct r600_shader *shader;
271 struct r600_shader_src src[4];
272 uint32_t *literals;
273 uint32_t nliterals;
274 uint32_t max_driver_temp_used;
275 boolean use_llvm;
276 /* needed for evergreen interpolation */
277 boolean input_centroid;
278 boolean input_linear;
279 boolean input_perspective;
280 int num_interp_gpr;
281 int face_gpr;
282 int colors_used;
283 boolean clip_vertex_write;
284 unsigned cv_output;
285 int fragcoord_input;
286 int native_integers;
287 int next_ring_offset;
288 int gs_next_vertex;
289 struct r600_shader *gs_for_vs;
290 };
291
292 struct r600_shader_tgsi_instruction {
293 unsigned tgsi_opcode;
294 unsigned is_op3;
295 unsigned op;
296 int (*process)(struct r600_shader_ctx *ctx);
297 };
298
299 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx);
300 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
301 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
302 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
303 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
304 static int tgsi_else(struct r600_shader_ctx *ctx);
305 static int tgsi_endif(struct r600_shader_ctx *ctx);
306 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
307 static int tgsi_endloop(struct r600_shader_ctx *ctx);
308 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
309
310 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
311 {
312 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
313 int j;
314
315 if (i->Instruction.NumDstRegs > 1) {
316 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
317 return -EINVAL;
318 }
319 if (i->Instruction.Predicate) {
320 R600_ERR("predicate unsupported\n");
321 return -EINVAL;
322 }
323 #if 0
324 if (i->Instruction.Label) {
325 R600_ERR("label unsupported\n");
326 return -EINVAL;
327 }
328 #endif
329 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
330 if (i->Src[j].Register.Dimension) {
331 switch (i->Src[j].Register.File) {
332 case TGSI_FILE_CONSTANT:
333 break;
334 case TGSI_FILE_INPUT:
335 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
336 break;
337 default:
338 R600_ERR("unsupported src %d (dimension %d)\n", j,
339 i->Src[j].Register.Dimension);
340 return -EINVAL;
341 }
342 }
343 }
344 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
345 if (i->Dst[j].Register.Dimension) {
346 R600_ERR("unsupported dst (dimension)\n");
347 return -EINVAL;
348 }
349 }
350 return 0;
351 }
352
353 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
354 int input)
355 {
356 int ij_index = 0;
357
358 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
359 if (ctx->shader->input[input].centroid)
360 ij_index++;
361 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
362 /* if we have perspective add one */
363 if (ctx->input_perspective) {
364 ij_index++;
365 /* if we have perspective centroid */
366 if (ctx->input_centroid)
367 ij_index++;
368 }
369 if (ctx->shader->input[input].centroid)
370 ij_index++;
371 }
372
373 ctx->shader->input[input].ij_index = ij_index;
374 }
375
376 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
377 {
378 int i, r;
379 struct r600_bytecode_alu alu;
380 int gpr = 0, base_chan = 0;
381 int ij_index = ctx->shader->input[input].ij_index;
382
383 /* work out gpr and base_chan from index */
384 gpr = ij_index / 2;
385 base_chan = (2 * (ij_index % 2)) + 1;
386
387 for (i = 0; i < 8; i++) {
388 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
389
390 if (i < 4)
391 alu.op = ALU_OP2_INTERP_ZW;
392 else
393 alu.op = ALU_OP2_INTERP_XY;
394
395 if ((i > 1) && (i < 6)) {
396 alu.dst.sel = ctx->shader->input[input].gpr;
397 alu.dst.write = 1;
398 }
399
400 alu.dst.chan = i % 4;
401
402 alu.src[0].sel = gpr;
403 alu.src[0].chan = (base_chan - (i % 2));
404
405 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
406
407 alu.bank_swizzle_force = SQ_ALU_VEC_210;
408 if ((i % 4) == 3)
409 alu.last = 1;
410 r = r600_bytecode_add_alu(ctx->bc, &alu);
411 if (r)
412 return r;
413 }
414 return 0;
415 }
416
417 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
418 {
419 int i, r;
420 struct r600_bytecode_alu alu;
421
422 for (i = 0; i < 4; i++) {
423 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
424
425 alu.op = ALU_OP1_INTERP_LOAD_P0;
426
427 alu.dst.sel = ctx->shader->input[input].gpr;
428 alu.dst.write = 1;
429
430 alu.dst.chan = i;
431
432 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
433 alu.src[0].chan = i;
434
435 if (i == 3)
436 alu.last = 1;
437 r = r600_bytecode_add_alu(ctx->bc, &alu);
438 if (r)
439 return r;
440 }
441 return 0;
442 }
443
444 /*
445 * Special export handling in shaders
446 *
447 * shader export ARRAY_BASE for EXPORT_POS:
448 * 60 is position
449 * 61 is misc vector
450 * 62, 63 are clip distance vectors
451 *
452 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
453 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
454 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
455 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
456 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
457 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
458 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
459 * exclusive from render target index)
460 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
461 *
462 *
463 * shader export ARRAY_BASE for EXPORT_PIXEL:
464 * 0-7 CB targets
465 * 61 computed Z vector
466 *
467 * The use of the values exported in the computed Z vector are controlled
468 * by DB_SHADER_CONTROL:
469 * Z_EXPORT_ENABLE - Z as a float in RED
470 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
471 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
472 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
473 * DB_SOURCE_FORMAT - export control restrictions
474 *
475 */
476
477
478 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
479 static int r600_spi_sid(struct r600_shader_io * io)
480 {
481 int index, name = io->name;
482
483 /* These params are handled differently, they don't need
484 * semantic indices, so we'll use 0 for them.
485 */
486 if (name == TGSI_SEMANTIC_POSITION ||
487 name == TGSI_SEMANTIC_PSIZE ||
488 name == TGSI_SEMANTIC_FACE)
489 index = 0;
490 else {
491 if (name == TGSI_SEMANTIC_GENERIC) {
492 /* For generic params simply use sid from tgsi */
493 index = io->sid;
494 } else {
495 /* For non-generic params - pack name and sid into 8 bits */
496 index = 0x80 | (name<<3) | (io->sid);
497 }
498
499 /* Make sure that all really used indices have nonzero value, so
500 * we can just compare it to 0 later instead of comparing the name
501 * with different values to detect special cases. */
502 index++;
503 }
504
505 return index;
506 };
507
508 /* turn input into interpolate on EG */
509 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
510 {
511 int r = 0;
512
513 if (ctx->shader->input[index].spi_sid) {
514 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
515 if (ctx->shader->input[index].interpolate > 0) {
516 evergreen_interp_assign_ij_index(ctx, index);
517 if (!ctx->use_llvm)
518 r = evergreen_interp_alu(ctx, index);
519 } else {
520 if (!ctx->use_llvm)
521 r = evergreen_interp_flat(ctx, index);
522 }
523 }
524 return r;
525 }
526
527 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
528 {
529 struct r600_bytecode_alu alu;
530 int i, r;
531 int gpr_front = ctx->shader->input[front].gpr;
532 int gpr_back = ctx->shader->input[back].gpr;
533
534 for (i = 0; i < 4; i++) {
535 memset(&alu, 0, sizeof(alu));
536 alu.op = ALU_OP3_CNDGT;
537 alu.is_op3 = 1;
538 alu.dst.write = 1;
539 alu.dst.sel = gpr_front;
540 alu.src[0].sel = ctx->face_gpr;
541 alu.src[1].sel = gpr_front;
542 alu.src[2].sel = gpr_back;
543
544 alu.dst.chan = i;
545 alu.src[1].chan = i;
546 alu.src[2].chan = i;
547 alu.last = (i==3);
548
549 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
550 return r;
551 }
552
553 return 0;
554 }
555
556 static int tgsi_declaration(struct r600_shader_ctx *ctx)
557 {
558 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
559 int r, i, j, count = d->Range.Last - d->Range.First + 1;
560
561 switch (d->Declaration.File) {
562 case TGSI_FILE_INPUT:
563 i = ctx->shader->ninput;
564 assert(i < Elements(ctx->shader->input));
565 ctx->shader->ninput += count;
566 ctx->shader->input[i].name = d->Semantic.Name;
567 ctx->shader->input[i].sid = d->Semantic.Index;
568 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
569 ctx->shader->input[i].centroid = d->Interp.Centroid;
570 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
571 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
572 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
573 switch (ctx->shader->input[i].name) {
574 case TGSI_SEMANTIC_FACE:
575 ctx->face_gpr = ctx->shader->input[i].gpr;
576 break;
577 case TGSI_SEMANTIC_COLOR:
578 ctx->colors_used++;
579 break;
580 case TGSI_SEMANTIC_POSITION:
581 ctx->fragcoord_input = i;
582 break;
583 }
584 if (ctx->bc->chip_class >= EVERGREEN) {
585 if ((r = evergreen_interp_input(ctx, i)))
586 return r;
587 }
588 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
589 /* FIXME probably skip inputs if they aren't passed in the ring */
590 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
591 ctx->next_ring_offset += 16;
592 }
593 for (j = 1; j < count; ++j) {
594 ctx->shader->input[i + j] = ctx->shader->input[i];
595 ctx->shader->input[i + j].gpr += j;
596 }
597 break;
598 case TGSI_FILE_OUTPUT:
599 i = ctx->shader->noutput++;
600 assert(i < Elements(ctx->shader->output));
601 ctx->shader->output[i].name = d->Semantic.Name;
602 ctx->shader->output[i].sid = d->Semantic.Index;
603 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
604 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
605 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
606 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
607 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
608 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
609 switch (d->Semantic.Name) {
610 case TGSI_SEMANTIC_CLIPDIST:
611 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
612 break;
613 case TGSI_SEMANTIC_PSIZE:
614 ctx->shader->vs_out_misc_write = 1;
615 ctx->shader->vs_out_point_size = 1;
616 break;
617 case TGSI_SEMANTIC_CLIPVERTEX:
618 ctx->clip_vertex_write = TRUE;
619 ctx->cv_output = i;
620 break;
621 }
622 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
623 switch (d->Semantic.Name) {
624 case TGSI_SEMANTIC_COLOR:
625 ctx->shader->nr_ps_max_color_exports++;
626 break;
627 }
628 }
629 break;
630 case TGSI_FILE_TEMPORARY:
631 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
632 if (d->Array.ArrayID) {
633 r600_add_gpr_array(ctx->shader,
634 ctx->file_offset[TGSI_FILE_TEMPORARY] +
635 d->Range.First,
636 d->Range.Last - d->Range.First + 1, 0x0F);
637 }
638 }
639 break;
640
641 case TGSI_FILE_CONSTANT:
642 case TGSI_FILE_SAMPLER:
643 case TGSI_FILE_ADDRESS:
644 break;
645
646 case TGSI_FILE_SYSTEM_VALUE:
647 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
648 if (!ctx->native_integers) {
649 struct r600_bytecode_alu alu;
650 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
651
652 alu.op = ALU_OP1_INT_TO_FLT;
653 alu.src[0].sel = 0;
654 alu.src[0].chan = 3;
655
656 alu.dst.sel = 0;
657 alu.dst.chan = 3;
658 alu.dst.write = 1;
659 alu.last = 1;
660
661 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
662 return r;
663 }
664 break;
665 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
666 break;
667 default:
668 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
669 return -EINVAL;
670 }
671 return 0;
672 }
673
674 static int r600_get_temp(struct r600_shader_ctx *ctx)
675 {
676 return ctx->temp_reg + ctx->max_driver_temp_used++;
677 }
678
679 /*
680 * for evergreen we need to scan the shader to find the number of GPRs we need to
681 * reserve for interpolation.
682 *
683 * we need to know if we are going to emit
684 * any centroid inputs
685 * if perspective and linear are required
686 */
687 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
688 {
689 int i;
690 int num_baryc;
691
692 ctx->input_linear = FALSE;
693 ctx->input_perspective = FALSE;
694 ctx->input_centroid = FALSE;
695 ctx->num_interp_gpr = 1;
696
697 /* any centroid inputs */
698 for (i = 0; i < ctx->info.num_inputs; i++) {
699 /* skip position/face */
700 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
701 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
702 continue;
703 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
704 ctx->input_linear = TRUE;
705 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
706 ctx->input_perspective = TRUE;
707 if (ctx->info.input_centroid[i])
708 ctx->input_centroid = TRUE;
709 }
710
711 num_baryc = 0;
712 /* ignoring sample for now */
713 if (ctx->input_perspective)
714 num_baryc++;
715 if (ctx->input_linear)
716 num_baryc++;
717 if (ctx->input_centroid)
718 num_baryc *= 2;
719
720 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
721
722 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
723 return ctx->num_interp_gpr;
724 }
725
726 static void tgsi_src(struct r600_shader_ctx *ctx,
727 const struct tgsi_full_src_register *tgsi_src,
728 struct r600_shader_src *r600_src)
729 {
730 memset(r600_src, 0, sizeof(*r600_src));
731 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
732 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
733 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
734 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
735 r600_src->neg = tgsi_src->Register.Negate;
736 r600_src->abs = tgsi_src->Register.Absolute;
737
738 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
739 int index;
740 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
741 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
742 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
743
744 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
745 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
746 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
747 return;
748 }
749 index = tgsi_src->Register.Index;
750 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
751 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
752 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
753 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
754 r600_src->swizzle[0] = 3;
755 r600_src->swizzle[1] = 3;
756 r600_src->swizzle[2] = 3;
757 r600_src->swizzle[3] = 3;
758 r600_src->sel = 0;
759 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
760 r600_src->swizzle[0] = 0;
761 r600_src->swizzle[1] = 0;
762 r600_src->swizzle[2] = 0;
763 r600_src->swizzle[3] = 0;
764 r600_src->sel = 0;
765 }
766 } else {
767 if (tgsi_src->Register.Indirect)
768 r600_src->rel = V_SQ_REL_RELATIVE;
769 r600_src->sel = tgsi_src->Register.Index;
770 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
771 }
772 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
773 if (tgsi_src->Register.Dimension) {
774 r600_src->kc_bank = tgsi_src->Dimension.Index;
775 }
776 }
777 }
778
779 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
780 {
781 struct r600_bytecode_vtx vtx;
782 unsigned int ar_reg;
783 int r;
784
785 if (offset) {
786 struct r600_bytecode_alu alu;
787
788 memset(&alu, 0, sizeof(alu));
789
790 alu.op = ALU_OP2_ADD_INT;
791 alu.src[0].sel = ctx->bc->ar_reg;
792
793 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
794 alu.src[1].value = offset;
795
796 alu.dst.sel = dst_reg;
797 alu.dst.write = 1;
798 alu.last = 1;
799
800 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
801 return r;
802
803 ar_reg = dst_reg;
804 } else {
805 ar_reg = ctx->bc->ar_reg;
806 }
807
808 memset(&vtx, 0, sizeof(vtx));
809 vtx.buffer_id = cb_idx;
810 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
811 vtx.src_gpr = ar_reg;
812 vtx.mega_fetch_count = 16;
813 vtx.dst_gpr = dst_reg;
814 vtx.dst_sel_x = 0; /* SEL_X */
815 vtx.dst_sel_y = 1; /* SEL_Y */
816 vtx.dst_sel_z = 2; /* SEL_Z */
817 vtx.dst_sel_w = 3; /* SEL_W */
818 vtx.data_format = FMT_32_32_32_32_FLOAT;
819 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
820 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
821 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
822 vtx.endian = r600_endian_swap(32);
823
824 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
825 return r;
826
827 return 0;
828 }
829
830 static int fetch_gs_input(struct r600_shader_ctx *ctx, unsigned index, unsigned vtx_id, unsigned int dst_reg)
831 {
832 struct r600_bytecode_vtx vtx;
833 int r;
834 int offset_reg = vtx_id / 3;
835 int offset_chan = vtx_id % 3;
836
837 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
838 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
839
840 if (offset_reg == 0 && offset_chan == 2)
841 offset_chan = 3;
842
843 memset(&vtx, 0, sizeof(vtx));
844 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
845 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
846 vtx.src_gpr = offset_reg;
847 vtx.src_sel_x = offset_chan;
848 vtx.offset = index * 16; /*bytes*/
849 vtx.mega_fetch_count = 16;
850 vtx.dst_gpr = dst_reg;
851 vtx.dst_sel_x = 0; /* SEL_X */
852 vtx.dst_sel_y = 1; /* SEL_Y */
853 vtx.dst_sel_z = 2; /* SEL_Z */
854 vtx.dst_sel_w = 3; /* SEL_W */
855 vtx.use_const_fields = 1;
856
857 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
858 return r;
859
860 return 0;
861 }
862
863 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
864 {
865 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
866 int i;
867
868 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
869 struct tgsi_full_src_register *src = &inst->Src[i];
870
871 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
872 int treg = r600_get_temp(ctx);
873 int index = src->Register.Index;
874 int vtx_id = src->Dimension.Index;
875
876 fetch_gs_input(ctx, index, vtx_id, treg);
877 ctx->src[i].sel = treg;
878 }
879 }
880 return 0;
881 }
882
883 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
884 {
885 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
886 struct r600_bytecode_alu alu;
887 int i, j, k, nconst, r;
888
889 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
890 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
891 nconst++;
892 }
893 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
894 }
895 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
896 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
897 continue;
898 }
899
900 if (ctx->src[i].rel) {
901 int treg = r600_get_temp(ctx);
902 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
903 return r;
904
905 ctx->src[i].kc_bank = 0;
906 ctx->src[i].sel = treg;
907 ctx->src[i].rel = 0;
908 j--;
909 } else if (j > 0) {
910 int treg = r600_get_temp(ctx);
911 for (k = 0; k < 4; k++) {
912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
913 alu.op = ALU_OP1_MOV;
914 alu.src[0].sel = ctx->src[i].sel;
915 alu.src[0].chan = k;
916 alu.src[0].rel = ctx->src[i].rel;
917 alu.dst.sel = treg;
918 alu.dst.chan = k;
919 alu.dst.write = 1;
920 if (k == 3)
921 alu.last = 1;
922 r = r600_bytecode_add_alu(ctx->bc, &alu);
923 if (r)
924 return r;
925 }
926 ctx->src[i].sel = treg;
927 ctx->src[i].rel =0;
928 j--;
929 }
930 }
931 return 0;
932 }
933
934 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
935 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
936 {
937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
938 struct r600_bytecode_alu alu;
939 int i, j, k, nliteral, r;
940
941 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
942 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
943 nliteral++;
944 }
945 }
946 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
947 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
948 int treg = r600_get_temp(ctx);
949 for (k = 0; k < 4; k++) {
950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
951 alu.op = ALU_OP1_MOV;
952 alu.src[0].sel = ctx->src[i].sel;
953 alu.src[0].chan = k;
954 alu.src[0].value = ctx->src[i].value[k];
955 alu.dst.sel = treg;
956 alu.dst.chan = k;
957 alu.dst.write = 1;
958 if (k == 3)
959 alu.last = 1;
960 r = r600_bytecode_add_alu(ctx->bc, &alu);
961 if (r)
962 return r;
963 }
964 ctx->src[i].sel = treg;
965 j--;
966 }
967 }
968 return 0;
969 }
970
971 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
972 {
973 int i, r, count = ctx->shader->ninput;
974
975 for (i = 0; i < count; i++) {
976 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
977 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
978 if (r)
979 return r;
980 }
981 }
982 return 0;
983 }
984
985 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so)
986 {
987 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
988 int i, j, r;
989
990 /* Sanity checking. */
991 if (so->num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
992 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
993 r = -EINVAL;
994 goto out_err;
995 }
996 for (i = 0; i < so->num_outputs; i++) {
997 if (so->output[i].output_buffer >= 4) {
998 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
999 so->output[i].output_buffer);
1000 r = -EINVAL;
1001 goto out_err;
1002 }
1003 }
1004
1005 /* Initialize locations where the outputs are stored. */
1006 for (i = 0; i < so->num_outputs; i++) {
1007 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1008
1009 /* Lower outputs with dst_offset < start_component.
1010 *
1011 * We can only output 4D vectors with a write mask, e.g. we can
1012 * only output the W component at offset 3, etc. If we want
1013 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1014 * to move it to X and output X. */
1015 if (so->output[i].dst_offset < so->output[i].start_component) {
1016 unsigned tmp = r600_get_temp(ctx);
1017
1018 for (j = 0; j < so->output[i].num_components; j++) {
1019 struct r600_bytecode_alu alu;
1020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1021 alu.op = ALU_OP1_MOV;
1022 alu.src[0].sel = so_gpr[i];
1023 alu.src[0].chan = so->output[i].start_component + j;
1024
1025 alu.dst.sel = tmp;
1026 alu.dst.chan = j;
1027 alu.dst.write = 1;
1028 if (j == so->output[i].num_components - 1)
1029 alu.last = 1;
1030 r = r600_bytecode_add_alu(ctx->bc, &alu);
1031 if (r)
1032 return r;
1033 }
1034 so->output[i].start_component = 0;
1035 so_gpr[i] = tmp;
1036 }
1037 }
1038
1039 /* Write outputs to buffers. */
1040 for (i = 0; i < so->num_outputs; i++) {
1041 struct r600_bytecode_output output;
1042
1043 memset(&output, 0, sizeof(struct r600_bytecode_output));
1044 output.gpr = so_gpr[i];
1045 output.elem_size = so->output[i].num_components;
1046 output.array_base = so->output[i].dst_offset - so->output[i].start_component;
1047 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1048 output.burst_count = 1;
1049 /* array_size is an upper limit for the burst_count
1050 * with MEM_STREAM instructions */
1051 output.array_size = 0xFFF;
1052 output.comp_mask = ((1 << so->output[i].num_components) - 1) << so->output[i].start_component;
1053 if (ctx->bc->chip_class >= EVERGREEN) {
1054 switch (so->output[i].output_buffer) {
1055 case 0:
1056 output.op = CF_OP_MEM_STREAM0_BUF0;
1057 break;
1058 case 1:
1059 output.op = CF_OP_MEM_STREAM0_BUF1;
1060 break;
1061 case 2:
1062 output.op = CF_OP_MEM_STREAM0_BUF2;
1063 break;
1064 case 3:
1065 output.op = CF_OP_MEM_STREAM0_BUF3;
1066 break;
1067 }
1068 } else {
1069 switch (so->output[i].output_buffer) {
1070 case 0:
1071 output.op = CF_OP_MEM_STREAM0;
1072 break;
1073 case 1:
1074 output.op = CF_OP_MEM_STREAM1;
1075 break;
1076 case 2:
1077 output.op = CF_OP_MEM_STREAM2;
1078 break;
1079 case 3:
1080 output.op = CF_OP_MEM_STREAM3;
1081 break;
1082 }
1083 }
1084 r = r600_bytecode_add_output(ctx->bc, &output);
1085 if (r)
1086 goto out_err;
1087 }
1088 return 0;
1089 out_err:
1090 return r;
1091 }
1092
1093 static int generate_gs_copy_shader(struct r600_context *rctx,
1094 struct r600_pipe_shader *gs)
1095 {
1096 struct r600_shader_ctx ctx = {};
1097 struct r600_shader *gs_shader = &gs->shader;
1098 struct r600_pipe_shader *cshader;
1099 int ocnt = gs_shader->noutput;
1100 struct r600_bytecode_alu alu;
1101 struct r600_bytecode_vtx vtx;
1102 struct r600_bytecode_output output;
1103 struct r600_bytecode_cf *cf_jump, *cf_pop,
1104 *last_exp_pos = NULL, *last_exp_param = NULL;
1105 int i, next_pos = 60, next_param = 0;
1106
1107 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1108 if (!cshader)
1109 return 0;
1110
1111 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1112 sizeof(struct r600_shader_io));
1113
1114 cshader->shader.noutput = ocnt;
1115
1116 ctx.shader = &cshader->shader;
1117 ctx.bc = &ctx.shader->bc;
1118 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1119
1120 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1121 rctx->screen->has_compressed_msaa_texturing);
1122
1123 ctx.bc->isa = rctx->isa;
1124
1125 /* R0.x = R0.x & 0x3fffffff */
1126 memset(&alu, 0, sizeof(alu));
1127 alu.op = ALU_OP2_AND_INT;
1128 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1129 alu.src[1].value = 0x3fffffff;
1130 alu.dst.write = 1;
1131 r600_bytecode_add_alu(ctx.bc, &alu);
1132
1133 /* R0.y = R0.x >> 30 */
1134 memset(&alu, 0, sizeof(alu));
1135 alu.op = ALU_OP2_LSHR_INT;
1136 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1137 alu.src[1].value = 0x1e;
1138 alu.dst.chan = 1;
1139 alu.dst.write = 1;
1140 alu.last = 1;
1141 r600_bytecode_add_alu(ctx.bc, &alu);
1142
1143 /* PRED_SETE_INT __, R0.y, 0 */
1144 memset(&alu, 0, sizeof(alu));
1145 alu.op = ALU_OP2_PRED_SETE_INT;
1146 alu.src[0].chan = 1;
1147 alu.src[1].sel = V_SQ_ALU_SRC_0;
1148 alu.execute_mask = 1;
1149 alu.update_pred = 1;
1150 alu.last = 1;
1151 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1152
1153 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1154 cf_jump = ctx.bc->cf_last;
1155
1156 /* fetch vertex data from GSVS ring */
1157 for (i = 0; i < ocnt; ++i) {
1158 struct r600_shader_io *out = &ctx.shader->output[i];
1159 out->gpr = i + 1;
1160 out->ring_offset = i * 16;
1161
1162 memset(&vtx, 0, sizeof(vtx));
1163 vtx.op = FETCH_OP_VFETCH;
1164 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1165 vtx.fetch_type = 2;
1166 vtx.offset = out->ring_offset;
1167 vtx.dst_gpr = out->gpr;
1168 vtx.dst_sel_x = 0;
1169 vtx.dst_sel_y = 1;
1170 vtx.dst_sel_z = 2;
1171 vtx.dst_sel_w = 3;
1172 vtx.use_const_fields = 1;
1173
1174 r600_bytecode_add_vtx(ctx.bc, &vtx);
1175 }
1176
1177 /* XXX handle clipvertex, streamout? */
1178
1179 /* export vertex data */
1180 /* XXX factor out common code with r600_shader_from_tgsi ? */
1181 for (i = 0; i < ocnt; ++i) {
1182 struct r600_shader_io *out = &ctx.shader->output[i];
1183
1184 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1185 continue;
1186
1187 memset(&output, 0, sizeof(output));
1188 output.gpr = out->gpr;
1189 output.elem_size = 3;
1190 output.swizzle_x = 0;
1191 output.swizzle_y = 1;
1192 output.swizzle_z = 2;
1193 output.swizzle_w = 3;
1194 output.burst_count = 1;
1195 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1196 output.op = CF_OP_EXPORT;
1197 switch (out->name) {
1198 case TGSI_SEMANTIC_POSITION:
1199 output.array_base = next_pos++;
1200 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1201 break;
1202
1203 case TGSI_SEMANTIC_PSIZE:
1204 output.array_base = next_pos++;
1205 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1206 break;
1207 case TGSI_SEMANTIC_CLIPDIST:
1208 /* spi_sid is 0 for clipdistance outputs that were generated
1209 * for clipvertex - we don't need to pass them to PS */
1210 if (out->spi_sid) {
1211 /* duplicate it as PARAM to pass to the pixel shader */
1212 output.array_base = next_param++;
1213 r600_bytecode_add_output(ctx.bc, &output);
1214 last_exp_param = ctx.bc->cf_last;
1215 }
1216 output.array_base = next_pos++;
1217 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1218 break;
1219 case TGSI_SEMANTIC_FOG:
1220 output.swizzle_y = 4; /* 0 */
1221 output.swizzle_z = 4; /* 0 */
1222 output.swizzle_w = 5; /* 1 */
1223 break;
1224 default:
1225 output.array_base = next_param++;
1226 break;
1227 }
1228 r600_bytecode_add_output(ctx.bc, &output);
1229 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1230 last_exp_param = ctx.bc->cf_last;
1231 else
1232 last_exp_pos = ctx.bc->cf_last;
1233 }
1234
1235 if (!last_exp_pos) {
1236 memset(&output, 0, sizeof(output));
1237 output.gpr = 0;
1238 output.elem_size = 3;
1239 output.swizzle_x = 7;
1240 output.swizzle_y = 7;
1241 output.swizzle_z = 7;
1242 output.swizzle_w = 7;
1243 output.burst_count = 1;
1244 output.type = 2;
1245 output.op = CF_OP_EXPORT;
1246 output.array_base = next_pos++;
1247 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1248 r600_bytecode_add_output(ctx.bc, &output);
1249 last_exp_pos = ctx.bc->cf_last;
1250 }
1251
1252 if (!last_exp_param) {
1253 memset(&output, 0, sizeof(output));
1254 output.gpr = 0;
1255 output.elem_size = 3;
1256 output.swizzle_x = 7;
1257 output.swizzle_y = 7;
1258 output.swizzle_z = 7;
1259 output.swizzle_w = 7;
1260 output.burst_count = 1;
1261 output.type = 2;
1262 output.op = CF_OP_EXPORT;
1263 output.array_base = next_param++;
1264 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1265 r600_bytecode_add_output(ctx.bc, &output);
1266 last_exp_param = ctx.bc->cf_last;
1267 }
1268
1269 last_exp_pos->op = CF_OP_EXPORT_DONE;
1270 last_exp_param->op = CF_OP_EXPORT_DONE;
1271
1272 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1273 cf_pop = ctx.bc->cf_last;
1274
1275 cf_jump->cf_addr = cf_pop->id + 2;
1276 cf_jump->pop_count = 1;
1277 cf_pop->cf_addr = cf_pop->id + 2;
1278 cf_pop->pop_count = 1;
1279
1280 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1281 ctx.bc->cf_last->end_of_program = 1;
1282
1283 gs->gs_copy_shader = cshader;
1284
1285 ctx.bc->nstack = 1;
1286 cshader->shader.ring_item_size = ocnt * 16;
1287
1288 return r600_bytecode_build(ctx.bc);
1289 }
1290
1291 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx)
1292 {
1293 struct r600_bytecode_output output;
1294 int i, k, ring_offset;
1295
1296 for (i = 0; i < ctx->shader->noutput; i++) {
1297 if (ctx->gs_for_vs) {
1298 /* for ES we need to lookup corresponding ring offset expected by GS
1299 * (map this output to GS input by name and sid) */
1300 /* FIXME precompute offsets */
1301 ring_offset = -1;
1302 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1303 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1304 struct r600_shader_io *out = &ctx->shader->output[i];
1305 if (in->name == out->name && in->sid == out->sid)
1306 ring_offset = in->ring_offset;
1307 }
1308
1309 if (ring_offset == -1)
1310 continue;
1311 } else
1312 ring_offset = i * 16;
1313
1314 /* next_ring_offset after parsing input decls contains total size of
1315 * single vertex data, gs_next_vertex - current vertex index */
1316 ring_offset += ctx->next_ring_offset * ctx->gs_next_vertex;
1317
1318 memset(&output, 0, sizeof(struct r600_bytecode_output));
1319 output.gpr = ctx->shader->output[i].gpr;
1320 output.elem_size = 3;
1321 output.comp_mask = 0xF;
1322 output.burst_count = 1;
1323 output.op = CF_OP_MEM_RING;
1324 output.array_base = ring_offset >> 2; /* in dwords */
1325 r600_bytecode_add_output(ctx->bc, &output);
1326 }
1327 ++ctx->gs_next_vertex;
1328 return 0;
1329 }
1330
1331 static int r600_shader_from_tgsi(struct r600_context *rctx,
1332 struct r600_pipe_shader *pipeshader,
1333 struct r600_shader_key key)
1334 {
1335 struct r600_screen *rscreen = rctx->screen;
1336 struct r600_shader *shader = &pipeshader->shader;
1337 struct tgsi_token *tokens = pipeshader->selector->tokens;
1338 struct pipe_stream_output_info so = pipeshader->selector->so;
1339 struct tgsi_full_immediate *immediate;
1340 struct tgsi_full_property *property;
1341 struct r600_shader_ctx ctx;
1342 struct r600_bytecode_output output[32];
1343 unsigned output_done, noutput;
1344 unsigned opcode;
1345 int i, j, k, r = 0;
1346 int next_pos_base = 60, next_param_base = 0;
1347 int max_color_exports = MAX2(key.nr_cbufs, 1);
1348 /* Declarations used by llvm code */
1349 bool use_llvm = false;
1350 bool indirect_gprs;
1351 bool ring_outputs = false;
1352
1353 #ifdef R600_USE_LLVM
1354 use_llvm = !(rscreen->b.debug_flags & DBG_NO_LLVM);
1355 #endif
1356 ctx.bc = &shader->bc;
1357 ctx.shader = shader;
1358 ctx.native_integers = true;
1359
1360 shader->vs_as_es = key.vs_as_es;
1361
1362 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
1363 rscreen->has_compressed_msaa_texturing);
1364 ctx.tokens = tokens;
1365 tgsi_scan_shader(tokens, &ctx.info);
1366 shader->indirect_files = ctx.info.indirect_files;
1367 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
1368 tgsi_parse_init(&ctx.parse, tokens);
1369 ctx.type = ctx.parse.FullHeader.Processor.Processor;
1370 shader->processor_type = ctx.type;
1371 ctx.bc->type = shader->processor_type;
1372
1373 ring_outputs = key.vs_as_es || (ctx.type == TGSI_PROCESSOR_GEOMETRY);
1374
1375 if (key.vs_as_es) {
1376 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
1377 } else {
1378 ctx.gs_for_vs = NULL;
1379 }
1380
1381 ctx.next_ring_offset = 0;
1382 ctx.gs_next_vertex = 0;
1383
1384 ctx.face_gpr = -1;
1385 ctx.fragcoord_input = -1;
1386 ctx.colors_used = 0;
1387 ctx.clip_vertex_write = 0;
1388
1389 shader->nr_ps_color_exports = 0;
1390 shader->nr_ps_max_color_exports = 0;
1391
1392 shader->two_side = key.color_two_side;
1393
1394 /* register allocations */
1395 /* Values [0,127] correspond to GPR[0..127].
1396 * Values [128,159] correspond to constant buffer bank 0
1397 * Values [160,191] correspond to constant buffer bank 1
1398 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1399 * Values [256,287] correspond to constant buffer bank 2 (EG)
1400 * Values [288,319] correspond to constant buffer bank 3 (EG)
1401 * Other special values are shown in the list below.
1402 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1403 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1404 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1405 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1406 * 248 SQ_ALU_SRC_0: special constant 0.0.
1407 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1408 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1409 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1410 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1411 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1412 * 254 SQ_ALU_SRC_PV: previous vector result.
1413 * 255 SQ_ALU_SRC_PS: previous scalar result.
1414 */
1415 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1416 ctx.file_offset[i] = 0;
1417 }
1418
1419 #ifdef R600_USE_LLVM
1420 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1421 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1422 "indirect adressing. Falling back to TGSI "
1423 "backend.\n");
1424 use_llvm = 0;
1425 }
1426 #endif
1427 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1428 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1429 if (!use_llvm) {
1430 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1431 }
1432 }
1433 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1434 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1435 }
1436 if (ctx.type == TGSI_PROCESSOR_GEOMETRY && ctx.bc->chip_class >= EVERGREEN) {
1437 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
1438 ctx.file_offset[TGSI_FILE_INPUT] = 2;
1439 }
1440 ctx.use_llvm = use_llvm;
1441
1442 if (use_llvm) {
1443 ctx.file_offset[TGSI_FILE_OUTPUT] =
1444 ctx.file_offset[TGSI_FILE_INPUT];
1445 } else {
1446 ctx.file_offset[TGSI_FILE_OUTPUT] =
1447 ctx.file_offset[TGSI_FILE_INPUT] +
1448 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1449 }
1450 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1451 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1452
1453 /* Outside the GPR range. This will be translated to one of the
1454 * kcache banks later. */
1455 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1456
1457 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1458 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1459 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1460 ctx.temp_reg = ctx.bc->ar_reg + 1;
1461
1462 if (indirect_gprs) {
1463 shader->max_arrays = 0;
1464 shader->num_arrays = 0;
1465
1466 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1467 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1468 ctx.file_offset[TGSI_FILE_OUTPUT] -
1469 ctx.file_offset[TGSI_FILE_INPUT],
1470 0x0F);
1471 }
1472 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1473 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1474 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1475 ctx.file_offset[TGSI_FILE_OUTPUT],
1476 0x0F);
1477 }
1478 }
1479
1480 ctx.nliterals = 0;
1481 ctx.literals = NULL;
1482 shader->fs_write_all = FALSE;
1483 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1484 tgsi_parse_token(&ctx.parse);
1485 switch (ctx.parse.FullToken.Token.Type) {
1486 case TGSI_TOKEN_TYPE_IMMEDIATE:
1487 immediate = &ctx.parse.FullToken.FullImmediate;
1488 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1489 if(ctx.literals == NULL) {
1490 r = -ENOMEM;
1491 goto out_err;
1492 }
1493 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1494 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1495 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1496 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1497 ctx.nliterals++;
1498 break;
1499 case TGSI_TOKEN_TYPE_DECLARATION:
1500 r = tgsi_declaration(&ctx);
1501 if (r)
1502 goto out_err;
1503 break;
1504 case TGSI_TOKEN_TYPE_INSTRUCTION:
1505 break;
1506 case TGSI_TOKEN_TYPE_PROPERTY:
1507 property = &ctx.parse.FullToken.FullProperty;
1508 switch (property->Property.PropertyName) {
1509 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1510 if (property->u[0].Data == 1)
1511 shader->fs_write_all = TRUE;
1512 break;
1513 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1514 /* we don't need this one */
1515 break;
1516 case TGSI_PROPERTY_GS_INPUT_PRIM:
1517 shader->gs_input_prim = property->u[0].Data;
1518 break;
1519 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1520 shader->gs_output_prim = property->u[0].Data;
1521 break;
1522 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1523 shader->gs_max_out_vertices = property->u[0].Data;
1524 break;
1525 }
1526 break;
1527 default:
1528 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1529 r = -EINVAL;
1530 goto out_err;
1531 }
1532 }
1533
1534 shader->ring_item_size = ctx.next_ring_offset;
1535
1536 /* Process two side if needed */
1537 if (shader->two_side && ctx.colors_used) {
1538 int i, count = ctx.shader->ninput;
1539 unsigned next_lds_loc = ctx.shader->nlds;
1540
1541 /* additional inputs will be allocated right after the existing inputs,
1542 * we won't need them after the color selection, so we don't need to
1543 * reserve these gprs for the rest of the shader code and to adjust
1544 * output offsets etc. */
1545 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1546 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1547
1548 if (ctx.face_gpr == -1) {
1549 i = ctx.shader->ninput++;
1550 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1551 ctx.shader->input[i].spi_sid = 0;
1552 ctx.shader->input[i].gpr = gpr++;
1553 ctx.face_gpr = ctx.shader->input[i].gpr;
1554 }
1555
1556 for (i = 0; i < count; i++) {
1557 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1558 int ni = ctx.shader->ninput++;
1559 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1560 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1561 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1562 ctx.shader->input[ni].gpr = gpr++;
1563 // TGSI to LLVM needs to know the lds position of inputs.
1564 // Non LLVM path computes it later (in process_twoside_color)
1565 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1566 ctx.shader->input[i].back_color_input = ni;
1567 if (ctx.bc->chip_class >= EVERGREEN) {
1568 if ((r = evergreen_interp_input(&ctx, ni)))
1569 return r;
1570 }
1571 }
1572 }
1573 }
1574
1575 /* LLVM backend setup */
1576 #ifdef R600_USE_LLVM
1577 if (use_llvm) {
1578 struct radeon_llvm_context radeon_llvm_ctx;
1579 LLVMModuleRef mod;
1580 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
1581 boolean use_kill = false;
1582
1583 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1584 radeon_llvm_ctx.type = ctx.type;
1585 radeon_llvm_ctx.two_side = shader->two_side;
1586 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1587 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
1588 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1589 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1590 radeon_llvm_ctx.color_buffer_count = max_color_exports;
1591 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1592 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
1593 radeon_llvm_ctx.stream_outputs = &so;
1594 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1595 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1596 radeon_llvm_ctx.has_compressed_msaa_texturing =
1597 ctx.bc->has_compressed_msaa_texturing;
1598 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1599 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
1600 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
1601
1602 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
1603 radeon_llvm_dispose(&radeon_llvm_ctx);
1604 use_llvm = 0;
1605 fprintf(stderr, "R600 LLVM backend failed to compile "
1606 "shader. Falling back to TGSI\n");
1607 } else {
1608 ctx.file_offset[TGSI_FILE_OUTPUT] =
1609 ctx.file_offset[TGSI_FILE_INPUT];
1610 }
1611 if (use_kill)
1612 ctx.shader->uses_kill = use_kill;
1613 radeon_llvm_dispose(&radeon_llvm_ctx);
1614 }
1615 #endif
1616 /* End of LLVM backend setup */
1617
1618 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
1619 shader->nr_ps_max_color_exports = 8;
1620
1621 if (!use_llvm) {
1622 if (ctx.fragcoord_input >= 0) {
1623 if (ctx.bc->chip_class == CAYMAN) {
1624 for (j = 0 ; j < 4; j++) {
1625 struct r600_bytecode_alu alu;
1626 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1627 alu.op = ALU_OP1_RECIP_IEEE;
1628 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1629 alu.src[0].chan = 3;
1630
1631 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1632 alu.dst.chan = j;
1633 alu.dst.write = (j == 3);
1634 alu.last = 1;
1635 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1636 return r;
1637 }
1638 } else {
1639 struct r600_bytecode_alu alu;
1640 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1641 alu.op = ALU_OP1_RECIP_IEEE;
1642 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1643 alu.src[0].chan = 3;
1644
1645 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1646 alu.dst.chan = 3;
1647 alu.dst.write = 1;
1648 alu.last = 1;
1649 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1650 return r;
1651 }
1652 }
1653
1654 if (shader->two_side && ctx.colors_used) {
1655 if ((r = process_twoside_color_inputs(&ctx)))
1656 return r;
1657 }
1658
1659 tgsi_parse_init(&ctx.parse, tokens);
1660 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1661 tgsi_parse_token(&ctx.parse);
1662 switch (ctx.parse.FullToken.Token.Type) {
1663 case TGSI_TOKEN_TYPE_INSTRUCTION:
1664 r = tgsi_is_supported(&ctx);
1665 if (r)
1666 goto out_err;
1667 ctx.max_driver_temp_used = 0;
1668 /* reserve first tmp for everyone */
1669 r600_get_temp(&ctx);
1670
1671 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1672 if ((r = tgsi_split_constant(&ctx)))
1673 goto out_err;
1674 if ((r = tgsi_split_literal_constant(&ctx)))
1675 goto out_err;
1676 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
1677 if ((r = tgsi_split_gs_inputs(&ctx)))
1678 goto out_err;
1679 if (ctx.bc->chip_class == CAYMAN)
1680 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1681 else if (ctx.bc->chip_class >= EVERGREEN)
1682 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1683 else
1684 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1685 r = ctx.inst_info->process(&ctx);
1686 if (r)
1687 goto out_err;
1688 break;
1689 default:
1690 break;
1691 }
1692 }
1693 }
1694
1695 /* Reset the temporary register counter. */
1696 ctx.max_driver_temp_used = 0;
1697
1698 noutput = shader->noutput;
1699
1700 if (!ring_outputs && ctx.clip_vertex_write) {
1701 unsigned clipdist_temp[2];
1702
1703 clipdist_temp[0] = r600_get_temp(&ctx);
1704 clipdist_temp[1] = r600_get_temp(&ctx);
1705
1706 /* need to convert a clipvertex write into clipdistance writes and not export
1707 the clip vertex anymore */
1708
1709 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1710 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1711 shader->output[noutput].gpr = clipdist_temp[0];
1712 noutput++;
1713 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1714 shader->output[noutput].gpr = clipdist_temp[1];
1715 noutput++;
1716
1717 /* reset spi_sid for clipvertex output to avoid confusing spi */
1718 shader->output[ctx.cv_output].spi_sid = 0;
1719
1720 shader->clip_dist_write = 0xFF;
1721
1722 for (i = 0; i < 8; i++) {
1723 int oreg = i >> 2;
1724 int ochan = i & 3;
1725
1726 for (j = 0; j < 4; j++) {
1727 struct r600_bytecode_alu alu;
1728 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1729 alu.op = ALU_OP2_DOT4;
1730 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1731 alu.src[0].chan = j;
1732
1733 alu.src[1].sel = 512 + i;
1734 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1735 alu.src[1].chan = j;
1736
1737 alu.dst.sel = clipdist_temp[oreg];
1738 alu.dst.chan = j;
1739 alu.dst.write = (j == ochan);
1740 if (j == 3)
1741 alu.last = 1;
1742 if (!use_llvm)
1743 r = r600_bytecode_add_alu(ctx.bc, &alu);
1744 if (r)
1745 return r;
1746 }
1747 }
1748 }
1749
1750 /* Add stream outputs. */
1751 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
1752 so.num_outputs && !use_llvm)
1753 emit_streamout(&ctx, &so);
1754
1755 if (ring_outputs) {
1756 if (key.vs_as_es)
1757 emit_gs_ring_writes(&ctx);
1758 } else {
1759 /* export output */
1760 for (i = 0, j = 0; i < noutput; i++, j++) {
1761 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1762 output[j].gpr = shader->output[i].gpr;
1763 output[j].elem_size = 3;
1764 output[j].swizzle_x = 0;
1765 output[j].swizzle_y = 1;
1766 output[j].swizzle_z = 2;
1767 output[j].swizzle_w = 3;
1768 output[j].burst_count = 1;
1769 output[j].type = -1;
1770 output[j].op = CF_OP_EXPORT;
1771 switch (ctx.type) {
1772 case TGSI_PROCESSOR_VERTEX:
1773 switch (shader->output[i].name) {
1774 case TGSI_SEMANTIC_POSITION:
1775 output[j].array_base = next_pos_base++;
1776 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1777 break;
1778
1779 case TGSI_SEMANTIC_PSIZE:
1780 output[j].array_base = next_pos_base++;
1781 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1782 break;
1783 case TGSI_SEMANTIC_CLIPVERTEX:
1784 j--;
1785 break;
1786 case TGSI_SEMANTIC_CLIPDIST:
1787 output[j].array_base = next_pos_base++;
1788 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1789 /* spi_sid is 0 for clipdistance outputs that were generated
1790 * for clipvertex - we don't need to pass them to PS */
1791 if (shader->output[i].spi_sid) {
1792 j++;
1793 /* duplicate it as PARAM to pass to the pixel shader */
1794 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1795 output[j].array_base = next_param_base++;
1796 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1797 }
1798 break;
1799 case TGSI_SEMANTIC_FOG:
1800 output[j].swizzle_y = 4; /* 0 */
1801 output[j].swizzle_z = 4; /* 0 */
1802 output[j].swizzle_w = 5; /* 1 */
1803 break;
1804 }
1805 break;
1806 case TGSI_PROCESSOR_FRAGMENT:
1807 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1808 /* never export more colors than the number of CBs */
1809 if (shader->output[i].sid >= max_color_exports) {
1810 /* skip export */
1811 j--;
1812 continue;
1813 }
1814 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1815 output[j].array_base = shader->output[i].sid;
1816 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1817 shader->nr_ps_color_exports++;
1818 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
1819 for (k = 1; k < max_color_exports; k++) {
1820 j++;
1821 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1822 output[j].gpr = shader->output[i].gpr;
1823 output[j].elem_size = 3;
1824 output[j].swizzle_x = 0;
1825 output[j].swizzle_y = 1;
1826 output[j].swizzle_z = 2;
1827 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1828 output[j].burst_count = 1;
1829 output[j].array_base = k;
1830 output[j].op = CF_OP_EXPORT;
1831 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1832 shader->nr_ps_color_exports++;
1833 }
1834 }
1835 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1836 output[j].array_base = 61;
1837 output[j].swizzle_x = 2;
1838 output[j].swizzle_y = 7;
1839 output[j].swizzle_z = output[j].swizzle_w = 7;
1840 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1841 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1842 output[j].array_base = 61;
1843 output[j].swizzle_x = 7;
1844 output[j].swizzle_y = 1;
1845 output[j].swizzle_z = output[j].swizzle_w = 7;
1846 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1847 } else {
1848 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1849 r = -EINVAL;
1850 goto out_err;
1851 }
1852 break;
1853 default:
1854 R600_ERR("unsupported processor type %d\n", ctx.type);
1855 r = -EINVAL;
1856 goto out_err;
1857 }
1858
1859 if (output[j].type==-1) {
1860 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1861 output[j].array_base = next_param_base++;
1862 }
1863 }
1864
1865 /* add fake position export */
1866 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1867 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1868 output[j].gpr = 0;
1869 output[j].elem_size = 3;
1870 output[j].swizzle_x = 7;
1871 output[j].swizzle_y = 7;
1872 output[j].swizzle_z = 7;
1873 output[j].swizzle_w = 7;
1874 output[j].burst_count = 1;
1875 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1876 output[j].array_base = next_pos_base;
1877 output[j].op = CF_OP_EXPORT;
1878 j++;
1879 }
1880
1881 /* add fake param output for vertex shader if no param is exported */
1882 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1883 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1884 output[j].gpr = 0;
1885 output[j].elem_size = 3;
1886 output[j].swizzle_x = 7;
1887 output[j].swizzle_y = 7;
1888 output[j].swizzle_z = 7;
1889 output[j].swizzle_w = 7;
1890 output[j].burst_count = 1;
1891 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1892 output[j].array_base = 0;
1893 output[j].op = CF_OP_EXPORT;
1894 j++;
1895 }
1896
1897 /* add fake pixel export */
1898 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
1899 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1900 output[j].gpr = 0;
1901 output[j].elem_size = 3;
1902 output[j].swizzle_x = 7;
1903 output[j].swizzle_y = 7;
1904 output[j].swizzle_z = 7;
1905 output[j].swizzle_w = 7;
1906 output[j].burst_count = 1;
1907 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1908 output[j].array_base = 0;
1909 output[j].op = CF_OP_EXPORT;
1910 j++;
1911 }
1912
1913 noutput = j;
1914
1915 /* set export done on last export of each type */
1916 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1917 if (!(output_done & (1 << output[i].type))) {
1918 output_done |= (1 << output[i].type);
1919 output[i].op = CF_OP_EXPORT_DONE;
1920 }
1921 }
1922 /* add output to bytecode */
1923 if (!use_llvm) {
1924 for (i = 0; i < noutput; i++) {
1925 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1926 if (r)
1927 goto out_err;
1928 }
1929 }
1930 }
1931
1932 /* add program end */
1933 if (!use_llvm) {
1934 if (ctx.bc->chip_class == CAYMAN)
1935 cm_bytecode_add_cf_end(ctx.bc);
1936 else {
1937 const struct cf_op_info *last = NULL;
1938
1939 if (ctx.bc->cf_last)
1940 last = r600_isa_cf(ctx.bc->cf_last->op);
1941
1942 /* alu clause instructions don't have EOP bit, so add NOP */
1943 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
1944 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1945
1946 ctx.bc->cf_last->end_of_program = 1;
1947 }
1948 }
1949
1950 /* check GPR limit - we have 124 = 128 - 4
1951 * (4 are reserved as alu clause temporary registers) */
1952 if (ctx.bc->ngpr > 124) {
1953 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1954 r = -ENOMEM;
1955 goto out_err;
1956 }
1957
1958 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1959 if ((r = generate_gs_copy_shader(rctx, pipeshader)))
1960 return r;
1961 }
1962
1963 free(ctx.literals);
1964 tgsi_parse_free(&ctx.parse);
1965 return 0;
1966 out_err:
1967 free(ctx.literals);
1968 tgsi_parse_free(&ctx.parse);
1969 return r;
1970 }
1971
1972 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1973 {
1974 R600_ERR("%s tgsi opcode unsupported\n",
1975 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1976 return -EINVAL;
1977 }
1978
1979 static int tgsi_end(struct r600_shader_ctx *ctx)
1980 {
1981 return 0;
1982 }
1983
1984 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1985 const struct r600_shader_src *shader_src,
1986 unsigned chan)
1987 {
1988 bc_src->sel = shader_src->sel;
1989 bc_src->chan = shader_src->swizzle[chan];
1990 bc_src->neg = shader_src->neg;
1991 bc_src->abs = shader_src->abs;
1992 bc_src->rel = shader_src->rel;
1993 bc_src->value = shader_src->value[bc_src->chan];
1994 bc_src->kc_bank = shader_src->kc_bank;
1995 }
1996
1997 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1998 {
1999 bc_src->abs = 1;
2000 bc_src->neg = 0;
2001 }
2002
2003 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2004 {
2005 bc_src->neg = !bc_src->neg;
2006 }
2007
2008 static void tgsi_dst(struct r600_shader_ctx *ctx,
2009 const struct tgsi_full_dst_register *tgsi_dst,
2010 unsigned swizzle,
2011 struct r600_bytecode_alu_dst *r600_dst)
2012 {
2013 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2014
2015 r600_dst->sel = tgsi_dst->Register.Index;
2016 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2017 r600_dst->chan = swizzle;
2018 r600_dst->write = 1;
2019 if (tgsi_dst->Register.Indirect)
2020 r600_dst->rel = V_SQ_REL_RELATIVE;
2021 if (inst->Instruction.Saturate) {
2022 r600_dst->clamp = 1;
2023 }
2024 }
2025
2026 static int tgsi_last_instruction(unsigned writemask)
2027 {
2028 int i, lasti = 0;
2029
2030 for (i = 0; i < 4; i++) {
2031 if (writemask & (1 << i)) {
2032 lasti = i;
2033 }
2034 }
2035 return lasti;
2036 }
2037
2038 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
2039 {
2040 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2041 struct r600_bytecode_alu alu;
2042 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2043 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2044 /* use temp register if trans_only and more than one dst component */
2045 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
2046
2047 for (i = 0; i <= lasti; i++) {
2048 if (!(write_mask & (1 << i)))
2049 continue;
2050
2051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2052 if (use_tmp) {
2053 alu.dst.sel = ctx->temp_reg;
2054 alu.dst.chan = i;
2055 alu.dst.write = 1;
2056 } else
2057 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2058
2059 alu.op = ctx->inst_info->op;
2060 if (!swap) {
2061 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2062 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2063 }
2064 } else {
2065 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2066 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2067 }
2068 /* handle some special cases */
2069 switch (ctx->inst_info->tgsi_opcode) {
2070 case TGSI_OPCODE_SUB:
2071 r600_bytecode_src_toggle_neg(&alu.src[1]);
2072 break;
2073 case TGSI_OPCODE_ABS:
2074 r600_bytecode_src_set_abs(&alu.src[0]);
2075 break;
2076 default:
2077 break;
2078 }
2079 if (i == lasti || trans_only) {
2080 alu.last = 1;
2081 }
2082 r = r600_bytecode_add_alu(ctx->bc, &alu);
2083 if (r)
2084 return r;
2085 }
2086
2087 if (use_tmp) {
2088 /* move result from temp to dst */
2089 for (i = 0; i <= lasti; i++) {
2090 if (!(write_mask & (1 << i)))
2091 continue;
2092
2093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2094 alu.op = ALU_OP1_MOV;
2095 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2096 alu.src[0].sel = ctx->temp_reg;
2097 alu.src[0].chan = i;
2098 alu.last = (i == lasti);
2099
2100 r = r600_bytecode_add_alu(ctx->bc, &alu);
2101 if (r)
2102 return r;
2103 }
2104 }
2105 return 0;
2106 }
2107
2108 static int tgsi_op2(struct r600_shader_ctx *ctx)
2109 {
2110 return tgsi_op2_s(ctx, 0, 0);
2111 }
2112
2113 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2114 {
2115 return tgsi_op2_s(ctx, 1, 0);
2116 }
2117
2118 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2119 {
2120 return tgsi_op2_s(ctx, 0, 1);
2121 }
2122
2123 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2124 {
2125 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2126 struct r600_bytecode_alu alu;
2127 int i, r;
2128 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2129
2130 for (i = 0; i < lasti + 1; i++) {
2131
2132 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2133 continue;
2134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2135 alu.op = ctx->inst_info->op;
2136
2137 alu.src[0].sel = V_SQ_ALU_SRC_0;
2138
2139 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2140
2141 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2142
2143 if (i == lasti) {
2144 alu.last = 1;
2145 }
2146 r = r600_bytecode_add_alu(ctx->bc, &alu);
2147 if (r)
2148 return r;
2149 }
2150 return 0;
2151
2152 }
2153
2154 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
2155 {
2156 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2157 int i, j, r;
2158 struct r600_bytecode_alu alu;
2159 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2160
2161 for (i = 0 ; i < last_slot; i++) {
2162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2163 alu.op = ctx->inst_info->op;
2164 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2165 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
2166
2167 /* RSQ should take the absolute value of src */
2168 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
2169 r600_bytecode_src_set_abs(&alu.src[j]);
2170 }
2171 }
2172 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2173 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2174
2175 if (i == last_slot - 1)
2176 alu.last = 1;
2177 r = r600_bytecode_add_alu(ctx->bc, &alu);
2178 if (r)
2179 return r;
2180 }
2181 return 0;
2182 }
2183
2184 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
2185 {
2186 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2187 int i, j, k, r;
2188 struct r600_bytecode_alu alu;
2189 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2190 for (k = 0; k < last_slot; k++) {
2191 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
2192 continue;
2193
2194 for (i = 0 ; i < 4; i++) {
2195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2196 alu.op = ctx->inst_info->op;
2197 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2198 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
2199 }
2200 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2201 alu.dst.write = (i == k);
2202 if (i == 3)
2203 alu.last = 1;
2204 r = r600_bytecode_add_alu(ctx->bc, &alu);
2205 if (r)
2206 return r;
2207 }
2208 }
2209 return 0;
2210 }
2211
2212 /*
2213 * r600 - trunc to -PI..PI range
2214 * r700 - normalize by dividing by 2PI
2215 * see fdo bug 27901
2216 */
2217 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
2218 {
2219 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
2220 static float double_pi = 3.1415926535 * 2;
2221 static float neg_pi = -3.1415926535;
2222
2223 int r;
2224 struct r600_bytecode_alu alu;
2225
2226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2227 alu.op = ALU_OP3_MULADD;
2228 alu.is_op3 = 1;
2229
2230 alu.dst.chan = 0;
2231 alu.dst.sel = ctx->temp_reg;
2232 alu.dst.write = 1;
2233
2234 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2235
2236 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2237 alu.src[1].chan = 0;
2238 alu.src[1].value = *(uint32_t *)&half_inv_pi;
2239 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2240 alu.src[2].chan = 0;
2241 alu.last = 1;
2242 r = r600_bytecode_add_alu(ctx->bc, &alu);
2243 if (r)
2244 return r;
2245
2246 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2247 alu.op = ALU_OP1_FRACT;
2248
2249 alu.dst.chan = 0;
2250 alu.dst.sel = ctx->temp_reg;
2251 alu.dst.write = 1;
2252
2253 alu.src[0].sel = ctx->temp_reg;
2254 alu.src[0].chan = 0;
2255 alu.last = 1;
2256 r = r600_bytecode_add_alu(ctx->bc, &alu);
2257 if (r)
2258 return r;
2259
2260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2261 alu.op = ALU_OP3_MULADD;
2262 alu.is_op3 = 1;
2263
2264 alu.dst.chan = 0;
2265 alu.dst.sel = ctx->temp_reg;
2266 alu.dst.write = 1;
2267
2268 alu.src[0].sel = ctx->temp_reg;
2269 alu.src[0].chan = 0;
2270
2271 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2272 alu.src[1].chan = 0;
2273 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2274 alu.src[2].chan = 0;
2275
2276 if (ctx->bc->chip_class == R600) {
2277 alu.src[1].value = *(uint32_t *)&double_pi;
2278 alu.src[2].value = *(uint32_t *)&neg_pi;
2279 } else {
2280 alu.src[1].sel = V_SQ_ALU_SRC_1;
2281 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2282 alu.src[2].neg = 1;
2283 }
2284
2285 alu.last = 1;
2286 r = r600_bytecode_add_alu(ctx->bc, &alu);
2287 if (r)
2288 return r;
2289 return 0;
2290 }
2291
2292 static int cayman_trig(struct r600_shader_ctx *ctx)
2293 {
2294 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2295 struct r600_bytecode_alu alu;
2296 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2297 int i, r;
2298
2299 r = tgsi_setup_trig(ctx);
2300 if (r)
2301 return r;
2302
2303
2304 for (i = 0; i < last_slot; i++) {
2305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2306 alu.op = ctx->inst_info->op;
2307 alu.dst.chan = i;
2308
2309 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2310 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2311
2312 alu.src[0].sel = ctx->temp_reg;
2313 alu.src[0].chan = 0;
2314 if (i == last_slot - 1)
2315 alu.last = 1;
2316 r = r600_bytecode_add_alu(ctx->bc, &alu);
2317 if (r)
2318 return r;
2319 }
2320 return 0;
2321 }
2322
2323 static int tgsi_trig(struct r600_shader_ctx *ctx)
2324 {
2325 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2326 struct r600_bytecode_alu alu;
2327 int i, r;
2328 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2329
2330 r = tgsi_setup_trig(ctx);
2331 if (r)
2332 return r;
2333
2334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2335 alu.op = ctx->inst_info->op;
2336 alu.dst.chan = 0;
2337 alu.dst.sel = ctx->temp_reg;
2338 alu.dst.write = 1;
2339
2340 alu.src[0].sel = ctx->temp_reg;
2341 alu.src[0].chan = 0;
2342 alu.last = 1;
2343 r = r600_bytecode_add_alu(ctx->bc, &alu);
2344 if (r)
2345 return r;
2346
2347 /* replicate result */
2348 for (i = 0; i < lasti + 1; i++) {
2349 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2350 continue;
2351
2352 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2353 alu.op = ALU_OP1_MOV;
2354
2355 alu.src[0].sel = ctx->temp_reg;
2356 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2357 if (i == lasti)
2358 alu.last = 1;
2359 r = r600_bytecode_add_alu(ctx->bc, &alu);
2360 if (r)
2361 return r;
2362 }
2363 return 0;
2364 }
2365
2366 static int tgsi_scs(struct r600_shader_ctx *ctx)
2367 {
2368 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2369 struct r600_bytecode_alu alu;
2370 int i, r;
2371
2372 /* We'll only need the trig stuff if we are going to write to the
2373 * X or Y components of the destination vector.
2374 */
2375 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2376 r = tgsi_setup_trig(ctx);
2377 if (r)
2378 return r;
2379 }
2380
2381 /* dst.x = COS */
2382 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2383 if (ctx->bc->chip_class == CAYMAN) {
2384 for (i = 0 ; i < 3; i++) {
2385 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2386 alu.op = ALU_OP1_COS;
2387 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2388
2389 if (i == 0)
2390 alu.dst.write = 1;
2391 else
2392 alu.dst.write = 0;
2393 alu.src[0].sel = ctx->temp_reg;
2394 alu.src[0].chan = 0;
2395 if (i == 2)
2396 alu.last = 1;
2397 r = r600_bytecode_add_alu(ctx->bc, &alu);
2398 if (r)
2399 return r;
2400 }
2401 } else {
2402 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2403 alu.op = ALU_OP1_COS;
2404 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2405
2406 alu.src[0].sel = ctx->temp_reg;
2407 alu.src[0].chan = 0;
2408 alu.last = 1;
2409 r = r600_bytecode_add_alu(ctx->bc, &alu);
2410 if (r)
2411 return r;
2412 }
2413 }
2414
2415 /* dst.y = SIN */
2416 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2417 if (ctx->bc->chip_class == CAYMAN) {
2418 for (i = 0 ; i < 3; i++) {
2419 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2420 alu.op = ALU_OP1_SIN;
2421 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2422 if (i == 1)
2423 alu.dst.write = 1;
2424 else
2425 alu.dst.write = 0;
2426 alu.src[0].sel = ctx->temp_reg;
2427 alu.src[0].chan = 0;
2428 if (i == 2)
2429 alu.last = 1;
2430 r = r600_bytecode_add_alu(ctx->bc, &alu);
2431 if (r)
2432 return r;
2433 }
2434 } else {
2435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2436 alu.op = ALU_OP1_SIN;
2437 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2438
2439 alu.src[0].sel = ctx->temp_reg;
2440 alu.src[0].chan = 0;
2441 alu.last = 1;
2442 r = r600_bytecode_add_alu(ctx->bc, &alu);
2443 if (r)
2444 return r;
2445 }
2446 }
2447
2448 /* dst.z = 0.0; */
2449 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2450 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2451
2452 alu.op = ALU_OP1_MOV;
2453
2454 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2455
2456 alu.src[0].sel = V_SQ_ALU_SRC_0;
2457 alu.src[0].chan = 0;
2458
2459 alu.last = 1;
2460
2461 r = r600_bytecode_add_alu(ctx->bc, &alu);
2462 if (r)
2463 return r;
2464 }
2465
2466 /* dst.w = 1.0; */
2467 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2469
2470 alu.op = ALU_OP1_MOV;
2471
2472 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2473
2474 alu.src[0].sel = V_SQ_ALU_SRC_1;
2475 alu.src[0].chan = 0;
2476
2477 alu.last = 1;
2478
2479 r = r600_bytecode_add_alu(ctx->bc, &alu);
2480 if (r)
2481 return r;
2482 }
2483
2484 return 0;
2485 }
2486
2487 static int tgsi_kill(struct r600_shader_ctx *ctx)
2488 {
2489 struct r600_bytecode_alu alu;
2490 int i, r;
2491
2492 for (i = 0; i < 4; i++) {
2493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2494 alu.op = ctx->inst_info->op;
2495
2496 alu.dst.chan = i;
2497
2498 alu.src[0].sel = V_SQ_ALU_SRC_0;
2499
2500 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILL) {
2501 alu.src[1].sel = V_SQ_ALU_SRC_1;
2502 alu.src[1].neg = 1;
2503 } else {
2504 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2505 }
2506 if (i == 3) {
2507 alu.last = 1;
2508 }
2509 r = r600_bytecode_add_alu(ctx->bc, &alu);
2510 if (r)
2511 return r;
2512 }
2513
2514 /* kill must be last in ALU */
2515 ctx->bc->force_add_cf = 1;
2516 ctx->shader->uses_kill = TRUE;
2517 return 0;
2518 }
2519
2520 static int tgsi_lit(struct r600_shader_ctx *ctx)
2521 {
2522 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2523 struct r600_bytecode_alu alu;
2524 int r;
2525
2526 /* tmp.x = max(src.y, 0.0) */
2527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2528 alu.op = ALU_OP2_MAX;
2529 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2530 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2531 alu.src[1].chan = 1;
2532
2533 alu.dst.sel = ctx->temp_reg;
2534 alu.dst.chan = 0;
2535 alu.dst.write = 1;
2536
2537 alu.last = 1;
2538 r = r600_bytecode_add_alu(ctx->bc, &alu);
2539 if (r)
2540 return r;
2541
2542 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2543 {
2544 int chan;
2545 int sel;
2546 int i;
2547
2548 if (ctx->bc->chip_class == CAYMAN) {
2549 for (i = 0; i < 3; i++) {
2550 /* tmp.z = log(tmp.x) */
2551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2552 alu.op = ALU_OP1_LOG_CLAMPED;
2553 alu.src[0].sel = ctx->temp_reg;
2554 alu.src[0].chan = 0;
2555 alu.dst.sel = ctx->temp_reg;
2556 alu.dst.chan = i;
2557 if (i == 2) {
2558 alu.dst.write = 1;
2559 alu.last = 1;
2560 } else
2561 alu.dst.write = 0;
2562
2563 r = r600_bytecode_add_alu(ctx->bc, &alu);
2564 if (r)
2565 return r;
2566 }
2567 } else {
2568 /* tmp.z = log(tmp.x) */
2569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2570 alu.op = ALU_OP1_LOG_CLAMPED;
2571 alu.src[0].sel = ctx->temp_reg;
2572 alu.src[0].chan = 0;
2573 alu.dst.sel = ctx->temp_reg;
2574 alu.dst.chan = 2;
2575 alu.dst.write = 1;
2576 alu.last = 1;
2577 r = r600_bytecode_add_alu(ctx->bc, &alu);
2578 if (r)
2579 return r;
2580 }
2581
2582 chan = alu.dst.chan;
2583 sel = alu.dst.sel;
2584
2585 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2586 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2587 alu.op = ALU_OP3_MUL_LIT;
2588 alu.src[0].sel = sel;
2589 alu.src[0].chan = chan;
2590 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2591 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2592 alu.dst.sel = ctx->temp_reg;
2593 alu.dst.chan = 0;
2594 alu.dst.write = 1;
2595 alu.is_op3 = 1;
2596 alu.last = 1;
2597 r = r600_bytecode_add_alu(ctx->bc, &alu);
2598 if (r)
2599 return r;
2600
2601 if (ctx->bc->chip_class == CAYMAN) {
2602 for (i = 0; i < 3; i++) {
2603 /* dst.z = exp(tmp.x) */
2604 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2605 alu.op = ALU_OP1_EXP_IEEE;
2606 alu.src[0].sel = ctx->temp_reg;
2607 alu.src[0].chan = 0;
2608 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2609 if (i == 2) {
2610 alu.dst.write = 1;
2611 alu.last = 1;
2612 } else
2613 alu.dst.write = 0;
2614 r = r600_bytecode_add_alu(ctx->bc, &alu);
2615 if (r)
2616 return r;
2617 }
2618 } else {
2619 /* dst.z = exp(tmp.x) */
2620 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2621 alu.op = ALU_OP1_EXP_IEEE;
2622 alu.src[0].sel = ctx->temp_reg;
2623 alu.src[0].chan = 0;
2624 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2625 alu.last = 1;
2626 r = r600_bytecode_add_alu(ctx->bc, &alu);
2627 if (r)
2628 return r;
2629 }
2630 }
2631
2632 /* dst.x, <- 1.0 */
2633 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2634 alu.op = ALU_OP1_MOV;
2635 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2636 alu.src[0].chan = 0;
2637 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2638 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2639 r = r600_bytecode_add_alu(ctx->bc, &alu);
2640 if (r)
2641 return r;
2642
2643 /* dst.y = max(src.x, 0.0) */
2644 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2645 alu.op = ALU_OP2_MAX;
2646 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2647 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2648 alu.src[1].chan = 0;
2649 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2650 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2651 r = r600_bytecode_add_alu(ctx->bc, &alu);
2652 if (r)
2653 return r;
2654
2655 /* dst.w, <- 1.0 */
2656 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2657 alu.op = ALU_OP1_MOV;
2658 alu.src[0].sel = V_SQ_ALU_SRC_1;
2659 alu.src[0].chan = 0;
2660 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2661 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2662 alu.last = 1;
2663 r = r600_bytecode_add_alu(ctx->bc, &alu);
2664 if (r)
2665 return r;
2666
2667 return 0;
2668 }
2669
2670 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2671 {
2672 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2673 struct r600_bytecode_alu alu;
2674 int i, r;
2675
2676 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2677
2678 /* XXX:
2679 * For state trackers other than OpenGL, we'll want to use
2680 * _RECIPSQRT_IEEE instead.
2681 */
2682 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2683
2684 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2685 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2686 r600_bytecode_src_set_abs(&alu.src[i]);
2687 }
2688 alu.dst.sel = ctx->temp_reg;
2689 alu.dst.write = 1;
2690 alu.last = 1;
2691 r = r600_bytecode_add_alu(ctx->bc, &alu);
2692 if (r)
2693 return r;
2694 /* replicate result */
2695 return tgsi_helper_tempx_replicate(ctx);
2696 }
2697
2698 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2699 {
2700 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2701 struct r600_bytecode_alu alu;
2702 int i, r;
2703
2704 for (i = 0; i < 4; i++) {
2705 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2706 alu.src[0].sel = ctx->temp_reg;
2707 alu.op = ALU_OP1_MOV;
2708 alu.dst.chan = i;
2709 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2710 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2711 if (i == 3)
2712 alu.last = 1;
2713 r = r600_bytecode_add_alu(ctx->bc, &alu);
2714 if (r)
2715 return r;
2716 }
2717 return 0;
2718 }
2719
2720 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2721 {
2722 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2723 struct r600_bytecode_alu alu;
2724 int i, r;
2725
2726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2727 alu.op = ctx->inst_info->op;
2728 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2729 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2730 }
2731 alu.dst.sel = ctx->temp_reg;
2732 alu.dst.write = 1;
2733 alu.last = 1;
2734 r = r600_bytecode_add_alu(ctx->bc, &alu);
2735 if (r)
2736 return r;
2737 /* replicate result */
2738 return tgsi_helper_tempx_replicate(ctx);
2739 }
2740
2741 static int cayman_pow(struct r600_shader_ctx *ctx)
2742 {
2743 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2744 int i, r;
2745 struct r600_bytecode_alu alu;
2746 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2747
2748 for (i = 0; i < 3; i++) {
2749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2750 alu.op = ALU_OP1_LOG_IEEE;
2751 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2752 alu.dst.sel = ctx->temp_reg;
2753 alu.dst.chan = i;
2754 alu.dst.write = 1;
2755 if (i == 2)
2756 alu.last = 1;
2757 r = r600_bytecode_add_alu(ctx->bc, &alu);
2758 if (r)
2759 return r;
2760 }
2761
2762 /* b * LOG2(a) */
2763 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2764 alu.op = ALU_OP2_MUL;
2765 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2766 alu.src[1].sel = ctx->temp_reg;
2767 alu.dst.sel = ctx->temp_reg;
2768 alu.dst.write = 1;
2769 alu.last = 1;
2770 r = r600_bytecode_add_alu(ctx->bc, &alu);
2771 if (r)
2772 return r;
2773
2774 for (i = 0; i < last_slot; i++) {
2775 /* POW(a,b) = EXP2(b * LOG2(a))*/
2776 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2777 alu.op = ALU_OP1_EXP_IEEE;
2778 alu.src[0].sel = ctx->temp_reg;
2779
2780 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2781 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2782 if (i == last_slot - 1)
2783 alu.last = 1;
2784 r = r600_bytecode_add_alu(ctx->bc, &alu);
2785 if (r)
2786 return r;
2787 }
2788 return 0;
2789 }
2790
2791 static int tgsi_pow(struct r600_shader_ctx *ctx)
2792 {
2793 struct r600_bytecode_alu alu;
2794 int r;
2795
2796 /* LOG2(a) */
2797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2798 alu.op = ALU_OP1_LOG_IEEE;
2799 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2800 alu.dst.sel = ctx->temp_reg;
2801 alu.dst.write = 1;
2802 alu.last = 1;
2803 r = r600_bytecode_add_alu(ctx->bc, &alu);
2804 if (r)
2805 return r;
2806 /* b * LOG2(a) */
2807 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2808 alu.op = ALU_OP2_MUL;
2809 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2810 alu.src[1].sel = ctx->temp_reg;
2811 alu.dst.sel = ctx->temp_reg;
2812 alu.dst.write = 1;
2813 alu.last = 1;
2814 r = r600_bytecode_add_alu(ctx->bc, &alu);
2815 if (r)
2816 return r;
2817 /* POW(a,b) = EXP2(b * LOG2(a))*/
2818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2819 alu.op = ALU_OP1_EXP_IEEE;
2820 alu.src[0].sel = ctx->temp_reg;
2821 alu.dst.sel = ctx->temp_reg;
2822 alu.dst.write = 1;
2823 alu.last = 1;
2824 r = r600_bytecode_add_alu(ctx->bc, &alu);
2825 if (r)
2826 return r;
2827 return tgsi_helper_tempx_replicate(ctx);
2828 }
2829
2830 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2831 {
2832 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2833 struct r600_bytecode_alu alu;
2834 int i, r, j;
2835 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2836 int tmp0 = ctx->temp_reg;
2837 int tmp1 = r600_get_temp(ctx);
2838 int tmp2 = r600_get_temp(ctx);
2839 int tmp3 = r600_get_temp(ctx);
2840 /* Unsigned path:
2841 *
2842 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2843 *
2844 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2845 * 2. tmp0.z = lo (tmp0.x * src2)
2846 * 3. tmp0.w = -tmp0.z
2847 * 4. tmp0.y = hi (tmp0.x * src2)
2848 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2849 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2850 * 7. tmp1.x = tmp0.x - tmp0.w
2851 * 8. tmp1.y = tmp0.x + tmp0.w
2852 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2853 * 10. tmp0.z = hi(tmp0.x * src1) = q
2854 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2855 *
2856 * 12. tmp0.w = src1 - tmp0.y = r
2857 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2858 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2859 *
2860 * if DIV
2861 *
2862 * 15. tmp1.z = tmp0.z + 1 = q + 1
2863 * 16. tmp1.w = tmp0.z - 1 = q - 1
2864 *
2865 * else MOD
2866 *
2867 * 15. tmp1.z = tmp0.w - src2 = r - src2
2868 * 16. tmp1.w = tmp0.w + src2 = r + src2
2869 *
2870 * endif
2871 *
2872 * 17. tmp1.x = tmp1.x & tmp1.y
2873 *
2874 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2875 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2876 *
2877 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2878 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2879 *
2880 * Signed path:
2881 *
2882 * Same as unsigned, using abs values of the operands,
2883 * and fixing the sign of the result in the end.
2884 */
2885
2886 for (i = 0; i < 4; i++) {
2887 if (!(write_mask & (1<<i)))
2888 continue;
2889
2890 if (signed_op) {
2891
2892 /* tmp2.x = -src0 */
2893 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2894 alu.op = ALU_OP2_SUB_INT;
2895
2896 alu.dst.sel = tmp2;
2897 alu.dst.chan = 0;
2898 alu.dst.write = 1;
2899
2900 alu.src[0].sel = V_SQ_ALU_SRC_0;
2901
2902 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2903
2904 alu.last = 1;
2905 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2906 return r;
2907
2908 /* tmp2.y = -src1 */
2909 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2910 alu.op = ALU_OP2_SUB_INT;
2911
2912 alu.dst.sel = tmp2;
2913 alu.dst.chan = 1;
2914 alu.dst.write = 1;
2915
2916 alu.src[0].sel = V_SQ_ALU_SRC_0;
2917
2918 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2919
2920 alu.last = 1;
2921 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2922 return r;
2923
2924 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2925 /* it will be a sign of the quotient */
2926 if (!mod) {
2927
2928 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2929 alu.op = ALU_OP2_XOR_INT;
2930
2931 alu.dst.sel = tmp2;
2932 alu.dst.chan = 2;
2933 alu.dst.write = 1;
2934
2935 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2936 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2937
2938 alu.last = 1;
2939 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2940 return r;
2941 }
2942
2943 /* tmp2.x = |src0| */
2944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2945 alu.op = ALU_OP3_CNDGE_INT;
2946 alu.is_op3 = 1;
2947
2948 alu.dst.sel = tmp2;
2949 alu.dst.chan = 0;
2950 alu.dst.write = 1;
2951
2952 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2953 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2954 alu.src[2].sel = tmp2;
2955 alu.src[2].chan = 0;
2956
2957 alu.last = 1;
2958 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2959 return r;
2960
2961 /* tmp2.y = |src1| */
2962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2963 alu.op = ALU_OP3_CNDGE_INT;
2964 alu.is_op3 = 1;
2965
2966 alu.dst.sel = tmp2;
2967 alu.dst.chan = 1;
2968 alu.dst.write = 1;
2969
2970 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2971 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2972 alu.src[2].sel = tmp2;
2973 alu.src[2].chan = 1;
2974
2975 alu.last = 1;
2976 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2977 return r;
2978
2979 }
2980
2981 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2982 if (ctx->bc->chip_class == CAYMAN) {
2983 /* tmp3.x = u2f(src2) */
2984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2985 alu.op = ALU_OP1_UINT_TO_FLT;
2986
2987 alu.dst.sel = tmp3;
2988 alu.dst.chan = 0;
2989 alu.dst.write = 1;
2990
2991 if (signed_op) {
2992 alu.src[0].sel = tmp2;
2993 alu.src[0].chan = 1;
2994 } else {
2995 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2996 }
2997
2998 alu.last = 1;
2999 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3000 return r;
3001
3002 /* tmp0.x = recip(tmp3.x) */
3003 for (j = 0 ; j < 3; j++) {
3004 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3005 alu.op = ALU_OP1_RECIP_IEEE;
3006
3007 alu.dst.sel = tmp0;
3008 alu.dst.chan = j;
3009 alu.dst.write = (j == 0);
3010
3011 alu.src[0].sel = tmp3;
3012 alu.src[0].chan = 0;
3013
3014 if (j == 2)
3015 alu.last = 1;
3016 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3017 return r;
3018 }
3019
3020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3021 alu.op = ALU_OP2_MUL;
3022
3023 alu.src[0].sel = tmp0;
3024 alu.src[0].chan = 0;
3025
3026 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3027 alu.src[1].value = 0x4f800000;
3028
3029 alu.dst.sel = tmp3;
3030 alu.dst.write = 1;
3031 alu.last = 1;
3032 r = r600_bytecode_add_alu(ctx->bc, &alu);
3033 if (r)
3034 return r;
3035
3036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3037 alu.op = ALU_OP1_FLT_TO_UINT;
3038
3039 alu.dst.sel = tmp0;
3040 alu.dst.chan = 0;
3041 alu.dst.write = 1;
3042
3043 alu.src[0].sel = tmp3;
3044 alu.src[0].chan = 0;
3045
3046 alu.last = 1;
3047 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3048 return r;
3049
3050 } else {
3051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3052 alu.op = ALU_OP1_RECIP_UINT;
3053
3054 alu.dst.sel = tmp0;
3055 alu.dst.chan = 0;
3056 alu.dst.write = 1;
3057
3058 if (signed_op) {
3059 alu.src[0].sel = tmp2;
3060 alu.src[0].chan = 1;
3061 } else {
3062 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3063 }
3064
3065 alu.last = 1;
3066 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3067 return r;
3068 }
3069
3070 /* 2. tmp0.z = lo (tmp0.x * src2) */
3071 if (ctx->bc->chip_class == CAYMAN) {
3072 for (j = 0 ; j < 4; j++) {
3073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3074 alu.op = ALU_OP2_MULLO_UINT;
3075
3076 alu.dst.sel = tmp0;
3077 alu.dst.chan = j;
3078 alu.dst.write = (j == 2);
3079
3080 alu.src[0].sel = tmp0;
3081 alu.src[0].chan = 0;
3082 if (signed_op) {
3083 alu.src[1].sel = tmp2;
3084 alu.src[1].chan = 1;
3085 } else {
3086 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3087 }
3088
3089 alu.last = (j == 3);
3090 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3091 return r;
3092 }
3093 } else {
3094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3095 alu.op = ALU_OP2_MULLO_UINT;
3096
3097 alu.dst.sel = tmp0;
3098 alu.dst.chan = 2;
3099 alu.dst.write = 1;
3100
3101 alu.src[0].sel = tmp0;
3102 alu.src[0].chan = 0;
3103 if (signed_op) {
3104 alu.src[1].sel = tmp2;
3105 alu.src[1].chan = 1;
3106 } else {
3107 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3108 }
3109
3110 alu.last = 1;
3111 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3112 return r;
3113 }
3114
3115 /* 3. tmp0.w = -tmp0.z */
3116 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3117 alu.op = ALU_OP2_SUB_INT;
3118
3119 alu.dst.sel = tmp0;
3120 alu.dst.chan = 3;
3121 alu.dst.write = 1;
3122
3123 alu.src[0].sel = V_SQ_ALU_SRC_0;
3124 alu.src[1].sel = tmp0;
3125 alu.src[1].chan = 2;
3126
3127 alu.last = 1;
3128 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3129 return r;
3130
3131 /* 4. tmp0.y = hi (tmp0.x * src2) */
3132 if (ctx->bc->chip_class == CAYMAN) {
3133 for (j = 0 ; j < 4; j++) {
3134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3135 alu.op = ALU_OP2_MULHI_UINT;
3136
3137 alu.dst.sel = tmp0;
3138 alu.dst.chan = j;
3139 alu.dst.write = (j == 1);
3140
3141 alu.src[0].sel = tmp0;
3142 alu.src[0].chan = 0;
3143
3144 if (signed_op) {
3145 alu.src[1].sel = tmp2;
3146 alu.src[1].chan = 1;
3147 } else {
3148 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3149 }
3150 alu.last = (j == 3);
3151 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3152 return r;
3153 }
3154 } else {
3155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3156 alu.op = ALU_OP2_MULHI_UINT;
3157
3158 alu.dst.sel = tmp0;
3159 alu.dst.chan = 1;
3160 alu.dst.write = 1;
3161
3162 alu.src[0].sel = tmp0;
3163 alu.src[0].chan = 0;
3164
3165 if (signed_op) {
3166 alu.src[1].sel = tmp2;
3167 alu.src[1].chan = 1;
3168 } else {
3169 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3170 }
3171
3172 alu.last = 1;
3173 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3174 return r;
3175 }
3176
3177 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
3178 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3179 alu.op = ALU_OP3_CNDE_INT;
3180 alu.is_op3 = 1;
3181
3182 alu.dst.sel = tmp0;
3183 alu.dst.chan = 2;
3184 alu.dst.write = 1;
3185
3186 alu.src[0].sel = tmp0;
3187 alu.src[0].chan = 1;
3188 alu.src[1].sel = tmp0;
3189 alu.src[1].chan = 3;
3190 alu.src[2].sel = tmp0;
3191 alu.src[2].chan = 2;
3192
3193 alu.last = 1;
3194 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3195 return r;
3196
3197 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
3198 if (ctx->bc->chip_class == CAYMAN) {
3199 for (j = 0 ; j < 4; j++) {
3200 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3201 alu.op = ALU_OP2_MULHI_UINT;
3202
3203 alu.dst.sel = tmp0;
3204 alu.dst.chan = j;
3205 alu.dst.write = (j == 3);
3206
3207 alu.src[0].sel = tmp0;
3208 alu.src[0].chan = 2;
3209
3210 alu.src[1].sel = tmp0;
3211 alu.src[1].chan = 0;
3212
3213 alu.last = (j == 3);
3214 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3215 return r;
3216 }
3217 } else {
3218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3219 alu.op = ALU_OP2_MULHI_UINT;
3220
3221 alu.dst.sel = tmp0;
3222 alu.dst.chan = 3;
3223 alu.dst.write = 1;
3224
3225 alu.src[0].sel = tmp0;
3226 alu.src[0].chan = 2;
3227
3228 alu.src[1].sel = tmp0;
3229 alu.src[1].chan = 0;
3230
3231 alu.last = 1;
3232 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3233 return r;
3234 }
3235
3236 /* 7. tmp1.x = tmp0.x - tmp0.w */
3237 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3238 alu.op = ALU_OP2_SUB_INT;
3239
3240 alu.dst.sel = tmp1;
3241 alu.dst.chan = 0;
3242 alu.dst.write = 1;
3243
3244 alu.src[0].sel = tmp0;
3245 alu.src[0].chan = 0;
3246 alu.src[1].sel = tmp0;
3247 alu.src[1].chan = 3;
3248
3249 alu.last = 1;
3250 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3251 return r;
3252
3253 /* 8. tmp1.y = tmp0.x + tmp0.w */
3254 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3255 alu.op = ALU_OP2_ADD_INT;
3256
3257 alu.dst.sel = tmp1;
3258 alu.dst.chan = 1;
3259 alu.dst.write = 1;
3260
3261 alu.src[0].sel = tmp0;
3262 alu.src[0].chan = 0;
3263 alu.src[1].sel = tmp0;
3264 alu.src[1].chan = 3;
3265
3266 alu.last = 1;
3267 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3268 return r;
3269
3270 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3272 alu.op = ALU_OP3_CNDE_INT;
3273 alu.is_op3 = 1;
3274
3275 alu.dst.sel = tmp0;
3276 alu.dst.chan = 0;
3277 alu.dst.write = 1;
3278
3279 alu.src[0].sel = tmp0;
3280 alu.src[0].chan = 1;
3281 alu.src[1].sel = tmp1;
3282 alu.src[1].chan = 1;
3283 alu.src[2].sel = tmp1;
3284 alu.src[2].chan = 0;
3285
3286 alu.last = 1;
3287 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3288 return r;
3289
3290 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3291 if (ctx->bc->chip_class == CAYMAN) {
3292 for (j = 0 ; j < 4; j++) {
3293 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3294 alu.op = ALU_OP2_MULHI_UINT;
3295
3296 alu.dst.sel = tmp0;
3297 alu.dst.chan = j;
3298 alu.dst.write = (j == 2);
3299
3300 alu.src[0].sel = tmp0;
3301 alu.src[0].chan = 0;
3302
3303 if (signed_op) {
3304 alu.src[1].sel = tmp2;
3305 alu.src[1].chan = 0;
3306 } else {
3307 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3308 }
3309
3310 alu.last = (j == 3);
3311 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3312 return r;
3313 }
3314 } else {
3315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3316 alu.op = ALU_OP2_MULHI_UINT;
3317
3318 alu.dst.sel = tmp0;
3319 alu.dst.chan = 2;
3320 alu.dst.write = 1;
3321
3322 alu.src[0].sel = tmp0;
3323 alu.src[0].chan = 0;
3324
3325 if (signed_op) {
3326 alu.src[1].sel = tmp2;
3327 alu.src[1].chan = 0;
3328 } else {
3329 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3330 }
3331
3332 alu.last = 1;
3333 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3334 return r;
3335 }
3336
3337 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3338 if (ctx->bc->chip_class == CAYMAN) {
3339 for (j = 0 ; j < 4; j++) {
3340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3341 alu.op = ALU_OP2_MULLO_UINT;
3342
3343 alu.dst.sel = tmp0;
3344 alu.dst.chan = j;
3345 alu.dst.write = (j == 1);
3346
3347 if (signed_op) {
3348 alu.src[0].sel = tmp2;
3349 alu.src[0].chan = 1;
3350 } else {
3351 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3352 }
3353
3354 alu.src[1].sel = tmp0;
3355 alu.src[1].chan = 2;
3356
3357 alu.last = (j == 3);
3358 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3359 return r;
3360 }
3361 } else {
3362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3363 alu.op = ALU_OP2_MULLO_UINT;
3364
3365 alu.dst.sel = tmp0;
3366 alu.dst.chan = 1;
3367 alu.dst.write = 1;
3368
3369 if (signed_op) {
3370 alu.src[0].sel = tmp2;
3371 alu.src[0].chan = 1;
3372 } else {
3373 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3374 }
3375
3376 alu.src[1].sel = tmp0;
3377 alu.src[1].chan = 2;
3378
3379 alu.last = 1;
3380 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3381 return r;
3382 }
3383
3384 /* 12. tmp0.w = src1 - tmp0.y = r */
3385 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3386 alu.op = ALU_OP2_SUB_INT;
3387
3388 alu.dst.sel = tmp0;
3389 alu.dst.chan = 3;
3390 alu.dst.write = 1;
3391
3392 if (signed_op) {
3393 alu.src[0].sel = tmp2;
3394 alu.src[0].chan = 0;
3395 } else {
3396 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3397 }
3398
3399 alu.src[1].sel = tmp0;
3400 alu.src[1].chan = 1;
3401
3402 alu.last = 1;
3403 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3404 return r;
3405
3406 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3407 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3408 alu.op = ALU_OP2_SETGE_UINT;
3409
3410 alu.dst.sel = tmp1;
3411 alu.dst.chan = 0;
3412 alu.dst.write = 1;
3413
3414 alu.src[0].sel = tmp0;
3415 alu.src[0].chan = 3;
3416 if (signed_op) {
3417 alu.src[1].sel = tmp2;
3418 alu.src[1].chan = 1;
3419 } else {
3420 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3421 }
3422
3423 alu.last = 1;
3424 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3425 return r;
3426
3427 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3428 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3429 alu.op = ALU_OP2_SETGE_UINT;
3430
3431 alu.dst.sel = tmp1;
3432 alu.dst.chan = 1;
3433 alu.dst.write = 1;
3434
3435 if (signed_op) {
3436 alu.src[0].sel = tmp2;
3437 alu.src[0].chan = 0;
3438 } else {
3439 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3440 }
3441
3442 alu.src[1].sel = tmp0;
3443 alu.src[1].chan = 1;
3444
3445 alu.last = 1;
3446 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3447 return r;
3448
3449 if (mod) { /* UMOD */
3450
3451 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3453 alu.op = ALU_OP2_SUB_INT;
3454
3455 alu.dst.sel = tmp1;
3456 alu.dst.chan = 2;
3457 alu.dst.write = 1;
3458
3459 alu.src[0].sel = tmp0;
3460 alu.src[0].chan = 3;
3461
3462 if (signed_op) {
3463 alu.src[1].sel = tmp2;
3464 alu.src[1].chan = 1;
3465 } else {
3466 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3467 }
3468
3469 alu.last = 1;
3470 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3471 return r;
3472
3473 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3475 alu.op = ALU_OP2_ADD_INT;
3476
3477 alu.dst.sel = tmp1;
3478 alu.dst.chan = 3;
3479 alu.dst.write = 1;
3480
3481 alu.src[0].sel = tmp0;
3482 alu.src[0].chan = 3;
3483 if (signed_op) {
3484 alu.src[1].sel = tmp2;
3485 alu.src[1].chan = 1;
3486 } else {
3487 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3488 }
3489
3490 alu.last = 1;
3491 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3492 return r;
3493
3494 } else { /* UDIV */
3495
3496 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3498 alu.op = ALU_OP2_ADD_INT;
3499
3500 alu.dst.sel = tmp1;
3501 alu.dst.chan = 2;
3502 alu.dst.write = 1;
3503
3504 alu.src[0].sel = tmp0;
3505 alu.src[0].chan = 2;
3506 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3507
3508 alu.last = 1;
3509 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3510 return r;
3511
3512 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3513 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3514 alu.op = ALU_OP2_ADD_INT;
3515
3516 alu.dst.sel = tmp1;
3517 alu.dst.chan = 3;
3518 alu.dst.write = 1;
3519
3520 alu.src[0].sel = tmp0;
3521 alu.src[0].chan = 2;
3522 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3523
3524 alu.last = 1;
3525 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3526 return r;
3527
3528 }
3529
3530 /* 17. tmp1.x = tmp1.x & tmp1.y */
3531 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3532 alu.op = ALU_OP2_AND_INT;
3533
3534 alu.dst.sel = tmp1;
3535 alu.dst.chan = 0;
3536 alu.dst.write = 1;
3537
3538 alu.src[0].sel = tmp1;
3539 alu.src[0].chan = 0;
3540 alu.src[1].sel = tmp1;
3541 alu.src[1].chan = 1;
3542
3543 alu.last = 1;
3544 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3545 return r;
3546
3547 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3548 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3550 alu.op = ALU_OP3_CNDE_INT;
3551 alu.is_op3 = 1;
3552
3553 alu.dst.sel = tmp0;
3554 alu.dst.chan = 2;
3555 alu.dst.write = 1;
3556
3557 alu.src[0].sel = tmp1;
3558 alu.src[0].chan = 0;
3559 alu.src[1].sel = tmp0;
3560 alu.src[1].chan = mod ? 3 : 2;
3561 alu.src[2].sel = tmp1;
3562 alu.src[2].chan = 2;
3563
3564 alu.last = 1;
3565 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3566 return r;
3567
3568 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3570 alu.op = ALU_OP3_CNDE_INT;
3571 alu.is_op3 = 1;
3572
3573 if (signed_op) {
3574 alu.dst.sel = tmp0;
3575 alu.dst.chan = 2;
3576 alu.dst.write = 1;
3577 } else {
3578 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3579 }
3580
3581 alu.src[0].sel = tmp1;
3582 alu.src[0].chan = 1;
3583 alu.src[1].sel = tmp1;
3584 alu.src[1].chan = 3;
3585 alu.src[2].sel = tmp0;
3586 alu.src[2].chan = 2;
3587
3588 alu.last = 1;
3589 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3590 return r;
3591
3592 if (signed_op) {
3593
3594 /* fix the sign of the result */
3595
3596 if (mod) {
3597
3598 /* tmp0.x = -tmp0.z */
3599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3600 alu.op = ALU_OP2_SUB_INT;
3601
3602 alu.dst.sel = tmp0;
3603 alu.dst.chan = 0;
3604 alu.dst.write = 1;
3605
3606 alu.src[0].sel = V_SQ_ALU_SRC_0;
3607 alu.src[1].sel = tmp0;
3608 alu.src[1].chan = 2;
3609
3610 alu.last = 1;
3611 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3612 return r;
3613
3614 /* sign of the remainder is the same as the sign of src0 */
3615 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3616 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3617 alu.op = ALU_OP3_CNDGE_INT;
3618 alu.is_op3 = 1;
3619
3620 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3621
3622 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3623 alu.src[1].sel = tmp0;
3624 alu.src[1].chan = 2;
3625 alu.src[2].sel = tmp0;
3626 alu.src[2].chan = 0;
3627
3628 alu.last = 1;
3629 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3630 return r;
3631
3632 } else {
3633
3634 /* tmp0.x = -tmp0.z */
3635 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3636 alu.op = ALU_OP2_SUB_INT;
3637
3638 alu.dst.sel = tmp0;
3639 alu.dst.chan = 0;
3640 alu.dst.write = 1;
3641
3642 alu.src[0].sel = V_SQ_ALU_SRC_0;
3643 alu.src[1].sel = tmp0;
3644 alu.src[1].chan = 2;
3645
3646 alu.last = 1;
3647 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3648 return r;
3649
3650 /* fix the quotient sign (same as the sign of src0*src1) */
3651 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3652 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3653 alu.op = ALU_OP3_CNDGE_INT;
3654 alu.is_op3 = 1;
3655
3656 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3657
3658 alu.src[0].sel = tmp2;
3659 alu.src[0].chan = 2;
3660 alu.src[1].sel = tmp0;
3661 alu.src[1].chan = 2;
3662 alu.src[2].sel = tmp0;
3663 alu.src[2].chan = 0;
3664
3665 alu.last = 1;
3666 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3667 return r;
3668 }
3669 }
3670 }
3671 return 0;
3672 }
3673
3674 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3675 {
3676 return tgsi_divmod(ctx, 0, 0);
3677 }
3678
3679 static int tgsi_umod(struct r600_shader_ctx *ctx)
3680 {
3681 return tgsi_divmod(ctx, 1, 0);
3682 }
3683
3684 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3685 {
3686 return tgsi_divmod(ctx, 0, 1);
3687 }
3688
3689 static int tgsi_imod(struct r600_shader_ctx *ctx)
3690 {
3691 return tgsi_divmod(ctx, 1, 1);
3692 }
3693
3694
3695 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3696 {
3697 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3698 struct r600_bytecode_alu alu;
3699 int i, r;
3700 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3701 int last_inst = tgsi_last_instruction(write_mask);
3702
3703 for (i = 0; i < 4; i++) {
3704 if (!(write_mask & (1<<i)))
3705 continue;
3706
3707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3708 alu.op = ALU_OP1_TRUNC;
3709
3710 alu.dst.sel = ctx->temp_reg;
3711 alu.dst.chan = i;
3712 alu.dst.write = 1;
3713
3714 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3715 if (i == last_inst)
3716 alu.last = 1;
3717 r = r600_bytecode_add_alu(ctx->bc, &alu);
3718 if (r)
3719 return r;
3720 }
3721
3722 for (i = 0; i < 4; i++) {
3723 if (!(write_mask & (1<<i)))
3724 continue;
3725
3726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3727 alu.op = ctx->inst_info->op;
3728
3729 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3730
3731 alu.src[0].sel = ctx->temp_reg;
3732 alu.src[0].chan = i;
3733
3734 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3735 alu.last = 1;
3736 r = r600_bytecode_add_alu(ctx->bc, &alu);
3737 if (r)
3738 return r;
3739 }
3740
3741 return 0;
3742 }
3743
3744 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3745 {
3746 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3747 struct r600_bytecode_alu alu;
3748 int i, r;
3749 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3750 int last_inst = tgsi_last_instruction(write_mask);
3751
3752 /* tmp = -src */
3753 for (i = 0; i < 4; i++) {
3754 if (!(write_mask & (1<<i)))
3755 continue;
3756
3757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3758 alu.op = ALU_OP2_SUB_INT;
3759
3760 alu.dst.sel = ctx->temp_reg;
3761 alu.dst.chan = i;
3762 alu.dst.write = 1;
3763
3764 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3765 alu.src[0].sel = V_SQ_ALU_SRC_0;
3766
3767 if (i == last_inst)
3768 alu.last = 1;
3769 r = r600_bytecode_add_alu(ctx->bc, &alu);
3770 if (r)
3771 return r;
3772 }
3773
3774 /* dst = (src >= 0 ? src : tmp) */
3775 for (i = 0; i < 4; i++) {
3776 if (!(write_mask & (1<<i)))
3777 continue;
3778
3779 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3780 alu.op = ALU_OP3_CNDGE_INT;
3781 alu.is_op3 = 1;
3782 alu.dst.write = 1;
3783
3784 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3785
3786 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3787 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3788 alu.src[2].sel = ctx->temp_reg;
3789 alu.src[2].chan = i;
3790
3791 if (i == last_inst)
3792 alu.last = 1;
3793 r = r600_bytecode_add_alu(ctx->bc, &alu);
3794 if (r)
3795 return r;
3796 }
3797 return 0;
3798 }
3799
3800 static int tgsi_issg(struct r600_shader_ctx *ctx)
3801 {
3802 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3803 struct r600_bytecode_alu alu;
3804 int i, r;
3805 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3806 int last_inst = tgsi_last_instruction(write_mask);
3807
3808 /* tmp = (src >= 0 ? src : -1) */
3809 for (i = 0; i < 4; i++) {
3810 if (!(write_mask & (1<<i)))
3811 continue;
3812
3813 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3814 alu.op = ALU_OP3_CNDGE_INT;
3815 alu.is_op3 = 1;
3816
3817 alu.dst.sel = ctx->temp_reg;
3818 alu.dst.chan = i;
3819 alu.dst.write = 1;
3820
3821 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3822 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3823 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3824
3825 if (i == last_inst)
3826 alu.last = 1;
3827 r = r600_bytecode_add_alu(ctx->bc, &alu);
3828 if (r)
3829 return r;
3830 }
3831
3832 /* dst = (tmp > 0 ? 1 : tmp) */
3833 for (i = 0; i < 4; i++) {
3834 if (!(write_mask & (1<<i)))
3835 continue;
3836
3837 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3838 alu.op = ALU_OP3_CNDGT_INT;
3839 alu.is_op3 = 1;
3840 alu.dst.write = 1;
3841
3842 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3843
3844 alu.src[0].sel = ctx->temp_reg;
3845 alu.src[0].chan = i;
3846
3847 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3848
3849 alu.src[2].sel = ctx->temp_reg;
3850 alu.src[2].chan = i;
3851
3852 if (i == last_inst)
3853 alu.last = 1;
3854 r = r600_bytecode_add_alu(ctx->bc, &alu);
3855 if (r)
3856 return r;
3857 }
3858 return 0;
3859 }
3860
3861
3862
3863 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3864 {
3865 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3866 struct r600_bytecode_alu alu;
3867 int i, r;
3868
3869 /* tmp = (src > 0 ? 1 : src) */
3870 for (i = 0; i < 4; i++) {
3871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3872 alu.op = ALU_OP3_CNDGT;
3873 alu.is_op3 = 1;
3874
3875 alu.dst.sel = ctx->temp_reg;
3876 alu.dst.chan = i;
3877
3878 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3879 alu.src[1].sel = V_SQ_ALU_SRC_1;
3880 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3881
3882 if (i == 3)
3883 alu.last = 1;
3884 r = r600_bytecode_add_alu(ctx->bc, &alu);
3885 if (r)
3886 return r;
3887 }
3888
3889 /* dst = (-tmp > 0 ? -1 : tmp) */
3890 for (i = 0; i < 4; i++) {
3891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3892 alu.op = ALU_OP3_CNDGT;
3893 alu.is_op3 = 1;
3894 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3895
3896 alu.src[0].sel = ctx->temp_reg;
3897 alu.src[0].chan = i;
3898 alu.src[0].neg = 1;
3899
3900 alu.src[1].sel = V_SQ_ALU_SRC_1;
3901 alu.src[1].neg = 1;
3902
3903 alu.src[2].sel = ctx->temp_reg;
3904 alu.src[2].chan = i;
3905
3906 if (i == 3)
3907 alu.last = 1;
3908 r = r600_bytecode_add_alu(ctx->bc, &alu);
3909 if (r)
3910 return r;
3911 }
3912 return 0;
3913 }
3914
3915 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3916 {
3917 struct r600_bytecode_alu alu;
3918 int i, r;
3919
3920 for (i = 0; i < 4; i++) {
3921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3922 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3923 alu.op = ALU_OP0_NOP;
3924 alu.dst.chan = i;
3925 } else {
3926 alu.op = ALU_OP1_MOV;
3927 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3928 alu.src[0].sel = ctx->temp_reg;
3929 alu.src[0].chan = i;
3930 }
3931 if (i == 3) {
3932 alu.last = 1;
3933 }
3934 r = r600_bytecode_add_alu(ctx->bc, &alu);
3935 if (r)
3936 return r;
3937 }
3938 return 0;
3939 }
3940
3941 static int tgsi_op3(struct r600_shader_ctx *ctx)
3942 {
3943 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3944 struct r600_bytecode_alu alu;
3945 int i, j, r;
3946 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3947
3948 for (i = 0; i < lasti + 1; i++) {
3949 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3950 continue;
3951
3952 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3953 alu.op = ctx->inst_info->op;
3954 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3955 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3956 }
3957
3958 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3959 alu.dst.chan = i;
3960 alu.dst.write = 1;
3961 alu.is_op3 = 1;
3962 if (i == lasti) {
3963 alu.last = 1;
3964 }
3965 r = r600_bytecode_add_alu(ctx->bc, &alu);
3966 if (r)
3967 return r;
3968 }
3969 return 0;
3970 }
3971
3972 static int tgsi_dp(struct r600_shader_ctx *ctx)
3973 {
3974 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3975 struct r600_bytecode_alu alu;
3976 int i, j, r;
3977
3978 for (i = 0; i < 4; i++) {
3979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3980 alu.op = ctx->inst_info->op;
3981 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3982 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3983 }
3984
3985 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3986 alu.dst.chan = i;
3987 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3988 /* handle some special cases */
3989 switch (ctx->inst_info->tgsi_opcode) {
3990 case TGSI_OPCODE_DP2:
3991 if (i > 1) {
3992 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3993 alu.src[0].chan = alu.src[1].chan = 0;
3994 }
3995 break;
3996 case TGSI_OPCODE_DP3:
3997 if (i > 2) {
3998 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3999 alu.src[0].chan = alu.src[1].chan = 0;
4000 }
4001 break;
4002 case TGSI_OPCODE_DPH:
4003 if (i == 3) {
4004 alu.src[0].sel = V_SQ_ALU_SRC_1;
4005 alu.src[0].chan = 0;
4006 alu.src[0].neg = 0;
4007 }
4008 break;
4009 default:
4010 break;
4011 }
4012 if (i == 3) {
4013 alu.last = 1;
4014 }
4015 r = r600_bytecode_add_alu(ctx->bc, &alu);
4016 if (r)
4017 return r;
4018 }
4019 return 0;
4020 }
4021
4022 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
4023 unsigned index)
4024 {
4025 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4026 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
4027 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
4028 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
4029 ctx->src[index].neg || ctx->src[index].abs;
4030 }
4031
4032 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
4033 unsigned index)
4034 {
4035 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4036 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
4037 }
4038
4039 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
4040 {
4041 struct r600_bytecode_vtx vtx;
4042 struct r600_bytecode_alu alu;
4043 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4044 int src_gpr, r, i;
4045 int id = tgsi_tex_get_src_gpr(ctx, 1);
4046
4047 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4048 if (src_requires_loading) {
4049 for (i = 0; i < 4; i++) {
4050 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4051 alu.op = ALU_OP1_MOV;
4052 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4053 alu.dst.sel = ctx->temp_reg;
4054 alu.dst.chan = i;
4055 if (i == 3)
4056 alu.last = 1;
4057 alu.dst.write = 1;
4058 r = r600_bytecode_add_alu(ctx->bc, &alu);
4059 if (r)
4060 return r;
4061 }
4062 src_gpr = ctx->temp_reg;
4063 }
4064
4065 memset(&vtx, 0, sizeof(vtx));
4066 vtx.op = FETCH_OP_VFETCH;
4067 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
4068 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
4069 vtx.src_gpr = src_gpr;
4070 vtx.mega_fetch_count = 16;
4071 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4072 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
4073 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
4074 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
4075 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
4076 vtx.use_const_fields = 1;
4077 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
4078
4079 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
4080 return r;
4081
4082 if (ctx->bc->chip_class >= EVERGREEN)
4083 return 0;
4084
4085 for (i = 0; i < 4; i++) {
4086 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4087 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4088 continue;
4089
4090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4091 alu.op = ALU_OP2_AND_INT;
4092
4093 alu.dst.chan = i;
4094 alu.dst.sel = vtx.dst_gpr;
4095 alu.dst.write = 1;
4096
4097 alu.src[0].sel = vtx.dst_gpr;
4098 alu.src[0].chan = i;
4099
4100 alu.src[1].sel = 512 + (id * 2);
4101 alu.src[1].chan = i % 4;
4102 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4103
4104 if (i == lasti)
4105 alu.last = 1;
4106 r = r600_bytecode_add_alu(ctx->bc, &alu);
4107 if (r)
4108 return r;
4109 }
4110
4111 if (inst->Dst[0].Register.WriteMask & 3) {
4112 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4113 alu.op = ALU_OP2_OR_INT;
4114
4115 alu.dst.chan = 3;
4116 alu.dst.sel = vtx.dst_gpr;
4117 alu.dst.write = 1;
4118
4119 alu.src[0].sel = vtx.dst_gpr;
4120 alu.src[0].chan = 3;
4121
4122 alu.src[1].sel = 512 + (id * 2) + 1;
4123 alu.src[1].chan = 0;
4124 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4125
4126 alu.last = 1;
4127 r = r600_bytecode_add_alu(ctx->bc, &alu);
4128 if (r)
4129 return r;
4130 }
4131 return 0;
4132 }
4133
4134 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
4135 {
4136 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4137 struct r600_bytecode_alu alu;
4138 int r;
4139 int id = tgsi_tex_get_src_gpr(ctx, 1);
4140
4141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4142 alu.op = ALU_OP1_MOV;
4143
4144 if (ctx->bc->chip_class >= EVERGREEN) {
4145 alu.src[0].sel = 512 + (id / 4);
4146 alu.src[0].chan = id % 4;
4147 } else {
4148 /* r600 we have them at channel 2 of the second dword */
4149 alu.src[0].sel = 512 + (id * 2) + 1;
4150 alu.src[0].chan = 1;
4151 }
4152 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4153 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4154 alu.last = 1;
4155 r = r600_bytecode_add_alu(ctx->bc, &alu);
4156 if (r)
4157 return r;
4158 return 0;
4159 }
4160
4161 static int tgsi_tex(struct r600_shader_ctx *ctx)
4162 {
4163 static float one_point_five = 1.5f;
4164 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4165 struct r600_bytecode_tex tex;
4166 struct r600_bytecode_alu alu;
4167 unsigned src_gpr;
4168 int r, i, j;
4169 int opcode;
4170 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
4171 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
4172 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
4173 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
4174
4175 /* Texture fetch instructions can only use gprs as source.
4176 * Also they cannot negate the source or take the absolute value */
4177 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
4178 tgsi_tex_src_requires_loading(ctx, 0)) ||
4179 read_compressed_msaa;
4180 boolean src_loaded = FALSE;
4181 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
4182 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
4183 boolean has_txq_cube_array_z = false;
4184
4185 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
4186 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4187 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
4188 if (inst->Dst[0].Register.WriteMask & 4) {
4189 ctx->shader->has_txq_cube_array_z_comp = true;
4190 has_txq_cube_array_z = true;
4191 }
4192
4193 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
4194 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4195 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4196 sampler_src_reg = 2;
4197
4198 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4199
4200 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
4201 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
4202 ctx->shader->uses_tex_buffers = true;
4203 return r600_do_buffer_txq(ctx);
4204 }
4205 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4206 if (ctx->bc->chip_class < EVERGREEN)
4207 ctx->shader->uses_tex_buffers = true;
4208 return do_vtx_fetch_inst(ctx, src_requires_loading);
4209 }
4210 }
4211
4212 /* get offset values */
4213 if (inst->Texture.NumOffsets) {
4214 assert(inst->Texture.NumOffsets == 1);
4215
4216 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
4217 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
4218 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
4219 }
4220
4221 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
4222 /* TGSI moves the sampler to src reg 3 for TXD */
4223 sampler_src_reg = 3;
4224
4225 for (i = 1; i < 3; i++) {
4226 /* set gradients h/v */
4227 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4228 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
4229 FETCH_OP_SET_GRADIENTS_V;
4230 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4231 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4232
4233 if (tgsi_tex_src_requires_loading(ctx, i)) {
4234 tex.src_gpr = r600_get_temp(ctx);
4235 tex.src_sel_x = 0;
4236 tex.src_sel_y = 1;
4237 tex.src_sel_z = 2;
4238 tex.src_sel_w = 3;
4239
4240 for (j = 0; j < 4; j++) {
4241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4242 alu.op = ALU_OP1_MOV;
4243 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
4244 alu.dst.sel = tex.src_gpr;
4245 alu.dst.chan = j;
4246 if (j == 3)
4247 alu.last = 1;
4248 alu.dst.write = 1;
4249 r = r600_bytecode_add_alu(ctx->bc, &alu);
4250 if (r)
4251 return r;
4252 }
4253
4254 } else {
4255 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
4256 tex.src_sel_x = ctx->src[i].swizzle[0];
4257 tex.src_sel_y = ctx->src[i].swizzle[1];
4258 tex.src_sel_z = ctx->src[i].swizzle[2];
4259 tex.src_sel_w = ctx->src[i].swizzle[3];
4260 tex.src_rel = ctx->src[i].rel;
4261 }
4262 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
4263 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4264 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
4265 tex.coord_type_x = 1;
4266 tex.coord_type_y = 1;
4267 tex.coord_type_z = 1;
4268 tex.coord_type_w = 1;
4269 }
4270 r = r600_bytecode_add_tex(ctx->bc, &tex);
4271 if (r)
4272 return r;
4273 }
4274 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
4275 int out_chan;
4276 /* Add perspective divide */
4277 if (ctx->bc->chip_class == CAYMAN) {
4278 out_chan = 2;
4279 for (i = 0; i < 3; i++) {
4280 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4281 alu.op = ALU_OP1_RECIP_IEEE;
4282 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4283
4284 alu.dst.sel = ctx->temp_reg;
4285 alu.dst.chan = i;
4286 if (i == 2)
4287 alu.last = 1;
4288 if (out_chan == i)
4289 alu.dst.write = 1;
4290 r = r600_bytecode_add_alu(ctx->bc, &alu);
4291 if (r)
4292 return r;
4293 }
4294
4295 } else {
4296 out_chan = 3;
4297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4298 alu.op = ALU_OP1_RECIP_IEEE;
4299 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4300
4301 alu.dst.sel = ctx->temp_reg;
4302 alu.dst.chan = out_chan;
4303 alu.last = 1;
4304 alu.dst.write = 1;
4305 r = r600_bytecode_add_alu(ctx->bc, &alu);
4306 if (r)
4307 return r;
4308 }
4309
4310 for (i = 0; i < 3; i++) {
4311 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4312 alu.op = ALU_OP2_MUL;
4313 alu.src[0].sel = ctx->temp_reg;
4314 alu.src[0].chan = out_chan;
4315 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4316 alu.dst.sel = ctx->temp_reg;
4317 alu.dst.chan = i;
4318 alu.dst.write = 1;
4319 r = r600_bytecode_add_alu(ctx->bc, &alu);
4320 if (r)
4321 return r;
4322 }
4323 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4324 alu.op = ALU_OP1_MOV;
4325 alu.src[0].sel = V_SQ_ALU_SRC_1;
4326 alu.src[0].chan = 0;
4327 alu.dst.sel = ctx->temp_reg;
4328 alu.dst.chan = 3;
4329 alu.last = 1;
4330 alu.dst.write = 1;
4331 r = r600_bytecode_add_alu(ctx->bc, &alu);
4332 if (r)
4333 return r;
4334 src_loaded = TRUE;
4335 src_gpr = ctx->temp_reg;
4336 }
4337
4338 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4339 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4340 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4341 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4342 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
4343 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
4344
4345 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
4346 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
4347
4348 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
4349 for (i = 0; i < 4; i++) {
4350 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4351 alu.op = ALU_OP2_CUBE;
4352 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4353 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
4354 alu.dst.sel = ctx->temp_reg;
4355 alu.dst.chan = i;
4356 if (i == 3)
4357 alu.last = 1;
4358 alu.dst.write = 1;
4359 r = r600_bytecode_add_alu(ctx->bc, &alu);
4360 if (r)
4361 return r;
4362 }
4363
4364 /* tmp1.z = RCP_e(|tmp1.z|) */
4365 if (ctx->bc->chip_class == CAYMAN) {
4366 for (i = 0; i < 3; i++) {
4367 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4368 alu.op = ALU_OP1_RECIP_IEEE;
4369 alu.src[0].sel = ctx->temp_reg;
4370 alu.src[0].chan = 2;
4371 alu.src[0].abs = 1;
4372 alu.dst.sel = ctx->temp_reg;
4373 alu.dst.chan = i;
4374 if (i == 2)
4375 alu.dst.write = 1;
4376 if (i == 2)
4377 alu.last = 1;
4378 r = r600_bytecode_add_alu(ctx->bc, &alu);
4379 if (r)
4380 return r;
4381 }
4382 } else {
4383 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4384 alu.op = ALU_OP1_RECIP_IEEE;
4385 alu.src[0].sel = ctx->temp_reg;
4386 alu.src[0].chan = 2;
4387 alu.src[0].abs = 1;
4388 alu.dst.sel = ctx->temp_reg;
4389 alu.dst.chan = 2;
4390 alu.dst.write = 1;
4391 alu.last = 1;
4392 r = r600_bytecode_add_alu(ctx->bc, &alu);
4393 if (r)
4394 return r;
4395 }
4396
4397 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4398 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4399 * muladd has no writemask, have to use another temp
4400 */
4401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4402 alu.op = ALU_OP3_MULADD;
4403 alu.is_op3 = 1;
4404
4405 alu.src[0].sel = ctx->temp_reg;
4406 alu.src[0].chan = 0;
4407 alu.src[1].sel = ctx->temp_reg;
4408 alu.src[1].chan = 2;
4409
4410 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4411 alu.src[2].chan = 0;
4412 alu.src[2].value = *(uint32_t *)&one_point_five;
4413
4414 alu.dst.sel = ctx->temp_reg;
4415 alu.dst.chan = 0;
4416 alu.dst.write = 1;
4417
4418 r = r600_bytecode_add_alu(ctx->bc, &alu);
4419 if (r)
4420 return r;
4421
4422 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4423 alu.op = ALU_OP3_MULADD;
4424 alu.is_op3 = 1;
4425
4426 alu.src[0].sel = ctx->temp_reg;
4427 alu.src[0].chan = 1;
4428 alu.src[1].sel = ctx->temp_reg;
4429 alu.src[1].chan = 2;
4430
4431 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4432 alu.src[2].chan = 0;
4433 alu.src[2].value = *(uint32_t *)&one_point_five;
4434
4435 alu.dst.sel = ctx->temp_reg;
4436 alu.dst.chan = 1;
4437 alu.dst.write = 1;
4438
4439 alu.last = 1;
4440 r = r600_bytecode_add_alu(ctx->bc, &alu);
4441 if (r)
4442 return r;
4443 /* write initial compare value into Z component
4444 - W src 0 for shadow cube
4445 - X src 1 for shadow cube array */
4446 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4447 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4448 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4449 alu.op = ALU_OP1_MOV;
4450 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4451 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4452 else
4453 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4454 alu.dst.sel = ctx->temp_reg;
4455 alu.dst.chan = 2;
4456 alu.dst.write = 1;
4457 alu.last = 1;
4458 r = r600_bytecode_add_alu(ctx->bc, &alu);
4459 if (r)
4460 return r;
4461 }
4462
4463 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4464 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4465 if (ctx->bc->chip_class >= EVERGREEN) {
4466 int mytmp = r600_get_temp(ctx);
4467 static const float eight = 8.0f;
4468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4469 alu.op = ALU_OP1_MOV;
4470 alu.src[0].sel = ctx->temp_reg;
4471 alu.src[0].chan = 3;
4472 alu.dst.sel = mytmp;
4473 alu.dst.chan = 0;
4474 alu.dst.write = 1;
4475 alu.last = 1;
4476 r = r600_bytecode_add_alu(ctx->bc, &alu);
4477 if (r)
4478 return r;
4479
4480 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4482 alu.op = ALU_OP3_MULADD;
4483 alu.is_op3 = 1;
4484 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4485 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4486 alu.src[1].chan = 0;
4487 alu.src[1].value = *(uint32_t *)&eight;
4488 alu.src[2].sel = mytmp;
4489 alu.src[2].chan = 0;
4490 alu.dst.sel = ctx->temp_reg;
4491 alu.dst.chan = 3;
4492 alu.dst.write = 1;
4493 alu.last = 1;
4494 r = r600_bytecode_add_alu(ctx->bc, &alu);
4495 if (r)
4496 return r;
4497 } else if (ctx->bc->chip_class < EVERGREEN) {
4498 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4499 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4500 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4501 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4502 tex.src_gpr = r600_get_temp(ctx);
4503 tex.src_sel_x = 0;
4504 tex.src_sel_y = 0;
4505 tex.src_sel_z = 0;
4506 tex.src_sel_w = 0;
4507 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4508 tex.coord_type_x = 1;
4509 tex.coord_type_y = 1;
4510 tex.coord_type_z = 1;
4511 tex.coord_type_w = 1;
4512 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4513 alu.op = ALU_OP1_MOV;
4514 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4515 alu.dst.sel = tex.src_gpr;
4516 alu.dst.chan = 0;
4517 alu.last = 1;
4518 alu.dst.write = 1;
4519 r = r600_bytecode_add_alu(ctx->bc, &alu);
4520 if (r)
4521 return r;
4522
4523 r = r600_bytecode_add_tex(ctx->bc, &tex);
4524 if (r)
4525 return r;
4526 }
4527
4528 }
4529
4530 /* for cube forms of lod and bias we need to route things */
4531 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4532 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4533 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4534 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4535 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4536 alu.op = ALU_OP1_MOV;
4537 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4538 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4539 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4540 else
4541 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4542 alu.dst.sel = ctx->temp_reg;
4543 alu.dst.chan = 2;
4544 alu.last = 1;
4545 alu.dst.write = 1;
4546 r = r600_bytecode_add_alu(ctx->bc, &alu);
4547 if (r)
4548 return r;
4549 }
4550
4551 src_loaded = TRUE;
4552 src_gpr = ctx->temp_reg;
4553 }
4554
4555 if (src_requires_loading && !src_loaded) {
4556 for (i = 0; i < 4; i++) {
4557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4558 alu.op = ALU_OP1_MOV;
4559 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4560 alu.dst.sel = ctx->temp_reg;
4561 alu.dst.chan = i;
4562 if (i == 3)
4563 alu.last = 1;
4564 alu.dst.write = 1;
4565 r = r600_bytecode_add_alu(ctx->bc, &alu);
4566 if (r)
4567 return r;
4568 }
4569 src_loaded = TRUE;
4570 src_gpr = ctx->temp_reg;
4571 }
4572
4573 /* Obtain the sample index for reading a compressed MSAA color texture.
4574 * To read the FMASK, we use the ldfptr instruction, which tells us
4575 * where the samples are stored.
4576 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4577 * which is the identity mapping. Each nibble says which physical sample
4578 * should be fetched to get that sample.
4579 *
4580 * Assume src.z contains the sample index. It should be modified like this:
4581 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4582 * Then fetch the texel with src.
4583 */
4584 if (read_compressed_msaa) {
4585 unsigned sample_chan = 3;
4586 unsigned temp = r600_get_temp(ctx);
4587 assert(src_loaded);
4588
4589 /* temp.w = ldfptr() */
4590 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4591 tex.op = FETCH_OP_LD;
4592 tex.inst_mod = 1; /* to indicate this is ldfptr */
4593 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4594 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4595 tex.src_gpr = src_gpr;
4596 tex.dst_gpr = temp;
4597 tex.dst_sel_x = 7; /* mask out these components */
4598 tex.dst_sel_y = 7;
4599 tex.dst_sel_z = 7;
4600 tex.dst_sel_w = 0; /* store X */
4601 tex.src_sel_x = 0;
4602 tex.src_sel_y = 1;
4603 tex.src_sel_z = 2;
4604 tex.src_sel_w = 3;
4605 tex.offset_x = offset_x;
4606 tex.offset_y = offset_y;
4607 tex.offset_z = offset_z;
4608 r = r600_bytecode_add_tex(ctx->bc, &tex);
4609 if (r)
4610 return r;
4611
4612 /* temp.x = sample_index*4 */
4613 if (ctx->bc->chip_class == CAYMAN) {
4614 for (i = 0 ; i < 4; i++) {
4615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4616 alu.op = ALU_OP2_MULLO_INT;
4617 alu.src[0].sel = src_gpr;
4618 alu.src[0].chan = sample_chan;
4619 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4620 alu.src[1].value = 4;
4621 alu.dst.sel = temp;
4622 alu.dst.chan = i;
4623 alu.dst.write = i == 0;
4624 if (i == 3)
4625 alu.last = 1;
4626 r = r600_bytecode_add_alu(ctx->bc, &alu);
4627 if (r)
4628 return r;
4629 }
4630 } else {
4631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4632 alu.op = ALU_OP2_MULLO_INT;
4633 alu.src[0].sel = src_gpr;
4634 alu.src[0].chan = sample_chan;
4635 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4636 alu.src[1].value = 4;
4637 alu.dst.sel = temp;
4638 alu.dst.chan = 0;
4639 alu.dst.write = 1;
4640 alu.last = 1;
4641 r = r600_bytecode_add_alu(ctx->bc, &alu);
4642 if (r)
4643 return r;
4644 }
4645
4646 /* sample_index = temp.w >> temp.x */
4647 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4648 alu.op = ALU_OP2_LSHR_INT;
4649 alu.src[0].sel = temp;
4650 alu.src[0].chan = 3;
4651 alu.src[1].sel = temp;
4652 alu.src[1].chan = 0;
4653 alu.dst.sel = src_gpr;
4654 alu.dst.chan = sample_chan;
4655 alu.dst.write = 1;
4656 alu.last = 1;
4657 r = r600_bytecode_add_alu(ctx->bc, &alu);
4658 if (r)
4659 return r;
4660
4661 /* sample_index & 0xF */
4662 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4663 alu.op = ALU_OP2_AND_INT;
4664 alu.src[0].sel = src_gpr;
4665 alu.src[0].chan = sample_chan;
4666 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4667 alu.src[1].value = 0xF;
4668 alu.dst.sel = src_gpr;
4669 alu.dst.chan = sample_chan;
4670 alu.dst.write = 1;
4671 alu.last = 1;
4672 r = r600_bytecode_add_alu(ctx->bc, &alu);
4673 if (r)
4674 return r;
4675 #if 0
4676 /* visualize the FMASK */
4677 for (i = 0; i < 4; i++) {
4678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4679 alu.op = ALU_OP1_INT_TO_FLT;
4680 alu.src[0].sel = src_gpr;
4681 alu.src[0].chan = sample_chan;
4682 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4683 alu.dst.chan = i;
4684 alu.dst.write = 1;
4685 alu.last = 1;
4686 r = r600_bytecode_add_alu(ctx->bc, &alu);
4687 if (r)
4688 return r;
4689 }
4690 return 0;
4691 #endif
4692 }
4693
4694 /* does this shader want a num layers from TXQ for a cube array? */
4695 if (has_txq_cube_array_z) {
4696 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4697
4698 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4699 alu.op = ALU_OP1_MOV;
4700
4701 alu.src[0].sel = 512 + (id / 4);
4702 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4703 alu.src[0].chan = id % 4;
4704 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4705 alu.last = 1;
4706 r = r600_bytecode_add_alu(ctx->bc, &alu);
4707 if (r)
4708 return r;
4709 /* disable writemask from texture instruction */
4710 inst->Dst[0].Register.WriteMask &= ~4;
4711 }
4712
4713 opcode = ctx->inst_info->op;
4714 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4715 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4716 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4717 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4718 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4719 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4720 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4721 switch (opcode) {
4722 case FETCH_OP_SAMPLE:
4723 opcode = FETCH_OP_SAMPLE_C;
4724 break;
4725 case FETCH_OP_SAMPLE_L:
4726 opcode = FETCH_OP_SAMPLE_C_L;
4727 break;
4728 case FETCH_OP_SAMPLE_LB:
4729 opcode = FETCH_OP_SAMPLE_C_LB;
4730 break;
4731 case FETCH_OP_SAMPLE_G:
4732 opcode = FETCH_OP_SAMPLE_C_G;
4733 break;
4734 }
4735 }
4736
4737 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4738 tex.op = opcode;
4739
4740 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4741 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4742 tex.src_gpr = src_gpr;
4743 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4744 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4745 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4746 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4747 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4748
4749 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4750 tex.src_sel_x = 4;
4751 tex.src_sel_y = 4;
4752 tex.src_sel_z = 4;
4753 tex.src_sel_w = 4;
4754 } else if (src_loaded) {
4755 tex.src_sel_x = 0;
4756 tex.src_sel_y = 1;
4757 tex.src_sel_z = 2;
4758 tex.src_sel_w = 3;
4759 } else {
4760 tex.src_sel_x = ctx->src[0].swizzle[0];
4761 tex.src_sel_y = ctx->src[0].swizzle[1];
4762 tex.src_sel_z = ctx->src[0].swizzle[2];
4763 tex.src_sel_w = ctx->src[0].swizzle[3];
4764 tex.src_rel = ctx->src[0].rel;
4765 }
4766
4767 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4768 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4769 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4770 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4771 tex.src_sel_x = 1;
4772 tex.src_sel_y = 0;
4773 tex.src_sel_z = 3;
4774 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4775 }
4776
4777 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4778 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4779 tex.coord_type_x = 1;
4780 tex.coord_type_y = 1;
4781 }
4782 tex.coord_type_z = 1;
4783 tex.coord_type_w = 1;
4784
4785 tex.offset_x = offset_x;
4786 tex.offset_y = offset_y;
4787 tex.offset_z = offset_z;
4788
4789 /* Put the depth for comparison in W.
4790 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4791 * Some instructions expect the depth in Z. */
4792 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4793 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4794 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4795 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4796 opcode != FETCH_OP_SAMPLE_C_L &&
4797 opcode != FETCH_OP_SAMPLE_C_LB) {
4798 tex.src_sel_w = tex.src_sel_z;
4799 }
4800
4801 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4802 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4803 if (opcode == FETCH_OP_SAMPLE_C_L ||
4804 opcode == FETCH_OP_SAMPLE_C_LB) {
4805 /* the array index is read from Y */
4806 tex.coord_type_y = 0;
4807 } else {
4808 /* the array index is read from Z */
4809 tex.coord_type_z = 0;
4810 tex.src_sel_z = tex.src_sel_y;
4811 }
4812 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4813 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4814 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4815 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4816 (ctx->bc->chip_class >= EVERGREEN)))
4817 /* the array index is read from Z */
4818 tex.coord_type_z = 0;
4819
4820 /* mask unused source components */
4821 if (opcode == FETCH_OP_SAMPLE) {
4822 switch (inst->Texture.Texture) {
4823 case TGSI_TEXTURE_2D:
4824 case TGSI_TEXTURE_RECT:
4825 tex.src_sel_z = 7;
4826 tex.src_sel_w = 7;
4827 break;
4828 case TGSI_TEXTURE_1D_ARRAY:
4829 tex.src_sel_y = 7;
4830 tex.src_sel_w = 7;
4831 break;
4832 case TGSI_TEXTURE_1D:
4833 tex.src_sel_y = 7;
4834 tex.src_sel_z = 7;
4835 tex.src_sel_w = 7;
4836 break;
4837 }
4838 }
4839
4840 r = r600_bytecode_add_tex(ctx->bc, &tex);
4841 if (r)
4842 return r;
4843
4844 /* add shadow ambient support - gallium doesn't do it yet */
4845 return 0;
4846 }
4847
4848 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4849 {
4850 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4851 struct r600_bytecode_alu alu;
4852 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4853 unsigned i;
4854 int r;
4855
4856 /* optimize if it's just an equal balance */
4857 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4858 for (i = 0; i < lasti + 1; i++) {
4859 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4860 continue;
4861
4862 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4863 alu.op = ALU_OP2_ADD;
4864 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4865 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4866 alu.omod = 3;
4867 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4868 alu.dst.chan = i;
4869 if (i == lasti) {
4870 alu.last = 1;
4871 }
4872 r = r600_bytecode_add_alu(ctx->bc, &alu);
4873 if (r)
4874 return r;
4875 }
4876 return 0;
4877 }
4878
4879 /* 1 - src0 */
4880 for (i = 0; i < lasti + 1; i++) {
4881 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4882 continue;
4883
4884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4885 alu.op = ALU_OP2_ADD;
4886 alu.src[0].sel = V_SQ_ALU_SRC_1;
4887 alu.src[0].chan = 0;
4888 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4889 r600_bytecode_src_toggle_neg(&alu.src[1]);
4890 alu.dst.sel = ctx->temp_reg;
4891 alu.dst.chan = i;
4892 if (i == lasti) {
4893 alu.last = 1;
4894 }
4895 alu.dst.write = 1;
4896 r = r600_bytecode_add_alu(ctx->bc, &alu);
4897 if (r)
4898 return r;
4899 }
4900
4901 /* (1 - src0) * src2 */
4902 for (i = 0; i < lasti + 1; i++) {
4903 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4904 continue;
4905
4906 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4907 alu.op = ALU_OP2_MUL;
4908 alu.src[0].sel = ctx->temp_reg;
4909 alu.src[0].chan = i;
4910 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4911 alu.dst.sel = ctx->temp_reg;
4912 alu.dst.chan = i;
4913 if (i == lasti) {
4914 alu.last = 1;
4915 }
4916 alu.dst.write = 1;
4917 r = r600_bytecode_add_alu(ctx->bc, &alu);
4918 if (r)
4919 return r;
4920 }
4921
4922 /* src0 * src1 + (1 - src0) * src2 */
4923 for (i = 0; i < lasti + 1; i++) {
4924 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4925 continue;
4926
4927 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4928 alu.op = ALU_OP3_MULADD;
4929 alu.is_op3 = 1;
4930 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4931 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4932 alu.src[2].sel = ctx->temp_reg;
4933 alu.src[2].chan = i;
4934
4935 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4936 alu.dst.chan = i;
4937 if (i == lasti) {
4938 alu.last = 1;
4939 }
4940 r = r600_bytecode_add_alu(ctx->bc, &alu);
4941 if (r)
4942 return r;
4943 }
4944 return 0;
4945 }
4946
4947 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4948 {
4949 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4950 struct r600_bytecode_alu alu;
4951 int i, r;
4952 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4953
4954 for (i = 0; i < lasti + 1; i++) {
4955 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4956 continue;
4957
4958 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4959 alu.op = ALU_OP3_CNDGE;
4960 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4961 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4962 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4963 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4964 alu.dst.chan = i;
4965 alu.dst.write = 1;
4966 alu.is_op3 = 1;
4967 if (i == lasti)
4968 alu.last = 1;
4969 r = r600_bytecode_add_alu(ctx->bc, &alu);
4970 if (r)
4971 return r;
4972 }
4973 return 0;
4974 }
4975
4976 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4977 {
4978 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4979 struct r600_bytecode_alu alu;
4980 int i, r;
4981 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4982
4983 for (i = 0; i < lasti + 1; i++) {
4984 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4985 continue;
4986
4987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4988 alu.op = ALU_OP3_CNDGE_INT;
4989 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4990 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4991 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4992 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4993 alu.dst.chan = i;
4994 alu.dst.write = 1;
4995 alu.is_op3 = 1;
4996 if (i == lasti)
4997 alu.last = 1;
4998 r = r600_bytecode_add_alu(ctx->bc, &alu);
4999 if (r)
5000 return r;
5001 }
5002 return 0;
5003 }
5004
5005 static int tgsi_xpd(struct r600_shader_ctx *ctx)
5006 {
5007 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5008 static const unsigned int src0_swizzle[] = {2, 0, 1};
5009 static const unsigned int src1_swizzle[] = {1, 2, 0};
5010 struct r600_bytecode_alu alu;
5011 uint32_t use_temp = 0;
5012 int i, r;
5013
5014 if (inst->Dst[0].Register.WriteMask != 0xf)
5015 use_temp = 1;
5016
5017 for (i = 0; i < 4; i++) {
5018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5019 alu.op = ALU_OP2_MUL;
5020 if (i < 3) {
5021 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5022 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
5023 } else {
5024 alu.src[0].sel = V_SQ_ALU_SRC_0;
5025 alu.src[0].chan = i;
5026 alu.src[1].sel = V_SQ_ALU_SRC_0;
5027 alu.src[1].chan = i;
5028 }
5029
5030 alu.dst.sel = ctx->temp_reg;
5031 alu.dst.chan = i;
5032 alu.dst.write = 1;
5033
5034 if (i == 3)
5035 alu.last = 1;
5036 r = r600_bytecode_add_alu(ctx->bc, &alu);
5037 if (r)
5038 return r;
5039 }
5040
5041 for (i = 0; i < 4; i++) {
5042 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5043 alu.op = ALU_OP3_MULADD;
5044
5045 if (i < 3) {
5046 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
5047 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
5048 } else {
5049 alu.src[0].sel = V_SQ_ALU_SRC_0;
5050 alu.src[0].chan = i;
5051 alu.src[1].sel = V_SQ_ALU_SRC_0;
5052 alu.src[1].chan = i;
5053 }
5054
5055 alu.src[2].sel = ctx->temp_reg;
5056 alu.src[2].neg = 1;
5057 alu.src[2].chan = i;
5058
5059 if (use_temp)
5060 alu.dst.sel = ctx->temp_reg;
5061 else
5062 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5063 alu.dst.chan = i;
5064 alu.dst.write = 1;
5065 alu.is_op3 = 1;
5066 if (i == 3)
5067 alu.last = 1;
5068 r = r600_bytecode_add_alu(ctx->bc, &alu);
5069 if (r)
5070 return r;
5071 }
5072 if (use_temp)
5073 return tgsi_helper_copy(ctx, inst);
5074 return 0;
5075 }
5076
5077 static int tgsi_exp(struct r600_shader_ctx *ctx)
5078 {
5079 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5080 struct r600_bytecode_alu alu;
5081 int r;
5082 int i;
5083
5084 /* result.x = 2^floor(src); */
5085 if (inst->Dst[0].Register.WriteMask & 1) {
5086 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5087
5088 alu.op = ALU_OP1_FLOOR;
5089 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5090
5091 alu.dst.sel = ctx->temp_reg;
5092 alu.dst.chan = 0;
5093 alu.dst.write = 1;
5094 alu.last = 1;
5095 r = r600_bytecode_add_alu(ctx->bc, &alu);
5096 if (r)
5097 return r;
5098
5099 if (ctx->bc->chip_class == CAYMAN) {
5100 for (i = 0; i < 3; i++) {
5101 alu.op = ALU_OP1_EXP_IEEE;
5102 alu.src[0].sel = ctx->temp_reg;
5103 alu.src[0].chan = 0;
5104
5105 alu.dst.sel = ctx->temp_reg;
5106 alu.dst.chan = i;
5107 alu.dst.write = i == 0;
5108 alu.last = i == 2;
5109 r = r600_bytecode_add_alu(ctx->bc, &alu);
5110 if (r)
5111 return r;
5112 }
5113 } else {
5114 alu.op = ALU_OP1_EXP_IEEE;
5115 alu.src[0].sel = ctx->temp_reg;
5116 alu.src[0].chan = 0;
5117
5118 alu.dst.sel = ctx->temp_reg;
5119 alu.dst.chan = 0;
5120 alu.dst.write = 1;
5121 alu.last = 1;
5122 r = r600_bytecode_add_alu(ctx->bc, &alu);
5123 if (r)
5124 return r;
5125 }
5126 }
5127
5128 /* result.y = tmp - floor(tmp); */
5129 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5130 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5131
5132 alu.op = ALU_OP1_FRACT;
5133 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5134
5135 alu.dst.sel = ctx->temp_reg;
5136 #if 0
5137 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5138 if (r)
5139 return r;
5140 #endif
5141 alu.dst.write = 1;
5142 alu.dst.chan = 1;
5143
5144 alu.last = 1;
5145
5146 r = r600_bytecode_add_alu(ctx->bc, &alu);
5147 if (r)
5148 return r;
5149 }
5150
5151 /* result.z = RoughApprox2ToX(tmp);*/
5152 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
5153 if (ctx->bc->chip_class == CAYMAN) {
5154 for (i = 0; i < 3; i++) {
5155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5156 alu.op = ALU_OP1_EXP_IEEE;
5157 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5158
5159 alu.dst.sel = ctx->temp_reg;
5160 alu.dst.chan = i;
5161 if (i == 2) {
5162 alu.dst.write = 1;
5163 alu.last = 1;
5164 }
5165
5166 r = r600_bytecode_add_alu(ctx->bc, &alu);
5167 if (r)
5168 return r;
5169 }
5170 } else {
5171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5172 alu.op = ALU_OP1_EXP_IEEE;
5173 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5174
5175 alu.dst.sel = ctx->temp_reg;
5176 alu.dst.write = 1;
5177 alu.dst.chan = 2;
5178
5179 alu.last = 1;
5180
5181 r = r600_bytecode_add_alu(ctx->bc, &alu);
5182 if (r)
5183 return r;
5184 }
5185 }
5186
5187 /* result.w = 1.0;*/
5188 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
5189 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5190
5191 alu.op = ALU_OP1_MOV;
5192 alu.src[0].sel = V_SQ_ALU_SRC_1;
5193 alu.src[0].chan = 0;
5194
5195 alu.dst.sel = ctx->temp_reg;
5196 alu.dst.chan = 3;
5197 alu.dst.write = 1;
5198 alu.last = 1;
5199 r = r600_bytecode_add_alu(ctx->bc, &alu);
5200 if (r)
5201 return r;
5202 }
5203 return tgsi_helper_copy(ctx, inst);
5204 }
5205
5206 static int tgsi_log(struct r600_shader_ctx *ctx)
5207 {
5208 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5209 struct r600_bytecode_alu alu;
5210 int r;
5211 int i;
5212
5213 /* result.x = floor(log2(|src|)); */
5214 if (inst->Dst[0].Register.WriteMask & 1) {
5215 if (ctx->bc->chip_class == CAYMAN) {
5216 for (i = 0; i < 3; i++) {
5217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5218
5219 alu.op = ALU_OP1_LOG_IEEE;
5220 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5221 r600_bytecode_src_set_abs(&alu.src[0]);
5222
5223 alu.dst.sel = ctx->temp_reg;
5224 alu.dst.chan = i;
5225 if (i == 0)
5226 alu.dst.write = 1;
5227 if (i == 2)
5228 alu.last = 1;
5229 r = r600_bytecode_add_alu(ctx->bc, &alu);
5230 if (r)
5231 return r;
5232 }
5233
5234 } else {
5235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5236
5237 alu.op = ALU_OP1_LOG_IEEE;
5238 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5239 r600_bytecode_src_set_abs(&alu.src[0]);
5240
5241 alu.dst.sel = ctx->temp_reg;
5242 alu.dst.chan = 0;
5243 alu.dst.write = 1;
5244 alu.last = 1;
5245 r = r600_bytecode_add_alu(ctx->bc, &alu);
5246 if (r)
5247 return r;
5248 }
5249
5250 alu.op = ALU_OP1_FLOOR;
5251 alu.src[0].sel = ctx->temp_reg;
5252 alu.src[0].chan = 0;
5253
5254 alu.dst.sel = ctx->temp_reg;
5255 alu.dst.chan = 0;
5256 alu.dst.write = 1;
5257 alu.last = 1;
5258
5259 r = r600_bytecode_add_alu(ctx->bc, &alu);
5260 if (r)
5261 return r;
5262 }
5263
5264 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
5265 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5266
5267 if (ctx->bc->chip_class == CAYMAN) {
5268 for (i = 0; i < 3; i++) {
5269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5270
5271 alu.op = ALU_OP1_LOG_IEEE;
5272 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5273 r600_bytecode_src_set_abs(&alu.src[0]);
5274
5275 alu.dst.sel = ctx->temp_reg;
5276 alu.dst.chan = i;
5277 if (i == 1)
5278 alu.dst.write = 1;
5279 if (i == 2)
5280 alu.last = 1;
5281
5282 r = r600_bytecode_add_alu(ctx->bc, &alu);
5283 if (r)
5284 return r;
5285 }
5286 } else {
5287 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5288
5289 alu.op = ALU_OP1_LOG_IEEE;
5290 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5291 r600_bytecode_src_set_abs(&alu.src[0]);
5292
5293 alu.dst.sel = ctx->temp_reg;
5294 alu.dst.chan = 1;
5295 alu.dst.write = 1;
5296 alu.last = 1;
5297
5298 r = r600_bytecode_add_alu(ctx->bc, &alu);
5299 if (r)
5300 return r;
5301 }
5302
5303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5304
5305 alu.op = ALU_OP1_FLOOR;
5306 alu.src[0].sel = ctx->temp_reg;
5307 alu.src[0].chan = 1;
5308
5309 alu.dst.sel = ctx->temp_reg;
5310 alu.dst.chan = 1;
5311 alu.dst.write = 1;
5312 alu.last = 1;
5313
5314 r = r600_bytecode_add_alu(ctx->bc, &alu);
5315 if (r)
5316 return r;
5317
5318 if (ctx->bc->chip_class == CAYMAN) {
5319 for (i = 0; i < 3; i++) {
5320 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5321 alu.op = ALU_OP1_EXP_IEEE;
5322 alu.src[0].sel = ctx->temp_reg;
5323 alu.src[0].chan = 1;
5324
5325 alu.dst.sel = ctx->temp_reg;
5326 alu.dst.chan = i;
5327 if (i == 1)
5328 alu.dst.write = 1;
5329 if (i == 2)
5330 alu.last = 1;
5331
5332 r = r600_bytecode_add_alu(ctx->bc, &alu);
5333 if (r)
5334 return r;
5335 }
5336 } else {
5337 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5338 alu.op = ALU_OP1_EXP_IEEE;
5339 alu.src[0].sel = ctx->temp_reg;
5340 alu.src[0].chan = 1;
5341
5342 alu.dst.sel = ctx->temp_reg;
5343 alu.dst.chan = 1;
5344 alu.dst.write = 1;
5345 alu.last = 1;
5346
5347 r = r600_bytecode_add_alu(ctx->bc, &alu);
5348 if (r)
5349 return r;
5350 }
5351
5352 if (ctx->bc->chip_class == CAYMAN) {
5353 for (i = 0; i < 3; i++) {
5354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5355 alu.op = ALU_OP1_RECIP_IEEE;
5356 alu.src[0].sel = ctx->temp_reg;
5357 alu.src[0].chan = 1;
5358
5359 alu.dst.sel = ctx->temp_reg;
5360 alu.dst.chan = i;
5361 if (i == 1)
5362 alu.dst.write = 1;
5363 if (i == 2)
5364 alu.last = 1;
5365
5366 r = r600_bytecode_add_alu(ctx->bc, &alu);
5367 if (r)
5368 return r;
5369 }
5370 } else {
5371 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5372 alu.op = ALU_OP1_RECIP_IEEE;
5373 alu.src[0].sel = ctx->temp_reg;
5374 alu.src[0].chan = 1;
5375
5376 alu.dst.sel = ctx->temp_reg;
5377 alu.dst.chan = 1;
5378 alu.dst.write = 1;
5379 alu.last = 1;
5380
5381 r = r600_bytecode_add_alu(ctx->bc, &alu);
5382 if (r)
5383 return r;
5384 }
5385
5386 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5387
5388 alu.op = ALU_OP2_MUL;
5389
5390 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5391 r600_bytecode_src_set_abs(&alu.src[0]);
5392
5393 alu.src[1].sel = ctx->temp_reg;
5394 alu.src[1].chan = 1;
5395
5396 alu.dst.sel = ctx->temp_reg;
5397 alu.dst.chan = 1;
5398 alu.dst.write = 1;
5399 alu.last = 1;
5400
5401 r = r600_bytecode_add_alu(ctx->bc, &alu);
5402 if (r)
5403 return r;
5404 }
5405
5406 /* result.z = log2(|src|);*/
5407 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5408 if (ctx->bc->chip_class == CAYMAN) {
5409 for (i = 0; i < 3; i++) {
5410 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5411
5412 alu.op = ALU_OP1_LOG_IEEE;
5413 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5414 r600_bytecode_src_set_abs(&alu.src[0]);
5415
5416 alu.dst.sel = ctx->temp_reg;
5417 if (i == 2)
5418 alu.dst.write = 1;
5419 alu.dst.chan = i;
5420 if (i == 2)
5421 alu.last = 1;
5422
5423 r = r600_bytecode_add_alu(ctx->bc, &alu);
5424 if (r)
5425 return r;
5426 }
5427 } else {
5428 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5429
5430 alu.op = ALU_OP1_LOG_IEEE;
5431 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5432 r600_bytecode_src_set_abs(&alu.src[0]);
5433
5434 alu.dst.sel = ctx->temp_reg;
5435 alu.dst.write = 1;
5436 alu.dst.chan = 2;
5437 alu.last = 1;
5438
5439 r = r600_bytecode_add_alu(ctx->bc, &alu);
5440 if (r)
5441 return r;
5442 }
5443 }
5444
5445 /* result.w = 1.0; */
5446 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5447 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5448
5449 alu.op = ALU_OP1_MOV;
5450 alu.src[0].sel = V_SQ_ALU_SRC_1;
5451 alu.src[0].chan = 0;
5452
5453 alu.dst.sel = ctx->temp_reg;
5454 alu.dst.chan = 3;
5455 alu.dst.write = 1;
5456 alu.last = 1;
5457
5458 r = r600_bytecode_add_alu(ctx->bc, &alu);
5459 if (r)
5460 return r;
5461 }
5462
5463 return tgsi_helper_copy(ctx, inst);
5464 }
5465
5466 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5467 {
5468 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5469 struct r600_bytecode_alu alu;
5470 int r;
5471
5472 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5473
5474 switch (inst->Instruction.Opcode) {
5475 case TGSI_OPCODE_ARL:
5476 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5477 break;
5478 case TGSI_OPCODE_ARR:
5479 alu.op = ALU_OP1_FLT_TO_INT;
5480 break;
5481 case TGSI_OPCODE_UARL:
5482 alu.op = ALU_OP1_MOV;
5483 break;
5484 default:
5485 assert(0);
5486 return -1;
5487 }
5488
5489 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5490 alu.last = 1;
5491 alu.dst.sel = ctx->bc->ar_reg;
5492 alu.dst.write = 1;
5493 r = r600_bytecode_add_alu(ctx->bc, &alu);
5494 if (r)
5495 return r;
5496
5497 ctx->bc->ar_loaded = 0;
5498 return 0;
5499 }
5500 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5501 {
5502 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5503 struct r600_bytecode_alu alu;
5504 int r;
5505
5506 switch (inst->Instruction.Opcode) {
5507 case TGSI_OPCODE_ARL:
5508 memset(&alu, 0, sizeof(alu));
5509 alu.op = ALU_OP1_FLOOR;
5510 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5511 alu.dst.sel = ctx->bc->ar_reg;
5512 alu.dst.write = 1;
5513 alu.last = 1;
5514
5515 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5516 return r;
5517
5518 memset(&alu, 0, sizeof(alu));
5519 alu.op = ALU_OP1_FLT_TO_INT;
5520 alu.src[0].sel = ctx->bc->ar_reg;
5521 alu.dst.sel = ctx->bc->ar_reg;
5522 alu.dst.write = 1;
5523 alu.last = 1;
5524
5525 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5526 return r;
5527 break;
5528 case TGSI_OPCODE_ARR:
5529 memset(&alu, 0, sizeof(alu));
5530 alu.op = ALU_OP1_FLT_TO_INT;
5531 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5532 alu.dst.sel = ctx->bc->ar_reg;
5533 alu.dst.write = 1;
5534 alu.last = 1;
5535
5536 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5537 return r;
5538 break;
5539 case TGSI_OPCODE_UARL:
5540 memset(&alu, 0, sizeof(alu));
5541 alu.op = ALU_OP1_MOV;
5542 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5543 alu.dst.sel = ctx->bc->ar_reg;
5544 alu.dst.write = 1;
5545 alu.last = 1;
5546
5547 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5548 return r;
5549 break;
5550 default:
5551 assert(0);
5552 return -1;
5553 }
5554
5555 ctx->bc->ar_loaded = 0;
5556 return 0;
5557 }
5558
5559 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5560 {
5561 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5562 struct r600_bytecode_alu alu;
5563 int i, r = 0;
5564
5565 for (i = 0; i < 4; i++) {
5566 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5567
5568 alu.op = ALU_OP2_MUL;
5569 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5570
5571 if (i == 0 || i == 3) {
5572 alu.src[0].sel = V_SQ_ALU_SRC_1;
5573 } else {
5574 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5575 }
5576
5577 if (i == 0 || i == 2) {
5578 alu.src[1].sel = V_SQ_ALU_SRC_1;
5579 } else {
5580 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5581 }
5582 if (i == 3)
5583 alu.last = 1;
5584 r = r600_bytecode_add_alu(ctx->bc, &alu);
5585 if (r)
5586 return r;
5587 }
5588 return 0;
5589 }
5590
5591 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5592 {
5593 struct r600_bytecode_alu alu;
5594 int r;
5595
5596 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5597 alu.op = opcode;
5598 alu.execute_mask = 1;
5599 alu.update_pred = 1;
5600
5601 alu.dst.sel = ctx->temp_reg;
5602 alu.dst.write = 1;
5603 alu.dst.chan = 0;
5604
5605 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5606 alu.src[1].sel = V_SQ_ALU_SRC_0;
5607 alu.src[1].chan = 0;
5608
5609 alu.last = 1;
5610
5611 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5612 if (r)
5613 return r;
5614 return 0;
5615 }
5616
5617 static int pops(struct r600_shader_ctx *ctx, int pops)
5618 {
5619 unsigned force_pop = ctx->bc->force_add_cf;
5620
5621 if (!force_pop) {
5622 int alu_pop = 3;
5623 if (ctx->bc->cf_last) {
5624 if (ctx->bc->cf_last->op == CF_OP_ALU)
5625 alu_pop = 0;
5626 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5627 alu_pop = 1;
5628 }
5629 alu_pop += pops;
5630 if (alu_pop == 1) {
5631 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5632 ctx->bc->force_add_cf = 1;
5633 } else if (alu_pop == 2) {
5634 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5635 ctx->bc->force_add_cf = 1;
5636 } else {
5637 force_pop = 1;
5638 }
5639 }
5640
5641 if (force_pop) {
5642 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5643 ctx->bc->cf_last->pop_count = pops;
5644 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5645 }
5646
5647 return 0;
5648 }
5649
5650 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5651 unsigned reason)
5652 {
5653 struct r600_stack_info *stack = &ctx->bc->stack;
5654 unsigned elements, entries;
5655
5656 unsigned entry_size = stack->entry_size;
5657
5658 elements = (stack->loop + stack->push_wqm ) * entry_size;
5659 elements += stack->push;
5660
5661 switch (ctx->bc->chip_class) {
5662 case R600:
5663 case R700:
5664 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5665 * the stack must be reserved to hold the current active/continue
5666 * masks */
5667 if (reason == FC_PUSH_VPM) {
5668 elements += 2;
5669 }
5670 break;
5671
5672 case CAYMAN:
5673 /* r9xx: any stack operation on empty stack consumes 2 additional
5674 * elements */
5675 elements += 2;
5676
5677 /* fallthrough */
5678 /* FIXME: do the two elements added above cover the cases for the
5679 * r8xx+ below? */
5680
5681 case EVERGREEN:
5682 /* r8xx+: 2 extra elements are not always required, but one extra
5683 * element must be added for each of the following cases:
5684 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5685 * stack usage.
5686 * (Currently we don't use ALU_ELSE_AFTER.)
5687 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5688 * PUSH instruction executed.
5689 *
5690 * NOTE: it seems we also need to reserve additional element in some
5691 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5692 * then STACK_SIZE should be 2 instead of 1 */
5693 if (reason == FC_PUSH_VPM) {
5694 elements += 1;
5695 }
5696 break;
5697
5698 default:
5699 assert(0);
5700 break;
5701 }
5702
5703 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5704 * for all chips, so we use 4 in the final formula, not the real entry_size
5705 * for the chip */
5706 entry_size = 4;
5707
5708 entries = (elements + (entry_size - 1)) / entry_size;
5709
5710 if (entries > stack->max_entries)
5711 stack->max_entries = entries;
5712 }
5713
5714 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5715 {
5716 switch(reason) {
5717 case FC_PUSH_VPM:
5718 --ctx->bc->stack.push;
5719 assert(ctx->bc->stack.push >= 0);
5720 break;
5721 case FC_PUSH_WQM:
5722 --ctx->bc->stack.push_wqm;
5723 assert(ctx->bc->stack.push_wqm >= 0);
5724 break;
5725 case FC_LOOP:
5726 --ctx->bc->stack.loop;
5727 assert(ctx->bc->stack.loop >= 0);
5728 break;
5729 default:
5730 assert(0);
5731 break;
5732 }
5733 }
5734
5735 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5736 {
5737 switch (reason) {
5738 case FC_PUSH_VPM:
5739 ++ctx->bc->stack.push;
5740 break;
5741 case FC_PUSH_WQM:
5742 ++ctx->bc->stack.push_wqm;
5743 case FC_LOOP:
5744 ++ctx->bc->stack.loop;
5745 break;
5746 default:
5747 assert(0);
5748 }
5749
5750 callstack_update_max_depth(ctx, reason);
5751 }
5752
5753 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5754 {
5755 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5756
5757 sp->mid = realloc((void *)sp->mid,
5758 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5759 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5760 sp->num_mid++;
5761 }
5762
5763 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5764 {
5765 ctx->bc->fc_sp++;
5766 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5767 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5768 }
5769
5770 static void fc_poplevel(struct r600_shader_ctx *ctx)
5771 {
5772 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5773 free(sp->mid);
5774 sp->mid = NULL;
5775 sp->num_mid = 0;
5776 sp->start = NULL;
5777 sp->type = 0;
5778 ctx->bc->fc_sp--;
5779 }
5780
5781 #if 0
5782 static int emit_return(struct r600_shader_ctx *ctx)
5783 {
5784 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5785 return 0;
5786 }
5787
5788 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5789 {
5790
5791 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5792 ctx->bc->cf_last->pop_count = pops;
5793 /* XXX work out offset */
5794 return 0;
5795 }
5796
5797 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5798 {
5799 return 0;
5800 }
5801
5802 static void emit_testflag(struct r600_shader_ctx *ctx)
5803 {
5804
5805 }
5806
5807 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5808 {
5809 emit_testflag(ctx);
5810 emit_jump_to_offset(ctx, 1, 4);
5811 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5812 pops(ctx, ifidx + 1);
5813 emit_return(ctx);
5814 }
5815
5816 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5817 {
5818 emit_testflag(ctx);
5819
5820 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5821 ctx->bc->cf_last->pop_count = 1;
5822
5823 fc_set_mid(ctx, fc_sp);
5824
5825 pops(ctx, 1);
5826 }
5827 #endif
5828
5829 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
5830 {
5831 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5832
5833 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
5834 * LOOP_STARTxxx for nested loops may put the branch stack into a state
5835 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
5836 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
5837 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
5838 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
5839 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5840 alu_type = CF_OP_ALU;
5841 }
5842
5843 emit_logic_pred(ctx, opcode, alu_type);
5844
5845 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5846
5847 fc_pushlevel(ctx, FC_IF);
5848
5849 callstack_push(ctx, FC_PUSH_VPM);
5850 return 0;
5851 }
5852
5853 static int tgsi_if(struct r600_shader_ctx *ctx)
5854 {
5855 return emit_if(ctx, ALU_OP2_PRED_SETNE);
5856 }
5857
5858 static int tgsi_uif(struct r600_shader_ctx *ctx)
5859 {
5860 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
5861 }
5862
5863 static int tgsi_else(struct r600_shader_ctx *ctx)
5864 {
5865 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5866 ctx->bc->cf_last->pop_count = 1;
5867
5868 fc_set_mid(ctx, ctx->bc->fc_sp);
5869 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5870 return 0;
5871 }
5872
5873 static int tgsi_endif(struct r600_shader_ctx *ctx)
5874 {
5875 pops(ctx, 1);
5876 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5877 R600_ERR("if/endif unbalanced in shader\n");
5878 return -1;
5879 }
5880
5881 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5882 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5883 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5884 } else {
5885 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5886 }
5887 fc_poplevel(ctx);
5888
5889 callstack_pop(ctx, FC_PUSH_VPM);
5890 return 0;
5891 }
5892
5893 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5894 {
5895 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5896 * limited to 4096 iterations, like the other LOOP_* instructions. */
5897 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5898
5899 fc_pushlevel(ctx, FC_LOOP);
5900
5901 /* check stack depth */
5902 callstack_push(ctx, FC_LOOP);
5903 return 0;
5904 }
5905
5906 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5907 {
5908 int i;
5909
5910 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5911
5912 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5913 R600_ERR("loop/endloop in shader code are not paired.\n");
5914 return -EINVAL;
5915 }
5916
5917 /* fixup loop pointers - from r600isa
5918 LOOP END points to CF after LOOP START,
5919 LOOP START point to CF after LOOP END
5920 BRK/CONT point to LOOP END CF
5921 */
5922 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5923
5924 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5925
5926 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5927 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5928 }
5929 /* XXX add LOOPRET support */
5930 fc_poplevel(ctx);
5931 callstack_pop(ctx, FC_LOOP);
5932 return 0;
5933 }
5934
5935 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5936 {
5937 unsigned int fscp;
5938
5939 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5940 {
5941 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5942 break;
5943 }
5944
5945 if (fscp == 0) {
5946 R600_ERR("Break not inside loop/endloop pair\n");
5947 return -EINVAL;
5948 }
5949
5950 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5951
5952 fc_set_mid(ctx, fscp);
5953
5954 return 0;
5955 }
5956
5957 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
5958 {
5959 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
5960 emit_gs_ring_writes(ctx);
5961
5962 return r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5963 }
5964
5965 static int tgsi_umad(struct r600_shader_ctx *ctx)
5966 {
5967 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5968 struct r600_bytecode_alu alu;
5969 int i, j, k, r;
5970 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5971
5972 /* src0 * src1 */
5973 for (i = 0; i < lasti + 1; i++) {
5974 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5975 continue;
5976
5977 if (ctx->bc->chip_class == CAYMAN) {
5978 for (j = 0 ; j < 4; j++) {
5979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5980
5981 alu.op = ALU_OP2_MULLO_UINT;
5982 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
5983 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
5984 }
5985 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
5986 alu.dst.sel = ctx->temp_reg;
5987 alu.dst.write = (j == i);
5988 if (j == 3)
5989 alu.last = 1;
5990 r = r600_bytecode_add_alu(ctx->bc, &alu);
5991 if (r)
5992 return r;
5993 }
5994 } else {
5995 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5996
5997 alu.dst.chan = i;
5998 alu.dst.sel = ctx->temp_reg;
5999 alu.dst.write = 1;
6000
6001 alu.op = ALU_OP2_MULLO_UINT;
6002 for (j = 0; j < 2; j++) {
6003 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6004 }
6005
6006 alu.last = 1;
6007 r = r600_bytecode_add_alu(ctx->bc, &alu);
6008 if (r)
6009 return r;
6010 }
6011 }
6012
6013
6014 for (i = 0; i < lasti + 1; i++) {
6015 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6016 continue;
6017
6018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6019 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6020
6021 alu.op = ALU_OP2_ADD_INT;
6022
6023 alu.src[0].sel = ctx->temp_reg;
6024 alu.src[0].chan = i;
6025
6026 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6027 if (i == lasti) {
6028 alu.last = 1;
6029 }
6030 r = r600_bytecode_add_alu(ctx->bc, &alu);
6031 if (r)
6032 return r;
6033 }
6034 return 0;
6035 }
6036
6037 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
6038 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
6039 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6040 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6041
6042 /* XXX:
6043 * For state trackers other than OpenGL, we'll want to use
6044 * _RECIP_IEEE instead.
6045 */
6046 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
6047
6048 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
6049 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6050 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6051 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6052 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6053 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6054 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6055 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6056 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6057 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6058 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6059 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6060 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6061 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6062 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6063 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6064 /* gap */
6065 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6066 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6067 /* gap */
6068 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6069 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6070 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6071 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6072 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6073 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6074 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6075 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6076 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6077 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6078 /* gap */
6079 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6080 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6081 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6082 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6083 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6084 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6085 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6086 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6087 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6088 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6089 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6090 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6091 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6092 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6093 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6094 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6095 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6096 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6097 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6098 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6099 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6100 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6101 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6102 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6103 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6104 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6105 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6106 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6107 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6108 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
6109 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6110 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6111 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6112 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6113 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6114 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6115 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6116 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6117 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6118 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6119 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6120 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6121 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6122 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6123 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6124 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6125 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6126 /* gap */
6127 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6128 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6129 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6130 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6131 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6132 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6133 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6134 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6135 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
6136 /* gap */
6137 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6138 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6139 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6140 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6141 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6142 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6143 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6144 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6145 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6146 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6147 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6148 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6149 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6150 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6151 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6152 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6153 /* gap */
6154 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6155 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6156 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6157 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6158 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6159 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6160 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6161 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6162 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6163 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6164 /* gap */
6165 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6166 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6167 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6168 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6169 /* gap */
6170 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6171 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
6172 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6173 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6174 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6175 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6176 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6177 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
6178 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6179 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
6180 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6181 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6182 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6183 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6184 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6185 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6186 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6187 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6188 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6189 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6190 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
6191 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6192 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
6193 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6194 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6195 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6196 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6197 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6198 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6199 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6200 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6201 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6202 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6203 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6204 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6205 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6206 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6207 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6208 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6209 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
6210 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6211 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6212 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6213 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6214 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6215 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6216 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6217 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6218 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6219 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6220 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6221 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6222 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6223 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6224 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6225 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6226 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6227 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6228 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6229 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6230 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6231 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6232 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6233 };
6234
6235 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
6236 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6237 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6238 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6239 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
6240 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
6241 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6242 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6243 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6244 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6245 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6246 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6247 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6248 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6249 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6250 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6251 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6252 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6253 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6254 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6255 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6256 /* gap */
6257 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6258 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6259 /* gap */
6260 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6261 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6262 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6263 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6264 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6265 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6266 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6267 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6268 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6269 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6270 /* gap */
6271 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6272 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6273 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6274 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6275 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6276 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6277 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6278 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6279 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6280 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6281 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6282 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6283 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6284 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6285 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6286 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6287 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6288 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6289 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6290 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6291 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6292 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6293 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6294 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6295 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6296 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6297 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6298 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6299 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6300 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6301 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6302 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6303 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6304 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6305 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6306 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6307 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6308 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6309 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6310 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6311 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6312 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6313 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6314 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6315 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6316 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6317 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6318 /* gap */
6319 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6320 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6321 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6322 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6323 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6324 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6325 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6326 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6327 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6328 /* gap */
6329 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6330 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6331 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6332 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6333 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6334 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6335 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6336 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6337 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6338 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6339 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6340 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6341 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6342 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6343 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6344 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6345 /* gap */
6346 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6347 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6348 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6349 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6350 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6351 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6352 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6353 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6354 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6355 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6356 /* gap */
6357 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6358 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6359 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6360 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6361 /* gap */
6362 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6363 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
6364 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6365 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6366 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6367 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6368 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6369 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6370 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6371 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
6372 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6373 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6374 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6375 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6376 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6377 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6378 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6379 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6380 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6381 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6382 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6383 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6384 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6385 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6386 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6387 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6388 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6389 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6390 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6391 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6392 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6393 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6394 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6395 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6396 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6397 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6398 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6399 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6400 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6401 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6402 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6403 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6404 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6405 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6406 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6407 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6408 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6409 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6410 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6411 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6412 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6413 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6414 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6415 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6416 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6417 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6418 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6419 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6420 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6421 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6422 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6423 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6424 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6425 };
6426
6427 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6428 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6429 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6430 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6431 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6432 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6433 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6434 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6435 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6436 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6437 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6438 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6439 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6440 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6441 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6442 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6443 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6444 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6445 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6446 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6447 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6448 /* gap */
6449 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6450 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6451 /* gap */
6452 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6453 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6454 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6455 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6456 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6457 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6458 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6459 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6460 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6461 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6462 /* gap */
6463 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6464 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6465 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6466 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6467 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6468 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6469 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6470 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6471 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6472 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6473 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6474 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6475 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6476 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6477 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6478 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6479 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6480 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6481 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6482 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6483 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6484 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6485 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6486 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6487 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6488 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6489 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6490 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6491 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6492 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6493 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6494 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6495 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6496 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6497 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6498 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6499 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6500 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6501 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6502 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6503 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6504 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6505 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6506 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6507 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6508 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6509 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6510 /* gap */
6511 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6512 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6513 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6514 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6515 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6516 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6517 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6518 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6519 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6520 /* gap */
6521 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6522 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6523 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6524 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6525 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6526 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6527 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6528 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6529 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6530 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6531 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6532 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6533 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6534 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6535 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6536 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6537 /* gap */
6538 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6539 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6540 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6541 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6542 /* gap */
6543 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6544 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6545 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6546 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6547 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6548 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6549 /* gap */
6550 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6551 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6552 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6553 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6554 /* gap */
6555 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6556 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6557 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6558 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6559 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6560 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6561 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6562 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6563 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6564 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6565 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6566 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6567 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6568 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6569 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6570 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6571 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6572 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6573 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6574 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6575 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6576 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6577 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6578 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6579 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6580 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6581 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6582 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6583 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6584 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6585 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6586 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6587 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6588 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6589 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6590 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6591 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6592 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6593 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6594 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6595 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6596 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6597 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6598 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6599 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6600 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6601 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6602 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6603 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6604 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6605 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6606 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6607 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6608 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6609 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6610 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6611 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6612 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6613 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6614 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6615 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6616 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6617 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6618 };