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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 for (i = 0; i < 10; i++) {
48 spi_vs_out_id[i] = 0;
49 }
50 for (i = 0; i < 32; i++) {
51 tmp = i << ((i & 3) * 8);
52 spi_vs_out_id[i / 4] |= tmp;
53 }
54 for (i = 0; i < 10; i++) {
55 r600_pipe_state_add_reg(rstate,
56 R_028614_SPI_VS_OUT_ID_0 + i * 4,
57 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
58 }
59
60 r600_pipe_state_add_reg(rstate,
61 R_0286C4_SPI_VS_OUT_CONFIG,
62 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
63 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate,
65 R_028868_SQ_PGM_RESOURCES_VS,
66 S_028868_NUM_GPRS(rshader->bc.ngpr) |
67 S_028868_STACK_SIZE(rshader->bc.nstack),
68 0xFFFFFFFF, NULL);
69 r600_pipe_state_add_reg(rstate,
70 R_0288A4_SQ_PGM_RESOURCES_FS,
71 0x00000000, 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS,
77 0x00000000, 0xFFFFFFFF, NULL);
78 r600_pipe_state_add_reg(rstate,
79 R_028858_SQ_PGM_START_VS,
80 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
81 r600_pipe_state_add_reg(rstate,
82 R_028894_SQ_PGM_START_FS,
83 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
84
85 r600_pipe_state_add_reg(rstate,
86 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
87 0xFFFFFFFF, NULL);
88
89 }
90
91 int r600_find_vs_semantic_index(struct r600_shader *vs,
92 struct r600_shader *ps, int id)
93 {
94 struct r600_shader_io *input = &ps->input[id];
95
96 for (int i = 0; i < vs->noutput; i++) {
97 if (input->name == vs->output[i].name &&
98 input->sid == vs->output[i].sid) {
99 return i - 1;
100 }
101 }
102 return 0;
103 }
104
105 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
106 {
107 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
108 struct r600_pipe_state *rstate = &shader->rstate;
109 struct r600_shader *rshader = &shader->shader;
110 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
111 int pos_index = -1, face_index = -1;
112
113 /* clear previous register */
114 rstate->nregs = 0;
115
116 for (i = 0; i < rshader->ninput; i++) {
117 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
118 if (rshader->input[i].centroid)
119 tmp |= S_028644_SEL_CENTROID(1);
120 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
121 tmp |= S_028644_SEL_LINEAR(1);
122
123 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
124 pos_index = i;
125 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
126 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
127 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
128 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
129 }
130 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
131 face_index = i;
132 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
133 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
134 tmp |= S_028644_PT_SPRITE_TEX(1);
135 }
136 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
137 }
138 for (i = 0; i < rshader->noutput; i++) {
139 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
140 r600_pipe_state_add_reg(rstate,
141 R_02880C_DB_SHADER_CONTROL,
142 S_02880C_Z_EXPORT_ENABLE(1),
143 S_02880C_Z_EXPORT_ENABLE(1), NULL);
144 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
145 r600_pipe_state_add_reg(rstate,
146 R_02880C_DB_SHADER_CONTROL,
147 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
148 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
149 }
150
151 exports_ps = 0;
152 num_cout = 0;
153 for (i = 0; i < rshader->noutput; i++) {
154 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
155 exports_ps |= 1;
156 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
157 num_cout++;
158 }
159 }
160 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
161 if (!exports_ps) {
162 /* always at least export 1 component per pixel */
163 exports_ps = 2;
164 }
165
166 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
167 S_0286CC_PERSP_GRADIENT_ENA(1);
168 spi_input_z = 0;
169 if (pos_index != -1) {
170 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
171 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
172 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
173 S_0286CC_BARYC_SAMPLE_CNTL(1));
174 spi_input_z |= 1;
175 }
176
177 spi_ps_in_control_1 = 0;
178 if (face_index != -1) {
179 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
180 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
181 }
182
183 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
184 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
185 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
186 r600_pipe_state_add_reg(rstate,
187 R_028840_SQ_PGM_START_PS,
188 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
189 r600_pipe_state_add_reg(rstate,
190 R_028850_SQ_PGM_RESOURCES_PS,
191 S_028868_NUM_GPRS(rshader->bc.ngpr) |
192 S_028868_STACK_SIZE(rshader->bc.nstack),
193 0xFFFFFFFF, NULL);
194 r600_pipe_state_add_reg(rstate,
195 R_028854_SQ_PGM_EXPORTS_PS,
196 exports_ps, 0xFFFFFFFF, NULL);
197 r600_pipe_state_add_reg(rstate,
198 R_0288CC_SQ_PGM_CF_OFFSET_PS,
199 0x00000000, 0xFFFFFFFF, NULL);
200
201 if (rshader->uses_kill) {
202 /* only set some bits here, the other bits are set in the dsa state */
203 r600_pipe_state_add_reg(rstate,
204 R_02880C_DB_SHADER_CONTROL,
205 S_02880C_KILL_ENABLE(1),
206 S_02880C_KILL_ENABLE(1), NULL);
207 }
208 r600_pipe_state_add_reg(rstate,
209 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
210 0xFFFFFFFF, NULL);
211 }
212
213 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
214 {
215 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
216 struct r600_shader *rshader = &shader->shader;
217 void *ptr;
218
219 /* copy new shader */
220 if (shader->bo == NULL) {
221 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
222 if (shader->bo == NULL) {
223 return -ENOMEM;
224 }
225 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
226 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
227 r600_bo_unmap(rctx->radeon, shader->bo);
228 }
229 /* build state */
230 rshader->flat_shade = rctx->flatshade;
231 switch (rshader->processor_type) {
232 case TGSI_PROCESSOR_VERTEX:
233 if (rshader->family >= CHIP_CEDAR) {
234 evergreen_pipe_shader_vs(ctx, shader);
235 } else {
236 r600_pipe_shader_vs(ctx, shader);
237 }
238 break;
239 case TGSI_PROCESSOR_FRAGMENT:
240 if (rshader->family >= CHIP_CEDAR) {
241 evergreen_pipe_shader_ps(ctx, shader);
242 } else {
243 r600_pipe_shader_ps(ctx, shader);
244 }
245 break;
246 default:
247 return -EINVAL;
248 }
249 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
250 return 0;
251 }
252
253 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
254 {
255 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
256 struct r600_shader *shader = &rshader->shader;
257 const struct util_format_description *desc;
258 enum pipe_format resource_format[160];
259 unsigned i, nresources = 0;
260 struct r600_bc *bc = &shader->bc;
261 struct r600_bc_cf *cf;
262 struct r600_bc_vtx *vtx;
263
264 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
265 return 0;
266 /* doing a full memcmp fell over the refcount */
267 if ((rshader->vertex_elements.count == rctx->vertex_elements->count) &&
268 (!memcmp(&rshader->vertex_elements.elements, &rctx->vertex_elements->elements, 32 * sizeof(struct pipe_vertex_element)))) {
269 return 0;
270 }
271 rshader->vertex_elements = *rctx->vertex_elements;
272 for (i = 0; i < rctx->vertex_elements->count; i++) {
273 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
274 }
275 r600_bo_reference(rctx->radeon, &rshader->bo, NULL);
276 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
277 switch (cf->inst) {
278 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
279 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
280 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
281 desc = util_format_description(resource_format[vtx->buffer_id]);
282 if (desc == NULL) {
283 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
284 return -EINVAL;
285 }
286 vtx->dst_sel_x = desc->swizzle[0];
287 vtx->dst_sel_y = desc->swizzle[1];
288 vtx->dst_sel_z = desc->swizzle[2];
289 vtx->dst_sel_w = desc->swizzle[3];
290 }
291 break;
292 default:
293 break;
294 }
295 }
296 return r600_bc_build(&shader->bc);
297 }
298
299 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
300 {
301 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
302 int r;
303
304 if (shader == NULL)
305 return -EINVAL;
306 /* there should be enough input */
307 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
308 R600_ERR("%d resources provided, expecting %d\n",
309 rctx->vertex_elements->count, shader->shader.bc.nresource);
310 return -EINVAL;
311 }
312 r = r600_shader_update(ctx, shader);
313 if (r)
314 return r;
315 return r600_pipe_shader(ctx, shader);
316 }
317
318 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
319 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
320 {
321 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
322 int r;
323
324 //fprintf(stderr, "--------------------------------------------------------------\n");
325 //tgsi_dump(tokens, 0);
326 shader->shader.family = r600_get_family(rctx->radeon);
327 r = r600_shader_from_tgsi(tokens, &shader->shader);
328 if (r) {
329 R600_ERR("translation from TGSI failed !\n");
330 return r;
331 }
332 r = r600_bc_build(&shader->shader.bc);
333 if (r) {
334 R600_ERR("building bytecode failed !\n");
335 return r;
336 }
337 //fprintf(stderr, "______________________________________________________________\n");
338 return 0;
339 }
340
341 /*
342 * tgsi -> r600 shader
343 */
344 struct r600_shader_tgsi_instruction;
345
346 struct r600_shader_ctx {
347 struct tgsi_shader_info info;
348 struct tgsi_parse_context parse;
349 const struct tgsi_token *tokens;
350 unsigned type;
351 unsigned file_offset[TGSI_FILE_COUNT];
352 unsigned temp_reg;
353 struct r600_shader_tgsi_instruction *inst_info;
354 struct r600_bc *bc;
355 struct r600_shader *shader;
356 u32 value[4];
357 u32 *literals;
358 u32 nliterals;
359 u32 max_driver_temp_used;
360 /* needed for evergreen interpolation */
361 boolean input_centroid;
362 boolean input_linear;
363 boolean input_perspective;
364 int num_interp_gpr;
365 };
366
367 struct r600_shader_tgsi_instruction {
368 unsigned tgsi_opcode;
369 unsigned is_op3;
370 unsigned r600_opcode;
371 int (*process)(struct r600_shader_ctx *ctx);
372 };
373
374 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
375 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
376
377 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
378 {
379 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
380 int j;
381
382 if (i->Instruction.NumDstRegs > 1) {
383 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
384 return -EINVAL;
385 }
386 if (i->Instruction.Predicate) {
387 R600_ERR("predicate unsupported\n");
388 return -EINVAL;
389 }
390 #if 0
391 if (i->Instruction.Label) {
392 R600_ERR("label unsupported\n");
393 return -EINVAL;
394 }
395 #endif
396 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
397 if (i->Src[j].Register.Dimension) {
398 R600_ERR("unsupported src %d (dimension %d)\n", j,
399 i->Src[j].Register.Dimension);
400 return -EINVAL;
401 }
402 }
403 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
404 if (i->Dst[j].Register.Dimension) {
405 R600_ERR("unsupported dst (dimension)\n");
406 return -EINVAL;
407 }
408 }
409 return 0;
410 }
411
412 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
413 {
414 int i, r;
415 struct r600_bc_alu alu;
416 int gpr = 0, base_chan = 0;
417 int ij_index = 0;
418
419 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
420 ij_index = 0;
421 if (ctx->shader->input[input].centroid)
422 ij_index++;
423 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
424 ij_index = 0;
425 /* if we have perspective add one */
426 if (ctx->input_perspective) {
427 ij_index++;
428 /* if we have perspective centroid */
429 if (ctx->input_centroid)
430 ij_index++;
431 }
432 if (ctx->shader->input[input].centroid)
433 ij_index++;
434 }
435
436 /* work out gpr and base_chan from index */
437 gpr = ij_index / 2;
438 base_chan = (2 * (ij_index % 2)) + 1;
439
440 for (i = 0; i < 8; i++) {
441 memset(&alu, 0, sizeof(struct r600_bc_alu));
442
443 if (i < 4)
444 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
445 else
446 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
447
448 if ((i > 1) && (i < 6)) {
449 alu.dst.sel = ctx->shader->input[input].gpr;
450 alu.dst.write = 1;
451 }
452
453 alu.dst.chan = i % 4;
454
455 alu.src[0].sel = gpr;
456 alu.src[0].chan = (base_chan - (i % 2));
457
458 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
459
460 alu.bank_swizzle_force = SQ_ALU_VEC_210;
461 if ((i % 4) == 3)
462 alu.last = 1;
463 r = r600_bc_add_alu(ctx->bc, &alu);
464 if (r)
465 return r;
466 }
467 return 0;
468 }
469
470
471 static int tgsi_declaration(struct r600_shader_ctx *ctx)
472 {
473 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
474 struct r600_bc_vtx vtx;
475 unsigned i;
476 int r;
477
478 switch (d->Declaration.File) {
479 case TGSI_FILE_INPUT:
480 i = ctx->shader->ninput++;
481 ctx->shader->input[i].name = d->Semantic.Name;
482 ctx->shader->input[i].sid = d->Semantic.Index;
483 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
484 ctx->shader->input[i].centroid = d->Declaration.Centroid;
485 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
486 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
487 /* turn input into fetch */
488 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
489 vtx.inst = 0;
490 vtx.fetch_type = 0;
491 vtx.buffer_id = i;
492 /* register containing the index into the buffer */
493 vtx.src_gpr = 0;
494 vtx.src_sel_x = 0;
495 vtx.mega_fetch_count = 0x1F;
496 vtx.dst_gpr = ctx->shader->input[i].gpr;
497 vtx.dst_sel_x = 0;
498 vtx.dst_sel_y = 1;
499 vtx.dst_sel_z = 2;
500 vtx.dst_sel_w = 3;
501 vtx.use_const_fields = 1;
502 r = r600_bc_add_vtx(ctx->bc, &vtx);
503 if (r)
504 return r;
505 }
506 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
507 /* turn input into interpolate on EG */
508 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
509 if (ctx->shader->input[i].interpolate > 0) {
510 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
511 evergreen_interp_alu(ctx, i);
512 }
513 }
514 }
515 break;
516 case TGSI_FILE_OUTPUT:
517 i = ctx->shader->noutput++;
518 ctx->shader->output[i].name = d->Semantic.Name;
519 ctx->shader->output[i].sid = d->Semantic.Index;
520 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
521 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
522 break;
523 case TGSI_FILE_CONSTANT:
524 case TGSI_FILE_TEMPORARY:
525 case TGSI_FILE_SAMPLER:
526 case TGSI_FILE_ADDRESS:
527 break;
528 default:
529 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
530 return -EINVAL;
531 }
532 return 0;
533 }
534
535 static int r600_get_temp(struct r600_shader_ctx *ctx)
536 {
537 return ctx->temp_reg + ctx->max_driver_temp_used++;
538 }
539
540 /*
541 * for evergreen we need to scan the shader to find the number of GPRs we need to
542 * reserve for interpolation.
543 *
544 * we need to know if we are going to emit
545 * any centroid inputs
546 * if perspective and linear are required
547 */
548 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
549 {
550 int i;
551 int num_baryc;
552
553 ctx->input_linear = FALSE;
554 ctx->input_perspective = FALSE;
555 ctx->input_centroid = FALSE;
556 ctx->num_interp_gpr = 1;
557
558 /* any centroid inputs */
559 for (i = 0; i < ctx->info.num_inputs; i++) {
560 /* skip position/face */
561 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
562 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
563 continue;
564 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
565 ctx->input_linear = TRUE;
566 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
567 ctx->input_perspective = TRUE;
568 if (ctx->info.input_centroid[i])
569 ctx->input_centroid = TRUE;
570 }
571
572 num_baryc = 0;
573 /* ignoring sample for now */
574 if (ctx->input_perspective)
575 num_baryc++;
576 if (ctx->input_linear)
577 num_baryc++;
578 if (ctx->input_centroid)
579 num_baryc *= 2;
580
581 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
582
583 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
584 return ctx->num_interp_gpr;
585 }
586
587 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
588 {
589 struct tgsi_full_immediate *immediate;
590 struct r600_shader_ctx ctx;
591 struct r600_bc_output output[32];
592 unsigned output_done, noutput;
593 unsigned opcode;
594 int i, r = 0, pos0;
595
596 ctx.bc = &shader->bc;
597 ctx.shader = shader;
598 r = r600_bc_init(ctx.bc, shader->family);
599 if (r)
600 return r;
601 ctx.tokens = tokens;
602 tgsi_scan_shader(tokens, &ctx.info);
603 tgsi_parse_init(&ctx.parse, tokens);
604 ctx.type = ctx.parse.FullHeader.Processor.Processor;
605 shader->processor_type = ctx.type;
606
607 /* register allocations */
608 /* Values [0,127] correspond to GPR[0..127].
609 * Values [128,159] correspond to constant buffer bank 0
610 * Values [160,191] correspond to constant buffer bank 1
611 * Values [256,511] correspond to cfile constants c[0..255].
612 * Other special values are shown in the list below.
613 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
614 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
615 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
616 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
617 * 248 SQ_ALU_SRC_0: special constant 0.0.
618 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
619 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
620 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
621 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
622 * 253 SQ_ALU_SRC_LITERAL: literal constant.
623 * 254 SQ_ALU_SRC_PV: previous vector result.
624 * 255 SQ_ALU_SRC_PS: previous scalar result.
625 */
626 for (i = 0; i < TGSI_FILE_COUNT; i++) {
627 ctx.file_offset[i] = 0;
628 }
629 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
630 ctx.file_offset[TGSI_FILE_INPUT] = 1;
631 }
632 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == 2) {
633 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
634 }
635 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
636 ctx.info.file_count[TGSI_FILE_INPUT];
637 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
638 ctx.info.file_count[TGSI_FILE_OUTPUT];
639
640 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
641
642 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
643 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
644 ctx.info.file_count[TGSI_FILE_TEMPORARY];
645
646 ctx.nliterals = 0;
647 ctx.literals = NULL;
648
649 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
650 tgsi_parse_token(&ctx.parse);
651 switch (ctx.parse.FullToken.Token.Type) {
652 case TGSI_TOKEN_TYPE_IMMEDIATE:
653 immediate = &ctx.parse.FullToken.FullImmediate;
654 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
655 if(ctx.literals == NULL) {
656 r = -ENOMEM;
657 goto out_err;
658 }
659 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
660 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
661 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
662 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
663 ctx.nliterals++;
664 break;
665 case TGSI_TOKEN_TYPE_DECLARATION:
666 r = tgsi_declaration(&ctx);
667 if (r)
668 goto out_err;
669 break;
670 case TGSI_TOKEN_TYPE_INSTRUCTION:
671 r = tgsi_is_supported(&ctx);
672 if (r)
673 goto out_err;
674 ctx.max_driver_temp_used = 0;
675 /* reserve first tmp for everyone */
676 r600_get_temp(&ctx);
677 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
678 if (ctx.bc->chiprev == 2)
679 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
680 else
681 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
682 r = ctx.inst_info->process(&ctx);
683 if (r)
684 goto out_err;
685 r = r600_bc_add_literal(ctx.bc, ctx.value);
686 if (r)
687 goto out_err;
688 break;
689 default:
690 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
691 r = -EINVAL;
692 goto out_err;
693 }
694 }
695 /* export output */
696 noutput = shader->noutput;
697 for (i = 0, pos0 = 0; i < noutput; i++) {
698 memset(&output[i], 0, sizeof(struct r600_bc_output));
699 output[i].gpr = shader->output[i].gpr;
700 output[i].elem_size = 3;
701 output[i].swizzle_x = 0;
702 output[i].swizzle_y = 1;
703 output[i].swizzle_z = 2;
704 output[i].swizzle_w = 3;
705 output[i].barrier = 1;
706 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
707 output[i].array_base = i - pos0;
708 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
709 switch (ctx.type) {
710 case TGSI_PROCESSOR_VERTEX:
711 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
712 output[i].array_base = 60;
713 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
714 /* position doesn't count in array_base */
715 pos0++;
716 }
717 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
718 output[i].array_base = 61;
719 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
720 /* position doesn't count in array_base */
721 pos0++;
722 }
723 break;
724 case TGSI_PROCESSOR_FRAGMENT:
725 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
726 output[i].array_base = shader->output[i].sid;
727 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
728 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
729 output[i].array_base = 61;
730 output[i].swizzle_x = 2;
731 output[i].swizzle_y = 7;
732 output[i].swizzle_z = output[i].swizzle_w = 7;
733 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
734 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
735 output[i].array_base = 61;
736 output[i].swizzle_x = 7;
737 output[i].swizzle_y = 1;
738 output[i].swizzle_z = output[i].swizzle_w = 7;
739 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
740 } else {
741 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
742 r = -EINVAL;
743 goto out_err;
744 }
745 break;
746 default:
747 R600_ERR("unsupported processor type %d\n", ctx.type);
748 r = -EINVAL;
749 goto out_err;
750 }
751 }
752 /* add fake param output for vertex shader if no param is exported */
753 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
754 for (i = 0, pos0 = 0; i < noutput; i++) {
755 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
756 pos0 = 1;
757 break;
758 }
759 }
760 if (!pos0) {
761 memset(&output[i], 0, sizeof(struct r600_bc_output));
762 output[i].gpr = 0;
763 output[i].elem_size = 3;
764 output[i].swizzle_x = 0;
765 output[i].swizzle_y = 1;
766 output[i].swizzle_z = 2;
767 output[i].swizzle_w = 3;
768 output[i].barrier = 1;
769 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
770 output[i].array_base = 0;
771 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
772 noutput++;
773 }
774 }
775 /* add fake pixel export */
776 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
777 memset(&output[0], 0, sizeof(struct r600_bc_output));
778 output[0].gpr = 0;
779 output[0].elem_size = 3;
780 output[0].swizzle_x = 7;
781 output[0].swizzle_y = 7;
782 output[0].swizzle_z = 7;
783 output[0].swizzle_w = 7;
784 output[0].barrier = 1;
785 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
786 output[0].array_base = 0;
787 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
788 noutput++;
789 }
790 /* set export done on last export of each type */
791 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
792 if (i == (noutput - 1)) {
793 output[i].end_of_program = 1;
794 }
795 if (!(output_done & (1 << output[i].type))) {
796 output_done |= (1 << output[i].type);
797 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
798 }
799 }
800 /* add output to bytecode */
801 for (i = 0; i < noutput; i++) {
802 r = r600_bc_add_output(ctx.bc, &output[i]);
803 if (r)
804 goto out_err;
805 }
806 free(ctx.literals);
807 tgsi_parse_free(&ctx.parse);
808 return 0;
809 out_err:
810 free(ctx.literals);
811 tgsi_parse_free(&ctx.parse);
812 return r;
813 }
814
815 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
816 {
817 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
818 return -EINVAL;
819 }
820
821 static int tgsi_end(struct r600_shader_ctx *ctx)
822 {
823 return 0;
824 }
825
826 static int tgsi_src(struct r600_shader_ctx *ctx,
827 const struct tgsi_full_src_register *tgsi_src,
828 struct r600_bc_alu_src *r600_src)
829 {
830 int index;
831 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
832 r600_src->sel = tgsi_src->Register.Index;
833 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
834 r600_src->sel = 0;
835 index = tgsi_src->Register.Index;
836 ctx->value[0] = ctx->literals[index * 4 + 0];
837 ctx->value[1] = ctx->literals[index * 4 + 1];
838 ctx->value[2] = ctx->literals[index * 4 + 2];
839 ctx->value[3] = ctx->literals[index * 4 + 3];
840 }
841 if (tgsi_src->Register.Indirect)
842 r600_src->rel = V_SQ_REL_RELATIVE;
843 r600_src->neg = tgsi_src->Register.Negate;
844 r600_src->abs = tgsi_src->Register.Absolute;
845 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
846 return 0;
847 }
848
849 static int tgsi_dst(struct r600_shader_ctx *ctx,
850 const struct tgsi_full_dst_register *tgsi_dst,
851 unsigned swizzle,
852 struct r600_bc_alu_dst *r600_dst)
853 {
854 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
855
856 r600_dst->sel = tgsi_dst->Register.Index;
857 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
858 r600_dst->chan = swizzle;
859 r600_dst->write = 1;
860 if (tgsi_dst->Register.Indirect)
861 r600_dst->rel = V_SQ_REL_RELATIVE;
862 if (inst->Instruction.Saturate) {
863 r600_dst->clamp = 1;
864 }
865 return 0;
866 }
867
868 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
869 {
870 switch (swizzle) {
871 case 0:
872 return tgsi_src->Register.SwizzleX;
873 case 1:
874 return tgsi_src->Register.SwizzleY;
875 case 2:
876 return tgsi_src->Register.SwizzleZ;
877 case 3:
878 return tgsi_src->Register.SwizzleW;
879 default:
880 return 0;
881 }
882 }
883
884 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
885 {
886 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
887 struct r600_bc_alu alu;
888 int i, j, k, nconst, r;
889
890 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
891 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
892 nconst++;
893 }
894 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
895 if (r) {
896 return r;
897 }
898 }
899 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
900 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
901 int treg = r600_get_temp(ctx);
902 for (k = 0; k < 4; k++) {
903 memset(&alu, 0, sizeof(struct r600_bc_alu));
904 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
905 alu.src[0].sel = r600_src[i].sel;
906 alu.src[0].chan = k;
907 alu.src[0].rel = r600_src[i].rel;
908 alu.dst.sel = treg;
909 alu.dst.chan = k;
910 alu.dst.write = 1;
911 if (k == 3)
912 alu.last = 1;
913 r = r600_bc_add_alu(ctx->bc, &alu);
914 if (r)
915 return r;
916 }
917 r600_src[i].sel = treg;
918 r600_src[i].rel =0;
919 j--;
920 }
921 }
922 return 0;
923 }
924
925 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
926 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
927 {
928 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
929 struct r600_bc_alu alu;
930 int i, j, k, nliteral, r;
931
932 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
933 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
934 nliteral++;
935 }
936 }
937 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
938 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
939 int treg = r600_get_temp(ctx);
940 for (k = 0; k < 4; k++) {
941 memset(&alu, 0, sizeof(struct r600_bc_alu));
942 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
943 alu.src[0].sel = r600_src[i].sel;
944 alu.src[0].chan = k;
945 alu.dst.sel = treg;
946 alu.dst.chan = k;
947 alu.dst.write = 1;
948 if (k == 3)
949 alu.last = 1;
950 r = r600_bc_add_alu(ctx->bc, &alu);
951 if (r)
952 return r;
953 }
954 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
955 if (r)
956 return r;
957 r600_src[i].sel = treg;
958 j--;
959 }
960 }
961 return 0;
962 }
963
964 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
965 {
966 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
967 struct r600_bc_alu_src r600_src[3];
968 struct r600_bc_alu alu;
969 int i, j, r;
970 int lasti = 0;
971
972 for (i = 0; i < 4; i++) {
973 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
974 lasti = i;
975 }
976 }
977
978 r = tgsi_split_constant(ctx, r600_src);
979 if (r)
980 return r;
981 r = tgsi_split_literal_constant(ctx, r600_src);
982 if (r)
983 return r;
984 for (i = 0; i < lasti + 1; i++) {
985 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
986 continue;
987
988 memset(&alu, 0, sizeof(struct r600_bc_alu));
989 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
990 if (r)
991 return r;
992
993 alu.inst = ctx->inst_info->r600_opcode;
994 if (!swap) {
995 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
996 alu.src[j] = r600_src[j];
997 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
998 }
999 } else {
1000 alu.src[0] = r600_src[1];
1001 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
1002
1003 alu.src[1] = r600_src[0];
1004 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1005 }
1006 /* handle some special cases */
1007 switch (ctx->inst_info->tgsi_opcode) {
1008 case TGSI_OPCODE_SUB:
1009 alu.src[1].neg = 1;
1010 break;
1011 case TGSI_OPCODE_ABS:
1012 alu.src[0].abs = 1;
1013 break;
1014 default:
1015 break;
1016 }
1017 if (i == lasti) {
1018 alu.last = 1;
1019 }
1020 r = r600_bc_add_alu(ctx->bc, &alu);
1021 if (r)
1022 return r;
1023 }
1024 return 0;
1025 }
1026
1027 static int tgsi_op2(struct r600_shader_ctx *ctx)
1028 {
1029 return tgsi_op2_s(ctx, 0);
1030 }
1031
1032 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1033 {
1034 return tgsi_op2_s(ctx, 1);
1035 }
1036
1037 /*
1038 * r600 - trunc to -PI..PI range
1039 * r700 - normalize by dividing by 2PI
1040 * see fdo bug 27901
1041 */
1042 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
1043 struct r600_bc_alu_src r600_src[3])
1044 {
1045 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1046 int r;
1047 uint32_t lit_vals[4];
1048 struct r600_bc_alu alu;
1049
1050 memset(lit_vals, 0, 4*4);
1051 r = tgsi_split_constant(ctx, r600_src);
1052 if (r)
1053 return r;
1054 r = tgsi_split_literal_constant(ctx, r600_src);
1055 if (r)
1056 return r;
1057
1058 r = tgsi_split_literal_constant(ctx, r600_src);
1059 if (r)
1060 return r;
1061
1062 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
1063 lit_vals[1] = fui(0.5f);
1064
1065 memset(&alu, 0, sizeof(struct r600_bc_alu));
1066 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1067 alu.is_op3 = 1;
1068
1069 alu.dst.chan = 0;
1070 alu.dst.sel = ctx->temp_reg;
1071 alu.dst.write = 1;
1072
1073 alu.src[0] = r600_src[0];
1074 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1075
1076 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1077 alu.src[1].chan = 0;
1078 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1079 alu.src[2].chan = 1;
1080 alu.last = 1;
1081 r = r600_bc_add_alu(ctx->bc, &alu);
1082 if (r)
1083 return r;
1084 r = r600_bc_add_literal(ctx->bc, lit_vals);
1085 if (r)
1086 return r;
1087
1088 memset(&alu, 0, sizeof(struct r600_bc_alu));
1089 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1090
1091 alu.dst.chan = 0;
1092 alu.dst.sel = ctx->temp_reg;
1093 alu.dst.write = 1;
1094
1095 alu.src[0].sel = ctx->temp_reg;
1096 alu.src[0].chan = 0;
1097 alu.last = 1;
1098 r = r600_bc_add_alu(ctx->bc, &alu);
1099 if (r)
1100 return r;
1101
1102 if (ctx->bc->chiprev == 0) {
1103 lit_vals[0] = fui(3.1415926535897f * 2.0f);
1104 lit_vals[1] = fui(-3.1415926535897f);
1105 } else {
1106 lit_vals[0] = fui(1.0f);
1107 lit_vals[1] = fui(-0.5f);
1108 }
1109
1110 memset(&alu, 0, sizeof(struct r600_bc_alu));
1111 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1112 alu.is_op3 = 1;
1113
1114 alu.dst.chan = 0;
1115 alu.dst.sel = ctx->temp_reg;
1116 alu.dst.write = 1;
1117
1118 alu.src[0].sel = ctx->temp_reg;
1119 alu.src[0].chan = 0;
1120
1121 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1122 alu.src[1].chan = 0;
1123 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1124 alu.src[2].chan = 1;
1125 alu.last = 1;
1126 r = r600_bc_add_alu(ctx->bc, &alu);
1127 if (r)
1128 return r;
1129 r = r600_bc_add_literal(ctx->bc, lit_vals);
1130 if (r)
1131 return r;
1132 return 0;
1133 }
1134
1135 static int tgsi_trig(struct r600_shader_ctx *ctx)
1136 {
1137 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1138 struct r600_bc_alu_src r600_src[3];
1139 struct r600_bc_alu alu;
1140 int i, r;
1141 int lasti = 0;
1142
1143 r = tgsi_setup_trig(ctx, r600_src);
1144 if (r)
1145 return r;
1146
1147 memset(&alu, 0, sizeof(struct r600_bc_alu));
1148 alu.inst = ctx->inst_info->r600_opcode;
1149 alu.dst.chan = 0;
1150 alu.dst.sel = ctx->temp_reg;
1151 alu.dst.write = 1;
1152
1153 alu.src[0].sel = ctx->temp_reg;
1154 alu.src[0].chan = 0;
1155 alu.last = 1;
1156 r = r600_bc_add_alu(ctx->bc, &alu);
1157 if (r)
1158 return r;
1159
1160 /* replicate result */
1161 for (i = 0; i < 4; i++) {
1162 if (inst->Dst[0].Register.WriteMask & (1 << i))
1163 lasti = i;
1164 }
1165 for (i = 0; i < lasti + 1; i++) {
1166 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1167 continue;
1168
1169 memset(&alu, 0, sizeof(struct r600_bc_alu));
1170 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1171
1172 alu.src[0].sel = ctx->temp_reg;
1173 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1174 if (r)
1175 return r;
1176 if (i == lasti)
1177 alu.last = 1;
1178 r = r600_bc_add_alu(ctx->bc, &alu);
1179 if (r)
1180 return r;
1181 }
1182 return 0;
1183 }
1184
1185 static int tgsi_scs(struct r600_shader_ctx *ctx)
1186 {
1187 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1188 struct r600_bc_alu_src r600_src[3];
1189 struct r600_bc_alu alu;
1190 int r;
1191
1192 /* We'll only need the trig stuff if we are going to write to the
1193 * X or Y components of the destination vector.
1194 */
1195 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1196 r = tgsi_setup_trig(ctx, r600_src);
1197 if (r)
1198 return r;
1199 }
1200
1201 /* dst.x = COS */
1202 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1203 memset(&alu, 0, sizeof(struct r600_bc_alu));
1204 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1205 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1206 if (r)
1207 return r;
1208
1209 alu.src[0].sel = ctx->temp_reg;
1210 alu.src[0].chan = 0;
1211 alu.last = 1;
1212 r = r600_bc_add_alu(ctx->bc, &alu);
1213 if (r)
1214 return r;
1215 }
1216
1217 /* dst.y = SIN */
1218 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1219 memset(&alu, 0, sizeof(struct r600_bc_alu));
1220 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1221 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1222 if (r)
1223 return r;
1224
1225 alu.src[0].sel = ctx->temp_reg;
1226 alu.src[0].chan = 0;
1227 alu.last = 1;
1228 r = r600_bc_add_alu(ctx->bc, &alu);
1229 if (r)
1230 return r;
1231 }
1232
1233 /* dst.z = 0.0; */
1234 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1235 memset(&alu, 0, sizeof(struct r600_bc_alu));
1236
1237 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1238
1239 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1240 if (r)
1241 return r;
1242
1243 alu.src[0].sel = V_SQ_ALU_SRC_0;
1244 alu.src[0].chan = 0;
1245
1246 alu.last = 1;
1247
1248 r = r600_bc_add_alu(ctx->bc, &alu);
1249 if (r)
1250 return r;
1251
1252 r = r600_bc_add_literal(ctx->bc, ctx->value);
1253 if (r)
1254 return r;
1255 }
1256
1257 /* dst.w = 1.0; */
1258 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1259 memset(&alu, 0, sizeof(struct r600_bc_alu));
1260
1261 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1262
1263 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1264 if (r)
1265 return r;
1266
1267 alu.src[0].sel = V_SQ_ALU_SRC_1;
1268 alu.src[0].chan = 0;
1269
1270 alu.last = 1;
1271
1272 r = r600_bc_add_alu(ctx->bc, &alu);
1273 if (r)
1274 return r;
1275
1276 r = r600_bc_add_literal(ctx->bc, ctx->value);
1277 if (r)
1278 return r;
1279 }
1280
1281 return 0;
1282 }
1283
1284 static int tgsi_kill(struct r600_shader_ctx *ctx)
1285 {
1286 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1287 struct r600_bc_alu alu;
1288 int i, r;
1289
1290 for (i = 0; i < 4; i++) {
1291 memset(&alu, 0, sizeof(struct r600_bc_alu));
1292 alu.inst = ctx->inst_info->r600_opcode;
1293
1294 alu.dst.chan = i;
1295
1296 alu.src[0].sel = V_SQ_ALU_SRC_0;
1297
1298 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1299 alu.src[1].sel = V_SQ_ALU_SRC_1;
1300 alu.src[1].neg = 1;
1301 } else {
1302 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1303 if (r)
1304 return r;
1305 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1306 }
1307 if (i == 3) {
1308 alu.last = 1;
1309 }
1310 r = r600_bc_add_alu(ctx->bc, &alu);
1311 if (r)
1312 return r;
1313 }
1314 r = r600_bc_add_literal(ctx->bc, ctx->value);
1315 if (r)
1316 return r;
1317
1318 /* kill must be last in ALU */
1319 ctx->bc->force_add_cf = 1;
1320 ctx->shader->uses_kill = TRUE;
1321 return 0;
1322 }
1323
1324 static int tgsi_lit(struct r600_shader_ctx *ctx)
1325 {
1326 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1327 struct r600_bc_alu alu;
1328 struct r600_bc_alu_src r600_src[3];
1329 int r;
1330
1331 r = tgsi_split_constant(ctx, r600_src);
1332 if (r)
1333 return r;
1334 r = tgsi_split_literal_constant(ctx, r600_src);
1335 if (r)
1336 return r;
1337
1338 /* dst.x, <- 1.0 */
1339 memset(&alu, 0, sizeof(struct r600_bc_alu));
1340 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1341 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1342 alu.src[0].chan = 0;
1343 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1344 if (r)
1345 return r;
1346 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1347 r = r600_bc_add_alu(ctx->bc, &alu);
1348 if (r)
1349 return r;
1350
1351 /* dst.y = max(src.x, 0.0) */
1352 memset(&alu, 0, sizeof(struct r600_bc_alu));
1353 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1354 alu.src[0] = r600_src[0];
1355 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1356 alu.src[1].chan = 0;
1357 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1358 if (r)
1359 return r;
1360 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1361 r = r600_bc_add_alu(ctx->bc, &alu);
1362 if (r)
1363 return r;
1364
1365 /* dst.w, <- 1.0 */
1366 memset(&alu, 0, sizeof(struct r600_bc_alu));
1367 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1368 alu.src[0].sel = V_SQ_ALU_SRC_1;
1369 alu.src[0].chan = 0;
1370 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1371 if (r)
1372 return r;
1373 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1374 alu.last = 1;
1375 r = r600_bc_add_alu(ctx->bc, &alu);
1376 if (r)
1377 return r;
1378
1379 r = r600_bc_add_literal(ctx->bc, ctx->value);
1380 if (r)
1381 return r;
1382
1383 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1384 {
1385 int chan;
1386 int sel;
1387
1388 /* dst.z = log(src.y) */
1389 memset(&alu, 0, sizeof(struct r600_bc_alu));
1390 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1391 alu.src[0] = r600_src[0];
1392 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1393 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1394 if (r)
1395 return r;
1396 alu.last = 1;
1397 r = r600_bc_add_alu(ctx->bc, &alu);
1398 if (r)
1399 return r;
1400
1401 r = r600_bc_add_literal(ctx->bc, ctx->value);
1402 if (r)
1403 return r;
1404
1405 chan = alu.dst.chan;
1406 sel = alu.dst.sel;
1407
1408 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1409 memset(&alu, 0, sizeof(struct r600_bc_alu));
1410 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1411 alu.src[0] = r600_src[0];
1412 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1413 alu.src[1].sel = sel;
1414 alu.src[1].chan = chan;
1415
1416 alu.src[2] = r600_src[0];
1417 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1418 alu.dst.sel = ctx->temp_reg;
1419 alu.dst.chan = 0;
1420 alu.dst.write = 1;
1421 alu.is_op3 = 1;
1422 alu.last = 1;
1423 r = r600_bc_add_alu(ctx->bc, &alu);
1424 if (r)
1425 return r;
1426
1427 r = r600_bc_add_literal(ctx->bc, ctx->value);
1428 if (r)
1429 return r;
1430 /* dst.z = exp(tmp.x) */
1431 memset(&alu, 0, sizeof(struct r600_bc_alu));
1432 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1433 alu.src[0].sel = ctx->temp_reg;
1434 alu.src[0].chan = 0;
1435 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1436 if (r)
1437 return r;
1438 alu.last = 1;
1439 r = r600_bc_add_alu(ctx->bc, &alu);
1440 if (r)
1441 return r;
1442 }
1443 return 0;
1444 }
1445
1446 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1447 {
1448 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1449 struct r600_bc_alu alu;
1450 int i, r;
1451
1452 memset(&alu, 0, sizeof(struct r600_bc_alu));
1453
1454 /* FIXME:
1455 * For state trackers other than OpenGL, we'll want to use
1456 * _RECIPSQRT_IEEE instead.
1457 */
1458 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1459
1460 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1461 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1462 if (r)
1463 return r;
1464 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1465 alu.src[i].abs = 1;
1466 }
1467 alu.dst.sel = ctx->temp_reg;
1468 alu.dst.write = 1;
1469 alu.last = 1;
1470 r = r600_bc_add_alu(ctx->bc, &alu);
1471 if (r)
1472 return r;
1473 r = r600_bc_add_literal(ctx->bc, ctx->value);
1474 if (r)
1475 return r;
1476 /* replicate result */
1477 return tgsi_helper_tempx_replicate(ctx);
1478 }
1479
1480 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1481 {
1482 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1483 struct r600_bc_alu alu;
1484 int i, r;
1485
1486 for (i = 0; i < 4; i++) {
1487 memset(&alu, 0, sizeof(struct r600_bc_alu));
1488 alu.src[0].sel = ctx->temp_reg;
1489 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1490 alu.dst.chan = i;
1491 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1492 if (r)
1493 return r;
1494 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1495 if (i == 3)
1496 alu.last = 1;
1497 r = r600_bc_add_alu(ctx->bc, &alu);
1498 if (r)
1499 return r;
1500 }
1501 return 0;
1502 }
1503
1504 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1505 {
1506 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1507 struct r600_bc_alu alu;
1508 int i, r;
1509
1510 memset(&alu, 0, sizeof(struct r600_bc_alu));
1511 alu.inst = ctx->inst_info->r600_opcode;
1512 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1513 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1514 if (r)
1515 return r;
1516 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1517 }
1518 alu.dst.sel = ctx->temp_reg;
1519 alu.dst.write = 1;
1520 alu.last = 1;
1521 r = r600_bc_add_alu(ctx->bc, &alu);
1522 if (r)
1523 return r;
1524 r = r600_bc_add_literal(ctx->bc, ctx->value);
1525 if (r)
1526 return r;
1527 /* replicate result */
1528 return tgsi_helper_tempx_replicate(ctx);
1529 }
1530
1531 static int tgsi_pow(struct r600_shader_ctx *ctx)
1532 {
1533 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1534 struct r600_bc_alu alu;
1535 int r;
1536
1537 /* LOG2(a) */
1538 memset(&alu, 0, sizeof(struct r600_bc_alu));
1539 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1540 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1541 if (r)
1542 return r;
1543 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1544 alu.dst.sel = ctx->temp_reg;
1545 alu.dst.write = 1;
1546 alu.last = 1;
1547 r = r600_bc_add_alu(ctx->bc, &alu);
1548 if (r)
1549 return r;
1550 r = r600_bc_add_literal(ctx->bc,ctx->value);
1551 if (r)
1552 return r;
1553 /* b * LOG2(a) */
1554 memset(&alu, 0, sizeof(struct r600_bc_alu));
1555 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1556 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1557 if (r)
1558 return r;
1559 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1560 alu.src[1].sel = ctx->temp_reg;
1561 alu.dst.sel = ctx->temp_reg;
1562 alu.dst.write = 1;
1563 alu.last = 1;
1564 r = r600_bc_add_alu(ctx->bc, &alu);
1565 if (r)
1566 return r;
1567 r = r600_bc_add_literal(ctx->bc,ctx->value);
1568 if (r)
1569 return r;
1570 /* POW(a,b) = EXP2(b * LOG2(a))*/
1571 memset(&alu, 0, sizeof(struct r600_bc_alu));
1572 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1573 alu.src[0].sel = ctx->temp_reg;
1574 alu.dst.sel = ctx->temp_reg;
1575 alu.dst.write = 1;
1576 alu.last = 1;
1577 r = r600_bc_add_alu(ctx->bc, &alu);
1578 if (r)
1579 return r;
1580 r = r600_bc_add_literal(ctx->bc,ctx->value);
1581 if (r)
1582 return r;
1583 return tgsi_helper_tempx_replicate(ctx);
1584 }
1585
1586 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1587 {
1588 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1589 struct r600_bc_alu alu;
1590 struct r600_bc_alu_src r600_src[3];
1591 int i, r;
1592
1593 r = tgsi_split_constant(ctx, r600_src);
1594 if (r)
1595 return r;
1596 r = tgsi_split_literal_constant(ctx, r600_src);
1597 if (r)
1598 return r;
1599
1600 /* tmp = (src > 0 ? 1 : src) */
1601 for (i = 0; i < 4; i++) {
1602 memset(&alu, 0, sizeof(struct r600_bc_alu));
1603 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1604 alu.is_op3 = 1;
1605
1606 alu.dst.sel = ctx->temp_reg;
1607 alu.dst.chan = i;
1608
1609 alu.src[0] = r600_src[0];
1610 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1611
1612 alu.src[1].sel = V_SQ_ALU_SRC_1;
1613
1614 alu.src[2] = r600_src[0];
1615 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1616 if (i == 3)
1617 alu.last = 1;
1618 r = r600_bc_add_alu(ctx->bc, &alu);
1619 if (r)
1620 return r;
1621 }
1622 r = r600_bc_add_literal(ctx->bc, ctx->value);
1623 if (r)
1624 return r;
1625
1626 /* dst = (-tmp > 0 ? -1 : tmp) */
1627 for (i = 0; i < 4; i++) {
1628 memset(&alu, 0, sizeof(struct r600_bc_alu));
1629 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1630 alu.is_op3 = 1;
1631 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1632 if (r)
1633 return r;
1634
1635 alu.src[0].sel = ctx->temp_reg;
1636 alu.src[0].chan = i;
1637 alu.src[0].neg = 1;
1638
1639 alu.src[1].sel = V_SQ_ALU_SRC_1;
1640 alu.src[1].neg = 1;
1641
1642 alu.src[2].sel = ctx->temp_reg;
1643 alu.src[2].chan = i;
1644
1645 if (i == 3)
1646 alu.last = 1;
1647 r = r600_bc_add_alu(ctx->bc, &alu);
1648 if (r)
1649 return r;
1650 }
1651 return 0;
1652 }
1653
1654 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1655 {
1656 struct r600_bc_alu alu;
1657 int i, r;
1658
1659 r = r600_bc_add_literal(ctx->bc, ctx->value);
1660 if (r)
1661 return r;
1662 for (i = 0; i < 4; i++) {
1663 memset(&alu, 0, sizeof(struct r600_bc_alu));
1664 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1665 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1666 alu.dst.chan = i;
1667 } else {
1668 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1669 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1670 if (r)
1671 return r;
1672 alu.src[0].sel = ctx->temp_reg;
1673 alu.src[0].chan = i;
1674 }
1675 if (i == 3) {
1676 alu.last = 1;
1677 }
1678 r = r600_bc_add_alu(ctx->bc, &alu);
1679 if (r)
1680 return r;
1681 }
1682 return 0;
1683 }
1684
1685 static int tgsi_op3(struct r600_shader_ctx *ctx)
1686 {
1687 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1688 struct r600_bc_alu_src r600_src[3];
1689 struct r600_bc_alu alu;
1690 int i, j, r;
1691
1692 r = tgsi_split_constant(ctx, r600_src);
1693 if (r)
1694 return r;
1695 r = tgsi_split_literal_constant(ctx, r600_src);
1696 if (r)
1697 return r;
1698 /* do it in 2 step as op3 doesn't support writemask */
1699 for (i = 0; i < 4; i++) {
1700 memset(&alu, 0, sizeof(struct r600_bc_alu));
1701 alu.inst = ctx->inst_info->r600_opcode;
1702 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1703 alu.src[j] = r600_src[j];
1704 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1705 }
1706 alu.dst.sel = ctx->temp_reg;
1707 alu.dst.chan = i;
1708 alu.dst.write = 1;
1709 alu.is_op3 = 1;
1710 if (i == 3) {
1711 alu.last = 1;
1712 }
1713 r = r600_bc_add_alu(ctx->bc, &alu);
1714 if (r)
1715 return r;
1716 }
1717 return tgsi_helper_copy(ctx, inst);
1718 }
1719
1720 static int tgsi_dp(struct r600_shader_ctx *ctx)
1721 {
1722 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1723 struct r600_bc_alu_src r600_src[3];
1724 struct r600_bc_alu alu;
1725 int i, j, r;
1726
1727 r = tgsi_split_constant(ctx, r600_src);
1728 if (r)
1729 return r;
1730 r = tgsi_split_literal_constant(ctx, r600_src);
1731 if (r)
1732 return r;
1733 for (i = 0; i < 4; i++) {
1734 memset(&alu, 0, sizeof(struct r600_bc_alu));
1735 alu.inst = ctx->inst_info->r600_opcode;
1736 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1737 alu.src[j] = r600_src[j];
1738 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1739 }
1740 alu.dst.sel = ctx->temp_reg;
1741 alu.dst.chan = i;
1742 alu.dst.write = 1;
1743 /* handle some special cases */
1744 switch (ctx->inst_info->tgsi_opcode) {
1745 case TGSI_OPCODE_DP2:
1746 if (i > 1) {
1747 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1748 alu.src[0].chan = alu.src[1].chan = 0;
1749 }
1750 break;
1751 case TGSI_OPCODE_DP3:
1752 if (i > 2) {
1753 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1754 alu.src[0].chan = alu.src[1].chan = 0;
1755 }
1756 break;
1757 case TGSI_OPCODE_DPH:
1758 if (i == 3) {
1759 alu.src[0].sel = V_SQ_ALU_SRC_1;
1760 alu.src[0].chan = 0;
1761 alu.src[0].neg = 0;
1762 }
1763 break;
1764 default:
1765 break;
1766 }
1767 if (i == 3) {
1768 alu.last = 1;
1769 }
1770 r = r600_bc_add_alu(ctx->bc, &alu);
1771 if (r)
1772 return r;
1773 }
1774 return tgsi_helper_copy(ctx, inst);
1775 }
1776
1777 static int tgsi_tex(struct r600_shader_ctx *ctx)
1778 {
1779 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1780 struct r600_bc_tex tex;
1781 struct r600_bc_alu alu;
1782 unsigned src_gpr;
1783 int r, i;
1784 int opcode;
1785 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1786 uint32_t lit_vals[4];
1787
1788 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1789
1790 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1791 /* Add perspective divide */
1792 memset(&alu, 0, sizeof(struct r600_bc_alu));
1793 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1794 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1795 if (r)
1796 return r;
1797
1798 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1799 alu.dst.sel = ctx->temp_reg;
1800 alu.dst.chan = 3;
1801 alu.last = 1;
1802 alu.dst.write = 1;
1803 r = r600_bc_add_alu(ctx->bc, &alu);
1804 if (r)
1805 return r;
1806
1807 for (i = 0; i < 3; i++) {
1808 memset(&alu, 0, sizeof(struct r600_bc_alu));
1809 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1810 alu.src[0].sel = ctx->temp_reg;
1811 alu.src[0].chan = 3;
1812 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1813 if (r)
1814 return r;
1815 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1816 alu.dst.sel = ctx->temp_reg;
1817 alu.dst.chan = i;
1818 alu.dst.write = 1;
1819 r = r600_bc_add_alu(ctx->bc, &alu);
1820 if (r)
1821 return r;
1822 }
1823 memset(&alu, 0, sizeof(struct r600_bc_alu));
1824 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1825 alu.src[0].sel = V_SQ_ALU_SRC_1;
1826 alu.src[0].chan = 0;
1827 alu.dst.sel = ctx->temp_reg;
1828 alu.dst.chan = 3;
1829 alu.last = 1;
1830 alu.dst.write = 1;
1831 r = r600_bc_add_alu(ctx->bc, &alu);
1832 if (r)
1833 return r;
1834 src_not_temp = FALSE;
1835 src_gpr = ctx->temp_reg;
1836 }
1837
1838 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1839 int src_chan, src2_chan;
1840
1841 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1842 for (i = 0; i < 4; i++) {
1843 memset(&alu, 0, sizeof(struct r600_bc_alu));
1844 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1845 switch (i) {
1846 case 0:
1847 src_chan = 2;
1848 src2_chan = 1;
1849 break;
1850 case 1:
1851 src_chan = 2;
1852 src2_chan = 0;
1853 break;
1854 case 2:
1855 src_chan = 0;
1856 src2_chan = 2;
1857 break;
1858 case 3:
1859 src_chan = 1;
1860 src2_chan = 2;
1861 break;
1862 default:
1863 assert(0);
1864 src_chan = 0;
1865 src2_chan = 0;
1866 break;
1867 }
1868 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1869 if (r)
1870 return r;
1871 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1872 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1873 if (r)
1874 return r;
1875 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1876 alu.dst.sel = ctx->temp_reg;
1877 alu.dst.chan = i;
1878 if (i == 3)
1879 alu.last = 1;
1880 alu.dst.write = 1;
1881 r = r600_bc_add_alu(ctx->bc, &alu);
1882 if (r)
1883 return r;
1884 }
1885
1886 /* tmp1.z = RCP_e(|tmp1.z|) */
1887 memset(&alu, 0, sizeof(struct r600_bc_alu));
1888 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1889 alu.src[0].sel = ctx->temp_reg;
1890 alu.src[0].chan = 2;
1891 alu.src[0].abs = 1;
1892 alu.dst.sel = ctx->temp_reg;
1893 alu.dst.chan = 2;
1894 alu.dst.write = 1;
1895 alu.last = 1;
1896 r = r600_bc_add_alu(ctx->bc, &alu);
1897 if (r)
1898 return r;
1899
1900 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1901 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1902 * muladd has no writemask, have to use another temp
1903 */
1904 memset(&alu, 0, sizeof(struct r600_bc_alu));
1905 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1906 alu.is_op3 = 1;
1907
1908 alu.src[0].sel = ctx->temp_reg;
1909 alu.src[0].chan = 0;
1910 alu.src[1].sel = ctx->temp_reg;
1911 alu.src[1].chan = 2;
1912
1913 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1914 alu.src[2].chan = 0;
1915
1916 alu.dst.sel = ctx->temp_reg;
1917 alu.dst.chan = 0;
1918 alu.dst.write = 1;
1919
1920 r = r600_bc_add_alu(ctx->bc, &alu);
1921 if (r)
1922 return r;
1923
1924 memset(&alu, 0, sizeof(struct r600_bc_alu));
1925 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1926 alu.is_op3 = 1;
1927
1928 alu.src[0].sel = ctx->temp_reg;
1929 alu.src[0].chan = 1;
1930 alu.src[1].sel = ctx->temp_reg;
1931 alu.src[1].chan = 2;
1932
1933 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1934 alu.src[2].chan = 0;
1935
1936 alu.dst.sel = ctx->temp_reg;
1937 alu.dst.chan = 1;
1938 alu.dst.write = 1;
1939
1940 alu.last = 1;
1941 r = r600_bc_add_alu(ctx->bc, &alu);
1942 if (r)
1943 return r;
1944
1945 lit_vals[0] = fui(1.5f);
1946
1947 r = r600_bc_add_literal(ctx->bc, lit_vals);
1948 if (r)
1949 return r;
1950 src_not_temp = FALSE;
1951 src_gpr = ctx->temp_reg;
1952 }
1953
1954 if (src_not_temp) {
1955 for (i = 0; i < 4; i++) {
1956 memset(&alu, 0, sizeof(struct r600_bc_alu));
1957 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1958 alu.src[0].sel = src_gpr;
1959 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1960 alu.dst.sel = ctx->temp_reg;
1961 alu.dst.chan = i;
1962 if (i == 3)
1963 alu.last = 1;
1964 alu.dst.write = 1;
1965 r = r600_bc_add_alu(ctx->bc, &alu);
1966 if (r)
1967 return r;
1968 }
1969 src_gpr = ctx->temp_reg;
1970 }
1971
1972 opcode = ctx->inst_info->r600_opcode;
1973 if (opcode == SQ_TEX_INST_SAMPLE &&
1974 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1975 opcode = SQ_TEX_INST_SAMPLE_C;
1976
1977 memset(&tex, 0, sizeof(struct r600_bc_tex));
1978 tex.inst = opcode;
1979 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1980 tex.resource_id = tex.sampler_id;
1981 if (ctx->shader->processor_type == TGSI_PROCESSOR_VERTEX)
1982 tex.resource_id += PIPE_MAX_ATTRIBS;
1983 tex.src_gpr = src_gpr;
1984 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1985 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1986 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1987 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1988 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1989 tex.src_sel_x = 0;
1990 tex.src_sel_y = 1;
1991 tex.src_sel_z = 2;
1992 tex.src_sel_w = 3;
1993
1994 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1995 tex.src_sel_x = 1;
1996 tex.src_sel_y = 0;
1997 tex.src_sel_z = 3;
1998 tex.src_sel_w = 1;
1999 }
2000
2001 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
2002 tex.coord_type_x = 1;
2003 tex.coord_type_y = 1;
2004 tex.coord_type_z = 1;
2005 tex.coord_type_w = 1;
2006 }
2007
2008 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
2009 tex.src_sel_w = 2;
2010
2011 r = r600_bc_add_tex(ctx->bc, &tex);
2012 if (r)
2013 return r;
2014
2015 /* add shadow ambient support - gallium doesn't do it yet */
2016 return 0;
2017
2018 }
2019
2020 static int tgsi_lrp(struct r600_shader_ctx *ctx)
2021 {
2022 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2023 struct r600_bc_alu_src r600_src[3];
2024 struct r600_bc_alu alu;
2025 unsigned i;
2026 int r;
2027
2028 r = tgsi_split_constant(ctx, r600_src);
2029 if (r)
2030 return r;
2031 r = tgsi_split_literal_constant(ctx, r600_src);
2032 if (r)
2033 return r;
2034 /* 1 - src0 */
2035 for (i = 0; i < 4; i++) {
2036 memset(&alu, 0, sizeof(struct r600_bc_alu));
2037 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
2038 alu.src[0].sel = V_SQ_ALU_SRC_1;
2039 alu.src[0].chan = 0;
2040 alu.src[1] = r600_src[0];
2041 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
2042 alu.src[1].neg = 1;
2043 alu.dst.sel = ctx->temp_reg;
2044 alu.dst.chan = i;
2045 if (i == 3) {
2046 alu.last = 1;
2047 }
2048 alu.dst.write = 1;
2049 r = r600_bc_add_alu(ctx->bc, &alu);
2050 if (r)
2051 return r;
2052 }
2053 r = r600_bc_add_literal(ctx->bc, ctx->value);
2054 if (r)
2055 return r;
2056
2057 /* (1 - src0) * src2 */
2058 for (i = 0; i < 4; i++) {
2059 memset(&alu, 0, sizeof(struct r600_bc_alu));
2060 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2061 alu.src[0].sel = ctx->temp_reg;
2062 alu.src[0].chan = i;
2063 alu.src[1] = r600_src[2];
2064 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2065 alu.dst.sel = ctx->temp_reg;
2066 alu.dst.chan = i;
2067 if (i == 3) {
2068 alu.last = 1;
2069 }
2070 alu.dst.write = 1;
2071 r = r600_bc_add_alu(ctx->bc, &alu);
2072 if (r)
2073 return r;
2074 }
2075 r = r600_bc_add_literal(ctx->bc, ctx->value);
2076 if (r)
2077 return r;
2078
2079 /* src0 * src1 + (1 - src0) * src2 */
2080 for (i = 0; i < 4; i++) {
2081 memset(&alu, 0, sizeof(struct r600_bc_alu));
2082 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2083 alu.is_op3 = 1;
2084 alu.src[0] = r600_src[0];
2085 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2086 alu.src[1] = r600_src[1];
2087 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2088 alu.src[2].sel = ctx->temp_reg;
2089 alu.src[2].chan = i;
2090 alu.dst.sel = ctx->temp_reg;
2091 alu.dst.chan = i;
2092 if (i == 3) {
2093 alu.last = 1;
2094 }
2095 r = r600_bc_add_alu(ctx->bc, &alu);
2096 if (r)
2097 return r;
2098 }
2099 return tgsi_helper_copy(ctx, inst);
2100 }
2101
2102 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2103 {
2104 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2105 struct r600_bc_alu_src r600_src[3];
2106 struct r600_bc_alu alu;
2107 int use_temp = 0;
2108 int i, r;
2109
2110 r = tgsi_split_constant(ctx, r600_src);
2111 if (r)
2112 return r;
2113 r = tgsi_split_literal_constant(ctx, r600_src);
2114 if (r)
2115 return r;
2116
2117 if (inst->Dst[0].Register.WriteMask != 0xf)
2118 use_temp = 1;
2119
2120 for (i = 0; i < 4; i++) {
2121 memset(&alu, 0, sizeof(struct r600_bc_alu));
2122 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2123 alu.src[0] = r600_src[0];
2124 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2125
2126 alu.src[1] = r600_src[2];
2127 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2128
2129 alu.src[2] = r600_src[1];
2130 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2131
2132 if (use_temp)
2133 alu.dst.sel = ctx->temp_reg;
2134 else {
2135 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2136 if (r)
2137 return r;
2138 }
2139 alu.dst.chan = i;
2140 alu.dst.write = 1;
2141 alu.is_op3 = 1;
2142 if (i == 3)
2143 alu.last = 1;
2144 r = r600_bc_add_alu(ctx->bc, &alu);
2145 if (r)
2146 return r;
2147 }
2148 if (use_temp)
2149 return tgsi_helper_copy(ctx, inst);
2150 return 0;
2151 }
2152
2153 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2154 {
2155 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2156 struct r600_bc_alu_src r600_src[3];
2157 struct r600_bc_alu alu;
2158 uint32_t use_temp = 0;
2159 int i, r;
2160
2161 if (inst->Dst[0].Register.WriteMask != 0xf)
2162 use_temp = 1;
2163
2164 r = tgsi_split_constant(ctx, r600_src);
2165 if (r)
2166 return r;
2167 r = tgsi_split_literal_constant(ctx, r600_src);
2168 if (r)
2169 return r;
2170
2171 for (i = 0; i < 4; i++) {
2172 memset(&alu, 0, sizeof(struct r600_bc_alu));
2173 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2174
2175 alu.src[0] = r600_src[0];
2176 switch (i) {
2177 case 0:
2178 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2179 break;
2180 case 1:
2181 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2182 break;
2183 case 2:
2184 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2185 break;
2186 case 3:
2187 alu.src[0].sel = V_SQ_ALU_SRC_0;
2188 alu.src[0].chan = i;
2189 }
2190
2191 alu.src[1] = r600_src[1];
2192 switch (i) {
2193 case 0:
2194 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2195 break;
2196 case 1:
2197 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2198 break;
2199 case 2:
2200 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2201 break;
2202 case 3:
2203 alu.src[1].sel = V_SQ_ALU_SRC_0;
2204 alu.src[1].chan = i;
2205 }
2206
2207 alu.dst.sel = ctx->temp_reg;
2208 alu.dst.chan = i;
2209 alu.dst.write = 1;
2210
2211 if (i == 3)
2212 alu.last = 1;
2213 r = r600_bc_add_alu(ctx->bc, &alu);
2214 if (r)
2215 return r;
2216
2217 r = r600_bc_add_literal(ctx->bc, ctx->value);
2218 if (r)
2219 return r;
2220 }
2221
2222 for (i = 0; i < 4; i++) {
2223 memset(&alu, 0, sizeof(struct r600_bc_alu));
2224 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2225
2226 alu.src[0] = r600_src[0];
2227 switch (i) {
2228 case 0:
2229 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2230 break;
2231 case 1:
2232 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2233 break;
2234 case 2:
2235 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2236 break;
2237 case 3:
2238 alu.src[0].sel = V_SQ_ALU_SRC_0;
2239 alu.src[0].chan = i;
2240 }
2241
2242 alu.src[1] = r600_src[1];
2243 switch (i) {
2244 case 0:
2245 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2246 break;
2247 case 1:
2248 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2249 break;
2250 case 2:
2251 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2252 break;
2253 case 3:
2254 alu.src[1].sel = V_SQ_ALU_SRC_0;
2255 alu.src[1].chan = i;
2256 }
2257
2258 alu.src[2].sel = ctx->temp_reg;
2259 alu.src[2].neg = 1;
2260 alu.src[2].chan = i;
2261
2262 if (use_temp)
2263 alu.dst.sel = ctx->temp_reg;
2264 else {
2265 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2266 if (r)
2267 return r;
2268 }
2269 alu.dst.chan = i;
2270 alu.dst.write = 1;
2271 alu.is_op3 = 1;
2272 if (i == 3)
2273 alu.last = 1;
2274 r = r600_bc_add_alu(ctx->bc, &alu);
2275 if (r)
2276 return r;
2277
2278 r = r600_bc_add_literal(ctx->bc, ctx->value);
2279 if (r)
2280 return r;
2281 }
2282 if (use_temp)
2283 return tgsi_helper_copy(ctx, inst);
2284 return 0;
2285 }
2286
2287 static int tgsi_exp(struct r600_shader_ctx *ctx)
2288 {
2289 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2290 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2291 struct r600_bc_alu alu;
2292 int r;
2293
2294 /* result.x = 2^floor(src); */
2295 if (inst->Dst[0].Register.WriteMask & 1) {
2296 memset(&alu, 0, sizeof(struct r600_bc_alu));
2297
2298 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2299 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2300 if (r)
2301 return r;
2302
2303 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2304
2305 alu.dst.sel = ctx->temp_reg;
2306 alu.dst.chan = 0;
2307 alu.dst.write = 1;
2308 alu.last = 1;
2309 r = r600_bc_add_alu(ctx->bc, &alu);
2310 if (r)
2311 return r;
2312
2313 r = r600_bc_add_literal(ctx->bc, ctx->value);
2314 if (r)
2315 return r;
2316
2317 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2318 alu.src[0].sel = ctx->temp_reg;
2319 alu.src[0].chan = 0;
2320
2321 alu.dst.sel = ctx->temp_reg;
2322 alu.dst.chan = 0;
2323 alu.dst.write = 1;
2324 alu.last = 1;
2325 r = r600_bc_add_alu(ctx->bc, &alu);
2326 if (r)
2327 return r;
2328
2329 r = r600_bc_add_literal(ctx->bc, ctx->value);
2330 if (r)
2331 return r;
2332 }
2333
2334 /* result.y = tmp - floor(tmp); */
2335 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2336 memset(&alu, 0, sizeof(struct r600_bc_alu));
2337
2338 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2339 alu.src[0] = r600_src[0];
2340 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2341 if (r)
2342 return r;
2343 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2344
2345 alu.dst.sel = ctx->temp_reg;
2346 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2347 // if (r)
2348 // return r;
2349 alu.dst.write = 1;
2350 alu.dst.chan = 1;
2351
2352 alu.last = 1;
2353
2354 r = r600_bc_add_alu(ctx->bc, &alu);
2355 if (r)
2356 return r;
2357 r = r600_bc_add_literal(ctx->bc, ctx->value);
2358 if (r)
2359 return r;
2360 }
2361
2362 /* result.z = RoughApprox2ToX(tmp);*/
2363 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2364 memset(&alu, 0, sizeof(struct r600_bc_alu));
2365 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2366 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2367 if (r)
2368 return r;
2369 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2370
2371 alu.dst.sel = ctx->temp_reg;
2372 alu.dst.write = 1;
2373 alu.dst.chan = 2;
2374
2375 alu.last = 1;
2376
2377 r = r600_bc_add_alu(ctx->bc, &alu);
2378 if (r)
2379 return r;
2380 r = r600_bc_add_literal(ctx->bc, ctx->value);
2381 if (r)
2382 return r;
2383 }
2384
2385 /* result.w = 1.0;*/
2386 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2387 memset(&alu, 0, sizeof(struct r600_bc_alu));
2388
2389 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2390 alu.src[0].sel = V_SQ_ALU_SRC_1;
2391 alu.src[0].chan = 0;
2392
2393 alu.dst.sel = ctx->temp_reg;
2394 alu.dst.chan = 3;
2395 alu.dst.write = 1;
2396 alu.last = 1;
2397 r = r600_bc_add_alu(ctx->bc, &alu);
2398 if (r)
2399 return r;
2400 r = r600_bc_add_literal(ctx->bc, ctx->value);
2401 if (r)
2402 return r;
2403 }
2404 return tgsi_helper_copy(ctx, inst);
2405 }
2406
2407 static int tgsi_log(struct r600_shader_ctx *ctx)
2408 {
2409 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2410 struct r600_bc_alu alu;
2411 int r;
2412
2413 /* result.x = floor(log2(src)); */
2414 if (inst->Dst[0].Register.WriteMask & 1) {
2415 memset(&alu, 0, sizeof(struct r600_bc_alu));
2416
2417 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2418 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2419 if (r)
2420 return r;
2421
2422 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2423
2424 alu.dst.sel = ctx->temp_reg;
2425 alu.dst.chan = 0;
2426 alu.dst.write = 1;
2427 alu.last = 1;
2428 r = r600_bc_add_alu(ctx->bc, &alu);
2429 if (r)
2430 return r;
2431
2432 r = r600_bc_add_literal(ctx->bc, ctx->value);
2433 if (r)
2434 return r;
2435
2436 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2437 alu.src[0].sel = ctx->temp_reg;
2438 alu.src[0].chan = 0;
2439
2440 alu.dst.sel = ctx->temp_reg;
2441 alu.dst.chan = 0;
2442 alu.dst.write = 1;
2443 alu.last = 1;
2444
2445 r = r600_bc_add_alu(ctx->bc, &alu);
2446 if (r)
2447 return r;
2448
2449 r = r600_bc_add_literal(ctx->bc, ctx->value);
2450 if (r)
2451 return r;
2452 }
2453
2454 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2455 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2456 memset(&alu, 0, sizeof(struct r600_bc_alu));
2457
2458 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2459 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2460 if (r)
2461 return r;
2462
2463 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2464
2465 alu.dst.sel = ctx->temp_reg;
2466 alu.dst.chan = 1;
2467 alu.dst.write = 1;
2468 alu.last = 1;
2469
2470 r = r600_bc_add_alu(ctx->bc, &alu);
2471 if (r)
2472 return r;
2473
2474 r = r600_bc_add_literal(ctx->bc, ctx->value);
2475 if (r)
2476 return r;
2477
2478 memset(&alu, 0, sizeof(struct r600_bc_alu));
2479
2480 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2481 alu.src[0].sel = ctx->temp_reg;
2482 alu.src[0].chan = 1;
2483
2484 alu.dst.sel = ctx->temp_reg;
2485 alu.dst.chan = 1;
2486 alu.dst.write = 1;
2487 alu.last = 1;
2488
2489 r = r600_bc_add_alu(ctx->bc, &alu);
2490 if (r)
2491 return r;
2492
2493 r = r600_bc_add_literal(ctx->bc, ctx->value);
2494 if (r)
2495 return r;
2496
2497 memset(&alu, 0, sizeof(struct r600_bc_alu));
2498
2499 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2500 alu.src[0].sel = ctx->temp_reg;
2501 alu.src[0].chan = 1;
2502
2503 alu.dst.sel = ctx->temp_reg;
2504 alu.dst.chan = 1;
2505 alu.dst.write = 1;
2506 alu.last = 1;
2507
2508 r = r600_bc_add_alu(ctx->bc, &alu);
2509 if (r)
2510 return r;
2511
2512 r = r600_bc_add_literal(ctx->bc, ctx->value);
2513 if (r)
2514 return r;
2515
2516 memset(&alu, 0, sizeof(struct r600_bc_alu));
2517
2518 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2519 alu.src[0].sel = ctx->temp_reg;
2520 alu.src[0].chan = 1;
2521
2522 alu.dst.sel = ctx->temp_reg;
2523 alu.dst.chan = 1;
2524 alu.dst.write = 1;
2525 alu.last = 1;
2526
2527 r = r600_bc_add_alu(ctx->bc, &alu);
2528 if (r)
2529 return r;
2530
2531 r = r600_bc_add_literal(ctx->bc, ctx->value);
2532 if (r)
2533 return r;
2534
2535 memset(&alu, 0, sizeof(struct r600_bc_alu));
2536
2537 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2538
2539 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2540 if (r)
2541 return r;
2542
2543 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2544
2545 alu.src[1].sel = ctx->temp_reg;
2546 alu.src[1].chan = 1;
2547
2548 alu.dst.sel = ctx->temp_reg;
2549 alu.dst.chan = 1;
2550 alu.dst.write = 1;
2551 alu.last = 1;
2552
2553 r = r600_bc_add_alu(ctx->bc, &alu);
2554 if (r)
2555 return r;
2556
2557 r = r600_bc_add_literal(ctx->bc, ctx->value);
2558 if (r)
2559 return r;
2560 }
2561
2562 /* result.z = log2(src);*/
2563 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2564 memset(&alu, 0, sizeof(struct r600_bc_alu));
2565
2566 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2567 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2568 if (r)
2569 return r;
2570
2571 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2572
2573 alu.dst.sel = ctx->temp_reg;
2574 alu.dst.write = 1;
2575 alu.dst.chan = 2;
2576 alu.last = 1;
2577
2578 r = r600_bc_add_alu(ctx->bc, &alu);
2579 if (r)
2580 return r;
2581
2582 r = r600_bc_add_literal(ctx->bc, ctx->value);
2583 if (r)
2584 return r;
2585 }
2586
2587 /* result.w = 1.0; */
2588 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2589 memset(&alu, 0, sizeof(struct r600_bc_alu));
2590
2591 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2592 alu.src[0].sel = V_SQ_ALU_SRC_1;
2593 alu.src[0].chan = 0;
2594
2595 alu.dst.sel = ctx->temp_reg;
2596 alu.dst.chan = 3;
2597 alu.dst.write = 1;
2598 alu.last = 1;
2599
2600 r = r600_bc_add_alu(ctx->bc, &alu);
2601 if (r)
2602 return r;
2603
2604 r = r600_bc_add_literal(ctx->bc, ctx->value);
2605 if (r)
2606 return r;
2607 }
2608
2609 return tgsi_helper_copy(ctx, inst);
2610 }
2611
2612 /* r6/7 only for now */
2613 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2614 {
2615 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2616 struct r600_bc_alu alu;
2617 int r;
2618
2619 memset(&alu, 0, sizeof(struct r600_bc_alu));
2620
2621 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2622 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2623 if (r)
2624 return r;
2625 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2626 alu.last = 1;
2627 alu.dst.chan = 0;
2628 alu.dst.sel = ctx->temp_reg;
2629 alu.dst.write = 1;
2630 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2631 if (r)
2632 return r;
2633 memset(&alu, 0, sizeof(struct r600_bc_alu));
2634 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2635 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2636 if (r)
2637 return r;
2638 alu.src[0].sel = ctx->temp_reg;
2639 alu.src[0].chan = 0;
2640 alu.last = 1;
2641 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2642 if (r)
2643 return r;
2644 return 0;
2645 }
2646 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2647 {
2648 /* TODO from r600c, ar values don't persist between clauses */
2649 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2650 struct r600_bc_alu alu;
2651 int r;
2652 memset(&alu, 0, sizeof(struct r600_bc_alu));
2653
2654 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2655
2656 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2657 if (r)
2658 return r;
2659 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2660
2661 alu.last = 1;
2662
2663 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2664 if (r)
2665 return r;
2666 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2667 return 0;
2668 }
2669
2670 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2671 {
2672 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2673 struct r600_bc_alu alu;
2674 int i, r = 0;
2675
2676 for (i = 0; i < 4; i++) {
2677 memset(&alu, 0, sizeof(struct r600_bc_alu));
2678
2679 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2680 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2681 if (r)
2682 return r;
2683
2684 if (i == 0 || i == 3) {
2685 alu.src[0].sel = V_SQ_ALU_SRC_1;
2686 } else {
2687 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2688 if (r)
2689 return r;
2690 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2691 }
2692
2693 if (i == 0 || i == 2) {
2694 alu.src[1].sel = V_SQ_ALU_SRC_1;
2695 } else {
2696 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2697 if (r)
2698 return r;
2699 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2700 }
2701 if (i == 3)
2702 alu.last = 1;
2703 r = r600_bc_add_alu(ctx->bc, &alu);
2704 if (r)
2705 return r;
2706 }
2707 return 0;
2708 }
2709
2710 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2711 {
2712 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2713 struct r600_bc_alu alu;
2714 int r;
2715
2716 memset(&alu, 0, sizeof(struct r600_bc_alu));
2717 alu.inst = opcode;
2718 alu.predicate = 1;
2719
2720 alu.dst.sel = ctx->temp_reg;
2721 alu.dst.write = 1;
2722 alu.dst.chan = 0;
2723
2724 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2725 if (r)
2726 return r;
2727 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2728 alu.src[1].sel = V_SQ_ALU_SRC_0;
2729 alu.src[1].chan = 0;
2730
2731 alu.last = 1;
2732
2733 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2734 if (r)
2735 return r;
2736 return 0;
2737 }
2738
2739 static int pops(struct r600_shader_ctx *ctx, int pops)
2740 {
2741 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2742 ctx->bc->cf_last->pop_count = pops;
2743 return 0;
2744 }
2745
2746 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2747 {
2748 switch(reason) {
2749 case FC_PUSH_VPM:
2750 ctx->bc->callstack[ctx->bc->call_sp].current--;
2751 break;
2752 case FC_PUSH_WQM:
2753 case FC_LOOP:
2754 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2755 break;
2756 case FC_REP:
2757 /* TOODO : for 16 vp asic should -= 2; */
2758 ctx->bc->callstack[ctx->bc->call_sp].current --;
2759 break;
2760 }
2761 }
2762
2763 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2764 {
2765 if (check_max_only) {
2766 int diff;
2767 switch (reason) {
2768 case FC_PUSH_VPM:
2769 diff = 1;
2770 break;
2771 case FC_PUSH_WQM:
2772 diff = 4;
2773 break;
2774 default:
2775 assert(0);
2776 diff = 0;
2777 }
2778 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2779 ctx->bc->callstack[ctx->bc->call_sp].max) {
2780 ctx->bc->callstack[ctx->bc->call_sp].max =
2781 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2782 }
2783 return;
2784 }
2785 switch (reason) {
2786 case FC_PUSH_VPM:
2787 ctx->bc->callstack[ctx->bc->call_sp].current++;
2788 break;
2789 case FC_PUSH_WQM:
2790 case FC_LOOP:
2791 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2792 break;
2793 case FC_REP:
2794 ctx->bc->callstack[ctx->bc->call_sp].current++;
2795 break;
2796 }
2797
2798 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2799 ctx->bc->callstack[ctx->bc->call_sp].max) {
2800 ctx->bc->callstack[ctx->bc->call_sp].max =
2801 ctx->bc->callstack[ctx->bc->call_sp].current;
2802 }
2803 }
2804
2805 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2806 {
2807 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2808
2809 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2810 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2811 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2812 sp->num_mid++;
2813 }
2814
2815 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2816 {
2817 ctx->bc->fc_sp++;
2818 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2819 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2820 }
2821
2822 static void fc_poplevel(struct r600_shader_ctx *ctx)
2823 {
2824 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2825 if (sp->mid) {
2826 free(sp->mid);
2827 sp->mid = NULL;
2828 }
2829 sp->num_mid = 0;
2830 sp->start = NULL;
2831 sp->type = 0;
2832 ctx->bc->fc_sp--;
2833 }
2834
2835 #if 0
2836 static int emit_return(struct r600_shader_ctx *ctx)
2837 {
2838 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2839 return 0;
2840 }
2841
2842 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2843 {
2844
2845 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2846 ctx->bc->cf_last->pop_count = pops;
2847 /* TODO work out offset */
2848 return 0;
2849 }
2850
2851 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2852 {
2853 return 0;
2854 }
2855
2856 static void emit_testflag(struct r600_shader_ctx *ctx)
2857 {
2858
2859 }
2860
2861 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2862 {
2863 emit_testflag(ctx);
2864 emit_jump_to_offset(ctx, 1, 4);
2865 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2866 pops(ctx, ifidx + 1);
2867 emit_return(ctx);
2868 }
2869
2870 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2871 {
2872 emit_testflag(ctx);
2873
2874 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2875 ctx->bc->cf_last->pop_count = 1;
2876
2877 fc_set_mid(ctx, fc_sp);
2878
2879 pops(ctx, 1);
2880 }
2881 #endif
2882
2883 static int tgsi_if(struct r600_shader_ctx *ctx)
2884 {
2885 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2886
2887 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2888
2889 fc_pushlevel(ctx, FC_IF);
2890
2891 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2892 return 0;
2893 }
2894
2895 static int tgsi_else(struct r600_shader_ctx *ctx)
2896 {
2897 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2898 ctx->bc->cf_last->pop_count = 1;
2899
2900 fc_set_mid(ctx, ctx->bc->fc_sp);
2901 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2902 return 0;
2903 }
2904
2905 static int tgsi_endif(struct r600_shader_ctx *ctx)
2906 {
2907 pops(ctx, 1);
2908 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2909 R600_ERR("if/endif unbalanced in shader\n");
2910 return -1;
2911 }
2912
2913 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2914 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2915 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2916 } else {
2917 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2918 }
2919 fc_poplevel(ctx);
2920
2921 callstack_decrease_current(ctx, FC_PUSH_VPM);
2922 return 0;
2923 }
2924
2925 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2926 {
2927 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2928
2929 fc_pushlevel(ctx, FC_LOOP);
2930
2931 /* check stack depth */
2932 callstack_check_depth(ctx, FC_LOOP, 0);
2933 return 0;
2934 }
2935
2936 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2937 {
2938 int i;
2939
2940 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2941
2942 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2943 R600_ERR("loop/endloop in shader code are not paired.\n");
2944 return -EINVAL;
2945 }
2946
2947 /* fixup loop pointers - from r600isa
2948 LOOP END points to CF after LOOP START,
2949 LOOP START point to CF after LOOP END
2950 BRK/CONT point to LOOP END CF
2951 */
2952 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2953
2954 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2955
2956 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2957 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2958 }
2959 /* TODO add LOOPRET support */
2960 fc_poplevel(ctx);
2961 callstack_decrease_current(ctx, FC_LOOP);
2962 return 0;
2963 }
2964
2965 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2966 {
2967 unsigned int fscp;
2968
2969 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2970 {
2971 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2972 break;
2973 }
2974
2975 if (fscp == 0) {
2976 R600_ERR("Break not inside loop/endloop pair\n");
2977 return -EINVAL;
2978 }
2979
2980 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2981 ctx->bc->cf_last->pop_count = 1;
2982
2983 fc_set_mid(ctx, fscp);
2984
2985 pops(ctx, 1);
2986 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2987 return 0;
2988 }
2989
2990 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2991 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2992 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2993 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2994
2995 /* FIXME:
2996 * For state trackers other than OpenGL, we'll want to use
2997 * _RECIP_IEEE instead.
2998 */
2999 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
3000
3001 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
3002 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3003 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
3004 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3005 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3006 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3007 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3008 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3009 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3010 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3011 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3012 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3013 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3014 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3015 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3016 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 /* gap */
3018 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 /* gap */
3021 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3024 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3026 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3027 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3028 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3029 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3030 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3031 /* gap */
3032 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3034 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3036 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3037 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3038 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3039 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3040 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3041 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3042 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3043 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3044 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3045 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3046 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3048 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3049 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3050 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3051 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3053 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3055 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3056 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3058 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3066 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3067 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3068 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3069 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3072 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3073 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3074 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3075 /* gap */
3076 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3077 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3078 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3079 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3080 /* gap */
3081 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3082 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3089 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 /* gap */
3091 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3092 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3100 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3103 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3105 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3106 /* gap */
3107 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3108 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 /* gap */
3113 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3115 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3116 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3118 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3122 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3123 /* gap */
3124 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3127 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3132 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3143 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3147 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3149 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 };
3153
3154 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3155 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3156 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3157 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3158 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3159 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3160 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3161 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3162 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3163 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3164 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3165 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3166 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3167 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3168 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3169 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3170 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3171 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3172 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3173 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3174 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 /* gap */
3176 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3177 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3178 /* gap */
3179 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3180 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3181 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3182 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3183 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3184 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3185 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3186 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3187 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3188 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3189 /* gap */
3190 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3191 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3192 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3193 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3194 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3195 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3196 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3197 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3198 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3199 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3200 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3201 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3202 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3203 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3204 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3205 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3206 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3207 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3208 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3209 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3210 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3211 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3212 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3213 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3214 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3215 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3216 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3217 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3218 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3219 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3220 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3221 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3222 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3223 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3224 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3225 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3226 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3227 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3228 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3229 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3230 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3231 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3232 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3233 /* gap */
3234 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3235 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3236 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3237 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3238 /* gap */
3239 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3240 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3241 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3242 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3243 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3244 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3245 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3246 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3247 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3248 /* gap */
3249 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3250 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3251 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3252 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3253 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3254 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3255 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3256 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3257 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3258 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3259 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3260 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3261 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3262 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3263 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3264 /* gap */
3265 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3266 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3267 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3268 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3269 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3270 /* gap */
3271 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3272 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3273 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3274 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3275 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3276 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3277 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3278 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3279 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3280 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3281 /* gap */
3282 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3283 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3284 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3285 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3286 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3287 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3288 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3289 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3290 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3291 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3292 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3293 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3294 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3295 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3296 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3297 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3298 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3299 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3300 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3301 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3302 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3303 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3304 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3305 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3306 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3307 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3308 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3309 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3310 };