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r600g: use full range of VS resources for vertex samplers
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 for (i = 0; i < 10; i++) {
48 spi_vs_out_id[i] = 0;
49 }
50 for (i = 0; i < 32; i++) {
51 tmp = i << ((i & 3) * 8);
52 spi_vs_out_id[i / 4] |= tmp;
53 }
54 for (i = 0; i < 10; i++) {
55 r600_pipe_state_add_reg(rstate,
56 R_028614_SPI_VS_OUT_ID_0 + i * 4,
57 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
58 }
59
60 r600_pipe_state_add_reg(rstate,
61 R_0286C4_SPI_VS_OUT_CONFIG,
62 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
63 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate,
65 R_028868_SQ_PGM_RESOURCES_VS,
66 S_028868_NUM_GPRS(rshader->bc.ngpr) |
67 S_028868_STACK_SIZE(rshader->bc.nstack),
68 0xFFFFFFFF, NULL);
69 r600_pipe_state_add_reg(rstate,
70 R_0288A4_SQ_PGM_RESOURCES_FS,
71 0x00000000, 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS,
77 0x00000000, 0xFFFFFFFF, NULL);
78 r600_pipe_state_add_reg(rstate,
79 R_028858_SQ_PGM_START_VS,
80 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
81 r600_pipe_state_add_reg(rstate,
82 R_028894_SQ_PGM_START_FS,
83 r600_bo_offset(shader->bo_fetch) >> 8, 0xFFFFFFFF, shader->bo_fetch);
84
85 r600_pipe_state_add_reg(rstate,
86 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
87 0xFFFFFFFF, NULL);
88
89 }
90
91 int r600_find_vs_semantic_index(struct r600_shader *vs,
92 struct r600_shader *ps, int id)
93 {
94 struct r600_shader_io *input = &ps->input[id];
95
96 for (int i = 0; i < vs->noutput; i++) {
97 if (input->name == vs->output[i].name &&
98 input->sid == vs->output[i].sid) {
99 return i - 1;
100 }
101 }
102 return 0;
103 }
104
105 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
106 {
107 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
108 struct r600_pipe_state *rstate = &shader->rstate;
109 struct r600_shader *rshader = &shader->shader;
110 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
111 int pos_index = -1, face_index = -1;
112
113 /* clear previous register */
114 rstate->nregs = 0;
115
116 for (i = 0; i < rshader->ninput; i++) {
117 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
118 if (rshader->input[i].centroid)
119 tmp |= S_028644_SEL_CENTROID(1);
120 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
121 tmp |= S_028644_SEL_LINEAR(1);
122
123 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
124 pos_index = i;
125 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
126 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
127 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
128 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
129 }
130 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
131 face_index = i;
132 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
133 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
134 tmp |= S_028644_PT_SPRITE_TEX(1);
135 }
136 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
137 }
138 for (i = 0; i < rshader->noutput; i++) {
139 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
140 r600_pipe_state_add_reg(rstate,
141 R_02880C_DB_SHADER_CONTROL,
142 S_02880C_Z_EXPORT_ENABLE(1),
143 S_02880C_Z_EXPORT_ENABLE(1), NULL);
144 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
145 r600_pipe_state_add_reg(rstate,
146 R_02880C_DB_SHADER_CONTROL,
147 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
148 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
149 }
150
151 exports_ps = 0;
152 num_cout = 0;
153 for (i = 0; i < rshader->noutput; i++) {
154 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
155 exports_ps |= 1;
156 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
157 num_cout++;
158 }
159 }
160 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
161 if (!exports_ps) {
162 /* always at least export 1 component per pixel */
163 exports_ps = 2;
164 }
165
166 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
167 S_0286CC_PERSP_GRADIENT_ENA(1);
168 spi_input_z = 0;
169 if (pos_index != -1) {
170 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
171 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
172 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
173 S_0286CC_BARYC_SAMPLE_CNTL(1));
174 spi_input_z |= 1;
175 }
176
177 spi_ps_in_control_1 = 0;
178 if (face_index != -1) {
179 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
180 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
181 }
182
183 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
184 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
185 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
186 r600_pipe_state_add_reg(rstate,
187 R_028840_SQ_PGM_START_PS,
188 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
189 r600_pipe_state_add_reg(rstate,
190 R_028850_SQ_PGM_RESOURCES_PS,
191 S_028868_NUM_GPRS(rshader->bc.ngpr) |
192 S_028868_STACK_SIZE(rshader->bc.nstack),
193 0xFFFFFFFF, NULL);
194 r600_pipe_state_add_reg(rstate,
195 R_028854_SQ_PGM_EXPORTS_PS,
196 exports_ps, 0xFFFFFFFF, NULL);
197 r600_pipe_state_add_reg(rstate,
198 R_0288CC_SQ_PGM_CF_OFFSET_PS,
199 0x00000000, 0xFFFFFFFF, NULL);
200
201 if (rshader->uses_kill) {
202 /* only set some bits here, the other bits are set in the dsa state */
203 r600_pipe_state_add_reg(rstate,
204 R_02880C_DB_SHADER_CONTROL,
205 S_02880C_KILL_ENABLE(1),
206 S_02880C_KILL_ENABLE(1), NULL);
207 }
208 r600_pipe_state_add_reg(rstate,
209 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
210 0xFFFFFFFF, NULL);
211 }
212
213 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
214 {
215 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
216 struct r600_shader *rshader = &shader->shader;
217 void *ptr;
218
219 /* copy new shader */
220 if (rshader->processor_type == TGSI_PROCESSOR_VERTEX && shader->bo_fetch == NULL) {
221 shader->bo_fetch = r600_bo(rctx->radeon, rshader->bc_fetch.ndw * 4, 4096, 0, 0);
222 if (shader->bo_fetch == NULL) {
223 return -ENOMEM;
224 }
225 ptr = r600_bo_map(rctx->radeon, shader->bo_fetch, 0, NULL);
226 memcpy(ptr, rshader->bc_fetch.bytecode, rshader->bc_fetch.ndw * 4);
227 r600_bo_unmap(rctx->radeon, shader->bo_fetch);
228 }
229 if (shader->bo == NULL) {
230 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
231 if (shader->bo == NULL) {
232 return -ENOMEM;
233 }
234 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
235 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
236 r600_bo_unmap(rctx->radeon, shader->bo);
237 }
238 /* build state */
239 rshader->flat_shade = rctx->flatshade;
240 switch (rshader->processor_type) {
241 case TGSI_PROCESSOR_VERTEX:
242 if (rshader->family >= CHIP_CEDAR) {
243 evergreen_pipe_shader_vs(ctx, shader);
244 } else {
245 r600_pipe_shader_vs(ctx, shader);
246 }
247 break;
248 case TGSI_PROCESSOR_FRAGMENT:
249 if (rshader->family >= CHIP_CEDAR) {
250 evergreen_pipe_shader_ps(ctx, shader);
251 } else {
252 r600_pipe_shader_ps(ctx, shader);
253 }
254 break;
255 default:
256 return -EINVAL;
257 }
258 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
259 return 0;
260 }
261
262 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
263 {
264 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
265 struct r600_shader *shader = &rshader->shader;
266 const struct util_format_description *desc;
267 enum pipe_format resource_format[160];
268 unsigned i, nresources = 0;
269 struct r600_bc *bc = &shader->bc_fetch;
270 struct r600_bc_cf *cf;
271 struct r600_bc_vtx *vtx;
272
273 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
274 return 0;
275 /* doing a full memcmp fell over the refcount */
276 if ((rshader->vertex_elements.count == rctx->vertex_elements->count) &&
277 (!memcmp(&rshader->vertex_elements.elements, &rctx->vertex_elements->elements, 32 * sizeof(struct pipe_vertex_element)))) {
278 return 0;
279 }
280 rshader->vertex_elements = *rctx->vertex_elements;
281 for (i = 0; i < rctx->vertex_elements->count; i++) {
282 resource_format[nresources++] = rctx->vertex_elements->hw_format[i];
283 }
284 r600_bo_reference(rctx->radeon, &rshader->bo_fetch, NULL);
285 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
286 switch (cf->inst) {
287 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
288 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
289 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
290 desc = util_format_description(resource_format[vtx->buffer_id]);
291 if (desc == NULL) {
292 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
293 return -EINVAL;
294 }
295 vtx->dst_sel_x = desc->swizzle[0];
296 vtx->dst_sel_y = desc->swizzle[1];
297 vtx->dst_sel_z = desc->swizzle[2];
298 vtx->dst_sel_w = desc->swizzle[3];
299 }
300 break;
301 default:
302 break;
303 }
304 }
305 return r600_bc_build(&shader->bc_fetch);
306 }
307
308 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
309 {
310 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
311 int r;
312
313 if (shader == NULL)
314 return -EINVAL;
315 /* there should be enough input */
316 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
317 R600_ERR("%d resources provided, expecting %d\n",
318 rctx->vertex_elements->count, shader->shader.bc.nresource);
319 return -EINVAL;
320 }
321 r = r600_shader_update(ctx, shader);
322 if (r)
323 return r;
324 return r600_pipe_shader(ctx, shader);
325 }
326
327 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
328 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
329 {
330 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
331 int r;
332
333 //fprintf(stderr, "--------------------------------------------------------------\n");
334 //tgsi_dump(tokens, 0);
335 shader->shader.family = r600_get_family(rctx->radeon);
336 r = r600_shader_from_tgsi(tokens, &shader->shader);
337 if (r) {
338 R600_ERR("translation from TGSI failed !\n");
339 return r;
340 }
341 r = r600_bc_build(&shader->shader.bc);
342 if (r) {
343 R600_ERR("building bytecode failed !\n");
344 return r;
345 }
346 if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) {
347 r = r600_bc_build(&shader->shader.bc_fetch);
348 if (r) {
349 R600_ERR("building bytecode failed !\n");
350 return r;
351 }
352 }
353 //fprintf(stderr, "______________________________________________________________\n");
354 return 0;
355 }
356
357 void
358 r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
359 {
360 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
361
362 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
363
364 r600_bc_clear(&shader->shader.bc);
365
366 /* FIXME: is there more stuff to free? */
367 }
368
369 /*
370 * tgsi -> r600 shader
371 */
372 struct r600_shader_tgsi_instruction;
373
374 struct r600_shader_ctx {
375 struct tgsi_shader_info info;
376 struct tgsi_parse_context parse;
377 const struct tgsi_token *tokens;
378 unsigned type;
379 unsigned file_offset[TGSI_FILE_COUNT];
380 unsigned temp_reg;
381 struct r600_shader_tgsi_instruction *inst_info;
382 struct r600_bc *bc;
383 struct r600_bc *bc_fetch;
384 struct r600_shader *shader;
385 u32 value[4];
386 u32 *literals;
387 u32 nliterals;
388 u32 max_driver_temp_used;
389 /* needed for evergreen interpolation */
390 boolean input_centroid;
391 boolean input_linear;
392 boolean input_perspective;
393 int num_interp_gpr;
394 };
395
396 struct r600_shader_tgsi_instruction {
397 unsigned tgsi_opcode;
398 unsigned is_op3;
399 unsigned r600_opcode;
400 int (*process)(struct r600_shader_ctx *ctx);
401 };
402
403 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
404 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
405
406 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
407 {
408 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
409 int j;
410
411 if (i->Instruction.NumDstRegs > 1) {
412 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
413 return -EINVAL;
414 }
415 if (i->Instruction.Predicate) {
416 R600_ERR("predicate unsupported\n");
417 return -EINVAL;
418 }
419 #if 0
420 if (i->Instruction.Label) {
421 R600_ERR("label unsupported\n");
422 return -EINVAL;
423 }
424 #endif
425 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
426 if (i->Src[j].Register.Dimension) {
427 R600_ERR("unsupported src %d (dimension %d)\n", j,
428 i->Src[j].Register.Dimension);
429 return -EINVAL;
430 }
431 }
432 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
433 if (i->Dst[j].Register.Dimension) {
434 R600_ERR("unsupported dst (dimension)\n");
435 return -EINVAL;
436 }
437 }
438 return 0;
439 }
440
441 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
442 {
443 int i, r;
444 struct r600_bc_alu alu;
445 int gpr = 0, base_chan = 0;
446 int ij_index = 0;
447
448 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
449 ij_index = 0;
450 if (ctx->shader->input[input].centroid)
451 ij_index++;
452 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
453 ij_index = 0;
454 /* if we have perspective add one */
455 if (ctx->input_perspective) {
456 ij_index++;
457 /* if we have perspective centroid */
458 if (ctx->input_centroid)
459 ij_index++;
460 }
461 if (ctx->shader->input[input].centroid)
462 ij_index++;
463 }
464
465 /* work out gpr and base_chan from index */
466 gpr = ij_index / 2;
467 base_chan = (2 * (ij_index % 2)) + 1;
468
469 for (i = 0; i < 8; i++) {
470 memset(&alu, 0, sizeof(struct r600_bc_alu));
471
472 if (i < 4)
473 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
474 else
475 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
476
477 if ((i > 1) && (i < 6)) {
478 alu.dst.sel = ctx->shader->input[input].gpr;
479 alu.dst.write = 1;
480 }
481
482 alu.dst.chan = i % 4;
483
484 alu.src[0].sel = gpr;
485 alu.src[0].chan = (base_chan - (i % 2));
486
487 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
488
489 alu.bank_swizzle_force = SQ_ALU_VEC_210;
490 if ((i % 4) == 3)
491 alu.last = 1;
492 r = r600_bc_add_alu(ctx->bc, &alu);
493 if (r)
494 return r;
495 }
496 return 0;
497 }
498
499
500 static int tgsi_declaration(struct r600_shader_ctx *ctx)
501 {
502 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
503 struct r600_bc_vtx vtx;
504 unsigned i;
505 int r;
506
507 switch (d->Declaration.File) {
508 case TGSI_FILE_INPUT:
509 i = ctx->shader->ninput++;
510 ctx->shader->input[i].name = d->Semantic.Name;
511 ctx->shader->input[i].sid = d->Semantic.Index;
512 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
513 ctx->shader->input[i].centroid = d->Declaration.Centroid;
514 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
515 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
516 /* turn input into fetch */
517 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
518 vtx.inst = 0;
519 vtx.fetch_type = 0;
520 vtx.buffer_id = i;
521 /* register containing the index into the buffer */
522 vtx.src_gpr = 0;
523 vtx.src_sel_x = 0;
524 vtx.mega_fetch_count = 0x1F;
525 vtx.dst_gpr = ctx->shader->input[i].gpr;
526 vtx.dst_sel_x = 0;
527 vtx.dst_sel_y = 1;
528 vtx.dst_sel_z = 2;
529 vtx.dst_sel_w = 3;
530 vtx.use_const_fields = 1;
531 r = r600_bc_add_vtx(ctx->bc_fetch, &vtx);
532 if (r)
533 return r;
534 }
535 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
536 /* turn input into interpolate on EG */
537 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
538 if (ctx->shader->input[i].interpolate > 0) {
539 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
540 evergreen_interp_alu(ctx, i);
541 }
542 }
543 }
544 break;
545 case TGSI_FILE_OUTPUT:
546 i = ctx->shader->noutput++;
547 ctx->shader->output[i].name = d->Semantic.Name;
548 ctx->shader->output[i].sid = d->Semantic.Index;
549 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
550 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
551 break;
552 case TGSI_FILE_CONSTANT:
553 case TGSI_FILE_TEMPORARY:
554 case TGSI_FILE_SAMPLER:
555 case TGSI_FILE_ADDRESS:
556 break;
557 default:
558 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
559 return -EINVAL;
560 }
561 return 0;
562 }
563
564 static int r600_get_temp(struct r600_shader_ctx *ctx)
565 {
566 return ctx->temp_reg + ctx->max_driver_temp_used++;
567 }
568
569 /*
570 * for evergreen we need to scan the shader to find the number of GPRs we need to
571 * reserve for interpolation.
572 *
573 * we need to know if we are going to emit
574 * any centroid inputs
575 * if perspective and linear are required
576 */
577 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
578 {
579 int i;
580 int num_baryc;
581
582 ctx->input_linear = FALSE;
583 ctx->input_perspective = FALSE;
584 ctx->input_centroid = FALSE;
585 ctx->num_interp_gpr = 1;
586
587 /* any centroid inputs */
588 for (i = 0; i < ctx->info.num_inputs; i++) {
589 /* skip position/face */
590 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
591 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
592 continue;
593 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
594 ctx->input_linear = TRUE;
595 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
596 ctx->input_perspective = TRUE;
597 if (ctx->info.input_centroid[i])
598 ctx->input_centroid = TRUE;
599 }
600
601 num_baryc = 0;
602 /* ignoring sample for now */
603 if (ctx->input_perspective)
604 num_baryc++;
605 if (ctx->input_linear)
606 num_baryc++;
607 if (ctx->input_centroid)
608 num_baryc *= 2;
609
610 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
611
612 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
613 return ctx->num_interp_gpr;
614 }
615
616 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
617 {
618 struct tgsi_full_immediate *immediate;
619 struct r600_shader_ctx ctx;
620 struct r600_bc_output output[32];
621 unsigned output_done, noutput;
622 unsigned opcode;
623 int i, r = 0, pos0;
624
625 ctx.bc = &shader->bc;
626 ctx.bc_fetch = &shader->bc_fetch;
627 ctx.shader = shader;
628 r = r600_bc_init(ctx.bc, shader->family);
629 if (r)
630 return r;
631 ctx.tokens = tokens;
632 tgsi_scan_shader(tokens, &ctx.info);
633 tgsi_parse_init(&ctx.parse, tokens);
634 ctx.type = ctx.parse.FullHeader.Processor.Processor;
635 shader->processor_type = ctx.type;
636 if (shader->processor_type == TGSI_PROCESSOR_VERTEX) {
637 r = r600_bc_init(ctx.bc_fetch, shader->family);
638 if (r)
639 return r;
640 ctx.bc_fetch->type = -1;
641 }
642 ctx.bc->type = shader->processor_type;
643
644 /* register allocations */
645 /* Values [0,127] correspond to GPR[0..127].
646 * Values [128,159] correspond to constant buffer bank 0
647 * Values [160,191] correspond to constant buffer bank 1
648 * Values [256,511] correspond to cfile constants c[0..255].
649 * Other special values are shown in the list below.
650 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
651 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
652 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
653 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
654 * 248 SQ_ALU_SRC_0: special constant 0.0.
655 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
656 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
657 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
658 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
659 * 253 SQ_ALU_SRC_LITERAL: literal constant.
660 * 254 SQ_ALU_SRC_PV: previous vector result.
661 * 255 SQ_ALU_SRC_PS: previous scalar result.
662 */
663 for (i = 0; i < TGSI_FILE_COUNT; i++) {
664 ctx.file_offset[i] = 0;
665 }
666 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
667 ctx.file_offset[TGSI_FILE_INPUT] = 1;
668 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
669 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
670 } else {
671 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
672 }
673 }
674 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
675 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
676 }
677 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
678 ctx.info.file_count[TGSI_FILE_INPUT];
679 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
680 ctx.info.file_count[TGSI_FILE_OUTPUT];
681
682 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
683
684 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
685 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
686 ctx.info.file_count[TGSI_FILE_TEMPORARY];
687
688 ctx.nliterals = 0;
689 ctx.literals = NULL;
690
691 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
692 tgsi_parse_token(&ctx.parse);
693 switch (ctx.parse.FullToken.Token.Type) {
694 case TGSI_TOKEN_TYPE_IMMEDIATE:
695 immediate = &ctx.parse.FullToken.FullImmediate;
696 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
697 if(ctx.literals == NULL) {
698 r = -ENOMEM;
699 goto out_err;
700 }
701 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
702 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
703 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
704 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
705 ctx.nliterals++;
706 break;
707 case TGSI_TOKEN_TYPE_DECLARATION:
708 r = tgsi_declaration(&ctx);
709 if (r)
710 goto out_err;
711 break;
712 case TGSI_TOKEN_TYPE_INSTRUCTION:
713 r = tgsi_is_supported(&ctx);
714 if (r)
715 goto out_err;
716 ctx.max_driver_temp_used = 0;
717 /* reserve first tmp for everyone */
718 r600_get_temp(&ctx);
719 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
720 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
721 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
722 else
723 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
724 r = ctx.inst_info->process(&ctx);
725 if (r)
726 goto out_err;
727 r = r600_bc_add_literal(ctx.bc, ctx.value);
728 if (r)
729 goto out_err;
730 break;
731 default:
732 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
733 r = -EINVAL;
734 goto out_err;
735 }
736 }
737 /* export output */
738 noutput = shader->noutput;
739 for (i = 0, pos0 = 0; i < noutput; i++) {
740 memset(&output[i], 0, sizeof(struct r600_bc_output));
741 output[i].gpr = shader->output[i].gpr;
742 output[i].elem_size = 3;
743 output[i].swizzle_x = 0;
744 output[i].swizzle_y = 1;
745 output[i].swizzle_z = 2;
746 output[i].swizzle_w = 3;
747 output[i].barrier = 1;
748 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
749 output[i].array_base = i - pos0;
750 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
751 switch (ctx.type) {
752 case TGSI_PROCESSOR_VERTEX:
753 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
754 output[i].array_base = 60;
755 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
756 /* position doesn't count in array_base */
757 pos0++;
758 }
759 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
760 output[i].array_base = 61;
761 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
762 /* position doesn't count in array_base */
763 pos0++;
764 }
765 break;
766 case TGSI_PROCESSOR_FRAGMENT:
767 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
768 output[i].array_base = shader->output[i].sid;
769 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
770 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
771 output[i].array_base = 61;
772 output[i].swizzle_x = 2;
773 output[i].swizzle_y = 7;
774 output[i].swizzle_z = output[i].swizzle_w = 7;
775 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
776 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
777 output[i].array_base = 61;
778 output[i].swizzle_x = 7;
779 output[i].swizzle_y = 1;
780 output[i].swizzle_z = output[i].swizzle_w = 7;
781 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
782 } else {
783 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
784 r = -EINVAL;
785 goto out_err;
786 }
787 break;
788 default:
789 R600_ERR("unsupported processor type %d\n", ctx.type);
790 r = -EINVAL;
791 goto out_err;
792 }
793 }
794 /* add fake param output for vertex shader if no param is exported */
795 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
796 for (i = 0, pos0 = 0; i < noutput; i++) {
797 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
798 pos0 = 1;
799 break;
800 }
801 }
802 if (!pos0) {
803 memset(&output[i], 0, sizeof(struct r600_bc_output));
804 output[i].gpr = 0;
805 output[i].elem_size = 3;
806 output[i].swizzle_x = 0;
807 output[i].swizzle_y = 1;
808 output[i].swizzle_z = 2;
809 output[i].swizzle_w = 3;
810 output[i].barrier = 1;
811 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
812 output[i].array_base = 0;
813 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
814 noutput++;
815 }
816 }
817 /* add fake pixel export */
818 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
819 memset(&output[0], 0, sizeof(struct r600_bc_output));
820 output[0].gpr = 0;
821 output[0].elem_size = 3;
822 output[0].swizzle_x = 7;
823 output[0].swizzle_y = 7;
824 output[0].swizzle_z = 7;
825 output[0].swizzle_w = 7;
826 output[0].barrier = 1;
827 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
828 output[0].array_base = 0;
829 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
830 noutput++;
831 }
832 /* set export done on last export of each type */
833 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
834 if (i == (noutput - 1)) {
835 output[i].end_of_program = 1;
836 }
837 if (!(output_done & (1 << output[i].type))) {
838 output_done |= (1 << output[i].type);
839 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
840 }
841 }
842 /* add return to fetch shader */
843 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
844 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
845 r600_bc_add_cfinst(ctx.bc_fetch, EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
846 } else {
847 r600_bc_add_cfinst(ctx.bc_fetch, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
848 }
849 }
850 /* add output to bytecode */
851 for (i = 0; i < noutput; i++) {
852 r = r600_bc_add_output(ctx.bc, &output[i]);
853 if (r)
854 goto out_err;
855 }
856 free(ctx.literals);
857 tgsi_parse_free(&ctx.parse);
858 return 0;
859 out_err:
860 free(ctx.literals);
861 tgsi_parse_free(&ctx.parse);
862 return r;
863 }
864
865 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
866 {
867 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
868 return -EINVAL;
869 }
870
871 static int tgsi_end(struct r600_shader_ctx *ctx)
872 {
873 return 0;
874 }
875
876 static int tgsi_src(struct r600_shader_ctx *ctx,
877 const struct tgsi_full_src_register *tgsi_src,
878 struct r600_bc_alu_src *r600_src)
879 {
880 int index;
881 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
882 r600_src->sel = tgsi_src->Register.Index;
883 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
884 r600_src->sel = 0;
885 index = tgsi_src->Register.Index;
886 ctx->value[0] = ctx->literals[index * 4 + 0];
887 ctx->value[1] = ctx->literals[index * 4 + 1];
888 ctx->value[2] = ctx->literals[index * 4 + 2];
889 ctx->value[3] = ctx->literals[index * 4 + 3];
890 }
891 if (tgsi_src->Register.Indirect)
892 r600_src->rel = V_SQ_REL_RELATIVE;
893 r600_src->neg = tgsi_src->Register.Negate;
894 r600_src->abs = tgsi_src->Register.Absolute;
895 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
896 return 0;
897 }
898
899 static int tgsi_dst(struct r600_shader_ctx *ctx,
900 const struct tgsi_full_dst_register *tgsi_dst,
901 unsigned swizzle,
902 struct r600_bc_alu_dst *r600_dst)
903 {
904 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
905
906 r600_dst->sel = tgsi_dst->Register.Index;
907 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
908 r600_dst->chan = swizzle;
909 r600_dst->write = 1;
910 if (tgsi_dst->Register.Indirect)
911 r600_dst->rel = V_SQ_REL_RELATIVE;
912 if (inst->Instruction.Saturate) {
913 r600_dst->clamp = 1;
914 }
915 return 0;
916 }
917
918 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
919 {
920 switch (swizzle) {
921 case 0:
922 return tgsi_src->Register.SwizzleX;
923 case 1:
924 return tgsi_src->Register.SwizzleY;
925 case 2:
926 return tgsi_src->Register.SwizzleZ;
927 case 3:
928 return tgsi_src->Register.SwizzleW;
929 default:
930 return 0;
931 }
932 }
933
934 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
935 {
936 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
937 struct r600_bc_alu alu;
938 int i, j, k, nconst, r;
939
940 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
941 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
942 nconst++;
943 }
944 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
945 if (r) {
946 return r;
947 }
948 }
949 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
950 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
951 int treg = r600_get_temp(ctx);
952 for (k = 0; k < 4; k++) {
953 memset(&alu, 0, sizeof(struct r600_bc_alu));
954 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
955 alu.src[0].sel = r600_src[i].sel;
956 alu.src[0].chan = k;
957 alu.src[0].rel = r600_src[i].rel;
958 alu.dst.sel = treg;
959 alu.dst.chan = k;
960 alu.dst.write = 1;
961 if (k == 3)
962 alu.last = 1;
963 r = r600_bc_add_alu(ctx->bc, &alu);
964 if (r)
965 return r;
966 }
967 r600_src[i].sel = treg;
968 r600_src[i].rel =0;
969 j--;
970 }
971 }
972 return 0;
973 }
974
975 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
976 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
977 {
978 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
979 struct r600_bc_alu alu;
980 int i, j, k, nliteral, r;
981
982 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
983 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
984 nliteral++;
985 }
986 }
987 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
988 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
989 int treg = r600_get_temp(ctx);
990 for (k = 0; k < 4; k++) {
991 memset(&alu, 0, sizeof(struct r600_bc_alu));
992 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
993 alu.src[0].sel = r600_src[i].sel;
994 alu.src[0].chan = k;
995 alu.dst.sel = treg;
996 alu.dst.chan = k;
997 alu.dst.write = 1;
998 if (k == 3)
999 alu.last = 1;
1000 r = r600_bc_add_alu(ctx->bc, &alu);
1001 if (r)
1002 return r;
1003 }
1004 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
1005 if (r)
1006 return r;
1007 r600_src[i].sel = treg;
1008 j--;
1009 }
1010 }
1011 return 0;
1012 }
1013
1014 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
1015 {
1016 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1017 struct r600_bc_alu_src r600_src[3];
1018 struct r600_bc_alu alu;
1019 int i, j, r;
1020 int lasti = 0;
1021
1022 for (i = 0; i < 4; i++) {
1023 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
1024 lasti = i;
1025 }
1026 }
1027
1028 r = tgsi_split_constant(ctx, r600_src);
1029 if (r)
1030 return r;
1031 r = tgsi_split_literal_constant(ctx, r600_src);
1032 if (r)
1033 return r;
1034 for (i = 0; i < lasti + 1; i++) {
1035 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1036 continue;
1037
1038 memset(&alu, 0, sizeof(struct r600_bc_alu));
1039 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1040 if (r)
1041 return r;
1042
1043 alu.inst = ctx->inst_info->r600_opcode;
1044 if (!swap) {
1045 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1046 alu.src[j] = r600_src[j];
1047 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1048 }
1049 } else {
1050 alu.src[0] = r600_src[1];
1051 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
1052
1053 alu.src[1] = r600_src[0];
1054 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1055 }
1056 /* handle some special cases */
1057 switch (ctx->inst_info->tgsi_opcode) {
1058 case TGSI_OPCODE_SUB:
1059 alu.src[1].neg = 1;
1060 break;
1061 case TGSI_OPCODE_ABS:
1062 alu.src[0].abs = 1;
1063 break;
1064 default:
1065 break;
1066 }
1067 if (i == lasti) {
1068 alu.last = 1;
1069 }
1070 r = r600_bc_add_alu(ctx->bc, &alu);
1071 if (r)
1072 return r;
1073 }
1074 return 0;
1075 }
1076
1077 static int tgsi_op2(struct r600_shader_ctx *ctx)
1078 {
1079 return tgsi_op2_s(ctx, 0);
1080 }
1081
1082 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1083 {
1084 return tgsi_op2_s(ctx, 1);
1085 }
1086
1087 /*
1088 * r600 - trunc to -PI..PI range
1089 * r700 - normalize by dividing by 2PI
1090 * see fdo bug 27901
1091 */
1092 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
1093 struct r600_bc_alu_src r600_src[3])
1094 {
1095 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1096 int r;
1097 uint32_t lit_vals[4];
1098 struct r600_bc_alu alu;
1099
1100 memset(lit_vals, 0, 4*4);
1101 r = tgsi_split_constant(ctx, r600_src);
1102 if (r)
1103 return r;
1104 r = tgsi_split_literal_constant(ctx, r600_src);
1105 if (r)
1106 return r;
1107
1108 r = tgsi_split_literal_constant(ctx, r600_src);
1109 if (r)
1110 return r;
1111
1112 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
1113 lit_vals[1] = fui(0.5f);
1114
1115 memset(&alu, 0, sizeof(struct r600_bc_alu));
1116 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1117 alu.is_op3 = 1;
1118
1119 alu.dst.chan = 0;
1120 alu.dst.sel = ctx->temp_reg;
1121 alu.dst.write = 1;
1122
1123 alu.src[0] = r600_src[0];
1124 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1125
1126 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1127 alu.src[1].chan = 0;
1128 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1129 alu.src[2].chan = 1;
1130 alu.last = 1;
1131 r = r600_bc_add_alu(ctx->bc, &alu);
1132 if (r)
1133 return r;
1134 r = r600_bc_add_literal(ctx->bc, lit_vals);
1135 if (r)
1136 return r;
1137
1138 memset(&alu, 0, sizeof(struct r600_bc_alu));
1139 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1140
1141 alu.dst.chan = 0;
1142 alu.dst.sel = ctx->temp_reg;
1143 alu.dst.write = 1;
1144
1145 alu.src[0].sel = ctx->temp_reg;
1146 alu.src[0].chan = 0;
1147 alu.last = 1;
1148 r = r600_bc_add_alu(ctx->bc, &alu);
1149 if (r)
1150 return r;
1151
1152 if (ctx->bc->chiprev == CHIPREV_R600) {
1153 lit_vals[0] = fui(3.1415926535897f * 2.0f);
1154 lit_vals[1] = fui(-3.1415926535897f);
1155 } else {
1156 lit_vals[0] = fui(1.0f);
1157 lit_vals[1] = fui(-0.5f);
1158 }
1159
1160 memset(&alu, 0, sizeof(struct r600_bc_alu));
1161 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1162 alu.is_op3 = 1;
1163
1164 alu.dst.chan = 0;
1165 alu.dst.sel = ctx->temp_reg;
1166 alu.dst.write = 1;
1167
1168 alu.src[0].sel = ctx->temp_reg;
1169 alu.src[0].chan = 0;
1170
1171 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1172 alu.src[1].chan = 0;
1173 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1174 alu.src[2].chan = 1;
1175 alu.last = 1;
1176 r = r600_bc_add_alu(ctx->bc, &alu);
1177 if (r)
1178 return r;
1179 r = r600_bc_add_literal(ctx->bc, lit_vals);
1180 if (r)
1181 return r;
1182 return 0;
1183 }
1184
1185 static int tgsi_trig(struct r600_shader_ctx *ctx)
1186 {
1187 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1188 struct r600_bc_alu_src r600_src[3];
1189 struct r600_bc_alu alu;
1190 int i, r;
1191 int lasti = 0;
1192
1193 r = tgsi_setup_trig(ctx, r600_src);
1194 if (r)
1195 return r;
1196
1197 memset(&alu, 0, sizeof(struct r600_bc_alu));
1198 alu.inst = ctx->inst_info->r600_opcode;
1199 alu.dst.chan = 0;
1200 alu.dst.sel = ctx->temp_reg;
1201 alu.dst.write = 1;
1202
1203 alu.src[0].sel = ctx->temp_reg;
1204 alu.src[0].chan = 0;
1205 alu.last = 1;
1206 r = r600_bc_add_alu(ctx->bc, &alu);
1207 if (r)
1208 return r;
1209
1210 /* replicate result */
1211 for (i = 0; i < 4; i++) {
1212 if (inst->Dst[0].Register.WriteMask & (1 << i))
1213 lasti = i;
1214 }
1215 for (i = 0; i < lasti + 1; i++) {
1216 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1217 continue;
1218
1219 memset(&alu, 0, sizeof(struct r600_bc_alu));
1220 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1221
1222 alu.src[0].sel = ctx->temp_reg;
1223 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1224 if (r)
1225 return r;
1226 if (i == lasti)
1227 alu.last = 1;
1228 r = r600_bc_add_alu(ctx->bc, &alu);
1229 if (r)
1230 return r;
1231 }
1232 return 0;
1233 }
1234
1235 static int tgsi_scs(struct r600_shader_ctx *ctx)
1236 {
1237 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1238 struct r600_bc_alu_src r600_src[3];
1239 struct r600_bc_alu alu;
1240 int r;
1241
1242 /* We'll only need the trig stuff if we are going to write to the
1243 * X or Y components of the destination vector.
1244 */
1245 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1246 r = tgsi_setup_trig(ctx, r600_src);
1247 if (r)
1248 return r;
1249 }
1250
1251 /* dst.x = COS */
1252 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1253 memset(&alu, 0, sizeof(struct r600_bc_alu));
1254 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1255 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1256 if (r)
1257 return r;
1258
1259 alu.src[0].sel = ctx->temp_reg;
1260 alu.src[0].chan = 0;
1261 alu.last = 1;
1262 r = r600_bc_add_alu(ctx->bc, &alu);
1263 if (r)
1264 return r;
1265 }
1266
1267 /* dst.y = SIN */
1268 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1269 memset(&alu, 0, sizeof(struct r600_bc_alu));
1270 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1271 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1272 if (r)
1273 return r;
1274
1275 alu.src[0].sel = ctx->temp_reg;
1276 alu.src[0].chan = 0;
1277 alu.last = 1;
1278 r = r600_bc_add_alu(ctx->bc, &alu);
1279 if (r)
1280 return r;
1281 }
1282
1283 /* dst.z = 0.0; */
1284 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1285 memset(&alu, 0, sizeof(struct r600_bc_alu));
1286
1287 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1288
1289 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1290 if (r)
1291 return r;
1292
1293 alu.src[0].sel = V_SQ_ALU_SRC_0;
1294 alu.src[0].chan = 0;
1295
1296 alu.last = 1;
1297
1298 r = r600_bc_add_alu(ctx->bc, &alu);
1299 if (r)
1300 return r;
1301
1302 r = r600_bc_add_literal(ctx->bc, ctx->value);
1303 if (r)
1304 return r;
1305 }
1306
1307 /* dst.w = 1.0; */
1308 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1309 memset(&alu, 0, sizeof(struct r600_bc_alu));
1310
1311 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1312
1313 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1314 if (r)
1315 return r;
1316
1317 alu.src[0].sel = V_SQ_ALU_SRC_1;
1318 alu.src[0].chan = 0;
1319
1320 alu.last = 1;
1321
1322 r = r600_bc_add_alu(ctx->bc, &alu);
1323 if (r)
1324 return r;
1325
1326 r = r600_bc_add_literal(ctx->bc, ctx->value);
1327 if (r)
1328 return r;
1329 }
1330
1331 return 0;
1332 }
1333
1334 static int tgsi_kill(struct r600_shader_ctx *ctx)
1335 {
1336 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1337 struct r600_bc_alu alu;
1338 int i, r;
1339
1340 for (i = 0; i < 4; i++) {
1341 memset(&alu, 0, sizeof(struct r600_bc_alu));
1342 alu.inst = ctx->inst_info->r600_opcode;
1343
1344 alu.dst.chan = i;
1345
1346 alu.src[0].sel = V_SQ_ALU_SRC_0;
1347
1348 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1349 alu.src[1].sel = V_SQ_ALU_SRC_1;
1350 alu.src[1].neg = 1;
1351 } else {
1352 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1353 if (r)
1354 return r;
1355 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1356 }
1357 if (i == 3) {
1358 alu.last = 1;
1359 }
1360 r = r600_bc_add_alu(ctx->bc, &alu);
1361 if (r)
1362 return r;
1363 }
1364 r = r600_bc_add_literal(ctx->bc, ctx->value);
1365 if (r)
1366 return r;
1367
1368 /* kill must be last in ALU */
1369 ctx->bc->force_add_cf = 1;
1370 ctx->shader->uses_kill = TRUE;
1371 return 0;
1372 }
1373
1374 static int tgsi_lit(struct r600_shader_ctx *ctx)
1375 {
1376 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1377 struct r600_bc_alu alu;
1378 struct r600_bc_alu_src r600_src[3];
1379 int r;
1380
1381 r = tgsi_split_constant(ctx, r600_src);
1382 if (r)
1383 return r;
1384 r = tgsi_split_literal_constant(ctx, r600_src);
1385 if (r)
1386 return r;
1387
1388 /* dst.x, <- 1.0 */
1389 memset(&alu, 0, sizeof(struct r600_bc_alu));
1390 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1391 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1392 alu.src[0].chan = 0;
1393 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1394 if (r)
1395 return r;
1396 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1397 r = r600_bc_add_alu(ctx->bc, &alu);
1398 if (r)
1399 return r;
1400
1401 /* dst.y = max(src.x, 0.0) */
1402 memset(&alu, 0, sizeof(struct r600_bc_alu));
1403 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1404 alu.src[0] = r600_src[0];
1405 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1406 alu.src[1].chan = 0;
1407 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1408 if (r)
1409 return r;
1410 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1411 r = r600_bc_add_alu(ctx->bc, &alu);
1412 if (r)
1413 return r;
1414
1415 /* dst.w, <- 1.0 */
1416 memset(&alu, 0, sizeof(struct r600_bc_alu));
1417 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1418 alu.src[0].sel = V_SQ_ALU_SRC_1;
1419 alu.src[0].chan = 0;
1420 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1421 if (r)
1422 return r;
1423 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1424 alu.last = 1;
1425 r = r600_bc_add_alu(ctx->bc, &alu);
1426 if (r)
1427 return r;
1428
1429 r = r600_bc_add_literal(ctx->bc, ctx->value);
1430 if (r)
1431 return r;
1432
1433 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1434 {
1435 int chan;
1436 int sel;
1437
1438 /* dst.z = log(src.y) */
1439 memset(&alu, 0, sizeof(struct r600_bc_alu));
1440 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1441 alu.src[0] = r600_src[0];
1442 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1443 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1444 if (r)
1445 return r;
1446 alu.last = 1;
1447 r = r600_bc_add_alu(ctx->bc, &alu);
1448 if (r)
1449 return r;
1450
1451 r = r600_bc_add_literal(ctx->bc, ctx->value);
1452 if (r)
1453 return r;
1454
1455 chan = alu.dst.chan;
1456 sel = alu.dst.sel;
1457
1458 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1459 memset(&alu, 0, sizeof(struct r600_bc_alu));
1460 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1461 alu.src[0] = r600_src[0];
1462 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1463 alu.src[1].sel = sel;
1464 alu.src[1].chan = chan;
1465
1466 alu.src[2] = r600_src[0];
1467 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1468 alu.dst.sel = ctx->temp_reg;
1469 alu.dst.chan = 0;
1470 alu.dst.write = 1;
1471 alu.is_op3 = 1;
1472 alu.last = 1;
1473 r = r600_bc_add_alu(ctx->bc, &alu);
1474 if (r)
1475 return r;
1476
1477 r = r600_bc_add_literal(ctx->bc, ctx->value);
1478 if (r)
1479 return r;
1480 /* dst.z = exp(tmp.x) */
1481 memset(&alu, 0, sizeof(struct r600_bc_alu));
1482 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1483 alu.src[0].sel = ctx->temp_reg;
1484 alu.src[0].chan = 0;
1485 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1486 if (r)
1487 return r;
1488 alu.last = 1;
1489 r = r600_bc_add_alu(ctx->bc, &alu);
1490 if (r)
1491 return r;
1492 }
1493 return 0;
1494 }
1495
1496 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1497 {
1498 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1499 struct r600_bc_alu alu;
1500 int i, r;
1501
1502 memset(&alu, 0, sizeof(struct r600_bc_alu));
1503
1504 /* FIXME:
1505 * For state trackers other than OpenGL, we'll want to use
1506 * _RECIPSQRT_IEEE instead.
1507 */
1508 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1509
1510 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1511 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1512 if (r)
1513 return r;
1514 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1515 alu.src[i].abs = 1;
1516 }
1517 alu.dst.sel = ctx->temp_reg;
1518 alu.dst.write = 1;
1519 alu.last = 1;
1520 r = r600_bc_add_alu(ctx->bc, &alu);
1521 if (r)
1522 return r;
1523 r = r600_bc_add_literal(ctx->bc, ctx->value);
1524 if (r)
1525 return r;
1526 /* replicate result */
1527 return tgsi_helper_tempx_replicate(ctx);
1528 }
1529
1530 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1531 {
1532 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1533 struct r600_bc_alu alu;
1534 int i, r;
1535
1536 for (i = 0; i < 4; i++) {
1537 memset(&alu, 0, sizeof(struct r600_bc_alu));
1538 alu.src[0].sel = ctx->temp_reg;
1539 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1540 alu.dst.chan = i;
1541 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1542 if (r)
1543 return r;
1544 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1545 if (i == 3)
1546 alu.last = 1;
1547 r = r600_bc_add_alu(ctx->bc, &alu);
1548 if (r)
1549 return r;
1550 }
1551 return 0;
1552 }
1553
1554 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1555 {
1556 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1557 struct r600_bc_alu alu;
1558 int i, r;
1559
1560 memset(&alu, 0, sizeof(struct r600_bc_alu));
1561 alu.inst = ctx->inst_info->r600_opcode;
1562 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1563 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1564 if (r)
1565 return r;
1566 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1567 }
1568 alu.dst.sel = ctx->temp_reg;
1569 alu.dst.write = 1;
1570 alu.last = 1;
1571 r = r600_bc_add_alu(ctx->bc, &alu);
1572 if (r)
1573 return r;
1574 r = r600_bc_add_literal(ctx->bc, ctx->value);
1575 if (r)
1576 return r;
1577 /* replicate result */
1578 return tgsi_helper_tempx_replicate(ctx);
1579 }
1580
1581 static int tgsi_pow(struct r600_shader_ctx *ctx)
1582 {
1583 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1584 struct r600_bc_alu alu;
1585 int r;
1586
1587 /* LOG2(a) */
1588 memset(&alu, 0, sizeof(struct r600_bc_alu));
1589 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1590 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1591 if (r)
1592 return r;
1593 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1594 alu.dst.sel = ctx->temp_reg;
1595 alu.dst.write = 1;
1596 alu.last = 1;
1597 r = r600_bc_add_alu(ctx->bc, &alu);
1598 if (r)
1599 return r;
1600 r = r600_bc_add_literal(ctx->bc,ctx->value);
1601 if (r)
1602 return r;
1603 /* b * LOG2(a) */
1604 memset(&alu, 0, sizeof(struct r600_bc_alu));
1605 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1606 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1607 if (r)
1608 return r;
1609 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1610 alu.src[1].sel = ctx->temp_reg;
1611 alu.dst.sel = ctx->temp_reg;
1612 alu.dst.write = 1;
1613 alu.last = 1;
1614 r = r600_bc_add_alu(ctx->bc, &alu);
1615 if (r)
1616 return r;
1617 r = r600_bc_add_literal(ctx->bc,ctx->value);
1618 if (r)
1619 return r;
1620 /* POW(a,b) = EXP2(b * LOG2(a))*/
1621 memset(&alu, 0, sizeof(struct r600_bc_alu));
1622 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1623 alu.src[0].sel = ctx->temp_reg;
1624 alu.dst.sel = ctx->temp_reg;
1625 alu.dst.write = 1;
1626 alu.last = 1;
1627 r = r600_bc_add_alu(ctx->bc, &alu);
1628 if (r)
1629 return r;
1630 r = r600_bc_add_literal(ctx->bc,ctx->value);
1631 if (r)
1632 return r;
1633 return tgsi_helper_tempx_replicate(ctx);
1634 }
1635
1636 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1637 {
1638 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1639 struct r600_bc_alu alu;
1640 struct r600_bc_alu_src r600_src[3];
1641 int i, r;
1642
1643 r = tgsi_split_constant(ctx, r600_src);
1644 if (r)
1645 return r;
1646 r = tgsi_split_literal_constant(ctx, r600_src);
1647 if (r)
1648 return r;
1649
1650 /* tmp = (src > 0 ? 1 : src) */
1651 for (i = 0; i < 4; i++) {
1652 memset(&alu, 0, sizeof(struct r600_bc_alu));
1653 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1654 alu.is_op3 = 1;
1655
1656 alu.dst.sel = ctx->temp_reg;
1657 alu.dst.chan = i;
1658
1659 alu.src[0] = r600_src[0];
1660 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1661
1662 alu.src[1].sel = V_SQ_ALU_SRC_1;
1663
1664 alu.src[2] = r600_src[0];
1665 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1666 if (i == 3)
1667 alu.last = 1;
1668 r = r600_bc_add_alu(ctx->bc, &alu);
1669 if (r)
1670 return r;
1671 }
1672 r = r600_bc_add_literal(ctx->bc, ctx->value);
1673 if (r)
1674 return r;
1675
1676 /* dst = (-tmp > 0 ? -1 : tmp) */
1677 for (i = 0; i < 4; i++) {
1678 memset(&alu, 0, sizeof(struct r600_bc_alu));
1679 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1680 alu.is_op3 = 1;
1681 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1682 if (r)
1683 return r;
1684
1685 alu.src[0].sel = ctx->temp_reg;
1686 alu.src[0].chan = i;
1687 alu.src[0].neg = 1;
1688
1689 alu.src[1].sel = V_SQ_ALU_SRC_1;
1690 alu.src[1].neg = 1;
1691
1692 alu.src[2].sel = ctx->temp_reg;
1693 alu.src[2].chan = i;
1694
1695 if (i == 3)
1696 alu.last = 1;
1697 r = r600_bc_add_alu(ctx->bc, &alu);
1698 if (r)
1699 return r;
1700 }
1701 return 0;
1702 }
1703
1704 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1705 {
1706 struct r600_bc_alu alu;
1707 int i, r;
1708
1709 r = r600_bc_add_literal(ctx->bc, ctx->value);
1710 if (r)
1711 return r;
1712 for (i = 0; i < 4; i++) {
1713 memset(&alu, 0, sizeof(struct r600_bc_alu));
1714 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1715 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1716 alu.dst.chan = i;
1717 } else {
1718 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1719 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1720 if (r)
1721 return r;
1722 alu.src[0].sel = ctx->temp_reg;
1723 alu.src[0].chan = i;
1724 }
1725 if (i == 3) {
1726 alu.last = 1;
1727 }
1728 r = r600_bc_add_alu(ctx->bc, &alu);
1729 if (r)
1730 return r;
1731 }
1732 return 0;
1733 }
1734
1735 static int tgsi_op3(struct r600_shader_ctx *ctx)
1736 {
1737 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1738 struct r600_bc_alu_src r600_src[3];
1739 struct r600_bc_alu alu;
1740 int i, j, r;
1741
1742 r = tgsi_split_constant(ctx, r600_src);
1743 if (r)
1744 return r;
1745 r = tgsi_split_literal_constant(ctx, r600_src);
1746 if (r)
1747 return r;
1748 /* do it in 2 step as op3 doesn't support writemask */
1749 for (i = 0; i < 4; i++) {
1750 memset(&alu, 0, sizeof(struct r600_bc_alu));
1751 alu.inst = ctx->inst_info->r600_opcode;
1752 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1753 alu.src[j] = r600_src[j];
1754 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1755 }
1756 alu.dst.sel = ctx->temp_reg;
1757 alu.dst.chan = i;
1758 alu.dst.write = 1;
1759 alu.is_op3 = 1;
1760 if (i == 3) {
1761 alu.last = 1;
1762 }
1763 r = r600_bc_add_alu(ctx->bc, &alu);
1764 if (r)
1765 return r;
1766 }
1767 return tgsi_helper_copy(ctx, inst);
1768 }
1769
1770 static int tgsi_dp(struct r600_shader_ctx *ctx)
1771 {
1772 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1773 struct r600_bc_alu_src r600_src[3];
1774 struct r600_bc_alu alu;
1775 int i, j, r;
1776
1777 r = tgsi_split_constant(ctx, r600_src);
1778 if (r)
1779 return r;
1780 r = tgsi_split_literal_constant(ctx, r600_src);
1781 if (r)
1782 return r;
1783 for (i = 0; i < 4; i++) {
1784 memset(&alu, 0, sizeof(struct r600_bc_alu));
1785 alu.inst = ctx->inst_info->r600_opcode;
1786 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1787 alu.src[j] = r600_src[j];
1788 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1789 }
1790 alu.dst.sel = ctx->temp_reg;
1791 alu.dst.chan = i;
1792 alu.dst.write = 1;
1793 /* handle some special cases */
1794 switch (ctx->inst_info->tgsi_opcode) {
1795 case TGSI_OPCODE_DP2:
1796 if (i > 1) {
1797 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1798 alu.src[0].chan = alu.src[1].chan = 0;
1799 }
1800 break;
1801 case TGSI_OPCODE_DP3:
1802 if (i > 2) {
1803 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1804 alu.src[0].chan = alu.src[1].chan = 0;
1805 }
1806 break;
1807 case TGSI_OPCODE_DPH:
1808 if (i == 3) {
1809 alu.src[0].sel = V_SQ_ALU_SRC_1;
1810 alu.src[0].chan = 0;
1811 alu.src[0].neg = 0;
1812 }
1813 break;
1814 default:
1815 break;
1816 }
1817 if (i == 3) {
1818 alu.last = 1;
1819 }
1820 r = r600_bc_add_alu(ctx->bc, &alu);
1821 if (r)
1822 return r;
1823 }
1824 return tgsi_helper_copy(ctx, inst);
1825 }
1826
1827 static int tgsi_tex(struct r600_shader_ctx *ctx)
1828 {
1829 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1830 struct r600_bc_tex tex;
1831 struct r600_bc_alu alu;
1832 unsigned src_gpr;
1833 int r, i;
1834 int opcode;
1835 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1836 uint32_t lit_vals[4];
1837
1838 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1839
1840 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1841 /* Add perspective divide */
1842 memset(&alu, 0, sizeof(struct r600_bc_alu));
1843 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1844 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1845 if (r)
1846 return r;
1847
1848 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1849 alu.dst.sel = ctx->temp_reg;
1850 alu.dst.chan = 3;
1851 alu.last = 1;
1852 alu.dst.write = 1;
1853 r = r600_bc_add_alu(ctx->bc, &alu);
1854 if (r)
1855 return r;
1856
1857 for (i = 0; i < 3; i++) {
1858 memset(&alu, 0, sizeof(struct r600_bc_alu));
1859 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1860 alu.src[0].sel = ctx->temp_reg;
1861 alu.src[0].chan = 3;
1862 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1863 if (r)
1864 return r;
1865 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1866 alu.dst.sel = ctx->temp_reg;
1867 alu.dst.chan = i;
1868 alu.dst.write = 1;
1869 r = r600_bc_add_alu(ctx->bc, &alu);
1870 if (r)
1871 return r;
1872 }
1873 memset(&alu, 0, sizeof(struct r600_bc_alu));
1874 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1875 alu.src[0].sel = V_SQ_ALU_SRC_1;
1876 alu.src[0].chan = 0;
1877 alu.dst.sel = ctx->temp_reg;
1878 alu.dst.chan = 3;
1879 alu.last = 1;
1880 alu.dst.write = 1;
1881 r = r600_bc_add_alu(ctx->bc, &alu);
1882 if (r)
1883 return r;
1884 src_not_temp = FALSE;
1885 src_gpr = ctx->temp_reg;
1886 }
1887
1888 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1889 int src_chan, src2_chan;
1890
1891 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1892 for (i = 0; i < 4; i++) {
1893 memset(&alu, 0, sizeof(struct r600_bc_alu));
1894 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1895 switch (i) {
1896 case 0:
1897 src_chan = 2;
1898 src2_chan = 1;
1899 break;
1900 case 1:
1901 src_chan = 2;
1902 src2_chan = 0;
1903 break;
1904 case 2:
1905 src_chan = 0;
1906 src2_chan = 2;
1907 break;
1908 case 3:
1909 src_chan = 1;
1910 src2_chan = 2;
1911 break;
1912 default:
1913 assert(0);
1914 src_chan = 0;
1915 src2_chan = 0;
1916 break;
1917 }
1918 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1919 if (r)
1920 return r;
1921 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1922 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1923 if (r)
1924 return r;
1925 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1926 alu.dst.sel = ctx->temp_reg;
1927 alu.dst.chan = i;
1928 if (i == 3)
1929 alu.last = 1;
1930 alu.dst.write = 1;
1931 r = r600_bc_add_alu(ctx->bc, &alu);
1932 if (r)
1933 return r;
1934 }
1935
1936 /* tmp1.z = RCP_e(|tmp1.z|) */
1937 memset(&alu, 0, sizeof(struct r600_bc_alu));
1938 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1939 alu.src[0].sel = ctx->temp_reg;
1940 alu.src[0].chan = 2;
1941 alu.src[0].abs = 1;
1942 alu.dst.sel = ctx->temp_reg;
1943 alu.dst.chan = 2;
1944 alu.dst.write = 1;
1945 alu.last = 1;
1946 r = r600_bc_add_alu(ctx->bc, &alu);
1947 if (r)
1948 return r;
1949
1950 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1951 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1952 * muladd has no writemask, have to use another temp
1953 */
1954 memset(&alu, 0, sizeof(struct r600_bc_alu));
1955 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1956 alu.is_op3 = 1;
1957
1958 alu.src[0].sel = ctx->temp_reg;
1959 alu.src[0].chan = 0;
1960 alu.src[1].sel = ctx->temp_reg;
1961 alu.src[1].chan = 2;
1962
1963 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1964 alu.src[2].chan = 0;
1965
1966 alu.dst.sel = ctx->temp_reg;
1967 alu.dst.chan = 0;
1968 alu.dst.write = 1;
1969
1970 r = r600_bc_add_alu(ctx->bc, &alu);
1971 if (r)
1972 return r;
1973
1974 memset(&alu, 0, sizeof(struct r600_bc_alu));
1975 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1976 alu.is_op3 = 1;
1977
1978 alu.src[0].sel = ctx->temp_reg;
1979 alu.src[0].chan = 1;
1980 alu.src[1].sel = ctx->temp_reg;
1981 alu.src[1].chan = 2;
1982
1983 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1984 alu.src[2].chan = 0;
1985
1986 alu.dst.sel = ctx->temp_reg;
1987 alu.dst.chan = 1;
1988 alu.dst.write = 1;
1989
1990 alu.last = 1;
1991 r = r600_bc_add_alu(ctx->bc, &alu);
1992 if (r)
1993 return r;
1994
1995 lit_vals[0] = fui(1.5f);
1996
1997 r = r600_bc_add_literal(ctx->bc, lit_vals);
1998 if (r)
1999 return r;
2000 src_not_temp = FALSE;
2001 src_gpr = ctx->temp_reg;
2002 }
2003
2004 if (src_not_temp) {
2005 for (i = 0; i < 4; i++) {
2006 memset(&alu, 0, sizeof(struct r600_bc_alu));
2007 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2008 alu.src[0].sel = src_gpr;
2009 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2010 alu.dst.sel = ctx->temp_reg;
2011 alu.dst.chan = i;
2012 if (i == 3)
2013 alu.last = 1;
2014 alu.dst.write = 1;
2015 r = r600_bc_add_alu(ctx->bc, &alu);
2016 if (r)
2017 return r;
2018 }
2019 src_gpr = ctx->temp_reg;
2020 }
2021
2022 opcode = ctx->inst_info->r600_opcode;
2023 if (opcode == SQ_TEX_INST_SAMPLE &&
2024 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
2025 opcode = SQ_TEX_INST_SAMPLE_C;
2026
2027 memset(&tex, 0, sizeof(struct r600_bc_tex));
2028 tex.inst = opcode;
2029 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
2030 tex.resource_id = tex.sampler_id;
2031 tex.src_gpr = src_gpr;
2032 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
2033 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
2034 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
2035 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
2036 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
2037 tex.src_sel_x = 0;
2038 tex.src_sel_y = 1;
2039 tex.src_sel_z = 2;
2040 tex.src_sel_w = 3;
2041
2042 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
2043 tex.src_sel_x = 1;
2044 tex.src_sel_y = 0;
2045 tex.src_sel_z = 3;
2046 tex.src_sel_w = 1;
2047 }
2048
2049 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
2050 tex.coord_type_x = 1;
2051 tex.coord_type_y = 1;
2052 tex.coord_type_z = 1;
2053 tex.coord_type_w = 1;
2054 }
2055
2056 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
2057 tex.src_sel_w = 2;
2058
2059 r = r600_bc_add_tex(ctx->bc, &tex);
2060 if (r)
2061 return r;
2062
2063 /* add shadow ambient support - gallium doesn't do it yet */
2064 return 0;
2065 }
2066
2067 static int tgsi_lrp(struct r600_shader_ctx *ctx)
2068 {
2069 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2070 struct r600_bc_alu_src r600_src[3];
2071 struct r600_bc_alu alu;
2072 unsigned i;
2073 int r;
2074
2075 r = tgsi_split_constant(ctx, r600_src);
2076 if (r)
2077 return r;
2078 r = tgsi_split_literal_constant(ctx, r600_src);
2079 if (r)
2080 return r;
2081 /* 1 - src0 */
2082 for (i = 0; i < 4; i++) {
2083 memset(&alu, 0, sizeof(struct r600_bc_alu));
2084 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
2085 alu.src[0].sel = V_SQ_ALU_SRC_1;
2086 alu.src[0].chan = 0;
2087 alu.src[1] = r600_src[0];
2088 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
2089 alu.src[1].neg = 1;
2090 alu.dst.sel = ctx->temp_reg;
2091 alu.dst.chan = i;
2092 if (i == 3) {
2093 alu.last = 1;
2094 }
2095 alu.dst.write = 1;
2096 r = r600_bc_add_alu(ctx->bc, &alu);
2097 if (r)
2098 return r;
2099 }
2100 r = r600_bc_add_literal(ctx->bc, ctx->value);
2101 if (r)
2102 return r;
2103
2104 /* (1 - src0) * src2 */
2105 for (i = 0; i < 4; i++) {
2106 memset(&alu, 0, sizeof(struct r600_bc_alu));
2107 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2108 alu.src[0].sel = ctx->temp_reg;
2109 alu.src[0].chan = i;
2110 alu.src[1] = r600_src[2];
2111 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2112 alu.dst.sel = ctx->temp_reg;
2113 alu.dst.chan = i;
2114 if (i == 3) {
2115 alu.last = 1;
2116 }
2117 alu.dst.write = 1;
2118 r = r600_bc_add_alu(ctx->bc, &alu);
2119 if (r)
2120 return r;
2121 }
2122 r = r600_bc_add_literal(ctx->bc, ctx->value);
2123 if (r)
2124 return r;
2125
2126 /* src0 * src1 + (1 - src0) * src2 */
2127 for (i = 0; i < 4; i++) {
2128 memset(&alu, 0, sizeof(struct r600_bc_alu));
2129 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2130 alu.is_op3 = 1;
2131 alu.src[0] = r600_src[0];
2132 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2133 alu.src[1] = r600_src[1];
2134 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2135 alu.src[2].sel = ctx->temp_reg;
2136 alu.src[2].chan = i;
2137 alu.dst.sel = ctx->temp_reg;
2138 alu.dst.chan = i;
2139 if (i == 3) {
2140 alu.last = 1;
2141 }
2142 r = r600_bc_add_alu(ctx->bc, &alu);
2143 if (r)
2144 return r;
2145 }
2146 return tgsi_helper_copy(ctx, inst);
2147 }
2148
2149 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2150 {
2151 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2152 struct r600_bc_alu_src r600_src[3];
2153 struct r600_bc_alu alu;
2154 int use_temp = 0;
2155 int i, r;
2156
2157 r = tgsi_split_constant(ctx, r600_src);
2158 if (r)
2159 return r;
2160 r = tgsi_split_literal_constant(ctx, r600_src);
2161 if (r)
2162 return r;
2163
2164 if (inst->Dst[0].Register.WriteMask != 0xf)
2165 use_temp = 1;
2166
2167 for (i = 0; i < 4; i++) {
2168 memset(&alu, 0, sizeof(struct r600_bc_alu));
2169 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2170 alu.src[0] = r600_src[0];
2171 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2172
2173 alu.src[1] = r600_src[2];
2174 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2175
2176 alu.src[2] = r600_src[1];
2177 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2178
2179 if (use_temp)
2180 alu.dst.sel = ctx->temp_reg;
2181 else {
2182 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2183 if (r)
2184 return r;
2185 }
2186 alu.dst.chan = i;
2187 alu.dst.write = 1;
2188 alu.is_op3 = 1;
2189 if (i == 3)
2190 alu.last = 1;
2191 r = r600_bc_add_alu(ctx->bc, &alu);
2192 if (r)
2193 return r;
2194 }
2195 if (use_temp)
2196 return tgsi_helper_copy(ctx, inst);
2197 return 0;
2198 }
2199
2200 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2201 {
2202 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2203 struct r600_bc_alu_src r600_src[3];
2204 struct r600_bc_alu alu;
2205 uint32_t use_temp = 0;
2206 int i, r;
2207
2208 if (inst->Dst[0].Register.WriteMask != 0xf)
2209 use_temp = 1;
2210
2211 r = tgsi_split_constant(ctx, r600_src);
2212 if (r)
2213 return r;
2214 r = tgsi_split_literal_constant(ctx, r600_src);
2215 if (r)
2216 return r;
2217
2218 for (i = 0; i < 4; i++) {
2219 memset(&alu, 0, sizeof(struct r600_bc_alu));
2220 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2221
2222 alu.src[0] = r600_src[0];
2223 switch (i) {
2224 case 0:
2225 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2226 break;
2227 case 1:
2228 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2229 break;
2230 case 2:
2231 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2232 break;
2233 case 3:
2234 alu.src[0].sel = V_SQ_ALU_SRC_0;
2235 alu.src[0].chan = i;
2236 }
2237
2238 alu.src[1] = r600_src[1];
2239 switch (i) {
2240 case 0:
2241 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2242 break;
2243 case 1:
2244 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2245 break;
2246 case 2:
2247 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2248 break;
2249 case 3:
2250 alu.src[1].sel = V_SQ_ALU_SRC_0;
2251 alu.src[1].chan = i;
2252 }
2253
2254 alu.dst.sel = ctx->temp_reg;
2255 alu.dst.chan = i;
2256 alu.dst.write = 1;
2257
2258 if (i == 3)
2259 alu.last = 1;
2260 r = r600_bc_add_alu(ctx->bc, &alu);
2261 if (r)
2262 return r;
2263
2264 r = r600_bc_add_literal(ctx->bc, ctx->value);
2265 if (r)
2266 return r;
2267 }
2268
2269 for (i = 0; i < 4; i++) {
2270 memset(&alu, 0, sizeof(struct r600_bc_alu));
2271 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2272
2273 alu.src[0] = r600_src[0];
2274 switch (i) {
2275 case 0:
2276 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2277 break;
2278 case 1:
2279 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2280 break;
2281 case 2:
2282 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2283 break;
2284 case 3:
2285 alu.src[0].sel = V_SQ_ALU_SRC_0;
2286 alu.src[0].chan = i;
2287 }
2288
2289 alu.src[1] = r600_src[1];
2290 switch (i) {
2291 case 0:
2292 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2293 break;
2294 case 1:
2295 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2296 break;
2297 case 2:
2298 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2299 break;
2300 case 3:
2301 alu.src[1].sel = V_SQ_ALU_SRC_0;
2302 alu.src[1].chan = i;
2303 }
2304
2305 alu.src[2].sel = ctx->temp_reg;
2306 alu.src[2].neg = 1;
2307 alu.src[2].chan = i;
2308
2309 if (use_temp)
2310 alu.dst.sel = ctx->temp_reg;
2311 else {
2312 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2313 if (r)
2314 return r;
2315 }
2316 alu.dst.chan = i;
2317 alu.dst.write = 1;
2318 alu.is_op3 = 1;
2319 if (i == 3)
2320 alu.last = 1;
2321 r = r600_bc_add_alu(ctx->bc, &alu);
2322 if (r)
2323 return r;
2324
2325 r = r600_bc_add_literal(ctx->bc, ctx->value);
2326 if (r)
2327 return r;
2328 }
2329 if (use_temp)
2330 return tgsi_helper_copy(ctx, inst);
2331 return 0;
2332 }
2333
2334 static int tgsi_exp(struct r600_shader_ctx *ctx)
2335 {
2336 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2337 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2338 struct r600_bc_alu alu;
2339 int r;
2340
2341 /* result.x = 2^floor(src); */
2342 if (inst->Dst[0].Register.WriteMask & 1) {
2343 memset(&alu, 0, sizeof(struct r600_bc_alu));
2344
2345 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2346 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2347 if (r)
2348 return r;
2349
2350 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2351
2352 alu.dst.sel = ctx->temp_reg;
2353 alu.dst.chan = 0;
2354 alu.dst.write = 1;
2355 alu.last = 1;
2356 r = r600_bc_add_alu(ctx->bc, &alu);
2357 if (r)
2358 return r;
2359
2360 r = r600_bc_add_literal(ctx->bc, ctx->value);
2361 if (r)
2362 return r;
2363
2364 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2365 alu.src[0].sel = ctx->temp_reg;
2366 alu.src[0].chan = 0;
2367
2368 alu.dst.sel = ctx->temp_reg;
2369 alu.dst.chan = 0;
2370 alu.dst.write = 1;
2371 alu.last = 1;
2372 r = r600_bc_add_alu(ctx->bc, &alu);
2373 if (r)
2374 return r;
2375
2376 r = r600_bc_add_literal(ctx->bc, ctx->value);
2377 if (r)
2378 return r;
2379 }
2380
2381 /* result.y = tmp - floor(tmp); */
2382 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2383 memset(&alu, 0, sizeof(struct r600_bc_alu));
2384
2385 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2386 alu.src[0] = r600_src[0];
2387 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2388 if (r)
2389 return r;
2390 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2391
2392 alu.dst.sel = ctx->temp_reg;
2393 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2394 // if (r)
2395 // return r;
2396 alu.dst.write = 1;
2397 alu.dst.chan = 1;
2398
2399 alu.last = 1;
2400
2401 r = r600_bc_add_alu(ctx->bc, &alu);
2402 if (r)
2403 return r;
2404 r = r600_bc_add_literal(ctx->bc, ctx->value);
2405 if (r)
2406 return r;
2407 }
2408
2409 /* result.z = RoughApprox2ToX(tmp);*/
2410 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2411 memset(&alu, 0, sizeof(struct r600_bc_alu));
2412 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2413 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2414 if (r)
2415 return r;
2416 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2417
2418 alu.dst.sel = ctx->temp_reg;
2419 alu.dst.write = 1;
2420 alu.dst.chan = 2;
2421
2422 alu.last = 1;
2423
2424 r = r600_bc_add_alu(ctx->bc, &alu);
2425 if (r)
2426 return r;
2427 r = r600_bc_add_literal(ctx->bc, ctx->value);
2428 if (r)
2429 return r;
2430 }
2431
2432 /* result.w = 1.0;*/
2433 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2434 memset(&alu, 0, sizeof(struct r600_bc_alu));
2435
2436 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2437 alu.src[0].sel = V_SQ_ALU_SRC_1;
2438 alu.src[0].chan = 0;
2439
2440 alu.dst.sel = ctx->temp_reg;
2441 alu.dst.chan = 3;
2442 alu.dst.write = 1;
2443 alu.last = 1;
2444 r = r600_bc_add_alu(ctx->bc, &alu);
2445 if (r)
2446 return r;
2447 r = r600_bc_add_literal(ctx->bc, ctx->value);
2448 if (r)
2449 return r;
2450 }
2451 return tgsi_helper_copy(ctx, inst);
2452 }
2453
2454 static int tgsi_log(struct r600_shader_ctx *ctx)
2455 {
2456 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2457 struct r600_bc_alu alu;
2458 int r;
2459
2460 /* result.x = floor(log2(src)); */
2461 if (inst->Dst[0].Register.WriteMask & 1) {
2462 memset(&alu, 0, sizeof(struct r600_bc_alu));
2463
2464 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2465 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2466 if (r)
2467 return r;
2468
2469 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2470
2471 alu.dst.sel = ctx->temp_reg;
2472 alu.dst.chan = 0;
2473 alu.dst.write = 1;
2474 alu.last = 1;
2475 r = r600_bc_add_alu(ctx->bc, &alu);
2476 if (r)
2477 return r;
2478
2479 r = r600_bc_add_literal(ctx->bc, ctx->value);
2480 if (r)
2481 return r;
2482
2483 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2484 alu.src[0].sel = ctx->temp_reg;
2485 alu.src[0].chan = 0;
2486
2487 alu.dst.sel = ctx->temp_reg;
2488 alu.dst.chan = 0;
2489 alu.dst.write = 1;
2490 alu.last = 1;
2491
2492 r = r600_bc_add_alu(ctx->bc, &alu);
2493 if (r)
2494 return r;
2495
2496 r = r600_bc_add_literal(ctx->bc, ctx->value);
2497 if (r)
2498 return r;
2499 }
2500
2501 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2502 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2503 memset(&alu, 0, sizeof(struct r600_bc_alu));
2504
2505 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2506 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2507 if (r)
2508 return r;
2509
2510 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2511
2512 alu.dst.sel = ctx->temp_reg;
2513 alu.dst.chan = 1;
2514 alu.dst.write = 1;
2515 alu.last = 1;
2516
2517 r = r600_bc_add_alu(ctx->bc, &alu);
2518 if (r)
2519 return r;
2520
2521 r = r600_bc_add_literal(ctx->bc, ctx->value);
2522 if (r)
2523 return r;
2524
2525 memset(&alu, 0, sizeof(struct r600_bc_alu));
2526
2527 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2528 alu.src[0].sel = ctx->temp_reg;
2529 alu.src[0].chan = 1;
2530
2531 alu.dst.sel = ctx->temp_reg;
2532 alu.dst.chan = 1;
2533 alu.dst.write = 1;
2534 alu.last = 1;
2535
2536 r = r600_bc_add_alu(ctx->bc, &alu);
2537 if (r)
2538 return r;
2539
2540 r = r600_bc_add_literal(ctx->bc, ctx->value);
2541 if (r)
2542 return r;
2543
2544 memset(&alu, 0, sizeof(struct r600_bc_alu));
2545
2546 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2547 alu.src[0].sel = ctx->temp_reg;
2548 alu.src[0].chan = 1;
2549
2550 alu.dst.sel = ctx->temp_reg;
2551 alu.dst.chan = 1;
2552 alu.dst.write = 1;
2553 alu.last = 1;
2554
2555 r = r600_bc_add_alu(ctx->bc, &alu);
2556 if (r)
2557 return r;
2558
2559 r = r600_bc_add_literal(ctx->bc, ctx->value);
2560 if (r)
2561 return r;
2562
2563 memset(&alu, 0, sizeof(struct r600_bc_alu));
2564
2565 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2566 alu.src[0].sel = ctx->temp_reg;
2567 alu.src[0].chan = 1;
2568
2569 alu.dst.sel = ctx->temp_reg;
2570 alu.dst.chan = 1;
2571 alu.dst.write = 1;
2572 alu.last = 1;
2573
2574 r = r600_bc_add_alu(ctx->bc, &alu);
2575 if (r)
2576 return r;
2577
2578 r = r600_bc_add_literal(ctx->bc, ctx->value);
2579 if (r)
2580 return r;
2581
2582 memset(&alu, 0, sizeof(struct r600_bc_alu));
2583
2584 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2585
2586 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2587 if (r)
2588 return r;
2589
2590 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2591
2592 alu.src[1].sel = ctx->temp_reg;
2593 alu.src[1].chan = 1;
2594
2595 alu.dst.sel = ctx->temp_reg;
2596 alu.dst.chan = 1;
2597 alu.dst.write = 1;
2598 alu.last = 1;
2599
2600 r = r600_bc_add_alu(ctx->bc, &alu);
2601 if (r)
2602 return r;
2603
2604 r = r600_bc_add_literal(ctx->bc, ctx->value);
2605 if (r)
2606 return r;
2607 }
2608
2609 /* result.z = log2(src);*/
2610 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2611 memset(&alu, 0, sizeof(struct r600_bc_alu));
2612
2613 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2614 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2615 if (r)
2616 return r;
2617
2618 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2619
2620 alu.dst.sel = ctx->temp_reg;
2621 alu.dst.write = 1;
2622 alu.dst.chan = 2;
2623 alu.last = 1;
2624
2625 r = r600_bc_add_alu(ctx->bc, &alu);
2626 if (r)
2627 return r;
2628
2629 r = r600_bc_add_literal(ctx->bc, ctx->value);
2630 if (r)
2631 return r;
2632 }
2633
2634 /* result.w = 1.0; */
2635 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2636 memset(&alu, 0, sizeof(struct r600_bc_alu));
2637
2638 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2639 alu.src[0].sel = V_SQ_ALU_SRC_1;
2640 alu.src[0].chan = 0;
2641
2642 alu.dst.sel = ctx->temp_reg;
2643 alu.dst.chan = 3;
2644 alu.dst.write = 1;
2645 alu.last = 1;
2646
2647 r = r600_bc_add_alu(ctx->bc, &alu);
2648 if (r)
2649 return r;
2650
2651 r = r600_bc_add_literal(ctx->bc, ctx->value);
2652 if (r)
2653 return r;
2654 }
2655
2656 return tgsi_helper_copy(ctx, inst);
2657 }
2658
2659 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2660 {
2661 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2662 struct r600_bc_alu alu;
2663 int r;
2664 memset(&alu, 0, sizeof(struct r600_bc_alu));
2665
2666 switch (inst->Instruction.Opcode) {
2667 case TGSI_OPCODE_ARL:
2668 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2669 break;
2670 case TGSI_OPCODE_ARR:
2671 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2672 break;
2673 default:
2674 assert(0);
2675 return -1;
2676 }
2677
2678 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2679 if (r)
2680 return r;
2681 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2682 alu.last = 1;
2683 alu.dst.chan = 0;
2684 alu.dst.sel = ctx->temp_reg;
2685 alu.dst.write = 1;
2686 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2687 if (r)
2688 return r;
2689 memset(&alu, 0, sizeof(struct r600_bc_alu));
2690 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2691 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2692 if (r)
2693 return r;
2694 alu.src[0].sel = ctx->temp_reg;
2695 alu.src[0].chan = 0;
2696 alu.last = 1;
2697 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2698 if (r)
2699 return r;
2700 return 0;
2701 }
2702 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2703 {
2704 /* TODO from r600c, ar values don't persist between clauses */
2705 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2706 struct r600_bc_alu alu;
2707 int r;
2708 memset(&alu, 0, sizeof(struct r600_bc_alu));
2709
2710 switch (inst->Instruction.Opcode) {
2711 case TGSI_OPCODE_ARL:
2712 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2713 break;
2714 case TGSI_OPCODE_ARR:
2715 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2716 break;
2717 default:
2718 assert(0);
2719 return -1;
2720 }
2721
2722
2723 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2724 if (r)
2725 return r;
2726 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2727
2728 alu.last = 1;
2729
2730 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2731 if (r)
2732 return r;
2733 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2734 return 0;
2735 }
2736
2737 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2738 {
2739 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2740 struct r600_bc_alu alu;
2741 int i, r = 0;
2742
2743 for (i = 0; i < 4; i++) {
2744 memset(&alu, 0, sizeof(struct r600_bc_alu));
2745
2746 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2747 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2748 if (r)
2749 return r;
2750
2751 if (i == 0 || i == 3) {
2752 alu.src[0].sel = V_SQ_ALU_SRC_1;
2753 } else {
2754 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2755 if (r)
2756 return r;
2757 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2758 }
2759
2760 if (i == 0 || i == 2) {
2761 alu.src[1].sel = V_SQ_ALU_SRC_1;
2762 } else {
2763 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2764 if (r)
2765 return r;
2766 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2767 }
2768 if (i == 3)
2769 alu.last = 1;
2770 r = r600_bc_add_alu(ctx->bc, &alu);
2771 if (r)
2772 return r;
2773 }
2774 return 0;
2775 }
2776
2777 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2778 {
2779 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2780 struct r600_bc_alu alu;
2781 int r;
2782
2783 memset(&alu, 0, sizeof(struct r600_bc_alu));
2784 alu.inst = opcode;
2785 alu.predicate = 1;
2786
2787 alu.dst.sel = ctx->temp_reg;
2788 alu.dst.write = 1;
2789 alu.dst.chan = 0;
2790
2791 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2792 if (r)
2793 return r;
2794 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2795 alu.src[1].sel = V_SQ_ALU_SRC_0;
2796 alu.src[1].chan = 0;
2797
2798 alu.last = 1;
2799
2800 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2801 if (r)
2802 return r;
2803 return 0;
2804 }
2805
2806 static int pops(struct r600_shader_ctx *ctx, int pops)
2807 {
2808 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2809 ctx->bc->cf_last->pop_count = pops;
2810 return 0;
2811 }
2812
2813 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2814 {
2815 switch(reason) {
2816 case FC_PUSH_VPM:
2817 ctx->bc->callstack[ctx->bc->call_sp].current--;
2818 break;
2819 case FC_PUSH_WQM:
2820 case FC_LOOP:
2821 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2822 break;
2823 case FC_REP:
2824 /* TOODO : for 16 vp asic should -= 2; */
2825 ctx->bc->callstack[ctx->bc->call_sp].current --;
2826 break;
2827 }
2828 }
2829
2830 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2831 {
2832 if (check_max_only) {
2833 int diff;
2834 switch (reason) {
2835 case FC_PUSH_VPM:
2836 diff = 1;
2837 break;
2838 case FC_PUSH_WQM:
2839 diff = 4;
2840 break;
2841 default:
2842 assert(0);
2843 diff = 0;
2844 }
2845 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2846 ctx->bc->callstack[ctx->bc->call_sp].max) {
2847 ctx->bc->callstack[ctx->bc->call_sp].max =
2848 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2849 }
2850 return;
2851 }
2852 switch (reason) {
2853 case FC_PUSH_VPM:
2854 ctx->bc->callstack[ctx->bc->call_sp].current++;
2855 break;
2856 case FC_PUSH_WQM:
2857 case FC_LOOP:
2858 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2859 break;
2860 case FC_REP:
2861 ctx->bc->callstack[ctx->bc->call_sp].current++;
2862 break;
2863 }
2864
2865 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2866 ctx->bc->callstack[ctx->bc->call_sp].max) {
2867 ctx->bc->callstack[ctx->bc->call_sp].max =
2868 ctx->bc->callstack[ctx->bc->call_sp].current;
2869 }
2870 }
2871
2872 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2873 {
2874 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2875
2876 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2877 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2878 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2879 sp->num_mid++;
2880 }
2881
2882 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2883 {
2884 ctx->bc->fc_sp++;
2885 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2886 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2887 }
2888
2889 static void fc_poplevel(struct r600_shader_ctx *ctx)
2890 {
2891 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2892 if (sp->mid) {
2893 free(sp->mid);
2894 sp->mid = NULL;
2895 }
2896 sp->num_mid = 0;
2897 sp->start = NULL;
2898 sp->type = 0;
2899 ctx->bc->fc_sp--;
2900 }
2901
2902 #if 0
2903 static int emit_return(struct r600_shader_ctx *ctx)
2904 {
2905 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2906 return 0;
2907 }
2908
2909 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2910 {
2911
2912 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2913 ctx->bc->cf_last->pop_count = pops;
2914 /* TODO work out offset */
2915 return 0;
2916 }
2917
2918 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2919 {
2920 return 0;
2921 }
2922
2923 static void emit_testflag(struct r600_shader_ctx *ctx)
2924 {
2925
2926 }
2927
2928 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2929 {
2930 emit_testflag(ctx);
2931 emit_jump_to_offset(ctx, 1, 4);
2932 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2933 pops(ctx, ifidx + 1);
2934 emit_return(ctx);
2935 }
2936
2937 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2938 {
2939 emit_testflag(ctx);
2940
2941 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2942 ctx->bc->cf_last->pop_count = 1;
2943
2944 fc_set_mid(ctx, fc_sp);
2945
2946 pops(ctx, 1);
2947 }
2948 #endif
2949
2950 static int tgsi_if(struct r600_shader_ctx *ctx)
2951 {
2952 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2953
2954 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2955
2956 fc_pushlevel(ctx, FC_IF);
2957
2958 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2959 return 0;
2960 }
2961
2962 static int tgsi_else(struct r600_shader_ctx *ctx)
2963 {
2964 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2965 ctx->bc->cf_last->pop_count = 1;
2966
2967 fc_set_mid(ctx, ctx->bc->fc_sp);
2968 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2969 return 0;
2970 }
2971
2972 static int tgsi_endif(struct r600_shader_ctx *ctx)
2973 {
2974 pops(ctx, 1);
2975 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2976 R600_ERR("if/endif unbalanced in shader\n");
2977 return -1;
2978 }
2979
2980 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2981 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2982 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2983 } else {
2984 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2985 }
2986 fc_poplevel(ctx);
2987
2988 callstack_decrease_current(ctx, FC_PUSH_VPM);
2989 return 0;
2990 }
2991
2992 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2993 {
2994 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2995
2996 fc_pushlevel(ctx, FC_LOOP);
2997
2998 /* check stack depth */
2999 callstack_check_depth(ctx, FC_LOOP, 0);
3000 return 0;
3001 }
3002
3003 static int tgsi_endloop(struct r600_shader_ctx *ctx)
3004 {
3005 int i;
3006
3007 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
3008
3009 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
3010 R600_ERR("loop/endloop in shader code are not paired.\n");
3011 return -EINVAL;
3012 }
3013
3014 /* fixup loop pointers - from r600isa
3015 LOOP END points to CF after LOOP START,
3016 LOOP START point to CF after LOOP END
3017 BRK/CONT point to LOOP END CF
3018 */
3019 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
3020
3021 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
3022
3023 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
3024 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
3025 }
3026 /* TODO add LOOPRET support */
3027 fc_poplevel(ctx);
3028 callstack_decrease_current(ctx, FC_LOOP);
3029 return 0;
3030 }
3031
3032 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
3033 {
3034 unsigned int fscp;
3035
3036 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
3037 {
3038 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
3039 break;
3040 }
3041
3042 if (fscp == 0) {
3043 R600_ERR("Break not inside loop/endloop pair\n");
3044 return -EINVAL;
3045 }
3046
3047 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
3048 ctx->bc->cf_last->pop_count = 1;
3049
3050 fc_set_mid(ctx, fscp);
3051
3052 pops(ctx, 1);
3053 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
3054 return 0;
3055 }
3056
3057 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
3058 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
3059 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3060 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3061
3062 /* FIXME:
3063 * For state trackers other than OpenGL, we'll want to use
3064 * _RECIP_IEEE instead.
3065 */
3066 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
3067
3068 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
3069 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3070 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
3071 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3072 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3073 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3074 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3075 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3076 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3077 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3078 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3079 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3080 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3081 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3082 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3083 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 /* gap */
3085 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 /* gap */
3088 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3091 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3092 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3093 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3095 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3096 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3097 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3098 /* gap */
3099 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3101 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3103 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3104 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3105 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3106 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3107 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3108 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3113 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3115 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3116 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3117 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3118 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3120 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3122 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3127 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
3129 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3132 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3133 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3134 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3135 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3136 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3139 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3140 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3141 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3142 /* gap */
3143 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3146 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3147 /* gap */
3148 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3149 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3153 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3154 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3156 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3157 /* gap */
3158 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3159 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3160 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3161 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3162 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3163 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3164 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3166 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3167 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3168 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3169 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3170 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3171 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3172 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3173 /* gap */
3174 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3176 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3177 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3178 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3179 /* gap */
3180 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3181 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3182 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3183 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3184 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3185 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3186 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3187 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3188 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3189 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3190 /* gap */
3191 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3192 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3193 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3194 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3195 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3196 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3197 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3198 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3199 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3200 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3201 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3202 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3203 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3204 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3205 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3206 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3207 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3208 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3209 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3210 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3211 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3212 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3213 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3214 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3215 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3216 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3217 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3218 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3219 };
3220
3221 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3222 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3223 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3224 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3225 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3226 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3227 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3228 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3229 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3230 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3231 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3232 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3233 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3234 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3235 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3236 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3237 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3238 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3239 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3240 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3241 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3242 /* gap */
3243 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3244 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3245 /* gap */
3246 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3247 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3248 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3249 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3250 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3251 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3252 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3253 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3254 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3255 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3256 /* gap */
3257 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3258 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3259 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3260 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3261 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3262 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3263 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3264 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3265 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3266 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3267 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3268 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3269 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3270 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3271 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3272 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3273 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3274 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3275 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3276 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3277 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3278 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3279 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3280 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3281 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3282 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3283 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3284 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3285 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3286 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3287 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3288 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3289 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3290 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3291 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3292 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3293 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3294 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3295 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3296 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3297 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3298 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3299 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3300 /* gap */
3301 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3302 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3303 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3304 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3305 /* gap */
3306 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3307 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3308 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3309 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3310 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3311 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3312 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3313 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3314 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3315 /* gap */
3316 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3317 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3318 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3319 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3320 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3321 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3322 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3323 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3324 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3325 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3326 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3327 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3328 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3329 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3330 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3331 /* gap */
3332 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3333 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3334 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3335 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3336 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3337 /* gap */
3338 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3339 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3340 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3341 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3342 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3343 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3344 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3345 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3346 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3347 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3348 /* gap */
3349 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3350 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3351 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3352 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3353 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3354 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3355 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3356 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3357 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3358 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3359 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3360 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3361 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3362 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3363 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3364 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3365 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3366 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3367 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3368 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3369 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3370 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3371 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3372 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3373 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3374 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3375 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3376 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3377 };