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r600/shader: add utility functions to do single slot arithmatic
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
64 static int r600_shader_from_tgsi(struct r600_context *rctx,
65 struct r600_pipe_shader *pipeshader,
66 union r600_shader_key key);
67
68
69 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
70 int size, unsigned comp_mask) {
71
72 if (!size)
73 return;
74
75 if (ps->num_arrays == ps->max_arrays) {
76 ps->max_arrays += 64;
77 ps->arrays = realloc(ps->arrays, ps->max_arrays *
78 sizeof(struct r600_shader_array));
79 }
80
81 int n = ps->num_arrays;
82 ++ps->num_arrays;
83
84 ps->arrays[n].comp_mask = comp_mask;
85 ps->arrays[n].gpr_start = start_gpr;
86 ps->arrays[n].gpr_count = size;
87 }
88
89 static void r600_dump_streamout(struct pipe_stream_output_info *so)
90 {
91 unsigned i;
92
93 fprintf(stderr, "STREAMOUT\n");
94 for (i = 0; i < so->num_outputs; i++) {
95 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
96 so->output[i].start_component;
97 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
98 i,
99 so->output[i].stream,
100 so->output[i].output_buffer,
101 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
102 so->output[i].register_index,
103 mask & 1 ? "x" : "",
104 mask & 2 ? "y" : "",
105 mask & 4 ? "z" : "",
106 mask & 8 ? "w" : "",
107 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
108 }
109 }
110
111 static int store_shader(struct pipe_context *ctx,
112 struct r600_pipe_shader *shader)
113 {
114 struct r600_context *rctx = (struct r600_context *)ctx;
115 uint32_t *ptr, i;
116
117 if (shader->bo == NULL) {
118 shader->bo = (struct r600_resource*)
119 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
120 if (shader->bo == NULL) {
121 return -ENOMEM;
122 }
123 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
124 if (R600_BIG_ENDIAN) {
125 for (i = 0; i < shader->shader.bc.ndw; ++i) {
126 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
127 }
128 } else {
129 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
130 }
131 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
132 }
133
134 return 0;
135 }
136
137 int r600_pipe_shader_create(struct pipe_context *ctx,
138 struct r600_pipe_shader *shader,
139 union r600_shader_key key)
140 {
141 struct r600_context *rctx = (struct r600_context *)ctx;
142 struct r600_pipe_shader_selector *sel = shader->selector;
143 int r;
144 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
145 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
146 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
147 unsigned export_shader;
148
149 shader->shader.bc.isa = rctx->isa;
150
151 if (dump) {
152 fprintf(stderr, "--------------------------------------------------------------\n");
153 tgsi_dump(sel->tokens, 0);
154
155 if (sel->so.num_outputs) {
156 r600_dump_streamout(&sel->so);
157 }
158 }
159 r = r600_shader_from_tgsi(rctx, shader, key);
160 if (r) {
161 R600_ERR("translation from TGSI failed !\n");
162 goto error;
163 }
164 if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) {
165 /* only disable for vertex shaders in tess paths */
166 if (key.vs.as_ls)
167 use_sb = 0;
168 }
169 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_CTRL);
170 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_EVAL);
171
172 /* disable SB for shaders using doubles */
173 use_sb &= !shader->shader.uses_doubles;
174
175 /* Check if the bytecode has already been built. When using the llvm
176 * backend, r600_shader_from_tgsi() will take care of building the
177 * bytecode.
178 */
179 if (!shader->shader.bc.bytecode) {
180 r = r600_bytecode_build(&shader->shader.bc);
181 if (r) {
182 R600_ERR("building bytecode failed !\n");
183 goto error;
184 }
185 }
186
187 if (dump && !sb_disasm) {
188 fprintf(stderr, "--------------------------------------------------------------\n");
189 r600_bytecode_disasm(&shader->shader.bc);
190 fprintf(stderr, "______________________________________________________________\n");
191 } else if ((dump && sb_disasm) || use_sb) {
192 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
193 dump, use_sb);
194 if (r) {
195 R600_ERR("r600_sb_bytecode_process failed !\n");
196 goto error;
197 }
198 }
199
200 if (shader->gs_copy_shader) {
201 if (dump) {
202 // dump copy shader
203 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
204 &shader->gs_copy_shader->shader, dump, 0);
205 if (r)
206 goto error;
207 }
208
209 if ((r = store_shader(ctx, shader->gs_copy_shader)))
210 goto error;
211 }
212
213 /* Store the shader in a buffer. */
214 if ((r = store_shader(ctx, shader)))
215 goto error;
216
217 /* Build state. */
218 switch (shader->shader.processor_type) {
219 case TGSI_PROCESSOR_TESS_CTRL:
220 evergreen_update_hs_state(ctx, shader);
221 break;
222 case TGSI_PROCESSOR_TESS_EVAL:
223 if (key.tes.as_es)
224 evergreen_update_es_state(ctx, shader);
225 else
226 evergreen_update_vs_state(ctx, shader);
227 break;
228 case TGSI_PROCESSOR_GEOMETRY:
229 if (rctx->b.chip_class >= EVERGREEN) {
230 evergreen_update_gs_state(ctx, shader);
231 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
232 } else {
233 r600_update_gs_state(ctx, shader);
234 r600_update_vs_state(ctx, shader->gs_copy_shader);
235 }
236 break;
237 case TGSI_PROCESSOR_VERTEX:
238 export_shader = key.vs.as_es;
239 if (rctx->b.chip_class >= EVERGREEN) {
240 if (key.vs.as_ls)
241 evergreen_update_ls_state(ctx, shader);
242 else if (key.vs.as_es)
243 evergreen_update_es_state(ctx, shader);
244 else
245 evergreen_update_vs_state(ctx, shader);
246 } else {
247 if (export_shader)
248 r600_update_es_state(ctx, shader);
249 else
250 r600_update_vs_state(ctx, shader);
251 }
252 break;
253 case TGSI_PROCESSOR_FRAGMENT:
254 if (rctx->b.chip_class >= EVERGREEN) {
255 evergreen_update_ps_state(ctx, shader);
256 } else {
257 r600_update_ps_state(ctx, shader);
258 }
259 break;
260 default:
261 r = -EINVAL;
262 goto error;
263 }
264 return 0;
265
266 error:
267 r600_pipe_shader_destroy(ctx, shader);
268 return r;
269 }
270
271 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
272 {
273 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
274 r600_bytecode_clear(&shader->shader.bc);
275 r600_release_command_buffer(&shader->command_buffer);
276 }
277
278 /*
279 * tgsi -> r600 shader
280 */
281 struct r600_shader_tgsi_instruction;
282
283 struct r600_shader_src {
284 unsigned sel;
285 unsigned swizzle[4];
286 unsigned neg;
287 unsigned abs;
288 unsigned rel;
289 unsigned kc_bank;
290 boolean kc_rel; /* true if cache bank is indexed */
291 uint32_t value[4];
292 };
293
294 struct eg_interp {
295 boolean enabled;
296 unsigned ij_index;
297 };
298
299 struct r600_shader_ctx {
300 struct tgsi_shader_info info;
301 struct tgsi_parse_context parse;
302 const struct tgsi_token *tokens;
303 unsigned type;
304 unsigned file_offset[TGSI_FILE_COUNT];
305 unsigned temp_reg;
306 const struct r600_shader_tgsi_instruction *inst_info;
307 struct r600_bytecode *bc;
308 struct r600_shader *shader;
309 struct r600_shader_src src[4];
310 uint32_t *literals;
311 uint32_t nliterals;
312 uint32_t max_driver_temp_used;
313 boolean use_llvm;
314 /* needed for evergreen interpolation */
315 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
316 /* evergreen/cayman also store sample mask in face register */
317 int face_gpr;
318 /* sample id is .w component stored in fixed point position register */
319 int fixed_pt_position_gpr;
320 int colors_used;
321 boolean clip_vertex_write;
322 unsigned cv_output;
323 unsigned edgeflag_output;
324 int fragcoord_input;
325 int native_integers;
326 int next_ring_offset;
327 int gs_out_ring_offset;
328 int gs_next_vertex;
329 struct r600_shader *gs_for_vs;
330 int gs_export_gpr_tregs[4];
331 const struct pipe_stream_output_info *gs_stream_output_info;
332 unsigned enabled_stream_buffers_mask;
333 };
334
335 struct r600_shader_tgsi_instruction {
336 unsigned op;
337 int (*process)(struct r600_shader_ctx *ctx);
338 };
339
340 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
341 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
342 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
343 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
344 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
345 static int tgsi_else(struct r600_shader_ctx *ctx);
346 static int tgsi_endif(struct r600_shader_ctx *ctx);
347 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
348 static int tgsi_endloop(struct r600_shader_ctx *ctx);
349 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
350 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
351 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
352 unsigned int dst_reg);
353 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
354 const struct r600_shader_src *shader_src,
355 unsigned chan);
356
357 static int tgsi_last_instruction(unsigned writemask)
358 {
359 int i, lasti = 0;
360
361 for (i = 0; i < 4; i++) {
362 if (writemask & (1 << i)) {
363 lasti = i;
364 }
365 }
366 return lasti;
367 }
368
369 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
370 {
371 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
372 int j;
373
374 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
375 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
376 return -EINVAL;
377 }
378 if (i->Instruction.Predicate) {
379 R600_ERR("predicate unsupported\n");
380 return -EINVAL;
381 }
382 #if 0
383 if (i->Instruction.Label) {
384 R600_ERR("label unsupported\n");
385 return -EINVAL;
386 }
387 #endif
388 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
389 if (i->Src[j].Register.Dimension) {
390 switch (i->Src[j].Register.File) {
391 case TGSI_FILE_CONSTANT:
392 break;
393 case TGSI_FILE_INPUT:
394 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
395 break;
396 default:
397 R600_ERR("unsupported src %d (dimension %d)\n", j,
398 i->Src[j].Register.Dimension);
399 return -EINVAL;
400 }
401 }
402 }
403 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
404 if (i->Dst[j].Register.Dimension) {
405 R600_ERR("unsupported dst (dimension)\n");
406 return -EINVAL;
407 }
408 }
409 return 0;
410 }
411
412 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
413 {
414 if (interpolate == TGSI_INTERPOLATE_COLOR ||
415 interpolate == TGSI_INTERPOLATE_LINEAR ||
416 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
417 {
418 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
419 int loc;
420
421 switch(location) {
422 case TGSI_INTERPOLATE_LOC_CENTER:
423 loc = 1;
424 break;
425 case TGSI_INTERPOLATE_LOC_CENTROID:
426 loc = 2;
427 break;
428 case TGSI_INTERPOLATE_LOC_SAMPLE:
429 default:
430 loc = 0; break;
431 }
432
433 return is_linear * 3 + loc;
434 }
435
436 return -1;
437 }
438
439 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
440 int input)
441 {
442 int i = eg_get_interpolator_index(
443 ctx->shader->input[input].interpolate,
444 ctx->shader->input[input].interpolate_location);
445 assert(i >= 0);
446 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
447 }
448
449 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
450 {
451 int i, r;
452 struct r600_bytecode_alu alu;
453 int gpr = 0, base_chan = 0;
454 int ij_index = ctx->shader->input[input].ij_index;
455
456 /* work out gpr and base_chan from index */
457 gpr = ij_index / 2;
458 base_chan = (2 * (ij_index % 2)) + 1;
459
460 for (i = 0; i < 8; i++) {
461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
462
463 if (i < 4)
464 alu.op = ALU_OP2_INTERP_ZW;
465 else
466 alu.op = ALU_OP2_INTERP_XY;
467
468 if ((i > 1) && (i < 6)) {
469 alu.dst.sel = ctx->shader->input[input].gpr;
470 alu.dst.write = 1;
471 }
472
473 alu.dst.chan = i % 4;
474
475 alu.src[0].sel = gpr;
476 alu.src[0].chan = (base_chan - (i % 2));
477
478 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
479
480 alu.bank_swizzle_force = SQ_ALU_VEC_210;
481 if ((i % 4) == 3)
482 alu.last = 1;
483 r = r600_bytecode_add_alu(ctx->bc, &alu);
484 if (r)
485 return r;
486 }
487 return 0;
488 }
489
490 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
491 {
492 int i, r;
493 struct r600_bytecode_alu alu;
494
495 for (i = 0; i < 4; i++) {
496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
497
498 alu.op = ALU_OP1_INTERP_LOAD_P0;
499
500 alu.dst.sel = ctx->shader->input[input].gpr;
501 alu.dst.write = 1;
502
503 alu.dst.chan = i;
504
505 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
506 alu.src[0].chan = i;
507
508 if (i == 3)
509 alu.last = 1;
510 r = r600_bytecode_add_alu(ctx->bc, &alu);
511 if (r)
512 return r;
513 }
514 return 0;
515 }
516
517 /*
518 * Special export handling in shaders
519 *
520 * shader export ARRAY_BASE for EXPORT_POS:
521 * 60 is position
522 * 61 is misc vector
523 * 62, 63 are clip distance vectors
524 *
525 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
526 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
527 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
528 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
529 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
530 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
531 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
532 * exclusive from render target index)
533 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
534 *
535 *
536 * shader export ARRAY_BASE for EXPORT_PIXEL:
537 * 0-7 CB targets
538 * 61 computed Z vector
539 *
540 * The use of the values exported in the computed Z vector are controlled
541 * by DB_SHADER_CONTROL:
542 * Z_EXPORT_ENABLE - Z as a float in RED
543 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
544 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
545 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
546 * DB_SOURCE_FORMAT - export control restrictions
547 *
548 */
549
550
551 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
552 static int r600_spi_sid(struct r600_shader_io * io)
553 {
554 int index, name = io->name;
555
556 /* These params are handled differently, they don't need
557 * semantic indices, so we'll use 0 for them.
558 */
559 if (name == TGSI_SEMANTIC_POSITION ||
560 name == TGSI_SEMANTIC_PSIZE ||
561 name == TGSI_SEMANTIC_EDGEFLAG ||
562 name == TGSI_SEMANTIC_FACE ||
563 name == TGSI_SEMANTIC_SAMPLEMASK)
564 index = 0;
565 else {
566 if (name == TGSI_SEMANTIC_GENERIC) {
567 /* For generic params simply use sid from tgsi */
568 index = io->sid;
569 } else {
570 /* For non-generic params - pack name and sid into 8 bits */
571 index = 0x80 | (name<<3) | (io->sid);
572 }
573
574 /* Make sure that all really used indices have nonzero value, so
575 * we can just compare it to 0 later instead of comparing the name
576 * with different values to detect special cases. */
577 index++;
578 }
579
580 return index;
581 };
582
583 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
584 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
585 {
586 switch (semantic_name) {
587 case TGSI_SEMANTIC_POSITION:
588 return 0;
589 case TGSI_SEMANTIC_PSIZE:
590 return 1;
591 case TGSI_SEMANTIC_CLIPDIST:
592 assert(index <= 1);
593 return 2 + index;
594 case TGSI_SEMANTIC_GENERIC:
595 if (index <= 63-4)
596 return 4 + index - 9;
597 else
598 /* same explanation as in the default statement,
599 * the only user hitting this is st/nine.
600 */
601 return 0;
602
603 /* patch indices are completely separate and thus start from 0 */
604 case TGSI_SEMANTIC_TESSOUTER:
605 return 0;
606 case TGSI_SEMANTIC_TESSINNER:
607 return 1;
608 case TGSI_SEMANTIC_PATCH:
609 return 2 + index;
610
611 default:
612 /* Don't fail here. The result of this function is only used
613 * for LS, TCS, TES, and GS, where legacy GL semantics can't
614 * occur, but this function is called for all vertex shaders
615 * before it's known whether LS will be compiled or not.
616 */
617 return 0;
618 }
619 }
620
621 /* turn input into interpolate on EG */
622 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
623 {
624 int r = 0;
625
626 if (ctx->shader->input[index].spi_sid) {
627 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
628 if (ctx->shader->input[index].interpolate > 0) {
629 evergreen_interp_assign_ij_index(ctx, index);
630 if (!ctx->use_llvm)
631 r = evergreen_interp_alu(ctx, index);
632 } else {
633 if (!ctx->use_llvm)
634 r = evergreen_interp_flat(ctx, index);
635 }
636 }
637 return r;
638 }
639
640 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
641 {
642 struct r600_bytecode_alu alu;
643 int i, r;
644 int gpr_front = ctx->shader->input[front].gpr;
645 int gpr_back = ctx->shader->input[back].gpr;
646
647 for (i = 0; i < 4; i++) {
648 memset(&alu, 0, sizeof(alu));
649 alu.op = ALU_OP3_CNDGT;
650 alu.is_op3 = 1;
651 alu.dst.write = 1;
652 alu.dst.sel = gpr_front;
653 alu.src[0].sel = ctx->face_gpr;
654 alu.src[1].sel = gpr_front;
655 alu.src[2].sel = gpr_back;
656
657 alu.dst.chan = i;
658 alu.src[1].chan = i;
659 alu.src[2].chan = i;
660 alu.last = (i==3);
661
662 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
663 return r;
664 }
665
666 return 0;
667 }
668
669 /* execute a single slot ALU calculation */
670 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
671 int dst_sel, int dst_chan,
672 int src0_sel, unsigned src0_chan_val,
673 int src1_sel, unsigned src1_chan_val)
674 {
675 struct r600_bytecode_alu alu;
676 int r, i;
677
678 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
679 for (i = 0; i < 4; i++) {
680 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
681 alu.op = op;
682 alu.src[0].sel = src0_sel;
683 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
684 alu.src[0].value = src0_chan_val;
685 else
686 alu.src[0].chan = src0_chan_val;
687 alu.src[1].sel = src1_sel;
688 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
689 alu.src[1].value = src1_chan_val;
690 else
691 alu.src[1].chan = src1_chan_val;
692 alu.dst.sel = dst_sel;
693 alu.dst.chan = i;
694 alu.dst.write = i == dst_chan;
695 alu.last = (i == 3);
696 r = r600_bytecode_add_alu(ctx->bc, &alu);
697 if (r)
698 return r;
699 }
700 return 0;
701 }
702
703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
704 alu.op = op;
705 alu.src[0].sel = src0_sel;
706 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
707 alu.src[0].value = src0_chan_val;
708 else
709 alu.src[0].chan = src0_chan_val;
710 alu.src[1].sel = src1_sel;
711 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
712 alu.src[1].value = src1_chan_val;
713 else
714 alu.src[1].chan = src1_chan_val;
715 alu.dst.sel = dst_sel;
716 alu.dst.chan = dst_chan;
717 alu.dst.write = 1;
718 alu.last = 1;
719 r = r600_bytecode_add_alu(ctx->bc, &alu);
720 if (r)
721 return r;
722 return 0;
723 }
724
725 /* execute a single slot ALU calculation */
726 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
727 int dst_sel, int dst_chan,
728 int src0_sel, unsigned src0_chan_val,
729 int src1_sel, unsigned src1_chan_val,
730 int src2_sel, unsigned src2_chan_val)
731 {
732 struct r600_bytecode_alu alu;
733 int r;
734
735 /* validate this for other ops */
736 assert(op == ALU_OP3_MULADD_UINT24);
737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
738 alu.op = op;
739 alu.src[0].sel = src0_sel;
740 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
741 alu.src[0].value = src0_chan_val;
742 else
743 alu.src[0].chan = src0_chan_val;
744 alu.src[1].sel = src1_sel;
745 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
746 alu.src[1].value = src1_chan_val;
747 else
748 alu.src[1].chan = src1_chan_val;
749 alu.src[2].sel = src2_sel;
750 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
751 alu.src[2].value = src2_chan_val;
752 else
753 alu.src[2].chan = src2_chan_val;
754 alu.dst.sel = dst_sel;
755 alu.dst.chan = dst_chan;
756 alu.is_op3 = 1;
757 alu.last = 1;
758 r = r600_bytecode_add_alu(ctx->bc, &alu);
759 if (r)
760 return r;
761 return 0;
762 }
763
764 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
765 {
766 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
767 }
768
769 static int r600_get_temp(struct r600_shader_ctx *ctx)
770 {
771 return ctx->temp_reg + ctx->max_driver_temp_used++;
772 }
773
774 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
775 {
776 int i;
777 i = ctx->shader->noutput++;
778 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
779 ctx->shader->output[i].sid = 0;
780 ctx->shader->output[i].gpr = 0;
781 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
782 ctx->shader->output[i].write_mask = 0x4;
783 ctx->shader->output[i].spi_sid = prim_id_sid;
784
785 return 0;
786 }
787
788 static int tgsi_declaration(struct r600_shader_ctx *ctx)
789 {
790 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
791 int r, i, j, count = d->Range.Last - d->Range.First + 1;
792
793 switch (d->Declaration.File) {
794 case TGSI_FILE_INPUT:
795 for (j = 0; j < count; j++) {
796 i = ctx->shader->ninput + j;
797 assert(i < Elements(ctx->shader->input));
798 ctx->shader->input[i].name = d->Semantic.Name;
799 ctx->shader->input[i].sid = d->Semantic.Index + j;
800 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
801 ctx->shader->input[i].interpolate_location = d->Interp.Location;
802 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
803 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
804 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
805 switch (ctx->shader->input[i].name) {
806 case TGSI_SEMANTIC_FACE:
807 if (ctx->face_gpr != -1)
808 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
809 else
810 ctx->face_gpr = ctx->shader->input[i].gpr;
811 break;
812 case TGSI_SEMANTIC_COLOR:
813 ctx->colors_used++;
814 break;
815 case TGSI_SEMANTIC_POSITION:
816 ctx->fragcoord_input = i;
817 break;
818 case TGSI_SEMANTIC_PRIMID:
819 /* set this for now */
820 ctx->shader->gs_prim_id_input = true;
821 ctx->shader->ps_prim_id_input = i;
822 break;
823 }
824 if (ctx->bc->chip_class >= EVERGREEN) {
825 if ((r = evergreen_interp_input(ctx, i)))
826 return r;
827 }
828 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
829 /* FIXME probably skip inputs if they aren't passed in the ring */
830 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
831 ctx->next_ring_offset += 16;
832 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
833 ctx->shader->gs_prim_id_input = true;
834 }
835 }
836 ctx->shader->ninput += count;
837 break;
838 case TGSI_FILE_OUTPUT:
839 for (j = 0; j < count; j++) {
840 i = ctx->shader->noutput + j;
841 assert(i < Elements(ctx->shader->output));
842 ctx->shader->output[i].name = d->Semantic.Name;
843 ctx->shader->output[i].sid = d->Semantic.Index + j;
844 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
845 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
846 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
847 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
848 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
849 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
850 switch (d->Semantic.Name) {
851 case TGSI_SEMANTIC_CLIPDIST:
852 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
853 ((d->Semantic.Index + j) << 2);
854 break;
855 case TGSI_SEMANTIC_PSIZE:
856 ctx->shader->vs_out_misc_write = 1;
857 ctx->shader->vs_out_point_size = 1;
858 break;
859 case TGSI_SEMANTIC_EDGEFLAG:
860 ctx->shader->vs_out_misc_write = 1;
861 ctx->shader->vs_out_edgeflag = 1;
862 ctx->edgeflag_output = i;
863 break;
864 case TGSI_SEMANTIC_VIEWPORT_INDEX:
865 ctx->shader->vs_out_misc_write = 1;
866 ctx->shader->vs_out_viewport = 1;
867 break;
868 case TGSI_SEMANTIC_LAYER:
869 ctx->shader->vs_out_misc_write = 1;
870 ctx->shader->vs_out_layer = 1;
871 break;
872 case TGSI_SEMANTIC_CLIPVERTEX:
873 ctx->clip_vertex_write = TRUE;
874 ctx->cv_output = i;
875 break;
876 }
877 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
878 ctx->gs_out_ring_offset += 16;
879 }
880 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
881 switch (d->Semantic.Name) {
882 case TGSI_SEMANTIC_COLOR:
883 ctx->shader->nr_ps_max_color_exports++;
884 break;
885 }
886 }
887 }
888 ctx->shader->noutput += count;
889 break;
890 case TGSI_FILE_TEMPORARY:
891 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
892 if (d->Array.ArrayID) {
893 r600_add_gpr_array(ctx->shader,
894 ctx->file_offset[TGSI_FILE_TEMPORARY] +
895 d->Range.First,
896 d->Range.Last - d->Range.First + 1, 0x0F);
897 }
898 }
899 break;
900
901 case TGSI_FILE_CONSTANT:
902 case TGSI_FILE_SAMPLER:
903 case TGSI_FILE_SAMPLER_VIEW:
904 case TGSI_FILE_ADDRESS:
905 break;
906
907 case TGSI_FILE_SYSTEM_VALUE:
908 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
909 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
910 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
911 break; /* Already handled from allocate_system_value_inputs */
912 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
913 if (!ctx->native_integers) {
914 struct r600_bytecode_alu alu;
915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
916
917 alu.op = ALU_OP1_INT_TO_FLT;
918 alu.src[0].sel = 0;
919 alu.src[0].chan = 3;
920
921 alu.dst.sel = 0;
922 alu.dst.chan = 3;
923 alu.dst.write = 1;
924 alu.last = 1;
925
926 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
927 return r;
928 }
929 break;
930 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
931 break;
932 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
933 break;
934 default:
935 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
936 return -EINVAL;
937 }
938 return 0;
939 }
940
941 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
942 {
943 struct tgsi_parse_context parse;
944 struct {
945 boolean enabled;
946 int *reg;
947 unsigned name, alternate_name;
948 } inputs[2] = {
949 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
950
951 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
952 };
953 int i, k, num_regs = 0;
954
955 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
956 return 0;
957 }
958
959 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
960 while (!tgsi_parse_end_of_tokens(&parse)) {
961 tgsi_parse_token(&parse);
962
963 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
964 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
965 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
966 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
967 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
968 {
969 int interpolate, location, k;
970
971 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
972 location = TGSI_INTERPOLATE_LOC_CENTER;
973 inputs[1].enabled = true; /* needs SAMPLEID */
974 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
975 location = TGSI_INTERPOLATE_LOC_CENTER;
976 /* Needs sample positions, currently those are always available */
977 } else {
978 location = TGSI_INTERPOLATE_LOC_CENTROID;
979 }
980
981 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
982 k = eg_get_interpolator_index(interpolate, location);
983 ctx->eg_interpolators[k].enabled = true;
984 }
985 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
986 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
987 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
988 for (k = 0; k < Elements(inputs); k++) {
989 if (d->Semantic.Name == inputs[k].name ||
990 d->Semantic.Name == inputs[k].alternate_name) {
991 inputs[k].enabled = true;
992 }
993 }
994 }
995 }
996 }
997
998 tgsi_parse_free(&parse);
999
1000 for (i = 0; i < Elements(inputs); i++) {
1001 boolean enabled = inputs[i].enabled;
1002 int *reg = inputs[i].reg;
1003 unsigned name = inputs[i].name;
1004
1005 if (enabled) {
1006 int gpr = gpr_offset + num_regs++;
1007
1008 // add to inputs, allocate a gpr
1009 k = ctx->shader->ninput ++;
1010 ctx->shader->input[k].name = name;
1011 ctx->shader->input[k].sid = 0;
1012 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1013 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1014 *reg = ctx->shader->input[k].gpr = gpr;
1015 }
1016 }
1017
1018 return gpr_offset + num_regs;
1019 }
1020
1021 /*
1022 * for evergreen we need to scan the shader to find the number of GPRs we need to
1023 * reserve for interpolation and system values
1024 *
1025 * we need to know if we are going to emit
1026 * any sample or centroid inputs
1027 * if perspective and linear are required
1028 */
1029 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1030 {
1031 int i;
1032 int num_baryc;
1033 struct tgsi_parse_context parse;
1034
1035 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1036
1037 for (i = 0; i < ctx->info.num_inputs; i++) {
1038 int k;
1039 /* skip position/face/mask/sampleid */
1040 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1041 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1042 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1043 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1044 continue;
1045
1046 k = eg_get_interpolator_index(
1047 ctx->info.input_interpolate[i],
1048 ctx->info.input_interpolate_loc[i]);
1049 if (k >= 0)
1050 ctx->eg_interpolators[k].enabled = TRUE;
1051 }
1052
1053 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1054 return 0;
1055 }
1056
1057 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1058 while (!tgsi_parse_end_of_tokens(&parse)) {
1059 tgsi_parse_token(&parse);
1060
1061 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1062 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1063 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1064 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1065 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1066 {
1067 int interpolate, location, k;
1068
1069 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1070 location = TGSI_INTERPOLATE_LOC_CENTER;
1071 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1072 location = TGSI_INTERPOLATE_LOC_CENTER;
1073 } else {
1074 location = TGSI_INTERPOLATE_LOC_CENTROID;
1075 }
1076
1077 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1078 k = eg_get_interpolator_index(interpolate, location);
1079 ctx->eg_interpolators[k].enabled = true;
1080 }
1081 }
1082 }
1083
1084 tgsi_parse_free(&parse);
1085
1086 /* assign gpr to each interpolator according to priority */
1087 num_baryc = 0;
1088 for (i = 0; i < Elements(ctx->eg_interpolators); i++) {
1089 if (ctx->eg_interpolators[i].enabled) {
1090 ctx->eg_interpolators[i].ij_index = num_baryc;
1091 num_baryc ++;
1092 }
1093 }
1094
1095 /* XXX PULL MODEL and LINE STIPPLE */
1096
1097 num_baryc = (num_baryc + 1) >> 1;
1098 return allocate_system_value_inputs(ctx, num_baryc);
1099 }
1100
1101 /* sample_id_sel == NULL means fetch for current sample */
1102 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1103 {
1104 struct r600_bytecode_vtx vtx;
1105 int r, t1;
1106
1107 assert(ctx->fixed_pt_position_gpr != -1);
1108
1109 t1 = r600_get_temp(ctx);
1110
1111 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1112 vtx.op = FETCH_OP_VFETCH;
1113 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1114 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1115 if (sample_id == NULL) {
1116 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1117 vtx.src_sel_x = 3;
1118 }
1119 else {
1120 struct r600_bytecode_alu alu;
1121
1122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1123 alu.op = ALU_OP1_MOV;
1124 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1125 alu.dst.sel = t1;
1126 alu.dst.write = 1;
1127 alu.last = 1;
1128 r = r600_bytecode_add_alu(ctx->bc, &alu);
1129 if (r)
1130 return r;
1131
1132 vtx.src_gpr = t1;
1133 vtx.src_sel_x = 0;
1134 }
1135 vtx.mega_fetch_count = 16;
1136 vtx.dst_gpr = t1;
1137 vtx.dst_sel_x = 0;
1138 vtx.dst_sel_y = 1;
1139 vtx.dst_sel_z = 2;
1140 vtx.dst_sel_w = 3;
1141 vtx.data_format = FMT_32_32_32_32_FLOAT;
1142 vtx.num_format_all = 2;
1143 vtx.format_comp_all = 1;
1144 vtx.use_const_fields = 0;
1145 vtx.offset = 1; // first element is size of buffer
1146 vtx.endian = r600_endian_swap(32);
1147 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1148
1149 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1150 if (r)
1151 return r;
1152
1153 return t1;
1154 }
1155
1156 static void tgsi_src(struct r600_shader_ctx *ctx,
1157 const struct tgsi_full_src_register *tgsi_src,
1158 struct r600_shader_src *r600_src)
1159 {
1160 memset(r600_src, 0, sizeof(*r600_src));
1161 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1162 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1163 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1164 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1165 r600_src->neg = tgsi_src->Register.Negate;
1166 r600_src->abs = tgsi_src->Register.Absolute;
1167
1168 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1169 int index;
1170 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1171 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1172 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1173
1174 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1175 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1176 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1177 return;
1178 }
1179 index = tgsi_src->Register.Index;
1180 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1181 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1182 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1183 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1184 r600_src->swizzle[0] = 2; // Z value
1185 r600_src->swizzle[1] = 2;
1186 r600_src->swizzle[2] = 2;
1187 r600_src->swizzle[3] = 2;
1188 r600_src->sel = ctx->face_gpr;
1189 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1190 r600_src->swizzle[0] = 3; // W value
1191 r600_src->swizzle[1] = 3;
1192 r600_src->swizzle[2] = 3;
1193 r600_src->swizzle[3] = 3;
1194 r600_src->sel = ctx->fixed_pt_position_gpr;
1195 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1196 r600_src->swizzle[0] = 0;
1197 r600_src->swizzle[1] = 1;
1198 r600_src->swizzle[2] = 4;
1199 r600_src->swizzle[3] = 4;
1200 r600_src->sel = load_sample_position(ctx, NULL, -1);
1201 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1202 r600_src->swizzle[0] = 3;
1203 r600_src->swizzle[1] = 3;
1204 r600_src->swizzle[2] = 3;
1205 r600_src->swizzle[3] = 3;
1206 r600_src->sel = 0;
1207 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1208 r600_src->swizzle[0] = 0;
1209 r600_src->swizzle[1] = 0;
1210 r600_src->swizzle[2] = 0;
1211 r600_src->swizzle[3] = 0;
1212 r600_src->sel = 0;
1213 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1214 r600_src->swizzle[0] = 3;
1215 r600_src->swizzle[1] = 3;
1216 r600_src->swizzle[2] = 3;
1217 r600_src->swizzle[3] = 3;
1218 r600_src->sel = 1;
1219 }
1220 } else {
1221 if (tgsi_src->Register.Indirect)
1222 r600_src->rel = V_SQ_REL_RELATIVE;
1223 r600_src->sel = tgsi_src->Register.Index;
1224 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1225 }
1226 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1227 if (tgsi_src->Register.Dimension) {
1228 r600_src->kc_bank = tgsi_src->Dimension.Index;
1229 if (tgsi_src->Dimension.Indirect) {
1230 r600_src->kc_rel = 1;
1231 }
1232 }
1233 }
1234 }
1235
1236 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1237 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1238 unsigned int dst_reg)
1239 {
1240 struct r600_bytecode_vtx vtx;
1241 unsigned int ar_reg;
1242 int r;
1243
1244 if (offset) {
1245 struct r600_bytecode_alu alu;
1246
1247 memset(&alu, 0, sizeof(alu));
1248
1249 alu.op = ALU_OP2_ADD_INT;
1250 alu.src[0].sel = ctx->bc->ar_reg;
1251 alu.src[0].chan = ar_chan;
1252
1253 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1254 alu.src[1].value = offset;
1255
1256 alu.dst.sel = dst_reg;
1257 alu.dst.chan = ar_chan;
1258 alu.dst.write = 1;
1259 alu.last = 1;
1260
1261 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1262 return r;
1263
1264 ar_reg = dst_reg;
1265 } else {
1266 ar_reg = ctx->bc->ar_reg;
1267 }
1268
1269 memset(&vtx, 0, sizeof(vtx));
1270 vtx.buffer_id = cb_idx;
1271 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1272 vtx.src_gpr = ar_reg;
1273 vtx.src_sel_x = ar_chan;
1274 vtx.mega_fetch_count = 16;
1275 vtx.dst_gpr = dst_reg;
1276 vtx.dst_sel_x = 0; /* SEL_X */
1277 vtx.dst_sel_y = 1; /* SEL_Y */
1278 vtx.dst_sel_z = 2; /* SEL_Z */
1279 vtx.dst_sel_w = 3; /* SEL_W */
1280 vtx.data_format = FMT_32_32_32_32_FLOAT;
1281 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1282 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1283 vtx.endian = r600_endian_swap(32);
1284 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1285
1286 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1287 return r;
1288
1289 return 0;
1290 }
1291
1292 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1293 {
1294 struct r600_bytecode_vtx vtx;
1295 int r;
1296 unsigned index = src->Register.Index;
1297 unsigned vtx_id = src->Dimension.Index;
1298 int offset_reg = vtx_id / 3;
1299 int offset_chan = vtx_id % 3;
1300
1301 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1302 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1303
1304 if (offset_reg == 0 && offset_chan == 2)
1305 offset_chan = 3;
1306
1307 if (src->Dimension.Indirect) {
1308 int treg[3];
1309 int t2;
1310 struct r600_bytecode_alu alu;
1311 int r, i;
1312
1313 /* you have got to be shitting me -
1314 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1315 at least this is what fglrx seems to do. */
1316 for (i = 0; i < 3; i++) {
1317 treg[i] = r600_get_temp(ctx);
1318 }
1319 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1320
1321 t2 = r600_get_temp(ctx);
1322 for (i = 0; i < 3; i++) {
1323 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1324 alu.op = ALU_OP1_MOV;
1325 alu.src[0].sel = 0;
1326 alu.src[0].chan = i == 2 ? 3 : i;
1327 alu.dst.sel = treg[i];
1328 alu.dst.chan = 0;
1329 alu.dst.write = 1;
1330 alu.last = 1;
1331 r = r600_bytecode_add_alu(ctx->bc, &alu);
1332 if (r)
1333 return r;
1334 }
1335 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1336 alu.op = ALU_OP1_MOV;
1337 alu.src[0].sel = treg[0];
1338 alu.src[0].rel = 1;
1339 alu.dst.sel = t2;
1340 alu.dst.write = 1;
1341 alu.last = 1;
1342 r = r600_bytecode_add_alu(ctx->bc, &alu);
1343 if (r)
1344 return r;
1345 offset_reg = t2;
1346 }
1347
1348
1349 memset(&vtx, 0, sizeof(vtx));
1350 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1351 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1352 vtx.src_gpr = offset_reg;
1353 vtx.src_sel_x = offset_chan;
1354 vtx.offset = index * 16; /*bytes*/
1355 vtx.mega_fetch_count = 16;
1356 vtx.dst_gpr = dst_reg;
1357 vtx.dst_sel_x = 0; /* SEL_X */
1358 vtx.dst_sel_y = 1; /* SEL_Y */
1359 vtx.dst_sel_z = 2; /* SEL_Z */
1360 vtx.dst_sel_w = 3; /* SEL_W */
1361 if (ctx->bc->chip_class >= EVERGREEN) {
1362 vtx.use_const_fields = 1;
1363 } else {
1364 vtx.data_format = FMT_32_32_32_32_FLOAT;
1365 }
1366
1367 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1368 return r;
1369
1370 return 0;
1371 }
1372
1373 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1374 {
1375 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1376 int i;
1377
1378 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1379 struct tgsi_full_src_register *src = &inst->Src[i];
1380
1381 if (src->Register.File == TGSI_FILE_INPUT) {
1382 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1383 /* primitive id is in R0.z */
1384 ctx->src[i].sel = 0;
1385 ctx->src[i].swizzle[0] = 2;
1386 }
1387 }
1388 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1389 int treg = r600_get_temp(ctx);
1390
1391 fetch_gs_input(ctx, src, treg);
1392 ctx->src[i].sel = treg;
1393 }
1394 }
1395 return 0;
1396 }
1397
1398 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1399 {
1400 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1401 struct r600_bytecode_alu alu;
1402 int i, j, k, nconst, r;
1403
1404 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1405 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1406 nconst++;
1407 }
1408 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1409 }
1410 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1411 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1412 continue;
1413 }
1414
1415 if (ctx->src[i].rel) {
1416 int chan = inst->Src[i].Indirect.Swizzle;
1417 int treg = r600_get_temp(ctx);
1418 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1419 return r;
1420
1421 ctx->src[i].kc_bank = 0;
1422 ctx->src[i].kc_rel = 0;
1423 ctx->src[i].sel = treg;
1424 ctx->src[i].rel = 0;
1425 j--;
1426 } else if (j > 0) {
1427 int treg = r600_get_temp(ctx);
1428 for (k = 0; k < 4; k++) {
1429 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1430 alu.op = ALU_OP1_MOV;
1431 alu.src[0].sel = ctx->src[i].sel;
1432 alu.src[0].chan = k;
1433 alu.src[0].rel = ctx->src[i].rel;
1434 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1435 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1436 alu.dst.sel = treg;
1437 alu.dst.chan = k;
1438 alu.dst.write = 1;
1439 if (k == 3)
1440 alu.last = 1;
1441 r = r600_bytecode_add_alu(ctx->bc, &alu);
1442 if (r)
1443 return r;
1444 }
1445 ctx->src[i].sel = treg;
1446 ctx->src[i].rel =0;
1447 j--;
1448 }
1449 }
1450 return 0;
1451 }
1452
1453 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1454 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1455 {
1456 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1457 struct r600_bytecode_alu alu;
1458 int i, j, k, nliteral, r;
1459
1460 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1461 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1462 nliteral++;
1463 }
1464 }
1465 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1466 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1467 int treg = r600_get_temp(ctx);
1468 for (k = 0; k < 4; k++) {
1469 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1470 alu.op = ALU_OP1_MOV;
1471 alu.src[0].sel = ctx->src[i].sel;
1472 alu.src[0].chan = k;
1473 alu.src[0].value = ctx->src[i].value[k];
1474 alu.dst.sel = treg;
1475 alu.dst.chan = k;
1476 alu.dst.write = 1;
1477 if (k == 3)
1478 alu.last = 1;
1479 r = r600_bytecode_add_alu(ctx->bc, &alu);
1480 if (r)
1481 return r;
1482 }
1483 ctx->src[i].sel = treg;
1484 j--;
1485 }
1486 }
1487 return 0;
1488 }
1489
1490 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1491 {
1492 int i, r, count = ctx->shader->ninput;
1493
1494 for (i = 0; i < count; i++) {
1495 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1496 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1497 if (r)
1498 return r;
1499 }
1500 }
1501 return 0;
1502 }
1503
1504 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1505 int stream, unsigned *stream_item_size)
1506 {
1507 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1508 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1509 int i, j, r;
1510
1511 /* Sanity checking. */
1512 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1513 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1514 r = -EINVAL;
1515 goto out_err;
1516 }
1517 for (i = 0; i < so->num_outputs; i++) {
1518 if (so->output[i].output_buffer >= 4) {
1519 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1520 so->output[i].output_buffer);
1521 r = -EINVAL;
1522 goto out_err;
1523 }
1524 }
1525
1526 /* Initialize locations where the outputs are stored. */
1527 for (i = 0; i < so->num_outputs; i++) {
1528
1529 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1530 start_comp[i] = so->output[i].start_component;
1531 /* Lower outputs with dst_offset < start_component.
1532 *
1533 * We can only output 4D vectors with a write mask, e.g. we can
1534 * only output the W component at offset 3, etc. If we want
1535 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1536 * to move it to X and output X. */
1537 if (so->output[i].dst_offset < so->output[i].start_component) {
1538 unsigned tmp = r600_get_temp(ctx);
1539
1540 for (j = 0; j < so->output[i].num_components; j++) {
1541 struct r600_bytecode_alu alu;
1542 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1543 alu.op = ALU_OP1_MOV;
1544 alu.src[0].sel = so_gpr[i];
1545 alu.src[0].chan = so->output[i].start_component + j;
1546
1547 alu.dst.sel = tmp;
1548 alu.dst.chan = j;
1549 alu.dst.write = 1;
1550 if (j == so->output[i].num_components - 1)
1551 alu.last = 1;
1552 r = r600_bytecode_add_alu(ctx->bc, &alu);
1553 if (r)
1554 return r;
1555 }
1556 start_comp[i] = 0;
1557 so_gpr[i] = tmp;
1558 }
1559 }
1560
1561 /* Write outputs to buffers. */
1562 for (i = 0; i < so->num_outputs; i++) {
1563 struct r600_bytecode_output output;
1564
1565 if (stream != -1 && stream != so->output[i].output_buffer)
1566 continue;
1567
1568 memset(&output, 0, sizeof(struct r600_bytecode_output));
1569 output.gpr = so_gpr[i];
1570 output.elem_size = so->output[i].num_components - 1;
1571 if (output.elem_size == 2)
1572 output.elem_size = 3; // 3 not supported, write 4 with junk at end
1573 output.array_base = so->output[i].dst_offset - start_comp[i];
1574 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1575 output.burst_count = 1;
1576 /* array_size is an upper limit for the burst_count
1577 * with MEM_STREAM instructions */
1578 output.array_size = 0xFFF;
1579 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
1580
1581 if (ctx->bc->chip_class >= EVERGREEN) {
1582 switch (so->output[i].output_buffer) {
1583 case 0:
1584 output.op = CF_OP_MEM_STREAM0_BUF0;
1585 break;
1586 case 1:
1587 output.op = CF_OP_MEM_STREAM0_BUF1;
1588 break;
1589 case 2:
1590 output.op = CF_OP_MEM_STREAM0_BUF2;
1591 break;
1592 case 3:
1593 output.op = CF_OP_MEM_STREAM0_BUF3;
1594 break;
1595 }
1596 output.op += so->output[i].stream * 4;
1597 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
1598 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
1599 } else {
1600 switch (so->output[i].output_buffer) {
1601 case 0:
1602 output.op = CF_OP_MEM_STREAM0;
1603 break;
1604 case 1:
1605 output.op = CF_OP_MEM_STREAM1;
1606 break;
1607 case 2:
1608 output.op = CF_OP_MEM_STREAM2;
1609 break;
1610 case 3:
1611 output.op = CF_OP_MEM_STREAM3;
1612 break;
1613 }
1614 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
1615 }
1616 r = r600_bytecode_add_output(ctx->bc, &output);
1617 if (r)
1618 goto out_err;
1619 }
1620 return 0;
1621 out_err:
1622 return r;
1623 }
1624
1625 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
1626 {
1627 struct r600_bytecode_alu alu;
1628 unsigned reg;
1629
1630 if (!ctx->shader->vs_out_edgeflag)
1631 return;
1632
1633 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
1634
1635 /* clamp(x, 0, 1) */
1636 memset(&alu, 0, sizeof(alu));
1637 alu.op = ALU_OP1_MOV;
1638 alu.src[0].sel = reg;
1639 alu.dst.sel = reg;
1640 alu.dst.write = 1;
1641 alu.dst.clamp = 1;
1642 alu.last = 1;
1643 r600_bytecode_add_alu(ctx->bc, &alu);
1644
1645 memset(&alu, 0, sizeof(alu));
1646 alu.op = ALU_OP1_FLT_TO_INT;
1647 alu.src[0].sel = reg;
1648 alu.dst.sel = reg;
1649 alu.dst.write = 1;
1650 alu.last = 1;
1651 r600_bytecode_add_alu(ctx->bc, &alu);
1652 }
1653
1654 static int generate_gs_copy_shader(struct r600_context *rctx,
1655 struct r600_pipe_shader *gs,
1656 struct pipe_stream_output_info *so)
1657 {
1658 struct r600_shader_ctx ctx = {};
1659 struct r600_shader *gs_shader = &gs->shader;
1660 struct r600_pipe_shader *cshader;
1661 int ocnt = gs_shader->noutput;
1662 struct r600_bytecode_alu alu;
1663 struct r600_bytecode_vtx vtx;
1664 struct r600_bytecode_output output;
1665 struct r600_bytecode_cf *cf_jump, *cf_pop,
1666 *last_exp_pos = NULL, *last_exp_param = NULL;
1667 int i, j, next_clip_pos = 61, next_param = 0;
1668 int ring;
1669
1670 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1671 if (!cshader)
1672 return 0;
1673
1674 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1675 sizeof(struct r600_shader_io));
1676
1677 cshader->shader.noutput = ocnt;
1678
1679 ctx.shader = &cshader->shader;
1680 ctx.bc = &ctx.shader->bc;
1681 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1682
1683 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1684 rctx->screen->has_compressed_msaa_texturing);
1685
1686 ctx.bc->isa = rctx->isa;
1687
1688 cf_jump = NULL;
1689 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
1690
1691 /* R0.x = R0.x & 0x3fffffff */
1692 memset(&alu, 0, sizeof(alu));
1693 alu.op = ALU_OP2_AND_INT;
1694 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1695 alu.src[1].value = 0x3fffffff;
1696 alu.dst.write = 1;
1697 r600_bytecode_add_alu(ctx.bc, &alu);
1698
1699 /* R0.y = R0.x >> 30 */
1700 memset(&alu, 0, sizeof(alu));
1701 alu.op = ALU_OP2_LSHR_INT;
1702 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1703 alu.src[1].value = 0x1e;
1704 alu.dst.chan = 1;
1705 alu.dst.write = 1;
1706 alu.last = 1;
1707 r600_bytecode_add_alu(ctx.bc, &alu);
1708
1709 /* fetch vertex data from GSVS ring */
1710 for (i = 0; i < ocnt; ++i) {
1711 struct r600_shader_io *out = &ctx.shader->output[i];
1712
1713 out->gpr = i + 1;
1714 out->ring_offset = i * 16;
1715
1716 memset(&vtx, 0, sizeof(vtx));
1717 vtx.op = FETCH_OP_VFETCH;
1718 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1719 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1720 vtx.mega_fetch_count = 16;
1721 vtx.offset = out->ring_offset;
1722 vtx.dst_gpr = out->gpr;
1723 vtx.src_gpr = 0;
1724 vtx.dst_sel_x = 0;
1725 vtx.dst_sel_y = 1;
1726 vtx.dst_sel_z = 2;
1727 vtx.dst_sel_w = 3;
1728 if (rctx->b.chip_class >= EVERGREEN) {
1729 vtx.use_const_fields = 1;
1730 } else {
1731 vtx.data_format = FMT_32_32_32_32_FLOAT;
1732 }
1733
1734 r600_bytecode_add_vtx(ctx.bc, &vtx);
1735 }
1736 ctx.temp_reg = i + 1;
1737 for (ring = 3; ring >= 0; --ring) {
1738 bool enabled = false;
1739 for (i = 0; i < so->num_outputs; i++) {
1740 if (so->output[i].stream == ring) {
1741 enabled = true;
1742 break;
1743 }
1744 }
1745 if (ring != 0 && !enabled) {
1746 cshader->shader.ring_item_sizes[ring] = 0;
1747 continue;
1748 }
1749
1750 if (cf_jump) {
1751 // Patch up jump label
1752 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1753 cf_pop = ctx.bc->cf_last;
1754
1755 cf_jump->cf_addr = cf_pop->id + 2;
1756 cf_jump->pop_count = 1;
1757 cf_pop->cf_addr = cf_pop->id + 2;
1758 cf_pop->pop_count = 1;
1759 }
1760
1761 /* PRED_SETE_INT __, R0.y, ring */
1762 memset(&alu, 0, sizeof(alu));
1763 alu.op = ALU_OP2_PRED_SETE_INT;
1764 alu.src[0].chan = 1;
1765 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1766 alu.src[1].value = ring;
1767 alu.execute_mask = 1;
1768 alu.update_pred = 1;
1769 alu.last = 1;
1770 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1771
1772 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1773 cf_jump = ctx.bc->cf_last;
1774
1775 if (enabled)
1776 emit_streamout(&ctx, so, ring, &cshader->shader.ring_item_sizes[ring]);
1777 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
1778 }
1779
1780 /* bc adds nops - copy it */
1781 if (ctx.bc->chip_class == R600) {
1782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1783 alu.op = ALU_OP0_NOP;
1784 alu.last = 1;
1785 r600_bytecode_add_alu(ctx.bc, &alu);
1786
1787 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1788 }
1789
1790 /* export vertex data */
1791 /* XXX factor out common code with r600_shader_from_tgsi ? */
1792 for (i = 0; i < ocnt; ++i) {
1793 struct r600_shader_io *out = &ctx.shader->output[i];
1794 bool instream0 = true;
1795 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1796 continue;
1797
1798 for (j = 0; j < so->num_outputs; j++) {
1799 if (so->output[j].register_index == i) {
1800 if (so->output[j].stream == 0)
1801 break;
1802 if (so->output[j].stream > 0)
1803 instream0 = false;
1804 }
1805 }
1806 if (!instream0)
1807 continue;
1808 memset(&output, 0, sizeof(output));
1809 output.gpr = out->gpr;
1810 output.elem_size = 3;
1811 output.swizzle_x = 0;
1812 output.swizzle_y = 1;
1813 output.swizzle_z = 2;
1814 output.swizzle_w = 3;
1815 output.burst_count = 1;
1816 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1817 output.op = CF_OP_EXPORT;
1818 switch (out->name) {
1819 case TGSI_SEMANTIC_POSITION:
1820 output.array_base = 60;
1821 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1822 break;
1823
1824 case TGSI_SEMANTIC_PSIZE:
1825 output.array_base = 61;
1826 if (next_clip_pos == 61)
1827 next_clip_pos = 62;
1828 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1829 output.swizzle_y = 7;
1830 output.swizzle_z = 7;
1831 output.swizzle_w = 7;
1832 ctx.shader->vs_out_misc_write = 1;
1833 ctx.shader->vs_out_point_size = 1;
1834 break;
1835 case TGSI_SEMANTIC_LAYER:
1836 if (out->spi_sid) {
1837 /* duplicate it as PARAM to pass to the pixel shader */
1838 output.array_base = next_param++;
1839 r600_bytecode_add_output(ctx.bc, &output);
1840 last_exp_param = ctx.bc->cf_last;
1841 }
1842 output.array_base = 61;
1843 if (next_clip_pos == 61)
1844 next_clip_pos = 62;
1845 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1846 output.swizzle_x = 7;
1847 output.swizzle_y = 7;
1848 output.swizzle_z = 0;
1849 output.swizzle_w = 7;
1850 ctx.shader->vs_out_misc_write = 1;
1851 ctx.shader->vs_out_layer = 1;
1852 break;
1853 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1854 if (out->spi_sid) {
1855 /* duplicate it as PARAM to pass to the pixel shader */
1856 output.array_base = next_param++;
1857 r600_bytecode_add_output(ctx.bc, &output);
1858 last_exp_param = ctx.bc->cf_last;
1859 }
1860 output.array_base = 61;
1861 if (next_clip_pos == 61)
1862 next_clip_pos = 62;
1863 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1864 ctx.shader->vs_out_misc_write = 1;
1865 ctx.shader->vs_out_viewport = 1;
1866 output.swizzle_x = 7;
1867 output.swizzle_y = 7;
1868 output.swizzle_z = 7;
1869 output.swizzle_w = 0;
1870 break;
1871 case TGSI_SEMANTIC_CLIPDIST:
1872 /* spi_sid is 0 for clipdistance outputs that were generated
1873 * for clipvertex - we don't need to pass them to PS */
1874 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
1875 if (out->spi_sid) {
1876 /* duplicate it as PARAM to pass to the pixel shader */
1877 output.array_base = next_param++;
1878 r600_bytecode_add_output(ctx.bc, &output);
1879 last_exp_param = ctx.bc->cf_last;
1880 }
1881 output.array_base = next_clip_pos++;
1882 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1883 break;
1884 case TGSI_SEMANTIC_FOG:
1885 output.swizzle_y = 4; /* 0 */
1886 output.swizzle_z = 4; /* 0 */
1887 output.swizzle_w = 5; /* 1 */
1888 break;
1889 default:
1890 output.array_base = next_param++;
1891 break;
1892 }
1893 r600_bytecode_add_output(ctx.bc, &output);
1894 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1895 last_exp_param = ctx.bc->cf_last;
1896 else
1897 last_exp_pos = ctx.bc->cf_last;
1898 }
1899
1900 if (!last_exp_pos) {
1901 memset(&output, 0, sizeof(output));
1902 output.gpr = 0;
1903 output.elem_size = 3;
1904 output.swizzle_x = 7;
1905 output.swizzle_y = 7;
1906 output.swizzle_z = 7;
1907 output.swizzle_w = 7;
1908 output.burst_count = 1;
1909 output.type = 2;
1910 output.op = CF_OP_EXPORT;
1911 output.array_base = 60;
1912 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1913 r600_bytecode_add_output(ctx.bc, &output);
1914 last_exp_pos = ctx.bc->cf_last;
1915 }
1916
1917 if (!last_exp_param) {
1918 memset(&output, 0, sizeof(output));
1919 output.gpr = 0;
1920 output.elem_size = 3;
1921 output.swizzle_x = 7;
1922 output.swizzle_y = 7;
1923 output.swizzle_z = 7;
1924 output.swizzle_w = 7;
1925 output.burst_count = 1;
1926 output.type = 2;
1927 output.op = CF_OP_EXPORT;
1928 output.array_base = next_param++;
1929 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1930 r600_bytecode_add_output(ctx.bc, &output);
1931 last_exp_param = ctx.bc->cf_last;
1932 }
1933
1934 last_exp_pos->op = CF_OP_EXPORT_DONE;
1935 last_exp_param->op = CF_OP_EXPORT_DONE;
1936
1937 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1938 cf_pop = ctx.bc->cf_last;
1939
1940 cf_jump->cf_addr = cf_pop->id + 2;
1941 cf_jump->pop_count = 1;
1942 cf_pop->cf_addr = cf_pop->id + 2;
1943 cf_pop->pop_count = 1;
1944
1945 if (ctx.bc->chip_class == CAYMAN)
1946 cm_bytecode_add_cf_end(ctx.bc);
1947 else {
1948 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1949 ctx.bc->cf_last->end_of_program = 1;
1950 }
1951
1952 gs->gs_copy_shader = cshader;
1953 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
1954
1955 ctx.bc->nstack = 1;
1956
1957 return r600_bytecode_build(ctx.bc);
1958 }
1959
1960 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
1961 {
1962 if (ind) {
1963 struct r600_bytecode_alu alu;
1964 int r;
1965
1966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1967 alu.op = ALU_OP2_ADD_INT;
1968 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
1969 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1970 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
1971 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
1972 alu.dst.write = 1;
1973 alu.last = 1;
1974 r = r600_bytecode_add_alu(ctx->bc, &alu);
1975 if (r)
1976 return r;
1977 }
1978 return 0;
1979 }
1980
1981 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
1982 {
1983 struct r600_bytecode_output output;
1984 int i, k, ring_offset;
1985 int effective_stream = stream == -1 ? 0 : stream;
1986 int idx = 0;
1987
1988 for (i = 0; i < ctx->shader->noutput; i++) {
1989 if (ctx->gs_for_vs) {
1990 /* for ES we need to lookup corresponding ring offset expected by GS
1991 * (map this output to GS input by name and sid) */
1992 /* FIXME precompute offsets */
1993 ring_offset = -1;
1994 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1995 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1996 struct r600_shader_io *out = &ctx->shader->output[i];
1997 if (in->name == out->name && in->sid == out->sid)
1998 ring_offset = in->ring_offset;
1999 }
2000
2001 if (ring_offset == -1)
2002 continue;
2003 } else {
2004 ring_offset = idx * 16;
2005 idx++;
2006 }
2007
2008 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2009 continue;
2010 /* next_ring_offset after parsing input decls contains total size of
2011 * single vertex data, gs_next_vertex - current vertex index */
2012 if (!ind)
2013 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2014
2015 memset(&output, 0, sizeof(struct r600_bytecode_output));
2016 output.gpr = ctx->shader->output[i].gpr;
2017 output.elem_size = 3;
2018 output.comp_mask = 0xF;
2019 output.burst_count = 1;
2020
2021 if (ind)
2022 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2023 else
2024 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2025
2026 switch (stream) {
2027 default:
2028 case 0:
2029 output.op = CF_OP_MEM_RING; break;
2030 case 1:
2031 output.op = CF_OP_MEM_RING1; break;
2032 case 2:
2033 output.op = CF_OP_MEM_RING2; break;
2034 case 3:
2035 output.op = CF_OP_MEM_RING3; break;
2036 }
2037
2038 if (ind) {
2039 output.array_base = ring_offset >> 2; /* in dwords */
2040 output.array_size = 0xfff;
2041 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2042 } else
2043 output.array_base = ring_offset >> 2; /* in dwords */
2044 r600_bytecode_add_output(ctx->bc, &output);
2045 }
2046
2047 ++ctx->gs_next_vertex;
2048 return 0;
2049 }
2050
2051 static int r600_shader_from_tgsi(struct r600_context *rctx,
2052 struct r600_pipe_shader *pipeshader,
2053 union r600_shader_key key)
2054 {
2055 struct r600_screen *rscreen = rctx->screen;
2056 struct r600_shader *shader = &pipeshader->shader;
2057 struct tgsi_token *tokens = pipeshader->selector->tokens;
2058 struct pipe_stream_output_info so = pipeshader->selector->so;
2059 struct tgsi_full_immediate *immediate;
2060 struct r600_shader_ctx ctx;
2061 struct r600_bytecode_output output[32];
2062 unsigned output_done, noutput;
2063 unsigned opcode;
2064 int i, j, k, r = 0;
2065 int next_param_base = 0, next_clip_base;
2066 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2067 /* Declarations used by llvm code */
2068 bool use_llvm = false;
2069 bool indirect_gprs;
2070 bool ring_outputs = false;
2071 bool pos_emitted = false;
2072
2073 #ifdef R600_USE_LLVM
2074 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
2075 #endif
2076 ctx.bc = &shader->bc;
2077 ctx.shader = shader;
2078 ctx.native_integers = true;
2079
2080
2081 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2082 rscreen->has_compressed_msaa_texturing);
2083 ctx.tokens = tokens;
2084 tgsi_scan_shader(tokens, &ctx.info);
2085 shader->indirect_files = ctx.info.indirect_files;
2086
2087 shader->uses_doubles = ctx.info.uses_doubles;
2088
2089 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2090 tgsi_parse_init(&ctx.parse, tokens);
2091 ctx.type = ctx.info.processor;
2092 shader->processor_type = ctx.type;
2093 ctx.bc->type = shader->processor_type;
2094
2095 switch (ctx.type) {
2096 case TGSI_PROCESSOR_VERTEX:
2097 shader->vs_as_gs_a = key.vs.as_gs_a;
2098 shader->vs_as_es = key.vs.as_es;
2099 shader->vs_as_ls = key.vs.as_ls;
2100 if (shader->vs_as_es)
2101 ring_outputs = true;
2102 break;
2103 case TGSI_PROCESSOR_GEOMETRY:
2104 ring_outputs = true;
2105 break;
2106 case TGSI_PROCESSOR_TESS_CTRL:
2107 shader->tcs_prim_mode = key.tcs.prim_mode;
2108 break;
2109 case TGSI_PROCESSOR_TESS_EVAL:
2110 shader->tes_as_es = key.tes.as_es;
2111 if (shader->tes_as_es)
2112 ring_outputs = true;
2113 break;
2114 case TGSI_PROCESSOR_FRAGMENT:
2115 shader->two_side = key.ps.color_two_side;
2116 break;
2117 default:
2118 break;
2119 }
2120
2121 if (shader->vs_as_es || shader->tes_as_es) {
2122 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
2123 } else {
2124 ctx.gs_for_vs = NULL;
2125 }
2126
2127 ctx.next_ring_offset = 0;
2128 ctx.gs_out_ring_offset = 0;
2129 ctx.gs_next_vertex = 0;
2130 ctx.gs_stream_output_info = &so;
2131
2132 ctx.face_gpr = -1;
2133 ctx.fixed_pt_position_gpr = -1;
2134 ctx.fragcoord_input = -1;
2135 ctx.colors_used = 0;
2136 ctx.clip_vertex_write = 0;
2137
2138 shader->nr_ps_color_exports = 0;
2139 shader->nr_ps_max_color_exports = 0;
2140
2141
2142 /* register allocations */
2143 /* Values [0,127] correspond to GPR[0..127].
2144 * Values [128,159] correspond to constant buffer bank 0
2145 * Values [160,191] correspond to constant buffer bank 1
2146 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
2147 * Values [256,287] correspond to constant buffer bank 2 (EG)
2148 * Values [288,319] correspond to constant buffer bank 3 (EG)
2149 * Other special values are shown in the list below.
2150 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
2151 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
2152 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
2153 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
2154 * 248 SQ_ALU_SRC_0: special constant 0.0.
2155 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
2156 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
2157 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
2158 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
2159 * 253 SQ_ALU_SRC_LITERAL: literal constant.
2160 * 254 SQ_ALU_SRC_PV: previous vector result.
2161 * 255 SQ_ALU_SRC_PS: previous scalar result.
2162 */
2163 for (i = 0; i < TGSI_FILE_COUNT; i++) {
2164 ctx.file_offset[i] = 0;
2165 }
2166
2167 #ifdef R600_USE_LLVM
2168 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
2169 fprintf(stderr, "Warning: R600 LLVM backend does not support "
2170 "indirect adressing. Falling back to TGSI "
2171 "backend.\n");
2172 use_llvm = 0;
2173 }
2174 #endif
2175 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
2176 ctx.file_offset[TGSI_FILE_INPUT] = 1;
2177 if (!use_llvm) {
2178 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
2179 }
2180 }
2181 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
2182 if (ctx.bc->chip_class >= EVERGREEN)
2183 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
2184 else
2185 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
2186 }
2187 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2188 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
2189 ctx.file_offset[TGSI_FILE_INPUT] = 2;
2190 }
2191 ctx.use_llvm = use_llvm;
2192
2193 if (use_llvm) {
2194 ctx.file_offset[TGSI_FILE_OUTPUT] =
2195 ctx.file_offset[TGSI_FILE_INPUT];
2196 } else {
2197 ctx.file_offset[TGSI_FILE_OUTPUT] =
2198 ctx.file_offset[TGSI_FILE_INPUT] +
2199 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2200 }
2201 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
2202 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
2203
2204 /* Outside the GPR range. This will be translated to one of the
2205 * kcache banks later. */
2206 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
2207
2208 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
2209 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
2210 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
2211 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
2212 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
2213
2214 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2215 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
2216 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
2217 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
2218 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
2219 ctx.temp_reg = ctx.bc->ar_reg + 7;
2220 } else {
2221 ctx.temp_reg = ctx.bc->ar_reg + 3;
2222 }
2223
2224 shader->max_arrays = 0;
2225 shader->num_arrays = 0;
2226 if (indirect_gprs) {
2227
2228 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
2229 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
2230 ctx.file_offset[TGSI_FILE_OUTPUT] -
2231 ctx.file_offset[TGSI_FILE_INPUT],
2232 0x0F);
2233 }
2234 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
2235 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
2236 ctx.file_offset[TGSI_FILE_TEMPORARY] -
2237 ctx.file_offset[TGSI_FILE_OUTPUT],
2238 0x0F);
2239 }
2240 }
2241
2242 ctx.nliterals = 0;
2243 ctx.literals = NULL;
2244
2245 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS];
2246 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2247 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
2248
2249 if (shader->vs_as_gs_a)
2250 vs_add_primid_output(&ctx, key.vs.prim_id_out);
2251
2252 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2253 tgsi_parse_token(&ctx.parse);
2254 switch (ctx.parse.FullToken.Token.Type) {
2255 case TGSI_TOKEN_TYPE_IMMEDIATE:
2256 immediate = &ctx.parse.FullToken.FullImmediate;
2257 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
2258 if(ctx.literals == NULL) {
2259 r = -ENOMEM;
2260 goto out_err;
2261 }
2262 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
2263 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
2264 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
2265 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
2266 ctx.nliterals++;
2267 break;
2268 case TGSI_TOKEN_TYPE_DECLARATION:
2269 r = tgsi_declaration(&ctx);
2270 if (r)
2271 goto out_err;
2272 break;
2273 case TGSI_TOKEN_TYPE_INSTRUCTION:
2274 case TGSI_TOKEN_TYPE_PROPERTY:
2275 break;
2276 default:
2277 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
2278 r = -EINVAL;
2279 goto out_err;
2280 }
2281 }
2282
2283 shader->ring_item_sizes[0] = ctx.next_ring_offset;
2284 shader->ring_item_sizes[1] = 0;
2285 shader->ring_item_sizes[2] = 0;
2286 shader->ring_item_sizes[3] = 0;
2287
2288 /* Process two side if needed */
2289 if (shader->two_side && ctx.colors_used) {
2290 int i, count = ctx.shader->ninput;
2291 unsigned next_lds_loc = ctx.shader->nlds;
2292
2293 /* additional inputs will be allocated right after the existing inputs,
2294 * we won't need them after the color selection, so we don't need to
2295 * reserve these gprs for the rest of the shader code and to adjust
2296 * output offsets etc. */
2297 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
2298 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2299
2300 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
2301 if (ctx.face_gpr == -1) {
2302 i = ctx.shader->ninput++;
2303 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
2304 ctx.shader->input[i].spi_sid = 0;
2305 ctx.shader->input[i].gpr = gpr++;
2306 ctx.face_gpr = ctx.shader->input[i].gpr;
2307 }
2308
2309 for (i = 0; i < count; i++) {
2310 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2311 int ni = ctx.shader->ninput++;
2312 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
2313 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
2314 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
2315 ctx.shader->input[ni].gpr = gpr++;
2316 // TGSI to LLVM needs to know the lds position of inputs.
2317 // Non LLVM path computes it later (in process_twoside_color)
2318 ctx.shader->input[ni].lds_pos = next_lds_loc++;
2319 ctx.shader->input[i].back_color_input = ni;
2320 if (ctx.bc->chip_class >= EVERGREEN) {
2321 if ((r = evergreen_interp_input(&ctx, ni)))
2322 return r;
2323 }
2324 }
2325 }
2326 }
2327
2328 /* LLVM backend setup */
2329 #ifdef R600_USE_LLVM
2330 if (use_llvm) {
2331 struct radeon_llvm_context radeon_llvm_ctx;
2332 LLVMModuleRef mod;
2333 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
2334 boolean use_kill = false;
2335
2336 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
2337 radeon_llvm_ctx.type = ctx.type;
2338 radeon_llvm_ctx.two_side = shader->two_side;
2339 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
2340 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
2341 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
2342 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
2343 radeon_llvm_ctx.color_buffer_count = max_color_exports;
2344 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
2345 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
2346 radeon_llvm_ctx.stream_outputs = &so;
2347 radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
2348 radeon_llvm_ctx.has_compressed_msaa_texturing =
2349 ctx.bc->has_compressed_msaa_texturing;
2350 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
2351 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
2352 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
2353
2354 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
2355 radeon_llvm_dispose(&radeon_llvm_ctx);
2356 use_llvm = 0;
2357 fprintf(stderr, "R600 LLVM backend failed to compile "
2358 "shader. Falling back to TGSI\n");
2359 } else {
2360 ctx.file_offset[TGSI_FILE_OUTPUT] =
2361 ctx.file_offset[TGSI_FILE_INPUT];
2362 }
2363 if (use_kill)
2364 ctx.shader->uses_kill = use_kill;
2365 radeon_llvm_dispose(&radeon_llvm_ctx);
2366 }
2367 #endif
2368 /* End of LLVM backend setup */
2369
2370 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
2371 shader->nr_ps_max_color_exports = 8;
2372
2373 if (!use_llvm) {
2374 if (ctx.fragcoord_input >= 0) {
2375 if (ctx.bc->chip_class == CAYMAN) {
2376 for (j = 0 ; j < 4; j++) {
2377 struct r600_bytecode_alu alu;
2378 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2379 alu.op = ALU_OP1_RECIP_IEEE;
2380 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2381 alu.src[0].chan = 3;
2382
2383 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2384 alu.dst.chan = j;
2385 alu.dst.write = (j == 3);
2386 alu.last = 1;
2387 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2388 return r;
2389 }
2390 } else {
2391 struct r600_bytecode_alu alu;
2392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2393 alu.op = ALU_OP1_RECIP_IEEE;
2394 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2395 alu.src[0].chan = 3;
2396
2397 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2398 alu.dst.chan = 3;
2399 alu.dst.write = 1;
2400 alu.last = 1;
2401 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2402 return r;
2403 }
2404 }
2405
2406 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2407 struct r600_bytecode_alu alu;
2408 int r;
2409
2410 /* GS thread with no output workaround - emit a cut at start of GS */
2411 if (ctx.bc->chip_class == R600)
2412 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
2413
2414 for (j = 0; j < 4; j++) {
2415 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2416 alu.op = ALU_OP1_MOV;
2417 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2418 alu.src[0].value = 0;
2419 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
2420 alu.dst.write = 1;
2421 alu.last = 1;
2422 r = r600_bytecode_add_alu(ctx.bc, &alu);
2423 if (r)
2424 return r;
2425 }
2426 }
2427 if (shader->two_side && ctx.colors_used) {
2428 if ((r = process_twoside_color_inputs(&ctx)))
2429 return r;
2430 }
2431
2432 tgsi_parse_init(&ctx.parse, tokens);
2433 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2434 tgsi_parse_token(&ctx.parse);
2435 switch (ctx.parse.FullToken.Token.Type) {
2436 case TGSI_TOKEN_TYPE_INSTRUCTION:
2437 r = tgsi_is_supported(&ctx);
2438 if (r)
2439 goto out_err;
2440 ctx.max_driver_temp_used = 0;
2441 /* reserve first tmp for everyone */
2442 r600_get_temp(&ctx);
2443
2444 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
2445 if ((r = tgsi_split_constant(&ctx)))
2446 goto out_err;
2447 if ((r = tgsi_split_literal_constant(&ctx)))
2448 goto out_err;
2449 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
2450 if ((r = tgsi_split_gs_inputs(&ctx)))
2451 goto out_err;
2452 if (ctx.bc->chip_class == CAYMAN)
2453 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
2454 else if (ctx.bc->chip_class >= EVERGREEN)
2455 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
2456 else
2457 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
2458 r = ctx.inst_info->process(&ctx);
2459 if (r)
2460 goto out_err;
2461 break;
2462 default:
2463 break;
2464 }
2465 }
2466 }
2467
2468 /* Reset the temporary register counter. */
2469 ctx.max_driver_temp_used = 0;
2470
2471 noutput = shader->noutput;
2472
2473 if (!ring_outputs && ctx.clip_vertex_write) {
2474 unsigned clipdist_temp[2];
2475
2476 clipdist_temp[0] = r600_get_temp(&ctx);
2477 clipdist_temp[1] = r600_get_temp(&ctx);
2478
2479 /* need to convert a clipvertex write into clipdistance writes and not export
2480 the clip vertex anymore */
2481
2482 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
2483 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2484 shader->output[noutput].gpr = clipdist_temp[0];
2485 noutput++;
2486 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2487 shader->output[noutput].gpr = clipdist_temp[1];
2488 noutput++;
2489
2490 /* reset spi_sid for clipvertex output to avoid confusing spi */
2491 shader->output[ctx.cv_output].spi_sid = 0;
2492
2493 shader->clip_dist_write = 0xFF;
2494
2495 for (i = 0; i < 8; i++) {
2496 int oreg = i >> 2;
2497 int ochan = i & 3;
2498
2499 for (j = 0; j < 4; j++) {
2500 struct r600_bytecode_alu alu;
2501 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2502 alu.op = ALU_OP2_DOT4;
2503 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
2504 alu.src[0].chan = j;
2505
2506 alu.src[1].sel = 512 + i;
2507 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
2508 alu.src[1].chan = j;
2509
2510 alu.dst.sel = clipdist_temp[oreg];
2511 alu.dst.chan = j;
2512 alu.dst.write = (j == ochan);
2513 if (j == 3)
2514 alu.last = 1;
2515 if (!use_llvm)
2516 r = r600_bytecode_add_alu(ctx.bc, &alu);
2517 if (r)
2518 return r;
2519 }
2520 }
2521 }
2522
2523 /* Add stream outputs. */
2524 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
2525 so.num_outputs && !use_llvm)
2526 emit_streamout(&ctx, &so, -1, NULL);
2527
2528 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2529 convert_edgeflag_to_int(&ctx);
2530
2531 if (ring_outputs) {
2532 if (shader->vs_as_es || shader->tes_as_es) {
2533 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
2534 ctx.gs_export_gpr_tregs[1] = -1;
2535 ctx.gs_export_gpr_tregs[2] = -1;
2536 ctx.gs_export_gpr_tregs[3] = -1;
2537
2538 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
2539 }
2540 } else {
2541 /* Export output */
2542 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
2543
2544 for (i = 0, j = 0; i < noutput; i++, j++) {
2545 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2546 output[j].gpr = shader->output[i].gpr;
2547 output[j].elem_size = 3;
2548 output[j].swizzle_x = 0;
2549 output[j].swizzle_y = 1;
2550 output[j].swizzle_z = 2;
2551 output[j].swizzle_w = 3;
2552 output[j].burst_count = 1;
2553 output[j].type = -1;
2554 output[j].op = CF_OP_EXPORT;
2555 switch (ctx.type) {
2556 case TGSI_PROCESSOR_VERTEX:
2557 switch (shader->output[i].name) {
2558 case TGSI_SEMANTIC_POSITION:
2559 output[j].array_base = 60;
2560 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2561 pos_emitted = true;
2562 break;
2563
2564 case TGSI_SEMANTIC_PSIZE:
2565 output[j].array_base = 61;
2566 output[j].swizzle_y = 7;
2567 output[j].swizzle_z = 7;
2568 output[j].swizzle_w = 7;
2569 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2570 pos_emitted = true;
2571 break;
2572 case TGSI_SEMANTIC_EDGEFLAG:
2573 output[j].array_base = 61;
2574 output[j].swizzle_x = 7;
2575 output[j].swizzle_y = 0;
2576 output[j].swizzle_z = 7;
2577 output[j].swizzle_w = 7;
2578 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2579 pos_emitted = true;
2580 break;
2581 case TGSI_SEMANTIC_LAYER:
2582 /* spi_sid is 0 for outputs that are
2583 * not consumed by PS */
2584 if (shader->output[i].spi_sid) {
2585 output[j].array_base = next_param_base++;
2586 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2587 j++;
2588 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2589 }
2590 output[j].array_base = 61;
2591 output[j].swizzle_x = 7;
2592 output[j].swizzle_y = 7;
2593 output[j].swizzle_z = 0;
2594 output[j].swizzle_w = 7;
2595 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2596 pos_emitted = true;
2597 break;
2598 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2599 /* spi_sid is 0 for outputs that are
2600 * not consumed by PS */
2601 if (shader->output[i].spi_sid) {
2602 output[j].array_base = next_param_base++;
2603 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2604 j++;
2605 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2606 }
2607 output[j].array_base = 61;
2608 output[j].swizzle_x = 7;
2609 output[j].swizzle_y = 7;
2610 output[j].swizzle_z = 7;
2611 output[j].swizzle_w = 0;
2612 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2613 pos_emitted = true;
2614 break;
2615 case TGSI_SEMANTIC_CLIPVERTEX:
2616 j--;
2617 break;
2618 case TGSI_SEMANTIC_CLIPDIST:
2619 output[j].array_base = next_clip_base++;
2620 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2621 pos_emitted = true;
2622 /* spi_sid is 0 for clipdistance outputs that were generated
2623 * for clipvertex - we don't need to pass them to PS */
2624 if (shader->output[i].spi_sid) {
2625 j++;
2626 /* duplicate it as PARAM to pass to the pixel shader */
2627 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2628 output[j].array_base = next_param_base++;
2629 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2630 }
2631 break;
2632 case TGSI_SEMANTIC_FOG:
2633 output[j].swizzle_y = 4; /* 0 */
2634 output[j].swizzle_z = 4; /* 0 */
2635 output[j].swizzle_w = 5; /* 1 */
2636 break;
2637 case TGSI_SEMANTIC_PRIMID:
2638 output[j].swizzle_x = 2;
2639 output[j].swizzle_y = 4; /* 0 */
2640 output[j].swizzle_z = 4; /* 0 */
2641 output[j].swizzle_w = 4; /* 0 */
2642 break;
2643 }
2644
2645 break;
2646 case TGSI_PROCESSOR_FRAGMENT:
2647 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
2648 /* never export more colors than the number of CBs */
2649 if (shader->output[i].sid >= max_color_exports) {
2650 /* skip export */
2651 j--;
2652 continue;
2653 }
2654 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2655 output[j].array_base = shader->output[i].sid;
2656 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2657 shader->nr_ps_color_exports++;
2658 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
2659 for (k = 1; k < max_color_exports; k++) {
2660 j++;
2661 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2662 output[j].gpr = shader->output[i].gpr;
2663 output[j].elem_size = 3;
2664 output[j].swizzle_x = 0;
2665 output[j].swizzle_y = 1;
2666 output[j].swizzle_z = 2;
2667 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2668 output[j].burst_count = 1;
2669 output[j].array_base = k;
2670 output[j].op = CF_OP_EXPORT;
2671 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2672 shader->nr_ps_color_exports++;
2673 }
2674 }
2675 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
2676 output[j].array_base = 61;
2677 output[j].swizzle_x = 2;
2678 output[j].swizzle_y = 7;
2679 output[j].swizzle_z = output[j].swizzle_w = 7;
2680 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2681 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2682 output[j].array_base = 61;
2683 output[j].swizzle_x = 7;
2684 output[j].swizzle_y = 1;
2685 output[j].swizzle_z = output[j].swizzle_w = 7;
2686 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2687 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2688 output[j].array_base = 61;
2689 output[j].swizzle_x = 7;
2690 output[j].swizzle_y = 7;
2691 output[j].swizzle_z = 0;
2692 output[j].swizzle_w = 7;
2693 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2694 } else {
2695 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
2696 r = -EINVAL;
2697 goto out_err;
2698 }
2699 break;
2700 default:
2701 R600_ERR("unsupported processor type %d\n", ctx.type);
2702 r = -EINVAL;
2703 goto out_err;
2704 }
2705
2706 if (output[j].type==-1) {
2707 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2708 output[j].array_base = next_param_base++;
2709 }
2710 }
2711
2712 /* add fake position export */
2713 if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
2714 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2715 output[j].gpr = 0;
2716 output[j].elem_size = 3;
2717 output[j].swizzle_x = 7;
2718 output[j].swizzle_y = 7;
2719 output[j].swizzle_z = 7;
2720 output[j].swizzle_w = 7;
2721 output[j].burst_count = 1;
2722 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2723 output[j].array_base = 60;
2724 output[j].op = CF_OP_EXPORT;
2725 j++;
2726 }
2727
2728 /* add fake param output for vertex shader if no param is exported */
2729 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
2730 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2731 output[j].gpr = 0;
2732 output[j].elem_size = 3;
2733 output[j].swizzle_x = 7;
2734 output[j].swizzle_y = 7;
2735 output[j].swizzle_z = 7;
2736 output[j].swizzle_w = 7;
2737 output[j].burst_count = 1;
2738 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2739 output[j].array_base = 0;
2740 output[j].op = CF_OP_EXPORT;
2741 j++;
2742 }
2743
2744 /* add fake pixel export */
2745 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
2746 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2747 output[j].gpr = 0;
2748 output[j].elem_size = 3;
2749 output[j].swizzle_x = 7;
2750 output[j].swizzle_y = 7;
2751 output[j].swizzle_z = 7;
2752 output[j].swizzle_w = 7;
2753 output[j].burst_count = 1;
2754 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2755 output[j].array_base = 0;
2756 output[j].op = CF_OP_EXPORT;
2757 j++;
2758 shader->nr_ps_color_exports++;
2759 }
2760
2761 noutput = j;
2762
2763 /* set export done on last export of each type */
2764 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
2765 if (!(output_done & (1 << output[i].type))) {
2766 output_done |= (1 << output[i].type);
2767 output[i].op = CF_OP_EXPORT_DONE;
2768 }
2769 }
2770 /* add output to bytecode */
2771 if (!use_llvm) {
2772 for (i = 0; i < noutput; i++) {
2773 r = r600_bytecode_add_output(ctx.bc, &output[i]);
2774 if (r)
2775 goto out_err;
2776 }
2777 }
2778 }
2779
2780 /* add program end */
2781 if (!use_llvm) {
2782 if (ctx.bc->chip_class == CAYMAN)
2783 cm_bytecode_add_cf_end(ctx.bc);
2784 else {
2785 const struct cf_op_info *last = NULL;
2786
2787 if (ctx.bc->cf_last)
2788 last = r600_isa_cf(ctx.bc->cf_last->op);
2789
2790 /* alu clause instructions don't have EOP bit, so add NOP */
2791 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
2792 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2793
2794 ctx.bc->cf_last->end_of_program = 1;
2795 }
2796 }
2797
2798 /* check GPR limit - we have 124 = 128 - 4
2799 * (4 are reserved as alu clause temporary registers) */
2800 if (ctx.bc->ngpr > 124) {
2801 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
2802 r = -ENOMEM;
2803 goto out_err;
2804 }
2805
2806 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2807 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
2808 return r;
2809 }
2810
2811 free(ctx.literals);
2812 tgsi_parse_free(&ctx.parse);
2813 return 0;
2814 out_err:
2815 free(ctx.literals);
2816 tgsi_parse_free(&ctx.parse);
2817 return r;
2818 }
2819
2820 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
2821 {
2822 const unsigned tgsi_opcode =
2823 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
2824 R600_ERR("%s tgsi opcode unsupported\n",
2825 tgsi_get_opcode_name(tgsi_opcode));
2826 return -EINVAL;
2827 }
2828
2829 static int tgsi_end(struct r600_shader_ctx *ctx)
2830 {
2831 return 0;
2832 }
2833
2834 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
2835 const struct r600_shader_src *shader_src,
2836 unsigned chan)
2837 {
2838 bc_src->sel = shader_src->sel;
2839 bc_src->chan = shader_src->swizzle[chan];
2840 bc_src->neg = shader_src->neg;
2841 bc_src->abs = shader_src->abs;
2842 bc_src->rel = shader_src->rel;
2843 bc_src->value = shader_src->value[bc_src->chan];
2844 bc_src->kc_bank = shader_src->kc_bank;
2845 bc_src->kc_rel = shader_src->kc_rel;
2846 }
2847
2848 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
2849 {
2850 bc_src->abs = 1;
2851 bc_src->neg = 0;
2852 }
2853
2854 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2855 {
2856 bc_src->neg = !bc_src->neg;
2857 }
2858
2859 static void tgsi_dst(struct r600_shader_ctx *ctx,
2860 const struct tgsi_full_dst_register *tgsi_dst,
2861 unsigned swizzle,
2862 struct r600_bytecode_alu_dst *r600_dst)
2863 {
2864 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2865
2866 r600_dst->sel = tgsi_dst->Register.Index;
2867 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2868 r600_dst->chan = swizzle;
2869 r600_dst->write = 1;
2870 if (tgsi_dst->Register.Indirect)
2871 r600_dst->rel = V_SQ_REL_RELATIVE;
2872 if (inst->Instruction.Saturate) {
2873 r600_dst->clamp = 1;
2874 }
2875 }
2876
2877 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
2878 {
2879 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2880 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2881 struct r600_bytecode_alu alu;
2882 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2883 int use_tmp = 0;
2884
2885 if (singledest) {
2886 switch (write_mask) {
2887 case 0x1:
2888 write_mask = 0x3;
2889 break;
2890 case 0x2:
2891 use_tmp = 1;
2892 write_mask = 0x3;
2893 break;
2894 case 0x4:
2895 write_mask = 0xc;
2896 break;
2897 case 0x8:
2898 write_mask = 0xc;
2899 use_tmp = 3;
2900 break;
2901 }
2902 }
2903
2904 lasti = tgsi_last_instruction(write_mask);
2905 for (i = 0; i <= lasti; i++) {
2906
2907 if (!(write_mask & (1 << i)))
2908 continue;
2909
2910 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2911
2912 if (singledest) {
2913 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2914 if (use_tmp) {
2915 alu.dst.sel = ctx->temp_reg;
2916 alu.dst.chan = i;
2917 alu.dst.write = 1;
2918 }
2919 if (i == 1 || i == 3)
2920 alu.dst.write = 0;
2921 } else
2922 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2923
2924 alu.op = ctx->inst_info->op;
2925 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
2926 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2927 } else if (!swap) {
2928 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2929 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
2930 }
2931 } else {
2932 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
2933 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
2934 }
2935
2936 /* handle some special cases */
2937 if (i == 1 || i == 3) {
2938 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
2939 case TGSI_OPCODE_SUB:
2940 r600_bytecode_src_toggle_neg(&alu.src[1]);
2941 break;
2942 case TGSI_OPCODE_DABS:
2943 r600_bytecode_src_set_abs(&alu.src[0]);
2944 break;
2945 default:
2946 break;
2947 }
2948 }
2949 if (i == lasti) {
2950 alu.last = 1;
2951 }
2952 r = r600_bytecode_add_alu(ctx->bc, &alu);
2953 if (r)
2954 return r;
2955 }
2956
2957 if (use_tmp) {
2958 write_mask = inst->Dst[0].Register.WriteMask;
2959
2960 /* move result from temp to dst */
2961 for (i = 0; i <= lasti; i++) {
2962 if (!(write_mask & (1 << i)))
2963 continue;
2964
2965 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2966 alu.op = ALU_OP1_MOV;
2967 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2968 alu.src[0].sel = ctx->temp_reg;
2969 alu.src[0].chan = use_tmp - 1;
2970 alu.last = (i == lasti);
2971
2972 r = r600_bytecode_add_alu(ctx->bc, &alu);
2973 if (r)
2974 return r;
2975 }
2976 }
2977 return 0;
2978 }
2979
2980 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
2981 {
2982 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2983 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2984 /* confirm writemasking */
2985 if ((write_mask & 0x3) != 0x3 &&
2986 (write_mask & 0xc) != 0xc) {
2987 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
2988 return -1;
2989 }
2990 return tgsi_op2_64_params(ctx, false, false);
2991 }
2992
2993 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
2994 {
2995 return tgsi_op2_64_params(ctx, true, false);
2996 }
2997
2998 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
2999 {
3000 return tgsi_op2_64_params(ctx, true, true);
3001 }
3002
3003 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3004 {
3005 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3006 struct r600_bytecode_alu alu;
3007 int i, j, r;
3008 int lasti = 3;
3009 int tmp = r600_get_temp(ctx);
3010
3011 for (i = 0; i < lasti + 1; i++) {
3012
3013 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3014 alu.op = ctx->inst_info->op;
3015 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3016 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3017 }
3018
3019 if (inst->Dst[0].Register.WriteMask & (1 << i))
3020 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3021 else
3022 alu.dst.sel = tmp;
3023
3024 alu.dst.chan = i;
3025 alu.is_op3 = 1;
3026 if (i == lasti) {
3027 alu.last = 1;
3028 }
3029 r = r600_bytecode_add_alu(ctx->bc, &alu);
3030 if (r)
3031 return r;
3032 }
3033 return 0;
3034 }
3035
3036 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3037 {
3038 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3039 struct r600_bytecode_alu alu;
3040 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3041 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3042 /* use temp register if trans_only and more than one dst component */
3043 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3044
3045 for (i = 0; i <= lasti; i++) {
3046 if (!(write_mask & (1 << i)))
3047 continue;
3048
3049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3050 if (use_tmp) {
3051 alu.dst.sel = ctx->temp_reg;
3052 alu.dst.chan = i;
3053 alu.dst.write = 1;
3054 } else
3055 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3056
3057 alu.op = ctx->inst_info->op;
3058 if (!swap) {
3059 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3060 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3061 }
3062 } else {
3063 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3064 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3065 }
3066 /* handle some special cases */
3067 switch (inst->Instruction.Opcode) {
3068 case TGSI_OPCODE_SUB:
3069 r600_bytecode_src_toggle_neg(&alu.src[1]);
3070 break;
3071 case TGSI_OPCODE_ABS:
3072 r600_bytecode_src_set_abs(&alu.src[0]);
3073 break;
3074 default:
3075 break;
3076 }
3077 if (i == lasti || trans_only) {
3078 alu.last = 1;
3079 }
3080 r = r600_bytecode_add_alu(ctx->bc, &alu);
3081 if (r)
3082 return r;
3083 }
3084
3085 if (use_tmp) {
3086 /* move result from temp to dst */
3087 for (i = 0; i <= lasti; i++) {
3088 if (!(write_mask & (1 << i)))
3089 continue;
3090
3091 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3092 alu.op = ALU_OP1_MOV;
3093 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3094 alu.src[0].sel = ctx->temp_reg;
3095 alu.src[0].chan = i;
3096 alu.last = (i == lasti);
3097
3098 r = r600_bytecode_add_alu(ctx->bc, &alu);
3099 if (r)
3100 return r;
3101 }
3102 }
3103 return 0;
3104 }
3105
3106 static int tgsi_op2(struct r600_shader_ctx *ctx)
3107 {
3108 return tgsi_op2_s(ctx, 0, 0);
3109 }
3110
3111 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
3112 {
3113 return tgsi_op2_s(ctx, 1, 0);
3114 }
3115
3116 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
3117 {
3118 return tgsi_op2_s(ctx, 0, 1);
3119 }
3120
3121 static int tgsi_ineg(struct r600_shader_ctx *ctx)
3122 {
3123 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3124 struct r600_bytecode_alu alu;
3125 int i, r;
3126 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3127
3128 for (i = 0; i < lasti + 1; i++) {
3129
3130 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3131 continue;
3132 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3133 alu.op = ctx->inst_info->op;
3134
3135 alu.src[0].sel = V_SQ_ALU_SRC_0;
3136
3137 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3138
3139 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3140
3141 if (i == lasti) {
3142 alu.last = 1;
3143 }
3144 r = r600_bytecode_add_alu(ctx->bc, &alu);
3145 if (r)
3146 return r;
3147 }
3148 return 0;
3149
3150 }
3151
3152 static int tgsi_dneg(struct r600_shader_ctx *ctx)
3153 {
3154 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3155 struct r600_bytecode_alu alu;
3156 int i, r;
3157 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3158
3159 for (i = 0; i < lasti + 1; i++) {
3160
3161 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3162 continue;
3163 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3164 alu.op = ALU_OP1_MOV;
3165
3166 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3167
3168 if (i == 1 || i == 3)
3169 r600_bytecode_src_toggle_neg(&alu.src[0]);
3170 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3171
3172 if (i == lasti) {
3173 alu.last = 1;
3174 }
3175 r = r600_bytecode_add_alu(ctx->bc, &alu);
3176 if (r)
3177 return r;
3178 }
3179 return 0;
3180
3181 }
3182
3183 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
3184 {
3185 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3186 struct r600_bytecode_alu alu;
3187 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3188 int i, j, r;
3189 int firsti = write_mask == 0xc ? 2 : 0;
3190
3191 for (i = 0; i <= 3; i++) {
3192 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3193 alu.op = ctx->inst_info->op;
3194
3195 alu.dst.sel = ctx->temp_reg;
3196 alu.dst.chan = i;
3197 alu.dst.write = 1;
3198 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3199 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3200 }
3201
3202 if (i == 3)
3203 alu.last = 1;
3204
3205 r = r600_bytecode_add_alu(ctx->bc, &alu);
3206 if (r)
3207 return r;
3208 }
3209
3210 /* MOV first two channels to writemask dst0 */
3211 for (i = 0; i <= 1; i++) {
3212 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3213 alu.op = ALU_OP1_MOV;
3214 alu.src[0].chan = i + 2;
3215 alu.src[0].sel = ctx->temp_reg;
3216
3217 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
3218 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
3219 alu.last = 1;
3220 r = r600_bytecode_add_alu(ctx->bc, &alu);
3221 if (r)
3222 return r;
3223 }
3224
3225 for (i = 0; i <= 3; i++) {
3226 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
3227 /* MOV third channels to writemask dst1 */
3228 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3229 alu.op = ALU_OP1_MOV;
3230 alu.src[0].chan = 1;
3231 alu.src[0].sel = ctx->temp_reg;
3232
3233 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
3234 alu.last = 1;
3235 r = r600_bytecode_add_alu(ctx->bc, &alu);
3236 if (r)
3237 return r;
3238 break;
3239 }
3240 }
3241 return 0;
3242 }
3243
3244
3245 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
3246 {
3247 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3248 struct r600_bytecode_alu alu;
3249 int i, r;
3250 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3251
3252 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
3253 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
3254
3255 for (i = 0; i <= (lasti+1)/2; i++) {
3256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3257 alu.op = ctx->inst_info->op;
3258
3259 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3260 alu.dst.sel = ctx->temp_reg;
3261 alu.dst.chan = i;
3262 alu.dst.write = 1;
3263 alu.last = 1;
3264
3265 r = r600_bytecode_add_alu(ctx->bc, &alu);
3266 if (r)
3267 return r;
3268 }
3269
3270 for (i = 0; i <= lasti; i++) {
3271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3272 alu.op = ALU_OP1_FLT32_TO_FLT64;
3273
3274 alu.src[0].chan = i/2;
3275 if (i%2 == 0)
3276 alu.src[0].sel = ctx->temp_reg;
3277 else {
3278 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3279 alu.src[0].value = 0x0;
3280 }
3281 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3282 alu.last = i == lasti;
3283
3284 r = r600_bytecode_add_alu(ctx->bc, &alu);
3285 if (r)
3286 return r;
3287 }
3288
3289 return 0;
3290 }
3291
3292 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
3293 {
3294 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3295 struct r600_bytecode_alu alu;
3296 int i, r;
3297 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3298
3299 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
3300 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
3301
3302 for (i = 0; i <= lasti; i++) {
3303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3304 alu.op = ALU_OP1_FLT64_TO_FLT32;
3305
3306 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
3307 alu.dst.chan = i;
3308 alu.dst.sel = ctx->temp_reg;
3309 alu.dst.write = i%2 == 0;
3310 alu.last = i == lasti;
3311
3312 r = r600_bytecode_add_alu(ctx->bc, &alu);
3313 if (r)
3314 return r;
3315 }
3316
3317 for (i = 0; i <= (lasti+1)/2; i++) {
3318 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3319 alu.op = ctx->inst_info->op;
3320
3321 alu.src[0].chan = i*2;
3322 alu.src[0].sel = ctx->temp_reg;
3323 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3324 alu.last = 1;
3325
3326 r = r600_bytecode_add_alu(ctx->bc, &alu);
3327 if (r)
3328 return r;
3329 }
3330
3331 return 0;
3332 }
3333
3334 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
3335 {
3336 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3337 int i, r;
3338 struct r600_bytecode_alu alu;
3339 int last_slot = 3;
3340 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3341 int t1 = ctx->temp_reg;
3342
3343 /* these have to write the result to X/Y by the looks of it */
3344 for (i = 0 ; i < last_slot; i++) {
3345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3346 alu.op = ctx->inst_info->op;
3347
3348 /* should only be one src regs */
3349 assert (inst->Instruction.NumSrcRegs == 1);
3350
3351 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3352 r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
3353
3354 /* RSQ should take the absolute value of src */
3355 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
3356 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT) {
3357 r600_bytecode_src_set_abs(&alu.src[1]);
3358 }
3359 alu.dst.sel = t1;
3360 alu.dst.chan = i;
3361 alu.dst.write = (i == 0 || i == 1);
3362
3363 if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
3364 alu.last = 1;
3365 r = r600_bytecode_add_alu(ctx->bc, &alu);
3366 if (r)
3367 return r;
3368 }
3369
3370 for (i = 0 ; i <= lasti; i++) {
3371 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3372 continue;
3373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3374 alu.op = ALU_OP1_MOV;
3375 alu.src[0].sel = t1;
3376 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
3377 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3378 alu.dst.write = 1;
3379 if (i == lasti)
3380 alu.last = 1;
3381 r = r600_bytecode_add_alu(ctx->bc, &alu);
3382 if (r)
3383 return r;
3384 }
3385 return 0;
3386 }
3387
3388 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
3389 {
3390 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3391 int i, j, r;
3392 struct r600_bytecode_alu alu;
3393 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3394
3395 for (i = 0 ; i < last_slot; i++) {
3396 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3397 alu.op = ctx->inst_info->op;
3398 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3399 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
3400
3401 /* RSQ should take the absolute value of src */
3402 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
3403 r600_bytecode_src_set_abs(&alu.src[j]);
3404 }
3405 }
3406 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3407 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3408
3409 if (i == last_slot - 1)
3410 alu.last = 1;
3411 r = r600_bytecode_add_alu(ctx->bc, &alu);
3412 if (r)
3413 return r;
3414 }
3415 return 0;
3416 }
3417
3418 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
3419 {
3420 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3421 int i, j, k, r;
3422 struct r600_bytecode_alu alu;
3423 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3424 int t1 = ctx->temp_reg;
3425
3426 for (k = 0; k <= lasti; k++) {
3427 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
3428 continue;
3429
3430 for (i = 0 ; i < 4; i++) {
3431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3432 alu.op = ctx->inst_info->op;
3433 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3434 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
3435 }
3436 alu.dst.sel = t1;
3437 alu.dst.chan = i;
3438 alu.dst.write = (i == k);
3439 if (i == 3)
3440 alu.last = 1;
3441 r = r600_bytecode_add_alu(ctx->bc, &alu);
3442 if (r)
3443 return r;
3444 }
3445 }
3446
3447 for (i = 0 ; i <= lasti; i++) {
3448 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3449 continue;
3450 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3451 alu.op = ALU_OP1_MOV;
3452 alu.src[0].sel = t1;
3453 alu.src[0].chan = i;
3454 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3455 alu.dst.write = 1;
3456 if (i == lasti)
3457 alu.last = 1;
3458 r = r600_bytecode_add_alu(ctx->bc, &alu);
3459 if (r)
3460 return r;
3461 }
3462
3463 return 0;
3464 }
3465
3466
3467 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
3468 {
3469 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3470 int i, j, k, r;
3471 struct r600_bytecode_alu alu;
3472 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3473 int t1 = ctx->temp_reg;
3474
3475 for (k = 0; k < 2; k++) {
3476 if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2))))
3477 continue;
3478
3479 for (i = 0; i < 4; i++) {
3480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3481 alu.op = ctx->inst_info->op;
3482 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3483 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));;
3484 }
3485 alu.dst.sel = t1;
3486 alu.dst.chan = i;
3487 alu.dst.write = 1;
3488 if (i == 3)
3489 alu.last = 1;
3490 r = r600_bytecode_add_alu(ctx->bc, &alu);
3491 if (r)
3492 return r;
3493 }
3494 }
3495
3496 for (i = 0; i <= lasti; i++) {
3497 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3498 continue;
3499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3500 alu.op = ALU_OP1_MOV;
3501 alu.src[0].sel = t1;
3502 alu.src[0].chan = i;
3503 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3504 alu.dst.write = 1;
3505 if (i == lasti)
3506 alu.last = 1;
3507 r = r600_bytecode_add_alu(ctx->bc, &alu);
3508 if (r)
3509 return r;
3510 }
3511
3512 return 0;
3513 }
3514
3515 /*
3516 * r600 - trunc to -PI..PI range
3517 * r700 - normalize by dividing by 2PI
3518 * see fdo bug 27901
3519 */
3520 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
3521 {
3522 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
3523 static float double_pi = 3.1415926535 * 2;
3524 static float neg_pi = -3.1415926535;
3525
3526 int r;
3527 struct r600_bytecode_alu alu;
3528
3529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3530 alu.op = ALU_OP3_MULADD;
3531 alu.is_op3 = 1;
3532
3533 alu.dst.chan = 0;
3534 alu.dst.sel = ctx->temp_reg;
3535 alu.dst.write = 1;
3536
3537 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3538
3539 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3540 alu.src[1].chan = 0;
3541 alu.src[1].value = *(uint32_t *)&half_inv_pi;
3542 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3543 alu.src[2].chan = 0;
3544 alu.last = 1;
3545 r = r600_bytecode_add_alu(ctx->bc, &alu);
3546 if (r)
3547 return r;
3548
3549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3550 alu.op = ALU_OP1_FRACT;
3551
3552 alu.dst.chan = 0;
3553 alu.dst.sel = ctx->temp_reg;
3554 alu.dst.write = 1;
3555
3556 alu.src[0].sel = ctx->temp_reg;
3557 alu.src[0].chan = 0;
3558 alu.last = 1;
3559 r = r600_bytecode_add_alu(ctx->bc, &alu);
3560 if (r)
3561 return r;
3562
3563 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3564 alu.op = ALU_OP3_MULADD;
3565 alu.is_op3 = 1;
3566
3567 alu.dst.chan = 0;
3568 alu.dst.sel = ctx->temp_reg;
3569 alu.dst.write = 1;
3570
3571 alu.src[0].sel = ctx->temp_reg;
3572 alu.src[0].chan = 0;
3573
3574 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3575 alu.src[1].chan = 0;
3576 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3577 alu.src[2].chan = 0;
3578
3579 if (ctx->bc->chip_class == R600) {
3580 alu.src[1].value = *(uint32_t *)&double_pi;
3581 alu.src[2].value = *(uint32_t *)&neg_pi;
3582 } else {
3583 alu.src[1].sel = V_SQ_ALU_SRC_1;
3584 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3585 alu.src[2].neg = 1;
3586 }
3587
3588 alu.last = 1;
3589 r = r600_bytecode_add_alu(ctx->bc, &alu);
3590 if (r)
3591 return r;
3592 return 0;
3593 }
3594
3595 static int cayman_trig(struct r600_shader_ctx *ctx)
3596 {
3597 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3598 struct r600_bytecode_alu alu;
3599 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3600 int i, r;
3601
3602 r = tgsi_setup_trig(ctx);
3603 if (r)
3604 return r;
3605
3606
3607 for (i = 0; i < last_slot; i++) {
3608 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3609 alu.op = ctx->inst_info->op;
3610 alu.dst.chan = i;
3611
3612 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3613 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3614
3615 alu.src[0].sel = ctx->temp_reg;
3616 alu.src[0].chan = 0;
3617 if (i == last_slot - 1)
3618 alu.last = 1;
3619 r = r600_bytecode_add_alu(ctx->bc, &alu);
3620 if (r)
3621 return r;
3622 }
3623 return 0;
3624 }
3625
3626 static int tgsi_trig(struct r600_shader_ctx *ctx)
3627 {
3628 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3629 struct r600_bytecode_alu alu;
3630 int i, r;
3631 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3632
3633 r = tgsi_setup_trig(ctx);
3634 if (r)
3635 return r;
3636
3637 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3638 alu.op = ctx->inst_info->op;
3639 alu.dst.chan = 0;
3640 alu.dst.sel = ctx->temp_reg;
3641 alu.dst.write = 1;
3642
3643 alu.src[0].sel = ctx->temp_reg;
3644 alu.src[0].chan = 0;
3645 alu.last = 1;
3646 r = r600_bytecode_add_alu(ctx->bc, &alu);
3647 if (r)
3648 return r;
3649
3650 /* replicate result */
3651 for (i = 0; i < lasti + 1; i++) {
3652 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3653 continue;
3654
3655 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3656 alu.op = ALU_OP1_MOV;
3657
3658 alu.src[0].sel = ctx->temp_reg;
3659 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3660 if (i == lasti)
3661 alu.last = 1;
3662 r = r600_bytecode_add_alu(ctx->bc, &alu);
3663 if (r)
3664 return r;
3665 }
3666 return 0;
3667 }
3668
3669 static int tgsi_scs(struct r600_shader_ctx *ctx)
3670 {
3671 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3672 struct r600_bytecode_alu alu;
3673 int i, r;
3674
3675 /* We'll only need the trig stuff if we are going to write to the
3676 * X or Y components of the destination vector.
3677 */
3678 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
3679 r = tgsi_setup_trig(ctx);
3680 if (r)
3681 return r;
3682 }
3683
3684 /* dst.x = COS */
3685 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3686 if (ctx->bc->chip_class == CAYMAN) {
3687 for (i = 0 ; i < 3; i++) {
3688 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3689 alu.op = ALU_OP1_COS;
3690 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3691
3692 if (i == 0)
3693 alu.dst.write = 1;
3694 else
3695 alu.dst.write = 0;
3696 alu.src[0].sel = ctx->temp_reg;
3697 alu.src[0].chan = 0;
3698 if (i == 2)
3699 alu.last = 1;
3700 r = r600_bytecode_add_alu(ctx->bc, &alu);
3701 if (r)
3702 return r;
3703 }
3704 } else {
3705 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3706 alu.op = ALU_OP1_COS;
3707 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3708
3709 alu.src[0].sel = ctx->temp_reg;
3710 alu.src[0].chan = 0;
3711 alu.last = 1;
3712 r = r600_bytecode_add_alu(ctx->bc, &alu);
3713 if (r)
3714 return r;
3715 }
3716 }
3717
3718 /* dst.y = SIN */
3719 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3720 if (ctx->bc->chip_class == CAYMAN) {
3721 for (i = 0 ; i < 3; i++) {
3722 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3723 alu.op = ALU_OP1_SIN;
3724 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3725 if (i == 1)
3726 alu.dst.write = 1;
3727 else
3728 alu.dst.write = 0;
3729 alu.src[0].sel = ctx->temp_reg;
3730 alu.src[0].chan = 0;
3731 if (i == 2)
3732 alu.last = 1;
3733 r = r600_bytecode_add_alu(ctx->bc, &alu);
3734 if (r)
3735 return r;
3736 }
3737 } else {
3738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3739 alu.op = ALU_OP1_SIN;
3740 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3741
3742 alu.src[0].sel = ctx->temp_reg;
3743 alu.src[0].chan = 0;
3744 alu.last = 1;
3745 r = r600_bytecode_add_alu(ctx->bc, &alu);
3746 if (r)
3747 return r;
3748 }
3749 }
3750
3751 /* dst.z = 0.0; */
3752 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3754
3755 alu.op = ALU_OP1_MOV;
3756
3757 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3758
3759 alu.src[0].sel = V_SQ_ALU_SRC_0;
3760 alu.src[0].chan = 0;
3761
3762 alu.last = 1;
3763
3764 r = r600_bytecode_add_alu(ctx->bc, &alu);
3765 if (r)
3766 return r;
3767 }
3768
3769 /* dst.w = 1.0; */
3770 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3771 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3772
3773 alu.op = ALU_OP1_MOV;
3774
3775 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3776
3777 alu.src[0].sel = V_SQ_ALU_SRC_1;
3778 alu.src[0].chan = 0;
3779
3780 alu.last = 1;
3781
3782 r = r600_bytecode_add_alu(ctx->bc, &alu);
3783 if (r)
3784 return r;
3785 }
3786
3787 return 0;
3788 }
3789
3790 static int tgsi_kill(struct r600_shader_ctx *ctx)
3791 {
3792 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3793 struct r600_bytecode_alu alu;
3794 int i, r;
3795
3796 for (i = 0; i < 4; i++) {
3797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3798 alu.op = ctx->inst_info->op;
3799
3800 alu.dst.chan = i;
3801
3802 alu.src[0].sel = V_SQ_ALU_SRC_0;
3803
3804 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
3805 alu.src[1].sel = V_SQ_ALU_SRC_1;
3806 alu.src[1].neg = 1;
3807 } else {
3808 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3809 }
3810 if (i == 3) {
3811 alu.last = 1;
3812 }
3813 r = r600_bytecode_add_alu(ctx->bc, &alu);
3814 if (r)
3815 return r;
3816 }
3817
3818 /* kill must be last in ALU */
3819 ctx->bc->force_add_cf = 1;
3820 ctx->shader->uses_kill = TRUE;
3821 return 0;
3822 }
3823
3824 static int tgsi_lit(struct r600_shader_ctx *ctx)
3825 {
3826 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3827 struct r600_bytecode_alu alu;
3828 int r;
3829
3830 /* tmp.x = max(src.y, 0.0) */
3831 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3832 alu.op = ALU_OP2_MAX;
3833 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3834 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3835 alu.src[1].chan = 1;
3836
3837 alu.dst.sel = ctx->temp_reg;
3838 alu.dst.chan = 0;
3839 alu.dst.write = 1;
3840
3841 alu.last = 1;
3842 r = r600_bytecode_add_alu(ctx->bc, &alu);
3843 if (r)
3844 return r;
3845
3846 if (inst->Dst[0].Register.WriteMask & (1 << 2))
3847 {
3848 int chan;
3849 int sel;
3850 int i;
3851
3852 if (ctx->bc->chip_class == CAYMAN) {
3853 for (i = 0; i < 3; i++) {
3854 /* tmp.z = log(tmp.x) */
3855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3856 alu.op = ALU_OP1_LOG_CLAMPED;
3857 alu.src[0].sel = ctx->temp_reg;
3858 alu.src[0].chan = 0;
3859 alu.dst.sel = ctx->temp_reg;
3860 alu.dst.chan = i;
3861 if (i == 2) {
3862 alu.dst.write = 1;
3863 alu.last = 1;
3864 } else
3865 alu.dst.write = 0;
3866
3867 r = r600_bytecode_add_alu(ctx->bc, &alu);
3868 if (r)
3869 return r;
3870 }
3871 } else {
3872 /* tmp.z = log(tmp.x) */
3873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3874 alu.op = ALU_OP1_LOG_CLAMPED;
3875 alu.src[0].sel = ctx->temp_reg;
3876 alu.src[0].chan = 0;
3877 alu.dst.sel = ctx->temp_reg;
3878 alu.dst.chan = 2;
3879 alu.dst.write = 1;
3880 alu.last = 1;
3881 r = r600_bytecode_add_alu(ctx->bc, &alu);
3882 if (r)
3883 return r;
3884 }
3885
3886 chan = alu.dst.chan;
3887 sel = alu.dst.sel;
3888
3889 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
3890 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3891 alu.op = ALU_OP3_MUL_LIT;
3892 alu.src[0].sel = sel;
3893 alu.src[0].chan = chan;
3894 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
3895 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
3896 alu.dst.sel = ctx->temp_reg;
3897 alu.dst.chan = 0;
3898 alu.dst.write = 1;
3899 alu.is_op3 = 1;
3900 alu.last = 1;
3901 r = r600_bytecode_add_alu(ctx->bc, &alu);
3902 if (r)
3903 return r;
3904
3905 if (ctx->bc->chip_class == CAYMAN) {
3906 for (i = 0; i < 3; i++) {
3907 /* dst.z = exp(tmp.x) */
3908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3909 alu.op = ALU_OP1_EXP_IEEE;
3910 alu.src[0].sel = ctx->temp_reg;
3911 alu.src[0].chan = 0;
3912 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3913 if (i == 2) {
3914 alu.dst.write = 1;
3915 alu.last = 1;
3916 } else
3917 alu.dst.write = 0;
3918 r = r600_bytecode_add_alu(ctx->bc, &alu);
3919 if (r)
3920 return r;
3921 }
3922 } else {
3923 /* dst.z = exp(tmp.x) */
3924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3925 alu.op = ALU_OP1_EXP_IEEE;
3926 alu.src[0].sel = ctx->temp_reg;
3927 alu.src[0].chan = 0;
3928 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3929 alu.last = 1;
3930 r = r600_bytecode_add_alu(ctx->bc, &alu);
3931 if (r)
3932 return r;
3933 }
3934 }
3935
3936 /* dst.x, <- 1.0 */
3937 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3938 alu.op = ALU_OP1_MOV;
3939 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
3940 alu.src[0].chan = 0;
3941 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3942 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
3943 r = r600_bytecode_add_alu(ctx->bc, &alu);
3944 if (r)
3945 return r;
3946
3947 /* dst.y = max(src.x, 0.0) */
3948 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3949 alu.op = ALU_OP2_MAX;
3950 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3951 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3952 alu.src[1].chan = 0;
3953 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3954 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
3955 r = r600_bytecode_add_alu(ctx->bc, &alu);
3956 if (r)
3957 return r;
3958
3959 /* dst.w, <- 1.0 */
3960 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3961 alu.op = ALU_OP1_MOV;
3962 alu.src[0].sel = V_SQ_ALU_SRC_1;
3963 alu.src[0].chan = 0;
3964 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3965 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
3966 alu.last = 1;
3967 r = r600_bytecode_add_alu(ctx->bc, &alu);
3968 if (r)
3969 return r;
3970
3971 return 0;
3972 }
3973
3974 static int tgsi_rsq(struct r600_shader_ctx *ctx)
3975 {
3976 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3977 struct r600_bytecode_alu alu;
3978 int i, r;
3979
3980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3981
3982 /* XXX:
3983 * For state trackers other than OpenGL, we'll want to use
3984 * _RECIPSQRT_IEEE instead.
3985 */
3986 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
3987
3988 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3989 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3990 r600_bytecode_src_set_abs(&alu.src[i]);
3991 }
3992 alu.dst.sel = ctx->temp_reg;
3993 alu.dst.write = 1;
3994 alu.last = 1;
3995 r = r600_bytecode_add_alu(ctx->bc, &alu);
3996 if (r)
3997 return r;
3998 /* replicate result */
3999 return tgsi_helper_tempx_replicate(ctx);
4000 }
4001
4002 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4003 {
4004 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4005 struct r600_bytecode_alu alu;
4006 int i, r;
4007
4008 for (i = 0; i < 4; i++) {
4009 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4010 alu.src[0].sel = ctx->temp_reg;
4011 alu.op = ALU_OP1_MOV;
4012 alu.dst.chan = i;
4013 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4014 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4015 if (i == 3)
4016 alu.last = 1;
4017 r = r600_bytecode_add_alu(ctx->bc, &alu);
4018 if (r)
4019 return r;
4020 }
4021 return 0;
4022 }
4023
4024 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4025 {
4026 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4027 struct r600_bytecode_alu alu;
4028 int i, r;
4029
4030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4031 alu.op = ctx->inst_info->op;
4032 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4033 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4034 }
4035 alu.dst.sel = ctx->temp_reg;
4036 alu.dst.write = 1;
4037 alu.last = 1;
4038 r = r600_bytecode_add_alu(ctx->bc, &alu);
4039 if (r)
4040 return r;
4041 /* replicate result */
4042 return tgsi_helper_tempx_replicate(ctx);
4043 }
4044
4045 static int cayman_pow(struct r600_shader_ctx *ctx)
4046 {
4047 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4048 int i, r;
4049 struct r600_bytecode_alu alu;
4050 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4051
4052 for (i = 0; i < 3; i++) {
4053 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4054 alu.op = ALU_OP1_LOG_IEEE;
4055 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4056 alu.dst.sel = ctx->temp_reg;
4057 alu.dst.chan = i;
4058 alu.dst.write = 1;
4059 if (i == 2)
4060 alu.last = 1;
4061 r = r600_bytecode_add_alu(ctx->bc, &alu);
4062 if (r)
4063 return r;
4064 }
4065
4066 /* b * LOG2(a) */
4067 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4068 alu.op = ALU_OP2_MUL;
4069 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4070 alu.src[1].sel = ctx->temp_reg;
4071 alu.dst.sel = ctx->temp_reg;
4072 alu.dst.write = 1;
4073 alu.last = 1;
4074 r = r600_bytecode_add_alu(ctx->bc, &alu);
4075 if (r)
4076 return r;
4077
4078 for (i = 0; i < last_slot; i++) {
4079 /* POW(a,b) = EXP2(b * LOG2(a))*/
4080 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4081 alu.op = ALU_OP1_EXP_IEEE;
4082 alu.src[0].sel = ctx->temp_reg;
4083
4084 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4085 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4086 if (i == last_slot - 1)
4087 alu.last = 1;
4088 r = r600_bytecode_add_alu(ctx->bc, &alu);
4089 if (r)
4090 return r;
4091 }
4092 return 0;
4093 }
4094
4095 static int tgsi_pow(struct r600_shader_ctx *ctx)
4096 {
4097 struct r600_bytecode_alu alu;
4098 int r;
4099
4100 /* LOG2(a) */
4101 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4102 alu.op = ALU_OP1_LOG_IEEE;
4103 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4104 alu.dst.sel = ctx->temp_reg;
4105 alu.dst.write = 1;
4106 alu.last = 1;
4107 r = r600_bytecode_add_alu(ctx->bc, &alu);
4108 if (r)
4109 return r;
4110 /* b * LOG2(a) */
4111 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4112 alu.op = ALU_OP2_MUL;
4113 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4114 alu.src[1].sel = ctx->temp_reg;
4115 alu.dst.sel = ctx->temp_reg;
4116 alu.dst.write = 1;
4117 alu.last = 1;
4118 r = r600_bytecode_add_alu(ctx->bc, &alu);
4119 if (r)
4120 return r;
4121 /* POW(a,b) = EXP2(b * LOG2(a))*/
4122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4123 alu.op = ALU_OP1_EXP_IEEE;
4124 alu.src[0].sel = ctx->temp_reg;
4125 alu.dst.sel = ctx->temp_reg;
4126 alu.dst.write = 1;
4127 alu.last = 1;
4128 r = r600_bytecode_add_alu(ctx->bc, &alu);
4129 if (r)
4130 return r;
4131 return tgsi_helper_tempx_replicate(ctx);
4132 }
4133
4134 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
4135 {
4136 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4137 struct r600_bytecode_alu alu;
4138 int i, r, j;
4139 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4140 int tmp0 = ctx->temp_reg;
4141 int tmp1 = r600_get_temp(ctx);
4142 int tmp2 = r600_get_temp(ctx);
4143 int tmp3 = r600_get_temp(ctx);
4144 /* Unsigned path:
4145 *
4146 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
4147 *
4148 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
4149 * 2. tmp0.z = lo (tmp0.x * src2)
4150 * 3. tmp0.w = -tmp0.z
4151 * 4. tmp0.y = hi (tmp0.x * src2)
4152 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
4153 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
4154 * 7. tmp1.x = tmp0.x - tmp0.w
4155 * 8. tmp1.y = tmp0.x + tmp0.w
4156 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
4157 * 10. tmp0.z = hi(tmp0.x * src1) = q
4158 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
4159 *
4160 * 12. tmp0.w = src1 - tmp0.y = r
4161 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
4162 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
4163 *
4164 * if DIV
4165 *
4166 * 15. tmp1.z = tmp0.z + 1 = q + 1
4167 * 16. tmp1.w = tmp0.z - 1 = q - 1
4168 *
4169 * else MOD
4170 *
4171 * 15. tmp1.z = tmp0.w - src2 = r - src2
4172 * 16. tmp1.w = tmp0.w + src2 = r + src2
4173 *
4174 * endif
4175 *
4176 * 17. tmp1.x = tmp1.x & tmp1.y
4177 *
4178 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
4179 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
4180 *
4181 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
4182 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
4183 *
4184 * Signed path:
4185 *
4186 * Same as unsigned, using abs values of the operands,
4187 * and fixing the sign of the result in the end.
4188 */
4189
4190 for (i = 0; i < 4; i++) {
4191 if (!(write_mask & (1<<i)))
4192 continue;
4193
4194 if (signed_op) {
4195
4196 /* tmp2.x = -src0 */
4197 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4198 alu.op = ALU_OP2_SUB_INT;
4199
4200 alu.dst.sel = tmp2;
4201 alu.dst.chan = 0;
4202 alu.dst.write = 1;
4203
4204 alu.src[0].sel = V_SQ_ALU_SRC_0;
4205
4206 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4207
4208 alu.last = 1;
4209 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4210 return r;
4211
4212 /* tmp2.y = -src1 */
4213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4214 alu.op = ALU_OP2_SUB_INT;
4215
4216 alu.dst.sel = tmp2;
4217 alu.dst.chan = 1;
4218 alu.dst.write = 1;
4219
4220 alu.src[0].sel = V_SQ_ALU_SRC_0;
4221
4222 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4223
4224 alu.last = 1;
4225 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4226 return r;
4227
4228 /* tmp2.z sign bit is set if src0 and src2 signs are different */
4229 /* it will be a sign of the quotient */
4230 if (!mod) {
4231
4232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4233 alu.op = ALU_OP2_XOR_INT;
4234
4235 alu.dst.sel = tmp2;
4236 alu.dst.chan = 2;
4237 alu.dst.write = 1;
4238
4239 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4240 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4241
4242 alu.last = 1;
4243 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4244 return r;
4245 }
4246
4247 /* tmp2.x = |src0| */
4248 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4249 alu.op = ALU_OP3_CNDGE_INT;
4250 alu.is_op3 = 1;
4251
4252 alu.dst.sel = tmp2;
4253 alu.dst.chan = 0;
4254 alu.dst.write = 1;
4255
4256 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4257 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4258 alu.src[2].sel = tmp2;
4259 alu.src[2].chan = 0;
4260
4261 alu.last = 1;
4262 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4263 return r;
4264
4265 /* tmp2.y = |src1| */
4266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4267 alu.op = ALU_OP3_CNDGE_INT;
4268 alu.is_op3 = 1;
4269
4270 alu.dst.sel = tmp2;
4271 alu.dst.chan = 1;
4272 alu.dst.write = 1;
4273
4274 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4275 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4276 alu.src[2].sel = tmp2;
4277 alu.src[2].chan = 1;
4278
4279 alu.last = 1;
4280 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4281 return r;
4282
4283 }
4284
4285 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
4286 if (ctx->bc->chip_class == CAYMAN) {
4287 /* tmp3.x = u2f(src2) */
4288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4289 alu.op = ALU_OP1_UINT_TO_FLT;
4290
4291 alu.dst.sel = tmp3;
4292 alu.dst.chan = 0;
4293 alu.dst.write = 1;
4294
4295 if (signed_op) {
4296 alu.src[0].sel = tmp2;
4297 alu.src[0].chan = 1;
4298 } else {
4299 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4300 }
4301
4302 alu.last = 1;
4303 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4304 return r;
4305
4306 /* tmp0.x = recip(tmp3.x) */
4307 for (j = 0 ; j < 3; j++) {
4308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4309 alu.op = ALU_OP1_RECIP_IEEE;
4310
4311 alu.dst.sel = tmp0;
4312 alu.dst.chan = j;
4313 alu.dst.write = (j == 0);
4314
4315 alu.src[0].sel = tmp3;
4316 alu.src[0].chan = 0;
4317
4318 if (j == 2)
4319 alu.last = 1;
4320 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4321 return r;
4322 }
4323
4324 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4325 alu.op = ALU_OP2_MUL;
4326
4327 alu.src[0].sel = tmp0;
4328 alu.src[0].chan = 0;
4329
4330 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4331 alu.src[1].value = 0x4f800000;
4332
4333 alu.dst.sel = tmp3;
4334 alu.dst.write = 1;
4335 alu.last = 1;
4336 r = r600_bytecode_add_alu(ctx->bc, &alu);
4337 if (r)
4338 return r;
4339
4340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4341 alu.op = ALU_OP1_FLT_TO_UINT;
4342
4343 alu.dst.sel = tmp0;
4344 alu.dst.chan = 0;
4345 alu.dst.write = 1;
4346
4347 alu.src[0].sel = tmp3;
4348 alu.src[0].chan = 0;
4349
4350 alu.last = 1;
4351 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4352 return r;
4353
4354 } else {
4355 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4356 alu.op = ALU_OP1_RECIP_UINT;
4357
4358 alu.dst.sel = tmp0;
4359 alu.dst.chan = 0;
4360 alu.dst.write = 1;
4361
4362 if (signed_op) {
4363 alu.src[0].sel = tmp2;
4364 alu.src[0].chan = 1;
4365 } else {
4366 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4367 }
4368
4369 alu.last = 1;
4370 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4371 return r;
4372 }
4373
4374 /* 2. tmp0.z = lo (tmp0.x * src2) */
4375 if (ctx->bc->chip_class == CAYMAN) {
4376 for (j = 0 ; j < 4; j++) {
4377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4378 alu.op = ALU_OP2_MULLO_UINT;
4379
4380 alu.dst.sel = tmp0;
4381 alu.dst.chan = j;
4382 alu.dst.write = (j == 2);
4383
4384 alu.src[0].sel = tmp0;
4385 alu.src[0].chan = 0;
4386 if (signed_op) {
4387 alu.src[1].sel = tmp2;
4388 alu.src[1].chan = 1;
4389 } else {
4390 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4391 }
4392
4393 alu.last = (j == 3);
4394 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4395 return r;
4396 }
4397 } else {
4398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4399 alu.op = ALU_OP2_MULLO_UINT;
4400
4401 alu.dst.sel = tmp0;
4402 alu.dst.chan = 2;
4403 alu.dst.write = 1;
4404
4405 alu.src[0].sel = tmp0;
4406 alu.src[0].chan = 0;
4407 if (signed_op) {
4408 alu.src[1].sel = tmp2;
4409 alu.src[1].chan = 1;
4410 } else {
4411 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4412 }
4413
4414 alu.last = 1;
4415 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4416 return r;
4417 }
4418
4419 /* 3. tmp0.w = -tmp0.z */
4420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4421 alu.op = ALU_OP2_SUB_INT;
4422
4423 alu.dst.sel = tmp0;
4424 alu.dst.chan = 3;
4425 alu.dst.write = 1;
4426
4427 alu.src[0].sel = V_SQ_ALU_SRC_0;
4428 alu.src[1].sel = tmp0;
4429 alu.src[1].chan = 2;
4430
4431 alu.last = 1;
4432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4433 return r;
4434
4435 /* 4. tmp0.y = hi (tmp0.x * src2) */
4436 if (ctx->bc->chip_class == CAYMAN) {
4437 for (j = 0 ; j < 4; j++) {
4438 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4439 alu.op = ALU_OP2_MULHI_UINT;
4440
4441 alu.dst.sel = tmp0;
4442 alu.dst.chan = j;
4443 alu.dst.write = (j == 1);
4444
4445 alu.src[0].sel = tmp0;
4446 alu.src[0].chan = 0;
4447
4448 if (signed_op) {
4449 alu.src[1].sel = tmp2;
4450 alu.src[1].chan = 1;
4451 } else {
4452 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4453 }
4454 alu.last = (j == 3);
4455 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4456 return r;
4457 }
4458 } else {
4459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4460 alu.op = ALU_OP2_MULHI_UINT;
4461
4462 alu.dst.sel = tmp0;
4463 alu.dst.chan = 1;
4464 alu.dst.write = 1;
4465
4466 alu.src[0].sel = tmp0;
4467 alu.src[0].chan = 0;
4468
4469 if (signed_op) {
4470 alu.src[1].sel = tmp2;
4471 alu.src[1].chan = 1;
4472 } else {
4473 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4474 }
4475
4476 alu.last = 1;
4477 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4478 return r;
4479 }
4480
4481 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
4482 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4483 alu.op = ALU_OP3_CNDE_INT;
4484 alu.is_op3 = 1;
4485
4486 alu.dst.sel = tmp0;
4487 alu.dst.chan = 2;
4488 alu.dst.write = 1;
4489
4490 alu.src[0].sel = tmp0;
4491 alu.src[0].chan = 1;
4492 alu.src[1].sel = tmp0;
4493 alu.src[1].chan = 3;
4494 alu.src[2].sel = tmp0;
4495 alu.src[2].chan = 2;
4496
4497 alu.last = 1;
4498 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4499 return r;
4500
4501 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
4502 if (ctx->bc->chip_class == CAYMAN) {
4503 for (j = 0 ; j < 4; j++) {
4504 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4505 alu.op = ALU_OP2_MULHI_UINT;
4506
4507 alu.dst.sel = tmp0;
4508 alu.dst.chan = j;
4509 alu.dst.write = (j == 3);
4510
4511 alu.src[0].sel = tmp0;
4512 alu.src[0].chan = 2;
4513
4514 alu.src[1].sel = tmp0;
4515 alu.src[1].chan = 0;
4516
4517 alu.last = (j == 3);
4518 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4519 return r;
4520 }
4521 } else {
4522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4523 alu.op = ALU_OP2_MULHI_UINT;
4524
4525 alu.dst.sel = tmp0;
4526 alu.dst.chan = 3;
4527 alu.dst.write = 1;
4528
4529 alu.src[0].sel = tmp0;
4530 alu.src[0].chan = 2;
4531
4532 alu.src[1].sel = tmp0;
4533 alu.src[1].chan = 0;
4534
4535 alu.last = 1;
4536 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4537 return r;
4538 }
4539
4540 /* 7. tmp1.x = tmp0.x - tmp0.w */
4541 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4542 alu.op = ALU_OP2_SUB_INT;
4543
4544 alu.dst.sel = tmp1;
4545 alu.dst.chan = 0;
4546 alu.dst.write = 1;
4547
4548 alu.src[0].sel = tmp0;
4549 alu.src[0].chan = 0;
4550 alu.src[1].sel = tmp0;
4551 alu.src[1].chan = 3;
4552
4553 alu.last = 1;
4554 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4555 return r;
4556
4557 /* 8. tmp1.y = tmp0.x + tmp0.w */
4558 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4559 alu.op = ALU_OP2_ADD_INT;
4560
4561 alu.dst.sel = tmp1;
4562 alu.dst.chan = 1;
4563 alu.dst.write = 1;
4564
4565 alu.src[0].sel = tmp0;
4566 alu.src[0].chan = 0;
4567 alu.src[1].sel = tmp0;
4568 alu.src[1].chan = 3;
4569
4570 alu.last = 1;
4571 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4572 return r;
4573
4574 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
4575 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4576 alu.op = ALU_OP3_CNDE_INT;
4577 alu.is_op3 = 1;
4578
4579 alu.dst.sel = tmp0;
4580 alu.dst.chan = 0;
4581 alu.dst.write = 1;
4582
4583 alu.src[0].sel = tmp0;
4584 alu.src[0].chan = 1;
4585 alu.src[1].sel = tmp1;
4586 alu.src[1].chan = 1;
4587 alu.src[2].sel = tmp1;
4588 alu.src[2].chan = 0;
4589
4590 alu.last = 1;
4591 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4592 return r;
4593
4594 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
4595 if (ctx->bc->chip_class == CAYMAN) {
4596 for (j = 0 ; j < 4; j++) {
4597 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4598 alu.op = ALU_OP2_MULHI_UINT;
4599
4600 alu.dst.sel = tmp0;
4601 alu.dst.chan = j;
4602 alu.dst.write = (j == 2);
4603
4604 alu.src[0].sel = tmp0;
4605 alu.src[0].chan = 0;
4606
4607 if (signed_op) {
4608 alu.src[1].sel = tmp2;
4609 alu.src[1].chan = 0;
4610 } else {
4611 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4612 }
4613
4614 alu.last = (j == 3);
4615 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4616 return r;
4617 }
4618 } else {
4619 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4620 alu.op = ALU_OP2_MULHI_UINT;
4621
4622 alu.dst.sel = tmp0;
4623 alu.dst.chan = 2;
4624 alu.dst.write = 1;
4625
4626 alu.src[0].sel = tmp0;
4627 alu.src[0].chan = 0;
4628
4629 if (signed_op) {
4630 alu.src[1].sel = tmp2;
4631 alu.src[1].chan = 0;
4632 } else {
4633 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4634 }
4635
4636 alu.last = 1;
4637 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4638 return r;
4639 }
4640
4641 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
4642 if (ctx->bc->chip_class == CAYMAN) {
4643 for (j = 0 ; j < 4; j++) {
4644 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4645 alu.op = ALU_OP2_MULLO_UINT;
4646
4647 alu.dst.sel = tmp0;
4648 alu.dst.chan = j;
4649 alu.dst.write = (j == 1);
4650
4651 if (signed_op) {
4652 alu.src[0].sel = tmp2;
4653 alu.src[0].chan = 1;
4654 } else {
4655 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4656 }
4657
4658 alu.src[1].sel = tmp0;
4659 alu.src[1].chan = 2;
4660
4661 alu.last = (j == 3);
4662 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4663 return r;
4664 }
4665 } else {
4666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4667 alu.op = ALU_OP2_MULLO_UINT;
4668
4669 alu.dst.sel = tmp0;
4670 alu.dst.chan = 1;
4671 alu.dst.write = 1;
4672
4673 if (signed_op) {
4674 alu.src[0].sel = tmp2;
4675 alu.src[0].chan = 1;
4676 } else {
4677 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4678 }
4679
4680 alu.src[1].sel = tmp0;
4681 alu.src[1].chan = 2;
4682
4683 alu.last = 1;
4684 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4685 return r;
4686 }
4687
4688 /* 12. tmp0.w = src1 - tmp0.y = r */
4689 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4690 alu.op = ALU_OP2_SUB_INT;
4691
4692 alu.dst.sel = tmp0;
4693 alu.dst.chan = 3;
4694 alu.dst.write = 1;
4695
4696 if (signed_op) {
4697 alu.src[0].sel = tmp2;
4698 alu.src[0].chan = 0;
4699 } else {
4700 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4701 }
4702
4703 alu.src[1].sel = tmp0;
4704 alu.src[1].chan = 1;
4705
4706 alu.last = 1;
4707 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4708 return r;
4709
4710 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
4711 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4712 alu.op = ALU_OP2_SETGE_UINT;
4713
4714 alu.dst.sel = tmp1;
4715 alu.dst.chan = 0;
4716 alu.dst.write = 1;
4717
4718 alu.src[0].sel = tmp0;
4719 alu.src[0].chan = 3;
4720 if (signed_op) {
4721 alu.src[1].sel = tmp2;
4722 alu.src[1].chan = 1;
4723 } else {
4724 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4725 }
4726
4727 alu.last = 1;
4728 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4729 return r;
4730
4731 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
4732 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4733 alu.op = ALU_OP2_SETGE_UINT;
4734
4735 alu.dst.sel = tmp1;
4736 alu.dst.chan = 1;
4737 alu.dst.write = 1;
4738
4739 if (signed_op) {
4740 alu.src[0].sel = tmp2;
4741 alu.src[0].chan = 0;
4742 } else {
4743 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4744 }
4745
4746 alu.src[1].sel = tmp0;
4747 alu.src[1].chan = 1;
4748
4749 alu.last = 1;
4750 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4751 return r;
4752
4753 if (mod) { /* UMOD */
4754
4755 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
4756 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4757 alu.op = ALU_OP2_SUB_INT;
4758
4759 alu.dst.sel = tmp1;
4760 alu.dst.chan = 2;
4761 alu.dst.write = 1;
4762
4763 alu.src[0].sel = tmp0;
4764 alu.src[0].chan = 3;
4765
4766 if (signed_op) {
4767 alu.src[1].sel = tmp2;
4768 alu.src[1].chan = 1;
4769 } else {
4770 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4771 }
4772
4773 alu.last = 1;
4774 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4775 return r;
4776
4777 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
4778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4779 alu.op = ALU_OP2_ADD_INT;
4780
4781 alu.dst.sel = tmp1;
4782 alu.dst.chan = 3;
4783 alu.dst.write = 1;
4784
4785 alu.src[0].sel = tmp0;
4786 alu.src[0].chan = 3;
4787 if (signed_op) {
4788 alu.src[1].sel = tmp2;
4789 alu.src[1].chan = 1;
4790 } else {
4791 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4792 }
4793
4794 alu.last = 1;
4795 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4796 return r;
4797
4798 } else { /* UDIV */
4799
4800 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
4801 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4802 alu.op = ALU_OP2_ADD_INT;
4803
4804 alu.dst.sel = tmp1;
4805 alu.dst.chan = 2;
4806 alu.dst.write = 1;
4807
4808 alu.src[0].sel = tmp0;
4809 alu.src[0].chan = 2;
4810 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4811
4812 alu.last = 1;
4813 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4814 return r;
4815
4816 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
4817 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4818 alu.op = ALU_OP2_ADD_INT;
4819
4820 alu.dst.sel = tmp1;
4821 alu.dst.chan = 3;
4822 alu.dst.write = 1;
4823
4824 alu.src[0].sel = tmp0;
4825 alu.src[0].chan = 2;
4826 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
4827
4828 alu.last = 1;
4829 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4830 return r;
4831
4832 }
4833
4834 /* 17. tmp1.x = tmp1.x & tmp1.y */
4835 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4836 alu.op = ALU_OP2_AND_INT;
4837
4838 alu.dst.sel = tmp1;
4839 alu.dst.chan = 0;
4840 alu.dst.write = 1;
4841
4842 alu.src[0].sel = tmp1;
4843 alu.src[0].chan = 0;
4844 alu.src[1].sel = tmp1;
4845 alu.src[1].chan = 1;
4846
4847 alu.last = 1;
4848 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4849 return r;
4850
4851 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
4852 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
4853 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4854 alu.op = ALU_OP3_CNDE_INT;
4855 alu.is_op3 = 1;
4856
4857 alu.dst.sel = tmp0;
4858 alu.dst.chan = 2;
4859 alu.dst.write = 1;
4860
4861 alu.src[0].sel = tmp1;
4862 alu.src[0].chan = 0;
4863 alu.src[1].sel = tmp0;
4864 alu.src[1].chan = mod ? 3 : 2;
4865 alu.src[2].sel = tmp1;
4866 alu.src[2].chan = 2;
4867
4868 alu.last = 1;
4869 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4870 return r;
4871
4872 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
4873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4874 alu.op = ALU_OP3_CNDE_INT;
4875 alu.is_op3 = 1;
4876
4877 if (signed_op) {
4878 alu.dst.sel = tmp0;
4879 alu.dst.chan = 2;
4880 alu.dst.write = 1;
4881 } else {
4882 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4883 }
4884
4885 alu.src[0].sel = tmp1;
4886 alu.src[0].chan = 1;
4887 alu.src[1].sel = tmp1;
4888 alu.src[1].chan = 3;
4889 alu.src[2].sel = tmp0;
4890 alu.src[2].chan = 2;
4891
4892 alu.last = 1;
4893 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4894 return r;
4895
4896 if (signed_op) {
4897
4898 /* fix the sign of the result */
4899
4900 if (mod) {
4901
4902 /* tmp0.x = -tmp0.z */
4903 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4904 alu.op = ALU_OP2_SUB_INT;
4905
4906 alu.dst.sel = tmp0;
4907 alu.dst.chan = 0;
4908 alu.dst.write = 1;
4909
4910 alu.src[0].sel = V_SQ_ALU_SRC_0;
4911 alu.src[1].sel = tmp0;
4912 alu.src[1].chan = 2;
4913
4914 alu.last = 1;
4915 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4916 return r;
4917
4918 /* sign of the remainder is the same as the sign of src0 */
4919 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
4920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4921 alu.op = ALU_OP3_CNDGE_INT;
4922 alu.is_op3 = 1;
4923
4924 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4925
4926 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4927 alu.src[1].sel = tmp0;
4928 alu.src[1].chan = 2;
4929 alu.src[2].sel = tmp0;
4930 alu.src[2].chan = 0;
4931
4932 alu.last = 1;
4933 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4934 return r;
4935
4936 } else {
4937
4938 /* tmp0.x = -tmp0.z */
4939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4940 alu.op = ALU_OP2_SUB_INT;
4941
4942 alu.dst.sel = tmp0;
4943 alu.dst.chan = 0;
4944 alu.dst.write = 1;
4945
4946 alu.src[0].sel = V_SQ_ALU_SRC_0;
4947 alu.src[1].sel = tmp0;
4948 alu.src[1].chan = 2;
4949
4950 alu.last = 1;
4951 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4952 return r;
4953
4954 /* fix the quotient sign (same as the sign of src0*src1) */
4955 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
4956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4957 alu.op = ALU_OP3_CNDGE_INT;
4958 alu.is_op3 = 1;
4959
4960 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4961
4962 alu.src[0].sel = tmp2;
4963 alu.src[0].chan = 2;
4964 alu.src[1].sel = tmp0;
4965 alu.src[1].chan = 2;
4966 alu.src[2].sel = tmp0;
4967 alu.src[2].chan = 0;
4968
4969 alu.last = 1;
4970 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4971 return r;
4972 }
4973 }
4974 }
4975 return 0;
4976 }
4977
4978 static int tgsi_udiv(struct r600_shader_ctx *ctx)
4979 {
4980 return tgsi_divmod(ctx, 0, 0);
4981 }
4982
4983 static int tgsi_umod(struct r600_shader_ctx *ctx)
4984 {
4985 return tgsi_divmod(ctx, 1, 0);
4986 }
4987
4988 static int tgsi_idiv(struct r600_shader_ctx *ctx)
4989 {
4990 return tgsi_divmod(ctx, 0, 1);
4991 }
4992
4993 static int tgsi_imod(struct r600_shader_ctx *ctx)
4994 {
4995 return tgsi_divmod(ctx, 1, 1);
4996 }
4997
4998
4999 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5000 {
5001 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5002 struct r600_bytecode_alu alu;
5003 int i, r;
5004 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5005 int last_inst = tgsi_last_instruction(write_mask);
5006
5007 for (i = 0; i < 4; i++) {
5008 if (!(write_mask & (1<<i)))
5009 continue;
5010
5011 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5012 alu.op = ALU_OP1_TRUNC;
5013
5014 alu.dst.sel = ctx->temp_reg;
5015 alu.dst.chan = i;
5016 alu.dst.write = 1;
5017
5018 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5019 if (i == last_inst)
5020 alu.last = 1;
5021 r = r600_bytecode_add_alu(ctx->bc, &alu);
5022 if (r)
5023 return r;
5024 }
5025
5026 for (i = 0; i < 4; i++) {
5027 if (!(write_mask & (1<<i)))
5028 continue;
5029
5030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5031 alu.op = ctx->inst_info->op;
5032
5033 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5034
5035 alu.src[0].sel = ctx->temp_reg;
5036 alu.src[0].chan = i;
5037
5038 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5039 alu.last = 1;
5040 r = r600_bytecode_add_alu(ctx->bc, &alu);
5041 if (r)
5042 return r;
5043 }
5044
5045 return 0;
5046 }
5047
5048 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5049 {
5050 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5051 struct r600_bytecode_alu alu;
5052 int i, r;
5053 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5054 int last_inst = tgsi_last_instruction(write_mask);
5055
5056 /* tmp = -src */
5057 for (i = 0; i < 4; i++) {
5058 if (!(write_mask & (1<<i)))
5059 continue;
5060
5061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5062 alu.op = ALU_OP2_SUB_INT;
5063
5064 alu.dst.sel = ctx->temp_reg;
5065 alu.dst.chan = i;
5066 alu.dst.write = 1;
5067
5068 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5069 alu.src[0].sel = V_SQ_ALU_SRC_0;
5070
5071 if (i == last_inst)
5072 alu.last = 1;
5073 r = r600_bytecode_add_alu(ctx->bc, &alu);
5074 if (r)
5075 return r;
5076 }
5077
5078 /* dst = (src >= 0 ? src : tmp) */
5079 for (i = 0; i < 4; i++) {
5080 if (!(write_mask & (1<<i)))
5081 continue;
5082
5083 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5084 alu.op = ALU_OP3_CNDGE_INT;
5085 alu.is_op3 = 1;
5086 alu.dst.write = 1;
5087
5088 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5089
5090 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5091 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5092 alu.src[2].sel = ctx->temp_reg;
5093 alu.src[2].chan = i;
5094
5095 if (i == last_inst)
5096 alu.last = 1;
5097 r = r600_bytecode_add_alu(ctx->bc, &alu);
5098 if (r)
5099 return r;
5100 }
5101 return 0;
5102 }
5103
5104 static int tgsi_issg(struct r600_shader_ctx *ctx)
5105 {
5106 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5107 struct r600_bytecode_alu alu;
5108 int i, r;
5109 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5110 int last_inst = tgsi_last_instruction(write_mask);
5111
5112 /* tmp = (src >= 0 ? src : -1) */
5113 for (i = 0; i < 4; i++) {
5114 if (!(write_mask & (1<<i)))
5115 continue;
5116
5117 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5118 alu.op = ALU_OP3_CNDGE_INT;
5119 alu.is_op3 = 1;
5120
5121 alu.dst.sel = ctx->temp_reg;
5122 alu.dst.chan = i;
5123 alu.dst.write = 1;
5124
5125 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5126 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5127 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
5128
5129 if (i == last_inst)
5130 alu.last = 1;
5131 r = r600_bytecode_add_alu(ctx->bc, &alu);
5132 if (r)
5133 return r;
5134 }
5135
5136 /* dst = (tmp > 0 ? 1 : tmp) */
5137 for (i = 0; i < 4; i++) {
5138 if (!(write_mask & (1<<i)))
5139 continue;
5140
5141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5142 alu.op = ALU_OP3_CNDGT_INT;
5143 alu.is_op3 = 1;
5144 alu.dst.write = 1;
5145
5146 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5147
5148 alu.src[0].sel = ctx->temp_reg;
5149 alu.src[0].chan = i;
5150
5151 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5152
5153 alu.src[2].sel = ctx->temp_reg;
5154 alu.src[2].chan = i;
5155
5156 if (i == last_inst)
5157 alu.last = 1;
5158 r = r600_bytecode_add_alu(ctx->bc, &alu);
5159 if (r)
5160 return r;
5161 }
5162 return 0;
5163 }
5164
5165
5166
5167 static int tgsi_ssg(struct r600_shader_ctx *ctx)
5168 {
5169 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5170 struct r600_bytecode_alu alu;
5171 int i, r;
5172
5173 /* tmp = (src > 0 ? 1 : src) */
5174 for (i = 0; i < 4; i++) {
5175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5176 alu.op = ALU_OP3_CNDGT;
5177 alu.is_op3 = 1;
5178
5179 alu.dst.sel = ctx->temp_reg;
5180 alu.dst.chan = i;
5181
5182 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5183 alu.src[1].sel = V_SQ_ALU_SRC_1;
5184 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
5185
5186 if (i == 3)
5187 alu.last = 1;
5188 r = r600_bytecode_add_alu(ctx->bc, &alu);
5189 if (r)
5190 return r;
5191 }
5192
5193 /* dst = (-tmp > 0 ? -1 : tmp) */
5194 for (i = 0; i < 4; i++) {
5195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5196 alu.op = ALU_OP3_CNDGT;
5197 alu.is_op3 = 1;
5198 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5199
5200 alu.src[0].sel = ctx->temp_reg;
5201 alu.src[0].chan = i;
5202 alu.src[0].neg = 1;
5203
5204 alu.src[1].sel = V_SQ_ALU_SRC_1;
5205 alu.src[1].neg = 1;
5206
5207 alu.src[2].sel = ctx->temp_reg;
5208 alu.src[2].chan = i;
5209
5210 if (i == 3)
5211 alu.last = 1;
5212 r = r600_bytecode_add_alu(ctx->bc, &alu);
5213 if (r)
5214 return r;
5215 }
5216 return 0;
5217 }
5218
5219 static int tgsi_bfi(struct r600_shader_ctx *ctx)
5220 {
5221 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5222 struct r600_bytecode_alu alu;
5223 int i, r, t1, t2;
5224
5225 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5226 int last_inst = tgsi_last_instruction(write_mask);
5227
5228 t1 = ctx->temp_reg;
5229
5230 for (i = 0; i < 4; i++) {
5231 if (!(write_mask & (1<<i)))
5232 continue;
5233
5234 /* create mask tmp */
5235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5236 alu.op = ALU_OP2_BFM_INT;
5237 alu.dst.sel = t1;
5238 alu.dst.chan = i;
5239 alu.dst.write = 1;
5240 alu.last = i == last_inst;
5241
5242 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
5243 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5244
5245 r = r600_bytecode_add_alu(ctx->bc, &alu);
5246 if (r)
5247 return r;
5248 }
5249
5250 t2 = r600_get_temp(ctx);
5251
5252 for (i = 0; i < 4; i++) {
5253 if (!(write_mask & (1<<i)))
5254 continue;
5255
5256 /* shift insert left */
5257 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5258 alu.op = ALU_OP2_LSHL_INT;
5259 alu.dst.sel = t2;
5260 alu.dst.chan = i;
5261 alu.dst.write = 1;
5262 alu.last = i == last_inst;
5263
5264 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5265 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5266
5267 r = r600_bytecode_add_alu(ctx->bc, &alu);
5268 if (r)
5269 return r;
5270 }
5271
5272 for (i = 0; i < 4; i++) {
5273 if (!(write_mask & (1<<i)))
5274 continue;
5275
5276 /* actual bitfield insert */
5277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5278 alu.op = ALU_OP3_BFI_INT;
5279 alu.is_op3 = 1;
5280 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5281 alu.dst.chan = i;
5282 alu.dst.write = 1;
5283 alu.last = i == last_inst;
5284
5285 alu.src[0].sel = t1;
5286 alu.src[0].chan = i;
5287 alu.src[1].sel = t2;
5288 alu.src[1].chan = i;
5289 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
5290
5291 r = r600_bytecode_add_alu(ctx->bc, &alu);
5292 if (r)
5293 return r;
5294 }
5295
5296 return 0;
5297 }
5298
5299 static int tgsi_msb(struct r600_shader_ctx *ctx)
5300 {
5301 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5302 struct r600_bytecode_alu alu;
5303 int i, r, t1, t2;
5304
5305 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5306 int last_inst = tgsi_last_instruction(write_mask);
5307
5308 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
5309 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
5310
5311 t1 = ctx->temp_reg;
5312
5313 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
5314 for (i = 0; i < 4; i++) {
5315 if (!(write_mask & (1<<i)))
5316 continue;
5317
5318 /* t1 = FFBH_INT / FFBH_UINT */
5319 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5320 alu.op = ctx->inst_info->op;
5321 alu.dst.sel = t1;
5322 alu.dst.chan = i;
5323 alu.dst.write = 1;
5324 alu.last = i == last_inst;
5325
5326 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5327
5328 r = r600_bytecode_add_alu(ctx->bc, &alu);
5329 if (r)
5330 return r;
5331 }
5332
5333 t2 = r600_get_temp(ctx);
5334
5335 for (i = 0; i < 4; i++) {
5336 if (!(write_mask & (1<<i)))
5337 continue;
5338
5339 /* t2 = 31 - t1 */
5340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5341 alu.op = ALU_OP2_SUB_INT;
5342 alu.dst.sel = t2;
5343 alu.dst.chan = i;
5344 alu.dst.write = 1;
5345 alu.last = i == last_inst;
5346
5347 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
5348 alu.src[0].value = 31;
5349 alu.src[1].sel = t1;
5350 alu.src[1].chan = i;
5351
5352 r = r600_bytecode_add_alu(ctx->bc, &alu);
5353 if (r)
5354 return r;
5355 }
5356
5357 for (i = 0; i < 4; i++) {
5358 if (!(write_mask & (1<<i)))
5359 continue;
5360
5361 /* result = t1 >= 0 ? t2 : t1 */
5362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5363 alu.op = ALU_OP3_CNDGE_INT;
5364 alu.is_op3 = 1;
5365 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5366 alu.dst.chan = i;
5367 alu.dst.write = 1;
5368 alu.last = i == last_inst;
5369
5370 alu.src[0].sel = t1;
5371 alu.src[0].chan = i;
5372 alu.src[1].sel = t2;
5373 alu.src[1].chan = i;
5374 alu.src[2].sel = t1;
5375 alu.src[2].chan = i;
5376
5377 r = r600_bytecode_add_alu(ctx->bc, &alu);
5378 if (r)
5379 return r;
5380 }
5381
5382 return 0;
5383 }
5384
5385 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
5386 {
5387 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5388 struct r600_bytecode_alu alu;
5389 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
5390 unsigned location;
5391 int input;
5392
5393 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5394
5395 input = inst->Src[0].Register.Index;
5396
5397 /* Interpolators have been marked for use already by allocate_system_value_inputs */
5398 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5399 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5400 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
5401 }
5402 else {
5403 location = TGSI_INTERPOLATE_LOC_CENTROID;
5404 }
5405
5406 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
5407 if (k < 0)
5408 k = 0;
5409 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
5410 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
5411
5412 /* NOTE: currently offset is not perspective correct */
5413 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5414 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5415 int sample_gpr = -1;
5416 int gradientsH, gradientsV;
5417 struct r600_bytecode_tex tex;
5418
5419 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5420 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
5421 }
5422
5423 gradientsH = r600_get_temp(ctx);
5424 gradientsV = r600_get_temp(ctx);
5425 for (i = 0; i < 2; i++) {
5426 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5427 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
5428 tex.src_gpr = interp_gpr;
5429 tex.src_sel_x = interp_base_chan + 0;
5430 tex.src_sel_y = interp_base_chan + 1;
5431 tex.src_sel_z = 0;
5432 tex.src_sel_w = 0;
5433 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
5434 tex.dst_sel_x = 0;
5435 tex.dst_sel_y = 1;
5436 tex.dst_sel_z = 7;
5437 tex.dst_sel_w = 7;
5438 tex.inst_mod = 1; // Use per pixel gradient calculation
5439 tex.sampler_id = 0;
5440 tex.resource_id = tex.sampler_id;
5441 r = r600_bytecode_add_tex(ctx->bc, &tex);
5442 if (r)
5443 return r;
5444 }
5445
5446 for (i = 0; i < 2; i++) {
5447 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5448 alu.op = ALU_OP3_MULADD;
5449 alu.is_op3 = 1;
5450 alu.src[0].sel = gradientsH;
5451 alu.src[0].chan = i;
5452 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5453 alu.src[1].sel = sample_gpr;
5454 alu.src[1].chan = 2;
5455 }
5456 else {
5457 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
5458 }
5459 alu.src[2].sel = interp_gpr;
5460 alu.src[2].chan = interp_base_chan + i;
5461 alu.dst.sel = ctx->temp_reg;
5462 alu.dst.chan = i;
5463 alu.last = i == 1;
5464
5465 r = r600_bytecode_add_alu(ctx->bc, &alu);
5466 if (r)
5467 return r;
5468 }
5469
5470 for (i = 0; i < 2; i++) {
5471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5472 alu.op = ALU_OP3_MULADD;
5473 alu.is_op3 = 1;
5474 alu.src[0].sel = gradientsV;
5475 alu.src[0].chan = i;
5476 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5477 alu.src[1].sel = sample_gpr;
5478 alu.src[1].chan = 3;
5479 }
5480 else {
5481 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
5482 }
5483 alu.src[2].sel = ctx->temp_reg;
5484 alu.src[2].chan = i;
5485 alu.dst.sel = ctx->temp_reg;
5486 alu.dst.chan = i;
5487 alu.last = i == 1;
5488
5489 r = r600_bytecode_add_alu(ctx->bc, &alu);
5490 if (r)
5491 return r;
5492 }
5493 }
5494
5495 tmp = r600_get_temp(ctx);
5496 for (i = 0; i < 8; i++) {
5497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5498 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
5499
5500 alu.dst.sel = tmp;
5501 if ((i > 1 && i < 6)) {
5502 alu.dst.write = 1;
5503 }
5504 else {
5505 alu.dst.write = 0;
5506 }
5507 alu.dst.chan = i % 4;
5508
5509 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5510 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5511 alu.src[0].sel = ctx->temp_reg;
5512 alu.src[0].chan = 1 - (i % 2);
5513 } else {
5514 alu.src[0].sel = interp_gpr;
5515 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
5516 }
5517 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
5518 alu.src[1].chan = 0;
5519
5520 alu.last = i % 4 == 3;
5521 alu.bank_swizzle_force = SQ_ALU_VEC_210;
5522
5523 r = r600_bytecode_add_alu(ctx->bc, &alu);
5524 if (r)
5525 return r;
5526 }
5527
5528 // INTERP can't swizzle dst
5529 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5530 for (i = 0; i <= lasti; i++) {
5531 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5532 continue;
5533
5534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5535 alu.op = ALU_OP1_MOV;
5536 alu.src[0].sel = tmp;
5537 alu.src[0].chan = ctx->src[0].swizzle[i];
5538 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5539 alu.dst.write = 1;
5540 alu.last = i == lasti;
5541 r = r600_bytecode_add_alu(ctx->bc, &alu);
5542 if (r)
5543 return r;
5544 }
5545
5546 return 0;
5547 }
5548
5549
5550 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
5551 {
5552 struct r600_bytecode_alu alu;
5553 int i, r;
5554
5555 for (i = 0; i < 4; i++) {
5556 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5557 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
5558 alu.op = ALU_OP0_NOP;
5559 alu.dst.chan = i;
5560 } else {
5561 alu.op = ALU_OP1_MOV;
5562 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5563 alu.src[0].sel = ctx->temp_reg;
5564 alu.src[0].chan = i;
5565 }
5566 if (i == 3) {
5567 alu.last = 1;
5568 }
5569 r = r600_bytecode_add_alu(ctx->bc, &alu);
5570 if (r)
5571 return r;
5572 }
5573 return 0;
5574 }
5575
5576 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
5577 unsigned temp, int chan,
5578 struct r600_bytecode_alu_src *bc_src,
5579 const struct r600_shader_src *shader_src)
5580 {
5581 struct r600_bytecode_alu alu;
5582 int r;
5583
5584 r600_bytecode_src(bc_src, shader_src, chan);
5585
5586 /* op3 operands don't support abs modifier */
5587 if (bc_src->abs) {
5588 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
5589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5590 alu.op = ALU_OP1_MOV;
5591 alu.dst.sel = temp;
5592 alu.dst.chan = chan;
5593 alu.dst.write = 1;
5594
5595 alu.src[0] = *bc_src;
5596 alu.last = true; // sufficient?
5597 r = r600_bytecode_add_alu(ctx->bc, &alu);
5598 if (r)
5599 return r;
5600
5601 memset(bc_src, 0, sizeof(*bc_src));
5602 bc_src->sel = temp;
5603 bc_src->chan = chan;
5604 }
5605 return 0;
5606 }
5607
5608 static int tgsi_op3(struct r600_shader_ctx *ctx)
5609 {
5610 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5611 struct r600_bytecode_alu alu;
5612 int i, j, r;
5613 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5614 int temp_regs[4];
5615
5616 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5617 temp_regs[j] = 0;
5618 if (ctx->src[j].abs)
5619 temp_regs[j] = r600_get_temp(ctx);
5620 }
5621 for (i = 0; i < lasti + 1; i++) {
5622 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5623 continue;
5624
5625 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5626 alu.op = ctx->inst_info->op;
5627 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5628 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
5629 if (r)
5630 return r;
5631 }
5632
5633 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5634 alu.dst.chan = i;
5635 alu.dst.write = 1;
5636 alu.is_op3 = 1;
5637 if (i == lasti) {
5638 alu.last = 1;
5639 }
5640 r = r600_bytecode_add_alu(ctx->bc, &alu);
5641 if (r)
5642 return r;
5643 }
5644 return 0;
5645 }
5646
5647 static int tgsi_dp(struct r600_shader_ctx *ctx)
5648 {
5649 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5650 struct r600_bytecode_alu alu;
5651 int i, j, r;
5652
5653 for (i = 0; i < 4; i++) {
5654 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5655 alu.op = ctx->inst_info->op;
5656 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5657 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5658 }
5659
5660 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5661 alu.dst.chan = i;
5662 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5663 /* handle some special cases */
5664 switch (inst->Instruction.Opcode) {
5665 case TGSI_OPCODE_DP2:
5666 if (i > 1) {
5667 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5668 alu.src[0].chan = alu.src[1].chan = 0;
5669 }
5670 break;
5671 case TGSI_OPCODE_DP3:
5672 if (i > 2) {
5673 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5674 alu.src[0].chan = alu.src[1].chan = 0;
5675 }
5676 break;
5677 case TGSI_OPCODE_DPH:
5678 if (i == 3) {
5679 alu.src[0].sel = V_SQ_ALU_SRC_1;
5680 alu.src[0].chan = 0;
5681 alu.src[0].neg = 0;
5682 }
5683 break;
5684 default:
5685 break;
5686 }
5687 if (i == 3) {
5688 alu.last = 1;
5689 }
5690 r = r600_bytecode_add_alu(ctx->bc, &alu);
5691 if (r)
5692 return r;
5693 }
5694 return 0;
5695 }
5696
5697 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
5698 unsigned index)
5699 {
5700 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5701 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
5702 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
5703 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
5704 ctx->src[index].neg || ctx->src[index].abs ||
5705 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
5706 }
5707
5708 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
5709 unsigned index)
5710 {
5711 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5712 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
5713 }
5714
5715 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
5716 {
5717 struct r600_bytecode_vtx vtx;
5718 struct r600_bytecode_alu alu;
5719 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5720 int src_gpr, r, i;
5721 int id = tgsi_tex_get_src_gpr(ctx, 1);
5722
5723 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5724 if (src_requires_loading) {
5725 for (i = 0; i < 4; i++) {
5726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5727 alu.op = ALU_OP1_MOV;
5728 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5729 alu.dst.sel = ctx->temp_reg;
5730 alu.dst.chan = i;
5731 if (i == 3)
5732 alu.last = 1;
5733 alu.dst.write = 1;
5734 r = r600_bytecode_add_alu(ctx->bc, &alu);
5735 if (r)
5736 return r;
5737 }
5738 src_gpr = ctx->temp_reg;
5739 }
5740
5741 memset(&vtx, 0, sizeof(vtx));
5742 vtx.op = FETCH_OP_VFETCH;
5743 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
5744 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
5745 vtx.src_gpr = src_gpr;
5746 vtx.mega_fetch_count = 16;
5747 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5748 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
5749 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
5750 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
5751 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
5752 vtx.use_const_fields = 1;
5753
5754 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
5755 return r;
5756
5757 if (ctx->bc->chip_class >= EVERGREEN)
5758 return 0;
5759
5760 for (i = 0; i < 4; i++) {
5761 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5762 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5763 continue;
5764
5765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5766 alu.op = ALU_OP2_AND_INT;
5767
5768 alu.dst.chan = i;
5769 alu.dst.sel = vtx.dst_gpr;
5770 alu.dst.write = 1;
5771
5772 alu.src[0].sel = vtx.dst_gpr;
5773 alu.src[0].chan = i;
5774
5775 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
5776 alu.src[1].sel += (id * 2);
5777 alu.src[1].chan = i % 4;
5778 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5779
5780 if (i == lasti)
5781 alu.last = 1;
5782 r = r600_bytecode_add_alu(ctx->bc, &alu);
5783 if (r)
5784 return r;
5785 }
5786
5787 if (inst->Dst[0].Register.WriteMask & 3) {
5788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5789 alu.op = ALU_OP2_OR_INT;
5790
5791 alu.dst.chan = 3;
5792 alu.dst.sel = vtx.dst_gpr;
5793 alu.dst.write = 1;
5794
5795 alu.src[0].sel = vtx.dst_gpr;
5796 alu.src[0].chan = 3;
5797
5798 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
5799 alu.src[1].chan = 0;
5800 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5801
5802 alu.last = 1;
5803 r = r600_bytecode_add_alu(ctx->bc, &alu);
5804 if (r)
5805 return r;
5806 }
5807 return 0;
5808 }
5809
5810 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
5811 {
5812 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5813 struct r600_bytecode_alu alu;
5814 int r;
5815 int id = tgsi_tex_get_src_gpr(ctx, 1);
5816
5817 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5818 alu.op = ALU_OP1_MOV;
5819 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
5820 if (ctx->bc->chip_class >= EVERGREEN) {
5821 /* channel 0 or 2 of each word */
5822 alu.src[0].sel += (id / 2);
5823 alu.src[0].chan = (id % 2) * 2;
5824 } else {
5825 /* r600 we have them at channel 2 of the second dword */
5826 alu.src[0].sel += (id * 2) + 1;
5827 alu.src[0].chan = 1;
5828 }
5829 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5830 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5831 alu.last = 1;
5832 r = r600_bytecode_add_alu(ctx->bc, &alu);
5833 if (r)
5834 return r;
5835 return 0;
5836 }
5837
5838 static int tgsi_tex(struct r600_shader_ctx *ctx)
5839 {
5840 static float one_point_five = 1.5f;
5841 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5842 struct r600_bytecode_tex tex;
5843 struct r600_bytecode_alu alu;
5844 unsigned src_gpr;
5845 int r, i, j;
5846 int opcode;
5847 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
5848 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5849 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
5850 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
5851
5852 bool txf_add_offsets = inst->Texture.NumOffsets &&
5853 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5854 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
5855
5856 /* Texture fetch instructions can only use gprs as source.
5857 * Also they cannot negate the source or take the absolute value */
5858 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
5859 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
5860 tgsi_tex_src_requires_loading(ctx, 0)) ||
5861 read_compressed_msaa || txf_add_offsets;
5862
5863 boolean src_loaded = FALSE;
5864 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
5865 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
5866 boolean has_txq_cube_array_z = false;
5867 unsigned sampler_index_mode;
5868
5869 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
5870 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5871 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
5872 if (inst->Dst[0].Register.WriteMask & 4) {
5873 ctx->shader->has_txq_cube_array_z_comp = true;
5874 has_txq_cube_array_z = true;
5875 }
5876
5877 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
5878 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5879 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
5880 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
5881 sampler_src_reg = 2;
5882
5883 /* TGSI moves the sampler to src reg 3 for TXD */
5884 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
5885 sampler_src_reg = 3;
5886
5887 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
5888
5889 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5890
5891 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
5892 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
5893 ctx->shader->uses_tex_buffers = true;
5894 return r600_do_buffer_txq(ctx);
5895 }
5896 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
5897 if (ctx->bc->chip_class < EVERGREEN)
5898 ctx->shader->uses_tex_buffers = true;
5899 return do_vtx_fetch_inst(ctx, src_requires_loading);
5900 }
5901 }
5902
5903 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
5904 int out_chan;
5905 /* Add perspective divide */
5906 if (ctx->bc->chip_class == CAYMAN) {
5907 out_chan = 2;
5908 for (i = 0; i < 3; i++) {
5909 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5910 alu.op = ALU_OP1_RECIP_IEEE;
5911 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5912
5913 alu.dst.sel = ctx->temp_reg;
5914 alu.dst.chan = i;
5915 if (i == 2)
5916 alu.last = 1;
5917 if (out_chan == i)
5918 alu.dst.write = 1;
5919 r = r600_bytecode_add_alu(ctx->bc, &alu);
5920 if (r)
5921 return r;
5922 }
5923
5924 } else {
5925 out_chan = 3;
5926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5927 alu.op = ALU_OP1_RECIP_IEEE;
5928 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5929
5930 alu.dst.sel = ctx->temp_reg;
5931 alu.dst.chan = out_chan;
5932 alu.last = 1;
5933 alu.dst.write = 1;
5934 r = r600_bytecode_add_alu(ctx->bc, &alu);
5935 if (r)
5936 return r;
5937 }
5938
5939 for (i = 0; i < 3; i++) {
5940 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5941 alu.op = ALU_OP2_MUL;
5942 alu.src[0].sel = ctx->temp_reg;
5943 alu.src[0].chan = out_chan;
5944 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5945 alu.dst.sel = ctx->temp_reg;
5946 alu.dst.chan = i;
5947 alu.dst.write = 1;
5948 r = r600_bytecode_add_alu(ctx->bc, &alu);
5949 if (r)
5950 return r;
5951 }
5952 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5953 alu.op = ALU_OP1_MOV;
5954 alu.src[0].sel = V_SQ_ALU_SRC_1;
5955 alu.src[0].chan = 0;
5956 alu.dst.sel = ctx->temp_reg;
5957 alu.dst.chan = 3;
5958 alu.last = 1;
5959 alu.dst.write = 1;
5960 r = r600_bytecode_add_alu(ctx->bc, &alu);
5961 if (r)
5962 return r;
5963 src_loaded = TRUE;
5964 src_gpr = ctx->temp_reg;
5965 }
5966
5967
5968 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
5969 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5970 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5971 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
5972 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
5973 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
5974
5975 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
5976 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
5977
5978 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
5979 for (i = 0; i < 4; i++) {
5980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5981 alu.op = ALU_OP2_CUBE;
5982 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5983 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
5984 alu.dst.sel = ctx->temp_reg;
5985 alu.dst.chan = i;
5986 if (i == 3)
5987 alu.last = 1;
5988 alu.dst.write = 1;
5989 r = r600_bytecode_add_alu(ctx->bc, &alu);
5990 if (r)
5991 return r;
5992 }
5993
5994 /* tmp1.z = RCP_e(|tmp1.z|) */
5995 if (ctx->bc->chip_class == CAYMAN) {
5996 for (i = 0; i < 3; i++) {
5997 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5998 alu.op = ALU_OP1_RECIP_IEEE;
5999 alu.src[0].sel = ctx->temp_reg;
6000 alu.src[0].chan = 2;
6001 alu.src[0].abs = 1;
6002 alu.dst.sel = ctx->temp_reg;
6003 alu.dst.chan = i;
6004 if (i == 2)
6005 alu.dst.write = 1;
6006 if (i == 2)
6007 alu.last = 1;
6008 r = r600_bytecode_add_alu(ctx->bc, &alu);
6009 if (r)
6010 return r;
6011 }
6012 } else {
6013 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6014 alu.op = ALU_OP1_RECIP_IEEE;
6015 alu.src[0].sel = ctx->temp_reg;
6016 alu.src[0].chan = 2;
6017 alu.src[0].abs = 1;
6018 alu.dst.sel = ctx->temp_reg;
6019 alu.dst.chan = 2;
6020 alu.dst.write = 1;
6021 alu.last = 1;
6022 r = r600_bytecode_add_alu(ctx->bc, &alu);
6023 if (r)
6024 return r;
6025 }
6026
6027 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6028 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6029 * muladd has no writemask, have to use another temp
6030 */
6031 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6032 alu.op = ALU_OP3_MULADD;
6033 alu.is_op3 = 1;
6034
6035 alu.src[0].sel = ctx->temp_reg;
6036 alu.src[0].chan = 0;
6037 alu.src[1].sel = ctx->temp_reg;
6038 alu.src[1].chan = 2;
6039
6040 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6041 alu.src[2].chan = 0;
6042 alu.src[2].value = *(uint32_t *)&one_point_five;
6043
6044 alu.dst.sel = ctx->temp_reg;
6045 alu.dst.chan = 0;
6046 alu.dst.write = 1;
6047
6048 r = r600_bytecode_add_alu(ctx->bc, &alu);
6049 if (r)
6050 return r;
6051
6052 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6053 alu.op = ALU_OP3_MULADD;
6054 alu.is_op3 = 1;
6055
6056 alu.src[0].sel = ctx->temp_reg;
6057 alu.src[0].chan = 1;
6058 alu.src[1].sel = ctx->temp_reg;
6059 alu.src[1].chan = 2;
6060
6061 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6062 alu.src[2].chan = 0;
6063 alu.src[2].value = *(uint32_t *)&one_point_five;
6064
6065 alu.dst.sel = ctx->temp_reg;
6066 alu.dst.chan = 1;
6067 alu.dst.write = 1;
6068
6069 alu.last = 1;
6070 r = r600_bytecode_add_alu(ctx->bc, &alu);
6071 if (r)
6072 return r;
6073 /* write initial compare value into Z component
6074 - W src 0 for shadow cube
6075 - X src 1 for shadow cube array */
6076 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6077 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6079 alu.op = ALU_OP1_MOV;
6080 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
6081 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
6082 else
6083 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6084 alu.dst.sel = ctx->temp_reg;
6085 alu.dst.chan = 2;
6086 alu.dst.write = 1;
6087 alu.last = 1;
6088 r = r600_bytecode_add_alu(ctx->bc, &alu);
6089 if (r)
6090 return r;
6091 }
6092
6093 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6094 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6095 if (ctx->bc->chip_class >= EVERGREEN) {
6096 int mytmp = r600_get_temp(ctx);
6097 static const float eight = 8.0f;
6098 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6099 alu.op = ALU_OP1_MOV;
6100 alu.src[0].sel = ctx->temp_reg;
6101 alu.src[0].chan = 3;
6102 alu.dst.sel = mytmp;
6103 alu.dst.chan = 0;
6104 alu.dst.write = 1;
6105 alu.last = 1;
6106 r = r600_bytecode_add_alu(ctx->bc, &alu);
6107 if (r)
6108 return r;
6109
6110 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
6111 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6112 alu.op = ALU_OP3_MULADD;
6113 alu.is_op3 = 1;
6114 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6115 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6116 alu.src[1].chan = 0;
6117 alu.src[1].value = *(uint32_t *)&eight;
6118 alu.src[2].sel = mytmp;
6119 alu.src[2].chan = 0;
6120 alu.dst.sel = ctx->temp_reg;
6121 alu.dst.chan = 3;
6122 alu.dst.write = 1;
6123 alu.last = 1;
6124 r = r600_bytecode_add_alu(ctx->bc, &alu);
6125 if (r)
6126 return r;
6127 } else if (ctx->bc->chip_class < EVERGREEN) {
6128 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6129 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
6130 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6131 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6132 tex.src_gpr = r600_get_temp(ctx);
6133 tex.src_sel_x = 0;
6134 tex.src_sel_y = 0;
6135 tex.src_sel_z = 0;
6136 tex.src_sel_w = 0;
6137 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
6138 tex.coord_type_x = 1;
6139 tex.coord_type_y = 1;
6140 tex.coord_type_z = 1;
6141 tex.coord_type_w = 1;
6142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6143 alu.op = ALU_OP1_MOV;
6144 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6145 alu.dst.sel = tex.src_gpr;
6146 alu.dst.chan = 0;
6147 alu.last = 1;
6148 alu.dst.write = 1;
6149 r = r600_bytecode_add_alu(ctx->bc, &alu);
6150 if (r)
6151 return r;
6152
6153 r = r600_bytecode_add_tex(ctx->bc, &tex);
6154 if (r)
6155 return r;
6156 }
6157
6158 }
6159
6160 /* for cube forms of lod and bias we need to route things */
6161 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
6162 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
6163 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6164 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
6165 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6166 alu.op = ALU_OP1_MOV;
6167 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6168 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
6169 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
6170 else
6171 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6172 alu.dst.sel = ctx->temp_reg;
6173 alu.dst.chan = 2;
6174 alu.last = 1;
6175 alu.dst.write = 1;
6176 r = r600_bytecode_add_alu(ctx->bc, &alu);
6177 if (r)
6178 return r;
6179 }
6180
6181 src_loaded = TRUE;
6182 src_gpr = ctx->temp_reg;
6183 }
6184
6185 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
6186 int temp_h = 0, temp_v = 0;
6187 int start_val = 0;
6188
6189 /* if we've already loaded the src (i.e. CUBE don't reload it). */
6190 if (src_loaded == TRUE)
6191 start_val = 1;
6192 else
6193 src_loaded = TRUE;
6194 for (i = start_val; i < 3; i++) {
6195 int treg = r600_get_temp(ctx);
6196
6197 if (i == 0)
6198 src_gpr = treg;
6199 else if (i == 1)
6200 temp_h = treg;
6201 else
6202 temp_v = treg;
6203
6204 for (j = 0; j < 4; j++) {
6205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6206 alu.op = ALU_OP1_MOV;
6207 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
6208 alu.dst.sel = treg;
6209 alu.dst.chan = j;
6210 if (j == 3)
6211 alu.last = 1;
6212 alu.dst.write = 1;
6213 r = r600_bytecode_add_alu(ctx->bc, &alu);
6214 if (r)
6215 return r;
6216 }
6217 }
6218 for (i = 1; i < 3; i++) {
6219 /* set gradients h/v */
6220 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6221 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
6222 FETCH_OP_SET_GRADIENTS_V;
6223 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6224 tex.sampler_index_mode = sampler_index_mode;
6225 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6226 tex.resource_index_mode = sampler_index_mode;
6227
6228 tex.src_gpr = (i == 1) ? temp_h : temp_v;
6229 tex.src_sel_x = 0;
6230 tex.src_sel_y = 1;
6231 tex.src_sel_z = 2;
6232 tex.src_sel_w = 3;
6233
6234 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
6235 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
6236 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
6237 tex.coord_type_x = 1;
6238 tex.coord_type_y = 1;
6239 tex.coord_type_z = 1;
6240 tex.coord_type_w = 1;
6241 }
6242 r = r600_bytecode_add_tex(ctx->bc, &tex);
6243 if (r)
6244 return r;
6245 }
6246 }
6247
6248 if (src_requires_loading && !src_loaded) {
6249 for (i = 0; i < 4; i++) {
6250 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6251 alu.op = ALU_OP1_MOV;
6252 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6253 alu.dst.sel = ctx->temp_reg;
6254 alu.dst.chan = i;
6255 if (i == 3)
6256 alu.last = 1;
6257 alu.dst.write = 1;
6258 r = r600_bytecode_add_alu(ctx->bc, &alu);
6259 if (r)
6260 return r;
6261 }
6262 src_loaded = TRUE;
6263 src_gpr = ctx->temp_reg;
6264 }
6265
6266 /* get offset values */
6267 if (inst->Texture.NumOffsets) {
6268 assert(inst->Texture.NumOffsets == 1);
6269
6270 /* The texture offset feature doesn't work with the TXF instruction
6271 * and must be emulated by adding the offset to the texture coordinates. */
6272 if (txf_add_offsets) {
6273 const struct tgsi_texture_offset *off = inst->TexOffsets;
6274
6275 switch (inst->Texture.Texture) {
6276 case TGSI_TEXTURE_3D:
6277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6278 alu.op = ALU_OP2_ADD_INT;
6279 alu.src[0].sel = src_gpr;
6280 alu.src[0].chan = 2;
6281 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6282 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
6283 alu.dst.sel = src_gpr;
6284 alu.dst.chan = 2;
6285 alu.dst.write = 1;
6286 alu.last = 1;
6287 r = r600_bytecode_add_alu(ctx->bc, &alu);
6288 if (r)
6289 return r;
6290 /* fall through */
6291
6292 case TGSI_TEXTURE_2D:
6293 case TGSI_TEXTURE_SHADOW2D:
6294 case TGSI_TEXTURE_RECT:
6295 case TGSI_TEXTURE_SHADOWRECT:
6296 case TGSI_TEXTURE_2D_ARRAY:
6297 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6298 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6299 alu.op = ALU_OP2_ADD_INT;
6300 alu.src[0].sel = src_gpr;
6301 alu.src[0].chan = 1;
6302 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6303 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
6304 alu.dst.sel = src_gpr;
6305 alu.dst.chan = 1;
6306 alu.dst.write = 1;
6307 alu.last = 1;
6308 r = r600_bytecode_add_alu(ctx->bc, &alu);
6309 if (r)
6310 return r;
6311 /* fall through */
6312
6313 case TGSI_TEXTURE_1D:
6314 case TGSI_TEXTURE_SHADOW1D:
6315 case TGSI_TEXTURE_1D_ARRAY:
6316 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6317 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6318 alu.op = ALU_OP2_ADD_INT;
6319 alu.src[0].sel = src_gpr;
6320 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6321 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
6322 alu.dst.sel = src_gpr;
6323 alu.dst.write = 1;
6324 alu.last = 1;
6325 r = r600_bytecode_add_alu(ctx->bc, &alu);
6326 if (r)
6327 return r;
6328 break;
6329 /* texture offsets do not apply to other texture targets */
6330 }
6331 } else {
6332 switch (inst->Texture.Texture) {
6333 case TGSI_TEXTURE_3D:
6334 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
6335 /* fallthrough */
6336 case TGSI_TEXTURE_2D:
6337 case TGSI_TEXTURE_SHADOW2D:
6338 case TGSI_TEXTURE_RECT:
6339 case TGSI_TEXTURE_SHADOWRECT:
6340 case TGSI_TEXTURE_2D_ARRAY:
6341 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6342 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
6343 /* fallthrough */
6344 case TGSI_TEXTURE_1D:
6345 case TGSI_TEXTURE_SHADOW1D:
6346 case TGSI_TEXTURE_1D_ARRAY:
6347 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6348 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
6349 }
6350 }
6351 }
6352
6353 /* Obtain the sample index for reading a compressed MSAA color texture.
6354 * To read the FMASK, we use the ldfptr instruction, which tells us
6355 * where the samples are stored.
6356 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
6357 * which is the identity mapping. Each nibble says which physical sample
6358 * should be fetched to get that sample.
6359 *
6360 * Assume src.z contains the sample index. It should be modified like this:
6361 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
6362 * Then fetch the texel with src.
6363 */
6364 if (read_compressed_msaa) {
6365 unsigned sample_chan = 3;
6366 unsigned temp = r600_get_temp(ctx);
6367 assert(src_loaded);
6368
6369 /* temp.w = ldfptr() */
6370 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6371 tex.op = FETCH_OP_LD;
6372 tex.inst_mod = 1; /* to indicate this is ldfptr */
6373 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6374 tex.sampler_index_mode = sampler_index_mode;
6375 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6376 tex.resource_index_mode = sampler_index_mode;
6377 tex.src_gpr = src_gpr;
6378 tex.dst_gpr = temp;
6379 tex.dst_sel_x = 7; /* mask out these components */
6380 tex.dst_sel_y = 7;
6381 tex.dst_sel_z = 7;
6382 tex.dst_sel_w = 0; /* store X */
6383 tex.src_sel_x = 0;
6384 tex.src_sel_y = 1;
6385 tex.src_sel_z = 2;
6386 tex.src_sel_w = 3;
6387 tex.offset_x = offset_x;
6388 tex.offset_y = offset_y;
6389 tex.offset_z = offset_z;
6390 r = r600_bytecode_add_tex(ctx->bc, &tex);
6391 if (r)
6392 return r;
6393
6394 /* temp.x = sample_index*4 */
6395 if (ctx->bc->chip_class == CAYMAN) {
6396 for (i = 0 ; i < 4; i++) {
6397 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6398 alu.op = ALU_OP2_MULLO_INT;
6399 alu.src[0].sel = src_gpr;
6400 alu.src[0].chan = sample_chan;
6401 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6402 alu.src[1].value = 4;
6403 alu.dst.sel = temp;
6404 alu.dst.chan = i;
6405 alu.dst.write = i == 0;
6406 if (i == 3)
6407 alu.last = 1;
6408 r = r600_bytecode_add_alu(ctx->bc, &alu);
6409 if (r)
6410 return r;
6411 }
6412 } else {
6413 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6414 alu.op = ALU_OP2_MULLO_INT;
6415 alu.src[0].sel = src_gpr;
6416 alu.src[0].chan = sample_chan;
6417 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6418 alu.src[1].value = 4;
6419 alu.dst.sel = temp;
6420 alu.dst.chan = 0;
6421 alu.dst.write = 1;
6422 alu.last = 1;
6423 r = r600_bytecode_add_alu(ctx->bc, &alu);
6424 if (r)
6425 return r;
6426 }
6427
6428 /* sample_index = temp.w >> temp.x */
6429 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6430 alu.op = ALU_OP2_LSHR_INT;
6431 alu.src[0].sel = temp;
6432 alu.src[0].chan = 3;
6433 alu.src[1].sel = temp;
6434 alu.src[1].chan = 0;
6435 alu.dst.sel = src_gpr;
6436 alu.dst.chan = sample_chan;
6437 alu.dst.write = 1;
6438 alu.last = 1;
6439 r = r600_bytecode_add_alu(ctx->bc, &alu);
6440 if (r)
6441 return r;
6442
6443 /* sample_index & 0xF */
6444 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6445 alu.op = ALU_OP2_AND_INT;
6446 alu.src[0].sel = src_gpr;
6447 alu.src[0].chan = sample_chan;
6448 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6449 alu.src[1].value = 0xF;
6450 alu.dst.sel = src_gpr;
6451 alu.dst.chan = sample_chan;
6452 alu.dst.write = 1;
6453 alu.last = 1;
6454 r = r600_bytecode_add_alu(ctx->bc, &alu);
6455 if (r)
6456 return r;
6457 #if 0
6458 /* visualize the FMASK */
6459 for (i = 0; i < 4; i++) {
6460 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6461 alu.op = ALU_OP1_INT_TO_FLT;
6462 alu.src[0].sel = src_gpr;
6463 alu.src[0].chan = sample_chan;
6464 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6465 alu.dst.chan = i;
6466 alu.dst.write = 1;
6467 alu.last = 1;
6468 r = r600_bytecode_add_alu(ctx->bc, &alu);
6469 if (r)
6470 return r;
6471 }
6472 return 0;
6473 #endif
6474 }
6475
6476 /* does this shader want a num layers from TXQ for a cube array? */
6477 if (has_txq_cube_array_z) {
6478 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6479
6480 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6481 alu.op = ALU_OP1_MOV;
6482
6483 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6484 if (ctx->bc->chip_class >= EVERGREEN) {
6485 /* channel 1 or 3 of each word */
6486 alu.src[0].sel += (id / 2);
6487 alu.src[0].chan = ((id % 2) * 2) + 1;
6488 } else {
6489 /* r600 we have them at channel 2 of the second dword */
6490 alu.src[0].sel += (id * 2) + 1;
6491 alu.src[0].chan = 2;
6492 }
6493 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6494 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
6495 alu.last = 1;
6496 r = r600_bytecode_add_alu(ctx->bc, &alu);
6497 if (r)
6498 return r;
6499 /* disable writemask from texture instruction */
6500 inst->Dst[0].Register.WriteMask &= ~4;
6501 }
6502
6503 opcode = ctx->inst_info->op;
6504 if (opcode == FETCH_OP_GATHER4 &&
6505 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
6506 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
6507 opcode = FETCH_OP_GATHER4_O;
6508
6509 /* GATHER4_O/GATHER4_C_O use offset values loaded by
6510 SET_TEXTURE_OFFSETS instruction. The immediate offset values
6511 encoded in the instruction are ignored. */
6512 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6513 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
6514 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6515 tex.sampler_index_mode = sampler_index_mode;
6516 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6517 tex.resource_index_mode = sampler_index_mode;
6518
6519 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
6520 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
6521 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
6522 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
6523 tex.src_sel_w = 4;
6524
6525 tex.dst_sel_x = 7;
6526 tex.dst_sel_y = 7;
6527 tex.dst_sel_z = 7;
6528 tex.dst_sel_w = 7;
6529
6530 r = r600_bytecode_add_tex(ctx->bc, &tex);
6531 if (r)
6532 return r;
6533 }
6534
6535 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6536 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6537 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6538 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6539 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
6540 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6541 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6542 switch (opcode) {
6543 case FETCH_OP_SAMPLE:
6544 opcode = FETCH_OP_SAMPLE_C;
6545 break;
6546 case FETCH_OP_SAMPLE_L:
6547 opcode = FETCH_OP_SAMPLE_C_L;
6548 break;
6549 case FETCH_OP_SAMPLE_LB:
6550 opcode = FETCH_OP_SAMPLE_C_LB;
6551 break;
6552 case FETCH_OP_SAMPLE_G:
6553 opcode = FETCH_OP_SAMPLE_C_G;
6554 break;
6555 /* Texture gather variants */
6556 case FETCH_OP_GATHER4:
6557 opcode = FETCH_OP_GATHER4_C;
6558 break;
6559 case FETCH_OP_GATHER4_O:
6560 opcode = FETCH_OP_GATHER4_C_O;
6561 break;
6562 }
6563 }
6564
6565 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6566 tex.op = opcode;
6567
6568 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6569 tex.sampler_index_mode = sampler_index_mode;
6570 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6571 tex.resource_index_mode = sampler_index_mode;
6572 tex.src_gpr = src_gpr;
6573 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6574
6575 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
6576 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
6577 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
6578 }
6579
6580 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
6581 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
6582 tex.inst_mod = texture_component_select;
6583
6584 if (ctx->bc->chip_class == CAYMAN) {
6585 /* GATHER4 result order is different from TGSI TG4 */
6586 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
6587 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
6588 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
6589 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6590 } else {
6591 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6592 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6593 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6594 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6595 }
6596 }
6597 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
6598 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6599 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6600 tex.dst_sel_z = 7;
6601 tex.dst_sel_w = 7;
6602 }
6603 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
6604 tex.dst_sel_x = 3;
6605 tex.dst_sel_y = 7;
6606 tex.dst_sel_z = 7;
6607 tex.dst_sel_w = 7;
6608 }
6609 else {
6610 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6611 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6612 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6613 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6614 }
6615
6616
6617 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
6618 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
6619 tex.src_sel_x = 4;
6620 tex.src_sel_y = 4;
6621 tex.src_sel_z = 4;
6622 tex.src_sel_w = 4;
6623 } else if (src_loaded) {
6624 tex.src_sel_x = 0;
6625 tex.src_sel_y = 1;
6626 tex.src_sel_z = 2;
6627 tex.src_sel_w = 3;
6628 } else {
6629 tex.src_sel_x = ctx->src[0].swizzle[0];
6630 tex.src_sel_y = ctx->src[0].swizzle[1];
6631 tex.src_sel_z = ctx->src[0].swizzle[2];
6632 tex.src_sel_w = ctx->src[0].swizzle[3];
6633 tex.src_rel = ctx->src[0].rel;
6634 }
6635
6636 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6637 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6638 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6639 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6640 tex.src_sel_x = 1;
6641 tex.src_sel_y = 0;
6642 tex.src_sel_z = 3;
6643 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
6644 }
6645
6646 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
6647 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
6648 tex.coord_type_x = 1;
6649 tex.coord_type_y = 1;
6650 }
6651 tex.coord_type_z = 1;
6652 tex.coord_type_w = 1;
6653
6654 tex.offset_x = offset_x;
6655 tex.offset_y = offset_y;
6656 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
6657 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6658 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
6659 tex.offset_z = 0;
6660 }
6661 else {
6662 tex.offset_z = offset_z;
6663 }
6664
6665 /* Put the depth for comparison in W.
6666 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
6667 * Some instructions expect the depth in Z. */
6668 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6669 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6670 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6671 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
6672 opcode != FETCH_OP_SAMPLE_C_L &&
6673 opcode != FETCH_OP_SAMPLE_C_LB) {
6674 tex.src_sel_w = tex.src_sel_z;
6675 }
6676
6677 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
6678 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
6679 if (opcode == FETCH_OP_SAMPLE_C_L ||
6680 opcode == FETCH_OP_SAMPLE_C_LB) {
6681 /* the array index is read from Y */
6682 tex.coord_type_y = 0;
6683 } else {
6684 /* the array index is read from Z */
6685 tex.coord_type_z = 0;
6686 tex.src_sel_z = tex.src_sel_y;
6687 }
6688 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6689 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6690 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6691 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6692 (ctx->bc->chip_class >= EVERGREEN)))
6693 /* the array index is read from Z */
6694 tex.coord_type_z = 0;
6695
6696 /* mask unused source components */
6697 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
6698 switch (inst->Texture.Texture) {
6699 case TGSI_TEXTURE_2D:
6700 case TGSI_TEXTURE_RECT:
6701 tex.src_sel_z = 7;
6702 tex.src_sel_w = 7;
6703 break;
6704 case TGSI_TEXTURE_1D_ARRAY:
6705 tex.src_sel_y = 7;
6706 tex.src_sel_w = 7;
6707 break;
6708 case TGSI_TEXTURE_1D:
6709 tex.src_sel_y = 7;
6710 tex.src_sel_z = 7;
6711 tex.src_sel_w = 7;
6712 break;
6713 }
6714 }
6715
6716 r = r600_bytecode_add_tex(ctx->bc, &tex);
6717 if (r)
6718 return r;
6719
6720 /* add shadow ambient support - gallium doesn't do it yet */
6721 return 0;
6722 }
6723
6724 static int tgsi_lrp(struct r600_shader_ctx *ctx)
6725 {
6726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6727 struct r600_bytecode_alu alu;
6728 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6729 unsigned i, temp_regs[2];
6730 int r;
6731
6732 /* optimize if it's just an equal balance */
6733 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
6734 for (i = 0; i < lasti + 1; i++) {
6735 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6736 continue;
6737
6738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6739 alu.op = ALU_OP2_ADD;
6740 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6741 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6742 alu.omod = 3;
6743 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6744 alu.dst.chan = i;
6745 if (i == lasti) {
6746 alu.last = 1;
6747 }
6748 r = r600_bytecode_add_alu(ctx->bc, &alu);
6749 if (r)
6750 return r;
6751 }
6752 return 0;
6753 }
6754
6755 /* 1 - src0 */
6756 for (i = 0; i < lasti + 1; i++) {
6757 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6758 continue;
6759
6760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6761 alu.op = ALU_OP2_ADD;
6762 alu.src[0].sel = V_SQ_ALU_SRC_1;
6763 alu.src[0].chan = 0;
6764 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6765 r600_bytecode_src_toggle_neg(&alu.src[1]);
6766 alu.dst.sel = ctx->temp_reg;
6767 alu.dst.chan = i;
6768 if (i == lasti) {
6769 alu.last = 1;
6770 }
6771 alu.dst.write = 1;
6772 r = r600_bytecode_add_alu(ctx->bc, &alu);
6773 if (r)
6774 return r;
6775 }
6776
6777 /* (1 - src0) * src2 */
6778 for (i = 0; i < lasti + 1; i++) {
6779 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6780 continue;
6781
6782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6783 alu.op = ALU_OP2_MUL;
6784 alu.src[0].sel = ctx->temp_reg;
6785 alu.src[0].chan = i;
6786 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6787 alu.dst.sel = ctx->temp_reg;
6788 alu.dst.chan = i;
6789 if (i == lasti) {
6790 alu.last = 1;
6791 }
6792 alu.dst.write = 1;
6793 r = r600_bytecode_add_alu(ctx->bc, &alu);
6794 if (r)
6795 return r;
6796 }
6797
6798 /* src0 * src1 + (1 - src0) * src2 */
6799 if (ctx->src[0].abs)
6800 temp_regs[0] = r600_get_temp(ctx);
6801 else
6802 temp_regs[0] = 0;
6803 if (ctx->src[1].abs)
6804 temp_regs[1] = r600_get_temp(ctx);
6805 else
6806 temp_regs[1] = 0;
6807
6808 for (i = 0; i < lasti + 1; i++) {
6809 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6810 continue;
6811
6812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6813 alu.op = ALU_OP3_MULADD;
6814 alu.is_op3 = 1;
6815 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6816 if (r)
6817 return r;
6818 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
6819 if (r)
6820 return r;
6821 alu.src[2].sel = ctx->temp_reg;
6822 alu.src[2].chan = i;
6823
6824 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6825 alu.dst.chan = i;
6826 if (i == lasti) {
6827 alu.last = 1;
6828 }
6829 r = r600_bytecode_add_alu(ctx->bc, &alu);
6830 if (r)
6831 return r;
6832 }
6833 return 0;
6834 }
6835
6836 static int tgsi_cmp(struct r600_shader_ctx *ctx)
6837 {
6838 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6839 struct r600_bytecode_alu alu;
6840 int i, r, j;
6841 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6842 int temp_regs[3];
6843
6844 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6845 temp_regs[j] = 0;
6846 if (ctx->src[j].abs)
6847 temp_regs[j] = r600_get_temp(ctx);
6848 }
6849
6850 for (i = 0; i < lasti + 1; i++) {
6851 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6852 continue;
6853
6854 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6855 alu.op = ALU_OP3_CNDGE;
6856 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6857 if (r)
6858 return r;
6859 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
6860 if (r)
6861 return r;
6862 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
6863 if (r)
6864 return r;
6865 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6866 alu.dst.chan = i;
6867 alu.dst.write = 1;
6868 alu.is_op3 = 1;
6869 if (i == lasti)
6870 alu.last = 1;
6871 r = r600_bytecode_add_alu(ctx->bc, &alu);
6872 if (r)
6873 return r;
6874 }
6875 return 0;
6876 }
6877
6878 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
6879 {
6880 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6881 struct r600_bytecode_alu alu;
6882 int i, r;
6883 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6884
6885 for (i = 0; i < lasti + 1; i++) {
6886 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6887 continue;
6888
6889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6890 alu.op = ALU_OP3_CNDE_INT;
6891 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6892 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6893 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6894 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6895 alu.dst.chan = i;
6896 alu.dst.write = 1;
6897 alu.is_op3 = 1;
6898 if (i == lasti)
6899 alu.last = 1;
6900 r = r600_bytecode_add_alu(ctx->bc, &alu);
6901 if (r)
6902 return r;
6903 }
6904 return 0;
6905 }
6906
6907 static int tgsi_xpd(struct r600_shader_ctx *ctx)
6908 {
6909 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6910 static const unsigned int src0_swizzle[] = {2, 0, 1};
6911 static const unsigned int src1_swizzle[] = {1, 2, 0};
6912 struct r600_bytecode_alu alu;
6913 uint32_t use_temp = 0;
6914 int i, r;
6915
6916 if (inst->Dst[0].Register.WriteMask != 0xf)
6917 use_temp = 1;
6918
6919 for (i = 0; i < 4; i++) {
6920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6921 alu.op = ALU_OP2_MUL;
6922 if (i < 3) {
6923 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6924 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
6925 } else {
6926 alu.src[0].sel = V_SQ_ALU_SRC_0;
6927 alu.src[0].chan = i;
6928 alu.src[1].sel = V_SQ_ALU_SRC_0;
6929 alu.src[1].chan = i;
6930 }
6931
6932 alu.dst.sel = ctx->temp_reg;
6933 alu.dst.chan = i;
6934 alu.dst.write = 1;
6935
6936 if (i == 3)
6937 alu.last = 1;
6938 r = r600_bytecode_add_alu(ctx->bc, &alu);
6939 if (r)
6940 return r;
6941 }
6942
6943 for (i = 0; i < 4; i++) {
6944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6945 alu.op = ALU_OP3_MULADD;
6946
6947 if (i < 3) {
6948 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
6949 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
6950 } else {
6951 alu.src[0].sel = V_SQ_ALU_SRC_0;
6952 alu.src[0].chan = i;
6953 alu.src[1].sel = V_SQ_ALU_SRC_0;
6954 alu.src[1].chan = i;
6955 }
6956
6957 alu.src[2].sel = ctx->temp_reg;
6958 alu.src[2].neg = 1;
6959 alu.src[2].chan = i;
6960
6961 if (use_temp)
6962 alu.dst.sel = ctx->temp_reg;
6963 else
6964 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6965 alu.dst.chan = i;
6966 alu.dst.write = 1;
6967 alu.is_op3 = 1;
6968 if (i == 3)
6969 alu.last = 1;
6970 r = r600_bytecode_add_alu(ctx->bc, &alu);
6971 if (r)
6972 return r;
6973 }
6974 if (use_temp)
6975 return tgsi_helper_copy(ctx, inst);
6976 return 0;
6977 }
6978
6979 static int tgsi_exp(struct r600_shader_ctx *ctx)
6980 {
6981 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6982 struct r600_bytecode_alu alu;
6983 int r;
6984 int i;
6985
6986 /* result.x = 2^floor(src); */
6987 if (inst->Dst[0].Register.WriteMask & 1) {
6988 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6989
6990 alu.op = ALU_OP1_FLOOR;
6991 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6992
6993 alu.dst.sel = ctx->temp_reg;
6994 alu.dst.chan = 0;
6995 alu.dst.write = 1;
6996 alu.last = 1;
6997 r = r600_bytecode_add_alu(ctx->bc, &alu);
6998 if (r)
6999 return r;
7000
7001 if (ctx->bc->chip_class == CAYMAN) {
7002 for (i = 0; i < 3; i++) {
7003 alu.op = ALU_OP1_EXP_IEEE;
7004 alu.src[0].sel = ctx->temp_reg;
7005 alu.src[0].chan = 0;
7006
7007 alu.dst.sel = ctx->temp_reg;
7008 alu.dst.chan = i;
7009 alu.dst.write = i == 0;
7010 alu.last = i == 2;
7011 r = r600_bytecode_add_alu(ctx->bc, &alu);
7012 if (r)
7013 return r;
7014 }
7015 } else {
7016 alu.op = ALU_OP1_EXP_IEEE;
7017 alu.src[0].sel = ctx->temp_reg;
7018 alu.src[0].chan = 0;
7019
7020 alu.dst.sel = ctx->temp_reg;
7021 alu.dst.chan = 0;
7022 alu.dst.write = 1;
7023 alu.last = 1;
7024 r = r600_bytecode_add_alu(ctx->bc, &alu);
7025 if (r)
7026 return r;
7027 }
7028 }
7029
7030 /* result.y = tmp - floor(tmp); */
7031 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7032 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7033
7034 alu.op = ALU_OP1_FRACT;
7035 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7036
7037 alu.dst.sel = ctx->temp_reg;
7038 #if 0
7039 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7040 if (r)
7041 return r;
7042 #endif
7043 alu.dst.write = 1;
7044 alu.dst.chan = 1;
7045
7046 alu.last = 1;
7047
7048 r = r600_bytecode_add_alu(ctx->bc, &alu);
7049 if (r)
7050 return r;
7051 }
7052
7053 /* result.z = RoughApprox2ToX(tmp);*/
7054 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
7055 if (ctx->bc->chip_class == CAYMAN) {
7056 for (i = 0; i < 3; i++) {
7057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7058 alu.op = ALU_OP1_EXP_IEEE;
7059 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7060
7061 alu.dst.sel = ctx->temp_reg;
7062 alu.dst.chan = i;
7063 if (i == 2) {
7064 alu.dst.write = 1;
7065 alu.last = 1;
7066 }
7067
7068 r = r600_bytecode_add_alu(ctx->bc, &alu);
7069 if (r)
7070 return r;
7071 }
7072 } else {
7073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7074 alu.op = ALU_OP1_EXP_IEEE;
7075 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7076
7077 alu.dst.sel = ctx->temp_reg;
7078 alu.dst.write = 1;
7079 alu.dst.chan = 2;
7080
7081 alu.last = 1;
7082
7083 r = r600_bytecode_add_alu(ctx->bc, &alu);
7084 if (r)
7085 return r;
7086 }
7087 }
7088
7089 /* result.w = 1.0;*/
7090 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
7091 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7092
7093 alu.op = ALU_OP1_MOV;
7094 alu.src[0].sel = V_SQ_ALU_SRC_1;
7095 alu.src[0].chan = 0;
7096
7097 alu.dst.sel = ctx->temp_reg;
7098 alu.dst.chan = 3;
7099 alu.dst.write = 1;
7100 alu.last = 1;
7101 r = r600_bytecode_add_alu(ctx->bc, &alu);
7102 if (r)
7103 return r;
7104 }
7105 return tgsi_helper_copy(ctx, inst);
7106 }
7107
7108 static int tgsi_log(struct r600_shader_ctx *ctx)
7109 {
7110 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7111 struct r600_bytecode_alu alu;
7112 int r;
7113 int i;
7114
7115 /* result.x = floor(log2(|src|)); */
7116 if (inst->Dst[0].Register.WriteMask & 1) {
7117 if (ctx->bc->chip_class == CAYMAN) {
7118 for (i = 0; i < 3; i++) {
7119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7120
7121 alu.op = ALU_OP1_LOG_IEEE;
7122 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7123 r600_bytecode_src_set_abs(&alu.src[0]);
7124
7125 alu.dst.sel = ctx->temp_reg;
7126 alu.dst.chan = i;
7127 if (i == 0)
7128 alu.dst.write = 1;
7129 if (i == 2)
7130 alu.last = 1;
7131 r = r600_bytecode_add_alu(ctx->bc, &alu);
7132 if (r)
7133 return r;
7134 }
7135
7136 } else {
7137 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7138
7139 alu.op = ALU_OP1_LOG_IEEE;
7140 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7141 r600_bytecode_src_set_abs(&alu.src[0]);
7142
7143 alu.dst.sel = ctx->temp_reg;
7144 alu.dst.chan = 0;
7145 alu.dst.write = 1;
7146 alu.last = 1;
7147 r = r600_bytecode_add_alu(ctx->bc, &alu);
7148 if (r)
7149 return r;
7150 }
7151
7152 alu.op = ALU_OP1_FLOOR;
7153 alu.src[0].sel = ctx->temp_reg;
7154 alu.src[0].chan = 0;
7155
7156 alu.dst.sel = ctx->temp_reg;
7157 alu.dst.chan = 0;
7158 alu.dst.write = 1;
7159 alu.last = 1;
7160
7161 r = r600_bytecode_add_alu(ctx->bc, &alu);
7162 if (r)
7163 return r;
7164 }
7165
7166 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
7167 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7168
7169 if (ctx->bc->chip_class == CAYMAN) {
7170 for (i = 0; i < 3; i++) {
7171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7172
7173 alu.op = ALU_OP1_LOG_IEEE;
7174 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7175 r600_bytecode_src_set_abs(&alu.src[0]);
7176
7177 alu.dst.sel = ctx->temp_reg;
7178 alu.dst.chan = i;
7179 if (i == 1)
7180 alu.dst.write = 1;
7181 if (i == 2)
7182 alu.last = 1;
7183
7184 r = r600_bytecode_add_alu(ctx->bc, &alu);
7185 if (r)
7186 return r;
7187 }
7188 } else {
7189 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7190
7191 alu.op = ALU_OP1_LOG_IEEE;
7192 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7193 r600_bytecode_src_set_abs(&alu.src[0]);
7194
7195 alu.dst.sel = ctx->temp_reg;
7196 alu.dst.chan = 1;
7197 alu.dst.write = 1;
7198 alu.last = 1;
7199
7200 r = r600_bytecode_add_alu(ctx->bc, &alu);
7201 if (r)
7202 return r;
7203 }
7204
7205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7206
7207 alu.op = ALU_OP1_FLOOR;
7208 alu.src[0].sel = ctx->temp_reg;
7209 alu.src[0].chan = 1;
7210
7211 alu.dst.sel = ctx->temp_reg;
7212 alu.dst.chan = 1;
7213 alu.dst.write = 1;
7214 alu.last = 1;
7215
7216 r = r600_bytecode_add_alu(ctx->bc, &alu);
7217 if (r)
7218 return r;
7219
7220 if (ctx->bc->chip_class == CAYMAN) {
7221 for (i = 0; i < 3; i++) {
7222 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7223 alu.op = ALU_OP1_EXP_IEEE;
7224 alu.src[0].sel = ctx->temp_reg;
7225 alu.src[0].chan = 1;
7226
7227 alu.dst.sel = ctx->temp_reg;
7228 alu.dst.chan = i;
7229 if (i == 1)
7230 alu.dst.write = 1;
7231 if (i == 2)
7232 alu.last = 1;
7233
7234 r = r600_bytecode_add_alu(ctx->bc, &alu);
7235 if (r)
7236 return r;
7237 }
7238 } else {
7239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7240 alu.op = ALU_OP1_EXP_IEEE;
7241 alu.src[0].sel = ctx->temp_reg;
7242 alu.src[0].chan = 1;
7243
7244 alu.dst.sel = ctx->temp_reg;
7245 alu.dst.chan = 1;
7246 alu.dst.write = 1;
7247 alu.last = 1;
7248
7249 r = r600_bytecode_add_alu(ctx->bc, &alu);
7250 if (r)
7251 return r;
7252 }
7253
7254 if (ctx->bc->chip_class == CAYMAN) {
7255 for (i = 0; i < 3; i++) {
7256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7257 alu.op = ALU_OP1_RECIP_IEEE;
7258 alu.src[0].sel = ctx->temp_reg;
7259 alu.src[0].chan = 1;
7260
7261 alu.dst.sel = ctx->temp_reg;
7262 alu.dst.chan = i;
7263 if (i == 1)
7264 alu.dst.write = 1;
7265 if (i == 2)
7266 alu.last = 1;
7267
7268 r = r600_bytecode_add_alu(ctx->bc, &alu);
7269 if (r)
7270 return r;
7271 }
7272 } else {
7273 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7274 alu.op = ALU_OP1_RECIP_IEEE;
7275 alu.src[0].sel = ctx->temp_reg;
7276 alu.src[0].chan = 1;
7277
7278 alu.dst.sel = ctx->temp_reg;
7279 alu.dst.chan = 1;
7280 alu.dst.write = 1;
7281 alu.last = 1;
7282
7283 r = r600_bytecode_add_alu(ctx->bc, &alu);
7284 if (r)
7285 return r;
7286 }
7287
7288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7289
7290 alu.op = ALU_OP2_MUL;
7291
7292 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7293 r600_bytecode_src_set_abs(&alu.src[0]);
7294
7295 alu.src[1].sel = ctx->temp_reg;
7296 alu.src[1].chan = 1;
7297
7298 alu.dst.sel = ctx->temp_reg;
7299 alu.dst.chan = 1;
7300 alu.dst.write = 1;
7301 alu.last = 1;
7302
7303 r = r600_bytecode_add_alu(ctx->bc, &alu);
7304 if (r)
7305 return r;
7306 }
7307
7308 /* result.z = log2(|src|);*/
7309 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
7310 if (ctx->bc->chip_class == CAYMAN) {
7311 for (i = 0; i < 3; i++) {
7312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7313
7314 alu.op = ALU_OP1_LOG_IEEE;
7315 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7316 r600_bytecode_src_set_abs(&alu.src[0]);
7317
7318 alu.dst.sel = ctx->temp_reg;
7319 if (i == 2)
7320 alu.dst.write = 1;
7321 alu.dst.chan = i;
7322 if (i == 2)
7323 alu.last = 1;
7324
7325 r = r600_bytecode_add_alu(ctx->bc, &alu);
7326 if (r)
7327 return r;
7328 }
7329 } else {
7330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7331
7332 alu.op = ALU_OP1_LOG_IEEE;
7333 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7334 r600_bytecode_src_set_abs(&alu.src[0]);
7335
7336 alu.dst.sel = ctx->temp_reg;
7337 alu.dst.write = 1;
7338 alu.dst.chan = 2;
7339 alu.last = 1;
7340
7341 r = r600_bytecode_add_alu(ctx->bc, &alu);
7342 if (r)
7343 return r;
7344 }
7345 }
7346
7347 /* result.w = 1.0; */
7348 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
7349 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7350
7351 alu.op = ALU_OP1_MOV;
7352 alu.src[0].sel = V_SQ_ALU_SRC_1;
7353 alu.src[0].chan = 0;
7354
7355 alu.dst.sel = ctx->temp_reg;
7356 alu.dst.chan = 3;
7357 alu.dst.write = 1;
7358 alu.last = 1;
7359
7360 r = r600_bytecode_add_alu(ctx->bc, &alu);
7361 if (r)
7362 return r;
7363 }
7364
7365 return tgsi_helper_copy(ctx, inst);
7366 }
7367
7368 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
7369 {
7370 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7371 struct r600_bytecode_alu alu;
7372 int r;
7373 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7374 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
7375
7376 assert(inst->Dst[0].Register.Index < 3);
7377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7378
7379 switch (inst->Instruction.Opcode) {
7380 case TGSI_OPCODE_ARL:
7381 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
7382 break;
7383 case TGSI_OPCODE_ARR:
7384 alu.op = ALU_OP1_FLT_TO_INT;
7385 break;
7386 case TGSI_OPCODE_UARL:
7387 alu.op = ALU_OP1_MOV;
7388 break;
7389 default:
7390 assert(0);
7391 return -1;
7392 }
7393
7394 for (i = 0; i <= lasti; ++i) {
7395 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7396 continue;
7397 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7398 alu.last = i == lasti;
7399 alu.dst.sel = reg;
7400 alu.dst.chan = i;
7401 alu.dst.write = 1;
7402 r = r600_bytecode_add_alu(ctx->bc, &alu);
7403 if (r)
7404 return r;
7405 }
7406
7407 if (inst->Dst[0].Register.Index > 0)
7408 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
7409 else
7410 ctx->bc->ar_loaded = 0;
7411
7412 return 0;
7413 }
7414 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
7415 {
7416 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7417 struct r600_bytecode_alu alu;
7418 int r;
7419 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7420
7421 switch (inst->Instruction.Opcode) {
7422 case TGSI_OPCODE_ARL:
7423 memset(&alu, 0, sizeof(alu));
7424 alu.op = ALU_OP1_FLOOR;
7425 alu.dst.sel = ctx->bc->ar_reg;
7426 alu.dst.write = 1;
7427 for (i = 0; i <= lasti; ++i) {
7428 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7429 alu.dst.chan = i;
7430 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7431 alu.last = i == lasti;
7432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7433 return r;
7434 }
7435 }
7436
7437 memset(&alu, 0, sizeof(alu));
7438 alu.op = ALU_OP1_FLT_TO_INT;
7439 alu.src[0].sel = ctx->bc->ar_reg;
7440 alu.dst.sel = ctx->bc->ar_reg;
7441 alu.dst.write = 1;
7442 /* FLT_TO_INT is trans-only on r600/r700 */
7443 alu.last = TRUE;
7444 for (i = 0; i <= lasti; ++i) {
7445 alu.dst.chan = i;
7446 alu.src[0].chan = i;
7447 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7448 return r;
7449 }
7450 break;
7451 case TGSI_OPCODE_ARR:
7452 memset(&alu, 0, sizeof(alu));
7453 alu.op = ALU_OP1_FLT_TO_INT;
7454 alu.dst.sel = ctx->bc->ar_reg;
7455 alu.dst.write = 1;
7456 /* FLT_TO_INT is trans-only on r600/r700 */
7457 alu.last = TRUE;
7458 for (i = 0; i <= lasti; ++i) {
7459 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7460 alu.dst.chan = i;
7461 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7462 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7463 return r;
7464 }
7465 }
7466 break;
7467 case TGSI_OPCODE_UARL:
7468 memset(&alu, 0, sizeof(alu));
7469 alu.op = ALU_OP1_MOV;
7470 alu.dst.sel = ctx->bc->ar_reg;
7471 alu.dst.write = 1;
7472 for (i = 0; i <= lasti; ++i) {
7473 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7474 alu.dst.chan = i;
7475 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7476 alu.last = i == lasti;
7477 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7478 return r;
7479 }
7480 }
7481 break;
7482 default:
7483 assert(0);
7484 return -1;
7485 }
7486
7487 ctx->bc->ar_loaded = 0;
7488 return 0;
7489 }
7490
7491 static int tgsi_opdst(struct r600_shader_ctx *ctx)
7492 {
7493 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7494 struct r600_bytecode_alu alu;
7495 int i, r = 0;
7496
7497 for (i = 0; i < 4; i++) {
7498 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7499
7500 alu.op = ALU_OP2_MUL;
7501 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7502
7503 if (i == 0 || i == 3) {
7504 alu.src[0].sel = V_SQ_ALU_SRC_1;
7505 } else {
7506 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7507 }
7508
7509 if (i == 0 || i == 2) {
7510 alu.src[1].sel = V_SQ_ALU_SRC_1;
7511 } else {
7512 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
7513 }
7514 if (i == 3)
7515 alu.last = 1;
7516 r = r600_bytecode_add_alu(ctx->bc, &alu);
7517 if (r)
7518 return r;
7519 }
7520 return 0;
7521 }
7522
7523 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
7524 {
7525 struct r600_bytecode_alu alu;
7526 int r;
7527
7528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7529 alu.op = opcode;
7530 alu.execute_mask = 1;
7531 alu.update_pred = 1;
7532
7533 alu.dst.sel = ctx->temp_reg;
7534 alu.dst.write = 1;
7535 alu.dst.chan = 0;
7536
7537 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7538 alu.src[1].sel = V_SQ_ALU_SRC_0;
7539 alu.src[1].chan = 0;
7540
7541 alu.last = 1;
7542
7543 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
7544 if (r)
7545 return r;
7546 return 0;
7547 }
7548
7549 static int pops(struct r600_shader_ctx *ctx, int pops)
7550 {
7551 unsigned force_pop = ctx->bc->force_add_cf;
7552
7553 if (!force_pop) {
7554 int alu_pop = 3;
7555 if (ctx->bc->cf_last) {
7556 if (ctx->bc->cf_last->op == CF_OP_ALU)
7557 alu_pop = 0;
7558 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
7559 alu_pop = 1;
7560 }
7561 alu_pop += pops;
7562 if (alu_pop == 1) {
7563 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
7564 ctx->bc->force_add_cf = 1;
7565 } else if (alu_pop == 2) {
7566 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
7567 ctx->bc->force_add_cf = 1;
7568 } else {
7569 force_pop = 1;
7570 }
7571 }
7572
7573 if (force_pop) {
7574 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
7575 ctx->bc->cf_last->pop_count = pops;
7576 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7577 }
7578
7579 return 0;
7580 }
7581
7582 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
7583 unsigned reason)
7584 {
7585 struct r600_stack_info *stack = &ctx->bc->stack;
7586 unsigned elements, entries;
7587
7588 unsigned entry_size = stack->entry_size;
7589
7590 elements = (stack->loop + stack->push_wqm ) * entry_size;
7591 elements += stack->push;
7592
7593 switch (ctx->bc->chip_class) {
7594 case R600:
7595 case R700:
7596 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
7597 * the stack must be reserved to hold the current active/continue
7598 * masks */
7599 if (reason == FC_PUSH_VPM) {
7600 elements += 2;
7601 }
7602 break;
7603
7604 case CAYMAN:
7605 /* r9xx: any stack operation on empty stack consumes 2 additional
7606 * elements */
7607 elements += 2;
7608
7609 /* fallthrough */
7610 /* FIXME: do the two elements added above cover the cases for the
7611 * r8xx+ below? */
7612
7613 case EVERGREEN:
7614 /* r8xx+: 2 extra elements are not always required, but one extra
7615 * element must be added for each of the following cases:
7616 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
7617 * stack usage.
7618 * (Currently we don't use ALU_ELSE_AFTER.)
7619 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
7620 * PUSH instruction executed.
7621 *
7622 * NOTE: it seems we also need to reserve additional element in some
7623 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
7624 * then STACK_SIZE should be 2 instead of 1 */
7625 if (reason == FC_PUSH_VPM) {
7626 elements += 1;
7627 }
7628 break;
7629
7630 default:
7631 assert(0);
7632 break;
7633 }
7634
7635 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
7636 * for all chips, so we use 4 in the final formula, not the real entry_size
7637 * for the chip */
7638 entry_size = 4;
7639
7640 entries = (elements + (entry_size - 1)) / entry_size;
7641
7642 if (entries > stack->max_entries)
7643 stack->max_entries = entries;
7644 }
7645
7646 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
7647 {
7648 switch(reason) {
7649 case FC_PUSH_VPM:
7650 --ctx->bc->stack.push;
7651 assert(ctx->bc->stack.push >= 0);
7652 break;
7653 case FC_PUSH_WQM:
7654 --ctx->bc->stack.push_wqm;
7655 assert(ctx->bc->stack.push_wqm >= 0);
7656 break;
7657 case FC_LOOP:
7658 --ctx->bc->stack.loop;
7659 assert(ctx->bc->stack.loop >= 0);
7660 break;
7661 default:
7662 assert(0);
7663 break;
7664 }
7665 }
7666
7667 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
7668 {
7669 switch (reason) {
7670 case FC_PUSH_VPM:
7671 ++ctx->bc->stack.push;
7672 break;
7673 case FC_PUSH_WQM:
7674 ++ctx->bc->stack.push_wqm;
7675 case FC_LOOP:
7676 ++ctx->bc->stack.loop;
7677 break;
7678 default:
7679 assert(0);
7680 }
7681
7682 callstack_update_max_depth(ctx, reason);
7683 }
7684
7685 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
7686 {
7687 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
7688
7689 sp->mid = realloc((void *)sp->mid,
7690 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
7691 sp->mid[sp->num_mid] = ctx->bc->cf_last;
7692 sp->num_mid++;
7693 }
7694
7695 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
7696 {
7697 ctx->bc->fc_sp++;
7698 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
7699 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
7700 }
7701
7702 static void fc_poplevel(struct r600_shader_ctx *ctx)
7703 {
7704 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
7705 free(sp->mid);
7706 sp->mid = NULL;
7707 sp->num_mid = 0;
7708 sp->start = NULL;
7709 sp->type = 0;
7710 ctx->bc->fc_sp--;
7711 }
7712
7713 #if 0
7714 static int emit_return(struct r600_shader_ctx *ctx)
7715 {
7716 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
7717 return 0;
7718 }
7719
7720 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
7721 {
7722
7723 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
7724 ctx->bc->cf_last->pop_count = pops;
7725 /* XXX work out offset */
7726 return 0;
7727 }
7728
7729 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
7730 {
7731 return 0;
7732 }
7733
7734 static void emit_testflag(struct r600_shader_ctx *ctx)
7735 {
7736
7737 }
7738
7739 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
7740 {
7741 emit_testflag(ctx);
7742 emit_jump_to_offset(ctx, 1, 4);
7743 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
7744 pops(ctx, ifidx + 1);
7745 emit_return(ctx);
7746 }
7747
7748 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
7749 {
7750 emit_testflag(ctx);
7751
7752 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7753 ctx->bc->cf_last->pop_count = 1;
7754
7755 fc_set_mid(ctx, fc_sp);
7756
7757 pops(ctx, 1);
7758 }
7759 #endif
7760
7761 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
7762 {
7763 int alu_type = CF_OP_ALU_PUSH_BEFORE;
7764
7765 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
7766 * LOOP_STARTxxx for nested loops may put the branch stack into a state
7767 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
7768 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
7769 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
7770 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
7771 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7772 alu_type = CF_OP_ALU;
7773 }
7774
7775 emit_logic_pred(ctx, opcode, alu_type);
7776
7777 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
7778
7779 fc_pushlevel(ctx, FC_IF);
7780
7781 callstack_push(ctx, FC_PUSH_VPM);
7782 return 0;
7783 }
7784
7785 static int tgsi_if(struct r600_shader_ctx *ctx)
7786 {
7787 return emit_if(ctx, ALU_OP2_PRED_SETNE);
7788 }
7789
7790 static int tgsi_uif(struct r600_shader_ctx *ctx)
7791 {
7792 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
7793 }
7794
7795 static int tgsi_else(struct r600_shader_ctx *ctx)
7796 {
7797 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
7798 ctx->bc->cf_last->pop_count = 1;
7799
7800 fc_set_mid(ctx, ctx->bc->fc_sp);
7801 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
7802 return 0;
7803 }
7804
7805 static int tgsi_endif(struct r600_shader_ctx *ctx)
7806 {
7807 pops(ctx, 1);
7808 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
7809 R600_ERR("if/endif unbalanced in shader\n");
7810 return -1;
7811 }
7812
7813 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
7814 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7815 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
7816 } else {
7817 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
7818 }
7819 fc_poplevel(ctx);
7820
7821 callstack_pop(ctx, FC_PUSH_VPM);
7822 return 0;
7823 }
7824
7825 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
7826 {
7827 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
7828 * limited to 4096 iterations, like the other LOOP_* instructions. */
7829 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
7830
7831 fc_pushlevel(ctx, FC_LOOP);
7832
7833 /* check stack depth */
7834 callstack_push(ctx, FC_LOOP);
7835 return 0;
7836 }
7837
7838 static int tgsi_endloop(struct r600_shader_ctx *ctx)
7839 {
7840 int i;
7841
7842 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
7843
7844 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
7845 R600_ERR("loop/endloop in shader code are not paired.\n");
7846 return -EINVAL;
7847 }
7848
7849 /* fixup loop pointers - from r600isa
7850 LOOP END points to CF after LOOP START,
7851 LOOP START point to CF after LOOP END
7852 BRK/CONT point to LOOP END CF
7853 */
7854 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
7855
7856 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7857
7858 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
7859 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
7860 }
7861 /* XXX add LOOPRET support */
7862 fc_poplevel(ctx);
7863 callstack_pop(ctx, FC_LOOP);
7864 return 0;
7865 }
7866
7867 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
7868 {
7869 int r;
7870 unsigned int fscp;
7871
7872 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7873 {
7874 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7875 break;
7876 }
7877 if (fscp == 0) {
7878 R600_ERR("BREAKC not inside loop/endloop pair\n");
7879 return -EINVAL;
7880 }
7881
7882 if (ctx->bc->chip_class == EVERGREEN &&
7883 ctx->bc->family != CHIP_CYPRESS &&
7884 ctx->bc->family != CHIP_JUNIPER) {
7885 /* HW bug: ALU_BREAK does not save the active mask correctly */
7886 r = tgsi_uif(ctx);
7887 if (r)
7888 return r;
7889
7890 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
7891 if (r)
7892 return r;
7893 fc_set_mid(ctx, fscp);
7894
7895 return tgsi_endif(ctx);
7896 } else {
7897 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
7898 if (r)
7899 return r;
7900 fc_set_mid(ctx, fscp);
7901 }
7902
7903 return 0;
7904 }
7905
7906 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
7907 {
7908 unsigned int fscp;
7909
7910 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7911 {
7912 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7913 break;
7914 }
7915
7916 if (fscp == 0) {
7917 R600_ERR("Break not inside loop/endloop pair\n");
7918 return -EINVAL;
7919 }
7920
7921 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7922
7923 fc_set_mid(ctx, fscp);
7924
7925 return 0;
7926 }
7927
7928 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
7929 {
7930 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7931 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
7932 int r;
7933
7934 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
7935 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
7936
7937 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7938 if (!r) {
7939 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
7940 return emit_inc_ring_offset(ctx, stream, TRUE);
7941 }
7942 return r;
7943 }
7944
7945 static int tgsi_umad(struct r600_shader_ctx *ctx)
7946 {
7947 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7948 struct r600_bytecode_alu alu;
7949 int i, j, k, r;
7950 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7951
7952 /* src0 * src1 */
7953 for (i = 0; i < lasti + 1; i++) {
7954 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7955 continue;
7956
7957 if (ctx->bc->chip_class == CAYMAN) {
7958 for (j = 0 ; j < 4; j++) {
7959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7960
7961 alu.op = ALU_OP2_MULLO_UINT;
7962 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
7963 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
7964 }
7965 alu.dst.chan = j;
7966 alu.dst.sel = ctx->temp_reg;
7967 alu.dst.write = (j == i);
7968 if (j == 3)
7969 alu.last = 1;
7970 r = r600_bytecode_add_alu(ctx->bc, &alu);
7971 if (r)
7972 return r;
7973 }
7974 } else {
7975 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7976
7977 alu.dst.chan = i;
7978 alu.dst.sel = ctx->temp_reg;
7979 alu.dst.write = 1;
7980
7981 alu.op = ALU_OP2_MULLO_UINT;
7982 for (j = 0; j < 2; j++) {
7983 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
7984 }
7985
7986 alu.last = 1;
7987 r = r600_bytecode_add_alu(ctx->bc, &alu);
7988 if (r)
7989 return r;
7990 }
7991 }
7992
7993
7994 for (i = 0; i < lasti + 1; i++) {
7995 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7996 continue;
7997
7998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7999 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8000
8001 alu.op = ALU_OP2_ADD_INT;
8002
8003 alu.src[0].sel = ctx->temp_reg;
8004 alu.src[0].chan = i;
8005
8006 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8007 if (i == lasti) {
8008 alu.last = 1;
8009 }
8010 r = r600_bytecode_add_alu(ctx->bc, &alu);
8011 if (r)
8012 return r;
8013 }
8014 return 0;
8015 }
8016
8017 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
8018 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
8019 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8020 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8021
8022 /* XXX:
8023 * For state trackers other than OpenGL, we'll want to use
8024 * _RECIP_IEEE instead.
8025 */
8026 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
8027
8028 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
8029 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8030 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8031 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8032 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8033 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8034 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8035 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8036 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8037 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8038 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8039 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8040 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8041 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8042 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8043 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8044 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
8045 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8046 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8047 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8048 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8049 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8050 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8051 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8052 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
8053 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
8054 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
8055 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8056 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8057 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8058 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8059 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8060 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
8061 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8062 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8063 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8064 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8065 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8066 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8067 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8068 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8069 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8070 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8071 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8072 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
8073 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8074 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8075 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8076 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8077 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8078 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8079 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8080 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8081 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8082 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8083 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8084 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8085 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
8086 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8087 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8088 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8089 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8090 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8091 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8092 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8093 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8094 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8095 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8096 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8097 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8098 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8099 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8100 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8101 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8102 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8103 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
8104 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
8105 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8106 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8107 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8108 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
8109 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8110 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8111 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
8112 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8113 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8114 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8115 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8116 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8117 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8118 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8119 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8120 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8121 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8122 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8123 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8124 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8125 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8126 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8127 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8128 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8129 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8130 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8131 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8132 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8133 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8134 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8135 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8136 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8137 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8138 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8139 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
8140 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8141 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8142 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8143 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
8144 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8145 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8146 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8147 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8148 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8149 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
8150 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8151 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
8152 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
8153 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8154 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8155 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8156 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8157 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8158 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8159 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
8160 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8161 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8162 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
8163 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8164 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
8165 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8166 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8167 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8168 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8169 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8170 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8171 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8172 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8173 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8174 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8175 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8176 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8177 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8178 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8179 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8180 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8181 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
8182 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8183 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8184 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8185 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8186 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8187 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8188 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8189 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8190 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8191 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8192 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8193 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8194 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8195 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8196 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8197 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8198 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8199 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8200 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8201 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8202 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8203 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8204 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
8205 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
8206 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
8207 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
8208 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
8209 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
8210 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
8211 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
8212 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
8213 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
8214 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
8215 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
8216 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
8217 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
8218 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
8219 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8220 };
8221
8222 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
8223 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
8224 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8225 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8226 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
8227 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
8228 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8229 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8230 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8231 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8232 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8233 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8234 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8235 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8236 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8237 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8238 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8239 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8240 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8241 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8242 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8243 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
8244 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8245 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8246 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8247 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8248 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8249 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8250 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8251 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
8252 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
8253 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
8254 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8255 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8256 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8257 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8258 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8259 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
8260 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8261 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8262 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8263 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8264 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8265 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8266 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8267 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8268 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8269 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8270 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8271 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
8272 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8273 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8274 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8275 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8276 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8277 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8278 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8279 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8280 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8281 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8282 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8283 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8284 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
8285 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8286 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8287 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8288 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8289 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8290 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8291 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8292 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8293 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8294 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8295 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8296 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8297 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8298 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8299 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8300 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8301 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8302 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8303 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8304 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8305 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8306 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8307 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
8308 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8309 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8310 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8311 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8312 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8313 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8314 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8315 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8316 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8317 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8318 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8319 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8320 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8321 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8322 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8323 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8324 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8325 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8326 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8327 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8328 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8329 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8330 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8331 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8332 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8333 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8334 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8335 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8336 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8337 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8338 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8339 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8340 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8341 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8342 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
8343 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8344 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8345 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8346 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8347 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8348 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8349 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8350 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
8351 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
8352 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8353 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8354 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8355 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8356 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8357 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8358 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
8359 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8360 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8361 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8362 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8363 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8364 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8365 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8366 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8367 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8368 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8369 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8370 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8371 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8372 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8373 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8374 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8375 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8376 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8377 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8378 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8379 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8380 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8381 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8382 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8383 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8384 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8385 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8386 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8387 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8388 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8389 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8390 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8391 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8392 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8393 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8394 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8395 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8396 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8397 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8398 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8399 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8400 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8401 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8402 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8403 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
8404 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
8405 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8406 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8407 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8408 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8409 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8410 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8411 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8412 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8413 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8414 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8415 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8416 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8417 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8418 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8419 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8420 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8421 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8422 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8423 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8424 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8425 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8426 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8427 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8428 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8429 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8430 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8431 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8432 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8433 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8434 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8435 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8436 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
8437 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
8438 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
8439 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
8440 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8441 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8442 };
8443
8444 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
8445 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
8446 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8447 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8448 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
8449 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
8450 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8451 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8452 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8453 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8454 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8455 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8456 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8457 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8458 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8459 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8460 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8461 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8462 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8463 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8464 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8465 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
8466 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8467 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8468 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8469 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8470 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8471 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8472 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8473 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
8474 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
8475 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
8476 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8477 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8478 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8479 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8480 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8481 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
8482 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8483 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8484 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8485 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8486 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8487 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8488 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8489 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8490 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8491 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8492 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8493 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
8494 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8495 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8496 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8497 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8498 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8499 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8500 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8501 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8502 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8503 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8504 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8505 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8506 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
8507 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8508 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8509 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8510 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8511 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8512 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8513 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8514 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8515 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8516 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8517 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8518 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8519 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8520 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8521 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8522 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8523 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8524 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8525 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8526 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8527 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8528 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8529 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
8530 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8531 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8532 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8533 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8534 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8535 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8536 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8537 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8538 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8539 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8540 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8541 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8542 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8543 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8544 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8545 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8546 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8547 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8548 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8549 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8550 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8551 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8552 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8553 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8554 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8555 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8556 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8557 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8558 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8559 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8560 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8561 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8562 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8563 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8564 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
8565 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8566 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8567 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8568 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8569 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8570 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8571 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8572 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
8573 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
8574 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8575 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8576 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8577 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8578 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8579 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8580 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
8581 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8582 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8583 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8584 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8585 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8586 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8587 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8588 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8589 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8590 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8591 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8592 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8593 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8594 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8595 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8596 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8597 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8598 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8599 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8600 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8601 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8602 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8603 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8604 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8605 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8606 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8607 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8608 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8609 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8610 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8611 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8612 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8613 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8614 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8615 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8616 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8617 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8618 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8619 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8620 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8621 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8622 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8623 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8624 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8625 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
8626 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
8627 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8628 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8629 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8630 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8631 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8632 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8633 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8634 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8635 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8636 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8637 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8638 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8639 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8640 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8641 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8642 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8643 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8644 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8645 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8646 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8647 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8648 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8649 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8650 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8651 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8652 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8653 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8654 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8655 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8656 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8657 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8658 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
8659 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
8660 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
8661 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
8662 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8663 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8664 };