2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
31 #include "r600_opcodes.h"
36 static void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
38 struct r600_pipe_state
*rstate
= &shader
->rstate
;
39 struct r600_shader
*rshader
= &shader
->shader
;
40 unsigned spi_vs_out_id
[10];
43 /* clear previous register */
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
50 for (i
= 0; i
< 10; i
++) {
53 for (i
= 0; i
< 32; i
++) {
54 tmp
= i
<< ((i
& 3) * 8);
55 spi_vs_out_id
[i
/ 4] |= tmp
;
57 for (i
= 0; i
< 10; i
++) {
58 r600_pipe_state_add_reg(rstate
,
59 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
60 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
);
63 r600_pipe_state_add_reg(rstate
,
64 R_0286C4_SPI_VS_OUT_CONFIG
,
65 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2),
67 r600_pipe_state_add_reg(rstate
,
68 R_028868_SQ_PGM_RESOURCES_VS
,
69 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
70 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
72 r600_pipe_state_add_reg(rstate
,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS
,
74 0x00000000, 0xFFFFFFFF, NULL
);
75 r600_pipe_state_add_reg(rstate
,
76 R_028858_SQ_PGM_START_VS
,
77 r600_bo_offset(shader
->bo
) >> 8, 0xFFFFFFFF, shader
->bo
);
79 r600_pipe_state_add_reg(rstate
,
80 R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF,
85 int r600_find_vs_semantic_index(struct r600_shader
*vs
,
86 struct r600_shader
*ps
, int id
)
88 struct r600_shader_io
*input
= &ps
->input
[id
];
90 for (int i
= 0; i
< vs
->noutput
; i
++) {
91 if (input
->name
== vs
->output
[i
].name
&&
92 input
->sid
== vs
->output
[i
].sid
) {
99 static void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
101 struct r600_pipe_state
*rstate
= &shader
->rstate
;
102 struct r600_shader
*rshader
= &shader
->shader
;
103 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
;
104 int pos_index
= -1, face_index
= -1;
108 for (i
= 0; i
< rshader
->ninput
; i
++) {
109 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
111 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
115 for (i
= 0; i
< rshader
->noutput
; i
++) {
116 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
117 r600_pipe_state_add_reg(rstate
,
118 R_02880C_DB_SHADER_CONTROL
,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL
);
121 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
122 r600_pipe_state_add_reg(rstate
,
123 R_02880C_DB_SHADER_CONTROL
,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL
);
130 for (i
= 0; i
< rshader
->noutput
; i
++) {
131 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
|| rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
133 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
137 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
139 /* always at least export 1 component per pixel */
143 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
146 if (pos_index
!= -1) {
147 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
149 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
154 spi_ps_in_control_1
= 0;
155 if (face_index
!= -1) {
156 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
160 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
, 0xFFFFFFFF, NULL
);
161 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
, 0xFFFFFFFF, NULL
);
162 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
);
163 r600_pipe_state_add_reg(rstate
,
164 R_028840_SQ_PGM_START_PS
,
165 r600_bo_offset(shader
->bo
) >> 8, 0xFFFFFFFF, shader
->bo
);
166 r600_pipe_state_add_reg(rstate
,
167 R_028850_SQ_PGM_RESOURCES_PS
,
168 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
169 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
171 r600_pipe_state_add_reg(rstate
,
172 R_028854_SQ_PGM_EXPORTS_PS
,
173 exports_ps
, 0xFFFFFFFF, NULL
);
174 r600_pipe_state_add_reg(rstate
,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS
,
176 0x00000000, 0xFFFFFFFF, NULL
);
178 if (rshader
->uses_kill
) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate
,
181 R_02880C_DB_SHADER_CONTROL
,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL
);
185 r600_pipe_state_add_reg(rstate
,
186 R_03E200_SQ_LOOP_CONST_0
, 0x01000FFF,
190 int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
192 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
193 struct r600_shader
*rshader
= &shader
->shader
;
196 /* copy new shader */
197 if (shader
->bo
== NULL
) {
198 shader
->bo
= r600_bo(rctx
->radeon
, rshader
->bc
.ndw
* 4, 4096, 0, 0);
199 if (shader
->bo
== NULL
) {
202 ptr
= r600_bo_map(rctx
->radeon
, shader
->bo
, 0, NULL
);
203 memcpy(ptr
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
204 r600_bo_unmap(rctx
->radeon
, shader
->bo
);
207 switch (rshader
->processor_type
) {
208 case TGSI_PROCESSOR_VERTEX
:
209 if (rshader
->family
>= CHIP_CEDAR
) {
210 evergreen_pipe_shader_vs(ctx
, shader
);
212 r600_pipe_shader_vs(ctx
, shader
);
215 case TGSI_PROCESSOR_FRAGMENT
:
216 if (rshader
->family
>= CHIP_CEDAR
) {
217 evergreen_pipe_shader_ps(ctx
, shader
);
219 r600_pipe_shader_ps(ctx
, shader
);
228 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
229 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
, const struct tgsi_token
*tokens
)
231 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
234 //fprintf(stderr, "--------------------------------------------------------------\n");
235 //tgsi_dump(tokens, 0);
236 shader
->shader
.family
= r600_get_family(rctx
->radeon
);
237 r
= r600_shader_from_tgsi(tokens
, &shader
->shader
);
239 R600_ERR("translation from TGSI failed !\n");
242 r
= r600_bc_build(&shader
->shader
.bc
);
244 R600_ERR("building bytecode failed !\n");
247 //r600_bc_dump(&shader->shader.bc);
248 //fprintf(stderr, "______________________________________________________________\n");
249 return r600_pipe_shader(ctx
, shader
);
252 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
254 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
256 r600_bo_reference(rctx
->radeon
, &shader
->bo
, NULL
);
257 r600_bc_clear(&shader
->shader
.bc
);
261 * tgsi -> r600 shader
263 struct r600_shader_tgsi_instruction
;
265 struct r600_shader_ctx
{
266 struct tgsi_shader_info info
;
267 struct tgsi_parse_context parse
;
268 const struct tgsi_token
*tokens
;
270 unsigned file_offset
[TGSI_FILE_COUNT
];
272 struct r600_shader_tgsi_instruction
*inst_info
;
274 struct r600_shader
*shader
;
278 u32 max_driver_temp_used
;
279 /* needed for evergreen interpolation */
280 boolean input_centroid
;
281 boolean input_linear
;
282 boolean input_perspective
;
286 struct r600_shader_tgsi_instruction
{
287 unsigned tgsi_opcode
;
289 unsigned r600_opcode
;
290 int (*process
)(struct r600_shader_ctx
*ctx
);
293 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[];
294 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
296 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
298 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
301 if (i
->Instruction
.NumDstRegs
> 1) {
302 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
305 if (i
->Instruction
.Predicate
) {
306 R600_ERR("predicate unsupported\n");
310 if (i
->Instruction
.Label
) {
311 R600_ERR("label unsupported\n");
315 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
316 if (i
->Src
[j
].Register
.Dimension
) {
317 R600_ERR("unsupported src %d (dimension %d)\n", j
,
318 i
->Src
[j
].Register
.Dimension
);
322 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
323 if (i
->Dst
[j
].Register
.Dimension
) {
324 R600_ERR("unsupported dst (dimension)\n");
331 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
334 struct r600_bc_alu alu
;
335 int gpr
= 0, base_chan
= 0;
338 if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
) {
340 if (ctx
->shader
->input
[input
].centroid
)
342 } else if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
344 /* if we have perspective add one */
345 if (ctx
->input_perspective
) {
347 /* if we have perspective centroid */
348 if (ctx
->input_centroid
)
351 if (ctx
->shader
->input
[input
].centroid
)
355 /* work out gpr and base_chan from index */
357 base_chan
= (2 * (ij_index
% 2)) + 1;
359 for (i
= 0; i
< 8; i
++) {
360 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
363 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW
;
365 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY
;
367 if ((i
> 1) && (i
< 6)) {
368 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
372 alu
.dst
.chan
= i
% 4;
374 alu
.src
[0].sel
= gpr
;
375 alu
.src
[0].chan
= (base_chan
- (i
% 2));
377 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
379 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
382 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
390 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
392 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
395 switch (d
->Declaration
.File
) {
396 case TGSI_FILE_INPUT
:
397 i
= ctx
->shader
->ninput
++;
398 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
399 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
400 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
401 ctx
->shader
->input
[i
].centroid
= d
->Declaration
.Centroid
;
402 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
403 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
->bc
->chiprev
== CHIPREV_EVERGREEN
) {
404 /* turn input into interpolate on EG */
405 if (ctx
->shader
->input
[i
].name
!= TGSI_SEMANTIC_POSITION
) {
406 if (ctx
->shader
->input
[i
].interpolate
> 0) {
407 ctx
->shader
->input
[i
].lds_pos
= ctx
->shader
->nlds
++;
408 evergreen_interp_alu(ctx
, i
);
413 case TGSI_FILE_OUTPUT
:
414 i
= ctx
->shader
->noutput
++;
415 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
416 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
417 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
418 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
420 case TGSI_FILE_CONSTANT
:
421 case TGSI_FILE_TEMPORARY
:
422 case TGSI_FILE_SAMPLER
:
423 case TGSI_FILE_ADDRESS
:
426 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
432 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
434 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
438 * for evergreen we need to scan the shader to find the number of GPRs we need to
439 * reserve for interpolation.
441 * we need to know if we are going to emit
442 * any centroid inputs
443 * if perspective and linear are required
445 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
450 ctx
->input_linear
= FALSE
;
451 ctx
->input_perspective
= FALSE
;
452 ctx
->input_centroid
= FALSE
;
453 ctx
->num_interp_gpr
= 1;
455 /* any centroid inputs */
456 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
457 /* skip position/face */
458 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
459 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
)
461 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_LINEAR
)
462 ctx
->input_linear
= TRUE
;
463 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_PERSPECTIVE
)
464 ctx
->input_perspective
= TRUE
;
465 if (ctx
->info
.input_centroid
[i
])
466 ctx
->input_centroid
= TRUE
;
470 /* ignoring sample for now */
471 if (ctx
->input_perspective
)
473 if (ctx
->input_linear
)
475 if (ctx
->input_centroid
)
478 ctx
->num_interp_gpr
+= (num_baryc
+ 1) >> 1;
480 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
481 return ctx
->num_interp_gpr
;
484 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
486 struct tgsi_full_immediate
*immediate
;
487 struct r600_shader_ctx ctx
;
488 struct r600_bc_output output
[32];
489 unsigned output_done
, noutput
;
493 ctx
.bc
= &shader
->bc
;
495 r
= r600_bc_init(ctx
.bc
, shader
->family
);
499 tgsi_scan_shader(tokens
, &ctx
.info
);
500 tgsi_parse_init(&ctx
.parse
, tokens
);
501 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
502 shader
->processor_type
= ctx
.type
;
503 ctx
.bc
->type
= shader
->processor_type
;
505 /* register allocations */
506 /* Values [0,127] correspond to GPR[0..127].
507 * Values [128,159] correspond to constant buffer bank 0
508 * Values [160,191] correspond to constant buffer bank 1
509 * Values [256,511] correspond to cfile constants c[0..255].
510 * Other special values are shown in the list below.
511 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
512 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
513 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
514 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
515 * 248 SQ_ALU_SRC_0: special constant 0.0.
516 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
517 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
518 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
519 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
520 * 253 SQ_ALU_SRC_LITERAL: literal constant.
521 * 254 SQ_ALU_SRC_PV: previous vector result.
522 * 255 SQ_ALU_SRC_PS: previous scalar result.
524 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
525 ctx
.file_offset
[i
] = 0;
527 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
528 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
529 if (ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
) {
530 r600_bc_add_cfinst(ctx
.bc
, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
532 r600_bc_add_cfinst(ctx
.bc
, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
535 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
) {
536 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
538 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
539 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
540 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
541 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
543 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 128;
545 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
546 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
547 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
552 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
553 tgsi_parse_token(&ctx
.parse
);
554 switch (ctx
.parse
.FullToken
.Token
.Type
) {
555 case TGSI_TOKEN_TYPE_IMMEDIATE
:
556 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
557 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
558 if(ctx
.literals
== NULL
) {
562 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
563 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
564 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
565 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
568 case TGSI_TOKEN_TYPE_DECLARATION
:
569 r
= tgsi_declaration(&ctx
);
573 case TGSI_TOKEN_TYPE_INSTRUCTION
:
574 r
= tgsi_is_supported(&ctx
);
577 ctx
.max_driver_temp_used
= 0;
578 /* reserve first tmp for everyone */
580 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
581 if (ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
)
582 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
584 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
585 r
= ctx
.inst_info
->process(&ctx
);
588 r
= r600_bc_add_literal(ctx
.bc
, ctx
.value
);
593 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
599 noutput
= shader
->noutput
;
600 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
601 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
602 output
[i
].gpr
= shader
->output
[i
].gpr
;
603 output
[i
].elem_size
= 3;
604 output
[i
].swizzle_x
= 0;
605 output
[i
].swizzle_y
= 1;
606 output
[i
].swizzle_z
= 2;
607 output
[i
].swizzle_w
= 3;
608 output
[i
].barrier
= 1;
609 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
610 output
[i
].array_base
= i
- pos0
;
611 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
613 case TGSI_PROCESSOR_VERTEX
:
614 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
615 output
[i
].array_base
= 60;
616 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
617 /* position doesn't count in array_base */
620 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
621 output
[i
].array_base
= 61;
622 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
623 /* position doesn't count in array_base */
627 case TGSI_PROCESSOR_FRAGMENT
:
628 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
629 output
[i
].array_base
= shader
->output
[i
].sid
;
630 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
631 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
632 output
[i
].array_base
= 61;
633 output
[i
].swizzle_x
= 2;
634 output
[i
].swizzle_y
= 7;
635 output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
636 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
637 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
638 output
[i
].array_base
= 61;
639 output
[i
].swizzle_x
= 7;
640 output
[i
].swizzle_y
= 1;
641 output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
642 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
644 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
650 R600_ERR("unsupported processor type %d\n", ctx
.type
);
655 /* add fake param output for vertex shader if no param is exported */
656 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
657 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
658 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
664 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
666 output
[i
].elem_size
= 3;
667 output
[i
].swizzle_x
= 0;
668 output
[i
].swizzle_y
= 1;
669 output
[i
].swizzle_z
= 2;
670 output
[i
].swizzle_w
= 3;
671 output
[i
].barrier
= 1;
672 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
673 output
[i
].array_base
= 0;
674 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
678 /* add fake pixel export */
679 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
680 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
682 output
[0].elem_size
= 3;
683 output
[0].swizzle_x
= 7;
684 output
[0].swizzle_y
= 7;
685 output
[0].swizzle_z
= 7;
686 output
[0].swizzle_w
= 7;
687 output
[0].barrier
= 1;
688 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
689 output
[0].array_base
= 0;
690 output
[0].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
693 /* set export done on last export of each type */
694 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
695 if (i
== (noutput
- 1)) {
696 output
[i
].end_of_program
= 1;
698 if (!(output_done
& (1 << output
[i
].type
))) {
699 output_done
|= (1 << output
[i
].type
);
700 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
);
703 /* add output to bytecode */
704 for (i
= 0; i
< noutput
; i
++) {
705 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
710 tgsi_parse_free(&ctx
.parse
);
714 tgsi_parse_free(&ctx
.parse
);
718 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
720 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
724 static int tgsi_end(struct r600_shader_ctx
*ctx
)
729 static int tgsi_src(struct r600_shader_ctx
*ctx
,
730 const struct tgsi_full_src_register
*tgsi_src
,
731 struct r600_bc_alu_src
*r600_src
)
733 memset(r600_src
, 0, sizeof(struct r600_bc_alu_src
));
734 r600_src
->neg
= tgsi_src
->Register
.Negate
;
735 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
736 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
738 if((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
739 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
740 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
742 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
743 switch(ctx
->literals
[index
]) {
745 r600_src
->sel
= V_SQ_ALU_SRC_0
;
748 r600_src
->sel
= V_SQ_ALU_SRC_1_INT
;
751 r600_src
->sel
= V_SQ_ALU_SRC_M_1_INT
;
753 case 0x3F800000: // 1.0f
754 r600_src
->sel
= V_SQ_ALU_SRC_1
;
756 case 0x3F000000: // 0.5f
757 r600_src
->sel
= V_SQ_ALU_SRC_0_5
;
759 case 0xBF800000: // -1.0f
760 r600_src
->sel
= V_SQ_ALU_SRC_1
;
763 case 0xBF000000: // -0.5f
764 r600_src
->sel
= V_SQ_ALU_SRC_0_5
;
769 index
= tgsi_src
->Register
.Index
;
770 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
771 ctx
->value
[0] = ctx
->literals
[index
* 4 + 0];
772 ctx
->value
[1] = ctx
->literals
[index
* 4 + 1];
773 ctx
->value
[2] = ctx
->literals
[index
* 4 + 2];
774 ctx
->value
[3] = ctx
->literals
[index
* 4 + 3];
776 if (tgsi_src
->Register
.Indirect
)
777 r600_src
->rel
= V_SQ_REL_RELATIVE
;
778 r600_src
->sel
= tgsi_src
->Register
.Index
;
779 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
784 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
785 const struct tgsi_full_dst_register
*tgsi_dst
,
787 struct r600_bc_alu_dst
*r600_dst
)
789 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
791 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
792 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
793 r600_dst
->chan
= swizzle
;
795 if (tgsi_dst
->Register
.Indirect
)
796 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
797 if (inst
->Instruction
.Saturate
) {
803 static unsigned tgsi_chan(const struct tgsi_full_src_register
*tgsi_src
, unsigned swizzle
)
807 return tgsi_src
->Register
.SwizzleX
;
809 return tgsi_src
->Register
.SwizzleY
;
811 return tgsi_src
->Register
.SwizzleZ
;
813 return tgsi_src
->Register
.SwizzleW
;
819 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
821 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
822 struct r600_bc_alu alu
;
823 int i
, j
, k
, nconst
, r
;
825 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
826 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
829 r
= tgsi_src(ctx
, &inst
->Src
[i
], &r600_src
[i
]);
834 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
835 if (j
> 0 && inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
836 int treg
= r600_get_temp(ctx
);
837 for (k
= 0; k
< 4; k
++) {
838 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
839 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
840 alu
.src
[0].sel
= r600_src
[i
].sel
;
842 alu
.src
[0].rel
= r600_src
[i
].rel
;
848 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
852 r600_src
[i
].sel
= treg
;
860 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
861 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
863 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
864 struct r600_bc_alu alu
;
865 int i
, j
, k
, nliteral
, r
;
867 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
868 if (r600_src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
872 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
873 if (j
> 0 && r600_src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
874 int treg
= r600_get_temp(ctx
);
875 for (k
= 0; k
< 4; k
++) {
876 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
877 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
878 alu
.src
[0].sel
= r600_src
[i
].sel
;
885 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
889 r
= r600_bc_add_literal(ctx
->bc
, &ctx
->literals
[inst
->Src
[i
].Register
.Index
* 4]);
892 r600_src
[i
].sel
= treg
;
899 static int tgsi_last_instruction(unsigned writemask
)
903 for (i
= 0; i
< 4; i
++) {
904 if (writemask
& (1 << i
)) {
911 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
)
913 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
914 struct r600_bc_alu_src r600_src
[3];
915 struct r600_bc_alu alu
;
917 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
919 r
= tgsi_split_constant(ctx
, r600_src
);
922 r
= tgsi_split_literal_constant(ctx
, r600_src
);
925 for (i
= 0; i
< lasti
+ 1; i
++) {
926 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
929 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
930 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
934 alu
.inst
= ctx
->inst_info
->r600_opcode
;
936 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
937 alu
.src
[j
] = r600_src
[j
];
938 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
941 alu
.src
[0] = r600_src
[1];
942 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
944 alu
.src
[1] = r600_src
[0];
945 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
947 /* handle some special cases */
948 switch (ctx
->inst_info
->tgsi_opcode
) {
949 case TGSI_OPCODE_SUB
:
952 case TGSI_OPCODE_ABS
:
961 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
968 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
970 return tgsi_op2_s(ctx
, 0);
973 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
975 return tgsi_op2_s(ctx
, 1);
979 * r600 - trunc to -PI..PI range
980 * r700 - normalize by dividing by 2PI
983 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
,
984 struct r600_bc_alu_src r600_src
[3])
986 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
988 uint32_t lit_vals
[4];
989 struct r600_bc_alu alu
;
991 memset(lit_vals
, 0, 4*4);
992 r
= tgsi_split_constant(ctx
, r600_src
);
995 r
= tgsi_split_literal_constant(ctx
, r600_src
);
999 lit_vals
[0] = fui(1.0 /(3.1415926535 * 2));
1000 lit_vals
[1] = fui(0.5f
);
1002 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1003 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1007 alu
.dst
.sel
= ctx
->temp_reg
;
1010 alu
.src
[0] = r600_src
[0];
1011 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1013 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1014 alu
.src
[1].chan
= 0;
1015 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1016 alu
.src
[2].chan
= 1;
1018 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1021 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
1025 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1026 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
1029 alu
.dst
.sel
= ctx
->temp_reg
;
1032 alu
.src
[0].sel
= ctx
->temp_reg
;
1033 alu
.src
[0].chan
= 0;
1035 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1039 if (ctx
->bc
->chiprev
== CHIPREV_R600
) {
1040 lit_vals
[0] = fui(3.1415926535897f
* 2.0f
);
1041 lit_vals
[1] = fui(-3.1415926535897f
);
1043 lit_vals
[0] = fui(1.0f
);
1044 lit_vals
[1] = fui(-0.5f
);
1047 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1048 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1052 alu
.dst
.sel
= ctx
->temp_reg
;
1055 alu
.src
[0].sel
= ctx
->temp_reg
;
1056 alu
.src
[0].chan
= 0;
1058 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1059 alu
.src
[1].chan
= 0;
1060 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1061 alu
.src
[2].chan
= 1;
1063 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1066 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
1072 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
1074 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1075 struct r600_bc_alu_src r600_src
[3];
1076 struct r600_bc_alu alu
;
1078 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1080 r
= tgsi_setup_trig(ctx
, r600_src
);
1084 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1085 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1087 alu
.dst
.sel
= ctx
->temp_reg
;
1090 alu
.src
[0].sel
= ctx
->temp_reg
;
1091 alu
.src
[0].chan
= 0;
1093 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1097 /* replicate result */
1098 for (i
= 0; i
< lasti
+ 1; i
++) {
1099 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1102 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1103 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1105 alu
.src
[0].sel
= ctx
->temp_reg
;
1106 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1111 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1118 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
1120 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1121 struct r600_bc_alu_src r600_src
[3];
1122 struct r600_bc_alu alu
;
1125 /* We'll only need the trig stuff if we are going to write to the
1126 * X or Y components of the destination vector.
1128 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
1129 r
= tgsi_setup_trig(ctx
, r600_src
);
1135 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
1136 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1137 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
1138 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1142 alu
.src
[0].sel
= ctx
->temp_reg
;
1143 alu
.src
[0].chan
= 0;
1145 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1151 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
1152 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1153 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
1154 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1158 alu
.src
[0].sel
= ctx
->temp_reg
;
1159 alu
.src
[0].chan
= 0;
1161 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1167 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
1168 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1170 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1172 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1176 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1177 alu
.src
[0].chan
= 0;
1181 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1185 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1191 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
1192 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1194 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1196 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1200 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1201 alu
.src
[0].chan
= 0;
1205 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1209 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1217 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
1219 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1220 struct r600_bc_alu alu
;
1223 for (i
= 0; i
< 4; i
++) {
1224 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1225 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1229 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1231 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILP
) {
1232 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1235 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1238 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1243 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1247 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1251 /* kill must be last in ALU */
1252 ctx
->bc
->force_add_cf
= 1;
1253 ctx
->shader
->uses_kill
= TRUE
;
1257 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
1259 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1260 struct r600_bc_alu alu
;
1261 struct r600_bc_alu_src r600_src
[3];
1264 r
= tgsi_split_constant(ctx
, r600_src
);
1267 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1272 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1273 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1274 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
1275 alu
.src
[0].chan
= 0;
1276 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1279 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
1280 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1284 /* dst.y = max(src.x, 0.0) */
1285 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1286 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
1287 alu
.src
[0] = r600_src
[0];
1288 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
1289 alu
.src
[1].chan
= 0;
1290 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1293 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
1294 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1299 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1300 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1301 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1302 alu
.src
[0].chan
= 0;
1303 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1306 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
1308 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1312 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1316 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
1321 /* dst.z = log(src.y) */
1322 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1323 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
1324 alu
.src
[0] = r600_src
[0];
1325 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
1326 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1330 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1334 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1338 chan
= alu
.dst
.chan
;
1341 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1342 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1343 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
);
1344 alu
.src
[0] = r600_src
[0];
1345 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1346 alu
.src
[1].sel
= sel
;
1347 alu
.src
[1].chan
= chan
;
1349 alu
.src
[2] = r600_src
[0];
1350 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], 0);
1351 alu
.dst
.sel
= ctx
->temp_reg
;
1356 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1360 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1363 /* dst.z = exp(tmp.x) */
1364 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1365 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1366 alu
.src
[0].sel
= ctx
->temp_reg
;
1367 alu
.src
[0].chan
= 0;
1368 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1372 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1379 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
1381 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1382 struct r600_bc_alu alu
;
1385 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1388 * For state trackers other than OpenGL, we'll want to use
1389 * _RECIPSQRT_IEEE instead.
1391 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
);
1393 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1394 r
= tgsi_src(ctx
, &inst
->Src
[i
], &alu
.src
[i
]);
1397 alu
.src
[i
].chan
= tgsi_chan(&inst
->Src
[i
], 0);
1400 alu
.dst
.sel
= ctx
->temp_reg
;
1403 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1406 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1409 /* replicate result */
1410 return tgsi_helper_tempx_replicate(ctx
);
1413 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
1415 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1416 struct r600_bc_alu alu
;
1419 for (i
= 0; i
< 4; i
++) {
1420 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1421 alu
.src
[0].sel
= ctx
->temp_reg
;
1422 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1424 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1427 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1430 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1437 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
1439 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1440 struct r600_bc_alu alu
;
1443 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1444 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1445 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1446 r
= tgsi_src(ctx
, &inst
->Src
[i
], &alu
.src
[i
]);
1449 alu
.src
[i
].chan
= tgsi_chan(&inst
->Src
[i
], 0);
1451 alu
.dst
.sel
= ctx
->temp_reg
;
1454 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1457 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1460 /* replicate result */
1461 return tgsi_helper_tempx_replicate(ctx
);
1464 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
1466 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1467 struct r600_bc_alu alu
;
1471 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1472 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
1473 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1476 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1477 alu
.dst
.sel
= ctx
->temp_reg
;
1480 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1483 r
= r600_bc_add_literal(ctx
->bc
,ctx
->value
);
1487 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1488 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE
);
1489 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[0]);
1492 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], 0);
1493 alu
.src
[1].sel
= ctx
->temp_reg
;
1494 alu
.dst
.sel
= ctx
->temp_reg
;
1497 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1500 r
= r600_bc_add_literal(ctx
->bc
,ctx
->value
);
1503 /* POW(a,b) = EXP2(b * LOG2(a))*/
1504 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1505 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1506 alu
.src
[0].sel
= ctx
->temp_reg
;
1507 alu
.dst
.sel
= ctx
->temp_reg
;
1510 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1513 r
= r600_bc_add_literal(ctx
->bc
,ctx
->value
);
1516 return tgsi_helper_tempx_replicate(ctx
);
1519 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
1521 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1522 struct r600_bc_alu alu
;
1523 struct r600_bc_alu_src r600_src
[3];
1526 r
= tgsi_split_constant(ctx
, r600_src
);
1529 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1533 /* tmp = (src > 0 ? 1 : src) */
1534 for (i
= 0; i
< 4; i
++) {
1535 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1536 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1539 alu
.dst
.sel
= ctx
->temp_reg
;
1542 alu
.src
[0] = r600_src
[0];
1543 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1545 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1547 alu
.src
[2] = r600_src
[0];
1548 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], i
);
1551 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1555 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1559 /* dst = (-tmp > 0 ? -1 : tmp) */
1560 for (i
= 0; i
< 4; i
++) {
1561 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1562 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1564 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1568 alu
.src
[0].sel
= ctx
->temp_reg
;
1569 alu
.src
[0].chan
= i
;
1572 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1575 alu
.src
[2].sel
= ctx
->temp_reg
;
1576 alu
.src
[2].chan
= i
;
1580 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1587 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
1589 struct r600_bc_alu alu
;
1592 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1595 for (i
= 0; i
< 4; i
++) {
1596 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1597 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
1598 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
1601 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1602 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1605 alu
.src
[0].sel
= ctx
->temp_reg
;
1606 alu
.src
[0].chan
= i
;
1611 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1618 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
1620 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1621 struct r600_bc_alu_src r600_src
[3];
1622 struct r600_bc_alu alu
;
1624 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1626 r
= tgsi_split_constant(ctx
, r600_src
);
1629 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1632 for (i
= 0; i
< lasti
+ 1; i
++) {
1633 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1636 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1637 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1638 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1639 alu
.src
[j
] = r600_src
[j
];
1640 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1643 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1653 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1660 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
1662 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1663 struct r600_bc_alu_src r600_src
[3];
1664 struct r600_bc_alu alu
;
1667 r
= tgsi_split_constant(ctx
, r600_src
);
1670 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1673 for (i
= 0; i
< 4; i
++) {
1674 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1675 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1676 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1677 alu
.src
[j
] = r600_src
[j
];
1678 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1681 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1686 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1687 /* handle some special cases */
1688 switch (ctx
->inst_info
->tgsi_opcode
) {
1689 case TGSI_OPCODE_DP2
:
1691 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1692 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1695 case TGSI_OPCODE_DP3
:
1697 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1698 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1701 case TGSI_OPCODE_DPH
:
1703 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1704 alu
.src
[0].chan
= 0;
1714 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1721 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1723 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1724 struct r600_bc_tex tex
;
1725 struct r600_bc_alu alu
;
1729 boolean src_not_temp
=
1730 inst
->Src
[0].Register
.File
!= TGSI_FILE_TEMPORARY
&&
1731 inst
->Src
[0].Register
.File
!= TGSI_FILE_INPUT
;
1732 uint32_t lit_vals
[4];
1734 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1736 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1737 /* Add perspective divide */
1738 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1739 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1740 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1744 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1745 alu
.dst
.sel
= ctx
->temp_reg
;
1749 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1753 for (i
= 0; i
< 3; i
++) {
1754 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1755 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1756 alu
.src
[0].sel
= ctx
->temp_reg
;
1757 alu
.src
[0].chan
= 3;
1758 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1761 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1762 alu
.dst
.sel
= ctx
->temp_reg
;
1765 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1769 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1770 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1771 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1772 alu
.src
[0].chan
= 0;
1773 alu
.dst
.sel
= ctx
->temp_reg
;
1777 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1780 src_not_temp
= FALSE
;
1781 src_gpr
= ctx
->temp_reg
;
1784 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1785 int src_chan
, src2_chan
;
1787 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1788 for (i
= 0; i
< 4; i
++) {
1789 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1790 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
);
1814 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1817 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], src_chan
);
1818 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1821 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], src2_chan
);
1822 alu
.dst
.sel
= ctx
->temp_reg
;
1827 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1832 /* tmp1.z = RCP_e(|tmp1.z|) */
1833 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1834 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1835 alu
.src
[0].sel
= ctx
->temp_reg
;
1836 alu
.src
[0].chan
= 2;
1838 alu
.dst
.sel
= ctx
->temp_reg
;
1842 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1846 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1847 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1848 * muladd has no writemask, have to use another temp
1850 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1851 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1854 alu
.src
[0].sel
= ctx
->temp_reg
;
1855 alu
.src
[0].chan
= 0;
1856 alu
.src
[1].sel
= ctx
->temp_reg
;
1857 alu
.src
[1].chan
= 2;
1859 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1860 alu
.src
[2].chan
= 0;
1862 alu
.dst
.sel
= ctx
->temp_reg
;
1866 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1870 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1871 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1874 alu
.src
[0].sel
= ctx
->temp_reg
;
1875 alu
.src
[0].chan
= 1;
1876 alu
.src
[1].sel
= ctx
->temp_reg
;
1877 alu
.src
[1].chan
= 2;
1879 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1880 alu
.src
[2].chan
= 0;
1882 alu
.dst
.sel
= ctx
->temp_reg
;
1887 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1891 lit_vals
[0] = fui(1.5f
);
1893 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
1896 src_not_temp
= FALSE
;
1897 src_gpr
= ctx
->temp_reg
;
1901 for (i
= 0; i
< 4; i
++) {
1902 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1903 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1904 alu
.src
[0].sel
= src_gpr
;
1905 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1906 alu
.dst
.sel
= ctx
->temp_reg
;
1911 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1915 src_gpr
= ctx
->temp_reg
;
1918 opcode
= ctx
->inst_info
->r600_opcode
;
1919 if (opcode
== SQ_TEX_INST_SAMPLE
&&
1920 (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
))
1921 opcode
= SQ_TEX_INST_SAMPLE_C
;
1923 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1925 tex
.sampler_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1926 tex
.resource_id
= tex
.sampler_id
;
1927 tex
.src_gpr
= src_gpr
;
1928 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1929 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
1930 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
1931 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
1932 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
1938 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1945 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1946 tex
.coord_type_x
= 1;
1947 tex
.coord_type_y
= 1;
1948 tex
.coord_type_z
= 1;
1949 tex
.coord_type_w
= 1;
1952 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
)
1955 r
= r600_bc_add_tex(ctx
->bc
, &tex
);
1959 /* add shadow ambient support - gallium doesn't do it yet */
1963 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1965 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1966 struct r600_bc_alu_src r600_src
[3];
1967 struct r600_bc_alu alu
;
1968 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1972 r
= tgsi_split_constant(ctx
, r600_src
);
1975 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1979 /* optimize if it's just an equal balance */
1980 if(r600_src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
1981 for (i
= 0; i
< lasti
+ 1; i
++) {
1982 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1985 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1986 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
1987 alu
.src
[0] = r600_src
[1];
1988 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
1989 alu
.src
[1] = r600_src
[2];
1990 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1992 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2000 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2008 for (i
= 0; i
< lasti
+ 1; i
++) {
2009 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
2012 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2013 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
2014 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2015 alu
.src
[0].chan
= 0;
2016 alu
.src
[1] = r600_src
[0];
2017 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
2019 alu
.dst
.sel
= ctx
->temp_reg
;
2025 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2029 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2033 /* (1 - src0) * src2 */
2034 for (i
= 0; i
< lasti
+ 1; i
++) {
2035 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
2038 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2039 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2040 alu
.src
[0].sel
= ctx
->temp_reg
;
2041 alu
.src
[0].chan
= i
;
2042 alu
.src
[1] = r600_src
[2];
2043 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
2044 alu
.dst
.sel
= ctx
->temp_reg
;
2050 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2054 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2058 /* src0 * src1 + (1 - src0) * src2 */
2059 for (i
= 0; i
< lasti
+ 1; i
++) {
2060 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
2063 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2064 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
2066 alu
.src
[0] = r600_src
[0];
2067 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
2068 alu
.src
[1] = r600_src
[1];
2069 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
2070 alu
.src
[2].sel
= ctx
->temp_reg
;
2071 alu
.src
[2].chan
= i
;
2073 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2081 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2088 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
2090 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2091 struct r600_bc_alu_src r600_src
[3];
2092 struct r600_bc_alu alu
;
2094 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
2096 r
= tgsi_split_constant(ctx
, r600_src
);
2099 r
= tgsi_split_literal_constant(ctx
, r600_src
);
2103 for (i
= 0; i
< lasti
+ 1; i
++) {
2104 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
2107 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2108 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
);
2109 alu
.src
[0] = r600_src
[0];
2110 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
2112 alu
.src
[1] = r600_src
[2];
2113 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
2115 alu
.src
[2] = r600_src
[1];
2116 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[1], i
);
2118 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2127 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2134 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
2136 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2137 struct r600_bc_alu_src r600_src
[3];
2138 struct r600_bc_alu alu
;
2139 uint32_t use_temp
= 0;
2142 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
2145 r
= tgsi_split_constant(ctx
, r600_src
);
2148 r
= tgsi_split_literal_constant(ctx
, r600_src
);
2152 for (i
= 0; i
< 4; i
++) {
2153 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2154 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2156 alu
.src
[0] = r600_src
[0];
2159 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
2162 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2165 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
2168 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2169 alu
.src
[0].chan
= i
;
2172 alu
.src
[1] = r600_src
[1];
2175 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
2178 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
2181 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
2184 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2185 alu
.src
[1].chan
= i
;
2188 alu
.dst
.sel
= ctx
->temp_reg
;
2194 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2198 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2203 for (i
= 0; i
< 4; i
++) {
2204 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2205 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
2207 alu
.src
[0] = r600_src
[0];
2210 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
2213 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
2216 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2219 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2220 alu
.src
[0].chan
= i
;
2223 alu
.src
[1] = r600_src
[1];
2226 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
2229 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
2232 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
2235 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2236 alu
.src
[1].chan
= i
;
2239 alu
.src
[2].sel
= ctx
->temp_reg
;
2241 alu
.src
[2].chan
= i
;
2244 alu
.dst
.sel
= ctx
->temp_reg
;
2246 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2255 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2259 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2264 return tgsi_helper_copy(ctx
, inst
);
2268 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
2270 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2271 struct r600_bc_alu_src r600_src
[3] = { { 0 } };
2272 struct r600_bc_alu alu
;
2275 /* result.x = 2^floor(src); */
2276 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
2277 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2279 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2280 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2284 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2286 alu
.dst
.sel
= ctx
->temp_reg
;
2290 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2294 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2298 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2299 alu
.src
[0].sel
= ctx
->temp_reg
;
2300 alu
.src
[0].chan
= 0;
2302 alu
.dst
.sel
= ctx
->temp_reg
;
2306 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2310 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2315 /* result.y = tmp - floor(tmp); */
2316 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
2317 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2319 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
2320 alu
.src
[0] = r600_src
[0];
2321 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2324 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2326 alu
.dst
.sel
= ctx
->temp_reg
;
2327 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2335 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2338 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2343 /* result.z = RoughApprox2ToX(tmp);*/
2344 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
2345 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2346 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2347 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2350 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2352 alu
.dst
.sel
= ctx
->temp_reg
;
2358 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2361 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2366 /* result.w = 1.0;*/
2367 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
2368 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2370 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2371 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2372 alu
.src
[0].chan
= 0;
2374 alu
.dst
.sel
= ctx
->temp_reg
;
2378 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2381 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2385 return tgsi_helper_copy(ctx
, inst
);
2388 static int tgsi_log(struct r600_shader_ctx
*ctx
)
2390 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2391 struct r600_bc_alu alu
;
2394 /* result.x = floor(log2(src)); */
2395 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
2396 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2398 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2399 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2403 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2405 alu
.dst
.sel
= ctx
->temp_reg
;
2409 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2413 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2417 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2418 alu
.src
[0].sel
= ctx
->temp_reg
;
2419 alu
.src
[0].chan
= 0;
2421 alu
.dst
.sel
= ctx
->temp_reg
;
2426 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2430 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2435 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2436 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
2437 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2439 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2440 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2444 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2446 alu
.dst
.sel
= ctx
->temp_reg
;
2451 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2455 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2459 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2461 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2462 alu
.src
[0].sel
= ctx
->temp_reg
;
2463 alu
.src
[0].chan
= 1;
2465 alu
.dst
.sel
= ctx
->temp_reg
;
2470 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2474 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2478 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2480 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2481 alu
.src
[0].sel
= ctx
->temp_reg
;
2482 alu
.src
[0].chan
= 1;
2484 alu
.dst
.sel
= ctx
->temp_reg
;
2489 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2493 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2497 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2499 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
2500 alu
.src
[0].sel
= ctx
->temp_reg
;
2501 alu
.src
[0].chan
= 1;
2503 alu
.dst
.sel
= ctx
->temp_reg
;
2508 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2512 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2516 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2518 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2520 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2524 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2526 alu
.src
[1].sel
= ctx
->temp_reg
;
2527 alu
.src
[1].chan
= 1;
2529 alu
.dst
.sel
= ctx
->temp_reg
;
2534 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2538 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2543 /* result.z = log2(src);*/
2544 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
2545 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2547 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2548 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2552 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2554 alu
.dst
.sel
= ctx
->temp_reg
;
2559 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2563 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2568 /* result.w = 1.0; */
2569 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
2570 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2572 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2573 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2574 alu
.src
[0].chan
= 0;
2576 alu
.dst
.sel
= ctx
->temp_reg
;
2581 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2585 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2590 return tgsi_helper_copy(ctx
, inst
);
2593 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
2595 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2596 struct r600_bc_alu alu
;
2598 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2600 switch (inst
->Instruction
.Opcode
) {
2601 case TGSI_OPCODE_ARL
:
2602 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
;
2604 case TGSI_OPCODE_ARR
:
2605 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
2612 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2615 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2618 alu
.dst
.sel
= ctx
->temp_reg
;
2620 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
));
2623 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2624 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
;
2625 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2628 alu
.src
[0].sel
= ctx
->temp_reg
;
2629 alu
.src
[0].chan
= 0;
2631 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
));
2636 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
2638 /* TODO from r600c, ar values don't persist between clauses */
2639 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2640 struct r600_bc_alu alu
;
2642 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2644 switch (inst
->Instruction
.Opcode
) {
2645 case TGSI_OPCODE_ARL
:
2646 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
;
2648 case TGSI_OPCODE_ARR
:
2649 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
;
2657 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2660 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2664 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
));
2667 ctx
->bc
->cf_last
->r6xx_uses_waterfall
= 1;
2671 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
2673 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2674 struct r600_bc_alu alu
;
2677 for (i
= 0; i
< 4; i
++) {
2678 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2680 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2681 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2685 if (i
== 0 || i
== 3) {
2686 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2688 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2691 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
2694 if (i
== 0 || i
== 2) {
2695 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
2697 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[1]);
2700 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
2704 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2711 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
2713 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2714 struct r600_bc_alu alu
;
2717 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2721 alu
.dst
.sel
= ctx
->temp_reg
;
2725 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2728 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2729 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2730 alu
.src
[1].chan
= 0;
2734 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
2740 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
2743 if (ctx
->bc
->cf_last
) {
2744 if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
) << 3)
2746 else if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
) << 3)
2751 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
) << 3;
2752 ctx
->bc
->force_add_cf
= 1;
2753 } else if (alu_pop
== 2) {
2754 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
) << 3;
2755 ctx
->bc
->force_add_cf
= 1;
2757 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP
));
2758 ctx
->bc
->cf_last
->pop_count
= pops
;
2759 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2764 static inline void callstack_decrease_current(struct r600_shader_ctx
*ctx
, unsigned reason
)
2768 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2772 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
-= 4;
2775 /* TOODO : for 16 vp asic should -= 2; */
2776 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2781 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
)
2783 if (check_max_only
) {
2796 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
) >
2797 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2798 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2799 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
;
2805 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2809 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+= 4;
2812 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2816 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
) >
2817 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2818 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2819 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
;
2823 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
2825 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
2827 sp
->mid
= (struct r600_bc_cf
**)realloc((void *)sp
->mid
,
2828 sizeof(struct r600_bc_cf
*) * (sp
->num_mid
+ 1));
2829 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
2833 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
2836 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
2837 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
2840 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
2842 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
2854 static int emit_return(struct r600_shader_ctx
*ctx
)
2856 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_RETURN
);
2860 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
2863 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_JUMP
);
2864 ctx
->bc
->cf_last
->pop_count
= pops
;
2865 /* TODO work out offset */
2869 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
2874 static void emit_testflag(struct r600_shader_ctx
*ctx
)
2879 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
2882 emit_jump_to_offset(ctx
, 1, 4);
2883 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
2884 pops(ctx
, ifidx
+ 1);
2888 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
2892 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2893 ctx
->bc
->cf_last
->pop_count
= 1;
2895 fc_set_mid(ctx
, fc_sp
);
2901 static int tgsi_if(struct r600_shader_ctx
*ctx
)
2903 emit_logic_pred(ctx
, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
));
2905 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
2907 fc_pushlevel(ctx
, FC_IF
);
2909 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
2913 static int tgsi_else(struct r600_shader_ctx
*ctx
)
2915 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE
));
2916 ctx
->bc
->cf_last
->pop_count
= 1;
2918 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
2919 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
2923 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
2926 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
2927 R600_ERR("if/endif unbalanced in shader\n");
2931 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
2932 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2933 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
2935 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2939 callstack_decrease_current(ctx
, FC_PUSH_VPM
);
2943 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
2945 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
));
2947 fc_pushlevel(ctx
, FC_LOOP
);
2949 /* check stack depth */
2950 callstack_check_depth(ctx
, FC_LOOP
, 0);
2954 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
2958 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
));
2960 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
2961 R600_ERR("loop/endloop in shader code are not paired.\n");
2965 /* fixup loop pointers - from r600isa
2966 LOOP END points to CF after LOOP START,
2967 LOOP START point to CF after LOOP END
2968 BRK/CONT point to LOOP END CF
2970 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
2972 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2974 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
2975 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
2977 /* TODO add LOOPRET support */
2979 callstack_decrease_current(ctx
, FC_LOOP
);
2983 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
2987 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
2989 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
2994 R600_ERR("Break not inside loop/endloop pair\n");
2998 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2999 ctx
->bc
->cf_last
->pop_count
= 1;
3001 fc_set_mid(ctx
, fscp
);
3004 callstack_check_depth(ctx
, FC_PUSH_VPM
, 1);
3008 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
3009 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
3010 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
3011 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
3014 * For state trackers other than OpenGL, we'll want to use
3015 * _RECIP_IEEE instead.
3017 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
3019 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_rsq
},
3020 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
3021 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
3022 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
3023 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
3024 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3025 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3026 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
3027 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
3028 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
3029 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
3030 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
3031 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
3032 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
3033 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
3034 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3036 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3037 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3039 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3040 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3041 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
3042 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3043 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
3044 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3045 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
3046 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
3047 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
3048 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
3050 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3051 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
3052 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3053 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3054 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
3055 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
3056 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
3057 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
3058 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3059 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3060 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3061 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3062 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3063 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
3064 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3065 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
3066 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
3067 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
3068 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
3069 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3070 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3071 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3072 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3073 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3074 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3075 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3076 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3077 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3078 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3079 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
3080 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3081 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3082 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3083 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
3084 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
3085 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
3086 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
3087 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3088 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3089 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3090 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
3091 {TGSI_OPCODE_BRK
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
3092 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
3094 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3095 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3096 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
3097 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
3099 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3100 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3101 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3102 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3103 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3104 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3105 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3106 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
3107 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3109 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3110 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3111 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3112 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3113 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3114 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3115 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3116 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3117 {TGSI_OPCODE_CONT
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
3118 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3119 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3120 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
3121 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3122 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
3123 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3125 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3126 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3127 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3128 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3129 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3131 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3132 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3133 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3134 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3135 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3136 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3137 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3138 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3139 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
3140 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
3142 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3143 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3144 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3145 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3146 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3147 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3148 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3149 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3150 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3151 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3152 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3153 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3154 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3155 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3156 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3157 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3158 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3159 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3160 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3161 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3162 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3163 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3164 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3165 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3166 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3167 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3168 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3169 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3172 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
3173 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
3174 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
3175 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
3176 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
3177 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
3178 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
3179 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3180 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
3181 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
3182 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3183 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3184 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
3185 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
3186 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
3187 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
3188 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
3189 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
3190 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
3191 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
3192 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3194 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3195 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3197 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3198 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3199 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
3200 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3201 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
3202 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3203 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
3204 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
3205 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
3206 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
3208 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3209 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
3210 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3211 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3212 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
3213 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
3214 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
3215 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
3216 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3217 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3218 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3219 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3220 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3221 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
3222 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3223 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
3224 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
3225 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
3226 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
3227 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3228 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3229 {TGSI_OPCODE_TXD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3230 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3231 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3232 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3233 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3234 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3235 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3236 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3237 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
3238 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3239 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3240 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3241 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
3242 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
3243 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
3244 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
3245 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3246 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3247 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3248 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
3249 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
3250 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
3252 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3253 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3254 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
3255 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
3257 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3258 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3259 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3260 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3261 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3262 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3263 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3264 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
3265 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3267 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3268 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3269 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3270 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3271 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3272 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3273 {TGSI_OPCODE_TXF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3274 {TGSI_OPCODE_TXQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3275 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
3276 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3277 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3278 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
3279 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3280 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
3281 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3283 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3284 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3285 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3286 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3287 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3289 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3290 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3291 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3292 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3293 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3294 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3295 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3296 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3297 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
3298 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
3300 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3301 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3302 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3303 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3304 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3305 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3306 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3307 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3308 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3309 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3310 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3311 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3312 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3313 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3314 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3315 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3316 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3317 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3318 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3319 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3320 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3321 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3322 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3323 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3324 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3325 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3326 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3327 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},