2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
31 #include "r600_formats.h"
32 #include "r600_opcodes.h"
37 static void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
39 struct r600_pipe_state
*rstate
= &shader
->rstate
;
40 struct r600_shader
*rshader
= &shader
->shader
;
41 unsigned spi_vs_out_id
[10];
44 /* clear previous register */
47 /* so far never got proper semantic id from tgsi */
48 /* FIXME better to move this in config things so they get emited
49 * only one time per cs
51 for (i
= 0; i
< 10; i
++) {
54 for (i
= 0; i
< 32; i
++) {
55 tmp
= i
<< ((i
& 3) * 8);
56 spi_vs_out_id
[i
/ 4] |= tmp
;
58 for (i
= 0; i
< 10; i
++) {
59 r600_pipe_state_add_reg(rstate
,
60 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
61 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
);
64 r600_pipe_state_add_reg(rstate
,
65 R_0286C4_SPI_VS_OUT_CONFIG
,
66 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2),
68 r600_pipe_state_add_reg(rstate
,
69 R_028868_SQ_PGM_RESOURCES_VS
,
70 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
71 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
73 r600_pipe_state_add_reg(rstate
,
74 R_0288D0_SQ_PGM_CF_OFFSET_VS
,
75 0x00000000, 0xFFFFFFFF, NULL
);
76 r600_pipe_state_add_reg(rstate
,
77 R_028858_SQ_PGM_START_VS
,
78 r600_bo_offset(shader
->bo
) >> 8, 0xFFFFFFFF, shader
->bo
);
80 r600_pipe_state_add_reg(rstate
,
81 R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF,
86 int r600_find_vs_semantic_index(struct r600_shader
*vs
,
87 struct r600_shader
*ps
, int id
)
89 struct r600_shader_io
*input
= &ps
->input
[id
];
91 for (int i
= 0; i
< vs
->noutput
; i
++) {
92 if (input
->name
== vs
->output
[i
].name
&&
93 input
->sid
== vs
->output
[i
].sid
) {
100 static void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
102 struct r600_pipe_state
*rstate
= &shader
->rstate
;
103 struct r600_shader
*rshader
= &shader
->shader
;
104 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
;
105 int pos_index
= -1, face_index
= -1;
109 for (i
= 0; i
< rshader
->ninput
; i
++) {
110 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
112 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
116 for (i
= 0; i
< rshader
->noutput
; i
++) {
117 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
118 r600_pipe_state_add_reg(rstate
,
119 R_02880C_DB_SHADER_CONTROL
,
120 S_02880C_Z_EXPORT_ENABLE(1),
121 S_02880C_Z_EXPORT_ENABLE(1), NULL
);
122 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
123 r600_pipe_state_add_reg(rstate
,
124 R_02880C_DB_SHADER_CONTROL
,
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
126 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL
);
131 for (i
= 0; i
< rshader
->noutput
; i
++) {
132 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
|| rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
134 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
138 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
140 /* always at least export 1 component per pixel */
144 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
145 S_0286CC_PERSP_GRADIENT_ENA(1);
147 if (pos_index
!= -1) {
148 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
149 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
150 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
151 S_0286CC_BARYC_SAMPLE_CNTL(1));
155 spi_ps_in_control_1
= 0;
156 if (face_index
!= -1) {
157 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
158 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
161 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
, 0xFFFFFFFF, NULL
);
162 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
, 0xFFFFFFFF, NULL
);
163 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
);
164 r600_pipe_state_add_reg(rstate
,
165 R_028840_SQ_PGM_START_PS
,
166 r600_bo_offset(shader
->bo
) >> 8, 0xFFFFFFFF, shader
->bo
);
167 r600_pipe_state_add_reg(rstate
,
168 R_028850_SQ_PGM_RESOURCES_PS
,
169 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
170 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
172 r600_pipe_state_add_reg(rstate
,
173 R_028854_SQ_PGM_EXPORTS_PS
,
174 exports_ps
, 0xFFFFFFFF, NULL
);
175 r600_pipe_state_add_reg(rstate
,
176 R_0288CC_SQ_PGM_CF_OFFSET_PS
,
177 0x00000000, 0xFFFFFFFF, NULL
);
179 if (rshader
->fs_write_all
) {
180 r600_pipe_state_add_reg(rstate
, R_028808_CB_COLOR_CONTROL
,
181 S_028808_MULTIWRITE_ENABLE(1),
182 S_028808_MULTIWRITE_ENABLE(1),
186 if (rshader
->uses_kill
) {
187 /* only set some bits here, the other bits are set in the dsa state */
188 r600_pipe_state_add_reg(rstate
,
189 R_02880C_DB_SHADER_CONTROL
,
190 S_02880C_KILL_ENABLE(1),
191 S_02880C_KILL_ENABLE(1), NULL
);
193 r600_pipe_state_add_reg(rstate
,
194 R_03E200_SQ_LOOP_CONST_0
, 0x01000FFF,
198 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
200 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
201 struct r600_shader
*rshader
= &shader
->shader
;
204 /* copy new shader */
205 if (shader
->bo
== NULL
) {
206 shader
->bo
= r600_bo(rctx
->radeon
, rshader
->bc
.ndw
* 4, 4096, 0, 0);
207 if (shader
->bo
== NULL
) {
210 ptr
= r600_bo_map(rctx
->radeon
, shader
->bo
, 0, NULL
);
211 memcpy(ptr
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
212 r600_bo_unmap(rctx
->radeon
, shader
->bo
);
215 switch (rshader
->processor_type
) {
216 case TGSI_PROCESSOR_VERTEX
:
217 if (rshader
->family
>= CHIP_CEDAR
) {
218 evergreen_pipe_shader_vs(ctx
, shader
);
220 r600_pipe_shader_vs(ctx
, shader
);
223 case TGSI_PROCESSOR_FRAGMENT
:
224 if (rshader
->family
>= CHIP_CEDAR
) {
225 evergreen_pipe_shader_ps(ctx
, shader
);
227 r600_pipe_shader_ps(ctx
, shader
);
236 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
238 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
, const struct tgsi_token
*tokens
)
240 static int dump_shaders
= -1;
241 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
244 /* Would like some magic "get_bool_option_once" routine.
246 if (dump_shaders
== -1)
247 dump_shaders
= debug_get_bool_option("R600_DUMP_SHADERS", FALSE
);
250 fprintf(stderr
, "--------------------------------------------------------------\n");
251 tgsi_dump(tokens
, 0);
253 shader
->shader
.family
= r600_get_family(rctx
->radeon
);
254 r
= r600_shader_from_tgsi(tokens
, &shader
->shader
);
256 R600_ERR("translation from TGSI failed !\n");
259 r
= r600_bc_build(&shader
->shader
.bc
);
261 R600_ERR("building bytecode failed !\n");
265 r600_bc_dump(&shader
->shader
.bc
);
266 fprintf(stderr
, "______________________________________________________________\n");
268 return r600_pipe_shader(ctx
, shader
);
271 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
273 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
275 r600_bo_reference(rctx
->radeon
, &shader
->bo
, NULL
);
276 r600_bc_clear(&shader
->shader
.bc
);
280 * tgsi -> r600 shader
282 struct r600_shader_tgsi_instruction
;
284 struct r600_shader_src
{
293 struct r600_shader_ctx
{
294 struct tgsi_shader_info info
;
295 struct tgsi_parse_context parse
;
296 const struct tgsi_token
*tokens
;
298 unsigned file_offset
[TGSI_FILE_COUNT
];
301 struct r600_shader_tgsi_instruction
*inst_info
;
303 struct r600_shader
*shader
;
304 struct r600_shader_src src
[3];
307 u32 max_driver_temp_used
;
308 /* needed for evergreen interpolation */
309 boolean input_centroid
;
310 boolean input_linear
;
311 boolean input_perspective
;
315 struct r600_shader_tgsi_instruction
{
316 unsigned tgsi_opcode
;
318 unsigned r600_opcode
;
319 int (*process
)(struct r600_shader_ctx
*ctx
);
322 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[];
323 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
325 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
327 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
330 if (i
->Instruction
.NumDstRegs
> 1) {
331 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
334 if (i
->Instruction
.Predicate
) {
335 R600_ERR("predicate unsupported\n");
339 if (i
->Instruction
.Label
) {
340 R600_ERR("label unsupported\n");
344 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
345 if (i
->Src
[j
].Register
.Dimension
) {
346 R600_ERR("unsupported src %d (dimension %d)\n", j
,
347 i
->Src
[j
].Register
.Dimension
);
351 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
352 if (i
->Dst
[j
].Register
.Dimension
) {
353 R600_ERR("unsupported dst (dimension)\n");
360 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
363 struct r600_bc_alu alu
;
364 int gpr
= 0, base_chan
= 0;
367 if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
) {
369 if (ctx
->shader
->input
[input
].centroid
)
371 } else if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
373 /* if we have perspective add one */
374 if (ctx
->input_perspective
) {
376 /* if we have perspective centroid */
377 if (ctx
->input_centroid
)
380 if (ctx
->shader
->input
[input
].centroid
)
384 /* work out gpr and base_chan from index */
386 base_chan
= (2 * (ij_index
% 2)) + 1;
388 for (i
= 0; i
< 8; i
++) {
389 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
392 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW
;
394 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY
;
396 if ((i
> 1) && (i
< 6)) {
397 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
401 alu
.dst
.chan
= i
% 4;
403 alu
.src
[0].sel
= gpr
;
404 alu
.src
[0].chan
= (base_chan
- (i
% 2));
406 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
408 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
411 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
419 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
421 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
424 switch (d
->Declaration
.File
) {
425 case TGSI_FILE_INPUT
:
426 i
= ctx
->shader
->ninput
++;
427 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
428 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
429 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
430 ctx
->shader
->input
[i
].centroid
= d
->Declaration
.Centroid
;
431 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
432 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
->bc
->chiprev
== CHIPREV_EVERGREEN
) {
433 /* turn input into interpolate on EG */
434 if (ctx
->shader
->input
[i
].name
!= TGSI_SEMANTIC_POSITION
) {
435 if (ctx
->shader
->input
[i
].interpolate
> 0) {
436 ctx
->shader
->input
[i
].lds_pos
= ctx
->shader
->nlds
++;
437 evergreen_interp_alu(ctx
, i
);
442 case TGSI_FILE_OUTPUT
:
443 i
= ctx
->shader
->noutput
++;
444 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
445 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
446 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
447 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
449 case TGSI_FILE_CONSTANT
:
450 case TGSI_FILE_TEMPORARY
:
451 case TGSI_FILE_SAMPLER
:
452 case TGSI_FILE_ADDRESS
:
455 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
461 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
463 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
467 * for evergreen we need to scan the shader to find the number of GPRs we need to
468 * reserve for interpolation.
470 * we need to know if we are going to emit
471 * any centroid inputs
472 * if perspective and linear are required
474 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
479 ctx
->input_linear
= FALSE
;
480 ctx
->input_perspective
= FALSE
;
481 ctx
->input_centroid
= FALSE
;
482 ctx
->num_interp_gpr
= 1;
484 /* any centroid inputs */
485 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
486 /* skip position/face */
487 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
488 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
)
490 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_LINEAR
)
491 ctx
->input_linear
= TRUE
;
492 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_PERSPECTIVE
)
493 ctx
->input_perspective
= TRUE
;
494 if (ctx
->info
.input_centroid
[i
])
495 ctx
->input_centroid
= TRUE
;
499 /* ignoring sample for now */
500 if (ctx
->input_perspective
)
502 if (ctx
->input_linear
)
504 if (ctx
->input_centroid
)
507 ctx
->num_interp_gpr
+= (num_baryc
+ 1) >> 1;
509 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
510 return ctx
->num_interp_gpr
;
513 static void tgsi_src(struct r600_shader_ctx
*ctx
,
514 const struct tgsi_full_src_register
*tgsi_src
,
515 struct r600_shader_src
*r600_src
)
517 memset(r600_src
, 0, sizeof(*r600_src
));
518 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
519 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
520 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
521 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
522 r600_src
->neg
= tgsi_src
->Register
.Negate
;
523 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
524 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
526 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
527 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
528 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
530 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
531 r600_bc_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
);
532 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
535 index
= tgsi_src
->Register
.Index
;
536 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
537 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
539 if (tgsi_src
->Register
.Indirect
)
540 r600_src
->rel
= V_SQ_REL_RELATIVE
;
541 r600_src
->sel
= tgsi_src
->Register
.Index
;
542 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
546 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
, unsigned int offset
, unsigned int dst_reg
)
548 struct r600_bc_vtx vtx
;
553 struct r600_bc_alu alu
;
555 memset(&alu
, 0, sizeof(alu
));
557 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
558 alu
.src
[0].sel
= ctx
->ar_reg
;
560 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
561 alu
.src
[1].value
= offset
;
563 alu
.dst
.sel
= dst_reg
;
567 if ((r
= r600_bc_add_alu(ctx
->bc
, &alu
)))
572 ar_reg
= ctx
->ar_reg
;
575 memset(&vtx
, 0, sizeof(vtx
));
576 vtx
.fetch_type
= 2; /* VTX_FETCH_NO_INDEX_OFFSET */
577 vtx
.src_gpr
= ar_reg
;
578 vtx
.mega_fetch_count
= 16;
579 vtx
.dst_gpr
= dst_reg
;
580 vtx
.dst_sel_x
= 0; /* SEL_X */
581 vtx
.dst_sel_y
= 1; /* SEL_Y */
582 vtx
.dst_sel_z
= 2; /* SEL_Z */
583 vtx
.dst_sel_w
= 3; /* SEL_W */
584 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
585 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
586 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
587 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
589 if ((r
= r600_bc_add_vtx(ctx
->bc
, &vtx
)))
595 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
597 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
598 struct r600_bc_alu alu
;
599 int i
, j
, k
, nconst
, r
;
601 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
602 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
605 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
607 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
608 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
612 if (ctx
->src
[i
].rel
) {
613 int treg
= r600_get_temp(ctx
);
614 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].sel
- 512, treg
)))
617 ctx
->src
[i
].sel
= treg
;
621 int treg
= r600_get_temp(ctx
);
622 for (k
= 0; k
< 4; k
++) {
623 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
624 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
625 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
627 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
633 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
637 ctx
->src
[i
].sel
= treg
;
645 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
646 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
648 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
649 struct r600_bc_alu alu
;
650 int i
, j
, k
, nliteral
, r
;
652 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
653 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
657 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
658 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
659 int treg
= r600_get_temp(ctx
);
660 for (k
= 0; k
< 4; k
++) {
661 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
662 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
663 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
665 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
671 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
675 ctx
->src
[i
].sel
= treg
;
682 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
684 struct tgsi_full_immediate
*immediate
;
685 struct tgsi_full_property
*property
;
686 struct r600_shader_ctx ctx
;
687 struct r600_bc_output output
[32];
688 unsigned output_done
, noutput
;
692 ctx
.bc
= &shader
->bc
;
694 r
= r600_bc_init(ctx
.bc
, shader
->family
);
698 tgsi_scan_shader(tokens
, &ctx
.info
);
699 tgsi_parse_init(&ctx
.parse
, tokens
);
700 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
701 shader
->processor_type
= ctx
.type
;
702 ctx
.bc
->type
= shader
->processor_type
;
704 /* register allocations */
705 /* Values [0,127] correspond to GPR[0..127].
706 * Values [128,159] correspond to constant buffer bank 0
707 * Values [160,191] correspond to constant buffer bank 1
708 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
709 * Values [256,287] correspond to constant buffer bank 2 (EG)
710 * Values [288,319] correspond to constant buffer bank 3 (EG)
711 * Other special values are shown in the list below.
712 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
713 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
714 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
715 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
716 * 248 SQ_ALU_SRC_0: special constant 0.0.
717 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
718 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
719 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
720 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
721 * 253 SQ_ALU_SRC_LITERAL: literal constant.
722 * 254 SQ_ALU_SRC_PV: previous vector result.
723 * 255 SQ_ALU_SRC_PS: previous scalar result.
725 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
726 ctx
.file_offset
[i
] = 0;
728 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
729 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
730 if (ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
) {
731 r600_bc_add_cfinst(ctx
.bc
, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
733 r600_bc_add_cfinst(ctx
.bc
, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
736 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
) {
737 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
739 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
740 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
741 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
742 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
744 /* Outside the GPR range. This will be translated to one of the
745 * kcache banks later. */
746 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
748 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
749 ctx
.ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
750 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
751 ctx
.temp_reg
= ctx
.ar_reg
+ 1;
755 shader
->fs_write_all
= FALSE
;
756 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
757 tgsi_parse_token(&ctx
.parse
);
758 switch (ctx
.parse
.FullToken
.Token
.Type
) {
759 case TGSI_TOKEN_TYPE_IMMEDIATE
:
760 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
761 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
762 if(ctx
.literals
== NULL
) {
766 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
767 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
768 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
769 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
772 case TGSI_TOKEN_TYPE_DECLARATION
:
773 r
= tgsi_declaration(&ctx
);
777 case TGSI_TOKEN_TYPE_INSTRUCTION
:
778 r
= tgsi_is_supported(&ctx
);
781 ctx
.max_driver_temp_used
= 0;
782 /* reserve first tmp for everyone */
785 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
786 if ((r
= tgsi_split_constant(&ctx
)))
788 if ((r
= tgsi_split_literal_constant(&ctx
)))
790 if (ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
)
791 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
793 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
794 r
= ctx
.inst_info
->process(&ctx
);
798 case TGSI_TOKEN_TYPE_PROPERTY
:
799 property
= &ctx
.parse
.FullToken
.FullProperty
;
800 if (property
->Property
.PropertyName
== TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
) {
801 if (property
->u
[0].Data
== 1)
802 shader
->fs_write_all
= TRUE
;
806 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
812 noutput
= shader
->noutput
;
813 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
814 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
815 output
[i
].gpr
= shader
->output
[i
].gpr
;
816 output
[i
].elem_size
= 3;
817 output
[i
].swizzle_x
= 0;
818 output
[i
].swizzle_y
= 1;
819 output
[i
].swizzle_z
= 2;
820 output
[i
].swizzle_w
= 3;
821 output
[i
].burst_count
= 1;
822 output
[i
].barrier
= 1;
823 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
824 output
[i
].array_base
= i
- pos0
;
825 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
827 case TGSI_PROCESSOR_VERTEX
:
828 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
829 output
[i
].array_base
= 60;
830 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
831 /* position doesn't count in array_base */
834 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
835 output
[i
].array_base
= 61;
836 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
837 /* position doesn't count in array_base */
841 case TGSI_PROCESSOR_FRAGMENT
:
842 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
843 output
[i
].array_base
= shader
->output
[i
].sid
;
844 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
845 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
846 output
[i
].array_base
= 61;
847 output
[i
].swizzle_x
= 2;
848 output
[i
].swizzle_y
= 7;
849 output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
850 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
851 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
852 output
[i
].array_base
= 61;
853 output
[i
].swizzle_x
= 7;
854 output
[i
].swizzle_y
= 1;
855 output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
856 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
858 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
864 R600_ERR("unsupported processor type %d\n", ctx
.type
);
869 /* add fake param output for vertex shader if no param is exported */
870 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
871 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
872 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
878 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
880 output
[i
].elem_size
= 3;
881 output
[i
].swizzle_x
= 0;
882 output
[i
].swizzle_y
= 1;
883 output
[i
].swizzle_z
= 2;
884 output
[i
].swizzle_w
= 3;
885 output
[i
].burst_count
= 1;
886 output
[i
].barrier
= 1;
887 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
888 output
[i
].array_base
= 0;
889 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
893 /* add fake pixel export */
894 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
895 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
897 output
[0].elem_size
= 3;
898 output
[0].swizzle_x
= 7;
899 output
[0].swizzle_y
= 7;
900 output
[0].swizzle_z
= 7;
901 output
[0].swizzle_w
= 7;
902 output
[0].burst_count
= 1;
903 output
[0].barrier
= 1;
904 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
905 output
[0].array_base
= 0;
906 output
[0].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
909 /* set export done on last export of each type */
910 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
911 if (i
== (noutput
- 1)) {
912 output
[i
].end_of_program
= 1;
914 if (!(output_done
& (1 << output
[i
].type
))) {
915 output_done
|= (1 << output
[i
].type
);
916 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
);
919 /* add output to bytecode */
920 for (i
= 0; i
< noutput
; i
++) {
921 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
926 tgsi_parse_free(&ctx
.parse
);
930 tgsi_parse_free(&ctx
.parse
);
934 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
936 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
940 static int tgsi_end(struct r600_shader_ctx
*ctx
)
945 static void r600_bc_src(struct r600_bc_alu_src
*bc_src
,
946 const struct r600_shader_src
*shader_src
,
949 bc_src
->sel
= shader_src
->sel
;
950 bc_src
->chan
= shader_src
->swizzle
[chan
];
951 bc_src
->neg
= shader_src
->neg
;
952 bc_src
->abs
= shader_src
->abs
;
953 bc_src
->rel
= shader_src
->rel
;
954 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
957 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
958 const struct tgsi_full_dst_register
*tgsi_dst
,
960 struct r600_bc_alu_dst
*r600_dst
)
962 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
964 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
965 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
966 r600_dst
->chan
= swizzle
;
968 if (tgsi_dst
->Register
.Indirect
)
969 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
970 if (inst
->Instruction
.Saturate
) {
975 static int tgsi_last_instruction(unsigned writemask
)
979 for (i
= 0; i
< 4; i
++) {
980 if (writemask
& (1 << i
)) {
987 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
)
989 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
990 struct r600_bc_alu alu
;
992 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
994 for (i
= 0; i
< lasti
+ 1; i
++) {
995 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
998 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
999 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1001 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1003 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1004 r600_bc_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
1007 r600_bc_src(&alu
.src
[0], &ctx
->src
[1], i
);
1008 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], i
);
1010 /* handle some special cases */
1011 switch (ctx
->inst_info
->tgsi_opcode
) {
1012 case TGSI_OPCODE_SUB
:
1015 case TGSI_OPCODE_ABS
:
1024 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1031 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
1033 return tgsi_op2_s(ctx
, 0);
1036 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
1038 return tgsi_op2_s(ctx
, 1);
1042 * r600 - trunc to -PI..PI range
1043 * r700 - normalize by dividing by 2PI
1046 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
1048 static float half_inv_pi
= 1.0 /(3.1415926535 * 2);
1049 static float double_pi
= 3.1415926535 * 2;
1050 static float neg_pi
= -3.1415926535;
1053 struct r600_bc_alu alu
;
1055 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1056 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1060 alu
.dst
.sel
= ctx
->temp_reg
;
1063 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
1065 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1066 alu
.src
[1].chan
= 0;
1067 alu
.src
[1].value
= *(uint32_t *)&half_inv_pi
;
1068 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
1069 alu
.src
[2].chan
= 0;
1071 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1075 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1076 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
1079 alu
.dst
.sel
= ctx
->temp_reg
;
1082 alu
.src
[0].sel
= ctx
->temp_reg
;
1083 alu
.src
[0].chan
= 0;
1085 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1089 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1090 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1094 alu
.dst
.sel
= ctx
->temp_reg
;
1097 alu
.src
[0].sel
= ctx
->temp_reg
;
1098 alu
.src
[0].chan
= 0;
1100 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1101 alu
.src
[1].chan
= 0;
1102 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1103 alu
.src
[2].chan
= 0;
1105 if (ctx
->bc
->chiprev
== CHIPREV_R600
) {
1106 alu
.src
[1].value
= *(uint32_t *)&double_pi
;
1107 alu
.src
[2].value
= *(uint32_t *)&neg_pi
;
1109 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1110 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
1115 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1121 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
1123 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1124 struct r600_bc_alu alu
;
1126 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1128 r
= tgsi_setup_trig(ctx
);
1132 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1133 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1135 alu
.dst
.sel
= ctx
->temp_reg
;
1138 alu
.src
[0].sel
= ctx
->temp_reg
;
1139 alu
.src
[0].chan
= 0;
1141 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1145 /* replicate result */
1146 for (i
= 0; i
< lasti
+ 1; i
++) {
1147 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1150 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1151 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1153 alu
.src
[0].sel
= ctx
->temp_reg
;
1154 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1157 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1164 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
1166 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1167 struct r600_bc_alu alu
;
1170 /* We'll only need the trig stuff if we are going to write to the
1171 * X or Y components of the destination vector.
1173 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
1174 r
= tgsi_setup_trig(ctx
);
1180 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
1181 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1182 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
1183 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1185 alu
.src
[0].sel
= ctx
->temp_reg
;
1186 alu
.src
[0].chan
= 0;
1188 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1194 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
1195 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1196 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
1197 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1199 alu
.src
[0].sel
= ctx
->temp_reg
;
1200 alu
.src
[0].chan
= 0;
1202 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1208 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
1209 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1211 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1213 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1215 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1216 alu
.src
[0].chan
= 0;
1220 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1226 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
1227 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1229 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1231 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1233 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1234 alu
.src
[0].chan
= 0;
1238 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1246 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
1248 struct r600_bc_alu alu
;
1251 for (i
= 0; i
< 4; i
++) {
1252 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1253 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1257 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1259 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILP
) {
1260 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1263 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], i
);
1268 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1273 /* kill must be last in ALU */
1274 ctx
->bc
->force_add_cf
= 1;
1275 ctx
->shader
->uses_kill
= TRUE
;
1279 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
1281 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1282 struct r600_bc_alu alu
;
1286 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1287 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1288 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
1289 alu
.src
[0].chan
= 0;
1290 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1291 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
1292 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1296 /* dst.y = max(src.x, 0.0) */
1297 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1298 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
1299 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
1300 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
1301 alu
.src
[1].chan
= 0;
1302 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1303 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
1304 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1309 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1310 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1311 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1312 alu
.src
[0].chan
= 0;
1313 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1314 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
1316 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1320 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
1325 /* dst.z = log(src.y) */
1326 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1327 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
1328 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 1);
1329 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1331 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1335 chan
= alu
.dst
.chan
;
1338 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1339 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1340 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
);
1341 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 3);
1342 alu
.src
[1].sel
= sel
;
1343 alu
.src
[1].chan
= chan
;
1345 r600_bc_src(&alu
.src
[2], &ctx
->src
[0], 0);
1346 alu
.dst
.sel
= ctx
->temp_reg
;
1351 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1355 /* dst.z = exp(tmp.x) */
1356 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1357 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1358 alu
.src
[0].sel
= ctx
->temp_reg
;
1359 alu
.src
[0].chan
= 0;
1360 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1362 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1369 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
1371 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1372 struct r600_bc_alu alu
;
1375 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1378 * For state trackers other than OpenGL, we'll want to use
1379 * _RECIPSQRT_IEEE instead.
1381 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
);
1383 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1384 r600_bc_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
1387 alu
.dst
.sel
= ctx
->temp_reg
;
1390 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1393 /* replicate result */
1394 return tgsi_helper_tempx_replicate(ctx
);
1397 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
1399 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1400 struct r600_bc_alu alu
;
1403 for (i
= 0; i
< 4; i
++) {
1404 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1405 alu
.src
[0].sel
= ctx
->temp_reg
;
1406 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1408 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1409 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1412 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1419 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
1421 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1422 struct r600_bc_alu alu
;
1425 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1426 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1427 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1428 r600_bc_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
1430 alu
.dst
.sel
= ctx
->temp_reg
;
1433 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1436 /* replicate result */
1437 return tgsi_helper_tempx_replicate(ctx
);
1440 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
1442 struct r600_bc_alu alu
;
1446 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1447 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
1448 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
1449 alu
.dst
.sel
= ctx
->temp_reg
;
1452 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1456 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1457 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1458 r600_bc_src(&alu
.src
[0], &ctx
->src
[1], 0);
1459 alu
.src
[1].sel
= ctx
->temp_reg
;
1460 alu
.dst
.sel
= ctx
->temp_reg
;
1463 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1466 /* POW(a,b) = EXP2(b * LOG2(a))*/
1467 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1468 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1469 alu
.src
[0].sel
= ctx
->temp_reg
;
1470 alu
.dst
.sel
= ctx
->temp_reg
;
1473 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1476 return tgsi_helper_tempx_replicate(ctx
);
1479 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
1481 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1482 struct r600_bc_alu alu
;
1485 /* tmp = (src > 0 ? 1 : src) */
1486 for (i
= 0; i
< 4; i
++) {
1487 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1488 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1491 alu
.dst
.sel
= ctx
->temp_reg
;
1494 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
1495 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1496 r600_bc_src(&alu
.src
[2], &ctx
->src
[0], i
);
1500 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1505 /* dst = (-tmp > 0 ? -1 : tmp) */
1506 for (i
= 0; i
< 4; i
++) {
1507 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1508 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1510 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1512 alu
.src
[0].sel
= ctx
->temp_reg
;
1513 alu
.src
[0].chan
= i
;
1516 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1519 alu
.src
[2].sel
= ctx
->temp_reg
;
1520 alu
.src
[2].chan
= i
;
1524 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1531 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
1533 struct r600_bc_alu alu
;
1536 for (i
= 0; i
< 4; i
++) {
1537 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1538 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
1539 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
1542 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1543 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1544 alu
.src
[0].sel
= ctx
->temp_reg
;
1545 alu
.src
[0].chan
= i
;
1550 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1557 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
1559 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1560 struct r600_bc_alu alu
;
1562 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1564 for (i
= 0; i
< lasti
+ 1; i
++) {
1565 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1568 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1569 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1570 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1571 r600_bc_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
1574 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1581 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1588 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
1590 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1591 struct r600_bc_alu alu
;
1594 for (i
= 0; i
< 4; i
++) {
1595 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1596 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1597 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1598 r600_bc_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
1601 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1603 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1604 /* handle some special cases */
1605 switch (ctx
->inst_info
->tgsi_opcode
) {
1606 case TGSI_OPCODE_DP2
:
1608 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1609 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1612 case TGSI_OPCODE_DP3
:
1614 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1615 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1618 case TGSI_OPCODE_DPH
:
1620 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1621 alu
.src
[0].chan
= 0;
1631 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1638 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1640 static float one_point_five
= 1.5f
;
1641 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1642 struct r600_bc_tex tex
;
1643 struct r600_bc_alu alu
;
1647 boolean src_not_temp
=
1648 inst
->Src
[0].Register
.File
!= TGSI_FILE_TEMPORARY
&&
1649 inst
->Src
[0].Register
.File
!= TGSI_FILE_INPUT
;
1651 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1653 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1654 /* Add perspective divide */
1655 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1656 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1657 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 3);
1659 alu
.dst
.sel
= ctx
->temp_reg
;
1663 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1667 for (i
= 0; i
< 3; i
++) {
1668 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1669 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1670 alu
.src
[0].sel
= ctx
->temp_reg
;
1671 alu
.src
[0].chan
= 3;
1672 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], i
);
1673 alu
.dst
.sel
= ctx
->temp_reg
;
1676 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1680 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1681 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1682 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1683 alu
.src
[0].chan
= 0;
1684 alu
.dst
.sel
= ctx
->temp_reg
;
1688 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1691 src_not_temp
= FALSE
;
1692 src_gpr
= ctx
->temp_reg
;
1695 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1696 int src_chan
, src2_chan
;
1698 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1699 for (i
= 0; i
< 4; i
++) {
1700 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1701 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
);
1725 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], src_chan
);
1726 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], src2_chan
);
1727 alu
.dst
.sel
= ctx
->temp_reg
;
1732 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1737 /* tmp1.z = RCP_e(|tmp1.z|) */
1738 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1739 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1740 alu
.src
[0].sel
= ctx
->temp_reg
;
1741 alu
.src
[0].chan
= 2;
1743 alu
.dst
.sel
= ctx
->temp_reg
;
1747 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1751 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1752 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1753 * muladd has no writemask, have to use another temp
1755 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1756 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1759 alu
.src
[0].sel
= ctx
->temp_reg
;
1760 alu
.src
[0].chan
= 0;
1761 alu
.src
[1].sel
= ctx
->temp_reg
;
1762 alu
.src
[1].chan
= 2;
1764 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1765 alu
.src
[2].chan
= 0;
1766 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
1768 alu
.dst
.sel
= ctx
->temp_reg
;
1772 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1776 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1777 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1780 alu
.src
[0].sel
= ctx
->temp_reg
;
1781 alu
.src
[0].chan
= 1;
1782 alu
.src
[1].sel
= ctx
->temp_reg
;
1783 alu
.src
[1].chan
= 2;
1785 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1786 alu
.src
[2].chan
= 0;
1787 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
1789 alu
.dst
.sel
= ctx
->temp_reg
;
1794 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1798 src_not_temp
= FALSE
;
1799 src_gpr
= ctx
->temp_reg
;
1803 for (i
= 0; i
< 4; i
++) {
1804 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1805 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1806 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
1807 alu
.dst
.sel
= ctx
->temp_reg
;
1812 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1816 src_gpr
= ctx
->temp_reg
;
1819 opcode
= ctx
->inst_info
->r600_opcode
;
1820 if (opcode
== SQ_TEX_INST_SAMPLE
&&
1821 (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
))
1822 opcode
= SQ_TEX_INST_SAMPLE_C
;
1824 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1826 tex
.sampler_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1827 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
1828 tex
.src_gpr
= src_gpr
;
1829 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1830 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
1831 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
1832 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
1833 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
1839 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1846 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1847 tex
.coord_type_x
= 1;
1848 tex
.coord_type_y
= 1;
1849 tex
.coord_type_z
= 1;
1850 tex
.coord_type_w
= 1;
1853 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
) {
1854 tex
.coord_type_z
= 0;
1856 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
)
1857 tex
.coord_type_z
= 0;
1859 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
)
1862 r
= r600_bc_add_tex(ctx
->bc
, &tex
);
1866 /* add shadow ambient support - gallium doesn't do it yet */
1870 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1872 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1873 struct r600_bc_alu alu
;
1874 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1878 /* optimize if it's just an equal balance */
1879 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
1880 for (i
= 0; i
< lasti
+ 1; i
++) {
1881 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1884 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1885 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
1886 r600_bc_src(&alu
.src
[0], &ctx
->src
[1], i
);
1887 r600_bc_src(&alu
.src
[1], &ctx
->src
[2], i
);
1889 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1894 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1902 for (i
= 0; i
< lasti
+ 1; i
++) {
1903 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1906 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1907 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
1908 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1909 alu
.src
[0].chan
= 0;
1910 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], i
);
1912 alu
.dst
.sel
= ctx
->temp_reg
;
1918 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1923 /* (1 - src0) * src2 */
1924 for (i
= 0; i
< lasti
+ 1; i
++) {
1925 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1928 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1929 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1930 alu
.src
[0].sel
= ctx
->temp_reg
;
1931 alu
.src
[0].chan
= i
;
1932 r600_bc_src(&alu
.src
[1], &ctx
->src
[2], i
);
1933 alu
.dst
.sel
= ctx
->temp_reg
;
1939 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1944 /* src0 * src1 + (1 - src0) * src2 */
1945 for (i
= 0; i
< lasti
+ 1; i
++) {
1946 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1949 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1950 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1952 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
1953 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], i
);
1954 alu
.src
[2].sel
= ctx
->temp_reg
;
1955 alu
.src
[2].chan
= i
;
1957 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1962 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1969 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
1971 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1972 struct r600_bc_alu alu
;
1974 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1976 for (i
= 0; i
< lasti
+ 1; i
++) {
1977 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1980 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1981 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
);
1982 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
1983 r600_bc_src(&alu
.src
[1], &ctx
->src
[2], i
);
1984 r600_bc_src(&alu
.src
[2], &ctx
->src
[1], i
);
1985 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1991 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1998 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
2000 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2001 struct r600_bc_alu alu
;
2002 uint32_t use_temp
= 0;
2005 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
2008 for (i
= 0; i
< 4; i
++) {
2009 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2010 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2014 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 2);
2017 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2020 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 1);
2023 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2024 alu
.src
[0].chan
= i
;
2029 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], 1);
2032 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], 2);
2035 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], 0);
2038 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2039 alu
.src
[1].chan
= i
;
2042 alu
.dst
.sel
= ctx
->temp_reg
;
2048 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2053 for (i
= 0; i
< 4; i
++) {
2054 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2055 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
2059 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 1);
2062 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 2);
2065 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2068 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2069 alu
.src
[0].chan
= i
;
2074 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], 2);
2077 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], 0);
2080 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], 1);
2083 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2084 alu
.src
[1].chan
= i
;
2087 alu
.src
[2].sel
= ctx
->temp_reg
;
2089 alu
.src
[2].chan
= i
;
2092 alu
.dst
.sel
= ctx
->temp_reg
;
2094 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2100 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2105 return tgsi_helper_copy(ctx
, inst
);
2109 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
2111 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2112 struct r600_bc_alu alu
;
2115 /* result.x = 2^floor(src); */
2116 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
2117 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2119 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2120 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2122 alu
.dst
.sel
= ctx
->temp_reg
;
2126 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2130 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2131 alu
.src
[0].sel
= ctx
->temp_reg
;
2132 alu
.src
[0].chan
= 0;
2134 alu
.dst
.sel
= ctx
->temp_reg
;
2138 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2143 /* result.y = tmp - floor(tmp); */
2144 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
2145 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2147 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
2148 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2150 alu
.dst
.sel
= ctx
->temp_reg
;
2151 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2159 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2164 /* result.z = RoughApprox2ToX(tmp);*/
2165 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
2166 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2167 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2168 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2170 alu
.dst
.sel
= ctx
->temp_reg
;
2176 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2181 /* result.w = 1.0;*/
2182 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
2183 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2185 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2186 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2187 alu
.src
[0].chan
= 0;
2189 alu
.dst
.sel
= ctx
->temp_reg
;
2193 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2197 return tgsi_helper_copy(ctx
, inst
);
2200 static int tgsi_log(struct r600_shader_ctx
*ctx
)
2202 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2203 struct r600_bc_alu alu
;
2206 /* result.x = floor(log2(src)); */
2207 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
2208 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2210 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2211 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2213 alu
.dst
.sel
= ctx
->temp_reg
;
2217 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2221 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2222 alu
.src
[0].sel
= ctx
->temp_reg
;
2223 alu
.src
[0].chan
= 0;
2225 alu
.dst
.sel
= ctx
->temp_reg
;
2230 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2235 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2236 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
2237 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2239 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2240 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2242 alu
.dst
.sel
= ctx
->temp_reg
;
2247 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2251 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2253 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2254 alu
.src
[0].sel
= ctx
->temp_reg
;
2255 alu
.src
[0].chan
= 1;
2257 alu
.dst
.sel
= ctx
->temp_reg
;
2262 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2266 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2268 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2269 alu
.src
[0].sel
= ctx
->temp_reg
;
2270 alu
.src
[0].chan
= 1;
2272 alu
.dst
.sel
= ctx
->temp_reg
;
2277 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2281 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2283 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
2284 alu
.src
[0].sel
= ctx
->temp_reg
;
2285 alu
.src
[0].chan
= 1;
2287 alu
.dst
.sel
= ctx
->temp_reg
;
2292 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2296 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2298 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2300 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2302 alu
.src
[1].sel
= ctx
->temp_reg
;
2303 alu
.src
[1].chan
= 1;
2305 alu
.dst
.sel
= ctx
->temp_reg
;
2310 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2315 /* result.z = log2(src);*/
2316 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
2317 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2319 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2320 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2322 alu
.dst
.sel
= ctx
->temp_reg
;
2327 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2332 /* result.w = 1.0; */
2333 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
2334 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2336 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2337 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2338 alu
.src
[0].chan
= 0;
2340 alu
.dst
.sel
= ctx
->temp_reg
;
2345 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2350 return tgsi_helper_copy(ctx
, inst
);
2353 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
2355 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2356 struct r600_bc_alu alu
;
2359 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2361 switch (inst
->Instruction
.Opcode
) {
2362 case TGSI_OPCODE_ARL
:
2363 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
;
2365 case TGSI_OPCODE_ARR
:
2366 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
2373 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2375 alu
.dst
.sel
= ctx
->ar_reg
;
2377 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2381 /* TODO: Note that the MOVA can be avoided if we never use AR for
2382 * indexing non-CB registers in the current ALU clause. Similarly, we
2383 * need to load AR from ar_reg again if we started a new clause
2384 * between ARL and AR usage. The easy way to do that is to remove
2385 * the MOVA here, and load it for the first AR access after ar_reg
2386 * has been modified in each clause. */
2387 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2388 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
;
2389 alu
.src
[0].sel
= ctx
->ar_reg
;
2390 alu
.src
[0].chan
= 0;
2392 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2397 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
2399 /* TODO from r600c, ar values don't persist between clauses */
2400 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2401 struct r600_bc_alu alu
;
2404 switch (inst
->Instruction
.Opcode
) {
2405 case TGSI_OPCODE_ARL
:
2406 memset(&alu
, 0, sizeof(alu
));
2407 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
;
2408 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2409 alu
.dst
.sel
= ctx
->ar_reg
;
2413 if ((r
= r600_bc_add_alu(ctx
->bc
, &alu
)))
2416 memset(&alu
, 0, sizeof(alu
));
2417 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
2418 alu
.src
[0].sel
= ctx
->ar_reg
;
2419 alu
.dst
.sel
= ctx
->ar_reg
;
2423 if ((r
= r600_bc_add_alu(ctx
->bc
, &alu
)))
2426 case TGSI_OPCODE_ARR
:
2427 memset(&alu
, 0, sizeof(alu
));
2428 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
2429 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2430 alu
.dst
.sel
= ctx
->ar_reg
;
2434 if ((r
= r600_bc_add_alu(ctx
->bc
, &alu
)))
2442 memset(&alu
, 0, sizeof(alu
));
2443 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
;
2444 alu
.src
[0].sel
= ctx
->ar_reg
;
2447 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2450 ctx
->bc
->cf_last
->r6xx_uses_waterfall
= 1;
2454 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
2456 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2457 struct r600_bc_alu alu
;
2460 for (i
= 0; i
< 4; i
++) {
2461 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2463 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2464 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2466 if (i
== 0 || i
== 3) {
2467 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2469 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
2472 if (i
== 0 || i
== 2) {
2473 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
2475 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], i
);
2479 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2486 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
2488 struct r600_bc_alu alu
;
2491 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2495 alu
.dst
.sel
= ctx
->temp_reg
;
2499 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2500 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2501 alu
.src
[1].chan
= 0;
2505 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
2511 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
2514 if (ctx
->bc
->cf_last
) {
2515 if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
) << 3)
2517 else if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
) << 3)
2522 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
) << 3;
2523 ctx
->bc
->force_add_cf
= 1;
2524 } else if (alu_pop
== 2) {
2525 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
) << 3;
2526 ctx
->bc
->force_add_cf
= 1;
2528 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP
));
2529 ctx
->bc
->cf_last
->pop_count
= pops
;
2530 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2535 static inline void callstack_decrease_current(struct r600_shader_ctx
*ctx
, unsigned reason
)
2539 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2543 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
-= 4;
2546 /* TOODO : for 16 vp asic should -= 2; */
2547 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2552 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
)
2554 if (check_max_only
) {
2567 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
) >
2568 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2569 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2570 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
;
2576 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2580 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+= 4;
2583 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2587 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
) >
2588 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2589 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2590 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
;
2594 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
2596 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
2598 sp
->mid
= (struct r600_bc_cf
**)realloc((void *)sp
->mid
,
2599 sizeof(struct r600_bc_cf
*) * (sp
->num_mid
+ 1));
2600 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
2604 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
2607 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
2608 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
2611 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
2613 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
2625 static int emit_return(struct r600_shader_ctx
*ctx
)
2627 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_RETURN
);
2631 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
2634 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_JUMP
);
2635 ctx
->bc
->cf_last
->pop_count
= pops
;
2636 /* TODO work out offset */
2640 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
2645 static void emit_testflag(struct r600_shader_ctx
*ctx
)
2650 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
2653 emit_jump_to_offset(ctx
, 1, 4);
2654 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
2655 pops(ctx
, ifidx
+ 1);
2659 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
2663 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2664 ctx
->bc
->cf_last
->pop_count
= 1;
2666 fc_set_mid(ctx
, fc_sp
);
2672 static int tgsi_if(struct r600_shader_ctx
*ctx
)
2674 emit_logic_pred(ctx
, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
));
2676 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
2678 fc_pushlevel(ctx
, FC_IF
);
2680 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
2684 static int tgsi_else(struct r600_shader_ctx
*ctx
)
2686 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE
));
2687 ctx
->bc
->cf_last
->pop_count
= 1;
2689 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
2690 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
2694 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
2697 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
2698 R600_ERR("if/endif unbalanced in shader\n");
2702 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
2703 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2704 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
2706 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2710 callstack_decrease_current(ctx
, FC_PUSH_VPM
);
2714 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
2716 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
));
2718 fc_pushlevel(ctx
, FC_LOOP
);
2720 /* check stack depth */
2721 callstack_check_depth(ctx
, FC_LOOP
, 0);
2725 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
2729 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
));
2731 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
2732 R600_ERR("loop/endloop in shader code are not paired.\n");
2736 /* fixup loop pointers - from r600isa
2737 LOOP END points to CF after LOOP START,
2738 LOOP START point to CF after LOOP END
2739 BRK/CONT point to LOOP END CF
2741 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
2743 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2745 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
2746 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
2748 /* TODO add LOOPRET support */
2750 callstack_decrease_current(ctx
, FC_LOOP
);
2754 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
2758 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
2760 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
2765 R600_ERR("Break not inside loop/endloop pair\n");
2769 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2770 ctx
->bc
->cf_last
->pop_count
= 1;
2772 fc_set_mid(ctx
, fscp
);
2775 callstack_check_depth(ctx
, FC_PUSH_VPM
, 1);
2779 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
2780 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
2781 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2782 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
2785 * For state trackers other than OpenGL, we'll want to use
2786 * _RECIP_IEEE instead.
2788 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
2790 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_rsq
},
2791 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
2792 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
2793 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
2794 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2795 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2796 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2797 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
2798 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
2799 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
2800 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
2801 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
2802 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
2803 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2804 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
2805 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2807 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2808 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2810 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2811 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2812 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
2813 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2814 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
2815 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2816 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
2817 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
2818 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
2819 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
2821 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2822 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2823 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2824 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2825 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
2826 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
2827 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
2828 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
2829 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2830 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2831 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2832 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2833 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2834 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
2835 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2836 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
2837 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
2838 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
2839 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
2840 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2841 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2842 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2843 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2844 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2845 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2846 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2847 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2848 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2849 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2850 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
2851 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2852 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2853 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2854 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
2855 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
2856 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
2857 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2858 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2859 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2860 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2861 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2862 {TGSI_OPCODE_BRK
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
2863 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
2865 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2866 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2867 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
2868 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
2870 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2871 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2872 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2873 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2874 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2875 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2876 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2877 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
2878 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2880 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2881 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2882 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2883 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2884 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2885 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2886 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2887 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2888 {TGSI_OPCODE_CONT
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
2889 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2890 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2891 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
2892 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2893 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
2894 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2896 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2897 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2898 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2899 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2900 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2902 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2903 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2904 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2905 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2906 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2907 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2908 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2909 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2910 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
2911 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
2913 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2914 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2915 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2916 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2917 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2918 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2919 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2920 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2921 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2922 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2923 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2924 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2925 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2926 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2927 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2928 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2929 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2930 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2931 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2932 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2933 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2934 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2935 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2936 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2937 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2938 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2939 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2940 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2943 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
2944 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
2945 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2946 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
2947 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
2948 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
2949 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
2950 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2951 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
2952 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2953 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2954 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2955 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
2956 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
2957 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
2958 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
2959 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
2960 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
2961 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2962 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
2963 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2965 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2966 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2968 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2969 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2970 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
2971 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2972 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
2973 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2974 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
2975 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
2976 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
2977 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
2979 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2980 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2981 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2982 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2983 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
2984 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
2985 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
2986 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
2987 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2988 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2989 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2990 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2991 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2992 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
2993 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2994 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
2995 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
2996 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
2997 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
2998 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2999 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3000 {TGSI_OPCODE_TXD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3001 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3002 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3003 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3004 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3005 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3006 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3007 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3008 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
3009 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3010 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3011 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3012 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
3013 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
3014 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
3015 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
3016 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3017 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3018 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3019 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
3020 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
3021 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
3023 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3024 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3025 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
3026 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
3028 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3029 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3030 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3031 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3032 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3033 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3034 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3035 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
3036 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3038 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3039 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3040 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3041 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3042 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3043 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3044 {TGSI_OPCODE_TXF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3045 {TGSI_OPCODE_TXQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3046 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
3047 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3048 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3049 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
3050 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3051 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
3052 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3054 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3055 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3056 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3057 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3058 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3060 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3061 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3062 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3063 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3064 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3065 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3066 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3067 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3068 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
3069 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
3071 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3072 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3073 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3074 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3075 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3076 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3077 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3078 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3079 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3080 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3081 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3082 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3083 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3084 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3085 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3086 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3087 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3088 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3089 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3090 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3091 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3092 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3093 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3094 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3095 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3096 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3097 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3098 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},