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r600g: implememt the LIT instruction
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
31 #include "r600_asm.h"
32 #include "r600_sq.h"
33 #include "r600d.h"
34 #include <stdio.h>
35 #include <errno.h>
36
37 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
38
39 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
40 {
41 struct r600_context *rctx = r600_context(ctx);
42 const struct util_format_description *desc;
43 enum pipe_format resource_format[160];
44 unsigned i, nresources = 0;
45 struct r600_bc *bc = &shader->bc;
46 struct r600_bc_cf *cf;
47 struct r600_bc_vtx *vtx;
48
49 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
50 return 0;
51 for (i = 0; i < rctx->vertex_elements->count; i++) {
52 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
53 }
54 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
55 switch (cf->inst) {
56 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
57 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
58 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
59 desc = util_format_description(resource_format[vtx->buffer_id]);
60 if (desc == NULL) {
61 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
62 return -EINVAL;
63 }
64 vtx->dst_sel_x = desc->swizzle[0];
65 vtx->dst_sel_y = desc->swizzle[1];
66 vtx->dst_sel_z = desc->swizzle[2];
67 vtx->dst_sel_w = desc->swizzle[3];
68 }
69 break;
70 default:
71 break;
72 }
73 }
74 return r600_bc_build(&shader->bc);
75 }
76
77 struct r600_pipe_shader *r600_pipe_shader_create(struct pipe_context *ctx,
78 const struct tgsi_token *tokens)
79 {
80 struct r600_screen *rscreen = r600_screen(ctx->screen);
81 struct r600_pipe_shader *rpshader = CALLOC_STRUCT(r600_pipe_shader);
82 int r;
83
84 fprintf(stderr, "--------------------------------------------------------------\n");
85 tgsi_dump(tokens, 0);
86 if (rpshader == NULL)
87 return NULL;
88 rpshader->shader.family = radeon_get_family(rscreen->rw);
89 r = r600_shader_from_tgsi(tokens, &rpshader->shader);
90 if (r) {
91 R600_ERR("translation from TGSI failed !\n");
92 goto out_err;
93 }
94 r = r600_bc_build(&rpshader->shader.bc);
95 if (r) {
96 R600_ERR("building bytecode failed !\n");
97 goto out_err;
98 }
99 fprintf(stderr, "______________________________________________________________\n");
100 return rpshader;
101 out_err:
102 free(rpshader);
103 return NULL;
104 }
105
106 static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
107 {
108 struct r600_screen *rscreen = r600_screen(ctx->screen);
109 struct r600_shader *rshader = &rpshader->shader;
110 struct radeon_state *state;
111 unsigned i, j, tmp;
112
113 rpshader->state = radeon_state_decref(rpshader->state);
114 state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
115 if (state == NULL)
116 return -ENOMEM;
117 for (i = 0; i < 10; i++) {
118 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
119 }
120 for (i = 0, j = 0; i < rshader->noutput; i++) {
121 if (rshader->output[i].name != TGSI_SEMANTIC_POSITION) {
122 tmp = rshader->output[i].sid << ((j & 3) * 8);
123 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + j / 4] |= tmp;
124 j++;
125 }
126 }
127 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
128 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
129 rpshader->state = state;
130 rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
131 rpshader->state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
132 rpshader->state->nbo = 2;
133 rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
134 return radeon_state_pm4(state);
135 }
136
137 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
138 {
139 struct r600_screen *rscreen = r600_screen(ctx->screen);
140 struct r600_shader *rshader = &rpshader->shader;
141 struct radeon_state *state;
142 unsigned i, tmp;
143
144 rpshader->state = radeon_state_decref(rpshader->state);
145 state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
146 if (state == NULL)
147 return -ENOMEM;
148 for (i = 0; i < rshader->ninput; i++) {
149 tmp = S_028644_SEMANTIC(rshader->input[i].sid);
150 tmp |= S_028644_SEL_CENTROID(1);
151 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
152 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
153 }
154 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
155 S_0286CC_PERSP_GRADIENT_ENA(1);
156 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
157 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
158 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
159 rpshader->state = state;
160 rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
161 rpshader->state->nbo = 1;
162 rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
163 return radeon_state_pm4(state);
164 }
165
166 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
167 {
168 struct r600_screen *rscreen = r600_screen(ctx->screen);
169 struct r600_context *rctx = r600_context(ctx);
170 struct r600_shader *rshader = &rpshader->shader;
171 int r;
172
173 /* copy new shader */
174 radeon_bo_decref(rscreen->rw, rpshader->bo);
175 rpshader->bo = NULL;
176 rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->bc.ndw * 4,
177 4096, NULL);
178 if (rpshader->bo == NULL) {
179 return -ENOMEM;
180 }
181 radeon_bo_map(rscreen->rw, rpshader->bo);
182 memcpy(rpshader->bo->data, rshader->bc.bytecode, rshader->bc.ndw * 4);
183 radeon_bo_unmap(rscreen->rw, rpshader->bo);
184 /* build state */
185 rshader->flat_shade = rctx->flat_shade;
186 switch (rshader->processor_type) {
187 case TGSI_PROCESSOR_VERTEX:
188 r = r600_pipe_shader_vs(ctx, rpshader);
189 break;
190 case TGSI_PROCESSOR_FRAGMENT:
191 r = r600_pipe_shader_ps(ctx, rpshader);
192 break;
193 default:
194 r = -EINVAL;
195 break;
196 }
197 return r;
198 }
199
200 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
201 {
202 struct r600_context *rctx = r600_context(ctx);
203 int r;
204
205 if (rpshader == NULL)
206 return -EINVAL;
207 /* there should be enough input */
208 if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
209 R600_ERR("%d resources provided, expecting %d\n",
210 rctx->vertex_elements->count, rpshader->shader.bc.nresource);
211 return -EINVAL;
212 }
213 r = r600_shader_update(ctx, &rpshader->shader);
214 if (r)
215 return r;
216 return r600_pipe_shader(ctx, rpshader);
217 }
218
219 struct r600_shader_tgsi_instruction;
220
221 struct r600_shader_ctx {
222 struct tgsi_shader_info info;
223 struct tgsi_parse_context parse;
224 const struct tgsi_token *tokens;
225 unsigned type;
226 unsigned file_offset[TGSI_FILE_COUNT];
227 unsigned temp_reg;
228 struct r600_shader_tgsi_instruction *inst_info;
229 struct r600_bc *bc;
230 struct r600_shader *shader;
231 };
232
233 struct r600_shader_tgsi_instruction {
234 unsigned tgsi_opcode;
235 unsigned is_op3;
236 unsigned r600_opcode;
237 int (*process)(struct r600_shader_ctx *ctx);
238 };
239
240 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
241
242 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
243 {
244 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
245 int j;
246
247 if (i->Instruction.NumDstRegs > 1) {
248 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
249 return -EINVAL;
250 }
251 if (i->Instruction.Saturate) {
252 R600_ERR("staturate unsupported\n");
253 return -EINVAL;
254 }
255 if (i->Instruction.Predicate) {
256 R600_ERR("predicate unsupported\n");
257 return -EINVAL;
258 }
259 if (i->Instruction.Label) {
260 R600_ERR("label unsupported\n");
261 return -EINVAL;
262 }
263 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
264 if (i->Src[j].Register.Indirect ||
265 i->Src[j].Register.Dimension ||
266 i->Src[j].Register.Absolute) {
267 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
268 return -EINVAL;
269 }
270 }
271 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
272 if (i->Dst[j].Register.Indirect || i->Dst[j].Register.Dimension) {
273 R600_ERR("unsupported dst (indirect|dimension)\n");
274 return -EINVAL;
275 }
276 }
277 return 0;
278 }
279
280 static int tgsi_declaration(struct r600_shader_ctx *ctx)
281 {
282 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
283 struct r600_bc_vtx vtx;
284 unsigned i;
285 int r;
286
287 switch (d->Declaration.File) {
288 case TGSI_FILE_INPUT:
289 i = ctx->shader->ninput++;
290 ctx->shader->input[i].name = d->Semantic.Name;
291 ctx->shader->input[i].sid = d->Semantic.Index;
292 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
293 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
294 /* turn input into fetch */
295 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
296 vtx.inst = 0;
297 vtx.fetch_type = 0;
298 vtx.buffer_id = i;
299 /* register containing the index into the buffer */
300 vtx.src_gpr = 0;
301 vtx.src_sel_x = 0;
302 vtx.mega_fetch_count = 0x1F;
303 vtx.dst_gpr = ctx->shader->input[i].gpr;
304 vtx.dst_sel_x = 0;
305 vtx.dst_sel_y = 1;
306 vtx.dst_sel_z = 2;
307 vtx.dst_sel_w = 3;
308 r = r600_bc_add_vtx(ctx->bc, &vtx);
309 if (r)
310 return r;
311 }
312 break;
313 case TGSI_FILE_OUTPUT:
314 i = ctx->shader->noutput++;
315 ctx->shader->output[i].name = d->Semantic.Name;
316 ctx->shader->output[i].sid = d->Semantic.Index;
317 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
318 break;
319 case TGSI_FILE_CONSTANT:
320 case TGSI_FILE_TEMPORARY:
321 case TGSI_FILE_SAMPLER:
322 break;
323 default:
324 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
325 return -EINVAL;
326 }
327 return 0;
328 }
329
330 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
331 {
332 struct tgsi_full_immediate *immediate;
333 struct r600_shader_ctx ctx;
334 struct r600_bc_output output;
335 unsigned opcode;
336 int i, r = 0, pos0;
337 u32 value[4];
338
339 ctx.bc = &shader->bc;
340 ctx.shader = shader;
341 r = r600_bc_init(ctx.bc, shader->family);
342 if (r)
343 return r;
344 ctx.tokens = tokens;
345 tgsi_scan_shader(tokens, &ctx.info);
346 tgsi_parse_init(&ctx.parse, tokens);
347 ctx.type = ctx.parse.FullHeader.Processor.Processor;
348 shader->processor_type = ctx.type;
349
350 /* register allocations */
351 /* Values [0,127] correspond to GPR[0..127].
352 * Values [256,511] correspond to cfile constants c[0..255].
353 * Other special values are shown in the list below.
354 * 248 SQ_ALU_SRC_0: special constant 0.0.
355 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
356 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
357 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
358 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
359 * 253 SQ_ALU_SRC_LITERAL: literal constant.
360 * 254 SQ_ALU_SRC_PV: previous vector result.
361 * 255 SQ_ALU_SRC_PS: previous scalar result.
362 */
363 for (i = 0; i < TGSI_FILE_COUNT; i++) {
364 ctx.file_offset[i] = 0;
365 }
366 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
367 ctx.file_offset[TGSI_FILE_INPUT] = 1;
368 }
369 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
370 ctx.info.file_count[TGSI_FILE_INPUT];
371 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
372 ctx.info.file_count[TGSI_FILE_OUTPUT];
373 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
374 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
375 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
376 ctx.info.file_count[TGSI_FILE_TEMPORARY];
377
378 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
379 tgsi_parse_token(&ctx.parse);
380 switch (ctx.parse.FullToken.Token.Type) {
381 case TGSI_TOKEN_TYPE_IMMEDIATE:
382 immediate = &ctx.parse.FullToken.FullImmediate;
383 value[0] = immediate->u[0].Uint;
384 value[1] = immediate->u[1].Uint;
385 value[2] = immediate->u[2].Uint;
386 value[3] = immediate->u[3].Uint;
387 break;
388 case TGSI_TOKEN_TYPE_DECLARATION:
389 r = tgsi_declaration(&ctx);
390 if (r)
391 goto out_err;
392 break;
393 case TGSI_TOKEN_TYPE_INSTRUCTION:
394 r = tgsi_is_supported(&ctx);
395 if (r)
396 goto out_err;
397 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
398 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
399 r = ctx.inst_info->process(&ctx);
400 if (r)
401 goto out_err;
402 r = r600_bc_add_literal(ctx.bc, value);
403 if (r)
404 goto out_err;
405 break;
406 default:
407 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
408 r = -EINVAL;
409 goto out_err;
410 }
411 }
412 /* export output */
413 for (i = 0, pos0 = 0; i < shader->noutput; i++) {
414 memset(&output, 0, sizeof(struct r600_bc_output));
415 output.gpr = shader->output[i].gpr;
416 output.elem_size = 3;
417 output.swizzle_x = 0;
418 output.swizzle_y = 1;
419 output.swizzle_z = 2;
420 output.swizzle_w = 3;
421 output.barrier = 1;
422 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
423 output.array_base = i - pos0;
424 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
425 switch (ctx.type == TGSI_PROCESSOR_VERTEX) {
426 case TGSI_PROCESSOR_VERTEX:
427 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
428 output.array_base = 60;
429 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
430 /* position doesn't count in array_base */
431 pos0 = 1;
432 }
433 break;
434 case TGSI_PROCESSOR_FRAGMENT:
435 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
436 output.array_base = 0;
437 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
438 } else {
439 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
440 r = -EINVAL;
441 goto out_err;
442 }
443 break;
444 default:
445 R600_ERR("unsupported processor type %d\n", ctx.type);
446 r = -EINVAL;
447 goto out_err;
448 }
449 if (i == (shader->noutput - 1)) {
450 output.end_of_program = 1;
451 }
452 r = r600_bc_add_output(ctx.bc, &output);
453 if (r)
454 goto out_err;
455 }
456 tgsi_parse_free(&ctx.parse);
457 return 0;
458 out_err:
459 tgsi_parse_free(&ctx.parse);
460 return r;
461 }
462
463 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
464 {
465 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
466 return -EINVAL;
467 }
468
469 static int tgsi_end(struct r600_shader_ctx *ctx)
470 {
471 return 0;
472 }
473
474 static int tgsi_src(struct r600_shader_ctx *ctx,
475 const struct tgsi_full_src_register *tgsi_src,
476 unsigned swizzle,
477 struct r600_bc_alu_src *r600_src)
478 {
479 r600_src->sel = tgsi_src->Register.Index;
480 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
481 r600_src->sel = 0;
482 }
483 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
484 switch (swizzle) {
485 case 0:
486 r600_src->chan = tgsi_src->Register.SwizzleX;
487 break;
488 case 1:
489 r600_src->chan = tgsi_src->Register.SwizzleY;
490 break;
491 case 2:
492 r600_src->chan = tgsi_src->Register.SwizzleZ;
493 break;
494 case 3:
495 r600_src->chan = tgsi_src->Register.SwizzleW;
496 break;
497 default:
498 return -EINVAL;
499 }
500 return 0;
501 }
502
503 static int tgsi_dst(struct r600_shader_ctx *ctx,
504 const struct tgsi_full_dst_register *tgsi_dst,
505 unsigned swizzle,
506 struct r600_bc_alu_dst *r600_dst)
507 {
508 r600_dst->sel = tgsi_dst->Register.Index;
509 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
510 r600_dst->chan = swizzle;
511 r600_dst->write = 1;
512 return 0;
513 }
514
515 static int tgsi_op2(struct r600_shader_ctx *ctx)
516 {
517 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
518 struct r600_bc_alu alu;
519 int i, j, r;
520
521 for (i = 0; i < 4; i++) {
522 memset(&alu, 0, sizeof(struct r600_bc_alu));
523 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
524 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
525 } else {
526 alu.inst = ctx->inst_info->r600_opcode;
527 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
528 r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
529 if (r)
530 return r;
531 }
532 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
533 if (r)
534 return r;
535 }
536 /* handle some special cases */
537 switch (ctx->inst_info->tgsi_opcode) {
538 case TGSI_OPCODE_SUB:
539 alu.src[1].neg = 1;
540 break;
541 default:
542 break;
543 }
544 if (i == 3) {
545 alu.last = 1;
546 }
547 r = r600_bc_add_alu(ctx->bc, &alu);
548 if (r)
549 return r;
550 }
551 return 0;
552 }
553
554 static int tgsi_slt(struct r600_shader_ctx *ctx)
555 {
556 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
557 struct r600_bc_alu alu;
558 int i, r;
559
560 for (i = 0; i < 4; i++) {
561 memset(&alu, 0, sizeof(struct r600_bc_alu));
562 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
563 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
564 } else {
565 alu.inst = ctx->inst_info->r600_opcode;
566 r = tgsi_src(ctx, &inst->Src[0], i, &alu.src[1]);
567 if (r)
568 return r;
569 r = tgsi_src(ctx, &inst->Src[1], i, &alu.src[0]);
570 if (r)
571 return r;
572 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
573 if (r)
574 return r;
575 }
576 if (i == 3) {
577 alu.last = 1;
578 }
579 r = r600_bc_add_alu(ctx->bc, &alu);
580 if (r)
581 return r;
582 }
583 return 0;
584 }
585
586 static int tgsi_lit(struct r600_shader_ctx *ctx)
587 {
588 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
589 struct r600_bc_alu alu;
590
591 int r;
592
593
594 if (inst->Dst[0].Register.WriteMask & (1 << 0))
595 {
596 /* dst.x, <- 1.0 */
597 memset(&alu, 0, sizeof(struct r600_bc_alu));
598 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
599 alu.src[0].sel = 249; /*1.0*/
600 alu.src[0].chan = 0;
601 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
602 if (r)
603 return r;
604 if ((inst->Dst[0].Register.WriteMask & 0xe) == 0)
605 alu.last = 1;
606 r = r600_bc_add_alu(ctx->bc, &alu);
607 if (r)
608 return r;
609 }
610
611
612 if (inst->Dst[0].Register.WriteMask & (1 << 1))
613 {
614 /* dst.y = max(src.x, 0.0) */
615 memset(&alu, 0, sizeof(struct r600_bc_alu));
616 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX;
617 r = tgsi_src(ctx, &inst->Src[0], 0, &alu.src[0]);
618 if (r)
619 return r;
620 alu.src[1].sel = 248; /*0.0*/
621 alu.src[1].chan = 0;
622 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
623 if (r)
624 return r;
625 if ((inst->Dst[0].Register.WriteMask & 0xa) == 0)
626 alu.last = 1;
627 r = r600_bc_add_alu(ctx->bc, &alu);
628 if (r)
629 return r;
630 }
631
632 if (inst->Dst[0].Register.WriteMask & (1 << 3))
633 {
634 /* dst.w, <- 1.0 */
635 memset(&alu, 0, sizeof(struct r600_bc_alu));
636 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
637 alu.src[0].sel = 249;
638 alu.src[0].chan = 0;
639 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
640 if (r)
641 return r;
642 if ((inst->Dst[0].Register.WriteMask & 0x4) == 0)
643 alu.last = 1;
644 r = r600_bc_add_alu(ctx->bc, &alu);
645 if (r)
646 return r;
647 }
648
649 if (inst->Dst[0].Register.WriteMask & (1 << 2))
650 {
651 /* dst.z = log(src.y) */
652 memset(&alu, 0, sizeof(struct r600_bc_alu));
653 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED;
654 r = tgsi_src(ctx, &inst->Src[0], 1, &alu.src[0]);
655 if (r)
656 return r;
657 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
658 if (r)
659 return r;
660 alu.last = 1;
661 r = r600_bc_add_alu(ctx->bc, &alu);
662 if (r)
663 return r;
664
665 int chan = alu.dst.chan;
666 int sel = alu.dst.sel;
667
668 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
669 memset(&alu, 0, sizeof(struct r600_bc_alu));
670 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
671 r = tgsi_src(ctx, &inst->Src[0], 3, &alu.src[0]);
672 if (r)
673 return r;
674 alu.src[1].sel = sel;
675 alu.src[1].chan = chan;
676 r = tgsi_src(ctx, &inst->Src[0], 0, &alu.src[2]);
677 if (r)
678 return r;
679 alu.dst.sel = ctx->temp_reg;
680 alu.dst.chan = 0;
681 alu.dst.write = 1;
682 alu.is_op3 = 1;
683 alu.last = 1;
684 r = r600_bc_add_alu(ctx->bc, &alu);
685 if (r)
686 return r;
687
688 /* dst.z = exp(tmp.x) */
689 memset(&alu, 0, sizeof(struct r600_bc_alu));
690 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
691 alu.src[0].sel = ctx->temp_reg;
692 alu.src[0].chan = 0;
693 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
694 if (r)
695 return r;
696 alu.last = 1;
697 r = r600_bc_add_alu(ctx->bc, &alu);
698 if (r)
699 return r;
700 }
701 return 0;
702 }
703
704 static int tgsi_trans(struct r600_shader_ctx *ctx)
705 {
706 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
707 struct r600_bc_alu alu;
708 int i, j, r;
709
710 for (i = 0; i < 4; i++) {
711 memset(&alu, 0, sizeof(struct r600_bc_alu));
712 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
713 alu.inst = ctx->inst_info->r600_opcode;
714 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
715 r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
716 if (r)
717 return r;
718 }
719 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
720 if (r)
721 return r;
722 alu.last = 1;
723 r = r600_bc_add_alu(ctx->bc, &alu);
724 if (r)
725 return r;
726 }
727 }
728 return 0;
729 }
730
731 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
732 {
733 struct r600_bc_alu alu;
734 int i, r;
735
736 for (i = 0; i < 4; i++) {
737 memset(&alu, 0, sizeof(struct r600_bc_alu));
738 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
739 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
740 } else {
741 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
742 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
743 if (r)
744 return r;
745 alu.src[0].sel = ctx->temp_reg;
746 alu.src[0].chan = i;
747 }
748 if (i == 3) {
749 alu.last = 1;
750 }
751 r = r600_bc_add_alu(ctx->bc, &alu);
752 if (r)
753 return r;
754 }
755 return 0;
756 }
757
758 static int tgsi_op3(struct r600_shader_ctx *ctx)
759 {
760 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
761 struct r600_bc_alu alu;
762 int i, j, r;
763
764 /* do it in 2 step as op3 doesn't support writemask */
765 for (i = 0; i < 4; i++) {
766 memset(&alu, 0, sizeof(struct r600_bc_alu));
767 alu.inst = ctx->inst_info->r600_opcode;
768 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
769 r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
770 if (r)
771 return r;
772 }
773 alu.dst.sel = ctx->temp_reg;
774 alu.dst.chan = i;
775 alu.dst.write = 1;
776 alu.is_op3 = 1;
777 if (i == 3) {
778 alu.last = 1;
779 }
780 r = r600_bc_add_alu(ctx->bc, &alu);
781 if (r)
782 return r;
783 }
784 return tgsi_helper_copy(ctx, inst);
785 }
786
787 static int tgsi_dp(struct r600_shader_ctx *ctx)
788 {
789 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
790 struct r600_bc_alu alu;
791 int i, j, r;
792
793 for (i = 0; i < 4; i++) {
794 memset(&alu, 0, sizeof(struct r600_bc_alu));
795 alu.inst = ctx->inst_info->r600_opcode;
796 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
797 r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
798 if (r)
799 return r;
800 }
801 alu.dst.sel = ctx->temp_reg;
802 alu.dst.chan = i;
803 alu.dst.write = 1;
804 /* handle some special cases */
805 switch (ctx->inst_info->tgsi_opcode) {
806 case TGSI_OPCODE_DP2:
807 if (i > 1) {
808 alu.src[0].sel = alu.src[1].sel = 248;
809 alu.src[0].chan = alu.src[1].chan = 0;
810 }
811 break;
812 case TGSI_OPCODE_DP3:
813 if (i > 2) {
814 alu.src[0].sel = alu.src[1].sel = 248;
815 alu.src[0].chan = alu.src[1].chan = 0;
816 }
817 break;
818 default:
819 break;
820 }
821 if (i == 3) {
822 alu.last = 1;
823 }
824 r = r600_bc_add_alu(ctx->bc, &alu);
825 if (r)
826 return r;
827 }
828 return tgsi_helper_copy(ctx, inst);
829 }
830
831 static int tgsi_tex(struct r600_shader_ctx *ctx)
832 {
833 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
834 struct r600_bc_tex tex;
835
836 memset(&tex, 0, sizeof(struct r600_bc_tex));
837 tex.inst = ctx->inst_info->r600_opcode;
838 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
839 tex.sampler_id = tex.resource_id;
840 tex.src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
841 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Src[0].Register.Index;
842 tex.dst_sel_x = 0;
843 tex.dst_sel_y = 1;
844 tex.dst_sel_z = 2;
845 tex.dst_sel_w = 3;
846 tex.src_sel_x = 0;
847 tex.src_sel_y = 1;
848 tex.src_sel_z = 2;
849 tex.src_sel_w = 3;
850 return r600_bc_add_tex(ctx->bc, &tex);
851 }
852
853 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
854 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
855 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
856 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
857 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
858 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans},
859 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
860 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
861 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
862 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
863 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
864 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
865 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
866 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
867 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
868 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_slt},
869 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
870 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
871 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
872 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
873 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
874 /* gap */
875 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
876 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
877 /* gap */
878 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
879 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
880 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
881 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
882 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
883 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
884 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
885 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
886 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
887 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
888 /* gap */
889 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
890 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
891 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
892 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
893 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
894 {TGSI_OPCODE_DDX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
895 {TGSI_OPCODE_DDY, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
896 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* predicated kill */
897 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
898 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
899 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
900 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
901 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
902 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
903 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
904 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
905 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
906 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
907 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
908 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
909 {TGSI_OPCODE_TEX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
910 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
911 {TGSI_OPCODE_TXP, 0, 0x10, tgsi_tex},
912 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
913 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
914 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
915 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
916 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
917 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
918 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
919 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
920 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
921 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
922 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* SGN */
923 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
924 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
925 {TGSI_OPCODE_TXB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
926 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
927 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
928 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
929 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
930 {TGSI_OPCODE_BRK, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
931 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
932 /* gap */
933 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
934 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
935 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
936 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
937 /* gap */
938 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
939 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
940 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
941 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
942 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
943 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
944 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
945 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
946 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
947 /* gap */
948 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
949 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
950 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
951 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
952 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
953 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
954 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
955 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
956 {TGSI_OPCODE_CONT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
957 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
958 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
959 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
960 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
961 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
962 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
963 /* gap */
964 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
965 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
966 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
967 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
968 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
969 /* gap */
970 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
971 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
972 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
973 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
974 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
975 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
976 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
977 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
978 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* conditional kill */
979 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
980 /* gap */
981 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
982 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
983 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
984 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
985 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
986 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
987 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
988 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
989 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
990 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
991 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
992 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
993 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
994 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
995 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
996 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
997 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
998 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
999 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1000 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1001 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1002 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1003 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1004 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1005 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1006 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1007 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1008 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1009 };