2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
31 #include "r600_opcodes.h"
36 static void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
38 struct r600_pipe_state
*rstate
= &shader
->rstate
;
39 struct r600_shader
*rshader
= &shader
->shader
;
40 unsigned spi_vs_out_id
[10];
43 /* clear previous register */
46 /* so far never got proper semantic id from tgsi */
47 for (i
= 0; i
< 10; i
++) {
50 for (i
= 0; i
< 32; i
++) {
51 tmp
= i
<< ((i
& 3) * 8);
52 spi_vs_out_id
[i
/ 4] |= tmp
;
54 for (i
= 0; i
< 10; i
++) {
55 r600_pipe_state_add_reg(rstate
,
56 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
57 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
);
60 r600_pipe_state_add_reg(rstate
,
61 R_0286C4_SPI_VS_OUT_CONFIG
,
62 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2),
64 r600_pipe_state_add_reg(rstate
,
65 R_028868_SQ_PGM_RESOURCES_VS
,
66 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
67 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
69 r600_pipe_state_add_reg(rstate
,
70 R_0288A4_SQ_PGM_RESOURCES_FS
,
71 0x00000000, 0xFFFFFFFF, NULL
);
72 r600_pipe_state_add_reg(rstate
,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS
,
74 0x00000000, 0xFFFFFFFF, NULL
);
75 r600_pipe_state_add_reg(rstate
,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS
,
77 0x00000000, 0xFFFFFFFF, NULL
);
78 r600_pipe_state_add_reg(rstate
,
79 R_028858_SQ_PGM_START_VS
,
80 0x00000000, 0xFFFFFFFF, shader
->bo
);
81 r600_pipe_state_add_reg(rstate
,
82 R_028894_SQ_PGM_START_FS
,
83 0x00000000, 0xFFFFFFFF, shader
->bo
);
86 int r600_find_vs_semantic_index2(struct r600_shader
*vs
,
87 struct r600_shader
*ps
, int id
)
89 struct r600_shader_io
*input
= &ps
->input
[id
];
91 for (int i
= 0; i
< vs
->noutput
; i
++) {
92 if (input
->name
== vs
->output
[i
].name
&&
93 input
->sid
== vs
->output
[i
].sid
) {
100 static void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
102 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
103 struct r600_pipe_state
*rstate
= &shader
->rstate
;
104 struct r600_shader
*rshader
= &shader
->shader
;
105 unsigned i
, tmp
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
;
106 boolean have_pos
= FALSE
, have_face
= FALSE
;
108 /* clear previous register */
111 for (i
= 0; i
< rshader
->ninput
; i
++) {
112 tmp
= S_028644_SEMANTIC(r600_find_vs_semantic_index2(&rctx
->vs_shader
->shader
, rshader
, i
));
113 tmp
|= S_028644_SEL_CENTROID(1);
114 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
116 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
117 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
||
118 rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
) {
119 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
121 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
123 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
124 rctx
->sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
125 tmp
|= S_028644_PT_SPRITE_TEX(1);
127 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4, tmp
, 0xFFFFFFFF, NULL
);
129 for (i
= 0; i
< rshader
->noutput
; i
++) {
130 r600_pipe_state_add_reg(rstate
,
131 R_02880C_DB_SHADER_CONTROL
,
132 S_02880C_Z_EXPORT_ENABLE(1),
133 S_02880C_Z_EXPORT_ENABLE(1), NULL
);
138 for (i
= 0; i
< rshader
->noutput
; i
++) {
139 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
141 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
145 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
147 /* always at least export 1 component per pixel */
151 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
152 S_0286CC_PERSP_GRADIENT_ENA(1);
155 spi_ps_in_control_0
|= S_0286CC_POSITION_ENA(1) |
156 S_0286CC_BARYC_SAMPLE_CNTL(1);
159 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
, 0xFFFFFFFF, NULL
);
160 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, S_0286D0_FRONT_FACE_ENA(have_face
), 0xFFFFFFFF, NULL
);
161 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
);
162 r600_pipe_state_add_reg(rstate
,
163 R_028840_SQ_PGM_START_PS
,
164 0x00000000, 0xFFFFFFFF, shader
->bo
);
165 r600_pipe_state_add_reg(rstate
,
166 R_028850_SQ_PGM_RESOURCES_PS
,
167 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
168 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
170 r600_pipe_state_add_reg(rstate
,
171 R_028854_SQ_PGM_EXPORTS_PS
,
172 exports_ps
, 0xFFFFFFFF, NULL
);
173 r600_pipe_state_add_reg(rstate
,
174 R_0288CC_SQ_PGM_CF_OFFSET_PS
,
175 0x00000000, 0xFFFFFFFF, NULL
);
177 if (rshader
->uses_kill
) {
178 /* only set some bits here, the other bits are set in the dsa state */
179 r600_pipe_state_add_reg(rstate
,
180 R_02880C_DB_SHADER_CONTROL
,
181 S_02880C_KILL_ENABLE(1),
182 S_02880C_KILL_ENABLE(1), NULL
);
186 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
188 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
189 struct r600_shader
*rshader
= &shader
->shader
;
192 /* copy new shader */
193 if (shader
->bo
== NULL
) {
194 shader
->bo
= radeon_ws_bo(rctx
->radeon
, rshader
->bc
.ndw
* 4, 4096, 0);
195 if (shader
->bo
== NULL
) {
198 ptr
= radeon_ws_bo_map(rctx
->radeon
, shader
->bo
, 0, NULL
);
199 memcpy(ptr
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
200 radeon_ws_bo_unmap(rctx
->radeon
, shader
->bo
);
203 rshader
->flat_shade
= rctx
->flatshade
;
204 switch (rshader
->processor_type
) {
205 case TGSI_PROCESSOR_VERTEX
:
206 if (rshader
->family
>= CHIP_CEDAR
) {
207 evergreen_pipe_shader_vs(ctx
, shader
);
209 r600_pipe_shader_vs(ctx
, shader
);
212 case TGSI_PROCESSOR_FRAGMENT
:
213 if (rshader
->family
>= CHIP_CEDAR
) {
214 evergreen_pipe_shader_ps(ctx
, shader
);
216 r600_pipe_shader_ps(ctx
, shader
);
222 r600_context_pipe_state_set(&rctx
->ctx
, &shader
->rstate
);
226 static int r600_shader_update(struct pipe_context
*ctx
, struct r600_pipe_shader
*rshader
)
228 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
229 struct r600_shader
*shader
= &rshader
->shader
;
230 const struct util_format_description
*desc
;
231 enum pipe_format resource_format
[160];
232 unsigned i
, nresources
= 0;
233 struct r600_bc
*bc
= &shader
->bc
;
234 struct r600_bc_cf
*cf
;
235 struct r600_bc_vtx
*vtx
;
237 if (shader
->processor_type
!= TGSI_PROCESSOR_VERTEX
)
239 if (!memcmp(&rshader
->vertex_elements
, rctx
->vertex_elements
, sizeof(struct r600_vertex_element
))) {
242 rshader
->vertex_elements
= *rctx
->vertex_elements
;
243 for (i
= 0; i
< rctx
->vertex_elements
->count
; i
++) {
244 resource_format
[nresources
++] = rctx
->vertex_elements
->elements
[i
].src_format
;
246 radeon_ws_bo_reference(rctx
->radeon
, &rshader
->bo
, NULL
);
247 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
249 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
250 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
251 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
252 desc
= util_format_description(resource_format
[vtx
->buffer_id
]);
254 R600_ERR("unknown format %d\n", resource_format
[vtx
->buffer_id
]);
257 vtx
->dst_sel_x
= desc
->swizzle
[0];
258 vtx
->dst_sel_y
= desc
->swizzle
[1];
259 vtx
->dst_sel_z
= desc
->swizzle
[2];
260 vtx
->dst_sel_w
= desc
->swizzle
[3];
267 return r600_bc_build(&shader
->bc
);
270 int r600_pipe_shader_update2(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
272 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
277 /* there should be enough input */
278 if (rctx
->vertex_elements
->count
< shader
->shader
.bc
.nresource
) {
279 R600_ERR("%d resources provided, expecting %d\n",
280 rctx
->vertex_elements
->count
, shader
->shader
.bc
.nresource
);
283 r
= r600_shader_update(ctx
, shader
);
286 return r600_pipe_shader(ctx
, shader
);
289 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
290 int r600_pipe_shader_create2(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
, const struct tgsi_token
*tokens
)
292 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
295 //fprintf(stderr, "--------------------------------------------------------------\n");
296 //tgsi_dump(tokens, 0);
297 shader
->shader
.family
= r600_get_family(rctx
->radeon
);
298 r
= r600_shader_from_tgsi(tokens
, &shader
->shader
);
300 R600_ERR("translation from TGSI failed !\n");
303 r
= r600_bc_build(&shader
->shader
.bc
);
305 R600_ERR("building bytecode failed !\n");
308 //fprintf(stderr, "______________________________________________________________\n");
313 * tgsi -> r600 shader
315 struct r600_shader_tgsi_instruction
;
317 struct r600_shader_ctx
{
318 struct tgsi_shader_info info
;
319 struct tgsi_parse_context parse
;
320 const struct tgsi_token
*tokens
;
322 unsigned file_offset
[TGSI_FILE_COUNT
];
324 struct r600_shader_tgsi_instruction
*inst_info
;
326 struct r600_shader
*shader
;
330 u32 max_driver_temp_used
;
333 struct r600_shader_tgsi_instruction
{
334 unsigned tgsi_opcode
;
336 unsigned r600_opcode
;
337 int (*process
)(struct r600_shader_ctx
*ctx
);
340 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[];
341 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
343 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
345 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
348 if (i
->Instruction
.NumDstRegs
> 1) {
349 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
352 if (i
->Instruction
.Predicate
) {
353 R600_ERR("predicate unsupported\n");
357 if (i
->Instruction
.Label
) {
358 R600_ERR("label unsupported\n");
362 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
363 if (i
->Src
[j
].Register
.Dimension
||
364 i
->Src
[j
].Register
.Absolute
) {
365 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j
,
366 i
->Src
[j
].Register
.Dimension
,
367 i
->Src
[j
].Register
.Absolute
);
371 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
372 if (i
->Dst
[j
].Register
.Dimension
) {
373 R600_ERR("unsupported dst (dimension)\n");
380 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int gpr
)
383 struct r600_bc_alu alu
;
385 for (i
= 0; i
< 8; i
++) {
386 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
389 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW
;
391 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY
;
393 if ((i
> 1) && (i
< 6)) {
394 alu
.dst
.sel
= ctx
->shader
->input
[gpr
].gpr
;
398 alu
.dst
.chan
= i
% 4;
399 alu
.src
[0].chan
= (1 - (i
% 2));
400 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ gpr
;
402 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
405 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
413 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
415 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
416 struct r600_bc_vtx vtx
;
420 switch (d
->Declaration
.File
) {
421 case TGSI_FILE_INPUT
:
422 i
= ctx
->shader
->ninput
++;
423 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
424 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
425 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
426 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
427 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
428 /* turn input into fetch */
429 memset(&vtx
, 0, sizeof(struct r600_bc_vtx
));
433 /* register containing the index into the buffer */
436 vtx
.mega_fetch_count
= 0x1F;
437 vtx
.dst_gpr
= ctx
->shader
->input
[i
].gpr
;
442 r
= r600_bc_add_vtx(ctx
->bc
, &vtx
);
446 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
->bc
->chiprev
== 2) {
447 /* turn input into interpolate on EG */
448 evergreen_interp_alu(ctx
, i
);
451 case TGSI_FILE_OUTPUT
:
452 i
= ctx
->shader
->noutput
++;
453 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
454 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
455 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
456 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
458 case TGSI_FILE_CONSTANT
:
459 case TGSI_FILE_TEMPORARY
:
460 case TGSI_FILE_SAMPLER
:
461 case TGSI_FILE_ADDRESS
:
464 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
470 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
472 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
475 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
477 struct tgsi_full_immediate
*immediate
;
478 struct r600_shader_ctx ctx
;
479 struct r600_bc_output output
[32];
480 unsigned output_done
, noutput
;
484 ctx
.bc
= &shader
->bc
;
486 r
= r600_bc_init(ctx
.bc
, shader
->family
);
489 ctx
.bc
->use_mem_constant
= shader
->use_mem_constant
;
491 tgsi_scan_shader(tokens
, &ctx
.info
);
492 tgsi_parse_init(&ctx
.parse
, tokens
);
493 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
494 shader
->processor_type
= ctx
.type
;
496 /* register allocations */
497 /* Values [0,127] correspond to GPR[0..127].
498 * Values [128,159] correspond to constant buffer bank 0
499 * Values [160,191] correspond to constant buffer bank 1
500 * Values [256,511] correspond to cfile constants c[0..255].
501 * Other special values are shown in the list below.
502 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
503 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
504 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
505 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
506 * 248 SQ_ALU_SRC_0: special constant 0.0.
507 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
508 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
509 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
510 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
511 * 253 SQ_ALU_SRC_LITERAL: literal constant.
512 * 254 SQ_ALU_SRC_PV: previous vector result.
513 * 255 SQ_ALU_SRC_PS: previous scalar result.
515 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
516 ctx
.file_offset
[i
] = 0;
518 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
519 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
521 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
522 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
523 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
524 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
525 if (ctx
.shader
->use_mem_constant
)
526 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 128;
528 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 256;
530 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = 253;
531 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
532 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
537 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
538 tgsi_parse_token(&ctx
.parse
);
539 switch (ctx
.parse
.FullToken
.Token
.Type
) {
540 case TGSI_TOKEN_TYPE_IMMEDIATE
:
541 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
542 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
543 if(ctx
.literals
== NULL
) {
547 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
548 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
549 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
550 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
553 case TGSI_TOKEN_TYPE_DECLARATION
:
554 r
= tgsi_declaration(&ctx
);
558 case TGSI_TOKEN_TYPE_INSTRUCTION
:
559 r
= tgsi_is_supported(&ctx
);
562 ctx
.max_driver_temp_used
= 0;
563 /* reserve first tmp for everyone */
565 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
566 if (ctx
.bc
->chiprev
== 2)
567 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
569 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
570 r
= ctx
.inst_info
->process(&ctx
);
573 r
= r600_bc_add_literal(ctx
.bc
, ctx
.value
);
578 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
584 noutput
= shader
->noutput
;
585 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
586 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
587 output
[i
].gpr
= shader
->output
[i
].gpr
;
588 output
[i
].elem_size
= 3;
589 output
[i
].swizzle_x
= 0;
590 output
[i
].swizzle_y
= 1;
591 output
[i
].swizzle_z
= 2;
592 output
[i
].swizzle_w
= 3;
593 output
[i
].barrier
= 1;
594 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
595 output
[i
].array_base
= i
- pos0
;
596 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
598 case TGSI_PROCESSOR_VERTEX
:
599 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
600 output
[i
].array_base
= 60;
601 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
602 /* position doesn't count in array_base */
605 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
606 output
[i
].array_base
= 61;
607 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
608 /* position doesn't count in array_base */
612 case TGSI_PROCESSOR_FRAGMENT
:
613 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
614 output
[i
].array_base
= shader
->output
[i
].sid
;
615 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
616 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
617 output
[i
].array_base
= 61;
618 output
[i
].swizzle_x
= 2;
619 output
[i
].swizzle_y
= output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
620 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
622 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
628 R600_ERR("unsupported processor type %d\n", ctx
.type
);
633 /* add fake param output for vertex shader if no param is exported */
634 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
635 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
636 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
642 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
644 output
[i
].elem_size
= 3;
645 output
[i
].swizzle_x
= 0;
646 output
[i
].swizzle_y
= 1;
647 output
[i
].swizzle_z
= 2;
648 output
[i
].swizzle_w
= 3;
649 output
[i
].barrier
= 1;
650 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
651 output
[i
].array_base
= 0;
652 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
656 /* add fake pixel export */
657 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
658 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
660 output
[0].elem_size
= 3;
661 output
[0].swizzle_x
= 7;
662 output
[0].swizzle_y
= 7;
663 output
[0].swizzle_z
= 7;
664 output
[0].swizzle_w
= 7;
665 output
[0].barrier
= 1;
666 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
667 output
[0].array_base
= 0;
668 output
[0].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
671 /* set export done on last export of each type */
672 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
673 if (i
== (noutput
- 1)) {
674 output
[i
].end_of_program
= 1;
676 if (!(output_done
& (1 << output
[i
].type
))) {
677 output_done
|= (1 << output
[i
].type
);
678 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
);
681 /* add output to bytecode */
682 for (i
= 0; i
< noutput
; i
++) {
683 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
688 tgsi_parse_free(&ctx
.parse
);
692 tgsi_parse_free(&ctx
.parse
);
696 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
698 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
702 static int tgsi_end(struct r600_shader_ctx
*ctx
)
707 static int tgsi_src(struct r600_shader_ctx
*ctx
,
708 const struct tgsi_full_src_register
*tgsi_src
,
709 struct r600_bc_alu_src
*r600_src
)
712 memset(r600_src
, 0, sizeof(struct r600_bc_alu_src
));
713 r600_src
->sel
= tgsi_src
->Register
.Index
;
714 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
716 index
= tgsi_src
->Register
.Index
;
717 ctx
->value
[0] = ctx
->literals
[index
* 4 + 0];
718 ctx
->value
[1] = ctx
->literals
[index
* 4 + 1];
719 ctx
->value
[2] = ctx
->literals
[index
* 4 + 2];
720 ctx
->value
[3] = ctx
->literals
[index
* 4 + 3];
722 if (tgsi_src
->Register
.Indirect
)
723 r600_src
->rel
= V_SQ_REL_RELATIVE
;
724 r600_src
->neg
= tgsi_src
->Register
.Negate
;
725 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
729 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
730 const struct tgsi_full_dst_register
*tgsi_dst
,
732 struct r600_bc_alu_dst
*r600_dst
)
734 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
736 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
737 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
738 r600_dst
->chan
= swizzle
;
740 if (tgsi_dst
->Register
.Indirect
)
741 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
742 if (inst
->Instruction
.Saturate
) {
748 static unsigned tgsi_chan(const struct tgsi_full_src_register
*tgsi_src
, unsigned swizzle
)
752 return tgsi_src
->Register
.SwizzleX
;
754 return tgsi_src
->Register
.SwizzleY
;
756 return tgsi_src
->Register
.SwizzleZ
;
758 return tgsi_src
->Register
.SwizzleW
;
764 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
766 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
767 struct r600_bc_alu alu
;
768 int i
, j
, k
, nconst
, r
;
770 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
771 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
774 r
= tgsi_src(ctx
, &inst
->Src
[i
], &r600_src
[i
]);
779 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
780 if (inst
->Src
[j
].Register
.File
== TGSI_FILE_CONSTANT
&& j
> 0) {
781 int treg
= r600_get_temp(ctx
);
782 for (k
= 0; k
< 4; k
++) {
783 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
784 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
785 alu
.src
[0].sel
= r600_src
[j
].sel
;
792 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
796 r600_src
[j
].sel
= treg
;
803 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
804 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
806 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
807 struct r600_bc_alu alu
;
808 int i
, j
, k
, nliteral
, r
;
810 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
811 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_IMMEDIATE
) {
815 for (i
= 0, j
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
816 if (inst
->Src
[j
].Register
.File
== TGSI_FILE_IMMEDIATE
) {
817 int treg
= r600_get_temp(ctx
);
818 for (k
= 0; k
< 4; k
++) {
819 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
820 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
821 alu
.src
[0].sel
= r600_src
[j
].sel
;
828 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
832 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
835 r600_src
[j
].sel
= treg
;
842 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
)
844 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
845 struct r600_bc_alu_src r600_src
[3];
846 struct r600_bc_alu alu
;
850 for (i
= 0; i
< 4; i
++) {
851 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
856 r
= tgsi_split_constant(ctx
, r600_src
);
859 for (i
= 0; i
< lasti
+ 1; i
++) {
860 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
863 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
864 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
868 alu
.inst
= ctx
->inst_info
->r600_opcode
;
870 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
871 alu
.src
[j
] = r600_src
[j
];
872 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
875 alu
.src
[0] = r600_src
[1];
876 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
878 alu
.src
[1] = r600_src
[0];
879 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
881 /* handle some special cases */
882 switch (ctx
->inst_info
->tgsi_opcode
) {
883 case TGSI_OPCODE_SUB
:
886 case TGSI_OPCODE_ABS
:
895 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
902 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
904 return tgsi_op2_s(ctx
, 0);
907 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
909 return tgsi_op2_s(ctx
, 1);
913 * r600 - trunc to -PI..PI range
914 * r700 - normalize by dividing by 2PI
917 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
,
918 struct r600_bc_alu_src r600_src
[3])
920 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
922 uint32_t lit_vals
[4];
923 struct r600_bc_alu alu
;
925 memset(lit_vals
, 0, 4*4);
926 r
= tgsi_split_constant(ctx
, r600_src
);
930 r
= tgsi_split_literal_constant(ctx
, r600_src
);
934 lit_vals
[0] = fui(1.0 /(3.1415926535 * 2));
935 lit_vals
[1] = fui(0.5f
);
937 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
938 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
942 alu
.dst
.sel
= ctx
->temp_reg
;
945 alu
.src
[0] = r600_src
[0];
946 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
948 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
950 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
953 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
956 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
960 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
961 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
964 alu
.dst
.sel
= ctx
->temp_reg
;
967 alu
.src
[0].sel
= ctx
->temp_reg
;
970 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
974 if (ctx
->bc
->chiprev
== 0) {
975 lit_vals
[0] = fui(3.1415926535897f
* 2.0f
);
976 lit_vals
[1] = fui(-3.1415926535897f
);
978 lit_vals
[0] = fui(1.0f
);
979 lit_vals
[1] = fui(-0.5f
);
982 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
983 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
987 alu
.dst
.sel
= ctx
->temp_reg
;
990 alu
.src
[0].sel
= ctx
->temp_reg
;
993 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
995 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
998 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1001 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
1007 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
1009 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1010 struct r600_bc_alu_src r600_src
[3];
1011 struct r600_bc_alu alu
;
1015 r
= tgsi_setup_trig(ctx
, r600_src
);
1019 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1020 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1022 alu
.dst
.sel
= ctx
->temp_reg
;
1025 alu
.src
[0].sel
= ctx
->temp_reg
;
1026 alu
.src
[0].chan
= 0;
1028 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1032 /* replicate result */
1033 for (i
= 0; i
< 4; i
++) {
1034 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
))
1037 for (i
= 0; i
< lasti
+ 1; i
++) {
1038 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1041 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1042 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1044 alu
.src
[0].sel
= ctx
->temp_reg
;
1045 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1050 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1057 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
1059 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1060 struct r600_bc_alu_src r600_src
[3];
1061 struct r600_bc_alu alu
;
1064 /* We'll only need the trig stuff if we are going to write to the
1065 * X or Y components of the destination vector.
1067 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
1068 r
= tgsi_setup_trig(ctx
, r600_src
);
1074 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
1075 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1076 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
1077 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1081 alu
.src
[0].sel
= ctx
->temp_reg
;
1082 alu
.src
[0].chan
= 0;
1084 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1090 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
1091 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1092 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
1093 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1097 alu
.src
[0].sel
= ctx
->temp_reg
;
1098 alu
.src
[0].chan
= 0;
1100 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1106 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
1107 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1109 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1111 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1115 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1116 alu
.src
[0].chan
= 0;
1120 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1124 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1130 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
1131 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1133 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1135 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1139 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1140 alu
.src
[0].chan
= 0;
1144 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1148 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1156 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
1158 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1159 struct r600_bc_alu alu
;
1162 for (i
= 0; i
< 4; i
++) {
1163 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1164 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1168 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1170 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILP
) {
1171 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1174 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1177 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1182 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1186 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1190 /* kill must be last in ALU */
1191 ctx
->bc
->force_add_cf
= 1;
1192 ctx
->shader
->uses_kill
= TRUE
;
1196 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
1198 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1199 struct r600_bc_alu alu
;
1200 struct r600_bc_alu_src r600_src
[3];
1203 r
= tgsi_split_constant(ctx
, r600_src
);
1206 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1211 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1212 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1213 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
1214 alu
.src
[0].chan
= 0;
1215 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1218 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
1219 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1223 /* dst.y = max(src.x, 0.0) */
1224 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1225 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
1226 alu
.src
[0] = r600_src
[0];
1227 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
1228 alu
.src
[1].chan
= 0;
1229 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1232 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
1233 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1238 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1239 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1240 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1241 alu
.src
[0].chan
= 0;
1242 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1245 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
1247 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1251 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1255 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
1260 /* dst.z = log(src.y) */
1261 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1262 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
1263 alu
.src
[0] = r600_src
[0];
1264 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
1265 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1269 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1273 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1277 chan
= alu
.dst
.chan
;
1280 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1281 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1282 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
);
1283 alu
.src
[0] = r600_src
[0];
1284 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1285 alu
.src
[1].sel
= sel
;
1286 alu
.src
[1].chan
= chan
;
1288 alu
.src
[2] = r600_src
[0];
1289 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], 0);
1290 alu
.dst
.sel
= ctx
->temp_reg
;
1295 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1299 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1302 /* dst.z = exp(tmp.x) */
1303 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1304 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1305 alu
.src
[0].sel
= ctx
->temp_reg
;
1306 alu
.src
[0].chan
= 0;
1307 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1311 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1318 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
1320 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1321 struct r600_bc_alu alu
;
1324 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1327 * For state trackers other than OpenGL, we'll want to use
1328 * _RECIPSQRT_IEEE instead.
1330 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
);
1332 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1333 r
= tgsi_src(ctx
, &inst
->Src
[i
], &alu
.src
[i
]);
1336 alu
.src
[i
].chan
= tgsi_chan(&inst
->Src
[i
], 0);
1339 alu
.dst
.sel
= ctx
->temp_reg
;
1342 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1345 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1348 /* replicate result */
1349 return tgsi_helper_tempx_replicate(ctx
);
1352 static int tgsi_trans(struct r600_shader_ctx
*ctx
)
1354 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1355 struct r600_bc_alu alu
;
1358 for (i
= 0; i
< 4; i
++) {
1359 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1360 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
1361 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1362 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1363 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
1366 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1368 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1372 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1380 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
1382 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1383 struct r600_bc_alu alu
;
1386 for (i
= 0; i
< 4; i
++) {
1387 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1388 alu
.src
[0].sel
= ctx
->temp_reg
;
1389 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1391 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1394 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1397 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1404 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
1406 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1407 struct r600_bc_alu alu
;
1410 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1411 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1412 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1413 r
= tgsi_src(ctx
, &inst
->Src
[i
], &alu
.src
[i
]);
1416 alu
.src
[i
].chan
= tgsi_chan(&inst
->Src
[i
], 0);
1418 alu
.dst
.sel
= ctx
->temp_reg
;
1421 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1424 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1427 /* replicate result */
1428 return tgsi_helper_tempx_replicate(ctx
);
1431 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
1433 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1434 struct r600_bc_alu alu
;
1438 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1439 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
1440 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1443 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1444 alu
.dst
.sel
= ctx
->temp_reg
;
1447 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1450 r
= r600_bc_add_literal(ctx
->bc
,ctx
->value
);
1454 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1455 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE
);
1456 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[0]);
1459 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], 0);
1460 alu
.src
[1].sel
= ctx
->temp_reg
;
1461 alu
.dst
.sel
= ctx
->temp_reg
;
1464 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1467 r
= r600_bc_add_literal(ctx
->bc
,ctx
->value
);
1470 /* POW(a,b) = EXP2(b * LOG2(a))*/
1471 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1472 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1473 alu
.src
[0].sel
= ctx
->temp_reg
;
1474 alu
.dst
.sel
= ctx
->temp_reg
;
1477 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1480 r
= r600_bc_add_literal(ctx
->bc
,ctx
->value
);
1483 return tgsi_helper_tempx_replicate(ctx
);
1486 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
1488 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1489 struct r600_bc_alu alu
;
1490 struct r600_bc_alu_src r600_src
[3];
1493 r
= tgsi_split_constant(ctx
, r600_src
);
1497 /* tmp = (src > 0 ? 1 : src) */
1498 for (i
= 0; i
< 4; i
++) {
1499 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1500 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1503 alu
.dst
.sel
= ctx
->temp_reg
;
1506 alu
.src
[0] = r600_src
[0];
1507 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1509 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1511 alu
.src
[2] = r600_src
[0];
1512 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], i
);
1515 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1519 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1523 /* dst = (-tmp > 0 ? -1 : tmp) */
1524 for (i
= 0; i
< 4; i
++) {
1525 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1526 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1528 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1532 alu
.src
[0].sel
= ctx
->temp_reg
;
1533 alu
.src
[0].chan
= i
;
1536 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1539 alu
.src
[2].sel
= ctx
->temp_reg
;
1540 alu
.src
[2].chan
= i
;
1544 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1551 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
1553 struct r600_bc_alu alu
;
1556 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1559 for (i
= 0; i
< 4; i
++) {
1560 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1561 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
1562 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
1565 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1566 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1569 alu
.src
[0].sel
= ctx
->temp_reg
;
1570 alu
.src
[0].chan
= i
;
1575 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1582 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
1584 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1585 struct r600_bc_alu_src r600_src
[3];
1586 struct r600_bc_alu alu
;
1589 r
= tgsi_split_constant(ctx
, r600_src
);
1592 /* do it in 2 step as op3 doesn't support writemask */
1593 for (i
= 0; i
< 4; i
++) {
1594 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1595 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1596 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1597 alu
.src
[j
] = r600_src
[j
];
1598 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1600 alu
.dst
.sel
= ctx
->temp_reg
;
1607 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1611 return tgsi_helper_copy(ctx
, inst
);
1614 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
1616 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1617 struct r600_bc_alu_src r600_src
[3];
1618 struct r600_bc_alu alu
;
1621 r
= tgsi_split_constant(ctx
, r600_src
);
1624 for (i
= 0; i
< 4; i
++) {
1625 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1626 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1627 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1628 alu
.src
[j
] = r600_src
[j
];
1629 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1631 alu
.dst
.sel
= ctx
->temp_reg
;
1634 /* handle some special cases */
1635 switch (ctx
->inst_info
->tgsi_opcode
) {
1636 case TGSI_OPCODE_DP2
:
1638 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1639 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1642 case TGSI_OPCODE_DP3
:
1644 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1645 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1648 case TGSI_OPCODE_DPH
:
1650 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1651 alu
.src
[0].chan
= 0;
1661 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1665 return tgsi_helper_copy(ctx
, inst
);
1668 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1670 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1671 struct r600_bc_tex tex
;
1672 struct r600_bc_alu alu
;
1676 boolean src_not_temp
= inst
->Src
[0].Register
.File
!= TGSI_FILE_TEMPORARY
;
1677 uint32_t lit_vals
[4];
1679 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1681 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1682 /* Add perspective divide */
1683 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1684 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1685 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1689 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1690 alu
.dst
.sel
= ctx
->temp_reg
;
1694 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1698 for (i
= 0; i
< 3; i
++) {
1699 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1700 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1701 alu
.src
[0].sel
= ctx
->temp_reg
;
1702 alu
.src
[0].chan
= 3;
1703 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1706 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1707 alu
.dst
.sel
= ctx
->temp_reg
;
1710 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1714 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1715 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1716 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1717 alu
.src
[0].chan
= 0;
1718 alu
.dst
.sel
= ctx
->temp_reg
;
1722 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1725 src_not_temp
= FALSE
;
1726 src_gpr
= ctx
->temp_reg
;
1729 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1730 int src_chan
, src2_chan
;
1732 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1733 for (i
= 0; i
< 4; i
++) {
1734 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1735 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
);
1759 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1762 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], src_chan
);
1763 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1766 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], src2_chan
);
1767 alu
.dst
.sel
= ctx
->temp_reg
;
1772 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1777 /* tmp1.z = RCP_e(|tmp1.z|) */
1778 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1779 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1780 alu
.src
[0].sel
= ctx
->temp_reg
;
1781 alu
.src
[0].chan
= 2;
1783 alu
.dst
.sel
= ctx
->temp_reg
;
1787 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1791 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1792 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1793 * muladd has no writemask, have to use another temp
1795 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1796 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1799 alu
.src
[0].sel
= ctx
->temp_reg
;
1800 alu
.src
[0].chan
= 0;
1801 alu
.src
[1].sel
= ctx
->temp_reg
;
1802 alu
.src
[1].chan
= 2;
1804 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1805 alu
.src
[2].chan
= 0;
1807 alu
.dst
.sel
= ctx
->temp_reg
;
1811 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1815 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1816 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1819 alu
.src
[0].sel
= ctx
->temp_reg
;
1820 alu
.src
[0].chan
= 1;
1821 alu
.src
[1].sel
= ctx
->temp_reg
;
1822 alu
.src
[1].chan
= 2;
1824 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1825 alu
.src
[2].chan
= 0;
1827 alu
.dst
.sel
= ctx
->temp_reg
;
1832 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1836 lit_vals
[0] = fui(1.5f
);
1838 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
1841 src_not_temp
= FALSE
;
1842 src_gpr
= ctx
->temp_reg
;
1846 for (i
= 0; i
< 4; i
++) {
1847 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1848 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1849 alu
.src
[0].sel
= src_gpr
;
1850 alu
.src
[0].chan
= i
;
1851 alu
.dst
.sel
= ctx
->temp_reg
;
1856 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1860 src_gpr
= ctx
->temp_reg
;
1863 opcode
= ctx
->inst_info
->r600_opcode
;
1864 if (opcode
== SQ_TEX_INST_SAMPLE
&&
1865 (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
))
1866 opcode
= SQ_TEX_INST_SAMPLE_C
;
1868 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1870 tex
.resource_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1871 tex
.sampler_id
= tex
.resource_id
;
1872 tex
.src_gpr
= src_gpr
;
1873 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1883 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1890 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1891 tex
.coord_type_x
= 1;
1892 tex
.coord_type_y
= 1;
1893 tex
.coord_type_z
= 1;
1894 tex
.coord_type_w
= 1;
1897 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
)
1900 r
= r600_bc_add_tex(ctx
->bc
, &tex
);
1904 /* add shadow ambient support - gallium doesn't do it yet */
1909 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1911 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1912 struct r600_bc_alu_src r600_src
[3];
1913 struct r600_bc_alu alu
;
1917 r
= tgsi_split_constant(ctx
, r600_src
);
1921 for (i
= 0; i
< 4; i
++) {
1922 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1923 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
1924 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1925 alu
.src
[0].chan
= 0;
1926 alu
.src
[1] = r600_src
[0];
1927 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1929 alu
.dst
.sel
= ctx
->temp_reg
;
1935 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1939 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1943 /* (1 - src0) * src2 */
1944 for (i
= 0; i
< 4; i
++) {
1945 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1946 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1947 alu
.src
[0].sel
= ctx
->temp_reg
;
1948 alu
.src
[0].chan
= i
;
1949 alu
.src
[1] = r600_src
[2];
1950 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1951 alu
.dst
.sel
= ctx
->temp_reg
;
1957 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1961 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1965 /* src0 * src1 + (1 - src0) * src2 */
1966 for (i
= 0; i
< 4; i
++) {
1967 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1968 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1970 alu
.src
[0] = r600_src
[0];
1971 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1972 alu
.src
[1] = r600_src
[1];
1973 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
1974 alu
.src
[2].sel
= ctx
->temp_reg
;
1975 alu
.src
[2].chan
= i
;
1976 alu
.dst
.sel
= ctx
->temp_reg
;
1981 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1985 return tgsi_helper_copy(ctx
, inst
);
1988 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
1990 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1991 struct r600_bc_alu_src r600_src
[3];
1992 struct r600_bc_alu alu
;
1996 r
= tgsi_split_constant(ctx
, r600_src
);
2000 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
2003 for (i
= 0; i
< 4; i
++) {
2004 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2005 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
);
2006 alu
.src
[0] = r600_src
[0];
2007 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
2009 alu
.src
[1] = r600_src
[2];
2010 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
2012 alu
.src
[2] = r600_src
[1];
2013 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[1], i
);
2016 alu
.dst
.sel
= ctx
->temp_reg
;
2018 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2027 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2032 return tgsi_helper_copy(ctx
, inst
);
2036 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
2038 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2039 struct r600_bc_alu_src r600_src
[3];
2040 struct r600_bc_alu alu
;
2041 uint32_t use_temp
= 0;
2044 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
2047 r
= tgsi_split_constant(ctx
, r600_src
);
2051 for (i
= 0; i
< 4; i
++) {
2052 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2053 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2055 alu
.src
[0] = r600_src
[0];
2058 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
2061 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2064 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
2067 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2068 alu
.src
[0].chan
= i
;
2071 alu
.src
[1] = r600_src
[1];
2074 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
2077 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
2080 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
2083 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2084 alu
.src
[1].chan
= i
;
2087 alu
.dst
.sel
= ctx
->temp_reg
;
2093 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2097 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2102 for (i
= 0; i
< 4; i
++) {
2103 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2104 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
2106 alu
.src
[0] = r600_src
[0];
2109 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
2112 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
2115 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2118 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2119 alu
.src
[0].chan
= i
;
2122 alu
.src
[1] = r600_src
[1];
2125 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
2128 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
2131 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
2134 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2135 alu
.src
[1].chan
= i
;
2138 alu
.src
[2].sel
= ctx
->temp_reg
;
2140 alu
.src
[2].chan
= i
;
2143 alu
.dst
.sel
= ctx
->temp_reg
;
2145 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2154 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2158 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2163 return tgsi_helper_copy(ctx
, inst
);
2167 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
2169 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2170 struct r600_bc_alu_src r600_src
[3];
2171 struct r600_bc_alu alu
;
2174 /* result.x = 2^floor(src); */
2175 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
2176 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2178 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2179 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2183 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2185 alu
.dst
.sel
= ctx
->temp_reg
;
2189 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2193 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2197 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2198 alu
.src
[0].sel
= ctx
->temp_reg
;
2199 alu
.src
[0].chan
= 0;
2201 alu
.dst
.sel
= ctx
->temp_reg
;
2205 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2209 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2214 /* result.y = tmp - floor(tmp); */
2215 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
2216 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2218 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
2219 alu
.src
[0] = r600_src
[0];
2220 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2223 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2225 alu
.dst
.sel
= ctx
->temp_reg
;
2226 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2234 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2237 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2242 /* result.z = RoughApprox2ToX(tmp);*/
2243 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
2244 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2245 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2246 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2249 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2251 alu
.dst
.sel
= ctx
->temp_reg
;
2257 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2260 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2265 /* result.w = 1.0;*/
2266 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
2267 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2269 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2270 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2271 alu
.src
[0].chan
= 0;
2273 alu
.dst
.sel
= ctx
->temp_reg
;
2277 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2280 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2284 return tgsi_helper_copy(ctx
, inst
);
2287 static int tgsi_log(struct r600_shader_ctx
*ctx
)
2289 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2290 struct r600_bc_alu alu
;
2293 /* result.x = floor(log2(src)); */
2294 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
2295 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2297 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2298 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2302 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2304 alu
.dst
.sel
= ctx
->temp_reg
;
2308 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2312 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2316 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2317 alu
.src
[0].sel
= ctx
->temp_reg
;
2318 alu
.src
[0].chan
= 0;
2320 alu
.dst
.sel
= ctx
->temp_reg
;
2325 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2329 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2334 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2335 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
2336 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2338 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2339 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2343 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2345 alu
.dst
.sel
= ctx
->temp_reg
;
2350 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2354 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2358 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2360 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2361 alu
.src
[0].sel
= ctx
->temp_reg
;
2362 alu
.src
[0].chan
= 1;
2364 alu
.dst
.sel
= ctx
->temp_reg
;
2369 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2373 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2377 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2379 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2380 alu
.src
[0].sel
= ctx
->temp_reg
;
2381 alu
.src
[0].chan
= 1;
2383 alu
.dst
.sel
= ctx
->temp_reg
;
2388 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2392 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2396 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2398 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
2399 alu
.src
[0].sel
= ctx
->temp_reg
;
2400 alu
.src
[0].chan
= 1;
2402 alu
.dst
.sel
= ctx
->temp_reg
;
2407 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2411 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2415 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2417 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2419 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2423 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2425 alu
.src
[1].sel
= ctx
->temp_reg
;
2426 alu
.src
[1].chan
= 1;
2428 alu
.dst
.sel
= ctx
->temp_reg
;
2433 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2437 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2442 /* result.z = log2(src);*/
2443 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
2444 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2446 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2447 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2451 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2453 alu
.dst
.sel
= ctx
->temp_reg
;
2458 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2462 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2467 /* result.w = 1.0; */
2468 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
2469 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2471 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2472 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2473 alu
.src
[0].chan
= 0;
2475 alu
.dst
.sel
= ctx
->temp_reg
;
2480 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2484 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2489 return tgsi_helper_copy(ctx
, inst
);
2492 /* r6/7 only for now */
2493 static int tgsi_arl(struct r600_shader_ctx
*ctx
)
2495 /* TODO from r600c, ar values don't persist between clauses */
2496 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2497 struct r600_bc_alu alu
;
2499 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2501 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
;
2503 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2506 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2510 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
));
2513 ctx
->bc
->cf_last
->r6xx_uses_waterfall
= 1;
2517 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
2519 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2520 struct r600_bc_alu alu
;
2523 for (i
= 0; i
< 4; i
++) {
2524 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2526 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2527 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2531 if (i
== 0 || i
== 3) {
2532 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2534 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2537 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
2540 if (i
== 0 || i
== 2) {
2541 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
2543 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[1]);
2546 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
2550 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2557 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
2559 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2560 struct r600_bc_alu alu
;
2563 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2567 alu
.dst
.sel
= ctx
->temp_reg
;
2571 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2574 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2575 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2576 alu
.src
[1].chan
= 0;
2580 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
2586 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
2588 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP
));
2589 ctx
->bc
->cf_last
->pop_count
= pops
;
2593 static inline void callstack_decrease_current(struct r600_shader_ctx
*ctx
, unsigned reason
)
2597 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2601 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
-= 4;
2604 /* TOODO : for 16 vp asic should -= 2; */
2605 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2610 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
)
2612 if (check_max_only
) {
2625 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
) >
2626 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2627 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2628 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
;
2634 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2638 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+= 4;
2641 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2645 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
) >
2646 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2647 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2648 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
;
2652 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
2654 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
2656 sp
->mid
= (struct r600_bc_cf
**)realloc((void *)sp
->mid
,
2657 sizeof(struct r600_bc_cf
*) * (sp
->num_mid
+ 1));
2658 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
2662 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
2665 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
2666 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
2669 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
2671 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
2683 static int emit_return(struct r600_shader_ctx
*ctx
)
2685 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_RETURN
);
2689 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
2692 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_JUMP
);
2693 ctx
->bc
->cf_last
->pop_count
= pops
;
2694 /* TODO work out offset */
2698 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
2703 static void emit_testflag(struct r600_shader_ctx
*ctx
)
2708 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
2711 emit_jump_to_offset(ctx
, 1, 4);
2712 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
2713 pops(ctx
, ifidx
+ 1);
2717 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
2721 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2722 ctx
->bc
->cf_last
->pop_count
= 1;
2724 fc_set_mid(ctx
, fc_sp
);
2730 static int tgsi_if(struct r600_shader_ctx
*ctx
)
2732 emit_logic_pred(ctx
, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
));
2734 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
2736 fc_pushlevel(ctx
, FC_IF
);
2738 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
2742 static int tgsi_else(struct r600_shader_ctx
*ctx
)
2744 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE
));
2745 ctx
->bc
->cf_last
->pop_count
= 1;
2747 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
2748 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
2752 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
2755 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
2756 R600_ERR("if/endif unbalanced in shader\n");
2760 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
2761 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2762 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
2764 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2768 callstack_decrease_current(ctx
, FC_PUSH_VPM
);
2772 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
2774 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
));
2776 fc_pushlevel(ctx
, FC_LOOP
);
2778 /* check stack depth */
2779 callstack_check_depth(ctx
, FC_LOOP
, 0);
2783 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
2787 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
));
2789 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
2790 R600_ERR("loop/endloop in shader code are not paired.\n");
2794 /* fixup loop pointers - from r600isa
2795 LOOP END points to CF after LOOP START,
2796 LOOP START point to CF after LOOP END
2797 BRK/CONT point to LOOP END CF
2799 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
2801 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2803 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
2804 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
2806 /* TODO add LOOPRET support */
2808 callstack_decrease_current(ctx
, FC_LOOP
);
2812 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
2816 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
2818 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
2823 R600_ERR("Break not inside loop/endloop pair\n");
2827 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2828 ctx
->bc
->cf_last
->pop_count
= 1;
2830 fc_set_mid(ctx
, fscp
);
2833 callstack_check_depth(ctx
, FC_PUSH_VPM
, 1);
2837 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
2838 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_arl
},
2839 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2840 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
2843 * For state trackers other than OpenGL, we'll want to use
2844 * _RECIP_IEEE instead.
2846 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
2848 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_rsq
},
2849 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
2850 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
2851 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
2852 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2853 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2854 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2855 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
2856 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
2857 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
2858 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
2859 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
2860 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
2861 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2862 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
2863 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2865 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2866 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2868 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2869 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2870 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
2871 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2872 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
2873 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2874 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
2875 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
2876 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
2877 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
2879 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2880 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2881 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2882 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2883 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
2884 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
2885 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
2886 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
2887 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2888 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2889 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2890 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2891 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2892 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
2893 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2894 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
2895 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
2896 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
2897 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
2898 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2899 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2900 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2901 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2902 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2903 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2904 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2905 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2906 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2907 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2908 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2909 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2910 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2911 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2912 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
2913 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
2914 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
2915 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2916 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2917 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2918 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2919 {TGSI_OPCODE_TXL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2920 {TGSI_OPCODE_BRK
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
2921 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
2923 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2924 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2925 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
2926 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
2928 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2929 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2930 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2931 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2932 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2933 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2934 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2935 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
2936 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2938 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2939 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2940 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2941 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2942 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2943 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2944 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2945 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2946 {TGSI_OPCODE_CONT
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
2947 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2948 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2949 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
2950 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2951 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
2952 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2954 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2955 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2956 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2957 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2958 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2960 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2961 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2962 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2963 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2964 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2965 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2966 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2967 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2968 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
2969 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
2971 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2972 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2973 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2974 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2975 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2976 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2977 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2978 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2979 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2980 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2981 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2982 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2983 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2984 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2985 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2986 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2987 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2988 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2989 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2990 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2991 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2992 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2993 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2994 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2995 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2996 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2997 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2998 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3001 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
3002 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3003 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
3004 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
3005 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
3006 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
3007 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
3008 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3009 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
3010 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
3011 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3012 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3013 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
3014 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
3015 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
3016 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
3017 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
3018 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
3019 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
3020 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
3021 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3023 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3024 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3026 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3027 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3028 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
3029 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3030 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
3031 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3032 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
3033 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
3034 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
3035 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
3037 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3038 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
3039 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3040 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3041 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
3042 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
3043 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
3044 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
3045 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3046 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3047 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3048 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3049 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3050 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
3051 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3052 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
3053 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
3054 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
3055 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
3056 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3057 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3058 {TGSI_OPCODE_TXD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3059 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3060 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3061 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3062 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3063 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3064 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3065 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3066 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3067 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3068 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3069 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3070 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
3071 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
3072 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
3073 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
3074 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3075 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3076 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3077 {TGSI_OPCODE_TXL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3078 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
3079 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
3081 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3082 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3083 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
3084 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
3086 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3087 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3088 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3089 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3090 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3091 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3092 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3093 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
3094 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3096 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3097 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3098 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3099 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3100 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3101 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3102 {TGSI_OPCODE_TXF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3103 {TGSI_OPCODE_TXQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3104 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
3105 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3106 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3107 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
3108 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3109 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
3110 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3112 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3113 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3114 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3115 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3116 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3118 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3119 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3120 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3121 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3122 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3123 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3124 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3125 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3126 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
3127 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
3129 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3130 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3131 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3132 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3133 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3134 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3135 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3136 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3137 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3138 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3139 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3140 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3141 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3142 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3143 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3144 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3145 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3146 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3147 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3148 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3149 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3150 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3151 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3152 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3153 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3154 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3155 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3156 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},