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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
64 static int r600_shader_from_tgsi(struct r600_context *rctx,
65 struct r600_pipe_shader *pipeshader,
66 union r600_shader_key key);
67
68
69 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
70 int size, unsigned comp_mask) {
71
72 if (!size)
73 return;
74
75 if (ps->num_arrays == ps->max_arrays) {
76 ps->max_arrays += 64;
77 ps->arrays = realloc(ps->arrays, ps->max_arrays *
78 sizeof(struct r600_shader_array));
79 }
80
81 int n = ps->num_arrays;
82 ++ps->num_arrays;
83
84 ps->arrays[n].comp_mask = comp_mask;
85 ps->arrays[n].gpr_start = start_gpr;
86 ps->arrays[n].gpr_count = size;
87 }
88
89 static void r600_dump_streamout(struct pipe_stream_output_info *so)
90 {
91 unsigned i;
92
93 fprintf(stderr, "STREAMOUT\n");
94 for (i = 0; i < so->num_outputs; i++) {
95 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
96 so->output[i].start_component;
97 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
98 i,
99 so->output[i].stream,
100 so->output[i].output_buffer,
101 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
102 so->output[i].register_index,
103 mask & 1 ? "x" : "",
104 mask & 2 ? "y" : "",
105 mask & 4 ? "z" : "",
106 mask & 8 ? "w" : "",
107 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
108 }
109 }
110
111 static int store_shader(struct pipe_context *ctx,
112 struct r600_pipe_shader *shader)
113 {
114 struct r600_context *rctx = (struct r600_context *)ctx;
115 uint32_t *ptr, i;
116
117 if (shader->bo == NULL) {
118 shader->bo = (struct r600_resource*)
119 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
120 if (shader->bo == NULL) {
121 return -ENOMEM;
122 }
123 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
124 if (R600_BIG_ENDIAN) {
125 for (i = 0; i < shader->shader.bc.ndw; ++i) {
126 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
127 }
128 } else {
129 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
130 }
131 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
132 }
133
134 return 0;
135 }
136
137 int r600_pipe_shader_create(struct pipe_context *ctx,
138 struct r600_pipe_shader *shader,
139 union r600_shader_key key)
140 {
141 struct r600_context *rctx = (struct r600_context *)ctx;
142 struct r600_pipe_shader_selector *sel = shader->selector;
143 int r;
144 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
145 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
146 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
147 unsigned export_shader;
148
149 shader->shader.bc.isa = rctx->isa;
150
151 if (dump) {
152 fprintf(stderr, "--------------------------------------------------------------\n");
153 tgsi_dump(sel->tokens, 0);
154
155 if (sel->so.num_outputs) {
156 r600_dump_streamout(&sel->so);
157 }
158 }
159 r = r600_shader_from_tgsi(rctx, shader, key);
160 if (r) {
161 R600_ERR("translation from TGSI failed !\n");
162 goto error;
163 }
164
165 /* disable SB for shaders using doubles */
166 use_sb &= !shader->shader.uses_doubles;
167
168 /* Check if the bytecode has already been built. When using the llvm
169 * backend, r600_shader_from_tgsi() will take care of building the
170 * bytecode.
171 */
172 if (!shader->shader.bc.bytecode) {
173 r = r600_bytecode_build(&shader->shader.bc);
174 if (r) {
175 R600_ERR("building bytecode failed !\n");
176 goto error;
177 }
178 }
179
180 if (dump && !sb_disasm) {
181 fprintf(stderr, "--------------------------------------------------------------\n");
182 r600_bytecode_disasm(&shader->shader.bc);
183 fprintf(stderr, "______________________________________________________________\n");
184 } else if ((dump && sb_disasm) || use_sb) {
185 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
186 dump, use_sb);
187 if (r) {
188 R600_ERR("r600_sb_bytecode_process failed !\n");
189 goto error;
190 }
191 }
192
193 if (shader->gs_copy_shader) {
194 if (dump) {
195 // dump copy shader
196 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
197 &shader->gs_copy_shader->shader, dump, 0);
198 if (r)
199 goto error;
200 }
201
202 if ((r = store_shader(ctx, shader->gs_copy_shader)))
203 goto error;
204 }
205
206 /* Store the shader in a buffer. */
207 if ((r = store_shader(ctx, shader)))
208 goto error;
209
210 /* Build state. */
211 switch (shader->shader.processor_type) {
212 case TGSI_PROCESSOR_GEOMETRY:
213 if (rctx->b.chip_class >= EVERGREEN) {
214 evergreen_update_gs_state(ctx, shader);
215 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
216 } else {
217 r600_update_gs_state(ctx, shader);
218 r600_update_vs_state(ctx, shader->gs_copy_shader);
219 }
220 break;
221 case TGSI_PROCESSOR_VERTEX:
222 export_shader = key.vs.as_es;
223 if (rctx->b.chip_class >= EVERGREEN) {
224 if (export_shader)
225 evergreen_update_es_state(ctx, shader);
226 else
227 evergreen_update_vs_state(ctx, shader);
228 } else {
229 if (export_shader)
230 r600_update_es_state(ctx, shader);
231 else
232 r600_update_vs_state(ctx, shader);
233 }
234 break;
235 case TGSI_PROCESSOR_FRAGMENT:
236 if (rctx->b.chip_class >= EVERGREEN) {
237 evergreen_update_ps_state(ctx, shader);
238 } else {
239 r600_update_ps_state(ctx, shader);
240 }
241 break;
242 default:
243 r = -EINVAL;
244 goto error;
245 }
246 return 0;
247
248 error:
249 r600_pipe_shader_destroy(ctx, shader);
250 return r;
251 }
252
253 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
254 {
255 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
256 r600_bytecode_clear(&shader->shader.bc);
257 r600_release_command_buffer(&shader->command_buffer);
258 }
259
260 /*
261 * tgsi -> r600 shader
262 */
263 struct r600_shader_tgsi_instruction;
264
265 struct r600_shader_src {
266 unsigned sel;
267 unsigned swizzle[4];
268 unsigned neg;
269 unsigned abs;
270 unsigned rel;
271 unsigned kc_bank;
272 boolean kc_rel; /* true if cache bank is indexed */
273 uint32_t value[4];
274 };
275
276 struct eg_interp {
277 boolean enabled;
278 unsigned ij_index;
279 };
280
281 struct r600_shader_ctx {
282 struct tgsi_shader_info info;
283 struct tgsi_parse_context parse;
284 const struct tgsi_token *tokens;
285 unsigned type;
286 unsigned file_offset[TGSI_FILE_COUNT];
287 unsigned temp_reg;
288 const struct r600_shader_tgsi_instruction *inst_info;
289 struct r600_bytecode *bc;
290 struct r600_shader *shader;
291 struct r600_shader_src src[4];
292 uint32_t *literals;
293 uint32_t nliterals;
294 uint32_t max_driver_temp_used;
295 boolean use_llvm;
296 /* needed for evergreen interpolation */
297 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
298 /* evergreen/cayman also store sample mask in face register */
299 int face_gpr;
300 /* sample id is .w component stored in fixed point position register */
301 int fixed_pt_position_gpr;
302 int colors_used;
303 boolean clip_vertex_write;
304 unsigned cv_output;
305 unsigned edgeflag_output;
306 int fragcoord_input;
307 int native_integers;
308 int next_ring_offset;
309 int gs_out_ring_offset;
310 int gs_next_vertex;
311 struct r600_shader *gs_for_vs;
312 int gs_export_gpr_tregs[4];
313 const struct pipe_stream_output_info *gs_stream_output_info;
314 unsigned enabled_stream_buffers_mask;
315 };
316
317 struct r600_shader_tgsi_instruction {
318 unsigned op;
319 int (*process)(struct r600_shader_ctx *ctx);
320 };
321
322 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
323 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
324 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
325 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
326 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
327 static int tgsi_else(struct r600_shader_ctx *ctx);
328 static int tgsi_endif(struct r600_shader_ctx *ctx);
329 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
330 static int tgsi_endloop(struct r600_shader_ctx *ctx);
331 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
332 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
333 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
334 unsigned int dst_reg);
335 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
336 const struct r600_shader_src *shader_src,
337 unsigned chan);
338
339 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
340 {
341 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
342 int j;
343
344 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
345 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
346 return -EINVAL;
347 }
348 if (i->Instruction.Predicate) {
349 R600_ERR("predicate unsupported\n");
350 return -EINVAL;
351 }
352 #if 0
353 if (i->Instruction.Label) {
354 R600_ERR("label unsupported\n");
355 return -EINVAL;
356 }
357 #endif
358 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
359 if (i->Src[j].Register.Dimension) {
360 switch (i->Src[j].Register.File) {
361 case TGSI_FILE_CONSTANT:
362 break;
363 case TGSI_FILE_INPUT:
364 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
365 break;
366 default:
367 R600_ERR("unsupported src %d (dimension %d)\n", j,
368 i->Src[j].Register.Dimension);
369 return -EINVAL;
370 }
371 }
372 }
373 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
374 if (i->Dst[j].Register.Dimension) {
375 R600_ERR("unsupported dst (dimension)\n");
376 return -EINVAL;
377 }
378 }
379 return 0;
380 }
381
382 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
383 {
384 if (interpolate == TGSI_INTERPOLATE_COLOR ||
385 interpolate == TGSI_INTERPOLATE_LINEAR ||
386 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
387 {
388 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
389 int loc;
390
391 switch(location) {
392 case TGSI_INTERPOLATE_LOC_CENTER:
393 loc = 1;
394 break;
395 case TGSI_INTERPOLATE_LOC_CENTROID:
396 loc = 2;
397 break;
398 case TGSI_INTERPOLATE_LOC_SAMPLE:
399 default:
400 loc = 0; break;
401 }
402
403 return is_linear * 3 + loc;
404 }
405
406 return -1;
407 }
408
409 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
410 int input)
411 {
412 int i = eg_get_interpolator_index(
413 ctx->shader->input[input].interpolate,
414 ctx->shader->input[input].interpolate_location);
415 assert(i >= 0);
416 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
417 }
418
419 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
420 {
421 int i, r;
422 struct r600_bytecode_alu alu;
423 int gpr = 0, base_chan = 0;
424 int ij_index = ctx->shader->input[input].ij_index;
425
426 /* work out gpr and base_chan from index */
427 gpr = ij_index / 2;
428 base_chan = (2 * (ij_index % 2)) + 1;
429
430 for (i = 0; i < 8; i++) {
431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
432
433 if (i < 4)
434 alu.op = ALU_OP2_INTERP_ZW;
435 else
436 alu.op = ALU_OP2_INTERP_XY;
437
438 if ((i > 1) && (i < 6)) {
439 alu.dst.sel = ctx->shader->input[input].gpr;
440 alu.dst.write = 1;
441 }
442
443 alu.dst.chan = i % 4;
444
445 alu.src[0].sel = gpr;
446 alu.src[0].chan = (base_chan - (i % 2));
447
448 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
449
450 alu.bank_swizzle_force = SQ_ALU_VEC_210;
451 if ((i % 4) == 3)
452 alu.last = 1;
453 r = r600_bytecode_add_alu(ctx->bc, &alu);
454 if (r)
455 return r;
456 }
457 return 0;
458 }
459
460 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
461 {
462 int i, r;
463 struct r600_bytecode_alu alu;
464
465 for (i = 0; i < 4; i++) {
466 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
467
468 alu.op = ALU_OP1_INTERP_LOAD_P0;
469
470 alu.dst.sel = ctx->shader->input[input].gpr;
471 alu.dst.write = 1;
472
473 alu.dst.chan = i;
474
475 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
476 alu.src[0].chan = i;
477
478 if (i == 3)
479 alu.last = 1;
480 r = r600_bytecode_add_alu(ctx->bc, &alu);
481 if (r)
482 return r;
483 }
484 return 0;
485 }
486
487 /*
488 * Special export handling in shaders
489 *
490 * shader export ARRAY_BASE for EXPORT_POS:
491 * 60 is position
492 * 61 is misc vector
493 * 62, 63 are clip distance vectors
494 *
495 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
496 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
497 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
498 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
499 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
500 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
501 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
502 * exclusive from render target index)
503 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
504 *
505 *
506 * shader export ARRAY_BASE for EXPORT_PIXEL:
507 * 0-7 CB targets
508 * 61 computed Z vector
509 *
510 * The use of the values exported in the computed Z vector are controlled
511 * by DB_SHADER_CONTROL:
512 * Z_EXPORT_ENABLE - Z as a float in RED
513 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
514 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
515 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
516 * DB_SOURCE_FORMAT - export control restrictions
517 *
518 */
519
520
521 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
522 static int r600_spi_sid(struct r600_shader_io * io)
523 {
524 int index, name = io->name;
525
526 /* These params are handled differently, they don't need
527 * semantic indices, so we'll use 0 for them.
528 */
529 if (name == TGSI_SEMANTIC_POSITION ||
530 name == TGSI_SEMANTIC_PSIZE ||
531 name == TGSI_SEMANTIC_EDGEFLAG ||
532 name == TGSI_SEMANTIC_FACE ||
533 name == TGSI_SEMANTIC_SAMPLEMASK)
534 index = 0;
535 else {
536 if (name == TGSI_SEMANTIC_GENERIC) {
537 /* For generic params simply use sid from tgsi */
538 index = io->sid;
539 } else {
540 /* For non-generic params - pack name and sid into 8 bits */
541 index = 0x80 | (name<<3) | (io->sid);
542 }
543
544 /* Make sure that all really used indices have nonzero value, so
545 * we can just compare it to 0 later instead of comparing the name
546 * with different values to detect special cases. */
547 index++;
548 }
549
550 return index;
551 };
552
553 /* turn input into interpolate on EG */
554 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
555 {
556 int r = 0;
557
558 if (ctx->shader->input[index].spi_sid) {
559 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
560 if (ctx->shader->input[index].interpolate > 0) {
561 evergreen_interp_assign_ij_index(ctx, index);
562 if (!ctx->use_llvm)
563 r = evergreen_interp_alu(ctx, index);
564 } else {
565 if (!ctx->use_llvm)
566 r = evergreen_interp_flat(ctx, index);
567 }
568 }
569 return r;
570 }
571
572 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
573 {
574 struct r600_bytecode_alu alu;
575 int i, r;
576 int gpr_front = ctx->shader->input[front].gpr;
577 int gpr_back = ctx->shader->input[back].gpr;
578
579 for (i = 0; i < 4; i++) {
580 memset(&alu, 0, sizeof(alu));
581 alu.op = ALU_OP3_CNDGT;
582 alu.is_op3 = 1;
583 alu.dst.write = 1;
584 alu.dst.sel = gpr_front;
585 alu.src[0].sel = ctx->face_gpr;
586 alu.src[1].sel = gpr_front;
587 alu.src[2].sel = gpr_back;
588
589 alu.dst.chan = i;
590 alu.src[1].chan = i;
591 alu.src[2].chan = i;
592 alu.last = (i==3);
593
594 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
595 return r;
596 }
597
598 return 0;
599 }
600
601 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
602 {
603 int i;
604 i = ctx->shader->noutput++;
605 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
606 ctx->shader->output[i].sid = 0;
607 ctx->shader->output[i].gpr = 0;
608 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
609 ctx->shader->output[i].write_mask = 0x4;
610 ctx->shader->output[i].spi_sid = prim_id_sid;
611
612 return 0;
613 }
614
615 static int tgsi_declaration(struct r600_shader_ctx *ctx)
616 {
617 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
618 int r, i, j, count = d->Range.Last - d->Range.First + 1;
619
620 switch (d->Declaration.File) {
621 case TGSI_FILE_INPUT:
622 for (j = 0; j < count; j++) {
623 i = ctx->shader->ninput + j;
624 assert(i < Elements(ctx->shader->input));
625 ctx->shader->input[i].name = d->Semantic.Name;
626 ctx->shader->input[i].sid = d->Semantic.Index + j;
627 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
628 ctx->shader->input[i].interpolate_location = d->Interp.Location;
629 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
630 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
631 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
632 switch (ctx->shader->input[i].name) {
633 case TGSI_SEMANTIC_FACE:
634 if (ctx->face_gpr != -1)
635 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
636 else
637 ctx->face_gpr = ctx->shader->input[i].gpr;
638 break;
639 case TGSI_SEMANTIC_COLOR:
640 ctx->colors_used++;
641 break;
642 case TGSI_SEMANTIC_POSITION:
643 ctx->fragcoord_input = i;
644 break;
645 case TGSI_SEMANTIC_PRIMID:
646 /* set this for now */
647 ctx->shader->gs_prim_id_input = true;
648 ctx->shader->ps_prim_id_input = i;
649 break;
650 }
651 if (ctx->bc->chip_class >= EVERGREEN) {
652 if ((r = evergreen_interp_input(ctx, i)))
653 return r;
654 }
655 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
656 /* FIXME probably skip inputs if they aren't passed in the ring */
657 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
658 ctx->next_ring_offset += 16;
659 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
660 ctx->shader->gs_prim_id_input = true;
661 }
662 }
663 ctx->shader->ninput += count;
664 break;
665 case TGSI_FILE_OUTPUT:
666 for (j = 0; j < count; j++) {
667 i = ctx->shader->noutput + j;
668 assert(i < Elements(ctx->shader->output));
669 ctx->shader->output[i].name = d->Semantic.Name;
670 ctx->shader->output[i].sid = d->Semantic.Index + j;
671 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
672 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
673 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
674 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
675 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
676 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
677 switch (d->Semantic.Name) {
678 case TGSI_SEMANTIC_CLIPDIST:
679 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
680 ((d->Semantic.Index + j) << 2);
681 break;
682 case TGSI_SEMANTIC_PSIZE:
683 ctx->shader->vs_out_misc_write = 1;
684 ctx->shader->vs_out_point_size = 1;
685 break;
686 case TGSI_SEMANTIC_EDGEFLAG:
687 ctx->shader->vs_out_misc_write = 1;
688 ctx->shader->vs_out_edgeflag = 1;
689 ctx->edgeflag_output = i;
690 break;
691 case TGSI_SEMANTIC_VIEWPORT_INDEX:
692 ctx->shader->vs_out_misc_write = 1;
693 ctx->shader->vs_out_viewport = 1;
694 break;
695 case TGSI_SEMANTIC_LAYER:
696 ctx->shader->vs_out_misc_write = 1;
697 ctx->shader->vs_out_layer = 1;
698 break;
699 case TGSI_SEMANTIC_CLIPVERTEX:
700 ctx->clip_vertex_write = TRUE;
701 ctx->cv_output = i;
702 break;
703 }
704 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
705 ctx->gs_out_ring_offset += 16;
706 }
707 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
708 switch (d->Semantic.Name) {
709 case TGSI_SEMANTIC_COLOR:
710 ctx->shader->nr_ps_max_color_exports++;
711 break;
712 }
713 }
714 }
715 ctx->shader->noutput += count;
716 break;
717 case TGSI_FILE_TEMPORARY:
718 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
719 if (d->Array.ArrayID) {
720 r600_add_gpr_array(ctx->shader,
721 ctx->file_offset[TGSI_FILE_TEMPORARY] +
722 d->Range.First,
723 d->Range.Last - d->Range.First + 1, 0x0F);
724 }
725 }
726 break;
727
728 case TGSI_FILE_CONSTANT:
729 case TGSI_FILE_SAMPLER:
730 case TGSI_FILE_SAMPLER_VIEW:
731 case TGSI_FILE_ADDRESS:
732 break;
733
734 case TGSI_FILE_SYSTEM_VALUE:
735 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
736 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
737 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
738 break; /* Already handled from allocate_system_value_inputs */
739 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
740 if (!ctx->native_integers) {
741 struct r600_bytecode_alu alu;
742 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
743
744 alu.op = ALU_OP1_INT_TO_FLT;
745 alu.src[0].sel = 0;
746 alu.src[0].chan = 3;
747
748 alu.dst.sel = 0;
749 alu.dst.chan = 3;
750 alu.dst.write = 1;
751 alu.last = 1;
752
753 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
754 return r;
755 }
756 break;
757 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
758 break;
759 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
760 break;
761 default:
762 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
763 return -EINVAL;
764 }
765 return 0;
766 }
767
768 static int r600_get_temp(struct r600_shader_ctx *ctx)
769 {
770 return ctx->temp_reg + ctx->max_driver_temp_used++;
771 }
772
773 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
774 {
775 struct tgsi_parse_context parse;
776 struct {
777 boolean enabled;
778 int *reg;
779 unsigned name, alternate_name;
780 } inputs[2] = {
781 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
782
783 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
784 };
785 int i, k, num_regs = 0;
786
787 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
788 return 0;
789 }
790
791 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
792 while (!tgsi_parse_end_of_tokens(&parse)) {
793 tgsi_parse_token(&parse);
794
795 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
796 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
797 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
798 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
799 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
800 {
801 int interpolate, location, k;
802
803 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
804 location = TGSI_INTERPOLATE_LOC_CENTER;
805 inputs[1].enabled = true; /* needs SAMPLEID */
806 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
807 location = TGSI_INTERPOLATE_LOC_CENTER;
808 /* Needs sample positions, currently those are always available */
809 } else {
810 location = TGSI_INTERPOLATE_LOC_CENTROID;
811 }
812
813 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
814 k = eg_get_interpolator_index(interpolate, location);
815 ctx->eg_interpolators[k].enabled = true;
816 }
817 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
818 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
819 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
820 for (k = 0; k < Elements(inputs); k++) {
821 if (d->Semantic.Name == inputs[k].name ||
822 d->Semantic.Name == inputs[k].alternate_name) {
823 inputs[k].enabled = true;
824 }
825 }
826 }
827 }
828 }
829
830 tgsi_parse_free(&parse);
831
832 for (i = 0; i < Elements(inputs); i++) {
833 boolean enabled = inputs[i].enabled;
834 int *reg = inputs[i].reg;
835 unsigned name = inputs[i].name;
836
837 if (enabled) {
838 int gpr = gpr_offset + num_regs++;
839
840 // add to inputs, allocate a gpr
841 k = ctx->shader->ninput ++;
842 ctx->shader->input[k].name = name;
843 ctx->shader->input[k].sid = 0;
844 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
845 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
846 *reg = ctx->shader->input[k].gpr = gpr;
847 }
848 }
849
850 return gpr_offset + num_regs;
851 }
852
853 /*
854 * for evergreen we need to scan the shader to find the number of GPRs we need to
855 * reserve for interpolation and system values
856 *
857 * we need to know if we are going to emit
858 * any sample or centroid inputs
859 * if perspective and linear are required
860 */
861 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
862 {
863 int i;
864 int num_baryc;
865 struct tgsi_parse_context parse;
866
867 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
868
869 for (i = 0; i < ctx->info.num_inputs; i++) {
870 int k;
871 /* skip position/face/mask/sampleid */
872 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
873 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
874 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
875 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
876 continue;
877
878 k = eg_get_interpolator_index(
879 ctx->info.input_interpolate[i],
880 ctx->info.input_interpolate_loc[i]);
881 if (k >= 0)
882 ctx->eg_interpolators[k].enabled = TRUE;
883 }
884
885 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
886 return 0;
887 }
888
889 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
890 while (!tgsi_parse_end_of_tokens(&parse)) {
891 tgsi_parse_token(&parse);
892
893 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
894 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
895 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
896 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
897 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
898 {
899 int interpolate, location, k;
900
901 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
902 location = TGSI_INTERPOLATE_LOC_CENTER;
903 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
904 location = TGSI_INTERPOLATE_LOC_CENTER;
905 } else {
906 location = TGSI_INTERPOLATE_LOC_CENTROID;
907 }
908
909 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
910 k = eg_get_interpolator_index(interpolate, location);
911 ctx->eg_interpolators[k].enabled = true;
912 }
913 }
914 }
915
916 tgsi_parse_free(&parse);
917
918 /* assign gpr to each interpolator according to priority */
919 num_baryc = 0;
920 for (i = 0; i < Elements(ctx->eg_interpolators); i++) {
921 if (ctx->eg_interpolators[i].enabled) {
922 ctx->eg_interpolators[i].ij_index = num_baryc;
923 num_baryc ++;
924 }
925 }
926
927 /* XXX PULL MODEL and LINE STIPPLE */
928
929 num_baryc = (num_baryc + 1) >> 1;
930 return allocate_system_value_inputs(ctx, num_baryc);
931 }
932
933 /* sample_id_sel == NULL means fetch for current sample */
934 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
935 {
936 struct r600_bytecode_vtx vtx;
937 int r, t1;
938
939 assert(ctx->fixed_pt_position_gpr != -1);
940
941 t1 = r600_get_temp(ctx);
942
943 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
944 vtx.op = FETCH_OP_VFETCH;
945 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
946 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
947 if (sample_id == NULL) {
948 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
949 vtx.src_sel_x = 3;
950 }
951 else {
952 struct r600_bytecode_alu alu;
953
954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
955 alu.op = ALU_OP1_MOV;
956 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
957 alu.dst.sel = t1;
958 alu.dst.write = 1;
959 alu.last = 1;
960 r = r600_bytecode_add_alu(ctx->bc, &alu);
961 if (r)
962 return r;
963
964 vtx.src_gpr = t1;
965 vtx.src_sel_x = 0;
966 }
967 vtx.mega_fetch_count = 16;
968 vtx.dst_gpr = t1;
969 vtx.dst_sel_x = 0;
970 vtx.dst_sel_y = 1;
971 vtx.dst_sel_z = 2;
972 vtx.dst_sel_w = 3;
973 vtx.data_format = FMT_32_32_32_32_FLOAT;
974 vtx.num_format_all = 2;
975 vtx.format_comp_all = 1;
976 vtx.use_const_fields = 0;
977 vtx.offset = 1; // first element is size of buffer
978 vtx.endian = r600_endian_swap(32);
979 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
980
981 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
982 if (r)
983 return r;
984
985 return t1;
986 }
987
988 static void tgsi_src(struct r600_shader_ctx *ctx,
989 const struct tgsi_full_src_register *tgsi_src,
990 struct r600_shader_src *r600_src)
991 {
992 memset(r600_src, 0, sizeof(*r600_src));
993 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
994 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
995 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
996 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
997 r600_src->neg = tgsi_src->Register.Negate;
998 r600_src->abs = tgsi_src->Register.Absolute;
999
1000 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1001 int index;
1002 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1003 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1004 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1005
1006 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1007 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1008 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1009 return;
1010 }
1011 index = tgsi_src->Register.Index;
1012 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1013 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1014 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1015 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1016 r600_src->swizzle[0] = 2; // Z value
1017 r600_src->swizzle[1] = 2;
1018 r600_src->swizzle[2] = 2;
1019 r600_src->swizzle[3] = 2;
1020 r600_src->sel = ctx->face_gpr;
1021 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1022 r600_src->swizzle[0] = 3; // W value
1023 r600_src->swizzle[1] = 3;
1024 r600_src->swizzle[2] = 3;
1025 r600_src->swizzle[3] = 3;
1026 r600_src->sel = ctx->fixed_pt_position_gpr;
1027 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1028 r600_src->swizzle[0] = 0;
1029 r600_src->swizzle[1] = 1;
1030 r600_src->swizzle[2] = 4;
1031 r600_src->swizzle[3] = 4;
1032 r600_src->sel = load_sample_position(ctx, NULL, -1);
1033 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1034 r600_src->swizzle[0] = 3;
1035 r600_src->swizzle[1] = 3;
1036 r600_src->swizzle[2] = 3;
1037 r600_src->swizzle[3] = 3;
1038 r600_src->sel = 0;
1039 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1040 r600_src->swizzle[0] = 0;
1041 r600_src->swizzle[1] = 0;
1042 r600_src->swizzle[2] = 0;
1043 r600_src->swizzle[3] = 0;
1044 r600_src->sel = 0;
1045 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1046 r600_src->swizzle[0] = 3;
1047 r600_src->swizzle[1] = 3;
1048 r600_src->swizzle[2] = 3;
1049 r600_src->swizzle[3] = 3;
1050 r600_src->sel = 1;
1051 }
1052 } else {
1053 if (tgsi_src->Register.Indirect)
1054 r600_src->rel = V_SQ_REL_RELATIVE;
1055 r600_src->sel = tgsi_src->Register.Index;
1056 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1057 }
1058 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1059 if (tgsi_src->Register.Dimension) {
1060 r600_src->kc_bank = tgsi_src->Dimension.Index;
1061 if (tgsi_src->Dimension.Indirect) {
1062 r600_src->kc_rel = 1;
1063 }
1064 }
1065 }
1066 }
1067
1068 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1069 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1070 unsigned int dst_reg)
1071 {
1072 struct r600_bytecode_vtx vtx;
1073 unsigned int ar_reg;
1074 int r;
1075
1076 if (offset) {
1077 struct r600_bytecode_alu alu;
1078
1079 memset(&alu, 0, sizeof(alu));
1080
1081 alu.op = ALU_OP2_ADD_INT;
1082 alu.src[0].sel = ctx->bc->ar_reg;
1083 alu.src[0].chan = ar_chan;
1084
1085 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1086 alu.src[1].value = offset;
1087
1088 alu.dst.sel = dst_reg;
1089 alu.dst.chan = ar_chan;
1090 alu.dst.write = 1;
1091 alu.last = 1;
1092
1093 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1094 return r;
1095
1096 ar_reg = dst_reg;
1097 } else {
1098 ar_reg = ctx->bc->ar_reg;
1099 }
1100
1101 memset(&vtx, 0, sizeof(vtx));
1102 vtx.buffer_id = cb_idx;
1103 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1104 vtx.src_gpr = ar_reg;
1105 vtx.src_sel_x = ar_chan;
1106 vtx.mega_fetch_count = 16;
1107 vtx.dst_gpr = dst_reg;
1108 vtx.dst_sel_x = 0; /* SEL_X */
1109 vtx.dst_sel_y = 1; /* SEL_Y */
1110 vtx.dst_sel_z = 2; /* SEL_Z */
1111 vtx.dst_sel_w = 3; /* SEL_W */
1112 vtx.data_format = FMT_32_32_32_32_FLOAT;
1113 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1114 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1115 vtx.endian = r600_endian_swap(32);
1116 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1117
1118 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1119 return r;
1120
1121 return 0;
1122 }
1123
1124 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1125 {
1126 struct r600_bytecode_vtx vtx;
1127 int r;
1128 unsigned index = src->Register.Index;
1129 unsigned vtx_id = src->Dimension.Index;
1130 int offset_reg = vtx_id / 3;
1131 int offset_chan = vtx_id % 3;
1132
1133 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1134 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1135
1136 if (offset_reg == 0 && offset_chan == 2)
1137 offset_chan = 3;
1138
1139 if (src->Dimension.Indirect) {
1140 int treg[3];
1141 int t2;
1142 struct r600_bytecode_alu alu;
1143 int r, i;
1144
1145 /* you have got to be shitting me -
1146 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1147 at least this is what fglrx seems to do. */
1148 for (i = 0; i < 3; i++) {
1149 treg[i] = r600_get_temp(ctx);
1150 }
1151 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1152
1153 t2 = r600_get_temp(ctx);
1154 for (i = 0; i < 3; i++) {
1155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1156 alu.op = ALU_OP1_MOV;
1157 alu.src[0].sel = 0;
1158 alu.src[0].chan = i == 2 ? 3 : i;
1159 alu.dst.sel = treg[i];
1160 alu.dst.chan = 0;
1161 alu.dst.write = 1;
1162 alu.last = 1;
1163 r = r600_bytecode_add_alu(ctx->bc, &alu);
1164 if (r)
1165 return r;
1166 }
1167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1168 alu.op = ALU_OP1_MOV;
1169 alu.src[0].sel = treg[0];
1170 alu.src[0].rel = 1;
1171 alu.dst.sel = t2;
1172 alu.dst.write = 1;
1173 alu.last = 1;
1174 r = r600_bytecode_add_alu(ctx->bc, &alu);
1175 if (r)
1176 return r;
1177 offset_reg = t2;
1178 }
1179
1180
1181 memset(&vtx, 0, sizeof(vtx));
1182 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1183 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1184 vtx.src_gpr = offset_reg;
1185 vtx.src_sel_x = offset_chan;
1186 vtx.offset = index * 16; /*bytes*/
1187 vtx.mega_fetch_count = 16;
1188 vtx.dst_gpr = dst_reg;
1189 vtx.dst_sel_x = 0; /* SEL_X */
1190 vtx.dst_sel_y = 1; /* SEL_Y */
1191 vtx.dst_sel_z = 2; /* SEL_Z */
1192 vtx.dst_sel_w = 3; /* SEL_W */
1193 if (ctx->bc->chip_class >= EVERGREEN) {
1194 vtx.use_const_fields = 1;
1195 } else {
1196 vtx.data_format = FMT_32_32_32_32_FLOAT;
1197 }
1198
1199 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1200 return r;
1201
1202 return 0;
1203 }
1204
1205 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1206 {
1207 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1208 int i;
1209
1210 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1211 struct tgsi_full_src_register *src = &inst->Src[i];
1212
1213 if (src->Register.File == TGSI_FILE_INPUT) {
1214 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1215 /* primitive id is in R0.z */
1216 ctx->src[i].sel = 0;
1217 ctx->src[i].swizzle[0] = 2;
1218 }
1219 }
1220 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1221 int treg = r600_get_temp(ctx);
1222
1223 fetch_gs_input(ctx, src, treg);
1224 ctx->src[i].sel = treg;
1225 }
1226 }
1227 return 0;
1228 }
1229
1230 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1231 {
1232 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1233 struct r600_bytecode_alu alu;
1234 int i, j, k, nconst, r;
1235
1236 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1237 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1238 nconst++;
1239 }
1240 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1241 }
1242 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1243 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1244 continue;
1245 }
1246
1247 if (ctx->src[i].rel) {
1248 int chan = inst->Src[i].Indirect.Swizzle;
1249 int treg = r600_get_temp(ctx);
1250 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1251 return r;
1252
1253 ctx->src[i].kc_bank = 0;
1254 ctx->src[i].kc_rel = 0;
1255 ctx->src[i].sel = treg;
1256 ctx->src[i].rel = 0;
1257 j--;
1258 } else if (j > 0) {
1259 int treg = r600_get_temp(ctx);
1260 for (k = 0; k < 4; k++) {
1261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1262 alu.op = ALU_OP1_MOV;
1263 alu.src[0].sel = ctx->src[i].sel;
1264 alu.src[0].chan = k;
1265 alu.src[0].rel = ctx->src[i].rel;
1266 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1267 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1268 alu.dst.sel = treg;
1269 alu.dst.chan = k;
1270 alu.dst.write = 1;
1271 if (k == 3)
1272 alu.last = 1;
1273 r = r600_bytecode_add_alu(ctx->bc, &alu);
1274 if (r)
1275 return r;
1276 }
1277 ctx->src[i].sel = treg;
1278 ctx->src[i].rel =0;
1279 j--;
1280 }
1281 }
1282 return 0;
1283 }
1284
1285 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1286 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1287 {
1288 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1289 struct r600_bytecode_alu alu;
1290 int i, j, k, nliteral, r;
1291
1292 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1293 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1294 nliteral++;
1295 }
1296 }
1297 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1298 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1299 int treg = r600_get_temp(ctx);
1300 for (k = 0; k < 4; k++) {
1301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1302 alu.op = ALU_OP1_MOV;
1303 alu.src[0].sel = ctx->src[i].sel;
1304 alu.src[0].chan = k;
1305 alu.src[0].value = ctx->src[i].value[k];
1306 alu.dst.sel = treg;
1307 alu.dst.chan = k;
1308 alu.dst.write = 1;
1309 if (k == 3)
1310 alu.last = 1;
1311 r = r600_bytecode_add_alu(ctx->bc, &alu);
1312 if (r)
1313 return r;
1314 }
1315 ctx->src[i].sel = treg;
1316 j--;
1317 }
1318 }
1319 return 0;
1320 }
1321
1322 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1323 {
1324 int i, r, count = ctx->shader->ninput;
1325
1326 for (i = 0; i < count; i++) {
1327 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1328 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1329 if (r)
1330 return r;
1331 }
1332 }
1333 return 0;
1334 }
1335
1336 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1337 int stream, unsigned *stream_item_size)
1338 {
1339 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1340 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1341 int i, j, r;
1342
1343 /* Sanity checking. */
1344 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1345 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1346 r = -EINVAL;
1347 goto out_err;
1348 }
1349 for (i = 0; i < so->num_outputs; i++) {
1350 if (so->output[i].output_buffer >= 4) {
1351 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1352 so->output[i].output_buffer);
1353 r = -EINVAL;
1354 goto out_err;
1355 }
1356 }
1357
1358 /* Initialize locations where the outputs are stored. */
1359 for (i = 0; i < so->num_outputs; i++) {
1360
1361 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1362 start_comp[i] = so->output[i].start_component;
1363 /* Lower outputs with dst_offset < start_component.
1364 *
1365 * We can only output 4D vectors with a write mask, e.g. we can
1366 * only output the W component at offset 3, etc. If we want
1367 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1368 * to move it to X and output X. */
1369 if (so->output[i].dst_offset < so->output[i].start_component) {
1370 unsigned tmp = r600_get_temp(ctx);
1371
1372 for (j = 0; j < so->output[i].num_components; j++) {
1373 struct r600_bytecode_alu alu;
1374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1375 alu.op = ALU_OP1_MOV;
1376 alu.src[0].sel = so_gpr[i];
1377 alu.src[0].chan = so->output[i].start_component + j;
1378
1379 alu.dst.sel = tmp;
1380 alu.dst.chan = j;
1381 alu.dst.write = 1;
1382 if (j == so->output[i].num_components - 1)
1383 alu.last = 1;
1384 r = r600_bytecode_add_alu(ctx->bc, &alu);
1385 if (r)
1386 return r;
1387 }
1388 start_comp[i] = 0;
1389 so_gpr[i] = tmp;
1390 }
1391 }
1392
1393 /* Write outputs to buffers. */
1394 for (i = 0; i < so->num_outputs; i++) {
1395 struct r600_bytecode_output output;
1396
1397 if (stream != -1 && stream != so->output[i].output_buffer)
1398 continue;
1399
1400 memset(&output, 0, sizeof(struct r600_bytecode_output));
1401 output.gpr = so_gpr[i];
1402 output.elem_size = so->output[i].num_components - 1;
1403 if (output.elem_size == 2)
1404 output.elem_size = 3; // 3 not supported, write 4 with junk at end
1405 output.array_base = so->output[i].dst_offset - start_comp[i];
1406 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1407 output.burst_count = 1;
1408 /* array_size is an upper limit for the burst_count
1409 * with MEM_STREAM instructions */
1410 output.array_size = 0xFFF;
1411 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
1412
1413 if (ctx->bc->chip_class >= EVERGREEN) {
1414 switch (so->output[i].output_buffer) {
1415 case 0:
1416 output.op = CF_OP_MEM_STREAM0_BUF0;
1417 break;
1418 case 1:
1419 output.op = CF_OP_MEM_STREAM0_BUF1;
1420 break;
1421 case 2:
1422 output.op = CF_OP_MEM_STREAM0_BUF2;
1423 break;
1424 case 3:
1425 output.op = CF_OP_MEM_STREAM0_BUF3;
1426 break;
1427 }
1428 output.op += so->output[i].stream * 4;
1429 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
1430 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
1431 } else {
1432 switch (so->output[i].output_buffer) {
1433 case 0:
1434 output.op = CF_OP_MEM_STREAM0;
1435 break;
1436 case 1:
1437 output.op = CF_OP_MEM_STREAM1;
1438 break;
1439 case 2:
1440 output.op = CF_OP_MEM_STREAM2;
1441 break;
1442 case 3:
1443 output.op = CF_OP_MEM_STREAM3;
1444 break;
1445 }
1446 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
1447 }
1448 r = r600_bytecode_add_output(ctx->bc, &output);
1449 if (r)
1450 goto out_err;
1451 }
1452 return 0;
1453 out_err:
1454 return r;
1455 }
1456
1457 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
1458 {
1459 struct r600_bytecode_alu alu;
1460 unsigned reg;
1461
1462 if (!ctx->shader->vs_out_edgeflag)
1463 return;
1464
1465 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
1466
1467 /* clamp(x, 0, 1) */
1468 memset(&alu, 0, sizeof(alu));
1469 alu.op = ALU_OP1_MOV;
1470 alu.src[0].sel = reg;
1471 alu.dst.sel = reg;
1472 alu.dst.write = 1;
1473 alu.dst.clamp = 1;
1474 alu.last = 1;
1475 r600_bytecode_add_alu(ctx->bc, &alu);
1476
1477 memset(&alu, 0, sizeof(alu));
1478 alu.op = ALU_OP1_FLT_TO_INT;
1479 alu.src[0].sel = reg;
1480 alu.dst.sel = reg;
1481 alu.dst.write = 1;
1482 alu.last = 1;
1483 r600_bytecode_add_alu(ctx->bc, &alu);
1484 }
1485
1486 static int generate_gs_copy_shader(struct r600_context *rctx,
1487 struct r600_pipe_shader *gs,
1488 struct pipe_stream_output_info *so)
1489 {
1490 struct r600_shader_ctx ctx = {};
1491 struct r600_shader *gs_shader = &gs->shader;
1492 struct r600_pipe_shader *cshader;
1493 int ocnt = gs_shader->noutput;
1494 struct r600_bytecode_alu alu;
1495 struct r600_bytecode_vtx vtx;
1496 struct r600_bytecode_output output;
1497 struct r600_bytecode_cf *cf_jump, *cf_pop,
1498 *last_exp_pos = NULL, *last_exp_param = NULL;
1499 int i, j, next_clip_pos = 61, next_param = 0;
1500 int ring;
1501
1502 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1503 if (!cshader)
1504 return 0;
1505
1506 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1507 sizeof(struct r600_shader_io));
1508
1509 cshader->shader.noutput = ocnt;
1510
1511 ctx.shader = &cshader->shader;
1512 ctx.bc = &ctx.shader->bc;
1513 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1514
1515 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1516 rctx->screen->has_compressed_msaa_texturing);
1517
1518 ctx.bc->isa = rctx->isa;
1519
1520 cf_jump = NULL;
1521 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
1522
1523 /* R0.x = R0.x & 0x3fffffff */
1524 memset(&alu, 0, sizeof(alu));
1525 alu.op = ALU_OP2_AND_INT;
1526 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1527 alu.src[1].value = 0x3fffffff;
1528 alu.dst.write = 1;
1529 r600_bytecode_add_alu(ctx.bc, &alu);
1530
1531 /* R0.y = R0.x >> 30 */
1532 memset(&alu, 0, sizeof(alu));
1533 alu.op = ALU_OP2_LSHR_INT;
1534 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1535 alu.src[1].value = 0x1e;
1536 alu.dst.chan = 1;
1537 alu.dst.write = 1;
1538 alu.last = 1;
1539 r600_bytecode_add_alu(ctx.bc, &alu);
1540
1541 /* fetch vertex data from GSVS ring */
1542 for (i = 0; i < ocnt; ++i) {
1543 struct r600_shader_io *out = &ctx.shader->output[i];
1544
1545 out->gpr = i + 1;
1546 out->ring_offset = i * 16;
1547
1548 memset(&vtx, 0, sizeof(vtx));
1549 vtx.op = FETCH_OP_VFETCH;
1550 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1551 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1552 vtx.offset = out->ring_offset;
1553 vtx.dst_gpr = out->gpr;
1554 vtx.src_gpr = 0;
1555 vtx.dst_sel_x = 0;
1556 vtx.dst_sel_y = 1;
1557 vtx.dst_sel_z = 2;
1558 vtx.dst_sel_w = 3;
1559 if (rctx->b.chip_class >= EVERGREEN) {
1560 vtx.use_const_fields = 1;
1561 } else {
1562 vtx.data_format = FMT_32_32_32_32_FLOAT;
1563 }
1564
1565 r600_bytecode_add_vtx(ctx.bc, &vtx);
1566 }
1567 ctx.temp_reg = i + 1;
1568 for (ring = 3; ring >= 0; --ring) {
1569 bool enabled = false;
1570 for (i = 0; i < so->num_outputs; i++) {
1571 if (so->output[i].stream == ring) {
1572 enabled = true;
1573 break;
1574 }
1575 }
1576 if (ring != 0 && !enabled) {
1577 cshader->shader.ring_item_sizes[ring] = 0;
1578 continue;
1579 }
1580
1581 if (cf_jump) {
1582 // Patch up jump label
1583 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1584 cf_pop = ctx.bc->cf_last;
1585
1586 cf_jump->cf_addr = cf_pop->id + 2;
1587 cf_jump->pop_count = 1;
1588 cf_pop->cf_addr = cf_pop->id + 2;
1589 cf_pop->pop_count = 1;
1590 }
1591
1592 /* PRED_SETE_INT __, R0.y, ring */
1593 memset(&alu, 0, sizeof(alu));
1594 alu.op = ALU_OP2_PRED_SETE_INT;
1595 alu.src[0].chan = 1;
1596 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1597 alu.src[1].value = ring;
1598 alu.execute_mask = 1;
1599 alu.update_pred = 1;
1600 alu.last = 1;
1601 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1602
1603 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1604 cf_jump = ctx.bc->cf_last;
1605
1606 if (enabled)
1607 emit_streamout(&ctx, so, ring, &cshader->shader.ring_item_sizes[ring]);
1608 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
1609 }
1610
1611 /* export vertex data */
1612 /* XXX factor out common code with r600_shader_from_tgsi ? */
1613 for (i = 0; i < ocnt; ++i) {
1614 struct r600_shader_io *out = &ctx.shader->output[i];
1615 bool instream0 = true;
1616 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1617 continue;
1618
1619 for (j = 0; j < so->num_outputs; j++) {
1620 if (so->output[j].register_index == i) {
1621 if (so->output[j].stream == 0)
1622 break;
1623 if (so->output[j].stream > 0)
1624 instream0 = false;
1625 }
1626 }
1627 if (!instream0)
1628 continue;
1629 memset(&output, 0, sizeof(output));
1630 output.gpr = out->gpr;
1631 output.elem_size = 3;
1632 output.swizzle_x = 0;
1633 output.swizzle_y = 1;
1634 output.swizzle_z = 2;
1635 output.swizzle_w = 3;
1636 output.burst_count = 1;
1637 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1638 output.op = CF_OP_EXPORT;
1639 switch (out->name) {
1640 case TGSI_SEMANTIC_POSITION:
1641 output.array_base = 60;
1642 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1643 break;
1644
1645 case TGSI_SEMANTIC_PSIZE:
1646 output.array_base = 61;
1647 if (next_clip_pos == 61)
1648 next_clip_pos = 62;
1649 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1650 output.swizzle_y = 7;
1651 output.swizzle_z = 7;
1652 output.swizzle_w = 7;
1653 ctx.shader->vs_out_misc_write = 1;
1654 ctx.shader->vs_out_point_size = 1;
1655 break;
1656 case TGSI_SEMANTIC_LAYER:
1657 if (out->spi_sid) {
1658 /* duplicate it as PARAM to pass to the pixel shader */
1659 output.array_base = next_param++;
1660 r600_bytecode_add_output(ctx.bc, &output);
1661 last_exp_param = ctx.bc->cf_last;
1662 }
1663 output.array_base = 61;
1664 if (next_clip_pos == 61)
1665 next_clip_pos = 62;
1666 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1667 output.swizzle_x = 7;
1668 output.swizzle_y = 7;
1669 output.swizzle_z = 0;
1670 output.swizzle_w = 7;
1671 ctx.shader->vs_out_misc_write = 1;
1672 ctx.shader->vs_out_layer = 1;
1673 break;
1674 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1675 if (out->spi_sid) {
1676 /* duplicate it as PARAM to pass to the pixel shader */
1677 output.array_base = next_param++;
1678 r600_bytecode_add_output(ctx.bc, &output);
1679 last_exp_param = ctx.bc->cf_last;
1680 }
1681 output.array_base = 61;
1682 if (next_clip_pos == 61)
1683 next_clip_pos = 62;
1684 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1685 ctx.shader->vs_out_misc_write = 1;
1686 ctx.shader->vs_out_viewport = 1;
1687 output.swizzle_x = 7;
1688 output.swizzle_y = 7;
1689 output.swizzle_z = 7;
1690 output.swizzle_w = 0;
1691 break;
1692 case TGSI_SEMANTIC_CLIPDIST:
1693 /* spi_sid is 0 for clipdistance outputs that were generated
1694 * for clipvertex - we don't need to pass them to PS */
1695 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
1696 if (out->spi_sid) {
1697 /* duplicate it as PARAM to pass to the pixel shader */
1698 output.array_base = next_param++;
1699 r600_bytecode_add_output(ctx.bc, &output);
1700 last_exp_param = ctx.bc->cf_last;
1701 }
1702 output.array_base = next_clip_pos++;
1703 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1704 break;
1705 case TGSI_SEMANTIC_FOG:
1706 output.swizzle_y = 4; /* 0 */
1707 output.swizzle_z = 4; /* 0 */
1708 output.swizzle_w = 5; /* 1 */
1709 break;
1710 default:
1711 output.array_base = next_param++;
1712 break;
1713 }
1714 r600_bytecode_add_output(ctx.bc, &output);
1715 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1716 last_exp_param = ctx.bc->cf_last;
1717 else
1718 last_exp_pos = ctx.bc->cf_last;
1719 }
1720
1721 if (!last_exp_pos) {
1722 memset(&output, 0, sizeof(output));
1723 output.gpr = 0;
1724 output.elem_size = 3;
1725 output.swizzle_x = 7;
1726 output.swizzle_y = 7;
1727 output.swizzle_z = 7;
1728 output.swizzle_w = 7;
1729 output.burst_count = 1;
1730 output.type = 2;
1731 output.op = CF_OP_EXPORT;
1732 output.array_base = 60;
1733 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1734 r600_bytecode_add_output(ctx.bc, &output);
1735 last_exp_pos = ctx.bc->cf_last;
1736 }
1737
1738 if (!last_exp_param) {
1739 memset(&output, 0, sizeof(output));
1740 output.gpr = 0;
1741 output.elem_size = 3;
1742 output.swizzle_x = 7;
1743 output.swizzle_y = 7;
1744 output.swizzle_z = 7;
1745 output.swizzle_w = 7;
1746 output.burst_count = 1;
1747 output.type = 2;
1748 output.op = CF_OP_EXPORT;
1749 output.array_base = next_param++;
1750 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1751 r600_bytecode_add_output(ctx.bc, &output);
1752 last_exp_param = ctx.bc->cf_last;
1753 }
1754
1755 last_exp_pos->op = CF_OP_EXPORT_DONE;
1756 last_exp_param->op = CF_OP_EXPORT_DONE;
1757
1758 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1759 cf_pop = ctx.bc->cf_last;
1760
1761 cf_jump->cf_addr = cf_pop->id + 2;
1762 cf_jump->pop_count = 1;
1763 cf_pop->cf_addr = cf_pop->id + 2;
1764 cf_pop->pop_count = 1;
1765
1766 if (ctx.bc->chip_class == CAYMAN)
1767 cm_bytecode_add_cf_end(ctx.bc);
1768 else {
1769 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1770 ctx.bc->cf_last->end_of_program = 1;
1771 }
1772
1773 gs->gs_copy_shader = cshader;
1774 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
1775
1776 ctx.bc->nstack = 1;
1777
1778 return r600_bytecode_build(ctx.bc);
1779 }
1780
1781 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
1782 {
1783 struct r600_bytecode_output output;
1784 int i, k, ring_offset;
1785 int effective_stream = stream == -1 ? 0 : stream;
1786 int idx = 0;
1787
1788 for (i = 0; i < ctx->shader->noutput; i++) {
1789 if (ctx->gs_for_vs) {
1790 /* for ES we need to lookup corresponding ring offset expected by GS
1791 * (map this output to GS input by name and sid) */
1792 /* FIXME precompute offsets */
1793 ring_offset = -1;
1794 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1795 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1796 struct r600_shader_io *out = &ctx->shader->output[i];
1797 if (in->name == out->name && in->sid == out->sid)
1798 ring_offset = in->ring_offset;
1799 }
1800
1801 if (ring_offset == -1)
1802 continue;
1803 } else {
1804 ring_offset = idx * 16;
1805 idx++;
1806 }
1807
1808 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
1809 continue;
1810 /* next_ring_offset after parsing input decls contains total size of
1811 * single vertex data, gs_next_vertex - current vertex index */
1812 if (!ind)
1813 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
1814
1815 memset(&output, 0, sizeof(struct r600_bytecode_output));
1816 output.gpr = ctx->shader->output[i].gpr;
1817 output.elem_size = 3;
1818 output.comp_mask = 0xF;
1819 output.burst_count = 1;
1820
1821 if (ind)
1822 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
1823 else
1824 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1825
1826 switch (stream) {
1827 default:
1828 case 0:
1829 output.op = CF_OP_MEM_RING; break;
1830 case 1:
1831 output.op = CF_OP_MEM_RING1; break;
1832 case 2:
1833 output.op = CF_OP_MEM_RING2; break;
1834 case 3:
1835 output.op = CF_OP_MEM_RING3; break;
1836 }
1837
1838 if (ind) {
1839 output.array_base = ring_offset >> 2; /* in dwords */
1840 output.array_size = 0xfff;
1841 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
1842 } else
1843 output.array_base = ring_offset >> 2; /* in dwords */
1844 r600_bytecode_add_output(ctx->bc, &output);
1845 }
1846
1847 if (ind) {
1848 /* get a temp and add the ring offset to the next vertex base in the shader */
1849 struct r600_bytecode_alu alu;
1850 int r;
1851
1852 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1853 alu.op = ALU_OP2_ADD_INT;
1854 alu.src[0].sel = ctx->gs_export_gpr_tregs[effective_stream];
1855 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1856 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
1857 alu.dst.sel = ctx->gs_export_gpr_tregs[effective_stream];
1858 alu.dst.write = 1;
1859 alu.last = 1;
1860 r = r600_bytecode_add_alu(ctx->bc, &alu);
1861 if (r)
1862 return r;
1863 }
1864 ++ctx->gs_next_vertex;
1865 return 0;
1866 }
1867
1868 static int r600_shader_from_tgsi(struct r600_context *rctx,
1869 struct r600_pipe_shader *pipeshader,
1870 union r600_shader_key key)
1871 {
1872 struct r600_screen *rscreen = rctx->screen;
1873 struct r600_shader *shader = &pipeshader->shader;
1874 struct tgsi_token *tokens = pipeshader->selector->tokens;
1875 struct pipe_stream_output_info so = pipeshader->selector->so;
1876 struct tgsi_full_immediate *immediate;
1877 struct r600_shader_ctx ctx;
1878 struct r600_bytecode_output output[32];
1879 unsigned output_done, noutput;
1880 unsigned opcode;
1881 int i, j, k, r = 0;
1882 int next_param_base = 0, next_clip_base;
1883 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
1884 /* Declarations used by llvm code */
1885 bool use_llvm = false;
1886 bool indirect_gprs;
1887 bool ring_outputs = false;
1888 bool pos_emitted = false;
1889
1890 #ifdef R600_USE_LLVM
1891 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
1892 #endif
1893 ctx.bc = &shader->bc;
1894 ctx.shader = shader;
1895 ctx.native_integers = true;
1896
1897
1898 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
1899 rscreen->has_compressed_msaa_texturing);
1900 ctx.tokens = tokens;
1901 tgsi_scan_shader(tokens, &ctx.info);
1902 shader->indirect_files = ctx.info.indirect_files;
1903
1904 shader->uses_doubles = ctx.info.uses_doubles;
1905
1906 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
1907 tgsi_parse_init(&ctx.parse, tokens);
1908 ctx.type = ctx.info.processor;
1909 shader->processor_type = ctx.type;
1910 ctx.bc->type = shader->processor_type;
1911
1912 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1913 shader->vs_as_gs_a = key.vs.as_gs_a;
1914 shader->vs_as_es = key.vs.as_es;
1915 }
1916
1917 ring_outputs = shader->vs_as_es || ctx.type == TGSI_PROCESSOR_GEOMETRY;
1918
1919 if (shader->vs_as_es) {
1920 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
1921 } else {
1922 ctx.gs_for_vs = NULL;
1923 }
1924
1925 ctx.next_ring_offset = 0;
1926 ctx.gs_out_ring_offset = 0;
1927 ctx.gs_next_vertex = 0;
1928 ctx.gs_stream_output_info = &so;
1929
1930 ctx.face_gpr = -1;
1931 ctx.fixed_pt_position_gpr = -1;
1932 ctx.fragcoord_input = -1;
1933 ctx.colors_used = 0;
1934 ctx.clip_vertex_write = 0;
1935
1936 shader->nr_ps_color_exports = 0;
1937 shader->nr_ps_max_color_exports = 0;
1938
1939 if (ctx.type == TGSI_PROCESSOR_FRAGMENT)
1940 shader->two_side = key.ps.color_two_side;
1941
1942 /* register allocations */
1943 /* Values [0,127] correspond to GPR[0..127].
1944 * Values [128,159] correspond to constant buffer bank 0
1945 * Values [160,191] correspond to constant buffer bank 1
1946 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1947 * Values [256,287] correspond to constant buffer bank 2 (EG)
1948 * Values [288,319] correspond to constant buffer bank 3 (EG)
1949 * Other special values are shown in the list below.
1950 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1951 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1952 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1953 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1954 * 248 SQ_ALU_SRC_0: special constant 0.0.
1955 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1956 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1957 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1958 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1959 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1960 * 254 SQ_ALU_SRC_PV: previous vector result.
1961 * 255 SQ_ALU_SRC_PS: previous scalar result.
1962 */
1963 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1964 ctx.file_offset[i] = 0;
1965 }
1966
1967 #ifdef R600_USE_LLVM
1968 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1969 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1970 "indirect adressing. Falling back to TGSI "
1971 "backend.\n");
1972 use_llvm = 0;
1973 }
1974 #endif
1975 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1976 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1977 if (!use_llvm) {
1978 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1979 }
1980 }
1981 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
1982 if (ctx.bc->chip_class >= EVERGREEN)
1983 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1984 else
1985 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
1986 }
1987 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1988 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
1989 ctx.file_offset[TGSI_FILE_INPUT] = 2;
1990 }
1991 ctx.use_llvm = use_llvm;
1992
1993 if (use_llvm) {
1994 ctx.file_offset[TGSI_FILE_OUTPUT] =
1995 ctx.file_offset[TGSI_FILE_INPUT];
1996 } else {
1997 ctx.file_offset[TGSI_FILE_OUTPUT] =
1998 ctx.file_offset[TGSI_FILE_INPUT] +
1999 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2000 }
2001 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
2002 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
2003
2004 /* Outside the GPR range. This will be translated to one of the
2005 * kcache banks later. */
2006 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
2007
2008 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
2009 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
2010 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
2011 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
2012 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
2013
2014 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2015 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
2016 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
2017 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
2018 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
2019 ctx.temp_reg = ctx.bc->ar_reg + 7;
2020 } else {
2021 ctx.temp_reg = ctx.bc->ar_reg + 3;
2022 }
2023
2024 shader->max_arrays = 0;
2025 shader->num_arrays = 0;
2026 if (indirect_gprs) {
2027
2028 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
2029 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
2030 ctx.file_offset[TGSI_FILE_OUTPUT] -
2031 ctx.file_offset[TGSI_FILE_INPUT],
2032 0x0F);
2033 }
2034 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
2035 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
2036 ctx.file_offset[TGSI_FILE_TEMPORARY] -
2037 ctx.file_offset[TGSI_FILE_OUTPUT],
2038 0x0F);
2039 }
2040 }
2041
2042 ctx.nliterals = 0;
2043 ctx.literals = NULL;
2044
2045 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS];
2046 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2047 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
2048
2049 if (shader->vs_as_gs_a)
2050 vs_add_primid_output(&ctx, key.vs.prim_id_out);
2051
2052 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2053 tgsi_parse_token(&ctx.parse);
2054 switch (ctx.parse.FullToken.Token.Type) {
2055 case TGSI_TOKEN_TYPE_IMMEDIATE:
2056 immediate = &ctx.parse.FullToken.FullImmediate;
2057 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
2058 if(ctx.literals == NULL) {
2059 r = -ENOMEM;
2060 goto out_err;
2061 }
2062 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
2063 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
2064 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
2065 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
2066 ctx.nliterals++;
2067 break;
2068 case TGSI_TOKEN_TYPE_DECLARATION:
2069 r = tgsi_declaration(&ctx);
2070 if (r)
2071 goto out_err;
2072 break;
2073 case TGSI_TOKEN_TYPE_INSTRUCTION:
2074 case TGSI_TOKEN_TYPE_PROPERTY:
2075 break;
2076 default:
2077 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
2078 r = -EINVAL;
2079 goto out_err;
2080 }
2081 }
2082
2083 shader->ring_item_sizes[0] = ctx.next_ring_offset;
2084 shader->ring_item_sizes[1] = 0;
2085 shader->ring_item_sizes[2] = 0;
2086 shader->ring_item_sizes[3] = 0;
2087
2088 /* Process two side if needed */
2089 if (shader->two_side && ctx.colors_used) {
2090 int i, count = ctx.shader->ninput;
2091 unsigned next_lds_loc = ctx.shader->nlds;
2092
2093 /* additional inputs will be allocated right after the existing inputs,
2094 * we won't need them after the color selection, so we don't need to
2095 * reserve these gprs for the rest of the shader code and to adjust
2096 * output offsets etc. */
2097 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
2098 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2099
2100 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
2101 if (ctx.face_gpr == -1) {
2102 i = ctx.shader->ninput++;
2103 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
2104 ctx.shader->input[i].spi_sid = 0;
2105 ctx.shader->input[i].gpr = gpr++;
2106 ctx.face_gpr = ctx.shader->input[i].gpr;
2107 }
2108
2109 for (i = 0; i < count; i++) {
2110 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2111 int ni = ctx.shader->ninput++;
2112 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
2113 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
2114 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
2115 ctx.shader->input[ni].gpr = gpr++;
2116 // TGSI to LLVM needs to know the lds position of inputs.
2117 // Non LLVM path computes it later (in process_twoside_color)
2118 ctx.shader->input[ni].lds_pos = next_lds_loc++;
2119 ctx.shader->input[i].back_color_input = ni;
2120 if (ctx.bc->chip_class >= EVERGREEN) {
2121 if ((r = evergreen_interp_input(&ctx, ni)))
2122 return r;
2123 }
2124 }
2125 }
2126 }
2127
2128 /* LLVM backend setup */
2129 #ifdef R600_USE_LLVM
2130 if (use_llvm) {
2131 struct radeon_llvm_context radeon_llvm_ctx;
2132 LLVMModuleRef mod;
2133 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
2134 boolean use_kill = false;
2135
2136 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
2137 radeon_llvm_ctx.type = ctx.type;
2138 radeon_llvm_ctx.two_side = shader->two_side;
2139 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
2140 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
2141 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
2142 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
2143 radeon_llvm_ctx.color_buffer_count = max_color_exports;
2144 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
2145 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
2146 radeon_llvm_ctx.stream_outputs = &so;
2147 radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
2148 radeon_llvm_ctx.has_compressed_msaa_texturing =
2149 ctx.bc->has_compressed_msaa_texturing;
2150 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
2151 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
2152 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
2153
2154 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
2155 radeon_llvm_dispose(&radeon_llvm_ctx);
2156 use_llvm = 0;
2157 fprintf(stderr, "R600 LLVM backend failed to compile "
2158 "shader. Falling back to TGSI\n");
2159 } else {
2160 ctx.file_offset[TGSI_FILE_OUTPUT] =
2161 ctx.file_offset[TGSI_FILE_INPUT];
2162 }
2163 if (use_kill)
2164 ctx.shader->uses_kill = use_kill;
2165 radeon_llvm_dispose(&radeon_llvm_ctx);
2166 }
2167 #endif
2168 /* End of LLVM backend setup */
2169
2170 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
2171 shader->nr_ps_max_color_exports = 8;
2172
2173 if (!use_llvm) {
2174 if (ctx.fragcoord_input >= 0) {
2175 if (ctx.bc->chip_class == CAYMAN) {
2176 for (j = 0 ; j < 4; j++) {
2177 struct r600_bytecode_alu alu;
2178 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2179 alu.op = ALU_OP1_RECIP_IEEE;
2180 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2181 alu.src[0].chan = 3;
2182
2183 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2184 alu.dst.chan = j;
2185 alu.dst.write = (j == 3);
2186 alu.last = 1;
2187 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2188 return r;
2189 }
2190 } else {
2191 struct r600_bytecode_alu alu;
2192 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2193 alu.op = ALU_OP1_RECIP_IEEE;
2194 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2195 alu.src[0].chan = 3;
2196
2197 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2198 alu.dst.chan = 3;
2199 alu.dst.write = 1;
2200 alu.last = 1;
2201 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2202 return r;
2203 }
2204 }
2205
2206 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2207 struct r600_bytecode_alu alu;
2208 int r;
2209 for (j = 0; j < 4; j++) {
2210 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2211 alu.op = ALU_OP1_MOV;
2212 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2213 alu.src[0].value = 0;
2214 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
2215 alu.dst.write = 1;
2216 alu.last = 1;
2217 r = r600_bytecode_add_alu(ctx.bc, &alu);
2218 if (r)
2219 return r;
2220 }
2221 }
2222 if (shader->two_side && ctx.colors_used) {
2223 if ((r = process_twoside_color_inputs(&ctx)))
2224 return r;
2225 }
2226
2227 tgsi_parse_init(&ctx.parse, tokens);
2228 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2229 tgsi_parse_token(&ctx.parse);
2230 switch (ctx.parse.FullToken.Token.Type) {
2231 case TGSI_TOKEN_TYPE_INSTRUCTION:
2232 r = tgsi_is_supported(&ctx);
2233 if (r)
2234 goto out_err;
2235 ctx.max_driver_temp_used = 0;
2236 /* reserve first tmp for everyone */
2237 r600_get_temp(&ctx);
2238
2239 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
2240 if ((r = tgsi_split_constant(&ctx)))
2241 goto out_err;
2242 if ((r = tgsi_split_literal_constant(&ctx)))
2243 goto out_err;
2244 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
2245 if ((r = tgsi_split_gs_inputs(&ctx)))
2246 goto out_err;
2247 if (ctx.bc->chip_class == CAYMAN)
2248 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
2249 else if (ctx.bc->chip_class >= EVERGREEN)
2250 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
2251 else
2252 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
2253 r = ctx.inst_info->process(&ctx);
2254 if (r)
2255 goto out_err;
2256 break;
2257 default:
2258 break;
2259 }
2260 }
2261 }
2262
2263 /* Reset the temporary register counter. */
2264 ctx.max_driver_temp_used = 0;
2265
2266 noutput = shader->noutput;
2267
2268 if (!ring_outputs && ctx.clip_vertex_write) {
2269 unsigned clipdist_temp[2];
2270
2271 clipdist_temp[0] = r600_get_temp(&ctx);
2272 clipdist_temp[1] = r600_get_temp(&ctx);
2273
2274 /* need to convert a clipvertex write into clipdistance writes and not export
2275 the clip vertex anymore */
2276
2277 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
2278 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2279 shader->output[noutput].gpr = clipdist_temp[0];
2280 noutput++;
2281 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2282 shader->output[noutput].gpr = clipdist_temp[1];
2283 noutput++;
2284
2285 /* reset spi_sid for clipvertex output to avoid confusing spi */
2286 shader->output[ctx.cv_output].spi_sid = 0;
2287
2288 shader->clip_dist_write = 0xFF;
2289
2290 for (i = 0; i < 8; i++) {
2291 int oreg = i >> 2;
2292 int ochan = i & 3;
2293
2294 for (j = 0; j < 4; j++) {
2295 struct r600_bytecode_alu alu;
2296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2297 alu.op = ALU_OP2_DOT4;
2298 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
2299 alu.src[0].chan = j;
2300
2301 alu.src[1].sel = 512 + i;
2302 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
2303 alu.src[1].chan = j;
2304
2305 alu.dst.sel = clipdist_temp[oreg];
2306 alu.dst.chan = j;
2307 alu.dst.write = (j == ochan);
2308 if (j == 3)
2309 alu.last = 1;
2310 if (!use_llvm)
2311 r = r600_bytecode_add_alu(ctx.bc, &alu);
2312 if (r)
2313 return r;
2314 }
2315 }
2316 }
2317
2318 /* Add stream outputs. */
2319 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
2320 so.num_outputs && !use_llvm)
2321 emit_streamout(&ctx, &so, -1, NULL);
2322
2323 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2324 convert_edgeflag_to_int(&ctx);
2325
2326 if (ring_outputs) {
2327 if (shader->vs_as_es) {
2328 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
2329 ctx.gs_export_gpr_tregs[1] = -1;
2330 ctx.gs_export_gpr_tregs[2] = -1;
2331 ctx.gs_export_gpr_tregs[3] = -1;
2332
2333 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
2334 }
2335 } else {
2336 /* Export output */
2337 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
2338
2339 for (i = 0, j = 0; i < noutput; i++, j++) {
2340 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2341 output[j].gpr = shader->output[i].gpr;
2342 output[j].elem_size = 3;
2343 output[j].swizzle_x = 0;
2344 output[j].swizzle_y = 1;
2345 output[j].swizzle_z = 2;
2346 output[j].swizzle_w = 3;
2347 output[j].burst_count = 1;
2348 output[j].type = -1;
2349 output[j].op = CF_OP_EXPORT;
2350 switch (ctx.type) {
2351 case TGSI_PROCESSOR_VERTEX:
2352 switch (shader->output[i].name) {
2353 case TGSI_SEMANTIC_POSITION:
2354 output[j].array_base = 60;
2355 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2356 pos_emitted = true;
2357 break;
2358
2359 case TGSI_SEMANTIC_PSIZE:
2360 output[j].array_base = 61;
2361 output[j].swizzle_y = 7;
2362 output[j].swizzle_z = 7;
2363 output[j].swizzle_w = 7;
2364 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2365 pos_emitted = true;
2366 break;
2367 case TGSI_SEMANTIC_EDGEFLAG:
2368 output[j].array_base = 61;
2369 output[j].swizzle_x = 7;
2370 output[j].swizzle_y = 0;
2371 output[j].swizzle_z = 7;
2372 output[j].swizzle_w = 7;
2373 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2374 pos_emitted = true;
2375 break;
2376 case TGSI_SEMANTIC_LAYER:
2377 /* spi_sid is 0 for outputs that are
2378 * not consumed by PS */
2379 if (shader->output[i].spi_sid) {
2380 output[j].array_base = next_param_base++;
2381 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2382 j++;
2383 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2384 }
2385 output[j].array_base = 61;
2386 output[j].swizzle_x = 7;
2387 output[j].swizzle_y = 7;
2388 output[j].swizzle_z = 0;
2389 output[j].swizzle_w = 7;
2390 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2391 pos_emitted = true;
2392 break;
2393 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2394 /* spi_sid is 0 for outputs that are
2395 * not consumed by PS */
2396 if (shader->output[i].spi_sid) {
2397 output[j].array_base = next_param_base++;
2398 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2399 j++;
2400 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2401 }
2402 output[j].array_base = 61;
2403 output[j].swizzle_x = 7;
2404 output[j].swizzle_y = 7;
2405 output[j].swizzle_z = 7;
2406 output[j].swizzle_w = 0;
2407 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2408 pos_emitted = true;
2409 break;
2410 case TGSI_SEMANTIC_CLIPVERTEX:
2411 j--;
2412 break;
2413 case TGSI_SEMANTIC_CLIPDIST:
2414 output[j].array_base = next_clip_base++;
2415 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2416 pos_emitted = true;
2417 /* spi_sid is 0 for clipdistance outputs that were generated
2418 * for clipvertex - we don't need to pass them to PS */
2419 if (shader->output[i].spi_sid) {
2420 j++;
2421 /* duplicate it as PARAM to pass to the pixel shader */
2422 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2423 output[j].array_base = next_param_base++;
2424 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2425 }
2426 break;
2427 case TGSI_SEMANTIC_FOG:
2428 output[j].swizzle_y = 4; /* 0 */
2429 output[j].swizzle_z = 4; /* 0 */
2430 output[j].swizzle_w = 5; /* 1 */
2431 break;
2432 case TGSI_SEMANTIC_PRIMID:
2433 output[j].swizzle_x = 2;
2434 output[j].swizzle_y = 4; /* 0 */
2435 output[j].swizzle_z = 4; /* 0 */
2436 output[j].swizzle_w = 4; /* 0 */
2437 break;
2438 }
2439
2440 break;
2441 case TGSI_PROCESSOR_FRAGMENT:
2442 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
2443 /* never export more colors than the number of CBs */
2444 if (shader->output[i].sid >= max_color_exports) {
2445 /* skip export */
2446 j--;
2447 continue;
2448 }
2449 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2450 output[j].array_base = shader->output[i].sid;
2451 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2452 shader->nr_ps_color_exports++;
2453 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
2454 for (k = 1; k < max_color_exports; k++) {
2455 j++;
2456 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2457 output[j].gpr = shader->output[i].gpr;
2458 output[j].elem_size = 3;
2459 output[j].swizzle_x = 0;
2460 output[j].swizzle_y = 1;
2461 output[j].swizzle_z = 2;
2462 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2463 output[j].burst_count = 1;
2464 output[j].array_base = k;
2465 output[j].op = CF_OP_EXPORT;
2466 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2467 shader->nr_ps_color_exports++;
2468 }
2469 }
2470 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
2471 output[j].array_base = 61;
2472 output[j].swizzle_x = 2;
2473 output[j].swizzle_y = 7;
2474 output[j].swizzle_z = output[j].swizzle_w = 7;
2475 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2476 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2477 output[j].array_base = 61;
2478 output[j].swizzle_x = 7;
2479 output[j].swizzle_y = 1;
2480 output[j].swizzle_z = output[j].swizzle_w = 7;
2481 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2482 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2483 output[j].array_base = 61;
2484 output[j].swizzle_x = 7;
2485 output[j].swizzle_y = 7;
2486 output[j].swizzle_z = 0;
2487 output[j].swizzle_w = 7;
2488 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2489 } else {
2490 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
2491 r = -EINVAL;
2492 goto out_err;
2493 }
2494 break;
2495 default:
2496 R600_ERR("unsupported processor type %d\n", ctx.type);
2497 r = -EINVAL;
2498 goto out_err;
2499 }
2500
2501 if (output[j].type==-1) {
2502 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2503 output[j].array_base = next_param_base++;
2504 }
2505 }
2506
2507 /* add fake position export */
2508 if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
2509 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2510 output[j].gpr = 0;
2511 output[j].elem_size = 3;
2512 output[j].swizzle_x = 7;
2513 output[j].swizzle_y = 7;
2514 output[j].swizzle_z = 7;
2515 output[j].swizzle_w = 7;
2516 output[j].burst_count = 1;
2517 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2518 output[j].array_base = 60;
2519 output[j].op = CF_OP_EXPORT;
2520 j++;
2521 }
2522
2523 /* add fake param output for vertex shader if no param is exported */
2524 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
2525 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2526 output[j].gpr = 0;
2527 output[j].elem_size = 3;
2528 output[j].swizzle_x = 7;
2529 output[j].swizzle_y = 7;
2530 output[j].swizzle_z = 7;
2531 output[j].swizzle_w = 7;
2532 output[j].burst_count = 1;
2533 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2534 output[j].array_base = 0;
2535 output[j].op = CF_OP_EXPORT;
2536 j++;
2537 }
2538
2539 /* add fake pixel export */
2540 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
2541 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2542 output[j].gpr = 0;
2543 output[j].elem_size = 3;
2544 output[j].swizzle_x = 7;
2545 output[j].swizzle_y = 7;
2546 output[j].swizzle_z = 7;
2547 output[j].swizzle_w = 7;
2548 output[j].burst_count = 1;
2549 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2550 output[j].array_base = 0;
2551 output[j].op = CF_OP_EXPORT;
2552 j++;
2553 shader->nr_ps_color_exports++;
2554 }
2555
2556 noutput = j;
2557
2558 /* set export done on last export of each type */
2559 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
2560 if (!(output_done & (1 << output[i].type))) {
2561 output_done |= (1 << output[i].type);
2562 output[i].op = CF_OP_EXPORT_DONE;
2563 }
2564 }
2565 /* add output to bytecode */
2566 if (!use_llvm) {
2567 for (i = 0; i < noutput; i++) {
2568 r = r600_bytecode_add_output(ctx.bc, &output[i]);
2569 if (r)
2570 goto out_err;
2571 }
2572 }
2573 }
2574
2575 /* add program end */
2576 if (!use_llvm) {
2577 if (ctx.bc->chip_class == CAYMAN)
2578 cm_bytecode_add_cf_end(ctx.bc);
2579 else {
2580 const struct cf_op_info *last = NULL;
2581
2582 if (ctx.bc->cf_last)
2583 last = r600_isa_cf(ctx.bc->cf_last->op);
2584
2585 /* alu clause instructions don't have EOP bit, so add NOP */
2586 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
2587 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2588
2589 ctx.bc->cf_last->end_of_program = 1;
2590 }
2591 }
2592
2593 /* check GPR limit - we have 124 = 128 - 4
2594 * (4 are reserved as alu clause temporary registers) */
2595 if (ctx.bc->ngpr > 124) {
2596 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
2597 r = -ENOMEM;
2598 goto out_err;
2599 }
2600
2601 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2602 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
2603 return r;
2604 }
2605
2606 free(ctx.literals);
2607 tgsi_parse_free(&ctx.parse);
2608 return 0;
2609 out_err:
2610 free(ctx.literals);
2611 tgsi_parse_free(&ctx.parse);
2612 return r;
2613 }
2614
2615 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
2616 {
2617 const unsigned tgsi_opcode =
2618 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
2619 R600_ERR("%s tgsi opcode unsupported\n",
2620 tgsi_get_opcode_name(tgsi_opcode));
2621 return -EINVAL;
2622 }
2623
2624 static int tgsi_end(struct r600_shader_ctx *ctx)
2625 {
2626 return 0;
2627 }
2628
2629 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
2630 const struct r600_shader_src *shader_src,
2631 unsigned chan)
2632 {
2633 bc_src->sel = shader_src->sel;
2634 bc_src->chan = shader_src->swizzle[chan];
2635 bc_src->neg = shader_src->neg;
2636 bc_src->abs = shader_src->abs;
2637 bc_src->rel = shader_src->rel;
2638 bc_src->value = shader_src->value[bc_src->chan];
2639 bc_src->kc_bank = shader_src->kc_bank;
2640 bc_src->kc_rel = shader_src->kc_rel;
2641 }
2642
2643 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
2644 {
2645 bc_src->abs = 1;
2646 bc_src->neg = 0;
2647 }
2648
2649 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2650 {
2651 bc_src->neg = !bc_src->neg;
2652 }
2653
2654 static void tgsi_dst(struct r600_shader_ctx *ctx,
2655 const struct tgsi_full_dst_register *tgsi_dst,
2656 unsigned swizzle,
2657 struct r600_bytecode_alu_dst *r600_dst)
2658 {
2659 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2660
2661 r600_dst->sel = tgsi_dst->Register.Index;
2662 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2663 r600_dst->chan = swizzle;
2664 r600_dst->write = 1;
2665 if (tgsi_dst->Register.Indirect)
2666 r600_dst->rel = V_SQ_REL_RELATIVE;
2667 if (inst->Instruction.Saturate) {
2668 r600_dst->clamp = 1;
2669 }
2670 }
2671
2672 static int tgsi_last_instruction(unsigned writemask)
2673 {
2674 int i, lasti = 0;
2675
2676 for (i = 0; i < 4; i++) {
2677 if (writemask & (1 << i)) {
2678 lasti = i;
2679 }
2680 }
2681 return lasti;
2682 }
2683
2684
2685
2686 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
2687 {
2688 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2689 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2690 struct r600_bytecode_alu alu;
2691 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2692 int use_tmp = 0;
2693
2694 if (singledest) {
2695 switch (write_mask) {
2696 case 0x1:
2697 write_mask = 0x3;
2698 break;
2699 case 0x2:
2700 use_tmp = 1;
2701 write_mask = 0x3;
2702 break;
2703 case 0x4:
2704 write_mask = 0xc;
2705 break;
2706 case 0x8:
2707 write_mask = 0xc;
2708 use_tmp = 3;
2709 break;
2710 }
2711 }
2712
2713 lasti = tgsi_last_instruction(write_mask);
2714 for (i = 0; i <= lasti; i++) {
2715
2716 if (!(write_mask & (1 << i)))
2717 continue;
2718
2719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2720
2721 if (singledest) {
2722 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2723 if (use_tmp) {
2724 alu.dst.sel = ctx->temp_reg;
2725 alu.dst.chan = i;
2726 alu.dst.write = 1;
2727 }
2728 if (i == 1 || i == 3)
2729 alu.dst.write = 0;
2730 } else
2731 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2732
2733 alu.op = ctx->inst_info->op;
2734 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
2735 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2736 } else if (!swap) {
2737 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2738 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
2739 }
2740 } else {
2741 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
2742 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
2743 }
2744
2745 /* handle some special cases */
2746 if (i == 1 || i == 3) {
2747 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
2748 case TGSI_OPCODE_SUB:
2749 r600_bytecode_src_toggle_neg(&alu.src[1]);
2750 break;
2751 case TGSI_OPCODE_DABS:
2752 r600_bytecode_src_set_abs(&alu.src[0]);
2753 break;
2754 default:
2755 break;
2756 }
2757 }
2758 if (i == lasti) {
2759 alu.last = 1;
2760 }
2761 r = r600_bytecode_add_alu(ctx->bc, &alu);
2762 if (r)
2763 return r;
2764 }
2765
2766 if (use_tmp) {
2767 write_mask = inst->Dst[0].Register.WriteMask;
2768
2769 /* move result from temp to dst */
2770 for (i = 0; i <= lasti; i++) {
2771 if (!(write_mask & (1 << i)))
2772 continue;
2773
2774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2775 alu.op = ALU_OP1_MOV;
2776 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2777 alu.src[0].sel = ctx->temp_reg;
2778 alu.src[0].chan = use_tmp - 1;
2779 alu.last = (i == lasti);
2780
2781 r = r600_bytecode_add_alu(ctx->bc, &alu);
2782 if (r)
2783 return r;
2784 }
2785 }
2786 return 0;
2787 }
2788
2789 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
2790 {
2791 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2792 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2793 /* confirm writemasking */
2794 if ((write_mask & 0x3) != 0x3 &&
2795 (write_mask & 0xc) != 0xc) {
2796 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
2797 return -1;
2798 }
2799 return tgsi_op2_64_params(ctx, false, false);
2800 }
2801
2802 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
2803 {
2804 return tgsi_op2_64_params(ctx, true, false);
2805 }
2806
2807 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
2808 {
2809 return tgsi_op2_64_params(ctx, true, true);
2810 }
2811
2812 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
2813 {
2814 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2815 struct r600_bytecode_alu alu;
2816 int i, j, r;
2817 int lasti = 3;
2818 int tmp = r600_get_temp(ctx);
2819
2820 for (i = 0; i < lasti + 1; i++) {
2821
2822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2823 alu.op = ctx->inst_info->op;
2824 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2825 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
2826 }
2827
2828 if (inst->Dst[0].Register.WriteMask & (1 << i))
2829 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2830 else
2831 alu.dst.sel = tmp;
2832
2833 alu.dst.chan = i;
2834 alu.is_op3 = 1;
2835 if (i == lasti) {
2836 alu.last = 1;
2837 }
2838 r = r600_bytecode_add_alu(ctx->bc, &alu);
2839 if (r)
2840 return r;
2841 }
2842 return 0;
2843 }
2844
2845 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
2846 {
2847 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2848 struct r600_bytecode_alu alu;
2849 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2850 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2851 /* use temp register if trans_only and more than one dst component */
2852 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
2853
2854 for (i = 0; i <= lasti; i++) {
2855 if (!(write_mask & (1 << i)))
2856 continue;
2857
2858 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2859 if (use_tmp) {
2860 alu.dst.sel = ctx->temp_reg;
2861 alu.dst.chan = i;
2862 alu.dst.write = 1;
2863 } else
2864 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2865
2866 alu.op = ctx->inst_info->op;
2867 if (!swap) {
2868 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2869 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2870 }
2871 } else {
2872 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2873 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2874 }
2875 /* handle some special cases */
2876 switch (inst->Instruction.Opcode) {
2877 case TGSI_OPCODE_SUB:
2878 r600_bytecode_src_toggle_neg(&alu.src[1]);
2879 break;
2880 case TGSI_OPCODE_ABS:
2881 r600_bytecode_src_set_abs(&alu.src[0]);
2882 break;
2883 default:
2884 break;
2885 }
2886 if (i == lasti || trans_only) {
2887 alu.last = 1;
2888 }
2889 r = r600_bytecode_add_alu(ctx->bc, &alu);
2890 if (r)
2891 return r;
2892 }
2893
2894 if (use_tmp) {
2895 /* move result from temp to dst */
2896 for (i = 0; i <= lasti; i++) {
2897 if (!(write_mask & (1 << i)))
2898 continue;
2899
2900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2901 alu.op = ALU_OP1_MOV;
2902 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2903 alu.src[0].sel = ctx->temp_reg;
2904 alu.src[0].chan = i;
2905 alu.last = (i == lasti);
2906
2907 r = r600_bytecode_add_alu(ctx->bc, &alu);
2908 if (r)
2909 return r;
2910 }
2911 }
2912 return 0;
2913 }
2914
2915 static int tgsi_op2(struct r600_shader_ctx *ctx)
2916 {
2917 return tgsi_op2_s(ctx, 0, 0);
2918 }
2919
2920 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2921 {
2922 return tgsi_op2_s(ctx, 1, 0);
2923 }
2924
2925 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2926 {
2927 return tgsi_op2_s(ctx, 0, 1);
2928 }
2929
2930 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2931 {
2932 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2933 struct r600_bytecode_alu alu;
2934 int i, r;
2935 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2936
2937 for (i = 0; i < lasti + 1; i++) {
2938
2939 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2940 continue;
2941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2942 alu.op = ctx->inst_info->op;
2943
2944 alu.src[0].sel = V_SQ_ALU_SRC_0;
2945
2946 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2947
2948 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2949
2950 if (i == lasti) {
2951 alu.last = 1;
2952 }
2953 r = r600_bytecode_add_alu(ctx->bc, &alu);
2954 if (r)
2955 return r;
2956 }
2957 return 0;
2958
2959 }
2960
2961 static int tgsi_dneg(struct r600_shader_ctx *ctx)
2962 {
2963 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2964 struct r600_bytecode_alu alu;
2965 int i, r;
2966 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2967
2968 for (i = 0; i < lasti + 1; i++) {
2969
2970 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2971 continue;
2972 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2973 alu.op = ALU_OP1_MOV;
2974
2975 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2976
2977 if (i == 1 || i == 3)
2978 r600_bytecode_src_toggle_neg(&alu.src[0]);
2979 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2980
2981 if (i == lasti) {
2982 alu.last = 1;
2983 }
2984 r = r600_bytecode_add_alu(ctx->bc, &alu);
2985 if (r)
2986 return r;
2987 }
2988 return 0;
2989
2990 }
2991
2992 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
2993 {
2994 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2995 struct r600_bytecode_alu alu;
2996 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2997 int i, j, r;
2998 int firsti = write_mask == 0xc ? 2 : 0;
2999
3000 for (i = 0; i <= 3; i++) {
3001 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3002 alu.op = ctx->inst_info->op;
3003
3004 alu.dst.sel = ctx->temp_reg;
3005 alu.dst.chan = i;
3006 alu.dst.write = 1;
3007 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3008 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3009 }
3010
3011 if (i == 3)
3012 alu.last = 1;
3013
3014 r = r600_bytecode_add_alu(ctx->bc, &alu);
3015 if (r)
3016 return r;
3017 }
3018
3019 /* MOV first two channels to writemask dst0 */
3020 for (i = 0; i <= 1; i++) {
3021 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3022 alu.op = ALU_OP1_MOV;
3023 alu.src[0].chan = i + 2;
3024 alu.src[0].sel = ctx->temp_reg;
3025
3026 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
3027 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
3028 alu.last = 1;
3029 r = r600_bytecode_add_alu(ctx->bc, &alu);
3030 if (r)
3031 return r;
3032 }
3033
3034 for (i = 0; i <= 3; i++) {
3035 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
3036 /* MOV third channels to writemask dst1 */
3037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3038 alu.op = ALU_OP1_MOV;
3039 alu.src[0].chan = 1;
3040 alu.src[0].sel = ctx->temp_reg;
3041
3042 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
3043 alu.last = 1;
3044 r = r600_bytecode_add_alu(ctx->bc, &alu);
3045 if (r)
3046 return r;
3047 break;
3048 }
3049 }
3050 return 0;
3051 }
3052
3053
3054 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
3055 {
3056 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3057 struct r600_bytecode_alu alu;
3058 int i, r;
3059 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3060
3061 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
3062 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
3063
3064 for (i = 0; i <= (lasti+1)/2; i++) {
3065 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3066 alu.op = ctx->inst_info->op;
3067
3068 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3069 alu.dst.sel = ctx->temp_reg;
3070 alu.dst.chan = i;
3071 alu.dst.write = 1;
3072 alu.last = 1;
3073
3074 r = r600_bytecode_add_alu(ctx->bc, &alu);
3075 if (r)
3076 return r;
3077 }
3078
3079 for (i = 0; i <= lasti; i++) {
3080 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3081 alu.op = ALU_OP1_FLT32_TO_FLT64;
3082
3083 alu.src[0].chan = i/2;
3084 if (i%2 == 0)
3085 alu.src[0].sel = ctx->temp_reg;
3086 else {
3087 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3088 alu.src[0].value = 0x0;
3089 }
3090 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3091 alu.last = i == lasti;
3092
3093 r = r600_bytecode_add_alu(ctx->bc, &alu);
3094 if (r)
3095 return r;
3096 }
3097
3098 return 0;
3099 }
3100
3101 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
3102 {
3103 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3104 struct r600_bytecode_alu alu;
3105 int i, r;
3106 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3107
3108 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
3109 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
3110
3111 for (i = 0; i <= lasti; i++) {
3112 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3113 alu.op = ALU_OP1_FLT64_TO_FLT32;
3114
3115 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
3116 alu.dst.chan = i;
3117 alu.dst.sel = ctx->temp_reg;
3118 alu.dst.write = i%2 == 0;
3119 alu.last = i == lasti;
3120
3121 r = r600_bytecode_add_alu(ctx->bc, &alu);
3122 if (r)
3123 return r;
3124 }
3125
3126 for (i = 0; i <= (lasti+1)/2; i++) {
3127 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3128 alu.op = ctx->inst_info->op;
3129
3130 alu.src[0].chan = i*2;
3131 alu.src[0].sel = ctx->temp_reg;
3132 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3133 alu.last = 1;
3134
3135 r = r600_bytecode_add_alu(ctx->bc, &alu);
3136 if (r)
3137 return r;
3138 }
3139
3140 return 0;
3141 }
3142
3143 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
3144 {
3145 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3146 int i, r;
3147 struct r600_bytecode_alu alu;
3148 int last_slot = 3;
3149 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3150 int t1 = ctx->temp_reg;
3151
3152 /* these have to write the result to X/Y by the looks of it */
3153 for (i = 0 ; i < last_slot; i++) {
3154 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3155 alu.op = ctx->inst_info->op;
3156
3157 /* should only be one src regs */
3158 assert (inst->Instruction.NumSrcRegs == 1);
3159
3160 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3161 r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
3162
3163 /* RSQ should take the absolute value of src */
3164 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
3165 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT) {
3166 r600_bytecode_src_set_abs(&alu.src[1]);
3167 }
3168 alu.dst.sel = t1;
3169 alu.dst.chan = i;
3170 alu.dst.write = (i == 0 || i == 1);
3171
3172 if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
3173 alu.last = 1;
3174 r = r600_bytecode_add_alu(ctx->bc, &alu);
3175 if (r)
3176 return r;
3177 }
3178
3179 for (i = 0 ; i <= lasti; i++) {
3180 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3181 continue;
3182 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3183 alu.op = ALU_OP1_MOV;
3184 alu.src[0].sel = t1;
3185 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
3186 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3187 alu.dst.write = 1;
3188 if (i == lasti)
3189 alu.last = 1;
3190 r = r600_bytecode_add_alu(ctx->bc, &alu);
3191 if (r)
3192 return r;
3193 }
3194 return 0;
3195 }
3196
3197 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
3198 {
3199 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3200 int i, j, r;
3201 struct r600_bytecode_alu alu;
3202 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3203
3204 for (i = 0 ; i < last_slot; i++) {
3205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3206 alu.op = ctx->inst_info->op;
3207 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3208 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
3209
3210 /* RSQ should take the absolute value of src */
3211 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
3212 r600_bytecode_src_set_abs(&alu.src[j]);
3213 }
3214 }
3215 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3216 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3217
3218 if (i == last_slot - 1)
3219 alu.last = 1;
3220 r = r600_bytecode_add_alu(ctx->bc, &alu);
3221 if (r)
3222 return r;
3223 }
3224 return 0;
3225 }
3226
3227 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
3228 {
3229 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3230 int i, j, k, r;
3231 struct r600_bytecode_alu alu;
3232 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3233 int t1 = ctx->temp_reg;
3234
3235 for (k = 0; k <= lasti; k++) {
3236 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
3237 continue;
3238
3239 for (i = 0 ; i < 4; i++) {
3240 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3241 alu.op = ctx->inst_info->op;
3242 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3243 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
3244 }
3245 alu.dst.sel = t1;
3246 alu.dst.chan = i;
3247 alu.dst.write = (i == k);
3248 if (i == 3)
3249 alu.last = 1;
3250 r = r600_bytecode_add_alu(ctx->bc, &alu);
3251 if (r)
3252 return r;
3253 }
3254 }
3255
3256 for (i = 0 ; i <= lasti; i++) {
3257 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3258 continue;
3259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3260 alu.op = ALU_OP1_MOV;
3261 alu.src[0].sel = t1;
3262 alu.src[0].chan = i;
3263 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3264 alu.dst.write = 1;
3265 if (i == lasti)
3266 alu.last = 1;
3267 r = r600_bytecode_add_alu(ctx->bc, &alu);
3268 if (r)
3269 return r;
3270 }
3271
3272 return 0;
3273 }
3274
3275
3276 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
3277 {
3278 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3279 int i, j, k, r;
3280 struct r600_bytecode_alu alu;
3281 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3282 int t1 = ctx->temp_reg;
3283
3284 for (k = 0; k < 2; k++) {
3285 if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2))))
3286 continue;
3287
3288 for (i = 0; i < 4; i++) {
3289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3290 alu.op = ctx->inst_info->op;
3291 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3292 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));;
3293 }
3294 alu.dst.sel = t1;
3295 alu.dst.chan = i;
3296 alu.dst.write = 1;
3297 if (i == 3)
3298 alu.last = 1;
3299 r = r600_bytecode_add_alu(ctx->bc, &alu);
3300 if (r)
3301 return r;
3302 }
3303 }
3304
3305 for (i = 0; i <= lasti; i++) {
3306 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3307 continue;
3308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3309 alu.op = ALU_OP1_MOV;
3310 alu.src[0].sel = t1;
3311 alu.src[0].chan = i;
3312 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3313 alu.dst.write = 1;
3314 if (i == lasti)
3315 alu.last = 1;
3316 r = r600_bytecode_add_alu(ctx->bc, &alu);
3317 if (r)
3318 return r;
3319 }
3320
3321 return 0;
3322 }
3323
3324 /*
3325 * r600 - trunc to -PI..PI range
3326 * r700 - normalize by dividing by 2PI
3327 * see fdo bug 27901
3328 */
3329 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
3330 {
3331 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
3332 static float double_pi = 3.1415926535 * 2;
3333 static float neg_pi = -3.1415926535;
3334
3335 int r;
3336 struct r600_bytecode_alu alu;
3337
3338 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3339 alu.op = ALU_OP3_MULADD;
3340 alu.is_op3 = 1;
3341
3342 alu.dst.chan = 0;
3343 alu.dst.sel = ctx->temp_reg;
3344 alu.dst.write = 1;
3345
3346 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3347
3348 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3349 alu.src[1].chan = 0;
3350 alu.src[1].value = *(uint32_t *)&half_inv_pi;
3351 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3352 alu.src[2].chan = 0;
3353 alu.last = 1;
3354 r = r600_bytecode_add_alu(ctx->bc, &alu);
3355 if (r)
3356 return r;
3357
3358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3359 alu.op = ALU_OP1_FRACT;
3360
3361 alu.dst.chan = 0;
3362 alu.dst.sel = ctx->temp_reg;
3363 alu.dst.write = 1;
3364
3365 alu.src[0].sel = ctx->temp_reg;
3366 alu.src[0].chan = 0;
3367 alu.last = 1;
3368 r = r600_bytecode_add_alu(ctx->bc, &alu);
3369 if (r)
3370 return r;
3371
3372 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3373 alu.op = ALU_OP3_MULADD;
3374 alu.is_op3 = 1;
3375
3376 alu.dst.chan = 0;
3377 alu.dst.sel = ctx->temp_reg;
3378 alu.dst.write = 1;
3379
3380 alu.src[0].sel = ctx->temp_reg;
3381 alu.src[0].chan = 0;
3382
3383 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3384 alu.src[1].chan = 0;
3385 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3386 alu.src[2].chan = 0;
3387
3388 if (ctx->bc->chip_class == R600) {
3389 alu.src[1].value = *(uint32_t *)&double_pi;
3390 alu.src[2].value = *(uint32_t *)&neg_pi;
3391 } else {
3392 alu.src[1].sel = V_SQ_ALU_SRC_1;
3393 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3394 alu.src[2].neg = 1;
3395 }
3396
3397 alu.last = 1;
3398 r = r600_bytecode_add_alu(ctx->bc, &alu);
3399 if (r)
3400 return r;
3401 return 0;
3402 }
3403
3404 static int cayman_trig(struct r600_shader_ctx *ctx)
3405 {
3406 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3407 struct r600_bytecode_alu alu;
3408 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3409 int i, r;
3410
3411 r = tgsi_setup_trig(ctx);
3412 if (r)
3413 return r;
3414
3415
3416 for (i = 0; i < last_slot; i++) {
3417 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3418 alu.op = ctx->inst_info->op;
3419 alu.dst.chan = i;
3420
3421 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3422 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3423
3424 alu.src[0].sel = ctx->temp_reg;
3425 alu.src[0].chan = 0;
3426 if (i == last_slot - 1)
3427 alu.last = 1;
3428 r = r600_bytecode_add_alu(ctx->bc, &alu);
3429 if (r)
3430 return r;
3431 }
3432 return 0;
3433 }
3434
3435 static int tgsi_trig(struct r600_shader_ctx *ctx)
3436 {
3437 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3438 struct r600_bytecode_alu alu;
3439 int i, r;
3440 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3441
3442 r = tgsi_setup_trig(ctx);
3443 if (r)
3444 return r;
3445
3446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3447 alu.op = ctx->inst_info->op;
3448 alu.dst.chan = 0;
3449 alu.dst.sel = ctx->temp_reg;
3450 alu.dst.write = 1;
3451
3452 alu.src[0].sel = ctx->temp_reg;
3453 alu.src[0].chan = 0;
3454 alu.last = 1;
3455 r = r600_bytecode_add_alu(ctx->bc, &alu);
3456 if (r)
3457 return r;
3458
3459 /* replicate result */
3460 for (i = 0; i < lasti + 1; i++) {
3461 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3462 continue;
3463
3464 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3465 alu.op = ALU_OP1_MOV;
3466
3467 alu.src[0].sel = ctx->temp_reg;
3468 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3469 if (i == lasti)
3470 alu.last = 1;
3471 r = r600_bytecode_add_alu(ctx->bc, &alu);
3472 if (r)
3473 return r;
3474 }
3475 return 0;
3476 }
3477
3478 static int tgsi_scs(struct r600_shader_ctx *ctx)
3479 {
3480 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3481 struct r600_bytecode_alu alu;
3482 int i, r;
3483
3484 /* We'll only need the trig stuff if we are going to write to the
3485 * X or Y components of the destination vector.
3486 */
3487 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
3488 r = tgsi_setup_trig(ctx);
3489 if (r)
3490 return r;
3491 }
3492
3493 /* dst.x = COS */
3494 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3495 if (ctx->bc->chip_class == CAYMAN) {
3496 for (i = 0 ; i < 3; i++) {
3497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3498 alu.op = ALU_OP1_COS;
3499 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3500
3501 if (i == 0)
3502 alu.dst.write = 1;
3503 else
3504 alu.dst.write = 0;
3505 alu.src[0].sel = ctx->temp_reg;
3506 alu.src[0].chan = 0;
3507 if (i == 2)
3508 alu.last = 1;
3509 r = r600_bytecode_add_alu(ctx->bc, &alu);
3510 if (r)
3511 return r;
3512 }
3513 } else {
3514 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3515 alu.op = ALU_OP1_COS;
3516 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3517
3518 alu.src[0].sel = ctx->temp_reg;
3519 alu.src[0].chan = 0;
3520 alu.last = 1;
3521 r = r600_bytecode_add_alu(ctx->bc, &alu);
3522 if (r)
3523 return r;
3524 }
3525 }
3526
3527 /* dst.y = SIN */
3528 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3529 if (ctx->bc->chip_class == CAYMAN) {
3530 for (i = 0 ; i < 3; i++) {
3531 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3532 alu.op = ALU_OP1_SIN;
3533 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3534 if (i == 1)
3535 alu.dst.write = 1;
3536 else
3537 alu.dst.write = 0;
3538 alu.src[0].sel = ctx->temp_reg;
3539 alu.src[0].chan = 0;
3540 if (i == 2)
3541 alu.last = 1;
3542 r = r600_bytecode_add_alu(ctx->bc, &alu);
3543 if (r)
3544 return r;
3545 }
3546 } else {
3547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3548 alu.op = ALU_OP1_SIN;
3549 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3550
3551 alu.src[0].sel = ctx->temp_reg;
3552 alu.src[0].chan = 0;
3553 alu.last = 1;
3554 r = r600_bytecode_add_alu(ctx->bc, &alu);
3555 if (r)
3556 return r;
3557 }
3558 }
3559
3560 /* dst.z = 0.0; */
3561 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3562 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3563
3564 alu.op = ALU_OP1_MOV;
3565
3566 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3567
3568 alu.src[0].sel = V_SQ_ALU_SRC_0;
3569 alu.src[0].chan = 0;
3570
3571 alu.last = 1;
3572
3573 r = r600_bytecode_add_alu(ctx->bc, &alu);
3574 if (r)
3575 return r;
3576 }
3577
3578 /* dst.w = 1.0; */
3579 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3580 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3581
3582 alu.op = ALU_OP1_MOV;
3583
3584 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3585
3586 alu.src[0].sel = V_SQ_ALU_SRC_1;
3587 alu.src[0].chan = 0;
3588
3589 alu.last = 1;
3590
3591 r = r600_bytecode_add_alu(ctx->bc, &alu);
3592 if (r)
3593 return r;
3594 }
3595
3596 return 0;
3597 }
3598
3599 static int tgsi_kill(struct r600_shader_ctx *ctx)
3600 {
3601 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3602 struct r600_bytecode_alu alu;
3603 int i, r;
3604
3605 for (i = 0; i < 4; i++) {
3606 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3607 alu.op = ctx->inst_info->op;
3608
3609 alu.dst.chan = i;
3610
3611 alu.src[0].sel = V_SQ_ALU_SRC_0;
3612
3613 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
3614 alu.src[1].sel = V_SQ_ALU_SRC_1;
3615 alu.src[1].neg = 1;
3616 } else {
3617 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3618 }
3619 if (i == 3) {
3620 alu.last = 1;
3621 }
3622 r = r600_bytecode_add_alu(ctx->bc, &alu);
3623 if (r)
3624 return r;
3625 }
3626
3627 /* kill must be last in ALU */
3628 ctx->bc->force_add_cf = 1;
3629 ctx->shader->uses_kill = TRUE;
3630 return 0;
3631 }
3632
3633 static int tgsi_lit(struct r600_shader_ctx *ctx)
3634 {
3635 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3636 struct r600_bytecode_alu alu;
3637 int r;
3638
3639 /* tmp.x = max(src.y, 0.0) */
3640 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3641 alu.op = ALU_OP2_MAX;
3642 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3643 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3644 alu.src[1].chan = 1;
3645
3646 alu.dst.sel = ctx->temp_reg;
3647 alu.dst.chan = 0;
3648 alu.dst.write = 1;
3649
3650 alu.last = 1;
3651 r = r600_bytecode_add_alu(ctx->bc, &alu);
3652 if (r)
3653 return r;
3654
3655 if (inst->Dst[0].Register.WriteMask & (1 << 2))
3656 {
3657 int chan;
3658 int sel;
3659 int i;
3660
3661 if (ctx->bc->chip_class == CAYMAN) {
3662 for (i = 0; i < 3; i++) {
3663 /* tmp.z = log(tmp.x) */
3664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3665 alu.op = ALU_OP1_LOG_CLAMPED;
3666 alu.src[0].sel = ctx->temp_reg;
3667 alu.src[0].chan = 0;
3668 alu.dst.sel = ctx->temp_reg;
3669 alu.dst.chan = i;
3670 if (i == 2) {
3671 alu.dst.write = 1;
3672 alu.last = 1;
3673 } else
3674 alu.dst.write = 0;
3675
3676 r = r600_bytecode_add_alu(ctx->bc, &alu);
3677 if (r)
3678 return r;
3679 }
3680 } else {
3681 /* tmp.z = log(tmp.x) */
3682 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3683 alu.op = ALU_OP1_LOG_CLAMPED;
3684 alu.src[0].sel = ctx->temp_reg;
3685 alu.src[0].chan = 0;
3686 alu.dst.sel = ctx->temp_reg;
3687 alu.dst.chan = 2;
3688 alu.dst.write = 1;
3689 alu.last = 1;
3690 r = r600_bytecode_add_alu(ctx->bc, &alu);
3691 if (r)
3692 return r;
3693 }
3694
3695 chan = alu.dst.chan;
3696 sel = alu.dst.sel;
3697
3698 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
3699 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3700 alu.op = ALU_OP3_MUL_LIT;
3701 alu.src[0].sel = sel;
3702 alu.src[0].chan = chan;
3703 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
3704 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
3705 alu.dst.sel = ctx->temp_reg;
3706 alu.dst.chan = 0;
3707 alu.dst.write = 1;
3708 alu.is_op3 = 1;
3709 alu.last = 1;
3710 r = r600_bytecode_add_alu(ctx->bc, &alu);
3711 if (r)
3712 return r;
3713
3714 if (ctx->bc->chip_class == CAYMAN) {
3715 for (i = 0; i < 3; i++) {
3716 /* dst.z = exp(tmp.x) */
3717 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3718 alu.op = ALU_OP1_EXP_IEEE;
3719 alu.src[0].sel = ctx->temp_reg;
3720 alu.src[0].chan = 0;
3721 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3722 if (i == 2) {
3723 alu.dst.write = 1;
3724 alu.last = 1;
3725 } else
3726 alu.dst.write = 0;
3727 r = r600_bytecode_add_alu(ctx->bc, &alu);
3728 if (r)
3729 return r;
3730 }
3731 } else {
3732 /* dst.z = exp(tmp.x) */
3733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3734 alu.op = ALU_OP1_EXP_IEEE;
3735 alu.src[0].sel = ctx->temp_reg;
3736 alu.src[0].chan = 0;
3737 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3738 alu.last = 1;
3739 r = r600_bytecode_add_alu(ctx->bc, &alu);
3740 if (r)
3741 return r;
3742 }
3743 }
3744
3745 /* dst.x, <- 1.0 */
3746 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3747 alu.op = ALU_OP1_MOV;
3748 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
3749 alu.src[0].chan = 0;
3750 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3751 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
3752 r = r600_bytecode_add_alu(ctx->bc, &alu);
3753 if (r)
3754 return r;
3755
3756 /* dst.y = max(src.x, 0.0) */
3757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3758 alu.op = ALU_OP2_MAX;
3759 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3760 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3761 alu.src[1].chan = 0;
3762 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3763 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
3764 r = r600_bytecode_add_alu(ctx->bc, &alu);
3765 if (r)
3766 return r;
3767
3768 /* dst.w, <- 1.0 */
3769 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3770 alu.op = ALU_OP1_MOV;
3771 alu.src[0].sel = V_SQ_ALU_SRC_1;
3772 alu.src[0].chan = 0;
3773 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3774 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
3775 alu.last = 1;
3776 r = r600_bytecode_add_alu(ctx->bc, &alu);
3777 if (r)
3778 return r;
3779
3780 return 0;
3781 }
3782
3783 static int tgsi_rsq(struct r600_shader_ctx *ctx)
3784 {
3785 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3786 struct r600_bytecode_alu alu;
3787 int i, r;
3788
3789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3790
3791 /* XXX:
3792 * For state trackers other than OpenGL, we'll want to use
3793 * _RECIPSQRT_IEEE instead.
3794 */
3795 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
3796
3797 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3798 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3799 r600_bytecode_src_set_abs(&alu.src[i]);
3800 }
3801 alu.dst.sel = ctx->temp_reg;
3802 alu.dst.write = 1;
3803 alu.last = 1;
3804 r = r600_bytecode_add_alu(ctx->bc, &alu);
3805 if (r)
3806 return r;
3807 /* replicate result */
3808 return tgsi_helper_tempx_replicate(ctx);
3809 }
3810
3811 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
3812 {
3813 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3814 struct r600_bytecode_alu alu;
3815 int i, r;
3816
3817 for (i = 0; i < 4; i++) {
3818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3819 alu.src[0].sel = ctx->temp_reg;
3820 alu.op = ALU_OP1_MOV;
3821 alu.dst.chan = i;
3822 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3823 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3824 if (i == 3)
3825 alu.last = 1;
3826 r = r600_bytecode_add_alu(ctx->bc, &alu);
3827 if (r)
3828 return r;
3829 }
3830 return 0;
3831 }
3832
3833 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
3834 {
3835 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3836 struct r600_bytecode_alu alu;
3837 int i, r;
3838
3839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3840 alu.op = ctx->inst_info->op;
3841 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3842 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3843 }
3844 alu.dst.sel = ctx->temp_reg;
3845 alu.dst.write = 1;
3846 alu.last = 1;
3847 r = r600_bytecode_add_alu(ctx->bc, &alu);
3848 if (r)
3849 return r;
3850 /* replicate result */
3851 return tgsi_helper_tempx_replicate(ctx);
3852 }
3853
3854 static int cayman_pow(struct r600_shader_ctx *ctx)
3855 {
3856 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3857 int i, r;
3858 struct r600_bytecode_alu alu;
3859 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3860
3861 for (i = 0; i < 3; i++) {
3862 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3863 alu.op = ALU_OP1_LOG_IEEE;
3864 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3865 alu.dst.sel = ctx->temp_reg;
3866 alu.dst.chan = i;
3867 alu.dst.write = 1;
3868 if (i == 2)
3869 alu.last = 1;
3870 r = r600_bytecode_add_alu(ctx->bc, &alu);
3871 if (r)
3872 return r;
3873 }
3874
3875 /* b * LOG2(a) */
3876 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3877 alu.op = ALU_OP2_MUL;
3878 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3879 alu.src[1].sel = ctx->temp_reg;
3880 alu.dst.sel = ctx->temp_reg;
3881 alu.dst.write = 1;
3882 alu.last = 1;
3883 r = r600_bytecode_add_alu(ctx->bc, &alu);
3884 if (r)
3885 return r;
3886
3887 for (i = 0; i < last_slot; i++) {
3888 /* POW(a,b) = EXP2(b * LOG2(a))*/
3889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3890 alu.op = ALU_OP1_EXP_IEEE;
3891 alu.src[0].sel = ctx->temp_reg;
3892
3893 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3894 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3895 if (i == last_slot - 1)
3896 alu.last = 1;
3897 r = r600_bytecode_add_alu(ctx->bc, &alu);
3898 if (r)
3899 return r;
3900 }
3901 return 0;
3902 }
3903
3904 static int tgsi_pow(struct r600_shader_ctx *ctx)
3905 {
3906 struct r600_bytecode_alu alu;
3907 int r;
3908
3909 /* LOG2(a) */
3910 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3911 alu.op = ALU_OP1_LOG_IEEE;
3912 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3913 alu.dst.sel = ctx->temp_reg;
3914 alu.dst.write = 1;
3915 alu.last = 1;
3916 r = r600_bytecode_add_alu(ctx->bc, &alu);
3917 if (r)
3918 return r;
3919 /* b * LOG2(a) */
3920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3921 alu.op = ALU_OP2_MUL;
3922 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3923 alu.src[1].sel = ctx->temp_reg;
3924 alu.dst.sel = ctx->temp_reg;
3925 alu.dst.write = 1;
3926 alu.last = 1;
3927 r = r600_bytecode_add_alu(ctx->bc, &alu);
3928 if (r)
3929 return r;
3930 /* POW(a,b) = EXP2(b * LOG2(a))*/
3931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3932 alu.op = ALU_OP1_EXP_IEEE;
3933 alu.src[0].sel = ctx->temp_reg;
3934 alu.dst.sel = ctx->temp_reg;
3935 alu.dst.write = 1;
3936 alu.last = 1;
3937 r = r600_bytecode_add_alu(ctx->bc, &alu);
3938 if (r)
3939 return r;
3940 return tgsi_helper_tempx_replicate(ctx);
3941 }
3942
3943 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
3944 {
3945 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3946 struct r600_bytecode_alu alu;
3947 int i, r, j;
3948 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3949 int tmp0 = ctx->temp_reg;
3950 int tmp1 = r600_get_temp(ctx);
3951 int tmp2 = r600_get_temp(ctx);
3952 int tmp3 = r600_get_temp(ctx);
3953 /* Unsigned path:
3954 *
3955 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
3956 *
3957 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
3958 * 2. tmp0.z = lo (tmp0.x * src2)
3959 * 3. tmp0.w = -tmp0.z
3960 * 4. tmp0.y = hi (tmp0.x * src2)
3961 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
3962 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
3963 * 7. tmp1.x = tmp0.x - tmp0.w
3964 * 8. tmp1.y = tmp0.x + tmp0.w
3965 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
3966 * 10. tmp0.z = hi(tmp0.x * src1) = q
3967 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
3968 *
3969 * 12. tmp0.w = src1 - tmp0.y = r
3970 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
3971 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
3972 *
3973 * if DIV
3974 *
3975 * 15. tmp1.z = tmp0.z + 1 = q + 1
3976 * 16. tmp1.w = tmp0.z - 1 = q - 1
3977 *
3978 * else MOD
3979 *
3980 * 15. tmp1.z = tmp0.w - src2 = r - src2
3981 * 16. tmp1.w = tmp0.w + src2 = r + src2
3982 *
3983 * endif
3984 *
3985 * 17. tmp1.x = tmp1.x & tmp1.y
3986 *
3987 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
3988 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
3989 *
3990 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
3991 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
3992 *
3993 * Signed path:
3994 *
3995 * Same as unsigned, using abs values of the operands,
3996 * and fixing the sign of the result in the end.
3997 */
3998
3999 for (i = 0; i < 4; i++) {
4000 if (!(write_mask & (1<<i)))
4001 continue;
4002
4003 if (signed_op) {
4004
4005 /* tmp2.x = -src0 */
4006 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4007 alu.op = ALU_OP2_SUB_INT;
4008
4009 alu.dst.sel = tmp2;
4010 alu.dst.chan = 0;
4011 alu.dst.write = 1;
4012
4013 alu.src[0].sel = V_SQ_ALU_SRC_0;
4014
4015 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4016
4017 alu.last = 1;
4018 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4019 return r;
4020
4021 /* tmp2.y = -src1 */
4022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4023 alu.op = ALU_OP2_SUB_INT;
4024
4025 alu.dst.sel = tmp2;
4026 alu.dst.chan = 1;
4027 alu.dst.write = 1;
4028
4029 alu.src[0].sel = V_SQ_ALU_SRC_0;
4030
4031 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4032
4033 alu.last = 1;
4034 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4035 return r;
4036
4037 /* tmp2.z sign bit is set if src0 and src2 signs are different */
4038 /* it will be a sign of the quotient */
4039 if (!mod) {
4040
4041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4042 alu.op = ALU_OP2_XOR_INT;
4043
4044 alu.dst.sel = tmp2;
4045 alu.dst.chan = 2;
4046 alu.dst.write = 1;
4047
4048 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4049 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4050
4051 alu.last = 1;
4052 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4053 return r;
4054 }
4055
4056 /* tmp2.x = |src0| */
4057 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4058 alu.op = ALU_OP3_CNDGE_INT;
4059 alu.is_op3 = 1;
4060
4061 alu.dst.sel = tmp2;
4062 alu.dst.chan = 0;
4063 alu.dst.write = 1;
4064
4065 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4066 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4067 alu.src[2].sel = tmp2;
4068 alu.src[2].chan = 0;
4069
4070 alu.last = 1;
4071 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4072 return r;
4073
4074 /* tmp2.y = |src1| */
4075 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4076 alu.op = ALU_OP3_CNDGE_INT;
4077 alu.is_op3 = 1;
4078
4079 alu.dst.sel = tmp2;
4080 alu.dst.chan = 1;
4081 alu.dst.write = 1;
4082
4083 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4084 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4085 alu.src[2].sel = tmp2;
4086 alu.src[2].chan = 1;
4087
4088 alu.last = 1;
4089 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4090 return r;
4091
4092 }
4093
4094 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
4095 if (ctx->bc->chip_class == CAYMAN) {
4096 /* tmp3.x = u2f(src2) */
4097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4098 alu.op = ALU_OP1_UINT_TO_FLT;
4099
4100 alu.dst.sel = tmp3;
4101 alu.dst.chan = 0;
4102 alu.dst.write = 1;
4103
4104 if (signed_op) {
4105 alu.src[0].sel = tmp2;
4106 alu.src[0].chan = 1;
4107 } else {
4108 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4109 }
4110
4111 alu.last = 1;
4112 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4113 return r;
4114
4115 /* tmp0.x = recip(tmp3.x) */
4116 for (j = 0 ; j < 3; j++) {
4117 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4118 alu.op = ALU_OP1_RECIP_IEEE;
4119
4120 alu.dst.sel = tmp0;
4121 alu.dst.chan = j;
4122 alu.dst.write = (j == 0);
4123
4124 alu.src[0].sel = tmp3;
4125 alu.src[0].chan = 0;
4126
4127 if (j == 2)
4128 alu.last = 1;
4129 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4130 return r;
4131 }
4132
4133 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4134 alu.op = ALU_OP2_MUL;
4135
4136 alu.src[0].sel = tmp0;
4137 alu.src[0].chan = 0;
4138
4139 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4140 alu.src[1].value = 0x4f800000;
4141
4142 alu.dst.sel = tmp3;
4143 alu.dst.write = 1;
4144 alu.last = 1;
4145 r = r600_bytecode_add_alu(ctx->bc, &alu);
4146 if (r)
4147 return r;
4148
4149 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4150 alu.op = ALU_OP1_FLT_TO_UINT;
4151
4152 alu.dst.sel = tmp0;
4153 alu.dst.chan = 0;
4154 alu.dst.write = 1;
4155
4156 alu.src[0].sel = tmp3;
4157 alu.src[0].chan = 0;
4158
4159 alu.last = 1;
4160 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4161 return r;
4162
4163 } else {
4164 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4165 alu.op = ALU_OP1_RECIP_UINT;
4166
4167 alu.dst.sel = tmp0;
4168 alu.dst.chan = 0;
4169 alu.dst.write = 1;
4170
4171 if (signed_op) {
4172 alu.src[0].sel = tmp2;
4173 alu.src[0].chan = 1;
4174 } else {
4175 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4176 }
4177
4178 alu.last = 1;
4179 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4180 return r;
4181 }
4182
4183 /* 2. tmp0.z = lo (tmp0.x * src2) */
4184 if (ctx->bc->chip_class == CAYMAN) {
4185 for (j = 0 ; j < 4; j++) {
4186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4187 alu.op = ALU_OP2_MULLO_UINT;
4188
4189 alu.dst.sel = tmp0;
4190 alu.dst.chan = j;
4191 alu.dst.write = (j == 2);
4192
4193 alu.src[0].sel = tmp0;
4194 alu.src[0].chan = 0;
4195 if (signed_op) {
4196 alu.src[1].sel = tmp2;
4197 alu.src[1].chan = 1;
4198 } else {
4199 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4200 }
4201
4202 alu.last = (j == 3);
4203 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4204 return r;
4205 }
4206 } else {
4207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4208 alu.op = ALU_OP2_MULLO_UINT;
4209
4210 alu.dst.sel = tmp0;
4211 alu.dst.chan = 2;
4212 alu.dst.write = 1;
4213
4214 alu.src[0].sel = tmp0;
4215 alu.src[0].chan = 0;
4216 if (signed_op) {
4217 alu.src[1].sel = tmp2;
4218 alu.src[1].chan = 1;
4219 } else {
4220 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4221 }
4222
4223 alu.last = 1;
4224 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4225 return r;
4226 }
4227
4228 /* 3. tmp0.w = -tmp0.z */
4229 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4230 alu.op = ALU_OP2_SUB_INT;
4231
4232 alu.dst.sel = tmp0;
4233 alu.dst.chan = 3;
4234 alu.dst.write = 1;
4235
4236 alu.src[0].sel = V_SQ_ALU_SRC_0;
4237 alu.src[1].sel = tmp0;
4238 alu.src[1].chan = 2;
4239
4240 alu.last = 1;
4241 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4242 return r;
4243
4244 /* 4. tmp0.y = hi (tmp0.x * src2) */
4245 if (ctx->bc->chip_class == CAYMAN) {
4246 for (j = 0 ; j < 4; j++) {
4247 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4248 alu.op = ALU_OP2_MULHI_UINT;
4249
4250 alu.dst.sel = tmp0;
4251 alu.dst.chan = j;
4252 alu.dst.write = (j == 1);
4253
4254 alu.src[0].sel = tmp0;
4255 alu.src[0].chan = 0;
4256
4257 if (signed_op) {
4258 alu.src[1].sel = tmp2;
4259 alu.src[1].chan = 1;
4260 } else {
4261 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4262 }
4263 alu.last = (j == 3);
4264 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4265 return r;
4266 }
4267 } else {
4268 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4269 alu.op = ALU_OP2_MULHI_UINT;
4270
4271 alu.dst.sel = tmp0;
4272 alu.dst.chan = 1;
4273 alu.dst.write = 1;
4274
4275 alu.src[0].sel = tmp0;
4276 alu.src[0].chan = 0;
4277
4278 if (signed_op) {
4279 alu.src[1].sel = tmp2;
4280 alu.src[1].chan = 1;
4281 } else {
4282 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4283 }
4284
4285 alu.last = 1;
4286 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4287 return r;
4288 }
4289
4290 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
4291 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4292 alu.op = ALU_OP3_CNDE_INT;
4293 alu.is_op3 = 1;
4294
4295 alu.dst.sel = tmp0;
4296 alu.dst.chan = 2;
4297 alu.dst.write = 1;
4298
4299 alu.src[0].sel = tmp0;
4300 alu.src[0].chan = 1;
4301 alu.src[1].sel = tmp0;
4302 alu.src[1].chan = 3;
4303 alu.src[2].sel = tmp0;
4304 alu.src[2].chan = 2;
4305
4306 alu.last = 1;
4307 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4308 return r;
4309
4310 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
4311 if (ctx->bc->chip_class == CAYMAN) {
4312 for (j = 0 ; j < 4; j++) {
4313 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4314 alu.op = ALU_OP2_MULHI_UINT;
4315
4316 alu.dst.sel = tmp0;
4317 alu.dst.chan = j;
4318 alu.dst.write = (j == 3);
4319
4320 alu.src[0].sel = tmp0;
4321 alu.src[0].chan = 2;
4322
4323 alu.src[1].sel = tmp0;
4324 alu.src[1].chan = 0;
4325
4326 alu.last = (j == 3);
4327 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4328 return r;
4329 }
4330 } else {
4331 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4332 alu.op = ALU_OP2_MULHI_UINT;
4333
4334 alu.dst.sel = tmp0;
4335 alu.dst.chan = 3;
4336 alu.dst.write = 1;
4337
4338 alu.src[0].sel = tmp0;
4339 alu.src[0].chan = 2;
4340
4341 alu.src[1].sel = tmp0;
4342 alu.src[1].chan = 0;
4343
4344 alu.last = 1;
4345 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4346 return r;
4347 }
4348
4349 /* 7. tmp1.x = tmp0.x - tmp0.w */
4350 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4351 alu.op = ALU_OP2_SUB_INT;
4352
4353 alu.dst.sel = tmp1;
4354 alu.dst.chan = 0;
4355 alu.dst.write = 1;
4356
4357 alu.src[0].sel = tmp0;
4358 alu.src[0].chan = 0;
4359 alu.src[1].sel = tmp0;
4360 alu.src[1].chan = 3;
4361
4362 alu.last = 1;
4363 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4364 return r;
4365
4366 /* 8. tmp1.y = tmp0.x + tmp0.w */
4367 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4368 alu.op = ALU_OP2_ADD_INT;
4369
4370 alu.dst.sel = tmp1;
4371 alu.dst.chan = 1;
4372 alu.dst.write = 1;
4373
4374 alu.src[0].sel = tmp0;
4375 alu.src[0].chan = 0;
4376 alu.src[1].sel = tmp0;
4377 alu.src[1].chan = 3;
4378
4379 alu.last = 1;
4380 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4381 return r;
4382
4383 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
4384 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4385 alu.op = ALU_OP3_CNDE_INT;
4386 alu.is_op3 = 1;
4387
4388 alu.dst.sel = tmp0;
4389 alu.dst.chan = 0;
4390 alu.dst.write = 1;
4391
4392 alu.src[0].sel = tmp0;
4393 alu.src[0].chan = 1;
4394 alu.src[1].sel = tmp1;
4395 alu.src[1].chan = 1;
4396 alu.src[2].sel = tmp1;
4397 alu.src[2].chan = 0;
4398
4399 alu.last = 1;
4400 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4401 return r;
4402
4403 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
4404 if (ctx->bc->chip_class == CAYMAN) {
4405 for (j = 0 ; j < 4; j++) {
4406 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4407 alu.op = ALU_OP2_MULHI_UINT;
4408
4409 alu.dst.sel = tmp0;
4410 alu.dst.chan = j;
4411 alu.dst.write = (j == 2);
4412
4413 alu.src[0].sel = tmp0;
4414 alu.src[0].chan = 0;
4415
4416 if (signed_op) {
4417 alu.src[1].sel = tmp2;
4418 alu.src[1].chan = 0;
4419 } else {
4420 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4421 }
4422
4423 alu.last = (j == 3);
4424 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4425 return r;
4426 }
4427 } else {
4428 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4429 alu.op = ALU_OP2_MULHI_UINT;
4430
4431 alu.dst.sel = tmp0;
4432 alu.dst.chan = 2;
4433 alu.dst.write = 1;
4434
4435 alu.src[0].sel = tmp0;
4436 alu.src[0].chan = 0;
4437
4438 if (signed_op) {
4439 alu.src[1].sel = tmp2;
4440 alu.src[1].chan = 0;
4441 } else {
4442 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4443 }
4444
4445 alu.last = 1;
4446 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4447 return r;
4448 }
4449
4450 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
4451 if (ctx->bc->chip_class == CAYMAN) {
4452 for (j = 0 ; j < 4; j++) {
4453 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4454 alu.op = ALU_OP2_MULLO_UINT;
4455
4456 alu.dst.sel = tmp0;
4457 alu.dst.chan = j;
4458 alu.dst.write = (j == 1);
4459
4460 if (signed_op) {
4461 alu.src[0].sel = tmp2;
4462 alu.src[0].chan = 1;
4463 } else {
4464 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4465 }
4466
4467 alu.src[1].sel = tmp0;
4468 alu.src[1].chan = 2;
4469
4470 alu.last = (j == 3);
4471 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4472 return r;
4473 }
4474 } else {
4475 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4476 alu.op = ALU_OP2_MULLO_UINT;
4477
4478 alu.dst.sel = tmp0;
4479 alu.dst.chan = 1;
4480 alu.dst.write = 1;
4481
4482 if (signed_op) {
4483 alu.src[0].sel = tmp2;
4484 alu.src[0].chan = 1;
4485 } else {
4486 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4487 }
4488
4489 alu.src[1].sel = tmp0;
4490 alu.src[1].chan = 2;
4491
4492 alu.last = 1;
4493 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4494 return r;
4495 }
4496
4497 /* 12. tmp0.w = src1 - tmp0.y = r */
4498 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4499 alu.op = ALU_OP2_SUB_INT;
4500
4501 alu.dst.sel = tmp0;
4502 alu.dst.chan = 3;
4503 alu.dst.write = 1;
4504
4505 if (signed_op) {
4506 alu.src[0].sel = tmp2;
4507 alu.src[0].chan = 0;
4508 } else {
4509 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4510 }
4511
4512 alu.src[1].sel = tmp0;
4513 alu.src[1].chan = 1;
4514
4515 alu.last = 1;
4516 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4517 return r;
4518
4519 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
4520 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4521 alu.op = ALU_OP2_SETGE_UINT;
4522
4523 alu.dst.sel = tmp1;
4524 alu.dst.chan = 0;
4525 alu.dst.write = 1;
4526
4527 alu.src[0].sel = tmp0;
4528 alu.src[0].chan = 3;
4529 if (signed_op) {
4530 alu.src[1].sel = tmp2;
4531 alu.src[1].chan = 1;
4532 } else {
4533 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4534 }
4535
4536 alu.last = 1;
4537 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4538 return r;
4539
4540 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
4541 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4542 alu.op = ALU_OP2_SETGE_UINT;
4543
4544 alu.dst.sel = tmp1;
4545 alu.dst.chan = 1;
4546 alu.dst.write = 1;
4547
4548 if (signed_op) {
4549 alu.src[0].sel = tmp2;
4550 alu.src[0].chan = 0;
4551 } else {
4552 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4553 }
4554
4555 alu.src[1].sel = tmp0;
4556 alu.src[1].chan = 1;
4557
4558 alu.last = 1;
4559 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4560 return r;
4561
4562 if (mod) { /* UMOD */
4563
4564 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
4565 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4566 alu.op = ALU_OP2_SUB_INT;
4567
4568 alu.dst.sel = tmp1;
4569 alu.dst.chan = 2;
4570 alu.dst.write = 1;
4571
4572 alu.src[0].sel = tmp0;
4573 alu.src[0].chan = 3;
4574
4575 if (signed_op) {
4576 alu.src[1].sel = tmp2;
4577 alu.src[1].chan = 1;
4578 } else {
4579 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4580 }
4581
4582 alu.last = 1;
4583 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4584 return r;
4585
4586 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
4587 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4588 alu.op = ALU_OP2_ADD_INT;
4589
4590 alu.dst.sel = tmp1;
4591 alu.dst.chan = 3;
4592 alu.dst.write = 1;
4593
4594 alu.src[0].sel = tmp0;
4595 alu.src[0].chan = 3;
4596 if (signed_op) {
4597 alu.src[1].sel = tmp2;
4598 alu.src[1].chan = 1;
4599 } else {
4600 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4601 }
4602
4603 alu.last = 1;
4604 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4605 return r;
4606
4607 } else { /* UDIV */
4608
4609 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
4610 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4611 alu.op = ALU_OP2_ADD_INT;
4612
4613 alu.dst.sel = tmp1;
4614 alu.dst.chan = 2;
4615 alu.dst.write = 1;
4616
4617 alu.src[0].sel = tmp0;
4618 alu.src[0].chan = 2;
4619 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4620
4621 alu.last = 1;
4622 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4623 return r;
4624
4625 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
4626 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4627 alu.op = ALU_OP2_ADD_INT;
4628
4629 alu.dst.sel = tmp1;
4630 alu.dst.chan = 3;
4631 alu.dst.write = 1;
4632
4633 alu.src[0].sel = tmp0;
4634 alu.src[0].chan = 2;
4635 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
4636
4637 alu.last = 1;
4638 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4639 return r;
4640
4641 }
4642
4643 /* 17. tmp1.x = tmp1.x & tmp1.y */
4644 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4645 alu.op = ALU_OP2_AND_INT;
4646
4647 alu.dst.sel = tmp1;
4648 alu.dst.chan = 0;
4649 alu.dst.write = 1;
4650
4651 alu.src[0].sel = tmp1;
4652 alu.src[0].chan = 0;
4653 alu.src[1].sel = tmp1;
4654 alu.src[1].chan = 1;
4655
4656 alu.last = 1;
4657 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4658 return r;
4659
4660 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
4661 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
4662 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4663 alu.op = ALU_OP3_CNDE_INT;
4664 alu.is_op3 = 1;
4665
4666 alu.dst.sel = tmp0;
4667 alu.dst.chan = 2;
4668 alu.dst.write = 1;
4669
4670 alu.src[0].sel = tmp1;
4671 alu.src[0].chan = 0;
4672 alu.src[1].sel = tmp0;
4673 alu.src[1].chan = mod ? 3 : 2;
4674 alu.src[2].sel = tmp1;
4675 alu.src[2].chan = 2;
4676
4677 alu.last = 1;
4678 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4679 return r;
4680
4681 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
4682 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4683 alu.op = ALU_OP3_CNDE_INT;
4684 alu.is_op3 = 1;
4685
4686 if (signed_op) {
4687 alu.dst.sel = tmp0;
4688 alu.dst.chan = 2;
4689 alu.dst.write = 1;
4690 } else {
4691 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4692 }
4693
4694 alu.src[0].sel = tmp1;
4695 alu.src[0].chan = 1;
4696 alu.src[1].sel = tmp1;
4697 alu.src[1].chan = 3;
4698 alu.src[2].sel = tmp0;
4699 alu.src[2].chan = 2;
4700
4701 alu.last = 1;
4702 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4703 return r;
4704
4705 if (signed_op) {
4706
4707 /* fix the sign of the result */
4708
4709 if (mod) {
4710
4711 /* tmp0.x = -tmp0.z */
4712 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4713 alu.op = ALU_OP2_SUB_INT;
4714
4715 alu.dst.sel = tmp0;
4716 alu.dst.chan = 0;
4717 alu.dst.write = 1;
4718
4719 alu.src[0].sel = V_SQ_ALU_SRC_0;
4720 alu.src[1].sel = tmp0;
4721 alu.src[1].chan = 2;
4722
4723 alu.last = 1;
4724 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4725 return r;
4726
4727 /* sign of the remainder is the same as the sign of src0 */
4728 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
4729 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4730 alu.op = ALU_OP3_CNDGE_INT;
4731 alu.is_op3 = 1;
4732
4733 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4734
4735 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4736 alu.src[1].sel = tmp0;
4737 alu.src[1].chan = 2;
4738 alu.src[2].sel = tmp0;
4739 alu.src[2].chan = 0;
4740
4741 alu.last = 1;
4742 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4743 return r;
4744
4745 } else {
4746
4747 /* tmp0.x = -tmp0.z */
4748 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4749 alu.op = ALU_OP2_SUB_INT;
4750
4751 alu.dst.sel = tmp0;
4752 alu.dst.chan = 0;
4753 alu.dst.write = 1;
4754
4755 alu.src[0].sel = V_SQ_ALU_SRC_0;
4756 alu.src[1].sel = tmp0;
4757 alu.src[1].chan = 2;
4758
4759 alu.last = 1;
4760 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4761 return r;
4762
4763 /* fix the quotient sign (same as the sign of src0*src1) */
4764 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
4765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4766 alu.op = ALU_OP3_CNDGE_INT;
4767 alu.is_op3 = 1;
4768
4769 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4770
4771 alu.src[0].sel = tmp2;
4772 alu.src[0].chan = 2;
4773 alu.src[1].sel = tmp0;
4774 alu.src[1].chan = 2;
4775 alu.src[2].sel = tmp0;
4776 alu.src[2].chan = 0;
4777
4778 alu.last = 1;
4779 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4780 return r;
4781 }
4782 }
4783 }
4784 return 0;
4785 }
4786
4787 static int tgsi_udiv(struct r600_shader_ctx *ctx)
4788 {
4789 return tgsi_divmod(ctx, 0, 0);
4790 }
4791
4792 static int tgsi_umod(struct r600_shader_ctx *ctx)
4793 {
4794 return tgsi_divmod(ctx, 1, 0);
4795 }
4796
4797 static int tgsi_idiv(struct r600_shader_ctx *ctx)
4798 {
4799 return tgsi_divmod(ctx, 0, 1);
4800 }
4801
4802 static int tgsi_imod(struct r600_shader_ctx *ctx)
4803 {
4804 return tgsi_divmod(ctx, 1, 1);
4805 }
4806
4807
4808 static int tgsi_f2i(struct r600_shader_ctx *ctx)
4809 {
4810 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4811 struct r600_bytecode_alu alu;
4812 int i, r;
4813 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4814 int last_inst = tgsi_last_instruction(write_mask);
4815
4816 for (i = 0; i < 4; i++) {
4817 if (!(write_mask & (1<<i)))
4818 continue;
4819
4820 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4821 alu.op = ALU_OP1_TRUNC;
4822
4823 alu.dst.sel = ctx->temp_reg;
4824 alu.dst.chan = i;
4825 alu.dst.write = 1;
4826
4827 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4828 if (i == last_inst)
4829 alu.last = 1;
4830 r = r600_bytecode_add_alu(ctx->bc, &alu);
4831 if (r)
4832 return r;
4833 }
4834
4835 for (i = 0; i < 4; i++) {
4836 if (!(write_mask & (1<<i)))
4837 continue;
4838
4839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4840 alu.op = ctx->inst_info->op;
4841
4842 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4843
4844 alu.src[0].sel = ctx->temp_reg;
4845 alu.src[0].chan = i;
4846
4847 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
4848 alu.last = 1;
4849 r = r600_bytecode_add_alu(ctx->bc, &alu);
4850 if (r)
4851 return r;
4852 }
4853
4854 return 0;
4855 }
4856
4857 static int tgsi_iabs(struct r600_shader_ctx *ctx)
4858 {
4859 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4860 struct r600_bytecode_alu alu;
4861 int i, r;
4862 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4863 int last_inst = tgsi_last_instruction(write_mask);
4864
4865 /* tmp = -src */
4866 for (i = 0; i < 4; i++) {
4867 if (!(write_mask & (1<<i)))
4868 continue;
4869
4870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4871 alu.op = ALU_OP2_SUB_INT;
4872
4873 alu.dst.sel = ctx->temp_reg;
4874 alu.dst.chan = i;
4875 alu.dst.write = 1;
4876
4877 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4878 alu.src[0].sel = V_SQ_ALU_SRC_0;
4879
4880 if (i == last_inst)
4881 alu.last = 1;
4882 r = r600_bytecode_add_alu(ctx->bc, &alu);
4883 if (r)
4884 return r;
4885 }
4886
4887 /* dst = (src >= 0 ? src : tmp) */
4888 for (i = 0; i < 4; i++) {
4889 if (!(write_mask & (1<<i)))
4890 continue;
4891
4892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4893 alu.op = ALU_OP3_CNDGE_INT;
4894 alu.is_op3 = 1;
4895 alu.dst.write = 1;
4896
4897 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4898
4899 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4900 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4901 alu.src[2].sel = ctx->temp_reg;
4902 alu.src[2].chan = i;
4903
4904 if (i == last_inst)
4905 alu.last = 1;
4906 r = r600_bytecode_add_alu(ctx->bc, &alu);
4907 if (r)
4908 return r;
4909 }
4910 return 0;
4911 }
4912
4913 static int tgsi_issg(struct r600_shader_ctx *ctx)
4914 {
4915 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4916 struct r600_bytecode_alu alu;
4917 int i, r;
4918 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4919 int last_inst = tgsi_last_instruction(write_mask);
4920
4921 /* tmp = (src >= 0 ? src : -1) */
4922 for (i = 0; i < 4; i++) {
4923 if (!(write_mask & (1<<i)))
4924 continue;
4925
4926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4927 alu.op = ALU_OP3_CNDGE_INT;
4928 alu.is_op3 = 1;
4929
4930 alu.dst.sel = ctx->temp_reg;
4931 alu.dst.chan = i;
4932 alu.dst.write = 1;
4933
4934 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4935 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4936 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
4937
4938 if (i == last_inst)
4939 alu.last = 1;
4940 r = r600_bytecode_add_alu(ctx->bc, &alu);
4941 if (r)
4942 return r;
4943 }
4944
4945 /* dst = (tmp > 0 ? 1 : tmp) */
4946 for (i = 0; i < 4; i++) {
4947 if (!(write_mask & (1<<i)))
4948 continue;
4949
4950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4951 alu.op = ALU_OP3_CNDGT_INT;
4952 alu.is_op3 = 1;
4953 alu.dst.write = 1;
4954
4955 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4956
4957 alu.src[0].sel = ctx->temp_reg;
4958 alu.src[0].chan = i;
4959
4960 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4961
4962 alu.src[2].sel = ctx->temp_reg;
4963 alu.src[2].chan = i;
4964
4965 if (i == last_inst)
4966 alu.last = 1;
4967 r = r600_bytecode_add_alu(ctx->bc, &alu);
4968 if (r)
4969 return r;
4970 }
4971 return 0;
4972 }
4973
4974
4975
4976 static int tgsi_ssg(struct r600_shader_ctx *ctx)
4977 {
4978 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4979 struct r600_bytecode_alu alu;
4980 int i, r;
4981
4982 /* tmp = (src > 0 ? 1 : src) */
4983 for (i = 0; i < 4; i++) {
4984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4985 alu.op = ALU_OP3_CNDGT;
4986 alu.is_op3 = 1;
4987
4988 alu.dst.sel = ctx->temp_reg;
4989 alu.dst.chan = i;
4990
4991 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4992 alu.src[1].sel = V_SQ_ALU_SRC_1;
4993 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
4994
4995 if (i == 3)
4996 alu.last = 1;
4997 r = r600_bytecode_add_alu(ctx->bc, &alu);
4998 if (r)
4999 return r;
5000 }
5001
5002 /* dst = (-tmp > 0 ? -1 : tmp) */
5003 for (i = 0; i < 4; i++) {
5004 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5005 alu.op = ALU_OP3_CNDGT;
5006 alu.is_op3 = 1;
5007 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5008
5009 alu.src[0].sel = ctx->temp_reg;
5010 alu.src[0].chan = i;
5011 alu.src[0].neg = 1;
5012
5013 alu.src[1].sel = V_SQ_ALU_SRC_1;
5014 alu.src[1].neg = 1;
5015
5016 alu.src[2].sel = ctx->temp_reg;
5017 alu.src[2].chan = i;
5018
5019 if (i == 3)
5020 alu.last = 1;
5021 r = r600_bytecode_add_alu(ctx->bc, &alu);
5022 if (r)
5023 return r;
5024 }
5025 return 0;
5026 }
5027
5028 static int tgsi_bfi(struct r600_shader_ctx *ctx)
5029 {
5030 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5031 struct r600_bytecode_alu alu;
5032 int i, r, t1, t2;
5033
5034 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5035 int last_inst = tgsi_last_instruction(write_mask);
5036
5037 t1 = ctx->temp_reg;
5038
5039 for (i = 0; i < 4; i++) {
5040 if (!(write_mask & (1<<i)))
5041 continue;
5042
5043 /* create mask tmp */
5044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5045 alu.op = ALU_OP2_BFM_INT;
5046 alu.dst.sel = t1;
5047 alu.dst.chan = i;
5048 alu.dst.write = 1;
5049 alu.last = i == last_inst;
5050
5051 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
5052 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5053
5054 r = r600_bytecode_add_alu(ctx->bc, &alu);
5055 if (r)
5056 return r;
5057 }
5058
5059 t2 = r600_get_temp(ctx);
5060
5061 for (i = 0; i < 4; i++) {
5062 if (!(write_mask & (1<<i)))
5063 continue;
5064
5065 /* shift insert left */
5066 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5067 alu.op = ALU_OP2_LSHL_INT;
5068 alu.dst.sel = t2;
5069 alu.dst.chan = i;
5070 alu.dst.write = 1;
5071 alu.last = i == last_inst;
5072
5073 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5074 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5075
5076 r = r600_bytecode_add_alu(ctx->bc, &alu);
5077 if (r)
5078 return r;
5079 }
5080
5081 for (i = 0; i < 4; i++) {
5082 if (!(write_mask & (1<<i)))
5083 continue;
5084
5085 /* actual bitfield insert */
5086 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5087 alu.op = ALU_OP3_BFI_INT;
5088 alu.is_op3 = 1;
5089 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5090 alu.dst.chan = i;
5091 alu.dst.write = 1;
5092 alu.last = i == last_inst;
5093
5094 alu.src[0].sel = t1;
5095 alu.src[0].chan = i;
5096 alu.src[1].sel = t2;
5097 alu.src[1].chan = i;
5098 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
5099
5100 r = r600_bytecode_add_alu(ctx->bc, &alu);
5101 if (r)
5102 return r;
5103 }
5104
5105 return 0;
5106 }
5107
5108 static int tgsi_msb(struct r600_shader_ctx *ctx)
5109 {
5110 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5111 struct r600_bytecode_alu alu;
5112 int i, r, t1, t2;
5113
5114 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5115 int last_inst = tgsi_last_instruction(write_mask);
5116
5117 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
5118 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
5119
5120 t1 = ctx->temp_reg;
5121
5122 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
5123 for (i = 0; i < 4; i++) {
5124 if (!(write_mask & (1<<i)))
5125 continue;
5126
5127 /* t1 = FFBH_INT / FFBH_UINT */
5128 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5129 alu.op = ctx->inst_info->op;
5130 alu.dst.sel = t1;
5131 alu.dst.chan = i;
5132 alu.dst.write = 1;
5133 alu.last = i == last_inst;
5134
5135 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5136
5137 r = r600_bytecode_add_alu(ctx->bc, &alu);
5138 if (r)
5139 return r;
5140 }
5141
5142 t2 = r600_get_temp(ctx);
5143
5144 for (i = 0; i < 4; i++) {
5145 if (!(write_mask & (1<<i)))
5146 continue;
5147
5148 /* t2 = 31 - t1 */
5149 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5150 alu.op = ALU_OP2_SUB_INT;
5151 alu.dst.sel = t2;
5152 alu.dst.chan = i;
5153 alu.dst.write = 1;
5154 alu.last = i == last_inst;
5155
5156 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
5157 alu.src[0].value = 31;
5158 alu.src[1].sel = t1;
5159 alu.src[1].chan = i;
5160
5161 r = r600_bytecode_add_alu(ctx->bc, &alu);
5162 if (r)
5163 return r;
5164 }
5165
5166 for (i = 0; i < 4; i++) {
5167 if (!(write_mask & (1<<i)))
5168 continue;
5169
5170 /* result = t1 >= 0 ? t2 : t1 */
5171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5172 alu.op = ALU_OP3_CNDGE_INT;
5173 alu.is_op3 = 1;
5174 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5175 alu.dst.chan = i;
5176 alu.dst.write = 1;
5177 alu.last = i == last_inst;
5178
5179 alu.src[0].sel = t1;
5180 alu.src[0].chan = i;
5181 alu.src[1].sel = t2;
5182 alu.src[1].chan = i;
5183 alu.src[2].sel = t1;
5184 alu.src[2].chan = i;
5185
5186 r = r600_bytecode_add_alu(ctx->bc, &alu);
5187 if (r)
5188 return r;
5189 }
5190
5191 return 0;
5192 }
5193
5194 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
5195 {
5196 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5197 struct r600_bytecode_alu alu;
5198 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
5199 unsigned location;
5200 int input;
5201
5202 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5203
5204 input = inst->Src[0].Register.Index;
5205
5206 /* Interpolators have been marked for use already by allocate_system_value_inputs */
5207 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5208 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5209 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
5210 }
5211 else {
5212 location = TGSI_INTERPOLATE_LOC_CENTROID;
5213 }
5214
5215 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
5216 if (k < 0)
5217 k = 0;
5218 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
5219 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
5220
5221 /* NOTE: currently offset is not perspective correct */
5222 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5223 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5224 int sample_gpr = -1;
5225 int gradientsH, gradientsV;
5226 struct r600_bytecode_tex tex;
5227
5228 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5229 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
5230 }
5231
5232 gradientsH = r600_get_temp(ctx);
5233 gradientsV = r600_get_temp(ctx);
5234 for (i = 0; i < 2; i++) {
5235 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5236 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
5237 tex.src_gpr = interp_gpr;
5238 tex.src_sel_x = interp_base_chan + 0;
5239 tex.src_sel_y = interp_base_chan + 1;
5240 tex.src_sel_z = 0;
5241 tex.src_sel_w = 0;
5242 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
5243 tex.dst_sel_x = 0;
5244 tex.dst_sel_y = 1;
5245 tex.dst_sel_z = 7;
5246 tex.dst_sel_w = 7;
5247 tex.inst_mod = 1; // Use per pixel gradient calculation
5248 tex.sampler_id = 0;
5249 tex.resource_id = tex.sampler_id;
5250 r = r600_bytecode_add_tex(ctx->bc, &tex);
5251 if (r)
5252 return r;
5253 }
5254
5255 for (i = 0; i < 2; i++) {
5256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5257 alu.op = ALU_OP3_MULADD;
5258 alu.is_op3 = 1;
5259 alu.src[0].sel = gradientsH;
5260 alu.src[0].chan = i;
5261 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5262 alu.src[1].sel = sample_gpr;
5263 alu.src[1].chan = 2;
5264 }
5265 else {
5266 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
5267 }
5268 alu.src[2].sel = interp_gpr;
5269 alu.src[2].chan = interp_base_chan + i;
5270 alu.dst.sel = ctx->temp_reg;
5271 alu.dst.chan = i;
5272 alu.last = i == 1;
5273
5274 r = r600_bytecode_add_alu(ctx->bc, &alu);
5275 if (r)
5276 return r;
5277 }
5278
5279 for (i = 0; i < 2; i++) {
5280 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5281 alu.op = ALU_OP3_MULADD;
5282 alu.is_op3 = 1;
5283 alu.src[0].sel = gradientsV;
5284 alu.src[0].chan = i;
5285 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5286 alu.src[1].sel = sample_gpr;
5287 alu.src[1].chan = 3;
5288 }
5289 else {
5290 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
5291 }
5292 alu.src[2].sel = ctx->temp_reg;
5293 alu.src[2].chan = i;
5294 alu.dst.sel = ctx->temp_reg;
5295 alu.dst.chan = i;
5296 alu.last = i == 1;
5297
5298 r = r600_bytecode_add_alu(ctx->bc, &alu);
5299 if (r)
5300 return r;
5301 }
5302 }
5303
5304 tmp = r600_get_temp(ctx);
5305 for (i = 0; i < 8; i++) {
5306 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5307 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
5308
5309 alu.dst.sel = tmp;
5310 if ((i > 1 && i < 6)) {
5311 alu.dst.write = 1;
5312 }
5313 else {
5314 alu.dst.write = 0;
5315 }
5316 alu.dst.chan = i % 4;
5317
5318 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5319 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5320 alu.src[0].sel = ctx->temp_reg;
5321 alu.src[0].chan = 1 - (i % 2);
5322 } else {
5323 alu.src[0].sel = interp_gpr;
5324 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
5325 }
5326 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
5327 alu.src[1].chan = 0;
5328
5329 alu.last = i % 4 == 3;
5330 alu.bank_swizzle_force = SQ_ALU_VEC_210;
5331
5332 r = r600_bytecode_add_alu(ctx->bc, &alu);
5333 if (r)
5334 return r;
5335 }
5336
5337 // INTERP can't swizzle dst
5338 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5339 for (i = 0; i <= lasti; i++) {
5340 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5341 continue;
5342
5343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5344 alu.op = ALU_OP1_MOV;
5345 alu.src[0].sel = tmp;
5346 alu.src[0].chan = ctx->src[0].swizzle[i];
5347 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5348 alu.dst.write = 1;
5349 alu.last = i == lasti;
5350 r = r600_bytecode_add_alu(ctx->bc, &alu);
5351 if (r)
5352 return r;
5353 }
5354
5355 return 0;
5356 }
5357
5358
5359 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
5360 {
5361 struct r600_bytecode_alu alu;
5362 int i, r;
5363
5364 for (i = 0; i < 4; i++) {
5365 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5366 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
5367 alu.op = ALU_OP0_NOP;
5368 alu.dst.chan = i;
5369 } else {
5370 alu.op = ALU_OP1_MOV;
5371 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5372 alu.src[0].sel = ctx->temp_reg;
5373 alu.src[0].chan = i;
5374 }
5375 if (i == 3) {
5376 alu.last = 1;
5377 }
5378 r = r600_bytecode_add_alu(ctx->bc, &alu);
5379 if (r)
5380 return r;
5381 }
5382 return 0;
5383 }
5384
5385 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
5386 unsigned temp, int chan,
5387 struct r600_bytecode_alu_src *bc_src,
5388 const struct r600_shader_src *shader_src)
5389 {
5390 struct r600_bytecode_alu alu;
5391 int r;
5392
5393 r600_bytecode_src(bc_src, shader_src, chan);
5394
5395 /* op3 operands don't support abs modifier */
5396 if (bc_src->abs) {
5397 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
5398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5399 alu.op = ALU_OP1_MOV;
5400 alu.dst.sel = temp;
5401 alu.dst.chan = chan;
5402 alu.dst.write = 1;
5403
5404 alu.src[0] = *bc_src;
5405 alu.last = true; // sufficient?
5406 r = r600_bytecode_add_alu(ctx->bc, &alu);
5407 if (r)
5408 return r;
5409
5410 memset(bc_src, 0, sizeof(*bc_src));
5411 bc_src->sel = temp;
5412 bc_src->chan = chan;
5413 }
5414 return 0;
5415 }
5416
5417 static int tgsi_op3(struct r600_shader_ctx *ctx)
5418 {
5419 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5420 struct r600_bytecode_alu alu;
5421 int i, j, r;
5422 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5423 int temp_regs[4];
5424
5425 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5426 temp_regs[j] = 0;
5427 if (ctx->src[j].abs)
5428 temp_regs[j] = r600_get_temp(ctx);
5429 }
5430 for (i = 0; i < lasti + 1; i++) {
5431 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5432 continue;
5433
5434 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5435 alu.op = ctx->inst_info->op;
5436 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5437 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
5438 if (r)
5439 return r;
5440 }
5441
5442 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5443 alu.dst.chan = i;
5444 alu.dst.write = 1;
5445 alu.is_op3 = 1;
5446 if (i == lasti) {
5447 alu.last = 1;
5448 }
5449 r = r600_bytecode_add_alu(ctx->bc, &alu);
5450 if (r)
5451 return r;
5452 }
5453 return 0;
5454 }
5455
5456 static int tgsi_dp(struct r600_shader_ctx *ctx)
5457 {
5458 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5459 struct r600_bytecode_alu alu;
5460 int i, j, r;
5461
5462 for (i = 0; i < 4; i++) {
5463 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5464 alu.op = ctx->inst_info->op;
5465 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5466 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5467 }
5468
5469 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5470 alu.dst.chan = i;
5471 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5472 /* handle some special cases */
5473 switch (inst->Instruction.Opcode) {
5474 case TGSI_OPCODE_DP2:
5475 if (i > 1) {
5476 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5477 alu.src[0].chan = alu.src[1].chan = 0;
5478 }
5479 break;
5480 case TGSI_OPCODE_DP3:
5481 if (i > 2) {
5482 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5483 alu.src[0].chan = alu.src[1].chan = 0;
5484 }
5485 break;
5486 case TGSI_OPCODE_DPH:
5487 if (i == 3) {
5488 alu.src[0].sel = V_SQ_ALU_SRC_1;
5489 alu.src[0].chan = 0;
5490 alu.src[0].neg = 0;
5491 }
5492 break;
5493 default:
5494 break;
5495 }
5496 if (i == 3) {
5497 alu.last = 1;
5498 }
5499 r = r600_bytecode_add_alu(ctx->bc, &alu);
5500 if (r)
5501 return r;
5502 }
5503 return 0;
5504 }
5505
5506 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
5507 unsigned index)
5508 {
5509 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5510 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
5511 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
5512 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
5513 ctx->src[index].neg || ctx->src[index].abs ||
5514 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
5515 }
5516
5517 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
5518 unsigned index)
5519 {
5520 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5521 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
5522 }
5523
5524 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
5525 {
5526 struct r600_bytecode_vtx vtx;
5527 struct r600_bytecode_alu alu;
5528 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5529 int src_gpr, r, i;
5530 int id = tgsi_tex_get_src_gpr(ctx, 1);
5531
5532 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5533 if (src_requires_loading) {
5534 for (i = 0; i < 4; i++) {
5535 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5536 alu.op = ALU_OP1_MOV;
5537 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5538 alu.dst.sel = ctx->temp_reg;
5539 alu.dst.chan = i;
5540 if (i == 3)
5541 alu.last = 1;
5542 alu.dst.write = 1;
5543 r = r600_bytecode_add_alu(ctx->bc, &alu);
5544 if (r)
5545 return r;
5546 }
5547 src_gpr = ctx->temp_reg;
5548 }
5549
5550 memset(&vtx, 0, sizeof(vtx));
5551 vtx.op = FETCH_OP_VFETCH;
5552 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
5553 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
5554 vtx.src_gpr = src_gpr;
5555 vtx.mega_fetch_count = 16;
5556 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5557 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
5558 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
5559 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
5560 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
5561 vtx.use_const_fields = 1;
5562
5563 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
5564 return r;
5565
5566 if (ctx->bc->chip_class >= EVERGREEN)
5567 return 0;
5568
5569 for (i = 0; i < 4; i++) {
5570 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5571 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5572 continue;
5573
5574 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5575 alu.op = ALU_OP2_AND_INT;
5576
5577 alu.dst.chan = i;
5578 alu.dst.sel = vtx.dst_gpr;
5579 alu.dst.write = 1;
5580
5581 alu.src[0].sel = vtx.dst_gpr;
5582 alu.src[0].chan = i;
5583
5584 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
5585 alu.src[1].sel += (id * 2);
5586 alu.src[1].chan = i % 4;
5587 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5588
5589 if (i == lasti)
5590 alu.last = 1;
5591 r = r600_bytecode_add_alu(ctx->bc, &alu);
5592 if (r)
5593 return r;
5594 }
5595
5596 if (inst->Dst[0].Register.WriteMask & 3) {
5597 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5598 alu.op = ALU_OP2_OR_INT;
5599
5600 alu.dst.chan = 3;
5601 alu.dst.sel = vtx.dst_gpr;
5602 alu.dst.write = 1;
5603
5604 alu.src[0].sel = vtx.dst_gpr;
5605 alu.src[0].chan = 3;
5606
5607 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
5608 alu.src[1].chan = 0;
5609 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5610
5611 alu.last = 1;
5612 r = r600_bytecode_add_alu(ctx->bc, &alu);
5613 if (r)
5614 return r;
5615 }
5616 return 0;
5617 }
5618
5619 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
5620 {
5621 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5622 struct r600_bytecode_alu alu;
5623 int r;
5624 int id = tgsi_tex_get_src_gpr(ctx, 1);
5625
5626 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5627 alu.op = ALU_OP1_MOV;
5628 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
5629 if (ctx->bc->chip_class >= EVERGREEN) {
5630 /* channel 0 or 2 of each word */
5631 alu.src[0].sel += (id / 2);
5632 alu.src[0].chan = (id % 2) * 2;
5633 } else {
5634 /* r600 we have them at channel 2 of the second dword */
5635 alu.src[0].sel += (id * 2) + 1;
5636 alu.src[0].chan = 1;
5637 }
5638 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5639 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5640 alu.last = 1;
5641 r = r600_bytecode_add_alu(ctx->bc, &alu);
5642 if (r)
5643 return r;
5644 return 0;
5645 }
5646
5647 static int tgsi_tex(struct r600_shader_ctx *ctx)
5648 {
5649 static float one_point_five = 1.5f;
5650 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5651 struct r600_bytecode_tex tex;
5652 struct r600_bytecode_alu alu;
5653 unsigned src_gpr;
5654 int r, i, j;
5655 int opcode;
5656 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
5657 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5658 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
5659 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
5660
5661 bool txf_add_offsets = inst->Texture.NumOffsets &&
5662 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5663 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
5664
5665 /* Texture fetch instructions can only use gprs as source.
5666 * Also they cannot negate the source or take the absolute value */
5667 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
5668 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
5669 tgsi_tex_src_requires_loading(ctx, 0)) ||
5670 read_compressed_msaa || txf_add_offsets;
5671
5672 boolean src_loaded = FALSE;
5673 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
5674 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
5675 boolean has_txq_cube_array_z = false;
5676 unsigned sampler_index_mode;
5677
5678 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
5679 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5680 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
5681 if (inst->Dst[0].Register.WriteMask & 4) {
5682 ctx->shader->has_txq_cube_array_z_comp = true;
5683 has_txq_cube_array_z = true;
5684 }
5685
5686 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
5687 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5688 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
5689 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
5690 sampler_src_reg = 2;
5691
5692 /* TGSI moves the sampler to src reg 3 for TXD */
5693 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
5694 sampler_src_reg = 3;
5695
5696 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
5697
5698 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5699
5700 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
5701 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
5702 ctx->shader->uses_tex_buffers = true;
5703 return r600_do_buffer_txq(ctx);
5704 }
5705 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
5706 if (ctx->bc->chip_class < EVERGREEN)
5707 ctx->shader->uses_tex_buffers = true;
5708 return do_vtx_fetch_inst(ctx, src_requires_loading);
5709 }
5710 }
5711
5712 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
5713 int out_chan;
5714 /* Add perspective divide */
5715 if (ctx->bc->chip_class == CAYMAN) {
5716 out_chan = 2;
5717 for (i = 0; i < 3; i++) {
5718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5719 alu.op = ALU_OP1_RECIP_IEEE;
5720 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5721
5722 alu.dst.sel = ctx->temp_reg;
5723 alu.dst.chan = i;
5724 if (i == 2)
5725 alu.last = 1;
5726 if (out_chan == i)
5727 alu.dst.write = 1;
5728 r = r600_bytecode_add_alu(ctx->bc, &alu);
5729 if (r)
5730 return r;
5731 }
5732
5733 } else {
5734 out_chan = 3;
5735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5736 alu.op = ALU_OP1_RECIP_IEEE;
5737 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5738
5739 alu.dst.sel = ctx->temp_reg;
5740 alu.dst.chan = out_chan;
5741 alu.last = 1;
5742 alu.dst.write = 1;
5743 r = r600_bytecode_add_alu(ctx->bc, &alu);
5744 if (r)
5745 return r;
5746 }
5747
5748 for (i = 0; i < 3; i++) {
5749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5750 alu.op = ALU_OP2_MUL;
5751 alu.src[0].sel = ctx->temp_reg;
5752 alu.src[0].chan = out_chan;
5753 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5754 alu.dst.sel = ctx->temp_reg;
5755 alu.dst.chan = i;
5756 alu.dst.write = 1;
5757 r = r600_bytecode_add_alu(ctx->bc, &alu);
5758 if (r)
5759 return r;
5760 }
5761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5762 alu.op = ALU_OP1_MOV;
5763 alu.src[0].sel = V_SQ_ALU_SRC_1;
5764 alu.src[0].chan = 0;
5765 alu.dst.sel = ctx->temp_reg;
5766 alu.dst.chan = 3;
5767 alu.last = 1;
5768 alu.dst.write = 1;
5769 r = r600_bytecode_add_alu(ctx->bc, &alu);
5770 if (r)
5771 return r;
5772 src_loaded = TRUE;
5773 src_gpr = ctx->temp_reg;
5774 }
5775
5776
5777 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
5778 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5779 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5780 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
5781 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
5782 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
5783
5784 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
5785 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
5786
5787 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
5788 for (i = 0; i < 4; i++) {
5789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5790 alu.op = ALU_OP2_CUBE;
5791 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5792 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
5793 alu.dst.sel = ctx->temp_reg;
5794 alu.dst.chan = i;
5795 if (i == 3)
5796 alu.last = 1;
5797 alu.dst.write = 1;
5798 r = r600_bytecode_add_alu(ctx->bc, &alu);
5799 if (r)
5800 return r;
5801 }
5802
5803 /* tmp1.z = RCP_e(|tmp1.z|) */
5804 if (ctx->bc->chip_class == CAYMAN) {
5805 for (i = 0; i < 3; i++) {
5806 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5807 alu.op = ALU_OP1_RECIP_IEEE;
5808 alu.src[0].sel = ctx->temp_reg;
5809 alu.src[0].chan = 2;
5810 alu.src[0].abs = 1;
5811 alu.dst.sel = ctx->temp_reg;
5812 alu.dst.chan = i;
5813 if (i == 2)
5814 alu.dst.write = 1;
5815 if (i == 2)
5816 alu.last = 1;
5817 r = r600_bytecode_add_alu(ctx->bc, &alu);
5818 if (r)
5819 return r;
5820 }
5821 } else {
5822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5823 alu.op = ALU_OP1_RECIP_IEEE;
5824 alu.src[0].sel = ctx->temp_reg;
5825 alu.src[0].chan = 2;
5826 alu.src[0].abs = 1;
5827 alu.dst.sel = ctx->temp_reg;
5828 alu.dst.chan = 2;
5829 alu.dst.write = 1;
5830 alu.last = 1;
5831 r = r600_bytecode_add_alu(ctx->bc, &alu);
5832 if (r)
5833 return r;
5834 }
5835
5836 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
5837 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
5838 * muladd has no writemask, have to use another temp
5839 */
5840 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5841 alu.op = ALU_OP3_MULADD;
5842 alu.is_op3 = 1;
5843
5844 alu.src[0].sel = ctx->temp_reg;
5845 alu.src[0].chan = 0;
5846 alu.src[1].sel = ctx->temp_reg;
5847 alu.src[1].chan = 2;
5848
5849 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5850 alu.src[2].chan = 0;
5851 alu.src[2].value = *(uint32_t *)&one_point_five;
5852
5853 alu.dst.sel = ctx->temp_reg;
5854 alu.dst.chan = 0;
5855 alu.dst.write = 1;
5856
5857 r = r600_bytecode_add_alu(ctx->bc, &alu);
5858 if (r)
5859 return r;
5860
5861 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5862 alu.op = ALU_OP3_MULADD;
5863 alu.is_op3 = 1;
5864
5865 alu.src[0].sel = ctx->temp_reg;
5866 alu.src[0].chan = 1;
5867 alu.src[1].sel = ctx->temp_reg;
5868 alu.src[1].chan = 2;
5869
5870 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5871 alu.src[2].chan = 0;
5872 alu.src[2].value = *(uint32_t *)&one_point_five;
5873
5874 alu.dst.sel = ctx->temp_reg;
5875 alu.dst.chan = 1;
5876 alu.dst.write = 1;
5877
5878 alu.last = 1;
5879 r = r600_bytecode_add_alu(ctx->bc, &alu);
5880 if (r)
5881 return r;
5882 /* write initial compare value into Z component
5883 - W src 0 for shadow cube
5884 - X src 1 for shadow cube array */
5885 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5886 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5888 alu.op = ALU_OP1_MOV;
5889 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
5890 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5891 else
5892 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5893 alu.dst.sel = ctx->temp_reg;
5894 alu.dst.chan = 2;
5895 alu.dst.write = 1;
5896 alu.last = 1;
5897 r = r600_bytecode_add_alu(ctx->bc, &alu);
5898 if (r)
5899 return r;
5900 }
5901
5902 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5903 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5904 if (ctx->bc->chip_class >= EVERGREEN) {
5905 int mytmp = r600_get_temp(ctx);
5906 static const float eight = 8.0f;
5907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5908 alu.op = ALU_OP1_MOV;
5909 alu.src[0].sel = ctx->temp_reg;
5910 alu.src[0].chan = 3;
5911 alu.dst.sel = mytmp;
5912 alu.dst.chan = 0;
5913 alu.dst.write = 1;
5914 alu.last = 1;
5915 r = r600_bytecode_add_alu(ctx->bc, &alu);
5916 if (r)
5917 return r;
5918
5919 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
5920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5921 alu.op = ALU_OP3_MULADD;
5922 alu.is_op3 = 1;
5923 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5924 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5925 alu.src[1].chan = 0;
5926 alu.src[1].value = *(uint32_t *)&eight;
5927 alu.src[2].sel = mytmp;
5928 alu.src[2].chan = 0;
5929 alu.dst.sel = ctx->temp_reg;
5930 alu.dst.chan = 3;
5931 alu.dst.write = 1;
5932 alu.last = 1;
5933 r = r600_bytecode_add_alu(ctx->bc, &alu);
5934 if (r)
5935 return r;
5936 } else if (ctx->bc->chip_class < EVERGREEN) {
5937 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5938 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
5939 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5940 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5941 tex.src_gpr = r600_get_temp(ctx);
5942 tex.src_sel_x = 0;
5943 tex.src_sel_y = 0;
5944 tex.src_sel_z = 0;
5945 tex.src_sel_w = 0;
5946 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
5947 tex.coord_type_x = 1;
5948 tex.coord_type_y = 1;
5949 tex.coord_type_z = 1;
5950 tex.coord_type_w = 1;
5951 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5952 alu.op = ALU_OP1_MOV;
5953 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5954 alu.dst.sel = tex.src_gpr;
5955 alu.dst.chan = 0;
5956 alu.last = 1;
5957 alu.dst.write = 1;
5958 r = r600_bytecode_add_alu(ctx->bc, &alu);
5959 if (r)
5960 return r;
5961
5962 r = r600_bytecode_add_tex(ctx->bc, &tex);
5963 if (r)
5964 return r;
5965 }
5966
5967 }
5968
5969 /* for cube forms of lod and bias we need to route things */
5970 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
5971 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
5972 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5973 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
5974 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5975 alu.op = ALU_OP1_MOV;
5976 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5977 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
5978 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5979 else
5980 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5981 alu.dst.sel = ctx->temp_reg;
5982 alu.dst.chan = 2;
5983 alu.last = 1;
5984 alu.dst.write = 1;
5985 r = r600_bytecode_add_alu(ctx->bc, &alu);
5986 if (r)
5987 return r;
5988 }
5989
5990 src_loaded = TRUE;
5991 src_gpr = ctx->temp_reg;
5992 }
5993
5994 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
5995 int temp_h = 0, temp_v = 0;
5996 int start_val = 0;
5997
5998 /* if we've already loaded the src (i.e. CUBE don't reload it). */
5999 if (src_loaded == TRUE)
6000 start_val = 1;
6001 else
6002 src_loaded = TRUE;
6003 for (i = start_val; i < 3; i++) {
6004 int treg = r600_get_temp(ctx);
6005
6006 if (i == 0)
6007 src_gpr = treg;
6008 else if (i == 1)
6009 temp_h = treg;
6010 else
6011 temp_v = treg;
6012
6013 for (j = 0; j < 4; j++) {
6014 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6015 alu.op = ALU_OP1_MOV;
6016 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
6017 alu.dst.sel = treg;
6018 alu.dst.chan = j;
6019 if (j == 3)
6020 alu.last = 1;
6021 alu.dst.write = 1;
6022 r = r600_bytecode_add_alu(ctx->bc, &alu);
6023 if (r)
6024 return r;
6025 }
6026 }
6027 for (i = 1; i < 3; i++) {
6028 /* set gradients h/v */
6029 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6030 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
6031 FETCH_OP_SET_GRADIENTS_V;
6032 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6033 tex.sampler_index_mode = sampler_index_mode;
6034 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6035 tex.resource_index_mode = sampler_index_mode;
6036
6037 tex.src_gpr = (i == 1) ? temp_h : temp_v;
6038 tex.src_sel_x = 0;
6039 tex.src_sel_y = 1;
6040 tex.src_sel_z = 2;
6041 tex.src_sel_w = 3;
6042
6043 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
6044 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
6045 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
6046 tex.coord_type_x = 1;
6047 tex.coord_type_y = 1;
6048 tex.coord_type_z = 1;
6049 tex.coord_type_w = 1;
6050 }
6051 r = r600_bytecode_add_tex(ctx->bc, &tex);
6052 if (r)
6053 return r;
6054 }
6055 }
6056
6057 if (src_requires_loading && !src_loaded) {
6058 for (i = 0; i < 4; i++) {
6059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6060 alu.op = ALU_OP1_MOV;
6061 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6062 alu.dst.sel = ctx->temp_reg;
6063 alu.dst.chan = i;
6064 if (i == 3)
6065 alu.last = 1;
6066 alu.dst.write = 1;
6067 r = r600_bytecode_add_alu(ctx->bc, &alu);
6068 if (r)
6069 return r;
6070 }
6071 src_loaded = TRUE;
6072 src_gpr = ctx->temp_reg;
6073 }
6074
6075 /* get offset values */
6076 if (inst->Texture.NumOffsets) {
6077 assert(inst->Texture.NumOffsets == 1);
6078
6079 /* The texture offset feature doesn't work with the TXF instruction
6080 * and must be emulated by adding the offset to the texture coordinates. */
6081 if (txf_add_offsets) {
6082 const struct tgsi_texture_offset *off = inst->TexOffsets;
6083
6084 switch (inst->Texture.Texture) {
6085 case TGSI_TEXTURE_3D:
6086 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6087 alu.op = ALU_OP2_ADD_INT;
6088 alu.src[0].sel = src_gpr;
6089 alu.src[0].chan = 2;
6090 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6091 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
6092 alu.dst.sel = src_gpr;
6093 alu.dst.chan = 2;
6094 alu.dst.write = 1;
6095 alu.last = 1;
6096 r = r600_bytecode_add_alu(ctx->bc, &alu);
6097 if (r)
6098 return r;
6099 /* fall through */
6100
6101 case TGSI_TEXTURE_2D:
6102 case TGSI_TEXTURE_SHADOW2D:
6103 case TGSI_TEXTURE_RECT:
6104 case TGSI_TEXTURE_SHADOWRECT:
6105 case TGSI_TEXTURE_2D_ARRAY:
6106 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6107 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6108 alu.op = ALU_OP2_ADD_INT;
6109 alu.src[0].sel = src_gpr;
6110 alu.src[0].chan = 1;
6111 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6112 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
6113 alu.dst.sel = src_gpr;
6114 alu.dst.chan = 1;
6115 alu.dst.write = 1;
6116 alu.last = 1;
6117 r = r600_bytecode_add_alu(ctx->bc, &alu);
6118 if (r)
6119 return r;
6120 /* fall through */
6121
6122 case TGSI_TEXTURE_1D:
6123 case TGSI_TEXTURE_SHADOW1D:
6124 case TGSI_TEXTURE_1D_ARRAY:
6125 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6126 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6127 alu.op = ALU_OP2_ADD_INT;
6128 alu.src[0].sel = src_gpr;
6129 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6130 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
6131 alu.dst.sel = src_gpr;
6132 alu.dst.write = 1;
6133 alu.last = 1;
6134 r = r600_bytecode_add_alu(ctx->bc, &alu);
6135 if (r)
6136 return r;
6137 break;
6138 /* texture offsets do not apply to other texture targets */
6139 }
6140 } else {
6141 switch (inst->Texture.Texture) {
6142 case TGSI_TEXTURE_3D:
6143 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
6144 /* fallthrough */
6145 case TGSI_TEXTURE_2D:
6146 case TGSI_TEXTURE_SHADOW2D:
6147 case TGSI_TEXTURE_RECT:
6148 case TGSI_TEXTURE_SHADOWRECT:
6149 case TGSI_TEXTURE_2D_ARRAY:
6150 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6151 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
6152 /* fallthrough */
6153 case TGSI_TEXTURE_1D:
6154 case TGSI_TEXTURE_SHADOW1D:
6155 case TGSI_TEXTURE_1D_ARRAY:
6156 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6157 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
6158 }
6159 }
6160 }
6161
6162 /* Obtain the sample index for reading a compressed MSAA color texture.
6163 * To read the FMASK, we use the ldfptr instruction, which tells us
6164 * where the samples are stored.
6165 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
6166 * which is the identity mapping. Each nibble says which physical sample
6167 * should be fetched to get that sample.
6168 *
6169 * Assume src.z contains the sample index. It should be modified like this:
6170 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
6171 * Then fetch the texel with src.
6172 */
6173 if (read_compressed_msaa) {
6174 unsigned sample_chan = 3;
6175 unsigned temp = r600_get_temp(ctx);
6176 assert(src_loaded);
6177
6178 /* temp.w = ldfptr() */
6179 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6180 tex.op = FETCH_OP_LD;
6181 tex.inst_mod = 1; /* to indicate this is ldfptr */
6182 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6183 tex.sampler_index_mode = sampler_index_mode;
6184 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6185 tex.resource_index_mode = sampler_index_mode;
6186 tex.src_gpr = src_gpr;
6187 tex.dst_gpr = temp;
6188 tex.dst_sel_x = 7; /* mask out these components */
6189 tex.dst_sel_y = 7;
6190 tex.dst_sel_z = 7;
6191 tex.dst_sel_w = 0; /* store X */
6192 tex.src_sel_x = 0;
6193 tex.src_sel_y = 1;
6194 tex.src_sel_z = 2;
6195 tex.src_sel_w = 3;
6196 tex.offset_x = offset_x;
6197 tex.offset_y = offset_y;
6198 tex.offset_z = offset_z;
6199 r = r600_bytecode_add_tex(ctx->bc, &tex);
6200 if (r)
6201 return r;
6202
6203 /* temp.x = sample_index*4 */
6204 if (ctx->bc->chip_class == CAYMAN) {
6205 for (i = 0 ; i < 4; i++) {
6206 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6207 alu.op = ALU_OP2_MULLO_INT;
6208 alu.src[0].sel = src_gpr;
6209 alu.src[0].chan = sample_chan;
6210 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6211 alu.src[1].value = 4;
6212 alu.dst.sel = temp;
6213 alu.dst.chan = i;
6214 alu.dst.write = i == 0;
6215 if (i == 3)
6216 alu.last = 1;
6217 r = r600_bytecode_add_alu(ctx->bc, &alu);
6218 if (r)
6219 return r;
6220 }
6221 } else {
6222 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6223 alu.op = ALU_OP2_MULLO_INT;
6224 alu.src[0].sel = src_gpr;
6225 alu.src[0].chan = sample_chan;
6226 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6227 alu.src[1].value = 4;
6228 alu.dst.sel = temp;
6229 alu.dst.chan = 0;
6230 alu.dst.write = 1;
6231 alu.last = 1;
6232 r = r600_bytecode_add_alu(ctx->bc, &alu);
6233 if (r)
6234 return r;
6235 }
6236
6237 /* sample_index = temp.w >> temp.x */
6238 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6239 alu.op = ALU_OP2_LSHR_INT;
6240 alu.src[0].sel = temp;
6241 alu.src[0].chan = 3;
6242 alu.src[1].sel = temp;
6243 alu.src[1].chan = 0;
6244 alu.dst.sel = src_gpr;
6245 alu.dst.chan = sample_chan;
6246 alu.dst.write = 1;
6247 alu.last = 1;
6248 r = r600_bytecode_add_alu(ctx->bc, &alu);
6249 if (r)
6250 return r;
6251
6252 /* sample_index & 0xF */
6253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6254 alu.op = ALU_OP2_AND_INT;
6255 alu.src[0].sel = src_gpr;
6256 alu.src[0].chan = sample_chan;
6257 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6258 alu.src[1].value = 0xF;
6259 alu.dst.sel = src_gpr;
6260 alu.dst.chan = sample_chan;
6261 alu.dst.write = 1;
6262 alu.last = 1;
6263 r = r600_bytecode_add_alu(ctx->bc, &alu);
6264 if (r)
6265 return r;
6266 #if 0
6267 /* visualize the FMASK */
6268 for (i = 0; i < 4; i++) {
6269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6270 alu.op = ALU_OP1_INT_TO_FLT;
6271 alu.src[0].sel = src_gpr;
6272 alu.src[0].chan = sample_chan;
6273 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6274 alu.dst.chan = i;
6275 alu.dst.write = 1;
6276 alu.last = 1;
6277 r = r600_bytecode_add_alu(ctx->bc, &alu);
6278 if (r)
6279 return r;
6280 }
6281 return 0;
6282 #endif
6283 }
6284
6285 /* does this shader want a num layers from TXQ for a cube array? */
6286 if (has_txq_cube_array_z) {
6287 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6288
6289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6290 alu.op = ALU_OP1_MOV;
6291
6292 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6293 if (ctx->bc->chip_class >= EVERGREEN) {
6294 /* channel 1 or 3 of each word */
6295 alu.src[0].sel += (id / 2);
6296 alu.src[0].chan = ((id % 2) * 2) + 1;
6297 } else {
6298 /* r600 we have them at channel 2 of the second dword */
6299 alu.src[0].sel += (id * 2) + 1;
6300 alu.src[0].chan = 2;
6301 }
6302 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6303 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
6304 alu.last = 1;
6305 r = r600_bytecode_add_alu(ctx->bc, &alu);
6306 if (r)
6307 return r;
6308 /* disable writemask from texture instruction */
6309 inst->Dst[0].Register.WriteMask &= ~4;
6310 }
6311
6312 opcode = ctx->inst_info->op;
6313 if (opcode == FETCH_OP_GATHER4 &&
6314 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
6315 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
6316 opcode = FETCH_OP_GATHER4_O;
6317
6318 /* GATHER4_O/GATHER4_C_O use offset values loaded by
6319 SET_TEXTURE_OFFSETS instruction. The immediate offset values
6320 encoded in the instruction are ignored. */
6321 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6322 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
6323 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6324 tex.sampler_index_mode = sampler_index_mode;
6325 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6326 tex.resource_index_mode = sampler_index_mode;
6327
6328 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
6329 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
6330 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
6331 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
6332 tex.src_sel_w = 4;
6333
6334 tex.dst_sel_x = 7;
6335 tex.dst_sel_y = 7;
6336 tex.dst_sel_z = 7;
6337 tex.dst_sel_w = 7;
6338
6339 r = r600_bytecode_add_tex(ctx->bc, &tex);
6340 if (r)
6341 return r;
6342 }
6343
6344 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6345 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6346 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6347 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6348 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
6349 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6350 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6351 switch (opcode) {
6352 case FETCH_OP_SAMPLE:
6353 opcode = FETCH_OP_SAMPLE_C;
6354 break;
6355 case FETCH_OP_SAMPLE_L:
6356 opcode = FETCH_OP_SAMPLE_C_L;
6357 break;
6358 case FETCH_OP_SAMPLE_LB:
6359 opcode = FETCH_OP_SAMPLE_C_LB;
6360 break;
6361 case FETCH_OP_SAMPLE_G:
6362 opcode = FETCH_OP_SAMPLE_C_G;
6363 break;
6364 /* Texture gather variants */
6365 case FETCH_OP_GATHER4:
6366 opcode = FETCH_OP_GATHER4_C;
6367 break;
6368 case FETCH_OP_GATHER4_O:
6369 opcode = FETCH_OP_GATHER4_C_O;
6370 break;
6371 }
6372 }
6373
6374 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6375 tex.op = opcode;
6376
6377 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6378 tex.sampler_index_mode = sampler_index_mode;
6379 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6380 tex.resource_index_mode = sampler_index_mode;
6381 tex.src_gpr = src_gpr;
6382 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6383
6384 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
6385 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
6386 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
6387 }
6388
6389 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
6390 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
6391 tex.inst_mod = texture_component_select;
6392
6393 if (ctx->bc->chip_class == CAYMAN) {
6394 /* GATHER4 result order is different from TGSI TG4 */
6395 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
6396 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
6397 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
6398 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6399 } else {
6400 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6401 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6402 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6403 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6404 }
6405 }
6406 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
6407 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6408 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6409 tex.dst_sel_z = 7;
6410 tex.dst_sel_w = 7;
6411 }
6412 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
6413 tex.dst_sel_x = 3;
6414 tex.dst_sel_y = 7;
6415 tex.dst_sel_z = 7;
6416 tex.dst_sel_w = 7;
6417 }
6418 else {
6419 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6420 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6421 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6422 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6423 }
6424
6425
6426 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
6427 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
6428 tex.src_sel_x = 4;
6429 tex.src_sel_y = 4;
6430 tex.src_sel_z = 4;
6431 tex.src_sel_w = 4;
6432 } else if (src_loaded) {
6433 tex.src_sel_x = 0;
6434 tex.src_sel_y = 1;
6435 tex.src_sel_z = 2;
6436 tex.src_sel_w = 3;
6437 } else {
6438 tex.src_sel_x = ctx->src[0].swizzle[0];
6439 tex.src_sel_y = ctx->src[0].swizzle[1];
6440 tex.src_sel_z = ctx->src[0].swizzle[2];
6441 tex.src_sel_w = ctx->src[0].swizzle[3];
6442 tex.src_rel = ctx->src[0].rel;
6443 }
6444
6445 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6446 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6447 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6448 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6449 tex.src_sel_x = 1;
6450 tex.src_sel_y = 0;
6451 tex.src_sel_z = 3;
6452 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
6453 }
6454
6455 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
6456 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
6457 tex.coord_type_x = 1;
6458 tex.coord_type_y = 1;
6459 }
6460 tex.coord_type_z = 1;
6461 tex.coord_type_w = 1;
6462
6463 tex.offset_x = offset_x;
6464 tex.offset_y = offset_y;
6465 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
6466 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6467 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
6468 tex.offset_z = 0;
6469 }
6470 else {
6471 tex.offset_z = offset_z;
6472 }
6473
6474 /* Put the depth for comparison in W.
6475 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
6476 * Some instructions expect the depth in Z. */
6477 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6478 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6479 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6480 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
6481 opcode != FETCH_OP_SAMPLE_C_L &&
6482 opcode != FETCH_OP_SAMPLE_C_LB) {
6483 tex.src_sel_w = tex.src_sel_z;
6484 }
6485
6486 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
6487 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
6488 if (opcode == FETCH_OP_SAMPLE_C_L ||
6489 opcode == FETCH_OP_SAMPLE_C_LB) {
6490 /* the array index is read from Y */
6491 tex.coord_type_y = 0;
6492 } else {
6493 /* the array index is read from Z */
6494 tex.coord_type_z = 0;
6495 tex.src_sel_z = tex.src_sel_y;
6496 }
6497 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6498 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6499 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6500 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6501 (ctx->bc->chip_class >= EVERGREEN)))
6502 /* the array index is read from Z */
6503 tex.coord_type_z = 0;
6504
6505 /* mask unused source components */
6506 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
6507 switch (inst->Texture.Texture) {
6508 case TGSI_TEXTURE_2D:
6509 case TGSI_TEXTURE_RECT:
6510 tex.src_sel_z = 7;
6511 tex.src_sel_w = 7;
6512 break;
6513 case TGSI_TEXTURE_1D_ARRAY:
6514 tex.src_sel_y = 7;
6515 tex.src_sel_w = 7;
6516 break;
6517 case TGSI_TEXTURE_1D:
6518 tex.src_sel_y = 7;
6519 tex.src_sel_z = 7;
6520 tex.src_sel_w = 7;
6521 break;
6522 }
6523 }
6524
6525 r = r600_bytecode_add_tex(ctx->bc, &tex);
6526 if (r)
6527 return r;
6528
6529 /* add shadow ambient support - gallium doesn't do it yet */
6530 return 0;
6531 }
6532
6533 static int tgsi_lrp(struct r600_shader_ctx *ctx)
6534 {
6535 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6536 struct r600_bytecode_alu alu;
6537 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6538 unsigned i, temp_regs[2];
6539 int r;
6540
6541 /* optimize if it's just an equal balance */
6542 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
6543 for (i = 0; i < lasti + 1; i++) {
6544 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6545 continue;
6546
6547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6548 alu.op = ALU_OP2_ADD;
6549 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6550 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6551 alu.omod = 3;
6552 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6553 alu.dst.chan = i;
6554 if (i == lasti) {
6555 alu.last = 1;
6556 }
6557 r = r600_bytecode_add_alu(ctx->bc, &alu);
6558 if (r)
6559 return r;
6560 }
6561 return 0;
6562 }
6563
6564 /* 1 - src0 */
6565 for (i = 0; i < lasti + 1; i++) {
6566 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6567 continue;
6568
6569 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6570 alu.op = ALU_OP2_ADD;
6571 alu.src[0].sel = V_SQ_ALU_SRC_1;
6572 alu.src[0].chan = 0;
6573 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6574 r600_bytecode_src_toggle_neg(&alu.src[1]);
6575 alu.dst.sel = ctx->temp_reg;
6576 alu.dst.chan = i;
6577 if (i == lasti) {
6578 alu.last = 1;
6579 }
6580 alu.dst.write = 1;
6581 r = r600_bytecode_add_alu(ctx->bc, &alu);
6582 if (r)
6583 return r;
6584 }
6585
6586 /* (1 - src0) * src2 */
6587 for (i = 0; i < lasti + 1; i++) {
6588 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6589 continue;
6590
6591 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6592 alu.op = ALU_OP2_MUL;
6593 alu.src[0].sel = ctx->temp_reg;
6594 alu.src[0].chan = i;
6595 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6596 alu.dst.sel = ctx->temp_reg;
6597 alu.dst.chan = i;
6598 if (i == lasti) {
6599 alu.last = 1;
6600 }
6601 alu.dst.write = 1;
6602 r = r600_bytecode_add_alu(ctx->bc, &alu);
6603 if (r)
6604 return r;
6605 }
6606
6607 /* src0 * src1 + (1 - src0) * src2 */
6608 if (ctx->src[0].abs)
6609 temp_regs[0] = r600_get_temp(ctx);
6610 else
6611 temp_regs[0] = 0;
6612 if (ctx->src[1].abs)
6613 temp_regs[1] = r600_get_temp(ctx);
6614 else
6615 temp_regs[1] = 0;
6616
6617 for (i = 0; i < lasti + 1; i++) {
6618 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6619 continue;
6620
6621 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6622 alu.op = ALU_OP3_MULADD;
6623 alu.is_op3 = 1;
6624 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6625 if (r)
6626 return r;
6627 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
6628 if (r)
6629 return r;
6630 alu.src[2].sel = ctx->temp_reg;
6631 alu.src[2].chan = i;
6632
6633 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6634 alu.dst.chan = i;
6635 if (i == lasti) {
6636 alu.last = 1;
6637 }
6638 r = r600_bytecode_add_alu(ctx->bc, &alu);
6639 if (r)
6640 return r;
6641 }
6642 return 0;
6643 }
6644
6645 static int tgsi_cmp(struct r600_shader_ctx *ctx)
6646 {
6647 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6648 struct r600_bytecode_alu alu;
6649 int i, r, j;
6650 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6651 int temp_regs[3];
6652
6653 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6654 temp_regs[j] = 0;
6655 if (ctx->src[j].abs)
6656 temp_regs[j] = r600_get_temp(ctx);
6657 }
6658
6659 for (i = 0; i < lasti + 1; i++) {
6660 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6661 continue;
6662
6663 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6664 alu.op = ALU_OP3_CNDGE;
6665 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6666 if (r)
6667 return r;
6668 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
6669 if (r)
6670 return r;
6671 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
6672 if (r)
6673 return r;
6674 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6675 alu.dst.chan = i;
6676 alu.dst.write = 1;
6677 alu.is_op3 = 1;
6678 if (i == lasti)
6679 alu.last = 1;
6680 r = r600_bytecode_add_alu(ctx->bc, &alu);
6681 if (r)
6682 return r;
6683 }
6684 return 0;
6685 }
6686
6687 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
6688 {
6689 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6690 struct r600_bytecode_alu alu;
6691 int i, r;
6692 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6693
6694 for (i = 0; i < lasti + 1; i++) {
6695 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6696 continue;
6697
6698 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6699 alu.op = ALU_OP3_CNDE_INT;
6700 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6701 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6702 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6703 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6704 alu.dst.chan = i;
6705 alu.dst.write = 1;
6706 alu.is_op3 = 1;
6707 if (i == lasti)
6708 alu.last = 1;
6709 r = r600_bytecode_add_alu(ctx->bc, &alu);
6710 if (r)
6711 return r;
6712 }
6713 return 0;
6714 }
6715
6716 static int tgsi_xpd(struct r600_shader_ctx *ctx)
6717 {
6718 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6719 static const unsigned int src0_swizzle[] = {2, 0, 1};
6720 static const unsigned int src1_swizzle[] = {1, 2, 0};
6721 struct r600_bytecode_alu alu;
6722 uint32_t use_temp = 0;
6723 int i, r;
6724
6725 if (inst->Dst[0].Register.WriteMask != 0xf)
6726 use_temp = 1;
6727
6728 for (i = 0; i < 4; i++) {
6729 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6730 alu.op = ALU_OP2_MUL;
6731 if (i < 3) {
6732 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6733 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
6734 } else {
6735 alu.src[0].sel = V_SQ_ALU_SRC_0;
6736 alu.src[0].chan = i;
6737 alu.src[1].sel = V_SQ_ALU_SRC_0;
6738 alu.src[1].chan = i;
6739 }
6740
6741 alu.dst.sel = ctx->temp_reg;
6742 alu.dst.chan = i;
6743 alu.dst.write = 1;
6744
6745 if (i == 3)
6746 alu.last = 1;
6747 r = r600_bytecode_add_alu(ctx->bc, &alu);
6748 if (r)
6749 return r;
6750 }
6751
6752 for (i = 0; i < 4; i++) {
6753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6754 alu.op = ALU_OP3_MULADD;
6755
6756 if (i < 3) {
6757 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
6758 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
6759 } else {
6760 alu.src[0].sel = V_SQ_ALU_SRC_0;
6761 alu.src[0].chan = i;
6762 alu.src[1].sel = V_SQ_ALU_SRC_0;
6763 alu.src[1].chan = i;
6764 }
6765
6766 alu.src[2].sel = ctx->temp_reg;
6767 alu.src[2].neg = 1;
6768 alu.src[2].chan = i;
6769
6770 if (use_temp)
6771 alu.dst.sel = ctx->temp_reg;
6772 else
6773 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6774 alu.dst.chan = i;
6775 alu.dst.write = 1;
6776 alu.is_op3 = 1;
6777 if (i == 3)
6778 alu.last = 1;
6779 r = r600_bytecode_add_alu(ctx->bc, &alu);
6780 if (r)
6781 return r;
6782 }
6783 if (use_temp)
6784 return tgsi_helper_copy(ctx, inst);
6785 return 0;
6786 }
6787
6788 static int tgsi_exp(struct r600_shader_ctx *ctx)
6789 {
6790 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6791 struct r600_bytecode_alu alu;
6792 int r;
6793 int i;
6794
6795 /* result.x = 2^floor(src); */
6796 if (inst->Dst[0].Register.WriteMask & 1) {
6797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6798
6799 alu.op = ALU_OP1_FLOOR;
6800 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6801
6802 alu.dst.sel = ctx->temp_reg;
6803 alu.dst.chan = 0;
6804 alu.dst.write = 1;
6805 alu.last = 1;
6806 r = r600_bytecode_add_alu(ctx->bc, &alu);
6807 if (r)
6808 return r;
6809
6810 if (ctx->bc->chip_class == CAYMAN) {
6811 for (i = 0; i < 3; i++) {
6812 alu.op = ALU_OP1_EXP_IEEE;
6813 alu.src[0].sel = ctx->temp_reg;
6814 alu.src[0].chan = 0;
6815
6816 alu.dst.sel = ctx->temp_reg;
6817 alu.dst.chan = i;
6818 alu.dst.write = i == 0;
6819 alu.last = i == 2;
6820 r = r600_bytecode_add_alu(ctx->bc, &alu);
6821 if (r)
6822 return r;
6823 }
6824 } else {
6825 alu.op = ALU_OP1_EXP_IEEE;
6826 alu.src[0].sel = ctx->temp_reg;
6827 alu.src[0].chan = 0;
6828
6829 alu.dst.sel = ctx->temp_reg;
6830 alu.dst.chan = 0;
6831 alu.dst.write = 1;
6832 alu.last = 1;
6833 r = r600_bytecode_add_alu(ctx->bc, &alu);
6834 if (r)
6835 return r;
6836 }
6837 }
6838
6839 /* result.y = tmp - floor(tmp); */
6840 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
6841 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6842
6843 alu.op = ALU_OP1_FRACT;
6844 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6845
6846 alu.dst.sel = ctx->temp_reg;
6847 #if 0
6848 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6849 if (r)
6850 return r;
6851 #endif
6852 alu.dst.write = 1;
6853 alu.dst.chan = 1;
6854
6855 alu.last = 1;
6856
6857 r = r600_bytecode_add_alu(ctx->bc, &alu);
6858 if (r)
6859 return r;
6860 }
6861
6862 /* result.z = RoughApprox2ToX(tmp);*/
6863 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
6864 if (ctx->bc->chip_class == CAYMAN) {
6865 for (i = 0; i < 3; i++) {
6866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6867 alu.op = ALU_OP1_EXP_IEEE;
6868 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6869
6870 alu.dst.sel = ctx->temp_reg;
6871 alu.dst.chan = i;
6872 if (i == 2) {
6873 alu.dst.write = 1;
6874 alu.last = 1;
6875 }
6876
6877 r = r600_bytecode_add_alu(ctx->bc, &alu);
6878 if (r)
6879 return r;
6880 }
6881 } else {
6882 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6883 alu.op = ALU_OP1_EXP_IEEE;
6884 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6885
6886 alu.dst.sel = ctx->temp_reg;
6887 alu.dst.write = 1;
6888 alu.dst.chan = 2;
6889
6890 alu.last = 1;
6891
6892 r = r600_bytecode_add_alu(ctx->bc, &alu);
6893 if (r)
6894 return r;
6895 }
6896 }
6897
6898 /* result.w = 1.0;*/
6899 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
6900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6901
6902 alu.op = ALU_OP1_MOV;
6903 alu.src[0].sel = V_SQ_ALU_SRC_1;
6904 alu.src[0].chan = 0;
6905
6906 alu.dst.sel = ctx->temp_reg;
6907 alu.dst.chan = 3;
6908 alu.dst.write = 1;
6909 alu.last = 1;
6910 r = r600_bytecode_add_alu(ctx->bc, &alu);
6911 if (r)
6912 return r;
6913 }
6914 return tgsi_helper_copy(ctx, inst);
6915 }
6916
6917 static int tgsi_log(struct r600_shader_ctx *ctx)
6918 {
6919 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6920 struct r600_bytecode_alu alu;
6921 int r;
6922 int i;
6923
6924 /* result.x = floor(log2(|src|)); */
6925 if (inst->Dst[0].Register.WriteMask & 1) {
6926 if (ctx->bc->chip_class == CAYMAN) {
6927 for (i = 0; i < 3; i++) {
6928 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6929
6930 alu.op = ALU_OP1_LOG_IEEE;
6931 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6932 r600_bytecode_src_set_abs(&alu.src[0]);
6933
6934 alu.dst.sel = ctx->temp_reg;
6935 alu.dst.chan = i;
6936 if (i == 0)
6937 alu.dst.write = 1;
6938 if (i == 2)
6939 alu.last = 1;
6940 r = r600_bytecode_add_alu(ctx->bc, &alu);
6941 if (r)
6942 return r;
6943 }
6944
6945 } else {
6946 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6947
6948 alu.op = ALU_OP1_LOG_IEEE;
6949 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6950 r600_bytecode_src_set_abs(&alu.src[0]);
6951
6952 alu.dst.sel = ctx->temp_reg;
6953 alu.dst.chan = 0;
6954 alu.dst.write = 1;
6955 alu.last = 1;
6956 r = r600_bytecode_add_alu(ctx->bc, &alu);
6957 if (r)
6958 return r;
6959 }
6960
6961 alu.op = ALU_OP1_FLOOR;
6962 alu.src[0].sel = ctx->temp_reg;
6963 alu.src[0].chan = 0;
6964
6965 alu.dst.sel = ctx->temp_reg;
6966 alu.dst.chan = 0;
6967 alu.dst.write = 1;
6968 alu.last = 1;
6969
6970 r = r600_bytecode_add_alu(ctx->bc, &alu);
6971 if (r)
6972 return r;
6973 }
6974
6975 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
6976 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
6977
6978 if (ctx->bc->chip_class == CAYMAN) {
6979 for (i = 0; i < 3; i++) {
6980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6981
6982 alu.op = ALU_OP1_LOG_IEEE;
6983 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6984 r600_bytecode_src_set_abs(&alu.src[0]);
6985
6986 alu.dst.sel = ctx->temp_reg;
6987 alu.dst.chan = i;
6988 if (i == 1)
6989 alu.dst.write = 1;
6990 if (i == 2)
6991 alu.last = 1;
6992
6993 r = r600_bytecode_add_alu(ctx->bc, &alu);
6994 if (r)
6995 return r;
6996 }
6997 } else {
6998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6999
7000 alu.op = ALU_OP1_LOG_IEEE;
7001 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7002 r600_bytecode_src_set_abs(&alu.src[0]);
7003
7004 alu.dst.sel = ctx->temp_reg;
7005 alu.dst.chan = 1;
7006 alu.dst.write = 1;
7007 alu.last = 1;
7008
7009 r = r600_bytecode_add_alu(ctx->bc, &alu);
7010 if (r)
7011 return r;
7012 }
7013
7014 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7015
7016 alu.op = ALU_OP1_FLOOR;
7017 alu.src[0].sel = ctx->temp_reg;
7018 alu.src[0].chan = 1;
7019
7020 alu.dst.sel = ctx->temp_reg;
7021 alu.dst.chan = 1;
7022 alu.dst.write = 1;
7023 alu.last = 1;
7024
7025 r = r600_bytecode_add_alu(ctx->bc, &alu);
7026 if (r)
7027 return r;
7028
7029 if (ctx->bc->chip_class == CAYMAN) {
7030 for (i = 0; i < 3; i++) {
7031 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7032 alu.op = ALU_OP1_EXP_IEEE;
7033 alu.src[0].sel = ctx->temp_reg;
7034 alu.src[0].chan = 1;
7035
7036 alu.dst.sel = ctx->temp_reg;
7037 alu.dst.chan = i;
7038 if (i == 1)
7039 alu.dst.write = 1;
7040 if (i == 2)
7041 alu.last = 1;
7042
7043 r = r600_bytecode_add_alu(ctx->bc, &alu);
7044 if (r)
7045 return r;
7046 }
7047 } else {
7048 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7049 alu.op = ALU_OP1_EXP_IEEE;
7050 alu.src[0].sel = ctx->temp_reg;
7051 alu.src[0].chan = 1;
7052
7053 alu.dst.sel = ctx->temp_reg;
7054 alu.dst.chan = 1;
7055 alu.dst.write = 1;
7056 alu.last = 1;
7057
7058 r = r600_bytecode_add_alu(ctx->bc, &alu);
7059 if (r)
7060 return r;
7061 }
7062
7063 if (ctx->bc->chip_class == CAYMAN) {
7064 for (i = 0; i < 3; i++) {
7065 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7066 alu.op = ALU_OP1_RECIP_IEEE;
7067 alu.src[0].sel = ctx->temp_reg;
7068 alu.src[0].chan = 1;
7069
7070 alu.dst.sel = ctx->temp_reg;
7071 alu.dst.chan = i;
7072 if (i == 1)
7073 alu.dst.write = 1;
7074 if (i == 2)
7075 alu.last = 1;
7076
7077 r = r600_bytecode_add_alu(ctx->bc, &alu);
7078 if (r)
7079 return r;
7080 }
7081 } else {
7082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7083 alu.op = ALU_OP1_RECIP_IEEE;
7084 alu.src[0].sel = ctx->temp_reg;
7085 alu.src[0].chan = 1;
7086
7087 alu.dst.sel = ctx->temp_reg;
7088 alu.dst.chan = 1;
7089 alu.dst.write = 1;
7090 alu.last = 1;
7091
7092 r = r600_bytecode_add_alu(ctx->bc, &alu);
7093 if (r)
7094 return r;
7095 }
7096
7097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7098
7099 alu.op = ALU_OP2_MUL;
7100
7101 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7102 r600_bytecode_src_set_abs(&alu.src[0]);
7103
7104 alu.src[1].sel = ctx->temp_reg;
7105 alu.src[1].chan = 1;
7106
7107 alu.dst.sel = ctx->temp_reg;
7108 alu.dst.chan = 1;
7109 alu.dst.write = 1;
7110 alu.last = 1;
7111
7112 r = r600_bytecode_add_alu(ctx->bc, &alu);
7113 if (r)
7114 return r;
7115 }
7116
7117 /* result.z = log2(|src|);*/
7118 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
7119 if (ctx->bc->chip_class == CAYMAN) {
7120 for (i = 0; i < 3; i++) {
7121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7122
7123 alu.op = ALU_OP1_LOG_IEEE;
7124 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7125 r600_bytecode_src_set_abs(&alu.src[0]);
7126
7127 alu.dst.sel = ctx->temp_reg;
7128 if (i == 2)
7129 alu.dst.write = 1;
7130 alu.dst.chan = i;
7131 if (i == 2)
7132 alu.last = 1;
7133
7134 r = r600_bytecode_add_alu(ctx->bc, &alu);
7135 if (r)
7136 return r;
7137 }
7138 } else {
7139 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7140
7141 alu.op = ALU_OP1_LOG_IEEE;
7142 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7143 r600_bytecode_src_set_abs(&alu.src[0]);
7144
7145 alu.dst.sel = ctx->temp_reg;
7146 alu.dst.write = 1;
7147 alu.dst.chan = 2;
7148 alu.last = 1;
7149
7150 r = r600_bytecode_add_alu(ctx->bc, &alu);
7151 if (r)
7152 return r;
7153 }
7154 }
7155
7156 /* result.w = 1.0; */
7157 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
7158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7159
7160 alu.op = ALU_OP1_MOV;
7161 alu.src[0].sel = V_SQ_ALU_SRC_1;
7162 alu.src[0].chan = 0;
7163
7164 alu.dst.sel = ctx->temp_reg;
7165 alu.dst.chan = 3;
7166 alu.dst.write = 1;
7167 alu.last = 1;
7168
7169 r = r600_bytecode_add_alu(ctx->bc, &alu);
7170 if (r)
7171 return r;
7172 }
7173
7174 return tgsi_helper_copy(ctx, inst);
7175 }
7176
7177 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
7178 {
7179 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7180 struct r600_bytecode_alu alu;
7181 int r;
7182 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7183 unsigned reg = inst->Dst[0].Register.Index > 0 ? ctx->bc->index_reg[inst->Dst[0].Register.Index - 1] : ctx->bc->ar_reg;
7184
7185 assert(inst->Dst[0].Register.Index < 3);
7186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7187
7188 switch (inst->Instruction.Opcode) {
7189 case TGSI_OPCODE_ARL:
7190 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
7191 break;
7192 case TGSI_OPCODE_ARR:
7193 alu.op = ALU_OP1_FLT_TO_INT;
7194 break;
7195 case TGSI_OPCODE_UARL:
7196 alu.op = ALU_OP1_MOV;
7197 break;
7198 default:
7199 assert(0);
7200 return -1;
7201 }
7202
7203 for (i = 0; i <= lasti; ++i) {
7204 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7205 continue;
7206 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7207 alu.last = i == lasti;
7208 alu.dst.sel = reg;
7209 alu.dst.chan = i;
7210 alu.dst.write = 1;
7211 r = r600_bytecode_add_alu(ctx->bc, &alu);
7212 if (r)
7213 return r;
7214 }
7215
7216 if (inst->Dst[0].Register.Index > 0)
7217 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
7218 else
7219 ctx->bc->ar_loaded = 0;
7220
7221 return 0;
7222 }
7223 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
7224 {
7225 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7226 struct r600_bytecode_alu alu;
7227 int r;
7228 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7229
7230 switch (inst->Instruction.Opcode) {
7231 case TGSI_OPCODE_ARL:
7232 memset(&alu, 0, sizeof(alu));
7233 alu.op = ALU_OP1_FLOOR;
7234 alu.dst.sel = ctx->bc->ar_reg;
7235 alu.dst.write = 1;
7236 for (i = 0; i <= lasti; ++i) {
7237 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7238 alu.dst.chan = i;
7239 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7240 alu.last = i == lasti;
7241 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7242 return r;
7243 }
7244 }
7245
7246 memset(&alu, 0, sizeof(alu));
7247 alu.op = ALU_OP1_FLT_TO_INT;
7248 alu.src[0].sel = ctx->bc->ar_reg;
7249 alu.dst.sel = ctx->bc->ar_reg;
7250 alu.dst.write = 1;
7251 /* FLT_TO_INT is trans-only on r600/r700 */
7252 alu.last = TRUE;
7253 for (i = 0; i <= lasti; ++i) {
7254 alu.dst.chan = i;
7255 alu.src[0].chan = i;
7256 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7257 return r;
7258 }
7259 break;
7260 case TGSI_OPCODE_ARR:
7261 memset(&alu, 0, sizeof(alu));
7262 alu.op = ALU_OP1_FLT_TO_INT;
7263 alu.dst.sel = ctx->bc->ar_reg;
7264 alu.dst.write = 1;
7265 /* FLT_TO_INT is trans-only on r600/r700 */
7266 alu.last = TRUE;
7267 for (i = 0; i <= lasti; ++i) {
7268 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7269 alu.dst.chan = i;
7270 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7271 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7272 return r;
7273 }
7274 }
7275 break;
7276 case TGSI_OPCODE_UARL:
7277 memset(&alu, 0, sizeof(alu));
7278 alu.op = ALU_OP1_MOV;
7279 alu.dst.sel = ctx->bc->ar_reg;
7280 alu.dst.write = 1;
7281 for (i = 0; i <= lasti; ++i) {
7282 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7283 alu.dst.chan = i;
7284 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7285 alu.last = i == lasti;
7286 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7287 return r;
7288 }
7289 }
7290 break;
7291 default:
7292 assert(0);
7293 return -1;
7294 }
7295
7296 ctx->bc->ar_loaded = 0;
7297 return 0;
7298 }
7299
7300 static int tgsi_opdst(struct r600_shader_ctx *ctx)
7301 {
7302 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7303 struct r600_bytecode_alu alu;
7304 int i, r = 0;
7305
7306 for (i = 0; i < 4; i++) {
7307 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7308
7309 alu.op = ALU_OP2_MUL;
7310 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7311
7312 if (i == 0 || i == 3) {
7313 alu.src[0].sel = V_SQ_ALU_SRC_1;
7314 } else {
7315 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7316 }
7317
7318 if (i == 0 || i == 2) {
7319 alu.src[1].sel = V_SQ_ALU_SRC_1;
7320 } else {
7321 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
7322 }
7323 if (i == 3)
7324 alu.last = 1;
7325 r = r600_bytecode_add_alu(ctx->bc, &alu);
7326 if (r)
7327 return r;
7328 }
7329 return 0;
7330 }
7331
7332 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
7333 {
7334 struct r600_bytecode_alu alu;
7335 int r;
7336
7337 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7338 alu.op = opcode;
7339 alu.execute_mask = 1;
7340 alu.update_pred = 1;
7341
7342 alu.dst.sel = ctx->temp_reg;
7343 alu.dst.write = 1;
7344 alu.dst.chan = 0;
7345
7346 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7347 alu.src[1].sel = V_SQ_ALU_SRC_0;
7348 alu.src[1].chan = 0;
7349
7350 alu.last = 1;
7351
7352 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
7353 if (r)
7354 return r;
7355 return 0;
7356 }
7357
7358 static int pops(struct r600_shader_ctx *ctx, int pops)
7359 {
7360 unsigned force_pop = ctx->bc->force_add_cf;
7361
7362 if (!force_pop) {
7363 int alu_pop = 3;
7364 if (ctx->bc->cf_last) {
7365 if (ctx->bc->cf_last->op == CF_OP_ALU)
7366 alu_pop = 0;
7367 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
7368 alu_pop = 1;
7369 }
7370 alu_pop += pops;
7371 if (alu_pop == 1) {
7372 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
7373 ctx->bc->force_add_cf = 1;
7374 } else if (alu_pop == 2) {
7375 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
7376 ctx->bc->force_add_cf = 1;
7377 } else {
7378 force_pop = 1;
7379 }
7380 }
7381
7382 if (force_pop) {
7383 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
7384 ctx->bc->cf_last->pop_count = pops;
7385 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7386 }
7387
7388 return 0;
7389 }
7390
7391 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
7392 unsigned reason)
7393 {
7394 struct r600_stack_info *stack = &ctx->bc->stack;
7395 unsigned elements, entries;
7396
7397 unsigned entry_size = stack->entry_size;
7398
7399 elements = (stack->loop + stack->push_wqm ) * entry_size;
7400 elements += stack->push;
7401
7402 switch (ctx->bc->chip_class) {
7403 case R600:
7404 case R700:
7405 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
7406 * the stack must be reserved to hold the current active/continue
7407 * masks */
7408 if (reason == FC_PUSH_VPM) {
7409 elements += 2;
7410 }
7411 break;
7412
7413 case CAYMAN:
7414 /* r9xx: any stack operation on empty stack consumes 2 additional
7415 * elements */
7416 elements += 2;
7417
7418 /* fallthrough */
7419 /* FIXME: do the two elements added above cover the cases for the
7420 * r8xx+ below? */
7421
7422 case EVERGREEN:
7423 /* r8xx+: 2 extra elements are not always required, but one extra
7424 * element must be added for each of the following cases:
7425 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
7426 * stack usage.
7427 * (Currently we don't use ALU_ELSE_AFTER.)
7428 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
7429 * PUSH instruction executed.
7430 *
7431 * NOTE: it seems we also need to reserve additional element in some
7432 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
7433 * then STACK_SIZE should be 2 instead of 1 */
7434 if (reason == FC_PUSH_VPM) {
7435 elements += 1;
7436 }
7437 break;
7438
7439 default:
7440 assert(0);
7441 break;
7442 }
7443
7444 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
7445 * for all chips, so we use 4 in the final formula, not the real entry_size
7446 * for the chip */
7447 entry_size = 4;
7448
7449 entries = (elements + (entry_size - 1)) / entry_size;
7450
7451 if (entries > stack->max_entries)
7452 stack->max_entries = entries;
7453 }
7454
7455 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
7456 {
7457 switch(reason) {
7458 case FC_PUSH_VPM:
7459 --ctx->bc->stack.push;
7460 assert(ctx->bc->stack.push >= 0);
7461 break;
7462 case FC_PUSH_WQM:
7463 --ctx->bc->stack.push_wqm;
7464 assert(ctx->bc->stack.push_wqm >= 0);
7465 break;
7466 case FC_LOOP:
7467 --ctx->bc->stack.loop;
7468 assert(ctx->bc->stack.loop >= 0);
7469 break;
7470 default:
7471 assert(0);
7472 break;
7473 }
7474 }
7475
7476 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
7477 {
7478 switch (reason) {
7479 case FC_PUSH_VPM:
7480 ++ctx->bc->stack.push;
7481 break;
7482 case FC_PUSH_WQM:
7483 ++ctx->bc->stack.push_wqm;
7484 case FC_LOOP:
7485 ++ctx->bc->stack.loop;
7486 break;
7487 default:
7488 assert(0);
7489 }
7490
7491 callstack_update_max_depth(ctx, reason);
7492 }
7493
7494 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
7495 {
7496 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
7497
7498 sp->mid = realloc((void *)sp->mid,
7499 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
7500 sp->mid[sp->num_mid] = ctx->bc->cf_last;
7501 sp->num_mid++;
7502 }
7503
7504 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
7505 {
7506 ctx->bc->fc_sp++;
7507 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
7508 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
7509 }
7510
7511 static void fc_poplevel(struct r600_shader_ctx *ctx)
7512 {
7513 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
7514 free(sp->mid);
7515 sp->mid = NULL;
7516 sp->num_mid = 0;
7517 sp->start = NULL;
7518 sp->type = 0;
7519 ctx->bc->fc_sp--;
7520 }
7521
7522 #if 0
7523 static int emit_return(struct r600_shader_ctx *ctx)
7524 {
7525 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
7526 return 0;
7527 }
7528
7529 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
7530 {
7531
7532 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
7533 ctx->bc->cf_last->pop_count = pops;
7534 /* XXX work out offset */
7535 return 0;
7536 }
7537
7538 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
7539 {
7540 return 0;
7541 }
7542
7543 static void emit_testflag(struct r600_shader_ctx *ctx)
7544 {
7545
7546 }
7547
7548 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
7549 {
7550 emit_testflag(ctx);
7551 emit_jump_to_offset(ctx, 1, 4);
7552 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
7553 pops(ctx, ifidx + 1);
7554 emit_return(ctx);
7555 }
7556
7557 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
7558 {
7559 emit_testflag(ctx);
7560
7561 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7562 ctx->bc->cf_last->pop_count = 1;
7563
7564 fc_set_mid(ctx, fc_sp);
7565
7566 pops(ctx, 1);
7567 }
7568 #endif
7569
7570 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
7571 {
7572 int alu_type = CF_OP_ALU_PUSH_BEFORE;
7573
7574 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
7575 * LOOP_STARTxxx for nested loops may put the branch stack into a state
7576 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
7577 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
7578 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
7579 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
7580 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7581 alu_type = CF_OP_ALU;
7582 }
7583
7584 emit_logic_pred(ctx, opcode, alu_type);
7585
7586 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
7587
7588 fc_pushlevel(ctx, FC_IF);
7589
7590 callstack_push(ctx, FC_PUSH_VPM);
7591 return 0;
7592 }
7593
7594 static int tgsi_if(struct r600_shader_ctx *ctx)
7595 {
7596 return emit_if(ctx, ALU_OP2_PRED_SETNE);
7597 }
7598
7599 static int tgsi_uif(struct r600_shader_ctx *ctx)
7600 {
7601 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
7602 }
7603
7604 static int tgsi_else(struct r600_shader_ctx *ctx)
7605 {
7606 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
7607 ctx->bc->cf_last->pop_count = 1;
7608
7609 fc_set_mid(ctx, ctx->bc->fc_sp);
7610 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
7611 return 0;
7612 }
7613
7614 static int tgsi_endif(struct r600_shader_ctx *ctx)
7615 {
7616 pops(ctx, 1);
7617 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
7618 R600_ERR("if/endif unbalanced in shader\n");
7619 return -1;
7620 }
7621
7622 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
7623 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7624 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
7625 } else {
7626 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
7627 }
7628 fc_poplevel(ctx);
7629
7630 callstack_pop(ctx, FC_PUSH_VPM);
7631 return 0;
7632 }
7633
7634 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
7635 {
7636 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
7637 * limited to 4096 iterations, like the other LOOP_* instructions. */
7638 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
7639
7640 fc_pushlevel(ctx, FC_LOOP);
7641
7642 /* check stack depth */
7643 callstack_push(ctx, FC_LOOP);
7644 return 0;
7645 }
7646
7647 static int tgsi_endloop(struct r600_shader_ctx *ctx)
7648 {
7649 int i;
7650
7651 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
7652
7653 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
7654 R600_ERR("loop/endloop in shader code are not paired.\n");
7655 return -EINVAL;
7656 }
7657
7658 /* fixup loop pointers - from r600isa
7659 LOOP END points to CF after LOOP START,
7660 LOOP START point to CF after LOOP END
7661 BRK/CONT point to LOOP END CF
7662 */
7663 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
7664
7665 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7666
7667 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
7668 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
7669 }
7670 /* XXX add LOOPRET support */
7671 fc_poplevel(ctx);
7672 callstack_pop(ctx, FC_LOOP);
7673 return 0;
7674 }
7675
7676 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
7677 {
7678 int r;
7679 unsigned int fscp;
7680
7681 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7682 {
7683 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7684 break;
7685 }
7686 if (fscp == 0) {
7687 R600_ERR("BREAKC not inside loop/endloop pair\n");
7688 return -EINVAL;
7689 }
7690
7691 if (ctx->bc->chip_class == EVERGREEN &&
7692 ctx->bc->family != CHIP_CYPRESS &&
7693 ctx->bc->family != CHIP_JUNIPER) {
7694 /* HW bug: ALU_BREAK does not save the active mask correctly */
7695 r = tgsi_uif(ctx);
7696 if (r)
7697 return r;
7698
7699 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
7700 if (r)
7701 return r;
7702 fc_set_mid(ctx, fscp);
7703
7704 return tgsi_endif(ctx);
7705 } else {
7706 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
7707 if (r)
7708 return r;
7709 fc_set_mid(ctx, fscp);
7710 }
7711
7712 return 0;
7713 }
7714
7715 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
7716 {
7717 unsigned int fscp;
7718
7719 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7720 {
7721 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7722 break;
7723 }
7724
7725 if (fscp == 0) {
7726 R600_ERR("Break not inside loop/endloop pair\n");
7727 return -EINVAL;
7728 }
7729
7730 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7731
7732 fc_set_mid(ctx, fscp);
7733
7734 return 0;
7735 }
7736
7737 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
7738 {
7739 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7740 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
7741 int r;
7742
7743 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
7744 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
7745
7746 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7747 if (!r)
7748 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
7749 return r;
7750 }
7751
7752 static int tgsi_umad(struct r600_shader_ctx *ctx)
7753 {
7754 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7755 struct r600_bytecode_alu alu;
7756 int i, j, k, r;
7757 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7758
7759 /* src0 * src1 */
7760 for (i = 0; i < lasti + 1; i++) {
7761 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7762 continue;
7763
7764 if (ctx->bc->chip_class == CAYMAN) {
7765 for (j = 0 ; j < 4; j++) {
7766 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7767
7768 alu.op = ALU_OP2_MULLO_UINT;
7769 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
7770 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
7771 }
7772 alu.dst.chan = j;
7773 alu.dst.sel = ctx->temp_reg;
7774 alu.dst.write = (j == i);
7775 if (j == 3)
7776 alu.last = 1;
7777 r = r600_bytecode_add_alu(ctx->bc, &alu);
7778 if (r)
7779 return r;
7780 }
7781 } else {
7782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7783
7784 alu.dst.chan = i;
7785 alu.dst.sel = ctx->temp_reg;
7786 alu.dst.write = 1;
7787
7788 alu.op = ALU_OP2_MULLO_UINT;
7789 for (j = 0; j < 2; j++) {
7790 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
7791 }
7792
7793 alu.last = 1;
7794 r = r600_bytecode_add_alu(ctx->bc, &alu);
7795 if (r)
7796 return r;
7797 }
7798 }
7799
7800
7801 for (i = 0; i < lasti + 1; i++) {
7802 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7803 continue;
7804
7805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7806 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7807
7808 alu.op = ALU_OP2_ADD_INT;
7809
7810 alu.src[0].sel = ctx->temp_reg;
7811 alu.src[0].chan = i;
7812
7813 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7814 if (i == lasti) {
7815 alu.last = 1;
7816 }
7817 r = r600_bytecode_add_alu(ctx->bc, &alu);
7818 if (r)
7819 return r;
7820 }
7821 return 0;
7822 }
7823
7824 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
7825 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
7826 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
7827 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
7828
7829 /* XXX:
7830 * For state trackers other than OpenGL, we'll want to use
7831 * _RECIP_IEEE instead.
7832 */
7833 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
7834
7835 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
7836 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
7837 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
7838 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
7839 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
7840 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
7841 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
7842 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
7843 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
7844 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
7845 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
7846 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
7847 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
7848 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
7849 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
7850 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
7851 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
7852 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
7853 [22] = { ALU_OP0_NOP, tgsi_unsupported},
7854 [23] = { ALU_OP0_NOP, tgsi_unsupported},
7855 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
7856 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
7857 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
7858 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
7859 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
7860 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
7861 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
7862 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
7863 [32] = { ALU_OP0_NOP, tgsi_unsupported},
7864 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
7865 [34] = { ALU_OP0_NOP, tgsi_unsupported},
7866 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
7867 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
7868 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7869 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7870 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
7871 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
7872 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
7873 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
7874 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7875 [44] = { ALU_OP0_NOP, tgsi_unsupported},
7876 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
7877 [46] = { ALU_OP0_NOP, tgsi_unsupported},
7878 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
7879 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
7880 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
7881 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
7882 [51] = { ALU_OP0_NOP, tgsi_unsupported},
7883 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
7884 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
7885 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
7886 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
7887 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
7888 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
7889 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7890 [59] = { ALU_OP0_NOP, tgsi_unsupported},
7891 [60] = { ALU_OP0_NOP, tgsi_unsupported},
7892 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
7893 [62] = { ALU_OP0_NOP, tgsi_unsupported},
7894 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
7895 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
7896 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
7897 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
7898 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
7899 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7900 [69] = { ALU_OP0_NOP, tgsi_unsupported},
7901 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
7902 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
7903 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7904 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
7905 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
7906 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
7907 [76] = { ALU_OP0_NOP, tgsi_unsupported},
7908 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
7909 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
7910 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
7911 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
7912 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
7913 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
7914 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
7915 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
7916 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
7917 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
7918 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
7919 [88] = { ALU_OP0_NOP, tgsi_unsupported},
7920 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
7921 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
7922 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
7923 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
7924 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
7925 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
7926 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7927 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
7928 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
7929 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
7930 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
7931 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7932 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
7933 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7934 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7935 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
7936 [105] = { ALU_OP0_NOP, tgsi_unsupported},
7937 [106] = { ALU_OP0_NOP, tgsi_unsupported},
7938 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
7939 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
7940 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
7941 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
7942 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
7943 [112] = { ALU_OP0_NOP, tgsi_unsupported},
7944 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
7945 [114] = { ALU_OP0_NOP, tgsi_unsupported},
7946 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
7947 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
7948 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
7949 [118] = { ALU_OP0_NOP, tgsi_unsupported},
7950 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
7951 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
7952 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
7953 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
7954 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
7955 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
7956 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
7957 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
7958 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
7959 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
7960 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
7961 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
7962 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
7963 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
7964 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
7965 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
7966 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
7967 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
7968 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
7969 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
7970 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
7971 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
7972 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7973 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
7974 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
7975 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7976 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
7977 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
7978 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
7979 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
7980 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
7981 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
7982 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
7983 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
7984 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
7985 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
7986 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
7987 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
7988 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
7989 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
7990 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
7991 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
7992 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
7993 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
7994 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7995 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7996 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7997 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
7998 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
7999 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8000 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8001 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8002 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8003 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8004 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8005 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8006 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8007 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8008 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8009 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8010 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8011 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
8012 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
8013 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
8014 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
8015 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
8016 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
8017 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
8018 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
8019 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
8020 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
8021 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
8022 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
8023 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
8024 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
8025 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
8026 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8027 };
8028
8029 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
8030 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
8031 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8032 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8033 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
8034 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
8035 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8036 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8037 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8038 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8039 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8040 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8041 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8042 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8043 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8044 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8045 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8046 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8047 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8048 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8049 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8050 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
8051 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8052 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8053 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8054 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8055 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8056 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8057 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8058 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
8059 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
8060 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
8061 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8062 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8063 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8064 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8065 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8066 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
8067 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8068 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8069 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8070 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8071 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8072 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8073 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8074 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8075 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8076 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8077 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8078 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
8079 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8080 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8081 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8082 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8083 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8084 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8085 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8086 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8087 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8088 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8089 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8090 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8091 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
8092 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8093 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8094 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8095 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8096 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8097 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8098 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8099 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8100 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8101 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8102 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8103 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8104 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8105 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8106 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8107 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8108 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8109 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8110 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8111 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8112 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8113 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8114 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
8115 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8116 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8117 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8118 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8119 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8120 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8121 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8122 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8123 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8124 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8125 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8126 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8127 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8128 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8129 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8130 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8131 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8132 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8133 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8134 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8135 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8136 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8137 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8138 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8139 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8140 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8141 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8142 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8143 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8144 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8145 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8146 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8147 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8148 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8149 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
8150 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8151 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8152 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8153 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8154 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8155 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8156 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8157 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
8158 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
8159 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8160 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8161 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8162 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8163 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8164 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8165 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
8166 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8167 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8168 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8169 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8170 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8171 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8172 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8173 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8174 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8175 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8176 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8177 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8178 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8179 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8180 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8181 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8182 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8183 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8184 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8185 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8186 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8187 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8188 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8189 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8190 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8191 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8192 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8193 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8194 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8195 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8196 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8197 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8198 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8199 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8200 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8201 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8202 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8203 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8204 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8205 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8206 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8207 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8208 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8209 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8210 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
8211 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
8212 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8213 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8214 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8215 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8216 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8217 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8218 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8219 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8220 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8221 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8222 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8223 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8224 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8225 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8226 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8227 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8228 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8229 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8230 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8231 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8232 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8233 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8234 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8235 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8236 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8237 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8238 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8239 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8240 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8241 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8242 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8243 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
8244 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
8245 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
8246 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
8247 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8248 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8249 };
8250
8251 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
8252 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
8253 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8254 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8255 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
8256 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
8257 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8258 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8259 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8260 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8261 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8262 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8263 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8264 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8265 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8266 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8267 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8268 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8269 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8270 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8271 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8272 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
8273 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8274 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8275 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8276 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8277 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8278 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8279 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8280 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
8281 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
8282 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
8283 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8284 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8285 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8286 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8287 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8288 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
8289 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8290 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8291 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8292 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8293 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8294 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8295 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8296 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8297 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8298 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8299 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8300 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
8301 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8302 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8303 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8304 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8305 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8306 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8307 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8308 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8309 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8310 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8311 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8312 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8313 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
8314 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8315 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8316 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8317 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8318 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8319 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8320 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8321 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8322 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8323 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8324 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8325 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8326 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8327 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8328 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8329 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8330 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8331 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8332 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8333 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8334 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8335 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8336 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
8337 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8338 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8339 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8340 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8341 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8342 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8343 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8344 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8345 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8346 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8347 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8348 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8349 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8350 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8351 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8352 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8353 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8354 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8355 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8356 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8357 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8358 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8359 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8360 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8361 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8362 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8363 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8364 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8365 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8366 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8367 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8368 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8369 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8370 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8371 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
8372 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8373 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8374 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8375 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8376 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8377 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8378 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8379 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
8380 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
8381 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8382 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8383 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8384 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8385 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8386 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8387 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
8388 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8389 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8390 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8391 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8392 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8393 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8394 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8395 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8396 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8397 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8398 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8399 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8400 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8401 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8402 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8403 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8404 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8405 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8406 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8407 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8408 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8409 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8410 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8411 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8412 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8413 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8414 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8415 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8416 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8417 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8418 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8419 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8420 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8421 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8422 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8423 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8424 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8425 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8426 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8427 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8428 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8429 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8430 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8431 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8432 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
8433 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
8434 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8435 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8436 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8437 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8438 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8439 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8440 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8441 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8442 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8443 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8444 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8445 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8446 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8447 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8448 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8449 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8450 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8451 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8452 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8453 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8454 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8455 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8456 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8457 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8458 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8459 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8460 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8461 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8462 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8463 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8464 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8465 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
8466 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
8467 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
8468 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
8469 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8470 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8471 };