2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
29 #include "pipe/p_shader_tokens.h"
30 #include "tgsi/tgsi_info.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "util/u_memory.h"
40 Why CAYMAN got loops for lots of instructions is explained here.
42 -These 8xx t-slot only ops are implemented in all vector slots.
43 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
44 These 8xx t-slot only opcodes become vector ops, with all four
45 slots expecting the arguments on sources a and b. Result is
46 broadcast to all channels.
47 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
48 These 8xx t-slot only opcodes become vector ops in the z, y, and
50 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
51 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
54 The w slot may have an independent co-issued operation, or if the
55 result is required to be in the w slot, the opcode above may be
56 issued in the w slot as well.
57 The compiler must issue the source argument to slots z, y, and x
60 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
62 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
63 struct r600_shader
*rshader
= &shader
->shader
;
68 if (shader
->bo
== NULL
) {
69 shader
->bo
= (struct r600_resource
*)
70 pipe_buffer_create(ctx
->screen
, PIPE_BIND_CUSTOM
, PIPE_USAGE_IMMUTABLE
, rshader
->bc
.ndw
* 4);
71 if (shader
->bo
== NULL
) {
74 ptr
= (uint32_t*)rctx
->ws
->buffer_map(shader
->bo
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
75 if (R600_BIG_ENDIAN
) {
76 for (i
= 0; i
< rshader
->bc
.ndw
; ++i
) {
77 ptr
[i
] = bswap_32(rshader
->bc
.bytecode
[i
]);
80 memcpy(ptr
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* sizeof(*ptr
));
82 rctx
->ws
->buffer_unmap(shader
->bo
->cs_buf
);
85 switch (rshader
->processor_type
) {
86 case TGSI_PROCESSOR_VERTEX
:
87 if (rctx
->chip_class
>= EVERGREEN
) {
88 evergreen_pipe_shader_vs(ctx
, shader
);
90 r600_pipe_shader_vs(ctx
, shader
);
93 case TGSI_PROCESSOR_FRAGMENT
:
94 if (rctx
->chip_class
>= EVERGREEN
) {
95 evergreen_pipe_shader_ps(ctx
, shader
);
97 r600_pipe_shader_ps(ctx
, shader
);
106 static int r600_shader_from_tgsi(struct r600_context
* rctx
, struct r600_pipe_shader
*pipeshader
);
108 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
110 static int dump_shaders
= -1;
111 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
114 /* Would like some magic "get_bool_option_once" routine.
116 if (dump_shaders
== -1)
117 dump_shaders
= debug_get_bool_option("R600_DUMP_SHADERS", FALSE
);
120 fprintf(stderr
, "--------------------------------------------------------------\n");
121 tgsi_dump(shader
->tokens
, 0);
123 if (shader
->so
.num_outputs
) {
125 fprintf(stderr
, "STREAMOUT\n");
126 for (i
= 0; i
< shader
->so
.num_outputs
; i
++) {
127 unsigned mask
= ((1 << shader
->so
.output
[i
].num_components
) - 1) <<
128 shader
->so
.output
[i
].start_component
;
129 fprintf(stderr
, " %i: MEM_STREAM0_BUF%i OUT[%i].%s%s%s%s\n", i
,
130 shader
->so
.output
[i
].output_buffer
, shader
->so
.output
[i
].register_index
,
131 mask
& 1 ? "x" : "_",
132 (mask
>> 1) & 1 ? "y" : "_",
133 (mask
>> 2) & 1 ? "z" : "_",
134 (mask
>> 3) & 1 ? "w" : "_");
138 r
= r600_shader_from_tgsi(rctx
, shader
);
140 R600_ERR("translation from TGSI failed !\n");
143 r
= r600_bytecode_build(&shader
->shader
.bc
);
145 R600_ERR("building bytecode failed !\n");
149 r600_bytecode_dump(&shader
->shader
.bc
);
150 fprintf(stderr
, "______________________________________________________________\n");
152 return r600_pipe_shader(ctx
, shader
);
155 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
157 pipe_resource_reference((struct pipe_resource
**)&shader
->bo
, NULL
);
158 r600_bytecode_clear(&shader
->shader
.bc
);
160 memset(&shader
->shader
,0,sizeof(struct r600_shader
));
164 * tgsi -> r600 shader
166 struct r600_shader_tgsi_instruction
;
168 struct r600_shader_src
{
177 struct r600_shader_ctx
{
178 struct tgsi_shader_info info
;
179 struct tgsi_parse_context parse
;
180 const struct tgsi_token
*tokens
;
182 unsigned file_offset
[TGSI_FILE_COUNT
];
184 struct r600_shader_tgsi_instruction
*inst_info
;
185 struct r600_bytecode
*bc
;
186 struct r600_shader
*shader
;
187 struct r600_shader_src src
[4];
190 uint32_t max_driver_temp_used
;
191 /* needed for evergreen interpolation */
192 boolean input_centroid
;
193 boolean input_linear
;
194 boolean input_perspective
;
198 boolean clip_vertex_write
;
204 struct r600_shader_tgsi_instruction
{
205 unsigned tgsi_opcode
;
207 unsigned r600_opcode
;
208 int (*process
)(struct r600_shader_ctx
*ctx
);
211 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
212 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
213 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
);
214 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
);
215 static int tgsi_else(struct r600_shader_ctx
*ctx
);
216 static int tgsi_endif(struct r600_shader_ctx
*ctx
);
217 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
);
218 static int tgsi_endloop(struct r600_shader_ctx
*ctx
);
219 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
);
222 * bytestream -> r600 shader
224 * These functions are used to transform the output of the LLVM backend into
225 * struct r600_bytecode.
228 static unsigned r600_src_from_byte_stream(unsigned char * bytes
,
229 unsigned bytes_read
, struct r600_bytecode_alu
* alu
, unsigned src_idx
)
233 sel0
= bytes
[bytes_read
++];
234 sel1
= bytes
[bytes_read
++];
235 alu
->src
[src_idx
].sel
= sel0
| (sel1
<< 8);
236 alu
->src
[src_idx
].chan
= bytes
[bytes_read
++];
237 alu
->src
[src_idx
].neg
= bytes
[bytes_read
++];
238 alu
->src
[src_idx
].abs
= bytes
[bytes_read
++];
239 alu
->src
[src_idx
].rel
= bytes
[bytes_read
++];
240 alu
->src
[src_idx
].kc_bank
= bytes
[bytes_read
++];
241 for (i
= 0; i
< 4; i
++) {
242 alu
->src
[src_idx
].value
|= bytes
[bytes_read
++] << (i
* 8);
247 static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx
*ctx
,
248 unsigned char * bytes
, unsigned bytes_read
)
251 unsigned inst0
, inst1
;
252 struct r600_bytecode_alu alu
;
253 memset(&alu
, 0, sizeof(alu
));
254 for(src_idx
= 0; src_idx
< 3; src_idx
++) {
255 bytes_read
= r600_src_from_byte_stream(bytes
, bytes_read
,
259 alu
.dst
.sel
= bytes
[bytes_read
++];
260 alu
.dst
.chan
= bytes
[bytes_read
++];
261 alu
.dst
.clamp
= bytes
[bytes_read
++];
262 alu
.dst
.write
= bytes
[bytes_read
++];
263 alu
.dst
.rel
= bytes
[bytes_read
++];
264 inst0
= bytes
[bytes_read
++];
265 inst1
= bytes
[bytes_read
++];
266 alu
.inst
= inst0
| (inst1
<< 8);
267 alu
.last
= bytes
[bytes_read
++];
268 alu
.is_op3
= bytes
[bytes_read
++];
269 alu
.predicate
= bytes
[bytes_read
++];
270 alu
.bank_swizzle
= bytes
[bytes_read
++];
271 alu
.bank_swizzle_force
= bytes
[bytes_read
++];
272 alu
.omod
= bytes
[bytes_read
++];
273 alu
.index_mode
= bytes
[bytes_read
++];
274 r600_bytecode_add_alu(ctx
->bc
, &alu
);
276 /* XXX: Handle other KILL instructions */
277 if (alu
.inst
== CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
)) {
278 ctx
->shader
->uses_kill
= 1;
279 /* XXX: This should be enforced in the LLVM backend. */
280 ctx
->bc
->force_add_cf
= 1;
285 static void llvm_if(struct r600_shader_ctx
*ctx
, struct r600_bytecode_alu
* alu
,
288 alu
->inst
= pred_inst
;
290 alu
->src
[1].sel
= V_SQ_ALU_SRC_0
;
291 alu
->src
[1].chan
= 0;
293 r600_bytecode_add_alu_type(ctx
->bc
, alu
,
294 CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
296 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
297 fc_pushlevel(ctx
, FC_IF
);
298 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
301 static void r600_break_from_byte_stream(struct r600_shader_ctx
*ctx
,
302 struct r600_bytecode_alu
*alu
, unsigned compare_opcode
)
304 unsigned opcode
= TGSI_OPCODE_BRK
;
305 if (ctx
->bc
->chip_class
== CAYMAN
)
306 ctx
->inst_info
= &cm_shader_tgsi_instruction
[opcode
];
307 else if (ctx
->bc
->chip_class
>= EVERGREEN
)
308 ctx
->inst_info
= &eg_shader_tgsi_instruction
[opcode
];
310 ctx
->inst_info
= &r600_shader_tgsi_instruction
[opcode
];
311 llvm_if(ctx
, alu
, compare_opcode
);
312 tgsi_loop_brk_cont(ctx
);
316 static unsigned r600_fc_from_byte_stream(struct r600_shader_ctx
*ctx
,
317 unsigned char * bytes
, unsigned bytes_read
)
319 struct r600_bytecode_alu alu
;
321 memset(&alu
, 0, sizeof(alu
));
322 bytes_read
= r600_src_from_byte_stream(bytes
, bytes_read
, &alu
, 0);
323 inst
= bytes
[bytes_read
++];
327 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
));
342 r600_break_from_byte_stream(ctx
, &alu
,
343 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE
));
346 r600_break_from_byte_stream(ctx
, &alu
,
347 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
));
351 unsigned opcode
= TGSI_OPCODE_CONT
;
352 if (ctx
->bc
->chip_class
== CAYMAN
) {
354 &cm_shader_tgsi_instruction
[opcode
];
355 } else if (ctx
->bc
->chip_class
>= EVERGREEN
) {
357 &eg_shader_tgsi_instruction
[opcode
];
360 &r600_shader_tgsi_instruction
[opcode
];
362 tgsi_loop_brk_cont(ctx
);
366 r600_break_from_byte_stream(ctx
, &alu
,
367 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT
));
374 static unsigned r600_tex_from_byte_stream(struct r600_shader_ctx
*ctx
,
375 unsigned char * bytes
, unsigned bytes_read
)
377 struct r600_bytecode_tex tex
;
379 tex
.inst
= bytes
[bytes_read
++];
380 tex
.resource_id
= bytes
[bytes_read
++];
381 tex
.src_gpr
= bytes
[bytes_read
++];
382 tex
.src_rel
= bytes
[bytes_read
++];
383 tex
.dst_gpr
= bytes
[bytes_read
++];
384 tex
.dst_rel
= bytes
[bytes_read
++];
385 tex
.dst_sel_x
= bytes
[bytes_read
++];
386 tex
.dst_sel_y
= bytes
[bytes_read
++];
387 tex
.dst_sel_z
= bytes
[bytes_read
++];
388 tex
.dst_sel_w
= bytes
[bytes_read
++];
389 tex
.lod_bias
= bytes
[bytes_read
++];
390 tex
.coord_type_x
= bytes
[bytes_read
++];
391 tex
.coord_type_y
= bytes
[bytes_read
++];
392 tex
.coord_type_z
= bytes
[bytes_read
++];
393 tex
.coord_type_w
= bytes
[bytes_read
++];
394 tex
.offset_x
= bytes
[bytes_read
++];
395 tex
.offset_y
= bytes
[bytes_read
++];
396 tex
.offset_z
= bytes
[bytes_read
++];
397 tex
.sampler_id
= bytes
[bytes_read
++];
398 tex
.src_sel_x
= bytes
[bytes_read
++];
399 tex
.src_sel_y
= bytes
[bytes_read
++];
400 tex
.src_sel_z
= bytes
[bytes_read
++];
401 tex
.src_sel_w
= bytes
[bytes_read
++];
403 r600_bytecode_add_tex(ctx
->bc
, &tex
);
408 static int r600_vtx_from_byte_stream(struct r600_shader_ctx
*ctx
,
409 unsigned char * bytes
, unsigned bytes_read
)
411 struct r600_bytecode_vtx vtx
;
412 memset(&vtx
, 0, sizeof(vtx
));
413 vtx
.inst
= bytes
[bytes_read
++];
414 vtx
.fetch_type
= bytes
[bytes_read
++];
415 vtx
.buffer_id
= bytes
[bytes_read
++];
416 vtx
.src_gpr
= bytes
[bytes_read
++];
417 vtx
.src_sel_x
= bytes
[bytes_read
++];
418 vtx
.mega_fetch_count
= bytes
[bytes_read
++];
419 vtx
.dst_gpr
= bytes
[bytes_read
++];
420 vtx
.dst_sel_x
= bytes
[bytes_read
++];
421 vtx
.dst_sel_y
= bytes
[bytes_read
++];
422 vtx
.dst_sel_z
= bytes
[bytes_read
++];
423 vtx
.dst_sel_w
= bytes
[bytes_read
++];
424 vtx
.use_const_fields
= bytes
[bytes_read
++];
425 vtx
.data_format
= bytes
[bytes_read
++];
426 vtx
.num_format_all
= bytes
[bytes_read
++];
427 vtx
.format_comp_all
= bytes
[bytes_read
++];
428 vtx
.srf_mode_all
= bytes
[bytes_read
++];
429 vtx
.offset
= bytes
[bytes_read
++];
430 vtx
.endian
= bytes
[bytes_read
++];
432 if (r600_bytecode_add_vtx(ctx
->bc
, &vtx
)) {
433 fprintf(stderr
, "Error adding vtx\n");
435 /* Use the Texture Cache */
436 ctx
->bc
->cf_last
->inst
= EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX
;
440 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx
*ctx
,
441 unsigned char * bytes
, unsigned num_bytes
)
443 unsigned bytes_read
= 0;
445 while (bytes_read
< num_bytes
) {
446 char inst_type
= bytes
[bytes_read
++];
449 bytes_read
= r600_alu_from_byte_stream(ctx
, bytes
,
453 bytes_read
= r600_tex_from_byte_stream(ctx
, bytes
,
457 bytes_read
= r600_fc_from_byte_stream(ctx
, bytes
,
461 r600_bytecode_add_cfinst(ctx
->bc
, CF_NATIVE
);
462 for (i
= 0; i
< 2; i
++) {
463 for (byte
= 0 ; byte
< 4; byte
++) {
464 ctx
->bc
->cf_last
->isa
[i
] |=
465 (bytes
[bytes_read
++] << (byte
* 8));
471 bytes_read
= r600_vtx_from_byte_stream(ctx
, bytes
,
475 /* XXX: Error here */
481 /* End bytestream -> r600 shader functions*/
483 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
485 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
488 if (i
->Instruction
.NumDstRegs
> 1) {
489 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
492 if (i
->Instruction
.Predicate
) {
493 R600_ERR("predicate unsupported\n");
497 if (i
->Instruction
.Label
) {
498 R600_ERR("label unsupported\n");
502 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
503 if (i
->Src
[j
].Register
.Dimension
) {
504 R600_ERR("unsupported src %d (dimension %d)\n", j
,
505 i
->Src
[j
].Register
.Dimension
);
509 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
510 if (i
->Dst
[j
].Register
.Dimension
) {
511 R600_ERR("unsupported dst (dimension)\n");
518 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
521 struct r600_bytecode_alu alu
;
522 int gpr
= 0, base_chan
= 0;
525 if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
) {
527 if (ctx
->shader
->input
[input
].centroid
)
529 } else if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
531 /* if we have perspective add one */
532 if (ctx
->input_perspective
) {
534 /* if we have perspective centroid */
535 if (ctx
->input_centroid
)
538 if (ctx
->shader
->input
[input
].centroid
)
542 /* work out gpr and base_chan from index */
544 base_chan
= (2 * (ij_index
% 2)) + 1;
546 for (i
= 0; i
< 8; i
++) {
547 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
550 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW
;
552 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY
;
554 if ((i
> 1) && (i
< 6)) {
555 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
559 alu
.dst
.chan
= i
% 4;
561 alu
.src
[0].sel
= gpr
;
562 alu
.src
[0].chan
= (base_chan
- (i
% 2));
564 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
566 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
569 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
576 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
579 struct r600_bytecode_alu alu
;
581 for (i
= 0; i
< 4; i
++) {
582 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
584 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0
;
586 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
591 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
596 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
604 * Special export handling in shaders
606 * shader export ARRAY_BASE for EXPORT_POS:
609 * 62, 63 are clip distance vectors
611 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
612 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
613 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
614 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
615 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
616 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
617 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
618 * exclusive from render target index)
619 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
622 * shader export ARRAY_BASE for EXPORT_PIXEL:
624 * 61 computed Z vector
626 * The use of the values exported in the computed Z vector are controlled
627 * by DB_SHADER_CONTROL:
628 * Z_EXPORT_ENABLE - Z as a float in RED
629 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
630 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
631 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
632 * DB_SOURCE_FORMAT - export control restrictions
637 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
638 static int r600_spi_sid(struct r600_shader_io
* io
)
640 int index
, name
= io
->name
;
642 /* These params are handled differently, they don't need
643 * semantic indices, so we'll use 0 for them.
645 if (name
== TGSI_SEMANTIC_POSITION
||
646 name
== TGSI_SEMANTIC_PSIZE
||
647 name
== TGSI_SEMANTIC_FACE
)
650 if (name
== TGSI_SEMANTIC_GENERIC
) {
651 /* For generic params simply use sid from tgsi */
654 /* For non-generic params - pack name and sid into 8 bits */
655 index
= 0x80 | (name
<<3) | (io
->sid
);
658 /* Make sure that all really used indices have nonzero value, so
659 * we can just compare it to 0 later instead of comparing the name
660 * with different values to detect special cases. */
667 /* turn input into interpolate on EG */
668 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
672 if (ctx
->shader
->input
[index
].spi_sid
) {
673 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
674 if (ctx
->shader
->input
[index
].interpolate
> 0) {
675 r
= evergreen_interp_alu(ctx
, index
);
677 r
= evergreen_interp_flat(ctx
, index
);
683 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
685 struct r600_bytecode_alu alu
;
687 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
688 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
690 for (i
= 0; i
< 4; i
++) {
691 memset(&alu
, 0, sizeof(alu
));
692 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
695 alu
.dst
.sel
= gpr_front
;
696 alu
.src
[0].sel
= ctx
->face_gpr
;
697 alu
.src
[1].sel
= gpr_front
;
698 alu
.src
[2].sel
= gpr_back
;
705 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
712 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
714 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
718 switch (d
->Declaration
.File
) {
719 case TGSI_FILE_INPUT
:
720 i
= ctx
->shader
->ninput
++;
721 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
722 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
723 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
724 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
725 ctx
->shader
->input
[i
].centroid
= d
->Declaration
.Centroid
;
726 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
;
727 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
728 switch (ctx
->shader
->input
[i
].name
) {
729 case TGSI_SEMANTIC_FACE
:
730 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
732 case TGSI_SEMANTIC_COLOR
:
735 case TGSI_SEMANTIC_POSITION
:
736 ctx
->fragcoord_input
= i
;
739 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
740 if ((r
= evergreen_interp_input(ctx
, i
)))
745 case TGSI_FILE_OUTPUT
:
746 i
= ctx
->shader
->noutput
++;
747 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
748 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
749 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
750 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
;
751 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
752 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
753 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
754 switch (d
->Semantic
.Name
) {
755 case TGSI_SEMANTIC_CLIPDIST
:
756 ctx
->shader
->clip_dist_write
|= d
->Declaration
.UsageMask
<< (d
->Semantic
.Index
<< 2);
758 case TGSI_SEMANTIC_PSIZE
:
759 ctx
->shader
->vs_out_misc_write
= 1;
760 ctx
->shader
->vs_out_point_size
= 1;
762 case TGSI_SEMANTIC_CLIPVERTEX
:
763 ctx
->clip_vertex_write
= TRUE
;
769 case TGSI_FILE_CONSTANT
:
770 case TGSI_FILE_TEMPORARY
:
771 case TGSI_FILE_SAMPLER
:
772 case TGSI_FILE_ADDRESS
:
775 case TGSI_FILE_SYSTEM_VALUE
:
776 if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
777 if (!ctx
->native_integers
) {
778 struct r600_bytecode_alu alu
;
779 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
781 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
);
790 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
794 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
797 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
803 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
805 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
809 * for evergreen we need to scan the shader to find the number of GPRs we need to
810 * reserve for interpolation.
812 * we need to know if we are going to emit
813 * any centroid inputs
814 * if perspective and linear are required
816 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
821 ctx
->input_linear
= FALSE
;
822 ctx
->input_perspective
= FALSE
;
823 ctx
->input_centroid
= FALSE
;
824 ctx
->num_interp_gpr
= 1;
826 /* any centroid inputs */
827 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
828 /* skip position/face */
829 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
830 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
)
832 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_LINEAR
)
833 ctx
->input_linear
= TRUE
;
834 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_PERSPECTIVE
)
835 ctx
->input_perspective
= TRUE
;
836 if (ctx
->info
.input_centroid
[i
])
837 ctx
->input_centroid
= TRUE
;
841 /* ignoring sample for now */
842 if (ctx
->input_perspective
)
844 if (ctx
->input_linear
)
846 if (ctx
->input_centroid
)
849 ctx
->num_interp_gpr
+= (num_baryc
+ 1) >> 1;
851 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
852 return ctx
->num_interp_gpr
;
855 static void tgsi_src(struct r600_shader_ctx
*ctx
,
856 const struct tgsi_full_src_register
*tgsi_src
,
857 struct r600_shader_src
*r600_src
)
859 memset(r600_src
, 0, sizeof(*r600_src
));
860 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
861 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
862 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
863 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
864 r600_src
->neg
= tgsi_src
->Register
.Negate
;
865 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
867 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
869 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
870 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
871 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
873 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
874 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
);
875 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
878 index
= tgsi_src
->Register
.Index
;
879 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
880 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
881 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
882 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
883 r600_src
->swizzle
[0] = 3;
884 r600_src
->swizzle
[1] = 3;
885 r600_src
->swizzle
[2] = 3;
886 r600_src
->swizzle
[3] = 3;
888 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
889 r600_src
->swizzle
[0] = 0;
890 r600_src
->swizzle
[1] = 0;
891 r600_src
->swizzle
[2] = 0;
892 r600_src
->swizzle
[3] = 0;
896 if (tgsi_src
->Register
.Indirect
)
897 r600_src
->rel
= V_SQ_REL_RELATIVE
;
898 r600_src
->sel
= tgsi_src
->Register
.Index
;
899 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
903 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
, unsigned int offset
, unsigned int dst_reg
)
905 struct r600_bytecode_vtx vtx
;
910 struct r600_bytecode_alu alu
;
912 memset(&alu
, 0, sizeof(alu
));
914 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
915 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
917 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
918 alu
.src
[1].value
= offset
;
920 alu
.dst
.sel
= dst_reg
;
924 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
929 ar_reg
= ctx
->bc
->ar_reg
;
932 memset(&vtx
, 0, sizeof(vtx
));
933 vtx
.fetch_type
= 2; /* VTX_FETCH_NO_INDEX_OFFSET */
934 vtx
.src_gpr
= ar_reg
;
935 vtx
.mega_fetch_count
= 16;
936 vtx
.dst_gpr
= dst_reg
;
937 vtx
.dst_sel_x
= 0; /* SEL_X */
938 vtx
.dst_sel_y
= 1; /* SEL_Y */
939 vtx
.dst_sel_z
= 2; /* SEL_Z */
940 vtx
.dst_sel_w
= 3; /* SEL_W */
941 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
942 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
943 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
944 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
945 vtx
.endian
= r600_endian_swap(32);
947 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
953 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
955 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
956 struct r600_bytecode_alu alu
;
957 int i
, j
, k
, nconst
, r
;
959 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
960 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
963 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
965 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
966 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
970 if (ctx
->src
[i
].rel
) {
971 int treg
= r600_get_temp(ctx
);
972 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].sel
- 512, treg
)))
975 ctx
->src
[i
].sel
= treg
;
979 int treg
= r600_get_temp(ctx
);
980 for (k
= 0; k
< 4; k
++) {
981 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
982 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
983 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
985 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
991 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
995 ctx
->src
[i
].sel
= treg
;
1003 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1004 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
1006 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1007 struct r600_bytecode_alu alu
;
1008 int i
, j
, k
, nliteral
, r
;
1010 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1011 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1015 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1016 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1017 int treg
= r600_get_temp(ctx
);
1018 for (k
= 0; k
< 4; k
++) {
1019 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1020 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1021 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1022 alu
.src
[0].chan
= k
;
1023 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
1029 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1033 ctx
->src
[i
].sel
= treg
;
1040 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
1042 int i
, r
, count
= ctx
->shader
->ninput
;
1044 /* additional inputs will be allocated right after the existing inputs,
1045 * we won't need them after the color selection, so we don't need to
1046 * reserve these gprs for the rest of the shader code and to adjust
1047 * output offsets etc. */
1048 int gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] +
1049 ctx
->info
.file_max
[TGSI_FILE_INPUT
] + 1;
1051 if (ctx
->face_gpr
== -1) {
1052 i
= ctx
->shader
->ninput
++;
1053 ctx
->shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
1054 ctx
->shader
->input
[i
].spi_sid
= 0;
1055 ctx
->shader
->input
[i
].gpr
= gpr
++;
1056 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
1059 for (i
= 0; i
< count
; i
++) {
1060 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1061 int ni
= ctx
->shader
->ninput
++;
1062 memcpy(&ctx
->shader
->input
[ni
],&ctx
->shader
->input
[i
], sizeof(struct r600_shader_io
));
1063 ctx
->shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
1064 ctx
->shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[ni
]);
1065 ctx
->shader
->input
[ni
].gpr
= gpr
++;
1067 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1068 r
= evergreen_interp_input(ctx
, ni
);
1073 r
= select_twoside_color(ctx
, i
, ni
);
1081 static int r600_shader_from_tgsi(struct r600_context
* rctx
, struct r600_pipe_shader
*pipeshader
)
1083 struct r600_shader
*shader
= &pipeshader
->shader
;
1084 struct tgsi_token
*tokens
= pipeshader
->tokens
;
1085 struct pipe_stream_output_info so
= pipeshader
->so
;
1086 struct tgsi_full_immediate
*immediate
;
1087 struct tgsi_full_property
*property
;
1088 struct r600_shader_ctx ctx
;
1089 struct r600_bytecode_output output
[32];
1090 unsigned output_done
, noutput
;
1093 int next_pixel_base
= 0, next_pos_base
= 60, next_param_base
= 0;
1094 /* Declarations used by llvm code */
1095 bool use_llvm
= false;
1096 unsigned char * inst_bytes
= NULL
;
1097 unsigned inst_byte_count
= 0;
1099 #ifdef R600_USE_LLVM
1100 use_llvm
= debug_get_bool_option("R600_LLVM", TRUE
);
1102 ctx
.bc
= &shader
->bc
;
1103 ctx
.shader
= shader
;
1104 ctx
.native_integers
= (rctx
->screen
->glsl_feature_level
>= 130);
1106 r600_bytecode_init(ctx
.bc
, rctx
->chip_class
, rctx
->family
);
1107 ctx
.tokens
= tokens
;
1108 tgsi_scan_shader(tokens
, &ctx
.info
);
1109 tgsi_parse_init(&ctx
.parse
, tokens
);
1110 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
1111 shader
->processor_type
= ctx
.type
;
1112 ctx
.bc
->type
= shader
->processor_type
;
1115 ctx
.fragcoord_input
= -1;
1116 ctx
.colors_used
= 0;
1117 ctx
.clip_vertex_write
= 0;
1119 shader
->two_side
= (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
) && rctx
->two_side
;
1120 shader
->nr_cbufs
= rctx
->nr_cbufs
;
1122 /* register allocations */
1123 /* Values [0,127] correspond to GPR[0..127].
1124 * Values [128,159] correspond to constant buffer bank 0
1125 * Values [160,191] correspond to constant buffer bank 1
1126 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1127 * Values [256,287] correspond to constant buffer bank 2 (EG)
1128 * Values [288,319] correspond to constant buffer bank 3 (EG)
1129 * Other special values are shown in the list below.
1130 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1131 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1132 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1133 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1134 * 248 SQ_ALU_SRC_0: special constant 0.0.
1135 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1136 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1137 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1138 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1139 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1140 * 254 SQ_ALU_SRC_PV: previous vector result.
1141 * 255 SQ_ALU_SRC_PS: previous scalar result.
1143 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
1144 ctx
.file_offset
[i
] = 0;
1146 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
1147 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
1148 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
1149 r600_bytecode_add_cfinst(ctx
.bc
, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
1151 r600_bytecode_add_cfinst(ctx
.bc
, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
1154 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
.bc
->chip_class
>= EVERGREEN
) {
1155 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
1158 /* LLVM backend setup */
1159 #ifdef R600_USE_LLVM
1160 if (use_llvm
&& ctx
.info
.indirect_files
) {
1161 fprintf(stderr
, "Warning: R600 LLVM backend does not support "
1162 "indirect adressing. Falling back to TGSI "
1167 struct radeon_llvm_context radeon_llvm_ctx
;
1170 memset(&radeon_llvm_ctx
, 0, sizeof(radeon_llvm_ctx
));
1171 radeon_llvm_ctx
.reserved_reg_count
= ctx
.file_offset
[TGSI_FILE_INPUT
];
1172 mod
= r600_tgsi_llvm(&radeon_llvm_ctx
, tokens
);
1173 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE
)) {
1176 if (r600_llvm_compile(mod
, &inst_bytes
, &inst_byte_count
,
1177 rctx
->family
, dump
)) {
1179 radeon_llvm_dispose(&radeon_llvm_ctx
);
1181 fprintf(stderr
, "R600 LLVM backend failed to compile "
1182 "shader. Falling back to TGSI\n");
1184 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
1185 ctx
.file_offset
[TGSI_FILE_INPUT
];
1187 radeon_llvm_dispose(&radeon_llvm_ctx
);
1190 /* End of LLVM backend setup */
1193 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
1194 ctx
.file_offset
[TGSI_FILE_INPUT
] +
1195 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
1197 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
1198 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
1200 /* Outside the GPR range. This will be translated to one of the
1201 * kcache banks later. */
1202 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
1204 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
1205 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
1206 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
1207 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 1;
1210 ctx
.literals
= NULL
;
1211 shader
->fs_write_all
= FALSE
;
1212 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
1213 tgsi_parse_token(&ctx
.parse
);
1214 switch (ctx
.parse
.FullToken
.Token
.Type
) {
1215 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1216 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
1217 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
1218 if(ctx
.literals
== NULL
) {
1222 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
1223 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
1224 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
1225 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
1228 case TGSI_TOKEN_TYPE_DECLARATION
:
1229 r
= tgsi_declaration(&ctx
);
1233 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1235 case TGSI_TOKEN_TYPE_PROPERTY
:
1236 property
= &ctx
.parse
.FullToken
.FullProperty
;
1237 switch (property
->Property
.PropertyName
) {
1238 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
:
1239 if (property
->u
[0].Data
== 1)
1240 shader
->fs_write_all
= TRUE
;
1242 case TGSI_PROPERTY_VS_PROHIBIT_UCPS
:
1243 if (property
->u
[0].Data
== 1)
1244 shader
->vs_prohibit_ucps
= TRUE
;
1249 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
1255 if (ctx
.fragcoord_input
>= 0) {
1256 if (ctx
.bc
->chip_class
== CAYMAN
) {
1257 for (j
= 0 ; j
< 4; j
++) {
1258 struct r600_bytecode_alu alu
;
1259 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1260 alu
.inst
= BC_INST(ctx
.bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1261 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
1262 alu
.src
[0].chan
= 3;
1264 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
1266 alu
.dst
.write
= (j
== 3);
1268 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
1272 struct r600_bytecode_alu alu
;
1273 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1274 alu
.inst
= BC_INST(ctx
.bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1275 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
1276 alu
.src
[0].chan
= 3;
1278 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
1282 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
1287 if (shader
->two_side
&& ctx
.colors_used
) {
1288 if ((r
= process_twoside_color_inputs(&ctx
)))
1292 tgsi_parse_init(&ctx
.parse
, tokens
);
1293 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
1294 tgsi_parse_token(&ctx
.parse
);
1295 switch (ctx
.parse
.FullToken
.Token
.Type
) {
1296 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1300 r
= tgsi_is_supported(&ctx
);
1303 ctx
.max_driver_temp_used
= 0;
1304 /* reserve first tmp for everyone */
1305 r600_get_temp(&ctx
);
1307 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
1308 if ((r
= tgsi_split_constant(&ctx
)))
1310 if ((r
= tgsi_split_literal_constant(&ctx
)))
1312 if (ctx
.bc
->chip_class
== CAYMAN
)
1313 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
1314 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
1315 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
1317 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
1318 r
= ctx
.inst_info
->process(&ctx
);
1327 /* Get instructions if we are using the LLVM backend. */
1329 r600_bytecode_from_byte_stream(&ctx
, inst_bytes
, inst_byte_count
);
1333 noutput
= shader
->noutput
;
1335 if (ctx
.clip_vertex_write
) {
1336 /* need to convert a clipvertex write into clipdistance writes and not export
1337 the clip vertex anymore */
1339 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
1340 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
1341 shader
->output
[noutput
].gpr
= ctx
.temp_reg
;
1343 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
1344 shader
->output
[noutput
].gpr
= ctx
.temp_reg
+1;
1347 /* reset spi_sid for clipvertex output to avoid confusing spi */
1348 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
1350 shader
->clip_dist_write
= 0xFF;
1352 for (i
= 0; i
< 8; i
++) {
1356 for (j
= 0; j
< 4; j
++) {
1357 struct r600_bytecode_alu alu
;
1358 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1359 alu
.inst
= BC_INST(ctx
.bc
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
);
1360 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
1361 alu
.src
[0].chan
= j
;
1363 alu
.src
[1].sel
= 512 + i
;
1364 alu
.src
[1].kc_bank
= 1;
1365 alu
.src
[1].chan
= j
;
1367 alu
.dst
.sel
= ctx
.temp_reg
+ oreg
;
1369 alu
.dst
.write
= (j
== ochan
);
1372 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
1379 /* Add stream outputs. */
1380 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
&& so
.num_outputs
) {
1381 for (i
= 0; i
< so
.num_outputs
; i
++) {
1382 struct r600_bytecode_output output
;
1384 if (so
.output
[i
].output_buffer
>= 4) {
1385 R600_ERR("exceeded the max number of stream output buffers, got: %d\n",
1386 so
.output
[i
].output_buffer
);
1390 if (so
.output
[i
].dst_offset
< so
.output
[i
].start_component
) {
1391 R600_ERR("stream_output - dst_offset cannot be less than start_component\n");
1396 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
1397 output
.gpr
= shader
->output
[so
.output
[i
].register_index
].gpr
;
1398 output
.elem_size
= 0;
1399 output
.array_base
= so
.output
[i
].dst_offset
- so
.output
[i
].start_component
;
1400 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
1401 output
.burst_count
= 1;
1403 /* array_size is an upper limit for the burst_count
1404 * with MEM_STREAM instructions */
1405 output
.array_size
= 0xFFF;
1406 output
.comp_mask
= ((1 << so
.output
[i
].num_components
) - 1) << so
.output
[i
].start_component
;
1407 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
1408 switch (so
.output
[i
].output_buffer
) {
1410 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0
;
1413 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1
;
1416 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2
;
1419 output
.inst
= EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3
;
1423 switch (so
.output
[i
].output_buffer
) {
1425 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0
;
1428 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1
;
1431 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2
;
1434 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3
;
1438 r
= r600_bytecode_add_output(ctx
.bc
, &output
);
1445 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
1446 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1447 output
[j
].gpr
= shader
->output
[i
].gpr
;
1448 output
[j
].elem_size
= 3;
1449 output
[j
].swizzle_x
= 0;
1450 output
[j
].swizzle_y
= 1;
1451 output
[j
].swizzle_z
= 2;
1452 output
[j
].swizzle_w
= 3;
1453 output
[j
].burst_count
= 1;
1454 output
[j
].barrier
= 1;
1455 output
[j
].type
= -1;
1456 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1458 case TGSI_PROCESSOR_VERTEX
:
1459 switch (shader
->output
[i
].name
) {
1460 case TGSI_SEMANTIC_POSITION
:
1461 output
[j
].array_base
= next_pos_base
++;
1462 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1465 case TGSI_SEMANTIC_PSIZE
:
1466 output
[j
].array_base
= next_pos_base
++;
1467 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1469 case TGSI_SEMANTIC_CLIPVERTEX
:
1472 case TGSI_SEMANTIC_CLIPDIST
:
1473 output
[j
].array_base
= next_pos_base
++;
1474 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
1475 /* spi_sid is 0 for clipdistance outputs that were generated
1476 * for clipvertex - we don't need to pass them to PS */
1477 if (shader
->output
[i
].spi_sid
) {
1479 /* duplicate it as PARAM to pass to the pixel shader */
1480 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
1481 output
[j
].array_base
= next_param_base
++;
1482 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1485 case TGSI_SEMANTIC_FOG
:
1486 output
[j
].swizzle_y
= 4; /* 0 */
1487 output
[j
].swizzle_z
= 4; /* 0 */
1488 output
[j
].swizzle_w
= 5; /* 1 */
1492 case TGSI_PROCESSOR_FRAGMENT
:
1493 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1494 output
[j
].array_base
= next_pixel_base
++;
1495 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1496 if (shader
->fs_write_all
&& (rctx
->chip_class
>= EVERGREEN
)) {
1497 for (k
= 1; k
< shader
->nr_cbufs
; k
++) {
1499 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1500 output
[j
].gpr
= shader
->output
[i
].gpr
;
1501 output
[j
].elem_size
= 3;
1502 output
[j
].swizzle_x
= 0;
1503 output
[j
].swizzle_y
= 1;
1504 output
[j
].swizzle_z
= 2;
1505 output
[j
].swizzle_w
= 3;
1506 output
[j
].burst_count
= 1;
1507 output
[j
].barrier
= 1;
1508 output
[j
].array_base
= next_pixel_base
++;
1509 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1510 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1513 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
1514 output
[j
].array_base
= 61;
1515 output
[j
].swizzle_x
= 2;
1516 output
[j
].swizzle_y
= 7;
1517 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
1518 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1519 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
1520 output
[j
].array_base
= 61;
1521 output
[j
].swizzle_x
= 7;
1522 output
[j
].swizzle_y
= 1;
1523 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
1524 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1526 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
1532 R600_ERR("unsupported processor type %d\n", ctx
.type
);
1537 if (output
[j
].type
==-1) {
1538 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1539 output
[j
].array_base
= next_param_base
++;
1543 /* add fake param output for vertex shader if no param is exported */
1544 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
&& next_param_base
== 0) {
1545 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1547 output
[j
].elem_size
= 3;
1548 output
[j
].swizzle_x
= 7;
1549 output
[j
].swizzle_y
= 7;
1550 output
[j
].swizzle_z
= 7;
1551 output
[j
].swizzle_w
= 7;
1552 output
[j
].burst_count
= 1;
1553 output
[j
].barrier
= 1;
1554 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
1555 output
[j
].array_base
= 0;
1556 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1560 /* add fake pixel export */
1561 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& j
== 0) {
1562 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
1564 output
[j
].elem_size
= 3;
1565 output
[j
].swizzle_x
= 7;
1566 output
[j
].swizzle_y
= 7;
1567 output
[j
].swizzle_z
= 7;
1568 output
[j
].swizzle_w
= 7;
1569 output
[j
].burst_count
= 1;
1570 output
[j
].barrier
= 1;
1571 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
1572 output
[j
].array_base
= 0;
1573 output
[j
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
1579 /* set export done on last export of each type */
1580 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
1581 if (ctx
.bc
->chip_class
< CAYMAN
) {
1582 if (i
== (noutput
- 1)) {
1583 output
[i
].end_of_program
= 1;
1586 if (!(output_done
& (1 << output
[i
].type
))) {
1587 output_done
|= (1 << output
[i
].type
);
1588 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
);
1591 /* add output to bytecode */
1592 for (i
= 0; i
< noutput
; i
++) {
1593 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
1597 /* add program end */
1598 if (ctx
.bc
->chip_class
== CAYMAN
)
1599 cm_bytecode_add_cf_end(ctx
.bc
);
1601 /* check GPR limit - we have 124 = 128 - 4
1602 * (4 are reserved as alu clause temporary registers) */
1603 if (ctx
.bc
->ngpr
> 124) {
1604 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx
.bc
->ngpr
);
1610 tgsi_parse_free(&ctx
.parse
);
1614 tgsi_parse_free(&ctx
.parse
);
1618 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
1620 R600_ERR("%s tgsi opcode unsupported\n",
1621 tgsi_get_opcode_name(ctx
->inst_info
->tgsi_opcode
));
1625 static int tgsi_end(struct r600_shader_ctx
*ctx
)
1630 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
1631 const struct r600_shader_src
*shader_src
,
1634 bc_src
->sel
= shader_src
->sel
;
1635 bc_src
->chan
= shader_src
->swizzle
[chan
];
1636 bc_src
->neg
= shader_src
->neg
;
1637 bc_src
->abs
= shader_src
->abs
;
1638 bc_src
->rel
= shader_src
->rel
;
1639 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
1642 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
1648 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
1650 bc_src
->neg
= !bc_src
->neg
;
1653 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
1654 const struct tgsi_full_dst_register
*tgsi_dst
,
1656 struct r600_bytecode_alu_dst
*r600_dst
)
1658 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1660 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
1661 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
1662 r600_dst
->chan
= swizzle
;
1663 r600_dst
->write
= 1;
1664 if (tgsi_dst
->Register
.Indirect
)
1665 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
1666 if (inst
->Instruction
.Saturate
) {
1667 r600_dst
->clamp
= 1;
1671 static int tgsi_last_instruction(unsigned writemask
)
1675 for (i
= 0; i
< 4; i
++) {
1676 if (writemask
& (1 << i
)) {
1683 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
1685 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1686 struct r600_bytecode_alu alu
;
1688 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1690 for (i
= 0; i
< lasti
+ 1; i
++) {
1691 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1694 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1695 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1697 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1699 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1700 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
1703 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
1704 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
1706 /* handle some special cases */
1707 switch (ctx
->inst_info
->tgsi_opcode
) {
1708 case TGSI_OPCODE_SUB
:
1709 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
1711 case TGSI_OPCODE_ABS
:
1712 r600_bytecode_src_set_abs(&alu
.src
[0]);
1717 if (i
== lasti
|| trans_only
) {
1720 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1727 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
1729 return tgsi_op2_s(ctx
, 0, 0);
1732 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
1734 return tgsi_op2_s(ctx
, 1, 0);
1737 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
1739 return tgsi_op2_s(ctx
, 0, 1);
1742 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
1744 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1745 struct r600_bytecode_alu alu
;
1747 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1749 for (i
= 0; i
< lasti
+ 1; i
++) {
1751 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1753 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1754 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1756 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1758 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
1760 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1765 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1773 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
1775 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1777 struct r600_bytecode_alu alu
;
1778 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
1780 for (i
= 0 ; i
< last_slot
; i
++) {
1781 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1782 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1783 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1784 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
1786 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1787 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1789 if (i
== last_slot
- 1)
1791 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1798 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
1800 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1802 struct r600_bytecode_alu alu
;
1803 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
1804 for (k
= 0; k
< last_slot
; k
++) {
1805 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
1808 for (i
= 0 ; i
< 4; i
++) {
1809 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1810 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1811 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1812 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
1814 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1815 alu
.dst
.write
= (i
== k
);
1818 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1827 * r600 - trunc to -PI..PI range
1828 * r700 - normalize by dividing by 2PI
1831 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
1833 static float half_inv_pi
= 1.0 /(3.1415926535 * 2);
1834 static float double_pi
= 3.1415926535 * 2;
1835 static float neg_pi
= -3.1415926535;
1838 struct r600_bytecode_alu alu
;
1840 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1841 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1845 alu
.dst
.sel
= ctx
->temp_reg
;
1848 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
1850 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1851 alu
.src
[1].chan
= 0;
1852 alu
.src
[1].value
= *(uint32_t *)&half_inv_pi
;
1853 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
1854 alu
.src
[2].chan
= 0;
1856 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1860 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1861 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
1864 alu
.dst
.sel
= ctx
->temp_reg
;
1867 alu
.src
[0].sel
= ctx
->temp_reg
;
1868 alu
.src
[0].chan
= 0;
1870 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1874 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1875 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1879 alu
.dst
.sel
= ctx
->temp_reg
;
1882 alu
.src
[0].sel
= ctx
->temp_reg
;
1883 alu
.src
[0].chan
= 0;
1885 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1886 alu
.src
[1].chan
= 0;
1887 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1888 alu
.src
[2].chan
= 0;
1890 if (ctx
->bc
->chip_class
== R600
) {
1891 alu
.src
[1].value
= *(uint32_t *)&double_pi
;
1892 alu
.src
[2].value
= *(uint32_t *)&neg_pi
;
1894 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1895 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
1900 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1906 static int cayman_trig(struct r600_shader_ctx
*ctx
)
1908 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1909 struct r600_bytecode_alu alu
;
1910 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
1913 r
= tgsi_setup_trig(ctx
);
1918 for (i
= 0; i
< last_slot
; i
++) {
1919 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1920 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1923 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1924 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1926 alu
.src
[0].sel
= ctx
->temp_reg
;
1927 alu
.src
[0].chan
= 0;
1928 if (i
== last_slot
- 1)
1930 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1937 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
1939 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1940 struct r600_bytecode_alu alu
;
1942 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1944 r
= tgsi_setup_trig(ctx
);
1948 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1949 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1951 alu
.dst
.sel
= ctx
->temp_reg
;
1954 alu
.src
[0].sel
= ctx
->temp_reg
;
1955 alu
.src
[0].chan
= 0;
1957 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1961 /* replicate result */
1962 for (i
= 0; i
< lasti
+ 1; i
++) {
1963 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1966 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1967 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1969 alu
.src
[0].sel
= ctx
->temp_reg
;
1970 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1973 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1980 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
1982 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1983 struct r600_bytecode_alu alu
;
1986 /* We'll only need the trig stuff if we are going to write to the
1987 * X or Y components of the destination vector.
1989 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
1990 r
= tgsi_setup_trig(ctx
);
1996 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
1997 if (ctx
->bc
->chip_class
== CAYMAN
) {
1998 for (i
= 0 ; i
< 3; i
++) {
1999 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2000 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
2001 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2007 alu
.src
[0].sel
= ctx
->temp_reg
;
2008 alu
.src
[0].chan
= 0;
2011 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2016 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2017 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
2018 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
2020 alu
.src
[0].sel
= ctx
->temp_reg
;
2021 alu
.src
[0].chan
= 0;
2023 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2030 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2031 if (ctx
->bc
->chip_class
== CAYMAN
) {
2032 for (i
= 0 ; i
< 3; i
++) {
2033 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2034 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
2035 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2040 alu
.src
[0].sel
= ctx
->temp_reg
;
2041 alu
.src
[0].chan
= 0;
2044 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2049 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2050 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
2051 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
2053 alu
.src
[0].sel
= ctx
->temp_reg
;
2054 alu
.src
[0].chan
= 0;
2056 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2063 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
2064 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2066 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2068 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
2070 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2071 alu
.src
[0].chan
= 0;
2075 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2081 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
2082 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2084 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2086 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
2088 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2089 alu
.src
[0].chan
= 0;
2093 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2101 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
2103 struct r600_bytecode_alu alu
;
2106 for (i
= 0; i
< 4; i
++) {
2107 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2108 alu
.inst
= ctx
->inst_info
->r600_opcode
;
2112 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2114 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILP
) {
2115 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
2118 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2123 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2128 /* kill must be last in ALU */
2129 ctx
->bc
->force_add_cf
= 1;
2130 ctx
->shader
->uses_kill
= TRUE
;
2134 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
2136 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2137 struct r600_bytecode_alu alu
;
2140 /* tmp.x = max(src.y, 0.0) */
2141 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2142 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
2143 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
2144 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
2145 alu
.src
[1].chan
= 1;
2147 alu
.dst
.sel
= ctx
->temp_reg
;
2152 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2156 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
2162 if (ctx
->bc
->chip_class
== CAYMAN
) {
2163 for (i
= 0; i
< 3; i
++) {
2164 /* tmp.z = log(tmp.x) */
2165 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2166 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
2167 alu
.src
[0].sel
= ctx
->temp_reg
;
2168 alu
.src
[0].chan
= 0;
2169 alu
.dst
.sel
= ctx
->temp_reg
;
2177 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2182 /* tmp.z = log(tmp.x) */
2183 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2184 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
2185 alu
.src
[0].sel
= ctx
->temp_reg
;
2186 alu
.src
[0].chan
= 0;
2187 alu
.dst
.sel
= ctx
->temp_reg
;
2191 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2196 chan
= alu
.dst
.chan
;
2199 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2200 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2201 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
);
2202 alu
.src
[0].sel
= sel
;
2203 alu
.src
[0].chan
= chan
;
2204 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
2205 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
2206 alu
.dst
.sel
= ctx
->temp_reg
;
2211 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2215 if (ctx
->bc
->chip_class
== CAYMAN
) {
2216 for (i
= 0; i
< 3; i
++) {
2217 /* dst.z = exp(tmp.x) */
2218 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2219 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2220 alu
.src
[0].sel
= ctx
->temp_reg
;
2221 alu
.src
[0].chan
= 0;
2222 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2228 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2233 /* dst.z = exp(tmp.x) */
2234 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2235 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2236 alu
.src
[0].sel
= ctx
->temp_reg
;
2237 alu
.src
[0].chan
= 0;
2238 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
2240 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2247 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2248 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2249 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
2250 alu
.src
[0].chan
= 0;
2251 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
2252 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
2253 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2257 /* dst.y = max(src.x, 0.0) */
2258 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2259 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
2260 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
2261 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
2262 alu
.src
[1].chan
= 0;
2263 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
2264 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
2265 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2270 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2271 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2272 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2273 alu
.src
[0].chan
= 0;
2274 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
2275 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
2277 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2284 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
2286 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2287 struct r600_bytecode_alu alu
;
2290 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2293 * For state trackers other than OpenGL, we'll want to use
2294 * _RECIPSQRT_IEEE instead.
2296 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
);
2298 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2299 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
2300 r600_bytecode_src_set_abs(&alu
.src
[i
]);
2302 alu
.dst
.sel
= ctx
->temp_reg
;
2305 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2308 /* replicate result */
2309 return tgsi_helper_tempx_replicate(ctx
);
2312 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
2314 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2315 struct r600_bytecode_alu alu
;
2318 for (i
= 0; i
< 4; i
++) {
2319 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2320 alu
.src
[0].sel
= ctx
->temp_reg
;
2321 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2323 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2324 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
2327 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2334 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
2336 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2337 struct r600_bytecode_alu alu
;
2340 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2341 alu
.inst
= ctx
->inst_info
->r600_opcode
;
2342 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2343 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
2345 alu
.dst
.sel
= ctx
->temp_reg
;
2348 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2351 /* replicate result */
2352 return tgsi_helper_tempx_replicate(ctx
);
2355 static int cayman_pow(struct r600_shader_ctx
*ctx
)
2357 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2359 struct r600_bytecode_alu alu
;
2360 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
2362 for (i
= 0; i
< 3; i
++) {
2363 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2364 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2365 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
2366 alu
.dst
.sel
= ctx
->temp_reg
;
2371 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2377 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2378 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2379 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
2380 alu
.src
[1].sel
= ctx
->temp_reg
;
2381 alu
.dst
.sel
= ctx
->temp_reg
;
2384 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2388 for (i
= 0; i
< last_slot
; i
++) {
2389 /* POW(a,b) = EXP2(b * LOG2(a))*/
2390 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2391 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2392 alu
.src
[0].sel
= ctx
->temp_reg
;
2394 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2395 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
2396 if (i
== last_slot
- 1)
2398 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2405 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
2407 struct r600_bytecode_alu alu
;
2411 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2412 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2413 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
2414 alu
.dst
.sel
= ctx
->temp_reg
;
2417 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2421 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2422 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2423 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
2424 alu
.src
[1].sel
= ctx
->temp_reg
;
2425 alu
.dst
.sel
= ctx
->temp_reg
;
2428 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2431 /* POW(a,b) = EXP2(b * LOG2(a))*/
2432 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2433 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2434 alu
.src
[0].sel
= ctx
->temp_reg
;
2435 alu
.dst
.sel
= ctx
->temp_reg
;
2438 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2441 return tgsi_helper_tempx_replicate(ctx
);
2444 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
2446 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2447 struct r600_bytecode_alu alu
;
2449 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
2450 int tmp0
= ctx
->temp_reg
;
2451 int tmp1
= r600_get_temp(ctx
);
2452 int tmp2
= r600_get_temp(ctx
);
2453 int tmp3
= r600_get_temp(ctx
);
2456 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2458 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2459 * 2. tmp0.z = lo (tmp0.x * src2)
2460 * 3. tmp0.w = -tmp0.z
2461 * 4. tmp0.y = hi (tmp0.x * src2)
2462 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2463 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2464 * 7. tmp1.x = tmp0.x - tmp0.w
2465 * 8. tmp1.y = tmp0.x + tmp0.w
2466 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2467 * 10. tmp0.z = hi(tmp0.x * src1) = q
2468 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2470 * 12. tmp0.w = src1 - tmp0.y = r
2471 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2472 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2476 * 15. tmp1.z = tmp0.z + 1 = q + 1
2477 * 16. tmp1.w = tmp0.z - 1 = q - 1
2481 * 15. tmp1.z = tmp0.w - src2 = r - src2
2482 * 16. tmp1.w = tmp0.w + src2 = r + src2
2486 * 17. tmp1.x = tmp1.x & tmp1.y
2488 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2489 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2491 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2492 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2496 * Same as unsigned, using abs values of the operands,
2497 * and fixing the sign of the result in the end.
2500 for (i
= 0; i
< 4; i
++) {
2501 if (!(write_mask
& (1<<i
)))
2506 /* tmp2.x = -src0 */
2507 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2508 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2514 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2516 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2519 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2522 /* tmp2.y = -src1 */
2523 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2524 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2530 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2532 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2535 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2538 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2539 /* it will be a sign of the quotient */
2542 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2543 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
);
2549 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
2550 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2553 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2557 /* tmp2.x = |src0| */
2558 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2559 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
2566 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
2567 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2568 alu
.src
[2].sel
= tmp2
;
2569 alu
.src
[2].chan
= 0;
2572 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2575 /* tmp2.y = |src1| */
2576 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2577 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
2584 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2585 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2586 alu
.src
[2].sel
= tmp2
;
2587 alu
.src
[2].chan
= 1;
2590 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2595 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2596 if (ctx
->bc
->chip_class
== CAYMAN
) {
2597 /* tmp3.x = u2f(src2) */
2598 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2599 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
);
2606 alu
.src
[0].sel
= tmp2
;
2607 alu
.src
[0].chan
= 1;
2609 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2613 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2616 /* tmp0.x = recip(tmp3.x) */
2617 for (j
= 0 ; j
< 3; j
++) {
2618 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2619 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
2623 alu
.dst
.write
= (j
== 0);
2625 alu
.src
[0].sel
= tmp3
;
2626 alu
.src
[0].chan
= 0;
2630 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2634 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2635 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2637 alu
.src
[0].sel
= tmp0
;
2638 alu
.src
[0].chan
= 0;
2640 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2641 alu
.src
[1].value
= 0x4f800000;
2646 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2650 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2651 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
);
2657 alu
.src
[0].sel
= tmp3
;
2658 alu
.src
[0].chan
= 0;
2661 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2665 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2666 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT
);
2673 alu
.src
[0].sel
= tmp2
;
2674 alu
.src
[0].chan
= 1;
2676 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2680 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2684 /* 2. tmp0.z = lo (tmp0.x * src2) */
2685 if (ctx
->bc
->chip_class
== CAYMAN
) {
2686 for (j
= 0 ; j
< 4; j
++) {
2687 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2688 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2692 alu
.dst
.write
= (j
== 2);
2694 alu
.src
[0].sel
= tmp0
;
2695 alu
.src
[0].chan
= 0;
2697 alu
.src
[1].sel
= tmp2
;
2698 alu
.src
[1].chan
= 1;
2700 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2703 alu
.last
= (j
== 3);
2704 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2708 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2709 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2715 alu
.src
[0].sel
= tmp0
;
2716 alu
.src
[0].chan
= 0;
2718 alu
.src
[1].sel
= tmp2
;
2719 alu
.src
[1].chan
= 1;
2721 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2725 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2729 /* 3. tmp0.w = -tmp0.z */
2730 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2731 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2737 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2738 alu
.src
[1].sel
= tmp0
;
2739 alu
.src
[1].chan
= 2;
2742 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2745 /* 4. tmp0.y = hi (tmp0.x * src2) */
2746 if (ctx
->bc
->chip_class
== CAYMAN
) {
2747 for (j
= 0 ; j
< 4; j
++) {
2748 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2749 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2753 alu
.dst
.write
= (j
== 1);
2755 alu
.src
[0].sel
= tmp0
;
2756 alu
.src
[0].chan
= 0;
2759 alu
.src
[1].sel
= tmp2
;
2760 alu
.src
[1].chan
= 1;
2762 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2764 alu
.last
= (j
== 3);
2765 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2769 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2770 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2776 alu
.src
[0].sel
= tmp0
;
2777 alu
.src
[0].chan
= 0;
2780 alu
.src
[1].sel
= tmp2
;
2781 alu
.src
[1].chan
= 1;
2783 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
2787 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2791 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2792 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2793 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
2800 alu
.src
[0].sel
= tmp0
;
2801 alu
.src
[0].chan
= 1;
2802 alu
.src
[1].sel
= tmp0
;
2803 alu
.src
[1].chan
= 3;
2804 alu
.src
[2].sel
= tmp0
;
2805 alu
.src
[2].chan
= 2;
2808 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2811 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2812 if (ctx
->bc
->chip_class
== CAYMAN
) {
2813 for (j
= 0 ; j
< 4; j
++) {
2814 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2815 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2819 alu
.dst
.write
= (j
== 3);
2821 alu
.src
[0].sel
= tmp0
;
2822 alu
.src
[0].chan
= 2;
2824 alu
.src
[1].sel
= tmp0
;
2825 alu
.src
[1].chan
= 0;
2827 alu
.last
= (j
== 3);
2828 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2832 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2833 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2839 alu
.src
[0].sel
= tmp0
;
2840 alu
.src
[0].chan
= 2;
2842 alu
.src
[1].sel
= tmp0
;
2843 alu
.src
[1].chan
= 0;
2846 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2850 /* 7. tmp1.x = tmp0.x - tmp0.w */
2851 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2852 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
2858 alu
.src
[0].sel
= tmp0
;
2859 alu
.src
[0].chan
= 0;
2860 alu
.src
[1].sel
= tmp0
;
2861 alu
.src
[1].chan
= 3;
2864 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2867 /* 8. tmp1.y = tmp0.x + tmp0.w */
2868 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2869 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
2875 alu
.src
[0].sel
= tmp0
;
2876 alu
.src
[0].chan
= 0;
2877 alu
.src
[1].sel
= tmp0
;
2878 alu
.src
[1].chan
= 3;
2881 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2884 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2885 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2886 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
2893 alu
.src
[0].sel
= tmp0
;
2894 alu
.src
[0].chan
= 1;
2895 alu
.src
[1].sel
= tmp1
;
2896 alu
.src
[1].chan
= 1;
2897 alu
.src
[2].sel
= tmp1
;
2898 alu
.src
[2].chan
= 0;
2901 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2904 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2905 if (ctx
->bc
->chip_class
== CAYMAN
) {
2906 for (j
= 0 ; j
< 4; j
++) {
2907 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2908 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2912 alu
.dst
.write
= (j
== 2);
2914 alu
.src
[0].sel
= tmp0
;
2915 alu
.src
[0].chan
= 0;
2918 alu
.src
[1].sel
= tmp2
;
2919 alu
.src
[1].chan
= 0;
2921 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2924 alu
.last
= (j
== 3);
2925 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2929 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2930 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT
);
2936 alu
.src
[0].sel
= tmp0
;
2937 alu
.src
[0].chan
= 0;
2940 alu
.src
[1].sel
= tmp2
;
2941 alu
.src
[1].chan
= 0;
2943 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
2947 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2951 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
2952 if (ctx
->bc
->chip_class
== CAYMAN
) {
2953 for (j
= 0 ; j
< 4; j
++) {
2954 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2955 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2959 alu
.dst
.write
= (j
== 1);
2962 alu
.src
[0].sel
= tmp2
;
2963 alu
.src
[0].chan
= 1;
2965 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2968 alu
.src
[1].sel
= tmp0
;
2969 alu
.src
[1].chan
= 2;
2971 alu
.last
= (j
== 3);
2972 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2976 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2977 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
2984 alu
.src
[0].sel
= tmp2
;
2985 alu
.src
[0].chan
= 1;
2987 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
2990 alu
.src
[1].sel
= tmp0
;
2991 alu
.src
[1].chan
= 2;
2994 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
2998 /* 12. tmp0.w = src1 - tmp0.y = r */
2999 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3000 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3007 alu
.src
[0].sel
= tmp2
;
3008 alu
.src
[0].chan
= 0;
3010 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3013 alu
.src
[1].sel
= tmp0
;
3014 alu
.src
[1].chan
= 1;
3017 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3020 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3021 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3022 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
);
3028 alu
.src
[0].sel
= tmp0
;
3029 alu
.src
[0].chan
= 3;
3031 alu
.src
[1].sel
= tmp2
;
3032 alu
.src
[1].chan
= 1;
3034 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3038 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3041 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3042 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3043 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
);
3050 alu
.src
[0].sel
= tmp2
;
3051 alu
.src
[0].chan
= 0;
3053 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3056 alu
.src
[1].sel
= tmp0
;
3057 alu
.src
[1].chan
= 1;
3060 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3063 if (mod
) { /* UMOD */
3065 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3066 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3067 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3073 alu
.src
[0].sel
= tmp0
;
3074 alu
.src
[0].chan
= 3;
3077 alu
.src
[1].sel
= tmp2
;
3078 alu
.src
[1].chan
= 1;
3080 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3084 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3087 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3088 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3089 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
3095 alu
.src
[0].sel
= tmp0
;
3096 alu
.src
[0].chan
= 3;
3098 alu
.src
[1].sel
= tmp2
;
3099 alu
.src
[1].chan
= 1;
3101 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
3105 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3110 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3111 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3112 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
3118 alu
.src
[0].sel
= tmp0
;
3119 alu
.src
[0].chan
= 2;
3120 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
3123 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3126 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3127 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3128 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
3134 alu
.src
[0].sel
= tmp0
;
3135 alu
.src
[0].chan
= 2;
3136 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
3139 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3144 /* 17. tmp1.x = tmp1.x & tmp1.y */
3145 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3146 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
);
3152 alu
.src
[0].sel
= tmp1
;
3153 alu
.src
[0].chan
= 0;
3154 alu
.src
[1].sel
= tmp1
;
3155 alu
.src
[1].chan
= 1;
3158 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3161 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3162 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3163 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3164 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
3171 alu
.src
[0].sel
= tmp1
;
3172 alu
.src
[0].chan
= 0;
3173 alu
.src
[1].sel
= tmp0
;
3174 alu
.src
[1].chan
= mod
? 3 : 2;
3175 alu
.src
[2].sel
= tmp1
;
3176 alu
.src
[2].chan
= 2;
3179 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3182 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3183 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3184 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT
);
3192 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3195 alu
.src
[0].sel
= tmp1
;
3196 alu
.src
[0].chan
= 1;
3197 alu
.src
[1].sel
= tmp1
;
3198 alu
.src
[1].chan
= 3;
3199 alu
.src
[2].sel
= tmp0
;
3200 alu
.src
[2].chan
= 2;
3203 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3208 /* fix the sign of the result */
3212 /* tmp0.x = -tmp0.z */
3213 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3214 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3220 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3221 alu
.src
[1].sel
= tmp0
;
3222 alu
.src
[1].chan
= 2;
3225 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3228 /* sign of the remainder is the same as the sign of src0 */
3229 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3230 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3231 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3234 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3236 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3237 alu
.src
[1].sel
= tmp0
;
3238 alu
.src
[1].chan
= 2;
3239 alu
.src
[2].sel
= tmp0
;
3240 alu
.src
[2].chan
= 0;
3243 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3248 /* tmp0.x = -tmp0.z */
3249 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3250 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3256 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3257 alu
.src
[1].sel
= tmp0
;
3258 alu
.src
[1].chan
= 2;
3261 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3264 /* fix the quotient sign (same as the sign of src0*src1) */
3265 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3266 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3267 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3270 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3272 alu
.src
[0].sel
= tmp2
;
3273 alu
.src
[0].chan
= 2;
3274 alu
.src
[1].sel
= tmp0
;
3275 alu
.src
[1].chan
= 2;
3276 alu
.src
[2].sel
= tmp0
;
3277 alu
.src
[2].chan
= 0;
3280 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
3288 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
3290 return tgsi_divmod(ctx
, 0, 0);
3293 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
3295 return tgsi_divmod(ctx
, 1, 0);
3298 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
3300 return tgsi_divmod(ctx
, 0, 1);
3303 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
3305 return tgsi_divmod(ctx
, 1, 1);
3308 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
3310 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3311 struct r600_bytecode_alu alu
;
3313 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3314 int last_inst
= tgsi_last_instruction(write_mask
);
3317 for (i
= 0; i
< 4; i
++) {
3318 if (!(write_mask
& (1<<i
)))
3321 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3322 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
);
3324 alu
.dst
.sel
= ctx
->temp_reg
;
3328 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3329 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
3333 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3338 /* dst = (src >= 0 ? src : tmp) */
3339 for (i
= 0; i
< 4; i
++) {
3340 if (!(write_mask
& (1<<i
)))
3343 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3344 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3348 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3350 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3351 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3352 alu
.src
[2].sel
= ctx
->temp_reg
;
3353 alu
.src
[2].chan
= i
;
3357 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3364 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
3366 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3367 struct r600_bytecode_alu alu
;
3369 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3370 int last_inst
= tgsi_last_instruction(write_mask
);
3372 /* tmp = (src >= 0 ? src : -1) */
3373 for (i
= 0; i
< 4; i
++) {
3374 if (!(write_mask
& (1<<i
)))
3377 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3378 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT
);
3381 alu
.dst
.sel
= ctx
->temp_reg
;
3385 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3386 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3387 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
3391 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3396 /* dst = (tmp > 0 ? 1 : tmp) */
3397 for (i
= 0; i
< 4; i
++) {
3398 if (!(write_mask
& (1<<i
)))
3401 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3402 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT
);
3406 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3408 alu
.src
[0].sel
= ctx
->temp_reg
;
3409 alu
.src
[0].chan
= i
;
3411 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
3413 alu
.src
[2].sel
= ctx
->temp_reg
;
3414 alu
.src
[2].chan
= i
;
3418 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3427 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
3429 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3430 struct r600_bytecode_alu alu
;
3433 /* tmp = (src > 0 ? 1 : src) */
3434 for (i
= 0; i
< 4; i
++) {
3435 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3436 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
3439 alu
.dst
.sel
= ctx
->temp_reg
;
3442 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3443 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
3444 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
3448 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3453 /* dst = (-tmp > 0 ? -1 : tmp) */
3454 for (i
= 0; i
< 4; i
++) {
3455 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3456 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
3458 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3460 alu
.src
[0].sel
= ctx
->temp_reg
;
3461 alu
.src
[0].chan
= i
;
3464 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
3467 alu
.src
[2].sel
= ctx
->temp_reg
;
3468 alu
.src
[2].chan
= i
;
3472 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3479 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
3481 struct r600_bytecode_alu alu
;
3484 for (i
= 0; i
< 4; i
++) {
3485 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3486 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
3487 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
3490 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3491 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3492 alu
.src
[0].sel
= ctx
->temp_reg
;
3493 alu
.src
[0].chan
= i
;
3498 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3505 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
3507 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3508 struct r600_bytecode_alu alu
;
3510 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
3512 for (i
= 0; i
< lasti
+ 1; i
++) {
3513 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
3516 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3517 alu
.inst
= ctx
->inst_info
->r600_opcode
;
3518 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3519 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
3522 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3529 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3536 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
3538 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3539 struct r600_bytecode_alu alu
;
3542 for (i
= 0; i
< 4; i
++) {
3543 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3544 alu
.inst
= ctx
->inst_info
->r600_opcode
;
3545 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3546 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
3549 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3551 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
3552 /* handle some special cases */
3553 switch (ctx
->inst_info
->tgsi_opcode
) {
3554 case TGSI_OPCODE_DP2
:
3556 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
3557 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
3560 case TGSI_OPCODE_DP3
:
3562 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
3563 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
3566 case TGSI_OPCODE_DPH
:
3568 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3569 alu
.src
[0].chan
= 0;
3579 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3586 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
3589 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3590 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
3591 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
&&
3592 inst
->Src
[index
].Register
.File
!= TGSI_FILE_OUTPUT
) ||
3593 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
;
3596 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
3599 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3600 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
3603 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
3605 static float one_point_five
= 1.5f
;
3606 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3607 struct r600_bytecode_tex tex
;
3608 struct r600_bytecode_alu alu
;
3612 /* Texture fetch instructions can only use gprs as source.
3613 * Also they cannot negate the source or take the absolute value */
3614 const boolean src_requires_loading
= tgsi_tex_src_requires_loading(ctx
, 0);
3615 boolean src_loaded
= FALSE
;
3616 unsigned sampler_src_reg
= 1;
3617 uint8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
3619 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
3621 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
3622 /* get offset values */
3623 if (inst
->Texture
.NumOffsets
) {
3624 assert(inst
->Texture
.NumOffsets
== 1);
3626 offset_x
= ctx
->literals
[inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
3627 offset_y
= ctx
->literals
[inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
3628 offset_z
= ctx
->literals
[inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
3630 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
3631 /* TGSI moves the sampler to src reg 3 for TXD */
3632 sampler_src_reg
= 3;
3634 for (i
= 1; i
< 3; i
++) {
3635 /* set gradients h/v */
3636 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
3637 tex
.inst
= (i
== 1) ? SQ_TEX_INST_SET_GRADIENTS_H
:
3638 SQ_TEX_INST_SET_GRADIENTS_V
;
3639 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
3640 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
3642 if (tgsi_tex_src_requires_loading(ctx
, i
)) {
3643 tex
.src_gpr
= r600_get_temp(ctx
);
3649 for (j
= 0; j
< 4; j
++) {
3650 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3651 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3652 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
3653 alu
.dst
.sel
= tex
.src_gpr
;
3658 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3664 tex
.src_gpr
= tgsi_tex_get_src_gpr(ctx
, i
);
3665 tex
.src_sel_x
= ctx
->src
[i
].swizzle
[0];
3666 tex
.src_sel_y
= ctx
->src
[i
].swizzle
[1];
3667 tex
.src_sel_z
= ctx
->src
[i
].swizzle
[2];
3668 tex
.src_sel_w
= ctx
->src
[i
].swizzle
[3];
3669 tex
.src_rel
= ctx
->src
[i
].rel
;
3671 tex
.dst_gpr
= ctx
->temp_reg
; /* just to avoid confusing the asm scheduler */
3672 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
3673 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
3674 tex
.coord_type_x
= 1;
3675 tex
.coord_type_y
= 1;
3676 tex
.coord_type_z
= 1;
3677 tex
.coord_type_w
= 1;
3679 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
3683 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
3685 /* Add perspective divide */
3686 if (ctx
->bc
->chip_class
== CAYMAN
) {
3688 for (i
= 0; i
< 3; i
++) {
3689 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3690 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3691 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
3693 alu
.dst
.sel
= ctx
->temp_reg
;
3699 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3706 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3707 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3708 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
3710 alu
.dst
.sel
= ctx
->temp_reg
;
3711 alu
.dst
.chan
= out_chan
;
3714 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3719 for (i
= 0; i
< 3; i
++) {
3720 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3721 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
3722 alu
.src
[0].sel
= ctx
->temp_reg
;
3723 alu
.src
[0].chan
= out_chan
;
3724 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
3725 alu
.dst
.sel
= ctx
->temp_reg
;
3728 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3732 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3733 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3734 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
3735 alu
.src
[0].chan
= 0;
3736 alu
.dst
.sel
= ctx
->temp_reg
;
3740 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3744 src_gpr
= ctx
->temp_reg
;
3747 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
3748 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) &&
3749 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
) {
3751 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
3752 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
3754 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3755 for (i
= 0; i
< 4; i
++) {
3756 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3757 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
);
3758 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
3759 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
3760 alu
.dst
.sel
= ctx
->temp_reg
;
3765 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3770 /* tmp1.z = RCP_e(|tmp1.z|) */
3771 if (ctx
->bc
->chip_class
== CAYMAN
) {
3772 for (i
= 0; i
< 3; i
++) {
3773 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3774 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3775 alu
.src
[0].sel
= ctx
->temp_reg
;
3776 alu
.src
[0].chan
= 2;
3778 alu
.dst
.sel
= ctx
->temp_reg
;
3784 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3789 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3790 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
3791 alu
.src
[0].sel
= ctx
->temp_reg
;
3792 alu
.src
[0].chan
= 2;
3794 alu
.dst
.sel
= ctx
->temp_reg
;
3798 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3803 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
3804 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
3805 * muladd has no writemask, have to use another temp
3807 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3808 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
3811 alu
.src
[0].sel
= ctx
->temp_reg
;
3812 alu
.src
[0].chan
= 0;
3813 alu
.src
[1].sel
= ctx
->temp_reg
;
3814 alu
.src
[1].chan
= 2;
3816 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
3817 alu
.src
[2].chan
= 0;
3818 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
3820 alu
.dst
.sel
= ctx
->temp_reg
;
3824 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3828 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3829 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
3832 alu
.src
[0].sel
= ctx
->temp_reg
;
3833 alu
.src
[0].chan
= 1;
3834 alu
.src
[1].sel
= ctx
->temp_reg
;
3835 alu
.src
[1].chan
= 2;
3837 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
3838 alu
.src
[2].chan
= 0;
3839 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
3841 alu
.dst
.sel
= ctx
->temp_reg
;
3846 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3849 /* write initial W value into Z component */
3850 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) {
3851 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3852 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3853 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
3854 alu
.dst
.sel
= ctx
->temp_reg
;
3858 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3863 src_gpr
= ctx
->temp_reg
;
3866 if (src_requires_loading
&& !src_loaded
) {
3867 for (i
= 0; i
< 4; i
++) {
3868 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3869 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
3870 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3871 alu
.dst
.sel
= ctx
->temp_reg
;
3876 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3881 src_gpr
= ctx
->temp_reg
;
3884 opcode
= ctx
->inst_info
->r600_opcode
;
3885 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
3886 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
3887 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
3888 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
3889 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
3890 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
) {
3892 case SQ_TEX_INST_SAMPLE
:
3893 opcode
= SQ_TEX_INST_SAMPLE_C
;
3895 case SQ_TEX_INST_SAMPLE_L
:
3896 opcode
= SQ_TEX_INST_SAMPLE_C_L
;
3898 case SQ_TEX_INST_SAMPLE_LB
:
3899 opcode
= SQ_TEX_INST_SAMPLE_C_LB
;
3901 case SQ_TEX_INST_SAMPLE_G
:
3902 opcode
= SQ_TEX_INST_SAMPLE_C_G
;
3907 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
3910 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
3911 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
3912 tex
.src_gpr
= src_gpr
;
3913 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
3914 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
3915 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
3916 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
3917 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
3924 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
3925 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
3926 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
3927 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
3928 tex
.src_rel
= ctx
->src
[0].rel
;
3931 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
3937 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
) {
3941 tex
.src_sel_w
= 2; /* route Z compare value into W */
3944 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
3945 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
3946 tex
.coord_type_x
= 1;
3947 tex
.coord_type_y
= 1;
3949 tex
.coord_type_z
= 1;
3950 tex
.coord_type_w
= 1;
3952 tex
.offset_x
= offset_x
;
3953 tex
.offset_y
= offset_y
;
3954 tex
.offset_z
= offset_z
;
3956 /* Put the depth for comparison in W.
3957 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
3958 * Some instructions expect the depth in Z. */
3959 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
3960 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
3961 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
3962 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
3963 opcode
!= SQ_TEX_INST_SAMPLE_C_L
&&
3964 opcode
!= SQ_TEX_INST_SAMPLE_C_LB
) {
3965 tex
.src_sel_w
= tex
.src_sel_z
;
3968 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
3969 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
3970 if (opcode
== SQ_TEX_INST_SAMPLE_C_L
||
3971 opcode
== SQ_TEX_INST_SAMPLE_C_LB
) {
3972 /* the array index is read from Y */
3973 tex
.coord_type_y
= 0;
3975 /* the array index is read from Z */
3976 tex
.coord_type_z
= 0;
3977 tex
.src_sel_z
= tex
.src_sel_y
;
3979 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
3980 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)
3981 /* the array index is read from Z */
3982 tex
.coord_type_z
= 0;
3984 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
3988 /* add shadow ambient support - gallium doesn't do it yet */
3992 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
3994 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3995 struct r600_bytecode_alu alu
;
3996 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4000 /* optimize if it's just an equal balance */
4001 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
4002 for (i
= 0; i
< lasti
+ 1; i
++) {
4003 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4006 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4007 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
4008 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
4009 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
4011 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4016 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4024 for (i
= 0; i
< lasti
+ 1; i
++) {
4025 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4028 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4029 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
4030 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4031 alu
.src
[0].chan
= 0;
4032 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4033 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
4034 alu
.dst
.sel
= ctx
->temp_reg
;
4040 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4045 /* (1 - src0) * src2 */
4046 for (i
= 0; i
< lasti
+ 1; i
++) {
4047 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4050 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4051 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4052 alu
.src
[0].sel
= ctx
->temp_reg
;
4053 alu
.src
[0].chan
= i
;
4054 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
4055 alu
.dst
.sel
= ctx
->temp_reg
;
4061 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4066 /* src0 * src1 + (1 - src0) * src2 */
4067 for (i
= 0; i
< lasti
+ 1; i
++) {
4068 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4071 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4072 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
4074 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4075 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
4076 alu
.src
[2].sel
= ctx
->temp_reg
;
4077 alu
.src
[2].chan
= i
;
4079 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4084 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4091 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
4093 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4094 struct r600_bytecode_alu alu
;
4096 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4098 for (i
= 0; i
< lasti
+ 1; i
++) {
4099 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4102 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4103 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
);
4104 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4105 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
4106 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
4107 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4113 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4120 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
4122 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4123 static const unsigned int src0_swizzle
[] = {2, 0, 1};
4124 static const unsigned int src1_swizzle
[] = {1, 2, 0};
4125 struct r600_bytecode_alu alu
;
4126 uint32_t use_temp
= 0;
4129 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
4132 for (i
= 0; i
< 4; i
++) {
4133 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4134 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4136 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
4137 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src1_swizzle
[i
]);
4139 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4140 alu
.src
[0].chan
= i
;
4141 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
4142 alu
.src
[1].chan
= i
;
4145 alu
.dst
.sel
= ctx
->temp_reg
;
4151 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4156 for (i
= 0; i
< 4; i
++) {
4157 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4158 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
4161 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src1_swizzle
[i
]);
4162 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], src0_swizzle
[i
]);
4164 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4165 alu
.src
[0].chan
= i
;
4166 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
4167 alu
.src
[1].chan
= i
;
4170 alu
.src
[2].sel
= ctx
->temp_reg
;
4172 alu
.src
[2].chan
= i
;
4175 alu
.dst
.sel
= ctx
->temp_reg
;
4177 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4183 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4188 return tgsi_helper_copy(ctx
, inst
);
4192 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
4194 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4195 struct r600_bytecode_alu alu
;
4199 /* result.x = 2^floor(src); */
4200 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
4201 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4203 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
4204 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4206 alu
.dst
.sel
= ctx
->temp_reg
;
4210 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4214 if (ctx
->bc
->chip_class
== CAYMAN
) {
4215 for (i
= 0; i
< 3; i
++) {
4216 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4217 alu
.src
[0].sel
= ctx
->temp_reg
;
4218 alu
.src
[0].chan
= 0;
4220 alu
.dst
.sel
= ctx
->temp_reg
;
4226 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4231 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4232 alu
.src
[0].sel
= ctx
->temp_reg
;
4233 alu
.src
[0].chan
= 0;
4235 alu
.dst
.sel
= ctx
->temp_reg
;
4239 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4245 /* result.y = tmp - floor(tmp); */
4246 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
4247 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4249 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
4250 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4252 alu
.dst
.sel
= ctx
->temp_reg
;
4254 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4263 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4268 /* result.z = RoughApprox2ToX(tmp);*/
4269 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
4270 if (ctx
->bc
->chip_class
== CAYMAN
) {
4271 for (i
= 0; i
< 3; i
++) {
4272 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4273 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4274 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4276 alu
.dst
.sel
= ctx
->temp_reg
;
4283 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4288 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4289 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4290 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4292 alu
.dst
.sel
= ctx
->temp_reg
;
4298 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4304 /* result.w = 1.0;*/
4305 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
4306 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4308 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
4309 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4310 alu
.src
[0].chan
= 0;
4312 alu
.dst
.sel
= ctx
->temp_reg
;
4316 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4320 return tgsi_helper_copy(ctx
, inst
);
4323 static int tgsi_log(struct r600_shader_ctx
*ctx
)
4325 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4326 struct r600_bytecode_alu alu
;
4330 /* result.x = floor(log2(|src|)); */
4331 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
4332 if (ctx
->bc
->chip_class
== CAYMAN
) {
4333 for (i
= 0; i
< 3; i
++) {
4334 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4336 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4337 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4338 r600_bytecode_src_set_abs(&alu
.src
[0]);
4340 alu
.dst
.sel
= ctx
->temp_reg
;
4346 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4352 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4354 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4355 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4356 r600_bytecode_src_set_abs(&alu
.src
[0]);
4358 alu
.dst
.sel
= ctx
->temp_reg
;
4362 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4367 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
4368 alu
.src
[0].sel
= ctx
->temp_reg
;
4369 alu
.src
[0].chan
= 0;
4371 alu
.dst
.sel
= ctx
->temp_reg
;
4376 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4381 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4382 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
4384 if (ctx
->bc
->chip_class
== CAYMAN
) {
4385 for (i
= 0; i
< 3; i
++) {
4386 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4388 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4389 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4390 r600_bytecode_src_set_abs(&alu
.src
[0]);
4392 alu
.dst
.sel
= ctx
->temp_reg
;
4399 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4404 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4406 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4407 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4408 r600_bytecode_src_set_abs(&alu
.src
[0]);
4410 alu
.dst
.sel
= ctx
->temp_reg
;
4415 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4420 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4422 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
4423 alu
.src
[0].sel
= ctx
->temp_reg
;
4424 alu
.src
[0].chan
= 1;
4426 alu
.dst
.sel
= ctx
->temp_reg
;
4431 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4435 if (ctx
->bc
->chip_class
== CAYMAN
) {
4436 for (i
= 0; i
< 3; i
++) {
4437 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4438 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4439 alu
.src
[0].sel
= ctx
->temp_reg
;
4440 alu
.src
[0].chan
= 1;
4442 alu
.dst
.sel
= ctx
->temp_reg
;
4449 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4454 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4455 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
4456 alu
.src
[0].sel
= ctx
->temp_reg
;
4457 alu
.src
[0].chan
= 1;
4459 alu
.dst
.sel
= ctx
->temp_reg
;
4464 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4469 if (ctx
->bc
->chip_class
== CAYMAN
) {
4470 for (i
= 0; i
< 3; i
++) {
4471 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4472 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
4473 alu
.src
[0].sel
= ctx
->temp_reg
;
4474 alu
.src
[0].chan
= 1;
4476 alu
.dst
.sel
= ctx
->temp_reg
;
4483 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4488 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4489 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
4490 alu
.src
[0].sel
= ctx
->temp_reg
;
4491 alu
.src
[0].chan
= 1;
4493 alu
.dst
.sel
= ctx
->temp_reg
;
4498 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4503 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4505 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4507 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4508 r600_bytecode_src_set_abs(&alu
.src
[0]);
4510 alu
.src
[1].sel
= ctx
->temp_reg
;
4511 alu
.src
[1].chan
= 1;
4513 alu
.dst
.sel
= ctx
->temp_reg
;
4518 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4523 /* result.z = log2(|src|);*/
4524 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
4525 if (ctx
->bc
->chip_class
== CAYMAN
) {
4526 for (i
= 0; i
< 3; i
++) {
4527 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4529 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4530 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4531 r600_bytecode_src_set_abs(&alu
.src
[0]);
4533 alu
.dst
.sel
= ctx
->temp_reg
;
4540 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4545 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4547 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
4548 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4549 r600_bytecode_src_set_abs(&alu
.src
[0]);
4551 alu
.dst
.sel
= ctx
->temp_reg
;
4556 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4562 /* result.w = 1.0; */
4563 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
4564 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4566 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
4567 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4568 alu
.src
[0].chan
= 0;
4570 alu
.dst
.sel
= ctx
->temp_reg
;
4575 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4580 return tgsi_helper_copy(ctx
, inst
);
4583 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
4585 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4586 struct r600_bytecode_alu alu
;
4589 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4591 switch (inst
->Instruction
.Opcode
) {
4592 case TGSI_OPCODE_ARL
:
4593 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
;
4595 case TGSI_OPCODE_ARR
:
4596 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
4598 case TGSI_OPCODE_UARL
:
4599 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
4606 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4608 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4610 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4614 ctx
->bc
->ar_loaded
= 0;
4617 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
4619 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4620 struct r600_bytecode_alu alu
;
4623 switch (inst
->Instruction
.Opcode
) {
4624 case TGSI_OPCODE_ARL
:
4625 memset(&alu
, 0, sizeof(alu
));
4626 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
;
4627 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4628 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4632 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4635 memset(&alu
, 0, sizeof(alu
));
4636 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
4637 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
4638 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4642 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4645 case TGSI_OPCODE_ARR
:
4646 memset(&alu
, 0, sizeof(alu
));
4647 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
4648 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4649 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4653 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4656 case TGSI_OPCODE_UARL
:
4657 memset(&alu
, 0, sizeof(alu
));
4658 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
4659 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4660 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
4664 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
4672 ctx
->bc
->ar_loaded
= 0;
4676 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
4678 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4679 struct r600_bytecode_alu alu
;
4682 for (i
= 0; i
< 4; i
++) {
4683 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4685 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
4686 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4688 if (i
== 0 || i
== 3) {
4689 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4691 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4694 if (i
== 0 || i
== 2) {
4695 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4697 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
4701 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4708 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
4710 struct r600_bytecode_alu alu
;
4713 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4717 alu
.dst
.sel
= ctx
->temp_reg
;
4721 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4722 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
4723 alu
.src
[1].chan
= 0;
4727 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
4733 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
4735 unsigned force_pop
= ctx
->bc
->force_add_cf
;
4739 if (ctx
->bc
->cf_last
) {
4740 if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
))
4742 else if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
))
4747 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
);
4748 ctx
->bc
->force_add_cf
= 1;
4749 } else if (alu_pop
== 2) {
4750 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
);
4751 ctx
->bc
->force_add_cf
= 1;
4758 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP
));
4759 ctx
->bc
->cf_last
->pop_count
= pops
;
4760 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
4766 static inline void callstack_decrease_current(struct r600_shader_ctx
*ctx
, unsigned reason
)
4770 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
4774 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
-= 4;
4777 /* TOODO : for 16 vp asic should -= 2; */
4778 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
4783 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
)
4785 if (check_max_only
) {
4798 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
) >
4799 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
4800 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
4801 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
;
4807 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
4811 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+= 4;
4814 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
4818 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
) >
4819 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
4820 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
4821 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
;
4825 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
4827 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
4829 sp
->mid
= (struct r600_bytecode_cf
**)realloc((void *)sp
->mid
,
4830 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
4831 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
4835 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
4838 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
4839 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
4842 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
4844 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
4856 static int emit_return(struct r600_shader_ctx
*ctx
)
4858 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN
));
4862 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
4865 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
4866 ctx
->bc
->cf_last
->pop_count
= pops
;
4867 /* XXX work out offset */
4871 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
4876 static void emit_testflag(struct r600_shader_ctx
*ctx
)
4881 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
4884 emit_jump_to_offset(ctx
, 1, 4);
4885 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
4886 pops(ctx
, ifidx
+ 1);
4890 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
4894 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
4895 ctx
->bc
->cf_last
->pop_count
= 1;
4897 fc_set_mid(ctx
, fc_sp
);
4903 static int tgsi_if(struct r600_shader_ctx
*ctx
)
4905 emit_logic_pred(ctx
, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT
));
4907 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
4909 fc_pushlevel(ctx
, FC_IF
);
4911 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
4915 static int tgsi_else(struct r600_shader_ctx
*ctx
)
4917 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE
));
4918 ctx
->bc
->cf_last
->pop_count
= 1;
4920 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
4921 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
4925 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
4928 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
4929 R600_ERR("if/endif unbalanced in shader\n");
4933 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
4934 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
4935 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
4937 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
4941 callstack_decrease_current(ctx
, FC_PUSH_VPM
);
4945 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
4947 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
));
4949 fc_pushlevel(ctx
, FC_LOOP
);
4951 /* check stack depth */
4952 callstack_check_depth(ctx
, FC_LOOP
, 0);
4956 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
4960 r600_bytecode_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
));
4962 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
4963 R600_ERR("loop/endloop in shader code are not paired.\n");
4967 /* fixup loop pointers - from r600isa
4968 LOOP END points to CF after LOOP START,
4969 LOOP START point to CF after LOOP END
4970 BRK/CONT point to LOOP END CF
4972 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
4974 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
4976 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
4977 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
4979 /* XXX add LOOPRET support */
4981 callstack_decrease_current(ctx
, FC_LOOP
);
4985 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
4989 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
4991 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
4996 R600_ERR("Break not inside loop/endloop pair\n");
5000 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
5002 fc_set_mid(ctx
, fscp
);
5004 callstack_check_depth(ctx
, FC_PUSH_VPM
, 1);
5008 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
5010 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5011 struct r600_bytecode_alu alu
;
5013 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
5016 for (i
= 0; i
< lasti
+ 1; i
++) {
5017 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
5020 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5023 alu
.dst
.sel
= ctx
->temp_reg
;
5026 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
);
5027 for (j
= 0; j
< 2; j
++) {
5028 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
5032 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5038 for (i
= 0; i
< lasti
+ 1; i
++) {
5039 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
5042 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5043 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5045 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
5047 alu
.src
[0].sel
= ctx
->temp_reg
;
5048 alu
.src
[0].chan
= i
;
5050 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
5054 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5061 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
5062 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
5063 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5064 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
5067 * For state trackers other than OpenGL, we'll want to use
5068 * _RECIP_IEEE instead.
5070 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
5072 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_rsq
},
5073 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
5074 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
5075 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
5076 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5077 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5078 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5079 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
5080 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
5081 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
5082 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
5083 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
5084 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
5085 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5086 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
5087 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5089 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5090 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5092 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5093 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5094 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
5095 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5096 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
5097 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
, tgsi_op2
},
5098 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
5099 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
5100 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
5101 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
5103 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5104 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5105 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5106 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5107 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
5108 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
5109 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
5110 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
5111 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5112 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5113 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5114 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5115 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5116 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
5117 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5118 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
5119 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
5120 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
5121 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
5122 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5123 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5124 {TGSI_OPCODE_TXD
, 0, SQ_TEX_INST_SAMPLE_G
, tgsi_tex
},
5125 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5126 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5127 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5128 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5129 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5130 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5131 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5132 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
5133 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5134 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5135 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5136 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
5137 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
5138 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
5139 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_LB
, tgsi_tex
},
5140 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5141 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5142 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5143 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
5144 {TGSI_OPCODE_BRK
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
5145 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
5147 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5148 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5149 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
5150 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
5152 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5153 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5154 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5155 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5156 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5157 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
, tgsi_op2_trans
},
5158 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
, tgsi_op2
},
5159 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
5160 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
, tgsi_op2_trans
},
5162 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5163 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
, tgsi_op2
},
5164 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
, tgsi_op2
},
5165 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_imod
},
5166 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
, tgsi_op2
},
5167 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5168 {TGSI_OPCODE_TXF
, 0, SQ_TEX_INST_LD
, tgsi_tex
},
5169 {TGSI_OPCODE_TXQ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5170 {TGSI_OPCODE_CONT
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
5171 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5172 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5173 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
5174 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5175 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
5176 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5178 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5179 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5180 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5181 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5182 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5184 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5185 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5186 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5187 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5188 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5189 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5190 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5191 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5192 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
5193 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
5195 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5196 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
, tgsi_op2_trans
},
5197 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_idiv
},
5198 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
, tgsi_op2
},
5199 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
, tgsi_op2
},
5200 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
, tgsi_ineg
},
5201 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
, tgsi_op2
},
5202 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
, tgsi_op2_trans
},
5203 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
, tgsi_op2_swap
},
5204 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
, tgsi_op2
},
5205 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
, tgsi_op2_trans
},
5206 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
, tgsi_op2
},
5207 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_udiv
},
5208 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umad
},
5209 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
, tgsi_op2
},
5210 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
, tgsi_op2
},
5211 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umod
},
5212 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
, tgsi_op2_trans
},
5213 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
, tgsi_op2
},
5214 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
, tgsi_op2
},
5215 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
, tgsi_op2_trans
},
5216 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
, tgsi_op2_swap
},
5217 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
, tgsi_op2_swap
},
5218 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5219 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5220 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5221 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5222 {TGSI_OPCODE_LOAD
, 0, 0, tgsi_unsupported
},
5223 {TGSI_OPCODE_LOAD_MS
, 0, 0, tgsi_unsupported
},
5224 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
5225 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
5226 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
5227 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
5228 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
5229 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
5230 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
5231 {TGSI_OPCODE_RESINFO
, 0, 0, tgsi_unsupported
},
5232 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
5233 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
5234 {TGSI_OPCODE_UARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
, tgsi_r600_arl
},
5235 {TGSI_OPCODE_UCMP
, 0, 0, tgsi_unsupported
},
5236 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
5237 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
5238 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5241 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
5242 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5243 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5244 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
5245 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
5246 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_rsq
},
5247 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
5248 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
5249 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
5250 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5251 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5252 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5253 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
5254 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
5255 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
5256 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
5257 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
5258 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
5259 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5260 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
5261 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5263 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5264 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5266 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5267 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5268 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
5269 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5270 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
5271 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
, tgsi_op2
},
5272 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
5273 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
5274 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
5275 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
5277 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5278 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5279 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5280 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5281 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
5282 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
5283 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
5284 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
5285 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5286 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5287 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5288 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5289 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5290 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
5291 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5292 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
5293 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
5294 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
5295 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
5296 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5297 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5298 {TGSI_OPCODE_TXD
, 0, SQ_TEX_INST_SAMPLE_G
, tgsi_tex
},
5299 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5300 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5301 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5302 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5303 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5304 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5305 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5306 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5307 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5308 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5309 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5310 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
5311 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
5312 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
5313 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_LB
, tgsi_tex
},
5314 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5315 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5316 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5317 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
5318 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
5319 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
5321 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5322 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5323 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
5324 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
5326 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5327 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5328 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5329 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5330 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5331 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
, tgsi_op2_trans
},
5332 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
, tgsi_op2
},
5333 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
5334 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
, tgsi_op2
},
5336 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5337 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
, tgsi_op2
},
5338 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
, tgsi_op2
},
5339 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_imod
},
5340 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
, tgsi_op2
},
5341 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5342 {TGSI_OPCODE_TXF
, 0, SQ_TEX_INST_LD
, tgsi_tex
},
5343 {TGSI_OPCODE_TXQ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5344 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
5345 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5346 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5347 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
5348 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5349 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
5350 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5352 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5353 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5354 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5355 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5356 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5358 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5359 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5360 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5361 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5362 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5363 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5364 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5365 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5366 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
5367 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
5369 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5370 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
, tgsi_op2
},
5371 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_idiv
},
5372 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
, tgsi_op2
},
5373 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
, tgsi_op2
},
5374 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
, tgsi_ineg
},
5375 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
, tgsi_op2
},
5376 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
, tgsi_op2
},
5377 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
, tgsi_op2_swap
},
5378 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
, tgsi_op2_trans
},
5379 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
, tgsi_op2_trans
},
5380 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
, tgsi_op2
},
5381 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_udiv
},
5382 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umad
},
5383 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
, tgsi_op2
},
5384 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
, tgsi_op2
},
5385 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umod
},
5386 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT
, tgsi_op2_trans
},
5387 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
, tgsi_op2
},
5388 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
, tgsi_op2
},
5389 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
, tgsi_op2
},
5390 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
, tgsi_op2_swap
},
5391 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
, tgsi_op2
},
5392 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5393 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5394 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5395 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5396 {TGSI_OPCODE_LOAD
, 0, 0, tgsi_unsupported
},
5397 {TGSI_OPCODE_LOAD_MS
, 0, 0, tgsi_unsupported
},
5398 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
5399 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
5400 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
5401 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
5402 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
5403 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
5404 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
5405 {TGSI_OPCODE_RESINFO
, 0, 0, tgsi_unsupported
},
5406 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
5407 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
5408 {TGSI_OPCODE_UARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
, tgsi_eg_arl
},
5409 {TGSI_OPCODE_UCMP
, 0, 0, tgsi_unsupported
},
5410 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
5411 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
5412 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5415 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
5416 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5417 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5418 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
5419 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, cayman_emit_float_instr
},
5420 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
5421 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
5422 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
5423 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
5424 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5425 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5426 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5427 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
5428 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
5429 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
5430 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
5431 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
5432 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
5433 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
5434 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
5435 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5437 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5438 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5440 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5441 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5442 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
5443 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5444 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
5445 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE
, tgsi_op2
},
5446 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, cayman_emit_float_instr
},
5447 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, cayman_emit_float_instr
},
5448 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, cayman_pow
},
5449 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
5451 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5452 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
5453 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5454 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5455 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, cayman_trig
},
5456 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
5457 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
5458 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
5459 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5460 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5461 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5462 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5463 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5464 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
5465 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5466 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
5467 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, cayman_trig
},
5468 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
5469 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
5470 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5471 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5472 {TGSI_OPCODE_TXD
, 0, SQ_TEX_INST_SAMPLE_G
, tgsi_tex
},
5473 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
5474 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5475 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5476 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5477 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5478 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5479 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5480 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
5481 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5482 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5483 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5484 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
5485 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
5486 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
5487 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_LB
, tgsi_tex
},
5488 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5489 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5490 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
5491 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
5492 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
5493 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
5495 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5496 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5497 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
5498 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
5500 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5501 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5502 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5503 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5504 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5505 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
, tgsi_op2
},
5506 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT
, tgsi_op2
},
5507 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
5508 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT
, tgsi_op2
},
5510 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5511 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT
, tgsi_op2
},
5512 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT
, tgsi_op2
},
5513 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_imod
},
5514 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT
, tgsi_op2
},
5515 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5516 {TGSI_OPCODE_TXF
, 0, SQ_TEX_INST_LD
, tgsi_tex
},
5517 {TGSI_OPCODE_TXQ
, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO
, tgsi_tex
},
5518 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
5519 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5520 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5521 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
5522 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5523 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
5524 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5526 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5527 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5528 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5529 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5530 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5532 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5533 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5534 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5535 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5536 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5537 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5538 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5539 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5540 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
5541 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
5543 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5544 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
, tgsi_op2
},
5545 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_idiv
},
5546 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT
, tgsi_op2
},
5547 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT
, tgsi_op2
},
5548 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT
, tgsi_ineg
},
5549 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT
, tgsi_op2
},
5550 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT
, tgsi_op2
},
5551 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT
, tgsi_op2_swap
},
5552 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT
, tgsi_op2
},
5553 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT
, tgsi_op2
},
5554 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
, tgsi_op2
},
5555 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_udiv
},
5556 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umad
},
5557 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT
, tgsi_op2
},
5558 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT
, tgsi_op2
},
5559 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_umod
},
5560 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT
, cayman_mul_int_instr
},
5561 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT
, tgsi_op2
},
5562 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT
, tgsi_op2
},
5563 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT
, tgsi_op2
},
5564 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT
, tgsi_op2_swap
},
5565 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT
, tgsi_op2
},
5566 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5567 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5568 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5569 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
5570 {TGSI_OPCODE_LOAD
, 0, 0, tgsi_unsupported
},
5571 {TGSI_OPCODE_LOAD_MS
, 0, 0, tgsi_unsupported
},
5572 {TGSI_OPCODE_SAMPLE
, 0, 0, tgsi_unsupported
},
5573 {TGSI_OPCODE_SAMPLE_B
, 0, 0, tgsi_unsupported
},
5574 {TGSI_OPCODE_SAMPLE_C
, 0, 0, tgsi_unsupported
},
5575 {TGSI_OPCODE_SAMPLE_C_LZ
, 0, 0, tgsi_unsupported
},
5576 {TGSI_OPCODE_SAMPLE_D
, 0, 0, tgsi_unsupported
},
5577 {TGSI_OPCODE_SAMPLE_L
, 0, 0, tgsi_unsupported
},
5578 {TGSI_OPCODE_GATHER4
, 0, 0, tgsi_unsupported
},
5579 {TGSI_OPCODE_RESINFO
, 0, 0, tgsi_unsupported
},
5580 {TGSI_OPCODE_SAMPLE_POS
, 0, 0, tgsi_unsupported
},
5581 {TGSI_OPCODE_SAMPLE_INFO
, 0, 0, tgsi_unsupported
},
5582 {TGSI_OPCODE_UARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
, tgsi_eg_arl
},
5583 {TGSI_OPCODE_UCMP
, 0, 0, tgsi_unsupported
},
5584 {TGSI_OPCODE_IABS
, 0, 0, tgsi_iabs
},
5585 {TGSI_OPCODE_ISSG
, 0, 0, tgsi_issg
},
5586 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},