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r600g: fixup pos/face ena/address properly
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 for (i = 0; i < 10; i++) {
48 spi_vs_out_id[i] = 0;
49 }
50 for (i = 0; i < 32; i++) {
51 tmp = i << ((i & 3) * 8);
52 spi_vs_out_id[i / 4] |= tmp;
53 }
54 for (i = 0; i < 10; i++) {
55 r600_pipe_state_add_reg(rstate,
56 R_028614_SPI_VS_OUT_ID_0 + i * 4,
57 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
58 }
59
60 r600_pipe_state_add_reg(rstate,
61 R_0286C4_SPI_VS_OUT_CONFIG,
62 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
63 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate,
65 R_028868_SQ_PGM_RESOURCES_VS,
66 S_028868_NUM_GPRS(rshader->bc.ngpr) |
67 S_028868_STACK_SIZE(rshader->bc.nstack),
68 0xFFFFFFFF, NULL);
69 r600_pipe_state_add_reg(rstate,
70 R_0288A4_SQ_PGM_RESOURCES_FS,
71 0x00000000, 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS,
77 0x00000000, 0xFFFFFFFF, NULL);
78 r600_pipe_state_add_reg(rstate,
79 R_028858_SQ_PGM_START_VS,
80 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
81 r600_pipe_state_add_reg(rstate,
82 R_028894_SQ_PGM_START_FS,
83 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
84
85 r600_pipe_state_add_reg(rstate,
86 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
87 0xFFFFFFFF, NULL);
88
89 }
90
91 int r600_find_vs_semantic_index(struct r600_shader *vs,
92 struct r600_shader *ps, int id)
93 {
94 struct r600_shader_io *input = &ps->input[id];
95
96 for (int i = 0; i < vs->noutput; i++) {
97 if (input->name == vs->output[i].name &&
98 input->sid == vs->output[i].sid) {
99 return i - 1;
100 }
101 }
102 return 0;
103 }
104
105 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
106 {
107 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
108 struct r600_pipe_state *rstate = &shader->rstate;
109 struct r600_shader *rshader = &shader->shader;
110 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
111 int pos_index = -1, face_index = -1;
112
113 /* clear previous register */
114 rstate->nregs = 0;
115
116 for (i = 0; i < rshader->ninput; i++) {
117 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
118 if (rshader->input[i].centroid)
119 tmp |= S_028644_SEL_CENTROID(1);
120 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
121 pos_index = i;
122 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
123 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
124 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
125 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
126 }
127 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
128 face_index = i;
129 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
130 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
131 tmp |= S_028644_PT_SPRITE_TEX(1);
132 }
133 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
134 }
135 for (i = 0; i < rshader->noutput; i++) {
136 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
137 r600_pipe_state_add_reg(rstate,
138 R_02880C_DB_SHADER_CONTROL,
139 S_02880C_Z_EXPORT_ENABLE(1),
140 S_02880C_Z_EXPORT_ENABLE(1), NULL);
141 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
142 r600_pipe_state_add_reg(rstate,
143 R_02880C_DB_SHADER_CONTROL,
144 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
145 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
146 }
147
148 exports_ps = 0;
149 num_cout = 0;
150 for (i = 0; i < rshader->noutput; i++) {
151 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
152 exports_ps |= 1;
153 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
154 num_cout++;
155 }
156 }
157 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
158 if (!exports_ps) {
159 /* always at least export 1 component per pixel */
160 exports_ps = 2;
161 }
162
163 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
164 S_0286CC_PERSP_GRADIENT_ENA(1);
165 spi_input_z = 0;
166 if (pos_index != -1) {
167 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
168 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
169 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
170 S_0286CC_BARYC_SAMPLE_CNTL(1));
171 spi_input_z |= 1;
172 }
173
174 spi_ps_in_control_1 = 0;
175 if (face_index != -1) {
176 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
177 S_286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
178 }
179
180 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
181 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
182 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
183 r600_pipe_state_add_reg(rstate,
184 R_028840_SQ_PGM_START_PS,
185 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
186 r600_pipe_state_add_reg(rstate,
187 R_028850_SQ_PGM_RESOURCES_PS,
188 S_028868_NUM_GPRS(rshader->bc.ngpr) |
189 S_028868_STACK_SIZE(rshader->bc.nstack),
190 0xFFFFFFFF, NULL);
191 r600_pipe_state_add_reg(rstate,
192 R_028854_SQ_PGM_EXPORTS_PS,
193 exports_ps, 0xFFFFFFFF, NULL);
194 r600_pipe_state_add_reg(rstate,
195 R_0288CC_SQ_PGM_CF_OFFSET_PS,
196 0x00000000, 0xFFFFFFFF, NULL);
197
198 if (rshader->uses_kill) {
199 /* only set some bits here, the other bits are set in the dsa state */
200 r600_pipe_state_add_reg(rstate,
201 R_02880C_DB_SHADER_CONTROL,
202 S_02880C_KILL_ENABLE(1),
203 S_02880C_KILL_ENABLE(1), NULL);
204 }
205 r600_pipe_state_add_reg(rstate,
206 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
207 0xFFFFFFFF, NULL);
208 }
209
210 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
211 {
212 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
213 struct r600_shader *rshader = &shader->shader;
214 void *ptr;
215
216 /* copy new shader */
217 if (shader->bo == NULL) {
218 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
219 if (shader->bo == NULL) {
220 return -ENOMEM;
221 }
222 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
223 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
224 r600_bo_unmap(rctx->radeon, shader->bo);
225 }
226 /* build state */
227 rshader->flat_shade = rctx->flatshade;
228 switch (rshader->processor_type) {
229 case TGSI_PROCESSOR_VERTEX:
230 if (rshader->family >= CHIP_CEDAR) {
231 evergreen_pipe_shader_vs(ctx, shader);
232 } else {
233 r600_pipe_shader_vs(ctx, shader);
234 }
235 break;
236 case TGSI_PROCESSOR_FRAGMENT:
237 if (rshader->family >= CHIP_CEDAR) {
238 evergreen_pipe_shader_ps(ctx, shader);
239 } else {
240 r600_pipe_shader_ps(ctx, shader);
241 }
242 break;
243 default:
244 return -EINVAL;
245 }
246 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
247 return 0;
248 }
249
250 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
251 {
252 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
253 struct r600_shader *shader = &rshader->shader;
254 const struct util_format_description *desc;
255 enum pipe_format resource_format[160];
256 unsigned i, nresources = 0;
257 struct r600_bc *bc = &shader->bc;
258 struct r600_bc_cf *cf;
259 struct r600_bc_vtx *vtx;
260
261 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
262 return 0;
263 /* doing a full memcmp fell over the refcount */
264 if ((rshader->vertex_elements.count == rctx->vertex_elements->count) &&
265 (!memcmp(&rshader->vertex_elements.elements, &rctx->vertex_elements->elements, 32 * sizeof(struct pipe_vertex_element)))) {
266 return 0;
267 }
268 rshader->vertex_elements = *rctx->vertex_elements;
269 for (i = 0; i < rctx->vertex_elements->count; i++) {
270 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
271 }
272 r600_bo_reference(rctx->radeon, &rshader->bo, NULL);
273 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
274 switch (cf->inst) {
275 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
276 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
277 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
278 desc = util_format_description(resource_format[vtx->buffer_id]);
279 if (desc == NULL) {
280 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
281 return -EINVAL;
282 }
283 vtx->dst_sel_x = desc->swizzle[0];
284 vtx->dst_sel_y = desc->swizzle[1];
285 vtx->dst_sel_z = desc->swizzle[2];
286 vtx->dst_sel_w = desc->swizzle[3];
287 }
288 break;
289 default:
290 break;
291 }
292 }
293 return r600_bc_build(&shader->bc);
294 }
295
296 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
297 {
298 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
299 int r;
300
301 if (shader == NULL)
302 return -EINVAL;
303 /* there should be enough input */
304 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
305 R600_ERR("%d resources provided, expecting %d\n",
306 rctx->vertex_elements->count, shader->shader.bc.nresource);
307 return -EINVAL;
308 }
309 r = r600_shader_update(ctx, shader);
310 if (r)
311 return r;
312 return r600_pipe_shader(ctx, shader);
313 }
314
315 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
316 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
317 {
318 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
319 int r;
320
321 //fprintf(stderr, "--------------------------------------------------------------\n");
322 //tgsi_dump(tokens, 0);
323 shader->shader.family = r600_get_family(rctx->radeon);
324 r = r600_shader_from_tgsi(tokens, &shader->shader);
325 if (r) {
326 R600_ERR("translation from TGSI failed !\n");
327 return r;
328 }
329 r = r600_bc_build(&shader->shader.bc);
330 if (r) {
331 R600_ERR("building bytecode failed !\n");
332 return r;
333 }
334 //fprintf(stderr, "______________________________________________________________\n");
335 return 0;
336 }
337
338 /*
339 * tgsi -> r600 shader
340 */
341 struct r600_shader_tgsi_instruction;
342
343 struct r600_shader_ctx {
344 struct tgsi_shader_info info;
345 struct tgsi_parse_context parse;
346 const struct tgsi_token *tokens;
347 unsigned type;
348 unsigned file_offset[TGSI_FILE_COUNT];
349 unsigned temp_reg;
350 struct r600_shader_tgsi_instruction *inst_info;
351 struct r600_bc *bc;
352 struct r600_shader *shader;
353 u32 value[4];
354 u32 *literals;
355 u32 nliterals;
356 u32 max_driver_temp_used;
357 };
358
359 struct r600_shader_tgsi_instruction {
360 unsigned tgsi_opcode;
361 unsigned is_op3;
362 unsigned r600_opcode;
363 int (*process)(struct r600_shader_ctx *ctx);
364 };
365
366 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
367 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
368
369 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
370 {
371 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
372 int j;
373
374 if (i->Instruction.NumDstRegs > 1) {
375 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
376 return -EINVAL;
377 }
378 if (i->Instruction.Predicate) {
379 R600_ERR("predicate unsupported\n");
380 return -EINVAL;
381 }
382 #if 0
383 if (i->Instruction.Label) {
384 R600_ERR("label unsupported\n");
385 return -EINVAL;
386 }
387 #endif
388 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
389 if (i->Src[j].Register.Dimension ||
390 i->Src[j].Register.Absolute) {
391 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
392 i->Src[j].Register.Dimension,
393 i->Src[j].Register.Absolute);
394 return -EINVAL;
395 }
396 }
397 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
398 if (i->Dst[j].Register.Dimension) {
399 R600_ERR("unsupported dst (dimension)\n");
400 return -EINVAL;
401 }
402 }
403 return 0;
404 }
405
406 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
407 {
408 int i, r;
409 struct r600_bc_alu alu;
410
411 for (i = 0; i < 8; i++) {
412 memset(&alu, 0, sizeof(struct r600_bc_alu));
413
414 if (i < 4)
415 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
416 else
417 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
418
419 if ((i > 1) && (i < 6)) {
420 alu.dst.sel = ctx->shader->input[gpr].gpr;
421 alu.dst.write = 1;
422 }
423
424 alu.dst.chan = i % 4;
425 alu.src[0].chan = (1 - (i % 2));
426 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
427
428 alu.bank_swizzle_force = SQ_ALU_VEC_210;
429 if ((i % 4) == 3)
430 alu.last = 1;
431 r = r600_bc_add_alu(ctx->bc, &alu);
432 if (r)
433 return r;
434 }
435 return 0;
436 }
437
438
439 static int tgsi_declaration(struct r600_shader_ctx *ctx)
440 {
441 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
442 struct r600_bc_vtx vtx;
443 unsigned i;
444 int r;
445
446 switch (d->Declaration.File) {
447 case TGSI_FILE_INPUT:
448 i = ctx->shader->ninput++;
449 ctx->shader->input[i].name = d->Semantic.Name;
450 ctx->shader->input[i].sid = d->Semantic.Index;
451 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
452 ctx->shader->input[i].centroid = d->Declaration.Centroid;
453 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
454 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
455 /* turn input into fetch */
456 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
457 vtx.inst = 0;
458 vtx.fetch_type = 0;
459 vtx.buffer_id = i;
460 /* register containing the index into the buffer */
461 vtx.src_gpr = 0;
462 vtx.src_sel_x = 0;
463 vtx.mega_fetch_count = 0x1F;
464 vtx.dst_gpr = ctx->shader->input[i].gpr;
465 vtx.dst_sel_x = 0;
466 vtx.dst_sel_y = 1;
467 vtx.dst_sel_z = 2;
468 vtx.dst_sel_w = 3;
469 vtx.use_const_fields = 1;
470 r = r600_bc_add_vtx(ctx->bc, &vtx);
471 if (r)
472 return r;
473 }
474 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
475 /* turn input into interpolate on EG */
476 evergreen_interp_alu(ctx, i);
477 }
478 break;
479 case TGSI_FILE_OUTPUT:
480 i = ctx->shader->noutput++;
481 ctx->shader->output[i].name = d->Semantic.Name;
482 ctx->shader->output[i].sid = d->Semantic.Index;
483 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
484 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
485 break;
486 case TGSI_FILE_CONSTANT:
487 case TGSI_FILE_TEMPORARY:
488 case TGSI_FILE_SAMPLER:
489 case TGSI_FILE_ADDRESS:
490 break;
491 default:
492 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
493 return -EINVAL;
494 }
495 return 0;
496 }
497
498 static int r600_get_temp(struct r600_shader_ctx *ctx)
499 {
500 return ctx->temp_reg + ctx->max_driver_temp_used++;
501 }
502
503 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
504 {
505 struct tgsi_full_immediate *immediate;
506 struct r600_shader_ctx ctx;
507 struct r600_bc_output output[32];
508 unsigned output_done, noutput;
509 unsigned opcode;
510 int i, r = 0, pos0;
511
512 ctx.bc = &shader->bc;
513 ctx.shader = shader;
514 r = r600_bc_init(ctx.bc, shader->family);
515 if (r)
516 return r;
517 ctx.tokens = tokens;
518 tgsi_scan_shader(tokens, &ctx.info);
519 tgsi_parse_init(&ctx.parse, tokens);
520 ctx.type = ctx.parse.FullHeader.Processor.Processor;
521 shader->processor_type = ctx.type;
522
523 /* register allocations */
524 /* Values [0,127] correspond to GPR[0..127].
525 * Values [128,159] correspond to constant buffer bank 0
526 * Values [160,191] correspond to constant buffer bank 1
527 * Values [256,511] correspond to cfile constants c[0..255].
528 * Other special values are shown in the list below.
529 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
530 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
531 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
532 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
533 * 248 SQ_ALU_SRC_0: special constant 0.0.
534 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
535 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
536 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
537 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
538 * 253 SQ_ALU_SRC_LITERAL: literal constant.
539 * 254 SQ_ALU_SRC_PV: previous vector result.
540 * 255 SQ_ALU_SRC_PS: previous scalar result.
541 */
542 for (i = 0; i < TGSI_FILE_COUNT; i++) {
543 ctx.file_offset[i] = 0;
544 }
545 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
546 ctx.file_offset[TGSI_FILE_INPUT] = 1;
547 }
548 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == 2) {
549 ctx.file_offset[TGSI_FILE_INPUT] = 1;
550 }
551 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
552 ctx.info.file_count[TGSI_FILE_INPUT];
553 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
554 ctx.info.file_count[TGSI_FILE_OUTPUT];
555
556 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
557
558 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
559 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
560 ctx.info.file_count[TGSI_FILE_TEMPORARY];
561
562 ctx.nliterals = 0;
563 ctx.literals = NULL;
564
565 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
566 tgsi_parse_token(&ctx.parse);
567 switch (ctx.parse.FullToken.Token.Type) {
568 case TGSI_TOKEN_TYPE_IMMEDIATE:
569 immediate = &ctx.parse.FullToken.FullImmediate;
570 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
571 if(ctx.literals == NULL) {
572 r = -ENOMEM;
573 goto out_err;
574 }
575 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
576 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
577 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
578 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
579 ctx.nliterals++;
580 break;
581 case TGSI_TOKEN_TYPE_DECLARATION:
582 r = tgsi_declaration(&ctx);
583 if (r)
584 goto out_err;
585 break;
586 case TGSI_TOKEN_TYPE_INSTRUCTION:
587 r = tgsi_is_supported(&ctx);
588 if (r)
589 goto out_err;
590 ctx.max_driver_temp_used = 0;
591 /* reserve first tmp for everyone */
592 r600_get_temp(&ctx);
593 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
594 if (ctx.bc->chiprev == 2)
595 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
596 else
597 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
598 r = ctx.inst_info->process(&ctx);
599 if (r)
600 goto out_err;
601 r = r600_bc_add_literal(ctx.bc, ctx.value);
602 if (r)
603 goto out_err;
604 break;
605 default:
606 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
607 r = -EINVAL;
608 goto out_err;
609 }
610 }
611 /* export output */
612 noutput = shader->noutput;
613 for (i = 0, pos0 = 0; i < noutput; i++) {
614 memset(&output[i], 0, sizeof(struct r600_bc_output));
615 output[i].gpr = shader->output[i].gpr;
616 output[i].elem_size = 3;
617 output[i].swizzle_x = 0;
618 output[i].swizzle_y = 1;
619 output[i].swizzle_z = 2;
620 output[i].swizzle_w = 3;
621 output[i].barrier = 1;
622 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
623 output[i].array_base = i - pos0;
624 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
625 switch (ctx.type) {
626 case TGSI_PROCESSOR_VERTEX:
627 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
628 output[i].array_base = 60;
629 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
630 /* position doesn't count in array_base */
631 pos0++;
632 }
633 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
634 output[i].array_base = 61;
635 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
636 /* position doesn't count in array_base */
637 pos0++;
638 }
639 break;
640 case TGSI_PROCESSOR_FRAGMENT:
641 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
642 output[i].array_base = shader->output[i].sid;
643 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
644 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
645 output[i].array_base = 61;
646 output[i].swizzle_x = 2;
647 output[i].swizzle_y = 7;
648 output[i].swizzle_z = output[i].swizzle_w = 7;
649 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
650 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
651 output[i].array_base = 61;
652 output[i].swizzle_x = 7;
653 output[i].swizzle_y = 1;
654 output[i].swizzle_z = output[i].swizzle_w = 7;
655 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
656 } else {
657 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
658 r = -EINVAL;
659 goto out_err;
660 }
661 break;
662 default:
663 R600_ERR("unsupported processor type %d\n", ctx.type);
664 r = -EINVAL;
665 goto out_err;
666 }
667 }
668 /* add fake param output for vertex shader if no param is exported */
669 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
670 for (i = 0, pos0 = 0; i < noutput; i++) {
671 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
672 pos0 = 1;
673 break;
674 }
675 }
676 if (!pos0) {
677 memset(&output[i], 0, sizeof(struct r600_bc_output));
678 output[i].gpr = 0;
679 output[i].elem_size = 3;
680 output[i].swizzle_x = 0;
681 output[i].swizzle_y = 1;
682 output[i].swizzle_z = 2;
683 output[i].swizzle_w = 3;
684 output[i].barrier = 1;
685 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
686 output[i].array_base = 0;
687 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
688 noutput++;
689 }
690 }
691 /* add fake pixel export */
692 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
693 memset(&output[0], 0, sizeof(struct r600_bc_output));
694 output[0].gpr = 0;
695 output[0].elem_size = 3;
696 output[0].swizzle_x = 7;
697 output[0].swizzle_y = 7;
698 output[0].swizzle_z = 7;
699 output[0].swizzle_w = 7;
700 output[0].barrier = 1;
701 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
702 output[0].array_base = 0;
703 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
704 noutput++;
705 }
706 /* set export done on last export of each type */
707 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
708 if (i == (noutput - 1)) {
709 output[i].end_of_program = 1;
710 }
711 if (!(output_done & (1 << output[i].type))) {
712 output_done |= (1 << output[i].type);
713 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
714 }
715 }
716 /* add output to bytecode */
717 for (i = 0; i < noutput; i++) {
718 r = r600_bc_add_output(ctx.bc, &output[i]);
719 if (r)
720 goto out_err;
721 }
722 free(ctx.literals);
723 tgsi_parse_free(&ctx.parse);
724 return 0;
725 out_err:
726 free(ctx.literals);
727 tgsi_parse_free(&ctx.parse);
728 return r;
729 }
730
731 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
732 {
733 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
734 return -EINVAL;
735 }
736
737 static int tgsi_end(struct r600_shader_ctx *ctx)
738 {
739 return 0;
740 }
741
742 static int tgsi_src(struct r600_shader_ctx *ctx,
743 const struct tgsi_full_src_register *tgsi_src,
744 struct r600_bc_alu_src *r600_src)
745 {
746 int index;
747 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
748 r600_src->sel = tgsi_src->Register.Index;
749 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
750 r600_src->sel = 0;
751 index = tgsi_src->Register.Index;
752 ctx->value[0] = ctx->literals[index * 4 + 0];
753 ctx->value[1] = ctx->literals[index * 4 + 1];
754 ctx->value[2] = ctx->literals[index * 4 + 2];
755 ctx->value[3] = ctx->literals[index * 4 + 3];
756 }
757 if (tgsi_src->Register.Indirect)
758 r600_src->rel = V_SQ_REL_RELATIVE;
759 r600_src->neg = tgsi_src->Register.Negate;
760 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
761 return 0;
762 }
763
764 static int tgsi_dst(struct r600_shader_ctx *ctx,
765 const struct tgsi_full_dst_register *tgsi_dst,
766 unsigned swizzle,
767 struct r600_bc_alu_dst *r600_dst)
768 {
769 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
770
771 r600_dst->sel = tgsi_dst->Register.Index;
772 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
773 r600_dst->chan = swizzle;
774 r600_dst->write = 1;
775 if (tgsi_dst->Register.Indirect)
776 r600_dst->rel = V_SQ_REL_RELATIVE;
777 if (inst->Instruction.Saturate) {
778 r600_dst->clamp = 1;
779 }
780 return 0;
781 }
782
783 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
784 {
785 switch (swizzle) {
786 case 0:
787 return tgsi_src->Register.SwizzleX;
788 case 1:
789 return tgsi_src->Register.SwizzleY;
790 case 2:
791 return tgsi_src->Register.SwizzleZ;
792 case 3:
793 return tgsi_src->Register.SwizzleW;
794 default:
795 return 0;
796 }
797 }
798
799 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
800 {
801 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
802 struct r600_bc_alu alu;
803 int i, j, k, nconst, r;
804
805 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
806 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
807 nconst++;
808 }
809 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
810 if (r) {
811 return r;
812 }
813 }
814 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
815 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
816 int treg = r600_get_temp(ctx);
817 for (k = 0; k < 4; k++) {
818 memset(&alu, 0, sizeof(struct r600_bc_alu));
819 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
820 alu.src[0].sel = r600_src[i].sel;
821 alu.src[0].chan = k;
822 alu.src[0].rel = r600_src[i].rel;
823 alu.dst.sel = treg;
824 alu.dst.chan = k;
825 alu.dst.write = 1;
826 if (k == 3)
827 alu.last = 1;
828 r = r600_bc_add_alu(ctx->bc, &alu);
829 if (r)
830 return r;
831 }
832 r600_src[i].sel = treg;
833 r600_src[i].rel =0;
834 j--;
835 }
836 }
837 return 0;
838 }
839
840 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
841 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
842 {
843 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
844 struct r600_bc_alu alu;
845 int i, j, k, nliteral, r;
846
847 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
848 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
849 nliteral++;
850 }
851 }
852 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
853 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
854 int treg = r600_get_temp(ctx);
855 for (k = 0; k < 4; k++) {
856 memset(&alu, 0, sizeof(struct r600_bc_alu));
857 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
858 alu.src[0].sel = r600_src[i].sel;
859 alu.src[0].chan = k;
860 alu.dst.sel = treg;
861 alu.dst.chan = k;
862 alu.dst.write = 1;
863 if (k == 3)
864 alu.last = 1;
865 r = r600_bc_add_alu(ctx->bc, &alu);
866 if (r)
867 return r;
868 }
869 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
870 if (r)
871 return r;
872 r600_src[i].sel = treg;
873 j--;
874 }
875 }
876 return 0;
877 }
878
879 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
880 {
881 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
882 struct r600_bc_alu_src r600_src[3];
883 struct r600_bc_alu alu;
884 int i, j, r;
885 int lasti = 0;
886
887 for (i = 0; i < 4; i++) {
888 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
889 lasti = i;
890 }
891 }
892
893 r = tgsi_split_constant(ctx, r600_src);
894 if (r)
895 return r;
896 r = tgsi_split_literal_constant(ctx, r600_src);
897 if (r)
898 return r;
899 for (i = 0; i < lasti + 1; i++) {
900 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
901 continue;
902
903 memset(&alu, 0, sizeof(struct r600_bc_alu));
904 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
905 if (r)
906 return r;
907
908 alu.inst = ctx->inst_info->r600_opcode;
909 if (!swap) {
910 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
911 alu.src[j] = r600_src[j];
912 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
913 }
914 } else {
915 alu.src[0] = r600_src[1];
916 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
917
918 alu.src[1] = r600_src[0];
919 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
920 }
921 /* handle some special cases */
922 switch (ctx->inst_info->tgsi_opcode) {
923 case TGSI_OPCODE_SUB:
924 alu.src[1].neg = 1;
925 break;
926 case TGSI_OPCODE_ABS:
927 alu.src[0].abs = 1;
928 break;
929 default:
930 break;
931 }
932 if (i == lasti) {
933 alu.last = 1;
934 }
935 r = r600_bc_add_alu(ctx->bc, &alu);
936 if (r)
937 return r;
938 }
939 return 0;
940 }
941
942 static int tgsi_op2(struct r600_shader_ctx *ctx)
943 {
944 return tgsi_op2_s(ctx, 0);
945 }
946
947 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
948 {
949 return tgsi_op2_s(ctx, 1);
950 }
951
952 /*
953 * r600 - trunc to -PI..PI range
954 * r700 - normalize by dividing by 2PI
955 * see fdo bug 27901
956 */
957 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
958 struct r600_bc_alu_src r600_src[3])
959 {
960 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
961 int r;
962 uint32_t lit_vals[4];
963 struct r600_bc_alu alu;
964
965 memset(lit_vals, 0, 4*4);
966 r = tgsi_split_constant(ctx, r600_src);
967 if (r)
968 return r;
969 r = tgsi_split_literal_constant(ctx, r600_src);
970 if (r)
971 return r;
972
973 r = tgsi_split_literal_constant(ctx, r600_src);
974 if (r)
975 return r;
976
977 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
978 lit_vals[1] = fui(0.5f);
979
980 memset(&alu, 0, sizeof(struct r600_bc_alu));
981 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
982 alu.is_op3 = 1;
983
984 alu.dst.chan = 0;
985 alu.dst.sel = ctx->temp_reg;
986 alu.dst.write = 1;
987
988 alu.src[0] = r600_src[0];
989 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
990
991 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
992 alu.src[1].chan = 0;
993 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
994 alu.src[2].chan = 1;
995 alu.last = 1;
996 r = r600_bc_add_alu(ctx->bc, &alu);
997 if (r)
998 return r;
999 r = r600_bc_add_literal(ctx->bc, lit_vals);
1000 if (r)
1001 return r;
1002
1003 memset(&alu, 0, sizeof(struct r600_bc_alu));
1004 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1005
1006 alu.dst.chan = 0;
1007 alu.dst.sel = ctx->temp_reg;
1008 alu.dst.write = 1;
1009
1010 alu.src[0].sel = ctx->temp_reg;
1011 alu.src[0].chan = 0;
1012 alu.last = 1;
1013 r = r600_bc_add_alu(ctx->bc, &alu);
1014 if (r)
1015 return r;
1016
1017 if (ctx->bc->chiprev == 0) {
1018 lit_vals[0] = fui(3.1415926535897f * 2.0f);
1019 lit_vals[1] = fui(-3.1415926535897f);
1020 } else {
1021 lit_vals[0] = fui(1.0f);
1022 lit_vals[1] = fui(-0.5f);
1023 }
1024
1025 memset(&alu, 0, sizeof(struct r600_bc_alu));
1026 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1027 alu.is_op3 = 1;
1028
1029 alu.dst.chan = 0;
1030 alu.dst.sel = ctx->temp_reg;
1031 alu.dst.write = 1;
1032
1033 alu.src[0].sel = ctx->temp_reg;
1034 alu.src[0].chan = 0;
1035
1036 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1037 alu.src[1].chan = 0;
1038 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1039 alu.src[2].chan = 1;
1040 alu.last = 1;
1041 r = r600_bc_add_alu(ctx->bc, &alu);
1042 if (r)
1043 return r;
1044 r = r600_bc_add_literal(ctx->bc, lit_vals);
1045 if (r)
1046 return r;
1047 return 0;
1048 }
1049
1050 static int tgsi_trig(struct r600_shader_ctx *ctx)
1051 {
1052 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1053 struct r600_bc_alu_src r600_src[3];
1054 struct r600_bc_alu alu;
1055 int i, r;
1056 int lasti = 0;
1057
1058 r = tgsi_setup_trig(ctx, r600_src);
1059 if (r)
1060 return r;
1061
1062 memset(&alu, 0, sizeof(struct r600_bc_alu));
1063 alu.inst = ctx->inst_info->r600_opcode;
1064 alu.dst.chan = 0;
1065 alu.dst.sel = ctx->temp_reg;
1066 alu.dst.write = 1;
1067
1068 alu.src[0].sel = ctx->temp_reg;
1069 alu.src[0].chan = 0;
1070 alu.last = 1;
1071 r = r600_bc_add_alu(ctx->bc, &alu);
1072 if (r)
1073 return r;
1074
1075 /* replicate result */
1076 for (i = 0; i < 4; i++) {
1077 if (inst->Dst[0].Register.WriteMask & (1 << i))
1078 lasti = i;
1079 }
1080 for (i = 0; i < lasti + 1; i++) {
1081 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1082 continue;
1083
1084 memset(&alu, 0, sizeof(struct r600_bc_alu));
1085 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1086
1087 alu.src[0].sel = ctx->temp_reg;
1088 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1089 if (r)
1090 return r;
1091 if (i == lasti)
1092 alu.last = 1;
1093 r = r600_bc_add_alu(ctx->bc, &alu);
1094 if (r)
1095 return r;
1096 }
1097 return 0;
1098 }
1099
1100 static int tgsi_scs(struct r600_shader_ctx *ctx)
1101 {
1102 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1103 struct r600_bc_alu_src r600_src[3];
1104 struct r600_bc_alu alu;
1105 int r;
1106
1107 /* We'll only need the trig stuff if we are going to write to the
1108 * X or Y components of the destination vector.
1109 */
1110 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1111 r = tgsi_setup_trig(ctx, r600_src);
1112 if (r)
1113 return r;
1114 }
1115
1116 /* dst.x = COS */
1117 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1118 memset(&alu, 0, sizeof(struct r600_bc_alu));
1119 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1120 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1121 if (r)
1122 return r;
1123
1124 alu.src[0].sel = ctx->temp_reg;
1125 alu.src[0].chan = 0;
1126 alu.last = 1;
1127 r = r600_bc_add_alu(ctx->bc, &alu);
1128 if (r)
1129 return r;
1130 }
1131
1132 /* dst.y = SIN */
1133 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1134 memset(&alu, 0, sizeof(struct r600_bc_alu));
1135 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1136 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1137 if (r)
1138 return r;
1139
1140 alu.src[0].sel = ctx->temp_reg;
1141 alu.src[0].chan = 0;
1142 alu.last = 1;
1143 r = r600_bc_add_alu(ctx->bc, &alu);
1144 if (r)
1145 return r;
1146 }
1147
1148 /* dst.z = 0.0; */
1149 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1150 memset(&alu, 0, sizeof(struct r600_bc_alu));
1151
1152 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1153
1154 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1155 if (r)
1156 return r;
1157
1158 alu.src[0].sel = V_SQ_ALU_SRC_0;
1159 alu.src[0].chan = 0;
1160
1161 alu.last = 1;
1162
1163 r = r600_bc_add_alu(ctx->bc, &alu);
1164 if (r)
1165 return r;
1166
1167 r = r600_bc_add_literal(ctx->bc, ctx->value);
1168 if (r)
1169 return r;
1170 }
1171
1172 /* dst.w = 1.0; */
1173 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1174 memset(&alu, 0, sizeof(struct r600_bc_alu));
1175
1176 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1177
1178 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1179 if (r)
1180 return r;
1181
1182 alu.src[0].sel = V_SQ_ALU_SRC_1;
1183 alu.src[0].chan = 0;
1184
1185 alu.last = 1;
1186
1187 r = r600_bc_add_alu(ctx->bc, &alu);
1188 if (r)
1189 return r;
1190
1191 r = r600_bc_add_literal(ctx->bc, ctx->value);
1192 if (r)
1193 return r;
1194 }
1195
1196 return 0;
1197 }
1198
1199 static int tgsi_kill(struct r600_shader_ctx *ctx)
1200 {
1201 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1202 struct r600_bc_alu alu;
1203 int i, r;
1204
1205 for (i = 0; i < 4; i++) {
1206 memset(&alu, 0, sizeof(struct r600_bc_alu));
1207 alu.inst = ctx->inst_info->r600_opcode;
1208
1209 alu.dst.chan = i;
1210
1211 alu.src[0].sel = V_SQ_ALU_SRC_0;
1212
1213 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1214 alu.src[1].sel = V_SQ_ALU_SRC_1;
1215 alu.src[1].neg = 1;
1216 } else {
1217 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1218 if (r)
1219 return r;
1220 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1221 }
1222 if (i == 3) {
1223 alu.last = 1;
1224 }
1225 r = r600_bc_add_alu(ctx->bc, &alu);
1226 if (r)
1227 return r;
1228 }
1229 r = r600_bc_add_literal(ctx->bc, ctx->value);
1230 if (r)
1231 return r;
1232
1233 /* kill must be last in ALU */
1234 ctx->bc->force_add_cf = 1;
1235 ctx->shader->uses_kill = TRUE;
1236 return 0;
1237 }
1238
1239 static int tgsi_lit(struct r600_shader_ctx *ctx)
1240 {
1241 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1242 struct r600_bc_alu alu;
1243 struct r600_bc_alu_src r600_src[3];
1244 int r;
1245
1246 r = tgsi_split_constant(ctx, r600_src);
1247 if (r)
1248 return r;
1249 r = tgsi_split_literal_constant(ctx, r600_src);
1250 if (r)
1251 return r;
1252
1253 /* dst.x, <- 1.0 */
1254 memset(&alu, 0, sizeof(struct r600_bc_alu));
1255 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1256 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1257 alu.src[0].chan = 0;
1258 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1259 if (r)
1260 return r;
1261 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1262 r = r600_bc_add_alu(ctx->bc, &alu);
1263 if (r)
1264 return r;
1265
1266 /* dst.y = max(src.x, 0.0) */
1267 memset(&alu, 0, sizeof(struct r600_bc_alu));
1268 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1269 alu.src[0] = r600_src[0];
1270 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1271 alu.src[1].chan = 0;
1272 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1273 if (r)
1274 return r;
1275 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1276 r = r600_bc_add_alu(ctx->bc, &alu);
1277 if (r)
1278 return r;
1279
1280 /* dst.w, <- 1.0 */
1281 memset(&alu, 0, sizeof(struct r600_bc_alu));
1282 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1283 alu.src[0].sel = V_SQ_ALU_SRC_1;
1284 alu.src[0].chan = 0;
1285 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1286 if (r)
1287 return r;
1288 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1289 alu.last = 1;
1290 r = r600_bc_add_alu(ctx->bc, &alu);
1291 if (r)
1292 return r;
1293
1294 r = r600_bc_add_literal(ctx->bc, ctx->value);
1295 if (r)
1296 return r;
1297
1298 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1299 {
1300 int chan;
1301 int sel;
1302
1303 /* dst.z = log(src.y) */
1304 memset(&alu, 0, sizeof(struct r600_bc_alu));
1305 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1306 alu.src[0] = r600_src[0];
1307 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1308 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1309 if (r)
1310 return r;
1311 alu.last = 1;
1312 r = r600_bc_add_alu(ctx->bc, &alu);
1313 if (r)
1314 return r;
1315
1316 r = r600_bc_add_literal(ctx->bc, ctx->value);
1317 if (r)
1318 return r;
1319
1320 chan = alu.dst.chan;
1321 sel = alu.dst.sel;
1322
1323 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1324 memset(&alu, 0, sizeof(struct r600_bc_alu));
1325 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1326 alu.src[0] = r600_src[0];
1327 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1328 alu.src[1].sel = sel;
1329 alu.src[1].chan = chan;
1330
1331 alu.src[2] = r600_src[0];
1332 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1333 alu.dst.sel = ctx->temp_reg;
1334 alu.dst.chan = 0;
1335 alu.dst.write = 1;
1336 alu.is_op3 = 1;
1337 alu.last = 1;
1338 r = r600_bc_add_alu(ctx->bc, &alu);
1339 if (r)
1340 return r;
1341
1342 r = r600_bc_add_literal(ctx->bc, ctx->value);
1343 if (r)
1344 return r;
1345 /* dst.z = exp(tmp.x) */
1346 memset(&alu, 0, sizeof(struct r600_bc_alu));
1347 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1348 alu.src[0].sel = ctx->temp_reg;
1349 alu.src[0].chan = 0;
1350 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1351 if (r)
1352 return r;
1353 alu.last = 1;
1354 r = r600_bc_add_alu(ctx->bc, &alu);
1355 if (r)
1356 return r;
1357 }
1358 return 0;
1359 }
1360
1361 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1362 {
1363 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1364 struct r600_bc_alu alu;
1365 int i, r;
1366
1367 memset(&alu, 0, sizeof(struct r600_bc_alu));
1368
1369 /* FIXME:
1370 * For state trackers other than OpenGL, we'll want to use
1371 * _RECIPSQRT_IEEE instead.
1372 */
1373 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1374
1375 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1376 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1377 if (r)
1378 return r;
1379 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1380 alu.src[i].abs = 1;
1381 }
1382 alu.dst.sel = ctx->temp_reg;
1383 alu.dst.write = 1;
1384 alu.last = 1;
1385 r = r600_bc_add_alu(ctx->bc, &alu);
1386 if (r)
1387 return r;
1388 r = r600_bc_add_literal(ctx->bc, ctx->value);
1389 if (r)
1390 return r;
1391 /* replicate result */
1392 return tgsi_helper_tempx_replicate(ctx);
1393 }
1394
1395 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1396 {
1397 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1398 struct r600_bc_alu alu;
1399 int i, r;
1400
1401 for (i = 0; i < 4; i++) {
1402 memset(&alu, 0, sizeof(struct r600_bc_alu));
1403 alu.src[0].sel = ctx->temp_reg;
1404 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1405 alu.dst.chan = i;
1406 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1407 if (r)
1408 return r;
1409 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1410 if (i == 3)
1411 alu.last = 1;
1412 r = r600_bc_add_alu(ctx->bc, &alu);
1413 if (r)
1414 return r;
1415 }
1416 return 0;
1417 }
1418
1419 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1420 {
1421 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1422 struct r600_bc_alu alu;
1423 int i, r;
1424
1425 memset(&alu, 0, sizeof(struct r600_bc_alu));
1426 alu.inst = ctx->inst_info->r600_opcode;
1427 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1428 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1429 if (r)
1430 return r;
1431 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1432 }
1433 alu.dst.sel = ctx->temp_reg;
1434 alu.dst.write = 1;
1435 alu.last = 1;
1436 r = r600_bc_add_alu(ctx->bc, &alu);
1437 if (r)
1438 return r;
1439 r = r600_bc_add_literal(ctx->bc, ctx->value);
1440 if (r)
1441 return r;
1442 /* replicate result */
1443 return tgsi_helper_tempx_replicate(ctx);
1444 }
1445
1446 static int tgsi_pow(struct r600_shader_ctx *ctx)
1447 {
1448 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1449 struct r600_bc_alu alu;
1450 int r;
1451
1452 /* LOG2(a) */
1453 memset(&alu, 0, sizeof(struct r600_bc_alu));
1454 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1455 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1456 if (r)
1457 return r;
1458 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1459 alu.dst.sel = ctx->temp_reg;
1460 alu.dst.write = 1;
1461 alu.last = 1;
1462 r = r600_bc_add_alu(ctx->bc, &alu);
1463 if (r)
1464 return r;
1465 r = r600_bc_add_literal(ctx->bc,ctx->value);
1466 if (r)
1467 return r;
1468 /* b * LOG2(a) */
1469 memset(&alu, 0, sizeof(struct r600_bc_alu));
1470 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1471 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1472 if (r)
1473 return r;
1474 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1475 alu.src[1].sel = ctx->temp_reg;
1476 alu.dst.sel = ctx->temp_reg;
1477 alu.dst.write = 1;
1478 alu.last = 1;
1479 r = r600_bc_add_alu(ctx->bc, &alu);
1480 if (r)
1481 return r;
1482 r = r600_bc_add_literal(ctx->bc,ctx->value);
1483 if (r)
1484 return r;
1485 /* POW(a,b) = EXP2(b * LOG2(a))*/
1486 memset(&alu, 0, sizeof(struct r600_bc_alu));
1487 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1488 alu.src[0].sel = ctx->temp_reg;
1489 alu.dst.sel = ctx->temp_reg;
1490 alu.dst.write = 1;
1491 alu.last = 1;
1492 r = r600_bc_add_alu(ctx->bc, &alu);
1493 if (r)
1494 return r;
1495 r = r600_bc_add_literal(ctx->bc,ctx->value);
1496 if (r)
1497 return r;
1498 return tgsi_helper_tempx_replicate(ctx);
1499 }
1500
1501 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1502 {
1503 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1504 struct r600_bc_alu alu;
1505 struct r600_bc_alu_src r600_src[3];
1506 int i, r;
1507
1508 r = tgsi_split_constant(ctx, r600_src);
1509 if (r)
1510 return r;
1511 r = tgsi_split_literal_constant(ctx, r600_src);
1512 if (r)
1513 return r;
1514
1515 /* tmp = (src > 0 ? 1 : src) */
1516 for (i = 0; i < 4; i++) {
1517 memset(&alu, 0, sizeof(struct r600_bc_alu));
1518 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1519 alu.is_op3 = 1;
1520
1521 alu.dst.sel = ctx->temp_reg;
1522 alu.dst.chan = i;
1523
1524 alu.src[0] = r600_src[0];
1525 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1526
1527 alu.src[1].sel = V_SQ_ALU_SRC_1;
1528
1529 alu.src[2] = r600_src[0];
1530 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1531 if (i == 3)
1532 alu.last = 1;
1533 r = r600_bc_add_alu(ctx->bc, &alu);
1534 if (r)
1535 return r;
1536 }
1537 r = r600_bc_add_literal(ctx->bc, ctx->value);
1538 if (r)
1539 return r;
1540
1541 /* dst = (-tmp > 0 ? -1 : tmp) */
1542 for (i = 0; i < 4; i++) {
1543 memset(&alu, 0, sizeof(struct r600_bc_alu));
1544 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1545 alu.is_op3 = 1;
1546 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1547 if (r)
1548 return r;
1549
1550 alu.src[0].sel = ctx->temp_reg;
1551 alu.src[0].chan = i;
1552 alu.src[0].neg = 1;
1553
1554 alu.src[1].sel = V_SQ_ALU_SRC_1;
1555 alu.src[1].neg = 1;
1556
1557 alu.src[2].sel = ctx->temp_reg;
1558 alu.src[2].chan = i;
1559
1560 if (i == 3)
1561 alu.last = 1;
1562 r = r600_bc_add_alu(ctx->bc, &alu);
1563 if (r)
1564 return r;
1565 }
1566 return 0;
1567 }
1568
1569 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1570 {
1571 struct r600_bc_alu alu;
1572 int i, r;
1573
1574 r = r600_bc_add_literal(ctx->bc, ctx->value);
1575 if (r)
1576 return r;
1577 for (i = 0; i < 4; i++) {
1578 memset(&alu, 0, sizeof(struct r600_bc_alu));
1579 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1580 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1581 alu.dst.chan = i;
1582 } else {
1583 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1584 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1585 if (r)
1586 return r;
1587 alu.src[0].sel = ctx->temp_reg;
1588 alu.src[0].chan = i;
1589 }
1590 if (i == 3) {
1591 alu.last = 1;
1592 }
1593 r = r600_bc_add_alu(ctx->bc, &alu);
1594 if (r)
1595 return r;
1596 }
1597 return 0;
1598 }
1599
1600 static int tgsi_op3(struct r600_shader_ctx *ctx)
1601 {
1602 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1603 struct r600_bc_alu_src r600_src[3];
1604 struct r600_bc_alu alu;
1605 int i, j, r;
1606
1607 r = tgsi_split_constant(ctx, r600_src);
1608 if (r)
1609 return r;
1610 r = tgsi_split_literal_constant(ctx, r600_src);
1611 if (r)
1612 return r;
1613 /* do it in 2 step as op3 doesn't support writemask */
1614 for (i = 0; i < 4; i++) {
1615 memset(&alu, 0, sizeof(struct r600_bc_alu));
1616 alu.inst = ctx->inst_info->r600_opcode;
1617 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1618 alu.src[j] = r600_src[j];
1619 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1620 }
1621 alu.dst.sel = ctx->temp_reg;
1622 alu.dst.chan = i;
1623 alu.dst.write = 1;
1624 alu.is_op3 = 1;
1625 if (i == 3) {
1626 alu.last = 1;
1627 }
1628 r = r600_bc_add_alu(ctx->bc, &alu);
1629 if (r)
1630 return r;
1631 }
1632 return tgsi_helper_copy(ctx, inst);
1633 }
1634
1635 static int tgsi_dp(struct r600_shader_ctx *ctx)
1636 {
1637 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1638 struct r600_bc_alu_src r600_src[3];
1639 struct r600_bc_alu alu;
1640 int i, j, r;
1641
1642 r = tgsi_split_constant(ctx, r600_src);
1643 if (r)
1644 return r;
1645 r = tgsi_split_literal_constant(ctx, r600_src);
1646 if (r)
1647 return r;
1648 for (i = 0; i < 4; i++) {
1649 memset(&alu, 0, sizeof(struct r600_bc_alu));
1650 alu.inst = ctx->inst_info->r600_opcode;
1651 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1652 alu.src[j] = r600_src[j];
1653 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1654 }
1655 alu.dst.sel = ctx->temp_reg;
1656 alu.dst.chan = i;
1657 alu.dst.write = 1;
1658 /* handle some special cases */
1659 switch (ctx->inst_info->tgsi_opcode) {
1660 case TGSI_OPCODE_DP2:
1661 if (i > 1) {
1662 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1663 alu.src[0].chan = alu.src[1].chan = 0;
1664 }
1665 break;
1666 case TGSI_OPCODE_DP3:
1667 if (i > 2) {
1668 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1669 alu.src[0].chan = alu.src[1].chan = 0;
1670 }
1671 break;
1672 case TGSI_OPCODE_DPH:
1673 if (i == 3) {
1674 alu.src[0].sel = V_SQ_ALU_SRC_1;
1675 alu.src[0].chan = 0;
1676 alu.src[0].neg = 0;
1677 }
1678 break;
1679 default:
1680 break;
1681 }
1682 if (i == 3) {
1683 alu.last = 1;
1684 }
1685 r = r600_bc_add_alu(ctx->bc, &alu);
1686 if (r)
1687 return r;
1688 }
1689 return tgsi_helper_copy(ctx, inst);
1690 }
1691
1692 static int tgsi_tex(struct r600_shader_ctx *ctx)
1693 {
1694 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1695 struct r600_bc_tex tex;
1696 struct r600_bc_alu alu;
1697 unsigned src_gpr;
1698 int r, i;
1699 int opcode;
1700 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1701 uint32_t lit_vals[4];
1702
1703 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1704
1705 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1706 /* Add perspective divide */
1707 memset(&alu, 0, sizeof(struct r600_bc_alu));
1708 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1709 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1710 if (r)
1711 return r;
1712
1713 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1714 alu.dst.sel = ctx->temp_reg;
1715 alu.dst.chan = 3;
1716 alu.last = 1;
1717 alu.dst.write = 1;
1718 r = r600_bc_add_alu(ctx->bc, &alu);
1719 if (r)
1720 return r;
1721
1722 for (i = 0; i < 3; i++) {
1723 memset(&alu, 0, sizeof(struct r600_bc_alu));
1724 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1725 alu.src[0].sel = ctx->temp_reg;
1726 alu.src[0].chan = 3;
1727 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1728 if (r)
1729 return r;
1730 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1731 alu.dst.sel = ctx->temp_reg;
1732 alu.dst.chan = i;
1733 alu.dst.write = 1;
1734 r = r600_bc_add_alu(ctx->bc, &alu);
1735 if (r)
1736 return r;
1737 }
1738 memset(&alu, 0, sizeof(struct r600_bc_alu));
1739 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1740 alu.src[0].sel = V_SQ_ALU_SRC_1;
1741 alu.src[0].chan = 0;
1742 alu.dst.sel = ctx->temp_reg;
1743 alu.dst.chan = 3;
1744 alu.last = 1;
1745 alu.dst.write = 1;
1746 r = r600_bc_add_alu(ctx->bc, &alu);
1747 if (r)
1748 return r;
1749 src_not_temp = FALSE;
1750 src_gpr = ctx->temp_reg;
1751 }
1752
1753 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1754 int src_chan, src2_chan;
1755
1756 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1757 for (i = 0; i < 4; i++) {
1758 memset(&alu, 0, sizeof(struct r600_bc_alu));
1759 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1760 switch (i) {
1761 case 0:
1762 src_chan = 2;
1763 src2_chan = 1;
1764 break;
1765 case 1:
1766 src_chan = 2;
1767 src2_chan = 0;
1768 break;
1769 case 2:
1770 src_chan = 0;
1771 src2_chan = 2;
1772 break;
1773 case 3:
1774 src_chan = 1;
1775 src2_chan = 2;
1776 break;
1777 default:
1778 assert(0);
1779 src_chan = 0;
1780 src2_chan = 0;
1781 break;
1782 }
1783 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1784 if (r)
1785 return r;
1786 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1787 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1788 if (r)
1789 return r;
1790 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1791 alu.dst.sel = ctx->temp_reg;
1792 alu.dst.chan = i;
1793 if (i == 3)
1794 alu.last = 1;
1795 alu.dst.write = 1;
1796 r = r600_bc_add_alu(ctx->bc, &alu);
1797 if (r)
1798 return r;
1799 }
1800
1801 /* tmp1.z = RCP_e(|tmp1.z|) */
1802 memset(&alu, 0, sizeof(struct r600_bc_alu));
1803 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1804 alu.src[0].sel = ctx->temp_reg;
1805 alu.src[0].chan = 2;
1806 alu.src[0].abs = 1;
1807 alu.dst.sel = ctx->temp_reg;
1808 alu.dst.chan = 2;
1809 alu.dst.write = 1;
1810 alu.last = 1;
1811 r = r600_bc_add_alu(ctx->bc, &alu);
1812 if (r)
1813 return r;
1814
1815 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1816 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1817 * muladd has no writemask, have to use another temp
1818 */
1819 memset(&alu, 0, sizeof(struct r600_bc_alu));
1820 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1821 alu.is_op3 = 1;
1822
1823 alu.src[0].sel = ctx->temp_reg;
1824 alu.src[0].chan = 0;
1825 alu.src[1].sel = ctx->temp_reg;
1826 alu.src[1].chan = 2;
1827
1828 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1829 alu.src[2].chan = 0;
1830
1831 alu.dst.sel = ctx->temp_reg;
1832 alu.dst.chan = 0;
1833 alu.dst.write = 1;
1834
1835 r = r600_bc_add_alu(ctx->bc, &alu);
1836 if (r)
1837 return r;
1838
1839 memset(&alu, 0, sizeof(struct r600_bc_alu));
1840 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1841 alu.is_op3 = 1;
1842
1843 alu.src[0].sel = ctx->temp_reg;
1844 alu.src[0].chan = 1;
1845 alu.src[1].sel = ctx->temp_reg;
1846 alu.src[1].chan = 2;
1847
1848 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1849 alu.src[2].chan = 0;
1850
1851 alu.dst.sel = ctx->temp_reg;
1852 alu.dst.chan = 1;
1853 alu.dst.write = 1;
1854
1855 alu.last = 1;
1856 r = r600_bc_add_alu(ctx->bc, &alu);
1857 if (r)
1858 return r;
1859
1860 lit_vals[0] = fui(1.5f);
1861
1862 r = r600_bc_add_literal(ctx->bc, lit_vals);
1863 if (r)
1864 return r;
1865 src_not_temp = FALSE;
1866 src_gpr = ctx->temp_reg;
1867 }
1868
1869 if (src_not_temp) {
1870 for (i = 0; i < 4; i++) {
1871 memset(&alu, 0, sizeof(struct r600_bc_alu));
1872 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1873 alu.src[0].sel = src_gpr;
1874 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1875 alu.dst.sel = ctx->temp_reg;
1876 alu.dst.chan = i;
1877 if (i == 3)
1878 alu.last = 1;
1879 alu.dst.write = 1;
1880 r = r600_bc_add_alu(ctx->bc, &alu);
1881 if (r)
1882 return r;
1883 }
1884 src_gpr = ctx->temp_reg;
1885 }
1886
1887 opcode = ctx->inst_info->r600_opcode;
1888 if (opcode == SQ_TEX_INST_SAMPLE &&
1889 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1890 opcode = SQ_TEX_INST_SAMPLE_C;
1891
1892 memset(&tex, 0, sizeof(struct r600_bc_tex));
1893 tex.inst = opcode;
1894 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1895 tex.resource_id = tex.sampler_id;
1896 if (ctx->shader->processor_type == TGSI_PROCESSOR_VERTEX)
1897 tex.resource_id += PIPE_MAX_ATTRIBS;
1898 tex.src_gpr = src_gpr;
1899 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1900 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1901 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1902 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1903 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1904 tex.src_sel_x = 0;
1905 tex.src_sel_y = 1;
1906 tex.src_sel_z = 2;
1907 tex.src_sel_w = 3;
1908
1909 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1910 tex.src_sel_x = 1;
1911 tex.src_sel_y = 0;
1912 tex.src_sel_z = 3;
1913 tex.src_sel_w = 1;
1914 }
1915
1916 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1917 tex.coord_type_x = 1;
1918 tex.coord_type_y = 1;
1919 tex.coord_type_z = 1;
1920 tex.coord_type_w = 1;
1921 }
1922
1923 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1924 tex.src_sel_w = 2;
1925
1926 r = r600_bc_add_tex(ctx->bc, &tex);
1927 if (r)
1928 return r;
1929
1930 /* add shadow ambient support - gallium doesn't do it yet */
1931 return 0;
1932
1933 }
1934
1935 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1936 {
1937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1938 struct r600_bc_alu_src r600_src[3];
1939 struct r600_bc_alu alu;
1940 unsigned i;
1941 int r;
1942
1943 r = tgsi_split_constant(ctx, r600_src);
1944 if (r)
1945 return r;
1946 r = tgsi_split_literal_constant(ctx, r600_src);
1947 if (r)
1948 return r;
1949 /* 1 - src0 */
1950 for (i = 0; i < 4; i++) {
1951 memset(&alu, 0, sizeof(struct r600_bc_alu));
1952 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1953 alu.src[0].sel = V_SQ_ALU_SRC_1;
1954 alu.src[0].chan = 0;
1955 alu.src[1] = r600_src[0];
1956 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1957 alu.src[1].neg = 1;
1958 alu.dst.sel = ctx->temp_reg;
1959 alu.dst.chan = i;
1960 if (i == 3) {
1961 alu.last = 1;
1962 }
1963 alu.dst.write = 1;
1964 r = r600_bc_add_alu(ctx->bc, &alu);
1965 if (r)
1966 return r;
1967 }
1968 r = r600_bc_add_literal(ctx->bc, ctx->value);
1969 if (r)
1970 return r;
1971
1972 /* (1 - src0) * src2 */
1973 for (i = 0; i < 4; i++) {
1974 memset(&alu, 0, sizeof(struct r600_bc_alu));
1975 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1976 alu.src[0].sel = ctx->temp_reg;
1977 alu.src[0].chan = i;
1978 alu.src[1] = r600_src[2];
1979 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1980 alu.dst.sel = ctx->temp_reg;
1981 alu.dst.chan = i;
1982 if (i == 3) {
1983 alu.last = 1;
1984 }
1985 alu.dst.write = 1;
1986 r = r600_bc_add_alu(ctx->bc, &alu);
1987 if (r)
1988 return r;
1989 }
1990 r = r600_bc_add_literal(ctx->bc, ctx->value);
1991 if (r)
1992 return r;
1993
1994 /* src0 * src1 + (1 - src0) * src2 */
1995 for (i = 0; i < 4; i++) {
1996 memset(&alu, 0, sizeof(struct r600_bc_alu));
1997 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1998 alu.is_op3 = 1;
1999 alu.src[0] = r600_src[0];
2000 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2001 alu.src[1] = r600_src[1];
2002 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2003 alu.src[2].sel = ctx->temp_reg;
2004 alu.src[2].chan = i;
2005 alu.dst.sel = ctx->temp_reg;
2006 alu.dst.chan = i;
2007 if (i == 3) {
2008 alu.last = 1;
2009 }
2010 r = r600_bc_add_alu(ctx->bc, &alu);
2011 if (r)
2012 return r;
2013 }
2014 return tgsi_helper_copy(ctx, inst);
2015 }
2016
2017 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2018 {
2019 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2020 struct r600_bc_alu_src r600_src[3];
2021 struct r600_bc_alu alu;
2022 int use_temp = 0;
2023 int i, r;
2024
2025 r = tgsi_split_constant(ctx, r600_src);
2026 if (r)
2027 return r;
2028 r = tgsi_split_literal_constant(ctx, r600_src);
2029 if (r)
2030 return r;
2031
2032 if (inst->Dst[0].Register.WriteMask != 0xf)
2033 use_temp = 1;
2034
2035 for (i = 0; i < 4; i++) {
2036 memset(&alu, 0, sizeof(struct r600_bc_alu));
2037 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2038 alu.src[0] = r600_src[0];
2039 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2040
2041 alu.src[1] = r600_src[2];
2042 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2043
2044 alu.src[2] = r600_src[1];
2045 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2046
2047 if (use_temp)
2048 alu.dst.sel = ctx->temp_reg;
2049 else {
2050 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2051 if (r)
2052 return r;
2053 }
2054 alu.dst.chan = i;
2055 alu.dst.write = 1;
2056 alu.is_op3 = 1;
2057 if (i == 3)
2058 alu.last = 1;
2059 r = r600_bc_add_alu(ctx->bc, &alu);
2060 if (r)
2061 return r;
2062 }
2063 if (use_temp)
2064 return tgsi_helper_copy(ctx, inst);
2065 return 0;
2066 }
2067
2068 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2069 {
2070 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2071 struct r600_bc_alu_src r600_src[3];
2072 struct r600_bc_alu alu;
2073 uint32_t use_temp = 0;
2074 int i, r;
2075
2076 if (inst->Dst[0].Register.WriteMask != 0xf)
2077 use_temp = 1;
2078
2079 r = tgsi_split_constant(ctx, r600_src);
2080 if (r)
2081 return r;
2082 r = tgsi_split_literal_constant(ctx, r600_src);
2083 if (r)
2084 return r;
2085
2086 for (i = 0; i < 4; i++) {
2087 memset(&alu, 0, sizeof(struct r600_bc_alu));
2088 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2089
2090 alu.src[0] = r600_src[0];
2091 switch (i) {
2092 case 0:
2093 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2094 break;
2095 case 1:
2096 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2097 break;
2098 case 2:
2099 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2100 break;
2101 case 3:
2102 alu.src[0].sel = V_SQ_ALU_SRC_0;
2103 alu.src[0].chan = i;
2104 }
2105
2106 alu.src[1] = r600_src[1];
2107 switch (i) {
2108 case 0:
2109 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2110 break;
2111 case 1:
2112 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2113 break;
2114 case 2:
2115 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2116 break;
2117 case 3:
2118 alu.src[1].sel = V_SQ_ALU_SRC_0;
2119 alu.src[1].chan = i;
2120 }
2121
2122 alu.dst.sel = ctx->temp_reg;
2123 alu.dst.chan = i;
2124 alu.dst.write = 1;
2125
2126 if (i == 3)
2127 alu.last = 1;
2128 r = r600_bc_add_alu(ctx->bc, &alu);
2129 if (r)
2130 return r;
2131
2132 r = r600_bc_add_literal(ctx->bc, ctx->value);
2133 if (r)
2134 return r;
2135 }
2136
2137 for (i = 0; i < 4; i++) {
2138 memset(&alu, 0, sizeof(struct r600_bc_alu));
2139 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2140
2141 alu.src[0] = r600_src[0];
2142 switch (i) {
2143 case 0:
2144 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2145 break;
2146 case 1:
2147 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2148 break;
2149 case 2:
2150 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2151 break;
2152 case 3:
2153 alu.src[0].sel = V_SQ_ALU_SRC_0;
2154 alu.src[0].chan = i;
2155 }
2156
2157 alu.src[1] = r600_src[1];
2158 switch (i) {
2159 case 0:
2160 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2161 break;
2162 case 1:
2163 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2164 break;
2165 case 2:
2166 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2167 break;
2168 case 3:
2169 alu.src[1].sel = V_SQ_ALU_SRC_0;
2170 alu.src[1].chan = i;
2171 }
2172
2173 alu.src[2].sel = ctx->temp_reg;
2174 alu.src[2].neg = 1;
2175 alu.src[2].chan = i;
2176
2177 if (use_temp)
2178 alu.dst.sel = ctx->temp_reg;
2179 else {
2180 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2181 if (r)
2182 return r;
2183 }
2184 alu.dst.chan = i;
2185 alu.dst.write = 1;
2186 alu.is_op3 = 1;
2187 if (i == 3)
2188 alu.last = 1;
2189 r = r600_bc_add_alu(ctx->bc, &alu);
2190 if (r)
2191 return r;
2192
2193 r = r600_bc_add_literal(ctx->bc, ctx->value);
2194 if (r)
2195 return r;
2196 }
2197 if (use_temp)
2198 return tgsi_helper_copy(ctx, inst);
2199 return 0;
2200 }
2201
2202 static int tgsi_exp(struct r600_shader_ctx *ctx)
2203 {
2204 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2205 struct r600_bc_alu_src r600_src[3];
2206 struct r600_bc_alu alu;
2207 int r;
2208
2209 /* result.x = 2^floor(src); */
2210 if (inst->Dst[0].Register.WriteMask & 1) {
2211 memset(&alu, 0, sizeof(struct r600_bc_alu));
2212
2213 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2214 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2215 if (r)
2216 return r;
2217
2218 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2219
2220 alu.dst.sel = ctx->temp_reg;
2221 alu.dst.chan = 0;
2222 alu.dst.write = 1;
2223 alu.last = 1;
2224 r = r600_bc_add_alu(ctx->bc, &alu);
2225 if (r)
2226 return r;
2227
2228 r = r600_bc_add_literal(ctx->bc, ctx->value);
2229 if (r)
2230 return r;
2231
2232 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2233 alu.src[0].sel = ctx->temp_reg;
2234 alu.src[0].chan = 0;
2235
2236 alu.dst.sel = ctx->temp_reg;
2237 alu.dst.chan = 0;
2238 alu.dst.write = 1;
2239 alu.last = 1;
2240 r = r600_bc_add_alu(ctx->bc, &alu);
2241 if (r)
2242 return r;
2243
2244 r = r600_bc_add_literal(ctx->bc, ctx->value);
2245 if (r)
2246 return r;
2247 }
2248
2249 /* result.y = tmp - floor(tmp); */
2250 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2251 memset(&alu, 0, sizeof(struct r600_bc_alu));
2252
2253 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2254 alu.src[0] = r600_src[0];
2255 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2256 if (r)
2257 return r;
2258 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2259
2260 alu.dst.sel = ctx->temp_reg;
2261 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2262 // if (r)
2263 // return r;
2264 alu.dst.write = 1;
2265 alu.dst.chan = 1;
2266
2267 alu.last = 1;
2268
2269 r = r600_bc_add_alu(ctx->bc, &alu);
2270 if (r)
2271 return r;
2272 r = r600_bc_add_literal(ctx->bc, ctx->value);
2273 if (r)
2274 return r;
2275 }
2276
2277 /* result.z = RoughApprox2ToX(tmp);*/
2278 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2279 memset(&alu, 0, sizeof(struct r600_bc_alu));
2280 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2281 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2282 if (r)
2283 return r;
2284 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2285
2286 alu.dst.sel = ctx->temp_reg;
2287 alu.dst.write = 1;
2288 alu.dst.chan = 2;
2289
2290 alu.last = 1;
2291
2292 r = r600_bc_add_alu(ctx->bc, &alu);
2293 if (r)
2294 return r;
2295 r = r600_bc_add_literal(ctx->bc, ctx->value);
2296 if (r)
2297 return r;
2298 }
2299
2300 /* result.w = 1.0;*/
2301 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2302 memset(&alu, 0, sizeof(struct r600_bc_alu));
2303
2304 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2305 alu.src[0].sel = V_SQ_ALU_SRC_1;
2306 alu.src[0].chan = 0;
2307
2308 alu.dst.sel = ctx->temp_reg;
2309 alu.dst.chan = 3;
2310 alu.dst.write = 1;
2311 alu.last = 1;
2312 r = r600_bc_add_alu(ctx->bc, &alu);
2313 if (r)
2314 return r;
2315 r = r600_bc_add_literal(ctx->bc, ctx->value);
2316 if (r)
2317 return r;
2318 }
2319 return tgsi_helper_copy(ctx, inst);
2320 }
2321
2322 static int tgsi_log(struct r600_shader_ctx *ctx)
2323 {
2324 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2325 struct r600_bc_alu alu;
2326 int r;
2327
2328 /* result.x = floor(log2(src)); */
2329 if (inst->Dst[0].Register.WriteMask & 1) {
2330 memset(&alu, 0, sizeof(struct r600_bc_alu));
2331
2332 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2333 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2334 if (r)
2335 return r;
2336
2337 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2338
2339 alu.dst.sel = ctx->temp_reg;
2340 alu.dst.chan = 0;
2341 alu.dst.write = 1;
2342 alu.last = 1;
2343 r = r600_bc_add_alu(ctx->bc, &alu);
2344 if (r)
2345 return r;
2346
2347 r = r600_bc_add_literal(ctx->bc, ctx->value);
2348 if (r)
2349 return r;
2350
2351 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2352 alu.src[0].sel = ctx->temp_reg;
2353 alu.src[0].chan = 0;
2354
2355 alu.dst.sel = ctx->temp_reg;
2356 alu.dst.chan = 0;
2357 alu.dst.write = 1;
2358 alu.last = 1;
2359
2360 r = r600_bc_add_alu(ctx->bc, &alu);
2361 if (r)
2362 return r;
2363
2364 r = r600_bc_add_literal(ctx->bc, ctx->value);
2365 if (r)
2366 return r;
2367 }
2368
2369 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2370 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2371 memset(&alu, 0, sizeof(struct r600_bc_alu));
2372
2373 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2374 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2375 if (r)
2376 return r;
2377
2378 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2379
2380 alu.dst.sel = ctx->temp_reg;
2381 alu.dst.chan = 1;
2382 alu.dst.write = 1;
2383 alu.last = 1;
2384
2385 r = r600_bc_add_alu(ctx->bc, &alu);
2386 if (r)
2387 return r;
2388
2389 r = r600_bc_add_literal(ctx->bc, ctx->value);
2390 if (r)
2391 return r;
2392
2393 memset(&alu, 0, sizeof(struct r600_bc_alu));
2394
2395 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2396 alu.src[0].sel = ctx->temp_reg;
2397 alu.src[0].chan = 1;
2398
2399 alu.dst.sel = ctx->temp_reg;
2400 alu.dst.chan = 1;
2401 alu.dst.write = 1;
2402 alu.last = 1;
2403
2404 r = r600_bc_add_alu(ctx->bc, &alu);
2405 if (r)
2406 return r;
2407
2408 r = r600_bc_add_literal(ctx->bc, ctx->value);
2409 if (r)
2410 return r;
2411
2412 memset(&alu, 0, sizeof(struct r600_bc_alu));
2413
2414 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2415 alu.src[0].sel = ctx->temp_reg;
2416 alu.src[0].chan = 1;
2417
2418 alu.dst.sel = ctx->temp_reg;
2419 alu.dst.chan = 1;
2420 alu.dst.write = 1;
2421 alu.last = 1;
2422
2423 r = r600_bc_add_alu(ctx->bc, &alu);
2424 if (r)
2425 return r;
2426
2427 r = r600_bc_add_literal(ctx->bc, ctx->value);
2428 if (r)
2429 return r;
2430
2431 memset(&alu, 0, sizeof(struct r600_bc_alu));
2432
2433 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2434 alu.src[0].sel = ctx->temp_reg;
2435 alu.src[0].chan = 1;
2436
2437 alu.dst.sel = ctx->temp_reg;
2438 alu.dst.chan = 1;
2439 alu.dst.write = 1;
2440 alu.last = 1;
2441
2442 r = r600_bc_add_alu(ctx->bc, &alu);
2443 if (r)
2444 return r;
2445
2446 r = r600_bc_add_literal(ctx->bc, ctx->value);
2447 if (r)
2448 return r;
2449
2450 memset(&alu, 0, sizeof(struct r600_bc_alu));
2451
2452 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2453
2454 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2455 if (r)
2456 return r;
2457
2458 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2459
2460 alu.src[1].sel = ctx->temp_reg;
2461 alu.src[1].chan = 1;
2462
2463 alu.dst.sel = ctx->temp_reg;
2464 alu.dst.chan = 1;
2465 alu.dst.write = 1;
2466 alu.last = 1;
2467
2468 r = r600_bc_add_alu(ctx->bc, &alu);
2469 if (r)
2470 return r;
2471
2472 r = r600_bc_add_literal(ctx->bc, ctx->value);
2473 if (r)
2474 return r;
2475 }
2476
2477 /* result.z = log2(src);*/
2478 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2479 memset(&alu, 0, sizeof(struct r600_bc_alu));
2480
2481 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2482 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2483 if (r)
2484 return r;
2485
2486 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2487
2488 alu.dst.sel = ctx->temp_reg;
2489 alu.dst.write = 1;
2490 alu.dst.chan = 2;
2491 alu.last = 1;
2492
2493 r = r600_bc_add_alu(ctx->bc, &alu);
2494 if (r)
2495 return r;
2496
2497 r = r600_bc_add_literal(ctx->bc, ctx->value);
2498 if (r)
2499 return r;
2500 }
2501
2502 /* result.w = 1.0; */
2503 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2504 memset(&alu, 0, sizeof(struct r600_bc_alu));
2505
2506 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2507 alu.src[0].sel = V_SQ_ALU_SRC_1;
2508 alu.src[0].chan = 0;
2509
2510 alu.dst.sel = ctx->temp_reg;
2511 alu.dst.chan = 3;
2512 alu.dst.write = 1;
2513 alu.last = 1;
2514
2515 r = r600_bc_add_alu(ctx->bc, &alu);
2516 if (r)
2517 return r;
2518
2519 r = r600_bc_add_literal(ctx->bc, ctx->value);
2520 if (r)
2521 return r;
2522 }
2523
2524 return tgsi_helper_copy(ctx, inst);
2525 }
2526
2527 /* r6/7 only for now */
2528 static int tgsi_arl(struct r600_shader_ctx *ctx)
2529 {
2530 /* TODO from r600c, ar values don't persist between clauses */
2531 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2532 struct r600_bc_alu alu;
2533 int r;
2534 memset(&alu, 0, sizeof(struct r600_bc_alu));
2535
2536 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2537
2538 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2539 if (r)
2540 return r;
2541 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2542
2543 alu.last = 1;
2544
2545 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2546 if (r)
2547 return r;
2548 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2549 return 0;
2550 }
2551
2552 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2553 {
2554 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2555 struct r600_bc_alu alu;
2556 int i, r = 0;
2557
2558 for (i = 0; i < 4; i++) {
2559 memset(&alu, 0, sizeof(struct r600_bc_alu));
2560
2561 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2562 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2563 if (r)
2564 return r;
2565
2566 if (i == 0 || i == 3) {
2567 alu.src[0].sel = V_SQ_ALU_SRC_1;
2568 } else {
2569 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2570 if (r)
2571 return r;
2572 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2573 }
2574
2575 if (i == 0 || i == 2) {
2576 alu.src[1].sel = V_SQ_ALU_SRC_1;
2577 } else {
2578 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2579 if (r)
2580 return r;
2581 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2582 }
2583 if (i == 3)
2584 alu.last = 1;
2585 r = r600_bc_add_alu(ctx->bc, &alu);
2586 if (r)
2587 return r;
2588 }
2589 return 0;
2590 }
2591
2592 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2593 {
2594 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2595 struct r600_bc_alu alu;
2596 int r;
2597
2598 memset(&alu, 0, sizeof(struct r600_bc_alu));
2599 alu.inst = opcode;
2600 alu.predicate = 1;
2601
2602 alu.dst.sel = ctx->temp_reg;
2603 alu.dst.write = 1;
2604 alu.dst.chan = 0;
2605
2606 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2607 if (r)
2608 return r;
2609 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2610 alu.src[1].sel = V_SQ_ALU_SRC_0;
2611 alu.src[1].chan = 0;
2612
2613 alu.last = 1;
2614
2615 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2616 if (r)
2617 return r;
2618 return 0;
2619 }
2620
2621 static int pops(struct r600_shader_ctx *ctx, int pops)
2622 {
2623 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2624 ctx->bc->cf_last->pop_count = pops;
2625 return 0;
2626 }
2627
2628 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2629 {
2630 switch(reason) {
2631 case FC_PUSH_VPM:
2632 ctx->bc->callstack[ctx->bc->call_sp].current--;
2633 break;
2634 case FC_PUSH_WQM:
2635 case FC_LOOP:
2636 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2637 break;
2638 case FC_REP:
2639 /* TOODO : for 16 vp asic should -= 2; */
2640 ctx->bc->callstack[ctx->bc->call_sp].current --;
2641 break;
2642 }
2643 }
2644
2645 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2646 {
2647 if (check_max_only) {
2648 int diff;
2649 switch (reason) {
2650 case FC_PUSH_VPM:
2651 diff = 1;
2652 break;
2653 case FC_PUSH_WQM:
2654 diff = 4;
2655 break;
2656 default:
2657 assert(0);
2658 diff = 0;
2659 }
2660 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2661 ctx->bc->callstack[ctx->bc->call_sp].max) {
2662 ctx->bc->callstack[ctx->bc->call_sp].max =
2663 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2664 }
2665 return;
2666 }
2667 switch (reason) {
2668 case FC_PUSH_VPM:
2669 ctx->bc->callstack[ctx->bc->call_sp].current++;
2670 break;
2671 case FC_PUSH_WQM:
2672 case FC_LOOP:
2673 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2674 break;
2675 case FC_REP:
2676 ctx->bc->callstack[ctx->bc->call_sp].current++;
2677 break;
2678 }
2679
2680 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2681 ctx->bc->callstack[ctx->bc->call_sp].max) {
2682 ctx->bc->callstack[ctx->bc->call_sp].max =
2683 ctx->bc->callstack[ctx->bc->call_sp].current;
2684 }
2685 }
2686
2687 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2688 {
2689 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2690
2691 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2692 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2693 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2694 sp->num_mid++;
2695 }
2696
2697 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2698 {
2699 ctx->bc->fc_sp++;
2700 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2701 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2702 }
2703
2704 static void fc_poplevel(struct r600_shader_ctx *ctx)
2705 {
2706 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2707 if (sp->mid) {
2708 free(sp->mid);
2709 sp->mid = NULL;
2710 }
2711 sp->num_mid = 0;
2712 sp->start = NULL;
2713 sp->type = 0;
2714 ctx->bc->fc_sp--;
2715 }
2716
2717 #if 0
2718 static int emit_return(struct r600_shader_ctx *ctx)
2719 {
2720 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2721 return 0;
2722 }
2723
2724 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2725 {
2726
2727 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2728 ctx->bc->cf_last->pop_count = pops;
2729 /* TODO work out offset */
2730 return 0;
2731 }
2732
2733 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2734 {
2735 return 0;
2736 }
2737
2738 static void emit_testflag(struct r600_shader_ctx *ctx)
2739 {
2740
2741 }
2742
2743 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2744 {
2745 emit_testflag(ctx);
2746 emit_jump_to_offset(ctx, 1, 4);
2747 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2748 pops(ctx, ifidx + 1);
2749 emit_return(ctx);
2750 }
2751
2752 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2753 {
2754 emit_testflag(ctx);
2755
2756 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2757 ctx->bc->cf_last->pop_count = 1;
2758
2759 fc_set_mid(ctx, fc_sp);
2760
2761 pops(ctx, 1);
2762 }
2763 #endif
2764
2765 static int tgsi_if(struct r600_shader_ctx *ctx)
2766 {
2767 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2768
2769 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2770
2771 fc_pushlevel(ctx, FC_IF);
2772
2773 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2774 return 0;
2775 }
2776
2777 static int tgsi_else(struct r600_shader_ctx *ctx)
2778 {
2779 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2780 ctx->bc->cf_last->pop_count = 1;
2781
2782 fc_set_mid(ctx, ctx->bc->fc_sp);
2783 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2784 return 0;
2785 }
2786
2787 static int tgsi_endif(struct r600_shader_ctx *ctx)
2788 {
2789 pops(ctx, 1);
2790 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2791 R600_ERR("if/endif unbalanced in shader\n");
2792 return -1;
2793 }
2794
2795 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2796 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2797 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2798 } else {
2799 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2800 }
2801 fc_poplevel(ctx);
2802
2803 callstack_decrease_current(ctx, FC_PUSH_VPM);
2804 return 0;
2805 }
2806
2807 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2808 {
2809 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2810
2811 fc_pushlevel(ctx, FC_LOOP);
2812
2813 /* check stack depth */
2814 callstack_check_depth(ctx, FC_LOOP, 0);
2815 return 0;
2816 }
2817
2818 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2819 {
2820 int i;
2821
2822 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2823
2824 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2825 R600_ERR("loop/endloop in shader code are not paired.\n");
2826 return -EINVAL;
2827 }
2828
2829 /* fixup loop pointers - from r600isa
2830 LOOP END points to CF after LOOP START,
2831 LOOP START point to CF after LOOP END
2832 BRK/CONT point to LOOP END CF
2833 */
2834 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2835
2836 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2837
2838 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2839 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2840 }
2841 /* TODO add LOOPRET support */
2842 fc_poplevel(ctx);
2843 callstack_decrease_current(ctx, FC_LOOP);
2844 return 0;
2845 }
2846
2847 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2848 {
2849 unsigned int fscp;
2850
2851 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2852 {
2853 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2854 break;
2855 }
2856
2857 if (fscp == 0) {
2858 R600_ERR("Break not inside loop/endloop pair\n");
2859 return -EINVAL;
2860 }
2861
2862 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2863 ctx->bc->cf_last->pop_count = 1;
2864
2865 fc_set_mid(ctx, fscp);
2866
2867 pops(ctx, 1);
2868 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2869 return 0;
2870 }
2871
2872 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2873 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2874 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2875 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2876
2877 /* FIXME:
2878 * For state trackers other than OpenGL, we'll want to use
2879 * _RECIP_IEEE instead.
2880 */
2881 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2882
2883 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2884 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2885 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2886 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2887 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2888 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2889 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2890 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2891 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2892 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2893 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2894 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2895 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2896 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2897 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2898 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2899 /* gap */
2900 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2901 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2902 /* gap */
2903 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2904 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2906 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2908 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2910 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2911 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2912 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2913 /* gap */
2914 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2916 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2917 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2918 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2919 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2920 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2921 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2922 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2924 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2926 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2927 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2928 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2930 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2931 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2932 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2933 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2934 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2935 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2937 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2948 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2949 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2950 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2951 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2954 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2955 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2956 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2957 /* gap */
2958 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2960 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2961 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2962 /* gap */
2963 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2968 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2969 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2971 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 /* gap */
2973 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2982 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2985 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2987 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 /* gap */
2989 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2993 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 /* gap */
2995 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3004 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3005 /* gap */
3006 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3010 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3015 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3026 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3027 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3028 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3029 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 };
3035
3036 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3037 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3039 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3040 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3041 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3042 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3043 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3044 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3045 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3046 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3047 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3048 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3049 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3050 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3051 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3052 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3053 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3054 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3055 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3056 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 /* gap */
3058 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 /* gap */
3061 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3064 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3066 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3068 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3069 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3070 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3071 /* gap */
3072 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3074 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3075 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3076 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3077 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3078 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3079 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3080 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3082 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3086 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3088 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3089 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3090 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3091 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3092 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3093 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3095 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3106 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3107 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3108 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3109 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3112 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3113 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3114 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3115 /* gap */
3116 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3118 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3119 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3120 /* gap */
3121 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3127 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3129 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 /* gap */
3131 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3132 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3140 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3143 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3145 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 /* gap */
3147 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3149 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 /* gap */
3153 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3154 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3156 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3157 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3158 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3159 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3160 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3161 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3162 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3163 /* gap */
3164 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3166 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3167 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3168 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3169 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3170 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3171 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3172 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3173 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3174 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3176 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3177 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3178 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3179 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3180 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3181 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3182 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3183 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3184 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3185 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3186 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3187 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3188 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3189 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3190 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3191 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3192 };