2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
38 struct r600_shader_tgsi_instruction
;
40 struct r600_shader_ctx
{
41 struct tgsi_shader_info info
;
42 struct tgsi_parse_context parse
;
43 const struct tgsi_token
*tokens
;
45 unsigned file_offset
[TGSI_FILE_COUNT
];
47 struct r600_shader_tgsi_instruction
*inst_info
;
49 struct r600_shader
*shader
;
53 struct r600_shader_tgsi_instruction
{
57 int (*process
)(struct r600_shader_ctx
*ctx
);
60 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[];
61 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
63 static int r600_shader_update(struct pipe_context
*ctx
, struct r600_shader
*shader
)
65 struct r600_context
*rctx
= r600_context(ctx
);
66 const struct util_format_description
*desc
;
67 enum pipe_format resource_format
[160];
68 unsigned i
, nresources
= 0;
69 struct r600_bc
*bc
= &shader
->bc
;
70 struct r600_bc_cf
*cf
;
71 struct r600_bc_vtx
*vtx
;
73 if (shader
->processor_type
!= TGSI_PROCESSOR_VERTEX
)
75 for (i
= 0; i
< rctx
->vertex_elements
->count
; i
++) {
76 resource_format
[nresources
++] = rctx
->vertex_elements
->elements
[i
].src_format
;
78 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
80 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
81 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
82 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
83 desc
= util_format_description(resource_format
[vtx
->buffer_id
]);
85 R600_ERR("unknown format %d\n", resource_format
[vtx
->buffer_id
]);
88 vtx
->dst_sel_x
= desc
->swizzle
[0];
89 vtx
->dst_sel_y
= desc
->swizzle
[1];
90 vtx
->dst_sel_z
= desc
->swizzle
[2];
91 vtx
->dst_sel_w
= desc
->swizzle
[3];
98 return r600_bc_build(&shader
->bc
);
101 int r600_pipe_shader_create(struct pipe_context
*ctx
,
102 struct r600_context_state
*rpshader
,
103 const struct tgsi_token
*tokens
)
105 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
108 //fprintf(stderr, "--------------------------------------------------------------\n");
109 //tgsi_dump(tokens, 0);
110 if (rpshader
== NULL
)
112 rpshader
->shader
.family
= radeon_get_family(rscreen
->rw
);
113 r
= r600_shader_from_tgsi(tokens
, &rpshader
->shader
);
115 R600_ERR("translation from TGSI failed !\n");
118 r
= r600_bc_build(&rpshader
->shader
.bc
);
120 R600_ERR("building bytecode failed !\n");
123 //fprintf(stderr, "______________________________________________________________\n");
127 static int r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
129 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
130 struct r600_shader
*rshader
= &rpshader
->shader
;
131 struct radeon_state
*state
;
134 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
135 state
= radeon_state(rscreen
->rw
, R600_VS_SHADER_TYPE
, R600_VS_SHADER
);
138 for (i
= 0; i
< 10; i
++) {
139 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
] = 0;
141 /* so far never got proper semantic id from tgsi */
142 for (i
= 0; i
< 32; i
++) {
143 tmp
= i
<< ((i
& 3) * 8);
144 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
/ 4] |= tmp
;
146 state
->states
[R600_VS_SHADER__SPI_VS_OUT_CONFIG
] = S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2);
147 state
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
148 S_028868_STACK_SIZE(rshader
->bc
.nstack
);
149 rpshader
->rstate
= state
;
150 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
151 rpshader
->rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
152 rpshader
->rstate
->nbo
= 2;
153 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
154 rpshader
->rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
155 return radeon_state_pm4(state
);
158 static int r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
160 const struct pipe_rasterizer_state
*rasterizer
;
161 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
162 struct r600_shader
*rshader
= &rpshader
->shader
;
163 struct r600_context
*rctx
= r600_context(ctx
);
164 struct radeon_state
*state
;
165 unsigned i
, tmp
, exports_ps
, num_cout
;
167 rasterizer
= &rctx
->rasterizer
->state
.rasterizer
;
168 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
169 state
= radeon_state(rscreen
->rw
, R600_PS_SHADER_TYPE
, R600_PS_SHADER
);
172 for (i
= 0; i
< rshader
->ninput
; i
++) {
173 tmp
= S_028644_SEMANTIC(i
);
174 tmp
|= S_028644_SEL_CENTROID(1);
175 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
176 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
) {
177 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
179 if (rasterizer
->sprite_coord_enable
& (1 << i
)) {
180 tmp
|= S_028644_PT_SPRITE_TEX(1);
182 state
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
+ i
] = tmp
;
187 for (i
= 0; i
< rshader
->noutput
; i
++) {
188 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
190 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
191 exports_ps
|= (1 << (num_cout
+1));
196 /* always at least export 1 component per pixel */
199 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] = S_0286CC_NUM_INTERP(rshader
->ninput
) |
200 S_0286CC_PERSP_GRADIENT_ENA(1);
201 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_1
] = 0x00000000;
202 state
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
203 S_028868_STACK_SIZE(rshader
->bc
.nstack
);
204 state
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = exports_ps
;
205 rpshader
->rstate
= state
;
206 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
207 rpshader
->rstate
->nbo
= 1;
208 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
209 return radeon_state_pm4(state
);
212 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
214 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
215 struct r600_context
*rctx
= r600_context(ctx
);
216 struct r600_shader
*rshader
= &rpshader
->shader
;
219 /* copy new shader */
220 radeon_bo_decref(rscreen
->rw
, rpshader
->bo
);
222 rpshader
->bo
= radeon_bo(rscreen
->rw
, 0, rshader
->bc
.ndw
* 4,
224 if (rpshader
->bo
== NULL
) {
227 radeon_bo_map(rscreen
->rw
, rpshader
->bo
);
228 memcpy(rpshader
->bo
->data
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
229 radeon_bo_unmap(rscreen
->rw
, rpshader
->bo
);
231 rshader
->flat_shade
= rctx
->flat_shade
;
232 switch (rshader
->processor_type
) {
233 case TGSI_PROCESSOR_VERTEX
:
234 r
= r600_pipe_shader_vs(ctx
, rpshader
);
236 case TGSI_PROCESSOR_FRAGMENT
:
237 r
= r600_pipe_shader_ps(ctx
, rpshader
);
246 int r600_pipe_shader_update(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
248 struct r600_context
*rctx
= r600_context(ctx
);
251 if (rpshader
== NULL
)
253 /* there should be enough input */
254 if (rctx
->vertex_elements
->count
< rpshader
->shader
.bc
.nresource
) {
255 R600_ERR("%d resources provided, expecting %d\n",
256 rctx
->vertex_elements
->count
, rpshader
->shader
.bc
.nresource
);
259 r
= r600_shader_update(ctx
, &rpshader
->shader
);
262 return r600_pipe_shader(ctx
, rpshader
);
265 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
267 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
270 if (i
->Instruction
.NumDstRegs
> 1) {
271 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
274 if (i
->Instruction
.Predicate
) {
275 R600_ERR("predicate unsupported\n");
279 if (i
->Instruction
.Label
) {
280 R600_ERR("label unsupported\n");
284 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
285 if (i
->Src
[j
].Register
.Indirect
||
286 i
->Src
[j
].Register
.Dimension
||
287 i
->Src
[j
].Register
.Absolute
) {
288 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
292 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
293 if (i
->Dst
[j
].Register
.Indirect
|| i
->Dst
[j
].Register
.Dimension
) {
294 R600_ERR("unsupported dst (indirect|dimension)\n");
301 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
303 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
304 struct r600_bc_vtx vtx
;
308 switch (d
->Declaration
.File
) {
309 case TGSI_FILE_INPUT
:
310 i
= ctx
->shader
->ninput
++;
311 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
312 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
313 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
314 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
315 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
316 /* turn input into fetch */
317 memset(&vtx
, 0, sizeof(struct r600_bc_vtx
));
321 /* register containing the index into the buffer */
324 vtx
.mega_fetch_count
= 0x1F;
325 vtx
.dst_gpr
= ctx
->shader
->input
[i
].gpr
;
330 r
= r600_bc_add_vtx(ctx
->bc
, &vtx
);
335 case TGSI_FILE_OUTPUT
:
336 i
= ctx
->shader
->noutput
++;
337 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
338 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
339 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
340 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
342 case TGSI_FILE_CONSTANT
:
343 case TGSI_FILE_TEMPORARY
:
344 case TGSI_FILE_SAMPLER
:
347 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
353 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
355 struct tgsi_full_immediate
*immediate
;
356 struct r600_shader_ctx ctx
;
357 struct r600_bc_output output
[32];
358 unsigned output_done
, noutput
;
362 ctx
.bc
= &shader
->bc
;
364 r
= r600_bc_init(ctx
.bc
, shader
->family
);
368 tgsi_scan_shader(tokens
, &ctx
.info
);
369 tgsi_parse_init(&ctx
.parse
, tokens
);
370 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
371 shader
->processor_type
= ctx
.type
;
373 /* register allocations */
374 /* Values [0,127] correspond to GPR[0..127].
375 * Values [128,159] correspond to constant buffer bank 0
376 * Values [160,191] correspond to constant buffer bank 1
377 * Values [256,511] correspond to cfile constants c[0..255].
378 * Other special values are shown in the list below.
379 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
380 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
381 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
382 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
383 * 248 SQ_ALU_SRC_0: special constant 0.0.
384 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
385 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
386 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
387 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
388 * 253 SQ_ALU_SRC_LITERAL: literal constant.
389 * 254 SQ_ALU_SRC_PV: previous vector result.
390 * 255 SQ_ALU_SRC_PS: previous scalar result.
392 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
393 ctx
.file_offset
[i
] = 0;
395 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
396 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
398 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
399 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
400 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
401 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
402 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 256;
403 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = 253;
404 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
405 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
407 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
408 tgsi_parse_token(&ctx
.parse
);
409 switch (ctx
.parse
.FullToken
.Token
.Type
) {
410 case TGSI_TOKEN_TYPE_IMMEDIATE
:
411 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
412 ctx
.value
[0] = immediate
->u
[0].Uint
;
413 ctx
.value
[1] = immediate
->u
[1].Uint
;
414 ctx
.value
[2] = immediate
->u
[2].Uint
;
415 ctx
.value
[3] = immediate
->u
[3].Uint
;
417 case TGSI_TOKEN_TYPE_DECLARATION
:
418 r
= tgsi_declaration(&ctx
);
422 case TGSI_TOKEN_TYPE_INSTRUCTION
:
423 r
= tgsi_is_supported(&ctx
);
426 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
427 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
428 r
= ctx
.inst_info
->process(&ctx
);
431 r
= r600_bc_add_literal(ctx
.bc
, ctx
.value
);
436 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
442 noutput
= shader
->noutput
;
443 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
444 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
445 output
[i
].gpr
= shader
->output
[i
].gpr
;
446 output
[i
].elem_size
= 3;
447 output
[i
].swizzle_x
= 0;
448 output
[i
].swizzle_y
= 1;
449 output
[i
].swizzle_z
= 2;
450 output
[i
].swizzle_w
= 3;
451 output
[i
].barrier
= 1;
452 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
453 output
[i
].array_base
= i
- pos0
;
454 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
456 case TGSI_PROCESSOR_VERTEX
:
457 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
458 output
[i
].array_base
= 60;
459 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
460 /* position doesn't count in array_base */
463 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
464 output
[i
].array_base
= 61;
465 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
466 /* position doesn't count in array_base */
470 case TGSI_PROCESSOR_FRAGMENT
:
471 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
472 output
[i
].array_base
= shader
->output
[i
].sid
;
473 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
474 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
475 output
[i
].array_base
= 61;
476 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
478 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
484 R600_ERR("unsupported processor type %d\n", ctx
.type
);
489 /* add fake param output for vertex shader if no param is exported */
490 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
491 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
492 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
498 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
500 output
[i
].elem_size
= 3;
501 output
[i
].swizzle_x
= 0;
502 output
[i
].swizzle_y
= 1;
503 output
[i
].swizzle_z
= 2;
504 output
[i
].swizzle_w
= 3;
505 output
[i
].barrier
= 1;
506 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
507 output
[i
].array_base
= 0;
508 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
512 /* add fake pixel export */
513 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
514 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
516 output
[0].elem_size
= 3;
517 output
[0].swizzle_x
= 7;
518 output
[0].swizzle_y
= 7;
519 output
[0].swizzle_z
= 7;
520 output
[0].swizzle_w
= 7;
521 output
[0].barrier
= 1;
522 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
523 output
[0].array_base
= 0;
524 output
[0].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
527 /* set export done on last export of each type */
528 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
529 if (i
== (noutput
- 1)) {
530 output
[i
].end_of_program
= 1;
532 if (!(output_done
& (1 << output
[i
].type
))) {
533 output_done
|= (1 << output
[i
].type
);
534 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
;
537 /* add output to bytecode */
538 for (i
= 0; i
< noutput
; i
++) {
539 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
543 tgsi_parse_free(&ctx
.parse
);
546 tgsi_parse_free(&ctx
.parse
);
550 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
552 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
556 static int tgsi_end(struct r600_shader_ctx
*ctx
)
561 static int tgsi_src(struct r600_shader_ctx
*ctx
,
562 const struct tgsi_full_src_register
*tgsi_src
,
563 struct r600_bc_alu_src
*r600_src
)
565 memset(r600_src
, 0, sizeof(struct r600_bc_alu_src
));
566 r600_src
->sel
= tgsi_src
->Register
.Index
;
567 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
570 r600_src
->neg
= tgsi_src
->Register
.Negate
;
571 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
575 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
576 const struct tgsi_full_dst_register
*tgsi_dst
,
578 struct r600_bc_alu_dst
*r600_dst
)
580 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
582 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
583 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
584 r600_dst
->chan
= swizzle
;
586 if (inst
->Instruction
.Saturate
) {
592 static unsigned tgsi_chan(const struct tgsi_full_src_register
*tgsi_src
, unsigned swizzle
)
596 return tgsi_src
->Register
.SwizzleX
;
598 return tgsi_src
->Register
.SwizzleY
;
600 return tgsi_src
->Register
.SwizzleZ
;
602 return tgsi_src
->Register
.SwizzleW
;
608 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
610 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
611 struct r600_bc_alu alu
;
612 int i
, j
, k
, nconst
, r
;
614 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
615 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
618 r
= tgsi_src(ctx
, &inst
->Src
[i
], &r600_src
[i
]);
623 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
624 if (inst
->Src
[j
].Register
.File
== TGSI_FILE_CONSTANT
&& j
> 0) {
625 for (k
= 0; k
< 4; k
++) {
626 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
627 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
628 alu
.src
[0].sel
= r600_src
[0].sel
;
630 alu
.dst
.sel
= ctx
->temp_reg
+ j
;
635 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
639 r600_src
[0].sel
= ctx
->temp_reg
+ j
;
646 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
)
648 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
649 struct r600_bc_alu_src r600_src
[3];
650 struct r600_bc_alu alu
;
654 for (i
= 0; i
< 4; i
++) {
655 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
660 r
= tgsi_split_constant(ctx
, r600_src
);
663 for (i
= 0; i
< lasti
+ 1; i
++) {
664 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
667 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
668 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
672 alu
.inst
= ctx
->inst_info
->r600_opcode
;
674 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
675 alu
.src
[j
] = r600_src
[j
];
676 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
679 alu
.src
[0] = r600_src
[1];
680 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
682 alu
.src
[1] = r600_src
[0];
683 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
685 /* handle some special cases */
686 switch (ctx
->inst_info
->tgsi_opcode
) {
687 case TGSI_OPCODE_SUB
:
690 case TGSI_OPCODE_ABS
:
699 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
706 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
708 return tgsi_op2_s(ctx
, 0);
711 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
713 return tgsi_op2_s(ctx
, 1);
717 * r600 - trunc to -PI..PI range
718 * r700 - normalize by dividing by 2PI
721 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
723 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
724 struct r600_bc_alu_src r600_src
[3];
725 struct r600_bc_alu alu
;
727 uint32_t lit_vals
[4];
729 memset(lit_vals
, 0, 4*4);
730 r
= tgsi_split_constant(ctx
, r600_src
);
733 lit_vals
[0] = fui(1.0 /(3.1415926535 * 2));
734 lit_vals
[1] = fui(0.5f
);
736 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
737 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
741 alu
.dst
.sel
= ctx
->temp_reg
;
744 alu
.src
[0] = r600_src
[0];
745 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
747 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
749 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
752 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
755 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
759 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
760 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
;
763 alu
.dst
.sel
= ctx
->temp_reg
;
766 alu
.src
[0].sel
= ctx
->temp_reg
;
769 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
773 if (ctx
->bc
->chiprev
== 0) {
774 lit_vals
[0] = fui(3.1415926535897f
* 2.0f
);
775 lit_vals
[1] = fui(-3.1415926535897f
);
777 lit_vals
[0] = fui(1.0f
);
778 lit_vals
[1] = fui(-0.5f
);
781 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
782 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
786 alu
.dst
.sel
= ctx
->temp_reg
;
789 alu
.src
[0].sel
= ctx
->temp_reg
;
792 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
794 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
797 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
800 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
804 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
805 alu
.inst
= ctx
->inst_info
->r600_opcode
;
807 alu
.dst
.sel
= ctx
->temp_reg
;
810 alu
.src
[0].sel
= ctx
->temp_reg
;
813 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
817 /* replicate result */
818 for (i
= 0; i
< 4; i
++) {
819 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
820 alu
.src
[0].sel
= ctx
->temp_reg
;
821 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
823 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
826 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
829 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
836 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
838 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
839 struct r600_bc_alu alu
;
842 for (i
= 0; i
< 4; i
++) {
843 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
844 alu
.inst
= ctx
->inst_info
->r600_opcode
;
846 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
847 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
850 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
854 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
861 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
863 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
864 struct r600_bc_alu alu
;
868 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
869 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
870 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
872 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
875 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
876 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
880 /* dst.y = max(src.x, 0.0) */
881 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
882 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
;
883 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
886 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
887 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 0);
888 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
891 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
892 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
896 /* dst.z = NOP - fill Z slot */
897 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
898 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
900 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
905 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
906 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
907 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
909 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
912 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
914 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
918 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
923 /* dst.z = log(src.y) */
924 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
925 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
;
926 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
929 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
930 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
934 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
941 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
942 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
943 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
944 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
947 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
948 alu
.src
[1].sel
= sel
;
949 alu
.src
[1].chan
= chan
;
950 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[2]);
953 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], 0);
954 alu
.dst
.sel
= ctx
->temp_reg
;
959 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
963 /* dst.z = exp(tmp.x) */
964 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
965 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
966 alu
.src
[0].sel
= ctx
->temp_reg
;
968 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
972 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
979 static int tgsi_trans(struct r600_shader_ctx
*ctx
)
981 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
982 struct r600_bc_alu alu
;
985 for (i
= 0; i
< 4; i
++) {
986 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
987 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
988 alu
.inst
= ctx
->inst_info
->r600_opcode
;
989 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
990 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
993 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
995 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
999 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1007 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
1009 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1010 struct r600_bc_alu alu
;
1013 for (i
= 0; i
< 4; i
++) {
1014 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1015 alu
.src
[0].sel
= ctx
->temp_reg
;
1016 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1018 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1021 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1024 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1031 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
1033 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1034 struct r600_bc_alu alu
;
1037 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1038 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1039 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1040 r
= tgsi_src(ctx
, &inst
->Src
[i
], &alu
.src
[i
]);
1043 alu
.src
[i
].chan
= tgsi_chan(&inst
->Src
[i
], 0);
1045 alu
.dst
.sel
= ctx
->temp_reg
;
1048 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1051 /* replicate result */
1052 return tgsi_helper_tempx_replicate(ctx
);
1055 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
1057 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1058 struct r600_bc_alu alu
;
1062 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1063 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
;
1064 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1067 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1068 alu
.dst
.sel
= ctx
->temp_reg
;
1071 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1075 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1076 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE
;
1077 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[0]);
1080 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], 0);
1081 alu
.src
[1].sel
= ctx
->temp_reg
;
1082 alu
.dst
.sel
= ctx
->temp_reg
;
1085 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1088 /* POW(a,b) = EXP2(b * LOG2(a))*/
1089 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1090 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
1091 alu
.src
[0].sel
= ctx
->temp_reg
;
1092 alu
.dst
.sel
= ctx
->temp_reg
;
1095 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1098 return tgsi_helper_tempx_replicate(ctx
);
1101 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
1103 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1104 struct r600_bc_alu alu
;
1105 struct r600_bc_alu_src r600_src
[3];
1108 r
= tgsi_split_constant(ctx
, r600_src
);
1112 /* tmp = (src > 0 ? 1 : src) */
1113 for (i
= 0; i
< 4; i
++) {
1114 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1115 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
;
1117 alu
.dst
.sel
= ctx
->temp_reg
;
1120 alu
.src
[0] = r600_src
[0];
1121 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1123 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1125 alu
.src
[2] = r600_src
[0];
1126 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], i
);
1129 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1134 /* dst = (-tmp > 0 ? -1 : tmp) */
1135 for (i
= 0; i
< 4; i
++) {
1136 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1137 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
;
1139 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1143 alu
.src
[0].sel
= ctx
->temp_reg
;
1146 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1149 alu
.src
[2].sel
= ctx
->temp_reg
;
1154 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1161 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
1163 struct r600_bc_alu alu
;
1166 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1169 for (i
= 0; i
< 4; i
++) {
1170 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1171 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
1172 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
1175 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1176 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1179 alu
.src
[0].sel
= ctx
->temp_reg
;
1180 alu
.src
[0].chan
= i
;
1185 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1192 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
1194 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1195 struct r600_bc_alu_src r600_src
[3];
1196 struct r600_bc_alu alu
;
1199 r
= tgsi_split_constant(ctx
, r600_src
);
1202 /* do it in 2 step as op3 doesn't support writemask */
1203 for (i
= 0; i
< 4; i
++) {
1204 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1205 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1206 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1207 alu
.src
[j
] = r600_src
[j
];
1208 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1210 alu
.dst
.sel
= ctx
->temp_reg
;
1217 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1221 return tgsi_helper_copy(ctx
, inst
);
1224 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
1226 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1227 struct r600_bc_alu_src r600_src
[3];
1228 struct r600_bc_alu alu
;
1231 r
= tgsi_split_constant(ctx
, r600_src
);
1234 for (i
= 0; i
< 4; i
++) {
1235 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1236 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1237 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1238 alu
.src
[j
] = r600_src
[j
];
1239 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1241 alu
.dst
.sel
= ctx
->temp_reg
;
1244 /* handle some special cases */
1245 switch (ctx
->inst_info
->tgsi_opcode
) {
1246 case TGSI_OPCODE_DP2
:
1248 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1249 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1252 case TGSI_OPCODE_DP3
:
1254 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1255 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1258 case TGSI_OPCODE_DPH
:
1260 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1261 alu
.src
[0].chan
= 0;
1271 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1275 return tgsi_helper_copy(ctx
, inst
);
1278 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1280 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1281 struct r600_bc_tex tex
;
1282 struct r600_bc_alu alu
;
1286 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1288 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1289 /* Add perspective divide */
1290 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1291 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
1292 alu
.src
[0].sel
= src_gpr
;
1293 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1294 alu
.dst
.sel
= ctx
->temp_reg
;
1298 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1302 for (i
= 0; i
< 3; i
++) {
1303 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1304 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1305 alu
.src
[0].sel
= ctx
->temp_reg
;
1306 alu
.src
[0].chan
= 3;
1307 alu
.src
[1].sel
= src_gpr
;
1308 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1309 alu
.dst
.sel
= ctx
->temp_reg
;
1312 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1316 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1317 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1318 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1319 alu
.src
[0].chan
= 0;
1320 alu
.dst
.sel
= ctx
->temp_reg
;
1324 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1327 src_gpr
= ctx
->temp_reg
;
1328 } else if (inst
->Src
[0].Register
.File
!= TGSI_FILE_TEMPORARY
) {
1329 for (i
= 0; i
< 4; i
++) {
1330 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1331 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1332 alu
.src
[0].sel
= src_gpr
;
1333 alu
.src
[0].chan
= i
;
1334 alu
.dst
.sel
= ctx
->temp_reg
;
1339 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1343 src_gpr
= ctx
->temp_reg
;
1346 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1347 tex
.inst
= ctx
->inst_info
->r600_opcode
;
1348 tex
.resource_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1349 tex
.sampler_id
= tex
.resource_id
;
1350 tex
.src_gpr
= src_gpr
;
1351 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1361 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1362 tex
.coord_type_x
= 1;
1363 tex
.coord_type_y
= 1;
1364 tex
.coord_type_z
= 1;
1365 tex
.coord_type_w
= 1;
1367 return r600_bc_add_tex(ctx
->bc
, &tex
);
1370 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1372 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1373 struct r600_bc_alu_src r600_src
[3];
1374 struct r600_bc_alu alu
;
1378 r
= tgsi_split_constant(ctx
, r600_src
);
1382 for (i
= 0; i
< 4; i
++) {
1383 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1384 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
;
1385 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1386 alu
.src
[0].chan
= 0;
1387 alu
.src
[1] = r600_src
[0];
1388 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1390 alu
.dst
.sel
= ctx
->temp_reg
;
1396 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1400 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1404 /* (1 - src0) * src2 */
1405 for (i
= 0; i
< 4; i
++) {
1406 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1407 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1408 alu
.src
[0].sel
= ctx
->temp_reg
;
1409 alu
.src
[0].chan
= i
;
1410 alu
.src
[1] = r600_src
[2];
1411 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1412 alu
.dst
.sel
= ctx
->temp_reg
;
1418 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1422 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1426 /* src0 * src1 + (1 - src0) * src2 */
1427 for (i
= 0; i
< 4; i
++) {
1428 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1429 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1431 alu
.src
[0] = r600_src
[0];
1432 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1433 alu
.src
[1] = r600_src
[1];
1434 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
1435 alu
.src
[2].sel
= ctx
->temp_reg
;
1436 alu
.src
[2].chan
= i
;
1437 alu
.dst
.sel
= ctx
->temp_reg
;
1442 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1446 return tgsi_helper_copy(ctx
, inst
);
1449 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
1451 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1452 struct r600_bc_alu_src r600_src
[3];
1453 struct r600_bc_alu alu
;
1457 r
= tgsi_split_constant(ctx
, r600_src
);
1461 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
1464 for (i
= 0; i
< 4; i
++) {
1465 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1466 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
;
1467 alu
.src
[0] = r600_src
[0];
1468 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1470 alu
.src
[1] = r600_src
[2];
1471 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1473 alu
.src
[2] = r600_src
[1];
1474 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[1], i
);
1477 alu
.dst
.sel
= ctx
->temp_reg
;
1479 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1488 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1493 return tgsi_helper_copy(ctx
, inst
);
1497 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
1499 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1500 struct r600_bc_alu_src r600_src
[3];
1501 struct r600_bc_alu alu
;
1502 uint32_t use_temp
= 0;
1505 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
1508 r
= tgsi_split_constant(ctx
, r600_src
);
1512 for (i
= 0; i
< 4; i
++) {
1513 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1514 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1516 alu
.src
[0] = r600_src
[0];
1519 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
1522 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1525 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
1528 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1529 alu
.src
[0].chan
= i
;
1532 alu
.src
[1] = r600_src
[1];
1535 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
1538 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
1541 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
1544 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1545 alu
.src
[1].chan
= i
;
1548 alu
.dst
.sel
= ctx
->temp_reg
;
1554 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1559 for (i
= 0; i
< 4; i
++) {
1560 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1561 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1563 alu
.src
[0] = r600_src
[0];
1566 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
1569 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
1572 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1575 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1576 alu
.src
[0].chan
= i
;
1579 alu
.src
[1] = r600_src
[1];
1582 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
1585 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
1588 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
1591 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1592 alu
.src
[1].chan
= i
;
1595 alu
.src
[2].sel
= ctx
->temp_reg
;
1597 alu
.src
[2].chan
= i
;
1600 alu
.dst
.sel
= ctx
->temp_reg
;
1602 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1611 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1616 return tgsi_helper_copy(ctx
, inst
);
1620 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
1622 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1623 struct r600_bc_alu_src r600_src
[3];
1624 struct r600_bc_alu alu
;
1625 uint32_t use_temp
= 0;
1628 /* result.x = 2^floor(src); */
1629 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
1630 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1632 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
;
1633 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1637 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1639 alu
.dst
.sel
= ctx
->temp_reg
;
1643 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1647 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
1648 alu
.src
[0].sel
= ctx
->temp_reg
;
1649 alu
.src
[0].chan
= 0;
1651 alu
.dst
.sel
= ctx
->temp_reg
;
1655 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1660 /* result.y = tmp - floor(tmp); */
1661 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
1662 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1664 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
;
1665 alu
.src
[0] = r600_src
[0];
1666 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1669 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1671 alu
.dst
.sel
= ctx
->temp_reg
;
1672 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1680 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1685 /* result.z = RoughApprox2ToX(tmp);*/
1686 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
1687 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1688 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
1689 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1692 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1694 alu
.dst
.sel
= ctx
->temp_reg
;
1700 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1706 /* result.w = 1.0;*/
1707 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
1708 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1710 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1711 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1712 alu
.src
[0].chan
= 0;
1714 alu
.dst
.sel
= ctx
->temp_reg
;
1718 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1722 return tgsi_helper_copy(ctx
, inst
);
1725 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
1727 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1728 struct r600_bc_alu alu
, *lalu
;
1729 struct r600_bc_cf
*last
;
1732 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1736 alu
.dst
.sel
= ctx
->temp_reg
;
1740 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1743 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1744 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1745 alu
.src
[1].chan
= 0;
1749 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
);
1756 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
1758 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_POP
);
1759 ctx
->bc
->cf_last
->pop_count
= pops
;
1763 static int tgsi_if(struct r600_shader_ctx
*ctx
)
1765 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1767 emit_logic_pred(ctx
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
);
1770 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= FC_IF
;
1771 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
= NULL
;
1772 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_JUMP
);
1774 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
1778 static int tgsi_else(struct r600_shader_ctx
*ctx
)
1780 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1781 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_ELSE
);
1782 ctx
->bc
->cf_last
->pop_count
= 1;
1785 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
= ctx
->bc
->cf_last
;
1786 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
1790 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
1793 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
1794 R600_ERR("if/endif unbalanced in shader\n");
1798 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
1799 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
1800 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
1802 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
1809 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
1810 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1811 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1812 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
1813 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
1814 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
1815 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
1816 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1817 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
1818 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1819 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1820 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1821 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1822 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
1823 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
1824 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
1825 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
1826 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
1827 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1828 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
1829 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1831 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1832 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1834 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1835 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1836 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
1837 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1838 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
1839 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1840 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
1841 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
1842 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
1843 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
1845 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1846 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1847 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1848 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1849 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
1850 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
1851 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
1852 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
}, /* predicated kill */
1853 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1854 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1855 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1856 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1857 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1858 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
1859 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1860 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
1861 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
1862 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
1863 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
1864 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1865 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
1866 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1867 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
1868 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1869 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1870 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1871 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1872 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1873 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1874 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1875 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1876 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1877 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1878 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
1879 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
1880 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1881 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
1882 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1883 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1884 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1885 {TGSI_OPCODE_TXL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1886 {TGSI_OPCODE_BRK
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1887 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
1889 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1890 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1891 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
1892 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
1894 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1895 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1896 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1897 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1898 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1899 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1900 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1901 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
1902 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1904 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1905 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1906 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1907 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1908 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1909 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1910 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1911 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1912 {TGSI_OPCODE_CONT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1913 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1914 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1915 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1916 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1917 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1918 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1920 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1921 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1922 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1923 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1924 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1926 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1927 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1928 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1929 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1930 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1931 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1932 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1933 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1934 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
1935 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
1937 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1938 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1939 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1940 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1941 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1942 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1943 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1944 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1945 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1946 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1947 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1948 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1949 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1950 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1951 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1952 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1953 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1954 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1955 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1956 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1957 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1958 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1959 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1960 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1961 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1962 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1963 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1964 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},