2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
31 #include "r600_formats.h"
32 #include "r600_opcodes.h"
37 int r600_find_vs_semantic_index(struct r600_shader
*vs
,
38 struct r600_shader
*ps
, int id
)
40 struct r600_shader_io
*input
= &ps
->input
[id
];
42 for (int i
= 0; i
< vs
->noutput
; i
++) {
43 if (input
->name
== vs
->output
[i
].name
&&
44 input
->sid
== vs
->output
[i
].sid
) {
51 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
53 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
54 struct r600_shader
*rshader
= &shader
->shader
;
58 if (shader
->bo
== NULL
) {
59 shader
->bo
= r600_bo(rctx
->radeon
, rshader
->bc
.ndw
* 4, 4096, 0, 0);
60 if (shader
->bo
== NULL
) {
63 ptr
= r600_bo_map(rctx
->radeon
, shader
->bo
, 0, NULL
);
64 memcpy(ptr
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
65 r600_bo_unmap(rctx
->radeon
, shader
->bo
);
68 switch (rshader
->processor_type
) {
69 case TGSI_PROCESSOR_VERTEX
:
70 if (rshader
->family
>= CHIP_CEDAR
) {
71 evergreen_pipe_shader_vs(ctx
, shader
);
73 r600_pipe_shader_vs(ctx
, shader
);
76 case TGSI_PROCESSOR_FRAGMENT
:
77 if (rshader
->family
>= CHIP_CEDAR
) {
78 evergreen_pipe_shader_ps(ctx
, shader
);
80 r600_pipe_shader_ps(ctx
, shader
);
89 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
91 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
, const struct tgsi_token
*tokens
)
93 static int dump_shaders
= -1;
94 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
97 /* Would like some magic "get_bool_option_once" routine.
99 if (dump_shaders
== -1)
100 dump_shaders
= debug_get_bool_option("R600_DUMP_SHADERS", FALSE
);
103 fprintf(stderr
, "--------------------------------------------------------------\n");
104 tgsi_dump(tokens
, 0);
106 shader
->shader
.family
= r600_get_family(rctx
->radeon
);
107 r
= r600_shader_from_tgsi(tokens
, &shader
->shader
);
109 R600_ERR("translation from TGSI failed !\n");
112 r
= r600_bc_build(&shader
->shader
.bc
);
114 R600_ERR("building bytecode failed !\n");
118 r600_bc_dump(&shader
->shader
.bc
);
119 fprintf(stderr
, "______________________________________________________________\n");
121 return r600_pipe_shader(ctx
, shader
);
124 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
126 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
128 r600_bo_reference(rctx
->radeon
, &shader
->bo
, NULL
);
129 r600_bc_clear(&shader
->shader
.bc
);
133 * tgsi -> r600 shader
135 struct r600_shader_tgsi_instruction
;
137 struct r600_shader_src
{
146 struct r600_shader_ctx
{
147 struct tgsi_shader_info info
;
148 struct tgsi_parse_context parse
;
149 const struct tgsi_token
*tokens
;
151 unsigned file_offset
[TGSI_FILE_COUNT
];
154 struct r600_shader_tgsi_instruction
*inst_info
;
156 struct r600_shader
*shader
;
157 struct r600_shader_src src
[3];
160 u32 max_driver_temp_used
;
161 /* needed for evergreen interpolation */
162 boolean input_centroid
;
163 boolean input_linear
;
164 boolean input_perspective
;
168 struct r600_shader_tgsi_instruction
{
169 unsigned tgsi_opcode
;
171 unsigned r600_opcode
;
172 int (*process
)(struct r600_shader_ctx
*ctx
);
175 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[];
176 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
178 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
180 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
183 if (i
->Instruction
.NumDstRegs
> 1) {
184 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
187 if (i
->Instruction
.Predicate
) {
188 R600_ERR("predicate unsupported\n");
192 if (i
->Instruction
.Label
) {
193 R600_ERR("label unsupported\n");
197 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
198 if (i
->Src
[j
].Register
.Dimension
) {
199 R600_ERR("unsupported src %d (dimension %d)\n", j
,
200 i
->Src
[j
].Register
.Dimension
);
204 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
205 if (i
->Dst
[j
].Register
.Dimension
) {
206 R600_ERR("unsupported dst (dimension)\n");
213 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
216 struct r600_bc_alu alu
;
217 int gpr
= 0, base_chan
= 0;
220 if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
) {
222 if (ctx
->shader
->input
[input
].centroid
)
224 } else if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
226 /* if we have perspective add one */
227 if (ctx
->input_perspective
) {
229 /* if we have perspective centroid */
230 if (ctx
->input_centroid
)
233 if (ctx
->shader
->input
[input
].centroid
)
237 /* work out gpr and base_chan from index */
239 base_chan
= (2 * (ij_index
% 2)) + 1;
241 for (i
= 0; i
< 8; i
++) {
242 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
245 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW
;
247 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY
;
249 if ((i
> 1) && (i
< 6)) {
250 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
254 alu
.dst
.chan
= i
% 4;
256 alu
.src
[0].sel
= gpr
;
257 alu
.src
[0].chan
= (base_chan
- (i
% 2));
259 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
261 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
264 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
272 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
274 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
278 switch (d
->Declaration
.File
) {
279 case TGSI_FILE_INPUT
:
280 i
= ctx
->shader
->ninput
++;
281 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
282 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
283 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
284 ctx
->shader
->input
[i
].centroid
= d
->Declaration
.Centroid
;
285 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
286 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
->bc
->chiprev
== CHIPREV_EVERGREEN
) {
287 /* turn input into interpolate on EG */
288 if (ctx
->shader
->input
[i
].name
!= TGSI_SEMANTIC_POSITION
) {
289 if (ctx
->shader
->input
[i
].interpolate
> 0) {
290 ctx
->shader
->input
[i
].lds_pos
= ctx
->shader
->nlds
++;
291 evergreen_interp_alu(ctx
, i
);
296 case TGSI_FILE_OUTPUT
:
297 i
= ctx
->shader
->noutput
++;
298 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
299 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
300 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
301 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
303 case TGSI_FILE_CONSTANT
:
304 case TGSI_FILE_TEMPORARY
:
305 case TGSI_FILE_SAMPLER
:
306 case TGSI_FILE_ADDRESS
:
309 case TGSI_FILE_SYSTEM_VALUE
:
310 if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
311 struct r600_bc_alu alu
;
312 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
314 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT
);
323 if ((r
= r600_bc_add_alu(ctx
->bc
, &alu
)))
329 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
335 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
337 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
341 * for evergreen we need to scan the shader to find the number of GPRs we need to
342 * reserve for interpolation.
344 * we need to know if we are going to emit
345 * any centroid inputs
346 * if perspective and linear are required
348 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
353 ctx
->input_linear
= FALSE
;
354 ctx
->input_perspective
= FALSE
;
355 ctx
->input_centroid
= FALSE
;
356 ctx
->num_interp_gpr
= 1;
358 /* any centroid inputs */
359 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
360 /* skip position/face */
361 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
362 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
)
364 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_LINEAR
)
365 ctx
->input_linear
= TRUE
;
366 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_PERSPECTIVE
)
367 ctx
->input_perspective
= TRUE
;
368 if (ctx
->info
.input_centroid
[i
])
369 ctx
->input_centroid
= TRUE
;
373 /* ignoring sample for now */
374 if (ctx
->input_perspective
)
376 if (ctx
->input_linear
)
378 if (ctx
->input_centroid
)
381 ctx
->num_interp_gpr
+= (num_baryc
+ 1) >> 1;
383 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
384 return ctx
->num_interp_gpr
;
387 static void tgsi_src(struct r600_shader_ctx
*ctx
,
388 const struct tgsi_full_src_register
*tgsi_src
,
389 struct r600_shader_src
*r600_src
)
391 memset(r600_src
, 0, sizeof(*r600_src
));
392 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
393 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
394 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
395 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
396 r600_src
->neg
= tgsi_src
->Register
.Negate
;
397 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
399 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
401 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
402 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
403 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
405 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
406 r600_bc_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
);
407 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
410 index
= tgsi_src
->Register
.Index
;
411 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
412 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
413 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
414 /* assume we wan't TGSI_SEMANTIC_INSTANCEID here */
415 r600_src
->swizzle
[0] = 3;
416 r600_src
->swizzle
[1] = 3;
417 r600_src
->swizzle
[2] = 3;
418 r600_src
->swizzle
[3] = 3;
421 if (tgsi_src
->Register
.Indirect
)
422 r600_src
->rel
= V_SQ_REL_RELATIVE
;
423 r600_src
->sel
= tgsi_src
->Register
.Index
;
424 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
428 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
, unsigned int offset
, unsigned int dst_reg
)
430 struct r600_bc_vtx vtx
;
435 struct r600_bc_alu alu
;
437 memset(&alu
, 0, sizeof(alu
));
439 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT
);
440 alu
.src
[0].sel
= ctx
->ar_reg
;
442 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
443 alu
.src
[1].value
= offset
;
445 alu
.dst
.sel
= dst_reg
;
449 if ((r
= r600_bc_add_alu(ctx
->bc
, &alu
)))
454 ar_reg
= ctx
->ar_reg
;
457 memset(&vtx
, 0, sizeof(vtx
));
458 vtx
.fetch_type
= 2; /* VTX_FETCH_NO_INDEX_OFFSET */
459 vtx
.src_gpr
= ar_reg
;
460 vtx
.mega_fetch_count
= 16;
461 vtx
.dst_gpr
= dst_reg
;
462 vtx
.dst_sel_x
= 0; /* SEL_X */
463 vtx
.dst_sel_y
= 1; /* SEL_Y */
464 vtx
.dst_sel_z
= 2; /* SEL_Z */
465 vtx
.dst_sel_w
= 3; /* SEL_W */
466 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
467 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
468 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
469 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
471 if ((r
= r600_bc_add_vtx(ctx
->bc
, &vtx
)))
477 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
479 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
480 struct r600_bc_alu alu
;
481 int i
, j
, k
, nconst
, r
;
483 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
484 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
487 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
489 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
490 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
494 if (ctx
->src
[i
].rel
) {
495 int treg
= r600_get_temp(ctx
);
496 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].sel
- 512, treg
)))
499 ctx
->src
[i
].sel
= treg
;
503 int treg
= r600_get_temp(ctx
);
504 for (k
= 0; k
< 4; k
++) {
505 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
506 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
507 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
509 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
515 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
519 ctx
->src
[i
].sel
= treg
;
527 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
528 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
530 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
531 struct r600_bc_alu alu
;
532 int i
, j
, k
, nliteral
, r
;
534 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
535 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
539 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
540 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
541 int treg
= r600_get_temp(ctx
);
542 for (k
= 0; k
< 4; k
++) {
543 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
544 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
545 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
547 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
553 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
557 ctx
->src
[i
].sel
= treg
;
564 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
566 struct tgsi_full_immediate
*immediate
;
567 struct tgsi_full_property
*property
;
568 struct r600_shader_ctx ctx
;
569 struct r600_bc_output output
[32];
570 unsigned output_done
, noutput
;
574 ctx
.bc
= &shader
->bc
;
576 r
= r600_bc_init(ctx
.bc
, shader
->family
);
580 tgsi_scan_shader(tokens
, &ctx
.info
);
581 tgsi_parse_init(&ctx
.parse
, tokens
);
582 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
583 shader
->processor_type
= ctx
.type
;
584 ctx
.bc
->type
= shader
->processor_type
;
586 /* register allocations */
587 /* Values [0,127] correspond to GPR[0..127].
588 * Values [128,159] correspond to constant buffer bank 0
589 * Values [160,191] correspond to constant buffer bank 1
590 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
591 * Values [256,287] correspond to constant buffer bank 2 (EG)
592 * Values [288,319] correspond to constant buffer bank 3 (EG)
593 * Other special values are shown in the list below.
594 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
595 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
596 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
597 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
598 * 248 SQ_ALU_SRC_0: special constant 0.0.
599 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
600 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
601 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
602 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
603 * 253 SQ_ALU_SRC_LITERAL: literal constant.
604 * 254 SQ_ALU_SRC_PV: previous vector result.
605 * 255 SQ_ALU_SRC_PS: previous scalar result.
607 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
608 ctx
.file_offset
[i
] = 0;
610 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
611 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
612 if (ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
) {
613 r600_bc_add_cfinst(ctx
.bc
, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
615 r600_bc_add_cfinst(ctx
.bc
, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
618 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
) {
619 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
621 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
622 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
623 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
624 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
626 /* Outside the GPR range. This will be translated to one of the
627 * kcache banks later. */
628 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
630 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
631 ctx
.ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
632 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
633 ctx
.temp_reg
= ctx
.ar_reg
+ 1;
637 shader
->fs_write_all
= FALSE
;
638 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
639 tgsi_parse_token(&ctx
.parse
);
640 switch (ctx
.parse
.FullToken
.Token
.Type
) {
641 case TGSI_TOKEN_TYPE_IMMEDIATE
:
642 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
643 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
644 if(ctx
.literals
== NULL
) {
648 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
649 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
650 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
651 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
654 case TGSI_TOKEN_TYPE_DECLARATION
:
655 r
= tgsi_declaration(&ctx
);
659 case TGSI_TOKEN_TYPE_INSTRUCTION
:
660 r
= tgsi_is_supported(&ctx
);
663 ctx
.max_driver_temp_used
= 0;
664 /* reserve first tmp for everyone */
667 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
668 if ((r
= tgsi_split_constant(&ctx
)))
670 if ((r
= tgsi_split_literal_constant(&ctx
)))
672 if (ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
)
673 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
675 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
676 r
= ctx
.inst_info
->process(&ctx
);
680 case TGSI_TOKEN_TYPE_PROPERTY
:
681 property
= &ctx
.parse
.FullToken
.FullProperty
;
682 if (property
->Property
.PropertyName
== TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
) {
683 if (property
->u
[0].Data
== 1)
684 shader
->fs_write_all
= TRUE
;
688 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
694 noutput
= shader
->noutput
;
695 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
696 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
697 output
[i
].gpr
= shader
->output
[i
].gpr
;
698 output
[i
].elem_size
= 3;
699 output
[i
].swizzle_x
= 0;
700 output
[i
].swizzle_y
= 1;
701 output
[i
].swizzle_z
= 2;
702 output
[i
].swizzle_w
= 3;
703 output
[i
].burst_count
= 1;
704 output
[i
].barrier
= 1;
705 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
706 output
[i
].array_base
= i
- pos0
;
707 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
709 case TGSI_PROCESSOR_VERTEX
:
710 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
711 output
[i
].array_base
= 60;
712 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
713 /* position doesn't count in array_base */
716 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
717 output
[i
].array_base
= 61;
718 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
719 /* position doesn't count in array_base */
723 case TGSI_PROCESSOR_FRAGMENT
:
724 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
725 output
[i
].array_base
= shader
->output
[i
].sid
;
726 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
727 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
728 output
[i
].array_base
= 61;
729 output
[i
].swizzle_x
= 2;
730 output
[i
].swizzle_y
= 7;
731 output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
732 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
733 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
734 output
[i
].array_base
= 61;
735 output
[i
].swizzle_x
= 7;
736 output
[i
].swizzle_y
= 1;
737 output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
738 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
740 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
746 R600_ERR("unsupported processor type %d\n", ctx
.type
);
751 /* add fake param output for vertex shader if no param is exported */
752 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
753 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
754 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
760 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
762 output
[i
].elem_size
= 3;
763 output
[i
].swizzle_x
= 0;
764 output
[i
].swizzle_y
= 1;
765 output
[i
].swizzle_z
= 2;
766 output
[i
].swizzle_w
= 3;
767 output
[i
].burst_count
= 1;
768 output
[i
].barrier
= 1;
769 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
770 output
[i
].array_base
= 0;
771 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
775 /* add fake pixel export */
776 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
777 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
779 output
[0].elem_size
= 3;
780 output
[0].swizzle_x
= 7;
781 output
[0].swizzle_y
= 7;
782 output
[0].swizzle_z
= 7;
783 output
[0].swizzle_w
= 7;
784 output
[0].burst_count
= 1;
785 output
[0].barrier
= 1;
786 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
787 output
[0].array_base
= 0;
788 output
[0].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
);
791 /* set export done on last export of each type */
792 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
793 if (i
== (noutput
- 1)) {
794 output
[i
].end_of_program
= 1;
796 if (!(output_done
& (1 << output
[i
].type
))) {
797 output_done
|= (1 << output
[i
].type
);
798 output
[i
].inst
= BC_INST(ctx
.bc
, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
);
801 /* add output to bytecode */
802 for (i
= 0; i
< noutput
; i
++) {
803 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
808 tgsi_parse_free(&ctx
.parse
);
812 tgsi_parse_free(&ctx
.parse
);
816 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
818 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
822 static int tgsi_end(struct r600_shader_ctx
*ctx
)
827 static void r600_bc_src(struct r600_bc_alu_src
*bc_src
,
828 const struct r600_shader_src
*shader_src
,
831 bc_src
->sel
= shader_src
->sel
;
832 bc_src
->chan
= shader_src
->swizzle
[chan
];
833 bc_src
->neg
= shader_src
->neg
;
834 bc_src
->abs
= shader_src
->abs
;
835 bc_src
->rel
= shader_src
->rel
;
836 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
839 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
840 const struct tgsi_full_dst_register
*tgsi_dst
,
842 struct r600_bc_alu_dst
*r600_dst
)
844 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
846 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
847 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
848 r600_dst
->chan
= swizzle
;
850 if (tgsi_dst
->Register
.Indirect
)
851 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
852 if (inst
->Instruction
.Saturate
) {
857 static int tgsi_last_instruction(unsigned writemask
)
861 for (i
= 0; i
< 4; i
++) {
862 if (writemask
& (1 << i
)) {
869 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
)
871 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
872 struct r600_bc_alu alu
;
874 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
876 for (i
= 0; i
< lasti
+ 1; i
++) {
877 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
880 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
881 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
883 alu
.inst
= ctx
->inst_info
->r600_opcode
;
885 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
886 r600_bc_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
889 r600_bc_src(&alu
.src
[0], &ctx
->src
[1], i
);
890 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], i
);
892 /* handle some special cases */
893 switch (ctx
->inst_info
->tgsi_opcode
) {
894 case TGSI_OPCODE_SUB
:
897 case TGSI_OPCODE_ABS
:
906 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
913 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
915 return tgsi_op2_s(ctx
, 0);
918 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
920 return tgsi_op2_s(ctx
, 1);
924 * r600 - trunc to -PI..PI range
925 * r700 - normalize by dividing by 2PI
928 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
930 static float half_inv_pi
= 1.0 /(3.1415926535 * 2);
931 static float double_pi
= 3.1415926535 * 2;
932 static float neg_pi
= -3.1415926535;
935 struct r600_bc_alu alu
;
937 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
938 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
942 alu
.dst
.sel
= ctx
->temp_reg
;
945 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
947 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
949 alu
.src
[1].value
= *(uint32_t *)&half_inv_pi
;
950 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
953 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
957 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
958 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
961 alu
.dst
.sel
= ctx
->temp_reg
;
964 alu
.src
[0].sel
= ctx
->temp_reg
;
967 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
971 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
972 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
976 alu
.dst
.sel
= ctx
->temp_reg
;
979 alu
.src
[0].sel
= ctx
->temp_reg
;
982 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
984 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
987 if (ctx
->bc
->chiprev
== CHIPREV_R600
) {
988 alu
.src
[1].value
= *(uint32_t *)&double_pi
;
989 alu
.src
[2].value
= *(uint32_t *)&neg_pi
;
991 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
992 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
997 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1003 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
1005 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1006 struct r600_bc_alu alu
;
1008 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1010 r
= tgsi_setup_trig(ctx
);
1014 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1015 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1017 alu
.dst
.sel
= ctx
->temp_reg
;
1020 alu
.src
[0].sel
= ctx
->temp_reg
;
1021 alu
.src
[0].chan
= 0;
1023 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1027 /* replicate result */
1028 for (i
= 0; i
< lasti
+ 1; i
++) {
1029 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1032 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1033 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1035 alu
.src
[0].sel
= ctx
->temp_reg
;
1036 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1039 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1046 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
1048 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1049 struct r600_bc_alu alu
;
1052 /* We'll only need the trig stuff if we are going to write to the
1053 * X or Y components of the destination vector.
1055 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
1056 r
= tgsi_setup_trig(ctx
);
1062 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
1063 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1064 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
1065 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1067 alu
.src
[0].sel
= ctx
->temp_reg
;
1068 alu
.src
[0].chan
= 0;
1070 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1076 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
1077 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1078 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
1079 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1081 alu
.src
[0].sel
= ctx
->temp_reg
;
1082 alu
.src
[0].chan
= 0;
1084 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1090 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
1091 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1093 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1095 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1097 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1098 alu
.src
[0].chan
= 0;
1102 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1108 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
1109 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1111 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1113 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1115 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1116 alu
.src
[0].chan
= 0;
1120 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1128 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
1130 struct r600_bc_alu alu
;
1133 for (i
= 0; i
< 4; i
++) {
1134 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1135 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1139 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1141 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILP
) {
1142 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1145 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], i
);
1150 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1155 /* kill must be last in ALU */
1156 ctx
->bc
->force_add_cf
= 1;
1157 ctx
->shader
->uses_kill
= TRUE
;
1161 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
1163 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1164 struct r600_bc_alu alu
;
1168 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1169 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1170 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
1171 alu
.src
[0].chan
= 0;
1172 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1173 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
1174 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1178 /* dst.y = max(src.x, 0.0) */
1179 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1180 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
1181 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
1182 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
1183 alu
.src
[1].chan
= 0;
1184 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1185 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
1186 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1191 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1192 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1193 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1194 alu
.src
[0].chan
= 0;
1195 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1196 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
1198 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1202 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
1207 /* dst.z = log(src.y) */
1208 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1209 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
1210 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 1);
1211 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1213 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1217 chan
= alu
.dst
.chan
;
1220 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1221 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1222 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
);
1223 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 3);
1224 alu
.src
[1].sel
= sel
;
1225 alu
.src
[1].chan
= chan
;
1227 r600_bc_src(&alu
.src
[2], &ctx
->src
[0], 0);
1228 alu
.dst
.sel
= ctx
->temp_reg
;
1233 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1237 /* dst.z = exp(tmp.x) */
1238 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1239 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1240 alu
.src
[0].sel
= ctx
->temp_reg
;
1241 alu
.src
[0].chan
= 0;
1242 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1244 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1251 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
1253 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1254 struct r600_bc_alu alu
;
1257 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1260 * For state trackers other than OpenGL, we'll want to use
1261 * _RECIPSQRT_IEEE instead.
1263 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
);
1265 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1266 r600_bc_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
1269 alu
.dst
.sel
= ctx
->temp_reg
;
1272 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1275 /* replicate result */
1276 return tgsi_helper_tempx_replicate(ctx
);
1279 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
1281 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1282 struct r600_bc_alu alu
;
1285 for (i
= 0; i
< 4; i
++) {
1286 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1287 alu
.src
[0].sel
= ctx
->temp_reg
;
1288 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1290 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1291 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1294 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1301 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
1303 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1304 struct r600_bc_alu alu
;
1307 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1308 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1309 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1310 r600_bc_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
1312 alu
.dst
.sel
= ctx
->temp_reg
;
1315 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1318 /* replicate result */
1319 return tgsi_helper_tempx_replicate(ctx
);
1322 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
1324 struct r600_bc_alu alu
;
1328 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1329 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
1330 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
1331 alu
.dst
.sel
= ctx
->temp_reg
;
1334 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1338 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1339 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1340 r600_bc_src(&alu
.src
[0], &ctx
->src
[1], 0);
1341 alu
.src
[1].sel
= ctx
->temp_reg
;
1342 alu
.dst
.sel
= ctx
->temp_reg
;
1345 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1348 /* POW(a,b) = EXP2(b * LOG2(a))*/
1349 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1350 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1351 alu
.src
[0].sel
= ctx
->temp_reg
;
1352 alu
.dst
.sel
= ctx
->temp_reg
;
1355 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1358 return tgsi_helper_tempx_replicate(ctx
);
1361 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
1363 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1364 struct r600_bc_alu alu
;
1367 /* tmp = (src > 0 ? 1 : src) */
1368 for (i
= 0; i
< 4; i
++) {
1369 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1370 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1373 alu
.dst
.sel
= ctx
->temp_reg
;
1376 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
1377 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1378 r600_bc_src(&alu
.src
[2], &ctx
->src
[0], i
);
1382 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1387 /* dst = (-tmp > 0 ? -1 : tmp) */
1388 for (i
= 0; i
< 4; i
++) {
1389 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1390 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1392 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1394 alu
.src
[0].sel
= ctx
->temp_reg
;
1395 alu
.src
[0].chan
= i
;
1398 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1401 alu
.src
[2].sel
= ctx
->temp_reg
;
1402 alu
.src
[2].chan
= i
;
1406 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1413 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
1415 struct r600_bc_alu alu
;
1418 for (i
= 0; i
< 4; i
++) {
1419 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1420 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
1421 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
1424 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1425 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1426 alu
.src
[0].sel
= ctx
->temp_reg
;
1427 alu
.src
[0].chan
= i
;
1432 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1439 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
1441 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1442 struct r600_bc_alu alu
;
1444 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1446 for (i
= 0; i
< lasti
+ 1; i
++) {
1447 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1450 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1451 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1452 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1453 r600_bc_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
1456 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1463 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1470 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
1472 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1473 struct r600_bc_alu alu
;
1476 for (i
= 0; i
< 4; i
++) {
1477 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1478 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1479 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1480 r600_bc_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
1483 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1485 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1486 /* handle some special cases */
1487 switch (ctx
->inst_info
->tgsi_opcode
) {
1488 case TGSI_OPCODE_DP2
:
1490 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1491 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1494 case TGSI_OPCODE_DP3
:
1496 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1497 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1500 case TGSI_OPCODE_DPH
:
1502 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1503 alu
.src
[0].chan
= 0;
1513 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1520 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1522 static float one_point_five
= 1.5f
;
1523 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1524 struct r600_bc_tex tex
;
1525 struct r600_bc_alu alu
;
1529 /* Texture fetch instructions can only use gprs as source.
1530 * Also they cannot negate the source or take the absolute value */
1531 const boolean src_requires_loading
=
1532 (inst
->Src
[0].Register
.File
!= TGSI_FILE_TEMPORARY
&&
1533 inst
->Src
[0].Register
.File
!= TGSI_FILE_INPUT
) ||
1534 ctx
->src
[0].neg
|| ctx
->src
[0].abs
;
1535 boolean src_loaded
= FALSE
;
1537 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1539 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1540 /* Add perspective divide */
1541 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1542 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1543 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 3);
1545 alu
.dst
.sel
= ctx
->temp_reg
;
1549 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1553 for (i
= 0; i
< 3; i
++) {
1554 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1555 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1556 alu
.src
[0].sel
= ctx
->temp_reg
;
1557 alu
.src
[0].chan
= 3;
1558 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], i
);
1559 alu
.dst
.sel
= ctx
->temp_reg
;
1562 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1566 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1567 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1568 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1569 alu
.src
[0].chan
= 0;
1570 alu
.dst
.sel
= ctx
->temp_reg
;
1574 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1578 src_gpr
= ctx
->temp_reg
;
1581 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1582 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
1583 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
1585 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1586 for (i
= 0; i
< 4; i
++) {
1587 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1588 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
);
1589 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
1590 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
1591 alu
.dst
.sel
= ctx
->temp_reg
;
1596 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1601 /* tmp1.z = RCP_e(|tmp1.z|) */
1602 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1603 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1604 alu
.src
[0].sel
= ctx
->temp_reg
;
1605 alu
.src
[0].chan
= 2;
1607 alu
.dst
.sel
= ctx
->temp_reg
;
1611 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1615 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1616 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1617 * muladd has no writemask, have to use another temp
1619 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1620 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1623 alu
.src
[0].sel
= ctx
->temp_reg
;
1624 alu
.src
[0].chan
= 0;
1625 alu
.src
[1].sel
= ctx
->temp_reg
;
1626 alu
.src
[1].chan
= 2;
1628 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1629 alu
.src
[2].chan
= 0;
1630 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
1632 alu
.dst
.sel
= ctx
->temp_reg
;
1636 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1640 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1641 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1644 alu
.src
[0].sel
= ctx
->temp_reg
;
1645 alu
.src
[0].chan
= 1;
1646 alu
.src
[1].sel
= ctx
->temp_reg
;
1647 alu
.src
[1].chan
= 2;
1649 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1650 alu
.src
[2].chan
= 0;
1651 alu
.src
[2].value
= *(uint32_t *)&one_point_five
;
1653 alu
.dst
.sel
= ctx
->temp_reg
;
1658 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1663 src_gpr
= ctx
->temp_reg
;
1666 if (src_requires_loading
&& !src_loaded
) {
1667 for (i
= 0; i
< 4; i
++) {
1668 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1669 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1670 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
1671 alu
.dst
.sel
= ctx
->temp_reg
;
1676 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1681 src_gpr
= ctx
->temp_reg
;
1684 opcode
= ctx
->inst_info
->r600_opcode
;
1685 if (opcode
== SQ_TEX_INST_SAMPLE
&&
1686 (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
))
1687 opcode
= SQ_TEX_INST_SAMPLE_C
;
1689 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1691 tex
.sampler_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1692 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
1693 tex
.src_gpr
= src_gpr
;
1694 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1695 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
1696 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
1697 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
1698 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
1705 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
1706 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
1707 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
1708 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
1709 tex
.src_rel
= ctx
->src
[0].rel
;
1712 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1719 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1720 tex
.coord_type_x
= 1;
1721 tex
.coord_type_y
= 1;
1722 tex
.coord_type_z
= 1;
1723 tex
.coord_type_w
= 1;
1726 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
) {
1727 tex
.coord_type_z
= 0;
1728 tex
.src_sel_z
= tex
.src_sel_y
;
1729 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
)
1730 tex
.coord_type_z
= 0;
1732 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
)
1733 tex
.src_sel_w
= tex
.src_sel_z
;
1735 r
= r600_bc_add_tex(ctx
->bc
, &tex
);
1739 /* add shadow ambient support - gallium doesn't do it yet */
1743 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1745 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1746 struct r600_bc_alu alu
;
1747 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1751 /* optimize if it's just an equal balance */
1752 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
1753 for (i
= 0; i
< lasti
+ 1; i
++) {
1754 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1757 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1758 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
1759 r600_bc_src(&alu
.src
[0], &ctx
->src
[1], i
);
1760 r600_bc_src(&alu
.src
[1], &ctx
->src
[2], i
);
1762 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1767 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1775 for (i
= 0; i
< lasti
+ 1; i
++) {
1776 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1779 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1780 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
1781 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1782 alu
.src
[0].chan
= 0;
1783 r600_bc_src(&alu
.src
[1], &ctx
->src
[0], i
);
1785 alu
.dst
.sel
= ctx
->temp_reg
;
1791 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1796 /* (1 - src0) * src2 */
1797 for (i
= 0; i
< lasti
+ 1; i
++) {
1798 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1801 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1802 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1803 alu
.src
[0].sel
= ctx
->temp_reg
;
1804 alu
.src
[0].chan
= i
;
1805 r600_bc_src(&alu
.src
[1], &ctx
->src
[2], i
);
1806 alu
.dst
.sel
= ctx
->temp_reg
;
1812 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1817 /* src0 * src1 + (1 - src0) * src2 */
1818 for (i
= 0; i
< lasti
+ 1; i
++) {
1819 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1822 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1823 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1825 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
1826 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], i
);
1827 alu
.src
[2].sel
= ctx
->temp_reg
;
1828 alu
.src
[2].chan
= i
;
1830 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1835 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1842 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
1844 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1845 struct r600_bc_alu alu
;
1847 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1849 for (i
= 0; i
< lasti
+ 1; i
++) {
1850 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1853 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1854 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
);
1855 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
1856 r600_bc_src(&alu
.src
[1], &ctx
->src
[2], i
);
1857 r600_bc_src(&alu
.src
[2], &ctx
->src
[1], i
);
1858 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1864 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1871 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
1873 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1874 static const unsigned int src0_swizzle
[] = {2, 0, 1};
1875 static const unsigned int src1_swizzle
[] = {1, 2, 0};
1876 struct r600_bc_alu alu
;
1877 uint32_t use_temp
= 0;
1880 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
1883 for (i
= 0; i
< 4; i
++) {
1884 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1885 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1887 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
1888 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], src1_swizzle
[i
]);
1890 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1891 alu
.src
[0].chan
= i
;
1892 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1893 alu
.src
[1].chan
= i
;
1896 alu
.dst
.sel
= ctx
->temp_reg
;
1902 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1907 for (i
= 0; i
< 4; i
++) {
1908 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1909 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1912 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], src1_swizzle
[i
]);
1913 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], src0_swizzle
[i
]);
1915 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1916 alu
.src
[0].chan
= i
;
1917 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1918 alu
.src
[1].chan
= i
;
1921 alu
.src
[2].sel
= ctx
->temp_reg
;
1923 alu
.src
[2].chan
= i
;
1926 alu
.dst
.sel
= ctx
->temp_reg
;
1928 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1934 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1939 return tgsi_helper_copy(ctx
, inst
);
1943 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
1945 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1946 struct r600_bc_alu alu
;
1949 /* result.x = 2^floor(src); */
1950 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
1951 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1953 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
1954 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
1956 alu
.dst
.sel
= ctx
->temp_reg
;
1960 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1964 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1965 alu
.src
[0].sel
= ctx
->temp_reg
;
1966 alu
.src
[0].chan
= 0;
1968 alu
.dst
.sel
= ctx
->temp_reg
;
1972 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1977 /* result.y = tmp - floor(tmp); */
1978 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
1979 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1981 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
1982 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
1984 alu
.dst
.sel
= ctx
->temp_reg
;
1985 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1993 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1998 /* result.z = RoughApprox2ToX(tmp);*/
1999 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
2000 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2001 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2002 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2004 alu
.dst
.sel
= ctx
->temp_reg
;
2010 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2015 /* result.w = 1.0;*/
2016 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
2017 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2019 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2020 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2021 alu
.src
[0].chan
= 0;
2023 alu
.dst
.sel
= ctx
->temp_reg
;
2027 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2031 return tgsi_helper_copy(ctx
, inst
);
2034 static int tgsi_log(struct r600_shader_ctx
*ctx
)
2036 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2037 struct r600_bc_alu alu
;
2040 /* result.x = floor(log2(src)); */
2041 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
2042 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2044 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2045 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2047 alu
.dst
.sel
= ctx
->temp_reg
;
2051 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2055 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2056 alu
.src
[0].sel
= ctx
->temp_reg
;
2057 alu
.src
[0].chan
= 0;
2059 alu
.dst
.sel
= ctx
->temp_reg
;
2064 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2069 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2070 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
2071 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2073 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2074 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2076 alu
.dst
.sel
= ctx
->temp_reg
;
2081 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2085 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2087 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2088 alu
.src
[0].sel
= ctx
->temp_reg
;
2089 alu
.src
[0].chan
= 1;
2091 alu
.dst
.sel
= ctx
->temp_reg
;
2096 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2100 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2102 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2103 alu
.src
[0].sel
= ctx
->temp_reg
;
2104 alu
.src
[0].chan
= 1;
2106 alu
.dst
.sel
= ctx
->temp_reg
;
2111 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2115 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2117 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
2118 alu
.src
[0].sel
= ctx
->temp_reg
;
2119 alu
.src
[0].chan
= 1;
2121 alu
.dst
.sel
= ctx
->temp_reg
;
2126 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2130 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2132 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2134 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2136 alu
.src
[1].sel
= ctx
->temp_reg
;
2137 alu
.src
[1].chan
= 1;
2139 alu
.dst
.sel
= ctx
->temp_reg
;
2144 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2149 /* result.z = log2(src);*/
2150 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
2151 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2153 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2154 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2156 alu
.dst
.sel
= ctx
->temp_reg
;
2161 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2166 /* result.w = 1.0; */
2167 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
2168 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2170 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2171 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2172 alu
.src
[0].chan
= 0;
2174 alu
.dst
.sel
= ctx
->temp_reg
;
2179 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2184 return tgsi_helper_copy(ctx
, inst
);
2187 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
2189 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2190 struct r600_bc_alu alu
;
2193 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2195 switch (inst
->Instruction
.Opcode
) {
2196 case TGSI_OPCODE_ARL
:
2197 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
;
2199 case TGSI_OPCODE_ARR
:
2200 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
2207 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2209 alu
.dst
.sel
= ctx
->ar_reg
;
2211 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2215 /* TODO: Note that the MOVA can be avoided if we never use AR for
2216 * indexing non-CB registers in the current ALU clause. Similarly, we
2217 * need to load AR from ar_reg again if we started a new clause
2218 * between ARL and AR usage. The easy way to do that is to remove
2219 * the MOVA here, and load it for the first AR access after ar_reg
2220 * has been modified in each clause. */
2221 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2222 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
;
2223 alu
.src
[0].sel
= ctx
->ar_reg
;
2224 alu
.src
[0].chan
= 0;
2226 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2231 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
2233 /* TODO from r600c, ar values don't persist between clauses */
2234 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2235 struct r600_bc_alu alu
;
2238 switch (inst
->Instruction
.Opcode
) {
2239 case TGSI_OPCODE_ARL
:
2240 memset(&alu
, 0, sizeof(alu
));
2241 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
;
2242 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2243 alu
.dst
.sel
= ctx
->ar_reg
;
2247 if ((r
= r600_bc_add_alu(ctx
->bc
, &alu
)))
2250 memset(&alu
, 0, sizeof(alu
));
2251 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
2252 alu
.src
[0].sel
= ctx
->ar_reg
;
2253 alu
.dst
.sel
= ctx
->ar_reg
;
2257 if ((r
= r600_bc_add_alu(ctx
->bc
, &alu
)))
2260 case TGSI_OPCODE_ARR
:
2261 memset(&alu
, 0, sizeof(alu
));
2262 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
2263 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2264 alu
.dst
.sel
= ctx
->ar_reg
;
2268 if ((r
= r600_bc_add_alu(ctx
->bc
, &alu
)))
2276 memset(&alu
, 0, sizeof(alu
));
2277 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
;
2278 alu
.src
[0].sel
= ctx
->ar_reg
;
2281 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2284 ctx
->bc
->cf_last
->r6xx_uses_waterfall
= 1;
2288 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
2290 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2291 struct r600_bc_alu alu
;
2294 for (i
= 0; i
< 4; i
++) {
2295 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2297 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2298 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2300 if (i
== 0 || i
== 3) {
2301 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2303 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], i
);
2306 if (i
== 0 || i
== 2) {
2307 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
2309 r600_bc_src(&alu
.src
[1], &ctx
->src
[1], i
);
2313 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2320 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
2322 struct r600_bc_alu alu
;
2325 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2329 alu
.dst
.sel
= ctx
->temp_reg
;
2333 r600_bc_src(&alu
.src
[0], &ctx
->src
[0], 0);
2334 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2335 alu
.src
[1].chan
= 0;
2339 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
2345 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
2348 if (ctx
->bc
->cf_last
) {
2349 if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
) << 3)
2351 else if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
) << 3)
2356 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
) << 3;
2357 ctx
->bc
->force_add_cf
= 1;
2358 } else if (alu_pop
== 2) {
2359 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
) << 3;
2360 ctx
->bc
->force_add_cf
= 1;
2362 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP
));
2363 ctx
->bc
->cf_last
->pop_count
= pops
;
2364 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2369 static inline void callstack_decrease_current(struct r600_shader_ctx
*ctx
, unsigned reason
)
2373 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2377 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
-= 4;
2380 /* TOODO : for 16 vp asic should -= 2; */
2381 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2386 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
)
2388 if (check_max_only
) {
2401 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
) >
2402 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2403 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2404 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
;
2410 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2414 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+= 4;
2417 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2421 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
) >
2422 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2423 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2424 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
;
2428 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
2430 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
2432 sp
->mid
= (struct r600_bc_cf
**)realloc((void *)sp
->mid
,
2433 sizeof(struct r600_bc_cf
*) * (sp
->num_mid
+ 1));
2434 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
2438 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
2441 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
2442 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
2445 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
2447 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
2459 static int emit_return(struct r600_shader_ctx
*ctx
)
2461 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_RETURN
);
2465 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
2468 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_JUMP
);
2469 ctx
->bc
->cf_last
->pop_count
= pops
;
2470 /* TODO work out offset */
2474 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
2479 static void emit_testflag(struct r600_shader_ctx
*ctx
)
2484 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
2487 emit_jump_to_offset(ctx
, 1, 4);
2488 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
2489 pops(ctx
, ifidx
+ 1);
2493 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
2497 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2498 ctx
->bc
->cf_last
->pop_count
= 1;
2500 fc_set_mid(ctx
, fc_sp
);
2506 static int tgsi_if(struct r600_shader_ctx
*ctx
)
2508 emit_logic_pred(ctx
, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
));
2510 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
2512 fc_pushlevel(ctx
, FC_IF
);
2514 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
2518 static int tgsi_else(struct r600_shader_ctx
*ctx
)
2520 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE
));
2521 ctx
->bc
->cf_last
->pop_count
= 1;
2523 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
2524 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
2528 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
2531 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
2532 R600_ERR("if/endif unbalanced in shader\n");
2536 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
2537 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2538 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
2540 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2544 callstack_decrease_current(ctx
, FC_PUSH_VPM
);
2548 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
2550 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
));
2552 fc_pushlevel(ctx
, FC_LOOP
);
2554 /* check stack depth */
2555 callstack_check_depth(ctx
, FC_LOOP
, 0);
2559 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
2563 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
));
2565 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
2566 R600_ERR("loop/endloop in shader code are not paired.\n");
2570 /* fixup loop pointers - from r600isa
2571 LOOP END points to CF after LOOP START,
2572 LOOP START point to CF after LOOP END
2573 BRK/CONT point to LOOP END CF
2575 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
2577 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2579 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
2580 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
2582 /* TODO add LOOPRET support */
2584 callstack_decrease_current(ctx
, FC_LOOP
);
2588 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
2592 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
2594 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
2599 R600_ERR("Break not inside loop/endloop pair\n");
2603 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2604 ctx
->bc
->cf_last
->pop_count
= 1;
2606 fc_set_mid(ctx
, fscp
);
2609 callstack_check_depth(ctx
, FC_PUSH_VPM
, 1);
2613 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
2614 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
2615 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2616 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
2619 * For state trackers other than OpenGL, we'll want to use
2620 * _RECIP_IEEE instead.
2622 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
2624 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_rsq
},
2625 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
2626 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
2627 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
2628 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2629 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2630 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2631 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
2632 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
2633 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
2634 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
2635 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
2636 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
2637 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2638 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
2639 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2641 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2642 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2644 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2645 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2646 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
2647 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2648 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
2649 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2650 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
2651 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
2652 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
2653 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
2655 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2656 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2657 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2658 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2659 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
2660 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
2661 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
2662 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
2663 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2664 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2665 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2666 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2667 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2668 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
2669 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2670 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
2671 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
2672 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
2673 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
2674 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2675 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2676 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2677 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2678 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2679 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2680 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2681 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2682 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2683 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2684 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
2685 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2686 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2687 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2688 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
2689 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
2690 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
2691 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2692 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2693 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2694 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2695 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2696 {TGSI_OPCODE_BRK
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
2697 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
2699 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2700 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2701 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
2702 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
2704 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2705 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2706 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2707 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2708 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2709 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2710 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2711 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
2712 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2714 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2715 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2716 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2717 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2718 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2719 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2720 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2721 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2722 {TGSI_OPCODE_CONT
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
2723 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2724 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2725 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
2726 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2727 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
2728 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2730 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2731 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2732 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2733 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2734 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2736 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2737 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2738 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2739 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2740 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2741 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2742 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2743 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2744 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
2745 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
2747 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2748 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2749 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2750 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2751 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2752 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2753 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2754 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2755 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2756 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2757 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2758 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2759 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2760 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2761 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2762 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2763 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2764 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2765 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2766 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2767 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2768 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2769 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2770 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2771 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2772 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2773 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2774 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2777 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
2778 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
2779 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2780 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
2781 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
2782 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
2783 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
2784 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
2785 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
2786 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2787 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2788 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2789 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
2790 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
2791 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
2792 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
2793 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
2794 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
2795 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2796 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
2797 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2799 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2800 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2802 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2803 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2804 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
2805 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2806 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
2807 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2808 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
2809 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
2810 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
2811 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
2813 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2814 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2815 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2816 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2817 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
2818 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
2819 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
2820 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
2821 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2822 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2823 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2824 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2825 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2826 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
2827 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2828 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
2829 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
2830 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
2831 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
2832 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2833 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2834 {TGSI_OPCODE_TXD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2835 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2836 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2837 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2838 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2839 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2840 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2841 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2842 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
2843 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2844 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2845 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2846 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
2847 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
2848 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
2849 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2850 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2851 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2852 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2853 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2854 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
2855 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
2857 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2858 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2859 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
2860 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
2862 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2863 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2864 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2865 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2866 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2867 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2868 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2869 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_op2
},
2870 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2872 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2873 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2874 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2875 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2876 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2877 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2878 {TGSI_OPCODE_TXF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2879 {TGSI_OPCODE_TXQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2880 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
2881 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2882 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2883 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
2884 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2885 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
2886 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2888 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2889 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2890 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2891 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2892 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2894 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2895 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2896 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2897 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2898 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2899 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2900 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2901 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2902 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
2903 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
2905 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2906 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2907 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2908 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2909 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2910 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2911 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2912 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2913 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2914 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2915 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2916 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2917 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2918 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2919 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2920 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2921 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2922 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2923 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2924 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2925 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2926 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2927 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2928 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2929 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2930 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2931 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2932 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},