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gallium/radeon: pass pipe_debug_callback into radeon_llvm_compile (v2)
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
166 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
167 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
168 unsigned export_shader;
169
170 shader->shader.bc.isa = rctx->isa;
171
172 if (dump) {
173 fprintf(stderr, "--------------------------------------------------------------\n");
174 tgsi_dump(sel->tokens, 0);
175
176 if (sel->so.num_outputs) {
177 r600_dump_streamout(&sel->so);
178 }
179 }
180 r = r600_shader_from_tgsi(rctx, shader, key);
181 if (r) {
182 R600_ERR("translation from TGSI failed !\n");
183 goto error;
184 }
185 if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) {
186 /* only disable for vertex shaders in tess paths */
187 if (key.vs.as_ls)
188 use_sb = 0;
189 }
190 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_CTRL);
191 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_EVAL);
192
193 /* disable SB for shaders using doubles */
194 use_sb &= !shader->shader.uses_doubles;
195
196 /* Check if the bytecode has already been built. When using the llvm
197 * backend, r600_shader_from_tgsi() will take care of building the
198 * bytecode.
199 */
200 if (!shader->shader.bc.bytecode) {
201 r = r600_bytecode_build(&shader->shader.bc);
202 if (r) {
203 R600_ERR("building bytecode failed !\n");
204 goto error;
205 }
206 }
207
208 if (dump && !sb_disasm) {
209 fprintf(stderr, "--------------------------------------------------------------\n");
210 r600_bytecode_disasm(&shader->shader.bc);
211 fprintf(stderr, "______________________________________________________________\n");
212 } else if ((dump && sb_disasm) || use_sb) {
213 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
214 dump, use_sb);
215 if (r) {
216 R600_ERR("r600_sb_bytecode_process failed !\n");
217 goto error;
218 }
219 }
220
221 if (shader->gs_copy_shader) {
222 if (dump) {
223 // dump copy shader
224 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
225 &shader->gs_copy_shader->shader, dump, 0);
226 if (r)
227 goto error;
228 }
229
230 if ((r = store_shader(ctx, shader->gs_copy_shader)))
231 goto error;
232 }
233
234 /* Store the shader in a buffer. */
235 if ((r = store_shader(ctx, shader)))
236 goto error;
237
238 /* Build state. */
239 switch (shader->shader.processor_type) {
240 case TGSI_PROCESSOR_TESS_CTRL:
241 evergreen_update_hs_state(ctx, shader);
242 break;
243 case TGSI_PROCESSOR_TESS_EVAL:
244 if (key.tes.as_es)
245 evergreen_update_es_state(ctx, shader);
246 else
247 evergreen_update_vs_state(ctx, shader);
248 break;
249 case TGSI_PROCESSOR_GEOMETRY:
250 if (rctx->b.chip_class >= EVERGREEN) {
251 evergreen_update_gs_state(ctx, shader);
252 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
253 } else {
254 r600_update_gs_state(ctx, shader);
255 r600_update_vs_state(ctx, shader->gs_copy_shader);
256 }
257 break;
258 case TGSI_PROCESSOR_VERTEX:
259 export_shader = key.vs.as_es;
260 if (rctx->b.chip_class >= EVERGREEN) {
261 if (key.vs.as_ls)
262 evergreen_update_ls_state(ctx, shader);
263 else if (key.vs.as_es)
264 evergreen_update_es_state(ctx, shader);
265 else
266 evergreen_update_vs_state(ctx, shader);
267 } else {
268 if (export_shader)
269 r600_update_es_state(ctx, shader);
270 else
271 r600_update_vs_state(ctx, shader);
272 }
273 break;
274 case TGSI_PROCESSOR_FRAGMENT:
275 if (rctx->b.chip_class >= EVERGREEN) {
276 evergreen_update_ps_state(ctx, shader);
277 } else {
278 r600_update_ps_state(ctx, shader);
279 }
280 break;
281 default:
282 r = -EINVAL;
283 goto error;
284 }
285 return 0;
286
287 error:
288 r600_pipe_shader_destroy(ctx, shader);
289 return r;
290 }
291
292 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
293 {
294 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
295 r600_bytecode_clear(&shader->shader.bc);
296 r600_release_command_buffer(&shader->command_buffer);
297 }
298
299 /*
300 * tgsi -> r600 shader
301 */
302 struct r600_shader_tgsi_instruction;
303
304 struct r600_shader_src {
305 unsigned sel;
306 unsigned swizzle[4];
307 unsigned neg;
308 unsigned abs;
309 unsigned rel;
310 unsigned kc_bank;
311 boolean kc_rel; /* true if cache bank is indexed */
312 uint32_t value[4];
313 };
314
315 struct eg_interp {
316 boolean enabled;
317 unsigned ij_index;
318 };
319
320 struct r600_shader_ctx {
321 struct tgsi_shader_info info;
322 struct tgsi_parse_context parse;
323 const struct tgsi_token *tokens;
324 unsigned type;
325 unsigned file_offset[TGSI_FILE_COUNT];
326 unsigned temp_reg;
327 const struct r600_shader_tgsi_instruction *inst_info;
328 struct r600_bytecode *bc;
329 struct r600_shader *shader;
330 struct r600_shader_src src[4];
331 uint32_t *literals;
332 uint32_t nliterals;
333 uint32_t max_driver_temp_used;
334 boolean use_llvm;
335 /* needed for evergreen interpolation */
336 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
337 /* evergreen/cayman also store sample mask in face register */
338 int face_gpr;
339 /* sample id is .w component stored in fixed point position register */
340 int fixed_pt_position_gpr;
341 int colors_used;
342 boolean clip_vertex_write;
343 unsigned cv_output;
344 unsigned edgeflag_output;
345 int fragcoord_input;
346 int native_integers;
347 int next_ring_offset;
348 int gs_out_ring_offset;
349 int gs_next_vertex;
350 struct r600_shader *gs_for_vs;
351 int gs_export_gpr_tregs[4];
352 const struct pipe_stream_output_info *gs_stream_output_info;
353 unsigned enabled_stream_buffers_mask;
354 unsigned tess_input_info; /* temp with tess input offsets */
355 unsigned tess_output_info; /* temp with tess input offsets */
356 };
357
358 struct r600_shader_tgsi_instruction {
359 unsigned op;
360 int (*process)(struct r600_shader_ctx *ctx);
361 };
362
363 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
364 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
365 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
366 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
367 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
368 static int tgsi_else(struct r600_shader_ctx *ctx);
369 static int tgsi_endif(struct r600_shader_ctx *ctx);
370 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
371 static int tgsi_endloop(struct r600_shader_ctx *ctx);
372 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
373 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
374 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
375 unsigned int dst_reg);
376 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
377 const struct r600_shader_src *shader_src,
378 unsigned chan);
379 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
380 unsigned dst_reg);
381
382 static int tgsi_last_instruction(unsigned writemask)
383 {
384 int i, lasti = 0;
385
386 for (i = 0; i < 4; i++) {
387 if (writemask & (1 << i)) {
388 lasti = i;
389 }
390 }
391 return lasti;
392 }
393
394 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
395 {
396 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
397 int j;
398
399 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
400 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
401 return -EINVAL;
402 }
403 if (i->Instruction.Predicate) {
404 R600_ERR("predicate unsupported\n");
405 return -EINVAL;
406 }
407 #if 0
408 if (i->Instruction.Label) {
409 R600_ERR("label unsupported\n");
410 return -EINVAL;
411 }
412 #endif
413 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
414 if (i->Src[j].Register.Dimension) {
415 switch (i->Src[j].Register.File) {
416 case TGSI_FILE_CONSTANT:
417 break;
418 case TGSI_FILE_INPUT:
419 if (ctx->type == TGSI_PROCESSOR_GEOMETRY ||
420 ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
421 ctx->type == TGSI_PROCESSOR_TESS_EVAL)
422 break;
423 case TGSI_FILE_OUTPUT:
424 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
425 break;
426 default:
427 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
428 i->Src[j].Register.File,
429 i->Src[j].Register.Dimension);
430 return -EINVAL;
431 }
432 }
433 }
434 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
435 if (i->Dst[j].Register.Dimension) {
436 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
437 continue;
438 R600_ERR("unsupported dst (dimension)\n");
439 return -EINVAL;
440 }
441 }
442 return 0;
443 }
444
445 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
446 {
447 if (interpolate == TGSI_INTERPOLATE_COLOR ||
448 interpolate == TGSI_INTERPOLATE_LINEAR ||
449 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
450 {
451 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
452 int loc;
453
454 switch(location) {
455 case TGSI_INTERPOLATE_LOC_CENTER:
456 loc = 1;
457 break;
458 case TGSI_INTERPOLATE_LOC_CENTROID:
459 loc = 2;
460 break;
461 case TGSI_INTERPOLATE_LOC_SAMPLE:
462 default:
463 loc = 0; break;
464 }
465
466 return is_linear * 3 + loc;
467 }
468
469 return -1;
470 }
471
472 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
473 int input)
474 {
475 int i = eg_get_interpolator_index(
476 ctx->shader->input[input].interpolate,
477 ctx->shader->input[input].interpolate_location);
478 assert(i >= 0);
479 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
480 }
481
482 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
483 {
484 int i, r;
485 struct r600_bytecode_alu alu;
486 int gpr = 0, base_chan = 0;
487 int ij_index = ctx->shader->input[input].ij_index;
488
489 /* work out gpr and base_chan from index */
490 gpr = ij_index / 2;
491 base_chan = (2 * (ij_index % 2)) + 1;
492
493 for (i = 0; i < 8; i++) {
494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
495
496 if (i < 4)
497 alu.op = ALU_OP2_INTERP_ZW;
498 else
499 alu.op = ALU_OP2_INTERP_XY;
500
501 if ((i > 1) && (i < 6)) {
502 alu.dst.sel = ctx->shader->input[input].gpr;
503 alu.dst.write = 1;
504 }
505
506 alu.dst.chan = i % 4;
507
508 alu.src[0].sel = gpr;
509 alu.src[0].chan = (base_chan - (i % 2));
510
511 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
512
513 alu.bank_swizzle_force = SQ_ALU_VEC_210;
514 if ((i % 4) == 3)
515 alu.last = 1;
516 r = r600_bytecode_add_alu(ctx->bc, &alu);
517 if (r)
518 return r;
519 }
520 return 0;
521 }
522
523 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
524 {
525 int i, r;
526 struct r600_bytecode_alu alu;
527
528 for (i = 0; i < 4; i++) {
529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
530
531 alu.op = ALU_OP1_INTERP_LOAD_P0;
532
533 alu.dst.sel = ctx->shader->input[input].gpr;
534 alu.dst.write = 1;
535
536 alu.dst.chan = i;
537
538 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
539 alu.src[0].chan = i;
540
541 if (i == 3)
542 alu.last = 1;
543 r = r600_bytecode_add_alu(ctx->bc, &alu);
544 if (r)
545 return r;
546 }
547 return 0;
548 }
549
550 /*
551 * Special export handling in shaders
552 *
553 * shader export ARRAY_BASE for EXPORT_POS:
554 * 60 is position
555 * 61 is misc vector
556 * 62, 63 are clip distance vectors
557 *
558 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
559 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
560 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
561 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
562 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
563 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
564 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
565 * exclusive from render target index)
566 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
567 *
568 *
569 * shader export ARRAY_BASE for EXPORT_PIXEL:
570 * 0-7 CB targets
571 * 61 computed Z vector
572 *
573 * The use of the values exported in the computed Z vector are controlled
574 * by DB_SHADER_CONTROL:
575 * Z_EXPORT_ENABLE - Z as a float in RED
576 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
577 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
578 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
579 * DB_SOURCE_FORMAT - export control restrictions
580 *
581 */
582
583
584 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
585 static int r600_spi_sid(struct r600_shader_io * io)
586 {
587 int index, name = io->name;
588
589 /* These params are handled differently, they don't need
590 * semantic indices, so we'll use 0 for them.
591 */
592 if (name == TGSI_SEMANTIC_POSITION ||
593 name == TGSI_SEMANTIC_PSIZE ||
594 name == TGSI_SEMANTIC_EDGEFLAG ||
595 name == TGSI_SEMANTIC_FACE ||
596 name == TGSI_SEMANTIC_SAMPLEMASK)
597 index = 0;
598 else {
599 if (name == TGSI_SEMANTIC_GENERIC) {
600 /* For generic params simply use sid from tgsi */
601 index = io->sid;
602 } else {
603 /* For non-generic params - pack name and sid into 8 bits */
604 index = 0x80 | (name<<3) | (io->sid);
605 }
606
607 /* Make sure that all really used indices have nonzero value, so
608 * we can just compare it to 0 later instead of comparing the name
609 * with different values to detect special cases. */
610 index++;
611 }
612
613 return index;
614 };
615
616 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
617 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
618 {
619 switch (semantic_name) {
620 case TGSI_SEMANTIC_POSITION:
621 return 0;
622 case TGSI_SEMANTIC_PSIZE:
623 return 1;
624 case TGSI_SEMANTIC_CLIPDIST:
625 assert(index <= 1);
626 return 2 + index;
627 case TGSI_SEMANTIC_GENERIC:
628 if (index <= 63-4)
629 return 4 + index - 9;
630 else
631 /* same explanation as in the default statement,
632 * the only user hitting this is st/nine.
633 */
634 return 0;
635
636 /* patch indices are completely separate and thus start from 0 */
637 case TGSI_SEMANTIC_TESSOUTER:
638 return 0;
639 case TGSI_SEMANTIC_TESSINNER:
640 return 1;
641 case TGSI_SEMANTIC_PATCH:
642 return 2 + index;
643
644 default:
645 /* Don't fail here. The result of this function is only used
646 * for LS, TCS, TES, and GS, where legacy GL semantics can't
647 * occur, but this function is called for all vertex shaders
648 * before it's known whether LS will be compiled or not.
649 */
650 return 0;
651 }
652 }
653
654 /* turn input into interpolate on EG */
655 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
656 {
657 int r = 0;
658
659 if (ctx->shader->input[index].spi_sid) {
660 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
661 if (ctx->shader->input[index].interpolate > 0) {
662 evergreen_interp_assign_ij_index(ctx, index);
663 if (!ctx->use_llvm)
664 r = evergreen_interp_alu(ctx, index);
665 } else {
666 if (!ctx->use_llvm)
667 r = evergreen_interp_flat(ctx, index);
668 }
669 }
670 return r;
671 }
672
673 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
674 {
675 struct r600_bytecode_alu alu;
676 int i, r;
677 int gpr_front = ctx->shader->input[front].gpr;
678 int gpr_back = ctx->shader->input[back].gpr;
679
680 for (i = 0; i < 4; i++) {
681 memset(&alu, 0, sizeof(alu));
682 alu.op = ALU_OP3_CNDGT;
683 alu.is_op3 = 1;
684 alu.dst.write = 1;
685 alu.dst.sel = gpr_front;
686 alu.src[0].sel = ctx->face_gpr;
687 alu.src[1].sel = gpr_front;
688 alu.src[2].sel = gpr_back;
689
690 alu.dst.chan = i;
691 alu.src[1].chan = i;
692 alu.src[2].chan = i;
693 alu.last = (i==3);
694
695 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
696 return r;
697 }
698
699 return 0;
700 }
701
702 /* execute a single slot ALU calculation */
703 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
704 int dst_sel, int dst_chan,
705 int src0_sel, unsigned src0_chan_val,
706 int src1_sel, unsigned src1_chan_val)
707 {
708 struct r600_bytecode_alu alu;
709 int r, i;
710
711 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
712 for (i = 0; i < 4; i++) {
713 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
714 alu.op = op;
715 alu.src[0].sel = src0_sel;
716 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
717 alu.src[0].value = src0_chan_val;
718 else
719 alu.src[0].chan = src0_chan_val;
720 alu.src[1].sel = src1_sel;
721 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
722 alu.src[1].value = src1_chan_val;
723 else
724 alu.src[1].chan = src1_chan_val;
725 alu.dst.sel = dst_sel;
726 alu.dst.chan = i;
727 alu.dst.write = i == dst_chan;
728 alu.last = (i == 3);
729 r = r600_bytecode_add_alu(ctx->bc, &alu);
730 if (r)
731 return r;
732 }
733 return 0;
734 }
735
736 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
737 alu.op = op;
738 alu.src[0].sel = src0_sel;
739 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
740 alu.src[0].value = src0_chan_val;
741 else
742 alu.src[0].chan = src0_chan_val;
743 alu.src[1].sel = src1_sel;
744 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
745 alu.src[1].value = src1_chan_val;
746 else
747 alu.src[1].chan = src1_chan_val;
748 alu.dst.sel = dst_sel;
749 alu.dst.chan = dst_chan;
750 alu.dst.write = 1;
751 alu.last = 1;
752 r = r600_bytecode_add_alu(ctx->bc, &alu);
753 if (r)
754 return r;
755 return 0;
756 }
757
758 /* execute a single slot ALU calculation */
759 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
760 int dst_sel, int dst_chan,
761 int src0_sel, unsigned src0_chan_val,
762 int src1_sel, unsigned src1_chan_val,
763 int src2_sel, unsigned src2_chan_val)
764 {
765 struct r600_bytecode_alu alu;
766 int r;
767
768 /* validate this for other ops */
769 assert(op == ALU_OP3_MULADD_UINT24);
770 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
771 alu.op = op;
772 alu.src[0].sel = src0_sel;
773 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
774 alu.src[0].value = src0_chan_val;
775 else
776 alu.src[0].chan = src0_chan_val;
777 alu.src[1].sel = src1_sel;
778 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
779 alu.src[1].value = src1_chan_val;
780 else
781 alu.src[1].chan = src1_chan_val;
782 alu.src[2].sel = src2_sel;
783 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
784 alu.src[2].value = src2_chan_val;
785 else
786 alu.src[2].chan = src2_chan_val;
787 alu.dst.sel = dst_sel;
788 alu.dst.chan = dst_chan;
789 alu.is_op3 = 1;
790 alu.last = 1;
791 r = r600_bytecode_add_alu(ctx->bc, &alu);
792 if (r)
793 return r;
794 return 0;
795 }
796
797 /* put it in temp_reg.x */
798 static int get_lds_offset0(struct r600_shader_ctx *ctx,
799 int rel_patch_chan,
800 int temp_reg, bool is_patch_var)
801 {
802 int r;
803
804 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
805 /* ADD
806 Dimension - patch0_offset (input_vals.z),
807 Non-dim - patch0_data_offset (input_vals.w)
808 */
809 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
810 temp_reg, 0,
811 ctx->tess_output_info, 0,
812 0, rel_patch_chan,
813 ctx->tess_output_info, is_patch_var ? 3 : 2);
814 if (r)
815 return r;
816 return 0;
817 }
818
819 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
820 {
821 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
822 }
823
824 static int r600_get_temp(struct r600_shader_ctx *ctx)
825 {
826 return ctx->temp_reg + ctx->max_driver_temp_used++;
827 }
828
829 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
830 {
831 int i;
832 i = ctx->shader->noutput++;
833 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
834 ctx->shader->output[i].sid = 0;
835 ctx->shader->output[i].gpr = 0;
836 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
837 ctx->shader->output[i].write_mask = 0x4;
838 ctx->shader->output[i].spi_sid = prim_id_sid;
839
840 return 0;
841 }
842
843 static int tgsi_barrier(struct r600_shader_ctx *ctx)
844 {
845 struct r600_bytecode_alu alu;
846 int r;
847
848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
849 alu.op = ctx->inst_info->op;
850 alu.last = 1;
851
852 r = r600_bytecode_add_alu(ctx->bc, &alu);
853 if (r)
854 return r;
855 return 0;
856 }
857
858 static int tgsi_declaration(struct r600_shader_ctx *ctx)
859 {
860 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
861 int r, i, j, count = d->Range.Last - d->Range.First + 1;
862
863 switch (d->Declaration.File) {
864 case TGSI_FILE_INPUT:
865 for (j = 0; j < count; j++) {
866 i = ctx->shader->ninput + j;
867 assert(i < Elements(ctx->shader->input));
868 ctx->shader->input[i].name = d->Semantic.Name;
869 ctx->shader->input[i].sid = d->Semantic.Index + j;
870 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
871 ctx->shader->input[i].interpolate_location = d->Interp.Location;
872 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
873 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
874 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
875 switch (ctx->shader->input[i].name) {
876 case TGSI_SEMANTIC_FACE:
877 if (ctx->face_gpr != -1)
878 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
879 else
880 ctx->face_gpr = ctx->shader->input[i].gpr;
881 break;
882 case TGSI_SEMANTIC_COLOR:
883 ctx->colors_used++;
884 break;
885 case TGSI_SEMANTIC_POSITION:
886 ctx->fragcoord_input = i;
887 break;
888 case TGSI_SEMANTIC_PRIMID:
889 /* set this for now */
890 ctx->shader->gs_prim_id_input = true;
891 ctx->shader->ps_prim_id_input = i;
892 break;
893 }
894 if (ctx->bc->chip_class >= EVERGREEN) {
895 if ((r = evergreen_interp_input(ctx, i)))
896 return r;
897 }
898 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
899 /* FIXME probably skip inputs if they aren't passed in the ring */
900 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
901 ctx->next_ring_offset += 16;
902 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
903 ctx->shader->gs_prim_id_input = true;
904 }
905 }
906 ctx->shader->ninput += count;
907 break;
908 case TGSI_FILE_OUTPUT:
909 for (j = 0; j < count; j++) {
910 i = ctx->shader->noutput + j;
911 assert(i < Elements(ctx->shader->output));
912 ctx->shader->output[i].name = d->Semantic.Name;
913 ctx->shader->output[i].sid = d->Semantic.Index + j;
914 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
915 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
916 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
917 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
918 ctx->type == TGSI_PROCESSOR_GEOMETRY ||
919 ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
920 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
921 switch (d->Semantic.Name) {
922 case TGSI_SEMANTIC_CLIPDIST:
923 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
924 ((d->Semantic.Index + j) << 2);
925 break;
926 case TGSI_SEMANTIC_PSIZE:
927 ctx->shader->vs_out_misc_write = 1;
928 ctx->shader->vs_out_point_size = 1;
929 break;
930 case TGSI_SEMANTIC_EDGEFLAG:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_edgeflag = 1;
933 ctx->edgeflag_output = i;
934 break;
935 case TGSI_SEMANTIC_VIEWPORT_INDEX:
936 ctx->shader->vs_out_misc_write = 1;
937 ctx->shader->vs_out_viewport = 1;
938 break;
939 case TGSI_SEMANTIC_LAYER:
940 ctx->shader->vs_out_misc_write = 1;
941 ctx->shader->vs_out_layer = 1;
942 break;
943 case TGSI_SEMANTIC_CLIPVERTEX:
944 ctx->clip_vertex_write = TRUE;
945 ctx->cv_output = i;
946 break;
947 }
948 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
949 ctx->gs_out_ring_offset += 16;
950 }
951 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
952 switch (d->Semantic.Name) {
953 case TGSI_SEMANTIC_COLOR:
954 ctx->shader->nr_ps_max_color_exports++;
955 break;
956 }
957 }
958 }
959 ctx->shader->noutput += count;
960 break;
961 case TGSI_FILE_TEMPORARY:
962 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
963 if (d->Array.ArrayID) {
964 r600_add_gpr_array(ctx->shader,
965 ctx->file_offset[TGSI_FILE_TEMPORARY] +
966 d->Range.First,
967 d->Range.Last - d->Range.First + 1, 0x0F);
968 }
969 }
970 break;
971
972 case TGSI_FILE_CONSTANT:
973 case TGSI_FILE_SAMPLER:
974 case TGSI_FILE_SAMPLER_VIEW:
975 case TGSI_FILE_ADDRESS:
976 break;
977
978 case TGSI_FILE_SYSTEM_VALUE:
979 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
980 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
981 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
982 break; /* Already handled from allocate_system_value_inputs */
983 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
984 if (!ctx->native_integers) {
985 struct r600_bytecode_alu alu;
986 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
987
988 alu.op = ALU_OP1_INT_TO_FLT;
989 alu.src[0].sel = 0;
990 alu.src[0].chan = 3;
991
992 alu.dst.sel = 0;
993 alu.dst.chan = 3;
994 alu.dst.write = 1;
995 alu.last = 1;
996
997 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
998 return r;
999 }
1000 break;
1001 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1002 break;
1003 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1004 break;
1005 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1006 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1007 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1008 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1009 unsigned temp_reg = r600_get_temp(ctx);
1010
1011 r = get_lds_offset0(ctx, 2, temp_reg, true);
1012 if (r)
1013 return r;
1014
1015 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1016 temp_reg, 0,
1017 temp_reg, 0,
1018 V_SQ_ALU_SRC_LITERAL, param * 16);
1019 if (r)
1020 return r;
1021
1022 do_lds_fetch_values(ctx, temp_reg, dreg);
1023 }
1024 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1025 /* MOV r1.x, r0.x;
1026 MOV r1.y, r0.y;
1027 */
1028 for (i = 0; i < 2; i++) {
1029 struct r600_bytecode_alu alu;
1030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1031 alu.op = ALU_OP1_MOV;
1032 alu.src[0].sel = 0;
1033 alu.src[0].chan = 0 + i;
1034 alu.dst.sel = 1;
1035 alu.dst.chan = 0 + i;
1036 alu.dst.write = 1;
1037 alu.last = (i == 1) ? 1 : 0;
1038 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1039 return r;
1040 }
1041 /* ADD r1.z, 1.0f, -r0.x */
1042 struct r600_bytecode_alu alu;
1043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1044 alu.op = ALU_OP2_ADD;
1045 alu.src[0].sel = V_SQ_ALU_SRC_1;
1046 alu.src[1].sel = 1;
1047 alu.src[1].chan = 0;
1048 alu.src[1].neg = 1;
1049 alu.dst.sel = 1;
1050 alu.dst.chan = 2;
1051 alu.dst.write = 1;
1052 alu.last = 1;
1053 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1054 return r;
1055
1056 /* ADD r1.z, r1.z, -r1.y */
1057 alu.op = ALU_OP2_ADD;
1058 alu.src[0].sel = 1;
1059 alu.src[0].chan = 2;
1060 alu.src[1].sel = 1;
1061 alu.src[1].chan = 1;
1062 alu.src[1].neg = 1;
1063 alu.dst.sel = 1;
1064 alu.dst.chan = 2;
1065 alu.dst.write = 1;
1066 alu.last = 1;
1067 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1068 return r;
1069 break;
1070 }
1071 break;
1072 default:
1073 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1074 return -EINVAL;
1075 }
1076 return 0;
1077 }
1078
1079 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1080 {
1081 struct tgsi_parse_context parse;
1082 struct {
1083 boolean enabled;
1084 int *reg;
1085 unsigned name, alternate_name;
1086 } inputs[2] = {
1087 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1088
1089 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1090 };
1091 int i, k, num_regs = 0;
1092
1093 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1094 return 0;
1095 }
1096
1097 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1098 while (!tgsi_parse_end_of_tokens(&parse)) {
1099 tgsi_parse_token(&parse);
1100
1101 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1102 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1103 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1104 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1105 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1106 {
1107 int interpolate, location, k;
1108
1109 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1110 location = TGSI_INTERPOLATE_LOC_CENTER;
1111 inputs[1].enabled = true; /* needs SAMPLEID */
1112 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1113 location = TGSI_INTERPOLATE_LOC_CENTER;
1114 /* Needs sample positions, currently those are always available */
1115 } else {
1116 location = TGSI_INTERPOLATE_LOC_CENTROID;
1117 }
1118
1119 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1120 k = eg_get_interpolator_index(interpolate, location);
1121 ctx->eg_interpolators[k].enabled = true;
1122 }
1123 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1124 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1125 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1126 for (k = 0; k < Elements(inputs); k++) {
1127 if (d->Semantic.Name == inputs[k].name ||
1128 d->Semantic.Name == inputs[k].alternate_name) {
1129 inputs[k].enabled = true;
1130 }
1131 }
1132 }
1133 }
1134 }
1135
1136 tgsi_parse_free(&parse);
1137
1138 for (i = 0; i < Elements(inputs); i++) {
1139 boolean enabled = inputs[i].enabled;
1140 int *reg = inputs[i].reg;
1141 unsigned name = inputs[i].name;
1142
1143 if (enabled) {
1144 int gpr = gpr_offset + num_regs++;
1145
1146 // add to inputs, allocate a gpr
1147 k = ctx->shader->ninput ++;
1148 ctx->shader->input[k].name = name;
1149 ctx->shader->input[k].sid = 0;
1150 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1151 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1152 *reg = ctx->shader->input[k].gpr = gpr;
1153 }
1154 }
1155
1156 return gpr_offset + num_regs;
1157 }
1158
1159 /*
1160 * for evergreen we need to scan the shader to find the number of GPRs we need to
1161 * reserve for interpolation and system values
1162 *
1163 * we need to know if we are going to emit
1164 * any sample or centroid inputs
1165 * if perspective and linear are required
1166 */
1167 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1168 {
1169 int i;
1170 int num_baryc;
1171 struct tgsi_parse_context parse;
1172
1173 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1174
1175 for (i = 0; i < ctx->info.num_inputs; i++) {
1176 int k;
1177 /* skip position/face/mask/sampleid */
1178 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1179 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1180 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1181 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1182 continue;
1183
1184 k = eg_get_interpolator_index(
1185 ctx->info.input_interpolate[i],
1186 ctx->info.input_interpolate_loc[i]);
1187 if (k >= 0)
1188 ctx->eg_interpolators[k].enabled = TRUE;
1189 }
1190
1191 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1192 return 0;
1193 }
1194
1195 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1196 while (!tgsi_parse_end_of_tokens(&parse)) {
1197 tgsi_parse_token(&parse);
1198
1199 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1200 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1201 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1202 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1203 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1204 {
1205 int interpolate, location, k;
1206
1207 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1208 location = TGSI_INTERPOLATE_LOC_CENTER;
1209 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1210 location = TGSI_INTERPOLATE_LOC_CENTER;
1211 } else {
1212 location = TGSI_INTERPOLATE_LOC_CENTROID;
1213 }
1214
1215 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1216 k = eg_get_interpolator_index(interpolate, location);
1217 ctx->eg_interpolators[k].enabled = true;
1218 }
1219 }
1220 }
1221
1222 tgsi_parse_free(&parse);
1223
1224 /* assign gpr to each interpolator according to priority */
1225 num_baryc = 0;
1226 for (i = 0; i < Elements(ctx->eg_interpolators); i++) {
1227 if (ctx->eg_interpolators[i].enabled) {
1228 ctx->eg_interpolators[i].ij_index = num_baryc;
1229 num_baryc ++;
1230 }
1231 }
1232
1233 /* XXX PULL MODEL and LINE STIPPLE */
1234
1235 num_baryc = (num_baryc + 1) >> 1;
1236 return allocate_system_value_inputs(ctx, num_baryc);
1237 }
1238
1239 /* sample_id_sel == NULL means fetch for current sample */
1240 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1241 {
1242 struct r600_bytecode_vtx vtx;
1243 int r, t1;
1244
1245 assert(ctx->fixed_pt_position_gpr != -1);
1246
1247 t1 = r600_get_temp(ctx);
1248
1249 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1250 vtx.op = FETCH_OP_VFETCH;
1251 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1252 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1253 if (sample_id == NULL) {
1254 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1255 vtx.src_sel_x = 3;
1256 }
1257 else {
1258 struct r600_bytecode_alu alu;
1259
1260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1261 alu.op = ALU_OP1_MOV;
1262 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1263 alu.dst.sel = t1;
1264 alu.dst.write = 1;
1265 alu.last = 1;
1266 r = r600_bytecode_add_alu(ctx->bc, &alu);
1267 if (r)
1268 return r;
1269
1270 vtx.src_gpr = t1;
1271 vtx.src_sel_x = 0;
1272 }
1273 vtx.mega_fetch_count = 16;
1274 vtx.dst_gpr = t1;
1275 vtx.dst_sel_x = 0;
1276 vtx.dst_sel_y = 1;
1277 vtx.dst_sel_z = 2;
1278 vtx.dst_sel_w = 3;
1279 vtx.data_format = FMT_32_32_32_32_FLOAT;
1280 vtx.num_format_all = 2;
1281 vtx.format_comp_all = 1;
1282 vtx.use_const_fields = 0;
1283 vtx.offset = 1; // first element is size of buffer
1284 vtx.endian = r600_endian_swap(32);
1285 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1286
1287 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1288 if (r)
1289 return r;
1290
1291 return t1;
1292 }
1293
1294 static void tgsi_src(struct r600_shader_ctx *ctx,
1295 const struct tgsi_full_src_register *tgsi_src,
1296 struct r600_shader_src *r600_src)
1297 {
1298 memset(r600_src, 0, sizeof(*r600_src));
1299 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1300 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1301 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1302 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1303 r600_src->neg = tgsi_src->Register.Negate;
1304 r600_src->abs = tgsi_src->Register.Absolute;
1305
1306 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1307 int index;
1308 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1309 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1310 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1311
1312 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1313 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1314 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1315 return;
1316 }
1317 index = tgsi_src->Register.Index;
1318 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1319 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1320 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1321 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1322 r600_src->swizzle[0] = 2; // Z value
1323 r600_src->swizzle[1] = 2;
1324 r600_src->swizzle[2] = 2;
1325 r600_src->swizzle[3] = 2;
1326 r600_src->sel = ctx->face_gpr;
1327 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1328 r600_src->swizzle[0] = 3; // W value
1329 r600_src->swizzle[1] = 3;
1330 r600_src->swizzle[2] = 3;
1331 r600_src->swizzle[3] = 3;
1332 r600_src->sel = ctx->fixed_pt_position_gpr;
1333 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1334 r600_src->swizzle[0] = 0;
1335 r600_src->swizzle[1] = 1;
1336 r600_src->swizzle[2] = 4;
1337 r600_src->swizzle[3] = 4;
1338 r600_src->sel = load_sample_position(ctx, NULL, -1);
1339 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1340 r600_src->swizzle[0] = 3;
1341 r600_src->swizzle[1] = 3;
1342 r600_src->swizzle[2] = 3;
1343 r600_src->swizzle[3] = 3;
1344 r600_src->sel = 0;
1345 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1346 r600_src->swizzle[0] = 0;
1347 r600_src->swizzle[1] = 0;
1348 r600_src->swizzle[2] = 0;
1349 r600_src->swizzle[3] = 0;
1350 r600_src->sel = 0;
1351 } else if (ctx->type != TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1352 r600_src->swizzle[0] = 3;
1353 r600_src->swizzle[1] = 3;
1354 r600_src->swizzle[2] = 3;
1355 r600_src->swizzle[3] = 3;
1356 r600_src->sel = 1;
1357 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1358 r600_src->swizzle[0] = 2;
1359 r600_src->swizzle[1] = 2;
1360 r600_src->swizzle[2] = 2;
1361 r600_src->swizzle[3] = 2;
1362 r600_src->sel = 0;
1363 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1364 r600_src->sel = 1;
1365 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1366 r600_src->sel = 3;
1367 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1368 r600_src->sel = 2;
1369 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1370 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
1371 r600_src->sel = ctx->tess_input_info;
1372 r600_src->swizzle[0] = 2;
1373 r600_src->swizzle[1] = 2;
1374 r600_src->swizzle[2] = 2;
1375 r600_src->swizzle[3] = 2;
1376 } else {
1377 r600_src->sel = ctx->tess_input_info;
1378 r600_src->swizzle[0] = 3;
1379 r600_src->swizzle[1] = 3;
1380 r600_src->swizzle[2] = 3;
1381 r600_src->swizzle[3] = 3;
1382 }
1383 } else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1384 r600_src->sel = 0;
1385 r600_src->swizzle[0] = 0;
1386 r600_src->swizzle[1] = 0;
1387 r600_src->swizzle[2] = 0;
1388 r600_src->swizzle[3] = 0;
1389 } else if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1390 r600_src->sel = 0;
1391 r600_src->swizzle[0] = 3;
1392 r600_src->swizzle[1] = 3;
1393 r600_src->swizzle[2] = 3;
1394 r600_src->swizzle[3] = 3;
1395 }
1396 } else {
1397 if (tgsi_src->Register.Indirect)
1398 r600_src->rel = V_SQ_REL_RELATIVE;
1399 r600_src->sel = tgsi_src->Register.Index;
1400 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1401 }
1402 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1403 if (tgsi_src->Register.Dimension) {
1404 r600_src->kc_bank = tgsi_src->Dimension.Index;
1405 if (tgsi_src->Dimension.Indirect) {
1406 r600_src->kc_rel = 1;
1407 }
1408 }
1409 }
1410 }
1411
1412 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1413 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1414 unsigned int dst_reg)
1415 {
1416 struct r600_bytecode_vtx vtx;
1417 unsigned int ar_reg;
1418 int r;
1419
1420 if (offset) {
1421 struct r600_bytecode_alu alu;
1422
1423 memset(&alu, 0, sizeof(alu));
1424
1425 alu.op = ALU_OP2_ADD_INT;
1426 alu.src[0].sel = ctx->bc->ar_reg;
1427 alu.src[0].chan = ar_chan;
1428
1429 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1430 alu.src[1].value = offset;
1431
1432 alu.dst.sel = dst_reg;
1433 alu.dst.chan = ar_chan;
1434 alu.dst.write = 1;
1435 alu.last = 1;
1436
1437 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1438 return r;
1439
1440 ar_reg = dst_reg;
1441 } else {
1442 ar_reg = ctx->bc->ar_reg;
1443 }
1444
1445 memset(&vtx, 0, sizeof(vtx));
1446 vtx.buffer_id = cb_idx;
1447 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1448 vtx.src_gpr = ar_reg;
1449 vtx.src_sel_x = ar_chan;
1450 vtx.mega_fetch_count = 16;
1451 vtx.dst_gpr = dst_reg;
1452 vtx.dst_sel_x = 0; /* SEL_X */
1453 vtx.dst_sel_y = 1; /* SEL_Y */
1454 vtx.dst_sel_z = 2; /* SEL_Z */
1455 vtx.dst_sel_w = 3; /* SEL_W */
1456 vtx.data_format = FMT_32_32_32_32_FLOAT;
1457 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1458 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1459 vtx.endian = r600_endian_swap(32);
1460 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1461
1462 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1463 return r;
1464
1465 return 0;
1466 }
1467
1468 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1469 {
1470 struct r600_bytecode_vtx vtx;
1471 int r;
1472 unsigned index = src->Register.Index;
1473 unsigned vtx_id = src->Dimension.Index;
1474 int offset_reg = vtx_id / 3;
1475 int offset_chan = vtx_id % 3;
1476 int t2 = 0;
1477
1478 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1479 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1480
1481 if (offset_reg == 0 && offset_chan == 2)
1482 offset_chan = 3;
1483
1484 if (src->Dimension.Indirect || src->Register.Indirect)
1485 t2 = r600_get_temp(ctx);
1486
1487 if (src->Dimension.Indirect) {
1488 int treg[3];
1489 struct r600_bytecode_alu alu;
1490 int r, i;
1491 unsigned addr_reg;
1492 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1493 if (src->DimIndirect.Index > 0) {
1494 r = single_alu_op2(ctx, ALU_OP1_MOV,
1495 ctx->bc->ar_reg, 0,
1496 addr_reg, 0,
1497 0, 0);
1498 if (r)
1499 return r;
1500 }
1501 /*
1502 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1503 at least this is what fglrx seems to do. */
1504 for (i = 0; i < 3; i++) {
1505 treg[i] = r600_get_temp(ctx);
1506 }
1507 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1508
1509 for (i = 0; i < 3; i++) {
1510 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1511 alu.op = ALU_OP1_MOV;
1512 alu.src[0].sel = 0;
1513 alu.src[0].chan = i == 2 ? 3 : i;
1514 alu.dst.sel = treg[i];
1515 alu.dst.chan = 0;
1516 alu.dst.write = 1;
1517 alu.last = 1;
1518 r = r600_bytecode_add_alu(ctx->bc, &alu);
1519 if (r)
1520 return r;
1521 }
1522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1523 alu.op = ALU_OP1_MOV;
1524 alu.src[0].sel = treg[0];
1525 alu.src[0].rel = 1;
1526 alu.dst.sel = t2;
1527 alu.dst.write = 1;
1528 alu.last = 1;
1529 r = r600_bytecode_add_alu(ctx->bc, &alu);
1530 if (r)
1531 return r;
1532 offset_reg = t2;
1533 offset_chan = 0;
1534 }
1535
1536 if (src->Register.Indirect) {
1537 int addr_reg;
1538 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1539
1540 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1541
1542 /* pull the value from index_reg */
1543 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1544 t2, 1,
1545 addr_reg, 0,
1546 V_SQ_ALU_SRC_LITERAL, first);
1547 if (r)
1548 return r;
1549 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1550 t2, 0,
1551 t2, 1,
1552 V_SQ_ALU_SRC_LITERAL, 4,
1553 offset_reg, offset_chan);
1554 if (r)
1555 return r;
1556 offset_reg = t2;
1557 offset_chan = 0;
1558 index = src->Register.Index - first;
1559 }
1560
1561 memset(&vtx, 0, sizeof(vtx));
1562 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1563 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1564 vtx.src_gpr = offset_reg;
1565 vtx.src_sel_x = offset_chan;
1566 vtx.offset = index * 16; /*bytes*/
1567 vtx.mega_fetch_count = 16;
1568 vtx.dst_gpr = dst_reg;
1569 vtx.dst_sel_x = 0; /* SEL_X */
1570 vtx.dst_sel_y = 1; /* SEL_Y */
1571 vtx.dst_sel_z = 2; /* SEL_Z */
1572 vtx.dst_sel_w = 3; /* SEL_W */
1573 if (ctx->bc->chip_class >= EVERGREEN) {
1574 vtx.use_const_fields = 1;
1575 } else {
1576 vtx.data_format = FMT_32_32_32_32_FLOAT;
1577 }
1578
1579 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1580 return r;
1581
1582 return 0;
1583 }
1584
1585 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1586 {
1587 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1588 int i;
1589
1590 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1591 struct tgsi_full_src_register *src = &inst->Src[i];
1592
1593 if (src->Register.File == TGSI_FILE_INPUT) {
1594 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1595 /* primitive id is in R0.z */
1596 ctx->src[i].sel = 0;
1597 ctx->src[i].swizzle[0] = 2;
1598 }
1599 }
1600 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1601 int treg = r600_get_temp(ctx);
1602
1603 fetch_gs_input(ctx, src, treg);
1604 ctx->src[i].sel = treg;
1605 ctx->src[i].rel = 0;
1606 }
1607 }
1608 return 0;
1609 }
1610
1611
1612 /* Tessellation shaders pass outputs to the next shader using LDS.
1613 *
1614 * LS outputs = TCS(HS) inputs
1615 * TCS(HS) outputs = TES(DS) inputs
1616 *
1617 * The LDS layout is:
1618 * - TCS inputs for patch 0
1619 * - TCS inputs for patch 1
1620 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1621 * - ...
1622 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1623 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1624 * - TCS outputs for patch 1
1625 * - Per-patch TCS outputs for patch 1
1626 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1627 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1628 * - ...
1629 *
1630 * All three shaders VS(LS), TCS, TES share the same LDS space.
1631 */
1632 /* this will return with the dw address in temp_reg.x */
1633 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1634 const struct tgsi_full_dst_register *dst,
1635 const struct tgsi_full_src_register *src,
1636 int stride_bytes_reg, int stride_bytes_chan)
1637 {
1638 struct tgsi_full_dst_register reg;
1639 ubyte *name, *index, *array_first;
1640 int r;
1641 int param;
1642 struct tgsi_shader_info *info = &ctx->info;
1643 /* Set the register description. The address computation is the same
1644 * for sources and destinations. */
1645 if (src) {
1646 reg.Register.File = src->Register.File;
1647 reg.Register.Index = src->Register.Index;
1648 reg.Register.Indirect = src->Register.Indirect;
1649 reg.Register.Dimension = src->Register.Dimension;
1650 reg.Indirect = src->Indirect;
1651 reg.Dimension = src->Dimension;
1652 reg.DimIndirect = src->DimIndirect;
1653 } else
1654 reg = *dst;
1655
1656 /* If the register is 2-dimensional (e.g. an array of vertices
1657 * in a primitive), calculate the base address of the vertex. */
1658 if (reg.Register.Dimension) {
1659 int sel, chan;
1660 if (reg.Dimension.Indirect) {
1661 unsigned addr_reg;
1662 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1663
1664 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1665 /* pull the value from index_reg */
1666 sel = addr_reg;
1667 chan = 0;
1668 } else {
1669 sel = V_SQ_ALU_SRC_LITERAL;
1670 chan = reg.Dimension.Index;
1671 }
1672
1673 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1674 temp_reg, 0,
1675 stride_bytes_reg, stride_bytes_chan,
1676 sel, chan,
1677 temp_reg, 0);
1678 if (r)
1679 return r;
1680 }
1681
1682 if (reg.Register.File == TGSI_FILE_INPUT) {
1683 name = info->input_semantic_name;
1684 index = info->input_semantic_index;
1685 array_first = info->input_array_first;
1686 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1687 name = info->output_semantic_name;
1688 index = info->output_semantic_index;
1689 array_first = info->output_array_first;
1690 } else {
1691 assert(0);
1692 return -1;
1693 }
1694 if (reg.Register.Indirect) {
1695 int addr_reg;
1696 int first;
1697 /* Add the relative address of the element. */
1698 if (reg.Indirect.ArrayID)
1699 first = array_first[reg.Indirect.ArrayID];
1700 else
1701 first = reg.Register.Index;
1702
1703 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1704
1705 /* pull the value from index_reg */
1706 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1707 temp_reg, 0,
1708 V_SQ_ALU_SRC_LITERAL, 16,
1709 addr_reg, 0,
1710 temp_reg, 0);
1711 if (r)
1712 return r;
1713
1714 param = r600_get_lds_unique_index(name[first],
1715 index[first]);
1716
1717 } else {
1718 param = r600_get_lds_unique_index(name[reg.Register.Index],
1719 index[reg.Register.Index]);
1720 }
1721
1722 /* add to base_addr - passed in temp_reg.x */
1723 if (param) {
1724 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1725 temp_reg, 0,
1726 temp_reg, 0,
1727 V_SQ_ALU_SRC_LITERAL, param * 16);
1728 if (r)
1729 return r;
1730
1731 }
1732 return 0;
1733 }
1734
1735 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1736 unsigned dst_reg)
1737 {
1738 struct r600_bytecode_alu alu;
1739 int r, i;
1740
1741 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1742 ctx->bc->force_add_cf = 1;
1743 for (i = 1; i < 4; i++) {
1744 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1745 temp_reg, i,
1746 temp_reg, 0,
1747 V_SQ_ALU_SRC_LITERAL, 4 * i);
1748 if (r)
1749 return r;
1750 }
1751 for (i = 0; i < 4; i++) {
1752 /* emit an LDS_READ_RET */
1753 memset(&alu, 0, sizeof(alu));
1754 alu.op = LDS_OP1_LDS_READ_RET;
1755 alu.src[0].sel = temp_reg;
1756 alu.src[0].chan = i;
1757 alu.src[1].sel = V_SQ_ALU_SRC_0;
1758 alu.src[2].sel = V_SQ_ALU_SRC_0;
1759 alu.dst.chan = 0;
1760 alu.is_lds_idx_op = true;
1761 alu.last = 1;
1762 r = r600_bytecode_add_alu(ctx->bc, &alu);
1763 if (r)
1764 return r;
1765 }
1766 for (i = 0; i < 4; i++) {
1767 /* then read from LDS_OQ_A_POP */
1768 memset(&alu, 0, sizeof(alu));
1769
1770 alu.op = ALU_OP1_MOV;
1771 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1772 alu.src[0].chan = 0;
1773 alu.dst.sel = dst_reg;
1774 alu.dst.chan = i;
1775 alu.dst.write = 1;
1776 alu.last = 1;
1777 r = r600_bytecode_add_alu(ctx->bc, &alu);
1778 if (r)
1779 return r;
1780 }
1781 return 0;
1782 }
1783
1784 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1785 {
1786 int r;
1787 unsigned temp_reg = r600_get_temp(ctx);
1788
1789 r = get_lds_offset0(ctx, 2, temp_reg,
1790 src->Register.Dimension ? false : true);
1791 if (r)
1792 return r;
1793
1794 /* the base address is now in temp.x */
1795 r = r600_get_byte_address(ctx, temp_reg,
1796 NULL, src, ctx->tess_output_info, 1);
1797 if (r)
1798 return r;
1799
1800 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1801 if (r)
1802 return r;
1803 return 0;
1804 }
1805
1806 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1807 {
1808 int r;
1809 unsigned temp_reg = r600_get_temp(ctx);
1810
1811 /* t.x = ips * r0.y */
1812 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1813 temp_reg, 0,
1814 ctx->tess_input_info, 0,
1815 0, 1);
1816
1817 if (r)
1818 return r;
1819
1820 /* the base address is now in temp.x */
1821 r = r600_get_byte_address(ctx, temp_reg,
1822 NULL, src, ctx->tess_input_info, 1);
1823 if (r)
1824 return r;
1825
1826 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1827 if (r)
1828 return r;
1829 return 0;
1830 }
1831
1832 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1833 {
1834 int r;
1835 unsigned temp_reg = r600_get_temp(ctx);
1836
1837 r = get_lds_offset0(ctx, 1, temp_reg,
1838 src->Register.Dimension ? false : true);
1839 if (r)
1840 return r;
1841 /* the base address is now in temp.x */
1842 r = r600_get_byte_address(ctx, temp_reg,
1843 NULL, src,
1844 ctx->tess_output_info, 1);
1845 if (r)
1846 return r;
1847
1848 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1849 if (r)
1850 return r;
1851 return 0;
1852 }
1853
1854 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1855 {
1856 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1857 int i;
1858
1859 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1860 struct tgsi_full_src_register *src = &inst->Src[i];
1861
1862 if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1863 int treg = r600_get_temp(ctx);
1864 fetch_tes_input(ctx, src, treg);
1865 ctx->src[i].sel = treg;
1866 ctx->src[i].rel = 0;
1867 }
1868 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1869 int treg = r600_get_temp(ctx);
1870 fetch_tcs_input(ctx, src, treg);
1871 ctx->src[i].sel = treg;
1872 ctx->src[i].rel = 0;
1873 }
1874 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1875 int treg = r600_get_temp(ctx);
1876 fetch_tcs_output(ctx, src, treg);
1877 ctx->src[i].sel = treg;
1878 ctx->src[i].rel = 0;
1879 }
1880 }
1881 return 0;
1882 }
1883
1884 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1885 {
1886 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1887 struct r600_bytecode_alu alu;
1888 int i, j, k, nconst, r;
1889
1890 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1891 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1892 nconst++;
1893 }
1894 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1895 }
1896 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1897 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1898 continue;
1899 }
1900
1901 if (ctx->src[i].rel) {
1902 int chan = inst->Src[i].Indirect.Swizzle;
1903 int treg = r600_get_temp(ctx);
1904 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1905 return r;
1906
1907 ctx->src[i].kc_bank = 0;
1908 ctx->src[i].kc_rel = 0;
1909 ctx->src[i].sel = treg;
1910 ctx->src[i].rel = 0;
1911 j--;
1912 } else if (j > 0) {
1913 int treg = r600_get_temp(ctx);
1914 for (k = 0; k < 4; k++) {
1915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1916 alu.op = ALU_OP1_MOV;
1917 alu.src[0].sel = ctx->src[i].sel;
1918 alu.src[0].chan = k;
1919 alu.src[0].rel = ctx->src[i].rel;
1920 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1921 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1922 alu.dst.sel = treg;
1923 alu.dst.chan = k;
1924 alu.dst.write = 1;
1925 if (k == 3)
1926 alu.last = 1;
1927 r = r600_bytecode_add_alu(ctx->bc, &alu);
1928 if (r)
1929 return r;
1930 }
1931 ctx->src[i].sel = treg;
1932 ctx->src[i].rel =0;
1933 j--;
1934 }
1935 }
1936 return 0;
1937 }
1938
1939 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1940 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1941 {
1942 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1943 struct r600_bytecode_alu alu;
1944 int i, j, k, nliteral, r;
1945
1946 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1947 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1948 nliteral++;
1949 }
1950 }
1951 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1952 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1953 int treg = r600_get_temp(ctx);
1954 for (k = 0; k < 4; k++) {
1955 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1956 alu.op = ALU_OP1_MOV;
1957 alu.src[0].sel = ctx->src[i].sel;
1958 alu.src[0].chan = k;
1959 alu.src[0].value = ctx->src[i].value[k];
1960 alu.dst.sel = treg;
1961 alu.dst.chan = k;
1962 alu.dst.write = 1;
1963 if (k == 3)
1964 alu.last = 1;
1965 r = r600_bytecode_add_alu(ctx->bc, &alu);
1966 if (r)
1967 return r;
1968 }
1969 ctx->src[i].sel = treg;
1970 j--;
1971 }
1972 }
1973 return 0;
1974 }
1975
1976 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1977 {
1978 int i, r, count = ctx->shader->ninput;
1979
1980 for (i = 0; i < count; i++) {
1981 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1982 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1983 if (r)
1984 return r;
1985 }
1986 }
1987 return 0;
1988 }
1989
1990 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1991 int stream, unsigned *stream_item_size)
1992 {
1993 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1994 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1995 int i, j, r;
1996
1997 /* Sanity checking. */
1998 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1999 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2000 r = -EINVAL;
2001 goto out_err;
2002 }
2003 for (i = 0; i < so->num_outputs; i++) {
2004 if (so->output[i].output_buffer >= 4) {
2005 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2006 so->output[i].output_buffer);
2007 r = -EINVAL;
2008 goto out_err;
2009 }
2010 }
2011
2012 /* Initialize locations where the outputs are stored. */
2013 for (i = 0; i < so->num_outputs; i++) {
2014
2015 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2016 start_comp[i] = so->output[i].start_component;
2017 /* Lower outputs with dst_offset < start_component.
2018 *
2019 * We can only output 4D vectors with a write mask, e.g. we can
2020 * only output the W component at offset 3, etc. If we want
2021 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2022 * to move it to X and output X. */
2023 if (so->output[i].dst_offset < so->output[i].start_component) {
2024 unsigned tmp = r600_get_temp(ctx);
2025
2026 for (j = 0; j < so->output[i].num_components; j++) {
2027 struct r600_bytecode_alu alu;
2028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2029 alu.op = ALU_OP1_MOV;
2030 alu.src[0].sel = so_gpr[i];
2031 alu.src[0].chan = so->output[i].start_component + j;
2032
2033 alu.dst.sel = tmp;
2034 alu.dst.chan = j;
2035 alu.dst.write = 1;
2036 if (j == so->output[i].num_components - 1)
2037 alu.last = 1;
2038 r = r600_bytecode_add_alu(ctx->bc, &alu);
2039 if (r)
2040 return r;
2041 }
2042 start_comp[i] = 0;
2043 so_gpr[i] = tmp;
2044 }
2045 }
2046
2047 /* Write outputs to buffers. */
2048 for (i = 0; i < so->num_outputs; i++) {
2049 struct r600_bytecode_output output;
2050
2051 if (stream != -1 && stream != so->output[i].output_buffer)
2052 continue;
2053
2054 memset(&output, 0, sizeof(struct r600_bytecode_output));
2055 output.gpr = so_gpr[i];
2056 output.elem_size = so->output[i].num_components - 1;
2057 if (output.elem_size == 2)
2058 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2059 output.array_base = so->output[i].dst_offset - start_comp[i];
2060 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2061 output.burst_count = 1;
2062 /* array_size is an upper limit for the burst_count
2063 * with MEM_STREAM instructions */
2064 output.array_size = 0xFFF;
2065 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2066
2067 if (ctx->bc->chip_class >= EVERGREEN) {
2068 switch (so->output[i].output_buffer) {
2069 case 0:
2070 output.op = CF_OP_MEM_STREAM0_BUF0;
2071 break;
2072 case 1:
2073 output.op = CF_OP_MEM_STREAM0_BUF1;
2074 break;
2075 case 2:
2076 output.op = CF_OP_MEM_STREAM0_BUF2;
2077 break;
2078 case 3:
2079 output.op = CF_OP_MEM_STREAM0_BUF3;
2080 break;
2081 }
2082 output.op += so->output[i].stream * 4;
2083 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2084 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2085 } else {
2086 switch (so->output[i].output_buffer) {
2087 case 0:
2088 output.op = CF_OP_MEM_STREAM0;
2089 break;
2090 case 1:
2091 output.op = CF_OP_MEM_STREAM1;
2092 break;
2093 case 2:
2094 output.op = CF_OP_MEM_STREAM2;
2095 break;
2096 case 3:
2097 output.op = CF_OP_MEM_STREAM3;
2098 break;
2099 }
2100 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2101 }
2102 r = r600_bytecode_add_output(ctx->bc, &output);
2103 if (r)
2104 goto out_err;
2105 }
2106 return 0;
2107 out_err:
2108 return r;
2109 }
2110
2111 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2112 {
2113 struct r600_bytecode_alu alu;
2114 unsigned reg;
2115
2116 if (!ctx->shader->vs_out_edgeflag)
2117 return;
2118
2119 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2120
2121 /* clamp(x, 0, 1) */
2122 memset(&alu, 0, sizeof(alu));
2123 alu.op = ALU_OP1_MOV;
2124 alu.src[0].sel = reg;
2125 alu.dst.sel = reg;
2126 alu.dst.write = 1;
2127 alu.dst.clamp = 1;
2128 alu.last = 1;
2129 r600_bytecode_add_alu(ctx->bc, &alu);
2130
2131 memset(&alu, 0, sizeof(alu));
2132 alu.op = ALU_OP1_FLT_TO_INT;
2133 alu.src[0].sel = reg;
2134 alu.dst.sel = reg;
2135 alu.dst.write = 1;
2136 alu.last = 1;
2137 r600_bytecode_add_alu(ctx->bc, &alu);
2138 }
2139
2140 static int generate_gs_copy_shader(struct r600_context *rctx,
2141 struct r600_pipe_shader *gs,
2142 struct pipe_stream_output_info *so)
2143 {
2144 struct r600_shader_ctx ctx = {};
2145 struct r600_shader *gs_shader = &gs->shader;
2146 struct r600_pipe_shader *cshader;
2147 int ocnt = gs_shader->noutput;
2148 struct r600_bytecode_alu alu;
2149 struct r600_bytecode_vtx vtx;
2150 struct r600_bytecode_output output;
2151 struct r600_bytecode_cf *cf_jump, *cf_pop,
2152 *last_exp_pos = NULL, *last_exp_param = NULL;
2153 int i, j, next_clip_pos = 61, next_param = 0;
2154 int ring;
2155 bool only_ring_0 = true;
2156 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2157 if (!cshader)
2158 return 0;
2159
2160 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2161 sizeof(struct r600_shader_io));
2162
2163 cshader->shader.noutput = ocnt;
2164
2165 ctx.shader = &cshader->shader;
2166 ctx.bc = &ctx.shader->bc;
2167 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
2168
2169 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2170 rctx->screen->has_compressed_msaa_texturing);
2171
2172 ctx.bc->isa = rctx->isa;
2173
2174 cf_jump = NULL;
2175 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2176
2177 /* R0.x = R0.x & 0x3fffffff */
2178 memset(&alu, 0, sizeof(alu));
2179 alu.op = ALU_OP2_AND_INT;
2180 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2181 alu.src[1].value = 0x3fffffff;
2182 alu.dst.write = 1;
2183 r600_bytecode_add_alu(ctx.bc, &alu);
2184
2185 /* R0.y = R0.x >> 30 */
2186 memset(&alu, 0, sizeof(alu));
2187 alu.op = ALU_OP2_LSHR_INT;
2188 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2189 alu.src[1].value = 0x1e;
2190 alu.dst.chan = 1;
2191 alu.dst.write = 1;
2192 alu.last = 1;
2193 r600_bytecode_add_alu(ctx.bc, &alu);
2194
2195 /* fetch vertex data from GSVS ring */
2196 for (i = 0; i < ocnt; ++i) {
2197 struct r600_shader_io *out = &ctx.shader->output[i];
2198
2199 out->gpr = i + 1;
2200 out->ring_offset = i * 16;
2201
2202 memset(&vtx, 0, sizeof(vtx));
2203 vtx.op = FETCH_OP_VFETCH;
2204 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2205 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2206 vtx.mega_fetch_count = 16;
2207 vtx.offset = out->ring_offset;
2208 vtx.dst_gpr = out->gpr;
2209 vtx.src_gpr = 0;
2210 vtx.dst_sel_x = 0;
2211 vtx.dst_sel_y = 1;
2212 vtx.dst_sel_z = 2;
2213 vtx.dst_sel_w = 3;
2214 if (rctx->b.chip_class >= EVERGREEN) {
2215 vtx.use_const_fields = 1;
2216 } else {
2217 vtx.data_format = FMT_32_32_32_32_FLOAT;
2218 }
2219
2220 r600_bytecode_add_vtx(ctx.bc, &vtx);
2221 }
2222 ctx.temp_reg = i + 1;
2223 for (ring = 3; ring >= 0; --ring) {
2224 bool enabled = false;
2225 for (i = 0; i < so->num_outputs; i++) {
2226 if (so->output[i].stream == ring) {
2227 enabled = true;
2228 if (ring > 0)
2229 only_ring_0 = false;
2230 break;
2231 }
2232 }
2233 if (ring != 0 && !enabled) {
2234 cshader->shader.ring_item_sizes[ring] = 0;
2235 continue;
2236 }
2237
2238 if (cf_jump) {
2239 // Patch up jump label
2240 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2241 cf_pop = ctx.bc->cf_last;
2242
2243 cf_jump->cf_addr = cf_pop->id + 2;
2244 cf_jump->pop_count = 1;
2245 cf_pop->cf_addr = cf_pop->id + 2;
2246 cf_pop->pop_count = 1;
2247 }
2248
2249 /* PRED_SETE_INT __, R0.y, ring */
2250 memset(&alu, 0, sizeof(alu));
2251 alu.op = ALU_OP2_PRED_SETE_INT;
2252 alu.src[0].chan = 1;
2253 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2254 alu.src[1].value = ring;
2255 alu.execute_mask = 1;
2256 alu.update_pred = 1;
2257 alu.last = 1;
2258 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2259
2260 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2261 cf_jump = ctx.bc->cf_last;
2262
2263 if (enabled)
2264 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2265 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2266 }
2267
2268 /* bc adds nops - copy it */
2269 if (ctx.bc->chip_class == R600) {
2270 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2271 alu.op = ALU_OP0_NOP;
2272 alu.last = 1;
2273 r600_bytecode_add_alu(ctx.bc, &alu);
2274
2275 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2276 }
2277
2278 /* export vertex data */
2279 /* XXX factor out common code with r600_shader_from_tgsi ? */
2280 for (i = 0; i < ocnt; ++i) {
2281 struct r600_shader_io *out = &ctx.shader->output[i];
2282 bool instream0 = true;
2283 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2284 continue;
2285
2286 for (j = 0; j < so->num_outputs; j++) {
2287 if (so->output[j].register_index == i) {
2288 if (so->output[j].stream == 0)
2289 break;
2290 if (so->output[j].stream > 0)
2291 instream0 = false;
2292 }
2293 }
2294 if (!instream0)
2295 continue;
2296 memset(&output, 0, sizeof(output));
2297 output.gpr = out->gpr;
2298 output.elem_size = 3;
2299 output.swizzle_x = 0;
2300 output.swizzle_y = 1;
2301 output.swizzle_z = 2;
2302 output.swizzle_w = 3;
2303 output.burst_count = 1;
2304 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2305 output.op = CF_OP_EXPORT;
2306 switch (out->name) {
2307 case TGSI_SEMANTIC_POSITION:
2308 output.array_base = 60;
2309 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2310 break;
2311
2312 case TGSI_SEMANTIC_PSIZE:
2313 output.array_base = 61;
2314 if (next_clip_pos == 61)
2315 next_clip_pos = 62;
2316 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2317 output.swizzle_y = 7;
2318 output.swizzle_z = 7;
2319 output.swizzle_w = 7;
2320 ctx.shader->vs_out_misc_write = 1;
2321 ctx.shader->vs_out_point_size = 1;
2322 break;
2323 case TGSI_SEMANTIC_LAYER:
2324 if (out->spi_sid) {
2325 /* duplicate it as PARAM to pass to the pixel shader */
2326 output.array_base = next_param++;
2327 r600_bytecode_add_output(ctx.bc, &output);
2328 last_exp_param = ctx.bc->cf_last;
2329 }
2330 output.array_base = 61;
2331 if (next_clip_pos == 61)
2332 next_clip_pos = 62;
2333 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2334 output.swizzle_x = 7;
2335 output.swizzle_y = 7;
2336 output.swizzle_z = 0;
2337 output.swizzle_w = 7;
2338 ctx.shader->vs_out_misc_write = 1;
2339 ctx.shader->vs_out_layer = 1;
2340 break;
2341 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2342 if (out->spi_sid) {
2343 /* duplicate it as PARAM to pass to the pixel shader */
2344 output.array_base = next_param++;
2345 r600_bytecode_add_output(ctx.bc, &output);
2346 last_exp_param = ctx.bc->cf_last;
2347 }
2348 output.array_base = 61;
2349 if (next_clip_pos == 61)
2350 next_clip_pos = 62;
2351 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2352 ctx.shader->vs_out_misc_write = 1;
2353 ctx.shader->vs_out_viewport = 1;
2354 output.swizzle_x = 7;
2355 output.swizzle_y = 7;
2356 output.swizzle_z = 7;
2357 output.swizzle_w = 0;
2358 break;
2359 case TGSI_SEMANTIC_CLIPDIST:
2360 /* spi_sid is 0 for clipdistance outputs that were generated
2361 * for clipvertex - we don't need to pass them to PS */
2362 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2363 if (out->spi_sid) {
2364 /* duplicate it as PARAM to pass to the pixel shader */
2365 output.array_base = next_param++;
2366 r600_bytecode_add_output(ctx.bc, &output);
2367 last_exp_param = ctx.bc->cf_last;
2368 }
2369 output.array_base = next_clip_pos++;
2370 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2371 break;
2372 case TGSI_SEMANTIC_FOG:
2373 output.swizzle_y = 4; /* 0 */
2374 output.swizzle_z = 4; /* 0 */
2375 output.swizzle_w = 5; /* 1 */
2376 break;
2377 default:
2378 output.array_base = next_param++;
2379 break;
2380 }
2381 r600_bytecode_add_output(ctx.bc, &output);
2382 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2383 last_exp_param = ctx.bc->cf_last;
2384 else
2385 last_exp_pos = ctx.bc->cf_last;
2386 }
2387
2388 if (!last_exp_pos) {
2389 memset(&output, 0, sizeof(output));
2390 output.gpr = 0;
2391 output.elem_size = 3;
2392 output.swizzle_x = 7;
2393 output.swizzle_y = 7;
2394 output.swizzle_z = 7;
2395 output.swizzle_w = 7;
2396 output.burst_count = 1;
2397 output.type = 2;
2398 output.op = CF_OP_EXPORT;
2399 output.array_base = 60;
2400 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2401 r600_bytecode_add_output(ctx.bc, &output);
2402 last_exp_pos = ctx.bc->cf_last;
2403 }
2404
2405 if (!last_exp_param) {
2406 memset(&output, 0, sizeof(output));
2407 output.gpr = 0;
2408 output.elem_size = 3;
2409 output.swizzle_x = 7;
2410 output.swizzle_y = 7;
2411 output.swizzle_z = 7;
2412 output.swizzle_w = 7;
2413 output.burst_count = 1;
2414 output.type = 2;
2415 output.op = CF_OP_EXPORT;
2416 output.array_base = next_param++;
2417 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2418 r600_bytecode_add_output(ctx.bc, &output);
2419 last_exp_param = ctx.bc->cf_last;
2420 }
2421
2422 last_exp_pos->op = CF_OP_EXPORT_DONE;
2423 last_exp_param->op = CF_OP_EXPORT_DONE;
2424
2425 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2426 cf_pop = ctx.bc->cf_last;
2427
2428 cf_jump->cf_addr = cf_pop->id + 2;
2429 cf_jump->pop_count = 1;
2430 cf_pop->cf_addr = cf_pop->id + 2;
2431 cf_pop->pop_count = 1;
2432
2433 if (ctx.bc->chip_class == CAYMAN)
2434 cm_bytecode_add_cf_end(ctx.bc);
2435 else {
2436 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2437 ctx.bc->cf_last->end_of_program = 1;
2438 }
2439
2440 gs->gs_copy_shader = cshader;
2441 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2442
2443 ctx.bc->nstack = 1;
2444
2445 return r600_bytecode_build(ctx.bc);
2446 }
2447
2448 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2449 {
2450 if (ind) {
2451 struct r600_bytecode_alu alu;
2452 int r;
2453
2454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2455 alu.op = ALU_OP2_ADD_INT;
2456 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2457 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2458 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2459 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2460 alu.dst.write = 1;
2461 alu.last = 1;
2462 r = r600_bytecode_add_alu(ctx->bc, &alu);
2463 if (r)
2464 return r;
2465 }
2466 return 0;
2467 }
2468
2469 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2470 {
2471 struct r600_bytecode_output output;
2472 int i, k, ring_offset;
2473 int effective_stream = stream == -1 ? 0 : stream;
2474 int idx = 0;
2475
2476 for (i = 0; i < ctx->shader->noutput; i++) {
2477 if (ctx->gs_for_vs) {
2478 /* for ES we need to lookup corresponding ring offset expected by GS
2479 * (map this output to GS input by name and sid) */
2480 /* FIXME precompute offsets */
2481 ring_offset = -1;
2482 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2483 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2484 struct r600_shader_io *out = &ctx->shader->output[i];
2485 if (in->name == out->name && in->sid == out->sid)
2486 ring_offset = in->ring_offset;
2487 }
2488
2489 if (ring_offset == -1)
2490 continue;
2491 } else {
2492 ring_offset = idx * 16;
2493 idx++;
2494 }
2495
2496 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2497 continue;
2498 /* next_ring_offset after parsing input decls contains total size of
2499 * single vertex data, gs_next_vertex - current vertex index */
2500 if (!ind)
2501 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2502
2503 memset(&output, 0, sizeof(struct r600_bytecode_output));
2504 output.gpr = ctx->shader->output[i].gpr;
2505 output.elem_size = 3;
2506 output.comp_mask = 0xF;
2507 output.burst_count = 1;
2508
2509 if (ind)
2510 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2511 else
2512 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2513
2514 switch (stream) {
2515 default:
2516 case 0:
2517 output.op = CF_OP_MEM_RING; break;
2518 case 1:
2519 output.op = CF_OP_MEM_RING1; break;
2520 case 2:
2521 output.op = CF_OP_MEM_RING2; break;
2522 case 3:
2523 output.op = CF_OP_MEM_RING3; break;
2524 }
2525
2526 if (ind) {
2527 output.array_base = ring_offset >> 2; /* in dwords */
2528 output.array_size = 0xfff;
2529 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2530 } else
2531 output.array_base = ring_offset >> 2; /* in dwords */
2532 r600_bytecode_add_output(ctx->bc, &output);
2533 }
2534
2535 ++ctx->gs_next_vertex;
2536 return 0;
2537 }
2538
2539
2540 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2541 {
2542 int r;
2543 struct r600_bytecode_vtx vtx;
2544 int temp_val = ctx->temp_reg;
2545 /* need to store the TCS output somewhere */
2546 r = single_alu_op2(ctx, ALU_OP1_MOV,
2547 temp_val, 0,
2548 V_SQ_ALU_SRC_LITERAL, 0,
2549 0, 0);
2550 if (r)
2551 return r;
2552
2553 /* used by VS/TCS */
2554 if (ctx->tess_input_info) {
2555 /* fetch tcs input values into resv space */
2556 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2557 vtx.op = FETCH_OP_VFETCH;
2558 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2559 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2560 vtx.mega_fetch_count = 16;
2561 vtx.data_format = FMT_32_32_32_32;
2562 vtx.num_format_all = 2;
2563 vtx.format_comp_all = 1;
2564 vtx.use_const_fields = 0;
2565 vtx.endian = r600_endian_swap(32);
2566 vtx.srf_mode_all = 1;
2567 vtx.offset = 0;
2568 vtx.dst_gpr = ctx->tess_input_info;
2569 vtx.dst_sel_x = 0;
2570 vtx.dst_sel_y = 1;
2571 vtx.dst_sel_z = 2;
2572 vtx.dst_sel_w = 3;
2573 vtx.src_gpr = temp_val;
2574 vtx.src_sel_x = 0;
2575
2576 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2577 if (r)
2578 return r;
2579 }
2580
2581 /* used by TCS/TES */
2582 if (ctx->tess_output_info) {
2583 /* fetch tcs output values into resv space */
2584 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2585 vtx.op = FETCH_OP_VFETCH;
2586 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2587 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2588 vtx.mega_fetch_count = 16;
2589 vtx.data_format = FMT_32_32_32_32;
2590 vtx.num_format_all = 2;
2591 vtx.format_comp_all = 1;
2592 vtx.use_const_fields = 0;
2593 vtx.endian = r600_endian_swap(32);
2594 vtx.srf_mode_all = 1;
2595 vtx.offset = 16;
2596 vtx.dst_gpr = ctx->tess_output_info;
2597 vtx.dst_sel_x = 0;
2598 vtx.dst_sel_y = 1;
2599 vtx.dst_sel_z = 2;
2600 vtx.dst_sel_w = 3;
2601 vtx.src_gpr = temp_val;
2602 vtx.src_sel_x = 0;
2603
2604 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2605 if (r)
2606 return r;
2607 }
2608 return 0;
2609 }
2610
2611 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2612 {
2613 int i, j, r;
2614 int temp_reg;
2615
2616 /* fetch tcs input values into input_vals */
2617 ctx->tess_input_info = r600_get_temp(ctx);
2618 ctx->tess_output_info = 0;
2619 r = r600_fetch_tess_io_info(ctx);
2620 if (r)
2621 return r;
2622
2623 temp_reg = r600_get_temp(ctx);
2624 /* dst reg contains LDS address stride * idx */
2625 /* MUL vertexID, vertex_dw_stride */
2626 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2627 temp_reg, 0,
2628 ctx->tess_input_info, 1,
2629 0, 1); /* rel id in r0.y? */
2630 if (r)
2631 return r;
2632
2633 for (i = 0; i < ctx->shader->noutput; i++) {
2634 struct r600_bytecode_alu alu;
2635 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2636
2637 if (param) {
2638 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2639 temp_reg, 1,
2640 temp_reg, 0,
2641 V_SQ_ALU_SRC_LITERAL, param * 16);
2642 if (r)
2643 return r;
2644 }
2645
2646 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2647 temp_reg, 2,
2648 temp_reg, param ? 1 : 0,
2649 V_SQ_ALU_SRC_LITERAL, 8);
2650 if (r)
2651 return r;
2652
2653
2654 for (j = 0; j < 2; j++) {
2655 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2656 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2657 alu.op = LDS_OP3_LDS_WRITE_REL;
2658 alu.src[0].sel = temp_reg;
2659 alu.src[0].chan = chan;
2660 alu.src[1].sel = ctx->shader->output[i].gpr;
2661 alu.src[1].chan = j * 2;
2662 alu.src[2].sel = ctx->shader->output[i].gpr;
2663 alu.src[2].chan = (j * 2) + 1;
2664 alu.last = 1;
2665 alu.dst.chan = 0;
2666 alu.lds_idx = 1;
2667 alu.is_lds_idx_op = true;
2668 r = r600_bytecode_add_alu(ctx->bc, &alu);
2669 if (r)
2670 return r;
2671 }
2672 }
2673 return 0;
2674 }
2675
2676 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2677 {
2678 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2679 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2680 int i, r, lasti;
2681 int temp_reg = r600_get_temp(ctx);
2682 struct r600_bytecode_alu alu;
2683 unsigned write_mask = dst->Register.WriteMask;
2684
2685 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2686 return 0;
2687
2688 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2689 if (r)
2690 return r;
2691
2692 /* the base address is now in temp.x */
2693 r = r600_get_byte_address(ctx, temp_reg,
2694 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2695 if (r)
2696 return r;
2697
2698 /* LDS write */
2699 lasti = tgsi_last_instruction(write_mask);
2700 for (i = 1; i <= lasti; i++) {
2701
2702 if (!(write_mask & (1 << i)))
2703 continue;
2704 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2705 temp_reg, i,
2706 temp_reg, 0,
2707 V_SQ_ALU_SRC_LITERAL, 4 * i);
2708 if (r)
2709 return r;
2710 }
2711
2712 for (i = 0; i <= lasti; i++) {
2713 if (!(write_mask & (1 << i)))
2714 continue;
2715
2716 if ((i == 0 && ((write_mask & 3) == 3)) ||
2717 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2719 alu.op = LDS_OP3_LDS_WRITE_REL;
2720 alu.src[0].sel = temp_reg;
2721 alu.src[0].chan = i;
2722
2723 alu.src[1].sel = dst->Register.Index;
2724 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2725 alu.src[1].chan = i;
2726
2727 alu.src[2].sel = dst->Register.Index;
2728 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2729 alu.src[2].chan = i + 1;
2730 alu.lds_idx = 1;
2731 alu.dst.chan = 0;
2732 alu.last = 1;
2733 alu.is_lds_idx_op = true;
2734 r = r600_bytecode_add_alu(ctx->bc, &alu);
2735 if (r)
2736 return r;
2737 i += 1;
2738 continue;
2739 }
2740 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2741 alu.op = LDS_OP2_LDS_WRITE;
2742 alu.src[0].sel = temp_reg;
2743 alu.src[0].chan = i;
2744
2745 alu.src[1].sel = dst->Register.Index;
2746 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2747 alu.src[1].chan = i;
2748
2749 alu.src[2].sel = V_SQ_ALU_SRC_0;
2750 alu.dst.chan = 0;
2751 alu.last = 1;
2752 alu.is_lds_idx_op = true;
2753 r = r600_bytecode_add_alu(ctx->bc, &alu);
2754 if (r)
2755 return r;
2756 }
2757 return 0;
2758 }
2759
2760 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2761 int output_idx)
2762 {
2763 int param;
2764 unsigned temp_reg = r600_get_temp(ctx);
2765 unsigned name = ctx->shader->output[output_idx].name;
2766 int dreg = ctx->shader->output[output_idx].gpr;
2767 int r;
2768
2769 param = r600_get_lds_unique_index(name, 0);
2770 r = get_lds_offset0(ctx, 1, temp_reg, true);
2771 if (r)
2772 return r;
2773
2774 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2775 temp_reg, 0,
2776 temp_reg, 0,
2777 V_SQ_ALU_SRC_LITERAL, param * 16);
2778 if (r)
2779 return r;
2780
2781 do_lds_fetch_values(ctx, temp_reg, dreg);
2782 return 0;
2783 }
2784
2785 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2786 {
2787 int i;
2788 int stride, outer_comps, inner_comps;
2789 int tessinner_idx = -1, tessouter_idx = -1;
2790 int r;
2791 int temp_reg = r600_get_temp(ctx);
2792 int treg[3] = {-1, -1, -1};
2793 struct r600_bytecode_alu alu;
2794 struct r600_bytecode_cf *cf_jump, *cf_pop;
2795
2796 /* only execute factor emission for invocation 0 */
2797 /* PRED_SETE_INT __, R0.x, 0 */
2798 memset(&alu, 0, sizeof(alu));
2799 alu.op = ALU_OP2_PRED_SETE_INT;
2800 alu.src[0].chan = 2;
2801 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2802 alu.execute_mask = 1;
2803 alu.update_pred = 1;
2804 alu.last = 1;
2805 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2806
2807 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2808 cf_jump = ctx->bc->cf_last;
2809
2810 treg[0] = r600_get_temp(ctx);
2811 switch (ctx->shader->tcs_prim_mode) {
2812 case PIPE_PRIM_LINES:
2813 stride = 8; /* 2 dwords, 1 vec2 store */
2814 outer_comps = 2;
2815 inner_comps = 0;
2816 break;
2817 case PIPE_PRIM_TRIANGLES:
2818 stride = 16; /* 4 dwords, 1 vec4 store */
2819 outer_comps = 3;
2820 inner_comps = 1;
2821 treg[1] = r600_get_temp(ctx);
2822 break;
2823 case PIPE_PRIM_QUADS:
2824 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2825 outer_comps = 4;
2826 inner_comps = 2;
2827 treg[1] = r600_get_temp(ctx);
2828 treg[2] = r600_get_temp(ctx);
2829 break;
2830 default:
2831 assert(0);
2832 return -1;
2833 }
2834
2835 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2836 /* TF_WRITE takes index in R.x, value in R.y */
2837 for (i = 0; i < ctx->shader->noutput; i++) {
2838 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2839 tessinner_idx = i;
2840 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2841 tessouter_idx = i;
2842 }
2843
2844 if (tessouter_idx == -1)
2845 return -1;
2846
2847 if (tessinner_idx == -1 && inner_comps)
2848 return -1;
2849
2850 if (tessouter_idx != -1) {
2851 r = r600_tess_factor_read(ctx, tessouter_idx);
2852 if (r)
2853 return r;
2854 }
2855
2856 if (tessinner_idx != -1) {
2857 r = r600_tess_factor_read(ctx, tessinner_idx);
2858 if (r)
2859 return r;
2860 }
2861
2862 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2863 /* r.x = relpatchid(r0.y) * tf_stride */
2864
2865 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2866 /* add incoming r0.w to it: t.x = t.x + r0.w */
2867 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2868 temp_reg, 0,
2869 0, 1,
2870 V_SQ_ALU_SRC_LITERAL, stride,
2871 0, 3);
2872 if (r)
2873 return r;
2874
2875 for (i = 0; i < outer_comps + inner_comps; i++) {
2876 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2877 int out_comp = i >= outer_comps ? i - outer_comps : i;
2878
2879 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2880 treg[i / 2], (2 * (i % 2)),
2881 temp_reg, 0,
2882 V_SQ_ALU_SRC_LITERAL, 4 * i);
2883 if (r)
2884 return r;
2885 r = single_alu_op2(ctx, ALU_OP1_MOV,
2886 treg[i / 2], 1 + (2 * (i%2)),
2887 ctx->shader->output[out_idx].gpr, out_comp,
2888 0, 0);
2889 if (r)
2890 return r;
2891 }
2892 for (i = 0; i < outer_comps + inner_comps; i++) {
2893 struct r600_bytecode_gds gds;
2894
2895 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2896 gds.src_gpr = treg[i / 2];
2897 gds.src_sel_x = 2 * (i % 2);
2898 gds.src_sel_y = 1 + (2 * (i % 2));
2899 gds.src_sel_z = 4;
2900 gds.dst_sel_x = 7;
2901 gds.dst_sel_y = 7;
2902 gds.dst_sel_z = 7;
2903 gds.dst_sel_w = 7;
2904 gds.op = FETCH_OP_TF_WRITE;
2905 r = r600_bytecode_add_gds(ctx->bc, &gds);
2906 if (r)
2907 return r;
2908 }
2909
2910 // Patch up jump label
2911 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2912 cf_pop = ctx->bc->cf_last;
2913
2914 cf_jump->cf_addr = cf_pop->id + 2;
2915 cf_jump->pop_count = 1;
2916 cf_pop->cf_addr = cf_pop->id + 2;
2917 cf_pop->pop_count = 1;
2918
2919 return 0;
2920 }
2921
2922 static int r600_shader_from_tgsi(struct r600_context *rctx,
2923 struct r600_pipe_shader *pipeshader,
2924 union r600_shader_key key)
2925 {
2926 struct r600_screen *rscreen = rctx->screen;
2927 struct r600_shader *shader = &pipeshader->shader;
2928 struct tgsi_token *tokens = pipeshader->selector->tokens;
2929 struct pipe_stream_output_info so = pipeshader->selector->so;
2930 struct tgsi_full_immediate *immediate;
2931 struct r600_shader_ctx ctx;
2932 struct r600_bytecode_output output[32];
2933 unsigned output_done, noutput;
2934 unsigned opcode;
2935 int i, j, k, r = 0;
2936 int next_param_base = 0, next_clip_base;
2937 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2938 /* Declarations used by llvm code */
2939 bool use_llvm = false;
2940 bool indirect_gprs;
2941 bool ring_outputs = false;
2942 bool lds_outputs = false;
2943 bool lds_inputs = false;
2944 bool pos_emitted = false;
2945
2946 #ifdef R600_USE_LLVM
2947 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
2948 #endif
2949 ctx.bc = &shader->bc;
2950 ctx.shader = shader;
2951 ctx.native_integers = true;
2952
2953
2954 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2955 rscreen->has_compressed_msaa_texturing);
2956 ctx.tokens = tokens;
2957 tgsi_scan_shader(tokens, &ctx.info);
2958 shader->indirect_files = ctx.info.indirect_files;
2959
2960 shader->uses_doubles = ctx.info.uses_doubles;
2961
2962 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2963 tgsi_parse_init(&ctx.parse, tokens);
2964 ctx.type = ctx.info.processor;
2965 shader->processor_type = ctx.type;
2966 ctx.bc->type = shader->processor_type;
2967
2968 switch (ctx.type) {
2969 case TGSI_PROCESSOR_VERTEX:
2970 shader->vs_as_gs_a = key.vs.as_gs_a;
2971 shader->vs_as_es = key.vs.as_es;
2972 shader->vs_as_ls = key.vs.as_ls;
2973 if (shader->vs_as_es)
2974 ring_outputs = true;
2975 if (shader->vs_as_ls)
2976 lds_outputs = true;
2977 break;
2978 case TGSI_PROCESSOR_GEOMETRY:
2979 ring_outputs = true;
2980 break;
2981 case TGSI_PROCESSOR_TESS_CTRL:
2982 shader->tcs_prim_mode = key.tcs.prim_mode;
2983 lds_outputs = true;
2984 lds_inputs = true;
2985 break;
2986 case TGSI_PROCESSOR_TESS_EVAL:
2987 shader->tes_as_es = key.tes.as_es;
2988 lds_inputs = true;
2989 if (shader->tes_as_es)
2990 ring_outputs = true;
2991 break;
2992 case TGSI_PROCESSOR_FRAGMENT:
2993 shader->two_side = key.ps.color_two_side;
2994 break;
2995 default:
2996 break;
2997 }
2998
2999 if (shader->vs_as_es || shader->tes_as_es) {
3000 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3001 } else {
3002 ctx.gs_for_vs = NULL;
3003 }
3004
3005 ctx.next_ring_offset = 0;
3006 ctx.gs_out_ring_offset = 0;
3007 ctx.gs_next_vertex = 0;
3008 ctx.gs_stream_output_info = &so;
3009
3010 ctx.face_gpr = -1;
3011 ctx.fixed_pt_position_gpr = -1;
3012 ctx.fragcoord_input = -1;
3013 ctx.colors_used = 0;
3014 ctx.clip_vertex_write = 0;
3015
3016 shader->nr_ps_color_exports = 0;
3017 shader->nr_ps_max_color_exports = 0;
3018
3019
3020 /* register allocations */
3021 /* Values [0,127] correspond to GPR[0..127].
3022 * Values [128,159] correspond to constant buffer bank 0
3023 * Values [160,191] correspond to constant buffer bank 1
3024 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3025 * Values [256,287] correspond to constant buffer bank 2 (EG)
3026 * Values [288,319] correspond to constant buffer bank 3 (EG)
3027 * Other special values are shown in the list below.
3028 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3029 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3030 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3031 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3032 * 248 SQ_ALU_SRC_0: special constant 0.0.
3033 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3034 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3035 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3036 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3037 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3038 * 254 SQ_ALU_SRC_PV: previous vector result.
3039 * 255 SQ_ALU_SRC_PS: previous scalar result.
3040 */
3041 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3042 ctx.file_offset[i] = 0;
3043 }
3044
3045 #ifdef R600_USE_LLVM
3046 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
3047 fprintf(stderr, "Warning: R600 LLVM backend does not support "
3048 "indirect adressing. Falling back to TGSI "
3049 "backend.\n");
3050 use_llvm = 0;
3051 }
3052 #endif
3053 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
3054 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3055 if (!use_llvm) {
3056 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3057 }
3058 }
3059 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
3060 if (ctx.bc->chip_class >= EVERGREEN)
3061 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3062 else
3063 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3064 }
3065 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3066 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3067 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3068 }
3069 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
3070 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3071 if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) {
3072 bool add_tesscoord = false, add_tess_inout = false;
3073 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3074 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3075 /* if we have tesscoord save one reg */
3076 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3077 add_tesscoord = true;
3078 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3079 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3080 add_tess_inout = true;
3081 }
3082 if (add_tesscoord || add_tess_inout)
3083 ctx.file_offset[TGSI_FILE_INPUT]++;
3084 if (add_tess_inout)
3085 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3086 }
3087 ctx.use_llvm = use_llvm;
3088
3089 if (use_llvm) {
3090 ctx.file_offset[TGSI_FILE_OUTPUT] =
3091 ctx.file_offset[TGSI_FILE_INPUT];
3092 } else {
3093 ctx.file_offset[TGSI_FILE_OUTPUT] =
3094 ctx.file_offset[TGSI_FILE_INPUT] +
3095 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3096 }
3097 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3098 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3099
3100 /* Outside the GPR range. This will be translated to one of the
3101 * kcache banks later. */
3102 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3103
3104 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3105 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3106 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3107 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3108 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3109
3110 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
3111 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3112 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3113 ctx.temp_reg = ctx.bc->ar_reg + 5;
3114 } else if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) {
3115 ctx.tess_input_info = 0;
3116 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3117 ctx.temp_reg = ctx.bc->ar_reg + 4;
3118 } else if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3119 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3120 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3121 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3122 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3123 ctx.temp_reg = ctx.bc->ar_reg + 7;
3124 } else {
3125 ctx.temp_reg = ctx.bc->ar_reg + 3;
3126 }
3127
3128 shader->max_arrays = 0;
3129 shader->num_arrays = 0;
3130 if (indirect_gprs) {
3131
3132 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3133 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3134 ctx.file_offset[TGSI_FILE_OUTPUT] -
3135 ctx.file_offset[TGSI_FILE_INPUT],
3136 0x0F);
3137 }
3138 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3139 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3140 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3141 ctx.file_offset[TGSI_FILE_OUTPUT],
3142 0x0F);
3143 }
3144 }
3145
3146 ctx.nliterals = 0;
3147 ctx.literals = NULL;
3148
3149 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3150 ctx.info.colors_written == 1;
3151 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3152 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3153
3154 if (shader->vs_as_gs_a)
3155 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3156
3157 if (ctx.type == TGSI_PROCESSOR_TESS_EVAL)
3158 r600_fetch_tess_io_info(&ctx);
3159
3160 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3161 tgsi_parse_token(&ctx.parse);
3162 switch (ctx.parse.FullToken.Token.Type) {
3163 case TGSI_TOKEN_TYPE_IMMEDIATE:
3164 immediate = &ctx.parse.FullToken.FullImmediate;
3165 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3166 if(ctx.literals == NULL) {
3167 r = -ENOMEM;
3168 goto out_err;
3169 }
3170 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3171 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3172 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3173 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3174 ctx.nliterals++;
3175 break;
3176 case TGSI_TOKEN_TYPE_DECLARATION:
3177 r = tgsi_declaration(&ctx);
3178 if (r)
3179 goto out_err;
3180 break;
3181 case TGSI_TOKEN_TYPE_INSTRUCTION:
3182 case TGSI_TOKEN_TYPE_PROPERTY:
3183 break;
3184 default:
3185 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3186 r = -EINVAL;
3187 goto out_err;
3188 }
3189 }
3190
3191 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3192 shader->ring_item_sizes[1] = 0;
3193 shader->ring_item_sizes[2] = 0;
3194 shader->ring_item_sizes[3] = 0;
3195
3196 /* Process two side if needed */
3197 if (shader->two_side && ctx.colors_used) {
3198 int i, count = ctx.shader->ninput;
3199 unsigned next_lds_loc = ctx.shader->nlds;
3200
3201 /* additional inputs will be allocated right after the existing inputs,
3202 * we won't need them after the color selection, so we don't need to
3203 * reserve these gprs for the rest of the shader code and to adjust
3204 * output offsets etc. */
3205 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3206 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3207
3208 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3209 if (ctx.face_gpr == -1) {
3210 i = ctx.shader->ninput++;
3211 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3212 ctx.shader->input[i].spi_sid = 0;
3213 ctx.shader->input[i].gpr = gpr++;
3214 ctx.face_gpr = ctx.shader->input[i].gpr;
3215 }
3216
3217 for (i = 0; i < count; i++) {
3218 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3219 int ni = ctx.shader->ninput++;
3220 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3221 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3222 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3223 ctx.shader->input[ni].gpr = gpr++;
3224 // TGSI to LLVM needs to know the lds position of inputs.
3225 // Non LLVM path computes it later (in process_twoside_color)
3226 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3227 ctx.shader->input[i].back_color_input = ni;
3228 if (ctx.bc->chip_class >= EVERGREEN) {
3229 if ((r = evergreen_interp_input(&ctx, ni)))
3230 return r;
3231 }
3232 }
3233 }
3234 }
3235
3236 /* LLVM backend setup */
3237 #ifdef R600_USE_LLVM
3238 if (use_llvm) {
3239 struct radeon_llvm_context radeon_llvm_ctx;
3240 LLVMModuleRef mod;
3241 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
3242 boolean use_kill = false;
3243
3244 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
3245 radeon_llvm_ctx.type = ctx.type;
3246 radeon_llvm_ctx.two_side = shader->two_side;
3247 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
3248 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
3249 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
3250 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
3251 radeon_llvm_ctx.color_buffer_count = max_color_exports;
3252 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
3253 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
3254 radeon_llvm_ctx.stream_outputs = &so;
3255 radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
3256 radeon_llvm_ctx.has_compressed_msaa_texturing =
3257 ctx.bc->has_compressed_msaa_texturing;
3258 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
3259 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
3260 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
3261
3262 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill,
3263 dump, &rctx->b.debug)) {
3264 radeon_llvm_dispose(&radeon_llvm_ctx);
3265 use_llvm = 0;
3266 fprintf(stderr, "R600 LLVM backend failed to compile "
3267 "shader. Falling back to TGSI\n");
3268 } else {
3269 ctx.file_offset[TGSI_FILE_OUTPUT] =
3270 ctx.file_offset[TGSI_FILE_INPUT];
3271 }
3272 if (use_kill)
3273 ctx.shader->uses_kill = use_kill;
3274 radeon_llvm_dispose(&radeon_llvm_ctx);
3275 }
3276 #endif
3277 /* End of LLVM backend setup */
3278
3279 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3280 shader->nr_ps_max_color_exports = 8;
3281
3282 if (!use_llvm) {
3283 if (ctx.fragcoord_input >= 0) {
3284 if (ctx.bc->chip_class == CAYMAN) {
3285 for (j = 0 ; j < 4; j++) {
3286 struct r600_bytecode_alu alu;
3287 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3288 alu.op = ALU_OP1_RECIP_IEEE;
3289 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3290 alu.src[0].chan = 3;
3291
3292 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3293 alu.dst.chan = j;
3294 alu.dst.write = (j == 3);
3295 alu.last = 1;
3296 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3297 return r;
3298 }
3299 } else {
3300 struct r600_bytecode_alu alu;
3301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3302 alu.op = ALU_OP1_RECIP_IEEE;
3303 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3304 alu.src[0].chan = 3;
3305
3306 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3307 alu.dst.chan = 3;
3308 alu.dst.write = 1;
3309 alu.last = 1;
3310 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3311 return r;
3312 }
3313 }
3314
3315 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3316 struct r600_bytecode_alu alu;
3317 int r;
3318
3319 /* GS thread with no output workaround - emit a cut at start of GS */
3320 if (ctx.bc->chip_class == R600)
3321 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3322
3323 for (j = 0; j < 4; j++) {
3324 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3325 alu.op = ALU_OP1_MOV;
3326 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3327 alu.src[0].value = 0;
3328 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3329 alu.dst.write = 1;
3330 alu.last = 1;
3331 r = r600_bytecode_add_alu(ctx.bc, &alu);
3332 if (r)
3333 return r;
3334 }
3335 }
3336
3337 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
3338 r600_fetch_tess_io_info(&ctx);
3339
3340 if (shader->two_side && ctx.colors_used) {
3341 if ((r = process_twoside_color_inputs(&ctx)))
3342 return r;
3343 }
3344
3345 tgsi_parse_init(&ctx.parse, tokens);
3346 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3347 tgsi_parse_token(&ctx.parse);
3348 switch (ctx.parse.FullToken.Token.Type) {
3349 case TGSI_TOKEN_TYPE_INSTRUCTION:
3350 r = tgsi_is_supported(&ctx);
3351 if (r)
3352 goto out_err;
3353 ctx.max_driver_temp_used = 0;
3354 /* reserve first tmp for everyone */
3355 r600_get_temp(&ctx);
3356
3357 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3358 if ((r = tgsi_split_constant(&ctx)))
3359 goto out_err;
3360 if ((r = tgsi_split_literal_constant(&ctx)))
3361 goto out_err;
3362 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3363 if ((r = tgsi_split_gs_inputs(&ctx)))
3364 goto out_err;
3365 } else if (lds_inputs) {
3366 if ((r = tgsi_split_lds_inputs(&ctx)))
3367 goto out_err;
3368 }
3369 if (ctx.bc->chip_class == CAYMAN)
3370 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3371 else if (ctx.bc->chip_class >= EVERGREEN)
3372 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3373 else
3374 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3375 r = ctx.inst_info->process(&ctx);
3376 if (r)
3377 goto out_err;
3378
3379 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
3380 r = r600_store_tcs_output(&ctx);
3381 if (r)
3382 goto out_err;
3383 }
3384 break;
3385 default:
3386 break;
3387 }
3388 }
3389 }
3390
3391 /* Reset the temporary register counter. */
3392 ctx.max_driver_temp_used = 0;
3393
3394 noutput = shader->noutput;
3395
3396 if (!ring_outputs && ctx.clip_vertex_write) {
3397 unsigned clipdist_temp[2];
3398
3399 clipdist_temp[0] = r600_get_temp(&ctx);
3400 clipdist_temp[1] = r600_get_temp(&ctx);
3401
3402 /* need to convert a clipvertex write into clipdistance writes and not export
3403 the clip vertex anymore */
3404
3405 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3406 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3407 shader->output[noutput].gpr = clipdist_temp[0];
3408 noutput++;
3409 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3410 shader->output[noutput].gpr = clipdist_temp[1];
3411 noutput++;
3412
3413 /* reset spi_sid for clipvertex output to avoid confusing spi */
3414 shader->output[ctx.cv_output].spi_sid = 0;
3415
3416 shader->clip_dist_write = 0xFF;
3417
3418 for (i = 0; i < 8; i++) {
3419 int oreg = i >> 2;
3420 int ochan = i & 3;
3421
3422 for (j = 0; j < 4; j++) {
3423 struct r600_bytecode_alu alu;
3424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3425 alu.op = ALU_OP2_DOT4;
3426 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3427 alu.src[0].chan = j;
3428
3429 alu.src[1].sel = 512 + i;
3430 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3431 alu.src[1].chan = j;
3432
3433 alu.dst.sel = clipdist_temp[oreg];
3434 alu.dst.chan = j;
3435 alu.dst.write = (j == ochan);
3436 if (j == 3)
3437 alu.last = 1;
3438 if (!use_llvm)
3439 r = r600_bytecode_add_alu(ctx.bc, &alu);
3440 if (r)
3441 return r;
3442 }
3443 }
3444 }
3445
3446 /* Add stream outputs. */
3447 if (!use_llvm && so.num_outputs) {
3448 bool emit = false;
3449 if (!lds_outputs && !ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX)
3450 emit = true;
3451 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_TESS_EVAL)
3452 emit = true;
3453 if (emit)
3454 emit_streamout(&ctx, &so, -1, NULL);
3455 }
3456 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3457 convert_edgeflag_to_int(&ctx);
3458
3459 if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
3460 r600_emit_tess_factor(&ctx);
3461
3462 if (lds_outputs) {
3463 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
3464 if (ctx.shader->noutput)
3465 emit_lds_vs_writes(&ctx);
3466 }
3467 } else if (ring_outputs) {
3468 if (shader->vs_as_es || shader->tes_as_es) {
3469 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3470 ctx.gs_export_gpr_tregs[1] = -1;
3471 ctx.gs_export_gpr_tregs[2] = -1;
3472 ctx.gs_export_gpr_tregs[3] = -1;
3473
3474 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3475 }
3476 } else {
3477 /* Export output */
3478 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3479
3480 for (i = 0, j = 0; i < noutput; i++, j++) {
3481 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3482 output[j].gpr = shader->output[i].gpr;
3483 output[j].elem_size = 3;
3484 output[j].swizzle_x = 0;
3485 output[j].swizzle_y = 1;
3486 output[j].swizzle_z = 2;
3487 output[j].swizzle_w = 3;
3488 output[j].burst_count = 1;
3489 output[j].type = -1;
3490 output[j].op = CF_OP_EXPORT;
3491 switch (ctx.type) {
3492 case TGSI_PROCESSOR_VERTEX:
3493 case TGSI_PROCESSOR_TESS_EVAL:
3494 switch (shader->output[i].name) {
3495 case TGSI_SEMANTIC_POSITION:
3496 output[j].array_base = 60;
3497 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3498 pos_emitted = true;
3499 break;
3500
3501 case TGSI_SEMANTIC_PSIZE:
3502 output[j].array_base = 61;
3503 output[j].swizzle_y = 7;
3504 output[j].swizzle_z = 7;
3505 output[j].swizzle_w = 7;
3506 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3507 pos_emitted = true;
3508 break;
3509 case TGSI_SEMANTIC_EDGEFLAG:
3510 output[j].array_base = 61;
3511 output[j].swizzle_x = 7;
3512 output[j].swizzle_y = 0;
3513 output[j].swizzle_z = 7;
3514 output[j].swizzle_w = 7;
3515 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3516 pos_emitted = true;
3517 break;
3518 case TGSI_SEMANTIC_LAYER:
3519 /* spi_sid is 0 for outputs that are
3520 * not consumed by PS */
3521 if (shader->output[i].spi_sid) {
3522 output[j].array_base = next_param_base++;
3523 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3524 j++;
3525 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3526 }
3527 output[j].array_base = 61;
3528 output[j].swizzle_x = 7;
3529 output[j].swizzle_y = 7;
3530 output[j].swizzle_z = 0;
3531 output[j].swizzle_w = 7;
3532 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3533 pos_emitted = true;
3534 break;
3535 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3536 /* spi_sid is 0 for outputs that are
3537 * not consumed by PS */
3538 if (shader->output[i].spi_sid) {
3539 output[j].array_base = next_param_base++;
3540 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3541 j++;
3542 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3543 }
3544 output[j].array_base = 61;
3545 output[j].swizzle_x = 7;
3546 output[j].swizzle_y = 7;
3547 output[j].swizzle_z = 7;
3548 output[j].swizzle_w = 0;
3549 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3550 pos_emitted = true;
3551 break;
3552 case TGSI_SEMANTIC_CLIPVERTEX:
3553 j--;
3554 break;
3555 case TGSI_SEMANTIC_CLIPDIST:
3556 output[j].array_base = next_clip_base++;
3557 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3558 pos_emitted = true;
3559 /* spi_sid is 0 for clipdistance outputs that were generated
3560 * for clipvertex - we don't need to pass them to PS */
3561 if (shader->output[i].spi_sid) {
3562 j++;
3563 /* duplicate it as PARAM to pass to the pixel shader */
3564 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3565 output[j].array_base = next_param_base++;
3566 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3567 }
3568 break;
3569 case TGSI_SEMANTIC_FOG:
3570 output[j].swizzle_y = 4; /* 0 */
3571 output[j].swizzle_z = 4; /* 0 */
3572 output[j].swizzle_w = 5; /* 1 */
3573 break;
3574 case TGSI_SEMANTIC_PRIMID:
3575 output[j].swizzle_x = 2;
3576 output[j].swizzle_y = 4; /* 0 */
3577 output[j].swizzle_z = 4; /* 0 */
3578 output[j].swizzle_w = 4; /* 0 */
3579 break;
3580 }
3581
3582 break;
3583 case TGSI_PROCESSOR_FRAGMENT:
3584 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3585 /* never export more colors than the number of CBs */
3586 if (shader->output[i].sid >= max_color_exports) {
3587 /* skip export */
3588 j--;
3589 continue;
3590 }
3591 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3592 output[j].array_base = shader->output[i].sid;
3593 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3594 shader->nr_ps_color_exports++;
3595 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3596 for (k = 1; k < max_color_exports; k++) {
3597 j++;
3598 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3599 output[j].gpr = shader->output[i].gpr;
3600 output[j].elem_size = 3;
3601 output[j].swizzle_x = 0;
3602 output[j].swizzle_y = 1;
3603 output[j].swizzle_z = 2;
3604 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3605 output[j].burst_count = 1;
3606 output[j].array_base = k;
3607 output[j].op = CF_OP_EXPORT;
3608 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3609 shader->nr_ps_color_exports++;
3610 }
3611 }
3612 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3613 output[j].array_base = 61;
3614 output[j].swizzle_x = 2;
3615 output[j].swizzle_y = 7;
3616 output[j].swizzle_z = output[j].swizzle_w = 7;
3617 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3618 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3619 output[j].array_base = 61;
3620 output[j].swizzle_x = 7;
3621 output[j].swizzle_y = 1;
3622 output[j].swizzle_z = output[j].swizzle_w = 7;
3623 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3624 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3625 output[j].array_base = 61;
3626 output[j].swizzle_x = 7;
3627 output[j].swizzle_y = 7;
3628 output[j].swizzle_z = 0;
3629 output[j].swizzle_w = 7;
3630 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3631 } else {
3632 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3633 r = -EINVAL;
3634 goto out_err;
3635 }
3636 break;
3637 case TGSI_PROCESSOR_TESS_CTRL:
3638 break;
3639 default:
3640 R600_ERR("unsupported processor type %d\n", ctx.type);
3641 r = -EINVAL;
3642 goto out_err;
3643 }
3644
3645 if (output[j].type==-1) {
3646 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3647 output[j].array_base = next_param_base++;
3648 }
3649 }
3650
3651 /* add fake position export */
3652 if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && pos_emitted == false) {
3653 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3654 output[j].gpr = 0;
3655 output[j].elem_size = 3;
3656 output[j].swizzle_x = 7;
3657 output[j].swizzle_y = 7;
3658 output[j].swizzle_z = 7;
3659 output[j].swizzle_w = 7;
3660 output[j].burst_count = 1;
3661 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3662 output[j].array_base = 60;
3663 output[j].op = CF_OP_EXPORT;
3664 j++;
3665 }
3666
3667 /* add fake param output for vertex shader if no param is exported */
3668 if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && next_param_base == 0) {
3669 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3670 output[j].gpr = 0;
3671 output[j].elem_size = 3;
3672 output[j].swizzle_x = 7;
3673 output[j].swizzle_y = 7;
3674 output[j].swizzle_z = 7;
3675 output[j].swizzle_w = 7;
3676 output[j].burst_count = 1;
3677 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3678 output[j].array_base = 0;
3679 output[j].op = CF_OP_EXPORT;
3680 j++;
3681 }
3682
3683 /* add fake pixel export */
3684 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
3685 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3686 output[j].gpr = 0;
3687 output[j].elem_size = 3;
3688 output[j].swizzle_x = 7;
3689 output[j].swizzle_y = 7;
3690 output[j].swizzle_z = 7;
3691 output[j].swizzle_w = 7;
3692 output[j].burst_count = 1;
3693 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3694 output[j].array_base = 0;
3695 output[j].op = CF_OP_EXPORT;
3696 j++;
3697 shader->nr_ps_color_exports++;
3698 }
3699
3700 noutput = j;
3701
3702 /* set export done on last export of each type */
3703 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3704 if (!(output_done & (1 << output[i].type))) {
3705 output_done |= (1 << output[i].type);
3706 output[i].op = CF_OP_EXPORT_DONE;
3707 }
3708 }
3709 /* add output to bytecode */
3710 if (!use_llvm) {
3711 for (i = 0; i < noutput; i++) {
3712 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3713 if (r)
3714 goto out_err;
3715 }
3716 }
3717 }
3718
3719 /* add program end */
3720 if (!use_llvm) {
3721 if (ctx.bc->chip_class == CAYMAN)
3722 cm_bytecode_add_cf_end(ctx.bc);
3723 else {
3724 const struct cf_op_info *last = NULL;
3725
3726 if (ctx.bc->cf_last)
3727 last = r600_isa_cf(ctx.bc->cf_last->op);
3728
3729 /* alu clause instructions don't have EOP bit, so add NOP */
3730 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3731 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3732
3733 ctx.bc->cf_last->end_of_program = 1;
3734 }
3735 }
3736
3737 /* check GPR limit - we have 124 = 128 - 4
3738 * (4 are reserved as alu clause temporary registers) */
3739 if (ctx.bc->ngpr > 124) {
3740 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3741 r = -ENOMEM;
3742 goto out_err;
3743 }
3744
3745 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
3746 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3747 return r;
3748 }
3749
3750 free(ctx.literals);
3751 tgsi_parse_free(&ctx.parse);
3752 return 0;
3753 out_err:
3754 free(ctx.literals);
3755 tgsi_parse_free(&ctx.parse);
3756 return r;
3757 }
3758
3759 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3760 {
3761 const unsigned tgsi_opcode =
3762 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3763 R600_ERR("%s tgsi opcode unsupported\n",
3764 tgsi_get_opcode_name(tgsi_opcode));
3765 return -EINVAL;
3766 }
3767
3768 static int tgsi_end(struct r600_shader_ctx *ctx)
3769 {
3770 return 0;
3771 }
3772
3773 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3774 const struct r600_shader_src *shader_src,
3775 unsigned chan)
3776 {
3777 bc_src->sel = shader_src->sel;
3778 bc_src->chan = shader_src->swizzle[chan];
3779 bc_src->neg = shader_src->neg;
3780 bc_src->abs = shader_src->abs;
3781 bc_src->rel = shader_src->rel;
3782 bc_src->value = shader_src->value[bc_src->chan];
3783 bc_src->kc_bank = shader_src->kc_bank;
3784 bc_src->kc_rel = shader_src->kc_rel;
3785 }
3786
3787 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3788 {
3789 bc_src->abs = 1;
3790 bc_src->neg = 0;
3791 }
3792
3793 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3794 {
3795 bc_src->neg = !bc_src->neg;
3796 }
3797
3798 static void tgsi_dst(struct r600_shader_ctx *ctx,
3799 const struct tgsi_full_dst_register *tgsi_dst,
3800 unsigned swizzle,
3801 struct r600_bytecode_alu_dst *r600_dst)
3802 {
3803 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3804
3805 r600_dst->sel = tgsi_dst->Register.Index;
3806 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3807 r600_dst->chan = swizzle;
3808 r600_dst->write = 1;
3809 if (inst->Instruction.Saturate) {
3810 r600_dst->clamp = 1;
3811 }
3812 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
3813 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3814 return;
3815 }
3816 }
3817 if (tgsi_dst->Register.Indirect)
3818 r600_dst->rel = V_SQ_REL_RELATIVE;
3819
3820 }
3821
3822 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3823 {
3824 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3825 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3826 struct r600_bytecode_alu alu;
3827 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3828 int use_tmp = 0;
3829
3830 if (singledest) {
3831 switch (write_mask) {
3832 case 0x1:
3833 write_mask = 0x3;
3834 break;
3835 case 0x2:
3836 use_tmp = 1;
3837 write_mask = 0x3;
3838 break;
3839 case 0x4:
3840 write_mask = 0xc;
3841 break;
3842 case 0x8:
3843 write_mask = 0xc;
3844 use_tmp = 3;
3845 break;
3846 }
3847 }
3848
3849 lasti = tgsi_last_instruction(write_mask);
3850 for (i = 0; i <= lasti; i++) {
3851
3852 if (!(write_mask & (1 << i)))
3853 continue;
3854
3855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3856
3857 if (singledest) {
3858 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3859 if (use_tmp) {
3860 alu.dst.sel = ctx->temp_reg;
3861 alu.dst.chan = i;
3862 alu.dst.write = 1;
3863 }
3864 if (i == 1 || i == 3)
3865 alu.dst.write = 0;
3866 } else
3867 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3868
3869 alu.op = ctx->inst_info->op;
3870 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3871 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3872 } else if (!swap) {
3873 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3874 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3875 }
3876 } else {
3877 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3878 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3879 }
3880
3881 /* handle some special cases */
3882 if (i == 1 || i == 3) {
3883 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3884 case TGSI_OPCODE_SUB:
3885 r600_bytecode_src_toggle_neg(&alu.src[1]);
3886 break;
3887 case TGSI_OPCODE_DABS:
3888 r600_bytecode_src_set_abs(&alu.src[0]);
3889 break;
3890 default:
3891 break;
3892 }
3893 }
3894 if (i == lasti) {
3895 alu.last = 1;
3896 }
3897 r = r600_bytecode_add_alu(ctx->bc, &alu);
3898 if (r)
3899 return r;
3900 }
3901
3902 if (use_tmp) {
3903 write_mask = inst->Dst[0].Register.WriteMask;
3904
3905 /* move result from temp to dst */
3906 for (i = 0; i <= lasti; i++) {
3907 if (!(write_mask & (1 << i)))
3908 continue;
3909
3910 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3911 alu.op = ALU_OP1_MOV;
3912 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3913 alu.src[0].sel = ctx->temp_reg;
3914 alu.src[0].chan = use_tmp - 1;
3915 alu.last = (i == lasti);
3916
3917 r = r600_bytecode_add_alu(ctx->bc, &alu);
3918 if (r)
3919 return r;
3920 }
3921 }
3922 return 0;
3923 }
3924
3925 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3926 {
3927 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3928 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3929 /* confirm writemasking */
3930 if ((write_mask & 0x3) != 0x3 &&
3931 (write_mask & 0xc) != 0xc) {
3932 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3933 return -1;
3934 }
3935 return tgsi_op2_64_params(ctx, false, false);
3936 }
3937
3938 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
3939 {
3940 return tgsi_op2_64_params(ctx, true, false);
3941 }
3942
3943 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
3944 {
3945 return tgsi_op2_64_params(ctx, true, true);
3946 }
3947
3948 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3949 {
3950 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3951 struct r600_bytecode_alu alu;
3952 int i, j, r;
3953 int lasti = 3;
3954 int tmp = r600_get_temp(ctx);
3955
3956 for (i = 0; i < lasti + 1; i++) {
3957
3958 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3959 alu.op = ctx->inst_info->op;
3960 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3961 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3962 }
3963
3964 if (inst->Dst[0].Register.WriteMask & (1 << i))
3965 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3966 else
3967 alu.dst.sel = tmp;
3968
3969 alu.dst.chan = i;
3970 alu.is_op3 = 1;
3971 if (i == lasti) {
3972 alu.last = 1;
3973 }
3974 r = r600_bytecode_add_alu(ctx->bc, &alu);
3975 if (r)
3976 return r;
3977 }
3978 return 0;
3979 }
3980
3981 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3982 {
3983 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3984 struct r600_bytecode_alu alu;
3985 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3986 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3987 /* use temp register if trans_only and more than one dst component */
3988 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3989
3990 for (i = 0; i <= lasti; i++) {
3991 if (!(write_mask & (1 << i)))
3992 continue;
3993
3994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3995 if (use_tmp) {
3996 alu.dst.sel = ctx->temp_reg;
3997 alu.dst.chan = i;
3998 alu.dst.write = 1;
3999 } else
4000 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4001
4002 alu.op = ctx->inst_info->op;
4003 if (!swap) {
4004 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4005 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4006 }
4007 } else {
4008 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4009 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4010 }
4011 /* handle some special cases */
4012 switch (inst->Instruction.Opcode) {
4013 case TGSI_OPCODE_SUB:
4014 r600_bytecode_src_toggle_neg(&alu.src[1]);
4015 break;
4016 case TGSI_OPCODE_ABS:
4017 r600_bytecode_src_set_abs(&alu.src[0]);
4018 break;
4019 default:
4020 break;
4021 }
4022 if (i == lasti || trans_only) {
4023 alu.last = 1;
4024 }
4025 r = r600_bytecode_add_alu(ctx->bc, &alu);
4026 if (r)
4027 return r;
4028 }
4029
4030 if (use_tmp) {
4031 /* move result from temp to dst */
4032 for (i = 0; i <= lasti; i++) {
4033 if (!(write_mask & (1 << i)))
4034 continue;
4035
4036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4037 alu.op = ALU_OP1_MOV;
4038 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4039 alu.src[0].sel = ctx->temp_reg;
4040 alu.src[0].chan = i;
4041 alu.last = (i == lasti);
4042
4043 r = r600_bytecode_add_alu(ctx->bc, &alu);
4044 if (r)
4045 return r;
4046 }
4047 }
4048 return 0;
4049 }
4050
4051 static int tgsi_op2(struct r600_shader_ctx *ctx)
4052 {
4053 return tgsi_op2_s(ctx, 0, 0);
4054 }
4055
4056 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4057 {
4058 return tgsi_op2_s(ctx, 1, 0);
4059 }
4060
4061 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4062 {
4063 return tgsi_op2_s(ctx, 0, 1);
4064 }
4065
4066 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4067 {
4068 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4069 struct r600_bytecode_alu alu;
4070 int i, r;
4071 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4072
4073 for (i = 0; i < lasti + 1; i++) {
4074
4075 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4076 continue;
4077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4078 alu.op = ctx->inst_info->op;
4079
4080 alu.src[0].sel = V_SQ_ALU_SRC_0;
4081
4082 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4083
4084 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4085
4086 if (i == lasti) {
4087 alu.last = 1;
4088 }
4089 r = r600_bytecode_add_alu(ctx->bc, &alu);
4090 if (r)
4091 return r;
4092 }
4093 return 0;
4094
4095 }
4096
4097 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4098 {
4099 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4100 struct r600_bytecode_alu alu;
4101 int i, r;
4102 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4103
4104 for (i = 0; i < lasti + 1; i++) {
4105
4106 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4107 continue;
4108 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4109 alu.op = ALU_OP1_MOV;
4110
4111 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4112
4113 if (i == 1 || i == 3)
4114 r600_bytecode_src_toggle_neg(&alu.src[0]);
4115 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4116
4117 if (i == lasti) {
4118 alu.last = 1;
4119 }
4120 r = r600_bytecode_add_alu(ctx->bc, &alu);
4121 if (r)
4122 return r;
4123 }
4124 return 0;
4125
4126 }
4127
4128 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4129 {
4130 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4131 struct r600_bytecode_alu alu;
4132 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4133 int i, j, r;
4134 int firsti = write_mask == 0xc ? 2 : 0;
4135
4136 for (i = 0; i <= 3; i++) {
4137 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4138 alu.op = ctx->inst_info->op;
4139
4140 alu.dst.sel = ctx->temp_reg;
4141 alu.dst.chan = i;
4142 alu.dst.write = 1;
4143 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4144 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4145 }
4146
4147 if (i == 3)
4148 alu.last = 1;
4149
4150 r = r600_bytecode_add_alu(ctx->bc, &alu);
4151 if (r)
4152 return r;
4153 }
4154
4155 /* MOV first two channels to writemask dst0 */
4156 for (i = 0; i <= 1; i++) {
4157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4158 alu.op = ALU_OP1_MOV;
4159 alu.src[0].chan = i + 2;
4160 alu.src[0].sel = ctx->temp_reg;
4161
4162 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
4163 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
4164 alu.last = 1;
4165 r = r600_bytecode_add_alu(ctx->bc, &alu);
4166 if (r)
4167 return r;
4168 }
4169
4170 for (i = 0; i <= 3; i++) {
4171 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4172 /* MOV third channels to writemask dst1 */
4173 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4174 alu.op = ALU_OP1_MOV;
4175 alu.src[0].chan = 1;
4176 alu.src[0].sel = ctx->temp_reg;
4177
4178 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4179 alu.last = 1;
4180 r = r600_bytecode_add_alu(ctx->bc, &alu);
4181 if (r)
4182 return r;
4183 break;
4184 }
4185 }
4186 return 0;
4187 }
4188
4189
4190 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4191 {
4192 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4193 struct r600_bytecode_alu alu;
4194 int i, r;
4195 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4196
4197 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4198 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4199
4200 for (i = 0; i <= (lasti+1)/2; i++) {
4201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4202 alu.op = ctx->inst_info->op;
4203
4204 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4205 alu.dst.sel = ctx->temp_reg;
4206 alu.dst.chan = i;
4207 alu.dst.write = 1;
4208 alu.last = 1;
4209
4210 r = r600_bytecode_add_alu(ctx->bc, &alu);
4211 if (r)
4212 return r;
4213 }
4214
4215 for (i = 0; i <= lasti; i++) {
4216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4217 alu.op = ALU_OP1_FLT32_TO_FLT64;
4218
4219 alu.src[0].chan = i/2;
4220 if (i%2 == 0)
4221 alu.src[0].sel = ctx->temp_reg;
4222 else {
4223 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4224 alu.src[0].value = 0x0;
4225 }
4226 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4227 alu.last = i == lasti;
4228
4229 r = r600_bytecode_add_alu(ctx->bc, &alu);
4230 if (r)
4231 return r;
4232 }
4233
4234 return 0;
4235 }
4236
4237 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4238 {
4239 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4240 struct r600_bytecode_alu alu;
4241 int i, r;
4242 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4243
4244 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4245 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4246
4247 for (i = 0; i <= lasti; i++) {
4248 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4249 alu.op = ALU_OP1_FLT64_TO_FLT32;
4250
4251 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4252 alu.dst.chan = i;
4253 alu.dst.sel = ctx->temp_reg;
4254 alu.dst.write = i%2 == 0;
4255 alu.last = i == lasti;
4256
4257 r = r600_bytecode_add_alu(ctx->bc, &alu);
4258 if (r)
4259 return r;
4260 }
4261
4262 for (i = 0; i <= (lasti+1)/2; i++) {
4263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4264 alu.op = ctx->inst_info->op;
4265
4266 alu.src[0].chan = i*2;
4267 alu.src[0].sel = ctx->temp_reg;
4268 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4269 alu.last = 1;
4270
4271 r = r600_bytecode_add_alu(ctx->bc, &alu);
4272 if (r)
4273 return r;
4274 }
4275
4276 return 0;
4277 }
4278
4279 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4280 {
4281 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4282 int i, r;
4283 struct r600_bytecode_alu alu;
4284 int last_slot = 3;
4285 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4286 int t1 = ctx->temp_reg;
4287
4288 /* these have to write the result to X/Y by the looks of it */
4289 for (i = 0 ; i < last_slot; i++) {
4290 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4291 alu.op = ctx->inst_info->op;
4292
4293 /* should only be one src regs */
4294 assert (inst->Instruction.NumSrcRegs == 1);
4295
4296 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4297 r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
4298
4299 /* RSQ should take the absolute value of src */
4300 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4301 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT) {
4302 r600_bytecode_src_set_abs(&alu.src[1]);
4303 }
4304 alu.dst.sel = t1;
4305 alu.dst.chan = i;
4306 alu.dst.write = (i == 0 || i == 1);
4307
4308 if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
4309 alu.last = 1;
4310 r = r600_bytecode_add_alu(ctx->bc, &alu);
4311 if (r)
4312 return r;
4313 }
4314
4315 for (i = 0 ; i <= lasti; i++) {
4316 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4317 continue;
4318 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4319 alu.op = ALU_OP1_MOV;
4320 alu.src[0].sel = t1;
4321 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4322 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4323 alu.dst.write = 1;
4324 if (i == lasti)
4325 alu.last = 1;
4326 r = r600_bytecode_add_alu(ctx->bc, &alu);
4327 if (r)
4328 return r;
4329 }
4330 return 0;
4331 }
4332
4333 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4334 {
4335 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4336 int i, j, r;
4337 struct r600_bytecode_alu alu;
4338 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4339
4340 for (i = 0 ; i < last_slot; i++) {
4341 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4342 alu.op = ctx->inst_info->op;
4343 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4344 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4345
4346 /* RSQ should take the absolute value of src */
4347 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4348 r600_bytecode_src_set_abs(&alu.src[j]);
4349 }
4350 }
4351 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4352 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4353
4354 if (i == last_slot - 1)
4355 alu.last = 1;
4356 r = r600_bytecode_add_alu(ctx->bc, &alu);
4357 if (r)
4358 return r;
4359 }
4360 return 0;
4361 }
4362
4363 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4364 {
4365 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4366 int i, j, k, r;
4367 struct r600_bytecode_alu alu;
4368 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4369 int t1 = ctx->temp_reg;
4370
4371 for (k = 0; k <= lasti; k++) {
4372 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4373 continue;
4374
4375 for (i = 0 ; i < 4; i++) {
4376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4377 alu.op = ctx->inst_info->op;
4378 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4379 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4380 }
4381 alu.dst.sel = t1;
4382 alu.dst.chan = i;
4383 alu.dst.write = (i == k);
4384 if (i == 3)
4385 alu.last = 1;
4386 r = r600_bytecode_add_alu(ctx->bc, &alu);
4387 if (r)
4388 return r;
4389 }
4390 }
4391
4392 for (i = 0 ; i <= lasti; i++) {
4393 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4394 continue;
4395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4396 alu.op = ALU_OP1_MOV;
4397 alu.src[0].sel = t1;
4398 alu.src[0].chan = i;
4399 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4400 alu.dst.write = 1;
4401 if (i == lasti)
4402 alu.last = 1;
4403 r = r600_bytecode_add_alu(ctx->bc, &alu);
4404 if (r)
4405 return r;
4406 }
4407
4408 return 0;
4409 }
4410
4411
4412 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4413 {
4414 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4415 int i, j, k, r;
4416 struct r600_bytecode_alu alu;
4417 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4418 int t1 = ctx->temp_reg;
4419
4420 for (k = 0; k < 2; k++) {
4421 if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2))))
4422 continue;
4423
4424 for (i = 0; i < 4; i++) {
4425 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4426 alu.op = ctx->inst_info->op;
4427 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4428 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));;
4429 }
4430 alu.dst.sel = t1;
4431 alu.dst.chan = i;
4432 alu.dst.write = 1;
4433 if (i == 3)
4434 alu.last = 1;
4435 r = r600_bytecode_add_alu(ctx->bc, &alu);
4436 if (r)
4437 return r;
4438 }
4439 }
4440
4441 for (i = 0; i <= lasti; i++) {
4442 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4443 continue;
4444 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4445 alu.op = ALU_OP1_MOV;
4446 alu.src[0].sel = t1;
4447 alu.src[0].chan = i;
4448 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4449 alu.dst.write = 1;
4450 if (i == lasti)
4451 alu.last = 1;
4452 r = r600_bytecode_add_alu(ctx->bc, &alu);
4453 if (r)
4454 return r;
4455 }
4456
4457 return 0;
4458 }
4459
4460 /*
4461 * r600 - trunc to -PI..PI range
4462 * r700 - normalize by dividing by 2PI
4463 * see fdo bug 27901
4464 */
4465 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4466 {
4467 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
4468 static float double_pi = 3.1415926535 * 2;
4469 static float neg_pi = -3.1415926535;
4470
4471 int r;
4472 struct r600_bytecode_alu alu;
4473
4474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4475 alu.op = ALU_OP3_MULADD;
4476 alu.is_op3 = 1;
4477
4478 alu.dst.chan = 0;
4479 alu.dst.sel = ctx->temp_reg;
4480 alu.dst.write = 1;
4481
4482 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4483
4484 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4485 alu.src[1].chan = 0;
4486 alu.src[1].value = *(uint32_t *)&half_inv_pi;
4487 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4488 alu.src[2].chan = 0;
4489 alu.last = 1;
4490 r = r600_bytecode_add_alu(ctx->bc, &alu);
4491 if (r)
4492 return r;
4493
4494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4495 alu.op = ALU_OP1_FRACT;
4496
4497 alu.dst.chan = 0;
4498 alu.dst.sel = ctx->temp_reg;
4499 alu.dst.write = 1;
4500
4501 alu.src[0].sel = ctx->temp_reg;
4502 alu.src[0].chan = 0;
4503 alu.last = 1;
4504 r = r600_bytecode_add_alu(ctx->bc, &alu);
4505 if (r)
4506 return r;
4507
4508 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4509 alu.op = ALU_OP3_MULADD;
4510 alu.is_op3 = 1;
4511
4512 alu.dst.chan = 0;
4513 alu.dst.sel = ctx->temp_reg;
4514 alu.dst.write = 1;
4515
4516 alu.src[0].sel = ctx->temp_reg;
4517 alu.src[0].chan = 0;
4518
4519 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4520 alu.src[1].chan = 0;
4521 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4522 alu.src[2].chan = 0;
4523
4524 if (ctx->bc->chip_class == R600) {
4525 alu.src[1].value = *(uint32_t *)&double_pi;
4526 alu.src[2].value = *(uint32_t *)&neg_pi;
4527 } else {
4528 alu.src[1].sel = V_SQ_ALU_SRC_1;
4529 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4530 alu.src[2].neg = 1;
4531 }
4532
4533 alu.last = 1;
4534 r = r600_bytecode_add_alu(ctx->bc, &alu);
4535 if (r)
4536 return r;
4537 return 0;
4538 }
4539
4540 static int cayman_trig(struct r600_shader_ctx *ctx)
4541 {
4542 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4543 struct r600_bytecode_alu alu;
4544 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4545 int i, r;
4546
4547 r = tgsi_setup_trig(ctx);
4548 if (r)
4549 return r;
4550
4551
4552 for (i = 0; i < last_slot; i++) {
4553 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4554 alu.op = ctx->inst_info->op;
4555 alu.dst.chan = i;
4556
4557 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4558 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4559
4560 alu.src[0].sel = ctx->temp_reg;
4561 alu.src[0].chan = 0;
4562 if (i == last_slot - 1)
4563 alu.last = 1;
4564 r = r600_bytecode_add_alu(ctx->bc, &alu);
4565 if (r)
4566 return r;
4567 }
4568 return 0;
4569 }
4570
4571 static int tgsi_trig(struct r600_shader_ctx *ctx)
4572 {
4573 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4574 struct r600_bytecode_alu alu;
4575 int i, r;
4576 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4577
4578 r = tgsi_setup_trig(ctx);
4579 if (r)
4580 return r;
4581
4582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4583 alu.op = ctx->inst_info->op;
4584 alu.dst.chan = 0;
4585 alu.dst.sel = ctx->temp_reg;
4586 alu.dst.write = 1;
4587
4588 alu.src[0].sel = ctx->temp_reg;
4589 alu.src[0].chan = 0;
4590 alu.last = 1;
4591 r = r600_bytecode_add_alu(ctx->bc, &alu);
4592 if (r)
4593 return r;
4594
4595 /* replicate result */
4596 for (i = 0; i < lasti + 1; i++) {
4597 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4598 continue;
4599
4600 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4601 alu.op = ALU_OP1_MOV;
4602
4603 alu.src[0].sel = ctx->temp_reg;
4604 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4605 if (i == lasti)
4606 alu.last = 1;
4607 r = r600_bytecode_add_alu(ctx->bc, &alu);
4608 if (r)
4609 return r;
4610 }
4611 return 0;
4612 }
4613
4614 static int tgsi_scs(struct r600_shader_ctx *ctx)
4615 {
4616 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4617 struct r600_bytecode_alu alu;
4618 int i, r;
4619
4620 /* We'll only need the trig stuff if we are going to write to the
4621 * X or Y components of the destination vector.
4622 */
4623 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
4624 r = tgsi_setup_trig(ctx);
4625 if (r)
4626 return r;
4627 }
4628
4629 /* dst.x = COS */
4630 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4631 if (ctx->bc->chip_class == CAYMAN) {
4632 for (i = 0 ; i < 3; i++) {
4633 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4634 alu.op = ALU_OP1_COS;
4635 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4636
4637 if (i == 0)
4638 alu.dst.write = 1;
4639 else
4640 alu.dst.write = 0;
4641 alu.src[0].sel = ctx->temp_reg;
4642 alu.src[0].chan = 0;
4643 if (i == 2)
4644 alu.last = 1;
4645 r = r600_bytecode_add_alu(ctx->bc, &alu);
4646 if (r)
4647 return r;
4648 }
4649 } else {
4650 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4651 alu.op = ALU_OP1_COS;
4652 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4653
4654 alu.src[0].sel = ctx->temp_reg;
4655 alu.src[0].chan = 0;
4656 alu.last = 1;
4657 r = r600_bytecode_add_alu(ctx->bc, &alu);
4658 if (r)
4659 return r;
4660 }
4661 }
4662
4663 /* dst.y = SIN */
4664 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4665 if (ctx->bc->chip_class == CAYMAN) {
4666 for (i = 0 ; i < 3; i++) {
4667 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4668 alu.op = ALU_OP1_SIN;
4669 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4670 if (i == 1)
4671 alu.dst.write = 1;
4672 else
4673 alu.dst.write = 0;
4674 alu.src[0].sel = ctx->temp_reg;
4675 alu.src[0].chan = 0;
4676 if (i == 2)
4677 alu.last = 1;
4678 r = r600_bytecode_add_alu(ctx->bc, &alu);
4679 if (r)
4680 return r;
4681 }
4682 } else {
4683 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4684 alu.op = ALU_OP1_SIN;
4685 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4686
4687 alu.src[0].sel = ctx->temp_reg;
4688 alu.src[0].chan = 0;
4689 alu.last = 1;
4690 r = r600_bytecode_add_alu(ctx->bc, &alu);
4691 if (r)
4692 return r;
4693 }
4694 }
4695
4696 /* dst.z = 0.0; */
4697 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4698 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4699
4700 alu.op = ALU_OP1_MOV;
4701
4702 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4703
4704 alu.src[0].sel = V_SQ_ALU_SRC_0;
4705 alu.src[0].chan = 0;
4706
4707 alu.last = 1;
4708
4709 r = r600_bytecode_add_alu(ctx->bc, &alu);
4710 if (r)
4711 return r;
4712 }
4713
4714 /* dst.w = 1.0; */
4715 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4716 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4717
4718 alu.op = ALU_OP1_MOV;
4719
4720 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4721
4722 alu.src[0].sel = V_SQ_ALU_SRC_1;
4723 alu.src[0].chan = 0;
4724
4725 alu.last = 1;
4726
4727 r = r600_bytecode_add_alu(ctx->bc, &alu);
4728 if (r)
4729 return r;
4730 }
4731
4732 return 0;
4733 }
4734
4735 static int tgsi_kill(struct r600_shader_ctx *ctx)
4736 {
4737 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4738 struct r600_bytecode_alu alu;
4739 int i, r;
4740
4741 for (i = 0; i < 4; i++) {
4742 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4743 alu.op = ctx->inst_info->op;
4744
4745 alu.dst.chan = i;
4746
4747 alu.src[0].sel = V_SQ_ALU_SRC_0;
4748
4749 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4750 alu.src[1].sel = V_SQ_ALU_SRC_1;
4751 alu.src[1].neg = 1;
4752 } else {
4753 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4754 }
4755 if (i == 3) {
4756 alu.last = 1;
4757 }
4758 r = r600_bytecode_add_alu(ctx->bc, &alu);
4759 if (r)
4760 return r;
4761 }
4762
4763 /* kill must be last in ALU */
4764 ctx->bc->force_add_cf = 1;
4765 ctx->shader->uses_kill = TRUE;
4766 return 0;
4767 }
4768
4769 static int tgsi_lit(struct r600_shader_ctx *ctx)
4770 {
4771 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4772 struct r600_bytecode_alu alu;
4773 int r;
4774
4775 /* tmp.x = max(src.y, 0.0) */
4776 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4777 alu.op = ALU_OP2_MAX;
4778 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4779 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4780 alu.src[1].chan = 1;
4781
4782 alu.dst.sel = ctx->temp_reg;
4783 alu.dst.chan = 0;
4784 alu.dst.write = 1;
4785
4786 alu.last = 1;
4787 r = r600_bytecode_add_alu(ctx->bc, &alu);
4788 if (r)
4789 return r;
4790
4791 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4792 {
4793 int chan;
4794 int sel;
4795 int i;
4796
4797 if (ctx->bc->chip_class == CAYMAN) {
4798 for (i = 0; i < 3; i++) {
4799 /* tmp.z = log(tmp.x) */
4800 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4801 alu.op = ALU_OP1_LOG_CLAMPED;
4802 alu.src[0].sel = ctx->temp_reg;
4803 alu.src[0].chan = 0;
4804 alu.dst.sel = ctx->temp_reg;
4805 alu.dst.chan = i;
4806 if (i == 2) {
4807 alu.dst.write = 1;
4808 alu.last = 1;
4809 } else
4810 alu.dst.write = 0;
4811
4812 r = r600_bytecode_add_alu(ctx->bc, &alu);
4813 if (r)
4814 return r;
4815 }
4816 } else {
4817 /* tmp.z = log(tmp.x) */
4818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4819 alu.op = ALU_OP1_LOG_CLAMPED;
4820 alu.src[0].sel = ctx->temp_reg;
4821 alu.src[0].chan = 0;
4822 alu.dst.sel = ctx->temp_reg;
4823 alu.dst.chan = 2;
4824 alu.dst.write = 1;
4825 alu.last = 1;
4826 r = r600_bytecode_add_alu(ctx->bc, &alu);
4827 if (r)
4828 return r;
4829 }
4830
4831 chan = alu.dst.chan;
4832 sel = alu.dst.sel;
4833
4834 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4835 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4836 alu.op = ALU_OP3_MUL_LIT;
4837 alu.src[0].sel = sel;
4838 alu.src[0].chan = chan;
4839 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4840 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4841 alu.dst.sel = ctx->temp_reg;
4842 alu.dst.chan = 0;
4843 alu.dst.write = 1;
4844 alu.is_op3 = 1;
4845 alu.last = 1;
4846 r = r600_bytecode_add_alu(ctx->bc, &alu);
4847 if (r)
4848 return r;
4849
4850 if (ctx->bc->chip_class == CAYMAN) {
4851 for (i = 0; i < 3; i++) {
4852 /* dst.z = exp(tmp.x) */
4853 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4854 alu.op = ALU_OP1_EXP_IEEE;
4855 alu.src[0].sel = ctx->temp_reg;
4856 alu.src[0].chan = 0;
4857 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4858 if (i == 2) {
4859 alu.dst.write = 1;
4860 alu.last = 1;
4861 } else
4862 alu.dst.write = 0;
4863 r = r600_bytecode_add_alu(ctx->bc, &alu);
4864 if (r)
4865 return r;
4866 }
4867 } else {
4868 /* dst.z = exp(tmp.x) */
4869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4870 alu.op = ALU_OP1_EXP_IEEE;
4871 alu.src[0].sel = ctx->temp_reg;
4872 alu.src[0].chan = 0;
4873 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4874 alu.last = 1;
4875 r = r600_bytecode_add_alu(ctx->bc, &alu);
4876 if (r)
4877 return r;
4878 }
4879 }
4880
4881 /* dst.x, <- 1.0 */
4882 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4883 alu.op = ALU_OP1_MOV;
4884 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4885 alu.src[0].chan = 0;
4886 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4887 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4888 r = r600_bytecode_add_alu(ctx->bc, &alu);
4889 if (r)
4890 return r;
4891
4892 /* dst.y = max(src.x, 0.0) */
4893 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4894 alu.op = ALU_OP2_MAX;
4895 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4896 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4897 alu.src[1].chan = 0;
4898 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4899 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4900 r = r600_bytecode_add_alu(ctx->bc, &alu);
4901 if (r)
4902 return r;
4903
4904 /* dst.w, <- 1.0 */
4905 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4906 alu.op = ALU_OP1_MOV;
4907 alu.src[0].sel = V_SQ_ALU_SRC_1;
4908 alu.src[0].chan = 0;
4909 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4910 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4911 alu.last = 1;
4912 r = r600_bytecode_add_alu(ctx->bc, &alu);
4913 if (r)
4914 return r;
4915
4916 return 0;
4917 }
4918
4919 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4920 {
4921 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4922 struct r600_bytecode_alu alu;
4923 int i, r;
4924
4925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4926
4927 /* XXX:
4928 * For state trackers other than OpenGL, we'll want to use
4929 * _RECIPSQRT_IEEE instead.
4930 */
4931 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
4932
4933 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4934 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4935 r600_bytecode_src_set_abs(&alu.src[i]);
4936 }
4937 alu.dst.sel = ctx->temp_reg;
4938 alu.dst.write = 1;
4939 alu.last = 1;
4940 r = r600_bytecode_add_alu(ctx->bc, &alu);
4941 if (r)
4942 return r;
4943 /* replicate result */
4944 return tgsi_helper_tempx_replicate(ctx);
4945 }
4946
4947 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4948 {
4949 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4950 struct r600_bytecode_alu alu;
4951 int i, r;
4952
4953 for (i = 0; i < 4; i++) {
4954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4955 alu.src[0].sel = ctx->temp_reg;
4956 alu.op = ALU_OP1_MOV;
4957 alu.dst.chan = i;
4958 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4959 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4960 if (i == 3)
4961 alu.last = 1;
4962 r = r600_bytecode_add_alu(ctx->bc, &alu);
4963 if (r)
4964 return r;
4965 }
4966 return 0;
4967 }
4968
4969 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4970 {
4971 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4972 struct r600_bytecode_alu alu;
4973 int i, r;
4974
4975 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4976 alu.op = ctx->inst_info->op;
4977 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4978 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4979 }
4980 alu.dst.sel = ctx->temp_reg;
4981 alu.dst.write = 1;
4982 alu.last = 1;
4983 r = r600_bytecode_add_alu(ctx->bc, &alu);
4984 if (r)
4985 return r;
4986 /* replicate result */
4987 return tgsi_helper_tempx_replicate(ctx);
4988 }
4989
4990 static int cayman_pow(struct r600_shader_ctx *ctx)
4991 {
4992 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4993 int i, r;
4994 struct r600_bytecode_alu alu;
4995 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4996
4997 for (i = 0; i < 3; i++) {
4998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4999 alu.op = ALU_OP1_LOG_IEEE;
5000 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5001 alu.dst.sel = ctx->temp_reg;
5002 alu.dst.chan = i;
5003 alu.dst.write = 1;
5004 if (i == 2)
5005 alu.last = 1;
5006 r = r600_bytecode_add_alu(ctx->bc, &alu);
5007 if (r)
5008 return r;
5009 }
5010
5011 /* b * LOG2(a) */
5012 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5013 alu.op = ALU_OP2_MUL;
5014 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5015 alu.src[1].sel = ctx->temp_reg;
5016 alu.dst.sel = ctx->temp_reg;
5017 alu.dst.write = 1;
5018 alu.last = 1;
5019 r = r600_bytecode_add_alu(ctx->bc, &alu);
5020 if (r)
5021 return r;
5022
5023 for (i = 0; i < last_slot; i++) {
5024 /* POW(a,b) = EXP2(b * LOG2(a))*/
5025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5026 alu.op = ALU_OP1_EXP_IEEE;
5027 alu.src[0].sel = ctx->temp_reg;
5028
5029 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5030 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5031 if (i == last_slot - 1)
5032 alu.last = 1;
5033 r = r600_bytecode_add_alu(ctx->bc, &alu);
5034 if (r)
5035 return r;
5036 }
5037 return 0;
5038 }
5039
5040 static int tgsi_pow(struct r600_shader_ctx *ctx)
5041 {
5042 struct r600_bytecode_alu alu;
5043 int r;
5044
5045 /* LOG2(a) */
5046 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5047 alu.op = ALU_OP1_LOG_IEEE;
5048 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5049 alu.dst.sel = ctx->temp_reg;
5050 alu.dst.write = 1;
5051 alu.last = 1;
5052 r = r600_bytecode_add_alu(ctx->bc, &alu);
5053 if (r)
5054 return r;
5055 /* b * LOG2(a) */
5056 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5057 alu.op = ALU_OP2_MUL;
5058 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5059 alu.src[1].sel = ctx->temp_reg;
5060 alu.dst.sel = ctx->temp_reg;
5061 alu.dst.write = 1;
5062 alu.last = 1;
5063 r = r600_bytecode_add_alu(ctx->bc, &alu);
5064 if (r)
5065 return r;
5066 /* POW(a,b) = EXP2(b * LOG2(a))*/
5067 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5068 alu.op = ALU_OP1_EXP_IEEE;
5069 alu.src[0].sel = ctx->temp_reg;
5070 alu.dst.sel = ctx->temp_reg;
5071 alu.dst.write = 1;
5072 alu.last = 1;
5073 r = r600_bytecode_add_alu(ctx->bc, &alu);
5074 if (r)
5075 return r;
5076 return tgsi_helper_tempx_replicate(ctx);
5077 }
5078
5079 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5080 {
5081 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5082 struct r600_bytecode_alu alu;
5083 int i, r, j;
5084 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5085 int tmp0 = ctx->temp_reg;
5086 int tmp1 = r600_get_temp(ctx);
5087 int tmp2 = r600_get_temp(ctx);
5088 int tmp3 = r600_get_temp(ctx);
5089 /* Unsigned path:
5090 *
5091 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5092 *
5093 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5094 * 2. tmp0.z = lo (tmp0.x * src2)
5095 * 3. tmp0.w = -tmp0.z
5096 * 4. tmp0.y = hi (tmp0.x * src2)
5097 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5098 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5099 * 7. tmp1.x = tmp0.x - tmp0.w
5100 * 8. tmp1.y = tmp0.x + tmp0.w
5101 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5102 * 10. tmp0.z = hi(tmp0.x * src1) = q
5103 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5104 *
5105 * 12. tmp0.w = src1 - tmp0.y = r
5106 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5107 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5108 *
5109 * if DIV
5110 *
5111 * 15. tmp1.z = tmp0.z + 1 = q + 1
5112 * 16. tmp1.w = tmp0.z - 1 = q - 1
5113 *
5114 * else MOD
5115 *
5116 * 15. tmp1.z = tmp0.w - src2 = r - src2
5117 * 16. tmp1.w = tmp0.w + src2 = r + src2
5118 *
5119 * endif
5120 *
5121 * 17. tmp1.x = tmp1.x & tmp1.y
5122 *
5123 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5124 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5125 *
5126 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5127 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5128 *
5129 * Signed path:
5130 *
5131 * Same as unsigned, using abs values of the operands,
5132 * and fixing the sign of the result in the end.
5133 */
5134
5135 for (i = 0; i < 4; i++) {
5136 if (!(write_mask & (1<<i)))
5137 continue;
5138
5139 if (signed_op) {
5140
5141 /* tmp2.x = -src0 */
5142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5143 alu.op = ALU_OP2_SUB_INT;
5144
5145 alu.dst.sel = tmp2;
5146 alu.dst.chan = 0;
5147 alu.dst.write = 1;
5148
5149 alu.src[0].sel = V_SQ_ALU_SRC_0;
5150
5151 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5152
5153 alu.last = 1;
5154 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5155 return r;
5156
5157 /* tmp2.y = -src1 */
5158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5159 alu.op = ALU_OP2_SUB_INT;
5160
5161 alu.dst.sel = tmp2;
5162 alu.dst.chan = 1;
5163 alu.dst.write = 1;
5164
5165 alu.src[0].sel = V_SQ_ALU_SRC_0;
5166
5167 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5168
5169 alu.last = 1;
5170 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5171 return r;
5172
5173 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5174 /* it will be a sign of the quotient */
5175 if (!mod) {
5176
5177 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5178 alu.op = ALU_OP2_XOR_INT;
5179
5180 alu.dst.sel = tmp2;
5181 alu.dst.chan = 2;
5182 alu.dst.write = 1;
5183
5184 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5185 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5186
5187 alu.last = 1;
5188 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5189 return r;
5190 }
5191
5192 /* tmp2.x = |src0| */
5193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5194 alu.op = ALU_OP3_CNDGE_INT;
5195 alu.is_op3 = 1;
5196
5197 alu.dst.sel = tmp2;
5198 alu.dst.chan = 0;
5199 alu.dst.write = 1;
5200
5201 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5202 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5203 alu.src[2].sel = tmp2;
5204 alu.src[2].chan = 0;
5205
5206 alu.last = 1;
5207 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5208 return r;
5209
5210 /* tmp2.y = |src1| */
5211 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5212 alu.op = ALU_OP3_CNDGE_INT;
5213 alu.is_op3 = 1;
5214
5215 alu.dst.sel = tmp2;
5216 alu.dst.chan = 1;
5217 alu.dst.write = 1;
5218
5219 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5220 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5221 alu.src[2].sel = tmp2;
5222 alu.src[2].chan = 1;
5223
5224 alu.last = 1;
5225 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5226 return r;
5227
5228 }
5229
5230 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5231 if (ctx->bc->chip_class == CAYMAN) {
5232 /* tmp3.x = u2f(src2) */
5233 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5234 alu.op = ALU_OP1_UINT_TO_FLT;
5235
5236 alu.dst.sel = tmp3;
5237 alu.dst.chan = 0;
5238 alu.dst.write = 1;
5239
5240 if (signed_op) {
5241 alu.src[0].sel = tmp2;
5242 alu.src[0].chan = 1;
5243 } else {
5244 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5245 }
5246
5247 alu.last = 1;
5248 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5249 return r;
5250
5251 /* tmp0.x = recip(tmp3.x) */
5252 for (j = 0 ; j < 3; j++) {
5253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5254 alu.op = ALU_OP1_RECIP_IEEE;
5255
5256 alu.dst.sel = tmp0;
5257 alu.dst.chan = j;
5258 alu.dst.write = (j == 0);
5259
5260 alu.src[0].sel = tmp3;
5261 alu.src[0].chan = 0;
5262
5263 if (j == 2)
5264 alu.last = 1;
5265 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5266 return r;
5267 }
5268
5269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5270 alu.op = ALU_OP2_MUL;
5271
5272 alu.src[0].sel = tmp0;
5273 alu.src[0].chan = 0;
5274
5275 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5276 alu.src[1].value = 0x4f800000;
5277
5278 alu.dst.sel = tmp3;
5279 alu.dst.write = 1;
5280 alu.last = 1;
5281 r = r600_bytecode_add_alu(ctx->bc, &alu);
5282 if (r)
5283 return r;
5284
5285 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5286 alu.op = ALU_OP1_FLT_TO_UINT;
5287
5288 alu.dst.sel = tmp0;
5289 alu.dst.chan = 0;
5290 alu.dst.write = 1;
5291
5292 alu.src[0].sel = tmp3;
5293 alu.src[0].chan = 0;
5294
5295 alu.last = 1;
5296 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5297 return r;
5298
5299 } else {
5300 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5301 alu.op = ALU_OP1_RECIP_UINT;
5302
5303 alu.dst.sel = tmp0;
5304 alu.dst.chan = 0;
5305 alu.dst.write = 1;
5306
5307 if (signed_op) {
5308 alu.src[0].sel = tmp2;
5309 alu.src[0].chan = 1;
5310 } else {
5311 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5312 }
5313
5314 alu.last = 1;
5315 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5316 return r;
5317 }
5318
5319 /* 2. tmp0.z = lo (tmp0.x * src2) */
5320 if (ctx->bc->chip_class == CAYMAN) {
5321 for (j = 0 ; j < 4; j++) {
5322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5323 alu.op = ALU_OP2_MULLO_UINT;
5324
5325 alu.dst.sel = tmp0;
5326 alu.dst.chan = j;
5327 alu.dst.write = (j == 2);
5328
5329 alu.src[0].sel = tmp0;
5330 alu.src[0].chan = 0;
5331 if (signed_op) {
5332 alu.src[1].sel = tmp2;
5333 alu.src[1].chan = 1;
5334 } else {
5335 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5336 }
5337
5338 alu.last = (j == 3);
5339 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5340 return r;
5341 }
5342 } else {
5343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5344 alu.op = ALU_OP2_MULLO_UINT;
5345
5346 alu.dst.sel = tmp0;
5347 alu.dst.chan = 2;
5348 alu.dst.write = 1;
5349
5350 alu.src[0].sel = tmp0;
5351 alu.src[0].chan = 0;
5352 if (signed_op) {
5353 alu.src[1].sel = tmp2;
5354 alu.src[1].chan = 1;
5355 } else {
5356 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5357 }
5358
5359 alu.last = 1;
5360 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5361 return r;
5362 }
5363
5364 /* 3. tmp0.w = -tmp0.z */
5365 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5366 alu.op = ALU_OP2_SUB_INT;
5367
5368 alu.dst.sel = tmp0;
5369 alu.dst.chan = 3;
5370 alu.dst.write = 1;
5371
5372 alu.src[0].sel = V_SQ_ALU_SRC_0;
5373 alu.src[1].sel = tmp0;
5374 alu.src[1].chan = 2;
5375
5376 alu.last = 1;
5377 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5378 return r;
5379
5380 /* 4. tmp0.y = hi (tmp0.x * src2) */
5381 if (ctx->bc->chip_class == CAYMAN) {
5382 for (j = 0 ; j < 4; j++) {
5383 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5384 alu.op = ALU_OP2_MULHI_UINT;
5385
5386 alu.dst.sel = tmp0;
5387 alu.dst.chan = j;
5388 alu.dst.write = (j == 1);
5389
5390 alu.src[0].sel = tmp0;
5391 alu.src[0].chan = 0;
5392
5393 if (signed_op) {
5394 alu.src[1].sel = tmp2;
5395 alu.src[1].chan = 1;
5396 } else {
5397 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5398 }
5399 alu.last = (j == 3);
5400 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5401 return r;
5402 }
5403 } else {
5404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5405 alu.op = ALU_OP2_MULHI_UINT;
5406
5407 alu.dst.sel = tmp0;
5408 alu.dst.chan = 1;
5409 alu.dst.write = 1;
5410
5411 alu.src[0].sel = tmp0;
5412 alu.src[0].chan = 0;
5413
5414 if (signed_op) {
5415 alu.src[1].sel = tmp2;
5416 alu.src[1].chan = 1;
5417 } else {
5418 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5419 }
5420
5421 alu.last = 1;
5422 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5423 return r;
5424 }
5425
5426 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5428 alu.op = ALU_OP3_CNDE_INT;
5429 alu.is_op3 = 1;
5430
5431 alu.dst.sel = tmp0;
5432 alu.dst.chan = 2;
5433 alu.dst.write = 1;
5434
5435 alu.src[0].sel = tmp0;
5436 alu.src[0].chan = 1;
5437 alu.src[1].sel = tmp0;
5438 alu.src[1].chan = 3;
5439 alu.src[2].sel = tmp0;
5440 alu.src[2].chan = 2;
5441
5442 alu.last = 1;
5443 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5444 return r;
5445
5446 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5447 if (ctx->bc->chip_class == CAYMAN) {
5448 for (j = 0 ; j < 4; j++) {
5449 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5450 alu.op = ALU_OP2_MULHI_UINT;
5451
5452 alu.dst.sel = tmp0;
5453 alu.dst.chan = j;
5454 alu.dst.write = (j == 3);
5455
5456 alu.src[0].sel = tmp0;
5457 alu.src[0].chan = 2;
5458
5459 alu.src[1].sel = tmp0;
5460 alu.src[1].chan = 0;
5461
5462 alu.last = (j == 3);
5463 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5464 return r;
5465 }
5466 } else {
5467 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5468 alu.op = ALU_OP2_MULHI_UINT;
5469
5470 alu.dst.sel = tmp0;
5471 alu.dst.chan = 3;
5472 alu.dst.write = 1;
5473
5474 alu.src[0].sel = tmp0;
5475 alu.src[0].chan = 2;
5476
5477 alu.src[1].sel = tmp0;
5478 alu.src[1].chan = 0;
5479
5480 alu.last = 1;
5481 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5482 return r;
5483 }
5484
5485 /* 7. tmp1.x = tmp0.x - tmp0.w */
5486 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5487 alu.op = ALU_OP2_SUB_INT;
5488
5489 alu.dst.sel = tmp1;
5490 alu.dst.chan = 0;
5491 alu.dst.write = 1;
5492
5493 alu.src[0].sel = tmp0;
5494 alu.src[0].chan = 0;
5495 alu.src[1].sel = tmp0;
5496 alu.src[1].chan = 3;
5497
5498 alu.last = 1;
5499 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5500 return r;
5501
5502 /* 8. tmp1.y = tmp0.x + tmp0.w */
5503 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5504 alu.op = ALU_OP2_ADD_INT;
5505
5506 alu.dst.sel = tmp1;
5507 alu.dst.chan = 1;
5508 alu.dst.write = 1;
5509
5510 alu.src[0].sel = tmp0;
5511 alu.src[0].chan = 0;
5512 alu.src[1].sel = tmp0;
5513 alu.src[1].chan = 3;
5514
5515 alu.last = 1;
5516 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5517 return r;
5518
5519 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5520 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5521 alu.op = ALU_OP3_CNDE_INT;
5522 alu.is_op3 = 1;
5523
5524 alu.dst.sel = tmp0;
5525 alu.dst.chan = 0;
5526 alu.dst.write = 1;
5527
5528 alu.src[0].sel = tmp0;
5529 alu.src[0].chan = 1;
5530 alu.src[1].sel = tmp1;
5531 alu.src[1].chan = 1;
5532 alu.src[2].sel = tmp1;
5533 alu.src[2].chan = 0;
5534
5535 alu.last = 1;
5536 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5537 return r;
5538
5539 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5540 if (ctx->bc->chip_class == CAYMAN) {
5541 for (j = 0 ; j < 4; j++) {
5542 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5543 alu.op = ALU_OP2_MULHI_UINT;
5544
5545 alu.dst.sel = tmp0;
5546 alu.dst.chan = j;
5547 alu.dst.write = (j == 2);
5548
5549 alu.src[0].sel = tmp0;
5550 alu.src[0].chan = 0;
5551
5552 if (signed_op) {
5553 alu.src[1].sel = tmp2;
5554 alu.src[1].chan = 0;
5555 } else {
5556 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5557 }
5558
5559 alu.last = (j == 3);
5560 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5561 return r;
5562 }
5563 } else {
5564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5565 alu.op = ALU_OP2_MULHI_UINT;
5566
5567 alu.dst.sel = tmp0;
5568 alu.dst.chan = 2;
5569 alu.dst.write = 1;
5570
5571 alu.src[0].sel = tmp0;
5572 alu.src[0].chan = 0;
5573
5574 if (signed_op) {
5575 alu.src[1].sel = tmp2;
5576 alu.src[1].chan = 0;
5577 } else {
5578 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5579 }
5580
5581 alu.last = 1;
5582 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5583 return r;
5584 }
5585
5586 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5587 if (ctx->bc->chip_class == CAYMAN) {
5588 for (j = 0 ; j < 4; j++) {
5589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5590 alu.op = ALU_OP2_MULLO_UINT;
5591
5592 alu.dst.sel = tmp0;
5593 alu.dst.chan = j;
5594 alu.dst.write = (j == 1);
5595
5596 if (signed_op) {
5597 alu.src[0].sel = tmp2;
5598 alu.src[0].chan = 1;
5599 } else {
5600 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5601 }
5602
5603 alu.src[1].sel = tmp0;
5604 alu.src[1].chan = 2;
5605
5606 alu.last = (j == 3);
5607 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5608 return r;
5609 }
5610 } else {
5611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5612 alu.op = ALU_OP2_MULLO_UINT;
5613
5614 alu.dst.sel = tmp0;
5615 alu.dst.chan = 1;
5616 alu.dst.write = 1;
5617
5618 if (signed_op) {
5619 alu.src[0].sel = tmp2;
5620 alu.src[0].chan = 1;
5621 } else {
5622 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5623 }
5624
5625 alu.src[1].sel = tmp0;
5626 alu.src[1].chan = 2;
5627
5628 alu.last = 1;
5629 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5630 return r;
5631 }
5632
5633 /* 12. tmp0.w = src1 - tmp0.y = r */
5634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5635 alu.op = ALU_OP2_SUB_INT;
5636
5637 alu.dst.sel = tmp0;
5638 alu.dst.chan = 3;
5639 alu.dst.write = 1;
5640
5641 if (signed_op) {
5642 alu.src[0].sel = tmp2;
5643 alu.src[0].chan = 0;
5644 } else {
5645 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5646 }
5647
5648 alu.src[1].sel = tmp0;
5649 alu.src[1].chan = 1;
5650
5651 alu.last = 1;
5652 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5653 return r;
5654
5655 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5656 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5657 alu.op = ALU_OP2_SETGE_UINT;
5658
5659 alu.dst.sel = tmp1;
5660 alu.dst.chan = 0;
5661 alu.dst.write = 1;
5662
5663 alu.src[0].sel = tmp0;
5664 alu.src[0].chan = 3;
5665 if (signed_op) {
5666 alu.src[1].sel = tmp2;
5667 alu.src[1].chan = 1;
5668 } else {
5669 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5670 }
5671
5672 alu.last = 1;
5673 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5674 return r;
5675
5676 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5677 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5678 alu.op = ALU_OP2_SETGE_UINT;
5679
5680 alu.dst.sel = tmp1;
5681 alu.dst.chan = 1;
5682 alu.dst.write = 1;
5683
5684 if (signed_op) {
5685 alu.src[0].sel = tmp2;
5686 alu.src[0].chan = 0;
5687 } else {
5688 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5689 }
5690
5691 alu.src[1].sel = tmp0;
5692 alu.src[1].chan = 1;
5693
5694 alu.last = 1;
5695 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5696 return r;
5697
5698 if (mod) { /* UMOD */
5699
5700 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5702 alu.op = ALU_OP2_SUB_INT;
5703
5704 alu.dst.sel = tmp1;
5705 alu.dst.chan = 2;
5706 alu.dst.write = 1;
5707
5708 alu.src[0].sel = tmp0;
5709 alu.src[0].chan = 3;
5710
5711 if (signed_op) {
5712 alu.src[1].sel = tmp2;
5713 alu.src[1].chan = 1;
5714 } else {
5715 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5716 }
5717
5718 alu.last = 1;
5719 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5720 return r;
5721
5722 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5723 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5724 alu.op = ALU_OP2_ADD_INT;
5725
5726 alu.dst.sel = tmp1;
5727 alu.dst.chan = 3;
5728 alu.dst.write = 1;
5729
5730 alu.src[0].sel = tmp0;
5731 alu.src[0].chan = 3;
5732 if (signed_op) {
5733 alu.src[1].sel = tmp2;
5734 alu.src[1].chan = 1;
5735 } else {
5736 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5737 }
5738
5739 alu.last = 1;
5740 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5741 return r;
5742
5743 } else { /* UDIV */
5744
5745 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5746 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5747 alu.op = ALU_OP2_ADD_INT;
5748
5749 alu.dst.sel = tmp1;
5750 alu.dst.chan = 2;
5751 alu.dst.write = 1;
5752
5753 alu.src[0].sel = tmp0;
5754 alu.src[0].chan = 2;
5755 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5756
5757 alu.last = 1;
5758 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5759 return r;
5760
5761 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5763 alu.op = ALU_OP2_ADD_INT;
5764
5765 alu.dst.sel = tmp1;
5766 alu.dst.chan = 3;
5767 alu.dst.write = 1;
5768
5769 alu.src[0].sel = tmp0;
5770 alu.src[0].chan = 2;
5771 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5772
5773 alu.last = 1;
5774 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5775 return r;
5776
5777 }
5778
5779 /* 17. tmp1.x = tmp1.x & tmp1.y */
5780 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5781 alu.op = ALU_OP2_AND_INT;
5782
5783 alu.dst.sel = tmp1;
5784 alu.dst.chan = 0;
5785 alu.dst.write = 1;
5786
5787 alu.src[0].sel = tmp1;
5788 alu.src[0].chan = 0;
5789 alu.src[1].sel = tmp1;
5790 alu.src[1].chan = 1;
5791
5792 alu.last = 1;
5793 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5794 return r;
5795
5796 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5797 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5798 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5799 alu.op = ALU_OP3_CNDE_INT;
5800 alu.is_op3 = 1;
5801
5802 alu.dst.sel = tmp0;
5803 alu.dst.chan = 2;
5804 alu.dst.write = 1;
5805
5806 alu.src[0].sel = tmp1;
5807 alu.src[0].chan = 0;
5808 alu.src[1].sel = tmp0;
5809 alu.src[1].chan = mod ? 3 : 2;
5810 alu.src[2].sel = tmp1;
5811 alu.src[2].chan = 2;
5812
5813 alu.last = 1;
5814 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5815 return r;
5816
5817 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5819 alu.op = ALU_OP3_CNDE_INT;
5820 alu.is_op3 = 1;
5821
5822 if (signed_op) {
5823 alu.dst.sel = tmp0;
5824 alu.dst.chan = 2;
5825 alu.dst.write = 1;
5826 } else {
5827 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5828 }
5829
5830 alu.src[0].sel = tmp1;
5831 alu.src[0].chan = 1;
5832 alu.src[1].sel = tmp1;
5833 alu.src[1].chan = 3;
5834 alu.src[2].sel = tmp0;
5835 alu.src[2].chan = 2;
5836
5837 alu.last = 1;
5838 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5839 return r;
5840
5841 if (signed_op) {
5842
5843 /* fix the sign of the result */
5844
5845 if (mod) {
5846
5847 /* tmp0.x = -tmp0.z */
5848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5849 alu.op = ALU_OP2_SUB_INT;
5850
5851 alu.dst.sel = tmp0;
5852 alu.dst.chan = 0;
5853 alu.dst.write = 1;
5854
5855 alu.src[0].sel = V_SQ_ALU_SRC_0;
5856 alu.src[1].sel = tmp0;
5857 alu.src[1].chan = 2;
5858
5859 alu.last = 1;
5860 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5861 return r;
5862
5863 /* sign of the remainder is the same as the sign of src0 */
5864 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5865 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5866 alu.op = ALU_OP3_CNDGE_INT;
5867 alu.is_op3 = 1;
5868
5869 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5870
5871 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5872 alu.src[1].sel = tmp0;
5873 alu.src[1].chan = 2;
5874 alu.src[2].sel = tmp0;
5875 alu.src[2].chan = 0;
5876
5877 alu.last = 1;
5878 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5879 return r;
5880
5881 } else {
5882
5883 /* tmp0.x = -tmp0.z */
5884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5885 alu.op = ALU_OP2_SUB_INT;
5886
5887 alu.dst.sel = tmp0;
5888 alu.dst.chan = 0;
5889 alu.dst.write = 1;
5890
5891 alu.src[0].sel = V_SQ_ALU_SRC_0;
5892 alu.src[1].sel = tmp0;
5893 alu.src[1].chan = 2;
5894
5895 alu.last = 1;
5896 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5897 return r;
5898
5899 /* fix the quotient sign (same as the sign of src0*src1) */
5900 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5901 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5902 alu.op = ALU_OP3_CNDGE_INT;
5903 alu.is_op3 = 1;
5904
5905 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5906
5907 alu.src[0].sel = tmp2;
5908 alu.src[0].chan = 2;
5909 alu.src[1].sel = tmp0;
5910 alu.src[1].chan = 2;
5911 alu.src[2].sel = tmp0;
5912 alu.src[2].chan = 0;
5913
5914 alu.last = 1;
5915 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5916 return r;
5917 }
5918 }
5919 }
5920 return 0;
5921 }
5922
5923 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5924 {
5925 return tgsi_divmod(ctx, 0, 0);
5926 }
5927
5928 static int tgsi_umod(struct r600_shader_ctx *ctx)
5929 {
5930 return tgsi_divmod(ctx, 1, 0);
5931 }
5932
5933 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5934 {
5935 return tgsi_divmod(ctx, 0, 1);
5936 }
5937
5938 static int tgsi_imod(struct r600_shader_ctx *ctx)
5939 {
5940 return tgsi_divmod(ctx, 1, 1);
5941 }
5942
5943
5944 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5945 {
5946 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5947 struct r600_bytecode_alu alu;
5948 int i, r;
5949 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5950 int last_inst = tgsi_last_instruction(write_mask);
5951
5952 for (i = 0; i < 4; i++) {
5953 if (!(write_mask & (1<<i)))
5954 continue;
5955
5956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5957 alu.op = ALU_OP1_TRUNC;
5958
5959 alu.dst.sel = ctx->temp_reg;
5960 alu.dst.chan = i;
5961 alu.dst.write = 1;
5962
5963 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5964 if (i == last_inst)
5965 alu.last = 1;
5966 r = r600_bytecode_add_alu(ctx->bc, &alu);
5967 if (r)
5968 return r;
5969 }
5970
5971 for (i = 0; i < 4; i++) {
5972 if (!(write_mask & (1<<i)))
5973 continue;
5974
5975 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5976 alu.op = ctx->inst_info->op;
5977
5978 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5979
5980 alu.src[0].sel = ctx->temp_reg;
5981 alu.src[0].chan = i;
5982
5983 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5984 alu.last = 1;
5985 r = r600_bytecode_add_alu(ctx->bc, &alu);
5986 if (r)
5987 return r;
5988 }
5989
5990 return 0;
5991 }
5992
5993 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5994 {
5995 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5996 struct r600_bytecode_alu alu;
5997 int i, r;
5998 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5999 int last_inst = tgsi_last_instruction(write_mask);
6000
6001 /* tmp = -src */
6002 for (i = 0; i < 4; i++) {
6003 if (!(write_mask & (1<<i)))
6004 continue;
6005
6006 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6007 alu.op = ALU_OP2_SUB_INT;
6008
6009 alu.dst.sel = ctx->temp_reg;
6010 alu.dst.chan = i;
6011 alu.dst.write = 1;
6012
6013 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6014 alu.src[0].sel = V_SQ_ALU_SRC_0;
6015
6016 if (i == last_inst)
6017 alu.last = 1;
6018 r = r600_bytecode_add_alu(ctx->bc, &alu);
6019 if (r)
6020 return r;
6021 }
6022
6023 /* dst = (src >= 0 ? src : tmp) */
6024 for (i = 0; i < 4; i++) {
6025 if (!(write_mask & (1<<i)))
6026 continue;
6027
6028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6029 alu.op = ALU_OP3_CNDGE_INT;
6030 alu.is_op3 = 1;
6031 alu.dst.write = 1;
6032
6033 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6034
6035 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6036 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6037 alu.src[2].sel = ctx->temp_reg;
6038 alu.src[2].chan = i;
6039
6040 if (i == last_inst)
6041 alu.last = 1;
6042 r = r600_bytecode_add_alu(ctx->bc, &alu);
6043 if (r)
6044 return r;
6045 }
6046 return 0;
6047 }
6048
6049 static int tgsi_issg(struct r600_shader_ctx *ctx)
6050 {
6051 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6052 struct r600_bytecode_alu alu;
6053 int i, r;
6054 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6055 int last_inst = tgsi_last_instruction(write_mask);
6056
6057 /* tmp = (src >= 0 ? src : -1) */
6058 for (i = 0; i < 4; i++) {
6059 if (!(write_mask & (1<<i)))
6060 continue;
6061
6062 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6063 alu.op = ALU_OP3_CNDGE_INT;
6064 alu.is_op3 = 1;
6065
6066 alu.dst.sel = ctx->temp_reg;
6067 alu.dst.chan = i;
6068 alu.dst.write = 1;
6069
6070 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6071 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6072 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6073
6074 if (i == last_inst)
6075 alu.last = 1;
6076 r = r600_bytecode_add_alu(ctx->bc, &alu);
6077 if (r)
6078 return r;
6079 }
6080
6081 /* dst = (tmp > 0 ? 1 : tmp) */
6082 for (i = 0; i < 4; i++) {
6083 if (!(write_mask & (1<<i)))
6084 continue;
6085
6086 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6087 alu.op = ALU_OP3_CNDGT_INT;
6088 alu.is_op3 = 1;
6089 alu.dst.write = 1;
6090
6091 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6092
6093 alu.src[0].sel = ctx->temp_reg;
6094 alu.src[0].chan = i;
6095
6096 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6097
6098 alu.src[2].sel = ctx->temp_reg;
6099 alu.src[2].chan = i;
6100
6101 if (i == last_inst)
6102 alu.last = 1;
6103 r = r600_bytecode_add_alu(ctx->bc, &alu);
6104 if (r)
6105 return r;
6106 }
6107 return 0;
6108 }
6109
6110
6111
6112 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6113 {
6114 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6115 struct r600_bytecode_alu alu;
6116 int i, r;
6117
6118 /* tmp = (src > 0 ? 1 : src) */
6119 for (i = 0; i < 4; i++) {
6120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6121 alu.op = ALU_OP3_CNDGT;
6122 alu.is_op3 = 1;
6123
6124 alu.dst.sel = ctx->temp_reg;
6125 alu.dst.chan = i;
6126
6127 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6128 alu.src[1].sel = V_SQ_ALU_SRC_1;
6129 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6130
6131 if (i == 3)
6132 alu.last = 1;
6133 r = r600_bytecode_add_alu(ctx->bc, &alu);
6134 if (r)
6135 return r;
6136 }
6137
6138 /* dst = (-tmp > 0 ? -1 : tmp) */
6139 for (i = 0; i < 4; i++) {
6140 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6141 alu.op = ALU_OP3_CNDGT;
6142 alu.is_op3 = 1;
6143 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6144
6145 alu.src[0].sel = ctx->temp_reg;
6146 alu.src[0].chan = i;
6147 alu.src[0].neg = 1;
6148
6149 alu.src[1].sel = V_SQ_ALU_SRC_1;
6150 alu.src[1].neg = 1;
6151
6152 alu.src[2].sel = ctx->temp_reg;
6153 alu.src[2].chan = i;
6154
6155 if (i == 3)
6156 alu.last = 1;
6157 r = r600_bytecode_add_alu(ctx->bc, &alu);
6158 if (r)
6159 return r;
6160 }
6161 return 0;
6162 }
6163
6164 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6165 {
6166 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6167 struct r600_bytecode_alu alu;
6168 int i, r, t1, t2;
6169
6170 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6171 int last_inst = tgsi_last_instruction(write_mask);
6172
6173 t1 = ctx->temp_reg;
6174
6175 for (i = 0; i < 4; i++) {
6176 if (!(write_mask & (1<<i)))
6177 continue;
6178
6179 /* create mask tmp */
6180 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6181 alu.op = ALU_OP2_BFM_INT;
6182 alu.dst.sel = t1;
6183 alu.dst.chan = i;
6184 alu.dst.write = 1;
6185 alu.last = i == last_inst;
6186
6187 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6188 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6189
6190 r = r600_bytecode_add_alu(ctx->bc, &alu);
6191 if (r)
6192 return r;
6193 }
6194
6195 t2 = r600_get_temp(ctx);
6196
6197 for (i = 0; i < 4; i++) {
6198 if (!(write_mask & (1<<i)))
6199 continue;
6200
6201 /* shift insert left */
6202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6203 alu.op = ALU_OP2_LSHL_INT;
6204 alu.dst.sel = t2;
6205 alu.dst.chan = i;
6206 alu.dst.write = 1;
6207 alu.last = i == last_inst;
6208
6209 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6210 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6211
6212 r = r600_bytecode_add_alu(ctx->bc, &alu);
6213 if (r)
6214 return r;
6215 }
6216
6217 for (i = 0; i < 4; i++) {
6218 if (!(write_mask & (1<<i)))
6219 continue;
6220
6221 /* actual bitfield insert */
6222 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6223 alu.op = ALU_OP3_BFI_INT;
6224 alu.is_op3 = 1;
6225 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6226 alu.dst.chan = i;
6227 alu.dst.write = 1;
6228 alu.last = i == last_inst;
6229
6230 alu.src[0].sel = t1;
6231 alu.src[0].chan = i;
6232 alu.src[1].sel = t2;
6233 alu.src[1].chan = i;
6234 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6235
6236 r = r600_bytecode_add_alu(ctx->bc, &alu);
6237 if (r)
6238 return r;
6239 }
6240
6241 return 0;
6242 }
6243
6244 static int tgsi_msb(struct r600_shader_ctx *ctx)
6245 {
6246 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6247 struct r600_bytecode_alu alu;
6248 int i, r, t1, t2;
6249
6250 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6251 int last_inst = tgsi_last_instruction(write_mask);
6252
6253 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6254 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6255
6256 t1 = ctx->temp_reg;
6257
6258 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6259 for (i = 0; i < 4; i++) {
6260 if (!(write_mask & (1<<i)))
6261 continue;
6262
6263 /* t1 = FFBH_INT / FFBH_UINT */
6264 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6265 alu.op = ctx->inst_info->op;
6266 alu.dst.sel = t1;
6267 alu.dst.chan = i;
6268 alu.dst.write = 1;
6269 alu.last = i == last_inst;
6270
6271 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6272
6273 r = r600_bytecode_add_alu(ctx->bc, &alu);
6274 if (r)
6275 return r;
6276 }
6277
6278 t2 = r600_get_temp(ctx);
6279
6280 for (i = 0; i < 4; i++) {
6281 if (!(write_mask & (1<<i)))
6282 continue;
6283
6284 /* t2 = 31 - t1 */
6285 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6286 alu.op = ALU_OP2_SUB_INT;
6287 alu.dst.sel = t2;
6288 alu.dst.chan = i;
6289 alu.dst.write = 1;
6290 alu.last = i == last_inst;
6291
6292 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6293 alu.src[0].value = 31;
6294 alu.src[1].sel = t1;
6295 alu.src[1].chan = i;
6296
6297 r = r600_bytecode_add_alu(ctx->bc, &alu);
6298 if (r)
6299 return r;
6300 }
6301
6302 for (i = 0; i < 4; i++) {
6303 if (!(write_mask & (1<<i)))
6304 continue;
6305
6306 /* result = t1 >= 0 ? t2 : t1 */
6307 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6308 alu.op = ALU_OP3_CNDGE_INT;
6309 alu.is_op3 = 1;
6310 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6311 alu.dst.chan = i;
6312 alu.dst.write = 1;
6313 alu.last = i == last_inst;
6314
6315 alu.src[0].sel = t1;
6316 alu.src[0].chan = i;
6317 alu.src[1].sel = t2;
6318 alu.src[1].chan = i;
6319 alu.src[2].sel = t1;
6320 alu.src[2].chan = i;
6321
6322 r = r600_bytecode_add_alu(ctx->bc, &alu);
6323 if (r)
6324 return r;
6325 }
6326
6327 return 0;
6328 }
6329
6330 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6331 {
6332 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6333 struct r600_bytecode_alu alu;
6334 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6335 unsigned location;
6336 int input;
6337
6338 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6339
6340 input = inst->Src[0].Register.Index;
6341
6342 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6343 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6344 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6345 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6346 }
6347 else {
6348 location = TGSI_INTERPOLATE_LOC_CENTROID;
6349 }
6350
6351 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6352 if (k < 0)
6353 k = 0;
6354 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6355 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6356
6357 /* NOTE: currently offset is not perspective correct */
6358 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6359 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6360 int sample_gpr = -1;
6361 int gradientsH, gradientsV;
6362 struct r600_bytecode_tex tex;
6363
6364 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6365 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6366 }
6367
6368 gradientsH = r600_get_temp(ctx);
6369 gradientsV = r600_get_temp(ctx);
6370 for (i = 0; i < 2; i++) {
6371 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6372 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6373 tex.src_gpr = interp_gpr;
6374 tex.src_sel_x = interp_base_chan + 0;
6375 tex.src_sel_y = interp_base_chan + 1;
6376 tex.src_sel_z = 0;
6377 tex.src_sel_w = 0;
6378 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6379 tex.dst_sel_x = 0;
6380 tex.dst_sel_y = 1;
6381 tex.dst_sel_z = 7;
6382 tex.dst_sel_w = 7;
6383 tex.inst_mod = 1; // Use per pixel gradient calculation
6384 tex.sampler_id = 0;
6385 tex.resource_id = tex.sampler_id;
6386 r = r600_bytecode_add_tex(ctx->bc, &tex);
6387 if (r)
6388 return r;
6389 }
6390
6391 for (i = 0; i < 2; i++) {
6392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6393 alu.op = ALU_OP3_MULADD;
6394 alu.is_op3 = 1;
6395 alu.src[0].sel = gradientsH;
6396 alu.src[0].chan = i;
6397 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6398 alu.src[1].sel = sample_gpr;
6399 alu.src[1].chan = 2;
6400 }
6401 else {
6402 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6403 }
6404 alu.src[2].sel = interp_gpr;
6405 alu.src[2].chan = interp_base_chan + i;
6406 alu.dst.sel = ctx->temp_reg;
6407 alu.dst.chan = i;
6408 alu.last = i == 1;
6409
6410 r = r600_bytecode_add_alu(ctx->bc, &alu);
6411 if (r)
6412 return r;
6413 }
6414
6415 for (i = 0; i < 2; i++) {
6416 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6417 alu.op = ALU_OP3_MULADD;
6418 alu.is_op3 = 1;
6419 alu.src[0].sel = gradientsV;
6420 alu.src[0].chan = i;
6421 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6422 alu.src[1].sel = sample_gpr;
6423 alu.src[1].chan = 3;
6424 }
6425 else {
6426 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6427 }
6428 alu.src[2].sel = ctx->temp_reg;
6429 alu.src[2].chan = i;
6430 alu.dst.sel = ctx->temp_reg;
6431 alu.dst.chan = i;
6432 alu.last = i == 1;
6433
6434 r = r600_bytecode_add_alu(ctx->bc, &alu);
6435 if (r)
6436 return r;
6437 }
6438 }
6439
6440 tmp = r600_get_temp(ctx);
6441 for (i = 0; i < 8; i++) {
6442 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6443 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6444
6445 alu.dst.sel = tmp;
6446 if ((i > 1 && i < 6)) {
6447 alu.dst.write = 1;
6448 }
6449 else {
6450 alu.dst.write = 0;
6451 }
6452 alu.dst.chan = i % 4;
6453
6454 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6455 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6456 alu.src[0].sel = ctx->temp_reg;
6457 alu.src[0].chan = 1 - (i % 2);
6458 } else {
6459 alu.src[0].sel = interp_gpr;
6460 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6461 }
6462 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6463 alu.src[1].chan = 0;
6464
6465 alu.last = i % 4 == 3;
6466 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6467
6468 r = r600_bytecode_add_alu(ctx->bc, &alu);
6469 if (r)
6470 return r;
6471 }
6472
6473 // INTERP can't swizzle dst
6474 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6475 for (i = 0; i <= lasti; i++) {
6476 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6477 continue;
6478
6479 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6480 alu.op = ALU_OP1_MOV;
6481 alu.src[0].sel = tmp;
6482 alu.src[0].chan = ctx->src[0].swizzle[i];
6483 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6484 alu.dst.write = 1;
6485 alu.last = i == lasti;
6486 r = r600_bytecode_add_alu(ctx->bc, &alu);
6487 if (r)
6488 return r;
6489 }
6490
6491 return 0;
6492 }
6493
6494
6495 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6496 {
6497 struct r600_bytecode_alu alu;
6498 int i, r;
6499
6500 for (i = 0; i < 4; i++) {
6501 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6502 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6503 alu.op = ALU_OP0_NOP;
6504 alu.dst.chan = i;
6505 } else {
6506 alu.op = ALU_OP1_MOV;
6507 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6508 alu.src[0].sel = ctx->temp_reg;
6509 alu.src[0].chan = i;
6510 }
6511 if (i == 3) {
6512 alu.last = 1;
6513 }
6514 r = r600_bytecode_add_alu(ctx->bc, &alu);
6515 if (r)
6516 return r;
6517 }
6518 return 0;
6519 }
6520
6521 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6522 unsigned temp, int chan,
6523 struct r600_bytecode_alu_src *bc_src,
6524 const struct r600_shader_src *shader_src)
6525 {
6526 struct r600_bytecode_alu alu;
6527 int r;
6528
6529 r600_bytecode_src(bc_src, shader_src, chan);
6530
6531 /* op3 operands don't support abs modifier */
6532 if (bc_src->abs) {
6533 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6535 alu.op = ALU_OP1_MOV;
6536 alu.dst.sel = temp;
6537 alu.dst.chan = chan;
6538 alu.dst.write = 1;
6539
6540 alu.src[0] = *bc_src;
6541 alu.last = true; // sufficient?
6542 r = r600_bytecode_add_alu(ctx->bc, &alu);
6543 if (r)
6544 return r;
6545
6546 memset(bc_src, 0, sizeof(*bc_src));
6547 bc_src->sel = temp;
6548 bc_src->chan = chan;
6549 }
6550 return 0;
6551 }
6552
6553 static int tgsi_op3(struct r600_shader_ctx *ctx)
6554 {
6555 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6556 struct r600_bytecode_alu alu;
6557 int i, j, r;
6558 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6559 int temp_regs[4];
6560
6561 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6562 temp_regs[j] = 0;
6563 if (ctx->src[j].abs)
6564 temp_regs[j] = r600_get_temp(ctx);
6565 }
6566 for (i = 0; i < lasti + 1; i++) {
6567 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6568 continue;
6569
6570 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6571 alu.op = ctx->inst_info->op;
6572 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6573 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6574 if (r)
6575 return r;
6576 }
6577
6578 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6579 alu.dst.chan = i;
6580 alu.dst.write = 1;
6581 alu.is_op3 = 1;
6582 if (i == lasti) {
6583 alu.last = 1;
6584 }
6585 r = r600_bytecode_add_alu(ctx->bc, &alu);
6586 if (r)
6587 return r;
6588 }
6589 return 0;
6590 }
6591
6592 static int tgsi_dp(struct r600_shader_ctx *ctx)
6593 {
6594 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6595 struct r600_bytecode_alu alu;
6596 int i, j, r;
6597
6598 for (i = 0; i < 4; i++) {
6599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6600 alu.op = ctx->inst_info->op;
6601 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6602 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6603 }
6604
6605 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6606 alu.dst.chan = i;
6607 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6608 /* handle some special cases */
6609 switch (inst->Instruction.Opcode) {
6610 case TGSI_OPCODE_DP2:
6611 if (i > 1) {
6612 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6613 alu.src[0].chan = alu.src[1].chan = 0;
6614 }
6615 break;
6616 case TGSI_OPCODE_DP3:
6617 if (i > 2) {
6618 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6619 alu.src[0].chan = alu.src[1].chan = 0;
6620 }
6621 break;
6622 case TGSI_OPCODE_DPH:
6623 if (i == 3) {
6624 alu.src[0].sel = V_SQ_ALU_SRC_1;
6625 alu.src[0].chan = 0;
6626 alu.src[0].neg = 0;
6627 }
6628 break;
6629 default:
6630 break;
6631 }
6632 if (i == 3) {
6633 alu.last = 1;
6634 }
6635 r = r600_bytecode_add_alu(ctx->bc, &alu);
6636 if (r)
6637 return r;
6638 }
6639 return 0;
6640 }
6641
6642 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6643 unsigned index)
6644 {
6645 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6646 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6647 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6648 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6649 ctx->src[index].neg || ctx->src[index].abs ||
6650 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
6651 }
6652
6653 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6654 unsigned index)
6655 {
6656 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6657 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6658 }
6659
6660 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6661 {
6662 struct r600_bytecode_vtx vtx;
6663 struct r600_bytecode_alu alu;
6664 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6665 int src_gpr, r, i;
6666 int id = tgsi_tex_get_src_gpr(ctx, 1);
6667
6668 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6669 if (src_requires_loading) {
6670 for (i = 0; i < 4; i++) {
6671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6672 alu.op = ALU_OP1_MOV;
6673 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6674 alu.dst.sel = ctx->temp_reg;
6675 alu.dst.chan = i;
6676 if (i == 3)
6677 alu.last = 1;
6678 alu.dst.write = 1;
6679 r = r600_bytecode_add_alu(ctx->bc, &alu);
6680 if (r)
6681 return r;
6682 }
6683 src_gpr = ctx->temp_reg;
6684 }
6685
6686 memset(&vtx, 0, sizeof(vtx));
6687 vtx.op = FETCH_OP_VFETCH;
6688 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6689 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6690 vtx.src_gpr = src_gpr;
6691 vtx.mega_fetch_count = 16;
6692 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6693 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6694 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6695 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6696 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6697 vtx.use_const_fields = 1;
6698
6699 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6700 return r;
6701
6702 if (ctx->bc->chip_class >= EVERGREEN)
6703 return 0;
6704
6705 for (i = 0; i < 4; i++) {
6706 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6707 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6708 continue;
6709
6710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6711 alu.op = ALU_OP2_AND_INT;
6712
6713 alu.dst.chan = i;
6714 alu.dst.sel = vtx.dst_gpr;
6715 alu.dst.write = 1;
6716
6717 alu.src[0].sel = vtx.dst_gpr;
6718 alu.src[0].chan = i;
6719
6720 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6721 alu.src[1].sel += (id * 2);
6722 alu.src[1].chan = i % 4;
6723 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6724
6725 if (i == lasti)
6726 alu.last = 1;
6727 r = r600_bytecode_add_alu(ctx->bc, &alu);
6728 if (r)
6729 return r;
6730 }
6731
6732 if (inst->Dst[0].Register.WriteMask & 3) {
6733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6734 alu.op = ALU_OP2_OR_INT;
6735
6736 alu.dst.chan = 3;
6737 alu.dst.sel = vtx.dst_gpr;
6738 alu.dst.write = 1;
6739
6740 alu.src[0].sel = vtx.dst_gpr;
6741 alu.src[0].chan = 3;
6742
6743 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6744 alu.src[1].chan = 0;
6745 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6746
6747 alu.last = 1;
6748 r = r600_bytecode_add_alu(ctx->bc, &alu);
6749 if (r)
6750 return r;
6751 }
6752 return 0;
6753 }
6754
6755 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6756 {
6757 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6758 struct r600_bytecode_alu alu;
6759 int r;
6760 int id = tgsi_tex_get_src_gpr(ctx, 1);
6761
6762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6763 alu.op = ALU_OP1_MOV;
6764 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6765 if (ctx->bc->chip_class >= EVERGREEN) {
6766 /* channel 0 or 2 of each word */
6767 alu.src[0].sel += (id / 2);
6768 alu.src[0].chan = (id % 2) * 2;
6769 } else {
6770 /* r600 we have them at channel 2 of the second dword */
6771 alu.src[0].sel += (id * 2) + 1;
6772 alu.src[0].chan = 1;
6773 }
6774 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6775 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6776 alu.last = 1;
6777 r = r600_bytecode_add_alu(ctx->bc, &alu);
6778 if (r)
6779 return r;
6780 return 0;
6781 }
6782
6783 static int tgsi_tex(struct r600_shader_ctx *ctx)
6784 {
6785 static float one_point_five = 1.5f;
6786 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6787 struct r600_bytecode_tex tex;
6788 struct r600_bytecode_alu alu;
6789 unsigned src_gpr;
6790 int r, i, j;
6791 int opcode;
6792 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6793 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6794 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6795 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6796
6797 bool txf_add_offsets = inst->Texture.NumOffsets &&
6798 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6799 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6800
6801 /* Texture fetch instructions can only use gprs as source.
6802 * Also they cannot negate the source or take the absolute value */
6803 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
6804 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6805 tgsi_tex_src_requires_loading(ctx, 0)) ||
6806 read_compressed_msaa || txf_add_offsets;
6807
6808 boolean src_loaded = FALSE;
6809 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
6810 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6811 boolean has_txq_cube_array_z = false;
6812 unsigned sampler_index_mode;
6813
6814 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6815 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6816 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6817 if (inst->Dst[0].Register.WriteMask & 4) {
6818 ctx->shader->has_txq_cube_array_z_comp = true;
6819 has_txq_cube_array_z = true;
6820 }
6821
6822 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6823 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6824 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6825 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6826 sampler_src_reg = 2;
6827
6828 /* TGSI moves the sampler to src reg 3 for TXD */
6829 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6830 sampler_src_reg = 3;
6831
6832 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6833
6834 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6835
6836 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6837 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6838 ctx->shader->uses_tex_buffers = true;
6839 return r600_do_buffer_txq(ctx);
6840 }
6841 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6842 if (ctx->bc->chip_class < EVERGREEN)
6843 ctx->shader->uses_tex_buffers = true;
6844 return do_vtx_fetch_inst(ctx, src_requires_loading);
6845 }
6846 }
6847
6848 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6849 int out_chan;
6850 /* Add perspective divide */
6851 if (ctx->bc->chip_class == CAYMAN) {
6852 out_chan = 2;
6853 for (i = 0; i < 3; i++) {
6854 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6855 alu.op = ALU_OP1_RECIP_IEEE;
6856 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6857
6858 alu.dst.sel = ctx->temp_reg;
6859 alu.dst.chan = i;
6860 if (i == 2)
6861 alu.last = 1;
6862 if (out_chan == i)
6863 alu.dst.write = 1;
6864 r = r600_bytecode_add_alu(ctx->bc, &alu);
6865 if (r)
6866 return r;
6867 }
6868
6869 } else {
6870 out_chan = 3;
6871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6872 alu.op = ALU_OP1_RECIP_IEEE;
6873 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6874
6875 alu.dst.sel = ctx->temp_reg;
6876 alu.dst.chan = out_chan;
6877 alu.last = 1;
6878 alu.dst.write = 1;
6879 r = r600_bytecode_add_alu(ctx->bc, &alu);
6880 if (r)
6881 return r;
6882 }
6883
6884 for (i = 0; i < 3; i++) {
6885 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6886 alu.op = ALU_OP2_MUL;
6887 alu.src[0].sel = ctx->temp_reg;
6888 alu.src[0].chan = out_chan;
6889 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6890 alu.dst.sel = ctx->temp_reg;
6891 alu.dst.chan = i;
6892 alu.dst.write = 1;
6893 r = r600_bytecode_add_alu(ctx->bc, &alu);
6894 if (r)
6895 return r;
6896 }
6897 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6898 alu.op = ALU_OP1_MOV;
6899 alu.src[0].sel = V_SQ_ALU_SRC_1;
6900 alu.src[0].chan = 0;
6901 alu.dst.sel = ctx->temp_reg;
6902 alu.dst.chan = 3;
6903 alu.last = 1;
6904 alu.dst.write = 1;
6905 r = r600_bytecode_add_alu(ctx->bc, &alu);
6906 if (r)
6907 return r;
6908 src_loaded = TRUE;
6909 src_gpr = ctx->temp_reg;
6910 }
6911
6912
6913 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6914 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6915 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6916 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6917 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
6918 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
6919
6920 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6921 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6922
6923 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6924 for (i = 0; i < 4; i++) {
6925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6926 alu.op = ALU_OP2_CUBE;
6927 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6928 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6929 alu.dst.sel = ctx->temp_reg;
6930 alu.dst.chan = i;
6931 if (i == 3)
6932 alu.last = 1;
6933 alu.dst.write = 1;
6934 r = r600_bytecode_add_alu(ctx->bc, &alu);
6935 if (r)
6936 return r;
6937 }
6938
6939 /* tmp1.z = RCP_e(|tmp1.z|) */
6940 if (ctx->bc->chip_class == CAYMAN) {
6941 for (i = 0; i < 3; i++) {
6942 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6943 alu.op = ALU_OP1_RECIP_IEEE;
6944 alu.src[0].sel = ctx->temp_reg;
6945 alu.src[0].chan = 2;
6946 alu.src[0].abs = 1;
6947 alu.dst.sel = ctx->temp_reg;
6948 alu.dst.chan = i;
6949 if (i == 2)
6950 alu.dst.write = 1;
6951 if (i == 2)
6952 alu.last = 1;
6953 r = r600_bytecode_add_alu(ctx->bc, &alu);
6954 if (r)
6955 return r;
6956 }
6957 } else {
6958 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6959 alu.op = ALU_OP1_RECIP_IEEE;
6960 alu.src[0].sel = ctx->temp_reg;
6961 alu.src[0].chan = 2;
6962 alu.src[0].abs = 1;
6963 alu.dst.sel = ctx->temp_reg;
6964 alu.dst.chan = 2;
6965 alu.dst.write = 1;
6966 alu.last = 1;
6967 r = r600_bytecode_add_alu(ctx->bc, &alu);
6968 if (r)
6969 return r;
6970 }
6971
6972 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6973 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6974 * muladd has no writemask, have to use another temp
6975 */
6976 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6977 alu.op = ALU_OP3_MULADD;
6978 alu.is_op3 = 1;
6979
6980 alu.src[0].sel = ctx->temp_reg;
6981 alu.src[0].chan = 0;
6982 alu.src[1].sel = ctx->temp_reg;
6983 alu.src[1].chan = 2;
6984
6985 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6986 alu.src[2].chan = 0;
6987 alu.src[2].value = *(uint32_t *)&one_point_five;
6988
6989 alu.dst.sel = ctx->temp_reg;
6990 alu.dst.chan = 0;
6991 alu.dst.write = 1;
6992
6993 r = r600_bytecode_add_alu(ctx->bc, &alu);
6994 if (r)
6995 return r;
6996
6997 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6998 alu.op = ALU_OP3_MULADD;
6999 alu.is_op3 = 1;
7000
7001 alu.src[0].sel = ctx->temp_reg;
7002 alu.src[0].chan = 1;
7003 alu.src[1].sel = ctx->temp_reg;
7004 alu.src[1].chan = 2;
7005
7006 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7007 alu.src[2].chan = 0;
7008 alu.src[2].value = *(uint32_t *)&one_point_five;
7009
7010 alu.dst.sel = ctx->temp_reg;
7011 alu.dst.chan = 1;
7012 alu.dst.write = 1;
7013
7014 alu.last = 1;
7015 r = r600_bytecode_add_alu(ctx->bc, &alu);
7016 if (r)
7017 return r;
7018 /* write initial compare value into Z component
7019 - W src 0 for shadow cube
7020 - X src 1 for shadow cube array */
7021 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7022 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7024 alu.op = ALU_OP1_MOV;
7025 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7026 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7027 else
7028 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7029 alu.dst.sel = ctx->temp_reg;
7030 alu.dst.chan = 2;
7031 alu.dst.write = 1;
7032 alu.last = 1;
7033 r = r600_bytecode_add_alu(ctx->bc, &alu);
7034 if (r)
7035 return r;
7036 }
7037
7038 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7039 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7040 if (ctx->bc->chip_class >= EVERGREEN) {
7041 int mytmp = r600_get_temp(ctx);
7042 static const float eight = 8.0f;
7043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7044 alu.op = ALU_OP1_MOV;
7045 alu.src[0].sel = ctx->temp_reg;
7046 alu.src[0].chan = 3;
7047 alu.dst.sel = mytmp;
7048 alu.dst.chan = 0;
7049 alu.dst.write = 1;
7050 alu.last = 1;
7051 r = r600_bytecode_add_alu(ctx->bc, &alu);
7052 if (r)
7053 return r;
7054
7055 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7056 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7057 alu.op = ALU_OP3_MULADD;
7058 alu.is_op3 = 1;
7059 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7060 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7061 alu.src[1].chan = 0;
7062 alu.src[1].value = *(uint32_t *)&eight;
7063 alu.src[2].sel = mytmp;
7064 alu.src[2].chan = 0;
7065 alu.dst.sel = ctx->temp_reg;
7066 alu.dst.chan = 3;
7067 alu.dst.write = 1;
7068 alu.last = 1;
7069 r = r600_bytecode_add_alu(ctx->bc, &alu);
7070 if (r)
7071 return r;
7072 } else if (ctx->bc->chip_class < EVERGREEN) {
7073 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7074 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7075 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7076 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7077 tex.src_gpr = r600_get_temp(ctx);
7078 tex.src_sel_x = 0;
7079 tex.src_sel_y = 0;
7080 tex.src_sel_z = 0;
7081 tex.src_sel_w = 0;
7082 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7083 tex.coord_type_x = 1;
7084 tex.coord_type_y = 1;
7085 tex.coord_type_z = 1;
7086 tex.coord_type_w = 1;
7087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7088 alu.op = ALU_OP1_MOV;
7089 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7090 alu.dst.sel = tex.src_gpr;
7091 alu.dst.chan = 0;
7092 alu.last = 1;
7093 alu.dst.write = 1;
7094 r = r600_bytecode_add_alu(ctx->bc, &alu);
7095 if (r)
7096 return r;
7097
7098 r = r600_bytecode_add_tex(ctx->bc, &tex);
7099 if (r)
7100 return r;
7101 }
7102
7103 }
7104
7105 /* for cube forms of lod and bias we need to route things */
7106 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7107 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7108 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7109 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7110 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7111 alu.op = ALU_OP1_MOV;
7112 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7113 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7114 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7115 else
7116 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7117 alu.dst.sel = ctx->temp_reg;
7118 alu.dst.chan = 2;
7119 alu.last = 1;
7120 alu.dst.write = 1;
7121 r = r600_bytecode_add_alu(ctx->bc, &alu);
7122 if (r)
7123 return r;
7124 }
7125
7126 src_loaded = TRUE;
7127 src_gpr = ctx->temp_reg;
7128 }
7129
7130 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7131 int temp_h = 0, temp_v = 0;
7132 int start_val = 0;
7133
7134 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7135 if (src_loaded == TRUE)
7136 start_val = 1;
7137 else
7138 src_loaded = TRUE;
7139 for (i = start_val; i < 3; i++) {
7140 int treg = r600_get_temp(ctx);
7141
7142 if (i == 0)
7143 src_gpr = treg;
7144 else if (i == 1)
7145 temp_h = treg;
7146 else
7147 temp_v = treg;
7148
7149 for (j = 0; j < 4; j++) {
7150 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7151 alu.op = ALU_OP1_MOV;
7152 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7153 alu.dst.sel = treg;
7154 alu.dst.chan = j;
7155 if (j == 3)
7156 alu.last = 1;
7157 alu.dst.write = 1;
7158 r = r600_bytecode_add_alu(ctx->bc, &alu);
7159 if (r)
7160 return r;
7161 }
7162 }
7163 for (i = 1; i < 3; i++) {
7164 /* set gradients h/v */
7165 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7166 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7167 FETCH_OP_SET_GRADIENTS_V;
7168 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7169 tex.sampler_index_mode = sampler_index_mode;
7170 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7171 tex.resource_index_mode = sampler_index_mode;
7172
7173 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7174 tex.src_sel_x = 0;
7175 tex.src_sel_y = 1;
7176 tex.src_sel_z = 2;
7177 tex.src_sel_w = 3;
7178
7179 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7180 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7181 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7182 tex.coord_type_x = 1;
7183 tex.coord_type_y = 1;
7184 tex.coord_type_z = 1;
7185 tex.coord_type_w = 1;
7186 }
7187 r = r600_bytecode_add_tex(ctx->bc, &tex);
7188 if (r)
7189 return r;
7190 }
7191 }
7192
7193 if (src_requires_loading && !src_loaded) {
7194 for (i = 0; i < 4; i++) {
7195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7196 alu.op = ALU_OP1_MOV;
7197 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7198 alu.dst.sel = ctx->temp_reg;
7199 alu.dst.chan = i;
7200 if (i == 3)
7201 alu.last = 1;
7202 alu.dst.write = 1;
7203 r = r600_bytecode_add_alu(ctx->bc, &alu);
7204 if (r)
7205 return r;
7206 }
7207 src_loaded = TRUE;
7208 src_gpr = ctx->temp_reg;
7209 }
7210
7211 /* get offset values */
7212 if (inst->Texture.NumOffsets) {
7213 assert(inst->Texture.NumOffsets == 1);
7214
7215 /* The texture offset feature doesn't work with the TXF instruction
7216 * and must be emulated by adding the offset to the texture coordinates. */
7217 if (txf_add_offsets) {
7218 const struct tgsi_texture_offset *off = inst->TexOffsets;
7219
7220 switch (inst->Texture.Texture) {
7221 case TGSI_TEXTURE_3D:
7222 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7223 alu.op = ALU_OP2_ADD_INT;
7224 alu.src[0].sel = src_gpr;
7225 alu.src[0].chan = 2;
7226 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7227 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7228 alu.dst.sel = src_gpr;
7229 alu.dst.chan = 2;
7230 alu.dst.write = 1;
7231 alu.last = 1;
7232 r = r600_bytecode_add_alu(ctx->bc, &alu);
7233 if (r)
7234 return r;
7235 /* fall through */
7236
7237 case TGSI_TEXTURE_2D:
7238 case TGSI_TEXTURE_SHADOW2D:
7239 case TGSI_TEXTURE_RECT:
7240 case TGSI_TEXTURE_SHADOWRECT:
7241 case TGSI_TEXTURE_2D_ARRAY:
7242 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7243 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7244 alu.op = ALU_OP2_ADD_INT;
7245 alu.src[0].sel = src_gpr;
7246 alu.src[0].chan = 1;
7247 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7248 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7249 alu.dst.sel = src_gpr;
7250 alu.dst.chan = 1;
7251 alu.dst.write = 1;
7252 alu.last = 1;
7253 r = r600_bytecode_add_alu(ctx->bc, &alu);
7254 if (r)
7255 return r;
7256 /* fall through */
7257
7258 case TGSI_TEXTURE_1D:
7259 case TGSI_TEXTURE_SHADOW1D:
7260 case TGSI_TEXTURE_1D_ARRAY:
7261 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7262 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7263 alu.op = ALU_OP2_ADD_INT;
7264 alu.src[0].sel = src_gpr;
7265 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7266 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7267 alu.dst.sel = src_gpr;
7268 alu.dst.write = 1;
7269 alu.last = 1;
7270 r = r600_bytecode_add_alu(ctx->bc, &alu);
7271 if (r)
7272 return r;
7273 break;
7274 /* texture offsets do not apply to other texture targets */
7275 }
7276 } else {
7277 switch (inst->Texture.Texture) {
7278 case TGSI_TEXTURE_3D:
7279 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7280 /* fallthrough */
7281 case TGSI_TEXTURE_2D:
7282 case TGSI_TEXTURE_SHADOW2D:
7283 case TGSI_TEXTURE_RECT:
7284 case TGSI_TEXTURE_SHADOWRECT:
7285 case TGSI_TEXTURE_2D_ARRAY:
7286 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7287 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7288 /* fallthrough */
7289 case TGSI_TEXTURE_1D:
7290 case TGSI_TEXTURE_SHADOW1D:
7291 case TGSI_TEXTURE_1D_ARRAY:
7292 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7293 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7294 }
7295 }
7296 }
7297
7298 /* Obtain the sample index for reading a compressed MSAA color texture.
7299 * To read the FMASK, we use the ldfptr instruction, which tells us
7300 * where the samples are stored.
7301 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7302 * which is the identity mapping. Each nibble says which physical sample
7303 * should be fetched to get that sample.
7304 *
7305 * Assume src.z contains the sample index. It should be modified like this:
7306 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7307 * Then fetch the texel with src.
7308 */
7309 if (read_compressed_msaa) {
7310 unsigned sample_chan = 3;
7311 unsigned temp = r600_get_temp(ctx);
7312 assert(src_loaded);
7313
7314 /* temp.w = ldfptr() */
7315 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7316 tex.op = FETCH_OP_LD;
7317 tex.inst_mod = 1; /* to indicate this is ldfptr */
7318 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7319 tex.sampler_index_mode = sampler_index_mode;
7320 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7321 tex.resource_index_mode = sampler_index_mode;
7322 tex.src_gpr = src_gpr;
7323 tex.dst_gpr = temp;
7324 tex.dst_sel_x = 7; /* mask out these components */
7325 tex.dst_sel_y = 7;
7326 tex.dst_sel_z = 7;
7327 tex.dst_sel_w = 0; /* store X */
7328 tex.src_sel_x = 0;
7329 tex.src_sel_y = 1;
7330 tex.src_sel_z = 2;
7331 tex.src_sel_w = 3;
7332 tex.offset_x = offset_x;
7333 tex.offset_y = offset_y;
7334 tex.offset_z = offset_z;
7335 r = r600_bytecode_add_tex(ctx->bc, &tex);
7336 if (r)
7337 return r;
7338
7339 /* temp.x = sample_index*4 */
7340 if (ctx->bc->chip_class == CAYMAN) {
7341 for (i = 0 ; i < 4; i++) {
7342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7343 alu.op = ALU_OP2_MULLO_INT;
7344 alu.src[0].sel = src_gpr;
7345 alu.src[0].chan = sample_chan;
7346 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7347 alu.src[1].value = 4;
7348 alu.dst.sel = temp;
7349 alu.dst.chan = i;
7350 alu.dst.write = i == 0;
7351 if (i == 3)
7352 alu.last = 1;
7353 r = r600_bytecode_add_alu(ctx->bc, &alu);
7354 if (r)
7355 return r;
7356 }
7357 } else {
7358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7359 alu.op = ALU_OP2_MULLO_INT;
7360 alu.src[0].sel = src_gpr;
7361 alu.src[0].chan = sample_chan;
7362 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7363 alu.src[1].value = 4;
7364 alu.dst.sel = temp;
7365 alu.dst.chan = 0;
7366 alu.dst.write = 1;
7367 alu.last = 1;
7368 r = r600_bytecode_add_alu(ctx->bc, &alu);
7369 if (r)
7370 return r;
7371 }
7372
7373 /* sample_index = temp.w >> temp.x */
7374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7375 alu.op = ALU_OP2_LSHR_INT;
7376 alu.src[0].sel = temp;
7377 alu.src[0].chan = 3;
7378 alu.src[1].sel = temp;
7379 alu.src[1].chan = 0;
7380 alu.dst.sel = src_gpr;
7381 alu.dst.chan = sample_chan;
7382 alu.dst.write = 1;
7383 alu.last = 1;
7384 r = r600_bytecode_add_alu(ctx->bc, &alu);
7385 if (r)
7386 return r;
7387
7388 /* sample_index & 0xF */
7389 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7390 alu.op = ALU_OP2_AND_INT;
7391 alu.src[0].sel = src_gpr;
7392 alu.src[0].chan = sample_chan;
7393 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7394 alu.src[1].value = 0xF;
7395 alu.dst.sel = src_gpr;
7396 alu.dst.chan = sample_chan;
7397 alu.dst.write = 1;
7398 alu.last = 1;
7399 r = r600_bytecode_add_alu(ctx->bc, &alu);
7400 if (r)
7401 return r;
7402 #if 0
7403 /* visualize the FMASK */
7404 for (i = 0; i < 4; i++) {
7405 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7406 alu.op = ALU_OP1_INT_TO_FLT;
7407 alu.src[0].sel = src_gpr;
7408 alu.src[0].chan = sample_chan;
7409 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7410 alu.dst.chan = i;
7411 alu.dst.write = 1;
7412 alu.last = 1;
7413 r = r600_bytecode_add_alu(ctx->bc, &alu);
7414 if (r)
7415 return r;
7416 }
7417 return 0;
7418 #endif
7419 }
7420
7421 /* does this shader want a num layers from TXQ for a cube array? */
7422 if (has_txq_cube_array_z) {
7423 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7424
7425 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7426 alu.op = ALU_OP1_MOV;
7427
7428 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7429 if (ctx->bc->chip_class >= EVERGREEN) {
7430 /* channel 1 or 3 of each word */
7431 alu.src[0].sel += (id / 2);
7432 alu.src[0].chan = ((id % 2) * 2) + 1;
7433 } else {
7434 /* r600 we have them at channel 2 of the second dword */
7435 alu.src[0].sel += (id * 2) + 1;
7436 alu.src[0].chan = 2;
7437 }
7438 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7439 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7440 alu.last = 1;
7441 r = r600_bytecode_add_alu(ctx->bc, &alu);
7442 if (r)
7443 return r;
7444 /* disable writemask from texture instruction */
7445 inst->Dst[0].Register.WriteMask &= ~4;
7446 }
7447
7448 opcode = ctx->inst_info->op;
7449 if (opcode == FETCH_OP_GATHER4 &&
7450 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7451 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7452 opcode = FETCH_OP_GATHER4_O;
7453
7454 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7455 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7456 encoded in the instruction are ignored. */
7457 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7458 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7459 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7460 tex.sampler_index_mode = sampler_index_mode;
7461 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7462 tex.resource_index_mode = sampler_index_mode;
7463
7464 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7465 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7466 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7467 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7468 tex.src_sel_w = 4;
7469
7470 tex.dst_sel_x = 7;
7471 tex.dst_sel_y = 7;
7472 tex.dst_sel_z = 7;
7473 tex.dst_sel_w = 7;
7474
7475 r = r600_bytecode_add_tex(ctx->bc, &tex);
7476 if (r)
7477 return r;
7478 }
7479
7480 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7481 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7482 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7483 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7484 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7485 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7486 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7487 switch (opcode) {
7488 case FETCH_OP_SAMPLE:
7489 opcode = FETCH_OP_SAMPLE_C;
7490 break;
7491 case FETCH_OP_SAMPLE_L:
7492 opcode = FETCH_OP_SAMPLE_C_L;
7493 break;
7494 case FETCH_OP_SAMPLE_LB:
7495 opcode = FETCH_OP_SAMPLE_C_LB;
7496 break;
7497 case FETCH_OP_SAMPLE_G:
7498 opcode = FETCH_OP_SAMPLE_C_G;
7499 break;
7500 /* Texture gather variants */
7501 case FETCH_OP_GATHER4:
7502 opcode = FETCH_OP_GATHER4_C;
7503 break;
7504 case FETCH_OP_GATHER4_O:
7505 opcode = FETCH_OP_GATHER4_C_O;
7506 break;
7507 }
7508 }
7509
7510 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7511 tex.op = opcode;
7512
7513 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7514 tex.sampler_index_mode = sampler_index_mode;
7515 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7516 tex.resource_index_mode = sampler_index_mode;
7517 tex.src_gpr = src_gpr;
7518 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7519
7520 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7521 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7522 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7523 }
7524
7525 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7526 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7527 tex.inst_mod = texture_component_select;
7528
7529 if (ctx->bc->chip_class == CAYMAN) {
7530 /* GATHER4 result order is different from TGSI TG4 */
7531 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7532 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7533 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7534 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7535 } else {
7536 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7537 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7538 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7539 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7540 }
7541 }
7542 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7543 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7544 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7545 tex.dst_sel_z = 7;
7546 tex.dst_sel_w = 7;
7547 }
7548 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7549 tex.dst_sel_x = 3;
7550 tex.dst_sel_y = 7;
7551 tex.dst_sel_z = 7;
7552 tex.dst_sel_w = 7;
7553 }
7554 else {
7555 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7556 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7557 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7558 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7559 }
7560
7561
7562 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
7563 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7564 tex.src_sel_x = 4;
7565 tex.src_sel_y = 4;
7566 tex.src_sel_z = 4;
7567 tex.src_sel_w = 4;
7568 } else if (src_loaded) {
7569 tex.src_sel_x = 0;
7570 tex.src_sel_y = 1;
7571 tex.src_sel_z = 2;
7572 tex.src_sel_w = 3;
7573 } else {
7574 tex.src_sel_x = ctx->src[0].swizzle[0];
7575 tex.src_sel_y = ctx->src[0].swizzle[1];
7576 tex.src_sel_z = ctx->src[0].swizzle[2];
7577 tex.src_sel_w = ctx->src[0].swizzle[3];
7578 tex.src_rel = ctx->src[0].rel;
7579 }
7580
7581 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7582 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7583 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7584 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7585 tex.src_sel_x = 1;
7586 tex.src_sel_y = 0;
7587 tex.src_sel_z = 3;
7588 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7589 }
7590
7591 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7592 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7593 tex.coord_type_x = 1;
7594 tex.coord_type_y = 1;
7595 }
7596 tex.coord_type_z = 1;
7597 tex.coord_type_w = 1;
7598
7599 tex.offset_x = offset_x;
7600 tex.offset_y = offset_y;
7601 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7602 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7603 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7604 tex.offset_z = 0;
7605 }
7606 else {
7607 tex.offset_z = offset_z;
7608 }
7609
7610 /* Put the depth for comparison in W.
7611 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7612 * Some instructions expect the depth in Z. */
7613 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7614 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7615 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7616 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7617 opcode != FETCH_OP_SAMPLE_C_L &&
7618 opcode != FETCH_OP_SAMPLE_C_LB) {
7619 tex.src_sel_w = tex.src_sel_z;
7620 }
7621
7622 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7623 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7624 if (opcode == FETCH_OP_SAMPLE_C_L ||
7625 opcode == FETCH_OP_SAMPLE_C_LB) {
7626 /* the array index is read from Y */
7627 tex.coord_type_y = 0;
7628 } else {
7629 /* the array index is read from Z */
7630 tex.coord_type_z = 0;
7631 tex.src_sel_z = tex.src_sel_y;
7632 }
7633 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7634 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7635 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7636 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7637 (ctx->bc->chip_class >= EVERGREEN)))
7638 /* the array index is read from Z */
7639 tex.coord_type_z = 0;
7640
7641 /* mask unused source components */
7642 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7643 switch (inst->Texture.Texture) {
7644 case TGSI_TEXTURE_2D:
7645 case TGSI_TEXTURE_RECT:
7646 tex.src_sel_z = 7;
7647 tex.src_sel_w = 7;
7648 break;
7649 case TGSI_TEXTURE_1D_ARRAY:
7650 tex.src_sel_y = 7;
7651 tex.src_sel_w = 7;
7652 break;
7653 case TGSI_TEXTURE_1D:
7654 tex.src_sel_y = 7;
7655 tex.src_sel_z = 7;
7656 tex.src_sel_w = 7;
7657 break;
7658 }
7659 }
7660
7661 r = r600_bytecode_add_tex(ctx->bc, &tex);
7662 if (r)
7663 return r;
7664
7665 /* add shadow ambient support - gallium doesn't do it yet */
7666 return 0;
7667 }
7668
7669 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7670 {
7671 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7672 struct r600_bytecode_alu alu;
7673 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7674 unsigned i, temp_regs[2];
7675 int r;
7676
7677 /* optimize if it's just an equal balance */
7678 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7679 for (i = 0; i < lasti + 1; i++) {
7680 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7681 continue;
7682
7683 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7684 alu.op = ALU_OP2_ADD;
7685 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7686 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7687 alu.omod = 3;
7688 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7689 alu.dst.chan = i;
7690 if (i == lasti) {
7691 alu.last = 1;
7692 }
7693 r = r600_bytecode_add_alu(ctx->bc, &alu);
7694 if (r)
7695 return r;
7696 }
7697 return 0;
7698 }
7699
7700 /* 1 - src0 */
7701 for (i = 0; i < lasti + 1; i++) {
7702 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7703 continue;
7704
7705 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7706 alu.op = ALU_OP2_ADD;
7707 alu.src[0].sel = V_SQ_ALU_SRC_1;
7708 alu.src[0].chan = 0;
7709 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7710 r600_bytecode_src_toggle_neg(&alu.src[1]);
7711 alu.dst.sel = ctx->temp_reg;
7712 alu.dst.chan = i;
7713 if (i == lasti) {
7714 alu.last = 1;
7715 }
7716 alu.dst.write = 1;
7717 r = r600_bytecode_add_alu(ctx->bc, &alu);
7718 if (r)
7719 return r;
7720 }
7721
7722 /* (1 - src0) * src2 */
7723 for (i = 0; i < lasti + 1; i++) {
7724 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7725 continue;
7726
7727 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7728 alu.op = ALU_OP2_MUL;
7729 alu.src[0].sel = ctx->temp_reg;
7730 alu.src[0].chan = i;
7731 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7732 alu.dst.sel = ctx->temp_reg;
7733 alu.dst.chan = i;
7734 if (i == lasti) {
7735 alu.last = 1;
7736 }
7737 alu.dst.write = 1;
7738 r = r600_bytecode_add_alu(ctx->bc, &alu);
7739 if (r)
7740 return r;
7741 }
7742
7743 /* src0 * src1 + (1 - src0) * src2 */
7744 if (ctx->src[0].abs)
7745 temp_regs[0] = r600_get_temp(ctx);
7746 else
7747 temp_regs[0] = 0;
7748 if (ctx->src[1].abs)
7749 temp_regs[1] = r600_get_temp(ctx);
7750 else
7751 temp_regs[1] = 0;
7752
7753 for (i = 0; i < lasti + 1; i++) {
7754 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7755 continue;
7756
7757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7758 alu.op = ALU_OP3_MULADD;
7759 alu.is_op3 = 1;
7760 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7761 if (r)
7762 return r;
7763 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7764 if (r)
7765 return r;
7766 alu.src[2].sel = ctx->temp_reg;
7767 alu.src[2].chan = i;
7768
7769 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7770 alu.dst.chan = i;
7771 if (i == lasti) {
7772 alu.last = 1;
7773 }
7774 r = r600_bytecode_add_alu(ctx->bc, &alu);
7775 if (r)
7776 return r;
7777 }
7778 return 0;
7779 }
7780
7781 static int tgsi_cmp(struct r600_shader_ctx *ctx)
7782 {
7783 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7784 struct r600_bytecode_alu alu;
7785 int i, r, j;
7786 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7787 int temp_regs[3];
7788
7789 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7790 temp_regs[j] = 0;
7791 if (ctx->src[j].abs)
7792 temp_regs[j] = r600_get_temp(ctx);
7793 }
7794
7795 for (i = 0; i < lasti + 1; i++) {
7796 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7797 continue;
7798
7799 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7800 alu.op = ALU_OP3_CNDGE;
7801 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7802 if (r)
7803 return r;
7804 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
7805 if (r)
7806 return r;
7807 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
7808 if (r)
7809 return r;
7810 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7811 alu.dst.chan = i;
7812 alu.dst.write = 1;
7813 alu.is_op3 = 1;
7814 if (i == lasti)
7815 alu.last = 1;
7816 r = r600_bytecode_add_alu(ctx->bc, &alu);
7817 if (r)
7818 return r;
7819 }
7820 return 0;
7821 }
7822
7823 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
7824 {
7825 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7826 struct r600_bytecode_alu alu;
7827 int i, r;
7828 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7829
7830 for (i = 0; i < lasti + 1; i++) {
7831 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7832 continue;
7833
7834 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7835 alu.op = ALU_OP3_CNDE_INT;
7836 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7837 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7838 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
7839 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7840 alu.dst.chan = i;
7841 alu.dst.write = 1;
7842 alu.is_op3 = 1;
7843 if (i == lasti)
7844 alu.last = 1;
7845 r = r600_bytecode_add_alu(ctx->bc, &alu);
7846 if (r)
7847 return r;
7848 }
7849 return 0;
7850 }
7851
7852 static int tgsi_xpd(struct r600_shader_ctx *ctx)
7853 {
7854 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7855 static const unsigned int src0_swizzle[] = {2, 0, 1};
7856 static const unsigned int src1_swizzle[] = {1, 2, 0};
7857 struct r600_bytecode_alu alu;
7858 uint32_t use_temp = 0;
7859 int i, r;
7860
7861 if (inst->Dst[0].Register.WriteMask != 0xf)
7862 use_temp = 1;
7863
7864 for (i = 0; i < 4; i++) {
7865 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7866 alu.op = ALU_OP2_MUL;
7867 if (i < 3) {
7868 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7869 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
7870 } else {
7871 alu.src[0].sel = V_SQ_ALU_SRC_0;
7872 alu.src[0].chan = i;
7873 alu.src[1].sel = V_SQ_ALU_SRC_0;
7874 alu.src[1].chan = i;
7875 }
7876
7877 alu.dst.sel = ctx->temp_reg;
7878 alu.dst.chan = i;
7879 alu.dst.write = 1;
7880
7881 if (i == 3)
7882 alu.last = 1;
7883 r = r600_bytecode_add_alu(ctx->bc, &alu);
7884 if (r)
7885 return r;
7886 }
7887
7888 for (i = 0; i < 4; i++) {
7889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7890 alu.op = ALU_OP3_MULADD;
7891
7892 if (i < 3) {
7893 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
7894 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
7895 } else {
7896 alu.src[0].sel = V_SQ_ALU_SRC_0;
7897 alu.src[0].chan = i;
7898 alu.src[1].sel = V_SQ_ALU_SRC_0;
7899 alu.src[1].chan = i;
7900 }
7901
7902 alu.src[2].sel = ctx->temp_reg;
7903 alu.src[2].neg = 1;
7904 alu.src[2].chan = i;
7905
7906 if (use_temp)
7907 alu.dst.sel = ctx->temp_reg;
7908 else
7909 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7910 alu.dst.chan = i;
7911 alu.dst.write = 1;
7912 alu.is_op3 = 1;
7913 if (i == 3)
7914 alu.last = 1;
7915 r = r600_bytecode_add_alu(ctx->bc, &alu);
7916 if (r)
7917 return r;
7918 }
7919 if (use_temp)
7920 return tgsi_helper_copy(ctx, inst);
7921 return 0;
7922 }
7923
7924 static int tgsi_exp(struct r600_shader_ctx *ctx)
7925 {
7926 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7927 struct r600_bytecode_alu alu;
7928 int r;
7929 int i;
7930
7931 /* result.x = 2^floor(src); */
7932 if (inst->Dst[0].Register.WriteMask & 1) {
7933 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7934
7935 alu.op = ALU_OP1_FLOOR;
7936 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7937
7938 alu.dst.sel = ctx->temp_reg;
7939 alu.dst.chan = 0;
7940 alu.dst.write = 1;
7941 alu.last = 1;
7942 r = r600_bytecode_add_alu(ctx->bc, &alu);
7943 if (r)
7944 return r;
7945
7946 if (ctx->bc->chip_class == CAYMAN) {
7947 for (i = 0; i < 3; i++) {
7948 alu.op = ALU_OP1_EXP_IEEE;
7949 alu.src[0].sel = ctx->temp_reg;
7950 alu.src[0].chan = 0;
7951
7952 alu.dst.sel = ctx->temp_reg;
7953 alu.dst.chan = i;
7954 alu.dst.write = i == 0;
7955 alu.last = i == 2;
7956 r = r600_bytecode_add_alu(ctx->bc, &alu);
7957 if (r)
7958 return r;
7959 }
7960 } else {
7961 alu.op = ALU_OP1_EXP_IEEE;
7962 alu.src[0].sel = ctx->temp_reg;
7963 alu.src[0].chan = 0;
7964
7965 alu.dst.sel = ctx->temp_reg;
7966 alu.dst.chan = 0;
7967 alu.dst.write = 1;
7968 alu.last = 1;
7969 r = r600_bytecode_add_alu(ctx->bc, &alu);
7970 if (r)
7971 return r;
7972 }
7973 }
7974
7975 /* result.y = tmp - floor(tmp); */
7976 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7978
7979 alu.op = ALU_OP1_FRACT;
7980 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7981
7982 alu.dst.sel = ctx->temp_reg;
7983 #if 0
7984 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7985 if (r)
7986 return r;
7987 #endif
7988 alu.dst.write = 1;
7989 alu.dst.chan = 1;
7990
7991 alu.last = 1;
7992
7993 r = r600_bytecode_add_alu(ctx->bc, &alu);
7994 if (r)
7995 return r;
7996 }
7997
7998 /* result.z = RoughApprox2ToX(tmp);*/
7999 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8000 if (ctx->bc->chip_class == CAYMAN) {
8001 for (i = 0; i < 3; i++) {
8002 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8003 alu.op = ALU_OP1_EXP_IEEE;
8004 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8005
8006 alu.dst.sel = ctx->temp_reg;
8007 alu.dst.chan = i;
8008 if (i == 2) {
8009 alu.dst.write = 1;
8010 alu.last = 1;
8011 }
8012
8013 r = r600_bytecode_add_alu(ctx->bc, &alu);
8014 if (r)
8015 return r;
8016 }
8017 } else {
8018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8019 alu.op = ALU_OP1_EXP_IEEE;
8020 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8021
8022 alu.dst.sel = ctx->temp_reg;
8023 alu.dst.write = 1;
8024 alu.dst.chan = 2;
8025
8026 alu.last = 1;
8027
8028 r = r600_bytecode_add_alu(ctx->bc, &alu);
8029 if (r)
8030 return r;
8031 }
8032 }
8033
8034 /* result.w = 1.0;*/
8035 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8037
8038 alu.op = ALU_OP1_MOV;
8039 alu.src[0].sel = V_SQ_ALU_SRC_1;
8040 alu.src[0].chan = 0;
8041
8042 alu.dst.sel = ctx->temp_reg;
8043 alu.dst.chan = 3;
8044 alu.dst.write = 1;
8045 alu.last = 1;
8046 r = r600_bytecode_add_alu(ctx->bc, &alu);
8047 if (r)
8048 return r;
8049 }
8050 return tgsi_helper_copy(ctx, inst);
8051 }
8052
8053 static int tgsi_log(struct r600_shader_ctx *ctx)
8054 {
8055 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8056 struct r600_bytecode_alu alu;
8057 int r;
8058 int i;
8059
8060 /* result.x = floor(log2(|src|)); */
8061 if (inst->Dst[0].Register.WriteMask & 1) {
8062 if (ctx->bc->chip_class == CAYMAN) {
8063 for (i = 0; i < 3; i++) {
8064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8065
8066 alu.op = ALU_OP1_LOG_IEEE;
8067 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8068 r600_bytecode_src_set_abs(&alu.src[0]);
8069
8070 alu.dst.sel = ctx->temp_reg;
8071 alu.dst.chan = i;
8072 if (i == 0)
8073 alu.dst.write = 1;
8074 if (i == 2)
8075 alu.last = 1;
8076 r = r600_bytecode_add_alu(ctx->bc, &alu);
8077 if (r)
8078 return r;
8079 }
8080
8081 } else {
8082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8083
8084 alu.op = ALU_OP1_LOG_IEEE;
8085 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8086 r600_bytecode_src_set_abs(&alu.src[0]);
8087
8088 alu.dst.sel = ctx->temp_reg;
8089 alu.dst.chan = 0;
8090 alu.dst.write = 1;
8091 alu.last = 1;
8092 r = r600_bytecode_add_alu(ctx->bc, &alu);
8093 if (r)
8094 return r;
8095 }
8096
8097 alu.op = ALU_OP1_FLOOR;
8098 alu.src[0].sel = ctx->temp_reg;
8099 alu.src[0].chan = 0;
8100
8101 alu.dst.sel = ctx->temp_reg;
8102 alu.dst.chan = 0;
8103 alu.dst.write = 1;
8104 alu.last = 1;
8105
8106 r = r600_bytecode_add_alu(ctx->bc, &alu);
8107 if (r)
8108 return r;
8109 }
8110
8111 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8112 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8113
8114 if (ctx->bc->chip_class == CAYMAN) {
8115 for (i = 0; i < 3; i++) {
8116 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8117
8118 alu.op = ALU_OP1_LOG_IEEE;
8119 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8120 r600_bytecode_src_set_abs(&alu.src[0]);
8121
8122 alu.dst.sel = ctx->temp_reg;
8123 alu.dst.chan = i;
8124 if (i == 1)
8125 alu.dst.write = 1;
8126 if (i == 2)
8127 alu.last = 1;
8128
8129 r = r600_bytecode_add_alu(ctx->bc, &alu);
8130 if (r)
8131 return r;
8132 }
8133 } else {
8134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8135
8136 alu.op = ALU_OP1_LOG_IEEE;
8137 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8138 r600_bytecode_src_set_abs(&alu.src[0]);
8139
8140 alu.dst.sel = ctx->temp_reg;
8141 alu.dst.chan = 1;
8142 alu.dst.write = 1;
8143 alu.last = 1;
8144
8145 r = r600_bytecode_add_alu(ctx->bc, &alu);
8146 if (r)
8147 return r;
8148 }
8149
8150 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8151
8152 alu.op = ALU_OP1_FLOOR;
8153 alu.src[0].sel = ctx->temp_reg;
8154 alu.src[0].chan = 1;
8155
8156 alu.dst.sel = ctx->temp_reg;
8157 alu.dst.chan = 1;
8158 alu.dst.write = 1;
8159 alu.last = 1;
8160
8161 r = r600_bytecode_add_alu(ctx->bc, &alu);
8162 if (r)
8163 return r;
8164
8165 if (ctx->bc->chip_class == CAYMAN) {
8166 for (i = 0; i < 3; i++) {
8167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8168 alu.op = ALU_OP1_EXP_IEEE;
8169 alu.src[0].sel = ctx->temp_reg;
8170 alu.src[0].chan = 1;
8171
8172 alu.dst.sel = ctx->temp_reg;
8173 alu.dst.chan = i;
8174 if (i == 1)
8175 alu.dst.write = 1;
8176 if (i == 2)
8177 alu.last = 1;
8178
8179 r = r600_bytecode_add_alu(ctx->bc, &alu);
8180 if (r)
8181 return r;
8182 }
8183 } else {
8184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8185 alu.op = ALU_OP1_EXP_IEEE;
8186 alu.src[0].sel = ctx->temp_reg;
8187 alu.src[0].chan = 1;
8188
8189 alu.dst.sel = ctx->temp_reg;
8190 alu.dst.chan = 1;
8191 alu.dst.write = 1;
8192 alu.last = 1;
8193
8194 r = r600_bytecode_add_alu(ctx->bc, &alu);
8195 if (r)
8196 return r;
8197 }
8198
8199 if (ctx->bc->chip_class == CAYMAN) {
8200 for (i = 0; i < 3; i++) {
8201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8202 alu.op = ALU_OP1_RECIP_IEEE;
8203 alu.src[0].sel = ctx->temp_reg;
8204 alu.src[0].chan = 1;
8205
8206 alu.dst.sel = ctx->temp_reg;
8207 alu.dst.chan = i;
8208 if (i == 1)
8209 alu.dst.write = 1;
8210 if (i == 2)
8211 alu.last = 1;
8212
8213 r = r600_bytecode_add_alu(ctx->bc, &alu);
8214 if (r)
8215 return r;
8216 }
8217 } else {
8218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8219 alu.op = ALU_OP1_RECIP_IEEE;
8220 alu.src[0].sel = ctx->temp_reg;
8221 alu.src[0].chan = 1;
8222
8223 alu.dst.sel = ctx->temp_reg;
8224 alu.dst.chan = 1;
8225 alu.dst.write = 1;
8226 alu.last = 1;
8227
8228 r = r600_bytecode_add_alu(ctx->bc, &alu);
8229 if (r)
8230 return r;
8231 }
8232
8233 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8234
8235 alu.op = ALU_OP2_MUL;
8236
8237 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8238 r600_bytecode_src_set_abs(&alu.src[0]);
8239
8240 alu.src[1].sel = ctx->temp_reg;
8241 alu.src[1].chan = 1;
8242
8243 alu.dst.sel = ctx->temp_reg;
8244 alu.dst.chan = 1;
8245 alu.dst.write = 1;
8246 alu.last = 1;
8247
8248 r = r600_bytecode_add_alu(ctx->bc, &alu);
8249 if (r)
8250 return r;
8251 }
8252
8253 /* result.z = log2(|src|);*/
8254 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8255 if (ctx->bc->chip_class == CAYMAN) {
8256 for (i = 0; i < 3; i++) {
8257 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8258
8259 alu.op = ALU_OP1_LOG_IEEE;
8260 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8261 r600_bytecode_src_set_abs(&alu.src[0]);
8262
8263 alu.dst.sel = ctx->temp_reg;
8264 if (i == 2)
8265 alu.dst.write = 1;
8266 alu.dst.chan = i;
8267 if (i == 2)
8268 alu.last = 1;
8269
8270 r = r600_bytecode_add_alu(ctx->bc, &alu);
8271 if (r)
8272 return r;
8273 }
8274 } else {
8275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8276
8277 alu.op = ALU_OP1_LOG_IEEE;
8278 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8279 r600_bytecode_src_set_abs(&alu.src[0]);
8280
8281 alu.dst.sel = ctx->temp_reg;
8282 alu.dst.write = 1;
8283 alu.dst.chan = 2;
8284 alu.last = 1;
8285
8286 r = r600_bytecode_add_alu(ctx->bc, &alu);
8287 if (r)
8288 return r;
8289 }
8290 }
8291
8292 /* result.w = 1.0; */
8293 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8294 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8295
8296 alu.op = ALU_OP1_MOV;
8297 alu.src[0].sel = V_SQ_ALU_SRC_1;
8298 alu.src[0].chan = 0;
8299
8300 alu.dst.sel = ctx->temp_reg;
8301 alu.dst.chan = 3;
8302 alu.dst.write = 1;
8303 alu.last = 1;
8304
8305 r = r600_bytecode_add_alu(ctx->bc, &alu);
8306 if (r)
8307 return r;
8308 }
8309
8310 return tgsi_helper_copy(ctx, inst);
8311 }
8312
8313 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8314 {
8315 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8316 struct r600_bytecode_alu alu;
8317 int r;
8318 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8319 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8320
8321 assert(inst->Dst[0].Register.Index < 3);
8322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8323
8324 switch (inst->Instruction.Opcode) {
8325 case TGSI_OPCODE_ARL:
8326 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8327 break;
8328 case TGSI_OPCODE_ARR:
8329 alu.op = ALU_OP1_FLT_TO_INT;
8330 break;
8331 case TGSI_OPCODE_UARL:
8332 alu.op = ALU_OP1_MOV;
8333 break;
8334 default:
8335 assert(0);
8336 return -1;
8337 }
8338
8339 for (i = 0; i <= lasti; ++i) {
8340 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8341 continue;
8342 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8343 alu.last = i == lasti;
8344 alu.dst.sel = reg;
8345 alu.dst.chan = i;
8346 alu.dst.write = 1;
8347 r = r600_bytecode_add_alu(ctx->bc, &alu);
8348 if (r)
8349 return r;
8350 }
8351
8352 if (inst->Dst[0].Register.Index > 0)
8353 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8354 else
8355 ctx->bc->ar_loaded = 0;
8356
8357 return 0;
8358 }
8359 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8360 {
8361 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8362 struct r600_bytecode_alu alu;
8363 int r;
8364 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8365
8366 switch (inst->Instruction.Opcode) {
8367 case TGSI_OPCODE_ARL:
8368 memset(&alu, 0, sizeof(alu));
8369 alu.op = ALU_OP1_FLOOR;
8370 alu.dst.sel = ctx->bc->ar_reg;
8371 alu.dst.write = 1;
8372 for (i = 0; i <= lasti; ++i) {
8373 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8374 alu.dst.chan = i;
8375 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8376 alu.last = i == lasti;
8377 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8378 return r;
8379 }
8380 }
8381
8382 memset(&alu, 0, sizeof(alu));
8383 alu.op = ALU_OP1_FLT_TO_INT;
8384 alu.src[0].sel = ctx->bc->ar_reg;
8385 alu.dst.sel = ctx->bc->ar_reg;
8386 alu.dst.write = 1;
8387 /* FLT_TO_INT is trans-only on r600/r700 */
8388 alu.last = TRUE;
8389 for (i = 0; i <= lasti; ++i) {
8390 alu.dst.chan = i;
8391 alu.src[0].chan = i;
8392 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8393 return r;
8394 }
8395 break;
8396 case TGSI_OPCODE_ARR:
8397 memset(&alu, 0, sizeof(alu));
8398 alu.op = ALU_OP1_FLT_TO_INT;
8399 alu.dst.sel = ctx->bc->ar_reg;
8400 alu.dst.write = 1;
8401 /* FLT_TO_INT is trans-only on r600/r700 */
8402 alu.last = TRUE;
8403 for (i = 0; i <= lasti; ++i) {
8404 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8405 alu.dst.chan = i;
8406 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8407 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8408 return r;
8409 }
8410 }
8411 break;
8412 case TGSI_OPCODE_UARL:
8413 memset(&alu, 0, sizeof(alu));
8414 alu.op = ALU_OP1_MOV;
8415 alu.dst.sel = ctx->bc->ar_reg;
8416 alu.dst.write = 1;
8417 for (i = 0; i <= lasti; ++i) {
8418 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8419 alu.dst.chan = i;
8420 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8421 alu.last = i == lasti;
8422 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8423 return r;
8424 }
8425 }
8426 break;
8427 default:
8428 assert(0);
8429 return -1;
8430 }
8431
8432 ctx->bc->ar_loaded = 0;
8433 return 0;
8434 }
8435
8436 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8437 {
8438 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8439 struct r600_bytecode_alu alu;
8440 int i, r = 0;
8441
8442 for (i = 0; i < 4; i++) {
8443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8444
8445 alu.op = ALU_OP2_MUL;
8446 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8447
8448 if (i == 0 || i == 3) {
8449 alu.src[0].sel = V_SQ_ALU_SRC_1;
8450 } else {
8451 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8452 }
8453
8454 if (i == 0 || i == 2) {
8455 alu.src[1].sel = V_SQ_ALU_SRC_1;
8456 } else {
8457 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8458 }
8459 if (i == 3)
8460 alu.last = 1;
8461 r = r600_bytecode_add_alu(ctx->bc, &alu);
8462 if (r)
8463 return r;
8464 }
8465 return 0;
8466 }
8467
8468 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8469 {
8470 struct r600_bytecode_alu alu;
8471 int r;
8472
8473 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8474 alu.op = opcode;
8475 alu.execute_mask = 1;
8476 alu.update_pred = 1;
8477
8478 alu.dst.sel = ctx->temp_reg;
8479 alu.dst.write = 1;
8480 alu.dst.chan = 0;
8481
8482 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8483 alu.src[1].sel = V_SQ_ALU_SRC_0;
8484 alu.src[1].chan = 0;
8485
8486 alu.last = 1;
8487
8488 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8489 if (r)
8490 return r;
8491 return 0;
8492 }
8493
8494 static int pops(struct r600_shader_ctx *ctx, int pops)
8495 {
8496 unsigned force_pop = ctx->bc->force_add_cf;
8497
8498 if (!force_pop) {
8499 int alu_pop = 3;
8500 if (ctx->bc->cf_last) {
8501 if (ctx->bc->cf_last->op == CF_OP_ALU)
8502 alu_pop = 0;
8503 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8504 alu_pop = 1;
8505 }
8506 alu_pop += pops;
8507 if (alu_pop == 1) {
8508 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8509 ctx->bc->force_add_cf = 1;
8510 } else if (alu_pop == 2) {
8511 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8512 ctx->bc->force_add_cf = 1;
8513 } else {
8514 force_pop = 1;
8515 }
8516 }
8517
8518 if (force_pop) {
8519 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8520 ctx->bc->cf_last->pop_count = pops;
8521 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8522 }
8523
8524 return 0;
8525 }
8526
8527 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8528 unsigned reason)
8529 {
8530 struct r600_stack_info *stack = &ctx->bc->stack;
8531 unsigned elements, entries;
8532
8533 unsigned entry_size = stack->entry_size;
8534
8535 elements = (stack->loop + stack->push_wqm ) * entry_size;
8536 elements += stack->push;
8537
8538 switch (ctx->bc->chip_class) {
8539 case R600:
8540 case R700:
8541 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8542 * the stack must be reserved to hold the current active/continue
8543 * masks */
8544 if (reason == FC_PUSH_VPM) {
8545 elements += 2;
8546 }
8547 break;
8548
8549 case CAYMAN:
8550 /* r9xx: any stack operation on empty stack consumes 2 additional
8551 * elements */
8552 elements += 2;
8553
8554 /* fallthrough */
8555 /* FIXME: do the two elements added above cover the cases for the
8556 * r8xx+ below? */
8557
8558 case EVERGREEN:
8559 /* r8xx+: 2 extra elements are not always required, but one extra
8560 * element must be added for each of the following cases:
8561 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8562 * stack usage.
8563 * (Currently we don't use ALU_ELSE_AFTER.)
8564 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8565 * PUSH instruction executed.
8566 *
8567 * NOTE: it seems we also need to reserve additional element in some
8568 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8569 * then STACK_SIZE should be 2 instead of 1 */
8570 if (reason == FC_PUSH_VPM) {
8571 elements += 1;
8572 }
8573 break;
8574
8575 default:
8576 assert(0);
8577 break;
8578 }
8579
8580 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8581 * for all chips, so we use 4 in the final formula, not the real entry_size
8582 * for the chip */
8583 entry_size = 4;
8584
8585 entries = (elements + (entry_size - 1)) / entry_size;
8586
8587 if (entries > stack->max_entries)
8588 stack->max_entries = entries;
8589 }
8590
8591 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8592 {
8593 switch(reason) {
8594 case FC_PUSH_VPM:
8595 --ctx->bc->stack.push;
8596 assert(ctx->bc->stack.push >= 0);
8597 break;
8598 case FC_PUSH_WQM:
8599 --ctx->bc->stack.push_wqm;
8600 assert(ctx->bc->stack.push_wqm >= 0);
8601 break;
8602 case FC_LOOP:
8603 --ctx->bc->stack.loop;
8604 assert(ctx->bc->stack.loop >= 0);
8605 break;
8606 default:
8607 assert(0);
8608 break;
8609 }
8610 }
8611
8612 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8613 {
8614 switch (reason) {
8615 case FC_PUSH_VPM:
8616 ++ctx->bc->stack.push;
8617 break;
8618 case FC_PUSH_WQM:
8619 ++ctx->bc->stack.push_wqm;
8620 case FC_LOOP:
8621 ++ctx->bc->stack.loop;
8622 break;
8623 default:
8624 assert(0);
8625 }
8626
8627 callstack_update_max_depth(ctx, reason);
8628 }
8629
8630 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8631 {
8632 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8633
8634 sp->mid = realloc((void *)sp->mid,
8635 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8636 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8637 sp->num_mid++;
8638 }
8639
8640 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8641 {
8642 ctx->bc->fc_sp++;
8643 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8644 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8645 }
8646
8647 static void fc_poplevel(struct r600_shader_ctx *ctx)
8648 {
8649 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
8650 free(sp->mid);
8651 sp->mid = NULL;
8652 sp->num_mid = 0;
8653 sp->start = NULL;
8654 sp->type = 0;
8655 ctx->bc->fc_sp--;
8656 }
8657
8658 #if 0
8659 static int emit_return(struct r600_shader_ctx *ctx)
8660 {
8661 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8662 return 0;
8663 }
8664
8665 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8666 {
8667
8668 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8669 ctx->bc->cf_last->pop_count = pops;
8670 /* XXX work out offset */
8671 return 0;
8672 }
8673
8674 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8675 {
8676 return 0;
8677 }
8678
8679 static void emit_testflag(struct r600_shader_ctx *ctx)
8680 {
8681
8682 }
8683
8684 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8685 {
8686 emit_testflag(ctx);
8687 emit_jump_to_offset(ctx, 1, 4);
8688 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8689 pops(ctx, ifidx + 1);
8690 emit_return(ctx);
8691 }
8692
8693 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8694 {
8695 emit_testflag(ctx);
8696
8697 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8698 ctx->bc->cf_last->pop_count = 1;
8699
8700 fc_set_mid(ctx, fc_sp);
8701
8702 pops(ctx, 1);
8703 }
8704 #endif
8705
8706 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8707 {
8708 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8709
8710 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8711 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8712 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8713 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8714 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8715 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8716 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8717 alu_type = CF_OP_ALU;
8718 }
8719
8720 emit_logic_pred(ctx, opcode, alu_type);
8721
8722 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8723
8724 fc_pushlevel(ctx, FC_IF);
8725
8726 callstack_push(ctx, FC_PUSH_VPM);
8727 return 0;
8728 }
8729
8730 static int tgsi_if(struct r600_shader_ctx *ctx)
8731 {
8732 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8733 }
8734
8735 static int tgsi_uif(struct r600_shader_ctx *ctx)
8736 {
8737 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8738 }
8739
8740 static int tgsi_else(struct r600_shader_ctx *ctx)
8741 {
8742 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8743 ctx->bc->cf_last->pop_count = 1;
8744
8745 fc_set_mid(ctx, ctx->bc->fc_sp);
8746 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
8747 return 0;
8748 }
8749
8750 static int tgsi_endif(struct r600_shader_ctx *ctx)
8751 {
8752 pops(ctx, 1);
8753 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
8754 R600_ERR("if/endif unbalanced in shader\n");
8755 return -1;
8756 }
8757
8758 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
8759 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8760 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
8761 } else {
8762 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8763 }
8764 fc_poplevel(ctx);
8765
8766 callstack_pop(ctx, FC_PUSH_VPM);
8767 return 0;
8768 }
8769
8770 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8771 {
8772 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8773 * limited to 4096 iterations, like the other LOOP_* instructions. */
8774 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8775
8776 fc_pushlevel(ctx, FC_LOOP);
8777
8778 /* check stack depth */
8779 callstack_push(ctx, FC_LOOP);
8780 return 0;
8781 }
8782
8783 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8784 {
8785 int i;
8786
8787 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8788
8789 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
8790 R600_ERR("loop/endloop in shader code are not paired.\n");
8791 return -EINVAL;
8792 }
8793
8794 /* fixup loop pointers - from r600isa
8795 LOOP END points to CF after LOOP START,
8796 LOOP START point to CF after LOOP END
8797 BRK/CONT point to LOOP END CF
8798 */
8799 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
8800
8801 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
8802
8803 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
8804 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
8805 }
8806 /* XXX add LOOPRET support */
8807 fc_poplevel(ctx);
8808 callstack_pop(ctx, FC_LOOP);
8809 return 0;
8810 }
8811
8812 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
8813 {
8814 int r;
8815 unsigned int fscp;
8816
8817 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8818 {
8819 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8820 break;
8821 }
8822 if (fscp == 0) {
8823 R600_ERR("BREAKC not inside loop/endloop pair\n");
8824 return -EINVAL;
8825 }
8826
8827 if (ctx->bc->chip_class == EVERGREEN &&
8828 ctx->bc->family != CHIP_CYPRESS &&
8829 ctx->bc->family != CHIP_JUNIPER) {
8830 /* HW bug: ALU_BREAK does not save the active mask correctly */
8831 r = tgsi_uif(ctx);
8832 if (r)
8833 return r;
8834
8835 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
8836 if (r)
8837 return r;
8838 fc_set_mid(ctx, fscp);
8839
8840 return tgsi_endif(ctx);
8841 } else {
8842 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
8843 if (r)
8844 return r;
8845 fc_set_mid(ctx, fscp);
8846 }
8847
8848 return 0;
8849 }
8850
8851 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8852 {
8853 unsigned int fscp;
8854
8855 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8856 {
8857 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
8858 break;
8859 }
8860
8861 if (fscp == 0) {
8862 R600_ERR("Break not inside loop/endloop pair\n");
8863 return -EINVAL;
8864 }
8865
8866 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8867
8868 fc_set_mid(ctx, fscp);
8869
8870 return 0;
8871 }
8872
8873 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8874 {
8875 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8876 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8877 int r;
8878
8879 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8880 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
8881
8882 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8883 if (!r) {
8884 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
8885 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8886 return emit_inc_ring_offset(ctx, stream, TRUE);
8887 }
8888 return r;
8889 }
8890
8891 static int tgsi_umad(struct r600_shader_ctx *ctx)
8892 {
8893 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8894 struct r600_bytecode_alu alu;
8895 int i, j, k, r;
8896 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8897
8898 /* src0 * src1 */
8899 for (i = 0; i < lasti + 1; i++) {
8900 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8901 continue;
8902
8903 if (ctx->bc->chip_class == CAYMAN) {
8904 for (j = 0 ; j < 4; j++) {
8905 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8906
8907 alu.op = ALU_OP2_MULLO_UINT;
8908 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
8909 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
8910 }
8911 alu.dst.chan = j;
8912 alu.dst.sel = ctx->temp_reg;
8913 alu.dst.write = (j == i);
8914 if (j == 3)
8915 alu.last = 1;
8916 r = r600_bytecode_add_alu(ctx->bc, &alu);
8917 if (r)
8918 return r;
8919 }
8920 } else {
8921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8922
8923 alu.dst.chan = i;
8924 alu.dst.sel = ctx->temp_reg;
8925 alu.dst.write = 1;
8926
8927 alu.op = ALU_OP2_MULLO_UINT;
8928 for (j = 0; j < 2; j++) {
8929 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
8930 }
8931
8932 alu.last = 1;
8933 r = r600_bytecode_add_alu(ctx->bc, &alu);
8934 if (r)
8935 return r;
8936 }
8937 }
8938
8939
8940 for (i = 0; i < lasti + 1; i++) {
8941 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8942 continue;
8943
8944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8945 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8946
8947 alu.op = ALU_OP2_ADD_INT;
8948
8949 alu.src[0].sel = ctx->temp_reg;
8950 alu.src[0].chan = i;
8951
8952 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8953 if (i == lasti) {
8954 alu.last = 1;
8955 }
8956 r = r600_bytecode_add_alu(ctx->bc, &alu);
8957 if (r)
8958 return r;
8959 }
8960 return 0;
8961 }
8962
8963 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
8964 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
8965 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8966 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8967
8968 /* XXX:
8969 * For state trackers other than OpenGL, we'll want to use
8970 * _RECIP_IEEE instead.
8971 */
8972 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
8973
8974 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
8975 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8976 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8977 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8978 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8979 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8980 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8981 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8982 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8983 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8984 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8985 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8986 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8987 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8988 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8989 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8990 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
8991 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8992 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8993 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8994 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8995 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8996 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8997 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8998 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
8999 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9000 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9001 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9002 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9003 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
9004 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9005 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9006 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9007 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9008 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9009 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9010 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9011 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9012 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9013 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9014 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9015 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9016 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9017 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9018 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9019 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9020 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9021 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9022 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9023 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9024 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9025 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9026 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9027 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9028 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9029 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9030 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9031 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9032 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9033 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9034 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9035 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9036 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9037 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9038 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9039 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9040 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9041 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9042 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9043 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9044 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9045 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9046 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9047 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9048 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9049 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9050 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9051 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9052 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9053 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9054 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9055 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9056 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9057 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9058 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9059 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9060 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9061 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9062 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9063 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9064 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9065 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9066 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9067 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9068 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9069 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9070 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9071 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9072 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9073 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9074 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9075 [105] = { ALU_OP0_NOP, tgsi_unsupported},
9076 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9077 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9078 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9079 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9080 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9081 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9082 [112] = { ALU_OP0_NOP, tgsi_unsupported},
9083 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9084 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9085 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
9086 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9087 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9088 [118] = { ALU_OP0_NOP, tgsi_unsupported},
9089 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9090 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9091 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9092 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9093 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9094 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9095 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9096 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9097 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9098 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9099 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9100 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9101 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9102 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9103 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9104 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9105 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9106 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9107 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9108 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9109 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9110 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9111 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9112 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9113 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9114 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9115 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9116 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9117 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9118 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9119 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9120 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9121 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9122 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9123 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9124 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9125 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9126 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9127 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9128 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9129 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9130 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9131 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9132 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9133 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9134 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9135 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9136 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9137 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9138 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9139 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9140 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9141 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9142 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9143 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9144 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9145 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9146 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9147 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9148 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9149 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9150 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9151 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9152 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9153 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9154 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9155 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9156 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9157 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9158 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9159 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9160 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9161 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9162 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9163 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9164 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9165 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9166 };
9167
9168 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9169 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9170 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9171 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9172 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9173 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
9174 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9175 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9176 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9177 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9178 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9179 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9180 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9181 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9182 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9183 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9184 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9185 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9186 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
9187 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9188 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9189 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9190 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9191 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9192 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9193 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9194 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9195 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9196 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9197 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9198 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9199 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9200 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9201 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9202 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
9203 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9204 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9205 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9206 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9207 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9208 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9209 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9210 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9211 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9212 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9213 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9214 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9215 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9216 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9217 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9218 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9219 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9220 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9221 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9222 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9223 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9224 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9225 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9226 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9227 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9228 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9229 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9230 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9231 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9232 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9233 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9234 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9235 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9236 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9237 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9238 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9239 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9240 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9241 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9242 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9243 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9244 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9245 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9246 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9247 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9248 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9249 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9250 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9251 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9252 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9253 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9254 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9255 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9256 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9257 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9258 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9259 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9260 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9261 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9262 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9263 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9264 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9265 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9266 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9267 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9268 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9269 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9270 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9271 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9272 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9273 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9274 [105] = { ALU_OP0_NOP, tgsi_unsupported},
9275 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9276 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9277 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9278 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9279 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9280 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9281 [112] = { ALU_OP0_NOP, tgsi_unsupported},
9282 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9283 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9284 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9285 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9286 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9287 [118] = { ALU_OP0_NOP, tgsi_unsupported},
9288 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9289 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9290 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9291 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9292 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9293 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9294 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9295 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9296 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9297 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9298 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9299 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9300 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9301 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9302 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9303 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9304 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9305 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9306 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9307 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9308 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9309 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9310 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9311 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9312 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9313 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9314 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9315 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9316 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9317 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9318 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9319 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9320 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9321 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9322 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9323 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9324 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9325 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9326 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9327 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9328 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9329 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9330 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9331 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9332 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9333 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9334 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9335 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9336 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9337 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9338 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9339 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9340 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9341 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9342 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9343 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9344 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9345 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9346 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9347 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9348 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9349 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9350 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9351 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9352 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9353 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9354 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9355 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9356 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9357 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9358 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9359 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9360 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9361 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9362 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9363 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9364 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9365 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9366 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9367 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9368 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9369 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9370 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9371 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9372 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9373 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9374 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9375 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9376 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9377 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9378 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9379 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9380 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9381 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9382 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9383 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9384 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9385 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9386 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9387 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9388 };
9389
9390 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9391 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9392 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9393 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9394 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9395 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9396 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9397 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9398 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
9399 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9400 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
9401 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
9402 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9403 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9404 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9405 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9406 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9407 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
9408 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
9409 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9410 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9411 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9412 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
9413 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9414 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9415 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9416 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
9417 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9418 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9419 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9420 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9421 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9422 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
9423 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9424 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
9425 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9426 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
9427 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9428 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9429 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9430 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9431 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9432 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9433 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9434 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9435 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9436 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9437 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9438 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9439 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9440 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9441 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9442 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9443 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9444 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9445 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9446 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9447 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9448 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9449 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9450 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9451 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9452 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9453 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9454 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9455 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9456 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9457 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9458 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
9459 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9460 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9461 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9462 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
9463 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9464 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9465 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9466 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9467 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9468 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9469 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9470 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9471 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9472 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
9473 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
9474 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9475 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9476 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9477 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9478 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9479 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9480 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9481 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9482 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9483 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9484 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
9485 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9486 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9487 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9488 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9489 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9490 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9491 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9492 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9493 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9494 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9495 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9496 [105] = { ALU_OP0_NOP, tgsi_unsupported},
9497 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9498 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9499 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9500 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9501 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9502 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9503 [112] = { ALU_OP0_NOP, tgsi_unsupported},
9504 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
9505 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9506 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
9507 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9508 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9509 [118] = { ALU_OP0_NOP, tgsi_unsupported},
9510 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9511 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9512 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9513 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9514 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9515 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9516 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9517 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9518 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9519 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9520 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9521 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9522 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9523 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9524 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9525 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9526 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9527 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9528 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9529 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9530 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9531 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9532 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9533 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9534 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9535 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9536 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9537 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9538 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9539 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9540 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9541 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9542 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9543 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9544 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9545 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9546 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9547 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9548 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9549 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9550 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9551 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9552 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9553 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9554 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9555 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9556 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
9557 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9558 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9559 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9560 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9561 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9562 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9563 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9564 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9565 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9566 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9567 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9568 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9569 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9570 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9571 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9572 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9573 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9574 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9575 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9576 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9577 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9578 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9579 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9580 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9581 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9582 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9583 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9584 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9585 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9586 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9587 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9588 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9589 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9590 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9591 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9592 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9593 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9594 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9595 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9596 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9597 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9598 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9599 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9600 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9601 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9602 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9603 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9604 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9605 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9606 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9607 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9608 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9609 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9610 };