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Merge remote branch 'origin/nv50-compiler'
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
31 #include "r600_asm.h"
32 #include "r600_sq.h"
33 #include "r600_opcodes.h"
34 #include "r600d.h"
35 #include <stdio.h>
36 #include <errno.h>
37
38
39 struct r600_shader_tgsi_instruction;
40
41 struct r600_shader_ctx {
42 struct tgsi_shader_info info;
43 struct tgsi_parse_context parse;
44 const struct tgsi_token *tokens;
45 unsigned type;
46 unsigned file_offset[TGSI_FILE_COUNT];
47 unsigned temp_reg;
48 struct r600_shader_tgsi_instruction *inst_info;
49 struct r600_bc *bc;
50 struct r600_shader *shader;
51 u32 value[4];
52 u32 *literals;
53 u32 nliterals;
54 u32 max_driver_temp_used;
55 };
56
57 struct r600_shader_tgsi_instruction {
58 unsigned tgsi_opcode;
59 unsigned is_op3;
60 unsigned r600_opcode;
61 int (*process)(struct r600_shader_ctx *ctx);
62 };
63
64 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
65 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
66 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
67
68 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
69 {
70 struct r600_context *rctx = r600_context(ctx);
71 const struct util_format_description *desc;
72 enum pipe_format resource_format[160];
73 unsigned i, nresources = 0;
74 struct r600_bc *bc = &shader->bc;
75 struct r600_bc_cf *cf;
76 struct r600_bc_vtx *vtx;
77
78 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
79 return 0;
80 for (i = 0; i < rctx->vertex_elements->count; i++) {
81 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
82 }
83 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
84 switch (cf->inst) {
85 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
86 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
87 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
88 desc = util_format_description(resource_format[vtx->buffer_id]);
89 if (desc == NULL) {
90 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
91 return -EINVAL;
92 }
93 vtx->dst_sel_x = desc->swizzle[0];
94 vtx->dst_sel_y = desc->swizzle[1];
95 vtx->dst_sel_z = desc->swizzle[2];
96 vtx->dst_sel_w = desc->swizzle[3];
97 }
98 break;
99 default:
100 break;
101 }
102 }
103 return r600_bc_build(&shader->bc);
104 }
105
106 int r600_pipe_shader_create(struct pipe_context *ctx,
107 struct r600_context_state *rpshader,
108 const struct tgsi_token *tokens)
109 {
110 struct r600_screen *rscreen = r600_screen(ctx->screen);
111 int r;
112
113 //fprintf(stderr, "--------------------------------------------------------------\n");
114 //tgsi_dump(tokens, 0);
115 if (rpshader == NULL)
116 return -ENOMEM;
117 rpshader->shader.family = radeon_get_family(rscreen->rw);
118 rpshader->shader.use_mem_constant = rscreen->use_mem_constant;
119 r = r600_shader_from_tgsi(tokens, &rpshader->shader);
120 if (r) {
121 R600_ERR("translation from TGSI failed !\n");
122 return r;
123 }
124 r = r600_bc_build(&rpshader->shader.bc);
125 if (r) {
126 R600_ERR("building bytecode failed !\n");
127 return r;
128 }
129 //fprintf(stderr, "______________________________________________________________\n");
130 return 0;
131 }
132
133 static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
134 {
135 struct r600_context *rctx = r600_context(ctx);
136 struct radeon_state *state;
137
138 state = &rpshader->rstate[0];
139 radeon_state_fini(&rpshader->rstate[0]);
140
141 return rctx->vtbl->vs_shader(rctx, rpshader, state);
142 }
143
144 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
145 {
146 struct r600_context *rctx = r600_context(ctx);
147 struct radeon_state *state;
148
149 state = &rpshader->rstate[0];
150 radeon_state_fini(state);
151
152 return rctx->vtbl->ps_shader(rctx, rpshader, state);
153 }
154
155 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
156 {
157 struct r600_screen *rscreen = r600_screen(ctx->screen);
158 struct r600_context *rctx = r600_context(ctx);
159 struct r600_shader *rshader = &rpshader->shader;
160 int r;
161
162 /* copy new shader */
163 radeon_bo_decref(rscreen->rw, rpshader->bo);
164 rpshader->bo = NULL;
165 rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->bc.ndw * 4,
166 4096, NULL);
167 if (rpshader->bo == NULL) {
168 return -ENOMEM;
169 }
170 radeon_bo_map(rscreen->rw, rpshader->bo);
171 memcpy(rpshader->bo->data, rshader->bc.bytecode, rshader->bc.ndw * 4);
172 radeon_bo_unmap(rscreen->rw, rpshader->bo);
173 /* build state */
174 rshader->flat_shade = rctx->flat_shade;
175 switch (rshader->processor_type) {
176 case TGSI_PROCESSOR_VERTEX:
177 r = r600_pipe_shader_vs(ctx, rpshader);
178 break;
179 case TGSI_PROCESSOR_FRAGMENT:
180 r = r600_pipe_shader_ps(ctx, rpshader);
181 break;
182 default:
183 r = -EINVAL;
184 break;
185 }
186 return r;
187 }
188
189 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
190 {
191 struct r600_context *rctx = r600_context(ctx);
192 int r;
193
194 if (rpshader == NULL)
195 return -EINVAL;
196 /* there should be enough input */
197 if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
198 R600_ERR("%d resources provided, expecting %d\n",
199 rctx->vertex_elements->count, rpshader->shader.bc.nresource);
200 return -EINVAL;
201 }
202 r = r600_shader_update(ctx, &rpshader->shader);
203 if (r)
204 return r;
205 return r600_pipe_shader(ctx, rpshader);
206 }
207
208 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
209 {
210 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
211 int j;
212
213 if (i->Instruction.NumDstRegs > 1) {
214 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
215 return -EINVAL;
216 }
217 if (i->Instruction.Predicate) {
218 R600_ERR("predicate unsupported\n");
219 return -EINVAL;
220 }
221 #if 0
222 if (i->Instruction.Label) {
223 R600_ERR("label unsupported\n");
224 return -EINVAL;
225 }
226 #endif
227 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
228 if (i->Src[j].Register.Dimension ||
229 i->Src[j].Register.Absolute) {
230 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
231 i->Src[j].Register.Dimension,
232 i->Src[j].Register.Absolute);
233 return -EINVAL;
234 }
235 }
236 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
237 if (i->Dst[j].Register.Dimension) {
238 R600_ERR("unsupported dst (dimension)\n");
239 return -EINVAL;
240 }
241 }
242 return 0;
243 }
244
245 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
246 {
247 int i, r;
248 struct r600_bc_alu alu;
249
250 for (i = 0; i < 8; i++) {
251 memset(&alu, 0, sizeof(struct r600_bc_alu));
252
253 if (i < 4)
254 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
255 else
256 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
257
258 if ((i > 1) && (i < 6)) {
259 alu.dst.sel = ctx->shader->input[gpr].gpr;
260 alu.dst.write = 1;
261 }
262
263 alu.dst.chan = i % 4;
264 alu.src[0].chan = (1 - (i % 2));
265 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
266
267 alu.bank_swizzle_force = SQ_ALU_VEC_210;
268 if ((i % 4) == 3)
269 alu.last = 1;
270 r = r600_bc_add_alu(ctx->bc, &alu);
271 if (r)
272 return r;
273 }
274 return 0;
275 }
276
277
278 static int tgsi_declaration(struct r600_shader_ctx *ctx)
279 {
280 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
281 struct r600_bc_vtx vtx;
282 unsigned i;
283 int r;
284
285 switch (d->Declaration.File) {
286 case TGSI_FILE_INPUT:
287 i = ctx->shader->ninput++;
288 ctx->shader->input[i].name = d->Semantic.Name;
289 ctx->shader->input[i].sid = d->Semantic.Index;
290 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
291 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
292 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
293 /* turn input into fetch */
294 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
295 vtx.inst = 0;
296 vtx.fetch_type = 0;
297 vtx.buffer_id = i;
298 /* register containing the index into the buffer */
299 vtx.src_gpr = 0;
300 vtx.src_sel_x = 0;
301 vtx.mega_fetch_count = 0x1F;
302 vtx.dst_gpr = ctx->shader->input[i].gpr;
303 vtx.dst_sel_x = 0;
304 vtx.dst_sel_y = 1;
305 vtx.dst_sel_z = 2;
306 vtx.dst_sel_w = 3;
307 r = r600_bc_add_vtx(ctx->bc, &vtx);
308 if (r)
309 return r;
310 }
311 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
312 /* turn input into interpolate on EG */
313 evergreen_interp_alu(ctx, i);
314 }
315 break;
316 case TGSI_FILE_OUTPUT:
317 i = ctx->shader->noutput++;
318 ctx->shader->output[i].name = d->Semantic.Name;
319 ctx->shader->output[i].sid = d->Semantic.Index;
320 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
321 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
322 break;
323 case TGSI_FILE_CONSTANT:
324 case TGSI_FILE_TEMPORARY:
325 case TGSI_FILE_SAMPLER:
326 case TGSI_FILE_ADDRESS:
327 break;
328 default:
329 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
330 return -EINVAL;
331 }
332 return 0;
333 }
334
335 static int r600_get_temp(struct r600_shader_ctx *ctx)
336 {
337 return ctx->temp_reg + ctx->max_driver_temp_used++;
338 }
339
340 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
341 {
342 struct tgsi_full_immediate *immediate;
343 struct r600_shader_ctx ctx;
344 struct r600_bc_output output[32];
345 unsigned output_done, noutput;
346 unsigned opcode;
347 int i, r = 0, pos0;
348
349 ctx.bc = &shader->bc;
350 ctx.shader = shader;
351 r = r600_bc_init(ctx.bc, shader->family);
352 if (r)
353 return r;
354 ctx.bc->use_mem_constant = shader->use_mem_constant;
355 ctx.tokens = tokens;
356 tgsi_scan_shader(tokens, &ctx.info);
357 tgsi_parse_init(&ctx.parse, tokens);
358 ctx.type = ctx.parse.FullHeader.Processor.Processor;
359 shader->processor_type = ctx.type;
360
361 /* register allocations */
362 /* Values [0,127] correspond to GPR[0..127].
363 * Values [128,159] correspond to constant buffer bank 0
364 * Values [160,191] correspond to constant buffer bank 1
365 * Values [256,511] correspond to cfile constants c[0..255].
366 * Other special values are shown in the list below.
367 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
368 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
369 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
370 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
371 * 248 SQ_ALU_SRC_0: special constant 0.0.
372 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
373 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
374 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
375 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
376 * 253 SQ_ALU_SRC_LITERAL: literal constant.
377 * 254 SQ_ALU_SRC_PV: previous vector result.
378 * 255 SQ_ALU_SRC_PS: previous scalar result.
379 */
380 for (i = 0; i < TGSI_FILE_COUNT; i++) {
381 ctx.file_offset[i] = 0;
382 }
383 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
384 ctx.file_offset[TGSI_FILE_INPUT] = 1;
385 }
386 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
387 ctx.info.file_count[TGSI_FILE_INPUT];
388 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
389 ctx.info.file_count[TGSI_FILE_OUTPUT];
390 if (ctx.shader->use_mem_constant)
391 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
392 else
393 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
394
395 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
396 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
397 ctx.info.file_count[TGSI_FILE_TEMPORARY];
398
399 ctx.nliterals = 0;
400 ctx.literals = NULL;
401
402 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
403 tgsi_parse_token(&ctx.parse);
404 switch (ctx.parse.FullToken.Token.Type) {
405 case TGSI_TOKEN_TYPE_IMMEDIATE:
406 immediate = &ctx.parse.FullToken.FullImmediate;
407 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
408 if(ctx.literals == NULL) {
409 r = -ENOMEM;
410 goto out_err;
411 }
412 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
413 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
414 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
415 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
416 ctx.nliterals++;
417 break;
418 case TGSI_TOKEN_TYPE_DECLARATION:
419 r = tgsi_declaration(&ctx);
420 if (r)
421 goto out_err;
422 break;
423 case TGSI_TOKEN_TYPE_INSTRUCTION:
424 r = tgsi_is_supported(&ctx);
425 if (r)
426 goto out_err;
427 ctx.max_driver_temp_used = 0;
428 /* reserve first tmp for everyone */
429 r600_get_temp(&ctx);
430 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
431 if (ctx.bc->chiprev == 2)
432 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
433 else
434 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
435 r = ctx.inst_info->process(&ctx);
436 if (r)
437 goto out_err;
438 r = r600_bc_add_literal(ctx.bc, ctx.value);
439 if (r)
440 goto out_err;
441 break;
442 default:
443 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
444 r = -EINVAL;
445 goto out_err;
446 }
447 }
448 /* export output */
449 noutput = shader->noutput;
450 for (i = 0, pos0 = 0; i < noutput; i++) {
451 memset(&output[i], 0, sizeof(struct r600_bc_output));
452 output[i].gpr = shader->output[i].gpr;
453 output[i].elem_size = 3;
454 output[i].swizzle_x = 0;
455 output[i].swizzle_y = 1;
456 output[i].swizzle_z = 2;
457 output[i].swizzle_w = 3;
458 output[i].barrier = 1;
459 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
460 output[i].array_base = i - pos0;
461 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
462 switch (ctx.type) {
463 case TGSI_PROCESSOR_VERTEX:
464 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
465 output[i].array_base = 60;
466 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
467 /* position doesn't count in array_base */
468 pos0++;
469 }
470 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
471 output[i].array_base = 61;
472 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
473 /* position doesn't count in array_base */
474 pos0++;
475 }
476 break;
477 case TGSI_PROCESSOR_FRAGMENT:
478 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
479 output[i].array_base = shader->output[i].sid;
480 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
481 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
482 output[i].array_base = 61;
483 output[i].swizzle_x = 2;
484 output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
485 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
486 } else {
487 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
488 r = -EINVAL;
489 goto out_err;
490 }
491 break;
492 default:
493 R600_ERR("unsupported processor type %d\n", ctx.type);
494 r = -EINVAL;
495 goto out_err;
496 }
497 }
498 /* add fake param output for vertex shader if no param is exported */
499 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
500 for (i = 0, pos0 = 0; i < noutput; i++) {
501 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
502 pos0 = 1;
503 break;
504 }
505 }
506 if (!pos0) {
507 memset(&output[i], 0, sizeof(struct r600_bc_output));
508 output[i].gpr = 0;
509 output[i].elem_size = 3;
510 output[i].swizzle_x = 0;
511 output[i].swizzle_y = 1;
512 output[i].swizzle_z = 2;
513 output[i].swizzle_w = 3;
514 output[i].barrier = 1;
515 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
516 output[i].array_base = 0;
517 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
518 noutput++;
519 }
520 }
521 /* add fake pixel export */
522 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
523 memset(&output[0], 0, sizeof(struct r600_bc_output));
524 output[0].gpr = 0;
525 output[0].elem_size = 3;
526 output[0].swizzle_x = 7;
527 output[0].swizzle_y = 7;
528 output[0].swizzle_z = 7;
529 output[0].swizzle_w = 7;
530 output[0].barrier = 1;
531 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
532 output[0].array_base = 0;
533 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
534 noutput++;
535 }
536 /* set export done on last export of each type */
537 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
538 if (i == (noutput - 1)) {
539 output[i].end_of_program = 1;
540 }
541 if (!(output_done & (1 << output[i].type))) {
542 output_done |= (1 << output[i].type);
543 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
544 }
545 }
546 /* add output to bytecode */
547 for (i = 0; i < noutput; i++) {
548 r = r600_bc_add_output(ctx.bc, &output[i]);
549 if (r)
550 goto out_err;
551 }
552 free(ctx.literals);
553 tgsi_parse_free(&ctx.parse);
554 return 0;
555 out_err:
556 free(ctx.literals);
557 tgsi_parse_free(&ctx.parse);
558 return r;
559 }
560
561 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
562 {
563 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
564 return -EINVAL;
565 }
566
567 static int tgsi_end(struct r600_shader_ctx *ctx)
568 {
569 return 0;
570 }
571
572 static int tgsi_src(struct r600_shader_ctx *ctx,
573 const struct tgsi_full_src_register *tgsi_src,
574 struct r600_bc_alu_src *r600_src)
575 {
576 int index;
577 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
578 r600_src->sel = tgsi_src->Register.Index;
579 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
580 r600_src->sel = 0;
581 index = tgsi_src->Register.Index;
582 ctx->value[0] = ctx->literals[index * 4 + 0];
583 ctx->value[1] = ctx->literals[index * 4 + 1];
584 ctx->value[2] = ctx->literals[index * 4 + 2];
585 ctx->value[3] = ctx->literals[index * 4 + 3];
586 }
587 if (tgsi_src->Register.Indirect)
588 r600_src->rel = V_SQ_REL_RELATIVE;
589 r600_src->neg = tgsi_src->Register.Negate;
590 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
591 return 0;
592 }
593
594 static int tgsi_dst(struct r600_shader_ctx *ctx,
595 const struct tgsi_full_dst_register *tgsi_dst,
596 unsigned swizzle,
597 struct r600_bc_alu_dst *r600_dst)
598 {
599 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
600
601 r600_dst->sel = tgsi_dst->Register.Index;
602 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
603 r600_dst->chan = swizzle;
604 r600_dst->write = 1;
605 if (tgsi_dst->Register.Indirect)
606 r600_dst->rel = V_SQ_REL_RELATIVE;
607 if (inst->Instruction.Saturate) {
608 r600_dst->clamp = 1;
609 }
610 return 0;
611 }
612
613 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
614 {
615 switch (swizzle) {
616 case 0:
617 return tgsi_src->Register.SwizzleX;
618 case 1:
619 return tgsi_src->Register.SwizzleY;
620 case 2:
621 return tgsi_src->Register.SwizzleZ;
622 case 3:
623 return tgsi_src->Register.SwizzleW;
624 default:
625 return 0;
626 }
627 }
628
629 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
630 {
631 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
632 struct r600_bc_alu alu;
633 int i, j, k, nconst, r;
634
635 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
636 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
637 nconst++;
638 }
639 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
640 if (r) {
641 return r;
642 }
643 }
644 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
645 if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
646 int treg = r600_get_temp(ctx);
647 for (k = 0; k < 4; k++) {
648 memset(&alu, 0, sizeof(struct r600_bc_alu));
649 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
650 alu.src[0].sel = r600_src[j].sel;
651 alu.src[0].chan = k;
652 alu.dst.sel = treg;
653 alu.dst.chan = k;
654 alu.dst.write = 1;
655 if (k == 3)
656 alu.last = 1;
657 r = r600_bc_add_alu(ctx->bc, &alu);
658 if (r)
659 return r;
660 }
661 r600_src[j].sel = treg;
662 j--;
663 }
664 }
665 return 0;
666 }
667
668 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
669 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
670 {
671 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
672 struct r600_bc_alu alu;
673 int i, j, k, nliteral, r;
674
675 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
676 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
677 nliteral++;
678 }
679 }
680 for (i = 0, j = 0; i < inst->Instruction.NumSrcRegs; i++) {
681 if (inst->Src[j].Register.File == TGSI_FILE_IMMEDIATE) {
682 int treg = r600_get_temp(ctx);
683 for (k = 0; k < 4; k++) {
684 memset(&alu, 0, sizeof(struct r600_bc_alu));
685 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
686 alu.src[0].sel = r600_src[j].sel;
687 alu.src[0].chan = k;
688 alu.dst.sel = treg;
689 alu.dst.chan = k;
690 alu.dst.write = 1;
691 if (k == 3)
692 alu.last = 1;
693 r = r600_bc_add_alu(ctx->bc, &alu);
694 if (r)
695 return r;
696 }
697 r = r600_bc_add_literal(ctx->bc, ctx->value);
698 if (r)
699 return r;
700 r600_src[j].sel = treg;
701 j++;
702 }
703 }
704 return 0;
705 }
706
707 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
708 {
709 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
710 struct r600_bc_alu_src r600_src[3];
711 struct r600_bc_alu alu;
712 int i, j, r;
713 int lasti = 0;
714
715 for (i = 0; i < 4; i++) {
716 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
717 lasti = i;
718 }
719 }
720
721 r = tgsi_split_constant(ctx, r600_src);
722 if (r)
723 return r;
724 for (i = 0; i < lasti + 1; i++) {
725 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
726 continue;
727
728 memset(&alu, 0, sizeof(struct r600_bc_alu));
729 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
730 if (r)
731 return r;
732
733 alu.inst = ctx->inst_info->r600_opcode;
734 if (!swap) {
735 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
736 alu.src[j] = r600_src[j];
737 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
738 }
739 } else {
740 alu.src[0] = r600_src[1];
741 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
742
743 alu.src[1] = r600_src[0];
744 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
745 }
746 /* handle some special cases */
747 switch (ctx->inst_info->tgsi_opcode) {
748 case TGSI_OPCODE_SUB:
749 alu.src[1].neg = 1;
750 break;
751 case TGSI_OPCODE_ABS:
752 alu.src[0].abs = 1;
753 break;
754 default:
755 break;
756 }
757 if (i == lasti) {
758 alu.last = 1;
759 }
760 r = r600_bc_add_alu(ctx->bc, &alu);
761 if (r)
762 return r;
763 }
764 return 0;
765 }
766
767 static int tgsi_op2(struct r600_shader_ctx *ctx)
768 {
769 return tgsi_op2_s(ctx, 0);
770 }
771
772 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
773 {
774 return tgsi_op2_s(ctx, 1);
775 }
776
777 /*
778 * r600 - trunc to -PI..PI range
779 * r700 - normalize by dividing by 2PI
780 * see fdo bug 27901
781 */
782 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
783 struct r600_bc_alu_src r600_src[3])
784 {
785 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
786 int r;
787 uint32_t lit_vals[4];
788 struct r600_bc_alu alu;
789
790 memset(lit_vals, 0, 4*4);
791 r = tgsi_split_constant(ctx, r600_src);
792 if (r)
793 return r;
794
795 r = tgsi_split_literal_constant(ctx, r600_src);
796 if (r)
797 return r;
798
799 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
800 lit_vals[1] = fui(0.5f);
801
802 memset(&alu, 0, sizeof(struct r600_bc_alu));
803 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
804 alu.is_op3 = 1;
805
806 alu.dst.chan = 0;
807 alu.dst.sel = ctx->temp_reg;
808 alu.dst.write = 1;
809
810 alu.src[0] = r600_src[0];
811 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
812
813 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
814 alu.src[1].chan = 0;
815 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
816 alu.src[2].chan = 1;
817 alu.last = 1;
818 r = r600_bc_add_alu(ctx->bc, &alu);
819 if (r)
820 return r;
821 r = r600_bc_add_literal(ctx->bc, lit_vals);
822 if (r)
823 return r;
824
825 memset(&alu, 0, sizeof(struct r600_bc_alu));
826 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
827
828 alu.dst.chan = 0;
829 alu.dst.sel = ctx->temp_reg;
830 alu.dst.write = 1;
831
832 alu.src[0].sel = ctx->temp_reg;
833 alu.src[0].chan = 0;
834 alu.last = 1;
835 r = r600_bc_add_alu(ctx->bc, &alu);
836 if (r)
837 return r;
838
839 if (ctx->bc->chiprev == 0) {
840 lit_vals[0] = fui(3.1415926535897f * 2.0f);
841 lit_vals[1] = fui(-3.1415926535897f);
842 } else {
843 lit_vals[0] = fui(1.0f);
844 lit_vals[1] = fui(-0.5f);
845 }
846
847 memset(&alu, 0, sizeof(struct r600_bc_alu));
848 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
849 alu.is_op3 = 1;
850
851 alu.dst.chan = 0;
852 alu.dst.sel = ctx->temp_reg;
853 alu.dst.write = 1;
854
855 alu.src[0].sel = ctx->temp_reg;
856 alu.src[0].chan = 0;
857
858 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
859 alu.src[1].chan = 0;
860 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
861 alu.src[2].chan = 1;
862 alu.last = 1;
863 r = r600_bc_add_alu(ctx->bc, &alu);
864 if (r)
865 return r;
866 r = r600_bc_add_literal(ctx->bc, lit_vals);
867 if (r)
868 return r;
869 return 0;
870 }
871
872 static int tgsi_trig(struct r600_shader_ctx *ctx)
873 {
874 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
875 struct r600_bc_alu_src r600_src[3];
876 struct r600_bc_alu alu;
877 int i, r;
878 int lasti = 0;
879
880 r = tgsi_setup_trig(ctx, r600_src);
881 if (r)
882 return r;
883
884 memset(&alu, 0, sizeof(struct r600_bc_alu));
885 alu.inst = ctx->inst_info->r600_opcode;
886 alu.dst.chan = 0;
887 alu.dst.sel = ctx->temp_reg;
888 alu.dst.write = 1;
889
890 alu.src[0].sel = ctx->temp_reg;
891 alu.src[0].chan = 0;
892 alu.last = 1;
893 r = r600_bc_add_alu(ctx->bc, &alu);
894 if (r)
895 return r;
896
897 /* replicate result */
898 for (i = 0; i < 4; i++) {
899 if (inst->Dst[0].Register.WriteMask & (1 << i))
900 lasti = i;
901 }
902 for (i = 0; i < lasti + 1; i++) {
903 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
904 continue;
905
906 memset(&alu, 0, sizeof(struct r600_bc_alu));
907 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
908
909 alu.src[0].sel = ctx->temp_reg;
910 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
911 if (r)
912 return r;
913 if (i == lasti)
914 alu.last = 1;
915 r = r600_bc_add_alu(ctx->bc, &alu);
916 if (r)
917 return r;
918 }
919 return 0;
920 }
921
922 static int tgsi_scs(struct r600_shader_ctx *ctx)
923 {
924 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
925 struct r600_bc_alu_src r600_src[3];
926 struct r600_bc_alu alu;
927 int r;
928
929 r = tgsi_setup_trig(ctx, r600_src);
930 if (r)
931 return r;
932
933
934 /* dst.x = COS */
935 memset(&alu, 0, sizeof(struct r600_bc_alu));
936 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
937 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
938 if (r)
939 return r;
940
941 alu.src[0].sel = ctx->temp_reg;
942 alu.src[0].chan = 0;
943 alu.last = 1;
944 r = r600_bc_add_alu(ctx->bc, &alu);
945 if (r)
946 return r;
947
948 /* dst.y = SIN */
949 memset(&alu, 0, sizeof(struct r600_bc_alu));
950 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
951 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
952 if (r)
953 return r;
954
955 alu.src[0].sel = ctx->temp_reg;
956 alu.src[0].chan = 0;
957 alu.last = 1;
958 r = r600_bc_add_alu(ctx->bc, &alu);
959 if (r)
960 return r;
961 return 0;
962 }
963
964 static int tgsi_kill(struct r600_shader_ctx *ctx)
965 {
966 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
967 struct r600_bc_alu alu;
968 int i, r;
969
970 for (i = 0; i < 4; i++) {
971 memset(&alu, 0, sizeof(struct r600_bc_alu));
972 alu.inst = ctx->inst_info->r600_opcode;
973
974 alu.dst.chan = i;
975
976 alu.src[0].sel = V_SQ_ALU_SRC_0;
977
978 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
979 alu.src[1].sel = V_SQ_ALU_SRC_1;
980 alu.src[1].neg = 1;
981 } else {
982 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
983 if (r)
984 return r;
985 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
986 }
987 if (i == 3) {
988 alu.last = 1;
989 }
990 r = r600_bc_add_alu(ctx->bc, &alu);
991 if (r)
992 return r;
993 }
994 r = r600_bc_add_literal(ctx->bc, ctx->value);
995 if (r)
996 return r;
997
998 /* kill must be last in ALU */
999 ctx->bc->force_add_cf = 1;
1000 ctx->shader->uses_kill = TRUE;
1001 return 0;
1002 }
1003
1004 static int tgsi_lit(struct r600_shader_ctx *ctx)
1005 {
1006 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1007 struct r600_bc_alu alu;
1008 struct r600_bc_alu_src r600_src[3];
1009 int r;
1010
1011 r = tgsi_split_constant(ctx, r600_src);
1012 if (r)
1013 return r;
1014 r = tgsi_split_literal_constant(ctx, r600_src);
1015 if (r)
1016 return r;
1017
1018 /* dst.x, <- 1.0 */
1019 memset(&alu, 0, sizeof(struct r600_bc_alu));
1020 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1021 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1022 alu.src[0].chan = 0;
1023 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1024 if (r)
1025 return r;
1026 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1027 r = r600_bc_add_alu(ctx->bc, &alu);
1028 if (r)
1029 return r;
1030
1031 /* dst.y = max(src.x, 0.0) */
1032 memset(&alu, 0, sizeof(struct r600_bc_alu));
1033 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1034 alu.src[0] = r600_src[0];
1035 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1036 alu.src[1].chan = 0;
1037 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1038 if (r)
1039 return r;
1040 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1041 r = r600_bc_add_alu(ctx->bc, &alu);
1042 if (r)
1043 return r;
1044
1045 /* dst.w, <- 1.0 */
1046 memset(&alu, 0, sizeof(struct r600_bc_alu));
1047 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1048 alu.src[0].sel = V_SQ_ALU_SRC_1;
1049 alu.src[0].chan = 0;
1050 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1051 if (r)
1052 return r;
1053 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1054 alu.last = 1;
1055 r = r600_bc_add_alu(ctx->bc, &alu);
1056 if (r)
1057 return r;
1058
1059 r = r600_bc_add_literal(ctx->bc, ctx->value);
1060 if (r)
1061 return r;
1062
1063 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1064 {
1065 int chan;
1066 int sel;
1067
1068 /* dst.z = log(src.y) */
1069 memset(&alu, 0, sizeof(struct r600_bc_alu));
1070 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1071 alu.src[0] = r600_src[0];
1072 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1073 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1074 if (r)
1075 return r;
1076 alu.last = 1;
1077 r = r600_bc_add_alu(ctx->bc, &alu);
1078 if (r)
1079 return r;
1080
1081 r = r600_bc_add_literal(ctx->bc, ctx->value);
1082 if (r)
1083 return r;
1084
1085 chan = alu.dst.chan;
1086 sel = alu.dst.sel;
1087
1088 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1089 memset(&alu, 0, sizeof(struct r600_bc_alu));
1090 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1091 alu.src[0] = r600_src[0];
1092 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1093 alu.src[1].sel = sel;
1094 alu.src[1].chan = chan;
1095
1096 alu.src[2] = r600_src[0];
1097 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1098 alu.dst.sel = ctx->temp_reg;
1099 alu.dst.chan = 0;
1100 alu.dst.write = 1;
1101 alu.is_op3 = 1;
1102 alu.last = 1;
1103 r = r600_bc_add_alu(ctx->bc, &alu);
1104 if (r)
1105 return r;
1106
1107 r = r600_bc_add_literal(ctx->bc, ctx->value);
1108 if (r)
1109 return r;
1110 /* dst.z = exp(tmp.x) */
1111 memset(&alu, 0, sizeof(struct r600_bc_alu));
1112 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1113 alu.src[0].sel = ctx->temp_reg;
1114 alu.src[0].chan = 0;
1115 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1116 if (r)
1117 return r;
1118 alu.last = 1;
1119 r = r600_bc_add_alu(ctx->bc, &alu);
1120 if (r)
1121 return r;
1122 }
1123 return 0;
1124 }
1125
1126 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1127 {
1128 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1129 struct r600_bc_alu alu;
1130 int i, r;
1131
1132 memset(&alu, 0, sizeof(struct r600_bc_alu));
1133 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE);
1134 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1135 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1136 if (r)
1137 return r;
1138 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1139 alu.src[i].abs = 1;
1140 }
1141 alu.dst.sel = ctx->temp_reg;
1142 alu.dst.write = 1;
1143 alu.last = 1;
1144 r = r600_bc_add_alu(ctx->bc, &alu);
1145 if (r)
1146 return r;
1147 r = r600_bc_add_literal(ctx->bc, ctx->value);
1148 if (r)
1149 return r;
1150 /* replicate result */
1151 return tgsi_helper_tempx_replicate(ctx);
1152 }
1153
1154 static int tgsi_trans(struct r600_shader_ctx *ctx)
1155 {
1156 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1157 struct r600_bc_alu alu;
1158 int i, j, r;
1159
1160 for (i = 0; i < 4; i++) {
1161 memset(&alu, 0, sizeof(struct r600_bc_alu));
1162 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
1163 alu.inst = ctx->inst_info->r600_opcode;
1164 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1165 r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
1166 if (r)
1167 return r;
1168 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1169 }
1170 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1171 if (r)
1172 return r;
1173 alu.last = 1;
1174 r = r600_bc_add_alu(ctx->bc, &alu);
1175 if (r)
1176 return r;
1177 }
1178 }
1179 return 0;
1180 }
1181
1182 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1183 {
1184 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1185 struct r600_bc_alu alu;
1186 int i, r;
1187
1188 for (i = 0; i < 4; i++) {
1189 memset(&alu, 0, sizeof(struct r600_bc_alu));
1190 alu.src[0].sel = ctx->temp_reg;
1191 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1192 alu.dst.chan = i;
1193 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1194 if (r)
1195 return r;
1196 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1197 if (i == 3)
1198 alu.last = 1;
1199 r = r600_bc_add_alu(ctx->bc, &alu);
1200 if (r)
1201 return r;
1202 }
1203 return 0;
1204 }
1205
1206 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1207 {
1208 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1209 struct r600_bc_alu alu;
1210 int i, r;
1211
1212 memset(&alu, 0, sizeof(struct r600_bc_alu));
1213 alu.inst = ctx->inst_info->r600_opcode;
1214 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1215 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1216 if (r)
1217 return r;
1218 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1219 }
1220 alu.dst.sel = ctx->temp_reg;
1221 alu.dst.write = 1;
1222 alu.last = 1;
1223 r = r600_bc_add_alu(ctx->bc, &alu);
1224 if (r)
1225 return r;
1226 r = r600_bc_add_literal(ctx->bc, ctx->value);
1227 if (r)
1228 return r;
1229 /* replicate result */
1230 return tgsi_helper_tempx_replicate(ctx);
1231 }
1232
1233 static int tgsi_pow(struct r600_shader_ctx *ctx)
1234 {
1235 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1236 struct r600_bc_alu alu;
1237 int r;
1238
1239 /* LOG2(a) */
1240 memset(&alu, 0, sizeof(struct r600_bc_alu));
1241 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1242 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1243 if (r)
1244 return r;
1245 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1246 alu.dst.sel = ctx->temp_reg;
1247 alu.dst.write = 1;
1248 alu.last = 1;
1249 r = r600_bc_add_alu(ctx->bc, &alu);
1250 if (r)
1251 return r;
1252 r = r600_bc_add_literal(ctx->bc,ctx->value);
1253 if (r)
1254 return r;
1255 /* b * LOG2(a) */
1256 memset(&alu, 0, sizeof(struct r600_bc_alu));
1257 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1258 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1259 if (r)
1260 return r;
1261 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1262 alu.src[1].sel = ctx->temp_reg;
1263 alu.dst.sel = ctx->temp_reg;
1264 alu.dst.write = 1;
1265 alu.last = 1;
1266 r = r600_bc_add_alu(ctx->bc, &alu);
1267 if (r)
1268 return r;
1269 r = r600_bc_add_literal(ctx->bc,ctx->value);
1270 if (r)
1271 return r;
1272 /* POW(a,b) = EXP2(b * LOG2(a))*/
1273 memset(&alu, 0, sizeof(struct r600_bc_alu));
1274 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1275 alu.src[0].sel = ctx->temp_reg;
1276 alu.dst.sel = ctx->temp_reg;
1277 alu.dst.write = 1;
1278 alu.last = 1;
1279 r = r600_bc_add_alu(ctx->bc, &alu);
1280 if (r)
1281 return r;
1282 r = r600_bc_add_literal(ctx->bc,ctx->value);
1283 if (r)
1284 return r;
1285 return tgsi_helper_tempx_replicate(ctx);
1286 }
1287
1288 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1289 {
1290 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1291 struct r600_bc_alu alu;
1292 struct r600_bc_alu_src r600_src[3];
1293 int i, r;
1294
1295 r = tgsi_split_constant(ctx, r600_src);
1296 if (r)
1297 return r;
1298
1299 /* tmp = (src > 0 ? 1 : src) */
1300 for (i = 0; i < 4; i++) {
1301 memset(&alu, 0, sizeof(struct r600_bc_alu));
1302 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1303 alu.is_op3 = 1;
1304
1305 alu.dst.sel = ctx->temp_reg;
1306 alu.dst.chan = i;
1307
1308 alu.src[0] = r600_src[0];
1309 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1310
1311 alu.src[1].sel = V_SQ_ALU_SRC_1;
1312
1313 alu.src[2] = r600_src[0];
1314 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1315 if (i == 3)
1316 alu.last = 1;
1317 r = r600_bc_add_alu(ctx->bc, &alu);
1318 if (r)
1319 return r;
1320 }
1321 r = r600_bc_add_literal(ctx->bc, ctx->value);
1322 if (r)
1323 return r;
1324
1325 /* dst = (-tmp > 0 ? -1 : tmp) */
1326 for (i = 0; i < 4; i++) {
1327 memset(&alu, 0, sizeof(struct r600_bc_alu));
1328 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1329 alu.is_op3 = 1;
1330 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1331 if (r)
1332 return r;
1333
1334 alu.src[0].sel = ctx->temp_reg;
1335 alu.src[0].chan = i;
1336 alu.src[0].neg = 1;
1337
1338 alu.src[1].sel = V_SQ_ALU_SRC_1;
1339 alu.src[1].neg = 1;
1340
1341 alu.src[2].sel = ctx->temp_reg;
1342 alu.src[2].chan = i;
1343
1344 if (i == 3)
1345 alu.last = 1;
1346 r = r600_bc_add_alu(ctx->bc, &alu);
1347 if (r)
1348 return r;
1349 }
1350 return 0;
1351 }
1352
1353 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1354 {
1355 struct r600_bc_alu alu;
1356 int i, r;
1357
1358 r = r600_bc_add_literal(ctx->bc, ctx->value);
1359 if (r)
1360 return r;
1361 for (i = 0; i < 4; i++) {
1362 memset(&alu, 0, sizeof(struct r600_bc_alu));
1363 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1364 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1365 alu.dst.chan = i;
1366 } else {
1367 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1368 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1369 if (r)
1370 return r;
1371 alu.src[0].sel = ctx->temp_reg;
1372 alu.src[0].chan = i;
1373 }
1374 if (i == 3) {
1375 alu.last = 1;
1376 }
1377 r = r600_bc_add_alu(ctx->bc, &alu);
1378 if (r)
1379 return r;
1380 }
1381 return 0;
1382 }
1383
1384 static int tgsi_op3(struct r600_shader_ctx *ctx)
1385 {
1386 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1387 struct r600_bc_alu_src r600_src[3];
1388 struct r600_bc_alu alu;
1389 int i, j, r;
1390
1391 r = tgsi_split_constant(ctx, r600_src);
1392 if (r)
1393 return r;
1394 /* do it in 2 step as op3 doesn't support writemask */
1395 for (i = 0; i < 4; i++) {
1396 memset(&alu, 0, sizeof(struct r600_bc_alu));
1397 alu.inst = ctx->inst_info->r600_opcode;
1398 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1399 alu.src[j] = r600_src[j];
1400 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1401 }
1402 alu.dst.sel = ctx->temp_reg;
1403 alu.dst.chan = i;
1404 alu.dst.write = 1;
1405 alu.is_op3 = 1;
1406 if (i == 3) {
1407 alu.last = 1;
1408 }
1409 r = r600_bc_add_alu(ctx->bc, &alu);
1410 if (r)
1411 return r;
1412 }
1413 return tgsi_helper_copy(ctx, inst);
1414 }
1415
1416 static int tgsi_dp(struct r600_shader_ctx *ctx)
1417 {
1418 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1419 struct r600_bc_alu_src r600_src[3];
1420 struct r600_bc_alu alu;
1421 int i, j, r;
1422
1423 r = tgsi_split_constant(ctx, r600_src);
1424 if (r)
1425 return r;
1426 for (i = 0; i < 4; i++) {
1427 memset(&alu, 0, sizeof(struct r600_bc_alu));
1428 alu.inst = ctx->inst_info->r600_opcode;
1429 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1430 alu.src[j] = r600_src[j];
1431 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1432 }
1433 alu.dst.sel = ctx->temp_reg;
1434 alu.dst.chan = i;
1435 alu.dst.write = 1;
1436 /* handle some special cases */
1437 switch (ctx->inst_info->tgsi_opcode) {
1438 case TGSI_OPCODE_DP2:
1439 if (i > 1) {
1440 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1441 alu.src[0].chan = alu.src[1].chan = 0;
1442 }
1443 break;
1444 case TGSI_OPCODE_DP3:
1445 if (i > 2) {
1446 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1447 alu.src[0].chan = alu.src[1].chan = 0;
1448 }
1449 break;
1450 case TGSI_OPCODE_DPH:
1451 if (i == 3) {
1452 alu.src[0].sel = V_SQ_ALU_SRC_1;
1453 alu.src[0].chan = 0;
1454 alu.src[0].neg = 0;
1455 }
1456 break;
1457 default:
1458 break;
1459 }
1460 if (i == 3) {
1461 alu.last = 1;
1462 }
1463 r = r600_bc_add_alu(ctx->bc, &alu);
1464 if (r)
1465 return r;
1466 }
1467 return tgsi_helper_copy(ctx, inst);
1468 }
1469
1470 static int tgsi_tex(struct r600_shader_ctx *ctx)
1471 {
1472 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1473 struct r600_bc_tex tex;
1474 struct r600_bc_alu alu;
1475 unsigned src_gpr;
1476 int r, i;
1477 int opcode;
1478 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1479 uint32_t lit_vals[4];
1480
1481 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1482
1483 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1484 /* Add perspective divide */
1485 memset(&alu, 0, sizeof(struct r600_bc_alu));
1486 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1487 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1488 if (r)
1489 return r;
1490
1491 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1492 alu.dst.sel = ctx->temp_reg;
1493 alu.dst.chan = 3;
1494 alu.last = 1;
1495 alu.dst.write = 1;
1496 r = r600_bc_add_alu(ctx->bc, &alu);
1497 if (r)
1498 return r;
1499
1500 for (i = 0; i < 3; i++) {
1501 memset(&alu, 0, sizeof(struct r600_bc_alu));
1502 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1503 alu.src[0].sel = ctx->temp_reg;
1504 alu.src[0].chan = 3;
1505 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1506 if (r)
1507 return r;
1508 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1509 alu.dst.sel = ctx->temp_reg;
1510 alu.dst.chan = i;
1511 alu.dst.write = 1;
1512 r = r600_bc_add_alu(ctx->bc, &alu);
1513 if (r)
1514 return r;
1515 }
1516 memset(&alu, 0, sizeof(struct r600_bc_alu));
1517 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1518 alu.src[0].sel = V_SQ_ALU_SRC_1;
1519 alu.src[0].chan = 0;
1520 alu.dst.sel = ctx->temp_reg;
1521 alu.dst.chan = 3;
1522 alu.last = 1;
1523 alu.dst.write = 1;
1524 r = r600_bc_add_alu(ctx->bc, &alu);
1525 if (r)
1526 return r;
1527 src_not_temp = false;
1528 src_gpr = ctx->temp_reg;
1529 }
1530
1531 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1532 int src_chan, src2_chan;
1533
1534 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1535 for (i = 0; i < 4; i++) {
1536 memset(&alu, 0, sizeof(struct r600_bc_alu));
1537 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1538 switch (i) {
1539 case 0:
1540 src_chan = 2;
1541 src2_chan = 1;
1542 break;
1543 case 1:
1544 src_chan = 2;
1545 src2_chan = 0;
1546 break;
1547 case 2:
1548 src_chan = 0;
1549 src2_chan = 2;
1550 break;
1551 case 3:
1552 src_chan = 1;
1553 src2_chan = 2;
1554 break;
1555 }
1556 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1557 if (r)
1558 return r;
1559 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1560 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1561 if (r)
1562 return r;
1563 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1564 alu.dst.sel = ctx->temp_reg;
1565 alu.dst.chan = i;
1566 if (i == 3)
1567 alu.last = 1;
1568 alu.dst.write = 1;
1569 r = r600_bc_add_alu(ctx->bc, &alu);
1570 if (r)
1571 return r;
1572 }
1573
1574 /* tmp1.z = RCP_e(|tmp1.z|) */
1575 memset(&alu, 0, sizeof(struct r600_bc_alu));
1576 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1577 alu.src[0].sel = ctx->temp_reg;
1578 alu.src[0].chan = 2;
1579 alu.src[0].abs = 1;
1580 alu.dst.sel = ctx->temp_reg;
1581 alu.dst.chan = 2;
1582 alu.dst.write = 1;
1583 alu.last = 1;
1584 r = r600_bc_add_alu(ctx->bc, &alu);
1585 if (r)
1586 return r;
1587
1588 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1589 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1590 * muladd has no writemask, have to use another temp
1591 */
1592 memset(&alu, 0, sizeof(struct r600_bc_alu));
1593 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1594 alu.is_op3 = 1;
1595
1596 alu.src[0].sel = ctx->temp_reg;
1597 alu.src[0].chan = 0;
1598 alu.src[1].sel = ctx->temp_reg;
1599 alu.src[1].chan = 2;
1600
1601 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1602 alu.src[2].chan = 0;
1603
1604 alu.dst.sel = ctx->temp_reg;
1605 alu.dst.chan = 0;
1606 alu.dst.write = 1;
1607
1608 r = r600_bc_add_alu(ctx->bc, &alu);
1609 if (r)
1610 return r;
1611
1612 memset(&alu, 0, sizeof(struct r600_bc_alu));
1613 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1614 alu.is_op3 = 1;
1615
1616 alu.src[0].sel = ctx->temp_reg;
1617 alu.src[0].chan = 1;
1618 alu.src[1].sel = ctx->temp_reg;
1619 alu.src[1].chan = 2;
1620
1621 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1622 alu.src[2].chan = 0;
1623
1624 alu.dst.sel = ctx->temp_reg;
1625 alu.dst.chan = 1;
1626 alu.dst.write = 1;
1627
1628 alu.last = 1;
1629 r = r600_bc_add_alu(ctx->bc, &alu);
1630 if (r)
1631 return r;
1632
1633 lit_vals[0] = fui(1.5f);
1634
1635 r = r600_bc_add_literal(ctx->bc, lit_vals);
1636 if (r)
1637 return r;
1638 src_not_temp = false;
1639 src_gpr = ctx->temp_reg;
1640 }
1641
1642 if (src_not_temp) {
1643 for (i = 0; i < 4; i++) {
1644 memset(&alu, 0, sizeof(struct r600_bc_alu));
1645 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1646 alu.src[0].sel = src_gpr;
1647 alu.src[0].chan = i;
1648 alu.dst.sel = ctx->temp_reg;
1649 alu.dst.chan = i;
1650 if (i == 3)
1651 alu.last = 1;
1652 alu.dst.write = 1;
1653 r = r600_bc_add_alu(ctx->bc, &alu);
1654 if (r)
1655 return r;
1656 }
1657 src_gpr = ctx->temp_reg;
1658 }
1659
1660 opcode = ctx->inst_info->r600_opcode;
1661 if (opcode == SQ_TEX_INST_SAMPLE &&
1662 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1663 opcode = SQ_TEX_INST_SAMPLE_C;
1664
1665 memset(&tex, 0, sizeof(struct r600_bc_tex));
1666 tex.inst = opcode;
1667 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1668 tex.sampler_id = tex.resource_id;
1669 tex.src_gpr = src_gpr;
1670 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1671 tex.dst_sel_x = 0;
1672 tex.dst_sel_y = 1;
1673 tex.dst_sel_z = 2;
1674 tex.dst_sel_w = 3;
1675 tex.src_sel_x = 0;
1676 tex.src_sel_y = 1;
1677 tex.src_sel_z = 2;
1678 tex.src_sel_w = 3;
1679
1680 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1681 tex.src_sel_x = 1;
1682 tex.src_sel_y = 0;
1683 tex.src_sel_z = 3;
1684 tex.src_sel_w = 1;
1685 }
1686
1687 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1688 tex.coord_type_x = 1;
1689 tex.coord_type_y = 1;
1690 tex.coord_type_z = 1;
1691 tex.coord_type_w = 1;
1692 }
1693
1694 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1695 tex.src_sel_w = 2;
1696
1697 r = r600_bc_add_tex(ctx->bc, &tex);
1698 if (r)
1699 return r;
1700
1701 /* add shadow ambient support - gallium doesn't do it yet */
1702 return 0;
1703
1704 }
1705
1706 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1707 {
1708 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1709 struct r600_bc_alu_src r600_src[3];
1710 struct r600_bc_alu alu;
1711 unsigned i;
1712 int r;
1713
1714 r = tgsi_split_constant(ctx, r600_src);
1715 if (r)
1716 return r;
1717 /* 1 - src0 */
1718 for (i = 0; i < 4; i++) {
1719 memset(&alu, 0, sizeof(struct r600_bc_alu));
1720 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1721 alu.src[0].sel = V_SQ_ALU_SRC_1;
1722 alu.src[0].chan = 0;
1723 alu.src[1] = r600_src[0];
1724 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1725 alu.src[1].neg = 1;
1726 alu.dst.sel = ctx->temp_reg;
1727 alu.dst.chan = i;
1728 if (i == 3) {
1729 alu.last = 1;
1730 }
1731 alu.dst.write = 1;
1732 r = r600_bc_add_alu(ctx->bc, &alu);
1733 if (r)
1734 return r;
1735 }
1736 r = r600_bc_add_literal(ctx->bc, ctx->value);
1737 if (r)
1738 return r;
1739
1740 /* (1 - src0) * src2 */
1741 for (i = 0; i < 4; i++) {
1742 memset(&alu, 0, sizeof(struct r600_bc_alu));
1743 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1744 alu.src[0].sel = ctx->temp_reg;
1745 alu.src[0].chan = i;
1746 alu.src[1] = r600_src[2];
1747 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1748 alu.dst.sel = ctx->temp_reg;
1749 alu.dst.chan = i;
1750 if (i == 3) {
1751 alu.last = 1;
1752 }
1753 alu.dst.write = 1;
1754 r = r600_bc_add_alu(ctx->bc, &alu);
1755 if (r)
1756 return r;
1757 }
1758 r = r600_bc_add_literal(ctx->bc, ctx->value);
1759 if (r)
1760 return r;
1761
1762 /* src0 * src1 + (1 - src0) * src2 */
1763 for (i = 0; i < 4; i++) {
1764 memset(&alu, 0, sizeof(struct r600_bc_alu));
1765 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1766 alu.is_op3 = 1;
1767 alu.src[0] = r600_src[0];
1768 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1769 alu.src[1] = r600_src[1];
1770 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1771 alu.src[2].sel = ctx->temp_reg;
1772 alu.src[2].chan = i;
1773 alu.dst.sel = ctx->temp_reg;
1774 alu.dst.chan = i;
1775 if (i == 3) {
1776 alu.last = 1;
1777 }
1778 r = r600_bc_add_alu(ctx->bc, &alu);
1779 if (r)
1780 return r;
1781 }
1782 return tgsi_helper_copy(ctx, inst);
1783 }
1784
1785 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1786 {
1787 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1788 struct r600_bc_alu_src r600_src[3];
1789 struct r600_bc_alu alu;
1790 int use_temp = 0;
1791 int i, r;
1792
1793 r = tgsi_split_constant(ctx, r600_src);
1794 if (r)
1795 return r;
1796
1797 if (inst->Dst[0].Register.WriteMask != 0xf)
1798 use_temp = 1;
1799
1800 for (i = 0; i < 4; i++) {
1801 memset(&alu, 0, sizeof(struct r600_bc_alu));
1802 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1803 alu.src[0] = r600_src[0];
1804 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1805
1806 alu.src[1] = r600_src[2];
1807 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1808
1809 alu.src[2] = r600_src[1];
1810 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
1811
1812 if (use_temp)
1813 alu.dst.sel = ctx->temp_reg;
1814 else {
1815 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1816 if (r)
1817 return r;
1818 }
1819 alu.dst.chan = i;
1820 alu.dst.write = 1;
1821 alu.is_op3 = 1;
1822 if (i == 3)
1823 alu.last = 1;
1824 r = r600_bc_add_alu(ctx->bc, &alu);
1825 if (r)
1826 return r;
1827 }
1828 if (use_temp)
1829 return tgsi_helper_copy(ctx, inst);
1830 return 0;
1831 }
1832
1833 static int tgsi_xpd(struct r600_shader_ctx *ctx)
1834 {
1835 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1836 struct r600_bc_alu_src r600_src[3];
1837 struct r600_bc_alu alu;
1838 uint32_t use_temp = 0;
1839 int i, r;
1840
1841 if (inst->Dst[0].Register.WriteMask != 0xf)
1842 use_temp = 1;
1843
1844 r = tgsi_split_constant(ctx, r600_src);
1845 if (r)
1846 return r;
1847
1848 for (i = 0; i < 4; i++) {
1849 memset(&alu, 0, sizeof(struct r600_bc_alu));
1850 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1851
1852 alu.src[0] = r600_src[0];
1853 switch (i) {
1854 case 0:
1855 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1856 break;
1857 case 1:
1858 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1859 break;
1860 case 2:
1861 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1862 break;
1863 case 3:
1864 alu.src[0].sel = V_SQ_ALU_SRC_0;
1865 alu.src[0].chan = i;
1866 }
1867
1868 alu.src[1] = r600_src[1];
1869 switch (i) {
1870 case 0:
1871 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1872 break;
1873 case 1:
1874 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1875 break;
1876 case 2:
1877 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1878 break;
1879 case 3:
1880 alu.src[1].sel = V_SQ_ALU_SRC_0;
1881 alu.src[1].chan = i;
1882 }
1883
1884 alu.dst.sel = ctx->temp_reg;
1885 alu.dst.chan = i;
1886 alu.dst.write = 1;
1887
1888 if (i == 3)
1889 alu.last = 1;
1890 r = r600_bc_add_alu(ctx->bc, &alu);
1891 if (r)
1892 return r;
1893
1894 r = r600_bc_add_literal(ctx->bc, ctx->value);
1895 if (r)
1896 return r;
1897 }
1898
1899 for (i = 0; i < 4; i++) {
1900 memset(&alu, 0, sizeof(struct r600_bc_alu));
1901 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1902
1903 alu.src[0] = r600_src[0];
1904 switch (i) {
1905 case 0:
1906 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1907 break;
1908 case 1:
1909 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1910 break;
1911 case 2:
1912 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1913 break;
1914 case 3:
1915 alu.src[0].sel = V_SQ_ALU_SRC_0;
1916 alu.src[0].chan = i;
1917 }
1918
1919 alu.src[1] = r600_src[1];
1920 switch (i) {
1921 case 0:
1922 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1923 break;
1924 case 1:
1925 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1926 break;
1927 case 2:
1928 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1929 break;
1930 case 3:
1931 alu.src[1].sel = V_SQ_ALU_SRC_0;
1932 alu.src[1].chan = i;
1933 }
1934
1935 alu.src[2].sel = ctx->temp_reg;
1936 alu.src[2].neg = 1;
1937 alu.src[2].chan = i;
1938
1939 if (use_temp)
1940 alu.dst.sel = ctx->temp_reg;
1941 else {
1942 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1943 if (r)
1944 return r;
1945 }
1946 alu.dst.chan = i;
1947 alu.dst.write = 1;
1948 alu.is_op3 = 1;
1949 if (i == 3)
1950 alu.last = 1;
1951 r = r600_bc_add_alu(ctx->bc, &alu);
1952 if (r)
1953 return r;
1954
1955 r = r600_bc_add_literal(ctx->bc, ctx->value);
1956 if (r)
1957 return r;
1958 }
1959 if (use_temp)
1960 return tgsi_helper_copy(ctx, inst);
1961 return 0;
1962 }
1963
1964 static int tgsi_exp(struct r600_shader_ctx *ctx)
1965 {
1966 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1967 struct r600_bc_alu_src r600_src[3];
1968 struct r600_bc_alu alu;
1969 int r;
1970
1971 /* result.x = 2^floor(src); */
1972 if (inst->Dst[0].Register.WriteMask & 1) {
1973 memset(&alu, 0, sizeof(struct r600_bc_alu));
1974
1975 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
1976 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1977 if (r)
1978 return r;
1979
1980 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1981
1982 alu.dst.sel = ctx->temp_reg;
1983 alu.dst.chan = 0;
1984 alu.dst.write = 1;
1985 alu.last = 1;
1986 r = r600_bc_add_alu(ctx->bc, &alu);
1987 if (r)
1988 return r;
1989
1990 r = r600_bc_add_literal(ctx->bc, ctx->value);
1991 if (r)
1992 return r;
1993
1994 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1995 alu.src[0].sel = ctx->temp_reg;
1996 alu.src[0].chan = 0;
1997
1998 alu.dst.sel = ctx->temp_reg;
1999 alu.dst.chan = 0;
2000 alu.dst.write = 1;
2001 alu.last = 1;
2002 r = r600_bc_add_alu(ctx->bc, &alu);
2003 if (r)
2004 return r;
2005
2006 r = r600_bc_add_literal(ctx->bc, ctx->value);
2007 if (r)
2008 return r;
2009 }
2010
2011 /* result.y = tmp - floor(tmp); */
2012 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2013 memset(&alu, 0, sizeof(struct r600_bc_alu));
2014
2015 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2016 alu.src[0] = r600_src[0];
2017 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2018 if (r)
2019 return r;
2020 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2021
2022 alu.dst.sel = ctx->temp_reg;
2023 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2024 // if (r)
2025 // return r;
2026 alu.dst.write = 1;
2027 alu.dst.chan = 1;
2028
2029 alu.last = 1;
2030
2031 r = r600_bc_add_alu(ctx->bc, &alu);
2032 if (r)
2033 return r;
2034 r = r600_bc_add_literal(ctx->bc, ctx->value);
2035 if (r)
2036 return r;
2037 }
2038
2039 /* result.z = RoughApprox2ToX(tmp);*/
2040 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2041 memset(&alu, 0, sizeof(struct r600_bc_alu));
2042 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2043 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2044 if (r)
2045 return r;
2046 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2047
2048 alu.dst.sel = ctx->temp_reg;
2049 alu.dst.write = 1;
2050 alu.dst.chan = 2;
2051
2052 alu.last = 1;
2053
2054 r = r600_bc_add_alu(ctx->bc, &alu);
2055 if (r)
2056 return r;
2057 r = r600_bc_add_literal(ctx->bc, ctx->value);
2058 if (r)
2059 return r;
2060 }
2061
2062 /* result.w = 1.0;*/
2063 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2064 memset(&alu, 0, sizeof(struct r600_bc_alu));
2065
2066 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2067 alu.src[0].sel = V_SQ_ALU_SRC_1;
2068 alu.src[0].chan = 0;
2069
2070 alu.dst.sel = ctx->temp_reg;
2071 alu.dst.chan = 3;
2072 alu.dst.write = 1;
2073 alu.last = 1;
2074 r = r600_bc_add_alu(ctx->bc, &alu);
2075 if (r)
2076 return r;
2077 r = r600_bc_add_literal(ctx->bc, ctx->value);
2078 if (r)
2079 return r;
2080 }
2081 return tgsi_helper_copy(ctx, inst);
2082 }
2083
2084 static int tgsi_log(struct r600_shader_ctx *ctx)
2085 {
2086 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2087 struct r600_bc_alu alu;
2088 int r;
2089
2090 /* result.x = floor(log2(src)); */
2091 if (inst->Dst[0].Register.WriteMask & 1) {
2092 memset(&alu, 0, sizeof(struct r600_bc_alu));
2093
2094 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2095 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2096 if (r)
2097 return r;
2098
2099 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2100
2101 alu.dst.sel = ctx->temp_reg;
2102 alu.dst.chan = 0;
2103 alu.dst.write = 1;
2104 alu.last = 1;
2105 r = r600_bc_add_alu(ctx->bc, &alu);
2106 if (r)
2107 return r;
2108
2109 r = r600_bc_add_literal(ctx->bc, ctx->value);
2110 if (r)
2111 return r;
2112
2113 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2114 alu.src[0].sel = ctx->temp_reg;
2115 alu.src[0].chan = 0;
2116
2117 alu.dst.sel = ctx->temp_reg;
2118 alu.dst.chan = 0;
2119 alu.dst.write = 1;
2120 alu.last = 1;
2121
2122 r = r600_bc_add_alu(ctx->bc, &alu);
2123 if (r)
2124 return r;
2125
2126 r = r600_bc_add_literal(ctx->bc, ctx->value);
2127 if (r)
2128 return r;
2129 }
2130
2131 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2132 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2133 memset(&alu, 0, sizeof(struct r600_bc_alu));
2134
2135 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2136 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2137 if (r)
2138 return r;
2139
2140 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2141
2142 alu.dst.sel = ctx->temp_reg;
2143 alu.dst.chan = 1;
2144 alu.dst.write = 1;
2145 alu.last = 1;
2146
2147 r = r600_bc_add_alu(ctx->bc, &alu);
2148 if (r)
2149 return r;
2150
2151 r = r600_bc_add_literal(ctx->bc, ctx->value);
2152 if (r)
2153 return r;
2154
2155 memset(&alu, 0, sizeof(struct r600_bc_alu));
2156
2157 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2158 alu.src[0].sel = ctx->temp_reg;
2159 alu.src[0].chan = 1;
2160
2161 alu.dst.sel = ctx->temp_reg;
2162 alu.dst.chan = 1;
2163 alu.dst.write = 1;
2164 alu.last = 1;
2165
2166 r = r600_bc_add_alu(ctx->bc, &alu);
2167 if (r)
2168 return r;
2169
2170 r = r600_bc_add_literal(ctx->bc, ctx->value);
2171 if (r)
2172 return r;
2173
2174 memset(&alu, 0, sizeof(struct r600_bc_alu));
2175
2176 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2177 alu.src[0].sel = ctx->temp_reg;
2178 alu.src[0].chan = 1;
2179
2180 alu.dst.sel = ctx->temp_reg;
2181 alu.dst.chan = 1;
2182 alu.dst.write = 1;
2183 alu.last = 1;
2184
2185 r = r600_bc_add_alu(ctx->bc, &alu);
2186 if (r)
2187 return r;
2188
2189 r = r600_bc_add_literal(ctx->bc, ctx->value);
2190 if (r)
2191 return r;
2192
2193 memset(&alu, 0, sizeof(struct r600_bc_alu));
2194
2195 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2196 alu.src[0].sel = ctx->temp_reg;
2197 alu.src[0].chan = 1;
2198
2199 alu.dst.sel = ctx->temp_reg;
2200 alu.dst.chan = 1;
2201 alu.dst.write = 1;
2202 alu.last = 1;
2203
2204 r = r600_bc_add_alu(ctx->bc, &alu);
2205 if (r)
2206 return r;
2207
2208 r = r600_bc_add_literal(ctx->bc, ctx->value);
2209 if (r)
2210 return r;
2211
2212 memset(&alu, 0, sizeof(struct r600_bc_alu));
2213
2214 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2215
2216 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2217 if (r)
2218 return r;
2219
2220 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2221
2222 alu.src[1].sel = ctx->temp_reg;
2223 alu.src[1].chan = 1;
2224
2225 alu.dst.sel = ctx->temp_reg;
2226 alu.dst.chan = 1;
2227 alu.dst.write = 1;
2228 alu.last = 1;
2229
2230 r = r600_bc_add_alu(ctx->bc, &alu);
2231 if (r)
2232 return r;
2233
2234 r = r600_bc_add_literal(ctx->bc, ctx->value);
2235 if (r)
2236 return r;
2237 }
2238
2239 /* result.z = log2(src);*/
2240 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2241 memset(&alu, 0, sizeof(struct r600_bc_alu));
2242
2243 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2244 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2245 if (r)
2246 return r;
2247
2248 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2249
2250 alu.dst.sel = ctx->temp_reg;
2251 alu.dst.write = 1;
2252 alu.dst.chan = 2;
2253 alu.last = 1;
2254
2255 r = r600_bc_add_alu(ctx->bc, &alu);
2256 if (r)
2257 return r;
2258
2259 r = r600_bc_add_literal(ctx->bc, ctx->value);
2260 if (r)
2261 return r;
2262 }
2263
2264 /* result.w = 1.0; */
2265 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2266 memset(&alu, 0, sizeof(struct r600_bc_alu));
2267
2268 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2269 alu.src[0].sel = V_SQ_ALU_SRC_1;
2270 alu.src[0].chan = 0;
2271
2272 alu.dst.sel = ctx->temp_reg;
2273 alu.dst.chan = 3;
2274 alu.dst.write = 1;
2275 alu.last = 1;
2276
2277 r = r600_bc_add_alu(ctx->bc, &alu);
2278 if (r)
2279 return r;
2280
2281 r = r600_bc_add_literal(ctx->bc, ctx->value);
2282 if (r)
2283 return r;
2284 }
2285
2286 return tgsi_helper_copy(ctx, inst);
2287 }
2288
2289 /* r6/7 only for now */
2290 static int tgsi_arl(struct r600_shader_ctx *ctx)
2291 {
2292 /* TODO from r600c, ar values don't persist between clauses */
2293 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2294 struct r600_bc_alu alu;
2295 int r;
2296 memset(&alu, 0, sizeof(struct r600_bc_alu));
2297
2298 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2299
2300 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2301 if (r)
2302 return r;
2303 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2304
2305 alu.last = 1;
2306
2307 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2308 if (r)
2309 return r;
2310 return 0;
2311 }
2312
2313 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2314 {
2315 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2316 struct r600_bc_alu alu;
2317 int i, r = 0;
2318
2319 for (i = 0; i < 4; i++) {
2320 memset(&alu, 0, sizeof(struct r600_bc_alu));
2321
2322 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2323 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2324 if (r)
2325 return r;
2326
2327 if (i == 0 || i == 3) {
2328 alu.src[0].sel = V_SQ_ALU_SRC_1;
2329 } else {
2330 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2331 if (r)
2332 return r;
2333 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2334 }
2335
2336 if (i == 0 || i == 2) {
2337 alu.src[1].sel = V_SQ_ALU_SRC_1;
2338 } else {
2339 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2340 if (r)
2341 return r;
2342 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2343 }
2344 if (i == 3)
2345 alu.last = 1;
2346 r = r600_bc_add_alu(ctx->bc, &alu);
2347 if (r)
2348 return r;
2349 }
2350 return 0;
2351 }
2352
2353 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2354 {
2355 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2356 struct r600_bc_alu alu;
2357 int r;
2358
2359 memset(&alu, 0, sizeof(struct r600_bc_alu));
2360 alu.inst = opcode;
2361 alu.predicate = 1;
2362
2363 alu.dst.sel = ctx->temp_reg;
2364 alu.dst.write = 1;
2365 alu.dst.chan = 0;
2366
2367 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2368 if (r)
2369 return r;
2370 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2371 alu.src[1].sel = V_SQ_ALU_SRC_0;
2372 alu.src[1].chan = 0;
2373
2374 alu.last = 1;
2375
2376 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2377 if (r)
2378 return r;
2379 return 0;
2380 }
2381
2382 static int pops(struct r600_shader_ctx *ctx, int pops)
2383 {
2384 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2385 ctx->bc->cf_last->pop_count = pops;
2386 return 0;
2387 }
2388
2389 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2390 {
2391 switch(reason) {
2392 case FC_PUSH_VPM:
2393 ctx->bc->callstack[ctx->bc->call_sp].current--;
2394 break;
2395 case FC_PUSH_WQM:
2396 case FC_LOOP:
2397 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2398 break;
2399 case FC_REP:
2400 /* TOODO : for 16 vp asic should -= 2; */
2401 ctx->bc->callstack[ctx->bc->call_sp].current --;
2402 break;
2403 }
2404 }
2405
2406 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2407 {
2408 if (check_max_only) {
2409 int diff;
2410 switch (reason) {
2411 case FC_PUSH_VPM:
2412 diff = 1;
2413 break;
2414 case FC_PUSH_WQM:
2415 diff = 4;
2416 break;
2417 default:
2418 assert(0);
2419 diff = 0;
2420 }
2421 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2422 ctx->bc->callstack[ctx->bc->call_sp].max) {
2423 ctx->bc->callstack[ctx->bc->call_sp].max =
2424 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2425 }
2426 return;
2427 }
2428 switch (reason) {
2429 case FC_PUSH_VPM:
2430 ctx->bc->callstack[ctx->bc->call_sp].current++;
2431 break;
2432 case FC_PUSH_WQM:
2433 case FC_LOOP:
2434 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2435 break;
2436 case FC_REP:
2437 ctx->bc->callstack[ctx->bc->call_sp].current++;
2438 break;
2439 }
2440
2441 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2442 ctx->bc->callstack[ctx->bc->call_sp].max) {
2443 ctx->bc->callstack[ctx->bc->call_sp].max =
2444 ctx->bc->callstack[ctx->bc->call_sp].current;
2445 }
2446 }
2447
2448 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2449 {
2450 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2451
2452 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2453 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2454 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2455 sp->num_mid++;
2456 }
2457
2458 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2459 {
2460 ctx->bc->fc_sp++;
2461 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2462 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2463 }
2464
2465 static void fc_poplevel(struct r600_shader_ctx *ctx)
2466 {
2467 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2468 if (sp->mid) {
2469 free(sp->mid);
2470 sp->mid = NULL;
2471 }
2472 sp->num_mid = 0;
2473 sp->start = NULL;
2474 sp->type = 0;
2475 ctx->bc->fc_sp--;
2476 }
2477
2478 #if 0
2479 static int emit_return(struct r600_shader_ctx *ctx)
2480 {
2481 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2482 return 0;
2483 }
2484
2485 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2486 {
2487
2488 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2489 ctx->bc->cf_last->pop_count = pops;
2490 /* TODO work out offset */
2491 return 0;
2492 }
2493
2494 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2495 {
2496 return 0;
2497 }
2498
2499 static void emit_testflag(struct r600_shader_ctx *ctx)
2500 {
2501
2502 }
2503
2504 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2505 {
2506 emit_testflag(ctx);
2507 emit_jump_to_offset(ctx, 1, 4);
2508 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2509 pops(ctx, ifidx + 1);
2510 emit_return(ctx);
2511 }
2512
2513 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2514 {
2515 emit_testflag(ctx);
2516
2517 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2518 ctx->bc->cf_last->pop_count = 1;
2519
2520 fc_set_mid(ctx, fc_sp);
2521
2522 pops(ctx, 1);
2523 }
2524 #endif
2525
2526 static int tgsi_if(struct r600_shader_ctx *ctx)
2527 {
2528 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2529
2530 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2531
2532 fc_pushlevel(ctx, FC_IF);
2533
2534 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2535 return 0;
2536 }
2537
2538 static int tgsi_else(struct r600_shader_ctx *ctx)
2539 {
2540 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2541 ctx->bc->cf_last->pop_count = 1;
2542
2543 fc_set_mid(ctx, ctx->bc->fc_sp);
2544 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2545 return 0;
2546 }
2547
2548 static int tgsi_endif(struct r600_shader_ctx *ctx)
2549 {
2550 pops(ctx, 1);
2551 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2552 R600_ERR("if/endif unbalanced in shader\n");
2553 return -1;
2554 }
2555
2556 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2557 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2558 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2559 } else {
2560 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2561 }
2562 fc_poplevel(ctx);
2563
2564 callstack_decrease_current(ctx, FC_PUSH_VPM);
2565 return 0;
2566 }
2567
2568 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2569 {
2570 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2571
2572 fc_pushlevel(ctx, FC_LOOP);
2573
2574 /* check stack depth */
2575 callstack_check_depth(ctx, FC_LOOP, 0);
2576 return 0;
2577 }
2578
2579 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2580 {
2581 int i;
2582
2583 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2584
2585 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2586 R600_ERR("loop/endloop in shader code are not paired.\n");
2587 return -EINVAL;
2588 }
2589
2590 /* fixup loop pointers - from r600isa
2591 LOOP END points to CF after LOOP START,
2592 LOOP START point to CF after LOOP END
2593 BRK/CONT point to LOOP END CF
2594 */
2595 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2596
2597 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2598
2599 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2600 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2601 }
2602 /* TODO add LOOPRET support */
2603 fc_poplevel(ctx);
2604 callstack_decrease_current(ctx, FC_LOOP);
2605 return 0;
2606 }
2607
2608 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2609 {
2610 unsigned int fscp;
2611
2612 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2613 {
2614 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2615 break;
2616 }
2617
2618 if (fscp == 0) {
2619 R600_ERR("Break not inside loop/endloop pair\n");
2620 return -EINVAL;
2621 }
2622
2623 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2624 ctx->bc->cf_last->pop_count = 1;
2625
2626 fc_set_mid(ctx, fscp);
2627
2628 pops(ctx, 1);
2629 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2630 return 0;
2631 }
2632
2633 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2634 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2635 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2636 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2637 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2638 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2639 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2640 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2641 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2642 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2643 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2644 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2645 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2646 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2647 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2648 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2649 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2650 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2651 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2652 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2653 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2654 /* gap */
2655 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2656 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2657 /* gap */
2658 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2659 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2660 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2661 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2662 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2663 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2664 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2665 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2666 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2667 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2668 /* gap */
2669 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2670 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2671 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2672 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2673 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2674 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2675 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2676 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2677 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2678 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2679 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2680 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2681 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2682 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2683 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2684 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2685 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2686 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2687 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2688 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2689 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2690 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2691 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2692 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2693 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2694 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2695 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2696 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2697 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2698 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2699 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2700 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2701 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2702 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2703 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2704 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2705 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2706 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2707 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2708 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2709 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2710 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2711 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2712 /* gap */
2713 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2714 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2715 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2716 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2717 /* gap */
2718 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2719 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2720 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2721 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2722 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2723 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2724 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2725 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2726 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2727 /* gap */
2728 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2729 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2730 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2731 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2732 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2733 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2734 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2735 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2736 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2737 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2738 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2739 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2740 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2741 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2742 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2743 /* gap */
2744 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2745 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2746 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2747 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2748 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2749 /* gap */
2750 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2751 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2752 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2753 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2754 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2755 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2756 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2757 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2758 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2759 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2760 /* gap */
2761 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2762 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2763 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2764 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2765 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2766 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2767 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2768 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2769 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2770 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2771 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2772 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2773 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2774 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2775 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2776 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2777 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2778 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2779 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2780 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2781 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2782 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2783 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2784 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2785 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2786 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2787 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2788 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2789 };
2790
2791 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
2792 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2793 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2794 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2795 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2796 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
2797 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2798 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2799 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2800 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2801 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2802 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2803 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2804 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2805 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2806 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2807 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2808 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2809 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2810 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2811 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2812 /* gap */
2813 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2814 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2815 /* gap */
2816 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2817 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2818 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2819 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2820 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2821 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2822 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2823 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2824 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2825 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2826 /* gap */
2827 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2828 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2829 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2830 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2831 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2832 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2833 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2834 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2835 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2836 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2837 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2838 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2839 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2840 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2841 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2842 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2843 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2844 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2845 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2846 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2847 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2848 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2849 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2850 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2851 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2852 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2853 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2854 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2855 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2856 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2857 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2858 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2859 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2860 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2861 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2862 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2863 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2864 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2865 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2866 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2867 {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2868 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2869 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2870 /* gap */
2871 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2872 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2873 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2874 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2875 /* gap */
2876 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2877 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2878 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2879 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2880 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2881 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2882 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2883 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2884 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2885 /* gap */
2886 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2887 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2888 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2889 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2891 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2892 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2893 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2894 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2895 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2896 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2897 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2898 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2899 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2900 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2901 /* gap */
2902 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2903 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2904 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 /* gap */
2908 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2910 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2911 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2912 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2914 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2917 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2918 /* gap */
2919 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2920 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2921 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2922 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2924 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2926 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2927 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2932 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2934 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2937 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 };