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r600g: rename radeon_ws_bo to r600_bo
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 for (i = 0; i < 10; i++) {
48 spi_vs_out_id[i] = 0;
49 }
50 for (i = 0; i < 32; i++) {
51 tmp = i << ((i & 3) * 8);
52 spi_vs_out_id[i / 4] |= tmp;
53 }
54 for (i = 0; i < 10; i++) {
55 r600_pipe_state_add_reg(rstate,
56 R_028614_SPI_VS_OUT_ID_0 + i * 4,
57 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
58 }
59
60 r600_pipe_state_add_reg(rstate,
61 R_0286C4_SPI_VS_OUT_CONFIG,
62 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
63 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate,
65 R_028868_SQ_PGM_RESOURCES_VS,
66 S_028868_NUM_GPRS(rshader->bc.ngpr) |
67 S_028868_STACK_SIZE(rshader->bc.nstack),
68 0xFFFFFFFF, NULL);
69 r600_pipe_state_add_reg(rstate,
70 R_0288A4_SQ_PGM_RESOURCES_FS,
71 0x00000000, 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS,
77 0x00000000, 0xFFFFFFFF, NULL);
78 r600_pipe_state_add_reg(rstate,
79 R_028858_SQ_PGM_START_VS,
80 0x00000000, 0xFFFFFFFF, shader->bo);
81 r600_pipe_state_add_reg(rstate,
82 R_028894_SQ_PGM_START_FS,
83 0x00000000, 0xFFFFFFFF, shader->bo);
84
85 r600_pipe_state_add_reg(rstate,
86 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
87 0xFFFFFFFF, NULL);
88
89 }
90
91 int r600_find_vs_semantic_index(struct r600_shader *vs,
92 struct r600_shader *ps, int id)
93 {
94 struct r600_shader_io *input = &ps->input[id];
95
96 for (int i = 0; i < vs->noutput; i++) {
97 if (input->name == vs->output[i].name &&
98 input->sid == vs->output[i].sid) {
99 return i - 1;
100 }
101 }
102 return 0;
103 }
104
105 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
106 {
107 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
108 struct r600_pipe_state *rstate = &shader->rstate;
109 struct r600_shader *rshader = &shader->shader;
110 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
111 boolean have_pos = FALSE, have_face = FALSE;
112
113 /* clear previous register */
114 rstate->nregs = 0;
115
116 for (i = 0; i < rshader->ninput; i++) {
117 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
118 tmp |= S_028644_SEL_CENTROID(1);
119 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
120 have_pos = TRUE;
121 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
122 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
123 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
124 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
125 }
126 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
127 have_face = TRUE;
128 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
129 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
130 tmp |= S_028644_PT_SPRITE_TEX(1);
131 }
132 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
133 }
134 for (i = 0; i < rshader->noutput; i++) {
135 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
136 r600_pipe_state_add_reg(rstate,
137 R_02880C_DB_SHADER_CONTROL,
138 S_02880C_Z_EXPORT_ENABLE(1),
139 S_02880C_Z_EXPORT_ENABLE(1), NULL);
140 }
141
142 exports_ps = 0;
143 num_cout = 0;
144 for (i = 0; i < rshader->noutput; i++) {
145 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
146 exports_ps |= 1;
147 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
148 num_cout++;
149 }
150 }
151 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
152 if (!exports_ps) {
153 /* always at least export 1 component per pixel */
154 exports_ps = 2;
155 }
156
157 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
158 S_0286CC_PERSP_GRADIENT_ENA(1);
159 spi_input_z = 0;
160 if (have_pos) {
161 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
162 S_0286CC_BARYC_SAMPLE_CNTL(1);
163 spi_input_z |= 1;
164 }
165 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
166 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
167 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
168 r600_pipe_state_add_reg(rstate,
169 R_028840_SQ_PGM_START_PS,
170 0x00000000, 0xFFFFFFFF, shader->bo);
171 r600_pipe_state_add_reg(rstate,
172 R_028850_SQ_PGM_RESOURCES_PS,
173 S_028868_NUM_GPRS(rshader->bc.ngpr) |
174 S_028868_STACK_SIZE(rshader->bc.nstack),
175 0xFFFFFFFF, NULL);
176 r600_pipe_state_add_reg(rstate,
177 R_028854_SQ_PGM_EXPORTS_PS,
178 exports_ps, 0xFFFFFFFF, NULL);
179 r600_pipe_state_add_reg(rstate,
180 R_0288CC_SQ_PGM_CF_OFFSET_PS,
181 0x00000000, 0xFFFFFFFF, NULL);
182
183 if (rshader->uses_kill) {
184 /* only set some bits here, the other bits are set in the dsa state */
185 r600_pipe_state_add_reg(rstate,
186 R_02880C_DB_SHADER_CONTROL,
187 S_02880C_KILL_ENABLE(1),
188 S_02880C_KILL_ENABLE(1), NULL);
189 }
190 r600_pipe_state_add_reg(rstate,
191 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
192 0xFFFFFFFF, NULL);
193 }
194
195 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
196 {
197 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
198 struct r600_shader *rshader = &shader->shader;
199 void *ptr;
200
201 /* copy new shader */
202 if (shader->bo == NULL) {
203 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
204 if (shader->bo == NULL) {
205 return -ENOMEM;
206 }
207 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
208 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
209 r600_bo_unmap(rctx->radeon, shader->bo);
210 }
211 /* build state */
212 rshader->flat_shade = rctx->flatshade;
213 switch (rshader->processor_type) {
214 case TGSI_PROCESSOR_VERTEX:
215 if (rshader->family >= CHIP_CEDAR) {
216 evergreen_pipe_shader_vs(ctx, shader);
217 } else {
218 r600_pipe_shader_vs(ctx, shader);
219 }
220 break;
221 case TGSI_PROCESSOR_FRAGMENT:
222 if (rshader->family >= CHIP_CEDAR) {
223 evergreen_pipe_shader_ps(ctx, shader);
224 } else {
225 r600_pipe_shader_ps(ctx, shader);
226 }
227 break;
228 default:
229 return -EINVAL;
230 }
231 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
232 return 0;
233 }
234
235 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
236 {
237 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
238 struct r600_shader *shader = &rshader->shader;
239 const struct util_format_description *desc;
240 enum pipe_format resource_format[160];
241 unsigned i, nresources = 0;
242 struct r600_bc *bc = &shader->bc;
243 struct r600_bc_cf *cf;
244 struct r600_bc_vtx *vtx;
245
246 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
247 return 0;
248 /* doing a full memcmp fell over the refcount */
249 if ((rshader->vertex_elements.count == rctx->vertex_elements->count) &&
250 (!memcmp(&rshader->vertex_elements.elements, &rctx->vertex_elements->elements, 32 * sizeof(struct pipe_vertex_element)))) {
251 return 0;
252 }
253 rshader->vertex_elements = *rctx->vertex_elements;
254 for (i = 0; i < rctx->vertex_elements->count; i++) {
255 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
256 }
257 r600_bo_reference(rctx->radeon, &rshader->bo, NULL);
258 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
259 switch (cf->inst) {
260 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
261 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
262 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
263 desc = util_format_description(resource_format[vtx->buffer_id]);
264 if (desc == NULL) {
265 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
266 return -EINVAL;
267 }
268 vtx->dst_sel_x = desc->swizzle[0];
269 vtx->dst_sel_y = desc->swizzle[1];
270 vtx->dst_sel_z = desc->swizzle[2];
271 vtx->dst_sel_w = desc->swizzle[3];
272 }
273 break;
274 default:
275 break;
276 }
277 }
278 return r600_bc_build(&shader->bc);
279 }
280
281 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
282 {
283 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
284 int r;
285
286 if (shader == NULL)
287 return -EINVAL;
288 /* there should be enough input */
289 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
290 R600_ERR("%d resources provided, expecting %d\n",
291 rctx->vertex_elements->count, shader->shader.bc.nresource);
292 return -EINVAL;
293 }
294 r = r600_shader_update(ctx, shader);
295 if (r)
296 return r;
297 return r600_pipe_shader(ctx, shader);
298 }
299
300 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
301 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
302 {
303 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
304 int r;
305
306 //fprintf(stderr, "--------------------------------------------------------------\n");
307 //tgsi_dump(tokens, 0);
308 shader->shader.family = r600_get_family(rctx->radeon);
309 r = r600_shader_from_tgsi(tokens, &shader->shader);
310 if (r) {
311 R600_ERR("translation from TGSI failed !\n");
312 return r;
313 }
314 r = r600_bc_build(&shader->shader.bc);
315 if (r) {
316 R600_ERR("building bytecode failed !\n");
317 return r;
318 }
319 //fprintf(stderr, "______________________________________________________________\n");
320 return 0;
321 }
322
323 /*
324 * tgsi -> r600 shader
325 */
326 struct r600_shader_tgsi_instruction;
327
328 struct r600_shader_ctx {
329 struct tgsi_shader_info info;
330 struct tgsi_parse_context parse;
331 const struct tgsi_token *tokens;
332 unsigned type;
333 unsigned file_offset[TGSI_FILE_COUNT];
334 unsigned temp_reg;
335 struct r600_shader_tgsi_instruction *inst_info;
336 struct r600_bc *bc;
337 struct r600_shader *shader;
338 u32 value[4];
339 u32 *literals;
340 u32 nliterals;
341 u32 max_driver_temp_used;
342 };
343
344 struct r600_shader_tgsi_instruction {
345 unsigned tgsi_opcode;
346 unsigned is_op3;
347 unsigned r600_opcode;
348 int (*process)(struct r600_shader_ctx *ctx);
349 };
350
351 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
352 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
353
354 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
355 {
356 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
357 int j;
358
359 if (i->Instruction.NumDstRegs > 1) {
360 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
361 return -EINVAL;
362 }
363 if (i->Instruction.Predicate) {
364 R600_ERR("predicate unsupported\n");
365 return -EINVAL;
366 }
367 #if 0
368 if (i->Instruction.Label) {
369 R600_ERR("label unsupported\n");
370 return -EINVAL;
371 }
372 #endif
373 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
374 if (i->Src[j].Register.Dimension ||
375 i->Src[j].Register.Absolute) {
376 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
377 i->Src[j].Register.Dimension,
378 i->Src[j].Register.Absolute);
379 return -EINVAL;
380 }
381 }
382 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
383 if (i->Dst[j].Register.Dimension) {
384 R600_ERR("unsupported dst (dimension)\n");
385 return -EINVAL;
386 }
387 }
388 return 0;
389 }
390
391 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
392 {
393 int i, r;
394 struct r600_bc_alu alu;
395
396 for (i = 0; i < 8; i++) {
397 memset(&alu, 0, sizeof(struct r600_bc_alu));
398
399 if (i < 4)
400 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
401 else
402 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
403
404 if ((i > 1) && (i < 6)) {
405 alu.dst.sel = ctx->shader->input[gpr].gpr;
406 alu.dst.write = 1;
407 }
408
409 alu.dst.chan = i % 4;
410 alu.src[0].chan = (1 - (i % 2));
411 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
412
413 alu.bank_swizzle_force = SQ_ALU_VEC_210;
414 if ((i % 4) == 3)
415 alu.last = 1;
416 r = r600_bc_add_alu(ctx->bc, &alu);
417 if (r)
418 return r;
419 }
420 return 0;
421 }
422
423
424 static int tgsi_declaration(struct r600_shader_ctx *ctx)
425 {
426 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
427 struct r600_bc_vtx vtx;
428 unsigned i;
429 int r;
430
431 switch (d->Declaration.File) {
432 case TGSI_FILE_INPUT:
433 i = ctx->shader->ninput++;
434 ctx->shader->input[i].name = d->Semantic.Name;
435 ctx->shader->input[i].sid = d->Semantic.Index;
436 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
437 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
438 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
439 /* turn input into fetch */
440 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
441 vtx.inst = 0;
442 vtx.fetch_type = 0;
443 vtx.buffer_id = i;
444 /* register containing the index into the buffer */
445 vtx.src_gpr = 0;
446 vtx.src_sel_x = 0;
447 vtx.mega_fetch_count = 0x1F;
448 vtx.dst_gpr = ctx->shader->input[i].gpr;
449 vtx.dst_sel_x = 0;
450 vtx.dst_sel_y = 1;
451 vtx.dst_sel_z = 2;
452 vtx.dst_sel_w = 3;
453 vtx.use_const_fields = 1;
454 r = r600_bc_add_vtx(ctx->bc, &vtx);
455 if (r)
456 return r;
457 }
458 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
459 /* turn input into interpolate on EG */
460 evergreen_interp_alu(ctx, i);
461 }
462 break;
463 case TGSI_FILE_OUTPUT:
464 i = ctx->shader->noutput++;
465 ctx->shader->output[i].name = d->Semantic.Name;
466 ctx->shader->output[i].sid = d->Semantic.Index;
467 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
468 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
469 break;
470 case TGSI_FILE_CONSTANT:
471 case TGSI_FILE_TEMPORARY:
472 case TGSI_FILE_SAMPLER:
473 case TGSI_FILE_ADDRESS:
474 break;
475 default:
476 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
477 return -EINVAL;
478 }
479 return 0;
480 }
481
482 static int r600_get_temp(struct r600_shader_ctx *ctx)
483 {
484 return ctx->temp_reg + ctx->max_driver_temp_used++;
485 }
486
487 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
488 {
489 struct tgsi_full_immediate *immediate;
490 struct r600_shader_ctx ctx;
491 struct r600_bc_output output[32];
492 unsigned output_done, noutput;
493 unsigned opcode;
494 int i, r = 0, pos0;
495
496 ctx.bc = &shader->bc;
497 ctx.shader = shader;
498 r = r600_bc_init(ctx.bc, shader->family);
499 if (r)
500 return r;
501 ctx.bc->use_mem_constant = shader->use_mem_constant;
502 ctx.tokens = tokens;
503 tgsi_scan_shader(tokens, &ctx.info);
504 tgsi_parse_init(&ctx.parse, tokens);
505 ctx.type = ctx.parse.FullHeader.Processor.Processor;
506 shader->processor_type = ctx.type;
507
508 /* register allocations */
509 /* Values [0,127] correspond to GPR[0..127].
510 * Values [128,159] correspond to constant buffer bank 0
511 * Values [160,191] correspond to constant buffer bank 1
512 * Values [256,511] correspond to cfile constants c[0..255].
513 * Other special values are shown in the list below.
514 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
515 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
516 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
517 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
518 * 248 SQ_ALU_SRC_0: special constant 0.0.
519 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
520 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
521 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
522 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
523 * 253 SQ_ALU_SRC_LITERAL: literal constant.
524 * 254 SQ_ALU_SRC_PV: previous vector result.
525 * 255 SQ_ALU_SRC_PS: previous scalar result.
526 */
527 for (i = 0; i < TGSI_FILE_COUNT; i++) {
528 ctx.file_offset[i] = 0;
529 }
530 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
531 ctx.file_offset[TGSI_FILE_INPUT] = 1;
532 }
533 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
534 ctx.info.file_count[TGSI_FILE_INPUT];
535 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
536 ctx.info.file_count[TGSI_FILE_OUTPUT];
537 if (ctx.shader->use_mem_constant)
538 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
539 else
540 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
541
542 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
543 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
544 ctx.info.file_count[TGSI_FILE_TEMPORARY];
545
546 ctx.nliterals = 0;
547 ctx.literals = NULL;
548
549 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
550 tgsi_parse_token(&ctx.parse);
551 switch (ctx.parse.FullToken.Token.Type) {
552 case TGSI_TOKEN_TYPE_IMMEDIATE:
553 immediate = &ctx.parse.FullToken.FullImmediate;
554 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
555 if(ctx.literals == NULL) {
556 r = -ENOMEM;
557 goto out_err;
558 }
559 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
560 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
561 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
562 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
563 ctx.nliterals++;
564 break;
565 case TGSI_TOKEN_TYPE_DECLARATION:
566 r = tgsi_declaration(&ctx);
567 if (r)
568 goto out_err;
569 break;
570 case TGSI_TOKEN_TYPE_INSTRUCTION:
571 r = tgsi_is_supported(&ctx);
572 if (r)
573 goto out_err;
574 ctx.max_driver_temp_used = 0;
575 /* reserve first tmp for everyone */
576 r600_get_temp(&ctx);
577 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
578 if (ctx.bc->chiprev == 2)
579 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
580 else
581 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
582 r = ctx.inst_info->process(&ctx);
583 if (r)
584 goto out_err;
585 r = r600_bc_add_literal(ctx.bc, ctx.value);
586 if (r)
587 goto out_err;
588 break;
589 default:
590 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
591 r = -EINVAL;
592 goto out_err;
593 }
594 }
595 /* export output */
596 noutput = shader->noutput;
597 for (i = 0, pos0 = 0; i < noutput; i++) {
598 memset(&output[i], 0, sizeof(struct r600_bc_output));
599 output[i].gpr = shader->output[i].gpr;
600 output[i].elem_size = 3;
601 output[i].swizzle_x = 0;
602 output[i].swizzle_y = 1;
603 output[i].swizzle_z = 2;
604 output[i].swizzle_w = 3;
605 output[i].barrier = 1;
606 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
607 output[i].array_base = i - pos0;
608 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
609 switch (ctx.type) {
610 case TGSI_PROCESSOR_VERTEX:
611 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
612 output[i].array_base = 60;
613 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
614 /* position doesn't count in array_base */
615 pos0++;
616 }
617 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
618 output[i].array_base = 61;
619 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
620 /* position doesn't count in array_base */
621 pos0++;
622 }
623 break;
624 case TGSI_PROCESSOR_FRAGMENT:
625 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
626 output[i].array_base = shader->output[i].sid;
627 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
628 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
629 output[i].array_base = 61;
630 output[i].swizzle_x = 2;
631 output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
632 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
633 } else {
634 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
635 r = -EINVAL;
636 goto out_err;
637 }
638 break;
639 default:
640 R600_ERR("unsupported processor type %d\n", ctx.type);
641 r = -EINVAL;
642 goto out_err;
643 }
644 }
645 /* add fake param output for vertex shader if no param is exported */
646 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
647 for (i = 0, pos0 = 0; i < noutput; i++) {
648 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
649 pos0 = 1;
650 break;
651 }
652 }
653 if (!pos0) {
654 memset(&output[i], 0, sizeof(struct r600_bc_output));
655 output[i].gpr = 0;
656 output[i].elem_size = 3;
657 output[i].swizzle_x = 0;
658 output[i].swizzle_y = 1;
659 output[i].swizzle_z = 2;
660 output[i].swizzle_w = 3;
661 output[i].barrier = 1;
662 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
663 output[i].array_base = 0;
664 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
665 noutput++;
666 }
667 }
668 /* add fake pixel export */
669 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
670 memset(&output[0], 0, sizeof(struct r600_bc_output));
671 output[0].gpr = 0;
672 output[0].elem_size = 3;
673 output[0].swizzle_x = 7;
674 output[0].swizzle_y = 7;
675 output[0].swizzle_z = 7;
676 output[0].swizzle_w = 7;
677 output[0].barrier = 1;
678 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
679 output[0].array_base = 0;
680 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
681 noutput++;
682 }
683 /* set export done on last export of each type */
684 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
685 if (i == (noutput - 1)) {
686 output[i].end_of_program = 1;
687 }
688 if (!(output_done & (1 << output[i].type))) {
689 output_done |= (1 << output[i].type);
690 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
691 }
692 }
693 /* add output to bytecode */
694 for (i = 0; i < noutput; i++) {
695 r = r600_bc_add_output(ctx.bc, &output[i]);
696 if (r)
697 goto out_err;
698 }
699 free(ctx.literals);
700 tgsi_parse_free(&ctx.parse);
701 return 0;
702 out_err:
703 free(ctx.literals);
704 tgsi_parse_free(&ctx.parse);
705 return r;
706 }
707
708 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
709 {
710 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
711 return -EINVAL;
712 }
713
714 static int tgsi_end(struct r600_shader_ctx *ctx)
715 {
716 return 0;
717 }
718
719 static int tgsi_src(struct r600_shader_ctx *ctx,
720 const struct tgsi_full_src_register *tgsi_src,
721 struct r600_bc_alu_src *r600_src)
722 {
723 int index;
724 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
725 r600_src->sel = tgsi_src->Register.Index;
726 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
727 r600_src->sel = 0;
728 index = tgsi_src->Register.Index;
729 ctx->value[0] = ctx->literals[index * 4 + 0];
730 ctx->value[1] = ctx->literals[index * 4 + 1];
731 ctx->value[2] = ctx->literals[index * 4 + 2];
732 ctx->value[3] = ctx->literals[index * 4 + 3];
733 }
734 if (tgsi_src->Register.Indirect)
735 r600_src->rel = V_SQ_REL_RELATIVE;
736 r600_src->neg = tgsi_src->Register.Negate;
737 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
738 return 0;
739 }
740
741 static int tgsi_dst(struct r600_shader_ctx *ctx,
742 const struct tgsi_full_dst_register *tgsi_dst,
743 unsigned swizzle,
744 struct r600_bc_alu_dst *r600_dst)
745 {
746 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
747
748 r600_dst->sel = tgsi_dst->Register.Index;
749 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
750 r600_dst->chan = swizzle;
751 r600_dst->write = 1;
752 if (tgsi_dst->Register.Indirect)
753 r600_dst->rel = V_SQ_REL_RELATIVE;
754 if (inst->Instruction.Saturate) {
755 r600_dst->clamp = 1;
756 }
757 return 0;
758 }
759
760 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
761 {
762 switch (swizzle) {
763 case 0:
764 return tgsi_src->Register.SwizzleX;
765 case 1:
766 return tgsi_src->Register.SwizzleY;
767 case 2:
768 return tgsi_src->Register.SwizzleZ;
769 case 3:
770 return tgsi_src->Register.SwizzleW;
771 default:
772 return 0;
773 }
774 }
775
776 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
777 {
778 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
779 struct r600_bc_alu alu;
780 int i, j, k, nconst, r;
781
782 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
783 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
784 nconst++;
785 }
786 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
787 if (r) {
788 return r;
789 }
790 }
791 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
792 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
793 int treg = r600_get_temp(ctx);
794 for (k = 0; k < 4; k++) {
795 memset(&alu, 0, sizeof(struct r600_bc_alu));
796 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
797 alu.src[0].sel = r600_src[i].sel;
798 alu.src[0].chan = k;
799 alu.dst.sel = treg;
800 alu.dst.chan = k;
801 alu.dst.write = 1;
802 if (k == 3)
803 alu.last = 1;
804 r = r600_bc_add_alu(ctx->bc, &alu);
805 if (r)
806 return r;
807 }
808 r600_src[i].sel = treg;
809 j--;
810 }
811 }
812 return 0;
813 }
814
815 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
816 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
817 {
818 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
819 struct r600_bc_alu alu;
820 int i, j, k, nliteral, r;
821
822 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
823 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
824 nliteral++;
825 }
826 }
827 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
828 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
829 int treg = r600_get_temp(ctx);
830 for (k = 0; k < 4; k++) {
831 memset(&alu, 0, sizeof(struct r600_bc_alu));
832 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
833 alu.src[0].sel = r600_src[i].sel;
834 alu.src[0].chan = k;
835 alu.dst.sel = treg;
836 alu.dst.chan = k;
837 alu.dst.write = 1;
838 if (k == 3)
839 alu.last = 1;
840 r = r600_bc_add_alu(ctx->bc, &alu);
841 if (r)
842 return r;
843 }
844 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
845 if (r)
846 return r;
847 r600_src[i].sel = treg;
848 j--;
849 }
850 }
851 return 0;
852 }
853
854 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
855 {
856 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
857 struct r600_bc_alu_src r600_src[3];
858 struct r600_bc_alu alu;
859 int i, j, r;
860 int lasti = 0;
861
862 for (i = 0; i < 4; i++) {
863 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
864 lasti = i;
865 }
866 }
867
868 r = tgsi_split_constant(ctx, r600_src);
869 if (r)
870 return r;
871 r = tgsi_split_literal_constant(ctx, r600_src);
872 if (r)
873 return r;
874 for (i = 0; i < lasti + 1; i++) {
875 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
876 continue;
877
878 memset(&alu, 0, sizeof(struct r600_bc_alu));
879 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
880 if (r)
881 return r;
882
883 alu.inst = ctx->inst_info->r600_opcode;
884 if (!swap) {
885 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
886 alu.src[j] = r600_src[j];
887 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
888 }
889 } else {
890 alu.src[0] = r600_src[1];
891 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
892
893 alu.src[1] = r600_src[0];
894 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
895 }
896 /* handle some special cases */
897 switch (ctx->inst_info->tgsi_opcode) {
898 case TGSI_OPCODE_SUB:
899 alu.src[1].neg = 1;
900 break;
901 case TGSI_OPCODE_ABS:
902 alu.src[0].abs = 1;
903 break;
904 default:
905 break;
906 }
907 if (i == lasti) {
908 alu.last = 1;
909 }
910 r = r600_bc_add_alu(ctx->bc, &alu);
911 if (r)
912 return r;
913 }
914 return 0;
915 }
916
917 static int tgsi_op2(struct r600_shader_ctx *ctx)
918 {
919 return tgsi_op2_s(ctx, 0);
920 }
921
922 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
923 {
924 return tgsi_op2_s(ctx, 1);
925 }
926
927 /*
928 * r600 - trunc to -PI..PI range
929 * r700 - normalize by dividing by 2PI
930 * see fdo bug 27901
931 */
932 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
933 struct r600_bc_alu_src r600_src[3])
934 {
935 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
936 int r;
937 uint32_t lit_vals[4];
938 struct r600_bc_alu alu;
939
940 memset(lit_vals, 0, 4*4);
941 r = tgsi_split_constant(ctx, r600_src);
942 if (r)
943 return r;
944 r = tgsi_split_literal_constant(ctx, r600_src);
945 if (r)
946 return r;
947
948 r = tgsi_split_literal_constant(ctx, r600_src);
949 if (r)
950 return r;
951
952 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
953 lit_vals[1] = fui(0.5f);
954
955 memset(&alu, 0, sizeof(struct r600_bc_alu));
956 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
957 alu.is_op3 = 1;
958
959 alu.dst.chan = 0;
960 alu.dst.sel = ctx->temp_reg;
961 alu.dst.write = 1;
962
963 alu.src[0] = r600_src[0];
964 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
965
966 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
967 alu.src[1].chan = 0;
968 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
969 alu.src[2].chan = 1;
970 alu.last = 1;
971 r = r600_bc_add_alu(ctx->bc, &alu);
972 if (r)
973 return r;
974 r = r600_bc_add_literal(ctx->bc, lit_vals);
975 if (r)
976 return r;
977
978 memset(&alu, 0, sizeof(struct r600_bc_alu));
979 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
980
981 alu.dst.chan = 0;
982 alu.dst.sel = ctx->temp_reg;
983 alu.dst.write = 1;
984
985 alu.src[0].sel = ctx->temp_reg;
986 alu.src[0].chan = 0;
987 alu.last = 1;
988 r = r600_bc_add_alu(ctx->bc, &alu);
989 if (r)
990 return r;
991
992 if (ctx->bc->chiprev == 0) {
993 lit_vals[0] = fui(3.1415926535897f * 2.0f);
994 lit_vals[1] = fui(-3.1415926535897f);
995 } else {
996 lit_vals[0] = fui(1.0f);
997 lit_vals[1] = fui(-0.5f);
998 }
999
1000 memset(&alu, 0, sizeof(struct r600_bc_alu));
1001 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1002 alu.is_op3 = 1;
1003
1004 alu.dst.chan = 0;
1005 alu.dst.sel = ctx->temp_reg;
1006 alu.dst.write = 1;
1007
1008 alu.src[0].sel = ctx->temp_reg;
1009 alu.src[0].chan = 0;
1010
1011 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1012 alu.src[1].chan = 0;
1013 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1014 alu.src[2].chan = 1;
1015 alu.last = 1;
1016 r = r600_bc_add_alu(ctx->bc, &alu);
1017 if (r)
1018 return r;
1019 r = r600_bc_add_literal(ctx->bc, lit_vals);
1020 if (r)
1021 return r;
1022 return 0;
1023 }
1024
1025 static int tgsi_trig(struct r600_shader_ctx *ctx)
1026 {
1027 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1028 struct r600_bc_alu_src r600_src[3];
1029 struct r600_bc_alu alu;
1030 int i, r;
1031 int lasti = 0;
1032
1033 r = tgsi_setup_trig(ctx, r600_src);
1034 if (r)
1035 return r;
1036
1037 memset(&alu, 0, sizeof(struct r600_bc_alu));
1038 alu.inst = ctx->inst_info->r600_opcode;
1039 alu.dst.chan = 0;
1040 alu.dst.sel = ctx->temp_reg;
1041 alu.dst.write = 1;
1042
1043 alu.src[0].sel = ctx->temp_reg;
1044 alu.src[0].chan = 0;
1045 alu.last = 1;
1046 r = r600_bc_add_alu(ctx->bc, &alu);
1047 if (r)
1048 return r;
1049
1050 /* replicate result */
1051 for (i = 0; i < 4; i++) {
1052 if (inst->Dst[0].Register.WriteMask & (1 << i))
1053 lasti = i;
1054 }
1055 for (i = 0; i < lasti + 1; i++) {
1056 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1057 continue;
1058
1059 memset(&alu, 0, sizeof(struct r600_bc_alu));
1060 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1061
1062 alu.src[0].sel = ctx->temp_reg;
1063 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1064 if (r)
1065 return r;
1066 if (i == lasti)
1067 alu.last = 1;
1068 r = r600_bc_add_alu(ctx->bc, &alu);
1069 if (r)
1070 return r;
1071 }
1072 return 0;
1073 }
1074
1075 static int tgsi_scs(struct r600_shader_ctx *ctx)
1076 {
1077 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1078 struct r600_bc_alu_src r600_src[3];
1079 struct r600_bc_alu alu;
1080 int r;
1081
1082 /* We'll only need the trig stuff if we are going to write to the
1083 * X or Y components of the destination vector.
1084 */
1085 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1086 r = tgsi_setup_trig(ctx, r600_src);
1087 if (r)
1088 return r;
1089 }
1090
1091 /* dst.x = COS */
1092 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1093 memset(&alu, 0, sizeof(struct r600_bc_alu));
1094 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1095 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1096 if (r)
1097 return r;
1098
1099 alu.src[0].sel = ctx->temp_reg;
1100 alu.src[0].chan = 0;
1101 alu.last = 1;
1102 r = r600_bc_add_alu(ctx->bc, &alu);
1103 if (r)
1104 return r;
1105 }
1106
1107 /* dst.y = SIN */
1108 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1109 memset(&alu, 0, sizeof(struct r600_bc_alu));
1110 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1111 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1112 if (r)
1113 return r;
1114
1115 alu.src[0].sel = ctx->temp_reg;
1116 alu.src[0].chan = 0;
1117 alu.last = 1;
1118 r = r600_bc_add_alu(ctx->bc, &alu);
1119 if (r)
1120 return r;
1121 }
1122
1123 /* dst.z = 0.0; */
1124 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1125 memset(&alu, 0, sizeof(struct r600_bc_alu));
1126
1127 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1128
1129 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1130 if (r)
1131 return r;
1132
1133 alu.src[0].sel = V_SQ_ALU_SRC_0;
1134 alu.src[0].chan = 0;
1135
1136 alu.last = 1;
1137
1138 r = r600_bc_add_alu(ctx->bc, &alu);
1139 if (r)
1140 return r;
1141
1142 r = r600_bc_add_literal(ctx->bc, ctx->value);
1143 if (r)
1144 return r;
1145 }
1146
1147 /* dst.w = 1.0; */
1148 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1149 memset(&alu, 0, sizeof(struct r600_bc_alu));
1150
1151 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1152
1153 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1154 if (r)
1155 return r;
1156
1157 alu.src[0].sel = V_SQ_ALU_SRC_1;
1158 alu.src[0].chan = 0;
1159
1160 alu.last = 1;
1161
1162 r = r600_bc_add_alu(ctx->bc, &alu);
1163 if (r)
1164 return r;
1165
1166 r = r600_bc_add_literal(ctx->bc, ctx->value);
1167 if (r)
1168 return r;
1169 }
1170
1171 return 0;
1172 }
1173
1174 static int tgsi_kill(struct r600_shader_ctx *ctx)
1175 {
1176 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1177 struct r600_bc_alu alu;
1178 int i, r;
1179
1180 for (i = 0; i < 4; i++) {
1181 memset(&alu, 0, sizeof(struct r600_bc_alu));
1182 alu.inst = ctx->inst_info->r600_opcode;
1183
1184 alu.dst.chan = i;
1185
1186 alu.src[0].sel = V_SQ_ALU_SRC_0;
1187
1188 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1189 alu.src[1].sel = V_SQ_ALU_SRC_1;
1190 alu.src[1].neg = 1;
1191 } else {
1192 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1193 if (r)
1194 return r;
1195 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1196 }
1197 if (i == 3) {
1198 alu.last = 1;
1199 }
1200 r = r600_bc_add_alu(ctx->bc, &alu);
1201 if (r)
1202 return r;
1203 }
1204 r = r600_bc_add_literal(ctx->bc, ctx->value);
1205 if (r)
1206 return r;
1207
1208 /* kill must be last in ALU */
1209 ctx->bc->force_add_cf = 1;
1210 ctx->shader->uses_kill = TRUE;
1211 return 0;
1212 }
1213
1214 static int tgsi_lit(struct r600_shader_ctx *ctx)
1215 {
1216 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1217 struct r600_bc_alu alu;
1218 struct r600_bc_alu_src r600_src[3];
1219 int r;
1220
1221 r = tgsi_split_constant(ctx, r600_src);
1222 if (r)
1223 return r;
1224 r = tgsi_split_literal_constant(ctx, r600_src);
1225 if (r)
1226 return r;
1227
1228 /* dst.x, <- 1.0 */
1229 memset(&alu, 0, sizeof(struct r600_bc_alu));
1230 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1231 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1232 alu.src[0].chan = 0;
1233 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1234 if (r)
1235 return r;
1236 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1237 r = r600_bc_add_alu(ctx->bc, &alu);
1238 if (r)
1239 return r;
1240
1241 /* dst.y = max(src.x, 0.0) */
1242 memset(&alu, 0, sizeof(struct r600_bc_alu));
1243 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1244 alu.src[0] = r600_src[0];
1245 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1246 alu.src[1].chan = 0;
1247 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1248 if (r)
1249 return r;
1250 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1251 r = r600_bc_add_alu(ctx->bc, &alu);
1252 if (r)
1253 return r;
1254
1255 /* dst.w, <- 1.0 */
1256 memset(&alu, 0, sizeof(struct r600_bc_alu));
1257 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1258 alu.src[0].sel = V_SQ_ALU_SRC_1;
1259 alu.src[0].chan = 0;
1260 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1261 if (r)
1262 return r;
1263 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1264 alu.last = 1;
1265 r = r600_bc_add_alu(ctx->bc, &alu);
1266 if (r)
1267 return r;
1268
1269 r = r600_bc_add_literal(ctx->bc, ctx->value);
1270 if (r)
1271 return r;
1272
1273 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1274 {
1275 int chan;
1276 int sel;
1277
1278 /* dst.z = log(src.y) */
1279 memset(&alu, 0, sizeof(struct r600_bc_alu));
1280 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1281 alu.src[0] = r600_src[0];
1282 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1283 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1284 if (r)
1285 return r;
1286 alu.last = 1;
1287 r = r600_bc_add_alu(ctx->bc, &alu);
1288 if (r)
1289 return r;
1290
1291 r = r600_bc_add_literal(ctx->bc, ctx->value);
1292 if (r)
1293 return r;
1294
1295 chan = alu.dst.chan;
1296 sel = alu.dst.sel;
1297
1298 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1299 memset(&alu, 0, sizeof(struct r600_bc_alu));
1300 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1301 alu.src[0] = r600_src[0];
1302 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1303 alu.src[1].sel = sel;
1304 alu.src[1].chan = chan;
1305
1306 alu.src[2] = r600_src[0];
1307 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1308 alu.dst.sel = ctx->temp_reg;
1309 alu.dst.chan = 0;
1310 alu.dst.write = 1;
1311 alu.is_op3 = 1;
1312 alu.last = 1;
1313 r = r600_bc_add_alu(ctx->bc, &alu);
1314 if (r)
1315 return r;
1316
1317 r = r600_bc_add_literal(ctx->bc, ctx->value);
1318 if (r)
1319 return r;
1320 /* dst.z = exp(tmp.x) */
1321 memset(&alu, 0, sizeof(struct r600_bc_alu));
1322 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1323 alu.src[0].sel = ctx->temp_reg;
1324 alu.src[0].chan = 0;
1325 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1326 if (r)
1327 return r;
1328 alu.last = 1;
1329 r = r600_bc_add_alu(ctx->bc, &alu);
1330 if (r)
1331 return r;
1332 }
1333 return 0;
1334 }
1335
1336 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1337 {
1338 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1339 struct r600_bc_alu alu;
1340 int i, r;
1341
1342 memset(&alu, 0, sizeof(struct r600_bc_alu));
1343
1344 /* FIXME:
1345 * For state trackers other than OpenGL, we'll want to use
1346 * _RECIPSQRT_IEEE instead.
1347 */
1348 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1349
1350 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1351 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1352 if (r)
1353 return r;
1354 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1355 alu.src[i].abs = 1;
1356 }
1357 alu.dst.sel = ctx->temp_reg;
1358 alu.dst.write = 1;
1359 alu.last = 1;
1360 r = r600_bc_add_alu(ctx->bc, &alu);
1361 if (r)
1362 return r;
1363 r = r600_bc_add_literal(ctx->bc, ctx->value);
1364 if (r)
1365 return r;
1366 /* replicate result */
1367 return tgsi_helper_tempx_replicate(ctx);
1368 }
1369
1370 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1371 {
1372 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1373 struct r600_bc_alu alu;
1374 int i, r;
1375
1376 for (i = 0; i < 4; i++) {
1377 memset(&alu, 0, sizeof(struct r600_bc_alu));
1378 alu.src[0].sel = ctx->temp_reg;
1379 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1380 alu.dst.chan = i;
1381 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1382 if (r)
1383 return r;
1384 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1385 if (i == 3)
1386 alu.last = 1;
1387 r = r600_bc_add_alu(ctx->bc, &alu);
1388 if (r)
1389 return r;
1390 }
1391 return 0;
1392 }
1393
1394 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1395 {
1396 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1397 struct r600_bc_alu alu;
1398 int i, r;
1399
1400 memset(&alu, 0, sizeof(struct r600_bc_alu));
1401 alu.inst = ctx->inst_info->r600_opcode;
1402 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1403 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1404 if (r)
1405 return r;
1406 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1407 }
1408 alu.dst.sel = ctx->temp_reg;
1409 alu.dst.write = 1;
1410 alu.last = 1;
1411 r = r600_bc_add_alu(ctx->bc, &alu);
1412 if (r)
1413 return r;
1414 r = r600_bc_add_literal(ctx->bc, ctx->value);
1415 if (r)
1416 return r;
1417 /* replicate result */
1418 return tgsi_helper_tempx_replicate(ctx);
1419 }
1420
1421 static int tgsi_pow(struct r600_shader_ctx *ctx)
1422 {
1423 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1424 struct r600_bc_alu alu;
1425 int r;
1426
1427 /* LOG2(a) */
1428 memset(&alu, 0, sizeof(struct r600_bc_alu));
1429 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1430 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1431 if (r)
1432 return r;
1433 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1434 alu.dst.sel = ctx->temp_reg;
1435 alu.dst.write = 1;
1436 alu.last = 1;
1437 r = r600_bc_add_alu(ctx->bc, &alu);
1438 if (r)
1439 return r;
1440 r = r600_bc_add_literal(ctx->bc,ctx->value);
1441 if (r)
1442 return r;
1443 /* b * LOG2(a) */
1444 memset(&alu, 0, sizeof(struct r600_bc_alu));
1445 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1446 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1447 if (r)
1448 return r;
1449 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1450 alu.src[1].sel = ctx->temp_reg;
1451 alu.dst.sel = ctx->temp_reg;
1452 alu.dst.write = 1;
1453 alu.last = 1;
1454 r = r600_bc_add_alu(ctx->bc, &alu);
1455 if (r)
1456 return r;
1457 r = r600_bc_add_literal(ctx->bc,ctx->value);
1458 if (r)
1459 return r;
1460 /* POW(a,b) = EXP2(b * LOG2(a))*/
1461 memset(&alu, 0, sizeof(struct r600_bc_alu));
1462 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1463 alu.src[0].sel = ctx->temp_reg;
1464 alu.dst.sel = ctx->temp_reg;
1465 alu.dst.write = 1;
1466 alu.last = 1;
1467 r = r600_bc_add_alu(ctx->bc, &alu);
1468 if (r)
1469 return r;
1470 r = r600_bc_add_literal(ctx->bc,ctx->value);
1471 if (r)
1472 return r;
1473 return tgsi_helper_tempx_replicate(ctx);
1474 }
1475
1476 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1477 {
1478 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1479 struct r600_bc_alu alu;
1480 struct r600_bc_alu_src r600_src[3];
1481 int i, r;
1482
1483 r = tgsi_split_constant(ctx, r600_src);
1484 if (r)
1485 return r;
1486 r = tgsi_split_literal_constant(ctx, r600_src);
1487 if (r)
1488 return r;
1489
1490 /* tmp = (src > 0 ? 1 : src) */
1491 for (i = 0; i < 4; i++) {
1492 memset(&alu, 0, sizeof(struct r600_bc_alu));
1493 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1494 alu.is_op3 = 1;
1495
1496 alu.dst.sel = ctx->temp_reg;
1497 alu.dst.chan = i;
1498
1499 alu.src[0] = r600_src[0];
1500 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1501
1502 alu.src[1].sel = V_SQ_ALU_SRC_1;
1503
1504 alu.src[2] = r600_src[0];
1505 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1506 if (i == 3)
1507 alu.last = 1;
1508 r = r600_bc_add_alu(ctx->bc, &alu);
1509 if (r)
1510 return r;
1511 }
1512 r = r600_bc_add_literal(ctx->bc, ctx->value);
1513 if (r)
1514 return r;
1515
1516 /* dst = (-tmp > 0 ? -1 : tmp) */
1517 for (i = 0; i < 4; i++) {
1518 memset(&alu, 0, sizeof(struct r600_bc_alu));
1519 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1520 alu.is_op3 = 1;
1521 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1522 if (r)
1523 return r;
1524
1525 alu.src[0].sel = ctx->temp_reg;
1526 alu.src[0].chan = i;
1527 alu.src[0].neg = 1;
1528
1529 alu.src[1].sel = V_SQ_ALU_SRC_1;
1530 alu.src[1].neg = 1;
1531
1532 alu.src[2].sel = ctx->temp_reg;
1533 alu.src[2].chan = i;
1534
1535 if (i == 3)
1536 alu.last = 1;
1537 r = r600_bc_add_alu(ctx->bc, &alu);
1538 if (r)
1539 return r;
1540 }
1541 return 0;
1542 }
1543
1544 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1545 {
1546 struct r600_bc_alu alu;
1547 int i, r;
1548
1549 r = r600_bc_add_literal(ctx->bc, ctx->value);
1550 if (r)
1551 return r;
1552 for (i = 0; i < 4; i++) {
1553 memset(&alu, 0, sizeof(struct r600_bc_alu));
1554 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1555 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1556 alu.dst.chan = i;
1557 } else {
1558 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1559 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1560 if (r)
1561 return r;
1562 alu.src[0].sel = ctx->temp_reg;
1563 alu.src[0].chan = i;
1564 }
1565 if (i == 3) {
1566 alu.last = 1;
1567 }
1568 r = r600_bc_add_alu(ctx->bc, &alu);
1569 if (r)
1570 return r;
1571 }
1572 return 0;
1573 }
1574
1575 static int tgsi_op3(struct r600_shader_ctx *ctx)
1576 {
1577 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1578 struct r600_bc_alu_src r600_src[3];
1579 struct r600_bc_alu alu;
1580 int i, j, r;
1581
1582 r = tgsi_split_constant(ctx, r600_src);
1583 if (r)
1584 return r;
1585 r = tgsi_split_literal_constant(ctx, r600_src);
1586 if (r)
1587 return r;
1588 /* do it in 2 step as op3 doesn't support writemask */
1589 for (i = 0; i < 4; i++) {
1590 memset(&alu, 0, sizeof(struct r600_bc_alu));
1591 alu.inst = ctx->inst_info->r600_opcode;
1592 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1593 alu.src[j] = r600_src[j];
1594 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1595 }
1596 alu.dst.sel = ctx->temp_reg;
1597 alu.dst.chan = i;
1598 alu.dst.write = 1;
1599 alu.is_op3 = 1;
1600 if (i == 3) {
1601 alu.last = 1;
1602 }
1603 r = r600_bc_add_alu(ctx->bc, &alu);
1604 if (r)
1605 return r;
1606 }
1607 return tgsi_helper_copy(ctx, inst);
1608 }
1609
1610 static int tgsi_dp(struct r600_shader_ctx *ctx)
1611 {
1612 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1613 struct r600_bc_alu_src r600_src[3];
1614 struct r600_bc_alu alu;
1615 int i, j, r;
1616
1617 r = tgsi_split_constant(ctx, r600_src);
1618 if (r)
1619 return r;
1620 r = tgsi_split_literal_constant(ctx, r600_src);
1621 if (r)
1622 return r;
1623 for (i = 0; i < 4; i++) {
1624 memset(&alu, 0, sizeof(struct r600_bc_alu));
1625 alu.inst = ctx->inst_info->r600_opcode;
1626 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1627 alu.src[j] = r600_src[j];
1628 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1629 }
1630 alu.dst.sel = ctx->temp_reg;
1631 alu.dst.chan = i;
1632 alu.dst.write = 1;
1633 /* handle some special cases */
1634 switch (ctx->inst_info->tgsi_opcode) {
1635 case TGSI_OPCODE_DP2:
1636 if (i > 1) {
1637 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1638 alu.src[0].chan = alu.src[1].chan = 0;
1639 }
1640 break;
1641 case TGSI_OPCODE_DP3:
1642 if (i > 2) {
1643 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1644 alu.src[0].chan = alu.src[1].chan = 0;
1645 }
1646 break;
1647 case TGSI_OPCODE_DPH:
1648 if (i == 3) {
1649 alu.src[0].sel = V_SQ_ALU_SRC_1;
1650 alu.src[0].chan = 0;
1651 alu.src[0].neg = 0;
1652 }
1653 break;
1654 default:
1655 break;
1656 }
1657 if (i == 3) {
1658 alu.last = 1;
1659 }
1660 r = r600_bc_add_alu(ctx->bc, &alu);
1661 if (r)
1662 return r;
1663 }
1664 return tgsi_helper_copy(ctx, inst);
1665 }
1666
1667 static int tgsi_tex(struct r600_shader_ctx *ctx)
1668 {
1669 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1670 struct r600_bc_tex tex;
1671 struct r600_bc_alu alu;
1672 unsigned src_gpr;
1673 int r, i;
1674 int opcode;
1675 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1676 uint32_t lit_vals[4];
1677
1678 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1679
1680 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1681 /* Add perspective divide */
1682 memset(&alu, 0, sizeof(struct r600_bc_alu));
1683 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1684 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1685 if (r)
1686 return r;
1687
1688 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1689 alu.dst.sel = ctx->temp_reg;
1690 alu.dst.chan = 3;
1691 alu.last = 1;
1692 alu.dst.write = 1;
1693 r = r600_bc_add_alu(ctx->bc, &alu);
1694 if (r)
1695 return r;
1696
1697 for (i = 0; i < 3; i++) {
1698 memset(&alu, 0, sizeof(struct r600_bc_alu));
1699 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1700 alu.src[0].sel = ctx->temp_reg;
1701 alu.src[0].chan = 3;
1702 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1703 if (r)
1704 return r;
1705 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1706 alu.dst.sel = ctx->temp_reg;
1707 alu.dst.chan = i;
1708 alu.dst.write = 1;
1709 r = r600_bc_add_alu(ctx->bc, &alu);
1710 if (r)
1711 return r;
1712 }
1713 memset(&alu, 0, sizeof(struct r600_bc_alu));
1714 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1715 alu.src[0].sel = V_SQ_ALU_SRC_1;
1716 alu.src[0].chan = 0;
1717 alu.dst.sel = ctx->temp_reg;
1718 alu.dst.chan = 3;
1719 alu.last = 1;
1720 alu.dst.write = 1;
1721 r = r600_bc_add_alu(ctx->bc, &alu);
1722 if (r)
1723 return r;
1724 src_not_temp = FALSE;
1725 src_gpr = ctx->temp_reg;
1726 }
1727
1728 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1729 int src_chan, src2_chan;
1730
1731 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1732 for (i = 0; i < 4; i++) {
1733 memset(&alu, 0, sizeof(struct r600_bc_alu));
1734 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1735 switch (i) {
1736 case 0:
1737 src_chan = 2;
1738 src2_chan = 1;
1739 break;
1740 case 1:
1741 src_chan = 2;
1742 src2_chan = 0;
1743 break;
1744 case 2:
1745 src_chan = 0;
1746 src2_chan = 2;
1747 break;
1748 case 3:
1749 src_chan = 1;
1750 src2_chan = 2;
1751 break;
1752 default:
1753 assert(0);
1754 src_chan = 0;
1755 src2_chan = 0;
1756 break;
1757 }
1758 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1759 if (r)
1760 return r;
1761 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1762 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1763 if (r)
1764 return r;
1765 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1766 alu.dst.sel = ctx->temp_reg;
1767 alu.dst.chan = i;
1768 if (i == 3)
1769 alu.last = 1;
1770 alu.dst.write = 1;
1771 r = r600_bc_add_alu(ctx->bc, &alu);
1772 if (r)
1773 return r;
1774 }
1775
1776 /* tmp1.z = RCP_e(|tmp1.z|) */
1777 memset(&alu, 0, sizeof(struct r600_bc_alu));
1778 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1779 alu.src[0].sel = ctx->temp_reg;
1780 alu.src[0].chan = 2;
1781 alu.src[0].abs = 1;
1782 alu.dst.sel = ctx->temp_reg;
1783 alu.dst.chan = 2;
1784 alu.dst.write = 1;
1785 alu.last = 1;
1786 r = r600_bc_add_alu(ctx->bc, &alu);
1787 if (r)
1788 return r;
1789
1790 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1791 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1792 * muladd has no writemask, have to use another temp
1793 */
1794 memset(&alu, 0, sizeof(struct r600_bc_alu));
1795 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1796 alu.is_op3 = 1;
1797
1798 alu.src[0].sel = ctx->temp_reg;
1799 alu.src[0].chan = 0;
1800 alu.src[1].sel = ctx->temp_reg;
1801 alu.src[1].chan = 2;
1802
1803 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1804 alu.src[2].chan = 0;
1805
1806 alu.dst.sel = ctx->temp_reg;
1807 alu.dst.chan = 0;
1808 alu.dst.write = 1;
1809
1810 r = r600_bc_add_alu(ctx->bc, &alu);
1811 if (r)
1812 return r;
1813
1814 memset(&alu, 0, sizeof(struct r600_bc_alu));
1815 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1816 alu.is_op3 = 1;
1817
1818 alu.src[0].sel = ctx->temp_reg;
1819 alu.src[0].chan = 1;
1820 alu.src[1].sel = ctx->temp_reg;
1821 alu.src[1].chan = 2;
1822
1823 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1824 alu.src[2].chan = 0;
1825
1826 alu.dst.sel = ctx->temp_reg;
1827 alu.dst.chan = 1;
1828 alu.dst.write = 1;
1829
1830 alu.last = 1;
1831 r = r600_bc_add_alu(ctx->bc, &alu);
1832 if (r)
1833 return r;
1834
1835 lit_vals[0] = fui(1.5f);
1836
1837 r = r600_bc_add_literal(ctx->bc, lit_vals);
1838 if (r)
1839 return r;
1840 src_not_temp = FALSE;
1841 src_gpr = ctx->temp_reg;
1842 }
1843
1844 if (src_not_temp) {
1845 for (i = 0; i < 4; i++) {
1846 memset(&alu, 0, sizeof(struct r600_bc_alu));
1847 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1848 alu.src[0].sel = src_gpr;
1849 alu.src[0].chan = i;
1850 alu.dst.sel = ctx->temp_reg;
1851 alu.dst.chan = i;
1852 if (i == 3)
1853 alu.last = 1;
1854 alu.dst.write = 1;
1855 r = r600_bc_add_alu(ctx->bc, &alu);
1856 if (r)
1857 return r;
1858 }
1859 src_gpr = ctx->temp_reg;
1860 }
1861
1862 opcode = ctx->inst_info->r600_opcode;
1863 if (opcode == SQ_TEX_INST_SAMPLE &&
1864 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1865 opcode = SQ_TEX_INST_SAMPLE_C;
1866
1867 memset(&tex, 0, sizeof(struct r600_bc_tex));
1868 tex.inst = opcode;
1869 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1870 tex.sampler_id = tex.resource_id;
1871 tex.src_gpr = src_gpr;
1872 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1873 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1874 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1875 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1876 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1877 tex.src_sel_x = 0;
1878 tex.src_sel_y = 1;
1879 tex.src_sel_z = 2;
1880 tex.src_sel_w = 3;
1881
1882 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1883 tex.src_sel_x = 1;
1884 tex.src_sel_y = 0;
1885 tex.src_sel_z = 3;
1886 tex.src_sel_w = 1;
1887 }
1888
1889 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1890 tex.coord_type_x = 1;
1891 tex.coord_type_y = 1;
1892 tex.coord_type_z = 1;
1893 tex.coord_type_w = 1;
1894 }
1895
1896 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1897 tex.src_sel_w = 2;
1898
1899 r = r600_bc_add_tex(ctx->bc, &tex);
1900 if (r)
1901 return r;
1902
1903 /* add shadow ambient support - gallium doesn't do it yet */
1904 return 0;
1905
1906 }
1907
1908 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1909 {
1910 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1911 struct r600_bc_alu_src r600_src[3];
1912 struct r600_bc_alu alu;
1913 unsigned i;
1914 int r;
1915
1916 r = tgsi_split_constant(ctx, r600_src);
1917 if (r)
1918 return r;
1919 r = tgsi_split_literal_constant(ctx, r600_src);
1920 if (r)
1921 return r;
1922 /* 1 - src0 */
1923 for (i = 0; i < 4; i++) {
1924 memset(&alu, 0, sizeof(struct r600_bc_alu));
1925 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1926 alu.src[0].sel = V_SQ_ALU_SRC_1;
1927 alu.src[0].chan = 0;
1928 alu.src[1] = r600_src[0];
1929 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1930 alu.src[1].neg = 1;
1931 alu.dst.sel = ctx->temp_reg;
1932 alu.dst.chan = i;
1933 if (i == 3) {
1934 alu.last = 1;
1935 }
1936 alu.dst.write = 1;
1937 r = r600_bc_add_alu(ctx->bc, &alu);
1938 if (r)
1939 return r;
1940 }
1941 r = r600_bc_add_literal(ctx->bc, ctx->value);
1942 if (r)
1943 return r;
1944
1945 /* (1 - src0) * src2 */
1946 for (i = 0; i < 4; i++) {
1947 memset(&alu, 0, sizeof(struct r600_bc_alu));
1948 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1949 alu.src[0].sel = ctx->temp_reg;
1950 alu.src[0].chan = i;
1951 alu.src[1] = r600_src[2];
1952 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1953 alu.dst.sel = ctx->temp_reg;
1954 alu.dst.chan = i;
1955 if (i == 3) {
1956 alu.last = 1;
1957 }
1958 alu.dst.write = 1;
1959 r = r600_bc_add_alu(ctx->bc, &alu);
1960 if (r)
1961 return r;
1962 }
1963 r = r600_bc_add_literal(ctx->bc, ctx->value);
1964 if (r)
1965 return r;
1966
1967 /* src0 * src1 + (1 - src0) * src2 */
1968 for (i = 0; i < 4; i++) {
1969 memset(&alu, 0, sizeof(struct r600_bc_alu));
1970 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1971 alu.is_op3 = 1;
1972 alu.src[0] = r600_src[0];
1973 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1974 alu.src[1] = r600_src[1];
1975 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1976 alu.src[2].sel = ctx->temp_reg;
1977 alu.src[2].chan = i;
1978 alu.dst.sel = ctx->temp_reg;
1979 alu.dst.chan = i;
1980 if (i == 3) {
1981 alu.last = 1;
1982 }
1983 r = r600_bc_add_alu(ctx->bc, &alu);
1984 if (r)
1985 return r;
1986 }
1987 return tgsi_helper_copy(ctx, inst);
1988 }
1989
1990 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1991 {
1992 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1993 struct r600_bc_alu_src r600_src[3];
1994 struct r600_bc_alu alu;
1995 int use_temp = 0;
1996 int i, r;
1997
1998 r = tgsi_split_constant(ctx, r600_src);
1999 if (r)
2000 return r;
2001 r = tgsi_split_literal_constant(ctx, r600_src);
2002 if (r)
2003 return r;
2004
2005 if (inst->Dst[0].Register.WriteMask != 0xf)
2006 use_temp = 1;
2007
2008 for (i = 0; i < 4; i++) {
2009 memset(&alu, 0, sizeof(struct r600_bc_alu));
2010 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2011 alu.src[0] = r600_src[0];
2012 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2013
2014 alu.src[1] = r600_src[2];
2015 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2016
2017 alu.src[2] = r600_src[1];
2018 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2019
2020 if (use_temp)
2021 alu.dst.sel = ctx->temp_reg;
2022 else {
2023 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2024 if (r)
2025 return r;
2026 }
2027 alu.dst.chan = i;
2028 alu.dst.write = 1;
2029 alu.is_op3 = 1;
2030 if (i == 3)
2031 alu.last = 1;
2032 r = r600_bc_add_alu(ctx->bc, &alu);
2033 if (r)
2034 return r;
2035 }
2036 if (use_temp)
2037 return tgsi_helper_copy(ctx, inst);
2038 return 0;
2039 }
2040
2041 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2042 {
2043 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2044 struct r600_bc_alu_src r600_src[3];
2045 struct r600_bc_alu alu;
2046 uint32_t use_temp = 0;
2047 int i, r;
2048
2049 if (inst->Dst[0].Register.WriteMask != 0xf)
2050 use_temp = 1;
2051
2052 r = tgsi_split_constant(ctx, r600_src);
2053 if (r)
2054 return r;
2055 r = tgsi_split_literal_constant(ctx, r600_src);
2056 if (r)
2057 return r;
2058
2059 for (i = 0; i < 4; i++) {
2060 memset(&alu, 0, sizeof(struct r600_bc_alu));
2061 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2062
2063 alu.src[0] = r600_src[0];
2064 switch (i) {
2065 case 0:
2066 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2067 break;
2068 case 1:
2069 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2070 break;
2071 case 2:
2072 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2073 break;
2074 case 3:
2075 alu.src[0].sel = V_SQ_ALU_SRC_0;
2076 alu.src[0].chan = i;
2077 }
2078
2079 alu.src[1] = r600_src[1];
2080 switch (i) {
2081 case 0:
2082 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2083 break;
2084 case 1:
2085 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2086 break;
2087 case 2:
2088 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2089 break;
2090 case 3:
2091 alu.src[1].sel = V_SQ_ALU_SRC_0;
2092 alu.src[1].chan = i;
2093 }
2094
2095 alu.dst.sel = ctx->temp_reg;
2096 alu.dst.chan = i;
2097 alu.dst.write = 1;
2098
2099 if (i == 3)
2100 alu.last = 1;
2101 r = r600_bc_add_alu(ctx->bc, &alu);
2102 if (r)
2103 return r;
2104
2105 r = r600_bc_add_literal(ctx->bc, ctx->value);
2106 if (r)
2107 return r;
2108 }
2109
2110 for (i = 0; i < 4; i++) {
2111 memset(&alu, 0, sizeof(struct r600_bc_alu));
2112 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2113
2114 alu.src[0] = r600_src[0];
2115 switch (i) {
2116 case 0:
2117 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2118 break;
2119 case 1:
2120 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2121 break;
2122 case 2:
2123 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2124 break;
2125 case 3:
2126 alu.src[0].sel = V_SQ_ALU_SRC_0;
2127 alu.src[0].chan = i;
2128 }
2129
2130 alu.src[1] = r600_src[1];
2131 switch (i) {
2132 case 0:
2133 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2134 break;
2135 case 1:
2136 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2137 break;
2138 case 2:
2139 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2140 break;
2141 case 3:
2142 alu.src[1].sel = V_SQ_ALU_SRC_0;
2143 alu.src[1].chan = i;
2144 }
2145
2146 alu.src[2].sel = ctx->temp_reg;
2147 alu.src[2].neg = 1;
2148 alu.src[2].chan = i;
2149
2150 if (use_temp)
2151 alu.dst.sel = ctx->temp_reg;
2152 else {
2153 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2154 if (r)
2155 return r;
2156 }
2157 alu.dst.chan = i;
2158 alu.dst.write = 1;
2159 alu.is_op3 = 1;
2160 if (i == 3)
2161 alu.last = 1;
2162 r = r600_bc_add_alu(ctx->bc, &alu);
2163 if (r)
2164 return r;
2165
2166 r = r600_bc_add_literal(ctx->bc, ctx->value);
2167 if (r)
2168 return r;
2169 }
2170 if (use_temp)
2171 return tgsi_helper_copy(ctx, inst);
2172 return 0;
2173 }
2174
2175 static int tgsi_exp(struct r600_shader_ctx *ctx)
2176 {
2177 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2178 struct r600_bc_alu_src r600_src[3];
2179 struct r600_bc_alu alu;
2180 int r;
2181
2182 /* result.x = 2^floor(src); */
2183 if (inst->Dst[0].Register.WriteMask & 1) {
2184 memset(&alu, 0, sizeof(struct r600_bc_alu));
2185
2186 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2187 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2188 if (r)
2189 return r;
2190
2191 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2192
2193 alu.dst.sel = ctx->temp_reg;
2194 alu.dst.chan = 0;
2195 alu.dst.write = 1;
2196 alu.last = 1;
2197 r = r600_bc_add_alu(ctx->bc, &alu);
2198 if (r)
2199 return r;
2200
2201 r = r600_bc_add_literal(ctx->bc, ctx->value);
2202 if (r)
2203 return r;
2204
2205 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2206 alu.src[0].sel = ctx->temp_reg;
2207 alu.src[0].chan = 0;
2208
2209 alu.dst.sel = ctx->temp_reg;
2210 alu.dst.chan = 0;
2211 alu.dst.write = 1;
2212 alu.last = 1;
2213 r = r600_bc_add_alu(ctx->bc, &alu);
2214 if (r)
2215 return r;
2216
2217 r = r600_bc_add_literal(ctx->bc, ctx->value);
2218 if (r)
2219 return r;
2220 }
2221
2222 /* result.y = tmp - floor(tmp); */
2223 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2224 memset(&alu, 0, sizeof(struct r600_bc_alu));
2225
2226 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2227 alu.src[0] = r600_src[0];
2228 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2229 if (r)
2230 return r;
2231 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2232
2233 alu.dst.sel = ctx->temp_reg;
2234 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2235 // if (r)
2236 // return r;
2237 alu.dst.write = 1;
2238 alu.dst.chan = 1;
2239
2240 alu.last = 1;
2241
2242 r = r600_bc_add_alu(ctx->bc, &alu);
2243 if (r)
2244 return r;
2245 r = r600_bc_add_literal(ctx->bc, ctx->value);
2246 if (r)
2247 return r;
2248 }
2249
2250 /* result.z = RoughApprox2ToX(tmp);*/
2251 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2252 memset(&alu, 0, sizeof(struct r600_bc_alu));
2253 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2254 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2255 if (r)
2256 return r;
2257 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2258
2259 alu.dst.sel = ctx->temp_reg;
2260 alu.dst.write = 1;
2261 alu.dst.chan = 2;
2262
2263 alu.last = 1;
2264
2265 r = r600_bc_add_alu(ctx->bc, &alu);
2266 if (r)
2267 return r;
2268 r = r600_bc_add_literal(ctx->bc, ctx->value);
2269 if (r)
2270 return r;
2271 }
2272
2273 /* result.w = 1.0;*/
2274 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2275 memset(&alu, 0, sizeof(struct r600_bc_alu));
2276
2277 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2278 alu.src[0].sel = V_SQ_ALU_SRC_1;
2279 alu.src[0].chan = 0;
2280
2281 alu.dst.sel = ctx->temp_reg;
2282 alu.dst.chan = 3;
2283 alu.dst.write = 1;
2284 alu.last = 1;
2285 r = r600_bc_add_alu(ctx->bc, &alu);
2286 if (r)
2287 return r;
2288 r = r600_bc_add_literal(ctx->bc, ctx->value);
2289 if (r)
2290 return r;
2291 }
2292 return tgsi_helper_copy(ctx, inst);
2293 }
2294
2295 static int tgsi_log(struct r600_shader_ctx *ctx)
2296 {
2297 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2298 struct r600_bc_alu alu;
2299 int r;
2300
2301 /* result.x = floor(log2(src)); */
2302 if (inst->Dst[0].Register.WriteMask & 1) {
2303 memset(&alu, 0, sizeof(struct r600_bc_alu));
2304
2305 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2306 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2307 if (r)
2308 return r;
2309
2310 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2311
2312 alu.dst.sel = ctx->temp_reg;
2313 alu.dst.chan = 0;
2314 alu.dst.write = 1;
2315 alu.last = 1;
2316 r = r600_bc_add_alu(ctx->bc, &alu);
2317 if (r)
2318 return r;
2319
2320 r = r600_bc_add_literal(ctx->bc, ctx->value);
2321 if (r)
2322 return r;
2323
2324 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2325 alu.src[0].sel = ctx->temp_reg;
2326 alu.src[0].chan = 0;
2327
2328 alu.dst.sel = ctx->temp_reg;
2329 alu.dst.chan = 0;
2330 alu.dst.write = 1;
2331 alu.last = 1;
2332
2333 r = r600_bc_add_alu(ctx->bc, &alu);
2334 if (r)
2335 return r;
2336
2337 r = r600_bc_add_literal(ctx->bc, ctx->value);
2338 if (r)
2339 return r;
2340 }
2341
2342 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2343 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2344 memset(&alu, 0, sizeof(struct r600_bc_alu));
2345
2346 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2347 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2348 if (r)
2349 return r;
2350
2351 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2352
2353 alu.dst.sel = ctx->temp_reg;
2354 alu.dst.chan = 1;
2355 alu.dst.write = 1;
2356 alu.last = 1;
2357
2358 r = r600_bc_add_alu(ctx->bc, &alu);
2359 if (r)
2360 return r;
2361
2362 r = r600_bc_add_literal(ctx->bc, ctx->value);
2363 if (r)
2364 return r;
2365
2366 memset(&alu, 0, sizeof(struct r600_bc_alu));
2367
2368 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2369 alu.src[0].sel = ctx->temp_reg;
2370 alu.src[0].chan = 1;
2371
2372 alu.dst.sel = ctx->temp_reg;
2373 alu.dst.chan = 1;
2374 alu.dst.write = 1;
2375 alu.last = 1;
2376
2377 r = r600_bc_add_alu(ctx->bc, &alu);
2378 if (r)
2379 return r;
2380
2381 r = r600_bc_add_literal(ctx->bc, ctx->value);
2382 if (r)
2383 return r;
2384
2385 memset(&alu, 0, sizeof(struct r600_bc_alu));
2386
2387 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2388 alu.src[0].sel = ctx->temp_reg;
2389 alu.src[0].chan = 1;
2390
2391 alu.dst.sel = ctx->temp_reg;
2392 alu.dst.chan = 1;
2393 alu.dst.write = 1;
2394 alu.last = 1;
2395
2396 r = r600_bc_add_alu(ctx->bc, &alu);
2397 if (r)
2398 return r;
2399
2400 r = r600_bc_add_literal(ctx->bc, ctx->value);
2401 if (r)
2402 return r;
2403
2404 memset(&alu, 0, sizeof(struct r600_bc_alu));
2405
2406 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2407 alu.src[0].sel = ctx->temp_reg;
2408 alu.src[0].chan = 1;
2409
2410 alu.dst.sel = ctx->temp_reg;
2411 alu.dst.chan = 1;
2412 alu.dst.write = 1;
2413 alu.last = 1;
2414
2415 r = r600_bc_add_alu(ctx->bc, &alu);
2416 if (r)
2417 return r;
2418
2419 r = r600_bc_add_literal(ctx->bc, ctx->value);
2420 if (r)
2421 return r;
2422
2423 memset(&alu, 0, sizeof(struct r600_bc_alu));
2424
2425 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2426
2427 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2428 if (r)
2429 return r;
2430
2431 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2432
2433 alu.src[1].sel = ctx->temp_reg;
2434 alu.src[1].chan = 1;
2435
2436 alu.dst.sel = ctx->temp_reg;
2437 alu.dst.chan = 1;
2438 alu.dst.write = 1;
2439 alu.last = 1;
2440
2441 r = r600_bc_add_alu(ctx->bc, &alu);
2442 if (r)
2443 return r;
2444
2445 r = r600_bc_add_literal(ctx->bc, ctx->value);
2446 if (r)
2447 return r;
2448 }
2449
2450 /* result.z = log2(src);*/
2451 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2452 memset(&alu, 0, sizeof(struct r600_bc_alu));
2453
2454 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2455 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2456 if (r)
2457 return r;
2458
2459 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2460
2461 alu.dst.sel = ctx->temp_reg;
2462 alu.dst.write = 1;
2463 alu.dst.chan = 2;
2464 alu.last = 1;
2465
2466 r = r600_bc_add_alu(ctx->bc, &alu);
2467 if (r)
2468 return r;
2469
2470 r = r600_bc_add_literal(ctx->bc, ctx->value);
2471 if (r)
2472 return r;
2473 }
2474
2475 /* result.w = 1.0; */
2476 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2477 memset(&alu, 0, sizeof(struct r600_bc_alu));
2478
2479 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2480 alu.src[0].sel = V_SQ_ALU_SRC_1;
2481 alu.src[0].chan = 0;
2482
2483 alu.dst.sel = ctx->temp_reg;
2484 alu.dst.chan = 3;
2485 alu.dst.write = 1;
2486 alu.last = 1;
2487
2488 r = r600_bc_add_alu(ctx->bc, &alu);
2489 if (r)
2490 return r;
2491
2492 r = r600_bc_add_literal(ctx->bc, ctx->value);
2493 if (r)
2494 return r;
2495 }
2496
2497 return tgsi_helper_copy(ctx, inst);
2498 }
2499
2500 /* r6/7 only for now */
2501 static int tgsi_arl(struct r600_shader_ctx *ctx)
2502 {
2503 /* TODO from r600c, ar values don't persist between clauses */
2504 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2505 struct r600_bc_alu alu;
2506 int r;
2507 memset(&alu, 0, sizeof(struct r600_bc_alu));
2508
2509 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2510
2511 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2512 if (r)
2513 return r;
2514 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2515
2516 alu.last = 1;
2517
2518 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2519 if (r)
2520 return r;
2521 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2522 return 0;
2523 }
2524
2525 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2526 {
2527 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2528 struct r600_bc_alu alu;
2529 int i, r = 0;
2530
2531 for (i = 0; i < 4; i++) {
2532 memset(&alu, 0, sizeof(struct r600_bc_alu));
2533
2534 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2535 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2536 if (r)
2537 return r;
2538
2539 if (i == 0 || i == 3) {
2540 alu.src[0].sel = V_SQ_ALU_SRC_1;
2541 } else {
2542 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2543 if (r)
2544 return r;
2545 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2546 }
2547
2548 if (i == 0 || i == 2) {
2549 alu.src[1].sel = V_SQ_ALU_SRC_1;
2550 } else {
2551 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2552 if (r)
2553 return r;
2554 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2555 }
2556 if (i == 3)
2557 alu.last = 1;
2558 r = r600_bc_add_alu(ctx->bc, &alu);
2559 if (r)
2560 return r;
2561 }
2562 return 0;
2563 }
2564
2565 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2566 {
2567 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2568 struct r600_bc_alu alu;
2569 int r;
2570
2571 memset(&alu, 0, sizeof(struct r600_bc_alu));
2572 alu.inst = opcode;
2573 alu.predicate = 1;
2574
2575 alu.dst.sel = ctx->temp_reg;
2576 alu.dst.write = 1;
2577 alu.dst.chan = 0;
2578
2579 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2580 if (r)
2581 return r;
2582 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2583 alu.src[1].sel = V_SQ_ALU_SRC_0;
2584 alu.src[1].chan = 0;
2585
2586 alu.last = 1;
2587
2588 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2589 if (r)
2590 return r;
2591 return 0;
2592 }
2593
2594 static int pops(struct r600_shader_ctx *ctx, int pops)
2595 {
2596 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2597 ctx->bc->cf_last->pop_count = pops;
2598 return 0;
2599 }
2600
2601 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2602 {
2603 switch(reason) {
2604 case FC_PUSH_VPM:
2605 ctx->bc->callstack[ctx->bc->call_sp].current--;
2606 break;
2607 case FC_PUSH_WQM:
2608 case FC_LOOP:
2609 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2610 break;
2611 case FC_REP:
2612 /* TOODO : for 16 vp asic should -= 2; */
2613 ctx->bc->callstack[ctx->bc->call_sp].current --;
2614 break;
2615 }
2616 }
2617
2618 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2619 {
2620 if (check_max_only) {
2621 int diff;
2622 switch (reason) {
2623 case FC_PUSH_VPM:
2624 diff = 1;
2625 break;
2626 case FC_PUSH_WQM:
2627 diff = 4;
2628 break;
2629 default:
2630 assert(0);
2631 diff = 0;
2632 }
2633 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2634 ctx->bc->callstack[ctx->bc->call_sp].max) {
2635 ctx->bc->callstack[ctx->bc->call_sp].max =
2636 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2637 }
2638 return;
2639 }
2640 switch (reason) {
2641 case FC_PUSH_VPM:
2642 ctx->bc->callstack[ctx->bc->call_sp].current++;
2643 break;
2644 case FC_PUSH_WQM:
2645 case FC_LOOP:
2646 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2647 break;
2648 case FC_REP:
2649 ctx->bc->callstack[ctx->bc->call_sp].current++;
2650 break;
2651 }
2652
2653 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2654 ctx->bc->callstack[ctx->bc->call_sp].max) {
2655 ctx->bc->callstack[ctx->bc->call_sp].max =
2656 ctx->bc->callstack[ctx->bc->call_sp].current;
2657 }
2658 }
2659
2660 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2661 {
2662 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2663
2664 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2665 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2666 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2667 sp->num_mid++;
2668 }
2669
2670 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2671 {
2672 ctx->bc->fc_sp++;
2673 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2674 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2675 }
2676
2677 static void fc_poplevel(struct r600_shader_ctx *ctx)
2678 {
2679 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2680 if (sp->mid) {
2681 free(sp->mid);
2682 sp->mid = NULL;
2683 }
2684 sp->num_mid = 0;
2685 sp->start = NULL;
2686 sp->type = 0;
2687 ctx->bc->fc_sp--;
2688 }
2689
2690 #if 0
2691 static int emit_return(struct r600_shader_ctx *ctx)
2692 {
2693 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2694 return 0;
2695 }
2696
2697 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2698 {
2699
2700 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2701 ctx->bc->cf_last->pop_count = pops;
2702 /* TODO work out offset */
2703 return 0;
2704 }
2705
2706 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2707 {
2708 return 0;
2709 }
2710
2711 static void emit_testflag(struct r600_shader_ctx *ctx)
2712 {
2713
2714 }
2715
2716 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2717 {
2718 emit_testflag(ctx);
2719 emit_jump_to_offset(ctx, 1, 4);
2720 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2721 pops(ctx, ifidx + 1);
2722 emit_return(ctx);
2723 }
2724
2725 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2726 {
2727 emit_testflag(ctx);
2728
2729 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2730 ctx->bc->cf_last->pop_count = 1;
2731
2732 fc_set_mid(ctx, fc_sp);
2733
2734 pops(ctx, 1);
2735 }
2736 #endif
2737
2738 static int tgsi_if(struct r600_shader_ctx *ctx)
2739 {
2740 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2741
2742 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2743
2744 fc_pushlevel(ctx, FC_IF);
2745
2746 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2747 return 0;
2748 }
2749
2750 static int tgsi_else(struct r600_shader_ctx *ctx)
2751 {
2752 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2753 ctx->bc->cf_last->pop_count = 1;
2754
2755 fc_set_mid(ctx, ctx->bc->fc_sp);
2756 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2757 return 0;
2758 }
2759
2760 static int tgsi_endif(struct r600_shader_ctx *ctx)
2761 {
2762 pops(ctx, 1);
2763 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2764 R600_ERR("if/endif unbalanced in shader\n");
2765 return -1;
2766 }
2767
2768 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2769 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2770 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2771 } else {
2772 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2773 }
2774 fc_poplevel(ctx);
2775
2776 callstack_decrease_current(ctx, FC_PUSH_VPM);
2777 return 0;
2778 }
2779
2780 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2781 {
2782 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2783
2784 fc_pushlevel(ctx, FC_LOOP);
2785
2786 /* check stack depth */
2787 callstack_check_depth(ctx, FC_LOOP, 0);
2788 return 0;
2789 }
2790
2791 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2792 {
2793 int i;
2794
2795 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2796
2797 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2798 R600_ERR("loop/endloop in shader code are not paired.\n");
2799 return -EINVAL;
2800 }
2801
2802 /* fixup loop pointers - from r600isa
2803 LOOP END points to CF after LOOP START,
2804 LOOP START point to CF after LOOP END
2805 BRK/CONT point to LOOP END CF
2806 */
2807 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2808
2809 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2810
2811 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2812 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2813 }
2814 /* TODO add LOOPRET support */
2815 fc_poplevel(ctx);
2816 callstack_decrease_current(ctx, FC_LOOP);
2817 return 0;
2818 }
2819
2820 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2821 {
2822 unsigned int fscp;
2823
2824 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2825 {
2826 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2827 break;
2828 }
2829
2830 if (fscp == 0) {
2831 R600_ERR("Break not inside loop/endloop pair\n");
2832 return -EINVAL;
2833 }
2834
2835 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2836 ctx->bc->cf_last->pop_count = 1;
2837
2838 fc_set_mid(ctx, fscp);
2839
2840 pops(ctx, 1);
2841 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2842 return 0;
2843 }
2844
2845 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2846 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2847 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2848 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2849
2850 /* FIXME:
2851 * For state trackers other than OpenGL, we'll want to use
2852 * _RECIP_IEEE instead.
2853 */
2854 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2855
2856 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2857 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2858 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2859 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2860 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2861 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2862 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2863 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2864 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2865 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2866 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2867 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2868 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2869 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2870 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2871 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2872 /* gap */
2873 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2874 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2875 /* gap */
2876 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2877 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2878 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2879 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2880 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2881 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2882 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2883 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2884 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2885 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2886 /* gap */
2887 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2888 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2889 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2891 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2892 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2893 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2894 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2895 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2896 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2897 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2898 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2899 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2900 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2901 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2902 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2903 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2904 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2905 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2906 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2908 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2910 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2911 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2912 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2914 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2917 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2918 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2919 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2920 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2921 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2922 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2923 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2924 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2926 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2927 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2929 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2930 /* gap */
2931 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2932 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2934 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2935 /* gap */
2936 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2937 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2944 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 /* gap */
2946 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2950 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2955 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2957 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2958 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2960 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2961 /* gap */
2962 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 /* gap */
2968 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2969 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2977 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2978 /* gap */
2979 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2993 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 };
3008
3009 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3010 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3012 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3013 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3014 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3015 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3016 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3018 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3019 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3020 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3021 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3022 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3023 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3024 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3025 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3026 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3027 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3028 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3029 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 /* gap */
3031 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 /* gap */
3034 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3037 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3039 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3040 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3041 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3042 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3043 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3044 /* gap */
3045 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3047 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3049 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3050 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3051 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3052 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3053 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3056 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3058 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3059 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3061 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3062 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3063 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3064 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3066 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3068 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3069 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3075 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3076 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3077 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3078 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3079 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3080 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3081 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3082 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3085 {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3087 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3088 /* gap */
3089 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3092 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3093 /* gap */
3094 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3102 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 /* gap */
3104 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3106 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3107 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3108 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3113 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3115 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3116 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3118 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 /* gap */
3120 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 /* gap */
3126 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3127 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3132 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3135 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3136 /* gap */
3137 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3143 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3147 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3149 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3153 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3154 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3156 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3157 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3158 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3159 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3160 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3161 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3162 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3163 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3164 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 };