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r600g: add shader stencil export support.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 for (i = 0; i < 10; i++) {
48 spi_vs_out_id[i] = 0;
49 }
50 for (i = 0; i < 32; i++) {
51 tmp = i << ((i & 3) * 8);
52 spi_vs_out_id[i / 4] |= tmp;
53 }
54 for (i = 0; i < 10; i++) {
55 r600_pipe_state_add_reg(rstate,
56 R_028614_SPI_VS_OUT_ID_0 + i * 4,
57 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
58 }
59
60 r600_pipe_state_add_reg(rstate,
61 R_0286C4_SPI_VS_OUT_CONFIG,
62 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
63 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate,
65 R_028868_SQ_PGM_RESOURCES_VS,
66 S_028868_NUM_GPRS(rshader->bc.ngpr) |
67 S_028868_STACK_SIZE(rshader->bc.nstack),
68 0xFFFFFFFF, NULL);
69 r600_pipe_state_add_reg(rstate,
70 R_0288A4_SQ_PGM_RESOURCES_FS,
71 0x00000000, 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS,
77 0x00000000, 0xFFFFFFFF, NULL);
78 r600_pipe_state_add_reg(rstate,
79 R_028858_SQ_PGM_START_VS,
80 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
81 r600_pipe_state_add_reg(rstate,
82 R_028894_SQ_PGM_START_FS,
83 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
84
85 r600_pipe_state_add_reg(rstate,
86 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
87 0xFFFFFFFF, NULL);
88
89 }
90
91 int r600_find_vs_semantic_index(struct r600_shader *vs,
92 struct r600_shader *ps, int id)
93 {
94 struct r600_shader_io *input = &ps->input[id];
95
96 for (int i = 0; i < vs->noutput; i++) {
97 if (input->name == vs->output[i].name &&
98 input->sid == vs->output[i].sid) {
99 return i - 1;
100 }
101 }
102 return 0;
103 }
104
105 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
106 {
107 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
108 struct r600_pipe_state *rstate = &shader->rstate;
109 struct r600_shader *rshader = &shader->shader;
110 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
111 boolean have_pos = FALSE, have_face = FALSE;
112
113 /* clear previous register */
114 rstate->nregs = 0;
115
116 for (i = 0; i < rshader->ninput; i++) {
117 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
118 tmp |= S_028644_SEL_CENTROID(1);
119 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
120 have_pos = TRUE;
121 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
122 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
123 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
124 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
125 }
126 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
127 have_face = TRUE;
128 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
129 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
130 tmp |= S_028644_PT_SPRITE_TEX(1);
131 }
132 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
133 }
134 for (i = 0; i < rshader->noutput; i++) {
135 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
136 r600_pipe_state_add_reg(rstate,
137 R_02880C_DB_SHADER_CONTROL,
138 S_02880C_Z_EXPORT_ENABLE(1),
139 S_02880C_Z_EXPORT_ENABLE(1), NULL);
140 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
141 r600_pipe_state_add_reg(rstate,
142 R_02880C_DB_SHADER_CONTROL,
143 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
144 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
145 }
146
147 exports_ps = 0;
148 num_cout = 0;
149 for (i = 0; i < rshader->noutput; i++) {
150 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
151 exports_ps |= 1;
152 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
153 num_cout++;
154 }
155 }
156 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
157 if (!exports_ps) {
158 /* always at least export 1 component per pixel */
159 exports_ps = 2;
160 }
161
162 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
163 S_0286CC_PERSP_GRADIENT_ENA(1);
164 spi_input_z = 0;
165 if (have_pos) {
166 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
167 S_0286CC_BARYC_SAMPLE_CNTL(1);
168 spi_input_z |= 1;
169 }
170 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
172 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
173 r600_pipe_state_add_reg(rstate,
174 R_028840_SQ_PGM_START_PS,
175 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
176 r600_pipe_state_add_reg(rstate,
177 R_028850_SQ_PGM_RESOURCES_PS,
178 S_028868_NUM_GPRS(rshader->bc.ngpr) |
179 S_028868_STACK_SIZE(rshader->bc.nstack),
180 0xFFFFFFFF, NULL);
181 r600_pipe_state_add_reg(rstate,
182 R_028854_SQ_PGM_EXPORTS_PS,
183 exports_ps, 0xFFFFFFFF, NULL);
184 r600_pipe_state_add_reg(rstate,
185 R_0288CC_SQ_PGM_CF_OFFSET_PS,
186 0x00000000, 0xFFFFFFFF, NULL);
187
188 if (rshader->uses_kill) {
189 /* only set some bits here, the other bits are set in the dsa state */
190 r600_pipe_state_add_reg(rstate,
191 R_02880C_DB_SHADER_CONTROL,
192 S_02880C_KILL_ENABLE(1),
193 S_02880C_KILL_ENABLE(1), NULL);
194 }
195 r600_pipe_state_add_reg(rstate,
196 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
197 0xFFFFFFFF, NULL);
198 }
199
200 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
201 {
202 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
203 struct r600_shader *rshader = &shader->shader;
204 void *ptr;
205
206 /* copy new shader */
207 if (shader->bo == NULL) {
208 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
209 if (shader->bo == NULL) {
210 return -ENOMEM;
211 }
212 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
213 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
214 r600_bo_unmap(rctx->radeon, shader->bo);
215 }
216 /* build state */
217 rshader->flat_shade = rctx->flatshade;
218 switch (rshader->processor_type) {
219 case TGSI_PROCESSOR_VERTEX:
220 if (rshader->family >= CHIP_CEDAR) {
221 evergreen_pipe_shader_vs(ctx, shader);
222 } else {
223 r600_pipe_shader_vs(ctx, shader);
224 }
225 break;
226 case TGSI_PROCESSOR_FRAGMENT:
227 if (rshader->family >= CHIP_CEDAR) {
228 evergreen_pipe_shader_ps(ctx, shader);
229 } else {
230 r600_pipe_shader_ps(ctx, shader);
231 }
232 break;
233 default:
234 return -EINVAL;
235 }
236 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
237 return 0;
238 }
239
240 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
241 {
242 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
243 struct r600_shader *shader = &rshader->shader;
244 const struct util_format_description *desc;
245 enum pipe_format resource_format[160];
246 unsigned i, nresources = 0;
247 struct r600_bc *bc = &shader->bc;
248 struct r600_bc_cf *cf;
249 struct r600_bc_vtx *vtx;
250
251 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
252 return 0;
253 /* doing a full memcmp fell over the refcount */
254 if ((rshader->vertex_elements.count == rctx->vertex_elements->count) &&
255 (!memcmp(&rshader->vertex_elements.elements, &rctx->vertex_elements->elements, 32 * sizeof(struct pipe_vertex_element)))) {
256 return 0;
257 }
258 rshader->vertex_elements = *rctx->vertex_elements;
259 for (i = 0; i < rctx->vertex_elements->count; i++) {
260 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
261 }
262 r600_bo_reference(rctx->radeon, &rshader->bo, NULL);
263 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
264 switch (cf->inst) {
265 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
266 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
267 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
268 desc = util_format_description(resource_format[vtx->buffer_id]);
269 if (desc == NULL) {
270 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
271 return -EINVAL;
272 }
273 vtx->dst_sel_x = desc->swizzle[0];
274 vtx->dst_sel_y = desc->swizzle[1];
275 vtx->dst_sel_z = desc->swizzle[2];
276 vtx->dst_sel_w = desc->swizzle[3];
277 }
278 break;
279 default:
280 break;
281 }
282 }
283 return r600_bc_build(&shader->bc);
284 }
285
286 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
287 {
288 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
289 int r;
290
291 if (shader == NULL)
292 return -EINVAL;
293 /* there should be enough input */
294 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
295 R600_ERR("%d resources provided, expecting %d\n",
296 rctx->vertex_elements->count, shader->shader.bc.nresource);
297 return -EINVAL;
298 }
299 r = r600_shader_update(ctx, shader);
300 if (r)
301 return r;
302 return r600_pipe_shader(ctx, shader);
303 }
304
305 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
306 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
307 {
308 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
309 int r;
310
311 //fprintf(stderr, "--------------------------------------------------------------\n");
312 //tgsi_dump(tokens, 0);
313 shader->shader.family = r600_get_family(rctx->radeon);
314 r = r600_shader_from_tgsi(tokens, &shader->shader);
315 if (r) {
316 R600_ERR("translation from TGSI failed !\n");
317 return r;
318 }
319 r = r600_bc_build(&shader->shader.bc);
320 if (r) {
321 R600_ERR("building bytecode failed !\n");
322 return r;
323 }
324 //fprintf(stderr, "______________________________________________________________\n");
325 return 0;
326 }
327
328 /*
329 * tgsi -> r600 shader
330 */
331 struct r600_shader_tgsi_instruction;
332
333 struct r600_shader_ctx {
334 struct tgsi_shader_info info;
335 struct tgsi_parse_context parse;
336 const struct tgsi_token *tokens;
337 unsigned type;
338 unsigned file_offset[TGSI_FILE_COUNT];
339 unsigned temp_reg;
340 struct r600_shader_tgsi_instruction *inst_info;
341 struct r600_bc *bc;
342 struct r600_shader *shader;
343 u32 value[4];
344 u32 *literals;
345 u32 nliterals;
346 u32 max_driver_temp_used;
347 };
348
349 struct r600_shader_tgsi_instruction {
350 unsigned tgsi_opcode;
351 unsigned is_op3;
352 unsigned r600_opcode;
353 int (*process)(struct r600_shader_ctx *ctx);
354 };
355
356 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
357 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
358
359 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
360 {
361 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
362 int j;
363
364 if (i->Instruction.NumDstRegs > 1) {
365 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
366 return -EINVAL;
367 }
368 if (i->Instruction.Predicate) {
369 R600_ERR("predicate unsupported\n");
370 return -EINVAL;
371 }
372 #if 0
373 if (i->Instruction.Label) {
374 R600_ERR("label unsupported\n");
375 return -EINVAL;
376 }
377 #endif
378 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
379 if (i->Src[j].Register.Dimension ||
380 i->Src[j].Register.Absolute) {
381 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
382 i->Src[j].Register.Dimension,
383 i->Src[j].Register.Absolute);
384 return -EINVAL;
385 }
386 }
387 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
388 if (i->Dst[j].Register.Dimension) {
389 R600_ERR("unsupported dst (dimension)\n");
390 return -EINVAL;
391 }
392 }
393 return 0;
394 }
395
396 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
397 {
398 int i, r;
399 struct r600_bc_alu alu;
400
401 for (i = 0; i < 8; i++) {
402 memset(&alu, 0, sizeof(struct r600_bc_alu));
403
404 if (i < 4)
405 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
406 else
407 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
408
409 if ((i > 1) && (i < 6)) {
410 alu.dst.sel = ctx->shader->input[gpr].gpr;
411 alu.dst.write = 1;
412 }
413
414 alu.dst.chan = i % 4;
415 alu.src[0].chan = (1 - (i % 2));
416 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
417
418 alu.bank_swizzle_force = SQ_ALU_VEC_210;
419 if ((i % 4) == 3)
420 alu.last = 1;
421 r = r600_bc_add_alu(ctx->bc, &alu);
422 if (r)
423 return r;
424 }
425 return 0;
426 }
427
428
429 static int tgsi_declaration(struct r600_shader_ctx *ctx)
430 {
431 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
432 struct r600_bc_vtx vtx;
433 unsigned i;
434 int r;
435
436 switch (d->Declaration.File) {
437 case TGSI_FILE_INPUT:
438 i = ctx->shader->ninput++;
439 ctx->shader->input[i].name = d->Semantic.Name;
440 ctx->shader->input[i].sid = d->Semantic.Index;
441 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
442 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
443 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
444 /* turn input into fetch */
445 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
446 vtx.inst = 0;
447 vtx.fetch_type = 0;
448 vtx.buffer_id = i;
449 /* register containing the index into the buffer */
450 vtx.src_gpr = 0;
451 vtx.src_sel_x = 0;
452 vtx.mega_fetch_count = 0x1F;
453 vtx.dst_gpr = ctx->shader->input[i].gpr;
454 vtx.dst_sel_x = 0;
455 vtx.dst_sel_y = 1;
456 vtx.dst_sel_z = 2;
457 vtx.dst_sel_w = 3;
458 vtx.use_const_fields = 1;
459 r = r600_bc_add_vtx(ctx->bc, &vtx);
460 if (r)
461 return r;
462 }
463 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
464 /* turn input into interpolate on EG */
465 evergreen_interp_alu(ctx, i);
466 }
467 break;
468 case TGSI_FILE_OUTPUT:
469 i = ctx->shader->noutput++;
470 ctx->shader->output[i].name = d->Semantic.Name;
471 ctx->shader->output[i].sid = d->Semantic.Index;
472 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
473 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
474 break;
475 case TGSI_FILE_CONSTANT:
476 case TGSI_FILE_TEMPORARY:
477 case TGSI_FILE_SAMPLER:
478 case TGSI_FILE_ADDRESS:
479 break;
480 default:
481 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
482 return -EINVAL;
483 }
484 return 0;
485 }
486
487 static int r600_get_temp(struct r600_shader_ctx *ctx)
488 {
489 return ctx->temp_reg + ctx->max_driver_temp_used++;
490 }
491
492 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
493 {
494 struct tgsi_full_immediate *immediate;
495 struct r600_shader_ctx ctx;
496 struct r600_bc_output output[32];
497 unsigned output_done, noutput;
498 unsigned opcode;
499 int i, r = 0, pos0;
500
501 ctx.bc = &shader->bc;
502 ctx.shader = shader;
503 r = r600_bc_init(ctx.bc, shader->family);
504 if (r)
505 return r;
506 ctx.tokens = tokens;
507 tgsi_scan_shader(tokens, &ctx.info);
508 tgsi_parse_init(&ctx.parse, tokens);
509 ctx.type = ctx.parse.FullHeader.Processor.Processor;
510 shader->processor_type = ctx.type;
511
512 /* register allocations */
513 /* Values [0,127] correspond to GPR[0..127].
514 * Values [128,159] correspond to constant buffer bank 0
515 * Values [160,191] correspond to constant buffer bank 1
516 * Values [256,511] correspond to cfile constants c[0..255].
517 * Other special values are shown in the list below.
518 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
519 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
520 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
521 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
522 * 248 SQ_ALU_SRC_0: special constant 0.0.
523 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
524 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
525 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
526 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
527 * 253 SQ_ALU_SRC_LITERAL: literal constant.
528 * 254 SQ_ALU_SRC_PV: previous vector result.
529 * 255 SQ_ALU_SRC_PS: previous scalar result.
530 */
531 for (i = 0; i < TGSI_FILE_COUNT; i++) {
532 ctx.file_offset[i] = 0;
533 }
534 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
535 ctx.file_offset[TGSI_FILE_INPUT] = 1;
536 }
537 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == 2) {
538 ctx.file_offset[TGSI_FILE_INPUT] = 1;
539 }
540 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
541 ctx.info.file_count[TGSI_FILE_INPUT];
542 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
543 ctx.info.file_count[TGSI_FILE_OUTPUT];
544
545 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
546
547 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
548 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
549 ctx.info.file_count[TGSI_FILE_TEMPORARY];
550
551 ctx.nliterals = 0;
552 ctx.literals = NULL;
553
554 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
555 tgsi_parse_token(&ctx.parse);
556 switch (ctx.parse.FullToken.Token.Type) {
557 case TGSI_TOKEN_TYPE_IMMEDIATE:
558 immediate = &ctx.parse.FullToken.FullImmediate;
559 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
560 if(ctx.literals == NULL) {
561 r = -ENOMEM;
562 goto out_err;
563 }
564 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
565 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
566 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
567 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
568 ctx.nliterals++;
569 break;
570 case TGSI_TOKEN_TYPE_DECLARATION:
571 r = tgsi_declaration(&ctx);
572 if (r)
573 goto out_err;
574 break;
575 case TGSI_TOKEN_TYPE_INSTRUCTION:
576 r = tgsi_is_supported(&ctx);
577 if (r)
578 goto out_err;
579 ctx.max_driver_temp_used = 0;
580 /* reserve first tmp for everyone */
581 r600_get_temp(&ctx);
582 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
583 if (ctx.bc->chiprev == 2)
584 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
585 else
586 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
587 r = ctx.inst_info->process(&ctx);
588 if (r)
589 goto out_err;
590 r = r600_bc_add_literal(ctx.bc, ctx.value);
591 if (r)
592 goto out_err;
593 break;
594 default:
595 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
596 r = -EINVAL;
597 goto out_err;
598 }
599 }
600 /* export output */
601 noutput = shader->noutput;
602 for (i = 0, pos0 = 0; i < noutput; i++) {
603 memset(&output[i], 0, sizeof(struct r600_bc_output));
604 output[i].gpr = shader->output[i].gpr;
605 output[i].elem_size = 3;
606 output[i].swizzle_x = 0;
607 output[i].swizzle_y = 1;
608 output[i].swizzle_z = 2;
609 output[i].swizzle_w = 3;
610 output[i].barrier = 1;
611 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
612 output[i].array_base = i - pos0;
613 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
614 switch (ctx.type) {
615 case TGSI_PROCESSOR_VERTEX:
616 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
617 output[i].array_base = 60;
618 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
619 /* position doesn't count in array_base */
620 pos0++;
621 }
622 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
623 output[i].array_base = 61;
624 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
625 /* position doesn't count in array_base */
626 pos0++;
627 }
628 break;
629 case TGSI_PROCESSOR_FRAGMENT:
630 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
631 output[i].array_base = shader->output[i].sid;
632 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
633 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
634 output[i].array_base = 61;
635 output[i].swizzle_x = 2;
636 output[i].swizzle_y = 7;
637 output[i].swizzle_z = output[i].swizzle_w = 7;
638 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
639 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
640 output[i].array_base = 61;
641 output[i].swizzle_x = 7;
642 output[i].swizzle_y = 1;
643 output[i].swizzle_z = output[i].swizzle_w = 7;
644 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
645 } else {
646 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
647 r = -EINVAL;
648 goto out_err;
649 }
650 break;
651 default:
652 R600_ERR("unsupported processor type %d\n", ctx.type);
653 r = -EINVAL;
654 goto out_err;
655 }
656 }
657 /* add fake param output for vertex shader if no param is exported */
658 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
659 for (i = 0, pos0 = 0; i < noutput; i++) {
660 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
661 pos0 = 1;
662 break;
663 }
664 }
665 if (!pos0) {
666 memset(&output[i], 0, sizeof(struct r600_bc_output));
667 output[i].gpr = 0;
668 output[i].elem_size = 3;
669 output[i].swizzle_x = 0;
670 output[i].swizzle_y = 1;
671 output[i].swizzle_z = 2;
672 output[i].swizzle_w = 3;
673 output[i].barrier = 1;
674 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
675 output[i].array_base = 0;
676 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
677 noutput++;
678 }
679 }
680 /* add fake pixel export */
681 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
682 memset(&output[0], 0, sizeof(struct r600_bc_output));
683 output[0].gpr = 0;
684 output[0].elem_size = 3;
685 output[0].swizzle_x = 7;
686 output[0].swizzle_y = 7;
687 output[0].swizzle_z = 7;
688 output[0].swizzle_w = 7;
689 output[0].barrier = 1;
690 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
691 output[0].array_base = 0;
692 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
693 noutput++;
694 }
695 /* set export done on last export of each type */
696 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
697 if (i == (noutput - 1)) {
698 output[i].end_of_program = 1;
699 }
700 if (!(output_done & (1 << output[i].type))) {
701 output_done |= (1 << output[i].type);
702 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
703 }
704 }
705 /* add output to bytecode */
706 for (i = 0; i < noutput; i++) {
707 r = r600_bc_add_output(ctx.bc, &output[i]);
708 if (r)
709 goto out_err;
710 }
711 free(ctx.literals);
712 tgsi_parse_free(&ctx.parse);
713 return 0;
714 out_err:
715 free(ctx.literals);
716 tgsi_parse_free(&ctx.parse);
717 return r;
718 }
719
720 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
721 {
722 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
723 return -EINVAL;
724 }
725
726 static int tgsi_end(struct r600_shader_ctx *ctx)
727 {
728 return 0;
729 }
730
731 static int tgsi_src(struct r600_shader_ctx *ctx,
732 const struct tgsi_full_src_register *tgsi_src,
733 struct r600_bc_alu_src *r600_src)
734 {
735 int index;
736 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
737 r600_src->sel = tgsi_src->Register.Index;
738 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
739 r600_src->sel = 0;
740 index = tgsi_src->Register.Index;
741 ctx->value[0] = ctx->literals[index * 4 + 0];
742 ctx->value[1] = ctx->literals[index * 4 + 1];
743 ctx->value[2] = ctx->literals[index * 4 + 2];
744 ctx->value[3] = ctx->literals[index * 4 + 3];
745 }
746 if (tgsi_src->Register.Indirect)
747 r600_src->rel = V_SQ_REL_RELATIVE;
748 r600_src->neg = tgsi_src->Register.Negate;
749 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
750 return 0;
751 }
752
753 static int tgsi_dst(struct r600_shader_ctx *ctx,
754 const struct tgsi_full_dst_register *tgsi_dst,
755 unsigned swizzle,
756 struct r600_bc_alu_dst *r600_dst)
757 {
758 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
759
760 r600_dst->sel = tgsi_dst->Register.Index;
761 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
762 r600_dst->chan = swizzle;
763 r600_dst->write = 1;
764 if (tgsi_dst->Register.Indirect)
765 r600_dst->rel = V_SQ_REL_RELATIVE;
766 if (inst->Instruction.Saturate) {
767 r600_dst->clamp = 1;
768 }
769 return 0;
770 }
771
772 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
773 {
774 switch (swizzle) {
775 case 0:
776 return tgsi_src->Register.SwizzleX;
777 case 1:
778 return tgsi_src->Register.SwizzleY;
779 case 2:
780 return tgsi_src->Register.SwizzleZ;
781 case 3:
782 return tgsi_src->Register.SwizzleW;
783 default:
784 return 0;
785 }
786 }
787
788 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
789 {
790 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
791 struct r600_bc_alu alu;
792 int i, j, k, nconst, r;
793
794 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
795 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
796 nconst++;
797 }
798 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
799 if (r) {
800 return r;
801 }
802 }
803 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
804 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
805 int treg = r600_get_temp(ctx);
806 for (k = 0; k < 4; k++) {
807 memset(&alu, 0, sizeof(struct r600_bc_alu));
808 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
809 alu.src[0].sel = r600_src[i].sel;
810 alu.src[0].chan = k;
811 alu.dst.sel = treg;
812 alu.dst.chan = k;
813 alu.dst.write = 1;
814 if (k == 3)
815 alu.last = 1;
816 r = r600_bc_add_alu(ctx->bc, &alu);
817 if (r)
818 return r;
819 }
820 r600_src[i].sel = treg;
821 j--;
822 }
823 }
824 return 0;
825 }
826
827 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
828 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
829 {
830 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
831 struct r600_bc_alu alu;
832 int i, j, k, nliteral, r;
833
834 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
835 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
836 nliteral++;
837 }
838 }
839 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
840 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
841 int treg = r600_get_temp(ctx);
842 for (k = 0; k < 4; k++) {
843 memset(&alu, 0, sizeof(struct r600_bc_alu));
844 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
845 alu.src[0].sel = r600_src[i].sel;
846 alu.src[0].chan = k;
847 alu.dst.sel = treg;
848 alu.dst.chan = k;
849 alu.dst.write = 1;
850 if (k == 3)
851 alu.last = 1;
852 r = r600_bc_add_alu(ctx->bc, &alu);
853 if (r)
854 return r;
855 }
856 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
857 if (r)
858 return r;
859 r600_src[i].sel = treg;
860 j--;
861 }
862 }
863 return 0;
864 }
865
866 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
867 {
868 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
869 struct r600_bc_alu_src r600_src[3];
870 struct r600_bc_alu alu;
871 int i, j, r;
872 int lasti = 0;
873
874 for (i = 0; i < 4; i++) {
875 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
876 lasti = i;
877 }
878 }
879
880 r = tgsi_split_constant(ctx, r600_src);
881 if (r)
882 return r;
883 r = tgsi_split_literal_constant(ctx, r600_src);
884 if (r)
885 return r;
886 for (i = 0; i < lasti + 1; i++) {
887 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
888 continue;
889
890 memset(&alu, 0, sizeof(struct r600_bc_alu));
891 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
892 if (r)
893 return r;
894
895 alu.inst = ctx->inst_info->r600_opcode;
896 if (!swap) {
897 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
898 alu.src[j] = r600_src[j];
899 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
900 }
901 } else {
902 alu.src[0] = r600_src[1];
903 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
904
905 alu.src[1] = r600_src[0];
906 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
907 }
908 /* handle some special cases */
909 switch (ctx->inst_info->tgsi_opcode) {
910 case TGSI_OPCODE_SUB:
911 alu.src[1].neg = 1;
912 break;
913 case TGSI_OPCODE_ABS:
914 alu.src[0].abs = 1;
915 break;
916 default:
917 break;
918 }
919 if (i == lasti) {
920 alu.last = 1;
921 }
922 r = r600_bc_add_alu(ctx->bc, &alu);
923 if (r)
924 return r;
925 }
926 return 0;
927 }
928
929 static int tgsi_op2(struct r600_shader_ctx *ctx)
930 {
931 return tgsi_op2_s(ctx, 0);
932 }
933
934 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
935 {
936 return tgsi_op2_s(ctx, 1);
937 }
938
939 /*
940 * r600 - trunc to -PI..PI range
941 * r700 - normalize by dividing by 2PI
942 * see fdo bug 27901
943 */
944 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
945 struct r600_bc_alu_src r600_src[3])
946 {
947 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
948 int r;
949 uint32_t lit_vals[4];
950 struct r600_bc_alu alu;
951
952 memset(lit_vals, 0, 4*4);
953 r = tgsi_split_constant(ctx, r600_src);
954 if (r)
955 return r;
956 r = tgsi_split_literal_constant(ctx, r600_src);
957 if (r)
958 return r;
959
960 r = tgsi_split_literal_constant(ctx, r600_src);
961 if (r)
962 return r;
963
964 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
965 lit_vals[1] = fui(0.5f);
966
967 memset(&alu, 0, sizeof(struct r600_bc_alu));
968 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
969 alu.is_op3 = 1;
970
971 alu.dst.chan = 0;
972 alu.dst.sel = ctx->temp_reg;
973 alu.dst.write = 1;
974
975 alu.src[0] = r600_src[0];
976 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
977
978 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
979 alu.src[1].chan = 0;
980 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
981 alu.src[2].chan = 1;
982 alu.last = 1;
983 r = r600_bc_add_alu(ctx->bc, &alu);
984 if (r)
985 return r;
986 r = r600_bc_add_literal(ctx->bc, lit_vals);
987 if (r)
988 return r;
989
990 memset(&alu, 0, sizeof(struct r600_bc_alu));
991 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
992
993 alu.dst.chan = 0;
994 alu.dst.sel = ctx->temp_reg;
995 alu.dst.write = 1;
996
997 alu.src[0].sel = ctx->temp_reg;
998 alu.src[0].chan = 0;
999 alu.last = 1;
1000 r = r600_bc_add_alu(ctx->bc, &alu);
1001 if (r)
1002 return r;
1003
1004 if (ctx->bc->chiprev == 0) {
1005 lit_vals[0] = fui(3.1415926535897f * 2.0f);
1006 lit_vals[1] = fui(-3.1415926535897f);
1007 } else {
1008 lit_vals[0] = fui(1.0f);
1009 lit_vals[1] = fui(-0.5f);
1010 }
1011
1012 memset(&alu, 0, sizeof(struct r600_bc_alu));
1013 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1014 alu.is_op3 = 1;
1015
1016 alu.dst.chan = 0;
1017 alu.dst.sel = ctx->temp_reg;
1018 alu.dst.write = 1;
1019
1020 alu.src[0].sel = ctx->temp_reg;
1021 alu.src[0].chan = 0;
1022
1023 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1024 alu.src[1].chan = 0;
1025 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1026 alu.src[2].chan = 1;
1027 alu.last = 1;
1028 r = r600_bc_add_alu(ctx->bc, &alu);
1029 if (r)
1030 return r;
1031 r = r600_bc_add_literal(ctx->bc, lit_vals);
1032 if (r)
1033 return r;
1034 return 0;
1035 }
1036
1037 static int tgsi_trig(struct r600_shader_ctx *ctx)
1038 {
1039 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1040 struct r600_bc_alu_src r600_src[3];
1041 struct r600_bc_alu alu;
1042 int i, r;
1043 int lasti = 0;
1044
1045 r = tgsi_setup_trig(ctx, r600_src);
1046 if (r)
1047 return r;
1048
1049 memset(&alu, 0, sizeof(struct r600_bc_alu));
1050 alu.inst = ctx->inst_info->r600_opcode;
1051 alu.dst.chan = 0;
1052 alu.dst.sel = ctx->temp_reg;
1053 alu.dst.write = 1;
1054
1055 alu.src[0].sel = ctx->temp_reg;
1056 alu.src[0].chan = 0;
1057 alu.last = 1;
1058 r = r600_bc_add_alu(ctx->bc, &alu);
1059 if (r)
1060 return r;
1061
1062 /* replicate result */
1063 for (i = 0; i < 4; i++) {
1064 if (inst->Dst[0].Register.WriteMask & (1 << i))
1065 lasti = i;
1066 }
1067 for (i = 0; i < lasti + 1; i++) {
1068 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1069 continue;
1070
1071 memset(&alu, 0, sizeof(struct r600_bc_alu));
1072 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1073
1074 alu.src[0].sel = ctx->temp_reg;
1075 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1076 if (r)
1077 return r;
1078 if (i == lasti)
1079 alu.last = 1;
1080 r = r600_bc_add_alu(ctx->bc, &alu);
1081 if (r)
1082 return r;
1083 }
1084 return 0;
1085 }
1086
1087 static int tgsi_scs(struct r600_shader_ctx *ctx)
1088 {
1089 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1090 struct r600_bc_alu_src r600_src[3];
1091 struct r600_bc_alu alu;
1092 int r;
1093
1094 /* We'll only need the trig stuff if we are going to write to the
1095 * X or Y components of the destination vector.
1096 */
1097 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1098 r = tgsi_setup_trig(ctx, r600_src);
1099 if (r)
1100 return r;
1101 }
1102
1103 /* dst.x = COS */
1104 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1105 memset(&alu, 0, sizeof(struct r600_bc_alu));
1106 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1107 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1108 if (r)
1109 return r;
1110
1111 alu.src[0].sel = ctx->temp_reg;
1112 alu.src[0].chan = 0;
1113 alu.last = 1;
1114 r = r600_bc_add_alu(ctx->bc, &alu);
1115 if (r)
1116 return r;
1117 }
1118
1119 /* dst.y = SIN */
1120 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1121 memset(&alu, 0, sizeof(struct r600_bc_alu));
1122 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1123 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1124 if (r)
1125 return r;
1126
1127 alu.src[0].sel = ctx->temp_reg;
1128 alu.src[0].chan = 0;
1129 alu.last = 1;
1130 r = r600_bc_add_alu(ctx->bc, &alu);
1131 if (r)
1132 return r;
1133 }
1134
1135 /* dst.z = 0.0; */
1136 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1137 memset(&alu, 0, sizeof(struct r600_bc_alu));
1138
1139 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1140
1141 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1142 if (r)
1143 return r;
1144
1145 alu.src[0].sel = V_SQ_ALU_SRC_0;
1146 alu.src[0].chan = 0;
1147
1148 alu.last = 1;
1149
1150 r = r600_bc_add_alu(ctx->bc, &alu);
1151 if (r)
1152 return r;
1153
1154 r = r600_bc_add_literal(ctx->bc, ctx->value);
1155 if (r)
1156 return r;
1157 }
1158
1159 /* dst.w = 1.0; */
1160 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1161 memset(&alu, 0, sizeof(struct r600_bc_alu));
1162
1163 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1164
1165 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1166 if (r)
1167 return r;
1168
1169 alu.src[0].sel = V_SQ_ALU_SRC_1;
1170 alu.src[0].chan = 0;
1171
1172 alu.last = 1;
1173
1174 r = r600_bc_add_alu(ctx->bc, &alu);
1175 if (r)
1176 return r;
1177
1178 r = r600_bc_add_literal(ctx->bc, ctx->value);
1179 if (r)
1180 return r;
1181 }
1182
1183 return 0;
1184 }
1185
1186 static int tgsi_kill(struct r600_shader_ctx *ctx)
1187 {
1188 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1189 struct r600_bc_alu alu;
1190 int i, r;
1191
1192 for (i = 0; i < 4; i++) {
1193 memset(&alu, 0, sizeof(struct r600_bc_alu));
1194 alu.inst = ctx->inst_info->r600_opcode;
1195
1196 alu.dst.chan = i;
1197
1198 alu.src[0].sel = V_SQ_ALU_SRC_0;
1199
1200 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1201 alu.src[1].sel = V_SQ_ALU_SRC_1;
1202 alu.src[1].neg = 1;
1203 } else {
1204 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1205 if (r)
1206 return r;
1207 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1208 }
1209 if (i == 3) {
1210 alu.last = 1;
1211 }
1212 r = r600_bc_add_alu(ctx->bc, &alu);
1213 if (r)
1214 return r;
1215 }
1216 r = r600_bc_add_literal(ctx->bc, ctx->value);
1217 if (r)
1218 return r;
1219
1220 /* kill must be last in ALU */
1221 ctx->bc->force_add_cf = 1;
1222 ctx->shader->uses_kill = TRUE;
1223 return 0;
1224 }
1225
1226 static int tgsi_lit(struct r600_shader_ctx *ctx)
1227 {
1228 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1229 struct r600_bc_alu alu;
1230 struct r600_bc_alu_src r600_src[3];
1231 int r;
1232
1233 r = tgsi_split_constant(ctx, r600_src);
1234 if (r)
1235 return r;
1236 r = tgsi_split_literal_constant(ctx, r600_src);
1237 if (r)
1238 return r;
1239
1240 /* dst.x, <- 1.0 */
1241 memset(&alu, 0, sizeof(struct r600_bc_alu));
1242 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1243 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1244 alu.src[0].chan = 0;
1245 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1246 if (r)
1247 return r;
1248 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1249 r = r600_bc_add_alu(ctx->bc, &alu);
1250 if (r)
1251 return r;
1252
1253 /* dst.y = max(src.x, 0.0) */
1254 memset(&alu, 0, sizeof(struct r600_bc_alu));
1255 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1256 alu.src[0] = r600_src[0];
1257 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1258 alu.src[1].chan = 0;
1259 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1260 if (r)
1261 return r;
1262 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1263 r = r600_bc_add_alu(ctx->bc, &alu);
1264 if (r)
1265 return r;
1266
1267 /* dst.w, <- 1.0 */
1268 memset(&alu, 0, sizeof(struct r600_bc_alu));
1269 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1270 alu.src[0].sel = V_SQ_ALU_SRC_1;
1271 alu.src[0].chan = 0;
1272 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1273 if (r)
1274 return r;
1275 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1276 alu.last = 1;
1277 r = r600_bc_add_alu(ctx->bc, &alu);
1278 if (r)
1279 return r;
1280
1281 r = r600_bc_add_literal(ctx->bc, ctx->value);
1282 if (r)
1283 return r;
1284
1285 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1286 {
1287 int chan;
1288 int sel;
1289
1290 /* dst.z = log(src.y) */
1291 memset(&alu, 0, sizeof(struct r600_bc_alu));
1292 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1293 alu.src[0] = r600_src[0];
1294 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1295 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1296 if (r)
1297 return r;
1298 alu.last = 1;
1299 r = r600_bc_add_alu(ctx->bc, &alu);
1300 if (r)
1301 return r;
1302
1303 r = r600_bc_add_literal(ctx->bc, ctx->value);
1304 if (r)
1305 return r;
1306
1307 chan = alu.dst.chan;
1308 sel = alu.dst.sel;
1309
1310 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1311 memset(&alu, 0, sizeof(struct r600_bc_alu));
1312 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1313 alu.src[0] = r600_src[0];
1314 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1315 alu.src[1].sel = sel;
1316 alu.src[1].chan = chan;
1317
1318 alu.src[2] = r600_src[0];
1319 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1320 alu.dst.sel = ctx->temp_reg;
1321 alu.dst.chan = 0;
1322 alu.dst.write = 1;
1323 alu.is_op3 = 1;
1324 alu.last = 1;
1325 r = r600_bc_add_alu(ctx->bc, &alu);
1326 if (r)
1327 return r;
1328
1329 r = r600_bc_add_literal(ctx->bc, ctx->value);
1330 if (r)
1331 return r;
1332 /* dst.z = exp(tmp.x) */
1333 memset(&alu, 0, sizeof(struct r600_bc_alu));
1334 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1335 alu.src[0].sel = ctx->temp_reg;
1336 alu.src[0].chan = 0;
1337 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1338 if (r)
1339 return r;
1340 alu.last = 1;
1341 r = r600_bc_add_alu(ctx->bc, &alu);
1342 if (r)
1343 return r;
1344 }
1345 return 0;
1346 }
1347
1348 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1349 {
1350 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1351 struct r600_bc_alu alu;
1352 int i, r;
1353
1354 memset(&alu, 0, sizeof(struct r600_bc_alu));
1355
1356 /* FIXME:
1357 * For state trackers other than OpenGL, we'll want to use
1358 * _RECIPSQRT_IEEE instead.
1359 */
1360 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1361
1362 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1363 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1364 if (r)
1365 return r;
1366 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1367 alu.src[i].abs = 1;
1368 }
1369 alu.dst.sel = ctx->temp_reg;
1370 alu.dst.write = 1;
1371 alu.last = 1;
1372 r = r600_bc_add_alu(ctx->bc, &alu);
1373 if (r)
1374 return r;
1375 r = r600_bc_add_literal(ctx->bc, ctx->value);
1376 if (r)
1377 return r;
1378 /* replicate result */
1379 return tgsi_helper_tempx_replicate(ctx);
1380 }
1381
1382 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1383 {
1384 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1385 struct r600_bc_alu alu;
1386 int i, r;
1387
1388 for (i = 0; i < 4; i++) {
1389 memset(&alu, 0, sizeof(struct r600_bc_alu));
1390 alu.src[0].sel = ctx->temp_reg;
1391 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1392 alu.dst.chan = i;
1393 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1394 if (r)
1395 return r;
1396 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1397 if (i == 3)
1398 alu.last = 1;
1399 r = r600_bc_add_alu(ctx->bc, &alu);
1400 if (r)
1401 return r;
1402 }
1403 return 0;
1404 }
1405
1406 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1407 {
1408 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1409 struct r600_bc_alu alu;
1410 int i, r;
1411
1412 memset(&alu, 0, sizeof(struct r600_bc_alu));
1413 alu.inst = ctx->inst_info->r600_opcode;
1414 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1415 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1416 if (r)
1417 return r;
1418 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1419 }
1420 alu.dst.sel = ctx->temp_reg;
1421 alu.dst.write = 1;
1422 alu.last = 1;
1423 r = r600_bc_add_alu(ctx->bc, &alu);
1424 if (r)
1425 return r;
1426 r = r600_bc_add_literal(ctx->bc, ctx->value);
1427 if (r)
1428 return r;
1429 /* replicate result */
1430 return tgsi_helper_tempx_replicate(ctx);
1431 }
1432
1433 static int tgsi_pow(struct r600_shader_ctx *ctx)
1434 {
1435 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1436 struct r600_bc_alu alu;
1437 int r;
1438
1439 /* LOG2(a) */
1440 memset(&alu, 0, sizeof(struct r600_bc_alu));
1441 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1442 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1443 if (r)
1444 return r;
1445 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1446 alu.dst.sel = ctx->temp_reg;
1447 alu.dst.write = 1;
1448 alu.last = 1;
1449 r = r600_bc_add_alu(ctx->bc, &alu);
1450 if (r)
1451 return r;
1452 r = r600_bc_add_literal(ctx->bc,ctx->value);
1453 if (r)
1454 return r;
1455 /* b * LOG2(a) */
1456 memset(&alu, 0, sizeof(struct r600_bc_alu));
1457 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1458 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1459 if (r)
1460 return r;
1461 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1462 alu.src[1].sel = ctx->temp_reg;
1463 alu.dst.sel = ctx->temp_reg;
1464 alu.dst.write = 1;
1465 alu.last = 1;
1466 r = r600_bc_add_alu(ctx->bc, &alu);
1467 if (r)
1468 return r;
1469 r = r600_bc_add_literal(ctx->bc,ctx->value);
1470 if (r)
1471 return r;
1472 /* POW(a,b) = EXP2(b * LOG2(a))*/
1473 memset(&alu, 0, sizeof(struct r600_bc_alu));
1474 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1475 alu.src[0].sel = ctx->temp_reg;
1476 alu.dst.sel = ctx->temp_reg;
1477 alu.dst.write = 1;
1478 alu.last = 1;
1479 r = r600_bc_add_alu(ctx->bc, &alu);
1480 if (r)
1481 return r;
1482 r = r600_bc_add_literal(ctx->bc,ctx->value);
1483 if (r)
1484 return r;
1485 return tgsi_helper_tempx_replicate(ctx);
1486 }
1487
1488 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1489 {
1490 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1491 struct r600_bc_alu alu;
1492 struct r600_bc_alu_src r600_src[3];
1493 int i, r;
1494
1495 r = tgsi_split_constant(ctx, r600_src);
1496 if (r)
1497 return r;
1498 r = tgsi_split_literal_constant(ctx, r600_src);
1499 if (r)
1500 return r;
1501
1502 /* tmp = (src > 0 ? 1 : src) */
1503 for (i = 0; i < 4; i++) {
1504 memset(&alu, 0, sizeof(struct r600_bc_alu));
1505 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1506 alu.is_op3 = 1;
1507
1508 alu.dst.sel = ctx->temp_reg;
1509 alu.dst.chan = i;
1510
1511 alu.src[0] = r600_src[0];
1512 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1513
1514 alu.src[1].sel = V_SQ_ALU_SRC_1;
1515
1516 alu.src[2] = r600_src[0];
1517 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1518 if (i == 3)
1519 alu.last = 1;
1520 r = r600_bc_add_alu(ctx->bc, &alu);
1521 if (r)
1522 return r;
1523 }
1524 r = r600_bc_add_literal(ctx->bc, ctx->value);
1525 if (r)
1526 return r;
1527
1528 /* dst = (-tmp > 0 ? -1 : tmp) */
1529 for (i = 0; i < 4; i++) {
1530 memset(&alu, 0, sizeof(struct r600_bc_alu));
1531 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1532 alu.is_op3 = 1;
1533 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1534 if (r)
1535 return r;
1536
1537 alu.src[0].sel = ctx->temp_reg;
1538 alu.src[0].chan = i;
1539 alu.src[0].neg = 1;
1540
1541 alu.src[1].sel = V_SQ_ALU_SRC_1;
1542 alu.src[1].neg = 1;
1543
1544 alu.src[2].sel = ctx->temp_reg;
1545 alu.src[2].chan = i;
1546
1547 if (i == 3)
1548 alu.last = 1;
1549 r = r600_bc_add_alu(ctx->bc, &alu);
1550 if (r)
1551 return r;
1552 }
1553 return 0;
1554 }
1555
1556 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1557 {
1558 struct r600_bc_alu alu;
1559 int i, r;
1560
1561 r = r600_bc_add_literal(ctx->bc, ctx->value);
1562 if (r)
1563 return r;
1564 for (i = 0; i < 4; i++) {
1565 memset(&alu, 0, sizeof(struct r600_bc_alu));
1566 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1567 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1568 alu.dst.chan = i;
1569 } else {
1570 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1571 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1572 if (r)
1573 return r;
1574 alu.src[0].sel = ctx->temp_reg;
1575 alu.src[0].chan = i;
1576 }
1577 if (i == 3) {
1578 alu.last = 1;
1579 }
1580 r = r600_bc_add_alu(ctx->bc, &alu);
1581 if (r)
1582 return r;
1583 }
1584 return 0;
1585 }
1586
1587 static int tgsi_op3(struct r600_shader_ctx *ctx)
1588 {
1589 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1590 struct r600_bc_alu_src r600_src[3];
1591 struct r600_bc_alu alu;
1592 int i, j, r;
1593
1594 r = tgsi_split_constant(ctx, r600_src);
1595 if (r)
1596 return r;
1597 r = tgsi_split_literal_constant(ctx, r600_src);
1598 if (r)
1599 return r;
1600 /* do it in 2 step as op3 doesn't support writemask */
1601 for (i = 0; i < 4; i++) {
1602 memset(&alu, 0, sizeof(struct r600_bc_alu));
1603 alu.inst = ctx->inst_info->r600_opcode;
1604 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1605 alu.src[j] = r600_src[j];
1606 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1607 }
1608 alu.dst.sel = ctx->temp_reg;
1609 alu.dst.chan = i;
1610 alu.dst.write = 1;
1611 alu.is_op3 = 1;
1612 if (i == 3) {
1613 alu.last = 1;
1614 }
1615 r = r600_bc_add_alu(ctx->bc, &alu);
1616 if (r)
1617 return r;
1618 }
1619 return tgsi_helper_copy(ctx, inst);
1620 }
1621
1622 static int tgsi_dp(struct r600_shader_ctx *ctx)
1623 {
1624 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1625 struct r600_bc_alu_src r600_src[3];
1626 struct r600_bc_alu alu;
1627 int i, j, r;
1628
1629 r = tgsi_split_constant(ctx, r600_src);
1630 if (r)
1631 return r;
1632 r = tgsi_split_literal_constant(ctx, r600_src);
1633 if (r)
1634 return r;
1635 for (i = 0; i < 4; i++) {
1636 memset(&alu, 0, sizeof(struct r600_bc_alu));
1637 alu.inst = ctx->inst_info->r600_opcode;
1638 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1639 alu.src[j] = r600_src[j];
1640 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1641 }
1642 alu.dst.sel = ctx->temp_reg;
1643 alu.dst.chan = i;
1644 alu.dst.write = 1;
1645 /* handle some special cases */
1646 switch (ctx->inst_info->tgsi_opcode) {
1647 case TGSI_OPCODE_DP2:
1648 if (i > 1) {
1649 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1650 alu.src[0].chan = alu.src[1].chan = 0;
1651 }
1652 break;
1653 case TGSI_OPCODE_DP3:
1654 if (i > 2) {
1655 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1656 alu.src[0].chan = alu.src[1].chan = 0;
1657 }
1658 break;
1659 case TGSI_OPCODE_DPH:
1660 if (i == 3) {
1661 alu.src[0].sel = V_SQ_ALU_SRC_1;
1662 alu.src[0].chan = 0;
1663 alu.src[0].neg = 0;
1664 }
1665 break;
1666 default:
1667 break;
1668 }
1669 if (i == 3) {
1670 alu.last = 1;
1671 }
1672 r = r600_bc_add_alu(ctx->bc, &alu);
1673 if (r)
1674 return r;
1675 }
1676 return tgsi_helper_copy(ctx, inst);
1677 }
1678
1679 static int tgsi_tex(struct r600_shader_ctx *ctx)
1680 {
1681 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1682 struct r600_bc_tex tex;
1683 struct r600_bc_alu alu;
1684 unsigned src_gpr;
1685 int r, i;
1686 int opcode;
1687 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1688 uint32_t lit_vals[4];
1689
1690 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1691
1692 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1693 /* Add perspective divide */
1694 memset(&alu, 0, sizeof(struct r600_bc_alu));
1695 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1696 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1697 if (r)
1698 return r;
1699
1700 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1701 alu.dst.sel = ctx->temp_reg;
1702 alu.dst.chan = 3;
1703 alu.last = 1;
1704 alu.dst.write = 1;
1705 r = r600_bc_add_alu(ctx->bc, &alu);
1706 if (r)
1707 return r;
1708
1709 for (i = 0; i < 3; i++) {
1710 memset(&alu, 0, sizeof(struct r600_bc_alu));
1711 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1712 alu.src[0].sel = ctx->temp_reg;
1713 alu.src[0].chan = 3;
1714 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1715 if (r)
1716 return r;
1717 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1718 alu.dst.sel = ctx->temp_reg;
1719 alu.dst.chan = i;
1720 alu.dst.write = 1;
1721 r = r600_bc_add_alu(ctx->bc, &alu);
1722 if (r)
1723 return r;
1724 }
1725 memset(&alu, 0, sizeof(struct r600_bc_alu));
1726 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1727 alu.src[0].sel = V_SQ_ALU_SRC_1;
1728 alu.src[0].chan = 0;
1729 alu.dst.sel = ctx->temp_reg;
1730 alu.dst.chan = 3;
1731 alu.last = 1;
1732 alu.dst.write = 1;
1733 r = r600_bc_add_alu(ctx->bc, &alu);
1734 if (r)
1735 return r;
1736 src_not_temp = FALSE;
1737 src_gpr = ctx->temp_reg;
1738 }
1739
1740 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1741 int src_chan, src2_chan;
1742
1743 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1744 for (i = 0; i < 4; i++) {
1745 memset(&alu, 0, sizeof(struct r600_bc_alu));
1746 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1747 switch (i) {
1748 case 0:
1749 src_chan = 2;
1750 src2_chan = 1;
1751 break;
1752 case 1:
1753 src_chan = 2;
1754 src2_chan = 0;
1755 break;
1756 case 2:
1757 src_chan = 0;
1758 src2_chan = 2;
1759 break;
1760 case 3:
1761 src_chan = 1;
1762 src2_chan = 2;
1763 break;
1764 default:
1765 assert(0);
1766 src_chan = 0;
1767 src2_chan = 0;
1768 break;
1769 }
1770 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1771 if (r)
1772 return r;
1773 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1774 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1775 if (r)
1776 return r;
1777 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1778 alu.dst.sel = ctx->temp_reg;
1779 alu.dst.chan = i;
1780 if (i == 3)
1781 alu.last = 1;
1782 alu.dst.write = 1;
1783 r = r600_bc_add_alu(ctx->bc, &alu);
1784 if (r)
1785 return r;
1786 }
1787
1788 /* tmp1.z = RCP_e(|tmp1.z|) */
1789 memset(&alu, 0, sizeof(struct r600_bc_alu));
1790 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1791 alu.src[0].sel = ctx->temp_reg;
1792 alu.src[0].chan = 2;
1793 alu.src[0].abs = 1;
1794 alu.dst.sel = ctx->temp_reg;
1795 alu.dst.chan = 2;
1796 alu.dst.write = 1;
1797 alu.last = 1;
1798 r = r600_bc_add_alu(ctx->bc, &alu);
1799 if (r)
1800 return r;
1801
1802 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1803 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1804 * muladd has no writemask, have to use another temp
1805 */
1806 memset(&alu, 0, sizeof(struct r600_bc_alu));
1807 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1808 alu.is_op3 = 1;
1809
1810 alu.src[0].sel = ctx->temp_reg;
1811 alu.src[0].chan = 0;
1812 alu.src[1].sel = ctx->temp_reg;
1813 alu.src[1].chan = 2;
1814
1815 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1816 alu.src[2].chan = 0;
1817
1818 alu.dst.sel = ctx->temp_reg;
1819 alu.dst.chan = 0;
1820 alu.dst.write = 1;
1821
1822 r = r600_bc_add_alu(ctx->bc, &alu);
1823 if (r)
1824 return r;
1825
1826 memset(&alu, 0, sizeof(struct r600_bc_alu));
1827 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1828 alu.is_op3 = 1;
1829
1830 alu.src[0].sel = ctx->temp_reg;
1831 alu.src[0].chan = 1;
1832 alu.src[1].sel = ctx->temp_reg;
1833 alu.src[1].chan = 2;
1834
1835 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1836 alu.src[2].chan = 0;
1837
1838 alu.dst.sel = ctx->temp_reg;
1839 alu.dst.chan = 1;
1840 alu.dst.write = 1;
1841
1842 alu.last = 1;
1843 r = r600_bc_add_alu(ctx->bc, &alu);
1844 if (r)
1845 return r;
1846
1847 lit_vals[0] = fui(1.5f);
1848
1849 r = r600_bc_add_literal(ctx->bc, lit_vals);
1850 if (r)
1851 return r;
1852 src_not_temp = FALSE;
1853 src_gpr = ctx->temp_reg;
1854 }
1855
1856 if (src_not_temp) {
1857 for (i = 0; i < 4; i++) {
1858 memset(&alu, 0, sizeof(struct r600_bc_alu));
1859 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1860 alu.src[0].sel = src_gpr;
1861 alu.src[0].chan = i;
1862 alu.dst.sel = ctx->temp_reg;
1863 alu.dst.chan = i;
1864 if (i == 3)
1865 alu.last = 1;
1866 alu.dst.write = 1;
1867 r = r600_bc_add_alu(ctx->bc, &alu);
1868 if (r)
1869 return r;
1870 }
1871 src_gpr = ctx->temp_reg;
1872 }
1873
1874 opcode = ctx->inst_info->r600_opcode;
1875 if (opcode == SQ_TEX_INST_SAMPLE &&
1876 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1877 opcode = SQ_TEX_INST_SAMPLE_C;
1878
1879 memset(&tex, 0, sizeof(struct r600_bc_tex));
1880 tex.inst = opcode;
1881 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1882 tex.resource_id = tex.sampler_id;
1883 if (ctx->shader->processor_type == TGSI_PROCESSOR_VERTEX)
1884 tex.resource_id += PIPE_MAX_ATTRIBS;
1885 tex.src_gpr = src_gpr;
1886 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1887 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1888 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1889 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1890 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1891 tex.src_sel_x = 0;
1892 tex.src_sel_y = 1;
1893 tex.src_sel_z = 2;
1894 tex.src_sel_w = 3;
1895
1896 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1897 tex.src_sel_x = 1;
1898 tex.src_sel_y = 0;
1899 tex.src_sel_z = 3;
1900 tex.src_sel_w = 1;
1901 }
1902
1903 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1904 tex.coord_type_x = 1;
1905 tex.coord_type_y = 1;
1906 tex.coord_type_z = 1;
1907 tex.coord_type_w = 1;
1908 }
1909
1910 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1911 tex.src_sel_w = 2;
1912
1913 r = r600_bc_add_tex(ctx->bc, &tex);
1914 if (r)
1915 return r;
1916
1917 /* add shadow ambient support - gallium doesn't do it yet */
1918 return 0;
1919
1920 }
1921
1922 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1923 {
1924 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1925 struct r600_bc_alu_src r600_src[3];
1926 struct r600_bc_alu alu;
1927 unsigned i;
1928 int r;
1929
1930 r = tgsi_split_constant(ctx, r600_src);
1931 if (r)
1932 return r;
1933 r = tgsi_split_literal_constant(ctx, r600_src);
1934 if (r)
1935 return r;
1936 /* 1 - src0 */
1937 for (i = 0; i < 4; i++) {
1938 memset(&alu, 0, sizeof(struct r600_bc_alu));
1939 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1940 alu.src[0].sel = V_SQ_ALU_SRC_1;
1941 alu.src[0].chan = 0;
1942 alu.src[1] = r600_src[0];
1943 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1944 alu.src[1].neg = 1;
1945 alu.dst.sel = ctx->temp_reg;
1946 alu.dst.chan = i;
1947 if (i == 3) {
1948 alu.last = 1;
1949 }
1950 alu.dst.write = 1;
1951 r = r600_bc_add_alu(ctx->bc, &alu);
1952 if (r)
1953 return r;
1954 }
1955 r = r600_bc_add_literal(ctx->bc, ctx->value);
1956 if (r)
1957 return r;
1958
1959 /* (1 - src0) * src2 */
1960 for (i = 0; i < 4; i++) {
1961 memset(&alu, 0, sizeof(struct r600_bc_alu));
1962 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1963 alu.src[0].sel = ctx->temp_reg;
1964 alu.src[0].chan = i;
1965 alu.src[1] = r600_src[2];
1966 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1967 alu.dst.sel = ctx->temp_reg;
1968 alu.dst.chan = i;
1969 if (i == 3) {
1970 alu.last = 1;
1971 }
1972 alu.dst.write = 1;
1973 r = r600_bc_add_alu(ctx->bc, &alu);
1974 if (r)
1975 return r;
1976 }
1977 r = r600_bc_add_literal(ctx->bc, ctx->value);
1978 if (r)
1979 return r;
1980
1981 /* src0 * src1 + (1 - src0) * src2 */
1982 for (i = 0; i < 4; i++) {
1983 memset(&alu, 0, sizeof(struct r600_bc_alu));
1984 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1985 alu.is_op3 = 1;
1986 alu.src[0] = r600_src[0];
1987 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1988 alu.src[1] = r600_src[1];
1989 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1990 alu.src[2].sel = ctx->temp_reg;
1991 alu.src[2].chan = i;
1992 alu.dst.sel = ctx->temp_reg;
1993 alu.dst.chan = i;
1994 if (i == 3) {
1995 alu.last = 1;
1996 }
1997 r = r600_bc_add_alu(ctx->bc, &alu);
1998 if (r)
1999 return r;
2000 }
2001 return tgsi_helper_copy(ctx, inst);
2002 }
2003
2004 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2005 {
2006 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2007 struct r600_bc_alu_src r600_src[3];
2008 struct r600_bc_alu alu;
2009 int use_temp = 0;
2010 int i, r;
2011
2012 r = tgsi_split_constant(ctx, r600_src);
2013 if (r)
2014 return r;
2015 r = tgsi_split_literal_constant(ctx, r600_src);
2016 if (r)
2017 return r;
2018
2019 if (inst->Dst[0].Register.WriteMask != 0xf)
2020 use_temp = 1;
2021
2022 for (i = 0; i < 4; i++) {
2023 memset(&alu, 0, sizeof(struct r600_bc_alu));
2024 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2025 alu.src[0] = r600_src[0];
2026 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2027
2028 alu.src[1] = r600_src[2];
2029 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2030
2031 alu.src[2] = r600_src[1];
2032 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2033
2034 if (use_temp)
2035 alu.dst.sel = ctx->temp_reg;
2036 else {
2037 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2038 if (r)
2039 return r;
2040 }
2041 alu.dst.chan = i;
2042 alu.dst.write = 1;
2043 alu.is_op3 = 1;
2044 if (i == 3)
2045 alu.last = 1;
2046 r = r600_bc_add_alu(ctx->bc, &alu);
2047 if (r)
2048 return r;
2049 }
2050 if (use_temp)
2051 return tgsi_helper_copy(ctx, inst);
2052 return 0;
2053 }
2054
2055 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2056 {
2057 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2058 struct r600_bc_alu_src r600_src[3];
2059 struct r600_bc_alu alu;
2060 uint32_t use_temp = 0;
2061 int i, r;
2062
2063 if (inst->Dst[0].Register.WriteMask != 0xf)
2064 use_temp = 1;
2065
2066 r = tgsi_split_constant(ctx, r600_src);
2067 if (r)
2068 return r;
2069 r = tgsi_split_literal_constant(ctx, r600_src);
2070 if (r)
2071 return r;
2072
2073 for (i = 0; i < 4; i++) {
2074 memset(&alu, 0, sizeof(struct r600_bc_alu));
2075 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2076
2077 alu.src[0] = r600_src[0];
2078 switch (i) {
2079 case 0:
2080 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2081 break;
2082 case 1:
2083 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2084 break;
2085 case 2:
2086 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2087 break;
2088 case 3:
2089 alu.src[0].sel = V_SQ_ALU_SRC_0;
2090 alu.src[0].chan = i;
2091 }
2092
2093 alu.src[1] = r600_src[1];
2094 switch (i) {
2095 case 0:
2096 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2097 break;
2098 case 1:
2099 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2100 break;
2101 case 2:
2102 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2103 break;
2104 case 3:
2105 alu.src[1].sel = V_SQ_ALU_SRC_0;
2106 alu.src[1].chan = i;
2107 }
2108
2109 alu.dst.sel = ctx->temp_reg;
2110 alu.dst.chan = i;
2111 alu.dst.write = 1;
2112
2113 if (i == 3)
2114 alu.last = 1;
2115 r = r600_bc_add_alu(ctx->bc, &alu);
2116 if (r)
2117 return r;
2118
2119 r = r600_bc_add_literal(ctx->bc, ctx->value);
2120 if (r)
2121 return r;
2122 }
2123
2124 for (i = 0; i < 4; i++) {
2125 memset(&alu, 0, sizeof(struct r600_bc_alu));
2126 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2127
2128 alu.src[0] = r600_src[0];
2129 switch (i) {
2130 case 0:
2131 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2132 break;
2133 case 1:
2134 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2135 break;
2136 case 2:
2137 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2138 break;
2139 case 3:
2140 alu.src[0].sel = V_SQ_ALU_SRC_0;
2141 alu.src[0].chan = i;
2142 }
2143
2144 alu.src[1] = r600_src[1];
2145 switch (i) {
2146 case 0:
2147 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2148 break;
2149 case 1:
2150 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2151 break;
2152 case 2:
2153 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2154 break;
2155 case 3:
2156 alu.src[1].sel = V_SQ_ALU_SRC_0;
2157 alu.src[1].chan = i;
2158 }
2159
2160 alu.src[2].sel = ctx->temp_reg;
2161 alu.src[2].neg = 1;
2162 alu.src[2].chan = i;
2163
2164 if (use_temp)
2165 alu.dst.sel = ctx->temp_reg;
2166 else {
2167 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2168 if (r)
2169 return r;
2170 }
2171 alu.dst.chan = i;
2172 alu.dst.write = 1;
2173 alu.is_op3 = 1;
2174 if (i == 3)
2175 alu.last = 1;
2176 r = r600_bc_add_alu(ctx->bc, &alu);
2177 if (r)
2178 return r;
2179
2180 r = r600_bc_add_literal(ctx->bc, ctx->value);
2181 if (r)
2182 return r;
2183 }
2184 if (use_temp)
2185 return tgsi_helper_copy(ctx, inst);
2186 return 0;
2187 }
2188
2189 static int tgsi_exp(struct r600_shader_ctx *ctx)
2190 {
2191 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2192 struct r600_bc_alu_src r600_src[3];
2193 struct r600_bc_alu alu;
2194 int r;
2195
2196 /* result.x = 2^floor(src); */
2197 if (inst->Dst[0].Register.WriteMask & 1) {
2198 memset(&alu, 0, sizeof(struct r600_bc_alu));
2199
2200 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2201 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2202 if (r)
2203 return r;
2204
2205 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2206
2207 alu.dst.sel = ctx->temp_reg;
2208 alu.dst.chan = 0;
2209 alu.dst.write = 1;
2210 alu.last = 1;
2211 r = r600_bc_add_alu(ctx->bc, &alu);
2212 if (r)
2213 return r;
2214
2215 r = r600_bc_add_literal(ctx->bc, ctx->value);
2216 if (r)
2217 return r;
2218
2219 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2220 alu.src[0].sel = ctx->temp_reg;
2221 alu.src[0].chan = 0;
2222
2223 alu.dst.sel = ctx->temp_reg;
2224 alu.dst.chan = 0;
2225 alu.dst.write = 1;
2226 alu.last = 1;
2227 r = r600_bc_add_alu(ctx->bc, &alu);
2228 if (r)
2229 return r;
2230
2231 r = r600_bc_add_literal(ctx->bc, ctx->value);
2232 if (r)
2233 return r;
2234 }
2235
2236 /* result.y = tmp - floor(tmp); */
2237 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2238 memset(&alu, 0, sizeof(struct r600_bc_alu));
2239
2240 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2241 alu.src[0] = r600_src[0];
2242 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2243 if (r)
2244 return r;
2245 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2246
2247 alu.dst.sel = ctx->temp_reg;
2248 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2249 // if (r)
2250 // return r;
2251 alu.dst.write = 1;
2252 alu.dst.chan = 1;
2253
2254 alu.last = 1;
2255
2256 r = r600_bc_add_alu(ctx->bc, &alu);
2257 if (r)
2258 return r;
2259 r = r600_bc_add_literal(ctx->bc, ctx->value);
2260 if (r)
2261 return r;
2262 }
2263
2264 /* result.z = RoughApprox2ToX(tmp);*/
2265 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2266 memset(&alu, 0, sizeof(struct r600_bc_alu));
2267 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2268 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2269 if (r)
2270 return r;
2271 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2272
2273 alu.dst.sel = ctx->temp_reg;
2274 alu.dst.write = 1;
2275 alu.dst.chan = 2;
2276
2277 alu.last = 1;
2278
2279 r = r600_bc_add_alu(ctx->bc, &alu);
2280 if (r)
2281 return r;
2282 r = r600_bc_add_literal(ctx->bc, ctx->value);
2283 if (r)
2284 return r;
2285 }
2286
2287 /* result.w = 1.0;*/
2288 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2289 memset(&alu, 0, sizeof(struct r600_bc_alu));
2290
2291 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2292 alu.src[0].sel = V_SQ_ALU_SRC_1;
2293 alu.src[0].chan = 0;
2294
2295 alu.dst.sel = ctx->temp_reg;
2296 alu.dst.chan = 3;
2297 alu.dst.write = 1;
2298 alu.last = 1;
2299 r = r600_bc_add_alu(ctx->bc, &alu);
2300 if (r)
2301 return r;
2302 r = r600_bc_add_literal(ctx->bc, ctx->value);
2303 if (r)
2304 return r;
2305 }
2306 return tgsi_helper_copy(ctx, inst);
2307 }
2308
2309 static int tgsi_log(struct r600_shader_ctx *ctx)
2310 {
2311 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2312 struct r600_bc_alu alu;
2313 int r;
2314
2315 /* result.x = floor(log2(src)); */
2316 if (inst->Dst[0].Register.WriteMask & 1) {
2317 memset(&alu, 0, sizeof(struct r600_bc_alu));
2318
2319 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2320 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2321 if (r)
2322 return r;
2323
2324 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2325
2326 alu.dst.sel = ctx->temp_reg;
2327 alu.dst.chan = 0;
2328 alu.dst.write = 1;
2329 alu.last = 1;
2330 r = r600_bc_add_alu(ctx->bc, &alu);
2331 if (r)
2332 return r;
2333
2334 r = r600_bc_add_literal(ctx->bc, ctx->value);
2335 if (r)
2336 return r;
2337
2338 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2339 alu.src[0].sel = ctx->temp_reg;
2340 alu.src[0].chan = 0;
2341
2342 alu.dst.sel = ctx->temp_reg;
2343 alu.dst.chan = 0;
2344 alu.dst.write = 1;
2345 alu.last = 1;
2346
2347 r = r600_bc_add_alu(ctx->bc, &alu);
2348 if (r)
2349 return r;
2350
2351 r = r600_bc_add_literal(ctx->bc, ctx->value);
2352 if (r)
2353 return r;
2354 }
2355
2356 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2357 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2358 memset(&alu, 0, sizeof(struct r600_bc_alu));
2359
2360 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2361 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2362 if (r)
2363 return r;
2364
2365 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2366
2367 alu.dst.sel = ctx->temp_reg;
2368 alu.dst.chan = 1;
2369 alu.dst.write = 1;
2370 alu.last = 1;
2371
2372 r = r600_bc_add_alu(ctx->bc, &alu);
2373 if (r)
2374 return r;
2375
2376 r = r600_bc_add_literal(ctx->bc, ctx->value);
2377 if (r)
2378 return r;
2379
2380 memset(&alu, 0, sizeof(struct r600_bc_alu));
2381
2382 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2383 alu.src[0].sel = ctx->temp_reg;
2384 alu.src[0].chan = 1;
2385
2386 alu.dst.sel = ctx->temp_reg;
2387 alu.dst.chan = 1;
2388 alu.dst.write = 1;
2389 alu.last = 1;
2390
2391 r = r600_bc_add_alu(ctx->bc, &alu);
2392 if (r)
2393 return r;
2394
2395 r = r600_bc_add_literal(ctx->bc, ctx->value);
2396 if (r)
2397 return r;
2398
2399 memset(&alu, 0, sizeof(struct r600_bc_alu));
2400
2401 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2402 alu.src[0].sel = ctx->temp_reg;
2403 alu.src[0].chan = 1;
2404
2405 alu.dst.sel = ctx->temp_reg;
2406 alu.dst.chan = 1;
2407 alu.dst.write = 1;
2408 alu.last = 1;
2409
2410 r = r600_bc_add_alu(ctx->bc, &alu);
2411 if (r)
2412 return r;
2413
2414 r = r600_bc_add_literal(ctx->bc, ctx->value);
2415 if (r)
2416 return r;
2417
2418 memset(&alu, 0, sizeof(struct r600_bc_alu));
2419
2420 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2421 alu.src[0].sel = ctx->temp_reg;
2422 alu.src[0].chan = 1;
2423
2424 alu.dst.sel = ctx->temp_reg;
2425 alu.dst.chan = 1;
2426 alu.dst.write = 1;
2427 alu.last = 1;
2428
2429 r = r600_bc_add_alu(ctx->bc, &alu);
2430 if (r)
2431 return r;
2432
2433 r = r600_bc_add_literal(ctx->bc, ctx->value);
2434 if (r)
2435 return r;
2436
2437 memset(&alu, 0, sizeof(struct r600_bc_alu));
2438
2439 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2440
2441 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2442 if (r)
2443 return r;
2444
2445 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2446
2447 alu.src[1].sel = ctx->temp_reg;
2448 alu.src[1].chan = 1;
2449
2450 alu.dst.sel = ctx->temp_reg;
2451 alu.dst.chan = 1;
2452 alu.dst.write = 1;
2453 alu.last = 1;
2454
2455 r = r600_bc_add_alu(ctx->bc, &alu);
2456 if (r)
2457 return r;
2458
2459 r = r600_bc_add_literal(ctx->bc, ctx->value);
2460 if (r)
2461 return r;
2462 }
2463
2464 /* result.z = log2(src);*/
2465 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2466 memset(&alu, 0, sizeof(struct r600_bc_alu));
2467
2468 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2469 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2470 if (r)
2471 return r;
2472
2473 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2474
2475 alu.dst.sel = ctx->temp_reg;
2476 alu.dst.write = 1;
2477 alu.dst.chan = 2;
2478 alu.last = 1;
2479
2480 r = r600_bc_add_alu(ctx->bc, &alu);
2481 if (r)
2482 return r;
2483
2484 r = r600_bc_add_literal(ctx->bc, ctx->value);
2485 if (r)
2486 return r;
2487 }
2488
2489 /* result.w = 1.0; */
2490 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2491 memset(&alu, 0, sizeof(struct r600_bc_alu));
2492
2493 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2494 alu.src[0].sel = V_SQ_ALU_SRC_1;
2495 alu.src[0].chan = 0;
2496
2497 alu.dst.sel = ctx->temp_reg;
2498 alu.dst.chan = 3;
2499 alu.dst.write = 1;
2500 alu.last = 1;
2501
2502 r = r600_bc_add_alu(ctx->bc, &alu);
2503 if (r)
2504 return r;
2505
2506 r = r600_bc_add_literal(ctx->bc, ctx->value);
2507 if (r)
2508 return r;
2509 }
2510
2511 return tgsi_helper_copy(ctx, inst);
2512 }
2513
2514 /* r6/7 only for now */
2515 static int tgsi_arl(struct r600_shader_ctx *ctx)
2516 {
2517 /* TODO from r600c, ar values don't persist between clauses */
2518 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2519 struct r600_bc_alu alu;
2520 int r;
2521 memset(&alu, 0, sizeof(struct r600_bc_alu));
2522
2523 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2524
2525 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2526 if (r)
2527 return r;
2528 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2529
2530 alu.last = 1;
2531
2532 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2533 if (r)
2534 return r;
2535 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2536 return 0;
2537 }
2538
2539 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2540 {
2541 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2542 struct r600_bc_alu alu;
2543 int i, r = 0;
2544
2545 for (i = 0; i < 4; i++) {
2546 memset(&alu, 0, sizeof(struct r600_bc_alu));
2547
2548 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2549 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2550 if (r)
2551 return r;
2552
2553 if (i == 0 || i == 3) {
2554 alu.src[0].sel = V_SQ_ALU_SRC_1;
2555 } else {
2556 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2557 if (r)
2558 return r;
2559 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2560 }
2561
2562 if (i == 0 || i == 2) {
2563 alu.src[1].sel = V_SQ_ALU_SRC_1;
2564 } else {
2565 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2566 if (r)
2567 return r;
2568 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2569 }
2570 if (i == 3)
2571 alu.last = 1;
2572 r = r600_bc_add_alu(ctx->bc, &alu);
2573 if (r)
2574 return r;
2575 }
2576 return 0;
2577 }
2578
2579 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2580 {
2581 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2582 struct r600_bc_alu alu;
2583 int r;
2584
2585 memset(&alu, 0, sizeof(struct r600_bc_alu));
2586 alu.inst = opcode;
2587 alu.predicate = 1;
2588
2589 alu.dst.sel = ctx->temp_reg;
2590 alu.dst.write = 1;
2591 alu.dst.chan = 0;
2592
2593 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2594 if (r)
2595 return r;
2596 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2597 alu.src[1].sel = V_SQ_ALU_SRC_0;
2598 alu.src[1].chan = 0;
2599
2600 alu.last = 1;
2601
2602 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2603 if (r)
2604 return r;
2605 return 0;
2606 }
2607
2608 static int pops(struct r600_shader_ctx *ctx, int pops)
2609 {
2610 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2611 ctx->bc->cf_last->pop_count = pops;
2612 return 0;
2613 }
2614
2615 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2616 {
2617 switch(reason) {
2618 case FC_PUSH_VPM:
2619 ctx->bc->callstack[ctx->bc->call_sp].current--;
2620 break;
2621 case FC_PUSH_WQM:
2622 case FC_LOOP:
2623 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2624 break;
2625 case FC_REP:
2626 /* TOODO : for 16 vp asic should -= 2; */
2627 ctx->bc->callstack[ctx->bc->call_sp].current --;
2628 break;
2629 }
2630 }
2631
2632 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2633 {
2634 if (check_max_only) {
2635 int diff;
2636 switch (reason) {
2637 case FC_PUSH_VPM:
2638 diff = 1;
2639 break;
2640 case FC_PUSH_WQM:
2641 diff = 4;
2642 break;
2643 default:
2644 assert(0);
2645 diff = 0;
2646 }
2647 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2648 ctx->bc->callstack[ctx->bc->call_sp].max) {
2649 ctx->bc->callstack[ctx->bc->call_sp].max =
2650 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2651 }
2652 return;
2653 }
2654 switch (reason) {
2655 case FC_PUSH_VPM:
2656 ctx->bc->callstack[ctx->bc->call_sp].current++;
2657 break;
2658 case FC_PUSH_WQM:
2659 case FC_LOOP:
2660 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2661 break;
2662 case FC_REP:
2663 ctx->bc->callstack[ctx->bc->call_sp].current++;
2664 break;
2665 }
2666
2667 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2668 ctx->bc->callstack[ctx->bc->call_sp].max) {
2669 ctx->bc->callstack[ctx->bc->call_sp].max =
2670 ctx->bc->callstack[ctx->bc->call_sp].current;
2671 }
2672 }
2673
2674 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2675 {
2676 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2677
2678 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2679 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2680 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2681 sp->num_mid++;
2682 }
2683
2684 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2685 {
2686 ctx->bc->fc_sp++;
2687 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2688 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2689 }
2690
2691 static void fc_poplevel(struct r600_shader_ctx *ctx)
2692 {
2693 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2694 if (sp->mid) {
2695 free(sp->mid);
2696 sp->mid = NULL;
2697 }
2698 sp->num_mid = 0;
2699 sp->start = NULL;
2700 sp->type = 0;
2701 ctx->bc->fc_sp--;
2702 }
2703
2704 #if 0
2705 static int emit_return(struct r600_shader_ctx *ctx)
2706 {
2707 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2708 return 0;
2709 }
2710
2711 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2712 {
2713
2714 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2715 ctx->bc->cf_last->pop_count = pops;
2716 /* TODO work out offset */
2717 return 0;
2718 }
2719
2720 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2721 {
2722 return 0;
2723 }
2724
2725 static void emit_testflag(struct r600_shader_ctx *ctx)
2726 {
2727
2728 }
2729
2730 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2731 {
2732 emit_testflag(ctx);
2733 emit_jump_to_offset(ctx, 1, 4);
2734 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2735 pops(ctx, ifidx + 1);
2736 emit_return(ctx);
2737 }
2738
2739 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2740 {
2741 emit_testflag(ctx);
2742
2743 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2744 ctx->bc->cf_last->pop_count = 1;
2745
2746 fc_set_mid(ctx, fc_sp);
2747
2748 pops(ctx, 1);
2749 }
2750 #endif
2751
2752 static int tgsi_if(struct r600_shader_ctx *ctx)
2753 {
2754 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2755
2756 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2757
2758 fc_pushlevel(ctx, FC_IF);
2759
2760 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2761 return 0;
2762 }
2763
2764 static int tgsi_else(struct r600_shader_ctx *ctx)
2765 {
2766 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2767 ctx->bc->cf_last->pop_count = 1;
2768
2769 fc_set_mid(ctx, ctx->bc->fc_sp);
2770 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2771 return 0;
2772 }
2773
2774 static int tgsi_endif(struct r600_shader_ctx *ctx)
2775 {
2776 pops(ctx, 1);
2777 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2778 R600_ERR("if/endif unbalanced in shader\n");
2779 return -1;
2780 }
2781
2782 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2783 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2784 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2785 } else {
2786 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2787 }
2788 fc_poplevel(ctx);
2789
2790 callstack_decrease_current(ctx, FC_PUSH_VPM);
2791 return 0;
2792 }
2793
2794 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2795 {
2796 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2797
2798 fc_pushlevel(ctx, FC_LOOP);
2799
2800 /* check stack depth */
2801 callstack_check_depth(ctx, FC_LOOP, 0);
2802 return 0;
2803 }
2804
2805 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2806 {
2807 int i;
2808
2809 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2810
2811 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2812 R600_ERR("loop/endloop in shader code are not paired.\n");
2813 return -EINVAL;
2814 }
2815
2816 /* fixup loop pointers - from r600isa
2817 LOOP END points to CF after LOOP START,
2818 LOOP START point to CF after LOOP END
2819 BRK/CONT point to LOOP END CF
2820 */
2821 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2822
2823 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2824
2825 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2826 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2827 }
2828 /* TODO add LOOPRET support */
2829 fc_poplevel(ctx);
2830 callstack_decrease_current(ctx, FC_LOOP);
2831 return 0;
2832 }
2833
2834 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2835 {
2836 unsigned int fscp;
2837
2838 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2839 {
2840 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2841 break;
2842 }
2843
2844 if (fscp == 0) {
2845 R600_ERR("Break not inside loop/endloop pair\n");
2846 return -EINVAL;
2847 }
2848
2849 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2850 ctx->bc->cf_last->pop_count = 1;
2851
2852 fc_set_mid(ctx, fscp);
2853
2854 pops(ctx, 1);
2855 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2856 return 0;
2857 }
2858
2859 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2860 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2861 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2862 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2863
2864 /* FIXME:
2865 * For state trackers other than OpenGL, we'll want to use
2866 * _RECIP_IEEE instead.
2867 */
2868 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2869
2870 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2871 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2872 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2873 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2874 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2875 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2876 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2877 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2878 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2879 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2880 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2881 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2882 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2883 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2884 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2885 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2886 /* gap */
2887 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2888 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2889 /* gap */
2890 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2891 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2892 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2893 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2894 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2895 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2896 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2897 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2898 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2899 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2900 /* gap */
2901 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2902 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2903 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2904 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2905 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2906 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2907 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2908 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2909 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2910 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2911 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2912 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2914 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2915 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2917 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2918 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2919 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2920 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2921 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2922 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2924 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2926 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2927 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2932 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2934 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2935 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2936 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2937 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2938 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2941 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2942 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2943 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2944 /* gap */
2945 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2948 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2949 /* gap */
2950 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2955 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2957 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2958 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 /* gap */
2960 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2961 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2968 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2969 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2972 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2974 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 /* gap */
2976 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 /* gap */
2982 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2991 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2992 /* gap */
2993 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3010 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3015 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 };
3022
3023 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3024 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3026 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3027 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3028 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3029 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3030 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3032 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3033 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3034 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3035 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3036 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3037 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3038 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3039 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3040 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3041 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3042 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3043 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3044 /* gap */
3045 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 /* gap */
3048 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3049 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3051 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3053 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3055 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3056 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3057 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3058 /* gap */
3059 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3061 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3063 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3064 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3065 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3066 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3067 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3069 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3073 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3075 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3076 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3077 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3078 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3079 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3080 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3082 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3092 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3093 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3094 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3095 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3096 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3099 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3100 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3101 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3102 /* gap */
3103 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3106 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3107 /* gap */
3108 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3113 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3115 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3116 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 /* gap */
3118 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3127 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3130 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3132 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 /* gap */
3134 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 /* gap */
3140 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3143 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3147 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3149 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3150 /* gap */
3151 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3153 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3154 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3156 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3157 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3158 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3159 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3160 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3161 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3162 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3163 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3164 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3166 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3167 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3168 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3169 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3170 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3171 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3172 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3173 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3174 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3176 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3177 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3178 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3179 };