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r600g: Store literal values in the r600_bc_alu_src structure.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
49 */
50 for (i = 0; i < 10; i++) {
51 spi_vs_out_id[i] = 0;
52 }
53 for (i = 0; i < 32; i++) {
54 tmp = i << ((i & 3) * 8);
55 spi_vs_out_id[i / 4] |= tmp;
56 }
57 for (i = 0; i < 10; i++) {
58 r600_pipe_state_add_reg(rstate,
59 R_028614_SPI_VS_OUT_ID_0 + i * 4,
60 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
61 }
62
63 r600_pipe_state_add_reg(rstate,
64 R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
66 0xFFFFFFFF, NULL);
67 r600_pipe_state_add_reg(rstate,
68 R_028868_SQ_PGM_RESOURCES_VS,
69 S_028868_NUM_GPRS(rshader->bc.ngpr) |
70 S_028868_STACK_SIZE(rshader->bc.nstack),
71 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_028858_SQ_PGM_START_VS,
77 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
78
79 r600_pipe_state_add_reg(rstate,
80 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
81 0xFFFFFFFF, NULL);
82
83 }
84
85 int r600_find_vs_semantic_index(struct r600_shader *vs,
86 struct r600_shader *ps, int id)
87 {
88 struct r600_shader_io *input = &ps->input[id];
89
90 for (int i = 0; i < vs->noutput; i++) {
91 if (input->name == vs->output[i].name &&
92 input->sid == vs->output[i].sid) {
93 return i - 1;
94 }
95 }
96 return 0;
97 }
98
99 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
100 {
101 struct r600_pipe_state *rstate = &shader->rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
104 int pos_index = -1, face_index = -1;
105
106 rstate->nregs = 0;
107
108 for (i = 0; i < rshader->ninput; i++) {
109 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
110 pos_index = i;
111 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
112 face_index = i;
113 }
114
115 for (i = 0; i < rshader->noutput; i++) {
116 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
117 r600_pipe_state_add_reg(rstate,
118 R_02880C_DB_SHADER_CONTROL,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL);
121 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
122 r600_pipe_state_add_reg(rstate,
123 R_02880C_DB_SHADER_CONTROL,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
126 }
127
128 exports_ps = 0;
129 num_cout = 0;
130 for (i = 0; i < rshader->noutput; i++) {
131 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
132 exports_ps |= 1;
133 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
134 num_cout++;
135 }
136 }
137 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
138 if (!exports_ps) {
139 /* always at least export 1 component per pixel */
140 exports_ps = 2;
141 }
142
143 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
145 spi_input_z = 0;
146 if (pos_index != -1) {
147 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
149 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
151 spi_input_z |= 1;
152 }
153
154 spi_ps_in_control_1 = 0;
155 if (face_index != -1) {
156 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
158 }
159
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->fs_write_all) {
179 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
180 S_028808_MULTIWRITE_ENABLE(1),
181 S_028808_MULTIWRITE_ENABLE(1),
182 NULL);
183 }
184
185 if (rshader->uses_kill) {
186 /* only set some bits here, the other bits are set in the dsa state */
187 r600_pipe_state_add_reg(rstate,
188 R_02880C_DB_SHADER_CONTROL,
189 S_02880C_KILL_ENABLE(1),
190 S_02880C_KILL_ENABLE(1), NULL);
191 }
192 r600_pipe_state_add_reg(rstate,
193 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
194 0xFFFFFFFF, NULL);
195 }
196
197 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
198 {
199 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
200 struct r600_shader *rshader = &shader->shader;
201 void *ptr;
202
203 /* copy new shader */
204 if (shader->bo == NULL) {
205 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
206 if (shader->bo == NULL) {
207 return -ENOMEM;
208 }
209 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
210 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
211 r600_bo_unmap(rctx->radeon, shader->bo);
212 }
213 /* build state */
214 switch (rshader->processor_type) {
215 case TGSI_PROCESSOR_VERTEX:
216 if (rshader->family >= CHIP_CEDAR) {
217 evergreen_pipe_shader_vs(ctx, shader);
218 } else {
219 r600_pipe_shader_vs(ctx, shader);
220 }
221 break;
222 case TGSI_PROCESSOR_FRAGMENT:
223 if (rshader->family >= CHIP_CEDAR) {
224 evergreen_pipe_shader_ps(ctx, shader);
225 } else {
226 r600_pipe_shader_ps(ctx, shader);
227 }
228 break;
229 default:
230 return -EINVAL;
231 }
232 return 0;
233 }
234
235 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
236
237 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
238 {
239 static int dump_shaders = -1;
240 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
241 int r;
242
243 /* Would like some magic "get_bool_option_once" routine.
244 */
245 if (dump_shaders == -1)
246 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
247
248 if (dump_shaders) {
249 fprintf(stderr, "--------------------------------------------------------------\n");
250 tgsi_dump(tokens, 0);
251 }
252 shader->shader.family = r600_get_family(rctx->radeon);
253 r = r600_shader_from_tgsi(tokens, &shader->shader);
254 if (r) {
255 R600_ERR("translation from TGSI failed !\n");
256 return r;
257 }
258 r = r600_bc_build(&shader->shader.bc);
259 if (r) {
260 R600_ERR("building bytecode failed !\n");
261 return r;
262 }
263 if (dump_shaders) {
264 r600_bc_dump(&shader->shader.bc);
265 fprintf(stderr, "______________________________________________________________\n");
266 }
267 return r600_pipe_shader(ctx, shader);
268 }
269
270 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
271 {
272 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
273
274 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
275 r600_bc_clear(&shader->shader.bc);
276 }
277
278 /*
279 * tgsi -> r600 shader
280 */
281 struct r600_shader_tgsi_instruction;
282
283 struct r600_shader_ctx {
284 struct tgsi_shader_info info;
285 struct tgsi_parse_context parse;
286 const struct tgsi_token *tokens;
287 unsigned type;
288 unsigned file_offset[TGSI_FILE_COUNT];
289 unsigned temp_reg;
290 struct r600_shader_tgsi_instruction *inst_info;
291 struct r600_bc *bc;
292 struct r600_shader *shader;
293 u32 *literals;
294 u32 nliterals;
295 u32 max_driver_temp_used;
296 /* needed for evergreen interpolation */
297 boolean input_centroid;
298 boolean input_linear;
299 boolean input_perspective;
300 int num_interp_gpr;
301 };
302
303 struct r600_shader_tgsi_instruction {
304 unsigned tgsi_opcode;
305 unsigned is_op3;
306 unsigned r600_opcode;
307 int (*process)(struct r600_shader_ctx *ctx);
308 };
309
310 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
311 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
312
313 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
314 {
315 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
316 int j;
317
318 if (i->Instruction.NumDstRegs > 1) {
319 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
320 return -EINVAL;
321 }
322 if (i->Instruction.Predicate) {
323 R600_ERR("predicate unsupported\n");
324 return -EINVAL;
325 }
326 #if 0
327 if (i->Instruction.Label) {
328 R600_ERR("label unsupported\n");
329 return -EINVAL;
330 }
331 #endif
332 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
333 if (i->Src[j].Register.Dimension) {
334 R600_ERR("unsupported src %d (dimension %d)\n", j,
335 i->Src[j].Register.Dimension);
336 return -EINVAL;
337 }
338 }
339 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
340 if (i->Dst[j].Register.Dimension) {
341 R600_ERR("unsupported dst (dimension)\n");
342 return -EINVAL;
343 }
344 }
345 return 0;
346 }
347
348 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
349 {
350 int i, r;
351 struct r600_bc_alu alu;
352 int gpr = 0, base_chan = 0;
353 int ij_index = 0;
354
355 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
356 ij_index = 0;
357 if (ctx->shader->input[input].centroid)
358 ij_index++;
359 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
360 ij_index = 0;
361 /* if we have perspective add one */
362 if (ctx->input_perspective) {
363 ij_index++;
364 /* if we have perspective centroid */
365 if (ctx->input_centroid)
366 ij_index++;
367 }
368 if (ctx->shader->input[input].centroid)
369 ij_index++;
370 }
371
372 /* work out gpr and base_chan from index */
373 gpr = ij_index / 2;
374 base_chan = (2 * (ij_index % 2)) + 1;
375
376 for (i = 0; i < 8; i++) {
377 memset(&alu, 0, sizeof(struct r600_bc_alu));
378
379 if (i < 4)
380 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
381 else
382 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
383
384 if ((i > 1) && (i < 6)) {
385 alu.dst.sel = ctx->shader->input[input].gpr;
386 alu.dst.write = 1;
387 }
388
389 alu.dst.chan = i % 4;
390
391 alu.src[0].sel = gpr;
392 alu.src[0].chan = (base_chan - (i % 2));
393
394 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
395
396 alu.bank_swizzle_force = SQ_ALU_VEC_210;
397 if ((i % 4) == 3)
398 alu.last = 1;
399 r = r600_bc_add_alu(ctx->bc, &alu);
400 if (r)
401 return r;
402 }
403 return 0;
404 }
405
406
407 static int tgsi_declaration(struct r600_shader_ctx *ctx)
408 {
409 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
410 unsigned i;
411
412 switch (d->Declaration.File) {
413 case TGSI_FILE_INPUT:
414 i = ctx->shader->ninput++;
415 ctx->shader->input[i].name = d->Semantic.Name;
416 ctx->shader->input[i].sid = d->Semantic.Index;
417 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
418 ctx->shader->input[i].centroid = d->Declaration.Centroid;
419 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
420 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
421 /* turn input into interpolate on EG */
422 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
423 if (ctx->shader->input[i].interpolate > 0) {
424 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
425 evergreen_interp_alu(ctx, i);
426 }
427 }
428 }
429 break;
430 case TGSI_FILE_OUTPUT:
431 i = ctx->shader->noutput++;
432 ctx->shader->output[i].name = d->Semantic.Name;
433 ctx->shader->output[i].sid = d->Semantic.Index;
434 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
435 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
436 break;
437 case TGSI_FILE_CONSTANT:
438 case TGSI_FILE_TEMPORARY:
439 case TGSI_FILE_SAMPLER:
440 case TGSI_FILE_ADDRESS:
441 break;
442 default:
443 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
444 return -EINVAL;
445 }
446 return 0;
447 }
448
449 static int r600_get_temp(struct r600_shader_ctx *ctx)
450 {
451 return ctx->temp_reg + ctx->max_driver_temp_used++;
452 }
453
454 /*
455 * for evergreen we need to scan the shader to find the number of GPRs we need to
456 * reserve for interpolation.
457 *
458 * we need to know if we are going to emit
459 * any centroid inputs
460 * if perspective and linear are required
461 */
462 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
463 {
464 int i;
465 int num_baryc;
466
467 ctx->input_linear = FALSE;
468 ctx->input_perspective = FALSE;
469 ctx->input_centroid = FALSE;
470 ctx->num_interp_gpr = 1;
471
472 /* any centroid inputs */
473 for (i = 0; i < ctx->info.num_inputs; i++) {
474 /* skip position/face */
475 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
476 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
477 continue;
478 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
479 ctx->input_linear = TRUE;
480 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
481 ctx->input_perspective = TRUE;
482 if (ctx->info.input_centroid[i])
483 ctx->input_centroid = TRUE;
484 }
485
486 num_baryc = 0;
487 /* ignoring sample for now */
488 if (ctx->input_perspective)
489 num_baryc++;
490 if (ctx->input_linear)
491 num_baryc++;
492 if (ctx->input_centroid)
493 num_baryc *= 2;
494
495 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
496
497 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
498 return ctx->num_interp_gpr;
499 }
500
501 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
502 {
503 struct tgsi_full_immediate *immediate;
504 struct tgsi_full_property *property;
505 struct r600_shader_ctx ctx;
506 struct r600_bc_output output[32];
507 unsigned output_done, noutput;
508 unsigned opcode;
509 int i, r = 0, pos0;
510
511 ctx.bc = &shader->bc;
512 ctx.shader = shader;
513 r = r600_bc_init(ctx.bc, shader->family);
514 if (r)
515 return r;
516 ctx.tokens = tokens;
517 tgsi_scan_shader(tokens, &ctx.info);
518 tgsi_parse_init(&ctx.parse, tokens);
519 ctx.type = ctx.parse.FullHeader.Processor.Processor;
520 shader->processor_type = ctx.type;
521 ctx.bc->type = shader->processor_type;
522
523 /* register allocations */
524 /* Values [0,127] correspond to GPR[0..127].
525 * Values [128,159] correspond to constant buffer bank 0
526 * Values [160,191] correspond to constant buffer bank 1
527 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
528 * Values [256,287] correspond to constant buffer bank 2 (EG)
529 * Values [288,319] correspond to constant buffer bank 3 (EG)
530 * Other special values are shown in the list below.
531 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
532 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
533 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
534 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
535 * 248 SQ_ALU_SRC_0: special constant 0.0.
536 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
537 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
538 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
539 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
540 * 253 SQ_ALU_SRC_LITERAL: literal constant.
541 * 254 SQ_ALU_SRC_PV: previous vector result.
542 * 255 SQ_ALU_SRC_PS: previous scalar result.
543 */
544 for (i = 0; i < TGSI_FILE_COUNT; i++) {
545 ctx.file_offset[i] = 0;
546 }
547 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
548 ctx.file_offset[TGSI_FILE_INPUT] = 1;
549 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
550 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
551 } else {
552 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
553 }
554 }
555 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
556 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
557 }
558 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
559 ctx.info.file_count[TGSI_FILE_INPUT];
560 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
561 ctx.info.file_count[TGSI_FILE_OUTPUT];
562
563 /* Outside the GPR range. This will be translated to one of the
564 * kcache banks later. */
565 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
566
567 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
568 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
569 ctx.info.file_count[TGSI_FILE_TEMPORARY];
570
571 ctx.nliterals = 0;
572 ctx.literals = NULL;
573 shader->fs_write_all = FALSE;
574 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
575 tgsi_parse_token(&ctx.parse);
576 switch (ctx.parse.FullToken.Token.Type) {
577 case TGSI_TOKEN_TYPE_IMMEDIATE:
578 immediate = &ctx.parse.FullToken.FullImmediate;
579 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
580 if(ctx.literals == NULL) {
581 r = -ENOMEM;
582 goto out_err;
583 }
584 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
585 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
586 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
587 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
588 ctx.nliterals++;
589 break;
590 case TGSI_TOKEN_TYPE_DECLARATION:
591 r = tgsi_declaration(&ctx);
592 if (r)
593 goto out_err;
594 break;
595 case TGSI_TOKEN_TYPE_INSTRUCTION:
596 r = tgsi_is_supported(&ctx);
597 if (r)
598 goto out_err;
599 ctx.max_driver_temp_used = 0;
600 /* reserve first tmp for everyone */
601 r600_get_temp(&ctx);
602 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
603 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
604 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
605 else
606 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
607 r = ctx.inst_info->process(&ctx);
608 if (r)
609 goto out_err;
610 break;
611 case TGSI_TOKEN_TYPE_PROPERTY:
612 property = &ctx.parse.FullToken.FullProperty;
613 if (property->Property.PropertyName == TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS) {
614 if (property->u[0].Data == 1)
615 shader->fs_write_all = TRUE;
616 }
617 break;
618 default:
619 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
620 r = -EINVAL;
621 goto out_err;
622 }
623 }
624 /* export output */
625 noutput = shader->noutput;
626 for (i = 0, pos0 = 0; i < noutput; i++) {
627 memset(&output[i], 0, sizeof(struct r600_bc_output));
628 output[i].gpr = shader->output[i].gpr;
629 output[i].elem_size = 3;
630 output[i].swizzle_x = 0;
631 output[i].swizzle_y = 1;
632 output[i].swizzle_z = 2;
633 output[i].swizzle_w = 3;
634 output[i].burst_count = 1;
635 output[i].barrier = 1;
636 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
637 output[i].array_base = i - pos0;
638 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
639 switch (ctx.type) {
640 case TGSI_PROCESSOR_VERTEX:
641 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
642 output[i].array_base = 60;
643 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
644 /* position doesn't count in array_base */
645 pos0++;
646 }
647 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
648 output[i].array_base = 61;
649 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
650 /* position doesn't count in array_base */
651 pos0++;
652 }
653 break;
654 case TGSI_PROCESSOR_FRAGMENT:
655 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
656 output[i].array_base = shader->output[i].sid;
657 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
658 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
659 output[i].array_base = 61;
660 output[i].swizzle_x = 2;
661 output[i].swizzle_y = 7;
662 output[i].swizzle_z = output[i].swizzle_w = 7;
663 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
664 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
665 output[i].array_base = 61;
666 output[i].swizzle_x = 7;
667 output[i].swizzle_y = 1;
668 output[i].swizzle_z = output[i].swizzle_w = 7;
669 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
670 } else {
671 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
672 r = -EINVAL;
673 goto out_err;
674 }
675 break;
676 default:
677 R600_ERR("unsupported processor type %d\n", ctx.type);
678 r = -EINVAL;
679 goto out_err;
680 }
681 }
682 /* add fake param output for vertex shader if no param is exported */
683 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
684 for (i = 0, pos0 = 0; i < noutput; i++) {
685 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
686 pos0 = 1;
687 break;
688 }
689 }
690 if (!pos0) {
691 memset(&output[i], 0, sizeof(struct r600_bc_output));
692 output[i].gpr = 0;
693 output[i].elem_size = 3;
694 output[i].swizzle_x = 0;
695 output[i].swizzle_y = 1;
696 output[i].swizzle_z = 2;
697 output[i].swizzle_w = 3;
698 output[i].burst_count = 1;
699 output[i].barrier = 1;
700 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
701 output[i].array_base = 0;
702 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
703 noutput++;
704 }
705 }
706 /* add fake pixel export */
707 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
708 memset(&output[0], 0, sizeof(struct r600_bc_output));
709 output[0].gpr = 0;
710 output[0].elem_size = 3;
711 output[0].swizzle_x = 7;
712 output[0].swizzle_y = 7;
713 output[0].swizzle_z = 7;
714 output[0].swizzle_w = 7;
715 output[0].burst_count = 1;
716 output[0].barrier = 1;
717 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
718 output[0].array_base = 0;
719 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
720 noutput++;
721 }
722 /* set export done on last export of each type */
723 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
724 if (i == (noutput - 1)) {
725 output[i].end_of_program = 1;
726 }
727 if (!(output_done & (1 << output[i].type))) {
728 output_done |= (1 << output[i].type);
729 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
730 }
731 }
732 /* add output to bytecode */
733 for (i = 0; i < noutput; i++) {
734 r = r600_bc_add_output(ctx.bc, &output[i]);
735 if (r)
736 goto out_err;
737 }
738 free(ctx.literals);
739 tgsi_parse_free(&ctx.parse);
740 return 0;
741 out_err:
742 free(ctx.literals);
743 tgsi_parse_free(&ctx.parse);
744 return r;
745 }
746
747 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
748 {
749 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
750 return -EINVAL;
751 }
752
753 static int tgsi_end(struct r600_shader_ctx *ctx)
754 {
755 return 0;
756 }
757
758 static void tgsi_src(struct r600_shader_ctx *ctx,
759 const struct tgsi_full_src_register *tgsi_src,
760 struct r600_bc_alu_src *r600_src)
761 {
762 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
763 r600_src->neg = tgsi_src->Register.Negate;
764 r600_src->abs = tgsi_src->Register.Absolute;
765 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
766 int index;
767 if((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
768 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
769 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
770
771 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
772 r600_bc_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
773 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
774 return;
775 }
776 index = tgsi_src->Register.Index;
777 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
778 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
779 } else {
780 if (tgsi_src->Register.Indirect)
781 r600_src->rel = V_SQ_REL_RELATIVE;
782 r600_src->sel = tgsi_src->Register.Index;
783 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
784 }
785 }
786
787 static void tgsi_dst(struct r600_shader_ctx *ctx,
788 const struct tgsi_full_dst_register *tgsi_dst,
789 unsigned swizzle,
790 struct r600_bc_alu_dst *r600_dst)
791 {
792 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
793
794 r600_dst->sel = tgsi_dst->Register.Index;
795 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
796 r600_dst->chan = swizzle;
797 r600_dst->write = 1;
798 if (tgsi_dst->Register.Indirect)
799 r600_dst->rel = V_SQ_REL_RELATIVE;
800 if (inst->Instruction.Saturate) {
801 r600_dst->clamp = 1;
802 }
803 }
804
805 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
806 {
807 switch (swizzle) {
808 case 0:
809 return tgsi_src->Register.SwizzleX;
810 case 1:
811 return tgsi_src->Register.SwizzleY;
812 case 2:
813 return tgsi_src->Register.SwizzleZ;
814 case 3:
815 return tgsi_src->Register.SwizzleW;
816 default:
817 return 0;
818 }
819 }
820
821 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
822 {
823 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
824 struct r600_bc_alu alu;
825 int i, j, k, nconst, r;
826
827 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
828 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
829 nconst++;
830 }
831 tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
832 }
833 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
834 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
835 int treg = r600_get_temp(ctx);
836 for (k = 0; k < 4; k++) {
837 memset(&alu, 0, sizeof(struct r600_bc_alu));
838 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
839 alu.src[0].sel = r600_src[i].sel;
840 alu.src[0].chan = k;
841 alu.src[0].rel = r600_src[i].rel;
842 alu.dst.sel = treg;
843 alu.dst.chan = k;
844 alu.dst.write = 1;
845 if (k == 3)
846 alu.last = 1;
847 r = r600_bc_add_alu(ctx->bc, &alu);
848 if (r)
849 return r;
850 }
851 r600_src[i].sel = treg;
852 r600_src[i].rel =0;
853 j--;
854 }
855 }
856 return 0;
857 }
858
859 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
860 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
861 {
862 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
863 struct r600_bc_alu alu;
864 int i, j, k, nliteral, r;
865
866 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
867 if (r600_src[i].sel == V_SQ_ALU_SRC_LITERAL) {
868 nliteral++;
869 }
870 }
871 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
872 if (j > 0 && r600_src[i].sel == V_SQ_ALU_SRC_LITERAL) {
873 int treg = r600_get_temp(ctx);
874 for (k = 0; k < 4; k++) {
875 memset(&alu, 0, sizeof(struct r600_bc_alu));
876 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
877 alu.src[0].sel = r600_src[i].sel;
878 alu.src[0].chan = k;
879 alu.src[0].value[k] = r600_src[i].value[k];
880 alu.dst.sel = treg;
881 alu.dst.chan = k;
882 alu.dst.write = 1;
883 if (k == 3)
884 alu.last = 1;
885 r = r600_bc_add_alu(ctx->bc, &alu);
886 if (r)
887 return r;
888 }
889 r600_src[i].sel = treg;
890 j--;
891 }
892 }
893 return 0;
894 }
895
896 static int tgsi_last_instruction(unsigned writemask)
897 {
898 int i, lasti = 0;
899
900 for (i = 0; i < 4; i++) {
901 if (writemask & (1 << i)) {
902 lasti = i;
903 }
904 }
905 return lasti;
906 }
907
908 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
909 {
910 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
911 struct r600_bc_alu_src r600_src[3];
912 struct r600_bc_alu alu;
913 int i, j, r;
914 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
915
916 r = tgsi_split_constant(ctx, r600_src);
917 if (r)
918 return r;
919 r = tgsi_split_literal_constant(ctx, r600_src);
920 if (r)
921 return r;
922 for (i = 0; i < lasti + 1; i++) {
923 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
924 continue;
925
926 memset(&alu, 0, sizeof(struct r600_bc_alu));
927 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
928
929 alu.inst = ctx->inst_info->r600_opcode;
930 if (!swap) {
931 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
932 alu.src[j] = r600_src[j];
933 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
934 }
935 } else {
936 alu.src[0] = r600_src[1];
937 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
938
939 alu.src[1] = r600_src[0];
940 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
941 }
942 /* handle some special cases */
943 switch (ctx->inst_info->tgsi_opcode) {
944 case TGSI_OPCODE_SUB:
945 alu.src[1].neg = 1;
946 break;
947 case TGSI_OPCODE_ABS:
948 alu.src[0].abs = 1;
949 break;
950 default:
951 break;
952 }
953 if (i == lasti) {
954 alu.last = 1;
955 }
956 r = r600_bc_add_alu(ctx->bc, &alu);
957 if (r)
958 return r;
959 }
960 return 0;
961 }
962
963 static int tgsi_op2(struct r600_shader_ctx *ctx)
964 {
965 return tgsi_op2_s(ctx, 0);
966 }
967
968 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
969 {
970 return tgsi_op2_s(ctx, 1);
971 }
972
973 /*
974 * r600 - trunc to -PI..PI range
975 * r700 - normalize by dividing by 2PI
976 * see fdo bug 27901
977 */
978 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
979 struct r600_bc_alu_src r600_src[3])
980 {
981 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
982 static float double_pi = 3.1415926535 * 2;
983 static float neg_pi = -3.1415926535;
984
985 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
986 int r;
987 struct r600_bc_alu alu;
988
989 r = tgsi_split_constant(ctx, r600_src);
990 if (r)
991 return r;
992 r = tgsi_split_literal_constant(ctx, r600_src);
993 if (r)
994 return r;
995
996 memset(&alu, 0, sizeof(struct r600_bc_alu));
997 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
998 alu.is_op3 = 1;
999
1000 alu.dst.chan = 0;
1001 alu.dst.sel = ctx->temp_reg;
1002 alu.dst.write = 1;
1003
1004 alu.src[0] = r600_src[0];
1005 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1006
1007 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1008 alu.src[1].chan = 0;
1009 alu.src[1].value[0] = *(uint32_t *)&half_inv_pi;
1010 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1011 alu.src[2].chan = 0;
1012 alu.last = 1;
1013 r = r600_bc_add_alu(ctx->bc, &alu);
1014 if (r)
1015 return r;
1016
1017 memset(&alu, 0, sizeof(struct r600_bc_alu));
1018 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1019
1020 alu.dst.chan = 0;
1021 alu.dst.sel = ctx->temp_reg;
1022 alu.dst.write = 1;
1023
1024 alu.src[0].sel = ctx->temp_reg;
1025 alu.src[0].chan = 0;
1026 alu.last = 1;
1027 r = r600_bc_add_alu(ctx->bc, &alu);
1028 if (r)
1029 return r;
1030
1031 memset(&alu, 0, sizeof(struct r600_bc_alu));
1032 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1033 alu.is_op3 = 1;
1034
1035 alu.dst.chan = 0;
1036 alu.dst.sel = ctx->temp_reg;
1037 alu.dst.write = 1;
1038
1039 alu.src[0].sel = ctx->temp_reg;
1040 alu.src[0].chan = 0;
1041
1042 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1043 alu.src[1].chan = 0;
1044 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1045 alu.src[2].chan = 0;
1046
1047 if (ctx->bc->chiprev == CHIPREV_R600) {
1048 alu.src[1].value[0] = *(uint32_t *)&double_pi;
1049 alu.src[2].value[0] = *(uint32_t *)&neg_pi;
1050 } else {
1051 alu.src[1].sel = V_SQ_ALU_SRC_1;
1052 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1053 alu.src[2].neg = 1;
1054 }
1055
1056 alu.last = 1;
1057 r = r600_bc_add_alu(ctx->bc, &alu);
1058 if (r)
1059 return r;
1060 return 0;
1061 }
1062
1063 static int tgsi_trig(struct r600_shader_ctx *ctx)
1064 {
1065 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1066 struct r600_bc_alu_src r600_src[3];
1067 struct r600_bc_alu alu;
1068 int i, r;
1069 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1070
1071 r = tgsi_setup_trig(ctx, r600_src);
1072 if (r)
1073 return r;
1074
1075 memset(&alu, 0, sizeof(struct r600_bc_alu));
1076 alu.inst = ctx->inst_info->r600_opcode;
1077 alu.dst.chan = 0;
1078 alu.dst.sel = ctx->temp_reg;
1079 alu.dst.write = 1;
1080
1081 alu.src[0].sel = ctx->temp_reg;
1082 alu.src[0].chan = 0;
1083 alu.last = 1;
1084 r = r600_bc_add_alu(ctx->bc, &alu);
1085 if (r)
1086 return r;
1087
1088 /* replicate result */
1089 for (i = 0; i < lasti + 1; i++) {
1090 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1091 continue;
1092
1093 memset(&alu, 0, sizeof(struct r600_bc_alu));
1094 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1095
1096 alu.src[0].sel = ctx->temp_reg;
1097 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1098 if (i == lasti)
1099 alu.last = 1;
1100 r = r600_bc_add_alu(ctx->bc, &alu);
1101 if (r)
1102 return r;
1103 }
1104 return 0;
1105 }
1106
1107 static int tgsi_scs(struct r600_shader_ctx *ctx)
1108 {
1109 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1110 struct r600_bc_alu_src r600_src[3];
1111 struct r600_bc_alu alu;
1112 int r;
1113
1114 /* We'll only need the trig stuff if we are going to write to the
1115 * X or Y components of the destination vector.
1116 */
1117 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1118 r = tgsi_setup_trig(ctx, r600_src);
1119 if (r)
1120 return r;
1121 }
1122
1123 /* dst.x = COS */
1124 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1125 memset(&alu, 0, sizeof(struct r600_bc_alu));
1126 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1127 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1128
1129 alu.src[0].sel = ctx->temp_reg;
1130 alu.src[0].chan = 0;
1131 alu.last = 1;
1132 r = r600_bc_add_alu(ctx->bc, &alu);
1133 if (r)
1134 return r;
1135 }
1136
1137 /* dst.y = SIN */
1138 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1139 memset(&alu, 0, sizeof(struct r600_bc_alu));
1140 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1141 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1142
1143 alu.src[0].sel = ctx->temp_reg;
1144 alu.src[0].chan = 0;
1145 alu.last = 1;
1146 r = r600_bc_add_alu(ctx->bc, &alu);
1147 if (r)
1148 return r;
1149 }
1150
1151 /* dst.z = 0.0; */
1152 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1153 memset(&alu, 0, sizeof(struct r600_bc_alu));
1154
1155 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1156
1157 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1158
1159 alu.src[0].sel = V_SQ_ALU_SRC_0;
1160 alu.src[0].chan = 0;
1161
1162 alu.last = 1;
1163
1164 r = r600_bc_add_alu(ctx->bc, &alu);
1165 if (r)
1166 return r;
1167 }
1168
1169 /* dst.w = 1.0; */
1170 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1171 memset(&alu, 0, sizeof(struct r600_bc_alu));
1172
1173 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1174
1175 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1176
1177 alu.src[0].sel = V_SQ_ALU_SRC_1;
1178 alu.src[0].chan = 0;
1179
1180 alu.last = 1;
1181
1182 r = r600_bc_add_alu(ctx->bc, &alu);
1183 if (r)
1184 return r;
1185 }
1186
1187 return 0;
1188 }
1189
1190 static int tgsi_kill(struct r600_shader_ctx *ctx)
1191 {
1192 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1193 struct r600_bc_alu alu;
1194 int i, r;
1195
1196 for (i = 0; i < 4; i++) {
1197 memset(&alu, 0, sizeof(struct r600_bc_alu));
1198 alu.inst = ctx->inst_info->r600_opcode;
1199
1200 alu.dst.chan = i;
1201
1202 alu.src[0].sel = V_SQ_ALU_SRC_0;
1203
1204 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1205 alu.src[1].sel = V_SQ_ALU_SRC_1;
1206 alu.src[1].neg = 1;
1207 } else {
1208 tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1209 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1210 }
1211 if (i == 3) {
1212 alu.last = 1;
1213 }
1214 r = r600_bc_add_alu(ctx->bc, &alu);
1215 if (r)
1216 return r;
1217 }
1218
1219 /* kill must be last in ALU */
1220 ctx->bc->force_add_cf = 1;
1221 ctx->shader->uses_kill = TRUE;
1222 return 0;
1223 }
1224
1225 static int tgsi_lit(struct r600_shader_ctx *ctx)
1226 {
1227 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1228 struct r600_bc_alu alu;
1229 struct r600_bc_alu_src r600_src[3];
1230 int r;
1231
1232 r = tgsi_split_constant(ctx, r600_src);
1233 if (r)
1234 return r;
1235 r = tgsi_split_literal_constant(ctx, r600_src);
1236 if (r)
1237 return r;
1238
1239 /* dst.x, <- 1.0 */
1240 memset(&alu, 0, sizeof(struct r600_bc_alu));
1241 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1242 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1243 alu.src[0].chan = 0;
1244 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1245 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1246 r = r600_bc_add_alu(ctx->bc, &alu);
1247 if (r)
1248 return r;
1249
1250 /* dst.y = max(src.x, 0.0) */
1251 memset(&alu, 0, sizeof(struct r600_bc_alu));
1252 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1253 alu.src[0] = r600_src[0];
1254 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1255 alu.src[1].chan = 0;
1256 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1257 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1258 r = r600_bc_add_alu(ctx->bc, &alu);
1259 if (r)
1260 return r;
1261
1262 /* dst.w, <- 1.0 */
1263 memset(&alu, 0, sizeof(struct r600_bc_alu));
1264 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1265 alu.src[0].sel = V_SQ_ALU_SRC_1;
1266 alu.src[0].chan = 0;
1267 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1268 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1269 alu.last = 1;
1270 r = r600_bc_add_alu(ctx->bc, &alu);
1271 if (r)
1272 return r;
1273
1274 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1275 {
1276 int chan;
1277 int sel;
1278
1279 /* dst.z = log(src.y) */
1280 memset(&alu, 0, sizeof(struct r600_bc_alu));
1281 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1282 alu.src[0] = r600_src[0];
1283 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1284 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1285 alu.last = 1;
1286 r = r600_bc_add_alu(ctx->bc, &alu);
1287 if (r)
1288 return r;
1289
1290 chan = alu.dst.chan;
1291 sel = alu.dst.sel;
1292
1293 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1294 memset(&alu, 0, sizeof(struct r600_bc_alu));
1295 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1296 alu.src[0] = r600_src[0];
1297 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1298 alu.src[1].sel = sel;
1299 alu.src[1].chan = chan;
1300
1301 alu.src[2] = r600_src[0];
1302 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1303 alu.dst.sel = ctx->temp_reg;
1304 alu.dst.chan = 0;
1305 alu.dst.write = 1;
1306 alu.is_op3 = 1;
1307 alu.last = 1;
1308 r = r600_bc_add_alu(ctx->bc, &alu);
1309 if (r)
1310 return r;
1311
1312 /* dst.z = exp(tmp.x) */
1313 memset(&alu, 0, sizeof(struct r600_bc_alu));
1314 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1315 alu.src[0].sel = ctx->temp_reg;
1316 alu.src[0].chan = 0;
1317 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1318 alu.last = 1;
1319 r = r600_bc_add_alu(ctx->bc, &alu);
1320 if (r)
1321 return r;
1322 }
1323 return 0;
1324 }
1325
1326 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1327 {
1328 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1329 struct r600_bc_alu alu;
1330 int i, r;
1331
1332 memset(&alu, 0, sizeof(struct r600_bc_alu));
1333
1334 /* FIXME:
1335 * For state trackers other than OpenGL, we'll want to use
1336 * _RECIPSQRT_IEEE instead.
1337 */
1338 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1339
1340 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1341 tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1342 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1343 alu.src[i].abs = 1;
1344 }
1345 alu.dst.sel = ctx->temp_reg;
1346 alu.dst.write = 1;
1347 alu.last = 1;
1348 r = r600_bc_add_alu(ctx->bc, &alu);
1349 if (r)
1350 return r;
1351 /* replicate result */
1352 return tgsi_helper_tempx_replicate(ctx);
1353 }
1354
1355 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1356 {
1357 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1358 struct r600_bc_alu alu;
1359 int i, r;
1360
1361 for (i = 0; i < 4; i++) {
1362 memset(&alu, 0, sizeof(struct r600_bc_alu));
1363 alu.src[0].sel = ctx->temp_reg;
1364 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1365 alu.dst.chan = i;
1366 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1367 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1368 if (i == 3)
1369 alu.last = 1;
1370 r = r600_bc_add_alu(ctx->bc, &alu);
1371 if (r)
1372 return r;
1373 }
1374 return 0;
1375 }
1376
1377 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1378 {
1379 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1380 struct r600_bc_alu alu;
1381 int i, r;
1382
1383 memset(&alu, 0, sizeof(struct r600_bc_alu));
1384 alu.inst = ctx->inst_info->r600_opcode;
1385 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1386 tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1387 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1388 }
1389 alu.dst.sel = ctx->temp_reg;
1390 alu.dst.write = 1;
1391 alu.last = 1;
1392 r = r600_bc_add_alu(ctx->bc, &alu);
1393 if (r)
1394 return r;
1395 /* replicate result */
1396 return tgsi_helper_tempx_replicate(ctx);
1397 }
1398
1399 static int tgsi_pow(struct r600_shader_ctx *ctx)
1400 {
1401 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1402 struct r600_bc_alu alu;
1403 int r;
1404
1405 /* LOG2(a) */
1406 memset(&alu, 0, sizeof(struct r600_bc_alu));
1407 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1408 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1409 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1410 alu.dst.sel = ctx->temp_reg;
1411 alu.dst.write = 1;
1412 alu.last = 1;
1413 r = r600_bc_add_alu(ctx->bc, &alu);
1414 if (r)
1415 return r;
1416 /* b * LOG2(a) */
1417 memset(&alu, 0, sizeof(struct r600_bc_alu));
1418 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1419 tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1420 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1421 alu.src[1].sel = ctx->temp_reg;
1422 alu.dst.sel = ctx->temp_reg;
1423 alu.dst.write = 1;
1424 alu.last = 1;
1425 r = r600_bc_add_alu(ctx->bc, &alu);
1426 if (r)
1427 return r;
1428 /* POW(a,b) = EXP2(b * LOG2(a))*/
1429 memset(&alu, 0, sizeof(struct r600_bc_alu));
1430 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1431 alu.src[0].sel = ctx->temp_reg;
1432 alu.dst.sel = ctx->temp_reg;
1433 alu.dst.write = 1;
1434 alu.last = 1;
1435 r = r600_bc_add_alu(ctx->bc, &alu);
1436 if (r)
1437 return r;
1438 return tgsi_helper_tempx_replicate(ctx);
1439 }
1440
1441 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1442 {
1443 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1444 struct r600_bc_alu alu;
1445 struct r600_bc_alu_src r600_src[3];
1446 int i, r;
1447
1448 r = tgsi_split_constant(ctx, r600_src);
1449 if (r)
1450 return r;
1451 r = tgsi_split_literal_constant(ctx, r600_src);
1452 if (r)
1453 return r;
1454
1455 /* tmp = (src > 0 ? 1 : src) */
1456 for (i = 0; i < 4; i++) {
1457 memset(&alu, 0, sizeof(struct r600_bc_alu));
1458 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1459 alu.is_op3 = 1;
1460
1461 alu.dst.sel = ctx->temp_reg;
1462 alu.dst.chan = i;
1463
1464 alu.src[0] = r600_src[0];
1465 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1466
1467 alu.src[1].sel = V_SQ_ALU_SRC_1;
1468
1469 alu.src[2] = r600_src[0];
1470 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1471 if (i == 3)
1472 alu.last = 1;
1473 r = r600_bc_add_alu(ctx->bc, &alu);
1474 if (r)
1475 return r;
1476 }
1477
1478 /* dst = (-tmp > 0 ? -1 : tmp) */
1479 for (i = 0; i < 4; i++) {
1480 memset(&alu, 0, sizeof(struct r600_bc_alu));
1481 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1482 alu.is_op3 = 1;
1483 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1484
1485 alu.src[0].sel = ctx->temp_reg;
1486 alu.src[0].chan = i;
1487 alu.src[0].neg = 1;
1488
1489 alu.src[1].sel = V_SQ_ALU_SRC_1;
1490 alu.src[1].neg = 1;
1491
1492 alu.src[2].sel = ctx->temp_reg;
1493 alu.src[2].chan = i;
1494
1495 if (i == 3)
1496 alu.last = 1;
1497 r = r600_bc_add_alu(ctx->bc, &alu);
1498 if (r)
1499 return r;
1500 }
1501 return 0;
1502 }
1503
1504 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1505 {
1506 struct r600_bc_alu alu;
1507 int i, r;
1508
1509 for (i = 0; i < 4; i++) {
1510 memset(&alu, 0, sizeof(struct r600_bc_alu));
1511 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1512 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1513 alu.dst.chan = i;
1514 } else {
1515 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1516 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1517 alu.src[0].sel = ctx->temp_reg;
1518 alu.src[0].chan = i;
1519 }
1520 if (i == 3) {
1521 alu.last = 1;
1522 }
1523 r = r600_bc_add_alu(ctx->bc, &alu);
1524 if (r)
1525 return r;
1526 }
1527 return 0;
1528 }
1529
1530 static int tgsi_op3(struct r600_shader_ctx *ctx)
1531 {
1532 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1533 struct r600_bc_alu_src r600_src[3];
1534 struct r600_bc_alu alu;
1535 int i, j, r;
1536 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1537
1538 r = tgsi_split_constant(ctx, r600_src);
1539 if (r)
1540 return r;
1541 r = tgsi_split_literal_constant(ctx, r600_src);
1542 if (r)
1543 return r;
1544 for (i = 0; i < lasti + 1; i++) {
1545 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1546 continue;
1547
1548 memset(&alu, 0, sizeof(struct r600_bc_alu));
1549 alu.inst = ctx->inst_info->r600_opcode;
1550 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1551 alu.src[j] = r600_src[j];
1552 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1553 }
1554
1555 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1556 alu.dst.chan = i;
1557 alu.dst.write = 1;
1558 alu.is_op3 = 1;
1559 if (i == lasti) {
1560 alu.last = 1;
1561 }
1562 r = r600_bc_add_alu(ctx->bc, &alu);
1563 if (r)
1564 return r;
1565 }
1566 return 0;
1567 }
1568
1569 static int tgsi_dp(struct r600_shader_ctx *ctx)
1570 {
1571 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1572 struct r600_bc_alu_src r600_src[3];
1573 struct r600_bc_alu alu;
1574 int i, j, r;
1575
1576 r = tgsi_split_constant(ctx, r600_src);
1577 if (r)
1578 return r;
1579 r = tgsi_split_literal_constant(ctx, r600_src);
1580 if (r)
1581 return r;
1582 for (i = 0; i < 4; i++) {
1583 memset(&alu, 0, sizeof(struct r600_bc_alu));
1584 alu.inst = ctx->inst_info->r600_opcode;
1585 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1586 alu.src[j] = r600_src[j];
1587 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1588 }
1589
1590 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1591 alu.dst.chan = i;
1592 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1593 /* handle some special cases */
1594 switch (ctx->inst_info->tgsi_opcode) {
1595 case TGSI_OPCODE_DP2:
1596 if (i > 1) {
1597 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1598 alu.src[0].chan = alu.src[1].chan = 0;
1599 }
1600 break;
1601 case TGSI_OPCODE_DP3:
1602 if (i > 2) {
1603 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1604 alu.src[0].chan = alu.src[1].chan = 0;
1605 }
1606 break;
1607 case TGSI_OPCODE_DPH:
1608 if (i == 3) {
1609 alu.src[0].sel = V_SQ_ALU_SRC_1;
1610 alu.src[0].chan = 0;
1611 alu.src[0].neg = 0;
1612 }
1613 break;
1614 default:
1615 break;
1616 }
1617 if (i == 3) {
1618 alu.last = 1;
1619 }
1620 r = r600_bc_add_alu(ctx->bc, &alu);
1621 if (r)
1622 return r;
1623 }
1624 return 0;
1625 }
1626
1627 static int tgsi_tex(struct r600_shader_ctx *ctx)
1628 {
1629 static float one_point_five = 1.5f;
1630 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1631 struct r600_bc_tex tex;
1632 struct r600_bc_alu alu;
1633 unsigned src_gpr;
1634 int r, i;
1635 int opcode;
1636 boolean src_not_temp =
1637 inst->Src[0].Register.File != TGSI_FILE_TEMPORARY &&
1638 inst->Src[0].Register.File != TGSI_FILE_INPUT;
1639
1640 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1641
1642 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1643 /* Add perspective divide */
1644 memset(&alu, 0, sizeof(struct r600_bc_alu));
1645 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1646 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1647
1648 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1649 alu.dst.sel = ctx->temp_reg;
1650 alu.dst.chan = 3;
1651 alu.last = 1;
1652 alu.dst.write = 1;
1653 r = r600_bc_add_alu(ctx->bc, &alu);
1654 if (r)
1655 return r;
1656
1657 for (i = 0; i < 3; i++) {
1658 memset(&alu, 0, sizeof(struct r600_bc_alu));
1659 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1660 alu.src[0].sel = ctx->temp_reg;
1661 alu.src[0].chan = 3;
1662 tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1663 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1664 alu.dst.sel = ctx->temp_reg;
1665 alu.dst.chan = i;
1666 alu.dst.write = 1;
1667 r = r600_bc_add_alu(ctx->bc, &alu);
1668 if (r)
1669 return r;
1670 }
1671 memset(&alu, 0, sizeof(struct r600_bc_alu));
1672 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1673 alu.src[0].sel = V_SQ_ALU_SRC_1;
1674 alu.src[0].chan = 0;
1675 alu.dst.sel = ctx->temp_reg;
1676 alu.dst.chan = 3;
1677 alu.last = 1;
1678 alu.dst.write = 1;
1679 r = r600_bc_add_alu(ctx->bc, &alu);
1680 if (r)
1681 return r;
1682 src_not_temp = FALSE;
1683 src_gpr = ctx->temp_reg;
1684 }
1685
1686 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1687 int src_chan, src2_chan;
1688
1689 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1690 for (i = 0; i < 4; i++) {
1691 memset(&alu, 0, sizeof(struct r600_bc_alu));
1692 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1693 switch (i) {
1694 case 0:
1695 src_chan = 2;
1696 src2_chan = 1;
1697 break;
1698 case 1:
1699 src_chan = 2;
1700 src2_chan = 0;
1701 break;
1702 case 2:
1703 src_chan = 0;
1704 src2_chan = 2;
1705 break;
1706 case 3:
1707 src_chan = 1;
1708 src2_chan = 2;
1709 break;
1710 default:
1711 assert(0);
1712 src_chan = 0;
1713 src2_chan = 0;
1714 break;
1715 }
1716 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1717 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1718 tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1719 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1720 alu.dst.sel = ctx->temp_reg;
1721 alu.dst.chan = i;
1722 if (i == 3)
1723 alu.last = 1;
1724 alu.dst.write = 1;
1725 r = r600_bc_add_alu(ctx->bc, &alu);
1726 if (r)
1727 return r;
1728 }
1729
1730 /* tmp1.z = RCP_e(|tmp1.z|) */
1731 memset(&alu, 0, sizeof(struct r600_bc_alu));
1732 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1733 alu.src[0].sel = ctx->temp_reg;
1734 alu.src[0].chan = 2;
1735 alu.src[0].abs = 1;
1736 alu.dst.sel = ctx->temp_reg;
1737 alu.dst.chan = 2;
1738 alu.dst.write = 1;
1739 alu.last = 1;
1740 r = r600_bc_add_alu(ctx->bc, &alu);
1741 if (r)
1742 return r;
1743
1744 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1745 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1746 * muladd has no writemask, have to use another temp
1747 */
1748 memset(&alu, 0, sizeof(struct r600_bc_alu));
1749 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1750 alu.is_op3 = 1;
1751
1752 alu.src[0].sel = ctx->temp_reg;
1753 alu.src[0].chan = 0;
1754 alu.src[1].sel = ctx->temp_reg;
1755 alu.src[1].chan = 2;
1756
1757 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1758 alu.src[2].chan = 0;
1759 alu.src[2].value[0] = *(uint32_t *)&one_point_five;
1760
1761 alu.dst.sel = ctx->temp_reg;
1762 alu.dst.chan = 0;
1763 alu.dst.write = 1;
1764
1765 r = r600_bc_add_alu(ctx->bc, &alu);
1766 if (r)
1767 return r;
1768
1769 memset(&alu, 0, sizeof(struct r600_bc_alu));
1770 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1771 alu.is_op3 = 1;
1772
1773 alu.src[0].sel = ctx->temp_reg;
1774 alu.src[0].chan = 1;
1775 alu.src[1].sel = ctx->temp_reg;
1776 alu.src[1].chan = 2;
1777
1778 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1779 alu.src[2].chan = 0;
1780 alu.src[2].value[0] = *(uint32_t *)&one_point_five;
1781
1782 alu.dst.sel = ctx->temp_reg;
1783 alu.dst.chan = 1;
1784 alu.dst.write = 1;
1785
1786 alu.last = 1;
1787 r = r600_bc_add_alu(ctx->bc, &alu);
1788 if (r)
1789 return r;
1790
1791 src_not_temp = FALSE;
1792 src_gpr = ctx->temp_reg;
1793 }
1794
1795 if (src_not_temp) {
1796 for (i = 0; i < 4; i++) {
1797 memset(&alu, 0, sizeof(struct r600_bc_alu));
1798 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1799 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1800 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1801 alu.dst.sel = ctx->temp_reg;
1802 alu.dst.chan = i;
1803 if (i == 3)
1804 alu.last = 1;
1805 alu.dst.write = 1;
1806 r = r600_bc_add_alu(ctx->bc, &alu);
1807 if (r)
1808 return r;
1809 }
1810 src_gpr = ctx->temp_reg;
1811 }
1812
1813 opcode = ctx->inst_info->r600_opcode;
1814 if (opcode == SQ_TEX_INST_SAMPLE &&
1815 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1816 opcode = SQ_TEX_INST_SAMPLE_C;
1817
1818 memset(&tex, 0, sizeof(struct r600_bc_tex));
1819 tex.inst = opcode;
1820 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1821 tex.resource_id = tex.sampler_id;
1822 tex.src_gpr = src_gpr;
1823 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1824 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1825 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1826 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1827 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1828 tex.src_sel_x = 0;
1829 tex.src_sel_y = 1;
1830 tex.src_sel_z = 2;
1831 tex.src_sel_w = 3;
1832
1833 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1834 tex.src_sel_x = 1;
1835 tex.src_sel_y = 0;
1836 tex.src_sel_z = 3;
1837 tex.src_sel_w = 1;
1838 }
1839
1840 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1841 tex.coord_type_x = 1;
1842 tex.coord_type_y = 1;
1843 tex.coord_type_z = 1;
1844 tex.coord_type_w = 1;
1845 }
1846
1847 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1848 tex.src_sel_w = 2;
1849
1850 r = r600_bc_add_tex(ctx->bc, &tex);
1851 if (r)
1852 return r;
1853
1854 /* add shadow ambient support - gallium doesn't do it yet */
1855 return 0;
1856 }
1857
1858 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1859 {
1860 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1861 struct r600_bc_alu_src r600_src[3];
1862 struct r600_bc_alu alu;
1863 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1864 unsigned i;
1865 int r;
1866
1867 r = tgsi_split_constant(ctx, r600_src);
1868 if (r)
1869 return r;
1870 r = tgsi_split_literal_constant(ctx, r600_src);
1871 if (r)
1872 return r;
1873
1874 /* optimize if it's just an equal balance */
1875 if(r600_src[0].sel == V_SQ_ALU_SRC_0_5) {
1876 for (i = 0; i < lasti + 1; i++) {
1877 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1878 continue;
1879
1880 memset(&alu, 0, sizeof(struct r600_bc_alu));
1881 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1882 alu.src[0] = r600_src[1];
1883 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
1884 alu.src[1] = r600_src[2];
1885 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1886 alu.omod = 3;
1887 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1888 alu.dst.chan = i;
1889 if (i == lasti) {
1890 alu.last = 1;
1891 }
1892 r = r600_bc_add_alu(ctx->bc, &alu);
1893 if (r)
1894 return r;
1895 }
1896 return 0;
1897 }
1898
1899 /* 1 - src0 */
1900 for (i = 0; i < lasti + 1; i++) {
1901 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1902 continue;
1903
1904 memset(&alu, 0, sizeof(struct r600_bc_alu));
1905 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1906 alu.src[0].sel = V_SQ_ALU_SRC_1;
1907 alu.src[0].chan = 0;
1908 alu.src[1] = r600_src[0];
1909 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1910 alu.src[1].neg = 1;
1911 alu.dst.sel = ctx->temp_reg;
1912 alu.dst.chan = i;
1913 if (i == lasti) {
1914 alu.last = 1;
1915 }
1916 alu.dst.write = 1;
1917 r = r600_bc_add_alu(ctx->bc, &alu);
1918 if (r)
1919 return r;
1920 }
1921
1922 /* (1 - src0) * src2 */
1923 for (i = 0; i < lasti + 1; i++) {
1924 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1925 continue;
1926
1927 memset(&alu, 0, sizeof(struct r600_bc_alu));
1928 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1929 alu.src[0].sel = ctx->temp_reg;
1930 alu.src[0].chan = i;
1931 alu.src[1] = r600_src[2];
1932 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1933 alu.dst.sel = ctx->temp_reg;
1934 alu.dst.chan = i;
1935 if (i == lasti) {
1936 alu.last = 1;
1937 }
1938 alu.dst.write = 1;
1939 r = r600_bc_add_alu(ctx->bc, &alu);
1940 if (r)
1941 return r;
1942 }
1943
1944 /* src0 * src1 + (1 - src0) * src2 */
1945 for (i = 0; i < lasti + 1; i++) {
1946 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1947 continue;
1948
1949 memset(&alu, 0, sizeof(struct r600_bc_alu));
1950 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1951 alu.is_op3 = 1;
1952 alu.src[0] = r600_src[0];
1953 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1954 alu.src[1] = r600_src[1];
1955 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1956 alu.src[2].sel = ctx->temp_reg;
1957 alu.src[2].chan = i;
1958
1959 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1960 alu.dst.chan = i;
1961 if (i == lasti) {
1962 alu.last = 1;
1963 }
1964 r = r600_bc_add_alu(ctx->bc, &alu);
1965 if (r)
1966 return r;
1967 }
1968 return 0;
1969 }
1970
1971 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1972 {
1973 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1974 struct r600_bc_alu_src r600_src[3];
1975 struct r600_bc_alu alu;
1976 int i, r;
1977 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1978
1979 r = tgsi_split_constant(ctx, r600_src);
1980 if (r)
1981 return r;
1982 r = tgsi_split_literal_constant(ctx, r600_src);
1983 if (r)
1984 return r;
1985
1986 for (i = 0; i < lasti + 1; i++) {
1987 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1988 continue;
1989
1990 memset(&alu, 0, sizeof(struct r600_bc_alu));
1991 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1992 alu.src[0] = r600_src[0];
1993 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1994
1995 alu.src[1] = r600_src[2];
1996 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1997
1998 alu.src[2] = r600_src[1];
1999 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2000
2001 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2002 alu.dst.chan = i;
2003 alu.dst.write = 1;
2004 alu.is_op3 = 1;
2005 if (i == lasti)
2006 alu.last = 1;
2007 r = r600_bc_add_alu(ctx->bc, &alu);
2008 if (r)
2009 return r;
2010 }
2011 return 0;
2012 }
2013
2014 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2015 {
2016 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2017 struct r600_bc_alu_src r600_src[3];
2018 struct r600_bc_alu alu;
2019 uint32_t use_temp = 0;
2020 int i, r;
2021
2022 if (inst->Dst[0].Register.WriteMask != 0xf)
2023 use_temp = 1;
2024
2025 r = tgsi_split_constant(ctx, r600_src);
2026 if (r)
2027 return r;
2028 r = tgsi_split_literal_constant(ctx, r600_src);
2029 if (r)
2030 return r;
2031
2032 for (i = 0; i < 4; i++) {
2033 memset(&alu, 0, sizeof(struct r600_bc_alu));
2034 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2035
2036 alu.src[0] = r600_src[0];
2037 switch (i) {
2038 case 0:
2039 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2040 break;
2041 case 1:
2042 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2043 break;
2044 case 2:
2045 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2046 break;
2047 case 3:
2048 alu.src[0].sel = V_SQ_ALU_SRC_0;
2049 alu.src[0].chan = i;
2050 }
2051
2052 alu.src[1] = r600_src[1];
2053 switch (i) {
2054 case 0:
2055 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2056 break;
2057 case 1:
2058 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2059 break;
2060 case 2:
2061 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2062 break;
2063 case 3:
2064 alu.src[1].sel = V_SQ_ALU_SRC_0;
2065 alu.src[1].chan = i;
2066 }
2067
2068 alu.dst.sel = ctx->temp_reg;
2069 alu.dst.chan = i;
2070 alu.dst.write = 1;
2071
2072 if (i == 3)
2073 alu.last = 1;
2074 r = r600_bc_add_alu(ctx->bc, &alu);
2075 if (r)
2076 return r;
2077 }
2078
2079 for (i = 0; i < 4; i++) {
2080 memset(&alu, 0, sizeof(struct r600_bc_alu));
2081 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2082
2083 alu.src[0] = r600_src[0];
2084 switch (i) {
2085 case 0:
2086 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2087 break;
2088 case 1:
2089 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2090 break;
2091 case 2:
2092 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2093 break;
2094 case 3:
2095 alu.src[0].sel = V_SQ_ALU_SRC_0;
2096 alu.src[0].chan = i;
2097 }
2098
2099 alu.src[1] = r600_src[1];
2100 switch (i) {
2101 case 0:
2102 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2103 break;
2104 case 1:
2105 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2106 break;
2107 case 2:
2108 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2109 break;
2110 case 3:
2111 alu.src[1].sel = V_SQ_ALU_SRC_0;
2112 alu.src[1].chan = i;
2113 }
2114
2115 alu.src[2].sel = ctx->temp_reg;
2116 alu.src[2].neg = 1;
2117 alu.src[2].chan = i;
2118
2119 if (use_temp)
2120 alu.dst.sel = ctx->temp_reg;
2121 else
2122 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2123 alu.dst.chan = i;
2124 alu.dst.write = 1;
2125 alu.is_op3 = 1;
2126 if (i == 3)
2127 alu.last = 1;
2128 r = r600_bc_add_alu(ctx->bc, &alu);
2129 if (r)
2130 return r;
2131 }
2132 if (use_temp)
2133 return tgsi_helper_copy(ctx, inst);
2134 return 0;
2135 }
2136
2137 static int tgsi_exp(struct r600_shader_ctx *ctx)
2138 {
2139 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2140 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2141 struct r600_bc_alu alu;
2142 int r;
2143
2144 /* result.x = 2^floor(src); */
2145 if (inst->Dst[0].Register.WriteMask & 1) {
2146 memset(&alu, 0, sizeof(struct r600_bc_alu));
2147
2148 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2149 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2150
2151 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2152
2153 alu.dst.sel = ctx->temp_reg;
2154 alu.dst.chan = 0;
2155 alu.dst.write = 1;
2156 alu.last = 1;
2157 r = r600_bc_add_alu(ctx->bc, &alu);
2158 if (r)
2159 return r;
2160
2161 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2162 alu.src[0].sel = ctx->temp_reg;
2163 alu.src[0].chan = 0;
2164
2165 alu.dst.sel = ctx->temp_reg;
2166 alu.dst.chan = 0;
2167 alu.dst.write = 1;
2168 alu.last = 1;
2169 r = r600_bc_add_alu(ctx->bc, &alu);
2170 if (r)
2171 return r;
2172 }
2173
2174 /* result.y = tmp - floor(tmp); */
2175 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2176 memset(&alu, 0, sizeof(struct r600_bc_alu));
2177
2178 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2179 alu.src[0] = r600_src[0];
2180 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2181 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2182
2183 alu.dst.sel = ctx->temp_reg;
2184 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2185 // if (r)
2186 // return r;
2187 alu.dst.write = 1;
2188 alu.dst.chan = 1;
2189
2190 alu.last = 1;
2191
2192 r = r600_bc_add_alu(ctx->bc, &alu);
2193 if (r)
2194 return r;
2195 }
2196
2197 /* result.z = RoughApprox2ToX(tmp);*/
2198 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2199 memset(&alu, 0, sizeof(struct r600_bc_alu));
2200 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2201 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2202 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2203
2204 alu.dst.sel = ctx->temp_reg;
2205 alu.dst.write = 1;
2206 alu.dst.chan = 2;
2207
2208 alu.last = 1;
2209
2210 r = r600_bc_add_alu(ctx->bc, &alu);
2211 if (r)
2212 return r;
2213 }
2214
2215 /* result.w = 1.0;*/
2216 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2217 memset(&alu, 0, sizeof(struct r600_bc_alu));
2218
2219 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2220 alu.src[0].sel = V_SQ_ALU_SRC_1;
2221 alu.src[0].chan = 0;
2222
2223 alu.dst.sel = ctx->temp_reg;
2224 alu.dst.chan = 3;
2225 alu.dst.write = 1;
2226 alu.last = 1;
2227 r = r600_bc_add_alu(ctx->bc, &alu);
2228 if (r)
2229 return r;
2230 }
2231 return tgsi_helper_copy(ctx, inst);
2232 }
2233
2234 static int tgsi_log(struct r600_shader_ctx *ctx)
2235 {
2236 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2237 struct r600_bc_alu alu;
2238 int r;
2239
2240 /* result.x = floor(log2(src)); */
2241 if (inst->Dst[0].Register.WriteMask & 1) {
2242 memset(&alu, 0, sizeof(struct r600_bc_alu));
2243
2244 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2245 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2246
2247 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2248
2249 alu.dst.sel = ctx->temp_reg;
2250 alu.dst.chan = 0;
2251 alu.dst.write = 1;
2252 alu.last = 1;
2253 r = r600_bc_add_alu(ctx->bc, &alu);
2254 if (r)
2255 return r;
2256
2257 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2258 alu.src[0].sel = ctx->temp_reg;
2259 alu.src[0].chan = 0;
2260
2261 alu.dst.sel = ctx->temp_reg;
2262 alu.dst.chan = 0;
2263 alu.dst.write = 1;
2264 alu.last = 1;
2265
2266 r = r600_bc_add_alu(ctx->bc, &alu);
2267 if (r)
2268 return r;
2269 }
2270
2271 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2272 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2273 memset(&alu, 0, sizeof(struct r600_bc_alu));
2274
2275 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2276 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2277
2278 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2279
2280 alu.dst.sel = ctx->temp_reg;
2281 alu.dst.chan = 1;
2282 alu.dst.write = 1;
2283 alu.last = 1;
2284
2285 r = r600_bc_add_alu(ctx->bc, &alu);
2286 if (r)
2287 return r;
2288
2289 memset(&alu, 0, sizeof(struct r600_bc_alu));
2290
2291 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2292 alu.src[0].sel = ctx->temp_reg;
2293 alu.src[0].chan = 1;
2294
2295 alu.dst.sel = ctx->temp_reg;
2296 alu.dst.chan = 1;
2297 alu.dst.write = 1;
2298 alu.last = 1;
2299
2300 r = r600_bc_add_alu(ctx->bc, &alu);
2301 if (r)
2302 return r;
2303
2304 memset(&alu, 0, sizeof(struct r600_bc_alu));
2305
2306 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2307 alu.src[0].sel = ctx->temp_reg;
2308 alu.src[0].chan = 1;
2309
2310 alu.dst.sel = ctx->temp_reg;
2311 alu.dst.chan = 1;
2312 alu.dst.write = 1;
2313 alu.last = 1;
2314
2315 r = r600_bc_add_alu(ctx->bc, &alu);
2316 if (r)
2317 return r;
2318
2319 memset(&alu, 0, sizeof(struct r600_bc_alu));
2320
2321 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2322 alu.src[0].sel = ctx->temp_reg;
2323 alu.src[0].chan = 1;
2324
2325 alu.dst.sel = ctx->temp_reg;
2326 alu.dst.chan = 1;
2327 alu.dst.write = 1;
2328 alu.last = 1;
2329
2330 r = r600_bc_add_alu(ctx->bc, &alu);
2331 if (r)
2332 return r;
2333
2334 memset(&alu, 0, sizeof(struct r600_bc_alu));
2335
2336 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2337
2338 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2339 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2340
2341 alu.src[1].sel = ctx->temp_reg;
2342 alu.src[1].chan = 1;
2343
2344 alu.dst.sel = ctx->temp_reg;
2345 alu.dst.chan = 1;
2346 alu.dst.write = 1;
2347 alu.last = 1;
2348
2349 r = r600_bc_add_alu(ctx->bc, &alu);
2350 if (r)
2351 return r;
2352 }
2353
2354 /* result.z = log2(src);*/
2355 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2356 memset(&alu, 0, sizeof(struct r600_bc_alu));
2357
2358 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2359 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2360 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2361
2362 alu.dst.sel = ctx->temp_reg;
2363 alu.dst.write = 1;
2364 alu.dst.chan = 2;
2365 alu.last = 1;
2366
2367 r = r600_bc_add_alu(ctx->bc, &alu);
2368 if (r)
2369 return r;
2370 }
2371
2372 /* result.w = 1.0; */
2373 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2374 memset(&alu, 0, sizeof(struct r600_bc_alu));
2375
2376 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2377 alu.src[0].sel = V_SQ_ALU_SRC_1;
2378 alu.src[0].chan = 0;
2379
2380 alu.dst.sel = ctx->temp_reg;
2381 alu.dst.chan = 3;
2382 alu.dst.write = 1;
2383 alu.last = 1;
2384
2385 r = r600_bc_add_alu(ctx->bc, &alu);
2386 if (r)
2387 return r;
2388 }
2389
2390 return tgsi_helper_copy(ctx, inst);
2391 }
2392
2393 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2394 {
2395 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2396 struct r600_bc_alu alu;
2397 int r;
2398 memset(&alu, 0, sizeof(struct r600_bc_alu));
2399
2400 switch (inst->Instruction.Opcode) {
2401 case TGSI_OPCODE_ARL:
2402 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2403 break;
2404 case TGSI_OPCODE_ARR:
2405 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2406 break;
2407 default:
2408 assert(0);
2409 return -1;
2410 }
2411
2412 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2413 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2414 alu.last = 1;
2415 alu.dst.chan = 0;
2416 alu.dst.sel = ctx->temp_reg;
2417 alu.dst.write = 1;
2418 r = r600_bc_add_alu(ctx->bc, &alu);
2419 if (r)
2420 return r;
2421 memset(&alu, 0, sizeof(struct r600_bc_alu));
2422 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2423 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2424 alu.src[0].sel = ctx->temp_reg;
2425 alu.src[0].chan = 0;
2426 alu.last = 1;
2427 r = r600_bc_add_alu(ctx->bc, &alu);
2428 if (r)
2429 return r;
2430 return 0;
2431 }
2432 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2433 {
2434 /* TODO from r600c, ar values don't persist between clauses */
2435 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2436 struct r600_bc_alu alu;
2437 int r;
2438 memset(&alu, 0, sizeof(struct r600_bc_alu));
2439
2440 switch (inst->Instruction.Opcode) {
2441 case TGSI_OPCODE_ARL:
2442 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2443 break;
2444 case TGSI_OPCODE_ARR:
2445 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2446 break;
2447 default:
2448 assert(0);
2449 return -1;
2450 }
2451
2452
2453 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2454 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2455
2456 alu.last = 1;
2457
2458 r = r600_bc_add_alu(ctx->bc, &alu);
2459 if (r)
2460 return r;
2461 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2462 return 0;
2463 }
2464
2465 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2466 {
2467 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2468 struct r600_bc_alu alu;
2469 int i, r = 0;
2470
2471 for (i = 0; i < 4; i++) {
2472 memset(&alu, 0, sizeof(struct r600_bc_alu));
2473
2474 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2475 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2476
2477 if (i == 0 || i == 3) {
2478 alu.src[0].sel = V_SQ_ALU_SRC_1;
2479 } else {
2480 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2481 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2482 }
2483
2484 if (i == 0 || i == 2) {
2485 alu.src[1].sel = V_SQ_ALU_SRC_1;
2486 } else {
2487 tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2488 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2489 }
2490 if (i == 3)
2491 alu.last = 1;
2492 r = r600_bc_add_alu(ctx->bc, &alu);
2493 if (r)
2494 return r;
2495 }
2496 return 0;
2497 }
2498
2499 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2500 {
2501 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2502 struct r600_bc_alu alu;
2503 int r;
2504
2505 memset(&alu, 0, sizeof(struct r600_bc_alu));
2506 alu.inst = opcode;
2507 alu.predicate = 1;
2508
2509 alu.dst.sel = ctx->temp_reg;
2510 alu.dst.write = 1;
2511 alu.dst.chan = 0;
2512
2513 tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2514 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2515 alu.src[1].sel = V_SQ_ALU_SRC_0;
2516 alu.src[1].chan = 0;
2517
2518 alu.last = 1;
2519
2520 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2521 if (r)
2522 return r;
2523 return 0;
2524 }
2525
2526 static int pops(struct r600_shader_ctx *ctx, int pops)
2527 {
2528 int alu_pop = 3;
2529 if (ctx->bc->cf_last) {
2530 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) << 3)
2531 alu_pop = 0;
2532 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3)
2533 alu_pop = 1;
2534 }
2535 alu_pop += pops;
2536 if (alu_pop == 1) {
2537 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3;
2538 ctx->bc->force_add_cf = 1;
2539 } else if (alu_pop == 2) {
2540 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER) << 3;
2541 ctx->bc->force_add_cf = 1;
2542 } else {
2543 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2544 ctx->bc->cf_last->pop_count = pops;
2545 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2546 }
2547 return 0;
2548 }
2549
2550 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2551 {
2552 switch(reason) {
2553 case FC_PUSH_VPM:
2554 ctx->bc->callstack[ctx->bc->call_sp].current--;
2555 break;
2556 case FC_PUSH_WQM:
2557 case FC_LOOP:
2558 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2559 break;
2560 case FC_REP:
2561 /* TOODO : for 16 vp asic should -= 2; */
2562 ctx->bc->callstack[ctx->bc->call_sp].current --;
2563 break;
2564 }
2565 }
2566
2567 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2568 {
2569 if (check_max_only) {
2570 int diff;
2571 switch (reason) {
2572 case FC_PUSH_VPM:
2573 diff = 1;
2574 break;
2575 case FC_PUSH_WQM:
2576 diff = 4;
2577 break;
2578 default:
2579 assert(0);
2580 diff = 0;
2581 }
2582 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2583 ctx->bc->callstack[ctx->bc->call_sp].max) {
2584 ctx->bc->callstack[ctx->bc->call_sp].max =
2585 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2586 }
2587 return;
2588 }
2589 switch (reason) {
2590 case FC_PUSH_VPM:
2591 ctx->bc->callstack[ctx->bc->call_sp].current++;
2592 break;
2593 case FC_PUSH_WQM:
2594 case FC_LOOP:
2595 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2596 break;
2597 case FC_REP:
2598 ctx->bc->callstack[ctx->bc->call_sp].current++;
2599 break;
2600 }
2601
2602 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2603 ctx->bc->callstack[ctx->bc->call_sp].max) {
2604 ctx->bc->callstack[ctx->bc->call_sp].max =
2605 ctx->bc->callstack[ctx->bc->call_sp].current;
2606 }
2607 }
2608
2609 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2610 {
2611 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2612
2613 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2614 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2615 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2616 sp->num_mid++;
2617 }
2618
2619 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2620 {
2621 ctx->bc->fc_sp++;
2622 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2623 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2624 }
2625
2626 static void fc_poplevel(struct r600_shader_ctx *ctx)
2627 {
2628 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2629 if (sp->mid) {
2630 free(sp->mid);
2631 sp->mid = NULL;
2632 }
2633 sp->num_mid = 0;
2634 sp->start = NULL;
2635 sp->type = 0;
2636 ctx->bc->fc_sp--;
2637 }
2638
2639 #if 0
2640 static int emit_return(struct r600_shader_ctx *ctx)
2641 {
2642 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2643 return 0;
2644 }
2645
2646 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2647 {
2648
2649 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2650 ctx->bc->cf_last->pop_count = pops;
2651 /* TODO work out offset */
2652 return 0;
2653 }
2654
2655 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2656 {
2657 return 0;
2658 }
2659
2660 static void emit_testflag(struct r600_shader_ctx *ctx)
2661 {
2662
2663 }
2664
2665 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2666 {
2667 emit_testflag(ctx);
2668 emit_jump_to_offset(ctx, 1, 4);
2669 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2670 pops(ctx, ifidx + 1);
2671 emit_return(ctx);
2672 }
2673
2674 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2675 {
2676 emit_testflag(ctx);
2677
2678 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2679 ctx->bc->cf_last->pop_count = 1;
2680
2681 fc_set_mid(ctx, fc_sp);
2682
2683 pops(ctx, 1);
2684 }
2685 #endif
2686
2687 static int tgsi_if(struct r600_shader_ctx *ctx)
2688 {
2689 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2690
2691 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2692
2693 fc_pushlevel(ctx, FC_IF);
2694
2695 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2696 return 0;
2697 }
2698
2699 static int tgsi_else(struct r600_shader_ctx *ctx)
2700 {
2701 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2702 ctx->bc->cf_last->pop_count = 1;
2703
2704 fc_set_mid(ctx, ctx->bc->fc_sp);
2705 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2706 return 0;
2707 }
2708
2709 static int tgsi_endif(struct r600_shader_ctx *ctx)
2710 {
2711 pops(ctx, 1);
2712 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2713 R600_ERR("if/endif unbalanced in shader\n");
2714 return -1;
2715 }
2716
2717 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2718 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2719 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2720 } else {
2721 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2722 }
2723 fc_poplevel(ctx);
2724
2725 callstack_decrease_current(ctx, FC_PUSH_VPM);
2726 return 0;
2727 }
2728
2729 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2730 {
2731 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2732
2733 fc_pushlevel(ctx, FC_LOOP);
2734
2735 /* check stack depth */
2736 callstack_check_depth(ctx, FC_LOOP, 0);
2737 return 0;
2738 }
2739
2740 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2741 {
2742 int i;
2743
2744 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2745
2746 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2747 R600_ERR("loop/endloop in shader code are not paired.\n");
2748 return -EINVAL;
2749 }
2750
2751 /* fixup loop pointers - from r600isa
2752 LOOP END points to CF after LOOP START,
2753 LOOP START point to CF after LOOP END
2754 BRK/CONT point to LOOP END CF
2755 */
2756 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2757
2758 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2759
2760 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2761 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2762 }
2763 /* TODO add LOOPRET support */
2764 fc_poplevel(ctx);
2765 callstack_decrease_current(ctx, FC_LOOP);
2766 return 0;
2767 }
2768
2769 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2770 {
2771 unsigned int fscp;
2772
2773 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2774 {
2775 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2776 break;
2777 }
2778
2779 if (fscp == 0) {
2780 R600_ERR("Break not inside loop/endloop pair\n");
2781 return -EINVAL;
2782 }
2783
2784 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2785 ctx->bc->cf_last->pop_count = 1;
2786
2787 fc_set_mid(ctx, fscp);
2788
2789 pops(ctx, 1);
2790 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2791 return 0;
2792 }
2793
2794 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2795 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2796 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2797 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2798
2799 /* FIXME:
2800 * For state trackers other than OpenGL, we'll want to use
2801 * _RECIP_IEEE instead.
2802 */
2803 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2804
2805 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2806 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2807 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2808 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2809 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2810 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2811 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2812 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2813 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2814 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2815 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2816 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2817 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2818 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2819 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2820 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2821 /* gap */
2822 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2823 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2824 /* gap */
2825 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2826 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2827 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2828 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2829 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2830 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2831 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2832 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2833 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2834 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2835 /* gap */
2836 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2837 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2838 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2839 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2840 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2841 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2842 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2843 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2844 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2845 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2846 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2847 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2848 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2849 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2850 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2851 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2852 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2853 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2854 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2855 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2856 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2857 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2858 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2859 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2860 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2861 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2862 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2863 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2864 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2865 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2866 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2867 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2868 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2869 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2870 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2871 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2872 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2873 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2874 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2875 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2876 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2877 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2878 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2879 /* gap */
2880 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2881 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2882 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2883 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2884 /* gap */
2885 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2886 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2887 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2888 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2889 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2891 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2892 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2893 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2894 /* gap */
2895 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2896 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2897 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2898 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2899 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2900 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2901 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2902 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2903 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2904 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2907 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2908 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2909 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2910 /* gap */
2911 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2912 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2914 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 /* gap */
2917 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2918 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2919 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2920 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2921 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2922 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2924 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2926 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2927 /* gap */
2928 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2932 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2934 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2937 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2950 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2955 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 };
2957
2958 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
2959 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
2960 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2961 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2962 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2963 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
2964 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2965 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2967 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2968 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2969 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2970 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2971 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2972 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2973 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2974 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2975 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2976 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2977 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2978 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 /* gap */
2980 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 /* gap */
2983 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2986 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2988 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2990 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2991 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2992 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2993 /* gap */
2994 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2996 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2998 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2999 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3000 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3001 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3002 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3008 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3010 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3011 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3012 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3013 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3015 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3017 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3024 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3026 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3027 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3028 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3029 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3030 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3031 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3034 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3035 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3036 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3037 /* gap */
3038 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3039 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3040 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3041 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3042 /* gap */
3043 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3044 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3045 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3049 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3051 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 /* gap */
3053 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3056 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3058 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3062 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3065 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3067 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 /* gap */
3069 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 /* gap */
3075 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3076 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3077 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3078 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3079 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3080 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3082 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3084 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3085 /* gap */
3086 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3092 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3106 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3107 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3108 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3113 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 };