2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
38 struct r600_shader_tgsi_instruction
;
40 struct r600_shader_ctx
{
41 struct tgsi_shader_info info
;
42 struct tgsi_parse_context parse
;
43 const struct tgsi_token
*tokens
;
45 unsigned file_offset
[TGSI_FILE_COUNT
];
47 struct r600_shader_tgsi_instruction
*inst_info
;
49 struct r600_shader
*shader
;
53 struct r600_shader_tgsi_instruction
{
57 int (*process
)(struct r600_shader_ctx
*ctx
);
60 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[];
61 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
63 static int r600_shader_update(struct pipe_context
*ctx
, struct r600_shader
*shader
)
65 struct r600_context
*rctx
= r600_context(ctx
);
66 const struct util_format_description
*desc
;
67 enum pipe_format resource_format
[160];
68 unsigned i
, nresources
= 0;
69 struct r600_bc
*bc
= &shader
->bc
;
70 struct r600_bc_cf
*cf
;
71 struct r600_bc_vtx
*vtx
;
73 if (shader
->processor_type
!= TGSI_PROCESSOR_VERTEX
)
75 for (i
= 0; i
< rctx
->vertex_elements
->count
; i
++) {
76 resource_format
[nresources
++] = rctx
->vertex_elements
->elements
[i
].src_format
;
78 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
80 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
81 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
82 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
83 desc
= util_format_description(resource_format
[vtx
->buffer_id
]);
85 R600_ERR("unknown format %d\n", resource_format
[vtx
->buffer_id
]);
88 vtx
->dst_sel_x
= desc
->swizzle
[0];
89 vtx
->dst_sel_y
= desc
->swizzle
[1];
90 vtx
->dst_sel_z
= desc
->swizzle
[2];
91 vtx
->dst_sel_w
= desc
->swizzle
[3];
98 return r600_bc_build(&shader
->bc
);
101 int r600_pipe_shader_create(struct pipe_context
*ctx
,
102 struct r600_context_state
*rpshader
,
103 const struct tgsi_token
*tokens
)
105 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
108 fprintf(stderr
, "--------------------------------------------------------------\n");
109 tgsi_dump(tokens
, 0);
110 if (rpshader
== NULL
)
112 rpshader
->shader
.family
= radeon_get_family(rscreen
->rw
);
113 r
= r600_shader_from_tgsi(tokens
, &rpshader
->shader
);
115 R600_ERR("translation from TGSI failed !\n");
118 r
= r600_bc_build(&rpshader
->shader
.bc
);
120 R600_ERR("building bytecode failed !\n");
123 fprintf(stderr
, "______________________________________________________________\n");
127 static int r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
129 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
130 struct r600_shader
*rshader
= &rpshader
->shader
;
131 struct radeon_state
*state
;
134 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
135 state
= radeon_state(rscreen
->rw
, R600_VS_SHADER_TYPE
, R600_VS_SHADER
);
138 for (i
= 0; i
< 10; i
++) {
139 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
] = 0;
141 /* so far never got proper semantic id from tgsi */
142 for (i
= 0; i
< 32; i
++) {
143 tmp
= i
<< ((i
& 3) * 8);
144 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
/ 4] |= tmp
;
146 state
->states
[R600_VS_SHADER__SPI_VS_OUT_CONFIG
] = S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2);
147 state
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
148 rpshader
->rstate
= state
;
149 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
150 rpshader
->rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
151 rpshader
->rstate
->nbo
= 2;
152 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
153 return radeon_state_pm4(state
);
156 static int r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
158 const struct pipe_rasterizer_state
*rasterizer
;
159 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
160 struct r600_shader
*rshader
= &rpshader
->shader
;
161 struct r600_context
*rctx
= r600_context(ctx
);
162 struct radeon_state
*state
;
163 unsigned i
, tmp
, exports_ps
, num_cout
;
165 rasterizer
= &rctx
->rasterizer
->state
.rasterizer
;
166 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
167 state
= radeon_state(rscreen
->rw
, R600_PS_SHADER_TYPE
, R600_PS_SHADER
);
170 for (i
= 0; i
< rshader
->ninput
; i
++) {
171 tmp
= S_028644_SEMANTIC(i
);
172 tmp
|= S_028644_SEL_CENTROID(1);
173 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
174 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
) {
175 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
177 if (rasterizer
->sprite_coord_enable
& (1 << i
)) {
178 tmp
|= S_028644_PT_SPRITE_TEX(1);
180 state
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
+ i
] = tmp
;
185 for (i
= 0; i
< rshader
->noutput
; i
++) {
186 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
188 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
189 exports_ps
|= (1 << (num_cout
+1));
193 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] = S_0286CC_NUM_INTERP(rshader
->ninput
) |
194 S_0286CC_PERSP_GRADIENT_ENA(1);
195 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_1
] = 0x00000000;
196 state
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
197 state
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = exports_ps
;
198 rpshader
->rstate
= state
;
199 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
200 rpshader
->rstate
->nbo
= 1;
201 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
202 return radeon_state_pm4(state
);
205 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
207 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
208 struct r600_context
*rctx
= r600_context(ctx
);
209 struct r600_shader
*rshader
= &rpshader
->shader
;
212 /* copy new shader */
213 radeon_bo_decref(rscreen
->rw
, rpshader
->bo
);
215 rpshader
->bo
= radeon_bo(rscreen
->rw
, 0, rshader
->bc
.ndw
* 4,
217 if (rpshader
->bo
== NULL
) {
220 radeon_bo_map(rscreen
->rw
, rpshader
->bo
);
221 memcpy(rpshader
->bo
->data
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
222 radeon_bo_unmap(rscreen
->rw
, rpshader
->bo
);
224 rshader
->flat_shade
= rctx
->flat_shade
;
225 switch (rshader
->processor_type
) {
226 case TGSI_PROCESSOR_VERTEX
:
227 r
= r600_pipe_shader_vs(ctx
, rpshader
);
229 case TGSI_PROCESSOR_FRAGMENT
:
230 r
= r600_pipe_shader_ps(ctx
, rpshader
);
239 int r600_pipe_shader_update(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
241 struct r600_context
*rctx
= r600_context(ctx
);
244 if (rpshader
== NULL
)
246 /* there should be enough input */
247 if (rctx
->vertex_elements
->count
< rpshader
->shader
.bc
.nresource
) {
248 R600_ERR("%d resources provided, expecting %d\n",
249 rctx
->vertex_elements
->count
, rpshader
->shader
.bc
.nresource
);
252 r
= r600_shader_update(ctx
, &rpshader
->shader
);
255 return r600_pipe_shader(ctx
, rpshader
);
258 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
260 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
263 if (i
->Instruction
.NumDstRegs
> 1) {
264 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
267 if (i
->Instruction
.Predicate
) {
268 R600_ERR("predicate unsupported\n");
271 if (i
->Instruction
.Label
) {
272 R600_ERR("label unsupported\n");
275 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
276 if (i
->Src
[j
].Register
.Indirect
||
277 i
->Src
[j
].Register
.Dimension
||
278 i
->Src
[j
].Register
.Absolute
) {
279 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
283 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
284 if (i
->Dst
[j
].Register
.Indirect
|| i
->Dst
[j
].Register
.Dimension
) {
285 R600_ERR("unsupported dst (indirect|dimension)\n");
292 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
294 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
295 struct r600_bc_vtx vtx
;
299 switch (d
->Declaration
.File
) {
300 case TGSI_FILE_INPUT
:
301 i
= ctx
->shader
->ninput
++;
302 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
303 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
304 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
305 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
306 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
307 /* turn input into fetch */
308 memset(&vtx
, 0, sizeof(struct r600_bc_vtx
));
312 /* register containing the index into the buffer */
315 vtx
.mega_fetch_count
= 0x1F;
316 vtx
.dst_gpr
= ctx
->shader
->input
[i
].gpr
;
321 r
= r600_bc_add_vtx(ctx
->bc
, &vtx
);
326 case TGSI_FILE_OUTPUT
:
327 i
= ctx
->shader
->noutput
++;
328 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
329 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
330 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
331 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
333 case TGSI_FILE_CONSTANT
:
334 case TGSI_FILE_TEMPORARY
:
335 case TGSI_FILE_SAMPLER
:
338 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
344 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
346 struct tgsi_full_immediate
*immediate
;
347 struct r600_shader_ctx ctx
;
348 struct r600_bc_output output
[32];
349 unsigned output_done
, noutput
;
353 ctx
.bc
= &shader
->bc
;
355 r
= r600_bc_init(ctx
.bc
, shader
->family
);
359 tgsi_scan_shader(tokens
, &ctx
.info
);
360 tgsi_parse_init(&ctx
.parse
, tokens
);
361 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
362 shader
->processor_type
= ctx
.type
;
364 /* register allocations */
365 /* Values [0,127] correspond to GPR[0..127].
366 * Values [256,511] correspond to cfile constants c[0..255].
367 * Other special values are shown in the list below.
368 * 248 SQ_ALU_SRC_0: special constant 0.0.
369 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
370 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
371 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
372 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
373 * 253 SQ_ALU_SRC_LITERAL: literal constant.
374 * 254 SQ_ALU_SRC_PV: previous vector result.
375 * 255 SQ_ALU_SRC_PS: previous scalar result.
377 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
378 ctx
.file_offset
[i
] = 0;
380 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
381 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
383 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
384 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
385 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
386 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
387 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 256;
388 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = 253;
389 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
390 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
392 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
393 tgsi_parse_token(&ctx
.parse
);
394 switch (ctx
.parse
.FullToken
.Token
.Type
) {
395 case TGSI_TOKEN_TYPE_IMMEDIATE
:
396 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
397 ctx
.value
[0] = immediate
->u
[0].Uint
;
398 ctx
.value
[1] = immediate
->u
[1].Uint
;
399 ctx
.value
[2] = immediate
->u
[2].Uint
;
400 ctx
.value
[3] = immediate
->u
[3].Uint
;
402 case TGSI_TOKEN_TYPE_DECLARATION
:
403 r
= tgsi_declaration(&ctx
);
407 case TGSI_TOKEN_TYPE_INSTRUCTION
:
408 r
= tgsi_is_supported(&ctx
);
411 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
412 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
413 r
= ctx
.inst_info
->process(&ctx
);
416 r
= r600_bc_add_literal(ctx
.bc
, ctx
.value
);
421 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
427 noutput
= shader
->noutput
;
428 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
429 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
430 output
[i
].gpr
= shader
->output
[i
].gpr
;
431 output
[i
].elem_size
= 3;
432 output
[i
].swizzle_x
= 0;
433 output
[i
].swizzle_y
= 1;
434 output
[i
].swizzle_z
= 2;
435 output
[i
].swizzle_w
= 3;
436 output
[i
].barrier
= 1;
437 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
438 output
[i
].array_base
= i
- pos0
;
439 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
441 case TGSI_PROCESSOR_VERTEX
:
442 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
443 output
[i
].array_base
= 60;
444 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
445 /* position doesn't count in array_base */
448 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
449 output
[i
].array_base
= 61;
450 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
451 /* position doesn't count in array_base */
455 case TGSI_PROCESSOR_FRAGMENT
:
456 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
457 output
[i
].array_base
= shader
->output
[i
].sid
;
458 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
459 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
460 output
[i
].array_base
= 61;
461 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
463 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
469 R600_ERR("unsupported processor type %d\n", ctx
.type
);
474 /* add fake param output for vertex shader if no param is exported */
475 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
476 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
477 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
483 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
485 output
[i
].elem_size
= 3;
486 output
[i
].swizzle_x
= 0;
487 output
[i
].swizzle_y
= 1;
488 output
[i
].swizzle_z
= 2;
489 output
[i
].swizzle_w
= 3;
490 output
[i
].barrier
= 1;
491 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
492 output
[i
].array_base
= 0;
493 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
497 /* add fake pixel export */
498 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
499 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
501 output
[0].elem_size
= 3;
502 output
[0].swizzle_x
= 7;
503 output
[0].swizzle_y
= 7;
504 output
[0].swizzle_z
= 7;
505 output
[0].swizzle_w
= 7;
506 output
[0].barrier
= 1;
507 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
508 output
[0].array_base
= 0;
509 output
[0].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
512 /* set export done on last export of each type */
513 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
514 if (i
== (noutput
- 1)) {
515 output
[i
].end_of_program
= 1;
517 if (!(output_done
& (1 << output
[i
].type
))) {
518 output_done
|= (1 << output
[i
].type
);
519 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
;
522 /* add output to bytecode */
523 for (i
= 0; i
< noutput
; i
++) {
524 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
528 tgsi_parse_free(&ctx
.parse
);
531 tgsi_parse_free(&ctx
.parse
);
535 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
537 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
541 static int tgsi_end(struct r600_shader_ctx
*ctx
)
546 static int tgsi_src(struct r600_shader_ctx
*ctx
,
547 const struct tgsi_full_src_register
*tgsi_src
,
548 struct r600_bc_alu_src
*r600_src
)
550 memset(r600_src
, 0, sizeof(struct r600_bc_alu_src
));
551 r600_src
->sel
= tgsi_src
->Register
.Index
;
552 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
555 r600_src
->neg
= tgsi_src
->Register
.Negate
;
556 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
560 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
561 const struct tgsi_full_dst_register
*tgsi_dst
,
563 struct r600_bc_alu_dst
*r600_dst
)
565 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
567 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
568 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
569 r600_dst
->chan
= swizzle
;
571 if (inst
->Instruction
.Saturate
) {
577 static unsigned tgsi_chan(const struct tgsi_full_src_register
*tgsi_src
, unsigned swizzle
)
581 return tgsi_src
->Register
.SwizzleX
;
583 return tgsi_src
->Register
.SwizzleY
;
585 return tgsi_src
->Register
.SwizzleZ
;
587 return tgsi_src
->Register
.SwizzleW
;
593 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
595 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
596 struct r600_bc_alu alu
;
597 int i
, j
, k
, nconst
, r
;
599 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
600 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
603 r
= tgsi_src(ctx
, &inst
->Src
[i
], &r600_src
[i
]);
608 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
609 if (inst
->Src
[j
].Register
.File
== TGSI_FILE_CONSTANT
&& j
> 0) {
610 for (k
= 0; k
< 4; k
++) {
611 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
612 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
613 alu
.src
[0].sel
= r600_src
[0].sel
;
615 alu
.dst
.sel
= ctx
->temp_reg
+ j
;
620 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
624 r600_src
[0].sel
= ctx
->temp_reg
+ j
;
631 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
633 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
634 struct r600_bc_alu_src r600_src
[3];
635 struct r600_bc_alu alu
;
638 r
= tgsi_split_constant(ctx
, r600_src
);
641 for (i
= 0; i
< 4; i
++) {
642 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
643 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
644 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
647 alu
.inst
= ctx
->inst_info
->r600_opcode
;
648 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
649 alu
.src
[j
] = r600_src
[j
];
650 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
652 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
656 /* handle some special cases */
657 switch (ctx
->inst_info
->tgsi_opcode
) {
658 case TGSI_OPCODE_SUB
:
661 case TGSI_OPCODE_ABS
:
670 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
677 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
679 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
680 struct r600_bc_alu alu
;
683 for (i
= 0; i
< 4; i
++) {
684 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
685 alu
.inst
= ctx
->inst_info
->r600_opcode
;
687 alu
.src
[0].sel
= 248;
688 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
691 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
695 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
702 static int tgsi_slt(struct r600_shader_ctx
*ctx
)
704 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
705 struct r600_bc_alu_src r600_src
[3];
706 struct r600_bc_alu alu
;
709 r
= tgsi_split_constant(ctx
, r600_src
);
712 for (i
= 0; i
< 4; i
++) {
713 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
714 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
715 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
718 alu
.inst
= ctx
->inst_info
->r600_opcode
;
719 alu
.src
[1] = r600_src
[0];
720 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
721 alu
.src
[0] = r600_src
[1];
722 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
723 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
730 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
737 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
739 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
740 struct r600_bc_alu alu
;
744 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
745 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
746 alu
.src
[0].sel
= 249; /*1.0*/
748 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
751 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
752 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
756 /* dst.y = max(src.x, 0.0) */
757 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
758 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
;
759 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
762 alu
.src
[1].sel
= 248; /*0.0*/
763 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 0);
764 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
767 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
768 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
772 /* dst.z = NOP - fill Z slot */
773 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
774 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
776 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
781 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
782 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
783 alu
.src
[0].sel
= 249;
785 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
788 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
790 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
794 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
799 /* dst.z = log(src.y) */
800 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
801 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
;
802 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
805 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
806 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
810 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
817 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
818 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
819 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
820 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
823 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
824 alu
.src
[1].sel
= sel
;
825 alu
.src
[1].chan
= chan
;
826 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[2]);
829 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], 0);
830 alu
.dst
.sel
= ctx
->temp_reg
;
835 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
839 /* dst.z = exp(tmp.x) */
840 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
841 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
842 alu
.src
[0].sel
= ctx
->temp_reg
;
844 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
848 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
855 static int tgsi_trans(struct r600_shader_ctx
*ctx
)
857 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
858 struct r600_bc_alu alu
;
861 for (i
= 0; i
< 4; i
++) {
862 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
863 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
864 alu
.inst
= ctx
->inst_info
->r600_opcode
;
865 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
866 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
869 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
871 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
875 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
883 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
885 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
886 struct r600_bc_alu alu
;
889 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
890 alu
.inst
= ctx
->inst_info
->r600_opcode
;
891 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
892 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
895 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], 0);
897 alu
.dst
.sel
= ctx
->temp_reg
;
900 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
903 /* replicate result */
904 for (i
= 0; i
< 4; i
++) {
905 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
906 alu
.src
[0].sel
= ctx
->temp_reg
;
907 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
909 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
912 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
915 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
922 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
924 struct r600_bc_alu alu
;
927 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
930 for (i
= 0; i
< 4; i
++) {
931 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
932 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
933 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
936 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
937 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
940 alu
.src
[0].sel
= ctx
->temp_reg
;
946 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
953 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
955 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
956 struct r600_bc_alu_src r600_src
[3];
957 struct r600_bc_alu alu
;
960 r
= tgsi_split_constant(ctx
, r600_src
);
963 /* do it in 2 step as op3 doesn't support writemask */
964 for (i
= 0; i
< 4; i
++) {
965 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
966 alu
.inst
= ctx
->inst_info
->r600_opcode
;
967 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
968 alu
.src
[j
] = r600_src
[j
];
969 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
971 alu
.dst
.sel
= ctx
->temp_reg
;
978 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
982 return tgsi_helper_copy(ctx
, inst
);
985 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
987 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
988 struct r600_bc_alu_src r600_src
[3];
989 struct r600_bc_alu alu
;
992 r
= tgsi_split_constant(ctx
, r600_src
);
995 for (i
= 0; i
< 4; i
++) {
996 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
997 alu
.inst
= ctx
->inst_info
->r600_opcode
;
998 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
999 alu
.src
[j
] = r600_src
[j
];
1000 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1002 alu
.dst
.sel
= ctx
->temp_reg
;
1005 /* handle some special cases */
1006 switch (ctx
->inst_info
->tgsi_opcode
) {
1007 case TGSI_OPCODE_DP2
:
1009 alu
.src
[0].sel
= alu
.src
[1].sel
= 248;
1010 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1013 case TGSI_OPCODE_DP3
:
1015 alu
.src
[0].sel
= alu
.src
[1].sel
= 248;
1016 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1025 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1029 return tgsi_helper_copy(ctx
, inst
);
1032 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1034 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1035 struct r600_bc_tex tex
;
1036 struct r600_bc_alu alu
;
1040 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1042 /* Add perspective divide */
1043 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1044 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
1045 alu
.src
[0].sel
= src_gpr
;
1046 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1047 alu
.dst
.sel
= ctx
->temp_reg
;
1051 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1055 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1056 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1057 alu
.src
[0].sel
= ctx
->temp_reg
;
1058 alu
.src
[0].chan
= 3;
1059 alu
.src
[1].sel
= src_gpr
;
1060 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 0);
1061 alu
.dst
.sel
= ctx
->temp_reg
;
1064 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1067 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1068 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1069 alu
.src
[0].sel
= ctx
->temp_reg
;
1070 alu
.src
[0].chan
= 3;
1071 alu
.src
[1].sel
= src_gpr
;
1072 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 1);
1073 alu
.dst
.sel
= ctx
->temp_reg
;
1076 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1079 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1080 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1081 alu
.src
[0].sel
= ctx
->temp_reg
;
1082 alu
.src
[0].chan
= 3;
1083 alu
.src
[1].sel
= src_gpr
;
1084 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 2);
1085 alu
.dst
.sel
= ctx
->temp_reg
;
1088 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1091 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1092 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1093 alu
.src
[0].sel
= 249;
1094 alu
.src
[0].chan
= 0;
1095 alu
.dst
.sel
= ctx
->temp_reg
;
1099 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1102 src_gpr
= ctx
->temp_reg
;
1104 /* TODO use temp if src_gpr is not a temporary reg (File != TEMPORARY) */
1105 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1106 tex
.inst
= ctx
->inst_info
->r600_opcode
;
1107 tex
.resource_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1108 tex
.sampler_id
= tex
.resource_id
;
1109 tex
.src_gpr
= src_gpr
;
1110 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1120 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1121 tex
.coord_type_x
= 1;
1122 tex
.coord_type_y
= 1;
1123 tex
.coord_type_z
= 1;
1124 tex
.coord_type_w
= 1;
1126 return r600_bc_add_tex(ctx
->bc
, &tex
);
1129 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1131 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1132 struct r600_bc_alu_src r600_src
[3];
1133 struct r600_bc_alu alu
;
1137 r
= tgsi_split_constant(ctx
, r600_src
);
1141 for (i
= 0; i
< 4; i
++) {
1142 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1143 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
;
1144 alu
.src
[0].sel
= 249;
1145 alu
.src
[0].chan
= 0;
1146 alu
.src
[1] = r600_src
[0];
1147 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1149 alu
.dst
.sel
= ctx
->temp_reg
;
1155 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1159 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1163 /* (1 - src0) * src2 */
1164 for (i
= 0; i
< 4; i
++) {
1165 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1166 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1167 alu
.src
[0].sel
= ctx
->temp_reg
;
1168 alu
.src
[0].chan
= i
;
1169 alu
.src
[1] = r600_src
[2];
1170 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1171 alu
.dst
.sel
= ctx
->temp_reg
;
1177 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1181 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1185 /* src0 * src1 + (1 - src0) * src2 */
1186 for (i
= 0; i
< 4; i
++) {
1187 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1188 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1190 alu
.src
[0] = r600_src
[0];
1191 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1192 alu
.src
[1] = r600_src
[1];
1193 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
1194 alu
.src
[2].sel
= ctx
->temp_reg
;
1195 alu
.src
[2].chan
= i
;
1196 alu
.dst
.sel
= ctx
->temp_reg
;
1201 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1205 return tgsi_helper_copy(ctx
, inst
);
1208 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
1209 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1210 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1211 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
1212 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
1213 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
1214 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1215 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1216 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
1217 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1218 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1219 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1220 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1221 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
1222 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
1223 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_slt
},
1224 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1225 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
1226 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1227 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
1228 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1230 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1231 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1233 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1234 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1235 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1236 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1237 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1238 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1239 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
1240 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1241 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1242 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1244 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1245 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1246 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1247 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1248 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1249 {TGSI_OPCODE_DDX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1250 {TGSI_OPCODE_DDY
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1251 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
}, /* predicated kill */
1252 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1253 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1254 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1255 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1256 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1257 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1258 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1259 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1260 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1261 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1262 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1263 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1264 {TGSI_OPCODE_TEX
, 0, 0x10, tgsi_tex
},
1265 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1266 {TGSI_OPCODE_TXP
, 0, 0x10, tgsi_tex
},
1267 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1268 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1269 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1270 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1271 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1272 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1273 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1274 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1275 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1276 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1277 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
}, /* SGN */
1278 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1279 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1280 {TGSI_OPCODE_TXB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1281 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1282 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1283 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1284 {TGSI_OPCODE_TXL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1285 {TGSI_OPCODE_BRK
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1286 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1288 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1289 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1290 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1291 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1293 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1294 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1295 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1296 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1297 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1298 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1299 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1300 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1301 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1303 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1304 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1305 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1306 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1307 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1308 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1309 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1310 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1311 {TGSI_OPCODE_CONT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1312 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1313 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1314 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1315 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1316 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1317 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1319 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1320 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1321 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1322 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1323 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1325 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1326 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1327 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1328 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1329 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1330 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1331 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1332 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1333 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
1334 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
1336 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1337 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1338 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1339 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1340 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1341 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1342 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1343 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1344 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1345 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1346 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1347 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1348 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1349 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1350 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1351 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1352 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1353 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1354 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1355 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1356 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1357 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1358 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1359 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1360 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1361 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1362 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1363 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},