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r600: Correct IDIV if DST and SRC use the same temporary
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm;
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193 use_sb &= (shader->shader.processor_type != PIPE_SHADER_COMPUTE);
194
195 /* disable SB for shaders using doubles */
196 use_sb &= !shader->shader.uses_doubles;
197
198 use_sb &= !shader->shader.uses_atomics;
199 use_sb &= !shader->shader.uses_images;
200 use_sb &= !shader->shader.uses_helper_invocation;
201
202 /* Check if the bytecode has already been built. */
203 if (!shader->shader.bc.bytecode) {
204 r = r600_bytecode_build(&shader->shader.bc);
205 if (r) {
206 R600_ERR("building bytecode failed !\n");
207 goto error;
208 }
209 }
210
211 sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
212 if (dump && !sb_disasm) {
213 fprintf(stderr, "--------------------------------------------------------------\n");
214 r600_bytecode_disasm(&shader->shader.bc);
215 fprintf(stderr, "______________________________________________________________\n");
216 } else if ((dump && sb_disasm) || use_sb) {
217 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
218 dump, use_sb);
219 if (r) {
220 R600_ERR("r600_sb_bytecode_process failed !\n");
221 goto error;
222 }
223 }
224
225 if (shader->gs_copy_shader) {
226 if (dump) {
227 // dump copy shader
228 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
229 &shader->gs_copy_shader->shader, dump, 0);
230 if (r)
231 goto error;
232 }
233
234 if ((r = store_shader(ctx, shader->gs_copy_shader)))
235 goto error;
236 }
237
238 /* Store the shader in a buffer. */
239 if ((r = store_shader(ctx, shader)))
240 goto error;
241
242 /* Build state. */
243 switch (shader->shader.processor_type) {
244 case PIPE_SHADER_TESS_CTRL:
245 evergreen_update_hs_state(ctx, shader);
246 break;
247 case PIPE_SHADER_TESS_EVAL:
248 if (key.tes.as_es)
249 evergreen_update_es_state(ctx, shader);
250 else
251 evergreen_update_vs_state(ctx, shader);
252 break;
253 case PIPE_SHADER_GEOMETRY:
254 if (rctx->b.chip_class >= EVERGREEN) {
255 evergreen_update_gs_state(ctx, shader);
256 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
257 } else {
258 r600_update_gs_state(ctx, shader);
259 r600_update_vs_state(ctx, shader->gs_copy_shader);
260 }
261 break;
262 case PIPE_SHADER_VERTEX:
263 export_shader = key.vs.as_es;
264 if (rctx->b.chip_class >= EVERGREEN) {
265 if (key.vs.as_ls)
266 evergreen_update_ls_state(ctx, shader);
267 else if (key.vs.as_es)
268 evergreen_update_es_state(ctx, shader);
269 else
270 evergreen_update_vs_state(ctx, shader);
271 } else {
272 if (export_shader)
273 r600_update_es_state(ctx, shader);
274 else
275 r600_update_vs_state(ctx, shader);
276 }
277 break;
278 case PIPE_SHADER_FRAGMENT:
279 if (rctx->b.chip_class >= EVERGREEN) {
280 evergreen_update_ps_state(ctx, shader);
281 } else {
282 r600_update_ps_state(ctx, shader);
283 }
284 break;
285 case PIPE_SHADER_COMPUTE:
286 evergreen_update_ls_state(ctx, shader);
287 break;
288 default:
289 r = -EINVAL;
290 goto error;
291 }
292 return 0;
293
294 error:
295 r600_pipe_shader_destroy(ctx, shader);
296 return r;
297 }
298
299 void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
300 {
301 r600_resource_reference(&shader->bo, NULL);
302 r600_bytecode_clear(&shader->shader.bc);
303 r600_release_command_buffer(&shader->command_buffer);
304 }
305
306 /*
307 * tgsi -> r600 shader
308 */
309 struct r600_shader_tgsi_instruction;
310
311 struct r600_shader_src {
312 unsigned sel;
313 unsigned swizzle[4];
314 unsigned neg;
315 unsigned abs;
316 unsigned rel;
317 unsigned kc_bank;
318 boolean kc_rel; /* true if cache bank is indexed */
319 uint32_t value[4];
320 };
321
322 struct eg_interp {
323 boolean enabled;
324 unsigned ij_index;
325 };
326
327 struct r600_shader_ctx {
328 struct tgsi_shader_info info;
329 struct tgsi_array_info *array_infos;
330 /* flag for each tgsi temp array if its been spilled or not */
331 bool *spilled_arrays;
332 struct tgsi_parse_context parse;
333 const struct tgsi_token *tokens;
334 unsigned type;
335 unsigned file_offset[TGSI_FILE_COUNT];
336 unsigned temp_reg;
337 const struct r600_shader_tgsi_instruction *inst_info;
338 struct r600_bytecode *bc;
339 struct r600_shader *shader;
340 struct r600_shader_src src[4];
341 uint32_t *literals;
342 uint32_t nliterals;
343 uint32_t max_driver_temp_used;
344 /* needed for evergreen interpolation */
345 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
346 /* evergreen/cayman also store sample mask in face register */
347 int face_gpr;
348 /* sample id is .w component stored in fixed point position register */
349 int fixed_pt_position_gpr;
350 int colors_used;
351 boolean clip_vertex_write;
352 unsigned cv_output;
353 unsigned edgeflag_output;
354 int helper_invoc_reg;
355 int cs_block_size_reg;
356 int cs_grid_size_reg;
357 bool cs_block_size_loaded, cs_grid_size_loaded;
358 int fragcoord_input;
359 int next_ring_offset;
360 int gs_out_ring_offset;
361 int gs_next_vertex;
362 struct r600_shader *gs_for_vs;
363 int gs_export_gpr_tregs[4];
364 int gs_rotated_input[2];
365 const struct pipe_stream_output_info *gs_stream_output_info;
366 unsigned enabled_stream_buffers_mask;
367 unsigned tess_input_info; /* temp with tess input offsets */
368 unsigned tess_output_info; /* temp with tess input offsets */
369 unsigned thread_id_gpr; /* temp with thread id calculated for images */
370 };
371
372 struct r600_shader_tgsi_instruction {
373 unsigned op;
374 int (*process)(struct r600_shader_ctx *ctx);
375 };
376
377 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
378 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
379 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
380 static inline int callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
381 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
382 static int tgsi_else(struct r600_shader_ctx *ctx);
383 static int tgsi_endif(struct r600_shader_ctx *ctx);
384 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
385 static int tgsi_endloop(struct r600_shader_ctx *ctx);
386 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
387 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
388 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
389 unsigned int dst_reg);
390 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
391 const struct r600_shader_src *shader_src,
392 unsigned chan);
393 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
394 unsigned dst_reg, unsigned mask);
395
396 static bool ctx_needs_stack_workaround_8xx(struct r600_shader_ctx *ctx)
397 {
398 if (ctx->bc->family == CHIP_HEMLOCK ||
399 ctx->bc->family == CHIP_CYPRESS ||
400 ctx->bc->family == CHIP_JUNIPER)
401 return false;
402 return true;
403 }
404
405 static int tgsi_last_instruction(unsigned writemask)
406 {
407 int i, lasti = 0;
408
409 for (i = 0; i < 4; i++) {
410 if (writemask & (1 << i)) {
411 lasti = i;
412 }
413 }
414 return lasti;
415 }
416
417 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
418 {
419 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
420 unsigned j;
421
422 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
423 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
424 return -EINVAL;
425 }
426 #if 0
427 if (i->Instruction.Label) {
428 R600_ERR("label unsupported\n");
429 return -EINVAL;
430 }
431 #endif
432 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
433 if (i->Src[j].Register.Dimension) {
434 switch (i->Src[j].Register.File) {
435 case TGSI_FILE_CONSTANT:
436 case TGSI_FILE_HW_ATOMIC:
437 break;
438 case TGSI_FILE_INPUT:
439 if (ctx->type == PIPE_SHADER_GEOMETRY ||
440 ctx->type == PIPE_SHADER_TESS_CTRL ||
441 ctx->type == PIPE_SHADER_TESS_EVAL)
442 break;
443 case TGSI_FILE_OUTPUT:
444 if (ctx->type == PIPE_SHADER_TESS_CTRL)
445 break;
446 default:
447 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
448 i->Src[j].Register.File,
449 i->Src[j].Register.Dimension);
450 return -EINVAL;
451 }
452 }
453 }
454 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
455 if (i->Dst[j].Register.Dimension) {
456 if (ctx->type == PIPE_SHADER_TESS_CTRL)
457 continue;
458 R600_ERR("unsupported dst (dimension)\n");
459 return -EINVAL;
460 }
461 }
462 return 0;
463 }
464
465 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
466 {
467 if (interpolate == TGSI_INTERPOLATE_COLOR ||
468 interpolate == TGSI_INTERPOLATE_LINEAR ||
469 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
470 {
471 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
472 int loc;
473
474 switch(location) {
475 case TGSI_INTERPOLATE_LOC_CENTER:
476 loc = 1;
477 break;
478 case TGSI_INTERPOLATE_LOC_CENTROID:
479 loc = 2;
480 break;
481 case TGSI_INTERPOLATE_LOC_SAMPLE:
482 default:
483 loc = 0; break;
484 }
485
486 return is_linear * 3 + loc;
487 }
488
489 return -1;
490 }
491
492 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
493 int input)
494 {
495 int i = eg_get_interpolator_index(
496 ctx->shader->input[input].interpolate,
497 ctx->shader->input[input].interpolate_location);
498 assert(i >= 0);
499 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
500 }
501
502 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
503 {
504 int i, r;
505 struct r600_bytecode_alu alu;
506 int gpr = 0, base_chan = 0;
507 int ij_index = ctx->shader->input[input].ij_index;
508
509 /* work out gpr and base_chan from index */
510 gpr = ij_index / 2;
511 base_chan = (2 * (ij_index % 2)) + 1;
512
513 for (i = 0; i < 8; i++) {
514 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
515
516 if (i < 4)
517 alu.op = ALU_OP2_INTERP_ZW;
518 else
519 alu.op = ALU_OP2_INTERP_XY;
520
521 if ((i > 1) && (i < 6)) {
522 alu.dst.sel = ctx->shader->input[input].gpr;
523 alu.dst.write = 1;
524 }
525
526 alu.dst.chan = i % 4;
527
528 alu.src[0].sel = gpr;
529 alu.src[0].chan = (base_chan - (i % 2));
530
531 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
532
533 alu.bank_swizzle_force = SQ_ALU_VEC_210;
534 if ((i % 4) == 3)
535 alu.last = 1;
536 r = r600_bytecode_add_alu(ctx->bc, &alu);
537 if (r)
538 return r;
539 }
540 return 0;
541 }
542
543 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
544 {
545 int i, r;
546 struct r600_bytecode_alu alu;
547
548 for (i = 0; i < 4; i++) {
549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
550
551 alu.op = ALU_OP1_INTERP_LOAD_P0;
552
553 alu.dst.sel = ctx->shader->input[input].gpr;
554 alu.dst.write = 1;
555
556 alu.dst.chan = i;
557
558 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
559 alu.src[0].chan = i;
560
561 if (i == 3)
562 alu.last = 1;
563 r = r600_bytecode_add_alu(ctx->bc, &alu);
564 if (r)
565 return r;
566 }
567 return 0;
568 }
569
570 /*
571 * Special export handling in shaders
572 *
573 * shader export ARRAY_BASE for EXPORT_POS:
574 * 60 is position
575 * 61 is misc vector
576 * 62, 63 are clip distance vectors
577 *
578 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
579 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
580 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
581 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
582 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
583 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
584 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
585 * exclusive from render target index)
586 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
587 *
588 *
589 * shader export ARRAY_BASE for EXPORT_PIXEL:
590 * 0-7 CB targets
591 * 61 computed Z vector
592 *
593 * The use of the values exported in the computed Z vector are controlled
594 * by DB_SHADER_CONTROL:
595 * Z_EXPORT_ENABLE - Z as a float in RED
596 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
597 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
598 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
599 * DB_SOURCE_FORMAT - export control restrictions
600 *
601 */
602
603
604 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
605 static int r600_spi_sid(struct r600_shader_io * io)
606 {
607 int index, name = io->name;
608
609 /* These params are handled differently, they don't need
610 * semantic indices, so we'll use 0 for them.
611 */
612 if (name == TGSI_SEMANTIC_POSITION ||
613 name == TGSI_SEMANTIC_PSIZE ||
614 name == TGSI_SEMANTIC_EDGEFLAG ||
615 name == TGSI_SEMANTIC_FACE ||
616 name == TGSI_SEMANTIC_SAMPLEMASK)
617 index = 0;
618 else {
619 if (name == TGSI_SEMANTIC_GENERIC) {
620 /* For generic params simply use sid from tgsi */
621 index = io->sid;
622 } else {
623 /* For non-generic params - pack name and sid into 8 bits */
624 index = 0x80 | (name<<3) | (io->sid);
625 }
626
627 /* Make sure that all really used indices have nonzero value, so
628 * we can just compare it to 0 later instead of comparing the name
629 * with different values to detect special cases. */
630 index++;
631 }
632
633 return index;
634 };
635
636 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
637 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
638 {
639 switch (semantic_name) {
640 case TGSI_SEMANTIC_POSITION:
641 return 0;
642 case TGSI_SEMANTIC_PSIZE:
643 return 1;
644 case TGSI_SEMANTIC_CLIPDIST:
645 assert(index <= 1);
646 return 2 + index;
647 case TGSI_SEMANTIC_GENERIC:
648 if (index <= 63-4)
649 return 4 + index - 9;
650 else
651 /* same explanation as in the default statement,
652 * the only user hitting this is st/nine.
653 */
654 return 0;
655
656 /* patch indices are completely separate and thus start from 0 */
657 case TGSI_SEMANTIC_TESSOUTER:
658 return 0;
659 case TGSI_SEMANTIC_TESSINNER:
660 return 1;
661 case TGSI_SEMANTIC_PATCH:
662 return 2 + index;
663
664 default:
665 /* Don't fail here. The result of this function is only used
666 * for LS, TCS, TES, and GS, where legacy GL semantics can't
667 * occur, but this function is called for all vertex shaders
668 * before it's known whether LS will be compiled or not.
669 */
670 return 0;
671 }
672 }
673
674 /* turn input into interpolate on EG */
675 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
676 {
677 int r = 0;
678
679 if (ctx->shader->input[index].spi_sid) {
680 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
681 if (ctx->shader->input[index].interpolate > 0) {
682 evergreen_interp_assign_ij_index(ctx, index);
683 r = evergreen_interp_alu(ctx, index);
684 } else {
685 r = evergreen_interp_flat(ctx, index);
686 }
687 }
688 return r;
689 }
690
691 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
692 {
693 struct r600_bytecode_alu alu;
694 int i, r;
695 int gpr_front = ctx->shader->input[front].gpr;
696 int gpr_back = ctx->shader->input[back].gpr;
697
698 for (i = 0; i < 4; i++) {
699 memset(&alu, 0, sizeof(alu));
700 alu.op = ALU_OP3_CNDGT;
701 alu.is_op3 = 1;
702 alu.dst.write = 1;
703 alu.dst.sel = gpr_front;
704 alu.src[0].sel = ctx->face_gpr;
705 alu.src[1].sel = gpr_front;
706 alu.src[2].sel = gpr_back;
707
708 alu.dst.chan = i;
709 alu.src[1].chan = i;
710 alu.src[2].chan = i;
711 alu.last = (i==3);
712
713 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
714 return r;
715 }
716
717 return 0;
718 }
719
720 /* execute a single slot ALU calculation */
721 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
722 int dst_sel, int dst_chan,
723 int src0_sel, unsigned src0_chan_val,
724 int src1_sel, unsigned src1_chan_val)
725 {
726 struct r600_bytecode_alu alu;
727 int r, i;
728
729 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
730 for (i = 0; i < 4; i++) {
731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
732 alu.op = op;
733 alu.src[0].sel = src0_sel;
734 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
735 alu.src[0].value = src0_chan_val;
736 else
737 alu.src[0].chan = src0_chan_val;
738 alu.src[1].sel = src1_sel;
739 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
740 alu.src[1].value = src1_chan_val;
741 else
742 alu.src[1].chan = src1_chan_val;
743 alu.dst.sel = dst_sel;
744 alu.dst.chan = i;
745 alu.dst.write = i == dst_chan;
746 alu.last = (i == 3);
747 r = r600_bytecode_add_alu(ctx->bc, &alu);
748 if (r)
749 return r;
750 }
751 return 0;
752 }
753
754 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
755 alu.op = op;
756 alu.src[0].sel = src0_sel;
757 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
758 alu.src[0].value = src0_chan_val;
759 else
760 alu.src[0].chan = src0_chan_val;
761 alu.src[1].sel = src1_sel;
762 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
763 alu.src[1].value = src1_chan_val;
764 else
765 alu.src[1].chan = src1_chan_val;
766 alu.dst.sel = dst_sel;
767 alu.dst.chan = dst_chan;
768 alu.dst.write = 1;
769 alu.last = 1;
770 r = r600_bytecode_add_alu(ctx->bc, &alu);
771 if (r)
772 return r;
773 return 0;
774 }
775
776 /* execute a single slot ALU calculation */
777 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
778 int dst_sel, int dst_chan,
779 int src0_sel, unsigned src0_chan_val,
780 int src1_sel, unsigned src1_chan_val,
781 int src2_sel, unsigned src2_chan_val)
782 {
783 struct r600_bytecode_alu alu;
784 int r;
785
786 /* validate this for other ops */
787 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT || op == ALU_OP3_BFE_UINT);
788 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
789 alu.op = op;
790 alu.src[0].sel = src0_sel;
791 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
792 alu.src[0].value = src0_chan_val;
793 else
794 alu.src[0].chan = src0_chan_val;
795 alu.src[1].sel = src1_sel;
796 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
797 alu.src[1].value = src1_chan_val;
798 else
799 alu.src[1].chan = src1_chan_val;
800 alu.src[2].sel = src2_sel;
801 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
802 alu.src[2].value = src2_chan_val;
803 else
804 alu.src[2].chan = src2_chan_val;
805 alu.dst.sel = dst_sel;
806 alu.dst.chan = dst_chan;
807 alu.is_op3 = 1;
808 alu.last = 1;
809 r = r600_bytecode_add_alu(ctx->bc, &alu);
810 if (r)
811 return r;
812 return 0;
813 }
814
815 /* put it in temp_reg.x */
816 static int get_lds_offset0(struct r600_shader_ctx *ctx,
817 int rel_patch_chan,
818 int temp_reg, bool is_patch_var)
819 {
820 int r;
821
822 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
823 /* ADD
824 Dimension - patch0_offset (input_vals.z),
825 Non-dim - patch0_data_offset (input_vals.w)
826 */
827 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
828 temp_reg, 0,
829 ctx->tess_output_info, 0,
830 0, rel_patch_chan,
831 ctx->tess_output_info, is_patch_var ? 3 : 2);
832 if (r)
833 return r;
834 return 0;
835 }
836
837 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
838 {
839 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
840 }
841
842 static int r600_get_temp(struct r600_shader_ctx *ctx)
843 {
844 return ctx->temp_reg + ctx->max_driver_temp_used++;
845 }
846
847 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
848 {
849 int i;
850 i = ctx->shader->noutput++;
851 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
852 ctx->shader->output[i].sid = 0;
853 ctx->shader->output[i].gpr = 0;
854 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
855 ctx->shader->output[i].write_mask = 0x4;
856 ctx->shader->output[i].spi_sid = prim_id_sid;
857
858 return 0;
859 }
860
861 static int tgsi_barrier(struct r600_shader_ctx *ctx)
862 {
863 struct r600_bytecode_alu alu;
864 int r;
865
866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
867 alu.op = ctx->inst_info->op;
868 alu.last = 1;
869
870 r = r600_bytecode_add_alu(ctx->bc, &alu);
871 if (r)
872 return r;
873 return 0;
874 }
875
876 static void choose_spill_arrays(struct r600_shader_ctx *ctx, int *regno, unsigned *scratch_space_needed)
877 {
878 // pick largest array and spill it, repeat until the number of temps is under limit or we run out of arrays
879 unsigned n = ctx->info.array_max[TGSI_FILE_TEMPORARY];
880 unsigned narrays_left = n;
881 bool *spilled = ctx->spilled_arrays; // assumed calloc:ed
882
883 *scratch_space_needed = 0;
884 while (*regno > 124 && narrays_left) {
885 unsigned i;
886 unsigned largest = 0;
887 unsigned largest_index = 0;
888
889 for (i = 0; i < n; i++) {
890 unsigned size = ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
891 if (!spilled[i] && size > largest) {
892 largest = size;
893 largest_index = i;
894 }
895 }
896
897 spilled[largest_index] = true;
898 *regno -= largest;
899 *scratch_space_needed += largest;
900
901 narrays_left --;
902 }
903
904 if (narrays_left == 0) {
905 ctx->info.indirect_files &= ~(1 << TGSI_FILE_TEMPORARY);
906 }
907 }
908
909 /* Take spilled temp arrays into account when translating tgsi register
910 * indexes into r600 gprs if spilled is false, or scratch array offset if
911 * spilled is true */
912 static int map_tgsi_reg_index_to_r600_gpr(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index, bool *spilled)
913 {
914 unsigned i;
915 unsigned spilled_size = 0;
916
917 for (i = 0; i < ctx->info.array_max[TGSI_FILE_TEMPORARY]; i++) {
918 if (tgsi_reg_index >= ctx->array_infos[i].range.First && tgsi_reg_index <= ctx->array_infos[i].range.Last) {
919 if (ctx->spilled_arrays[i]) {
920 /* vec4 index into spilled scratch memory */
921 *spilled = true;
922 return tgsi_reg_index - ctx->array_infos[i].range.First + spilled_size;
923 }
924 else {
925 /* regular GPR array */
926 *spilled = false;
927 return tgsi_reg_index - spilled_size + ctx->file_offset[TGSI_FILE_TEMPORARY];
928 }
929 }
930
931 if (tgsi_reg_index < ctx->array_infos[i].range.First)
932 break;
933 if (ctx->spilled_arrays[i]) {
934 spilled_size += ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
935 }
936 }
937
938 /* regular GPR index, minus the holes from spilled arrays */
939 *spilled = false;
940
941 return tgsi_reg_index - spilled_size + ctx->file_offset[TGSI_FILE_TEMPORARY];
942 }
943
944 /* look up spill area base offset and array size for a spilled temp array */
945 static void get_spilled_array_base_and_size(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index,
946 unsigned *array_base, unsigned *array_size)
947 {
948 unsigned i;
949 unsigned offset = 0;
950
951 for (i = 0; i < ctx->info.array_max[TGSI_FILE_TEMPORARY]; i++) {
952 if (ctx->spilled_arrays[i]) {
953 unsigned size = ctx->array_infos[i].range.Last - ctx->array_infos[i].range.First + 1;
954
955 if (tgsi_reg_index >= ctx->array_infos[i].range.First && tgsi_reg_index <= ctx->array_infos[i].range.Last) {
956 *array_base = offset;
957 *array_size = size - 1; /* hw counts from 1 */
958
959 return;
960 }
961
962 offset += size;
963 }
964 }
965 }
966
967 static int tgsi_declaration(struct r600_shader_ctx *ctx)
968 {
969 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
970 int r, i, j, count = d->Range.Last - d->Range.First + 1;
971
972 switch (d->Declaration.File) {
973 case TGSI_FILE_INPUT:
974 for (j = 0; j < count; j++) {
975 i = ctx->shader->ninput + j;
976 assert(i < ARRAY_SIZE(ctx->shader->input));
977 ctx->shader->input[i].name = d->Semantic.Name;
978 ctx->shader->input[i].sid = d->Semantic.Index + j;
979 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
980 ctx->shader->input[i].interpolate_location = d->Interp.Location;
981 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
982 if (ctx->type == PIPE_SHADER_FRAGMENT) {
983 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
984 switch (ctx->shader->input[i].name) {
985 case TGSI_SEMANTIC_FACE:
986 if (ctx->face_gpr != -1)
987 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
988 else
989 ctx->face_gpr = ctx->shader->input[i].gpr;
990 break;
991 case TGSI_SEMANTIC_COLOR:
992 ctx->colors_used++;
993 break;
994 case TGSI_SEMANTIC_POSITION:
995 ctx->fragcoord_input = i;
996 break;
997 case TGSI_SEMANTIC_PRIMID:
998 /* set this for now */
999 ctx->shader->gs_prim_id_input = true;
1000 ctx->shader->ps_prim_id_input = i;
1001 break;
1002 }
1003 if (ctx->bc->chip_class >= EVERGREEN) {
1004 if ((r = evergreen_interp_input(ctx, i)))
1005 return r;
1006 }
1007 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
1008 /* FIXME probably skip inputs if they aren't passed in the ring */
1009 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
1010 ctx->next_ring_offset += 16;
1011 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
1012 ctx->shader->gs_prim_id_input = true;
1013 }
1014 }
1015 ctx->shader->ninput += count;
1016 break;
1017 case TGSI_FILE_OUTPUT:
1018 for (j = 0; j < count; j++) {
1019 i = ctx->shader->noutput + j;
1020 assert(i < ARRAY_SIZE(ctx->shader->output));
1021 ctx->shader->output[i].name = d->Semantic.Name;
1022 ctx->shader->output[i].sid = d->Semantic.Index + j;
1023 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
1024 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
1025 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
1026 if (ctx->type == PIPE_SHADER_VERTEX ||
1027 ctx->type == PIPE_SHADER_GEOMETRY ||
1028 ctx->type == PIPE_SHADER_TESS_EVAL) {
1029 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
1030 switch (d->Semantic.Name) {
1031 case TGSI_SEMANTIC_CLIPDIST:
1032 break;
1033 case TGSI_SEMANTIC_PSIZE:
1034 ctx->shader->vs_out_misc_write = 1;
1035 ctx->shader->vs_out_point_size = 1;
1036 break;
1037 case TGSI_SEMANTIC_EDGEFLAG:
1038 ctx->shader->vs_out_misc_write = 1;
1039 ctx->shader->vs_out_edgeflag = 1;
1040 ctx->edgeflag_output = i;
1041 break;
1042 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1043 ctx->shader->vs_out_misc_write = 1;
1044 ctx->shader->vs_out_viewport = 1;
1045 break;
1046 case TGSI_SEMANTIC_LAYER:
1047 ctx->shader->vs_out_misc_write = 1;
1048 ctx->shader->vs_out_layer = 1;
1049 break;
1050 case TGSI_SEMANTIC_CLIPVERTEX:
1051 ctx->clip_vertex_write = TRUE;
1052 ctx->cv_output = i;
1053 break;
1054 }
1055 if (ctx->type == PIPE_SHADER_GEOMETRY) {
1056 ctx->gs_out_ring_offset += 16;
1057 }
1058 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
1059 switch (d->Semantic.Name) {
1060 case TGSI_SEMANTIC_COLOR:
1061 ctx->shader->nr_ps_max_color_exports++;
1062 break;
1063 }
1064 }
1065 }
1066 ctx->shader->noutput += count;
1067 break;
1068 case TGSI_FILE_TEMPORARY:
1069 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
1070 if (d->Array.ArrayID) {
1071 bool spilled;
1072 unsigned idx = map_tgsi_reg_index_to_r600_gpr(ctx,
1073 d->Range.First,
1074 &spilled);
1075
1076 if (!spilled) {
1077 r600_add_gpr_array(ctx->shader, idx,
1078 d->Range.Last - d->Range.First + 1, 0x0F);
1079 }
1080 }
1081 }
1082 break;
1083
1084 case TGSI_FILE_CONSTANT:
1085 case TGSI_FILE_SAMPLER:
1086 case TGSI_FILE_SAMPLER_VIEW:
1087 case TGSI_FILE_ADDRESS:
1088 case TGSI_FILE_BUFFER:
1089 case TGSI_FILE_IMAGE:
1090 case TGSI_FILE_MEMORY:
1091 break;
1092
1093 case TGSI_FILE_HW_ATOMIC:
1094 i = ctx->shader->nhwatomic_ranges;
1095 ctx->shader->atomics[i].start = d->Range.First;
1096 ctx->shader->atomics[i].end = d->Range.Last;
1097 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
1098 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
1099 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
1100 ctx->shader->nhwatomic_ranges++;
1101 ctx->shader->nhwatomic += count;
1102 break;
1103
1104 case TGSI_FILE_SYSTEM_VALUE:
1105 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
1106 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
1107 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
1108 break; /* Already handled from allocate_system_value_inputs */
1109 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
1110 break;
1111 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1112 break;
1113 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1114 break;
1115 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1116 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1117 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1118 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1119 unsigned temp_reg = r600_get_temp(ctx);
1120
1121 r = get_lds_offset0(ctx, 2, temp_reg, true);
1122 if (r)
1123 return r;
1124
1125 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1126 temp_reg, 0,
1127 temp_reg, 0,
1128 V_SQ_ALU_SRC_LITERAL, param * 16);
1129 if (r)
1130 return r;
1131
1132 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
1133 }
1134 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1135 /* MOV r1.x, r0.x;
1136 MOV r1.y, r0.y;
1137 */
1138 for (i = 0; i < 2; i++) {
1139 struct r600_bytecode_alu alu;
1140 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1141 alu.op = ALU_OP1_MOV;
1142 alu.src[0].sel = 0;
1143 alu.src[0].chan = 0 + i;
1144 alu.dst.sel = 1;
1145 alu.dst.chan = 0 + i;
1146 alu.dst.write = 1;
1147 alu.last = (i == 1) ? 1 : 0;
1148 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1149 return r;
1150 }
1151 /* ADD r1.z, 1.0f, -r0.x */
1152 struct r600_bytecode_alu alu;
1153 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1154 alu.op = ALU_OP2_ADD;
1155 alu.src[0].sel = V_SQ_ALU_SRC_1;
1156 alu.src[1].sel = 1;
1157 alu.src[1].chan = 0;
1158 alu.src[1].neg = 1;
1159 alu.dst.sel = 1;
1160 alu.dst.chan = 2;
1161 alu.dst.write = 1;
1162 alu.last = 1;
1163 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1164 return r;
1165
1166 /* ADD r1.z, r1.z, -r1.y */
1167 alu.op = ALU_OP2_ADD;
1168 alu.src[0].sel = 1;
1169 alu.src[0].chan = 2;
1170 alu.src[1].sel = 1;
1171 alu.src[1].chan = 1;
1172 alu.src[1].neg = 1;
1173 alu.dst.sel = 1;
1174 alu.dst.chan = 2;
1175 alu.dst.write = 1;
1176 alu.last = 1;
1177 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1178 return r;
1179 break;
1180 }
1181 break;
1182 default:
1183 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1184 return -EINVAL;
1185 }
1186 return 0;
1187 }
1188
1189 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1190 {
1191 struct tgsi_parse_context parse;
1192 struct {
1193 boolean enabled;
1194 int *reg;
1195 unsigned name, alternate_name;
1196 } inputs[2] = {
1197 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1198
1199 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1200 };
1201 int num_regs = 0;
1202 unsigned k, i;
1203
1204 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1205 return 0;
1206 }
1207
1208 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1209 while (!tgsi_parse_end_of_tokens(&parse)) {
1210 tgsi_parse_token(&parse);
1211
1212 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1213 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1214 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1215 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1216 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1217 {
1218 int interpolate, location, k;
1219
1220 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1221 location = TGSI_INTERPOLATE_LOC_CENTER;
1222 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1223 location = TGSI_INTERPOLATE_LOC_CENTER;
1224 /* Needs sample positions, currently those are always available */
1225 } else {
1226 location = TGSI_INTERPOLATE_LOC_CENTROID;
1227 }
1228
1229 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1230 k = eg_get_interpolator_index(interpolate, location);
1231 if (k >= 0)
1232 ctx->eg_interpolators[k].enabled = true;
1233 }
1234 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1235 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1236 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1237 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1238 if (d->Semantic.Name == inputs[k].name ||
1239 d->Semantic.Name == inputs[k].alternate_name) {
1240 inputs[k].enabled = true;
1241 }
1242 }
1243 }
1244 }
1245 }
1246
1247 tgsi_parse_free(&parse);
1248
1249 if (ctx->info.reads_samplemask &&
1250 (ctx->info.uses_linear_sample || ctx->info.uses_linear_sample)) {
1251 inputs[1].enabled = true;
1252 }
1253
1254 if (ctx->bc->chip_class >= EVERGREEN) {
1255 int num_baryc = 0;
1256 /* assign gpr to each interpolator according to priority */
1257 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1258 if (ctx->eg_interpolators[i].enabled) {
1259 ctx->eg_interpolators[i].ij_index = num_baryc;
1260 num_baryc++;
1261 }
1262 }
1263 num_baryc = (num_baryc + 1) >> 1;
1264 gpr_offset += num_baryc;
1265 }
1266
1267 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1268 boolean enabled = inputs[i].enabled;
1269 int *reg = inputs[i].reg;
1270 unsigned name = inputs[i].name;
1271
1272 if (enabled) {
1273 int gpr = gpr_offset + num_regs++;
1274 ctx->shader->nsys_inputs++;
1275
1276 // add to inputs, allocate a gpr
1277 k = ctx->shader->ninput++;
1278 ctx->shader->input[k].name = name;
1279 ctx->shader->input[k].sid = 0;
1280 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1281 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1282 *reg = ctx->shader->input[k].gpr = gpr;
1283 }
1284 }
1285
1286 return gpr_offset + num_regs;
1287 }
1288
1289 /*
1290 * for evergreen we need to scan the shader to find the number of GPRs we need to
1291 * reserve for interpolation and system values
1292 *
1293 * we need to know if we are going to emit any sample or centroid inputs
1294 * if perspective and linear are required
1295 */
1296 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1297 {
1298 unsigned i;
1299
1300 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1301
1302 /*
1303 * Could get this information from the shader info. But right now
1304 * we interpolate all declared inputs, whereas the shader info will
1305 * only contain the bits if the inputs are actually used, so it might
1306 * not be safe...
1307 */
1308 for (i = 0; i < ctx->info.num_inputs; i++) {
1309 int k;
1310 /* skip position/face/mask/sampleid */
1311 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1312 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1313 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1314 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1315 continue;
1316
1317 k = eg_get_interpolator_index(
1318 ctx->info.input_interpolate[i],
1319 ctx->info.input_interpolate_loc[i]);
1320 if (k >= 0)
1321 ctx->eg_interpolators[k].enabled = TRUE;
1322 }
1323
1324 /* XXX PULL MODEL and LINE STIPPLE */
1325
1326 return allocate_system_value_inputs(ctx, 0);
1327 }
1328
1329 /* sample_id_sel == NULL means fetch for current sample */
1330 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1331 {
1332 struct r600_bytecode_vtx vtx;
1333 int r, t1;
1334
1335 t1 = r600_get_temp(ctx);
1336
1337 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1338 vtx.op = FETCH_OP_VFETCH;
1339 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1340 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1341 if (sample_id == NULL) {
1342 assert(ctx->fixed_pt_position_gpr != -1);
1343
1344 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1345 vtx.src_sel_x = 3;
1346 }
1347 else {
1348 struct r600_bytecode_alu alu;
1349
1350 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1351 alu.op = ALU_OP1_MOV;
1352 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1353 alu.dst.sel = t1;
1354 alu.dst.write = 1;
1355 alu.last = 1;
1356 r = r600_bytecode_add_alu(ctx->bc, &alu);
1357 if (r)
1358 return r;
1359
1360 vtx.src_gpr = t1;
1361 vtx.src_sel_x = 0;
1362 }
1363 vtx.mega_fetch_count = 16;
1364 vtx.dst_gpr = t1;
1365 vtx.dst_sel_x = 0;
1366 vtx.dst_sel_y = 1;
1367 vtx.dst_sel_z = 2;
1368 vtx.dst_sel_w = 3;
1369 vtx.data_format = FMT_32_32_32_32_FLOAT;
1370 vtx.num_format_all = 2;
1371 vtx.format_comp_all = 1;
1372 vtx.use_const_fields = 0;
1373 vtx.offset = 0;
1374 vtx.endian = r600_endian_swap(32);
1375 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1376
1377 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1378 if (r)
1379 return r;
1380
1381 return t1;
1382 }
1383
1384 static int eg_load_helper_invocation(struct r600_shader_ctx *ctx)
1385 {
1386 int r;
1387 struct r600_bytecode_alu alu;
1388
1389 /* do a vtx fetch with wqm set on the vtx fetch */
1390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1391 alu.op = ALU_OP1_MOV;
1392 alu.dst.sel = ctx->helper_invoc_reg;
1393 alu.dst.chan = 0;
1394 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1395 alu.src[0].value = 0xffffffff;
1396 alu.dst.write = 1;
1397 alu.last = 1;
1398 r = r600_bytecode_add_alu(ctx->bc, &alu);
1399 if (r)
1400 return r;
1401
1402 /* do a vtx fetch in VPM mode */
1403 struct r600_bytecode_vtx vtx;
1404 memset(&vtx, 0, sizeof(vtx));
1405 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
1406 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1407 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1408 vtx.src_gpr = 0;
1409 vtx.mega_fetch_count = 16; /* no idea here really... */
1410 vtx.dst_gpr = ctx->helper_invoc_reg;
1411 vtx.dst_sel_x = 4;
1412 vtx.dst_sel_y = 7; /* SEL_Y */
1413 vtx.dst_sel_z = 7; /* SEL_Z */
1414 vtx.dst_sel_w = 7; /* SEL_W */
1415 vtx.data_format = FMT_32;
1416 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
1417 return r;
1418 ctx->bc->cf_last->vpm = 1;
1419 return 0;
1420 }
1421
1422 static int cm_load_helper_invocation(struct r600_shader_ctx *ctx)
1423 {
1424 int r;
1425 struct r600_bytecode_alu alu;
1426
1427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1428 alu.op = ALU_OP1_MOV;
1429 alu.dst.sel = ctx->helper_invoc_reg;
1430 alu.dst.chan = 0;
1431 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1432 alu.src[0].value = 0xffffffff;
1433 alu.dst.write = 1;
1434 alu.last = 1;
1435 r = r600_bytecode_add_alu(ctx->bc, &alu);
1436 if (r)
1437 return r;
1438
1439 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1440 alu.op = ALU_OP1_MOV;
1441 alu.dst.sel = ctx->helper_invoc_reg;
1442 alu.dst.chan = 0;
1443 alu.src[0].sel = V_SQ_ALU_SRC_0;
1444 alu.dst.write = 1;
1445 alu.last = 1;
1446 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_VALID_PIXEL_MODE);
1447 if (r)
1448 return r;
1449
1450 return ctx->helper_invoc_reg;
1451 }
1452
1453 static int load_block_grid_size(struct r600_shader_ctx *ctx, bool load_block)
1454 {
1455 struct r600_bytecode_vtx vtx;
1456 int r, t1;
1457
1458 if (ctx->cs_block_size_loaded)
1459 return ctx->cs_block_size_reg;
1460 if (ctx->cs_grid_size_loaded)
1461 return ctx->cs_grid_size_reg;
1462
1463 t1 = load_block ? ctx->cs_block_size_reg : ctx->cs_grid_size_reg;
1464 struct r600_bytecode_alu alu;
1465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1466 alu.op = ALU_OP1_MOV;
1467 alu.src[0].sel = V_SQ_ALU_SRC_0;
1468 alu.dst.sel = t1;
1469 alu.dst.write = 1;
1470 alu.last = 1;
1471 r = r600_bytecode_add_alu(ctx->bc, &alu);
1472 if (r)
1473 return r;
1474
1475 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1476 vtx.op = FETCH_OP_VFETCH;
1477 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1478 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1479 vtx.src_gpr = t1;
1480 vtx.src_sel_x = 0;
1481
1482 vtx.mega_fetch_count = 16;
1483 vtx.dst_gpr = t1;
1484 vtx.dst_sel_x = 0;
1485 vtx.dst_sel_y = 1;
1486 vtx.dst_sel_z = 2;
1487 vtx.dst_sel_w = 7;
1488 vtx.data_format = FMT_32_32_32_32;
1489 vtx.num_format_all = 1;
1490 vtx.format_comp_all = 0;
1491 vtx.use_const_fields = 0;
1492 vtx.offset = load_block ? 0 : 16; // first element is size of buffer
1493 vtx.endian = r600_endian_swap(32);
1494 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1495
1496 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1497 if (r)
1498 return r;
1499
1500 if (load_block)
1501 ctx->cs_block_size_loaded = true;
1502 else
1503 ctx->cs_grid_size_loaded = true;
1504 return t1;
1505 }
1506
1507 static void tgsi_src(struct r600_shader_ctx *ctx,
1508 const struct tgsi_full_src_register *tgsi_src,
1509 struct r600_shader_src *r600_src)
1510 {
1511 memset(r600_src, 0, sizeof(*r600_src));
1512 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1513 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1514 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1515 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1516 r600_src->neg = tgsi_src->Register.Negate;
1517 r600_src->abs = tgsi_src->Register.Absolute;
1518
1519 if (tgsi_src->Register.File == TGSI_FILE_TEMPORARY) {
1520 bool spilled;
1521 unsigned idx;
1522
1523 idx = map_tgsi_reg_index_to_r600_gpr(ctx, tgsi_src->Register.Index, &spilled);
1524
1525 if (spilled) {
1526 int reg = r600_get_temp(ctx);
1527 int r;
1528
1529 r600_src->sel = reg;
1530
1531 if (ctx->bc->chip_class < R700) {
1532 struct r600_bytecode_output cf;
1533
1534 memset(&cf, 0, sizeof(struct r600_bytecode_output));
1535 cf.op = CF_OP_MEM_SCRATCH;
1536 cf.elem_size = 3;
1537 cf.gpr = reg;
1538 cf.comp_mask = 0xF;
1539 cf.swizzle_x = 0;
1540 cf.swizzle_y = 1;
1541 cf.swizzle_z = 2;
1542 cf.swizzle_w = 3;
1543 cf.burst_count = 1;
1544
1545 get_spilled_array_base_and_size(ctx, tgsi_src->Register.Index,
1546 &cf.array_base, &cf.array_size);
1547
1548 if (tgsi_src->Register.Indirect) {
1549 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
1550 cf.index_gpr = ctx->bc->ar_reg;
1551 }
1552 else {
1553 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ;
1554 cf.array_base += idx;
1555 cf.array_size = 0;
1556 }
1557
1558 r = r600_bytecode_add_output(ctx->bc, &cf);
1559 }
1560 else {
1561 struct r600_bytecode_vtx vtx;
1562
1563 if (r600_bytecode_get_need_wait_ack(ctx->bc)) {
1564 r600_bytecode_need_wait_ack(ctx->bc, false);
1565 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
1566 }
1567
1568 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1569 vtx.op = FETCH_OP_READ_SCRATCH;
1570 vtx.dst_gpr = reg;
1571 vtx.uncached = 1; // Must bypass cache since prior spill written in same invocation
1572 vtx.elem_size = 3;
1573 vtx.data_format = FMT_32_32_32_32;
1574 vtx.num_format_all = V_038010_SQ_NUM_FORMAT_INT;
1575 vtx.dst_sel_x = tgsi_src->Register.SwizzleX;
1576 vtx.dst_sel_y = tgsi_src->Register.SwizzleY;
1577 vtx.dst_sel_z = tgsi_src->Register.SwizzleZ;
1578 vtx.dst_sel_w = tgsi_src->Register.SwizzleW;
1579
1580 get_spilled_array_base_and_size(ctx, tgsi_src->Register.Index,
1581 &vtx.array_base, &vtx.array_size);
1582
1583 if (tgsi_src->Register.Indirect) {
1584 vtx.indexed = 1;
1585 vtx.src_gpr = ctx->bc->ar_reg;
1586 }
1587 else {
1588 vtx.array_base += idx;
1589 vtx.array_size = 0;
1590 }
1591
1592 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1593 }
1594
1595 if (r)
1596 return;
1597 }
1598 else {
1599 if (tgsi_src->Register.Indirect)
1600 r600_src->rel = V_SQ_REL_RELATIVE;
1601
1602 r600_src->sel = idx;
1603 }
1604
1605 return;
1606 }
1607
1608 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1609 int index;
1610 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1611 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1612 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1613
1614 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1615 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1616 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1617 return;
1618 }
1619 index = tgsi_src->Register.Index;
1620 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1621 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1622 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1623 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1624 r600_src->swizzle[0] = 2; // Z value
1625 r600_src->swizzle[1] = 2;
1626 r600_src->swizzle[2] = 2;
1627 r600_src->swizzle[3] = 2;
1628 r600_src->sel = ctx->face_gpr;
1629 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1630 r600_src->swizzle[0] = 3; // W value
1631 r600_src->swizzle[1] = 3;
1632 r600_src->swizzle[2] = 3;
1633 r600_src->swizzle[3] = 3;
1634 r600_src->sel = ctx->fixed_pt_position_gpr;
1635 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1636 r600_src->swizzle[0] = 0;
1637 r600_src->swizzle[1] = 1;
1638 r600_src->swizzle[2] = 4;
1639 r600_src->swizzle[3] = 4;
1640 r600_src->sel = load_sample_position(ctx, NULL, -1);
1641 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1642 r600_src->swizzle[0] = 3;
1643 r600_src->swizzle[1] = 3;
1644 r600_src->swizzle[2] = 3;
1645 r600_src->swizzle[3] = 3;
1646 r600_src->sel = 0;
1647 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1648 r600_src->swizzle[0] = 0;
1649 r600_src->swizzle[1] = 0;
1650 r600_src->swizzle[2] = 0;
1651 r600_src->swizzle[3] = 0;
1652 r600_src->sel = 0;
1653 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_THREAD_ID) {
1654 r600_src->sel = 0;
1655 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_ID) {
1656 r600_src->sel = 1;
1657 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1658 r600_src->swizzle[0] = 3;
1659 r600_src->swizzle[1] = 3;
1660 r600_src->swizzle[2] = 3;
1661 r600_src->swizzle[3] = 3;
1662 r600_src->sel = 1;
1663 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1664 r600_src->swizzle[0] = 2;
1665 r600_src->swizzle[1] = 2;
1666 r600_src->swizzle[2] = 2;
1667 r600_src->swizzle[3] = 2;
1668 r600_src->sel = 0;
1669 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1670 r600_src->sel = 1;
1671 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1672 r600_src->sel = 3;
1673 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1674 r600_src->sel = 2;
1675 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1676 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1677 r600_src->sel = ctx->tess_input_info;
1678 r600_src->swizzle[0] = 2;
1679 r600_src->swizzle[1] = 2;
1680 r600_src->swizzle[2] = 2;
1681 r600_src->swizzle[3] = 2;
1682 } else {
1683 r600_src->sel = ctx->tess_input_info;
1684 r600_src->swizzle[0] = 3;
1685 r600_src->swizzle[1] = 3;
1686 r600_src->swizzle[2] = 3;
1687 r600_src->swizzle[3] = 3;
1688 }
1689 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1690 r600_src->sel = 0;
1691 r600_src->swizzle[0] = 0;
1692 r600_src->swizzle[1] = 0;
1693 r600_src->swizzle[2] = 0;
1694 r600_src->swizzle[3] = 0;
1695 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1696 r600_src->sel = 0;
1697 r600_src->swizzle[0] = 3;
1698 r600_src->swizzle[1] = 3;
1699 r600_src->swizzle[2] = 3;
1700 r600_src->swizzle[3] = 3;
1701 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_GRID_SIZE) {
1702 r600_src->sel = load_block_grid_size(ctx, false);
1703 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_SIZE) {
1704 r600_src->sel = load_block_grid_size(ctx, true);
1705 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_HELPER_INVOCATION) {
1706 r600_src->sel = ctx->helper_invoc_reg;
1707 r600_src->swizzle[0] = 0;
1708 r600_src->swizzle[1] = 0;
1709 r600_src->swizzle[2] = 0;
1710 r600_src->swizzle[3] = 0;
1711 }
1712 } else {
1713 if (tgsi_src->Register.Indirect)
1714 r600_src->rel = V_SQ_REL_RELATIVE;
1715 r600_src->sel = tgsi_src->Register.Index;
1716 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1717 }
1718 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1719 if (tgsi_src->Register.Dimension) {
1720 r600_src->kc_bank = tgsi_src->Dimension.Index;
1721 if (tgsi_src->Dimension.Indirect) {
1722 r600_src->kc_rel = 1;
1723 }
1724 }
1725 }
1726 }
1727
1728 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1729 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1730 unsigned int dst_reg)
1731 {
1732 struct r600_bytecode_vtx vtx;
1733 unsigned int ar_reg;
1734 int r;
1735
1736 if (offset) {
1737 struct r600_bytecode_alu alu;
1738
1739 memset(&alu, 0, sizeof(alu));
1740
1741 alu.op = ALU_OP2_ADD_INT;
1742 alu.src[0].sel = ctx->bc->ar_reg;
1743 alu.src[0].chan = ar_chan;
1744
1745 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1746 alu.src[1].value = offset;
1747
1748 alu.dst.sel = dst_reg;
1749 alu.dst.chan = ar_chan;
1750 alu.dst.write = 1;
1751 alu.last = 1;
1752
1753 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1754 return r;
1755
1756 ar_reg = dst_reg;
1757 } else {
1758 ar_reg = ctx->bc->ar_reg;
1759 }
1760
1761 memset(&vtx, 0, sizeof(vtx));
1762 vtx.buffer_id = cb_idx;
1763 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1764 vtx.src_gpr = ar_reg;
1765 vtx.src_sel_x = ar_chan;
1766 vtx.mega_fetch_count = 16;
1767 vtx.dst_gpr = dst_reg;
1768 vtx.dst_sel_x = 0; /* SEL_X */
1769 vtx.dst_sel_y = 1; /* SEL_Y */
1770 vtx.dst_sel_z = 2; /* SEL_Z */
1771 vtx.dst_sel_w = 3; /* SEL_W */
1772 vtx.data_format = FMT_32_32_32_32_FLOAT;
1773 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1774 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1775 vtx.endian = r600_endian_swap(32);
1776 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1777
1778 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1779 return r;
1780
1781 return 0;
1782 }
1783
1784 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1785 {
1786 struct r600_bytecode_vtx vtx;
1787 int r;
1788 unsigned index = src->Register.Index;
1789 unsigned vtx_id = src->Dimension.Index;
1790 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1791 int offset_chan = vtx_id % 3;
1792 int t2 = 0;
1793
1794 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1795 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1796
1797 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1798 offset_chan = 3;
1799
1800 if (src->Dimension.Indirect || src->Register.Indirect)
1801 t2 = r600_get_temp(ctx);
1802
1803 if (src->Dimension.Indirect) {
1804 int treg[3];
1805 struct r600_bytecode_alu alu;
1806 int r, i;
1807 unsigned addr_reg;
1808 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1809 if (src->DimIndirect.Index > 0) {
1810 r = single_alu_op2(ctx, ALU_OP1_MOV,
1811 ctx->bc->ar_reg, 0,
1812 addr_reg, 0,
1813 0, 0);
1814 if (r)
1815 return r;
1816 }
1817 /*
1818 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1819 at least this is what fglrx seems to do. */
1820 for (i = 0; i < 3; i++) {
1821 treg[i] = r600_get_temp(ctx);
1822 }
1823 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1824
1825 for (i = 0; i < 3; i++) {
1826 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1827 alu.op = ALU_OP1_MOV;
1828 alu.src[0].sel = ctx->gs_rotated_input[0];
1829 alu.src[0].chan = i == 2 ? 3 : i;
1830 alu.dst.sel = treg[i];
1831 alu.dst.chan = 0;
1832 alu.dst.write = 1;
1833 alu.last = 1;
1834 r = r600_bytecode_add_alu(ctx->bc, &alu);
1835 if (r)
1836 return r;
1837 }
1838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1839 alu.op = ALU_OP1_MOV;
1840 alu.src[0].sel = treg[0];
1841 alu.src[0].rel = 1;
1842 alu.dst.sel = t2;
1843 alu.dst.write = 1;
1844 alu.last = 1;
1845 r = r600_bytecode_add_alu(ctx->bc, &alu);
1846 if (r)
1847 return r;
1848 offset_reg = t2;
1849 offset_chan = 0;
1850 }
1851
1852 if (src->Register.Indirect) {
1853 int addr_reg;
1854 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1855
1856 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1857
1858 /* pull the value from index_reg */
1859 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1860 t2, 1,
1861 addr_reg, 0,
1862 V_SQ_ALU_SRC_LITERAL, first);
1863 if (r)
1864 return r;
1865 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1866 t2, 0,
1867 t2, 1,
1868 V_SQ_ALU_SRC_LITERAL, 4,
1869 offset_reg, offset_chan);
1870 if (r)
1871 return r;
1872 offset_reg = t2;
1873 offset_chan = 0;
1874 index = src->Register.Index - first;
1875 }
1876
1877 memset(&vtx, 0, sizeof(vtx));
1878 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1879 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1880 vtx.src_gpr = offset_reg;
1881 vtx.src_sel_x = offset_chan;
1882 vtx.offset = index * 16; /*bytes*/
1883 vtx.mega_fetch_count = 16;
1884 vtx.dst_gpr = dst_reg;
1885 vtx.dst_sel_x = 0; /* SEL_X */
1886 vtx.dst_sel_y = 1; /* SEL_Y */
1887 vtx.dst_sel_z = 2; /* SEL_Z */
1888 vtx.dst_sel_w = 3; /* SEL_W */
1889 if (ctx->bc->chip_class >= EVERGREEN) {
1890 vtx.use_const_fields = 1;
1891 } else {
1892 vtx.data_format = FMT_32_32_32_32_FLOAT;
1893 }
1894
1895 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1896 return r;
1897
1898 return 0;
1899 }
1900
1901 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1902 {
1903 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1904 unsigned i;
1905
1906 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1907 struct tgsi_full_src_register *src = &inst->Src[i];
1908
1909 if (src->Register.File == TGSI_FILE_INPUT) {
1910 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1911 /* primitive id is in R0.z */
1912 ctx->src[i].sel = 0;
1913 ctx->src[i].swizzle[0] = 2;
1914 }
1915 }
1916 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1917 int treg = r600_get_temp(ctx);
1918
1919 fetch_gs_input(ctx, src, treg);
1920 ctx->src[i].sel = treg;
1921 ctx->src[i].rel = 0;
1922 }
1923 }
1924 return 0;
1925 }
1926
1927
1928 /* Tessellation shaders pass outputs to the next shader using LDS.
1929 *
1930 * LS outputs = TCS(HS) inputs
1931 * TCS(HS) outputs = TES(DS) inputs
1932 *
1933 * The LDS layout is:
1934 * - TCS inputs for patch 0
1935 * - TCS inputs for patch 1
1936 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1937 * - ...
1938 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1939 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1940 * - TCS outputs for patch 1
1941 * - Per-patch TCS outputs for patch 1
1942 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1943 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1944 * - ...
1945 *
1946 * All three shaders VS(LS), TCS, TES share the same LDS space.
1947 */
1948 /* this will return with the dw address in temp_reg.x */
1949 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1950 const struct tgsi_full_dst_register *dst,
1951 const struct tgsi_full_src_register *src,
1952 int stride_bytes_reg, int stride_bytes_chan)
1953 {
1954 struct tgsi_full_dst_register reg;
1955 ubyte *name, *index, *array_first;
1956 int r;
1957 int param;
1958 struct tgsi_shader_info *info = &ctx->info;
1959 /* Set the register description. The address computation is the same
1960 * for sources and destinations. */
1961 if (src) {
1962 reg.Register.File = src->Register.File;
1963 reg.Register.Index = src->Register.Index;
1964 reg.Register.Indirect = src->Register.Indirect;
1965 reg.Register.Dimension = src->Register.Dimension;
1966 reg.Indirect = src->Indirect;
1967 reg.Dimension = src->Dimension;
1968 reg.DimIndirect = src->DimIndirect;
1969 } else
1970 reg = *dst;
1971
1972 /* If the register is 2-dimensional (e.g. an array of vertices
1973 * in a primitive), calculate the base address of the vertex. */
1974 if (reg.Register.Dimension) {
1975 int sel, chan;
1976 if (reg.Dimension.Indirect) {
1977 unsigned addr_reg;
1978 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1979
1980 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1981 /* pull the value from index_reg */
1982 sel = addr_reg;
1983 chan = 0;
1984 } else {
1985 sel = V_SQ_ALU_SRC_LITERAL;
1986 chan = reg.Dimension.Index;
1987 }
1988
1989 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1990 temp_reg, 0,
1991 stride_bytes_reg, stride_bytes_chan,
1992 sel, chan,
1993 temp_reg, 0);
1994 if (r)
1995 return r;
1996 }
1997
1998 if (reg.Register.File == TGSI_FILE_INPUT) {
1999 name = info->input_semantic_name;
2000 index = info->input_semantic_index;
2001 array_first = info->input_array_first;
2002 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
2003 name = info->output_semantic_name;
2004 index = info->output_semantic_index;
2005 array_first = info->output_array_first;
2006 } else {
2007 assert(0);
2008 return -1;
2009 }
2010 if (reg.Register.Indirect) {
2011 int addr_reg;
2012 int first;
2013 /* Add the relative address of the element. */
2014 if (reg.Indirect.ArrayID)
2015 first = array_first[reg.Indirect.ArrayID];
2016 else
2017 first = reg.Register.Index;
2018
2019 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
2020
2021 /* pull the value from index_reg */
2022 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2023 temp_reg, 0,
2024 V_SQ_ALU_SRC_LITERAL, 16,
2025 addr_reg, 0,
2026 temp_reg, 0);
2027 if (r)
2028 return r;
2029
2030 param = r600_get_lds_unique_index(name[first],
2031 index[first]);
2032
2033 } else {
2034 param = r600_get_lds_unique_index(name[reg.Register.Index],
2035 index[reg.Register.Index]);
2036 }
2037
2038 /* add to base_addr - passed in temp_reg.x */
2039 if (param) {
2040 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2041 temp_reg, 0,
2042 temp_reg, 0,
2043 V_SQ_ALU_SRC_LITERAL, param * 16);
2044 if (r)
2045 return r;
2046
2047 }
2048 return 0;
2049 }
2050
2051 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
2052 unsigned dst_reg, unsigned mask)
2053 {
2054 struct r600_bytecode_alu alu;
2055 int r, i, lasti;
2056
2057 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
2058 ctx->bc->force_add_cf = 1;
2059
2060 lasti = tgsi_last_instruction(mask);
2061 for (i = 1; i <= lasti; i++) {
2062 if (!(mask & (1 << i)))
2063 continue;
2064
2065 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2066 temp_reg, i,
2067 temp_reg, 0,
2068 V_SQ_ALU_SRC_LITERAL, 4 * i);
2069 if (r)
2070 return r;
2071 }
2072 for (i = 0; i <= lasti; i++) {
2073 if (!(mask & (1 << i)))
2074 continue;
2075
2076 /* emit an LDS_READ_RET */
2077 memset(&alu, 0, sizeof(alu));
2078 alu.op = LDS_OP1_LDS_READ_RET;
2079 alu.src[0].sel = temp_reg;
2080 alu.src[0].chan = i;
2081 alu.src[1].sel = V_SQ_ALU_SRC_0;
2082 alu.src[2].sel = V_SQ_ALU_SRC_0;
2083 alu.dst.chan = 0;
2084 alu.is_lds_idx_op = true;
2085 alu.last = 1;
2086 r = r600_bytecode_add_alu(ctx->bc, &alu);
2087 if (r)
2088 return r;
2089 }
2090 for (i = 0; i <= lasti; i++) {
2091 if (!(mask & (1 << i)))
2092 continue;
2093
2094 /* then read from LDS_OQ_A_POP */
2095 memset(&alu, 0, sizeof(alu));
2096
2097 alu.op = ALU_OP1_MOV;
2098 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
2099 alu.src[0].chan = 0;
2100 alu.dst.sel = dst_reg;
2101 alu.dst.chan = i;
2102 alu.dst.write = 1;
2103 alu.last = 1;
2104 r = r600_bytecode_add_alu(ctx->bc, &alu);
2105 if (r)
2106 return r;
2107 }
2108 return 0;
2109 }
2110
2111 static int fetch_mask(struct tgsi_src_register *reg)
2112 {
2113 int mask = 0;
2114 mask |= 1 << reg->SwizzleX;
2115 mask |= 1 << reg->SwizzleY;
2116 mask |= 1 << reg->SwizzleZ;
2117 mask |= 1 << reg->SwizzleW;
2118 return mask;
2119 }
2120
2121 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
2122 {
2123 int r;
2124 unsigned temp_reg = r600_get_temp(ctx);
2125
2126 r = get_lds_offset0(ctx, 2, temp_reg,
2127 src->Register.Dimension ? false : true);
2128 if (r)
2129 return r;
2130
2131 /* the base address is now in temp.x */
2132 r = r600_get_byte_address(ctx, temp_reg,
2133 NULL, src, ctx->tess_output_info, 1);
2134 if (r)
2135 return r;
2136
2137 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2138 if (r)
2139 return r;
2140 return 0;
2141 }
2142
2143 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
2144 {
2145 int r;
2146 unsigned temp_reg = r600_get_temp(ctx);
2147
2148 /* t.x = ips * r0.y */
2149 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2150 temp_reg, 0,
2151 ctx->tess_input_info, 0,
2152 0, 1);
2153
2154 if (r)
2155 return r;
2156
2157 /* the base address is now in temp.x */
2158 r = r600_get_byte_address(ctx, temp_reg,
2159 NULL, src, ctx->tess_input_info, 1);
2160 if (r)
2161 return r;
2162
2163 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2164 if (r)
2165 return r;
2166 return 0;
2167 }
2168
2169 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
2170 {
2171 int r;
2172 unsigned temp_reg = r600_get_temp(ctx);
2173
2174 r = get_lds_offset0(ctx, 1, temp_reg,
2175 src->Register.Dimension ? false : true);
2176 if (r)
2177 return r;
2178 /* the base address is now in temp.x */
2179 r = r600_get_byte_address(ctx, temp_reg,
2180 NULL, src,
2181 ctx->tess_output_info, 1);
2182 if (r)
2183 return r;
2184
2185 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
2186 if (r)
2187 return r;
2188 return 0;
2189 }
2190
2191 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
2192 {
2193 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2194 unsigned i;
2195
2196 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2197 struct tgsi_full_src_register *src = &inst->Src[i];
2198
2199 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
2200 int treg = r600_get_temp(ctx);
2201 fetch_tes_input(ctx, src, treg);
2202 ctx->src[i].sel = treg;
2203 ctx->src[i].rel = 0;
2204 }
2205 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
2206 int treg = r600_get_temp(ctx);
2207 fetch_tcs_input(ctx, src, treg);
2208 ctx->src[i].sel = treg;
2209 ctx->src[i].rel = 0;
2210 }
2211 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
2212 int treg = r600_get_temp(ctx);
2213 fetch_tcs_output(ctx, src, treg);
2214 ctx->src[i].sel = treg;
2215 ctx->src[i].rel = 0;
2216 }
2217 }
2218 return 0;
2219 }
2220
2221 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
2222 {
2223 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2224 struct r600_bytecode_alu alu;
2225 int i, j, k, nconst, r;
2226
2227 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
2228 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
2229 nconst++;
2230 }
2231 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
2232 }
2233 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
2234 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
2235 continue;
2236 }
2237
2238 if (ctx->src[i].rel) {
2239 int chan = inst->Src[i].Indirect.Swizzle;
2240 int treg = r600_get_temp(ctx);
2241 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
2242 return r;
2243
2244 ctx->src[i].kc_bank = 0;
2245 ctx->src[i].kc_rel = 0;
2246 ctx->src[i].sel = treg;
2247 ctx->src[i].rel = 0;
2248 j--;
2249 } else if (j > 0) {
2250 int treg = r600_get_temp(ctx);
2251 for (k = 0; k < 4; k++) {
2252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2253 alu.op = ALU_OP1_MOV;
2254 alu.src[0].sel = ctx->src[i].sel;
2255 alu.src[0].chan = k;
2256 alu.src[0].rel = ctx->src[i].rel;
2257 alu.src[0].kc_bank = ctx->src[i].kc_bank;
2258 alu.src[0].kc_rel = ctx->src[i].kc_rel;
2259 alu.dst.sel = treg;
2260 alu.dst.chan = k;
2261 alu.dst.write = 1;
2262 if (k == 3)
2263 alu.last = 1;
2264 r = r600_bytecode_add_alu(ctx->bc, &alu);
2265 if (r)
2266 return r;
2267 }
2268 ctx->src[i].sel = treg;
2269 ctx->src[i].rel =0;
2270 j--;
2271 }
2272 }
2273 return 0;
2274 }
2275
2276 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
2277 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
2278 {
2279 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2280 struct r600_bytecode_alu alu;
2281 int i, j, k, nliteral, r;
2282
2283 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
2284 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2285 nliteral++;
2286 }
2287 }
2288 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
2289 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2290 int treg = r600_get_temp(ctx);
2291 for (k = 0; k < 4; k++) {
2292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2293 alu.op = ALU_OP1_MOV;
2294 alu.src[0].sel = ctx->src[i].sel;
2295 alu.src[0].chan = k;
2296 alu.src[0].value = ctx->src[i].value[k];
2297 alu.dst.sel = treg;
2298 alu.dst.chan = k;
2299 alu.dst.write = 1;
2300 if (k == 3)
2301 alu.last = 1;
2302 r = r600_bytecode_add_alu(ctx->bc, &alu);
2303 if (r)
2304 return r;
2305 }
2306 ctx->src[i].sel = treg;
2307 j--;
2308 }
2309 }
2310 return 0;
2311 }
2312
2313 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
2314 {
2315 int i, r, count = ctx->shader->ninput;
2316
2317 for (i = 0; i < count; i++) {
2318 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2319 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
2320 if (r)
2321 return r;
2322 }
2323 }
2324 return 0;
2325 }
2326
2327 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2328 int stream, unsigned *stream_item_size UNUSED)
2329 {
2330 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2331 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2332 int j, r;
2333 unsigned i;
2334
2335 /* Sanity checking. */
2336 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2337 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2338 r = -EINVAL;
2339 goto out_err;
2340 }
2341 for (i = 0; i < so->num_outputs; i++) {
2342 if (so->output[i].output_buffer >= 4) {
2343 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2344 so->output[i].output_buffer);
2345 r = -EINVAL;
2346 goto out_err;
2347 }
2348 }
2349
2350 /* Initialize locations where the outputs are stored. */
2351 for (i = 0; i < so->num_outputs; i++) {
2352
2353 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2354 start_comp[i] = so->output[i].start_component;
2355 /* Lower outputs with dst_offset < start_component.
2356 *
2357 * We can only output 4D vectors with a write mask, e.g. we can
2358 * only output the W component at offset 3, etc. If we want
2359 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2360 * to move it to X and output X. */
2361 if (so->output[i].dst_offset < so->output[i].start_component) {
2362 unsigned tmp = r600_get_temp(ctx);
2363
2364 for (j = 0; j < so->output[i].num_components; j++) {
2365 struct r600_bytecode_alu alu;
2366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2367 alu.op = ALU_OP1_MOV;
2368 alu.src[0].sel = so_gpr[i];
2369 alu.src[0].chan = so->output[i].start_component + j;
2370
2371 alu.dst.sel = tmp;
2372 alu.dst.chan = j;
2373 alu.dst.write = 1;
2374 if (j == so->output[i].num_components - 1)
2375 alu.last = 1;
2376 r = r600_bytecode_add_alu(ctx->bc, &alu);
2377 if (r)
2378 return r;
2379 }
2380 start_comp[i] = 0;
2381 so_gpr[i] = tmp;
2382 }
2383 }
2384
2385 /* Write outputs to buffers. */
2386 for (i = 0; i < so->num_outputs; i++) {
2387 struct r600_bytecode_output output;
2388
2389 if (stream != -1 && stream != so->output[i].stream)
2390 continue;
2391
2392 memset(&output, 0, sizeof(struct r600_bytecode_output));
2393 output.gpr = so_gpr[i];
2394 output.elem_size = so->output[i].num_components - 1;
2395 if (output.elem_size == 2)
2396 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2397 output.array_base = so->output[i].dst_offset - start_comp[i];
2398 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2399 output.burst_count = 1;
2400 /* array_size is an upper limit for the burst_count
2401 * with MEM_STREAM instructions */
2402 output.array_size = 0xFFF;
2403 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2404
2405 if (ctx->bc->chip_class >= EVERGREEN) {
2406 switch (so->output[i].output_buffer) {
2407 case 0:
2408 output.op = CF_OP_MEM_STREAM0_BUF0;
2409 break;
2410 case 1:
2411 output.op = CF_OP_MEM_STREAM0_BUF1;
2412 break;
2413 case 2:
2414 output.op = CF_OP_MEM_STREAM0_BUF2;
2415 break;
2416 case 3:
2417 output.op = CF_OP_MEM_STREAM0_BUF3;
2418 break;
2419 }
2420 output.op += so->output[i].stream * 4;
2421 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2422 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2423 } else {
2424 switch (so->output[i].output_buffer) {
2425 case 0:
2426 output.op = CF_OP_MEM_STREAM0;
2427 break;
2428 case 1:
2429 output.op = CF_OP_MEM_STREAM1;
2430 break;
2431 case 2:
2432 output.op = CF_OP_MEM_STREAM2;
2433 break;
2434 case 3:
2435 output.op = CF_OP_MEM_STREAM3;
2436 break;
2437 }
2438 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2439 }
2440 r = r600_bytecode_add_output(ctx->bc, &output);
2441 if (r)
2442 goto out_err;
2443 }
2444 return 0;
2445 out_err:
2446 return r;
2447 }
2448
2449 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2450 {
2451 struct r600_bytecode_alu alu;
2452 unsigned reg;
2453
2454 if (!ctx->shader->vs_out_edgeflag)
2455 return;
2456
2457 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2458
2459 /* clamp(x, 0, 1) */
2460 memset(&alu, 0, sizeof(alu));
2461 alu.op = ALU_OP1_MOV;
2462 alu.src[0].sel = reg;
2463 alu.dst.sel = reg;
2464 alu.dst.write = 1;
2465 alu.dst.clamp = 1;
2466 alu.last = 1;
2467 r600_bytecode_add_alu(ctx->bc, &alu);
2468
2469 memset(&alu, 0, sizeof(alu));
2470 alu.op = ALU_OP1_FLT_TO_INT;
2471 alu.src[0].sel = reg;
2472 alu.dst.sel = reg;
2473 alu.dst.write = 1;
2474 alu.last = 1;
2475 r600_bytecode_add_alu(ctx->bc, &alu);
2476 }
2477
2478 static int generate_gs_copy_shader(struct r600_context *rctx,
2479 struct r600_pipe_shader *gs,
2480 struct pipe_stream_output_info *so)
2481 {
2482 struct r600_shader_ctx ctx = {};
2483 struct r600_shader *gs_shader = &gs->shader;
2484 struct r600_pipe_shader *cshader;
2485 unsigned ocnt = gs_shader->noutput;
2486 struct r600_bytecode_alu alu;
2487 struct r600_bytecode_vtx vtx;
2488 struct r600_bytecode_output output;
2489 struct r600_bytecode_cf *cf_jump, *cf_pop,
2490 *last_exp_pos = NULL, *last_exp_param = NULL;
2491 int next_clip_pos = 61, next_param = 0;
2492 unsigned i, j;
2493 int ring;
2494 bool only_ring_0 = true;
2495 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2496 if (!cshader)
2497 return 0;
2498
2499 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2500 sizeof(struct r600_shader_io));
2501
2502 cshader->shader.noutput = ocnt;
2503
2504 ctx.shader = &cshader->shader;
2505 ctx.bc = &ctx.shader->bc;
2506 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2507
2508 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2509 rctx->screen->has_compressed_msaa_texturing);
2510
2511 ctx.bc->isa = rctx->isa;
2512
2513 cf_jump = NULL;
2514 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2515
2516 /* R0.x = R0.x & 0x3fffffff */
2517 memset(&alu, 0, sizeof(alu));
2518 alu.op = ALU_OP2_AND_INT;
2519 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2520 alu.src[1].value = 0x3fffffff;
2521 alu.dst.write = 1;
2522 r600_bytecode_add_alu(ctx.bc, &alu);
2523
2524 /* R0.y = R0.x >> 30 */
2525 memset(&alu, 0, sizeof(alu));
2526 alu.op = ALU_OP2_LSHR_INT;
2527 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2528 alu.src[1].value = 0x1e;
2529 alu.dst.chan = 1;
2530 alu.dst.write = 1;
2531 alu.last = 1;
2532 r600_bytecode_add_alu(ctx.bc, &alu);
2533
2534 /* fetch vertex data from GSVS ring */
2535 for (i = 0; i < ocnt; ++i) {
2536 struct r600_shader_io *out = &ctx.shader->output[i];
2537
2538 out->gpr = i + 1;
2539 out->ring_offset = i * 16;
2540
2541 memset(&vtx, 0, sizeof(vtx));
2542 vtx.op = FETCH_OP_VFETCH;
2543 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2544 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2545 vtx.mega_fetch_count = 16;
2546 vtx.offset = out->ring_offset;
2547 vtx.dst_gpr = out->gpr;
2548 vtx.src_gpr = 0;
2549 vtx.dst_sel_x = 0;
2550 vtx.dst_sel_y = 1;
2551 vtx.dst_sel_z = 2;
2552 vtx.dst_sel_w = 3;
2553 if (rctx->b.chip_class >= EVERGREEN) {
2554 vtx.use_const_fields = 1;
2555 } else {
2556 vtx.data_format = FMT_32_32_32_32_FLOAT;
2557 }
2558
2559 r600_bytecode_add_vtx(ctx.bc, &vtx);
2560 }
2561 ctx.temp_reg = i + 1;
2562 for (ring = 3; ring >= 0; --ring) {
2563 bool enabled = false;
2564 for (i = 0; i < so->num_outputs; i++) {
2565 if (so->output[i].stream == ring) {
2566 enabled = true;
2567 if (ring > 0)
2568 only_ring_0 = false;
2569 break;
2570 }
2571 }
2572 if (ring != 0 && !enabled) {
2573 cshader->shader.ring_item_sizes[ring] = 0;
2574 continue;
2575 }
2576
2577 if (cf_jump) {
2578 // Patch up jump label
2579 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2580 cf_pop = ctx.bc->cf_last;
2581
2582 cf_jump->cf_addr = cf_pop->id + 2;
2583 cf_jump->pop_count = 1;
2584 cf_pop->cf_addr = cf_pop->id + 2;
2585 cf_pop->pop_count = 1;
2586 }
2587
2588 /* PRED_SETE_INT __, R0.y, ring */
2589 memset(&alu, 0, sizeof(alu));
2590 alu.op = ALU_OP2_PRED_SETE_INT;
2591 alu.src[0].chan = 1;
2592 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2593 alu.src[1].value = ring;
2594 alu.execute_mask = 1;
2595 alu.update_pred = 1;
2596 alu.last = 1;
2597 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2598
2599 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2600 cf_jump = ctx.bc->cf_last;
2601
2602 if (enabled)
2603 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2604 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2605 }
2606
2607 /* bc adds nops - copy it */
2608 if (ctx.bc->chip_class == R600) {
2609 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2610 alu.op = ALU_OP0_NOP;
2611 alu.last = 1;
2612 r600_bytecode_add_alu(ctx.bc, &alu);
2613
2614 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2615 }
2616
2617 /* export vertex data */
2618 /* XXX factor out common code with r600_shader_from_tgsi ? */
2619 for (i = 0; i < ocnt; ++i) {
2620 struct r600_shader_io *out = &ctx.shader->output[i];
2621 bool instream0 = true;
2622 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2623 continue;
2624
2625 for (j = 0; j < so->num_outputs; j++) {
2626 if (so->output[j].register_index == i) {
2627 if (so->output[j].stream == 0)
2628 break;
2629 if (so->output[j].stream > 0)
2630 instream0 = false;
2631 }
2632 }
2633 if (!instream0)
2634 continue;
2635 memset(&output, 0, sizeof(output));
2636 output.gpr = out->gpr;
2637 output.elem_size = 3;
2638 output.swizzle_x = 0;
2639 output.swizzle_y = 1;
2640 output.swizzle_z = 2;
2641 output.swizzle_w = 3;
2642 output.burst_count = 1;
2643 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2644 output.op = CF_OP_EXPORT;
2645 switch (out->name) {
2646 case TGSI_SEMANTIC_POSITION:
2647 output.array_base = 60;
2648 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2649 break;
2650
2651 case TGSI_SEMANTIC_PSIZE:
2652 output.array_base = 61;
2653 if (next_clip_pos == 61)
2654 next_clip_pos = 62;
2655 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2656 output.swizzle_y = 7;
2657 output.swizzle_z = 7;
2658 output.swizzle_w = 7;
2659 ctx.shader->vs_out_misc_write = 1;
2660 ctx.shader->vs_out_point_size = 1;
2661 break;
2662 case TGSI_SEMANTIC_LAYER:
2663 if (out->spi_sid) {
2664 /* duplicate it as PARAM to pass to the pixel shader */
2665 output.array_base = next_param++;
2666 r600_bytecode_add_output(ctx.bc, &output);
2667 last_exp_param = ctx.bc->cf_last;
2668 }
2669 output.array_base = 61;
2670 if (next_clip_pos == 61)
2671 next_clip_pos = 62;
2672 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2673 output.swizzle_x = 7;
2674 output.swizzle_y = 7;
2675 output.swizzle_z = 0;
2676 output.swizzle_w = 7;
2677 ctx.shader->vs_out_misc_write = 1;
2678 ctx.shader->vs_out_layer = 1;
2679 break;
2680 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2681 if (out->spi_sid) {
2682 /* duplicate it as PARAM to pass to the pixel shader */
2683 output.array_base = next_param++;
2684 r600_bytecode_add_output(ctx.bc, &output);
2685 last_exp_param = ctx.bc->cf_last;
2686 }
2687 output.array_base = 61;
2688 if (next_clip_pos == 61)
2689 next_clip_pos = 62;
2690 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2691 ctx.shader->vs_out_misc_write = 1;
2692 ctx.shader->vs_out_viewport = 1;
2693 output.swizzle_x = 7;
2694 output.swizzle_y = 7;
2695 output.swizzle_z = 7;
2696 output.swizzle_w = 0;
2697 break;
2698 case TGSI_SEMANTIC_CLIPDIST:
2699 /* spi_sid is 0 for clipdistance outputs that were generated
2700 * for clipvertex - we don't need to pass them to PS */
2701 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2702 ctx.shader->cull_dist_write = gs->shader.cull_dist_write;
2703 ctx.shader->cc_dist_mask = gs->shader.cc_dist_mask;
2704 if (out->spi_sid) {
2705 /* duplicate it as PARAM to pass to the pixel shader */
2706 output.array_base = next_param++;
2707 r600_bytecode_add_output(ctx.bc, &output);
2708 last_exp_param = ctx.bc->cf_last;
2709 }
2710 output.array_base = next_clip_pos++;
2711 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2712 break;
2713 case TGSI_SEMANTIC_FOG:
2714 output.swizzle_y = 4; /* 0 */
2715 output.swizzle_z = 4; /* 0 */
2716 output.swizzle_w = 5; /* 1 */
2717 break;
2718 default:
2719 output.array_base = next_param++;
2720 break;
2721 }
2722 r600_bytecode_add_output(ctx.bc, &output);
2723 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2724 last_exp_param = ctx.bc->cf_last;
2725 else
2726 last_exp_pos = ctx.bc->cf_last;
2727 }
2728
2729 if (!last_exp_pos) {
2730 memset(&output, 0, sizeof(output));
2731 output.gpr = 0;
2732 output.elem_size = 3;
2733 output.swizzle_x = 7;
2734 output.swizzle_y = 7;
2735 output.swizzle_z = 7;
2736 output.swizzle_w = 7;
2737 output.burst_count = 1;
2738 output.type = 2;
2739 output.op = CF_OP_EXPORT;
2740 output.array_base = 60;
2741 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2742 r600_bytecode_add_output(ctx.bc, &output);
2743 last_exp_pos = ctx.bc->cf_last;
2744 }
2745
2746 if (!last_exp_param) {
2747 memset(&output, 0, sizeof(output));
2748 output.gpr = 0;
2749 output.elem_size = 3;
2750 output.swizzle_x = 7;
2751 output.swizzle_y = 7;
2752 output.swizzle_z = 7;
2753 output.swizzle_w = 7;
2754 output.burst_count = 1;
2755 output.type = 2;
2756 output.op = CF_OP_EXPORT;
2757 output.array_base = next_param++;
2758 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2759 r600_bytecode_add_output(ctx.bc, &output);
2760 last_exp_param = ctx.bc->cf_last;
2761 }
2762
2763 last_exp_pos->op = CF_OP_EXPORT_DONE;
2764 last_exp_param->op = CF_OP_EXPORT_DONE;
2765
2766 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2767 cf_pop = ctx.bc->cf_last;
2768
2769 cf_jump->cf_addr = cf_pop->id + 2;
2770 cf_jump->pop_count = 1;
2771 cf_pop->cf_addr = cf_pop->id + 2;
2772 cf_pop->pop_count = 1;
2773
2774 if (ctx.bc->chip_class == CAYMAN)
2775 cm_bytecode_add_cf_end(ctx.bc);
2776 else {
2777 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2778 ctx.bc->cf_last->end_of_program = 1;
2779 }
2780
2781 gs->gs_copy_shader = cshader;
2782 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2783
2784 ctx.bc->nstack = 1;
2785
2786 return r600_bytecode_build(ctx.bc);
2787 }
2788
2789 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2790 {
2791 if (ind) {
2792 struct r600_bytecode_alu alu;
2793 int r;
2794
2795 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2796 alu.op = ALU_OP2_ADD_INT;
2797 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2798 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2799 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2800 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2801 alu.dst.write = 1;
2802 alu.last = 1;
2803 r = r600_bytecode_add_alu(ctx->bc, &alu);
2804 if (r)
2805 return r;
2806 }
2807 return 0;
2808 }
2809
2810 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so UNUSED, int stream, bool ind)
2811 {
2812 struct r600_bytecode_output output;
2813 int ring_offset;
2814 unsigned i, k;
2815 int effective_stream = stream == -1 ? 0 : stream;
2816 int idx = 0;
2817
2818 for (i = 0; i < ctx->shader->noutput; i++) {
2819 if (ctx->gs_for_vs) {
2820 /* for ES we need to lookup corresponding ring offset expected by GS
2821 * (map this output to GS input by name and sid) */
2822 /* FIXME precompute offsets */
2823 ring_offset = -1;
2824 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2825 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2826 struct r600_shader_io *out = &ctx->shader->output[i];
2827 if (in->name == out->name && in->sid == out->sid)
2828 ring_offset = in->ring_offset;
2829 }
2830
2831 if (ring_offset == -1)
2832 continue;
2833 } else {
2834 ring_offset = idx * 16;
2835 idx++;
2836 }
2837
2838 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2839 continue;
2840 /* next_ring_offset after parsing input decls contains total size of
2841 * single vertex data, gs_next_vertex - current vertex index */
2842 if (!ind)
2843 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2844
2845 memset(&output, 0, sizeof(struct r600_bytecode_output));
2846 output.gpr = ctx->shader->output[i].gpr;
2847 output.elem_size = 3;
2848 output.comp_mask = 0xF;
2849 output.burst_count = 1;
2850
2851 if (ind)
2852 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2853 else
2854 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2855
2856 switch (stream) {
2857 default:
2858 case 0:
2859 output.op = CF_OP_MEM_RING; break;
2860 case 1:
2861 output.op = CF_OP_MEM_RING1; break;
2862 case 2:
2863 output.op = CF_OP_MEM_RING2; break;
2864 case 3:
2865 output.op = CF_OP_MEM_RING3; break;
2866 }
2867
2868 if (ind) {
2869 output.array_base = ring_offset >> 2; /* in dwords */
2870 output.array_size = 0xfff;
2871 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2872 } else
2873 output.array_base = ring_offset >> 2; /* in dwords */
2874 r600_bytecode_add_output(ctx->bc, &output);
2875 }
2876
2877 ++ctx->gs_next_vertex;
2878 return 0;
2879 }
2880
2881
2882 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2883 {
2884 int r;
2885 struct r600_bytecode_vtx vtx;
2886 int temp_val = ctx->temp_reg;
2887 /* need to store the TCS output somewhere */
2888 r = single_alu_op2(ctx, ALU_OP1_MOV,
2889 temp_val, 0,
2890 V_SQ_ALU_SRC_LITERAL, 0,
2891 0, 0);
2892 if (r)
2893 return r;
2894
2895 /* used by VS/TCS */
2896 if (ctx->tess_input_info) {
2897 /* fetch tcs input values into resv space */
2898 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2899 vtx.op = FETCH_OP_VFETCH;
2900 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2901 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2902 vtx.mega_fetch_count = 16;
2903 vtx.data_format = FMT_32_32_32_32;
2904 vtx.num_format_all = 2;
2905 vtx.format_comp_all = 1;
2906 vtx.use_const_fields = 0;
2907 vtx.endian = r600_endian_swap(32);
2908 vtx.srf_mode_all = 1;
2909 vtx.offset = 0;
2910 vtx.dst_gpr = ctx->tess_input_info;
2911 vtx.dst_sel_x = 0;
2912 vtx.dst_sel_y = 1;
2913 vtx.dst_sel_z = 2;
2914 vtx.dst_sel_w = 3;
2915 vtx.src_gpr = temp_val;
2916 vtx.src_sel_x = 0;
2917
2918 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2919 if (r)
2920 return r;
2921 }
2922
2923 /* used by TCS/TES */
2924 if (ctx->tess_output_info) {
2925 /* fetch tcs output values into resv space */
2926 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2927 vtx.op = FETCH_OP_VFETCH;
2928 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2929 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2930 vtx.mega_fetch_count = 16;
2931 vtx.data_format = FMT_32_32_32_32;
2932 vtx.num_format_all = 2;
2933 vtx.format_comp_all = 1;
2934 vtx.use_const_fields = 0;
2935 vtx.endian = r600_endian_swap(32);
2936 vtx.srf_mode_all = 1;
2937 vtx.offset = 16;
2938 vtx.dst_gpr = ctx->tess_output_info;
2939 vtx.dst_sel_x = 0;
2940 vtx.dst_sel_y = 1;
2941 vtx.dst_sel_z = 2;
2942 vtx.dst_sel_w = 3;
2943 vtx.src_gpr = temp_val;
2944 vtx.src_sel_x = 0;
2945
2946 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2947 if (r)
2948 return r;
2949 }
2950 return 0;
2951 }
2952
2953 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2954 {
2955 int j, r;
2956 int temp_reg;
2957 unsigned i;
2958
2959 /* fetch tcs input values into input_vals */
2960 ctx->tess_input_info = r600_get_temp(ctx);
2961 ctx->tess_output_info = 0;
2962 r = r600_fetch_tess_io_info(ctx);
2963 if (r)
2964 return r;
2965
2966 temp_reg = r600_get_temp(ctx);
2967 /* dst reg contains LDS address stride * idx */
2968 /* MUL vertexID, vertex_dw_stride */
2969 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2970 temp_reg, 0,
2971 ctx->tess_input_info, 1,
2972 0, 1); /* rel id in r0.y? */
2973 if (r)
2974 return r;
2975
2976 for (i = 0; i < ctx->shader->noutput; i++) {
2977 struct r600_bytecode_alu alu;
2978 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2979
2980 if (param) {
2981 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2982 temp_reg, 1,
2983 temp_reg, 0,
2984 V_SQ_ALU_SRC_LITERAL, param * 16);
2985 if (r)
2986 return r;
2987 }
2988
2989 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2990 temp_reg, 2,
2991 temp_reg, param ? 1 : 0,
2992 V_SQ_ALU_SRC_LITERAL, 8);
2993 if (r)
2994 return r;
2995
2996
2997 for (j = 0; j < 2; j++) {
2998 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3000 alu.op = LDS_OP3_LDS_WRITE_REL;
3001 alu.src[0].sel = temp_reg;
3002 alu.src[0].chan = chan;
3003 alu.src[1].sel = ctx->shader->output[i].gpr;
3004 alu.src[1].chan = j * 2;
3005 alu.src[2].sel = ctx->shader->output[i].gpr;
3006 alu.src[2].chan = (j * 2) + 1;
3007 alu.last = 1;
3008 alu.dst.chan = 0;
3009 alu.lds_idx = 1;
3010 alu.is_lds_idx_op = true;
3011 r = r600_bytecode_add_alu(ctx->bc, &alu);
3012 if (r)
3013 return r;
3014 }
3015 }
3016 return 0;
3017 }
3018
3019 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
3020 {
3021 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3022 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
3023 int i, r, lasti;
3024 int temp_reg = r600_get_temp(ctx);
3025 struct r600_bytecode_alu alu;
3026 unsigned write_mask = dst->Register.WriteMask;
3027
3028 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
3029 return 0;
3030
3031 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
3032 if (r)
3033 return r;
3034
3035 /* the base address is now in temp.x */
3036 r = r600_get_byte_address(ctx, temp_reg,
3037 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
3038 if (r)
3039 return r;
3040
3041 /* LDS write */
3042 lasti = tgsi_last_instruction(write_mask);
3043 for (i = 1; i <= lasti; i++) {
3044
3045 if (!(write_mask & (1 << i)))
3046 continue;
3047 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3048 temp_reg, i,
3049 temp_reg, 0,
3050 V_SQ_ALU_SRC_LITERAL, 4 * i);
3051 if (r)
3052 return r;
3053 }
3054
3055 for (i = 0; i <= lasti; i++) {
3056 if (!(write_mask & (1 << i)))
3057 continue;
3058
3059 if ((i == 0 && ((write_mask & 3) == 3)) ||
3060 (i == 2 && ((write_mask & 0xc) == 0xc))) {
3061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3062 alu.op = LDS_OP3_LDS_WRITE_REL;
3063 alu.src[0].sel = temp_reg;
3064 alu.src[0].chan = i;
3065
3066 alu.src[1].sel = dst->Register.Index;
3067 alu.src[1].sel += ctx->file_offset[dst->Register.File];
3068 alu.src[1].chan = i;
3069
3070 alu.src[2].sel = dst->Register.Index;
3071 alu.src[2].sel += ctx->file_offset[dst->Register.File];
3072 alu.src[2].chan = i + 1;
3073 alu.lds_idx = 1;
3074 alu.dst.chan = 0;
3075 alu.last = 1;
3076 alu.is_lds_idx_op = true;
3077 r = r600_bytecode_add_alu(ctx->bc, &alu);
3078 if (r)
3079 return r;
3080 i += 1;
3081 continue;
3082 }
3083 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3084 alu.op = LDS_OP2_LDS_WRITE;
3085 alu.src[0].sel = temp_reg;
3086 alu.src[0].chan = i;
3087
3088 alu.src[1].sel = dst->Register.Index;
3089 alu.src[1].sel += ctx->file_offset[dst->Register.File];
3090 alu.src[1].chan = i;
3091
3092 alu.src[2].sel = V_SQ_ALU_SRC_0;
3093 alu.dst.chan = 0;
3094 alu.last = 1;
3095 alu.is_lds_idx_op = true;
3096 r = r600_bytecode_add_alu(ctx->bc, &alu);
3097 if (r)
3098 return r;
3099 }
3100 return 0;
3101 }
3102
3103 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
3104 int output_idx, int nc)
3105 {
3106 int param;
3107 unsigned temp_reg = r600_get_temp(ctx);
3108 unsigned name = ctx->shader->output[output_idx].name;
3109 int dreg = ctx->shader->output[output_idx].gpr;
3110 int r;
3111
3112 param = r600_get_lds_unique_index(name, 0);
3113 r = get_lds_offset0(ctx, 1, temp_reg, true);
3114 if (r)
3115 return r;
3116
3117 if (param) {
3118 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3119 temp_reg, 0,
3120 temp_reg, 0,
3121 V_SQ_ALU_SRC_LITERAL, param * 16);
3122 if (r)
3123 return r;
3124 }
3125
3126 do_lds_fetch_values(ctx, temp_reg, dreg, ((1u << nc) - 1));
3127 return 0;
3128 }
3129
3130 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
3131 {
3132 int stride, outer_comps, inner_comps;
3133 int tessinner_idx = -1, tessouter_idx = -1;
3134 int i, r;
3135 unsigned j;
3136 int temp_reg = r600_get_temp(ctx);
3137 int treg[3] = {-1, -1, -1};
3138 struct r600_bytecode_alu alu;
3139 struct r600_bytecode_cf *cf_jump, *cf_pop;
3140
3141 /* only execute factor emission for invocation 0 */
3142 /* PRED_SETE_INT __, R0.x, 0 */
3143 memset(&alu, 0, sizeof(alu));
3144 alu.op = ALU_OP2_PRED_SETE_INT;
3145 alu.src[0].chan = 2;
3146 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3147 alu.execute_mask = 1;
3148 alu.update_pred = 1;
3149 alu.last = 1;
3150 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
3151
3152 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
3153 cf_jump = ctx->bc->cf_last;
3154
3155 treg[0] = r600_get_temp(ctx);
3156 switch (ctx->shader->tcs_prim_mode) {
3157 case PIPE_PRIM_LINES:
3158 stride = 8; /* 2 dwords, 1 vec2 store */
3159 outer_comps = 2;
3160 inner_comps = 0;
3161 break;
3162 case PIPE_PRIM_TRIANGLES:
3163 stride = 16; /* 4 dwords, 1 vec4 store */
3164 outer_comps = 3;
3165 inner_comps = 1;
3166 treg[1] = r600_get_temp(ctx);
3167 break;
3168 case PIPE_PRIM_QUADS:
3169 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
3170 outer_comps = 4;
3171 inner_comps = 2;
3172 treg[1] = r600_get_temp(ctx);
3173 treg[2] = r600_get_temp(ctx);
3174 break;
3175 default:
3176 assert(0);
3177 return -1;
3178 }
3179
3180 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
3181 /* TF_WRITE takes index in R.x, value in R.y */
3182 for (j = 0; j < ctx->shader->noutput; j++) {
3183 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSINNER)
3184 tessinner_idx = j;
3185 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSOUTER)
3186 tessouter_idx = j;
3187 }
3188
3189 if (tessouter_idx == -1)
3190 return -1;
3191
3192 if (tessinner_idx == -1 && inner_comps)
3193 return -1;
3194
3195 if (tessouter_idx != -1) {
3196 r = r600_tess_factor_read(ctx, tessouter_idx, outer_comps);
3197 if (r)
3198 return r;
3199 }
3200
3201 if (tessinner_idx != -1) {
3202 r = r600_tess_factor_read(ctx, tessinner_idx, inner_comps);
3203 if (r)
3204 return r;
3205 }
3206
3207 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
3208 /* r.x = relpatchid(r0.y) * tf_stride */
3209
3210 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
3211 /* add incoming r0.w to it: t.x = t.x + r0.w */
3212 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3213 temp_reg, 0,
3214 0, 1,
3215 V_SQ_ALU_SRC_LITERAL, stride,
3216 0, 3);
3217 if (r)
3218 return r;
3219
3220 for (i = 0; i < outer_comps + inner_comps; i++) {
3221 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
3222 int out_comp = i >= outer_comps ? i - outer_comps : i;
3223
3224 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
3225 if (out_comp == 1)
3226 out_comp = 0;
3227 else if (out_comp == 0)
3228 out_comp = 1;
3229 }
3230
3231 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
3232 treg[i / 2], (2 * (i % 2)),
3233 temp_reg, 0,
3234 V_SQ_ALU_SRC_LITERAL, 4 * i);
3235 if (r)
3236 return r;
3237 r = single_alu_op2(ctx, ALU_OP1_MOV,
3238 treg[i / 2], 1 + (2 * (i%2)),
3239 ctx->shader->output[out_idx].gpr, out_comp,
3240 0, 0);
3241 if (r)
3242 return r;
3243 }
3244 for (i = 0; i < outer_comps + inner_comps; i++) {
3245 struct r600_bytecode_gds gds;
3246
3247 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
3248 gds.src_gpr = treg[i / 2];
3249 gds.src_sel_x = 2 * (i % 2);
3250 gds.src_sel_y = 1 + (2 * (i % 2));
3251 gds.src_sel_z = 4;
3252 gds.dst_sel_x = 7;
3253 gds.dst_sel_y = 7;
3254 gds.dst_sel_z = 7;
3255 gds.dst_sel_w = 7;
3256 gds.op = FETCH_OP_TF_WRITE;
3257 r = r600_bytecode_add_gds(ctx->bc, &gds);
3258 if (r)
3259 return r;
3260 }
3261
3262 // Patch up jump label
3263 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
3264 cf_pop = ctx->bc->cf_last;
3265
3266 cf_jump->cf_addr = cf_pop->id + 2;
3267 cf_jump->pop_count = 1;
3268 cf_pop->cf_addr = cf_pop->id + 2;
3269 cf_pop->pop_count = 1;
3270
3271 return 0;
3272 }
3273
3274 /*
3275 * We have to work out the thread ID for load and atomic
3276 * operations, which store the returned value to an index
3277 * in an intermediate buffer.
3278 * The index is calculated by taking the thread id,
3279 * calculated from the MBCNT instructions.
3280 * Then the shader engine ID is multiplied by 256,
3281 * and the wave id is added.
3282 * Then the result is multipled by 64 and thread id is
3283 * added.
3284 */
3285 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
3286 {
3287 struct r600_bytecode_alu alu;
3288 int r;
3289
3290 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3291 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
3292 alu.dst.sel = ctx->temp_reg;
3293 alu.dst.chan = 0;
3294 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3295 alu.src[0].value = 0xffffffff;
3296 alu.dst.write = 1;
3297 r = r600_bytecode_add_alu(ctx->bc, &alu);
3298 if (r)
3299 return r;
3300
3301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3302 alu.op = ALU_OP1_MBCNT_32HI_INT;
3303 alu.dst.sel = ctx->temp_reg;
3304 alu.dst.chan = 1;
3305 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3306 alu.src[0].value = 0xffffffff;
3307 alu.dst.write = 1;
3308 r = r600_bytecode_add_alu(ctx->bc, &alu);
3309 if (r)
3310 return r;
3311
3312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3313 alu.op = ALU_OP3_MULADD_UINT24;
3314 alu.dst.sel = ctx->temp_reg;
3315 alu.dst.chan = 2;
3316 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
3317 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3318 alu.src[1].value = 256;
3319 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
3320 alu.dst.write = 1;
3321 alu.is_op3 = 1;
3322 alu.last = 1;
3323 r = r600_bytecode_add_alu(ctx->bc, &alu);
3324 if (r)
3325 return r;
3326
3327 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3328 ctx->thread_id_gpr, 1,
3329 ctx->temp_reg, 2,
3330 V_SQ_ALU_SRC_LITERAL, 0x40,
3331 ctx->temp_reg, 0);
3332 if (r)
3333 return r;
3334 return 0;
3335 }
3336
3337 static int r600_shader_from_tgsi(struct r600_context *rctx,
3338 struct r600_pipe_shader *pipeshader,
3339 union r600_shader_key key)
3340 {
3341 struct r600_screen *rscreen = rctx->screen;
3342 struct r600_shader *shader = &pipeshader->shader;
3343 struct tgsi_token *tokens = pipeshader->selector->tokens;
3344 struct pipe_stream_output_info so = pipeshader->selector->so;
3345 struct tgsi_full_immediate *immediate;
3346 struct r600_shader_ctx ctx;
3347 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3348 unsigned output_done, noutput;
3349 unsigned opcode;
3350 int j, k, r = 0;
3351 unsigned i;
3352 int next_param_base = 0, next_clip_base;
3353 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3354 bool indirect_gprs;
3355 bool ring_outputs = false;
3356 bool lds_outputs = false;
3357 bool lds_inputs = false;
3358 bool pos_emitted = false;
3359
3360 ctx.bc = &shader->bc;
3361 ctx.shader = shader;
3362
3363 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3364 rscreen->has_compressed_msaa_texturing);
3365 ctx.tokens = tokens;
3366 tgsi_scan_shader(tokens, &ctx.info);
3367 shader->indirect_files = ctx.info.indirect_files;
3368
3369 int narrays = ctx.info.array_max[TGSI_FILE_TEMPORARY];
3370 ctx.array_infos = calloc(narrays, sizeof(*ctx.array_infos));
3371 ctx.spilled_arrays = calloc(narrays, sizeof(bool));
3372 tgsi_scan_arrays(tokens, TGSI_FILE_TEMPORARY, narrays, ctx.array_infos);
3373
3374 shader->uses_helper_invocation = false;
3375 shader->uses_doubles = ctx.info.uses_doubles;
3376 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3377 shader->nsys_inputs = 0;
3378
3379 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0 ||
3380 ctx.info.file_count[TGSI_FILE_BUFFER] > 0;
3381 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3382 tgsi_parse_init(&ctx.parse, tokens);
3383 ctx.type = ctx.info.processor;
3384 shader->processor_type = ctx.type;
3385 ctx.bc->type = shader->processor_type;
3386
3387 switch (ctx.type) {
3388 case PIPE_SHADER_VERTEX:
3389 shader->vs_as_gs_a = key.vs.as_gs_a;
3390 shader->vs_as_es = key.vs.as_es;
3391 shader->vs_as_ls = key.vs.as_ls;
3392 shader->atomic_base = key.vs.first_atomic_counter;
3393 if (shader->vs_as_es)
3394 ring_outputs = true;
3395 if (shader->vs_as_ls)
3396 lds_outputs = true;
3397 break;
3398 case PIPE_SHADER_GEOMETRY:
3399 ring_outputs = true;
3400 shader->atomic_base = key.gs.first_atomic_counter;
3401 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3402 break;
3403 case PIPE_SHADER_TESS_CTRL:
3404 shader->tcs_prim_mode = key.tcs.prim_mode;
3405 shader->atomic_base = key.tcs.first_atomic_counter;
3406 lds_outputs = true;
3407 lds_inputs = true;
3408 break;
3409 case PIPE_SHADER_TESS_EVAL:
3410 shader->tes_as_es = key.tes.as_es;
3411 shader->atomic_base = key.tes.first_atomic_counter;
3412 lds_inputs = true;
3413 if (shader->tes_as_es)
3414 ring_outputs = true;
3415 break;
3416 case PIPE_SHADER_FRAGMENT:
3417 shader->two_side = key.ps.color_two_side;
3418 shader->atomic_base = key.ps.first_atomic_counter;
3419 shader->rat_base = key.ps.nr_cbufs;
3420 shader->image_size_const_offset = key.ps.image_size_const_offset;
3421 break;
3422 case PIPE_SHADER_COMPUTE:
3423 shader->rat_base = 0;
3424 shader->image_size_const_offset = ctx.info.file_count[TGSI_FILE_SAMPLER];
3425 break;
3426 default:
3427 break;
3428 }
3429
3430 if (shader->vs_as_es || shader->tes_as_es) {
3431 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3432 } else {
3433 ctx.gs_for_vs = NULL;
3434 }
3435
3436 ctx.next_ring_offset = 0;
3437 ctx.gs_out_ring_offset = 0;
3438 ctx.gs_next_vertex = 0;
3439 ctx.gs_stream_output_info = &so;
3440
3441 ctx.thread_id_gpr = -1;
3442 ctx.face_gpr = -1;
3443 ctx.fixed_pt_position_gpr = -1;
3444 ctx.fragcoord_input = -1;
3445 ctx.colors_used = 0;
3446 ctx.clip_vertex_write = 0;
3447
3448 ctx.helper_invoc_reg = -1;
3449 ctx.cs_block_size_reg = -1;
3450 ctx.cs_grid_size_reg = -1;
3451 ctx.cs_block_size_loaded = false;
3452 ctx.cs_grid_size_loaded = false;
3453
3454 shader->nr_ps_color_exports = 0;
3455 shader->nr_ps_max_color_exports = 0;
3456
3457
3458 /* register allocations */
3459 /* Values [0,127] correspond to GPR[0..127].
3460 * Values [128,159] correspond to constant buffer bank 0
3461 * Values [160,191] correspond to constant buffer bank 1
3462 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3463 * Values [256,287] correspond to constant buffer bank 2 (EG)
3464 * Values [288,319] correspond to constant buffer bank 3 (EG)
3465 * Other special values are shown in the list below.
3466 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3467 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3468 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3469 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3470 * 248 SQ_ALU_SRC_0: special constant 0.0.
3471 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3472 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3473 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3474 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3475 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3476 * 254 SQ_ALU_SRC_PV: previous vector result.
3477 * 255 SQ_ALU_SRC_PS: previous scalar result.
3478 */
3479 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3480 ctx.file_offset[i] = 0;
3481 }
3482
3483 if (ctx.type == PIPE_SHADER_VERTEX) {
3484
3485 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3486 if (ctx.info.num_inputs)
3487 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3488 }
3489 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3490 if (ctx.bc->chip_class >= EVERGREEN)
3491 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3492 else
3493 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3494
3495 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3496 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_HELPER_INVOCATION) {
3497 ctx.helper_invoc_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3498 shader->uses_helper_invocation = true;
3499 }
3500 }
3501 }
3502 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3503 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3504 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3505 }
3506 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3507 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3508 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3509 bool add_tesscoord = false, add_tess_inout = false;
3510 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3511 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3512 /* if we have tesscoord save one reg */
3513 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3514 add_tesscoord = true;
3515 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3516 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3517 add_tess_inout = true;
3518 }
3519 if (add_tesscoord || add_tess_inout)
3520 ctx.file_offset[TGSI_FILE_INPUT]++;
3521 if (add_tess_inout)
3522 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3523 }
3524 if (ctx.type == PIPE_SHADER_COMPUTE) {
3525 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3526 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3527 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_GRID_SIZE)
3528 ctx.cs_grid_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3529 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_BLOCK_SIZE)
3530 ctx.cs_block_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3531 }
3532 }
3533
3534 ctx.file_offset[TGSI_FILE_OUTPUT] =
3535 ctx.file_offset[TGSI_FILE_INPUT] +
3536 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3537 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3538 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3539
3540 /* Outside the GPR range. This will be translated to one of the
3541 * kcache banks later. */
3542 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3543 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3544
3545 pipeshader->scratch_space_needed = 0;
3546 int regno = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3547 ctx.info.file_max[TGSI_FILE_TEMPORARY];
3548 if (regno > 124) {
3549 choose_spill_arrays(&ctx, &regno, &pipeshader->scratch_space_needed);
3550 shader->indirect_files = ctx.info.indirect_files;
3551 }
3552 shader->needs_scratch_space = pipeshader->scratch_space_needed != 0;
3553
3554 ctx.bc->ar_reg = ++regno;
3555 ctx.bc->index_reg[0] = ++regno;
3556 ctx.bc->index_reg[1] = ++regno;
3557
3558 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3559 ctx.tess_input_info = ++regno;
3560 ctx.tess_output_info = ++regno;
3561 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3562 ctx.tess_input_info = 0;
3563 ctx.tess_output_info = ++regno;
3564 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3565 ctx.gs_export_gpr_tregs[0] = ++regno;
3566 ctx.gs_export_gpr_tregs[1] = ++regno;
3567 ctx.gs_export_gpr_tregs[2] = ++regno;
3568 ctx.gs_export_gpr_tregs[3] = ++regno;
3569 if (ctx.shader->gs_tri_strip_adj_fix) {
3570 ctx.gs_rotated_input[0] = ++regno;
3571 ctx.gs_rotated_input[1] = ++regno;
3572 } else {
3573 ctx.gs_rotated_input[0] = 0;
3574 ctx.gs_rotated_input[1] = 1;
3575 }
3576 }
3577
3578 if (shader->uses_images) {
3579 ctx.thread_id_gpr = ++regno;
3580 }
3581 ctx.temp_reg = ++regno;
3582
3583 shader->max_arrays = 0;
3584 shader->num_arrays = 0;
3585 if (indirect_gprs) {
3586
3587 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3588 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3589 ctx.file_offset[TGSI_FILE_OUTPUT] -
3590 ctx.file_offset[TGSI_FILE_INPUT],
3591 0x0F);
3592 }
3593 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3594 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3595 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3596 ctx.file_offset[TGSI_FILE_OUTPUT],
3597 0x0F);
3598 }
3599 }
3600
3601 ctx.nliterals = 0;
3602 ctx.literals = NULL;
3603 ctx.max_driver_temp_used = 0;
3604
3605 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3606 ctx.info.colors_written == 1;
3607 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3608 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3609
3610 if (ctx.type == PIPE_SHADER_VERTEX ||
3611 ctx.type == PIPE_SHADER_GEOMETRY ||
3612 ctx.type == PIPE_SHADER_TESS_EVAL) {
3613 shader->cc_dist_mask = (1 << (ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED] +
3614 ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED])) - 1;
3615 shader->clip_dist_write = (1 << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED]) - 1;
3616 shader->cull_dist_write = ((1 << ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED]) - 1) << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED];
3617 }
3618
3619 if (shader->vs_as_gs_a)
3620 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3621
3622 if (ctx.thread_id_gpr != -1) {
3623 r = load_thread_id_gpr(&ctx);
3624 if (r)
3625 return r;
3626 }
3627
3628 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3629 r600_fetch_tess_io_info(&ctx);
3630
3631 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3632 tgsi_parse_token(&ctx.parse);
3633 switch (ctx.parse.FullToken.Token.Type) {
3634 case TGSI_TOKEN_TYPE_IMMEDIATE:
3635 immediate = &ctx.parse.FullToken.FullImmediate;
3636 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3637 if(ctx.literals == NULL) {
3638 r = -ENOMEM;
3639 goto out_err;
3640 }
3641 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3642 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3643 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3644 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3645 ctx.nliterals++;
3646 break;
3647 case TGSI_TOKEN_TYPE_DECLARATION:
3648 r = tgsi_declaration(&ctx);
3649 if (r)
3650 goto out_err;
3651 break;
3652 case TGSI_TOKEN_TYPE_INSTRUCTION:
3653 case TGSI_TOKEN_TYPE_PROPERTY:
3654 break;
3655 default:
3656 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3657 r = -EINVAL;
3658 goto out_err;
3659 }
3660 }
3661
3662 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3663 shader->ring_item_sizes[1] = 0;
3664 shader->ring_item_sizes[2] = 0;
3665 shader->ring_item_sizes[3] = 0;
3666
3667 /* Process two side if needed */
3668 if (shader->two_side && ctx.colors_used) {
3669 int i, count = ctx.shader->ninput;
3670 unsigned next_lds_loc = ctx.shader->nlds;
3671
3672 /* additional inputs will be allocated right after the existing inputs,
3673 * we won't need them after the color selection, so we don't need to
3674 * reserve these gprs for the rest of the shader code and to adjust
3675 * output offsets etc. */
3676 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3677 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3678
3679 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3680 if (ctx.face_gpr == -1) {
3681 i = ctx.shader->ninput++;
3682 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3683 ctx.shader->input[i].spi_sid = 0;
3684 ctx.shader->input[i].gpr = gpr++;
3685 ctx.face_gpr = ctx.shader->input[i].gpr;
3686 }
3687
3688 for (i = 0; i < count; i++) {
3689 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3690 int ni = ctx.shader->ninput++;
3691 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3692 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3693 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3694 ctx.shader->input[ni].gpr = gpr++;
3695 // TGSI to LLVM needs to know the lds position of inputs.
3696 // Non LLVM path computes it later (in process_twoside_color)
3697 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3698 ctx.shader->input[i].back_color_input = ni;
3699 if (ctx.bc->chip_class >= EVERGREEN) {
3700 if ((r = evergreen_interp_input(&ctx, ni)))
3701 return r;
3702 }
3703 }
3704 }
3705 }
3706
3707 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3708 shader->nr_ps_max_color_exports = 8;
3709
3710 if (ctx.shader->uses_helper_invocation) {
3711 if (ctx.bc->chip_class == CAYMAN)
3712 r = cm_load_helper_invocation(&ctx);
3713 else
3714 r = eg_load_helper_invocation(&ctx);
3715 if (r)
3716 return r;
3717 }
3718
3719 /*
3720 * XXX this relies on fixed_pt_position_gpr only being present when
3721 * this shader should be executed per sample. Should be the case for now...
3722 */
3723 if (ctx.fixed_pt_position_gpr != -1 && ctx.info.reads_samplemask) {
3724 /*
3725 * Fix up sample mask. The hw always gives us coverage mask for
3726 * the pixel. However, for per-sample shading, we need the
3727 * coverage for the shader invocation only.
3728 * Also, with disabled msaa, only the first bit should be set
3729 * (luckily the same fixup works for both problems).
3730 * For now, we can only do it if we know this shader is always
3731 * executed per sample (due to usage of bits in the shader
3732 * forcing per-sample execution).
3733 * If the fb is not multisampled, we'd do unnecessary work but
3734 * it should still be correct.
3735 * It will however do nothing for sample shading according
3736 * to MinSampleShading.
3737 */
3738 struct r600_bytecode_alu alu;
3739 int tmp = r600_get_temp(&ctx);
3740 assert(ctx.face_gpr != -1);
3741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3742
3743 alu.op = ALU_OP2_LSHL_INT;
3744 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3745 alu.src[0].value = 0x1;
3746 alu.src[1].sel = ctx.fixed_pt_position_gpr;
3747 alu.src[1].chan = 3;
3748 alu.dst.sel = tmp;
3749 alu.dst.chan = 0;
3750 alu.dst.write = 1;
3751 alu.last = 1;
3752 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3753 return r;
3754
3755 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3756 alu.op = ALU_OP2_AND_INT;
3757 alu.src[0].sel = tmp;
3758 alu.src[1].sel = ctx.face_gpr;
3759 alu.src[1].chan = 2;
3760 alu.dst.sel = ctx.face_gpr;
3761 alu.dst.chan = 2;
3762 alu.dst.write = 1;
3763 alu.last = 1;
3764 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3765 return r;
3766 }
3767
3768 if (ctx.fragcoord_input >= 0) {
3769 if (ctx.bc->chip_class == CAYMAN) {
3770 for (j = 0 ; j < 4; j++) {
3771 struct r600_bytecode_alu alu;
3772 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3773 alu.op = ALU_OP1_RECIP_IEEE;
3774 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3775 alu.src[0].chan = 3;
3776
3777 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3778 alu.dst.chan = j;
3779 alu.dst.write = (j == 3);
3780 alu.last = (j == 3);
3781 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3782 return r;
3783 }
3784 } else {
3785 struct r600_bytecode_alu alu;
3786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3787 alu.op = ALU_OP1_RECIP_IEEE;
3788 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3789 alu.src[0].chan = 3;
3790
3791 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3792 alu.dst.chan = 3;
3793 alu.dst.write = 1;
3794 alu.last = 1;
3795 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3796 return r;
3797 }
3798 }
3799
3800 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3801 struct r600_bytecode_alu alu;
3802 int r;
3803
3804 /* GS thread with no output workaround - emit a cut at start of GS */
3805 if (ctx.bc->chip_class == R600)
3806 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3807
3808 for (j = 0; j < 4; j++) {
3809 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3810 alu.op = ALU_OP1_MOV;
3811 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3812 alu.src[0].value = 0;
3813 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3814 alu.dst.write = 1;
3815 alu.last = 1;
3816 r = r600_bytecode_add_alu(ctx.bc, &alu);
3817 if (r)
3818 return r;
3819 }
3820
3821 if (ctx.shader->gs_tri_strip_adj_fix) {
3822 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3823 ctx.gs_rotated_input[0], 2,
3824 0, 2,
3825 V_SQ_ALU_SRC_LITERAL, 1);
3826 if (r)
3827 return r;
3828
3829 for (i = 0; i < 6; i++) {
3830 int rotated = (i + 4) % 6;
3831 int offset_reg = i / 3;
3832 int offset_chan = i % 3;
3833 int rotated_offset_reg = rotated / 3;
3834 int rotated_offset_chan = rotated % 3;
3835
3836 if (offset_reg == 0 && offset_chan == 2)
3837 offset_chan = 3;
3838 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3839 rotated_offset_chan = 3;
3840
3841 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3842 ctx.gs_rotated_input[offset_reg], offset_chan,
3843 ctx.gs_rotated_input[0], 2,
3844 offset_reg, offset_chan,
3845 rotated_offset_reg, rotated_offset_chan);
3846 if (r)
3847 return r;
3848 }
3849 }
3850 }
3851
3852 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3853 r600_fetch_tess_io_info(&ctx);
3854
3855 if (shader->two_side && ctx.colors_used) {
3856 if ((r = process_twoside_color_inputs(&ctx)))
3857 return r;
3858 }
3859
3860 tgsi_parse_init(&ctx.parse, tokens);
3861 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3862 tgsi_parse_token(&ctx.parse);
3863 switch (ctx.parse.FullToken.Token.Type) {
3864 case TGSI_TOKEN_TYPE_INSTRUCTION:
3865 r = tgsi_is_supported(&ctx);
3866 if (r)
3867 goto out_err;
3868 ctx.max_driver_temp_used = 0;
3869 /* reserve first tmp for everyone */
3870 r600_get_temp(&ctx);
3871
3872 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3873 if ((r = tgsi_split_constant(&ctx)))
3874 goto out_err;
3875 if ((r = tgsi_split_literal_constant(&ctx)))
3876 goto out_err;
3877 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3878 if ((r = tgsi_split_gs_inputs(&ctx)))
3879 goto out_err;
3880 } else if (lds_inputs) {
3881 if ((r = tgsi_split_lds_inputs(&ctx)))
3882 goto out_err;
3883 }
3884 if (ctx.bc->chip_class == CAYMAN)
3885 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3886 else if (ctx.bc->chip_class >= EVERGREEN)
3887 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3888 else
3889 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3890 r = ctx.inst_info->process(&ctx);
3891 if (r)
3892 goto out_err;
3893
3894 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3895 r = r600_store_tcs_output(&ctx);
3896 if (r)
3897 goto out_err;
3898 }
3899 break;
3900 default:
3901 break;
3902 }
3903 }
3904
3905 /* Reset the temporary register counter. */
3906 ctx.max_driver_temp_used = 0;
3907
3908 noutput = shader->noutput;
3909
3910 if (!ring_outputs && ctx.clip_vertex_write) {
3911 unsigned clipdist_temp[2];
3912
3913 clipdist_temp[0] = r600_get_temp(&ctx);
3914 clipdist_temp[1] = r600_get_temp(&ctx);
3915
3916 /* need to convert a clipvertex write into clipdistance writes and not export
3917 the clip vertex anymore */
3918
3919 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3920 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3921 shader->output[noutput].gpr = clipdist_temp[0];
3922 noutput++;
3923 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3924 shader->output[noutput].gpr = clipdist_temp[1];
3925 noutput++;
3926
3927 /* reset spi_sid for clipvertex output to avoid confusing spi */
3928 shader->output[ctx.cv_output].spi_sid = 0;
3929
3930 shader->clip_dist_write = 0xFF;
3931 shader->cc_dist_mask = 0xFF;
3932
3933 for (i = 0; i < 8; i++) {
3934 int oreg = i >> 2;
3935 int ochan = i & 3;
3936
3937 for (j = 0; j < 4; j++) {
3938 struct r600_bytecode_alu alu;
3939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3940 alu.op = ALU_OP2_DOT4;
3941 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3942 alu.src[0].chan = j;
3943
3944 alu.src[1].sel = 512 + i;
3945 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3946 alu.src[1].chan = j;
3947
3948 alu.dst.sel = clipdist_temp[oreg];
3949 alu.dst.chan = j;
3950 alu.dst.write = (j == ochan);
3951 if (j == 3)
3952 alu.last = 1;
3953 r = r600_bytecode_add_alu(ctx.bc, &alu);
3954 if (r)
3955 return r;
3956 }
3957 }
3958 }
3959
3960 /* Add stream outputs. */
3961 if (so.num_outputs) {
3962 bool emit = false;
3963 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3964 emit = true;
3965 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3966 emit = true;
3967 if (emit)
3968 emit_streamout(&ctx, &so, -1, NULL);
3969 }
3970 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3971 convert_edgeflag_to_int(&ctx);
3972
3973 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3974 r600_emit_tess_factor(&ctx);
3975
3976 if (lds_outputs) {
3977 if (ctx.type == PIPE_SHADER_VERTEX) {
3978 if (ctx.shader->noutput)
3979 emit_lds_vs_writes(&ctx);
3980 }
3981 } else if (ring_outputs) {
3982 if (shader->vs_as_es || shader->tes_as_es) {
3983 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3984 ctx.gs_export_gpr_tregs[1] = -1;
3985 ctx.gs_export_gpr_tregs[2] = -1;
3986 ctx.gs_export_gpr_tregs[3] = -1;
3987
3988 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3989 }
3990 } else {
3991 /* Export output */
3992 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3993
3994 for (i = 0, j = 0; i < noutput; i++, j++) {
3995 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3996 output[j].gpr = shader->output[i].gpr;
3997 output[j].elem_size = 3;
3998 output[j].swizzle_x = 0;
3999 output[j].swizzle_y = 1;
4000 output[j].swizzle_z = 2;
4001 output[j].swizzle_w = 3;
4002 output[j].burst_count = 1;
4003 output[j].type = 0xffffffff;
4004 output[j].op = CF_OP_EXPORT;
4005 switch (ctx.type) {
4006 case PIPE_SHADER_VERTEX:
4007 case PIPE_SHADER_TESS_EVAL:
4008 switch (shader->output[i].name) {
4009 case TGSI_SEMANTIC_POSITION:
4010 output[j].array_base = 60;
4011 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4012 pos_emitted = true;
4013 break;
4014
4015 case TGSI_SEMANTIC_PSIZE:
4016 output[j].array_base = 61;
4017 output[j].swizzle_y = 7;
4018 output[j].swizzle_z = 7;
4019 output[j].swizzle_w = 7;
4020 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4021 pos_emitted = true;
4022 break;
4023 case TGSI_SEMANTIC_EDGEFLAG:
4024 output[j].array_base = 61;
4025 output[j].swizzle_x = 7;
4026 output[j].swizzle_y = 0;
4027 output[j].swizzle_z = 7;
4028 output[j].swizzle_w = 7;
4029 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4030 pos_emitted = true;
4031 break;
4032 case TGSI_SEMANTIC_LAYER:
4033 /* spi_sid is 0 for outputs that are
4034 * not consumed by PS */
4035 if (shader->output[i].spi_sid) {
4036 output[j].array_base = next_param_base++;
4037 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4038 j++;
4039 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
4040 }
4041 output[j].array_base = 61;
4042 output[j].swizzle_x = 7;
4043 output[j].swizzle_y = 7;
4044 output[j].swizzle_z = 0;
4045 output[j].swizzle_w = 7;
4046 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4047 pos_emitted = true;
4048 break;
4049 case TGSI_SEMANTIC_VIEWPORT_INDEX:
4050 /* spi_sid is 0 for outputs that are
4051 * not consumed by PS */
4052 if (shader->output[i].spi_sid) {
4053 output[j].array_base = next_param_base++;
4054 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4055 j++;
4056 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
4057 }
4058 output[j].array_base = 61;
4059 output[j].swizzle_x = 7;
4060 output[j].swizzle_y = 7;
4061 output[j].swizzle_z = 7;
4062 output[j].swizzle_w = 0;
4063 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4064 pos_emitted = true;
4065 break;
4066 case TGSI_SEMANTIC_CLIPVERTEX:
4067 j--;
4068 break;
4069 case TGSI_SEMANTIC_CLIPDIST:
4070 output[j].array_base = next_clip_base++;
4071 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4072 pos_emitted = true;
4073 /* spi_sid is 0 for clipdistance outputs that were generated
4074 * for clipvertex - we don't need to pass them to PS */
4075 if (shader->output[i].spi_sid) {
4076 j++;
4077 /* duplicate it as PARAM to pass to the pixel shader */
4078 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
4079 output[j].array_base = next_param_base++;
4080 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4081 }
4082 break;
4083 case TGSI_SEMANTIC_FOG:
4084 output[j].swizzle_y = 4; /* 0 */
4085 output[j].swizzle_z = 4; /* 0 */
4086 output[j].swizzle_w = 5; /* 1 */
4087 break;
4088 case TGSI_SEMANTIC_PRIMID:
4089 output[j].swizzle_x = 2;
4090 output[j].swizzle_y = 4; /* 0 */
4091 output[j].swizzle_z = 4; /* 0 */
4092 output[j].swizzle_w = 4; /* 0 */
4093 break;
4094 }
4095
4096 break;
4097 case PIPE_SHADER_FRAGMENT:
4098 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
4099 /* never export more colors than the number of CBs */
4100 if (shader->output[i].sid >= max_color_exports) {
4101 /* skip export */
4102 j--;
4103 continue;
4104 }
4105 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
4106 output[j].array_base = shader->output[i].sid;
4107 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4108 shader->nr_ps_color_exports++;
4109 shader->ps_color_export_mask |= (0xf << (shader->output[i].sid * 4));
4110
4111 /* If the i-th target format is set, all previous target formats must
4112 * be non-zero to avoid hangs. - from radeonsi, seems to apply to eg as well.
4113 */
4114 if (shader->output[i].sid > 0)
4115 for (unsigned x = 0; x < shader->output[i].sid; x++)
4116 shader->ps_color_export_mask |= (1 << (x*4));
4117
4118 if (shader->output[i].sid > shader->ps_export_highest)
4119 shader->ps_export_highest = shader->output[i].sid;
4120 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
4121 for (k = 1; k < max_color_exports; k++) {
4122 j++;
4123 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4124 output[j].gpr = shader->output[i].gpr;
4125 output[j].elem_size = 3;
4126 output[j].swizzle_x = 0;
4127 output[j].swizzle_y = 1;
4128 output[j].swizzle_z = 2;
4129 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
4130 output[j].burst_count = 1;
4131 output[j].array_base = k;
4132 output[j].op = CF_OP_EXPORT;
4133 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4134 shader->nr_ps_color_exports++;
4135 if (k > shader->ps_export_highest)
4136 shader->ps_export_highest = k;
4137 shader->ps_color_export_mask |= (0xf << (j * 4));
4138 }
4139 }
4140 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
4141 output[j].array_base = 61;
4142 output[j].swizzle_x = 2;
4143 output[j].swizzle_y = 7;
4144 output[j].swizzle_z = output[j].swizzle_w = 7;
4145 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4146 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
4147 output[j].array_base = 61;
4148 output[j].swizzle_x = 7;
4149 output[j].swizzle_y = 1;
4150 output[j].swizzle_z = output[j].swizzle_w = 7;
4151 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4152 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
4153 output[j].array_base = 61;
4154 output[j].swizzle_x = 7;
4155 output[j].swizzle_y = 7;
4156 output[j].swizzle_z = 0;
4157 output[j].swizzle_w = 7;
4158 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4159 } else {
4160 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
4161 r = -EINVAL;
4162 goto out_err;
4163 }
4164 break;
4165 case PIPE_SHADER_TESS_CTRL:
4166 break;
4167 default:
4168 R600_ERR("unsupported processor type %d\n", ctx.type);
4169 r = -EINVAL;
4170 goto out_err;
4171 }
4172
4173 if (output[j].type == 0xffffffff) {
4174 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4175 output[j].array_base = next_param_base++;
4176 }
4177 }
4178
4179 /* add fake position export */
4180 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
4181 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4182 output[j].gpr = 0;
4183 output[j].elem_size = 3;
4184 output[j].swizzle_x = 7;
4185 output[j].swizzle_y = 7;
4186 output[j].swizzle_z = 7;
4187 output[j].swizzle_w = 7;
4188 output[j].burst_count = 1;
4189 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
4190 output[j].array_base = 60;
4191 output[j].op = CF_OP_EXPORT;
4192 j++;
4193 }
4194
4195 /* add fake param output for vertex shader if no param is exported */
4196 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
4197 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4198 output[j].gpr = 0;
4199 output[j].elem_size = 3;
4200 output[j].swizzle_x = 7;
4201 output[j].swizzle_y = 7;
4202 output[j].swizzle_z = 7;
4203 output[j].swizzle_w = 7;
4204 output[j].burst_count = 1;
4205 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
4206 output[j].array_base = 0;
4207 output[j].op = CF_OP_EXPORT;
4208 j++;
4209 }
4210
4211 /* add fake pixel export */
4212 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
4213 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
4214 output[j].gpr = 0;
4215 output[j].elem_size = 3;
4216 output[j].swizzle_x = 7;
4217 output[j].swizzle_y = 7;
4218 output[j].swizzle_z = 7;
4219 output[j].swizzle_w = 7;
4220 output[j].burst_count = 1;
4221 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
4222 output[j].array_base = 0;
4223 output[j].op = CF_OP_EXPORT;
4224 j++;
4225 shader->nr_ps_color_exports++;
4226 shader->ps_color_export_mask = 0xf;
4227 }
4228
4229 noutput = j;
4230
4231 /* set export done on last export of each type */
4232 for (k = noutput - 1, output_done = 0; k >= 0; k--) {
4233 if (!(output_done & (1 << output[k].type))) {
4234 output_done |= (1 << output[k].type);
4235 output[k].op = CF_OP_EXPORT_DONE;
4236 }
4237 }
4238 /* add output to bytecode */
4239 for (i = 0; i < noutput; i++) {
4240 r = r600_bytecode_add_output(ctx.bc, &output[i]);
4241 if (r)
4242 goto out_err;
4243 }
4244 }
4245
4246 /* add program end */
4247 if (ctx.bc->chip_class == CAYMAN)
4248 cm_bytecode_add_cf_end(ctx.bc);
4249 else {
4250 const struct cf_op_info *last = NULL;
4251
4252 if (ctx.bc->cf_last)
4253 last = r600_isa_cf(ctx.bc->cf_last->op);
4254
4255 /* alu clause instructions don't have EOP bit, so add NOP */
4256 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_POP)
4257 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
4258
4259 ctx.bc->cf_last->end_of_program = 1;
4260 }
4261
4262 /* check GPR limit - we have 124 = 128 - 4
4263 * (4 are reserved as alu clause temporary registers) */
4264 if (ctx.bc->ngpr > 124) {
4265 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
4266 r = -ENOMEM;
4267 goto out_err;
4268 }
4269
4270 if (ctx.type == PIPE_SHADER_GEOMETRY) {
4271 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
4272 return r;
4273 }
4274
4275 free(ctx.spilled_arrays);
4276 free(ctx.array_infos);
4277 free(ctx.literals);
4278 tgsi_parse_free(&ctx.parse);
4279 return 0;
4280 out_err:
4281 free(ctx.spilled_arrays);
4282 free(ctx.array_infos);
4283 free(ctx.literals);
4284 tgsi_parse_free(&ctx.parse);
4285 return r;
4286 }
4287
4288 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
4289 {
4290 const unsigned tgsi_opcode =
4291 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
4292 R600_ERR("%s tgsi opcode unsupported\n",
4293 tgsi_get_opcode_name(tgsi_opcode));
4294 return -EINVAL;
4295 }
4296
4297 static int tgsi_end(struct r600_shader_ctx *ctx UNUSED)
4298 {
4299 return 0;
4300 }
4301
4302 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
4303 const struct r600_shader_src *shader_src,
4304 unsigned chan)
4305 {
4306 bc_src->sel = shader_src->sel;
4307 bc_src->chan = shader_src->swizzle[chan];
4308 bc_src->neg = shader_src->neg;
4309 bc_src->abs = shader_src->abs;
4310 bc_src->rel = shader_src->rel;
4311 bc_src->value = shader_src->value[bc_src->chan];
4312 bc_src->kc_bank = shader_src->kc_bank;
4313 bc_src->kc_rel = shader_src->kc_rel;
4314 }
4315
4316 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
4317 {
4318 bc_src->abs = 1;
4319 bc_src->neg = 0;
4320 }
4321
4322 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
4323 {
4324 bc_src->neg = !bc_src->neg;
4325 }
4326
4327 static void tgsi_dst(struct r600_shader_ctx *ctx,
4328 const struct tgsi_full_dst_register *tgsi_dst,
4329 unsigned swizzle,
4330 struct r600_bytecode_alu_dst *r600_dst)
4331 {
4332 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4333
4334 if (tgsi_dst->Register.File == TGSI_FILE_TEMPORARY) {
4335 bool spilled;
4336 unsigned idx;
4337
4338 idx = map_tgsi_reg_index_to_r600_gpr(ctx, tgsi_dst->Register.Index, &spilled);
4339
4340 if (spilled) {
4341 struct r600_bytecode_output cf;
4342 int reg = r600_get_temp(ctx);
4343 int r;
4344
4345 r600_dst->sel = reg;
4346 r600_dst->chan = swizzle;
4347 r600_dst->write = 1;
4348 if (inst->Instruction.Saturate) {
4349 r600_dst->clamp = 1;
4350 }
4351
4352 // needs to be added after op using tgsi_dst
4353 memset(&cf, 0, sizeof(struct r600_bytecode_output));
4354 cf.op = CF_OP_MEM_SCRATCH;
4355 cf.elem_size = 3;
4356 cf.gpr = reg;
4357 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
4358 cf.mark = 1;
4359 cf.comp_mask = inst->Dst[0].Register.WriteMask;
4360 cf.swizzle_x = 0;
4361 cf.swizzle_y = 1;
4362 cf.swizzle_z = 2;
4363 cf.swizzle_w = 3;
4364 cf.burst_count = 1;
4365
4366 get_spilled_array_base_and_size(ctx, tgsi_dst->Register.Index,
4367 &cf.array_base, &cf.array_size);
4368
4369 if (tgsi_dst->Register.Indirect) {
4370 if (ctx->bc->chip_class < R700)
4371 cf.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
4372 else
4373 cf.type = 3; // V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK;
4374 cf.index_gpr = ctx->bc->ar_reg;
4375 }
4376 else {
4377 cf.array_base += idx;
4378 cf.array_size = 0;
4379 }
4380
4381 r = r600_bytecode_add_pending_output(ctx->bc, &cf);
4382 if (r)
4383 return;
4384
4385 if (ctx->bc->chip_class >= R700)
4386 r600_bytecode_need_wait_ack(ctx->bc, true);
4387
4388 return;
4389 }
4390 else {
4391 r600_dst->sel = idx;
4392 }
4393 }
4394 else {
4395 r600_dst->sel = tgsi_dst->Register.Index;
4396 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
4397 }
4398 r600_dst->chan = swizzle;
4399 r600_dst->write = 1;
4400 if (inst->Instruction.Saturate) {
4401 r600_dst->clamp = 1;
4402 }
4403 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
4404 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
4405 return;
4406 }
4407 }
4408 if (tgsi_dst->Register.Indirect)
4409 r600_dst->rel = V_SQ_REL_RELATIVE;
4410
4411 }
4412
4413 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap, int dest_temp, int op_override)
4414 {
4415 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4416 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4417 struct r600_bytecode_alu alu;
4418 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4419 int use_tmp = 0;
4420 int swizzle_x = inst->Src[0].Register.SwizzleX;
4421
4422 if (singledest) {
4423 switch (write_mask) {
4424 case 0x1:
4425 if (swizzle_x == 2) {
4426 write_mask = 0xc;
4427 use_tmp = 3;
4428 } else
4429 write_mask = 0x3;
4430 break;
4431 case 0x2:
4432 if (swizzle_x == 2) {
4433 write_mask = 0xc;
4434 use_tmp = 3;
4435 } else {
4436 write_mask = 0x3;
4437 use_tmp = 1;
4438 }
4439 break;
4440 case 0x4:
4441 if (swizzle_x == 0) {
4442 write_mask = 0x3;
4443 use_tmp = 1;
4444 } else
4445 write_mask = 0xc;
4446 break;
4447 case 0x8:
4448 if (swizzle_x == 0) {
4449 write_mask = 0x3;
4450 use_tmp = 1;
4451 } else {
4452 write_mask = 0xc;
4453 use_tmp = 3;
4454 }
4455 break;
4456 }
4457 }
4458
4459 lasti = tgsi_last_instruction(write_mask);
4460 for (i = 0; i <= lasti; i++) {
4461
4462 if (!(write_mask & (1 << i)))
4463 continue;
4464
4465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4466
4467 if (singledest) {
4468 if (use_tmp || dest_temp) {
4469 alu.dst.sel = use_tmp ? ctx->temp_reg : dest_temp;
4470 alu.dst.chan = i;
4471 alu.dst.write = 1;
4472 } else {
4473 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4474 }
4475 if (i == 1 || i == 3)
4476 alu.dst.write = 0;
4477 } else
4478 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4479
4480 alu.op = op_override ? op_override : ctx->inst_info->op;
4481 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
4482 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4483 } else if (!swap) {
4484 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4485 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4486 }
4487 } else {
4488 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
4489 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
4490 }
4491
4492 /* handle some special cases */
4493 if (i == 1 || i == 3) {
4494 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
4495 case TGSI_OPCODE_DABS:
4496 r600_bytecode_src_set_abs(&alu.src[0]);
4497 break;
4498 default:
4499 break;
4500 }
4501 }
4502 if (i == lasti) {
4503 alu.last = 1;
4504 }
4505 r = r600_bytecode_add_alu(ctx->bc, &alu);
4506 if (r)
4507 return r;
4508 }
4509
4510 if (use_tmp) {
4511 write_mask = inst->Dst[0].Register.WriteMask;
4512
4513 lasti = tgsi_last_instruction(write_mask);
4514 /* move result from temp to dst */
4515 for (i = 0; i <= lasti; i++) {
4516 if (!(write_mask & (1 << i)))
4517 continue;
4518
4519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4520 alu.op = ALU_OP1_MOV;
4521
4522 if (dest_temp) {
4523 alu.dst.sel = dest_temp;
4524 alu.dst.chan = i;
4525 alu.dst.write = 1;
4526 } else
4527 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4528 alu.src[0].sel = ctx->temp_reg;
4529 alu.src[0].chan = use_tmp - 1;
4530 alu.last = (i == lasti);
4531
4532 r = r600_bytecode_add_alu(ctx->bc, &alu);
4533 if (r)
4534 return r;
4535 }
4536 }
4537 return 0;
4538 }
4539
4540 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
4541 {
4542 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4543 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4544 /* confirm writemasking */
4545 if ((write_mask & 0x3) != 0x3 &&
4546 (write_mask & 0xc) != 0xc) {
4547 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4548 return -1;
4549 }
4550 return tgsi_op2_64_params(ctx, false, false, 0, 0);
4551 }
4552
4553 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4554 {
4555 return tgsi_op2_64_params(ctx, true, false, 0, 0);
4556 }
4557
4558 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4559 {
4560 return tgsi_op2_64_params(ctx, true, true, 0, 0);
4561 }
4562
4563 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4564 {
4565 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4566 struct r600_bytecode_alu alu;
4567 int i, j, r;
4568 int lasti = 3;
4569 int tmp = r600_get_temp(ctx);
4570
4571 for (i = 0; i < lasti + 1; i++) {
4572
4573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4574 alu.op = ctx->inst_info->op;
4575 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4576 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4577 }
4578
4579 if (inst->Dst[0].Register.WriteMask & (1 << i))
4580 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4581 else
4582 alu.dst.sel = tmp;
4583
4584 alu.dst.chan = i;
4585 alu.is_op3 = 1;
4586 if (i == lasti) {
4587 alu.last = 1;
4588 }
4589 r = r600_bytecode_add_alu(ctx->bc, &alu);
4590 if (r)
4591 return r;
4592 }
4593 return 0;
4594 }
4595
4596 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4597 {
4598 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4599 struct r600_bytecode_alu alu;
4600 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4601 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4602 /* use temp register if trans_only and more than one dst component */
4603 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4604 unsigned op = ctx->inst_info->op;
4605
4606 if (op == ALU_OP2_MUL_IEEE &&
4607 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4608 op = ALU_OP2_MUL;
4609
4610 for (i = 0; i <= lasti; i++) {
4611 if (!(write_mask & (1 << i)))
4612 continue;
4613
4614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4615 if (use_tmp) {
4616 alu.dst.sel = ctx->temp_reg;
4617 alu.dst.chan = i;
4618 alu.dst.write = 1;
4619 } else
4620 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4621
4622 alu.op = op;
4623 if (!swap) {
4624 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4625 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4626 }
4627 } else {
4628 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4629 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4630 }
4631 if (i == lasti || trans_only) {
4632 alu.last = 1;
4633 }
4634 r = r600_bytecode_add_alu(ctx->bc, &alu);
4635 if (r)
4636 return r;
4637 }
4638
4639 if (use_tmp) {
4640 /* move result from temp to dst */
4641 for (i = 0; i <= lasti; i++) {
4642 if (!(write_mask & (1 << i)))
4643 continue;
4644
4645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4646 alu.op = ALU_OP1_MOV;
4647 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4648 alu.src[0].sel = ctx->temp_reg;
4649 alu.src[0].chan = i;
4650 alu.last = (i == lasti);
4651
4652 r = r600_bytecode_add_alu(ctx->bc, &alu);
4653 if (r)
4654 return r;
4655 }
4656 }
4657 return 0;
4658 }
4659
4660 static int tgsi_op2(struct r600_shader_ctx *ctx)
4661 {
4662 return tgsi_op2_s(ctx, 0, 0);
4663 }
4664
4665 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4666 {
4667 return tgsi_op2_s(ctx, 1, 0);
4668 }
4669
4670 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4671 {
4672 return tgsi_op2_s(ctx, 0, 1);
4673 }
4674
4675 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4676 {
4677 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4678 struct r600_bytecode_alu alu;
4679 int i, r;
4680 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4681
4682 for (i = 0; i < lasti + 1; i++) {
4683
4684 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4685 continue;
4686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4687 alu.op = ctx->inst_info->op;
4688
4689 alu.src[0].sel = V_SQ_ALU_SRC_0;
4690
4691 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4692
4693 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4694
4695 if (i == lasti) {
4696 alu.last = 1;
4697 }
4698 r = r600_bytecode_add_alu(ctx->bc, &alu);
4699 if (r)
4700 return r;
4701 }
4702 return 0;
4703
4704 }
4705
4706 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4707 {
4708 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4709 struct r600_bytecode_alu alu;
4710 int i, r;
4711 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4712
4713 for (i = 0; i < lasti + 1; i++) {
4714
4715 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4716 continue;
4717 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4718 alu.op = ALU_OP1_MOV;
4719
4720 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4721
4722 if (i == 1 || i == 3)
4723 r600_bytecode_src_toggle_neg(&alu.src[0]);
4724 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4725
4726 if (i == lasti) {
4727 alu.last = 1;
4728 }
4729 r = r600_bytecode_add_alu(ctx->bc, &alu);
4730 if (r)
4731 return r;
4732 }
4733 return 0;
4734
4735 }
4736
4737 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4738 {
4739 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4740 struct r600_bytecode_alu alu;
4741 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4742 int i, j, r;
4743
4744 for (i = 0; i <= 3; i++) {
4745 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4746 alu.op = ctx->inst_info->op;
4747
4748 alu.dst.sel = ctx->temp_reg;
4749 alu.dst.chan = i;
4750 alu.dst.write = 1;
4751 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4752 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4753 }
4754
4755 if (i == 3)
4756 alu.last = 1;
4757
4758 r = r600_bytecode_add_alu(ctx->bc, &alu);
4759 if (r)
4760 return r;
4761 }
4762
4763 /* Replicate significand result across channels. */
4764 for (i = 0; i <= 3; i++) {
4765 if (!(write_mask & (1 << i)))
4766 continue;
4767
4768 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4769 alu.op = ALU_OP1_MOV;
4770 alu.src[0].chan = (i & 1) + 2;
4771 alu.src[0].sel = ctx->temp_reg;
4772
4773 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4774 alu.dst.write = 1;
4775 alu.last = 1;
4776 r = r600_bytecode_add_alu(ctx->bc, &alu);
4777 if (r)
4778 return r;
4779 }
4780
4781 for (i = 0; i <= 3; i++) {
4782 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4783 /* MOV third channels to writemask dst1 */
4784 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4785 alu.op = ALU_OP1_MOV;
4786 alu.src[0].chan = 1;
4787 alu.src[0].sel = ctx->temp_reg;
4788
4789 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4790 alu.last = 1;
4791 r = r600_bytecode_add_alu(ctx->bc, &alu);
4792 if (r)
4793 return r;
4794 break;
4795 }
4796 }
4797 return 0;
4798 }
4799
4800
4801 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4802 {
4803 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4804 struct r600_bytecode_alu alu;
4805 int i, c, r;
4806 int write_mask = inst->Dst[0].Register.WriteMask;
4807 int temp_reg = r600_get_temp(ctx);
4808
4809 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4810 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4811
4812 for (c = 0; c < 2; c++) {
4813 int dchan = c * 2;
4814 if (write_mask & (0x3 << dchan)) {
4815 /* split into 24-bit int and 8-bit int */
4816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4817 alu.op = ALU_OP2_AND_INT;
4818 alu.dst.sel = temp_reg;
4819 alu.dst.chan = dchan;
4820 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4821 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4822 alu.src[1].value = 0xffffff00;
4823 alu.dst.write = 1;
4824 r = r600_bytecode_add_alu(ctx->bc, &alu);
4825 if (r)
4826 return r;
4827
4828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4829 alu.op = ALU_OP2_AND_INT;
4830 alu.dst.sel = temp_reg;
4831 alu.dst.chan = dchan + 1;
4832 r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
4833 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4834 alu.src[1].value = 0xff;
4835 alu.dst.write = 1;
4836 alu.last = 1;
4837 r = r600_bytecode_add_alu(ctx->bc, &alu);
4838 if (r)
4839 return r;
4840 }
4841 }
4842
4843 for (c = 0; c < 2; c++) {
4844 int dchan = c * 2;
4845 if (write_mask & (0x3 << dchan)) {
4846 for (i = dchan; i <= dchan + 1; i++) {
4847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4848 alu.op = i == dchan ? ctx->inst_info->op : ALU_OP1_UINT_TO_FLT;
4849
4850 alu.src[0].sel = temp_reg;
4851 alu.src[0].chan = i;
4852 alu.dst.sel = temp_reg;
4853 alu.dst.chan = i;
4854 alu.dst.write = 1;
4855 if (ctx->bc->chip_class == CAYMAN)
4856 alu.last = i == dchan + 1;
4857 else
4858 alu.last = 1; /* trans only ops on evergreen */
4859
4860 r = r600_bytecode_add_alu(ctx->bc, &alu);
4861 if (r)
4862 return r;
4863 }
4864 }
4865 }
4866
4867 for (c = 0; c < 2; c++) {
4868 int dchan = c * 2;
4869 if (write_mask & (0x3 << dchan)) {
4870 for (i = 0; i < 4; i++) {
4871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4872 alu.op = ALU_OP1_FLT32_TO_FLT64;
4873
4874 alu.src[0].chan = dchan + (i / 2);
4875 if (i == 0 || i == 2)
4876 alu.src[0].sel = temp_reg;
4877 else {
4878 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4879 alu.src[0].value = 0x0;
4880 }
4881 alu.dst.sel = ctx->temp_reg;
4882 alu.dst.chan = i;
4883 alu.last = i == 3;
4884 alu.dst.write = 1;
4885
4886 r = r600_bytecode_add_alu(ctx->bc, &alu);
4887 if (r)
4888 return r;
4889 }
4890
4891 for (i = 0; i <= 1; i++) {
4892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4893 alu.op = ALU_OP2_ADD_64;
4894
4895 alu.src[0].chan = fp64_switch(i);
4896 alu.src[0].sel = ctx->temp_reg;
4897
4898 alu.src[1].chan = fp64_switch(i + 2);
4899 alu.src[1].sel = ctx->temp_reg;
4900 tgsi_dst(ctx, &inst->Dst[0], dchan + i, &alu.dst);
4901 alu.last = i == 1;
4902
4903 r = r600_bytecode_add_alu(ctx->bc, &alu);
4904 if (r)
4905 return r;
4906 }
4907 }
4908 }
4909
4910 return 0;
4911 }
4912
4913 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4914 {
4915 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4916 struct r600_bytecode_alu alu;
4917 int i, r;
4918 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4919 int treg = r600_get_temp(ctx);
4920 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4921 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4922
4923 /* do a 64->32 into a temp register */
4924 r = tgsi_op2_64_params(ctx, true, false, treg, ALU_OP1_FLT64_TO_FLT32);
4925 if (r)
4926 return r;
4927
4928 for (i = 0; i <= lasti; i++) {
4929 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4930 continue;
4931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4932 alu.op = ctx->inst_info->op;
4933
4934 alu.src[0].chan = i;
4935 alu.src[0].sel = treg;
4936 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4937 alu.last = (i == lasti);
4938
4939 r = r600_bytecode_add_alu(ctx->bc, &alu);
4940 if (r)
4941 return r;
4942 }
4943
4944 return 0;
4945 }
4946
4947 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4948 unsigned op,
4949 int dst_reg,
4950 struct r600_shader_src *src,
4951 bool abs)
4952 {
4953 struct r600_bytecode_alu alu;
4954 const int last_slot = 3;
4955 int r;
4956
4957 /* these have to write the result to X/Y by the looks of it */
4958 for (int i = 0 ; i < last_slot; i++) {
4959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4960 alu.op = op;
4961
4962 r600_bytecode_src(&alu.src[0], src, 1);
4963 r600_bytecode_src(&alu.src[1], src, 0);
4964
4965 if (abs)
4966 r600_bytecode_src_set_abs(&alu.src[1]);
4967
4968 alu.dst.sel = dst_reg;
4969 alu.dst.chan = i;
4970 alu.dst.write = (i == 0 || i == 1);
4971
4972 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4973 alu.last = 1;
4974 r = r600_bytecode_add_alu(bc, &alu);
4975 if (r)
4976 return r;
4977 }
4978
4979 return 0;
4980 }
4981
4982 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4983 {
4984 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4985 int i, r;
4986 struct r600_bytecode_alu alu;
4987 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4988 int t1 = ctx->temp_reg;
4989
4990 /* should only be one src regs */
4991 assert(inst->Instruction.NumSrcRegs == 1);
4992
4993 /* only support one double at a time */
4994 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4995 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4996
4997 r = cayman_emit_unary_double_raw(
4998 ctx->bc, ctx->inst_info->op, t1,
4999 &ctx->src[0],
5000 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
5001 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
5002 if (r)
5003 return r;
5004
5005 for (i = 0 ; i <= lasti; i++) {
5006 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5007 continue;
5008 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5009 alu.op = ALU_OP1_MOV;
5010 alu.src[0].sel = t1;
5011 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
5012 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5013 alu.dst.write = 1;
5014 if (i == lasti)
5015 alu.last = 1;
5016 r = r600_bytecode_add_alu(ctx->bc, &alu);
5017 if (r)
5018 return r;
5019 }
5020 return 0;
5021 }
5022
5023 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
5024 {
5025 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5026 int i, j, r;
5027 struct r600_bytecode_alu alu;
5028 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5029
5030 for (i = 0 ; i < last_slot; i++) {
5031 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5032 alu.op = ctx->inst_info->op;
5033 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5034 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
5035
5036 /* RSQ should take the absolute value of src */
5037 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
5038 r600_bytecode_src_set_abs(&alu.src[j]);
5039 }
5040 }
5041 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5042 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5043
5044 if (i == last_slot - 1)
5045 alu.last = 1;
5046 r = r600_bytecode_add_alu(ctx->bc, &alu);
5047 if (r)
5048 return r;
5049 }
5050 return 0;
5051 }
5052
5053 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
5054 {
5055 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5056 int i, j, k, r;
5057 struct r600_bytecode_alu alu;
5058 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5059 int t1 = ctx->temp_reg;
5060
5061 for (k = 0; k <= lasti; k++) {
5062 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
5063 continue;
5064
5065 for (i = 0 ; i < 4; i++) {
5066 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5067 alu.op = ctx->inst_info->op;
5068 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5069 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
5070 }
5071 alu.dst.sel = t1;
5072 alu.dst.chan = i;
5073 alu.dst.write = (i == k);
5074 if (i == 3)
5075 alu.last = 1;
5076 r = r600_bytecode_add_alu(ctx->bc, &alu);
5077 if (r)
5078 return r;
5079 }
5080 }
5081
5082 for (i = 0 ; i <= lasti; i++) {
5083 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5084 continue;
5085 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5086 alu.op = ALU_OP1_MOV;
5087 alu.src[0].sel = t1;
5088 alu.src[0].chan = i;
5089 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5090 alu.dst.write = 1;
5091 if (i == lasti)
5092 alu.last = 1;
5093 r = r600_bytecode_add_alu(ctx->bc, &alu);
5094 if (r)
5095 return r;
5096 }
5097
5098 return 0;
5099 }
5100
5101
5102 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
5103 {
5104 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5105 int i, j, k, r;
5106 struct r600_bytecode_alu alu;
5107 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5108 int t1 = ctx->temp_reg;
5109
5110 /* t1 would get overwritten below if we actually tried to
5111 * multiply two pairs of doubles at a time. */
5112 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
5113 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
5114
5115 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
5116
5117 for (i = 0; i < 4; i++) {
5118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5119 alu.op = ctx->inst_info->op;
5120 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5121 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
5122 }
5123 alu.dst.sel = t1;
5124 alu.dst.chan = i;
5125 alu.dst.write = 1;
5126 if (i == 3)
5127 alu.last = 1;
5128 r = r600_bytecode_add_alu(ctx->bc, &alu);
5129 if (r)
5130 return r;
5131 }
5132
5133 for (i = 0; i <= lasti; i++) {
5134 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5135 continue;
5136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5137 alu.op = ALU_OP1_MOV;
5138 alu.src[0].sel = t1;
5139 alu.src[0].chan = i;
5140 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5141 alu.dst.write = 1;
5142 if (i == lasti)
5143 alu.last = 1;
5144 r = r600_bytecode_add_alu(ctx->bc, &alu);
5145 if (r)
5146 return r;
5147 }
5148
5149 return 0;
5150 }
5151
5152 /*
5153 * Emit RECIP_64 + MUL_64 to implement division.
5154 */
5155 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
5156 {
5157 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5158 int r;
5159 struct r600_bytecode_alu alu;
5160 int t1 = ctx->temp_reg;
5161 int k;
5162
5163 /* Only support one double at a time. This is the same constraint as
5164 * in DMUL lowering. */
5165 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
5166 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
5167
5168 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
5169
5170 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
5171 if (r)
5172 return r;
5173
5174 for (int i = 0; i < 4; i++) {
5175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5176 alu.op = ALU_OP2_MUL_64;
5177
5178 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
5179
5180 alu.src[1].sel = t1;
5181 alu.src[1].chan = (i == 3) ? 0 : 1;
5182
5183 alu.dst.sel = t1;
5184 alu.dst.chan = i;
5185 alu.dst.write = 1;
5186 if (i == 3)
5187 alu.last = 1;
5188 r = r600_bytecode_add_alu(ctx->bc, &alu);
5189 if (r)
5190 return r;
5191 }
5192
5193 for (int i = 0; i < 2; i++) {
5194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5195 alu.op = ALU_OP1_MOV;
5196 alu.src[0].sel = t1;
5197 alu.src[0].chan = i;
5198 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
5199 alu.dst.write = 1;
5200 if (i == 1)
5201 alu.last = 1;
5202 r = r600_bytecode_add_alu(ctx->bc, &alu);
5203 if (r)
5204 return r;
5205 }
5206 return 0;
5207 }
5208
5209 /*
5210 * r600 - trunc to -PI..PI range
5211 * r700 - normalize by dividing by 2PI
5212 * see fdo bug 27901
5213 */
5214 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
5215 {
5216 int r;
5217 struct r600_bytecode_alu alu;
5218
5219 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5220 alu.op = ALU_OP3_MULADD;
5221 alu.is_op3 = 1;
5222
5223 alu.dst.chan = 0;
5224 alu.dst.sel = ctx->temp_reg;
5225 alu.dst.write = 1;
5226
5227 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5228
5229 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5230 alu.src[1].chan = 0;
5231 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
5232 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
5233 alu.src[2].chan = 0;
5234 alu.last = 1;
5235 r = r600_bytecode_add_alu(ctx->bc, &alu);
5236 if (r)
5237 return r;
5238
5239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5240 alu.op = ALU_OP1_FRACT;
5241
5242 alu.dst.chan = 0;
5243 alu.dst.sel = ctx->temp_reg;
5244 alu.dst.write = 1;
5245
5246 alu.src[0].sel = ctx->temp_reg;
5247 alu.src[0].chan = 0;
5248 alu.last = 1;
5249 r = r600_bytecode_add_alu(ctx->bc, &alu);
5250 if (r)
5251 return r;
5252
5253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5254 alu.op = ALU_OP3_MULADD;
5255 alu.is_op3 = 1;
5256
5257 alu.dst.chan = 0;
5258 alu.dst.sel = ctx->temp_reg;
5259 alu.dst.write = 1;
5260
5261 alu.src[0].sel = ctx->temp_reg;
5262 alu.src[0].chan = 0;
5263
5264 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5265 alu.src[1].chan = 0;
5266 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5267 alu.src[2].chan = 0;
5268
5269 if (ctx->bc->chip_class == R600) {
5270 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
5271 alu.src[2].value = u_bitcast_f2u(-M_PI);
5272 } else {
5273 alu.src[1].sel = V_SQ_ALU_SRC_1;
5274 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
5275 alu.src[2].neg = 1;
5276 }
5277
5278 alu.last = 1;
5279 r = r600_bytecode_add_alu(ctx->bc, &alu);
5280 if (r)
5281 return r;
5282 return 0;
5283 }
5284
5285 static int cayman_trig(struct r600_shader_ctx *ctx)
5286 {
5287 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5288 struct r600_bytecode_alu alu;
5289 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5290 int i, r;
5291
5292 r = tgsi_setup_trig(ctx);
5293 if (r)
5294 return r;
5295
5296
5297 for (i = 0; i < last_slot; i++) {
5298 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5299 alu.op = ctx->inst_info->op;
5300 alu.dst.chan = i;
5301
5302 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5303 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5304
5305 alu.src[0].sel = ctx->temp_reg;
5306 alu.src[0].chan = 0;
5307 if (i == last_slot - 1)
5308 alu.last = 1;
5309 r = r600_bytecode_add_alu(ctx->bc, &alu);
5310 if (r)
5311 return r;
5312 }
5313 return 0;
5314 }
5315
5316 static int tgsi_trig(struct r600_shader_ctx *ctx)
5317 {
5318 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5319 struct r600_bytecode_alu alu;
5320 int i, r;
5321 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5322
5323 r = tgsi_setup_trig(ctx);
5324 if (r)
5325 return r;
5326
5327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5328 alu.op = ctx->inst_info->op;
5329 alu.dst.chan = 0;
5330 alu.dst.sel = ctx->temp_reg;
5331 alu.dst.write = 1;
5332
5333 alu.src[0].sel = ctx->temp_reg;
5334 alu.src[0].chan = 0;
5335 alu.last = 1;
5336 r = r600_bytecode_add_alu(ctx->bc, &alu);
5337 if (r)
5338 return r;
5339
5340 /* replicate result */
5341 for (i = 0; i < lasti + 1; i++) {
5342 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5343 continue;
5344
5345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5346 alu.op = ALU_OP1_MOV;
5347
5348 alu.src[0].sel = ctx->temp_reg;
5349 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5350 if (i == lasti)
5351 alu.last = 1;
5352 r = r600_bytecode_add_alu(ctx->bc, &alu);
5353 if (r)
5354 return r;
5355 }
5356 return 0;
5357 }
5358
5359 static int tgsi_kill(struct r600_shader_ctx *ctx)
5360 {
5361 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5362 struct r600_bytecode_alu alu;
5363 int i, r;
5364
5365 for (i = 0; i < 4; i++) {
5366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5367 alu.op = ctx->inst_info->op;
5368
5369 alu.dst.chan = i;
5370
5371 alu.src[0].sel = V_SQ_ALU_SRC_0;
5372
5373 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
5374 alu.src[1].sel = V_SQ_ALU_SRC_1;
5375 alu.src[1].neg = 1;
5376 } else {
5377 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5378 }
5379 if (i == 3) {
5380 alu.last = 1;
5381 }
5382 r = r600_bytecode_add_alu(ctx->bc, &alu);
5383 if (r)
5384 return r;
5385 }
5386
5387 /* kill must be last in ALU */
5388 ctx->bc->force_add_cf = 1;
5389 ctx->shader->uses_kill = TRUE;
5390 return 0;
5391 }
5392
5393 static int tgsi_lit(struct r600_shader_ctx *ctx)
5394 {
5395 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5396 struct r600_bytecode_alu alu;
5397 int r;
5398
5399 /* tmp.x = max(src.y, 0.0) */
5400 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5401 alu.op = ALU_OP2_MAX;
5402 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
5403 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5404 alu.src[1].chan = 1;
5405
5406 alu.dst.sel = ctx->temp_reg;
5407 alu.dst.chan = 0;
5408 alu.dst.write = 1;
5409
5410 alu.last = 1;
5411 r = r600_bytecode_add_alu(ctx->bc, &alu);
5412 if (r)
5413 return r;
5414
5415 if (inst->Dst[0].Register.WriteMask & (1 << 2))
5416 {
5417 int chan;
5418 int sel;
5419 unsigned i;
5420
5421 if (ctx->bc->chip_class == CAYMAN) {
5422 for (i = 0; i < 3; i++) {
5423 /* tmp.z = log(tmp.x) */
5424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5425 alu.op = ALU_OP1_LOG_CLAMPED;
5426 alu.src[0].sel = ctx->temp_reg;
5427 alu.src[0].chan = 0;
5428 alu.dst.sel = ctx->temp_reg;
5429 alu.dst.chan = i;
5430 if (i == 2) {
5431 alu.dst.write = 1;
5432 alu.last = 1;
5433 } else
5434 alu.dst.write = 0;
5435
5436 r = r600_bytecode_add_alu(ctx->bc, &alu);
5437 if (r)
5438 return r;
5439 }
5440 } else {
5441 /* tmp.z = log(tmp.x) */
5442 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5443 alu.op = ALU_OP1_LOG_CLAMPED;
5444 alu.src[0].sel = ctx->temp_reg;
5445 alu.src[0].chan = 0;
5446 alu.dst.sel = ctx->temp_reg;
5447 alu.dst.chan = 2;
5448 alu.dst.write = 1;
5449 alu.last = 1;
5450 r = r600_bytecode_add_alu(ctx->bc, &alu);
5451 if (r)
5452 return r;
5453 }
5454
5455 chan = alu.dst.chan;
5456 sel = alu.dst.sel;
5457
5458 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
5459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5460 alu.op = ALU_OP3_MUL_LIT;
5461 alu.src[0].sel = sel;
5462 alu.src[0].chan = chan;
5463 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
5464 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
5465 alu.dst.sel = ctx->temp_reg;
5466 alu.dst.chan = 0;
5467 alu.dst.write = 1;
5468 alu.is_op3 = 1;
5469 alu.last = 1;
5470 r = r600_bytecode_add_alu(ctx->bc, &alu);
5471 if (r)
5472 return r;
5473
5474 if (ctx->bc->chip_class == CAYMAN) {
5475 for (i = 0; i < 3; i++) {
5476 /* dst.z = exp(tmp.x) */
5477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5478 alu.op = ALU_OP1_EXP_IEEE;
5479 alu.src[0].sel = ctx->temp_reg;
5480 alu.src[0].chan = 0;
5481 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5482 if (i == 2) {
5483 alu.dst.write = 1;
5484 alu.last = 1;
5485 } else
5486 alu.dst.write = 0;
5487 r = r600_bytecode_add_alu(ctx->bc, &alu);
5488 if (r)
5489 return r;
5490 }
5491 } else {
5492 /* dst.z = exp(tmp.x) */
5493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5494 alu.op = ALU_OP1_EXP_IEEE;
5495 alu.src[0].sel = ctx->temp_reg;
5496 alu.src[0].chan = 0;
5497 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5498 alu.last = 1;
5499 r = r600_bytecode_add_alu(ctx->bc, &alu);
5500 if (r)
5501 return r;
5502 }
5503 }
5504
5505 /* dst.x, <- 1.0 */
5506 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5507 alu.op = ALU_OP1_MOV;
5508 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
5509 alu.src[0].chan = 0;
5510 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5511 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
5512 r = r600_bytecode_add_alu(ctx->bc, &alu);
5513 if (r)
5514 return r;
5515
5516 /* dst.y = max(src.x, 0.0) */
5517 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5518 alu.op = ALU_OP2_MAX;
5519 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5520 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5521 alu.src[1].chan = 0;
5522 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
5523 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
5524 r = r600_bytecode_add_alu(ctx->bc, &alu);
5525 if (r)
5526 return r;
5527
5528 /* dst.w, <- 1.0 */
5529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5530 alu.op = ALU_OP1_MOV;
5531 alu.src[0].sel = V_SQ_ALU_SRC_1;
5532 alu.src[0].chan = 0;
5533 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
5534 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
5535 alu.last = 1;
5536 r = r600_bytecode_add_alu(ctx->bc, &alu);
5537 if (r)
5538 return r;
5539
5540 return 0;
5541 }
5542
5543 static int tgsi_rsq(struct r600_shader_ctx *ctx)
5544 {
5545 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5546 struct r600_bytecode_alu alu;
5547 int i, r;
5548
5549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5550
5551 alu.op = ALU_OP1_RECIPSQRT_IEEE;
5552
5553 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5554 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5555 r600_bytecode_src_set_abs(&alu.src[i]);
5556 }
5557 alu.dst.sel = ctx->temp_reg;
5558 alu.dst.write = 1;
5559 alu.last = 1;
5560 r = r600_bytecode_add_alu(ctx->bc, &alu);
5561 if (r)
5562 return r;
5563 /* replicate result */
5564 return tgsi_helper_tempx_replicate(ctx);
5565 }
5566
5567 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
5568 {
5569 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5570 struct r600_bytecode_alu alu;
5571 int i, r;
5572
5573 for (i = 0; i < 4; i++) {
5574 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5575 alu.src[0].sel = ctx->temp_reg;
5576 alu.op = ALU_OP1_MOV;
5577 alu.dst.chan = i;
5578 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5579 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5580 if (i == 3)
5581 alu.last = 1;
5582 r = r600_bytecode_add_alu(ctx->bc, &alu);
5583 if (r)
5584 return r;
5585 }
5586 return 0;
5587 }
5588
5589 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
5590 {
5591 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5592 struct r600_bytecode_alu alu;
5593 int i, r;
5594
5595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5596 alu.op = ctx->inst_info->op;
5597 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5598 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5599 }
5600 alu.dst.sel = ctx->temp_reg;
5601 alu.dst.write = 1;
5602 alu.last = 1;
5603 r = r600_bytecode_add_alu(ctx->bc, &alu);
5604 if (r)
5605 return r;
5606 /* replicate result */
5607 return tgsi_helper_tempx_replicate(ctx);
5608 }
5609
5610 static int cayman_pow(struct r600_shader_ctx *ctx)
5611 {
5612 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5613 int i, r;
5614 struct r600_bytecode_alu alu;
5615 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5616
5617 for (i = 0; i < 3; i++) {
5618 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5619 alu.op = ALU_OP1_LOG_IEEE;
5620 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5621 alu.dst.sel = ctx->temp_reg;
5622 alu.dst.chan = i;
5623 alu.dst.write = 1;
5624 if (i == 2)
5625 alu.last = 1;
5626 r = r600_bytecode_add_alu(ctx->bc, &alu);
5627 if (r)
5628 return r;
5629 }
5630
5631 /* b * LOG2(a) */
5632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5633 alu.op = ALU_OP2_MUL;
5634 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5635 alu.src[1].sel = ctx->temp_reg;
5636 alu.dst.sel = ctx->temp_reg;
5637 alu.dst.write = 1;
5638 alu.last = 1;
5639 r = r600_bytecode_add_alu(ctx->bc, &alu);
5640 if (r)
5641 return r;
5642
5643 for (i = 0; i < last_slot; i++) {
5644 /* POW(a,b) = EXP2(b * LOG2(a))*/
5645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5646 alu.op = ALU_OP1_EXP_IEEE;
5647 alu.src[0].sel = ctx->temp_reg;
5648
5649 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5650 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5651 if (i == last_slot - 1)
5652 alu.last = 1;
5653 r = r600_bytecode_add_alu(ctx->bc, &alu);
5654 if (r)
5655 return r;
5656 }
5657 return 0;
5658 }
5659
5660 static int tgsi_pow(struct r600_shader_ctx *ctx)
5661 {
5662 struct r600_bytecode_alu alu;
5663 int r;
5664
5665 /* LOG2(a) */
5666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5667 alu.op = ALU_OP1_LOG_IEEE;
5668 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5669 alu.dst.sel = ctx->temp_reg;
5670 alu.dst.write = 1;
5671 alu.last = 1;
5672 r = r600_bytecode_add_alu(ctx->bc, &alu);
5673 if (r)
5674 return r;
5675 /* b * LOG2(a) */
5676 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5677 alu.op = ALU_OP2_MUL;
5678 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5679 alu.src[1].sel = ctx->temp_reg;
5680 alu.dst.sel = ctx->temp_reg;
5681 alu.dst.write = 1;
5682 alu.last = 1;
5683 r = r600_bytecode_add_alu(ctx->bc, &alu);
5684 if (r)
5685 return r;
5686 /* POW(a,b) = EXP2(b * LOG2(a))*/
5687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5688 alu.op = ALU_OP1_EXP_IEEE;
5689 alu.src[0].sel = ctx->temp_reg;
5690 alu.dst.sel = ctx->temp_reg;
5691 alu.dst.write = 1;
5692 alu.last = 1;
5693 r = r600_bytecode_add_alu(ctx->bc, &alu);
5694 if (r)
5695 return r;
5696 return tgsi_helper_tempx_replicate(ctx);
5697 }
5698
5699 static int emit_mul_int_op(struct r600_bytecode *bc,
5700 struct r600_bytecode_alu *alu_src)
5701 {
5702 struct r600_bytecode_alu alu;
5703 int i, r;
5704 alu = *alu_src;
5705 if (bc->chip_class == CAYMAN) {
5706 for (i = 0; i < 4; i++) {
5707 alu.dst.chan = i;
5708 alu.dst.write = (i == alu_src->dst.chan);
5709 alu.last = (i == 3);
5710
5711 r = r600_bytecode_add_alu(bc, &alu);
5712 if (r)
5713 return r;
5714 }
5715 } else {
5716 alu.last = 1;
5717 r = r600_bytecode_add_alu(bc, &alu);
5718 if (r)
5719 return r;
5720 }
5721 return 0;
5722 }
5723
5724 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5725 {
5726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5727 struct r600_bytecode_alu alu;
5728 int i, r, j;
5729 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5730 int lasti = tgsi_last_instruction(write_mask);
5731 int tmp0 = ctx->temp_reg;
5732 int tmp1 = r600_get_temp(ctx);
5733 int tmp2 = r600_get_temp(ctx);
5734 int tmp3 = r600_get_temp(ctx);
5735 int tmp4 = 0;
5736
5737 /* Use additional temp if dst register and src register are the same */
5738 if (inst->Src[0].Register.Index == inst->Dst[0].Register.Index ||
5739 inst->Src[1].Register.Index == inst->Dst[0].Register.Index) {
5740 tmp4 = r600_get_temp(ctx);
5741 }
5742
5743 /* Unsigned path:
5744 *
5745 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5746 *
5747 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5748 * 2. tmp0.z = lo (tmp0.x * src2)
5749 * 3. tmp0.w = -tmp0.z
5750 * 4. tmp0.y = hi (tmp0.x * src2)
5751 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5752 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5753 * 7. tmp1.x = tmp0.x - tmp0.w
5754 * 8. tmp1.y = tmp0.x + tmp0.w
5755 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5756 * 10. tmp0.z = hi(tmp0.x * src1) = q
5757 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5758 *
5759 * 12. tmp0.w = src1 - tmp0.y = r
5760 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5761 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5762 *
5763 * if DIV
5764 *
5765 * 15. tmp1.z = tmp0.z + 1 = q + 1
5766 * 16. tmp1.w = tmp0.z - 1 = q - 1
5767 *
5768 * else MOD
5769 *
5770 * 15. tmp1.z = tmp0.w - src2 = r - src2
5771 * 16. tmp1.w = tmp0.w + src2 = r + src2
5772 *
5773 * endif
5774 *
5775 * 17. tmp1.x = tmp1.x & tmp1.y
5776 *
5777 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5778 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5779 *
5780 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5781 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5782 *
5783 * Signed path:
5784 *
5785 * Same as unsigned, using abs values of the operands,
5786 * and fixing the sign of the result in the end.
5787 */
5788
5789 for (i = 0; i < 4; i++) {
5790 if (!(write_mask & (1<<i)))
5791 continue;
5792
5793 if (signed_op) {
5794
5795 /* tmp2.x = -src0 */
5796 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5797 alu.op = ALU_OP2_SUB_INT;
5798
5799 alu.dst.sel = tmp2;
5800 alu.dst.chan = 0;
5801 alu.dst.write = 1;
5802
5803 alu.src[0].sel = V_SQ_ALU_SRC_0;
5804
5805 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5806
5807 alu.last = 1;
5808 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5809 return r;
5810
5811 /* tmp2.y = -src1 */
5812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5813 alu.op = ALU_OP2_SUB_INT;
5814
5815 alu.dst.sel = tmp2;
5816 alu.dst.chan = 1;
5817 alu.dst.write = 1;
5818
5819 alu.src[0].sel = V_SQ_ALU_SRC_0;
5820
5821 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5822
5823 alu.last = 1;
5824 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5825 return r;
5826
5827 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5828 /* it will be a sign of the quotient */
5829 if (!mod) {
5830
5831 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5832 alu.op = ALU_OP2_XOR_INT;
5833
5834 alu.dst.sel = tmp2;
5835 alu.dst.chan = 2;
5836 alu.dst.write = 1;
5837
5838 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5839 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5840
5841 alu.last = 1;
5842 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5843 return r;
5844 }
5845
5846 /* tmp2.x = |src0| */
5847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5848 alu.op = ALU_OP3_CNDGE_INT;
5849 alu.is_op3 = 1;
5850
5851 alu.dst.sel = tmp2;
5852 alu.dst.chan = 0;
5853 alu.dst.write = 1;
5854
5855 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5856 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5857 alu.src[2].sel = tmp2;
5858 alu.src[2].chan = 0;
5859
5860 alu.last = 1;
5861 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5862 return r;
5863
5864 /* tmp2.y = |src1| */
5865 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5866 alu.op = ALU_OP3_CNDGE_INT;
5867 alu.is_op3 = 1;
5868
5869 alu.dst.sel = tmp2;
5870 alu.dst.chan = 1;
5871 alu.dst.write = 1;
5872
5873 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5874 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5875 alu.src[2].sel = tmp2;
5876 alu.src[2].chan = 1;
5877
5878 alu.last = 1;
5879 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5880 return r;
5881
5882 }
5883
5884 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5885 if (ctx->bc->chip_class == CAYMAN) {
5886 /* tmp3.x = u2f(src2) */
5887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5888 alu.op = ALU_OP1_UINT_TO_FLT;
5889
5890 alu.dst.sel = tmp3;
5891 alu.dst.chan = 0;
5892 alu.dst.write = 1;
5893
5894 if (signed_op) {
5895 alu.src[0].sel = tmp2;
5896 alu.src[0].chan = 1;
5897 } else {
5898 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5899 }
5900
5901 alu.last = 1;
5902 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5903 return r;
5904
5905 /* tmp0.x = recip(tmp3.x) */
5906 for (j = 0 ; j < 3; j++) {
5907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5908 alu.op = ALU_OP1_RECIP_IEEE;
5909
5910 alu.dst.sel = tmp0;
5911 alu.dst.chan = j;
5912 alu.dst.write = (j == 0);
5913
5914 alu.src[0].sel = tmp3;
5915 alu.src[0].chan = 0;
5916
5917 if (j == 2)
5918 alu.last = 1;
5919 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5920 return r;
5921 }
5922
5923 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5924 alu.op = ALU_OP2_MUL;
5925
5926 alu.src[0].sel = tmp0;
5927 alu.src[0].chan = 0;
5928
5929 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5930 alu.src[1].value = 0x4f800000;
5931
5932 alu.dst.sel = tmp3;
5933 alu.dst.write = 1;
5934 alu.last = 1;
5935 r = r600_bytecode_add_alu(ctx->bc, &alu);
5936 if (r)
5937 return r;
5938
5939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5940 alu.op = ALU_OP1_FLT_TO_UINT;
5941
5942 alu.dst.sel = tmp0;
5943 alu.dst.chan = 0;
5944 alu.dst.write = 1;
5945
5946 alu.src[0].sel = tmp3;
5947 alu.src[0].chan = 0;
5948
5949 alu.last = 1;
5950 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5951 return r;
5952
5953 } else {
5954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5955 alu.op = ALU_OP1_RECIP_UINT;
5956
5957 alu.dst.sel = tmp0;
5958 alu.dst.chan = 0;
5959 alu.dst.write = 1;
5960
5961 if (signed_op) {
5962 alu.src[0].sel = tmp2;
5963 alu.src[0].chan = 1;
5964 } else {
5965 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5966 }
5967
5968 alu.last = 1;
5969 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5970 return r;
5971 }
5972
5973 /* 2. tmp0.z = lo (tmp0.x * src2) */
5974 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5975 alu.op = ALU_OP2_MULLO_UINT;
5976
5977 alu.dst.sel = tmp0;
5978 alu.dst.chan = 2;
5979 alu.dst.write = 1;
5980
5981 alu.src[0].sel = tmp0;
5982 alu.src[0].chan = 0;
5983 if (signed_op) {
5984 alu.src[1].sel = tmp2;
5985 alu.src[1].chan = 1;
5986 } else {
5987 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5988 }
5989
5990 if ((r = emit_mul_int_op(ctx->bc, &alu)))
5991 return r;
5992
5993 /* 3. tmp0.w = -tmp0.z */
5994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5995 alu.op = ALU_OP2_SUB_INT;
5996
5997 alu.dst.sel = tmp0;
5998 alu.dst.chan = 3;
5999 alu.dst.write = 1;
6000
6001 alu.src[0].sel = V_SQ_ALU_SRC_0;
6002 alu.src[1].sel = tmp0;
6003 alu.src[1].chan = 2;
6004
6005 alu.last = 1;
6006 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6007 return r;
6008
6009 /* 4. tmp0.y = hi (tmp0.x * src2) */
6010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6011 alu.op = ALU_OP2_MULHI_UINT;
6012
6013 alu.dst.sel = tmp0;
6014 alu.dst.chan = 1;
6015 alu.dst.write = 1;
6016
6017 alu.src[0].sel = tmp0;
6018 alu.src[0].chan = 0;
6019
6020 if (signed_op) {
6021 alu.src[1].sel = tmp2;
6022 alu.src[1].chan = 1;
6023 } else {
6024 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6025 }
6026
6027 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6028 return r;
6029
6030 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
6031 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6032 alu.op = ALU_OP3_CNDE_INT;
6033 alu.is_op3 = 1;
6034
6035 alu.dst.sel = tmp0;
6036 alu.dst.chan = 2;
6037 alu.dst.write = 1;
6038
6039 alu.src[0].sel = tmp0;
6040 alu.src[0].chan = 1;
6041 alu.src[1].sel = tmp0;
6042 alu.src[1].chan = 3;
6043 alu.src[2].sel = tmp0;
6044 alu.src[2].chan = 2;
6045
6046 alu.last = 1;
6047 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6048 return r;
6049
6050 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
6051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6052 alu.op = ALU_OP2_MULHI_UINT;
6053
6054 alu.dst.sel = tmp0;
6055 alu.dst.chan = 3;
6056 alu.dst.write = 1;
6057
6058 alu.src[0].sel = tmp0;
6059 alu.src[0].chan = 2;
6060
6061 alu.src[1].sel = tmp0;
6062 alu.src[1].chan = 0;
6063
6064 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6065 return r;
6066
6067 /* 7. tmp1.x = tmp0.x - tmp0.w */
6068 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6069 alu.op = ALU_OP2_SUB_INT;
6070
6071 alu.dst.sel = tmp1;
6072 alu.dst.chan = 0;
6073 alu.dst.write = 1;
6074
6075 alu.src[0].sel = tmp0;
6076 alu.src[0].chan = 0;
6077 alu.src[1].sel = tmp0;
6078 alu.src[1].chan = 3;
6079
6080 alu.last = 1;
6081 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6082 return r;
6083
6084 /* 8. tmp1.y = tmp0.x + tmp0.w */
6085 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6086 alu.op = ALU_OP2_ADD_INT;
6087
6088 alu.dst.sel = tmp1;
6089 alu.dst.chan = 1;
6090 alu.dst.write = 1;
6091
6092 alu.src[0].sel = tmp0;
6093 alu.src[0].chan = 0;
6094 alu.src[1].sel = tmp0;
6095 alu.src[1].chan = 3;
6096
6097 alu.last = 1;
6098 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6099 return r;
6100
6101 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
6102 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6103 alu.op = ALU_OP3_CNDE_INT;
6104 alu.is_op3 = 1;
6105
6106 alu.dst.sel = tmp0;
6107 alu.dst.chan = 0;
6108 alu.dst.write = 1;
6109
6110 alu.src[0].sel = tmp0;
6111 alu.src[0].chan = 1;
6112 alu.src[1].sel = tmp1;
6113 alu.src[1].chan = 1;
6114 alu.src[2].sel = tmp1;
6115 alu.src[2].chan = 0;
6116
6117 alu.last = 1;
6118 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6119 return r;
6120
6121 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
6122 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6123 alu.op = ALU_OP2_MULHI_UINT;
6124
6125 alu.dst.sel = tmp0;
6126 alu.dst.chan = 2;
6127 alu.dst.write = 1;
6128
6129 alu.src[0].sel = tmp0;
6130 alu.src[0].chan = 0;
6131
6132 if (signed_op) {
6133 alu.src[1].sel = tmp2;
6134 alu.src[1].chan = 0;
6135 } else {
6136 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6137 }
6138
6139 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6140 return r;
6141
6142 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
6143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6144 alu.op = ALU_OP2_MULLO_UINT;
6145
6146 alu.dst.sel = tmp0;
6147 alu.dst.chan = 1;
6148 alu.dst.write = 1;
6149
6150 if (signed_op) {
6151 alu.src[0].sel = tmp2;
6152 alu.src[0].chan = 1;
6153 } else {
6154 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6155 }
6156
6157 alu.src[1].sel = tmp0;
6158 alu.src[1].chan = 2;
6159
6160 if ((r = emit_mul_int_op(ctx->bc, &alu)))
6161 return r;
6162
6163 /* 12. tmp0.w = src1 - tmp0.y = r */
6164 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6165 alu.op = ALU_OP2_SUB_INT;
6166
6167 alu.dst.sel = tmp0;
6168 alu.dst.chan = 3;
6169 alu.dst.write = 1;
6170
6171 if (signed_op) {
6172 alu.src[0].sel = tmp2;
6173 alu.src[0].chan = 0;
6174 } else {
6175 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6176 }
6177
6178 alu.src[1].sel = tmp0;
6179 alu.src[1].chan = 1;
6180
6181 alu.last = 1;
6182 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6183 return r;
6184
6185 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
6186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6187 alu.op = ALU_OP2_SETGE_UINT;
6188
6189 alu.dst.sel = tmp1;
6190 alu.dst.chan = 0;
6191 alu.dst.write = 1;
6192
6193 alu.src[0].sel = tmp0;
6194 alu.src[0].chan = 3;
6195 if (signed_op) {
6196 alu.src[1].sel = tmp2;
6197 alu.src[1].chan = 1;
6198 } else {
6199 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6200 }
6201
6202 alu.last = 1;
6203 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6204 return r;
6205
6206 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
6207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6208 alu.op = ALU_OP2_SETGE_UINT;
6209
6210 alu.dst.sel = tmp1;
6211 alu.dst.chan = 1;
6212 alu.dst.write = 1;
6213
6214 if (signed_op) {
6215 alu.src[0].sel = tmp2;
6216 alu.src[0].chan = 0;
6217 } else {
6218 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6219 }
6220
6221 alu.src[1].sel = tmp0;
6222 alu.src[1].chan = 1;
6223
6224 alu.last = 1;
6225 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6226 return r;
6227
6228 if (mod) { /* UMOD */
6229
6230 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
6231 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6232 alu.op = ALU_OP2_SUB_INT;
6233
6234 alu.dst.sel = tmp1;
6235 alu.dst.chan = 2;
6236 alu.dst.write = 1;
6237
6238 alu.src[0].sel = tmp0;
6239 alu.src[0].chan = 3;
6240
6241 if (signed_op) {
6242 alu.src[1].sel = tmp2;
6243 alu.src[1].chan = 1;
6244 } else {
6245 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6246 }
6247
6248 alu.last = 1;
6249 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6250 return r;
6251
6252 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
6253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6254 alu.op = ALU_OP2_ADD_INT;
6255
6256 alu.dst.sel = tmp1;
6257 alu.dst.chan = 3;
6258 alu.dst.write = 1;
6259
6260 alu.src[0].sel = tmp0;
6261 alu.src[0].chan = 3;
6262 if (signed_op) {
6263 alu.src[1].sel = tmp2;
6264 alu.src[1].chan = 1;
6265 } else {
6266 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6267 }
6268
6269 alu.last = 1;
6270 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6271 return r;
6272
6273 } else { /* UDIV */
6274
6275 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
6276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6277 alu.op = ALU_OP2_ADD_INT;
6278
6279 alu.dst.sel = tmp1;
6280 alu.dst.chan = 2;
6281 alu.dst.write = 1;
6282
6283 alu.src[0].sel = tmp0;
6284 alu.src[0].chan = 2;
6285 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6286
6287 alu.last = 1;
6288 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6289 return r;
6290
6291 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
6292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6293 alu.op = ALU_OP2_ADD_INT;
6294
6295 alu.dst.sel = tmp1;
6296 alu.dst.chan = 3;
6297 alu.dst.write = 1;
6298
6299 alu.src[0].sel = tmp0;
6300 alu.src[0].chan = 2;
6301 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
6302
6303 alu.last = 1;
6304 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6305 return r;
6306
6307 }
6308
6309 /* 17. tmp1.x = tmp1.x & tmp1.y */
6310 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6311 alu.op = ALU_OP2_AND_INT;
6312
6313 alu.dst.sel = tmp1;
6314 alu.dst.chan = 0;
6315 alu.dst.write = 1;
6316
6317 alu.src[0].sel = tmp1;
6318 alu.src[0].chan = 0;
6319 alu.src[1].sel = tmp1;
6320 alu.src[1].chan = 1;
6321
6322 alu.last = 1;
6323 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6324 return r;
6325
6326 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
6327 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
6328 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6329 alu.op = ALU_OP3_CNDE_INT;
6330 alu.is_op3 = 1;
6331
6332 alu.dst.sel = tmp0;
6333 alu.dst.chan = 2;
6334 alu.dst.write = 1;
6335
6336 alu.src[0].sel = tmp1;
6337 alu.src[0].chan = 0;
6338 alu.src[1].sel = tmp0;
6339 alu.src[1].chan = mod ? 3 : 2;
6340 alu.src[2].sel = tmp1;
6341 alu.src[2].chan = 2;
6342
6343 alu.last = 1;
6344 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6345 return r;
6346
6347 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
6348 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6349 alu.op = ALU_OP3_CNDE_INT;
6350 alu.is_op3 = 1;
6351
6352 if (signed_op) {
6353 alu.dst.sel = tmp0;
6354 alu.dst.chan = 2;
6355 alu.dst.write = 1;
6356 } else {
6357 if (tmp4 > 0) {
6358 alu.dst.sel = tmp4;
6359 alu.dst.chan = i;
6360 alu.dst.write = 1;
6361 } else {
6362 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6363 }
6364 }
6365
6366 alu.src[0].sel = tmp1;
6367 alu.src[0].chan = 1;
6368 alu.src[1].sel = tmp1;
6369 alu.src[1].chan = 3;
6370 alu.src[2].sel = tmp0;
6371 alu.src[2].chan = 2;
6372
6373 alu.last = 1;
6374 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6375 return r;
6376
6377 if (signed_op) {
6378
6379 /* fix the sign of the result */
6380
6381 if (mod) {
6382
6383 /* tmp0.x = -tmp0.z */
6384 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6385 alu.op = ALU_OP2_SUB_INT;
6386
6387 alu.dst.sel = tmp0;
6388 alu.dst.chan = 0;
6389 alu.dst.write = 1;
6390
6391 alu.src[0].sel = V_SQ_ALU_SRC_0;
6392 alu.src[1].sel = tmp0;
6393 alu.src[1].chan = 2;
6394
6395 alu.last = 1;
6396 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6397 return r;
6398
6399 /* sign of the remainder is the same as the sign of src0 */
6400 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
6401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6402 alu.op = ALU_OP3_CNDGE_INT;
6403 alu.is_op3 = 1;
6404
6405 if (tmp4 > 0) {
6406 alu.dst.sel = tmp4;
6407 alu.dst.chan = i;
6408 alu.dst.write = 1;
6409 } else {
6410 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6411 }
6412
6413 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6414 alu.src[1].sel = tmp0;
6415 alu.src[1].chan = 2;
6416 alu.src[2].sel = tmp0;
6417 alu.src[2].chan = 0;
6418
6419 alu.last = 1;
6420 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6421 return r;
6422
6423 } else {
6424
6425 /* tmp0.x = -tmp0.z */
6426 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6427 alu.op = ALU_OP2_SUB_INT;
6428
6429 alu.dst.sel = tmp0;
6430 alu.dst.chan = 0;
6431 alu.dst.write = 1;
6432
6433 alu.src[0].sel = V_SQ_ALU_SRC_0;
6434 alu.src[1].sel = tmp0;
6435 alu.src[1].chan = 2;
6436
6437 alu.last = 1;
6438 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6439 return r;
6440
6441 /* fix the quotient sign (same as the sign of src0*src1) */
6442 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
6443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6444 alu.op = ALU_OP3_CNDGE_INT;
6445 alu.is_op3 = 1;
6446
6447 if (tmp4 > 0) {
6448 alu.dst.sel = tmp4;
6449 alu.dst.chan = i;
6450 alu.dst.write = 1;
6451 } else {
6452 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6453 }
6454
6455 alu.src[0].sel = tmp2;
6456 alu.src[0].chan = 2;
6457 alu.src[1].sel = tmp0;
6458 alu.src[1].chan = 2;
6459 alu.src[2].sel = tmp0;
6460 alu.src[2].chan = 0;
6461
6462 alu.last = 1;
6463 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6464 return r;
6465 }
6466 }
6467 }
6468
6469 if (tmp4 > 0) {
6470 for (i = 0; i <= lasti; ++i) {
6471 if (!(write_mask & (1<<i)))
6472 continue;
6473
6474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6475 alu.op = ALU_OP1_MOV;
6476 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6477 alu.src[0].sel = tmp4;
6478 alu.src[0].chan = i;
6479
6480 if (i == lasti)
6481 alu.last = 1;
6482 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6483 return r;
6484 }
6485 }
6486
6487 return 0;
6488 }
6489
6490 static int tgsi_udiv(struct r600_shader_ctx *ctx)
6491 {
6492 return tgsi_divmod(ctx, 0, 0);
6493 }
6494
6495 static int tgsi_umod(struct r600_shader_ctx *ctx)
6496 {
6497 return tgsi_divmod(ctx, 1, 0);
6498 }
6499
6500 static int tgsi_idiv(struct r600_shader_ctx *ctx)
6501 {
6502 return tgsi_divmod(ctx, 0, 1);
6503 }
6504
6505 static int tgsi_imod(struct r600_shader_ctx *ctx)
6506 {
6507 return tgsi_divmod(ctx, 1, 1);
6508 }
6509
6510
6511 static int tgsi_f2i(struct r600_shader_ctx *ctx)
6512 {
6513 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6514 struct r600_bytecode_alu alu;
6515 int i, r;
6516 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6517 int last_inst = tgsi_last_instruction(write_mask);
6518
6519 for (i = 0; i < 4; i++) {
6520 if (!(write_mask & (1<<i)))
6521 continue;
6522
6523 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6524 alu.op = ALU_OP1_TRUNC;
6525
6526 alu.dst.sel = ctx->temp_reg;
6527 alu.dst.chan = i;
6528 alu.dst.write = 1;
6529
6530 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6531 if (i == last_inst)
6532 alu.last = 1;
6533 r = r600_bytecode_add_alu(ctx->bc, &alu);
6534 if (r)
6535 return r;
6536 }
6537
6538 for (i = 0; i < 4; i++) {
6539 if (!(write_mask & (1<<i)))
6540 continue;
6541
6542 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6543 alu.op = ctx->inst_info->op;
6544
6545 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6546
6547 alu.src[0].sel = ctx->temp_reg;
6548 alu.src[0].chan = i;
6549
6550 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6551 alu.last = 1;
6552 r = r600_bytecode_add_alu(ctx->bc, &alu);
6553 if (r)
6554 return r;
6555 }
6556
6557 return 0;
6558 }
6559
6560 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6561 {
6562 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6563 struct r600_bytecode_alu alu;
6564 int i, r;
6565 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6566 int last_inst = tgsi_last_instruction(write_mask);
6567
6568 /* tmp = -src */
6569 for (i = 0; i < 4; i++) {
6570 if (!(write_mask & (1<<i)))
6571 continue;
6572
6573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6574 alu.op = ALU_OP2_SUB_INT;
6575
6576 alu.dst.sel = ctx->temp_reg;
6577 alu.dst.chan = i;
6578 alu.dst.write = 1;
6579
6580 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6581 alu.src[0].sel = V_SQ_ALU_SRC_0;
6582
6583 if (i == last_inst)
6584 alu.last = 1;
6585 r = r600_bytecode_add_alu(ctx->bc, &alu);
6586 if (r)
6587 return r;
6588 }
6589
6590 /* dst = (src >= 0 ? src : tmp) */
6591 for (i = 0; i < 4; i++) {
6592 if (!(write_mask & (1<<i)))
6593 continue;
6594
6595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6596 alu.op = ALU_OP3_CNDGE_INT;
6597 alu.is_op3 = 1;
6598 alu.dst.write = 1;
6599
6600 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6601
6602 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6603 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6604 alu.src[2].sel = ctx->temp_reg;
6605 alu.src[2].chan = i;
6606
6607 if (i == last_inst)
6608 alu.last = 1;
6609 r = r600_bytecode_add_alu(ctx->bc, &alu);
6610 if (r)
6611 return r;
6612 }
6613 return 0;
6614 }
6615
6616 static int tgsi_issg(struct r600_shader_ctx *ctx)
6617 {
6618 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6619 struct r600_bytecode_alu alu;
6620 int i, r;
6621 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6622 int last_inst = tgsi_last_instruction(write_mask);
6623
6624 /* tmp = (src >= 0 ? src : -1) */
6625 for (i = 0; i < 4; i++) {
6626 if (!(write_mask & (1<<i)))
6627 continue;
6628
6629 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6630 alu.op = ALU_OP3_CNDGE_INT;
6631 alu.is_op3 = 1;
6632
6633 alu.dst.sel = ctx->temp_reg;
6634 alu.dst.chan = i;
6635 alu.dst.write = 1;
6636
6637 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6638 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6639 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6640
6641 if (i == last_inst)
6642 alu.last = 1;
6643 r = r600_bytecode_add_alu(ctx->bc, &alu);
6644 if (r)
6645 return r;
6646 }
6647
6648 /* dst = (tmp > 0 ? 1 : tmp) */
6649 for (i = 0; i < 4; i++) {
6650 if (!(write_mask & (1<<i)))
6651 continue;
6652
6653 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6654 alu.op = ALU_OP3_CNDGT_INT;
6655 alu.is_op3 = 1;
6656 alu.dst.write = 1;
6657
6658 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6659
6660 alu.src[0].sel = ctx->temp_reg;
6661 alu.src[0].chan = i;
6662
6663 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6664
6665 alu.src[2].sel = ctx->temp_reg;
6666 alu.src[2].chan = i;
6667
6668 if (i == last_inst)
6669 alu.last = 1;
6670 r = r600_bytecode_add_alu(ctx->bc, &alu);
6671 if (r)
6672 return r;
6673 }
6674 return 0;
6675 }
6676
6677
6678
6679 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6680 {
6681 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6682 struct r600_bytecode_alu alu;
6683 int i, r;
6684
6685 /* tmp = (src > 0 ? 1 : src) */
6686 for (i = 0; i < 4; i++) {
6687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6688 alu.op = ALU_OP3_CNDGT;
6689 alu.is_op3 = 1;
6690
6691 alu.dst.sel = ctx->temp_reg;
6692 alu.dst.chan = i;
6693
6694 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6695 alu.src[1].sel = V_SQ_ALU_SRC_1;
6696 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6697
6698 if (i == 3)
6699 alu.last = 1;
6700 r = r600_bytecode_add_alu(ctx->bc, &alu);
6701 if (r)
6702 return r;
6703 }
6704
6705 /* dst = (-tmp > 0 ? -1 : tmp) */
6706 for (i = 0; i < 4; i++) {
6707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6708 alu.op = ALU_OP3_CNDGT;
6709 alu.is_op3 = 1;
6710 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6711
6712 alu.src[0].sel = ctx->temp_reg;
6713 alu.src[0].chan = i;
6714 alu.src[0].neg = 1;
6715
6716 alu.src[1].sel = V_SQ_ALU_SRC_1;
6717 alu.src[1].neg = 1;
6718
6719 alu.src[2].sel = ctx->temp_reg;
6720 alu.src[2].chan = i;
6721
6722 if (i == 3)
6723 alu.last = 1;
6724 r = r600_bytecode_add_alu(ctx->bc, &alu);
6725 if (r)
6726 return r;
6727 }
6728 return 0;
6729 }
6730
6731 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6732 {
6733 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6734 struct r600_bytecode_alu alu;
6735 int i, r, t1, t2;
6736
6737 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6738 int last_inst = tgsi_last_instruction(write_mask);
6739
6740 t1 = r600_get_temp(ctx);
6741
6742 for (i = 0; i < 4; i++) {
6743 if (!(write_mask & (1<<i)))
6744 continue;
6745
6746 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6747 alu.op = ALU_OP2_SETGE_INT;
6748 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6749 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6750 alu.src[1].value = 32;
6751 alu.dst.sel = ctx->temp_reg;
6752 alu.dst.chan = i;
6753 alu.dst.write = 1;
6754 alu.last = i == last_inst;
6755 r = r600_bytecode_add_alu(ctx->bc, &alu);
6756 if (r)
6757 return r;
6758 }
6759
6760 for (i = 0; i < 4; i++) {
6761 if (!(write_mask & (1<<i)))
6762 continue;
6763
6764 /* create mask tmp */
6765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6766 alu.op = ALU_OP2_BFM_INT;
6767 alu.dst.sel = t1;
6768 alu.dst.chan = i;
6769 alu.dst.write = 1;
6770 alu.last = i == last_inst;
6771
6772 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6773 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6774
6775 r = r600_bytecode_add_alu(ctx->bc, &alu);
6776 if (r)
6777 return r;
6778 }
6779
6780 t2 = r600_get_temp(ctx);
6781
6782 for (i = 0; i < 4; i++) {
6783 if (!(write_mask & (1<<i)))
6784 continue;
6785
6786 /* shift insert left */
6787 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6788 alu.op = ALU_OP2_LSHL_INT;
6789 alu.dst.sel = t2;
6790 alu.dst.chan = i;
6791 alu.dst.write = 1;
6792 alu.last = i == last_inst;
6793
6794 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6795 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6796
6797 r = r600_bytecode_add_alu(ctx->bc, &alu);
6798 if (r)
6799 return r;
6800 }
6801
6802 for (i = 0; i < 4; i++) {
6803 if (!(write_mask & (1<<i)))
6804 continue;
6805
6806 /* actual bitfield insert */
6807 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6808 alu.op = ALU_OP3_BFI_INT;
6809 alu.is_op3 = 1;
6810 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6811 alu.dst.chan = i;
6812 alu.dst.write = 1;
6813 alu.last = i == last_inst;
6814
6815 alu.src[0].sel = t1;
6816 alu.src[0].chan = i;
6817 alu.src[1].sel = t2;
6818 alu.src[1].chan = i;
6819 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6820
6821 r = r600_bytecode_add_alu(ctx->bc, &alu);
6822 if (r)
6823 return r;
6824 }
6825
6826 for (i = 0; i < 4; i++) {
6827 if (!(write_mask & (1<<i)))
6828 continue;
6829 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6830 alu.op = ALU_OP3_CNDE_INT;
6831 alu.is_op3 = 1;
6832 alu.src[0].sel = ctx->temp_reg;
6833 alu.src[0].chan = i;
6834 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6835
6836 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6837
6838 alu.src[1].sel = alu.dst.sel;
6839 alu.src[1].chan = i;
6840
6841 alu.last = i == last_inst;
6842 r = r600_bytecode_add_alu(ctx->bc, &alu);
6843 if (r)
6844 return r;
6845 }
6846 return 0;
6847 }
6848
6849 static int tgsi_msb(struct r600_shader_ctx *ctx)
6850 {
6851 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6852 struct r600_bytecode_alu alu;
6853 int i, r, t1, t2;
6854
6855 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6856 int last_inst = tgsi_last_instruction(write_mask);
6857
6858 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6859 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6860
6861 t1 = ctx->temp_reg;
6862
6863 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6864 for (i = 0; i < 4; i++) {
6865 if (!(write_mask & (1<<i)))
6866 continue;
6867
6868 /* t1 = FFBH_INT / FFBH_UINT */
6869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6870 alu.op = ctx->inst_info->op;
6871 alu.dst.sel = t1;
6872 alu.dst.chan = i;
6873 alu.dst.write = 1;
6874 alu.last = i == last_inst;
6875
6876 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6877
6878 r = r600_bytecode_add_alu(ctx->bc, &alu);
6879 if (r)
6880 return r;
6881 }
6882
6883 t2 = r600_get_temp(ctx);
6884
6885 for (i = 0; i < 4; i++) {
6886 if (!(write_mask & (1<<i)))
6887 continue;
6888
6889 /* t2 = 31 - t1 */
6890 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6891 alu.op = ALU_OP2_SUB_INT;
6892 alu.dst.sel = t2;
6893 alu.dst.chan = i;
6894 alu.dst.write = 1;
6895 alu.last = i == last_inst;
6896
6897 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6898 alu.src[0].value = 31;
6899 alu.src[1].sel = t1;
6900 alu.src[1].chan = i;
6901
6902 r = r600_bytecode_add_alu(ctx->bc, &alu);
6903 if (r)
6904 return r;
6905 }
6906
6907 for (i = 0; i < 4; i++) {
6908 if (!(write_mask & (1<<i)))
6909 continue;
6910
6911 /* result = t1 >= 0 ? t2 : t1 */
6912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6913 alu.op = ALU_OP3_CNDGE_INT;
6914 alu.is_op3 = 1;
6915 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6916 alu.dst.chan = i;
6917 alu.dst.write = 1;
6918 alu.last = i == last_inst;
6919
6920 alu.src[0].sel = t1;
6921 alu.src[0].chan = i;
6922 alu.src[1].sel = t2;
6923 alu.src[1].chan = i;
6924 alu.src[2].sel = t1;
6925 alu.src[2].chan = i;
6926
6927 r = r600_bytecode_add_alu(ctx->bc, &alu);
6928 if (r)
6929 return r;
6930 }
6931
6932 return 0;
6933 }
6934
6935 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6936 {
6937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6938 struct r600_bytecode_alu alu;
6939 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6940 unsigned location;
6941 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6942
6943 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6944
6945 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6946 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6947 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6948 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6949 }
6950 else {
6951 location = TGSI_INTERPOLATE_LOC_CENTROID;
6952 }
6953
6954 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6955 if (k < 0)
6956 k = 0;
6957 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6958 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6959
6960 /* NOTE: currently offset is not perspective correct */
6961 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6962 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6963 int sample_gpr = -1;
6964 int gradientsH, gradientsV;
6965 struct r600_bytecode_tex tex;
6966
6967 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6968 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6969 }
6970
6971 gradientsH = r600_get_temp(ctx);
6972 gradientsV = r600_get_temp(ctx);
6973 for (i = 0; i < 2; i++) {
6974 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6975 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6976 tex.src_gpr = interp_gpr;
6977 tex.src_sel_x = interp_base_chan + 0;
6978 tex.src_sel_y = interp_base_chan + 1;
6979 tex.src_sel_z = 0;
6980 tex.src_sel_w = 0;
6981 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6982 tex.dst_sel_x = 0;
6983 tex.dst_sel_y = 1;
6984 tex.dst_sel_z = 7;
6985 tex.dst_sel_w = 7;
6986 tex.inst_mod = 1; // Use per pixel gradient calculation
6987 tex.sampler_id = 0;
6988 tex.resource_id = tex.sampler_id;
6989 r = r600_bytecode_add_tex(ctx->bc, &tex);
6990 if (r)
6991 return r;
6992 }
6993
6994 for (i = 0; i < 2; i++) {
6995 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6996 alu.op = ALU_OP3_MULADD;
6997 alu.is_op3 = 1;
6998 alu.src[0].sel = gradientsH;
6999 alu.src[0].chan = i;
7000 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7001 alu.src[1].sel = sample_gpr;
7002 alu.src[1].chan = 2;
7003 }
7004 else {
7005 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
7006 }
7007 alu.src[2].sel = interp_gpr;
7008 alu.src[2].chan = interp_base_chan + i;
7009 alu.dst.sel = ctx->temp_reg;
7010 alu.dst.chan = i;
7011 alu.last = i == 1;
7012
7013 r = r600_bytecode_add_alu(ctx->bc, &alu);
7014 if (r)
7015 return r;
7016 }
7017
7018 for (i = 0; i < 2; i++) {
7019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7020 alu.op = ALU_OP3_MULADD;
7021 alu.is_op3 = 1;
7022 alu.src[0].sel = gradientsV;
7023 alu.src[0].chan = i;
7024 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7025 alu.src[1].sel = sample_gpr;
7026 alu.src[1].chan = 3;
7027 }
7028 else {
7029 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
7030 }
7031 alu.src[2].sel = ctx->temp_reg;
7032 alu.src[2].chan = i;
7033 alu.dst.sel = ctx->temp_reg;
7034 alu.dst.chan = i;
7035 alu.last = i == 1;
7036
7037 r = r600_bytecode_add_alu(ctx->bc, &alu);
7038 if (r)
7039 return r;
7040 }
7041 }
7042
7043 tmp = r600_get_temp(ctx);
7044 for (i = 0; i < 8; i++) {
7045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7046 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
7047
7048 alu.dst.sel = tmp;
7049 if ((i > 1 && i < 6)) {
7050 alu.dst.write = 1;
7051 }
7052 else {
7053 alu.dst.write = 0;
7054 }
7055 alu.dst.chan = i % 4;
7056
7057 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
7058 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7059 alu.src[0].sel = ctx->temp_reg;
7060 alu.src[0].chan = 1 - (i % 2);
7061 } else {
7062 alu.src[0].sel = interp_gpr;
7063 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
7064 }
7065 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
7066 alu.src[1].chan = 0;
7067
7068 alu.last = i % 4 == 3;
7069 alu.bank_swizzle_force = SQ_ALU_VEC_210;
7070
7071 r = r600_bytecode_add_alu(ctx->bc, &alu);
7072 if (r)
7073 return r;
7074 }
7075
7076 // INTERP can't swizzle dst
7077 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7078 for (i = 0; i <= lasti; i++) {
7079 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7080 continue;
7081
7082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7083 alu.op = ALU_OP1_MOV;
7084 alu.src[0].sel = tmp;
7085 alu.src[0].chan = ctx->src[0].swizzle[i];
7086 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7087 alu.dst.write = 1;
7088 alu.last = i == lasti;
7089 r = r600_bytecode_add_alu(ctx->bc, &alu);
7090 if (r)
7091 return r;
7092 }
7093
7094 return 0;
7095 }
7096
7097
7098 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
7099 {
7100 struct r600_bytecode_alu alu;
7101 int i, r;
7102
7103 for (i = 0; i < 4; i++) {
7104 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7105 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
7106 alu.op = ALU_OP0_NOP;
7107 alu.dst.chan = i;
7108 } else {
7109 alu.op = ALU_OP1_MOV;
7110 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7111 alu.src[0].sel = ctx->temp_reg;
7112 alu.src[0].chan = i;
7113 }
7114 if (i == 3) {
7115 alu.last = 1;
7116 }
7117 r = r600_bytecode_add_alu(ctx->bc, &alu);
7118 if (r)
7119 return r;
7120 }
7121 return 0;
7122 }
7123
7124 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
7125 unsigned writemask,
7126 struct r600_bytecode_alu_src *bc_src,
7127 const struct r600_shader_src *shader_src)
7128 {
7129 struct r600_bytecode_alu alu;
7130 int i, r;
7131 int lasti = tgsi_last_instruction(writemask);
7132 int temp_reg = 0;
7133
7134 r600_bytecode_src(&bc_src[0], shader_src, 0);
7135 r600_bytecode_src(&bc_src[1], shader_src, 1);
7136 r600_bytecode_src(&bc_src[2], shader_src, 2);
7137 r600_bytecode_src(&bc_src[3], shader_src, 3);
7138
7139 if (bc_src->abs) {
7140 temp_reg = r600_get_temp(ctx);
7141
7142 for (i = 0; i < lasti + 1; i++) {
7143 if (!(writemask & (1 << i)))
7144 continue;
7145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7146 alu.op = ALU_OP1_MOV;
7147 alu.dst.sel = temp_reg;
7148 alu.dst.chan = i;
7149 alu.dst.write = 1;
7150 alu.src[0] = bc_src[i];
7151 if (i == lasti) {
7152 alu.last = 1;
7153 }
7154 r = r600_bytecode_add_alu(ctx->bc, &alu);
7155 if (r)
7156 return r;
7157 memset(&bc_src[i], 0, sizeof(*bc_src));
7158 bc_src[i].sel = temp_reg;
7159 bc_src[i].chan = i;
7160 }
7161 }
7162 return 0;
7163 }
7164
7165 static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
7166 {
7167 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7168 struct r600_bytecode_alu alu;
7169 struct r600_bytecode_alu_src srcs[4][4];
7170 int i, j, r;
7171 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7172 unsigned op = ctx->inst_info->op;
7173
7174 if (op == ALU_OP3_MULADD_IEEE &&
7175 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
7176 op = ALU_OP3_MULADD;
7177
7178 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7179 r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
7180 srcs[j], &ctx->src[j]);
7181 if (r)
7182 return r;
7183 }
7184
7185 for (i = 0; i < lasti + 1; i++) {
7186 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7187 continue;
7188
7189 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7190 alu.op = op;
7191 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7192 alu.src[j] = srcs[j][i];
7193 }
7194
7195 if (dst == -1) {
7196 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7197 } else {
7198 alu.dst.sel = dst;
7199 }
7200 alu.dst.chan = i;
7201 alu.dst.write = 1;
7202 alu.is_op3 = 1;
7203 if (i == lasti) {
7204 alu.last = 1;
7205 }
7206 r = r600_bytecode_add_alu(ctx->bc, &alu);
7207 if (r)
7208 return r;
7209 }
7210 return 0;
7211 }
7212
7213 static int tgsi_op3(struct r600_shader_ctx *ctx)
7214 {
7215 return tgsi_op3_dst(ctx, -1);
7216 }
7217
7218 static int tgsi_dp(struct r600_shader_ctx *ctx)
7219 {
7220 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7221 struct r600_bytecode_alu alu;
7222 int i, j, r;
7223 unsigned op = ctx->inst_info->op;
7224 if (op == ALU_OP2_DOT4_IEEE &&
7225 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
7226 op = ALU_OP2_DOT4;
7227
7228 for (i = 0; i < 4; i++) {
7229 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7230 alu.op = op;
7231 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7232 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
7233 }
7234
7235 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7236 alu.dst.chan = i;
7237 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
7238 /* handle some special cases */
7239 switch (inst->Instruction.Opcode) {
7240 case TGSI_OPCODE_DP2:
7241 if (i > 1) {
7242 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
7243 alu.src[0].chan = alu.src[1].chan = 0;
7244 }
7245 break;
7246 case TGSI_OPCODE_DP3:
7247 if (i > 2) {
7248 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
7249 alu.src[0].chan = alu.src[1].chan = 0;
7250 }
7251 break;
7252 default:
7253 break;
7254 }
7255 if (i == 3) {
7256 alu.last = 1;
7257 }
7258 r = r600_bytecode_add_alu(ctx->bc, &alu);
7259 if (r)
7260 return r;
7261 }
7262 return 0;
7263 }
7264
7265 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
7266 unsigned index)
7267 {
7268 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7269 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
7270 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
7271 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
7272 ctx->src[index].neg || ctx->src[index].abs ||
7273 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
7274 }
7275
7276 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
7277 unsigned index)
7278 {
7279 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7280 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
7281 }
7282
7283 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
7284 {
7285 struct r600_bytecode_vtx vtx;
7286 struct r600_bytecode_alu alu;
7287 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7288 int src_gpr, r, i;
7289 int id = tgsi_tex_get_src_gpr(ctx, 1);
7290 int sampler_index_mode = inst->Src[1].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7291
7292 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7293 if (src_requires_loading) {
7294 for (i = 0; i < 4; i++) {
7295 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7296 alu.op = ALU_OP1_MOV;
7297 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7298 alu.dst.sel = ctx->temp_reg;
7299 alu.dst.chan = i;
7300 if (i == 3)
7301 alu.last = 1;
7302 alu.dst.write = 1;
7303 r = r600_bytecode_add_alu(ctx->bc, &alu);
7304 if (r)
7305 return r;
7306 }
7307 src_gpr = ctx->temp_reg;
7308 }
7309
7310 memset(&vtx, 0, sizeof(vtx));
7311 vtx.op = FETCH_OP_VFETCH;
7312 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
7313 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7314 vtx.src_gpr = src_gpr;
7315 vtx.mega_fetch_count = 16;
7316 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7317 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7318 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
7319 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
7320 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
7321 vtx.use_const_fields = 1;
7322 vtx.buffer_index_mode = sampler_index_mode;
7323
7324 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
7325 return r;
7326
7327 if (ctx->bc->chip_class >= EVERGREEN)
7328 return 0;
7329
7330 for (i = 0; i < 4; i++) {
7331 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7332 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7333 continue;
7334
7335 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7336 alu.op = ALU_OP2_AND_INT;
7337
7338 alu.dst.chan = i;
7339 alu.dst.sel = vtx.dst_gpr;
7340 alu.dst.write = 1;
7341
7342 alu.src[0].sel = vtx.dst_gpr;
7343 alu.src[0].chan = i;
7344
7345 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
7346 alu.src[1].sel += (id * 2);
7347 alu.src[1].chan = i % 4;
7348 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7349
7350 if (i == lasti)
7351 alu.last = 1;
7352 r = r600_bytecode_add_alu(ctx->bc, &alu);
7353 if (r)
7354 return r;
7355 }
7356
7357 if (inst->Dst[0].Register.WriteMask & 3) {
7358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7359 alu.op = ALU_OP2_OR_INT;
7360
7361 alu.dst.chan = 3;
7362 alu.dst.sel = vtx.dst_gpr;
7363 alu.dst.write = 1;
7364
7365 alu.src[0].sel = vtx.dst_gpr;
7366 alu.src[0].chan = 3;
7367
7368 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
7369 alu.src[1].chan = 0;
7370 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7371
7372 alu.last = 1;
7373 r = r600_bytecode_add_alu(ctx->bc, &alu);
7374 if (r)
7375 return r;
7376 }
7377 return 0;
7378 }
7379
7380 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset, int eg_buffer_base)
7381 {
7382 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7383 int r;
7384 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
7385 int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7386
7387 if (ctx->bc->chip_class < EVERGREEN) {
7388 struct r600_bytecode_alu alu;
7389 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7390 alu.op = ALU_OP1_MOV;
7391 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7392 /* r600 we have them at channel 2 of the second dword */
7393 alu.src[0].sel += (id * 2) + 1;
7394 alu.src[0].chan = 1;
7395 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7396 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
7397 alu.last = 1;
7398 r = r600_bytecode_add_alu(ctx->bc, &alu);
7399 if (r)
7400 return r;
7401 return 0;
7402 } else {
7403 struct r600_bytecode_vtx vtx;
7404 memset(&vtx, 0, sizeof(vtx));
7405 vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
7406 vtx.buffer_id = id + eg_buffer_base;
7407 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7408 vtx.src_gpr = 0;
7409 vtx.mega_fetch_count = 16; /* no idea here really... */
7410 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7411 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7412 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 4 : 7; /* SEL_Y */
7413 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 4 : 7; /* SEL_Z */
7414 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 4 : 7; /* SEL_W */
7415 vtx.data_format = FMT_32_32_32_32;
7416 vtx.buffer_index_mode = sampler_index_mode;
7417
7418 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
7419 return r;
7420 return 0;
7421 }
7422 }
7423
7424
7425 static int tgsi_tex(struct r600_shader_ctx *ctx)
7426 {
7427 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7428 struct r600_bytecode_tex tex;
7429 struct r600_bytecode_alu alu;
7430 unsigned src_gpr;
7431 int r, i, j;
7432 int opcode;
7433 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
7434 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7435 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
7436 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
7437
7438 bool txf_add_offsets = inst->Texture.NumOffsets &&
7439 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7440 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
7441
7442 /* Texture fetch instructions can only use gprs as source.
7443 * Also they cannot negate the source or take the absolute value */
7444 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
7445 tgsi_tex_src_requires_loading(ctx, 0)) ||
7446 read_compressed_msaa || txf_add_offsets;
7447
7448 boolean src_loaded = FALSE;
7449 unsigned sampler_src_reg = 1;
7450 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
7451 boolean has_txq_cube_array_z = false;
7452 unsigned sampler_index_mode;
7453
7454 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
7455 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7456 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
7457 if (inst->Dst[0].Register.WriteMask & 4) {
7458 ctx->shader->has_txq_cube_array_z_comp = true;
7459 has_txq_cube_array_z = true;
7460 }
7461
7462 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
7463 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7464 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
7465 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
7466 sampler_src_reg = 2;
7467
7468 /* TGSI moves the sampler to src reg 3 for TXD */
7469 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
7470 sampler_src_reg = 3;
7471
7472 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7473
7474 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7475
7476 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
7477 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
7478 if (ctx->bc->chip_class < EVERGREEN)
7479 ctx->shader->uses_tex_buffers = true;
7480 return r600_do_buffer_txq(ctx, 1, 0, R600_MAX_CONST_BUFFERS);
7481 }
7482 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
7483 if (ctx->bc->chip_class < EVERGREEN)
7484 ctx->shader->uses_tex_buffers = true;
7485 return do_vtx_fetch_inst(ctx, src_requires_loading);
7486 }
7487 }
7488
7489 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
7490 int out_chan;
7491 /* Add perspective divide */
7492 if (ctx->bc->chip_class == CAYMAN) {
7493 out_chan = 2;
7494 for (i = 0; i < 3; i++) {
7495 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7496 alu.op = ALU_OP1_RECIP_IEEE;
7497 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7498
7499 alu.dst.sel = ctx->temp_reg;
7500 alu.dst.chan = i;
7501 if (i == 2)
7502 alu.last = 1;
7503 if (out_chan == i)
7504 alu.dst.write = 1;
7505 r = r600_bytecode_add_alu(ctx->bc, &alu);
7506 if (r)
7507 return r;
7508 }
7509
7510 } else {
7511 out_chan = 3;
7512 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7513 alu.op = ALU_OP1_RECIP_IEEE;
7514 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7515
7516 alu.dst.sel = ctx->temp_reg;
7517 alu.dst.chan = out_chan;
7518 alu.last = 1;
7519 alu.dst.write = 1;
7520 r = r600_bytecode_add_alu(ctx->bc, &alu);
7521 if (r)
7522 return r;
7523 }
7524
7525 for (i = 0; i < 3; i++) {
7526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7527 alu.op = ALU_OP2_MUL;
7528 alu.src[0].sel = ctx->temp_reg;
7529 alu.src[0].chan = out_chan;
7530 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7531 alu.dst.sel = ctx->temp_reg;
7532 alu.dst.chan = i;
7533 alu.dst.write = 1;
7534 r = r600_bytecode_add_alu(ctx->bc, &alu);
7535 if (r)
7536 return r;
7537 }
7538 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7539 alu.op = ALU_OP1_MOV;
7540 alu.src[0].sel = V_SQ_ALU_SRC_1;
7541 alu.src[0].chan = 0;
7542 alu.dst.sel = ctx->temp_reg;
7543 alu.dst.chan = 3;
7544 alu.last = 1;
7545 alu.dst.write = 1;
7546 r = r600_bytecode_add_alu(ctx->bc, &alu);
7547 if (r)
7548 return r;
7549 src_loaded = TRUE;
7550 src_gpr = ctx->temp_reg;
7551 }
7552
7553
7554 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7555 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7556 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7557 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7558 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
7559
7560 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
7561 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
7562
7563 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7564 for (i = 0; i < 4; i++) {
7565 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7566 alu.op = ALU_OP2_CUBE;
7567 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7568 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
7569 alu.dst.sel = ctx->temp_reg;
7570 alu.dst.chan = i;
7571 if (i == 3)
7572 alu.last = 1;
7573 alu.dst.write = 1;
7574 r = r600_bytecode_add_alu(ctx->bc, &alu);
7575 if (r)
7576 return r;
7577 }
7578
7579 /* tmp1.z = RCP_e(|tmp1.z|) */
7580 if (ctx->bc->chip_class == CAYMAN) {
7581 for (i = 0; i < 3; i++) {
7582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7583 alu.op = ALU_OP1_RECIP_IEEE;
7584 alu.src[0].sel = ctx->temp_reg;
7585 alu.src[0].chan = 2;
7586 alu.src[0].abs = 1;
7587 alu.dst.sel = ctx->temp_reg;
7588 alu.dst.chan = i;
7589 if (i == 2)
7590 alu.dst.write = 1;
7591 if (i == 2)
7592 alu.last = 1;
7593 r = r600_bytecode_add_alu(ctx->bc, &alu);
7594 if (r)
7595 return r;
7596 }
7597 } else {
7598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7599 alu.op = ALU_OP1_RECIP_IEEE;
7600 alu.src[0].sel = ctx->temp_reg;
7601 alu.src[0].chan = 2;
7602 alu.src[0].abs = 1;
7603 alu.dst.sel = ctx->temp_reg;
7604 alu.dst.chan = 2;
7605 alu.dst.write = 1;
7606 alu.last = 1;
7607 r = r600_bytecode_add_alu(ctx->bc, &alu);
7608 if (r)
7609 return r;
7610 }
7611
7612 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7613 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7614 * muladd has no writemask, have to use another temp
7615 */
7616 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7617 alu.op = ALU_OP3_MULADD;
7618 alu.is_op3 = 1;
7619
7620 alu.src[0].sel = ctx->temp_reg;
7621 alu.src[0].chan = 0;
7622 alu.src[1].sel = ctx->temp_reg;
7623 alu.src[1].chan = 2;
7624
7625 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7626 alu.src[2].chan = 0;
7627 alu.src[2].value = u_bitcast_f2u(1.5f);
7628
7629 alu.dst.sel = ctx->temp_reg;
7630 alu.dst.chan = 0;
7631 alu.dst.write = 1;
7632
7633 r = r600_bytecode_add_alu(ctx->bc, &alu);
7634 if (r)
7635 return r;
7636
7637 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7638 alu.op = ALU_OP3_MULADD;
7639 alu.is_op3 = 1;
7640
7641 alu.src[0].sel = ctx->temp_reg;
7642 alu.src[0].chan = 1;
7643 alu.src[1].sel = ctx->temp_reg;
7644 alu.src[1].chan = 2;
7645
7646 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7647 alu.src[2].chan = 0;
7648 alu.src[2].value = u_bitcast_f2u(1.5f);
7649
7650 alu.dst.sel = ctx->temp_reg;
7651 alu.dst.chan = 1;
7652 alu.dst.write = 1;
7653
7654 alu.last = 1;
7655 r = r600_bytecode_add_alu(ctx->bc, &alu);
7656 if (r)
7657 return r;
7658 /* write initial compare value into Z component
7659 - W src 0 for shadow cube
7660 - X src 1 for shadow cube array */
7661 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7662 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7663 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7664 alu.op = ALU_OP1_MOV;
7665 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7666 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7667 else
7668 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7669 alu.dst.sel = ctx->temp_reg;
7670 alu.dst.chan = 2;
7671 alu.dst.write = 1;
7672 alu.last = 1;
7673 r = r600_bytecode_add_alu(ctx->bc, &alu);
7674 if (r)
7675 return r;
7676 }
7677
7678 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7679 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7680 if (ctx->bc->chip_class >= EVERGREEN) {
7681 int mytmp = r600_get_temp(ctx);
7682 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7683 alu.op = ALU_OP1_MOV;
7684 alu.src[0].sel = ctx->temp_reg;
7685 alu.src[0].chan = 3;
7686 alu.dst.sel = mytmp;
7687 alu.dst.chan = 0;
7688 alu.dst.write = 1;
7689 alu.last = 1;
7690 r = r600_bytecode_add_alu(ctx->bc, &alu);
7691 if (r)
7692 return r;
7693
7694 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7695 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7696 alu.op = ALU_OP3_MULADD;
7697 alu.is_op3 = 1;
7698 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7699 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7700 alu.src[1].chan = 0;
7701 alu.src[1].value = u_bitcast_f2u(8.0f);
7702 alu.src[2].sel = mytmp;
7703 alu.src[2].chan = 0;
7704 alu.dst.sel = ctx->temp_reg;
7705 alu.dst.chan = 3;
7706 alu.dst.write = 1;
7707 alu.last = 1;
7708 r = r600_bytecode_add_alu(ctx->bc, &alu);
7709 if (r)
7710 return r;
7711 } else if (ctx->bc->chip_class < EVERGREEN) {
7712 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7713 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7714 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7715 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7716 tex.src_gpr = r600_get_temp(ctx);
7717 tex.src_sel_x = 0;
7718 tex.src_sel_y = 0;
7719 tex.src_sel_z = 0;
7720 tex.src_sel_w = 0;
7721 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7722 tex.coord_type_x = 1;
7723 tex.coord_type_y = 1;
7724 tex.coord_type_z = 1;
7725 tex.coord_type_w = 1;
7726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7727 alu.op = ALU_OP1_MOV;
7728 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7729 alu.dst.sel = tex.src_gpr;
7730 alu.dst.chan = 0;
7731 alu.last = 1;
7732 alu.dst.write = 1;
7733 r = r600_bytecode_add_alu(ctx->bc, &alu);
7734 if (r)
7735 return r;
7736
7737 r = r600_bytecode_add_tex(ctx->bc, &tex);
7738 if (r)
7739 return r;
7740 }
7741
7742 }
7743
7744 /* for cube forms of lod and bias we need to route things */
7745 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7746 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7747 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7748 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7750 alu.op = ALU_OP1_MOV;
7751 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7752 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7753 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7754 else
7755 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7756 alu.dst.sel = ctx->temp_reg;
7757 alu.dst.chan = 2;
7758 alu.last = 1;
7759 alu.dst.write = 1;
7760 r = r600_bytecode_add_alu(ctx->bc, &alu);
7761 if (r)
7762 return r;
7763 }
7764
7765 src_loaded = TRUE;
7766 src_gpr = ctx->temp_reg;
7767 }
7768
7769 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7770 int temp_h = 0, temp_v = 0;
7771 int start_val = 0;
7772
7773 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7774 if (src_loaded == TRUE)
7775 start_val = 1;
7776 else
7777 src_loaded = TRUE;
7778 for (i = start_val; i < 3; i++) {
7779 int treg = r600_get_temp(ctx);
7780
7781 if (i == 0)
7782 src_gpr = treg;
7783 else if (i == 1)
7784 temp_h = treg;
7785 else
7786 temp_v = treg;
7787
7788 for (j = 0; j < 4; j++) {
7789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7790 alu.op = ALU_OP1_MOV;
7791 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7792 alu.dst.sel = treg;
7793 alu.dst.chan = j;
7794 if (j == 3)
7795 alu.last = 1;
7796 alu.dst.write = 1;
7797 r = r600_bytecode_add_alu(ctx->bc, &alu);
7798 if (r)
7799 return r;
7800 }
7801 }
7802 for (i = 1; i < 3; i++) {
7803 /* set gradients h/v */
7804 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7805 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7806 FETCH_OP_SET_GRADIENTS_V;
7807 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7808 tex.sampler_index_mode = sampler_index_mode;
7809 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7810 tex.resource_index_mode = sampler_index_mode;
7811
7812 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7813 tex.src_sel_x = 0;
7814 tex.src_sel_y = 1;
7815 tex.src_sel_z = 2;
7816 tex.src_sel_w = 3;
7817
7818 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7819 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7820 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7821 tex.coord_type_x = 1;
7822 tex.coord_type_y = 1;
7823 tex.coord_type_z = 1;
7824 tex.coord_type_w = 1;
7825 }
7826 r = r600_bytecode_add_tex(ctx->bc, &tex);
7827 if (r)
7828 return r;
7829 }
7830 }
7831
7832 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7833 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
7834 * incorrectly forces nearest filtering if the texture format is integer.
7835 * The only effect it has on Gather4, which always returns 4 texels for
7836 * bilinear filtering, is that the final coordinates are off by 0.5 of
7837 * the texel size.
7838 *
7839 * The workaround is to subtract 0.5 from the unnormalized coordinates,
7840 * or (0.5 / size) from the normalized coordinates.
7841 */
7842 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
7843 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
7844 int treg = r600_get_temp(ctx);
7845
7846 /* mov array and comparison oordinate to temp_reg if needed */
7847 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7848 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7849 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) && !src_loaded) {
7850 int end = inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ? 3 : 2;
7851 for (i = 2; i <= end; i++) {
7852 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7853 alu.op = ALU_OP1_MOV;
7854 alu.dst.sel = ctx->temp_reg;
7855 alu.dst.chan = i;
7856 alu.dst.write = 1;
7857 alu.last = (i == end);
7858 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7859 r = r600_bytecode_add_alu(ctx->bc, &alu);
7860 if (r)
7861 return r;
7862 }
7863 }
7864
7865 if (inst->Texture.Texture == TGSI_TEXTURE_RECT ||
7866 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
7867 for (i = 0; i < 2; i++) {
7868 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7869 alu.op = ALU_OP2_ADD;
7870 alu.dst.sel = ctx->temp_reg;
7871 alu.dst.chan = i;
7872 alu.dst.write = 1;
7873 alu.last = i == 1;
7874 if (src_loaded) {
7875 alu.src[0].sel = ctx->temp_reg;
7876 alu.src[0].chan = i;
7877 } else
7878 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7879 alu.src[1].sel = V_SQ_ALU_SRC_0_5;
7880 alu.src[1].neg = 1;
7881 r = r600_bytecode_add_alu(ctx->bc, &alu);
7882 if (r)
7883 return r;
7884 }
7885 } else {
7886 /* execute a TXQ */
7887 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7888 tex.op = FETCH_OP_GET_TEXTURE_RESINFO;
7889 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7890 tex.sampler_index_mode = sampler_index_mode;
7891 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7892 tex.resource_index_mode = sampler_index_mode;
7893 tex.dst_gpr = treg;
7894 tex.src_sel_x = 4;
7895 tex.src_sel_y = 4;
7896 tex.src_sel_z = 4;
7897 tex.src_sel_w = 4;
7898 tex.dst_sel_x = 0;
7899 tex.dst_sel_y = 1;
7900 tex.dst_sel_z = 7;
7901 tex.dst_sel_w = 7;
7902 r = r600_bytecode_add_tex(ctx->bc, &tex);
7903 if (r)
7904 return r;
7905
7906 /* coord.xy = -0.5 * (1.0/int_to_flt(size)) + coord.xy */
7907 if (ctx->bc->chip_class == CAYMAN) {
7908 /* */
7909 for (i = 0; i < 2; i++) {
7910 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7911 alu.op = ALU_OP1_INT_TO_FLT;
7912 alu.dst.sel = treg;
7913 alu.dst.chan = i;
7914 alu.dst.write = 1;
7915 alu.src[0].sel = treg;
7916 alu.src[0].chan = i;
7917 alu.last = (i == 1) ? 1 : 0;
7918 r = r600_bytecode_add_alu(ctx->bc, &alu);
7919 if (r)
7920 return r;
7921 }
7922 for (j = 0; j < 2; j++) {
7923 for (i = 0; i < 3; i++) {
7924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7925 alu.op = ALU_OP1_RECIP_IEEE;
7926 alu.src[0].sel = treg;
7927 alu.src[0].chan = j;
7928 alu.dst.sel = treg;
7929 alu.dst.chan = i;
7930 if (i == 2)
7931 alu.last = 1;
7932 if (i == j)
7933 alu.dst.write = 1;
7934 r = r600_bytecode_add_alu(ctx->bc, &alu);
7935 if (r)
7936 return r;
7937 }
7938 }
7939 } else {
7940 for (i = 0; i < 2; i++) {
7941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7942 alu.op = ALU_OP1_INT_TO_FLT;
7943 alu.dst.sel = treg;
7944 alu.dst.chan = i;
7945 alu.dst.write = 1;
7946 alu.src[0].sel = treg;
7947 alu.src[0].chan = i;
7948 alu.last = 1;
7949 r = r600_bytecode_add_alu(ctx->bc, &alu);
7950 if (r)
7951 return r;
7952 }
7953 for (i = 0; i < 2; i++) {
7954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7955 alu.op = ALU_OP1_RECIP_IEEE;
7956 alu.src[0].sel = treg;
7957 alu.src[0].chan = i;
7958 alu.dst.sel = treg;
7959 alu.dst.chan = i;
7960 alu.last = 1;
7961 alu.dst.write = 1;
7962 r = r600_bytecode_add_alu(ctx->bc, &alu);
7963 if (r)
7964 return r;
7965 }
7966 }
7967 for (i = 0; i < 2; i++) {
7968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7969 alu.op = ALU_OP3_MULADD;
7970 alu.is_op3 = 1;
7971 alu.dst.sel = ctx->temp_reg;
7972 alu.dst.chan = i;
7973 alu.dst.write = 1;
7974 alu.last = i == 1;
7975 alu.src[0].sel = treg;
7976 alu.src[0].chan = i;
7977 alu.src[1].sel = V_SQ_ALU_SRC_0_5;
7978 alu.src[1].neg = 1;
7979 if (src_loaded) {
7980 alu.src[2].sel = ctx->temp_reg;
7981 alu.src[2].chan = i;
7982 } else
7983 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
7984 r = r600_bytecode_add_alu(ctx->bc, &alu);
7985 if (r)
7986 return r;
7987 }
7988 }
7989 src_loaded = TRUE;
7990 src_gpr = ctx->temp_reg;
7991 }
7992 }
7993
7994 if (src_requires_loading && !src_loaded) {
7995 for (i = 0; i < 4; i++) {
7996 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7997 alu.op = ALU_OP1_MOV;
7998 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7999 alu.dst.sel = ctx->temp_reg;
8000 alu.dst.chan = i;
8001 if (i == 3)
8002 alu.last = 1;
8003 alu.dst.write = 1;
8004 r = r600_bytecode_add_alu(ctx->bc, &alu);
8005 if (r)
8006 return r;
8007 }
8008 src_loaded = TRUE;
8009 src_gpr = ctx->temp_reg;
8010 }
8011
8012 /* get offset values */
8013 if (inst->Texture.NumOffsets) {
8014 assert(inst->Texture.NumOffsets == 1);
8015
8016 /* The texture offset feature doesn't work with the TXF instruction
8017 * and must be emulated by adding the offset to the texture coordinates. */
8018 if (txf_add_offsets) {
8019 const struct tgsi_texture_offset *off = inst->TexOffsets;
8020
8021 switch (inst->Texture.Texture) {
8022 case TGSI_TEXTURE_3D:
8023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8024 alu.op = ALU_OP2_ADD_INT;
8025 alu.src[0].sel = src_gpr;
8026 alu.src[0].chan = 2;
8027 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8028 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
8029 alu.dst.sel = src_gpr;
8030 alu.dst.chan = 2;
8031 alu.dst.write = 1;
8032 alu.last = 1;
8033 r = r600_bytecode_add_alu(ctx->bc, &alu);
8034 if (r)
8035 return r;
8036 /* fall through */
8037
8038 case TGSI_TEXTURE_2D:
8039 case TGSI_TEXTURE_SHADOW2D:
8040 case TGSI_TEXTURE_RECT:
8041 case TGSI_TEXTURE_SHADOWRECT:
8042 case TGSI_TEXTURE_2D_ARRAY:
8043 case TGSI_TEXTURE_SHADOW2D_ARRAY:
8044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8045 alu.op = ALU_OP2_ADD_INT;
8046 alu.src[0].sel = src_gpr;
8047 alu.src[0].chan = 1;
8048 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8049 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
8050 alu.dst.sel = src_gpr;
8051 alu.dst.chan = 1;
8052 alu.dst.write = 1;
8053 alu.last = 1;
8054 r = r600_bytecode_add_alu(ctx->bc, &alu);
8055 if (r)
8056 return r;
8057 /* fall through */
8058
8059 case TGSI_TEXTURE_1D:
8060 case TGSI_TEXTURE_SHADOW1D:
8061 case TGSI_TEXTURE_1D_ARRAY:
8062 case TGSI_TEXTURE_SHADOW1D_ARRAY:
8063 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8064 alu.op = ALU_OP2_ADD_INT;
8065 alu.src[0].sel = src_gpr;
8066 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8067 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
8068 alu.dst.sel = src_gpr;
8069 alu.dst.write = 1;
8070 alu.last = 1;
8071 r = r600_bytecode_add_alu(ctx->bc, &alu);
8072 if (r)
8073 return r;
8074 break;
8075 /* texture offsets do not apply to other texture targets */
8076 }
8077 } else {
8078 switch (inst->Texture.Texture) {
8079 case TGSI_TEXTURE_3D:
8080 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
8081 /* fallthrough */
8082 case TGSI_TEXTURE_2D:
8083 case TGSI_TEXTURE_SHADOW2D:
8084 case TGSI_TEXTURE_RECT:
8085 case TGSI_TEXTURE_SHADOWRECT:
8086 case TGSI_TEXTURE_2D_ARRAY:
8087 case TGSI_TEXTURE_SHADOW2D_ARRAY:
8088 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
8089 /* fallthrough */
8090 case TGSI_TEXTURE_1D:
8091 case TGSI_TEXTURE_SHADOW1D:
8092 case TGSI_TEXTURE_1D_ARRAY:
8093 case TGSI_TEXTURE_SHADOW1D_ARRAY:
8094 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
8095 }
8096 }
8097 }
8098
8099 /* Obtain the sample index for reading a compressed MSAA color texture.
8100 * To read the FMASK, we use the ldfptr instruction, which tells us
8101 * where the samples are stored.
8102 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
8103 * which is the identity mapping. Each nibble says which physical sample
8104 * should be fetched to get that sample.
8105 *
8106 * Assume src.z contains the sample index. It should be modified like this:
8107 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
8108 * Then fetch the texel with src.
8109 */
8110 if (read_compressed_msaa) {
8111 unsigned sample_chan = 3;
8112 unsigned temp = r600_get_temp(ctx);
8113 assert(src_loaded);
8114
8115 /* temp.w = ldfptr() */
8116 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8117 tex.op = FETCH_OP_LD;
8118 tex.inst_mod = 1; /* to indicate this is ldfptr */
8119 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8120 tex.sampler_index_mode = sampler_index_mode;
8121 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
8122 tex.resource_index_mode = sampler_index_mode;
8123 tex.src_gpr = src_gpr;
8124 tex.dst_gpr = temp;
8125 tex.dst_sel_x = 7; /* mask out these components */
8126 tex.dst_sel_y = 7;
8127 tex.dst_sel_z = 7;
8128 tex.dst_sel_w = 0; /* store X */
8129 tex.src_sel_x = 0;
8130 tex.src_sel_y = 1;
8131 tex.src_sel_z = 2;
8132 tex.src_sel_w = 3;
8133 tex.offset_x = offset_x;
8134 tex.offset_y = offset_y;
8135 tex.offset_z = offset_z;
8136 r = r600_bytecode_add_tex(ctx->bc, &tex);
8137 if (r)
8138 return r;
8139
8140 /* temp.x = sample_index*4 */
8141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8142 alu.op = ALU_OP2_MULLO_INT;
8143 alu.src[0].sel = src_gpr;
8144 alu.src[0].chan = sample_chan;
8145 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8146 alu.src[1].value = 4;
8147 alu.dst.sel = temp;
8148 alu.dst.chan = 0;
8149 alu.dst.write = 1;
8150 r = emit_mul_int_op(ctx->bc, &alu);
8151 if (r)
8152 return r;
8153
8154 /* sample_index = temp.w >> temp.x */
8155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8156 alu.op = ALU_OP2_LSHR_INT;
8157 alu.src[0].sel = temp;
8158 alu.src[0].chan = 3;
8159 alu.src[1].sel = temp;
8160 alu.src[1].chan = 0;
8161 alu.dst.sel = src_gpr;
8162 alu.dst.chan = sample_chan;
8163 alu.dst.write = 1;
8164 alu.last = 1;
8165 r = r600_bytecode_add_alu(ctx->bc, &alu);
8166 if (r)
8167 return r;
8168
8169 /* sample_index & 0xF */
8170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8171 alu.op = ALU_OP2_AND_INT;
8172 alu.src[0].sel = src_gpr;
8173 alu.src[0].chan = sample_chan;
8174 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8175 alu.src[1].value = 0xF;
8176 alu.dst.sel = src_gpr;
8177 alu.dst.chan = sample_chan;
8178 alu.dst.write = 1;
8179 alu.last = 1;
8180 r = r600_bytecode_add_alu(ctx->bc, &alu);
8181 if (r)
8182 return r;
8183 #if 0
8184 /* visualize the FMASK */
8185 for (i = 0; i < 4; i++) {
8186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8187 alu.op = ALU_OP1_INT_TO_FLT;
8188 alu.src[0].sel = src_gpr;
8189 alu.src[0].chan = sample_chan;
8190 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8191 alu.dst.chan = i;
8192 alu.dst.write = 1;
8193 alu.last = 1;
8194 r = r600_bytecode_add_alu(ctx->bc, &alu);
8195 if (r)
8196 return r;
8197 }
8198 return 0;
8199 #endif
8200 }
8201
8202 /* does this shader want a num layers from TXQ for a cube array? */
8203 if (has_txq_cube_array_z) {
8204 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8205
8206 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8207 alu.op = ALU_OP1_MOV;
8208
8209 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8210 if (ctx->bc->chip_class >= EVERGREEN) {
8211 /* with eg each dword is number of cubes */
8212 alu.src[0].sel += id / 4;
8213 alu.src[0].chan = id % 4;
8214 } else {
8215 /* r600 we have them at channel 2 of the second dword */
8216 alu.src[0].sel += (id * 2) + 1;
8217 alu.src[0].chan = 2;
8218 }
8219 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8220 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8221 alu.last = 1;
8222 r = r600_bytecode_add_alu(ctx->bc, &alu);
8223 if (r)
8224 return r;
8225 /* disable writemask from texture instruction */
8226 inst->Dst[0].Register.WriteMask &= ~4;
8227 }
8228
8229 opcode = ctx->inst_info->op;
8230 if (opcode == FETCH_OP_GATHER4 &&
8231 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
8232 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
8233 opcode = FETCH_OP_GATHER4_O;
8234
8235 /* GATHER4_O/GATHER4_C_O use offset values loaded by
8236 SET_TEXTURE_OFFSETS instruction. The immediate offset values
8237 encoded in the instruction are ignored. */
8238 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8239 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
8240 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8241 tex.sampler_index_mode = sampler_index_mode;
8242 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
8243 tex.resource_index_mode = sampler_index_mode;
8244
8245 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
8246 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
8247 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
8248 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
8249 tex.src_sel_w = 4;
8250
8251 tex.dst_sel_x = 7;
8252 tex.dst_sel_y = 7;
8253 tex.dst_sel_z = 7;
8254 tex.dst_sel_w = 7;
8255
8256 r = r600_bytecode_add_tex(ctx->bc, &tex);
8257 if (r)
8258 return r;
8259 }
8260
8261 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
8262 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
8263 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
8264 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
8265 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
8266 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
8267 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
8268 switch (opcode) {
8269 case FETCH_OP_SAMPLE:
8270 opcode = FETCH_OP_SAMPLE_C;
8271 break;
8272 case FETCH_OP_SAMPLE_L:
8273 opcode = FETCH_OP_SAMPLE_C_L;
8274 break;
8275 case FETCH_OP_SAMPLE_LB:
8276 opcode = FETCH_OP_SAMPLE_C_LB;
8277 break;
8278 case FETCH_OP_SAMPLE_G:
8279 opcode = FETCH_OP_SAMPLE_C_G;
8280 break;
8281 /* Texture gather variants */
8282 case FETCH_OP_GATHER4:
8283 opcode = FETCH_OP_GATHER4_C;
8284 break;
8285 case FETCH_OP_GATHER4_O:
8286 opcode = FETCH_OP_GATHER4_C_O;
8287 break;
8288 }
8289 }
8290
8291 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8292 tex.op = opcode;
8293
8294 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
8295 tex.sampler_index_mode = sampler_index_mode;
8296 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
8297 tex.resource_index_mode = sampler_index_mode;
8298 tex.src_gpr = src_gpr;
8299 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8300
8301 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
8302 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
8303 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
8304 }
8305
8306 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
8307 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
8308 tex.inst_mod = texture_component_select;
8309
8310 if (ctx->bc->chip_class == CAYMAN) {
8311 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8312 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8313 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8314 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8315 } else {
8316 /* GATHER4 result order is different from TGSI TG4 */
8317 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 1 : 7;
8318 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 2 : 7;
8319 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 0 : 7;
8320 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8321 }
8322 }
8323 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
8324 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8325 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8326 tex.dst_sel_z = 7;
8327 tex.dst_sel_w = 7;
8328 }
8329 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
8330 tex.dst_sel_x = 3;
8331 tex.dst_sel_y = 7;
8332 tex.dst_sel_z = 7;
8333 tex.dst_sel_w = 7;
8334 }
8335 else {
8336 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8337 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8338 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8339 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8340 }
8341
8342
8343 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
8344 tex.src_sel_x = 4;
8345 tex.src_sel_y = 4;
8346 tex.src_sel_z = 4;
8347 tex.src_sel_w = 4;
8348 } else if (src_loaded) {
8349 tex.src_sel_x = 0;
8350 tex.src_sel_y = 1;
8351 tex.src_sel_z = 2;
8352 tex.src_sel_w = 3;
8353 } else {
8354 tex.src_sel_x = ctx->src[0].swizzle[0];
8355 tex.src_sel_y = ctx->src[0].swizzle[1];
8356 tex.src_sel_z = ctx->src[0].swizzle[2];
8357 tex.src_sel_w = ctx->src[0].swizzle[3];
8358 tex.src_rel = ctx->src[0].rel;
8359 }
8360
8361 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
8362 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
8363 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
8364 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
8365 tex.src_sel_x = 1;
8366 tex.src_sel_y = 0;
8367 tex.src_sel_z = 3;
8368 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
8369 }
8370
8371 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
8372 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
8373 tex.coord_type_x = 1;
8374 tex.coord_type_y = 1;
8375 }
8376 tex.coord_type_z = 1;
8377 tex.coord_type_w = 1;
8378
8379 tex.offset_x = offset_x;
8380 tex.offset_y = offset_y;
8381 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
8382 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8383 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
8384 tex.offset_z = 0;
8385 }
8386 else {
8387 tex.offset_z = offset_z;
8388 }
8389
8390 /* Put the depth for comparison in W.
8391 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
8392 * Some instructions expect the depth in Z. */
8393 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
8394 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
8395 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
8396 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
8397 opcode != FETCH_OP_SAMPLE_C_L &&
8398 opcode != FETCH_OP_SAMPLE_C_LB) {
8399 tex.src_sel_w = tex.src_sel_z;
8400 }
8401
8402 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
8403 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
8404 if (opcode == FETCH_OP_SAMPLE_C_L ||
8405 opcode == FETCH_OP_SAMPLE_C_LB) {
8406 /* the array index is read from Y */
8407 tex.coord_type_y = 0;
8408 } else {
8409 /* the array index is read from Z */
8410 tex.coord_type_z = 0;
8411 tex.src_sel_z = tex.src_sel_y;
8412 }
8413 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8414 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
8415 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
8416 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
8417 (ctx->bc->chip_class >= EVERGREEN)))
8418 /* the array index is read from Z */
8419 tex.coord_type_z = 0;
8420
8421 /* mask unused source components */
8422 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
8423 switch (inst->Texture.Texture) {
8424 case TGSI_TEXTURE_2D:
8425 case TGSI_TEXTURE_RECT:
8426 tex.src_sel_z = 7;
8427 tex.src_sel_w = 7;
8428 break;
8429 case TGSI_TEXTURE_1D_ARRAY:
8430 tex.src_sel_y = 7;
8431 tex.src_sel_w = 7;
8432 break;
8433 case TGSI_TEXTURE_1D:
8434 tex.src_sel_y = 7;
8435 tex.src_sel_z = 7;
8436 tex.src_sel_w = 7;
8437 break;
8438 }
8439 }
8440
8441 r = r600_bytecode_add_tex(ctx->bc, &tex);
8442 if (r)
8443 return r;
8444
8445 /* add shadow ambient support - gallium doesn't do it yet */
8446 return 0;
8447 }
8448
8449 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
8450 struct tgsi_full_src_register *src)
8451 {
8452 unsigned i;
8453
8454 if (src->Register.Indirect) {
8455 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
8456 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
8457 return ctx->shader->atomics[i].hw_idx;
8458 }
8459 } else {
8460 uint32_t index = src->Register.Index;
8461 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
8462 if (ctx->shader->atomics[i].buffer_id != (unsigned)src->Dimension.Index)
8463 continue;
8464 if (index > ctx->shader->atomics[i].end)
8465 continue;
8466 if (index < ctx->shader->atomics[i].start)
8467 continue;
8468 uint32_t offset = (index - ctx->shader->atomics[i].start);
8469 return ctx->shader->atomics[i].hw_idx + offset;
8470 }
8471 }
8472 assert(0);
8473 return -1;
8474 }
8475
8476 static int tgsi_set_gds_temp(struct r600_shader_ctx *ctx,
8477 int *uav_id_p, int *uav_index_mode_p)
8478 {
8479 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8480 int uav_id, uav_index_mode = 0;
8481 int r;
8482 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8483
8484 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
8485
8486 if (inst->Src[0].Register.Indirect) {
8487 if (is_cm) {
8488 struct r600_bytecode_alu alu;
8489 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8490 alu.op = ALU_OP2_LSHL_INT;
8491 alu.src[0].sel = get_address_file_reg(ctx, inst->Src[0].Indirect.Index);
8492 alu.src[0].chan = 0;
8493 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8494 alu.src[1].value = 2;
8495 alu.dst.sel = ctx->temp_reg;
8496 alu.dst.chan = 0;
8497 alu.dst.write = 1;
8498 alu.last = 1;
8499 r = r600_bytecode_add_alu(ctx->bc, &alu);
8500 if (r)
8501 return r;
8502
8503 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8504 ctx->temp_reg, 0,
8505 ctx->temp_reg, 0,
8506 V_SQ_ALU_SRC_LITERAL, uav_id * 4);
8507 if (r)
8508 return r;
8509 } else
8510 uav_index_mode = 2;
8511 } else if (is_cm) {
8512 r = single_alu_op2(ctx, ALU_OP1_MOV,
8513 ctx->temp_reg, 0,
8514 V_SQ_ALU_SRC_LITERAL, uav_id * 4,
8515 0, 0);
8516 if (r)
8517 return r;
8518 }
8519 *uav_id_p = uav_id;
8520 *uav_index_mode_p = uav_index_mode;
8521 return 0;
8522 }
8523
8524 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
8525 {
8526 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8527 int r;
8528 struct r600_bytecode_gds gds;
8529 int uav_id = 0;
8530 int uav_index_mode = 0;
8531 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8532
8533 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8534 if (r)
8535 return r;
8536
8537 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8538 gds.op = FETCH_OP_GDS_READ_RET;
8539 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8540 gds.uav_id = is_cm ? 0 : uav_id;
8541 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8542 gds.src_gpr = ctx->temp_reg;
8543 gds.src_sel_x = (is_cm) ? 0 : 4;
8544 gds.src_sel_y = 4;
8545 gds.src_sel_z = 4;
8546 gds.dst_sel_x = 0;
8547 gds.dst_sel_y = 7;
8548 gds.dst_sel_z = 7;
8549 gds.dst_sel_w = 7;
8550 gds.src_gpr2 = 0;
8551 gds.alloc_consume = !is_cm;
8552 r = r600_bytecode_add_gds(ctx->bc, &gds);
8553 if (r)
8554 return r;
8555
8556 ctx->bc->cf_last->vpm = 1;
8557 return 0;
8558 }
8559
8560 /* this fixes up 1D arrays properly */
8561 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
8562 {
8563 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8564 int r, i;
8565 struct r600_bytecode_alu alu;
8566 int temp_reg = r600_get_temp(ctx);
8567
8568 for (i = 0; i < 4; i++) {
8569 bool def_val = true, write_zero = false;
8570 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8571 alu.op = ALU_OP1_MOV;
8572 alu.dst.sel = temp_reg;
8573 alu.dst.chan = i;
8574
8575 switch (inst->Memory.Texture) {
8576 case TGSI_TEXTURE_BUFFER:
8577 case TGSI_TEXTURE_1D:
8578 if (i == 1 || i == 2 || i == 3) {
8579 write_zero = true;
8580 }
8581 break;
8582 case TGSI_TEXTURE_1D_ARRAY:
8583 if (i == 1 || i == 3)
8584 write_zero = true;
8585 else if (i == 2) {
8586 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
8587 def_val = false;
8588 }
8589 break;
8590 case TGSI_TEXTURE_2D:
8591 if (i == 2 || i == 3)
8592 write_zero = true;
8593 break;
8594 default:
8595 if (i == 3)
8596 write_zero = true;
8597 break;
8598 }
8599
8600 if (write_zero) {
8601 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8602 alu.src[0].value = 0;
8603 } else if (def_val) {
8604 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
8605 }
8606
8607 if (i == 3)
8608 alu.last = 1;
8609 alu.dst.write = 1;
8610 r = r600_bytecode_add_alu(ctx->bc, &alu);
8611 if (r)
8612 return r;
8613 }
8614 *idx_gpr = temp_reg;
8615 return 0;
8616 }
8617
8618 static int load_buffer_coord(struct r600_shader_ctx *ctx, int src_idx,
8619 int temp_reg)
8620 {
8621 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8622 int r;
8623 if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
8624 int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
8625 r = single_alu_op2(ctx, ALU_OP1_MOV,
8626 temp_reg, 0,
8627 V_SQ_ALU_SRC_LITERAL, value >> 2,
8628 0, 0);
8629 if (r)
8630 return r;
8631 } else {
8632 struct r600_bytecode_alu alu;
8633 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8634 alu.op = ALU_OP2_LSHR_INT;
8635 r600_bytecode_src(&alu.src[0], &ctx->src[src_idx], 0);
8636 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8637 alu.src[1].value = 2;
8638 alu.dst.sel = temp_reg;
8639 alu.dst.write = 1;
8640 alu.last = 1;
8641 r = r600_bytecode_add_alu(ctx->bc, &alu);
8642 if (r)
8643 return r;
8644 }
8645 return 0;
8646 }
8647
8648 static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
8649 {
8650 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8651 /* have to work out the offset into the RAT immediate return buffer */
8652 struct r600_bytecode_vtx vtx;
8653 struct r600_bytecode_cf *cf;
8654 int r;
8655 int temp_reg = r600_get_temp(ctx);
8656 unsigned rat_index_mode;
8657 unsigned base;
8658
8659 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8660 base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
8661
8662 r = load_buffer_coord(ctx, 1, temp_reg);
8663 if (r)
8664 return r;
8665 ctx->bc->cf_last->barrier = 1;
8666 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8667 vtx.op = FETCH_OP_VFETCH;
8668 vtx.buffer_id = inst->Src[0].Register.Index + base;
8669 vtx.buffer_index_mode = rat_index_mode;
8670 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8671 vtx.src_gpr = temp_reg;
8672 vtx.src_sel_x = 0;
8673 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8674 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
8675 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
8676 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
8677 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
8678 vtx.num_format_all = 1;
8679 vtx.format_comp_all = 1;
8680 vtx.srf_mode_all = 0;
8681
8682 if (inst->Dst[0].Register.WriteMask & 8) {
8683 vtx.data_format = FMT_32_32_32_32;
8684 vtx.use_const_fields = 0;
8685 } else if (inst->Dst[0].Register.WriteMask & 4) {
8686 vtx.data_format = FMT_32_32_32;
8687 vtx.use_const_fields = 0;
8688 } else if (inst->Dst[0].Register.WriteMask & 2) {
8689 vtx.data_format = FMT_32_32;
8690 vtx.use_const_fields = 0;
8691 } else {
8692 vtx.data_format = FMT_32;
8693 vtx.use_const_fields = 0;
8694 }
8695
8696 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8697 if (r)
8698 return r;
8699 cf = ctx->bc->cf_last;
8700 cf->barrier = 1;
8701 return 0;
8702 }
8703
8704 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
8705 {
8706 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8707 /* have to work out the offset into the RAT immediate return buffer */
8708 struct r600_bytecode_vtx vtx;
8709 struct r600_bytecode_cf *cf;
8710 int r;
8711 int idx_gpr;
8712 unsigned format, num_format, format_comp, endian;
8713 const struct util_format_description *desc;
8714 unsigned rat_index_mode;
8715 unsigned immed_base;
8716
8717 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8718
8719 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8720 r = load_index_src(ctx, 1, &idx_gpr);
8721 if (r)
8722 return r;
8723
8724 if (rat_index_mode)
8725 egcm_load_index_reg(ctx->bc, 1, false);
8726
8727 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8728 cf = ctx->bc->cf_last;
8729
8730 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8731 cf->rat.inst = V_RAT_INST_NOP_RTN;
8732 cf->rat.index_mode = rat_index_mode;
8733 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8734 cf->output.gpr = ctx->thread_id_gpr;
8735 cf->output.index_gpr = idx_gpr;
8736 cf->output.comp_mask = 0xf;
8737 cf->output.burst_count = 1;
8738 cf->vpm = 1;
8739 cf->barrier = 1;
8740 cf->mark = 1;
8741 cf->output.elem_size = 0;
8742
8743 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8744 cf = ctx->bc->cf_last;
8745 cf->barrier = 1;
8746
8747 desc = util_format_description(inst->Memory.Format);
8748 r600_vertex_data_type(inst->Memory.Format,
8749 &format, &num_format, &format_comp, &endian);
8750 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8751 vtx.op = FETCH_OP_VFETCH;
8752 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8753 vtx.buffer_index_mode = rat_index_mode;
8754 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8755 vtx.src_gpr = ctx->thread_id_gpr;
8756 vtx.src_sel_x = 1;
8757 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8758 vtx.dst_sel_x = desc->swizzle[0];
8759 vtx.dst_sel_y = desc->swizzle[1];
8760 vtx.dst_sel_z = desc->swizzle[2];
8761 vtx.dst_sel_w = desc->swizzle[3];
8762 vtx.srf_mode_all = 1;
8763 vtx.data_format = format;
8764 vtx.num_format_all = num_format;
8765 vtx.format_comp_all = format_comp;
8766 vtx.endian = endian;
8767 vtx.offset = 0;
8768 vtx.mega_fetch_count = 3;
8769 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8770 if (r)
8771 return r;
8772 cf = ctx->bc->cf_last;
8773 cf->barrier = 1;
8774 return 0;
8775 }
8776
8777 static int tgsi_load_lds(struct r600_shader_ctx *ctx)
8778 {
8779 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8780 struct r600_bytecode_alu alu;
8781 int r;
8782 int temp_reg = r600_get_temp(ctx);
8783
8784 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8785 alu.op = ALU_OP1_MOV;
8786 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8787 alu.dst.sel = temp_reg;
8788 alu.dst.write = 1;
8789 alu.last = 1;
8790 r = r600_bytecode_add_alu(ctx->bc, &alu);
8791 if (r)
8792 return r;
8793
8794 r = do_lds_fetch_values(ctx, temp_reg,
8795 ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
8796 if (r)
8797 return r;
8798 return 0;
8799 }
8800
8801 static int tgsi_load(struct r600_shader_ctx *ctx)
8802 {
8803 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8804 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8805 return tgsi_load_rat(ctx);
8806 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8807 return tgsi_load_gds(ctx);
8808 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8809 return tgsi_load_buffer(ctx);
8810 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8811 return tgsi_load_lds(ctx);
8812 return 0;
8813 }
8814
8815 static int tgsi_store_buffer_rat(struct r600_shader_ctx *ctx)
8816 {
8817 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8818 struct r600_bytecode_cf *cf;
8819 int r, i;
8820 unsigned rat_index_mode;
8821 int lasti;
8822 int temp_reg = r600_get_temp(ctx), treg2 = r600_get_temp(ctx);
8823
8824 r = load_buffer_coord(ctx, 0, treg2);
8825 if (r)
8826 return r;
8827
8828 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8829 if (rat_index_mode)
8830 egcm_load_index_reg(ctx->bc, 1, false);
8831
8832 for (i = 0; i <= 3; i++) {
8833 struct r600_bytecode_alu alu;
8834 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8835 alu.op = ALU_OP1_MOV;
8836 alu.dst.sel = temp_reg;
8837 alu.dst.chan = i;
8838 alu.src[0].sel = V_SQ_ALU_SRC_0;
8839 alu.last = (i == 3);
8840 alu.dst.write = 1;
8841 r = r600_bytecode_add_alu(ctx->bc, &alu);
8842 if (r)
8843 return r;
8844 }
8845
8846 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8847 for (i = 0; i <= lasti; i++) {
8848 struct r600_bytecode_alu alu;
8849 if (!((1 << i) & inst->Dst[0].Register.WriteMask))
8850 continue;
8851
8852 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8853 temp_reg, 0,
8854 treg2, 0,
8855 V_SQ_ALU_SRC_LITERAL, i);
8856 if (r)
8857 return r;
8858
8859 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8860 alu.op = ALU_OP1_MOV;
8861 alu.dst.sel = ctx->temp_reg;
8862 alu.dst.chan = 0;
8863
8864 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8865 alu.last = 1;
8866 alu.dst.write = 1;
8867 r = r600_bytecode_add_alu(ctx->bc, &alu);
8868 if (r)
8869 return r;
8870
8871 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8872 cf = ctx->bc->cf_last;
8873
8874 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index + ctx->info.file_count[TGSI_FILE_IMAGE];
8875 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8876 cf->rat.index_mode = rat_index_mode;
8877 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8878 cf->output.gpr = ctx->temp_reg;
8879 cf->output.index_gpr = temp_reg;
8880 cf->output.comp_mask = 1;
8881 cf->output.burst_count = 1;
8882 cf->vpm = 1;
8883 cf->barrier = 1;
8884 cf->output.elem_size = 0;
8885 }
8886 return 0;
8887 }
8888
8889 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
8890 {
8891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8892 struct r600_bytecode_cf *cf;
8893 bool src_requires_loading = false;
8894 int val_gpr, idx_gpr;
8895 int r, i;
8896 unsigned rat_index_mode;
8897
8898 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8899
8900 r = load_index_src(ctx, 0, &idx_gpr);
8901 if (r)
8902 return r;
8903
8904 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
8905 src_requires_loading = true;
8906
8907 if (src_requires_loading) {
8908 struct r600_bytecode_alu alu;
8909 for (i = 0; i < 4; i++) {
8910 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8911 alu.op = ALU_OP1_MOV;
8912 alu.dst.sel = ctx->temp_reg;
8913 alu.dst.chan = i;
8914
8915 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8916 if (i == 3)
8917 alu.last = 1;
8918 alu.dst.write = 1;
8919 r = r600_bytecode_add_alu(ctx->bc, &alu);
8920 if (r)
8921 return r;
8922 }
8923 val_gpr = ctx->temp_reg;
8924 } else
8925 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
8926 if (rat_index_mode)
8927 egcm_load_index_reg(ctx->bc, 1, false);
8928
8929 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8930 cf = ctx->bc->cf_last;
8931
8932 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
8933 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8934 cf->rat.index_mode = rat_index_mode;
8935 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8936 cf->output.gpr = val_gpr;
8937 cf->output.index_gpr = idx_gpr;
8938 cf->output.comp_mask = 0xf;
8939 cf->output.burst_count = 1;
8940 cf->vpm = 1;
8941 cf->barrier = 1;
8942 cf->output.elem_size = 0;
8943 return 0;
8944 }
8945
8946 static int tgsi_store_lds(struct r600_shader_ctx *ctx)
8947 {
8948 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8949 struct r600_bytecode_alu alu;
8950 int r, i, lasti;
8951 int write_mask = inst->Dst[0].Register.WriteMask;
8952 int temp_reg = r600_get_temp(ctx);
8953
8954 /* LDS write */
8955 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8956 alu.op = ALU_OP1_MOV;
8957 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8958 alu.dst.sel = temp_reg;
8959 alu.dst.write = 1;
8960 alu.last = 1;
8961 r = r600_bytecode_add_alu(ctx->bc, &alu);
8962 if (r)
8963 return r;
8964
8965 lasti = tgsi_last_instruction(write_mask);
8966 for (i = 1; i <= lasti; i++) {
8967 if (!(write_mask & (1 << i)))
8968 continue;
8969 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8970 temp_reg, i,
8971 temp_reg, 0,
8972 V_SQ_ALU_SRC_LITERAL, 4 * i);
8973 if (r)
8974 return r;
8975 }
8976 for (i = 0; i <= lasti; i++) {
8977 if (!(write_mask & (1 << i)))
8978 continue;
8979
8980 if ((i == 0 && ((write_mask & 3) == 3)) ||
8981 (i == 2 && ((write_mask & 0xc) == 0xc))) {
8982 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8983 alu.op = LDS_OP3_LDS_WRITE_REL;
8984
8985 alu.src[0].sel = temp_reg;
8986 alu.src[0].chan = i;
8987 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8988 r600_bytecode_src(&alu.src[2], &ctx->src[1], i + 1);
8989 alu.last = 1;
8990 alu.is_lds_idx_op = true;
8991 alu.lds_idx = 1;
8992 r = r600_bytecode_add_alu(ctx->bc, &alu);
8993 if (r)
8994 return r;
8995 i += 1;
8996 continue;
8997 }
8998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8999 alu.op = LDS_OP2_LDS_WRITE;
9000
9001 alu.src[0].sel = temp_reg;
9002 alu.src[0].chan = i;
9003 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
9004
9005 alu.last = 1;
9006 alu.is_lds_idx_op = true;
9007
9008 r = r600_bytecode_add_alu(ctx->bc, &alu);
9009 if (r)
9010 return r;
9011 }
9012 return 0;
9013 }
9014
9015 static int tgsi_store(struct r600_shader_ctx *ctx)
9016 {
9017 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9018 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
9019 return tgsi_store_buffer_rat(ctx);
9020 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
9021 return tgsi_store_lds(ctx);
9022 else
9023 return tgsi_store_rat(ctx);
9024 }
9025
9026 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
9027 {
9028 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9029 /* have to work out the offset into the RAT immediate return buffer */
9030 struct r600_bytecode_alu alu;
9031 struct r600_bytecode_vtx vtx;
9032 struct r600_bytecode_cf *cf;
9033 int r;
9034 int idx_gpr;
9035 unsigned format, num_format, format_comp, endian;
9036 const struct util_format_description *desc;
9037 unsigned rat_index_mode;
9038 unsigned immed_base;
9039 unsigned rat_base;
9040
9041 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
9042 rat_base = ctx->shader->rat_base;
9043
9044 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
9045 immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
9046 rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
9047
9048 r = load_buffer_coord(ctx, 1, ctx->temp_reg);
9049 if (r)
9050 return r;
9051 idx_gpr = ctx->temp_reg;
9052 } else {
9053 r = load_index_src(ctx, 1, &idx_gpr);
9054 if (r)
9055 return r;
9056 }
9057
9058 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
9059
9060 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
9061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9062 alu.op = ALU_OP1_MOV;
9063 alu.dst.sel = ctx->thread_id_gpr;
9064 alu.dst.chan = 0;
9065 alu.dst.write = 1;
9066 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
9067 alu.last = 1;
9068 r = r600_bytecode_add_alu(ctx->bc, &alu);
9069 if (r)
9070 return r;
9071
9072 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9073 alu.op = ALU_OP1_MOV;
9074 alu.dst.sel = ctx->thread_id_gpr;
9075 if (ctx->bc->chip_class == CAYMAN)
9076 alu.dst.chan = 2;
9077 else
9078 alu.dst.chan = 3;
9079 alu.dst.write = 1;
9080 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
9081 alu.last = 1;
9082 r = r600_bytecode_add_alu(ctx->bc, &alu);
9083 if (r)
9084 return r;
9085 } else {
9086 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9087 alu.op = ALU_OP1_MOV;
9088 alu.dst.sel = ctx->thread_id_gpr;
9089 alu.dst.chan = 0;
9090 alu.dst.write = 1;
9091 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
9092 alu.last = 1;
9093 r = r600_bytecode_add_alu(ctx->bc, &alu);
9094 if (r)
9095 return r;
9096 }
9097
9098 if (rat_index_mode)
9099 egcm_load_index_reg(ctx->bc, 1, false);
9100 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
9101 cf = ctx->bc->cf_last;
9102
9103 cf->rat.id = rat_base + inst->Src[0].Register.Index;
9104 cf->rat.inst = ctx->inst_info->op;
9105 cf->rat.index_mode = rat_index_mode;
9106 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
9107 cf->output.gpr = ctx->thread_id_gpr;
9108 cf->output.index_gpr = idx_gpr;
9109 cf->output.comp_mask = 0xf;
9110 cf->output.burst_count = 1;
9111 cf->vpm = 1;
9112 cf->barrier = 1;
9113 cf->mark = 1;
9114 cf->output.elem_size = 0;
9115 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
9116 cf = ctx->bc->cf_last;
9117 cf->barrier = 1;
9118 cf->cf_addr = 1;
9119
9120 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
9121 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
9122 desc = util_format_description(inst->Memory.Format);
9123 r600_vertex_data_type(inst->Memory.Format,
9124 &format, &num_format, &format_comp, &endian);
9125 vtx.dst_sel_x = desc->swizzle[0];
9126 } else {
9127 format = FMT_32;
9128 num_format = 1;
9129 format_comp = 0;
9130 endian = 0;
9131 vtx.dst_sel_x = 0;
9132 }
9133 vtx.op = FETCH_OP_VFETCH;
9134 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
9135 vtx.buffer_index_mode = rat_index_mode;
9136 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
9137 vtx.src_gpr = ctx->thread_id_gpr;
9138 vtx.src_sel_x = 1;
9139 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9140 vtx.dst_sel_y = 7;
9141 vtx.dst_sel_z = 7;
9142 vtx.dst_sel_w = 7;
9143 vtx.use_const_fields = 0;
9144 vtx.srf_mode_all = 1;
9145 vtx.data_format = format;
9146 vtx.num_format_all = num_format;
9147 vtx.format_comp_all = format_comp;
9148 vtx.endian = endian;
9149 vtx.offset = 0;
9150 vtx.mega_fetch_count = 0xf;
9151 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
9152 if (r)
9153 return r;
9154 cf = ctx->bc->cf_last;
9155 cf->vpm = 1;
9156 cf->barrier = 1;
9157 return 0;
9158 }
9159
9160 static int get_gds_op(int opcode)
9161 {
9162 switch (opcode) {
9163 case TGSI_OPCODE_ATOMUADD:
9164 return FETCH_OP_GDS_ADD_RET;
9165 case TGSI_OPCODE_ATOMAND:
9166 return FETCH_OP_GDS_AND_RET;
9167 case TGSI_OPCODE_ATOMOR:
9168 return FETCH_OP_GDS_OR_RET;
9169 case TGSI_OPCODE_ATOMXOR:
9170 return FETCH_OP_GDS_XOR_RET;
9171 case TGSI_OPCODE_ATOMUMIN:
9172 return FETCH_OP_GDS_MIN_UINT_RET;
9173 case TGSI_OPCODE_ATOMUMAX:
9174 return FETCH_OP_GDS_MAX_UINT_RET;
9175 case TGSI_OPCODE_ATOMXCHG:
9176 return FETCH_OP_GDS_XCHG_RET;
9177 case TGSI_OPCODE_ATOMCAS:
9178 return FETCH_OP_GDS_CMP_XCHG_RET;
9179 default:
9180 return -1;
9181 }
9182 }
9183
9184 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
9185 {
9186 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9187 struct r600_bytecode_gds gds;
9188 struct r600_bytecode_alu alu;
9189 int gds_op = get_gds_op(inst->Instruction.Opcode);
9190 int r;
9191 int uav_id = 0;
9192 int uav_index_mode = 0;
9193 bool is_cm = (ctx->bc->chip_class == CAYMAN);
9194
9195 if (gds_op == -1) {
9196 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
9197 return -1;
9198 }
9199
9200 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
9201 if (r)
9202 return r;
9203
9204 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET) {
9205 if (inst->Src[3].Register.File == TGSI_FILE_IMMEDIATE) {
9206 int value = (ctx->literals[4 * inst->Src[3].Register.Index + inst->Src[3].Register.SwizzleX]);
9207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9208 alu.op = ALU_OP1_MOV;
9209 alu.dst.sel = ctx->temp_reg;
9210 alu.dst.chan = is_cm ? 2 : 1;
9211 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
9212 alu.src[0].value = value;
9213 alu.last = 1;
9214 alu.dst.write = 1;
9215 r = r600_bytecode_add_alu(ctx->bc, &alu);
9216 if (r)
9217 return r;
9218 } else {
9219 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9220 alu.op = ALU_OP1_MOV;
9221 alu.dst.sel = ctx->temp_reg;
9222 alu.dst.chan = is_cm ? 2 : 1;
9223 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
9224 alu.last = 1;
9225 alu.dst.write = 1;
9226 r = r600_bytecode_add_alu(ctx->bc, &alu);
9227 if (r)
9228 return r;
9229 }
9230 }
9231 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
9232 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
9233 int abs_value = abs(value);
9234 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
9235 gds_op = FETCH_OP_GDS_SUB_RET;
9236 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9237 alu.op = ALU_OP1_MOV;
9238 alu.dst.sel = ctx->temp_reg;
9239 alu.dst.chan = is_cm ? 1 : 0;
9240 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
9241 alu.src[0].value = abs_value;
9242 alu.last = 1;
9243 alu.dst.write = 1;
9244 r = r600_bytecode_add_alu(ctx->bc, &alu);
9245 if (r)
9246 return r;
9247 } else {
9248 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9249 alu.op = ALU_OP1_MOV;
9250 alu.dst.sel = ctx->temp_reg;
9251 alu.dst.chan = is_cm ? 1 : 0;
9252 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
9253 alu.last = 1;
9254 alu.dst.write = 1;
9255 r = r600_bytecode_add_alu(ctx->bc, &alu);
9256 if (r)
9257 return r;
9258 }
9259
9260
9261 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
9262 gds.op = gds_op;
9263 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9264 gds.uav_id = is_cm ? 0 : uav_id;
9265 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
9266 gds.src_gpr = ctx->temp_reg;
9267 gds.src_gpr2 = 0;
9268 gds.src_sel_x = is_cm ? 0 : 4;
9269 gds.src_sel_y = is_cm ? 1 : 0;
9270 if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET)
9271 gds.src_sel_z = is_cm ? 2 : 1;
9272 else
9273 gds.src_sel_z = 7;
9274 gds.dst_sel_x = 0;
9275 gds.dst_sel_y = 7;
9276 gds.dst_sel_z = 7;
9277 gds.dst_sel_w = 7;
9278 gds.alloc_consume = !is_cm;
9279
9280 r = r600_bytecode_add_gds(ctx->bc, &gds);
9281 if (r)
9282 return r;
9283 ctx->bc->cf_last->vpm = 1;
9284 return 0;
9285 }
9286
9287 static int get_lds_op(int opcode)
9288 {
9289 switch (opcode) {
9290 case TGSI_OPCODE_ATOMUADD:
9291 return LDS_OP2_LDS_ADD_RET;
9292 case TGSI_OPCODE_ATOMAND:
9293 return LDS_OP2_LDS_AND_RET;
9294 case TGSI_OPCODE_ATOMOR:
9295 return LDS_OP2_LDS_OR_RET;
9296 case TGSI_OPCODE_ATOMXOR:
9297 return LDS_OP2_LDS_XOR_RET;
9298 case TGSI_OPCODE_ATOMUMIN:
9299 return LDS_OP2_LDS_MIN_UINT_RET;
9300 case TGSI_OPCODE_ATOMUMAX:
9301 return LDS_OP2_LDS_MAX_UINT_RET;
9302 case TGSI_OPCODE_ATOMIMIN:
9303 return LDS_OP2_LDS_MIN_INT_RET;
9304 case TGSI_OPCODE_ATOMIMAX:
9305 return LDS_OP2_LDS_MAX_INT_RET;
9306 case TGSI_OPCODE_ATOMXCHG:
9307 return LDS_OP2_LDS_XCHG_RET;
9308 case TGSI_OPCODE_ATOMCAS:
9309 return LDS_OP3_LDS_CMP_XCHG_RET;
9310 default:
9311 return -1;
9312 }
9313 }
9314
9315 static int tgsi_atomic_op_lds(struct r600_shader_ctx *ctx)
9316 {
9317 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9318 int lds_op = get_lds_op(inst->Instruction.Opcode);
9319 int r;
9320
9321 struct r600_bytecode_alu alu;
9322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9323 alu.op = lds_op;
9324 alu.is_lds_idx_op = true;
9325 alu.last = 1;
9326 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
9327 r600_bytecode_src(&alu.src[1], &ctx->src[2], 0);
9328 if (lds_op == LDS_OP3_LDS_CMP_XCHG_RET)
9329 r600_bytecode_src(&alu.src[2], &ctx->src[3], 0);
9330 else
9331 alu.src[2].sel = V_SQ_ALU_SRC_0;
9332 r = r600_bytecode_add_alu(ctx->bc, &alu);
9333 if (r)
9334 return r;
9335
9336 /* then read from LDS_OQ_A_POP */
9337 memset(&alu, 0, sizeof(alu));
9338
9339 alu.op = ALU_OP1_MOV;
9340 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
9341 alu.src[0].chan = 0;
9342 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
9343 alu.dst.write = 1;
9344 alu.last = 1;
9345 r = r600_bytecode_add_alu(ctx->bc, &alu);
9346 if (r)
9347 return r;
9348
9349 return 0;
9350 }
9351
9352 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
9353 {
9354 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9355 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
9356 return tgsi_atomic_op_rat(ctx);
9357 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
9358 return tgsi_atomic_op_gds(ctx);
9359 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
9360 return tgsi_atomic_op_rat(ctx);
9361 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
9362 return tgsi_atomic_op_lds(ctx);
9363 return 0;
9364 }
9365
9366 static int tgsi_resq(struct r600_shader_ctx *ctx)
9367 {
9368 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9369 unsigned sampler_index_mode;
9370 struct r600_bytecode_tex tex;
9371 int r;
9372 boolean has_txq_cube_array_z = false;
9373
9374 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
9375 (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
9376 if (ctx->bc->chip_class < EVERGREEN)
9377 ctx->shader->uses_tex_buffers = true;
9378 unsigned eg_buffer_base = 0;
9379 eg_buffer_base = R600_IMAGE_REAL_RESOURCE_OFFSET;
9380 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
9381 eg_buffer_base += ctx->info.file_count[TGSI_FILE_IMAGE];
9382 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset, eg_buffer_base);
9383 }
9384
9385 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
9386 inst->Dst[0].Register.WriteMask & 4) {
9387 ctx->shader->has_txq_cube_array_z_comp = true;
9388 has_txq_cube_array_z = true;
9389 }
9390
9391 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
9392 if (sampler_index_mode)
9393 egcm_load_index_reg(ctx->bc, 1, false);
9394
9395
9396 /* does this shader want a num layers from TXQ for a cube array? */
9397 if (has_txq_cube_array_z) {
9398 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
9399 struct r600_bytecode_alu alu;
9400
9401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9402 alu.op = ALU_OP1_MOV;
9403
9404 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
9405 /* with eg each dword is either number of cubes */
9406 alu.src[0].sel += id / 4;
9407 alu.src[0].chan = id % 4;
9408 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
9409 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
9410 alu.last = 1;
9411 r = r600_bytecode_add_alu(ctx->bc, &alu);
9412 if (r)
9413 return r;
9414 /* disable writemask from texture instruction */
9415 inst->Dst[0].Register.WriteMask &= ~4;
9416 }
9417 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
9418 tex.op = ctx->inst_info->op;
9419 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
9420 tex.sampler_index_mode = sampler_index_mode;
9421 tex.resource_id = tex.sampler_id;
9422 tex.resource_index_mode = sampler_index_mode;
9423 tex.src_sel_x = 4;
9424 tex.src_sel_y = 4;
9425 tex.src_sel_z = 4;
9426 tex.src_sel_w = 4;
9427 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
9428 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
9429 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
9430 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
9431 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9432 r = r600_bytecode_add_tex(ctx->bc, &tex);
9433 if (r)
9434 return r;
9435
9436 return 0;
9437 }
9438
9439 static int tgsi_lrp(struct r600_shader_ctx *ctx)
9440 {
9441 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9442 struct r600_bytecode_alu alu;
9443 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9444 struct r600_bytecode_alu_src srcs[2][4];
9445 unsigned i;
9446 int r;
9447
9448 /* optimize if it's just an equal balance */
9449 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
9450 for (i = 0; i < lasti + 1; i++) {
9451 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9452 continue;
9453
9454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9455 alu.op = ALU_OP2_ADD;
9456 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
9457 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9458 alu.omod = 3;
9459 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9460 alu.dst.chan = i;
9461 if (i == lasti) {
9462 alu.last = 1;
9463 }
9464 r = r600_bytecode_add_alu(ctx->bc, &alu);
9465 if (r)
9466 return r;
9467 }
9468 return 0;
9469 }
9470
9471 /* 1 - src0 */
9472 for (i = 0; i < lasti + 1; i++) {
9473 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9474 continue;
9475
9476 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9477 alu.op = ALU_OP2_ADD;
9478 alu.src[0].sel = V_SQ_ALU_SRC_1;
9479 alu.src[0].chan = 0;
9480 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
9481 r600_bytecode_src_toggle_neg(&alu.src[1]);
9482 alu.dst.sel = ctx->temp_reg;
9483 alu.dst.chan = i;
9484 if (i == lasti) {
9485 alu.last = 1;
9486 }
9487 alu.dst.write = 1;
9488 r = r600_bytecode_add_alu(ctx->bc, &alu);
9489 if (r)
9490 return r;
9491 }
9492
9493 /* (1 - src0) * src2 */
9494 for (i = 0; i < lasti + 1; i++) {
9495 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9496 continue;
9497
9498 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9499 alu.op = ALU_OP2_MUL;
9500 alu.src[0].sel = ctx->temp_reg;
9501 alu.src[0].chan = i;
9502 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9503 alu.dst.sel = ctx->temp_reg;
9504 alu.dst.chan = i;
9505 if (i == lasti) {
9506 alu.last = 1;
9507 }
9508 alu.dst.write = 1;
9509 r = r600_bytecode_add_alu(ctx->bc, &alu);
9510 if (r)
9511 return r;
9512 }
9513
9514 /* src0 * src1 + (1 - src0) * src2 */
9515
9516 for (i = 0; i < 2; i++) {
9517 r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
9518 srcs[i], &ctx->src[i]);
9519 if (r)
9520 return r;
9521 }
9522
9523 for (i = 0; i < lasti + 1; i++) {
9524 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9525 continue;
9526
9527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9528 alu.op = ALU_OP3_MULADD;
9529 alu.is_op3 = 1;
9530 alu.src[0] = srcs[0][i];
9531 alu.src[1] = srcs[1][i];
9532 alu.src[2].sel = ctx->temp_reg;
9533 alu.src[2].chan = i;
9534
9535 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9536 alu.dst.chan = i;
9537 if (i == lasti) {
9538 alu.last = 1;
9539 }
9540 r = r600_bytecode_add_alu(ctx->bc, &alu);
9541 if (r)
9542 return r;
9543 }
9544 return 0;
9545 }
9546
9547 static int tgsi_cmp(struct r600_shader_ctx *ctx)
9548 {
9549 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9550 struct r600_bytecode_alu alu;
9551 int i, r, j;
9552 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9553 struct r600_bytecode_alu_src srcs[3][4];
9554
9555 unsigned op;
9556
9557 if (ctx->src[0].abs && ctx->src[0].neg) {
9558 op = ALU_OP3_CNDE;
9559 ctx->src[0].abs = 0;
9560 ctx->src[0].neg = 0;
9561 } else {
9562 op = ALU_OP3_CNDGE;
9563 }
9564
9565 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
9566 r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
9567 srcs[j], &ctx->src[j]);
9568 if (r)
9569 return r;
9570 }
9571
9572 for (i = 0; i < lasti + 1; i++) {
9573 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9574 continue;
9575
9576 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9577 alu.op = op;
9578 alu.src[0] = srcs[0][i];
9579 alu.src[1] = srcs[2][i];
9580 alu.src[2] = srcs[1][i];
9581
9582 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9583 alu.dst.chan = i;
9584 alu.dst.write = 1;
9585 alu.is_op3 = 1;
9586 if (i == lasti)
9587 alu.last = 1;
9588 r = r600_bytecode_add_alu(ctx->bc, &alu);
9589 if (r)
9590 return r;
9591 }
9592 return 0;
9593 }
9594
9595 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
9596 {
9597 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9598 struct r600_bytecode_alu alu;
9599 int i, r;
9600 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9601
9602 for (i = 0; i < lasti + 1; i++) {
9603 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9604 continue;
9605
9606 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9607 alu.op = ALU_OP3_CNDE_INT;
9608 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9609 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9610 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
9611 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9612 alu.dst.chan = i;
9613 alu.dst.write = 1;
9614 alu.is_op3 = 1;
9615 if (i == lasti)
9616 alu.last = 1;
9617 r = r600_bytecode_add_alu(ctx->bc, &alu);
9618 if (r)
9619 return r;
9620 }
9621 return 0;
9622 }
9623
9624 static int tgsi_exp(struct r600_shader_ctx *ctx)
9625 {
9626 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9627 struct r600_bytecode_alu alu;
9628 int r;
9629 unsigned i;
9630
9631 /* result.x = 2^floor(src); */
9632 if (inst->Dst[0].Register.WriteMask & 1) {
9633 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9634
9635 alu.op = ALU_OP1_FLOOR;
9636 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9637
9638 alu.dst.sel = ctx->temp_reg;
9639 alu.dst.chan = 0;
9640 alu.dst.write = 1;
9641 alu.last = 1;
9642 r = r600_bytecode_add_alu(ctx->bc, &alu);
9643 if (r)
9644 return r;
9645
9646 if (ctx->bc->chip_class == CAYMAN) {
9647 for (i = 0; i < 3; i++) {
9648 alu.op = ALU_OP1_EXP_IEEE;
9649 alu.src[0].sel = ctx->temp_reg;
9650 alu.src[0].chan = 0;
9651
9652 alu.dst.sel = ctx->temp_reg;
9653 alu.dst.chan = i;
9654 alu.dst.write = i == 0;
9655 alu.last = i == 2;
9656 r = r600_bytecode_add_alu(ctx->bc, &alu);
9657 if (r)
9658 return r;
9659 }
9660 } else {
9661 alu.op = ALU_OP1_EXP_IEEE;
9662 alu.src[0].sel = ctx->temp_reg;
9663 alu.src[0].chan = 0;
9664
9665 alu.dst.sel = ctx->temp_reg;
9666 alu.dst.chan = 0;
9667 alu.dst.write = 1;
9668 alu.last = 1;
9669 r = r600_bytecode_add_alu(ctx->bc, &alu);
9670 if (r)
9671 return r;
9672 }
9673 }
9674
9675 /* result.y = tmp - floor(tmp); */
9676 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9677 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9678
9679 alu.op = ALU_OP1_FRACT;
9680 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9681
9682 alu.dst.sel = ctx->temp_reg;
9683 #if 0
9684 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9685 if (r)
9686 return r;
9687 #endif
9688 alu.dst.write = 1;
9689 alu.dst.chan = 1;
9690
9691 alu.last = 1;
9692
9693 r = r600_bytecode_add_alu(ctx->bc, &alu);
9694 if (r)
9695 return r;
9696 }
9697
9698 /* result.z = RoughApprox2ToX(tmp);*/
9699 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
9700 if (ctx->bc->chip_class == CAYMAN) {
9701 for (i = 0; i < 3; i++) {
9702 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9703 alu.op = ALU_OP1_EXP_IEEE;
9704 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9705
9706 alu.dst.sel = ctx->temp_reg;
9707 alu.dst.chan = i;
9708 if (i == 2) {
9709 alu.dst.write = 1;
9710 alu.last = 1;
9711 }
9712
9713 r = r600_bytecode_add_alu(ctx->bc, &alu);
9714 if (r)
9715 return r;
9716 }
9717 } else {
9718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9719 alu.op = ALU_OP1_EXP_IEEE;
9720 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9721
9722 alu.dst.sel = ctx->temp_reg;
9723 alu.dst.write = 1;
9724 alu.dst.chan = 2;
9725
9726 alu.last = 1;
9727
9728 r = r600_bytecode_add_alu(ctx->bc, &alu);
9729 if (r)
9730 return r;
9731 }
9732 }
9733
9734 /* result.w = 1.0;*/
9735 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
9736 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9737
9738 alu.op = ALU_OP1_MOV;
9739 alu.src[0].sel = V_SQ_ALU_SRC_1;
9740 alu.src[0].chan = 0;
9741
9742 alu.dst.sel = ctx->temp_reg;
9743 alu.dst.chan = 3;
9744 alu.dst.write = 1;
9745 alu.last = 1;
9746 r = r600_bytecode_add_alu(ctx->bc, &alu);
9747 if (r)
9748 return r;
9749 }
9750 return tgsi_helper_copy(ctx, inst);
9751 }
9752
9753 static int tgsi_log(struct r600_shader_ctx *ctx)
9754 {
9755 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9756 struct r600_bytecode_alu alu;
9757 int r;
9758 unsigned i;
9759
9760 /* result.x = floor(log2(|src|)); */
9761 if (inst->Dst[0].Register.WriteMask & 1) {
9762 if (ctx->bc->chip_class == CAYMAN) {
9763 for (i = 0; i < 3; i++) {
9764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9765
9766 alu.op = ALU_OP1_LOG_IEEE;
9767 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9768 r600_bytecode_src_set_abs(&alu.src[0]);
9769
9770 alu.dst.sel = ctx->temp_reg;
9771 alu.dst.chan = i;
9772 if (i == 0)
9773 alu.dst.write = 1;
9774 if (i == 2)
9775 alu.last = 1;
9776 r = r600_bytecode_add_alu(ctx->bc, &alu);
9777 if (r)
9778 return r;
9779 }
9780
9781 } else {
9782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9783
9784 alu.op = ALU_OP1_LOG_IEEE;
9785 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9786 r600_bytecode_src_set_abs(&alu.src[0]);
9787
9788 alu.dst.sel = ctx->temp_reg;
9789 alu.dst.chan = 0;
9790 alu.dst.write = 1;
9791 alu.last = 1;
9792 r = r600_bytecode_add_alu(ctx->bc, &alu);
9793 if (r)
9794 return r;
9795 }
9796
9797 alu.op = ALU_OP1_FLOOR;
9798 alu.src[0].sel = ctx->temp_reg;
9799 alu.src[0].chan = 0;
9800
9801 alu.dst.sel = ctx->temp_reg;
9802 alu.dst.chan = 0;
9803 alu.dst.write = 1;
9804 alu.last = 1;
9805
9806 r = r600_bytecode_add_alu(ctx->bc, &alu);
9807 if (r)
9808 return r;
9809 }
9810
9811 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
9812 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9813
9814 if (ctx->bc->chip_class == CAYMAN) {
9815 for (i = 0; i < 3; i++) {
9816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9817
9818 alu.op = ALU_OP1_LOG_IEEE;
9819 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9820 r600_bytecode_src_set_abs(&alu.src[0]);
9821
9822 alu.dst.sel = ctx->temp_reg;
9823 alu.dst.chan = i;
9824 if (i == 1)
9825 alu.dst.write = 1;
9826 if (i == 2)
9827 alu.last = 1;
9828
9829 r = r600_bytecode_add_alu(ctx->bc, &alu);
9830 if (r)
9831 return r;
9832 }
9833 } else {
9834 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9835
9836 alu.op = ALU_OP1_LOG_IEEE;
9837 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9838 r600_bytecode_src_set_abs(&alu.src[0]);
9839
9840 alu.dst.sel = ctx->temp_reg;
9841 alu.dst.chan = 1;
9842 alu.dst.write = 1;
9843 alu.last = 1;
9844
9845 r = r600_bytecode_add_alu(ctx->bc, &alu);
9846 if (r)
9847 return r;
9848 }
9849
9850 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9851
9852 alu.op = ALU_OP1_FLOOR;
9853 alu.src[0].sel = ctx->temp_reg;
9854 alu.src[0].chan = 1;
9855
9856 alu.dst.sel = ctx->temp_reg;
9857 alu.dst.chan = 1;
9858 alu.dst.write = 1;
9859 alu.last = 1;
9860
9861 r = r600_bytecode_add_alu(ctx->bc, &alu);
9862 if (r)
9863 return r;
9864
9865 if (ctx->bc->chip_class == CAYMAN) {
9866 for (i = 0; i < 3; i++) {
9867 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9868 alu.op = ALU_OP1_EXP_IEEE;
9869 alu.src[0].sel = ctx->temp_reg;
9870 alu.src[0].chan = 1;
9871
9872 alu.dst.sel = ctx->temp_reg;
9873 alu.dst.chan = i;
9874 if (i == 1)
9875 alu.dst.write = 1;
9876 if (i == 2)
9877 alu.last = 1;
9878
9879 r = r600_bytecode_add_alu(ctx->bc, &alu);
9880 if (r)
9881 return r;
9882 }
9883 } else {
9884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9885 alu.op = ALU_OP1_EXP_IEEE;
9886 alu.src[0].sel = ctx->temp_reg;
9887 alu.src[0].chan = 1;
9888
9889 alu.dst.sel = ctx->temp_reg;
9890 alu.dst.chan = 1;
9891 alu.dst.write = 1;
9892 alu.last = 1;
9893
9894 r = r600_bytecode_add_alu(ctx->bc, &alu);
9895 if (r)
9896 return r;
9897 }
9898
9899 if (ctx->bc->chip_class == CAYMAN) {
9900 for (i = 0; i < 3; i++) {
9901 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9902 alu.op = ALU_OP1_RECIP_IEEE;
9903 alu.src[0].sel = ctx->temp_reg;
9904 alu.src[0].chan = 1;
9905
9906 alu.dst.sel = ctx->temp_reg;
9907 alu.dst.chan = i;
9908 if (i == 1)
9909 alu.dst.write = 1;
9910 if (i == 2)
9911 alu.last = 1;
9912
9913 r = r600_bytecode_add_alu(ctx->bc, &alu);
9914 if (r)
9915 return r;
9916 }
9917 } else {
9918 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9919 alu.op = ALU_OP1_RECIP_IEEE;
9920 alu.src[0].sel = ctx->temp_reg;
9921 alu.src[0].chan = 1;
9922
9923 alu.dst.sel = ctx->temp_reg;
9924 alu.dst.chan = 1;
9925 alu.dst.write = 1;
9926 alu.last = 1;
9927
9928 r = r600_bytecode_add_alu(ctx->bc, &alu);
9929 if (r)
9930 return r;
9931 }
9932
9933 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9934
9935 alu.op = ALU_OP2_MUL;
9936
9937 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9938 r600_bytecode_src_set_abs(&alu.src[0]);
9939
9940 alu.src[1].sel = ctx->temp_reg;
9941 alu.src[1].chan = 1;
9942
9943 alu.dst.sel = ctx->temp_reg;
9944 alu.dst.chan = 1;
9945 alu.dst.write = 1;
9946 alu.last = 1;
9947
9948 r = r600_bytecode_add_alu(ctx->bc, &alu);
9949 if (r)
9950 return r;
9951 }
9952
9953 /* result.z = log2(|src|);*/
9954 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
9955 if (ctx->bc->chip_class == CAYMAN) {
9956 for (i = 0; i < 3; i++) {
9957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9958
9959 alu.op = ALU_OP1_LOG_IEEE;
9960 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9961 r600_bytecode_src_set_abs(&alu.src[0]);
9962
9963 alu.dst.sel = ctx->temp_reg;
9964 if (i == 2)
9965 alu.dst.write = 1;
9966 alu.dst.chan = i;
9967 if (i == 2)
9968 alu.last = 1;
9969
9970 r = r600_bytecode_add_alu(ctx->bc, &alu);
9971 if (r)
9972 return r;
9973 }
9974 } else {
9975 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9976
9977 alu.op = ALU_OP1_LOG_IEEE;
9978 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9979 r600_bytecode_src_set_abs(&alu.src[0]);
9980
9981 alu.dst.sel = ctx->temp_reg;
9982 alu.dst.write = 1;
9983 alu.dst.chan = 2;
9984 alu.last = 1;
9985
9986 r = r600_bytecode_add_alu(ctx->bc, &alu);
9987 if (r)
9988 return r;
9989 }
9990 }
9991
9992 /* result.w = 1.0; */
9993 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
9994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9995
9996 alu.op = ALU_OP1_MOV;
9997 alu.src[0].sel = V_SQ_ALU_SRC_1;
9998 alu.src[0].chan = 0;
9999
10000 alu.dst.sel = ctx->temp_reg;
10001 alu.dst.chan = 3;
10002 alu.dst.write = 1;
10003 alu.last = 1;
10004
10005 r = r600_bytecode_add_alu(ctx->bc, &alu);
10006 if (r)
10007 return r;
10008 }
10009
10010 return tgsi_helper_copy(ctx, inst);
10011 }
10012
10013 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
10014 {
10015 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10016 struct r600_bytecode_alu alu;
10017 int r;
10018 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10019 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
10020
10021 assert(inst->Dst[0].Register.Index < 3);
10022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10023
10024 switch (inst->Instruction.Opcode) {
10025 case TGSI_OPCODE_ARL:
10026 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
10027 break;
10028 case TGSI_OPCODE_ARR:
10029 alu.op = ALU_OP1_FLT_TO_INT;
10030 break;
10031 case TGSI_OPCODE_UARL:
10032 alu.op = ALU_OP1_MOV;
10033 break;
10034 default:
10035 assert(0);
10036 return -1;
10037 }
10038
10039 for (i = 0; i <= lasti; ++i) {
10040 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10041 continue;
10042 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10043 alu.last = i == lasti;
10044 alu.dst.sel = reg;
10045 alu.dst.chan = i;
10046 alu.dst.write = 1;
10047 r = r600_bytecode_add_alu(ctx->bc, &alu);
10048 if (r)
10049 return r;
10050 }
10051
10052 if (inst->Dst[0].Register.Index > 0)
10053 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
10054 else
10055 ctx->bc->ar_loaded = 0;
10056
10057 return 0;
10058 }
10059 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
10060 {
10061 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10062 struct r600_bytecode_alu alu;
10063 int r;
10064 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10065
10066 switch (inst->Instruction.Opcode) {
10067 case TGSI_OPCODE_ARL:
10068 memset(&alu, 0, sizeof(alu));
10069 alu.op = ALU_OP1_FLOOR;
10070 alu.dst.sel = ctx->bc->ar_reg;
10071 alu.dst.write = 1;
10072 for (i = 0; i <= lasti; ++i) {
10073 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10074 alu.dst.chan = i;
10075 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10076 alu.last = i == lasti;
10077 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10078 return r;
10079 }
10080 }
10081
10082 memset(&alu, 0, sizeof(alu));
10083 alu.op = ALU_OP1_FLT_TO_INT;
10084 alu.src[0].sel = ctx->bc->ar_reg;
10085 alu.dst.sel = ctx->bc->ar_reg;
10086 alu.dst.write = 1;
10087 /* FLT_TO_INT is trans-only on r600/r700 */
10088 alu.last = TRUE;
10089 for (i = 0; i <= lasti; ++i) {
10090 alu.dst.chan = i;
10091 alu.src[0].chan = i;
10092 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10093 return r;
10094 }
10095 break;
10096 case TGSI_OPCODE_ARR:
10097 memset(&alu, 0, sizeof(alu));
10098 alu.op = ALU_OP1_FLT_TO_INT;
10099 alu.dst.sel = ctx->bc->ar_reg;
10100 alu.dst.write = 1;
10101 /* FLT_TO_INT is trans-only on r600/r700 */
10102 alu.last = TRUE;
10103 for (i = 0; i <= lasti; ++i) {
10104 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10105 alu.dst.chan = i;
10106 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10107 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10108 return r;
10109 }
10110 }
10111 break;
10112 case TGSI_OPCODE_UARL:
10113 memset(&alu, 0, sizeof(alu));
10114 alu.op = ALU_OP1_MOV;
10115 alu.dst.sel = ctx->bc->ar_reg;
10116 alu.dst.write = 1;
10117 for (i = 0; i <= lasti; ++i) {
10118 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10119 alu.dst.chan = i;
10120 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10121 alu.last = i == lasti;
10122 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
10123 return r;
10124 }
10125 }
10126 break;
10127 default:
10128 assert(0);
10129 return -1;
10130 }
10131
10132 ctx->bc->ar_loaded = 0;
10133 return 0;
10134 }
10135
10136 static int tgsi_opdst(struct r600_shader_ctx *ctx)
10137 {
10138 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10139 struct r600_bytecode_alu alu;
10140 int i, r = 0;
10141
10142 for (i = 0; i < 4; i++) {
10143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10144
10145 alu.op = ALU_OP2_MUL;
10146 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10147
10148 if (i == 0 || i == 3) {
10149 alu.src[0].sel = V_SQ_ALU_SRC_1;
10150 } else {
10151 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
10152 }
10153
10154 if (i == 0 || i == 2) {
10155 alu.src[1].sel = V_SQ_ALU_SRC_1;
10156 } else {
10157 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
10158 }
10159 if (i == 3)
10160 alu.last = 1;
10161 r = r600_bytecode_add_alu(ctx->bc, &alu);
10162 if (r)
10163 return r;
10164 }
10165 return 0;
10166 }
10167
10168 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type,
10169 struct r600_bytecode_alu_src *src)
10170 {
10171 struct r600_bytecode_alu alu;
10172 int r;
10173
10174 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10175 alu.op = opcode;
10176 alu.execute_mask = 1;
10177 alu.update_pred = 1;
10178
10179 alu.dst.sel = ctx->temp_reg;
10180 alu.dst.write = 1;
10181 alu.dst.chan = 0;
10182
10183 alu.src[0] = *src;
10184 alu.src[1].sel = V_SQ_ALU_SRC_0;
10185 alu.src[1].chan = 0;
10186
10187 alu.last = 1;
10188
10189 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
10190 if (r)
10191 return r;
10192 return 0;
10193 }
10194
10195 static int pops(struct r600_shader_ctx *ctx, int pops)
10196 {
10197 unsigned force_pop = ctx->bc->force_add_cf;
10198
10199 if (!force_pop) {
10200 int alu_pop = 3;
10201 if (ctx->bc->cf_last) {
10202 if (ctx->bc->cf_last->op == CF_OP_ALU)
10203 alu_pop = 0;
10204 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
10205 alu_pop = 1;
10206 }
10207 alu_pop += pops;
10208 if (alu_pop == 1) {
10209 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
10210 ctx->bc->force_add_cf = 1;
10211 } else if (alu_pop == 2) {
10212 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
10213 ctx->bc->force_add_cf = 1;
10214 } else {
10215 force_pop = 1;
10216 }
10217 }
10218
10219 if (force_pop) {
10220 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
10221 ctx->bc->cf_last->pop_count = pops;
10222 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
10223 }
10224
10225 return 0;
10226 }
10227
10228 static inline int callstack_update_max_depth(struct r600_shader_ctx *ctx,
10229 unsigned reason)
10230 {
10231 struct r600_stack_info *stack = &ctx->bc->stack;
10232 unsigned elements;
10233 int entries;
10234
10235 unsigned entry_size = stack->entry_size;
10236
10237 elements = (stack->loop + stack->push_wqm ) * entry_size;
10238 elements += stack->push;
10239
10240 switch (ctx->bc->chip_class) {
10241 case R600:
10242 case R700:
10243 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
10244 * the stack must be reserved to hold the current active/continue
10245 * masks */
10246 if (reason == FC_PUSH_VPM || stack->push > 0) {
10247 elements += 2;
10248 }
10249 break;
10250
10251 case CAYMAN:
10252 /* r9xx: any stack operation on empty stack consumes 2 additional
10253 * elements */
10254 elements += 2;
10255
10256 /* fallthrough */
10257 /* FIXME: do the two elements added above cover the cases for the
10258 * r8xx+ below? */
10259
10260 case EVERGREEN:
10261 /* r8xx+: 2 extra elements are not always required, but one extra
10262 * element must be added for each of the following cases:
10263 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
10264 * stack usage.
10265 * (Currently we don't use ALU_ELSE_AFTER.)
10266 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
10267 * PUSH instruction executed.
10268 *
10269 * NOTE: it seems we also need to reserve additional element in some
10270 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
10271 * then STACK_SIZE should be 2 instead of 1 */
10272 if (reason == FC_PUSH_VPM || stack->push > 0) {
10273 elements += 1;
10274 }
10275 break;
10276
10277 default:
10278 assert(0);
10279 break;
10280 }
10281
10282 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
10283 * for all chips, so we use 4 in the final formula, not the real entry_size
10284 * for the chip */
10285 entry_size = 4;
10286
10287 entries = (elements + (entry_size - 1)) / entry_size;
10288
10289 if (entries > stack->max_entries)
10290 stack->max_entries = entries;
10291 return elements;
10292 }
10293
10294 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
10295 {
10296 switch(reason) {
10297 case FC_PUSH_VPM:
10298 --ctx->bc->stack.push;
10299 assert(ctx->bc->stack.push >= 0);
10300 break;
10301 case FC_PUSH_WQM:
10302 --ctx->bc->stack.push_wqm;
10303 assert(ctx->bc->stack.push_wqm >= 0);
10304 break;
10305 case FC_LOOP:
10306 --ctx->bc->stack.loop;
10307 assert(ctx->bc->stack.loop >= 0);
10308 break;
10309 default:
10310 assert(0);
10311 break;
10312 }
10313 }
10314
10315 static inline int callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
10316 {
10317 switch (reason) {
10318 case FC_PUSH_VPM:
10319 ++ctx->bc->stack.push;
10320 break;
10321 case FC_PUSH_WQM:
10322 ++ctx->bc->stack.push_wqm;
10323 break;
10324 case FC_LOOP:
10325 ++ctx->bc->stack.loop;
10326 break;
10327 default:
10328 assert(0);
10329 }
10330
10331 return callstack_update_max_depth(ctx, reason);
10332 }
10333
10334 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
10335 {
10336 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
10337
10338 sp->mid = realloc((void *)sp->mid,
10339 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
10340 sp->mid[sp->num_mid] = ctx->bc->cf_last;
10341 sp->num_mid++;
10342 }
10343
10344 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
10345 {
10346 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
10347 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
10348 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
10349 ctx->bc->fc_sp++;
10350 }
10351
10352 static void fc_poplevel(struct r600_shader_ctx *ctx)
10353 {
10354 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
10355 free(sp->mid);
10356 sp->mid = NULL;
10357 sp->num_mid = 0;
10358 sp->start = NULL;
10359 sp->type = 0;
10360 ctx->bc->fc_sp--;
10361 }
10362
10363 #if 0
10364 static int emit_return(struct r600_shader_ctx *ctx)
10365 {
10366 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
10367 return 0;
10368 }
10369
10370 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
10371 {
10372
10373 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
10374 ctx->bc->cf_last->pop_count = pops;
10375 /* XXX work out offset */
10376 return 0;
10377 }
10378
10379 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
10380 {
10381 return 0;
10382 }
10383
10384 static void emit_testflag(struct r600_shader_ctx *ctx)
10385 {
10386
10387 }
10388
10389 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
10390 {
10391 emit_testflag(ctx);
10392 emit_jump_to_offset(ctx, 1, 4);
10393 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
10394 pops(ctx, ifidx + 1);
10395 emit_return(ctx);
10396 }
10397
10398 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
10399 {
10400 emit_testflag(ctx);
10401
10402 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10403 ctx->bc->cf_last->pop_count = 1;
10404
10405 fc_set_mid(ctx, fc_sp);
10406
10407 pops(ctx, 1);
10408 }
10409 #endif
10410
10411 static int emit_if(struct r600_shader_ctx *ctx, int opcode,
10412 struct r600_bytecode_alu_src *src)
10413 {
10414 int alu_type = CF_OP_ALU_PUSH_BEFORE;
10415 bool needs_workaround = false;
10416 int elems = callstack_push(ctx, FC_PUSH_VPM);
10417
10418 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1)
10419 needs_workaround = true;
10420
10421 if (ctx->bc->chip_class == EVERGREEN && ctx_needs_stack_workaround_8xx(ctx)) {
10422 unsigned dmod1 = (elems - 1) % ctx->bc->stack.entry_size;
10423 unsigned dmod2 = (elems) % ctx->bc->stack.entry_size;
10424
10425 if (elems && (!dmod1 || !dmod2))
10426 needs_workaround = true;
10427 }
10428
10429 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
10430 * LOOP_STARTxxx for nested loops may put the branch stack into a state
10431 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
10432 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
10433 if (needs_workaround) {
10434 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
10435 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
10436 alu_type = CF_OP_ALU;
10437 }
10438
10439 emit_logic_pred(ctx, opcode, alu_type, src);
10440
10441 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
10442
10443 fc_pushlevel(ctx, FC_IF);
10444
10445 return 0;
10446 }
10447
10448 static int tgsi_if(struct r600_shader_ctx *ctx)
10449 {
10450 struct r600_bytecode_alu_src alu_src;
10451 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
10452
10453 return emit_if(ctx, ALU_OP2_PRED_SETNE, &alu_src);
10454 }
10455
10456 static int tgsi_uif(struct r600_shader_ctx *ctx)
10457 {
10458 struct r600_bytecode_alu_src alu_src;
10459 r600_bytecode_src(&alu_src, &ctx->src[0], 0);
10460 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
10461 }
10462
10463 static int tgsi_else(struct r600_shader_ctx *ctx)
10464 {
10465 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
10466 ctx->bc->cf_last->pop_count = 1;
10467
10468 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
10469 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
10470 return 0;
10471 }
10472
10473 static int tgsi_endif(struct r600_shader_ctx *ctx)
10474 {
10475 int offset = 2;
10476 pops(ctx, 1);
10477 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
10478 R600_ERR("if/endif unbalanced in shader\n");
10479 return -1;
10480 }
10481
10482 /* ALU_EXTENDED needs 4 DWords instead of two, adjust jump target offset accordingly */
10483 if (ctx->bc->cf_last->eg_alu_extended)
10484 offset += 2;
10485
10486 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
10487 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + offset;
10488 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
10489 } else {
10490 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + offset;
10491 }
10492 fc_poplevel(ctx);
10493
10494 callstack_pop(ctx, FC_PUSH_VPM);
10495 return 0;
10496 }
10497
10498 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
10499 {
10500 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
10501 * limited to 4096 iterations, like the other LOOP_* instructions. */
10502 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
10503
10504 fc_pushlevel(ctx, FC_LOOP);
10505
10506 /* check stack depth */
10507 callstack_push(ctx, FC_LOOP);
10508 return 0;
10509 }
10510
10511 static int tgsi_endloop(struct r600_shader_ctx *ctx)
10512 {
10513 int i;
10514
10515 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
10516
10517 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
10518 R600_ERR("loop/endloop in shader code are not paired.\n");
10519 return -EINVAL;
10520 }
10521
10522 /* fixup loop pointers - from r600isa
10523 LOOP END points to CF after LOOP START,
10524 LOOP START point to CF after LOOP END
10525 BRK/CONT point to LOOP END CF
10526 */
10527 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
10528
10529 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
10530
10531 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
10532 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
10533 }
10534 /* XXX add LOOPRET support */
10535 fc_poplevel(ctx);
10536 callstack_pop(ctx, FC_LOOP);
10537 return 0;
10538 }
10539
10540 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
10541 {
10542 unsigned int fscp;
10543
10544 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
10545 {
10546 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
10547 break;
10548 }
10549
10550 if (fscp == 0) {
10551 R600_ERR("Break not inside loop/endloop pair\n");
10552 return -EINVAL;
10553 }
10554
10555 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10556
10557 fc_set_mid(ctx, fscp - 1);
10558
10559 return 0;
10560 }
10561
10562 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
10563 {
10564 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10565 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
10566 int r;
10567
10568 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10569 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
10570
10571 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
10572 if (!r) {
10573 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
10574 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
10575 return emit_inc_ring_offset(ctx, stream, TRUE);
10576 }
10577 return r;
10578 }
10579
10580 static int tgsi_umad(struct r600_shader_ctx *ctx)
10581 {
10582 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10583 struct r600_bytecode_alu alu;
10584 int i, j, r;
10585 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10586
10587 /* src0 * src1 */
10588 for (i = 0; i < lasti + 1; i++) {
10589 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10590 continue;
10591
10592 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10593
10594 alu.dst.chan = i;
10595 alu.dst.sel = ctx->temp_reg;
10596 alu.dst.write = 1;
10597
10598 alu.op = ALU_OP2_MULLO_UINT;
10599 for (j = 0; j < 2; j++) {
10600 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
10601 }
10602
10603 alu.last = 1;
10604 r = emit_mul_int_op(ctx->bc, &alu);
10605 if (r)
10606 return r;
10607 }
10608
10609
10610 for (i = 0; i < lasti + 1; i++) {
10611 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10612 continue;
10613
10614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10615 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10616
10617 alu.op = ALU_OP2_ADD_INT;
10618
10619 alu.src[0].sel = ctx->temp_reg;
10620 alu.src[0].chan = i;
10621
10622 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
10623 if (i == lasti) {
10624 alu.last = 1;
10625 }
10626 r = r600_bytecode_add_alu(ctx->bc, &alu);
10627 if (r)
10628 return r;
10629 }
10630 return 0;
10631 }
10632
10633 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
10634 {
10635 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10636 struct r600_bytecode_alu alu;
10637 int r, i;
10638 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10639
10640 /* temp.xy = f32_to_f16(src) */
10641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10642 alu.op = ALU_OP1_FLT32_TO_FLT16;
10643 alu.dst.chan = 0;
10644 alu.dst.sel = ctx->temp_reg;
10645 alu.dst.write = 1;
10646 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10647 r = r600_bytecode_add_alu(ctx->bc, &alu);
10648 if (r)
10649 return r;
10650 alu.dst.chan = 1;
10651 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10652 alu.last = 1;
10653 r = r600_bytecode_add_alu(ctx->bc, &alu);
10654 if (r)
10655 return r;
10656
10657 /* dst.x = temp.y * 0x10000 + temp.x */
10658 for (i = 0; i < lasti + 1; i++) {
10659 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10660 continue;
10661
10662 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10663 alu.op = ALU_OP3_MULADD_UINT24;
10664 alu.is_op3 = 1;
10665 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10666 alu.last = i == lasti;
10667 alu.src[0].sel = ctx->temp_reg;
10668 alu.src[0].chan = 1;
10669 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10670 alu.src[1].value = 0x10000;
10671 alu.src[2].sel = ctx->temp_reg;
10672 alu.src[2].chan = 0;
10673 r = r600_bytecode_add_alu(ctx->bc, &alu);
10674 if (r)
10675 return r;
10676 }
10677
10678 return 0;
10679 }
10680
10681 static int tgsi_up2h(struct r600_shader_ctx *ctx)
10682 {
10683 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10684 struct r600_bytecode_alu alu;
10685 int r, i;
10686 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10687
10688 /* temp.x = src.x */
10689 /* note: no need to mask out the high bits */
10690 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10691 alu.op = ALU_OP1_MOV;
10692 alu.dst.chan = 0;
10693 alu.dst.sel = ctx->temp_reg;
10694 alu.dst.write = 1;
10695 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10696 r = r600_bytecode_add_alu(ctx->bc, &alu);
10697 if (r)
10698 return r;
10699
10700 /* temp.y = src.x >> 16 */
10701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10702 alu.op = ALU_OP2_LSHR_INT;
10703 alu.dst.chan = 1;
10704 alu.dst.sel = ctx->temp_reg;
10705 alu.dst.write = 1;
10706 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10707 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10708 alu.src[1].value = 16;
10709 alu.last = 1;
10710 r = r600_bytecode_add_alu(ctx->bc, &alu);
10711 if (r)
10712 return r;
10713
10714 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
10715 for (i = 0; i < lasti + 1; i++) {
10716 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10717 continue;
10718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10719 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10720 alu.op = ALU_OP1_FLT16_TO_FLT32;
10721 alu.src[0].sel = ctx->temp_reg;
10722 alu.src[0].chan = i % 2;
10723 alu.last = i == lasti;
10724 r = r600_bytecode_add_alu(ctx->bc, &alu);
10725 if (r)
10726 return r;
10727 }
10728
10729 return 0;
10730 }
10731
10732 static int tgsi_bfe(struct r600_shader_ctx *ctx)
10733 {
10734 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10735 struct r600_bytecode_alu alu;
10736 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10737 int r, i;
10738 int dst = -1;
10739
10740 if ((inst->Src[0].Register.File == inst->Dst[0].Register.File &&
10741 inst->Src[0].Register.Index == inst->Dst[0].Register.Index) ||
10742 (inst->Src[2].Register.File == inst->Dst[0].Register.File &&
10743 inst->Src[2].Register.Index == inst->Dst[0].Register.Index))
10744 dst = r600_get_temp(ctx);
10745
10746 r = tgsi_op3_dst(ctx, dst);
10747 if (r)
10748 return r;
10749
10750 for (i = 0; i < lasti + 1; i++) {
10751 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10752 alu.op = ALU_OP2_SETGE_INT;
10753 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
10754 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10755 alu.src[1].value = 32;
10756 alu.dst.sel = ctx->temp_reg;
10757 alu.dst.chan = i;
10758 alu.dst.write = 1;
10759 if (i == lasti)
10760 alu.last = 1;
10761 r = r600_bytecode_add_alu(ctx->bc, &alu);
10762 if (r)
10763 return r;
10764 }
10765
10766 for (i = 0; i < lasti + 1; i++) {
10767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10768 alu.op = ALU_OP3_CNDE_INT;
10769 alu.is_op3 = 1;
10770 alu.src[0].sel = ctx->temp_reg;
10771 alu.src[0].chan = i;
10772
10773 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10774 if (dst != -1)
10775 alu.src[1].sel = dst;
10776 else
10777 alu.src[1].sel = alu.dst.sel;
10778 alu.src[1].chan = i;
10779 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
10780 alu.dst.write = 1;
10781 if (i == lasti)
10782 alu.last = 1;
10783 r = r600_bytecode_add_alu(ctx->bc, &alu);
10784 if (r)
10785 return r;
10786 }
10787
10788 return 0;
10789 }
10790
10791 static int tgsi_clock(struct r600_shader_ctx *ctx)
10792 {
10793 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10794 struct r600_bytecode_alu alu;
10795 int r;
10796
10797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10798 alu.op = ALU_OP1_MOV;
10799 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10800 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_LO;
10801 r = r600_bytecode_add_alu(ctx->bc, &alu);
10802 if (r)
10803 return r;
10804 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10805 alu.op = ALU_OP1_MOV;
10806 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10807 alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
10808 alu.last = 1;
10809 r = r600_bytecode_add_alu(ctx->bc, &alu);
10810 if (r)
10811 return r;
10812 return 0;
10813 }
10814
10815 static int emit_u64add(struct r600_shader_ctx *ctx, int op,
10816 int treg,
10817 int src0_sel, int src0_chan,
10818 int src1_sel, int src1_chan)
10819 {
10820 struct r600_bytecode_alu alu;
10821 int r;
10822 int opc;
10823
10824 if (op == ALU_OP2_ADD_INT)
10825 opc = ALU_OP2_ADDC_UINT;
10826 else
10827 opc = ALU_OP2_SUBB_UINT;
10828
10829 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10830 alu.op = op; ;
10831 alu.dst.sel = treg;
10832 alu.dst.chan = 0;
10833 alu.dst.write = 1;
10834 alu.src[0].sel = src0_sel;
10835 alu.src[0].chan = src0_chan + 0;
10836 alu.src[1].sel = src1_sel;
10837 alu.src[1].chan = src1_chan + 0;
10838 alu.src[1].neg = 0;
10839 r = r600_bytecode_add_alu(ctx->bc, &alu);
10840 if (r)
10841 return r;
10842
10843 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10844 alu.op = op;
10845 alu.dst.sel = treg;
10846 alu.dst.chan = 1;
10847 alu.dst.write = 1;
10848 alu.src[0].sel = src0_sel;
10849 alu.src[0].chan = src0_chan + 1;
10850 alu.src[1].sel = src1_sel;
10851 alu.src[1].chan = src1_chan + 1;
10852 alu.src[1].neg = 0;
10853 r = r600_bytecode_add_alu(ctx->bc, &alu);
10854 if (r)
10855 return r;
10856
10857 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10858 alu.op = opc;
10859 alu.dst.sel = treg;
10860 alu.dst.chan = 2;
10861 alu.dst.write = 1;
10862 alu.last = 1;
10863 alu.src[0].sel = src0_sel;
10864 alu.src[0].chan = src0_chan + 0;
10865 alu.src[1].sel = src1_sel;
10866 alu.src[1].chan = src1_chan + 0;
10867 alu.src[1].neg = 0;
10868 r = r600_bytecode_add_alu(ctx->bc, &alu);
10869 if (r)
10870 return r;
10871
10872 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10873 alu.op = op;
10874 alu.dst.sel = treg;
10875 alu.dst.chan = 1;
10876 alu.dst.write = 1;
10877 alu.src[0].sel = treg;
10878 alu.src[0].chan = 1;
10879 alu.src[1].sel = treg;
10880 alu.src[1].chan = 2;
10881 alu.last = 1;
10882 r = r600_bytecode_add_alu(ctx->bc, &alu);
10883 if (r)
10884 return r;
10885 return 0;
10886 }
10887
10888 static int egcm_u64add(struct r600_shader_ctx *ctx)
10889 {
10890 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10891 struct r600_bytecode_alu alu;
10892 int r;
10893 int treg = ctx->temp_reg;
10894 int op = ALU_OP2_ADD_INT, opc = ALU_OP2_ADDC_UINT;
10895
10896 if (ctx->src[1].neg) {
10897 op = ALU_OP2_SUB_INT;
10898 opc = ALU_OP2_SUBB_UINT;
10899 }
10900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10901 alu.op = op; ;
10902 alu.dst.sel = treg;
10903 alu.dst.chan = 0;
10904 alu.dst.write = 1;
10905 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10906 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10907 alu.src[1].neg = 0;
10908 r = r600_bytecode_add_alu(ctx->bc, &alu);
10909 if (r)
10910 return r;
10911
10912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10913 alu.op = op;
10914 alu.dst.sel = treg;
10915 alu.dst.chan = 1;
10916 alu.dst.write = 1;
10917 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10918 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
10919 alu.src[1].neg = 0;
10920 r = r600_bytecode_add_alu(ctx->bc, &alu);
10921 if (r)
10922 return r;
10923
10924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10925 alu.op = opc ;
10926 alu.dst.sel = treg;
10927 alu.dst.chan = 2;
10928 alu.dst.write = 1;
10929 alu.last = 1;
10930 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10931 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10932 alu.src[1].neg = 0;
10933 r = r600_bytecode_add_alu(ctx->bc, &alu);
10934 if (r)
10935 return r;
10936
10937 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10938 alu.op = op;
10939 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
10940 alu.src[0].sel = treg;
10941 alu.src[0].chan = 1;
10942 alu.src[1].sel = treg;
10943 alu.src[1].chan = 2;
10944 alu.last = 1;
10945 r = r600_bytecode_add_alu(ctx->bc, &alu);
10946 if (r)
10947 return r;
10948 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10949 alu.op = ALU_OP1_MOV;
10950 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
10951 alu.src[0].sel = treg;
10952 alu.src[0].chan = 0;
10953 alu.last = 1;
10954 r = r600_bytecode_add_alu(ctx->bc, &alu);
10955 if (r)
10956 return r;
10957 return 0;
10958 }
10959
10960 /* result.y = mul_high a, b
10961 result.x = mul a,b
10962 result.y += a.x * b.y + a.y * b.x;
10963 */
10964 static int egcm_u64mul(struct r600_shader_ctx *ctx)
10965 {
10966 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10967 struct r600_bytecode_alu alu;
10968 int r;
10969 int treg = ctx->temp_reg;
10970
10971 /* temp.x = mul_lo a.x, b.x */
10972 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10973 alu.op = ALU_OP2_MULLO_UINT;
10974 alu.dst.sel = treg;
10975 alu.dst.chan = 0;
10976 alu.dst.write = 1;
10977 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10978 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10979 r = emit_mul_int_op(ctx->bc, &alu);
10980 if (r)
10981 return r;
10982
10983 /* temp.y = mul_hi a.x, b.x */
10984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10985 alu.op = ALU_OP2_MULHI_UINT;
10986 alu.dst.sel = treg;
10987 alu.dst.chan = 1;
10988 alu.dst.write = 1;
10989 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10990 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
10991 r = emit_mul_int_op(ctx->bc, &alu);
10992 if (r)
10993 return r;
10994
10995 /* temp.z = mul a.x, b.y */
10996 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10997 alu.op = ALU_OP2_MULLO_UINT;
10998 alu.dst.sel = treg;
10999 alu.dst.chan = 2;
11000 alu.dst.write = 1;
11001 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
11002 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
11003 r = emit_mul_int_op(ctx->bc, &alu);
11004 if (r)
11005 return r;
11006
11007 /* temp.w = mul a.y, b.x */
11008 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11009 alu.op = ALU_OP2_MULLO_UINT;
11010 alu.dst.sel = treg;
11011 alu.dst.chan = 3;
11012 alu.dst.write = 1;
11013 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
11014 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
11015 r = emit_mul_int_op(ctx->bc, &alu);
11016 if (r)
11017 return r;
11018
11019 /* temp.z = temp.z + temp.w */
11020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11021 alu.op = ALU_OP2_ADD_INT;
11022 alu.dst.sel = treg;
11023 alu.dst.chan = 2;
11024 alu.dst.write = 1;
11025 alu.src[0].sel = treg;
11026 alu.src[0].chan = 2;
11027 alu.src[1].sel = treg;
11028 alu.src[1].chan = 3;
11029 alu.last = 1;
11030 r = r600_bytecode_add_alu(ctx->bc, &alu);
11031 if (r)
11032 return r;
11033
11034 /* temp.y = temp.y + temp.z */
11035 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11036 alu.op = ALU_OP2_ADD_INT;
11037 alu.dst.sel = treg;
11038 alu.dst.chan = 1;
11039 alu.dst.write = 1;
11040 alu.src[0].sel = treg;
11041 alu.src[0].chan = 1;
11042 alu.src[1].sel = treg;
11043 alu.src[1].chan = 2;
11044 alu.last = 1;
11045 r = r600_bytecode_add_alu(ctx->bc, &alu);
11046 if (r)
11047 return r;
11048
11049 /* dst.x = temp.x */
11050 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11051 alu.op = ALU_OP1_MOV;
11052 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11053 alu.src[0].sel = treg;
11054 alu.src[0].chan = 0;
11055 r = r600_bytecode_add_alu(ctx->bc, &alu);
11056 if (r)
11057 return r;
11058
11059 /* dst.y = temp.y */
11060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11061 alu.op = ALU_OP1_MOV;
11062 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11063 alu.src[0].sel = treg;
11064 alu.src[0].chan = 1;
11065 alu.last = 1;
11066 r = r600_bytecode_add_alu(ctx->bc, &alu);
11067 if (r)
11068 return r;
11069
11070 return 0;
11071 }
11072
11073 static int emit_u64sge(struct r600_shader_ctx *ctx,
11074 int treg,
11075 int src0_sel, int src0_base_chan,
11076 int src1_sel, int src1_base_chan)
11077 {
11078 int r;
11079 /* for 64-bit sge */
11080 /* result = (src0.y > src1.y) || ((src0.y == src1.y) && src0.x >= src1.x)) */
11081 r = single_alu_op2(ctx, ALU_OP2_SETGT_UINT,
11082 treg, 1,
11083 src0_sel, src0_base_chan + 1,
11084 src1_sel, src1_base_chan + 1);
11085 if (r)
11086 return r;
11087
11088 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11089 treg, 0,
11090 src0_sel, src0_base_chan,
11091 src1_sel, src1_base_chan);
11092 if (r)
11093 return r;
11094
11095 r = single_alu_op2(ctx, ALU_OP2_SETE_INT,
11096 treg, 2,
11097 src0_sel, src0_base_chan + 1,
11098 src1_sel, src1_base_chan + 1);
11099 if (r)
11100 return r;
11101
11102 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
11103 treg, 0,
11104 treg, 0,
11105 treg, 2);
11106 if (r)
11107 return r;
11108
11109 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11110 treg, 0,
11111 treg, 0,
11112 treg, 1);
11113 if (r)
11114 return r;
11115 return 0;
11116 }
11117
11118 /* this isn't a complete div it's just enough for qbo shader to work */
11119 static int egcm_u64div(struct r600_shader_ctx *ctx)
11120 {
11121 struct r600_bytecode_alu alu;
11122 struct r600_bytecode_alu_src alu_num_hi, alu_num_lo, alu_denom_hi, alu_denom_lo, alu_src;
11123 int r, i;
11124 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11125
11126 /* make sure we are dividing my a const with 0 in the high bits */
11127 if (ctx->src[1].sel != V_SQ_ALU_SRC_LITERAL)
11128 return -1;
11129 if (ctx->src[1].value[ctx->src[1].swizzle[1]] != 0)
11130 return -1;
11131 /* make sure we are doing one division */
11132 if (inst->Dst[0].Register.WriteMask != 0x3)
11133 return -1;
11134
11135 /* emit_if uses ctx->temp_reg so we can't */
11136 int treg = r600_get_temp(ctx);
11137 int tmp_num = r600_get_temp(ctx);
11138 int sub_tmp = r600_get_temp(ctx);
11139
11140 /* tmp quot are tmp_num.zw */
11141 r600_bytecode_src(&alu_num_lo, &ctx->src[0], 0);
11142 r600_bytecode_src(&alu_num_hi, &ctx->src[0], 1);
11143 r600_bytecode_src(&alu_denom_lo, &ctx->src[1], 0);
11144 r600_bytecode_src(&alu_denom_hi, &ctx->src[1], 1);
11145
11146 /* MOV tmp_num.xy, numerator */
11147 r = single_alu_op2(ctx, ALU_OP1_MOV,
11148 tmp_num, 0,
11149 alu_num_lo.sel, alu_num_lo.chan,
11150 0, 0);
11151 if (r)
11152 return r;
11153 r = single_alu_op2(ctx, ALU_OP1_MOV,
11154 tmp_num, 1,
11155 alu_num_hi.sel, alu_num_hi.chan,
11156 0, 0);
11157 if (r)
11158 return r;
11159
11160 r = single_alu_op2(ctx, ALU_OP1_MOV,
11161 tmp_num, 2,
11162 V_SQ_ALU_SRC_LITERAL, 0,
11163 0, 0);
11164 if (r)
11165 return r;
11166
11167 r = single_alu_op2(ctx, ALU_OP1_MOV,
11168 tmp_num, 3,
11169 V_SQ_ALU_SRC_LITERAL, 0,
11170 0, 0);
11171 if (r)
11172 return r;
11173
11174 /* treg 0 is log2_denom */
11175 /* normally this gets the MSB for the denom high value
11176 - however we know this will always be 0 here. */
11177 r = single_alu_op2(ctx,
11178 ALU_OP1_MOV,
11179 treg, 0,
11180 V_SQ_ALU_SRC_LITERAL, 32,
11181 0, 0);
11182 if (r)
11183 return r;
11184
11185 /* normally check demon hi for 0, but we know it is already */
11186 /* t0.z = num_hi >= denom_lo */
11187 r = single_alu_op2(ctx,
11188 ALU_OP2_SETGE_UINT,
11189 treg, 1,
11190 alu_num_hi.sel, alu_num_hi.chan,
11191 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
11192 if (r)
11193 return r;
11194
11195 memset(&alu_src, 0, sizeof(alu_src));
11196 alu_src.sel = treg;
11197 alu_src.chan = 1;
11198 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11199 if (r)
11200 return r;
11201
11202 /* for loops in here */
11203 /* get msb t0.x = msb(src[1].x) first */
11204 int msb_lo = util_last_bit(alu_denom_lo.value);
11205 r = single_alu_op2(ctx, ALU_OP1_MOV,
11206 treg, 0,
11207 V_SQ_ALU_SRC_LITERAL, msb_lo,
11208 0, 0);
11209 if (r)
11210 return r;
11211
11212 /* unroll the asm here */
11213 for (i = 0; i < 31; i++) {
11214 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11215 treg, 2,
11216 V_SQ_ALU_SRC_LITERAL, i,
11217 treg, 0);
11218 if (r)
11219 return r;
11220
11221 /* we can do this on the CPU */
11222 uint32_t denom_lo_shl = alu_denom_lo.value << (31 - i);
11223 /* t0.z = tmp_num.y >= t0.z */
11224 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11225 treg, 1,
11226 tmp_num, 1,
11227 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
11228 if (r)
11229 return r;
11230
11231 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
11232 treg, 1,
11233 treg, 1,
11234 treg, 2);
11235 if (r)
11236 return r;
11237
11238 memset(&alu_src, 0, sizeof(alu_src));
11239 alu_src.sel = treg;
11240 alu_src.chan = 1;
11241 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11242 if (r)
11243 return r;
11244
11245 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
11246 tmp_num, 1,
11247 tmp_num, 1,
11248 V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
11249 if (r)
11250 return r;
11251
11252 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11253 tmp_num, 3,
11254 tmp_num, 3,
11255 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
11256 if (r)
11257 return r;
11258
11259 r = tgsi_endif(ctx);
11260 if (r)
11261 return r;
11262 }
11263
11264 /* log2_denom is always <= 31, so manually peel the last loop
11265 * iteration.
11266 */
11267 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11268 treg, 1,
11269 tmp_num, 1,
11270 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
11271 if (r)
11272 return r;
11273
11274 memset(&alu_src, 0, sizeof(alu_src));
11275 alu_src.sel = treg;
11276 alu_src.chan = 1;
11277 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11278 if (r)
11279 return r;
11280
11281 r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
11282 tmp_num, 1,
11283 tmp_num, 1,
11284 V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
11285 if (r)
11286 return r;
11287
11288 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11289 tmp_num, 3,
11290 tmp_num, 3,
11291 V_SQ_ALU_SRC_LITERAL, 1U);
11292 if (r)
11293 return r;
11294 r = tgsi_endif(ctx);
11295 if (r)
11296 return r;
11297
11298 r = tgsi_endif(ctx);
11299 if (r)
11300 return r;
11301
11302 /* onto the second loop to unroll */
11303 for (i = 0; i < 31; i++) {
11304 r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
11305 treg, 1,
11306 V_SQ_ALU_SRC_LITERAL, (63 - (31 - i)),
11307 treg, 0);
11308 if (r)
11309 return r;
11310
11311 uint64_t denom_shl = (uint64_t)alu_denom_lo.value << (31 - i);
11312 r = single_alu_op2(ctx, ALU_OP1_MOV,
11313 treg, 2,
11314 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
11315 0, 0);
11316 if (r)
11317 return r;
11318
11319 r = single_alu_op2(ctx, ALU_OP1_MOV,
11320 treg, 3,
11321 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
11322 0, 0);
11323 if (r)
11324 return r;
11325
11326 r = emit_u64sge(ctx, sub_tmp,
11327 tmp_num, 0,
11328 treg, 2);
11329 if (r)
11330 return r;
11331
11332 r = single_alu_op2(ctx, ALU_OP2_AND_INT,
11333 treg, 1,
11334 treg, 1,
11335 sub_tmp, 0);
11336 if (r)
11337 return r;
11338
11339 memset(&alu_src, 0, sizeof(alu_src));
11340 alu_src.sel = treg;
11341 alu_src.chan = 1;
11342 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11343 if (r)
11344 return r;
11345
11346
11347 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
11348 sub_tmp,
11349 tmp_num, 0,
11350 treg, 2);
11351 if (r)
11352 return r;
11353
11354 r = single_alu_op2(ctx, ALU_OP1_MOV,
11355 tmp_num, 0,
11356 sub_tmp, 0,
11357 0, 0);
11358 if (r)
11359 return r;
11360
11361 r = single_alu_op2(ctx, ALU_OP1_MOV,
11362 tmp_num, 1,
11363 sub_tmp, 1,
11364 0, 0);
11365 if (r)
11366 return r;
11367
11368 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11369 tmp_num, 2,
11370 tmp_num, 2,
11371 V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
11372 if (r)
11373 return r;
11374
11375 r = tgsi_endif(ctx);
11376 if (r)
11377 return r;
11378 }
11379
11380 /* log2_denom is always <= 63, so manually peel the last loop
11381 * iteration.
11382 */
11383 uint64_t denom_shl = (uint64_t)alu_denom_lo.value;
11384 r = single_alu_op2(ctx, ALU_OP1_MOV,
11385 treg, 2,
11386 V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
11387 0, 0);
11388 if (r)
11389 return r;
11390
11391 r = single_alu_op2(ctx, ALU_OP1_MOV,
11392 treg, 3,
11393 V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
11394 0, 0);
11395 if (r)
11396 return r;
11397
11398 r = emit_u64sge(ctx, sub_tmp,
11399 tmp_num, 0,
11400 treg, 2);
11401 if (r)
11402 return r;
11403
11404 memset(&alu_src, 0, sizeof(alu_src));
11405 alu_src.sel = sub_tmp;
11406 alu_src.chan = 0;
11407 r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
11408 if (r)
11409 return r;
11410
11411 r = emit_u64add(ctx, ALU_OP2_SUB_INT,
11412 sub_tmp,
11413 tmp_num, 0,
11414 treg, 2);
11415 if (r)
11416 return r;
11417
11418 r = single_alu_op2(ctx, ALU_OP2_OR_INT,
11419 tmp_num, 2,
11420 tmp_num, 2,
11421 V_SQ_ALU_SRC_LITERAL, 1U);
11422 if (r)
11423 return r;
11424 r = tgsi_endif(ctx);
11425 if (r)
11426 return r;
11427
11428 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11429 alu.op = ALU_OP1_MOV;
11430 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11431 alu.src[0].sel = tmp_num;
11432 alu.src[0].chan = 2;
11433 r = r600_bytecode_add_alu(ctx->bc, &alu);
11434 if (r)
11435 return r;
11436
11437 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11438 alu.op = ALU_OP1_MOV;
11439 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11440 alu.src[0].sel = tmp_num;
11441 alu.src[0].chan = 3;
11442 alu.last = 1;
11443 r = r600_bytecode_add_alu(ctx->bc, &alu);
11444 if (r)
11445 return r;
11446 return 0;
11447 }
11448
11449 static int egcm_u64sne(struct r600_shader_ctx *ctx)
11450 {
11451 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11452 struct r600_bytecode_alu alu;
11453 int r;
11454 int treg = ctx->temp_reg;
11455
11456 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11457 alu.op = ALU_OP2_SETNE_INT;
11458 alu.dst.sel = treg;
11459 alu.dst.chan = 0;
11460 alu.dst.write = 1;
11461 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
11462 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
11463 r = r600_bytecode_add_alu(ctx->bc, &alu);
11464 if (r)
11465 return r;
11466
11467 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11468 alu.op = ALU_OP2_SETNE_INT;
11469 alu.dst.sel = treg;
11470 alu.dst.chan = 1;
11471 alu.dst.write = 1;
11472 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
11473 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
11474 alu.last = 1;
11475 r = r600_bytecode_add_alu(ctx->bc, &alu);
11476 if (r)
11477 return r;
11478
11479 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
11480 alu.op = ALU_OP2_OR_INT;
11481 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11482 alu.src[0].sel = treg;
11483 alu.src[0].chan = 0;
11484 alu.src[1].sel = treg;
11485 alu.src[1].chan = 1;
11486 alu.last = 1;
11487 r = r600_bytecode_add_alu(ctx->bc, &alu);
11488 if (r)
11489 return r;
11490 return 0;
11491 }
11492
11493 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
11494 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
11495 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11496 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11497
11498 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
11499
11500 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
11501 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11502 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11503 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11504 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11505 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11506 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11507 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11508 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
11509 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11510 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11511 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11512 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11513 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11514 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11515 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
11516 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
11517 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11518 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11519 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11520 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11521 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11522 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11523 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11524 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11525 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11526 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11527 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11528 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11529 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_unsupported},
11530 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11531 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11532 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11533 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11534 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11535 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11536 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
11537 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11538 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11539 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11540 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11541 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11542 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11543 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11544 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11545 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11546 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11547 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11548 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11549 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11550 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11551 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
11552 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11553 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11554 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11555 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11556 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11557 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
11558 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11559 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11560 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11561 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11562 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11563 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11564 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11565 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11566 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11567 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11568 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11569 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11570 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11571 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11572 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11573 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11574 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11575 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11576 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
11577 [81] = { ALU_OP0_NOP, tgsi_unsupported},
11578 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11579 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11580 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11581 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11582 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11583 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
11584 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11585 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11586 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11587 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11588 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11589 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11590 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11591 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11592 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11593 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11594 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11595 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11596 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11597 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11598 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11599 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11600 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11601 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
11602 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11603 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11604 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11605 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11606 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11607 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11608 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
11609 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11610 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11611 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11612 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11613 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11614 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
11615 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
11616 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11617 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11618 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11619 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11620 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11621 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
11622 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11623 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
11624 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11625 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11626 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11627 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11628 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11629 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11630 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11631 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11632 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11633 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11634 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
11635 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11636 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
11637 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11638 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11639 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11640 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11641 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11642 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11643 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11644 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11645 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11646 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11647 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11648 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11649 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11650 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11651 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11652 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11653 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
11654 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11655 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11656 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11657 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
11658 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
11659 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11660 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11661 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11662 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
11663 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
11664 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
11665 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
11666 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
11667 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
11668 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
11669 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11670 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11671 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
11672 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
11673 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11674 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11675 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11676 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11677 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11678 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
11679 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
11680 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
11681 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
11682 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
11683 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
11684 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
11685 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
11686 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
11687 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
11688 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
11689 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
11690 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
11691 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11692 };
11693
11694 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
11695 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11696 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11697 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11698 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
11699 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
11700 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11701 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11702 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11703 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11704 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11705 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11706 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11707 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11708 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11709 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11710 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11711 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11712 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11713 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11714 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
11715 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11716 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11717 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11718 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11719 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11720 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11721 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11722 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
11723 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
11724 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
11725 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11726 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11727 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11728 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11729 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11730 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
11731 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11732 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11733 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11734 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11735 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11736 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11737 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11738 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11739 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11740 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11741 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11742 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
11743 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11744 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11745 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11746 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11747 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11748 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11749 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11750 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11751 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11752 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11753 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11754 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11755 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11756 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11757 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11758 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11759 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11760 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11761 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11762 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11763 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11764 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11765 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11766 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11767 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11768 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11769 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11770 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11771 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11772 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11773 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11774 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11775 [82] = { ALU_OP0_NOP, tgsi_unsupported},
11776 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
11777 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
11778 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
11779 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
11780 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
11781 [88] = { ALU_OP0_NOP, tgsi_unsupported},
11782 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11783 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
11784 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
11785 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
11786 [93] = { ALU_OP0_NOP, tgsi_unsupported},
11787 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
11788 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11789 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
11790 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
11791 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
11792 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
11793 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11794 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
11795 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
11796 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
11797 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
11798 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
11799 [106] = { ALU_OP0_NOP, tgsi_unsupported},
11800 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
11801 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
11802 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
11803 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
11804 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
11805 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11806 [113] = { ALU_OP0_NOP, tgsi_unsupported},
11807 [114] = { ALU_OP0_NOP, tgsi_unsupported},
11808 [115] = { ALU_OP0_NOP, tgsi_unsupported},
11809 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
11810 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
11811 /* Refer below for TGSI_OPCODE_DFMA */
11812 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
11813 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
11814 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
11815 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
11816 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
11817 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
11818 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
11819 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
11820 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
11821 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
11822 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
11823 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
11824 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
11825 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
11826 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
11827 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
11828 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
11829 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
11830 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
11831 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
11832 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
11833 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
11834 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11835 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
11836 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
11837 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
11838 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
11839 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
11840 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
11841 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
11842 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
11843 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
11844 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
11845 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
11846 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
11847 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
11848 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
11849 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
11850 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
11851 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
11852 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
11853 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
11854 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
11855 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
11856 [163] = { ALU_OP0_NOP, tgsi_unsupported},
11857 [164] = { ALU_OP0_NOP, tgsi_unsupported},
11858 [165] = { ALU_OP0_NOP, tgsi_unsupported},
11859 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
11860 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
11861 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
11862 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
11863 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
11864 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
11865 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
11866 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
11867 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
11868 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
11869 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
11870 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
11871 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11872 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11873 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
11874 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
11875 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
11876 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
11877 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
11878 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
11879 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
11880 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
11881 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
11882 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
11883 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
11884 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
11885 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
11886 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
11887 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
11888 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
11889 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
11890 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
11891 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
11892 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
11893 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
11894 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
11895 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
11896 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
11897 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
11898 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
11899 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
11900 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
11901 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
11902 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
11903 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
11904 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
11905 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
11906 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
11907 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
11908 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
11909 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
11910 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
11911 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
11912 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
11913 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
11914 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
11915 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
11916 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
11917 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
11918 };
11919
11920 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
11921 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
11922 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
11923 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
11924 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
11925 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
11926 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
11927 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
11928 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
11929 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
11930 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11931 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11932 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
11933 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
11934 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
11935 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
11936 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
11937 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
11938 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
11939 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
11940 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
11941 [21] = { ALU_OP0_NOP, tgsi_unsupported},
11942 [22] = { ALU_OP0_NOP, tgsi_unsupported},
11943 [23] = { ALU_OP0_NOP, tgsi_unsupported},
11944 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
11945 [25] = { ALU_OP0_NOP, tgsi_unsupported},
11946 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
11947 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
11948 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
11949 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
11950 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
11951 [31] = { ALU_OP0_NOP, tgsi_unsupported},
11952 [32] = { ALU_OP0_NOP, tgsi_unsupported},
11953 [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
11954 [34] = { ALU_OP0_NOP, tgsi_unsupported},
11955 [35] = { ALU_OP0_NOP, tgsi_unsupported},
11956 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
11957 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
11958 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
11959 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
11960 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
11961 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
11962 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
11963 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11964 [44] = { ALU_OP0_NOP, tgsi_unsupported},
11965 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
11966 [46] = { ALU_OP0_NOP, tgsi_unsupported},
11967 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
11968 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
11969 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
11970 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
11971 [51] = { ALU_OP0_NOP, tgsi_unsupported},
11972 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
11973 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
11974 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
11975 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
11976 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
11977 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
11978 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
11979 [59] = { ALU_OP0_NOP, tgsi_unsupported},
11980 [60] = { ALU_OP0_NOP, tgsi_unsupported},
11981 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
11982 [62] = { ALU_OP0_NOP, tgsi_unsupported},
11983 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
11984 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
11985 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
11986 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
11987 [67] = { ALU_OP0_NOP, tgsi_unsupported},
11988 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
11989 [69] = { ALU_OP0_NOP, tgsi_unsupported},
11990 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
11991 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
11992 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
11993 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
11994 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
11995 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
11996 [76] = { ALU_OP0_NOP, tgsi_unsupported},
11997 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
11998 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
11999 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
12000 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
12001 [82] = { ALU_OP0_NOP, tgsi_unsupported},
12002 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
12003 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
12004 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
12005 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
12006 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
12007 [88] = { ALU_OP0_NOP, tgsi_unsupported},
12008 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
12009 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
12010 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
12011 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
12012 [93] = { ALU_OP0_NOP, tgsi_unsupported},
12013 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
12014 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
12015 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
12016 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
12017 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
12018 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
12019 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
12020 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
12021 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
12022 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
12023 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
12024 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
12025 [106] = { ALU_OP0_NOP, tgsi_unsupported},
12026 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
12027 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
12028 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
12029 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
12030 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
12031 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
12032 [113] = { ALU_OP0_NOP, tgsi_unsupported},
12033 [114] = { ALU_OP0_NOP, tgsi_unsupported},
12034 [115] = { ALU_OP0_NOP, tgsi_unsupported},
12035 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
12036 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
12037 /* Refer below for TGSI_OPCODE_DFMA */
12038 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
12039 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
12040 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
12041 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
12042 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
12043 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
12044 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
12045 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
12046 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
12047 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
12048 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
12049 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
12050 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
12051 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
12052 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
12053 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
12054 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
12055 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
12056 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
12057 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
12058 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
12059 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
12060 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
12061 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
12062 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
12063 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
12064 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
12065 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
12066 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
12067 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
12068 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
12069 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
12070 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
12071 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
12072 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
12073 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
12074 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
12075 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
12076 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
12077 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
12078 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
12079 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
12080 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
12081 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
12082 [163] = { ALU_OP0_NOP, tgsi_unsupported},
12083 [164] = { ALU_OP0_NOP, tgsi_unsupported},
12084 [165] = { ALU_OP0_NOP, tgsi_unsupported},
12085 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
12086 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
12087 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
12088 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
12089 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
12090 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
12091 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
12092 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
12093 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
12094 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
12095 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
12096 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
12097 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
12098 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
12099 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
12100 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
12101 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
12102 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
12103 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
12104 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
12105 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
12106 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
12107 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
12108 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
12109 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
12110 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
12111 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
12112 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
12113 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
12114 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
12115 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
12116 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
12117 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
12118 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
12119 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
12120 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
12121 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
12122 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
12123 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
12124 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
12125 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
12126 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
12127 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
12128 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
12129 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
12130 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
12131 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
12132 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
12133 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
12134 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
12135 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
12136 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
12137 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
12138 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
12139 [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
12140 [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
12141 [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
12142 [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
12143 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
12144 };