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r600: add gs tri strip adjacency fix.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 use_sb &= !shader->shader.uses_atomics;
198
199 /* Check if the bytecode has already been built. */
200 if (!shader->shader.bc.bytecode) {
201 r = r600_bytecode_build(&shader->shader.bc);
202 if (r) {
203 R600_ERR("building bytecode failed !\n");
204 goto error;
205 }
206 }
207
208 if (dump && !sb_disasm) {
209 fprintf(stderr, "--------------------------------------------------------------\n");
210 r600_bytecode_disasm(&shader->shader.bc);
211 fprintf(stderr, "______________________________________________________________\n");
212 } else if ((dump && sb_disasm) || use_sb) {
213 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
214 dump, use_sb);
215 if (r) {
216 R600_ERR("r600_sb_bytecode_process failed !\n");
217 goto error;
218 }
219 }
220
221 if (shader->gs_copy_shader) {
222 if (dump) {
223 // dump copy shader
224 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
225 &shader->gs_copy_shader->shader, dump, 0);
226 if (r)
227 goto error;
228 }
229
230 if ((r = store_shader(ctx, shader->gs_copy_shader)))
231 goto error;
232 }
233
234 /* Store the shader in a buffer. */
235 if ((r = store_shader(ctx, shader)))
236 goto error;
237
238 /* Build state. */
239 switch (shader->shader.processor_type) {
240 case PIPE_SHADER_TESS_CTRL:
241 evergreen_update_hs_state(ctx, shader);
242 break;
243 case PIPE_SHADER_TESS_EVAL:
244 if (key.tes.as_es)
245 evergreen_update_es_state(ctx, shader);
246 else
247 evergreen_update_vs_state(ctx, shader);
248 break;
249 case PIPE_SHADER_GEOMETRY:
250 if (rctx->b.chip_class >= EVERGREEN) {
251 evergreen_update_gs_state(ctx, shader);
252 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
253 } else {
254 r600_update_gs_state(ctx, shader);
255 r600_update_vs_state(ctx, shader->gs_copy_shader);
256 }
257 break;
258 case PIPE_SHADER_VERTEX:
259 export_shader = key.vs.as_es;
260 if (rctx->b.chip_class >= EVERGREEN) {
261 if (key.vs.as_ls)
262 evergreen_update_ls_state(ctx, shader);
263 else if (key.vs.as_es)
264 evergreen_update_es_state(ctx, shader);
265 else
266 evergreen_update_vs_state(ctx, shader);
267 } else {
268 if (export_shader)
269 r600_update_es_state(ctx, shader);
270 else
271 r600_update_vs_state(ctx, shader);
272 }
273 break;
274 case PIPE_SHADER_FRAGMENT:
275 if (rctx->b.chip_class >= EVERGREEN) {
276 evergreen_update_ps_state(ctx, shader);
277 } else {
278 r600_update_ps_state(ctx, shader);
279 }
280 break;
281 default:
282 r = -EINVAL;
283 goto error;
284 }
285 return 0;
286
287 error:
288 r600_pipe_shader_destroy(ctx, shader);
289 return r;
290 }
291
292 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
293 {
294 r600_resource_reference(&shader->bo, NULL);
295 r600_bytecode_clear(&shader->shader.bc);
296 r600_release_command_buffer(&shader->command_buffer);
297 }
298
299 /*
300 * tgsi -> r600 shader
301 */
302 struct r600_shader_tgsi_instruction;
303
304 struct r600_shader_src {
305 unsigned sel;
306 unsigned swizzle[4];
307 unsigned neg;
308 unsigned abs;
309 unsigned rel;
310 unsigned kc_bank;
311 boolean kc_rel; /* true if cache bank is indexed */
312 uint32_t value[4];
313 };
314
315 struct eg_interp {
316 boolean enabled;
317 unsigned ij_index;
318 };
319
320 struct r600_shader_ctx {
321 struct tgsi_shader_info info;
322 struct tgsi_parse_context parse;
323 const struct tgsi_token *tokens;
324 unsigned type;
325 unsigned file_offset[TGSI_FILE_COUNT];
326 unsigned temp_reg;
327 const struct r600_shader_tgsi_instruction *inst_info;
328 struct r600_bytecode *bc;
329 struct r600_shader *shader;
330 struct r600_shader_src src[4];
331 uint32_t *literals;
332 uint32_t nliterals;
333 uint32_t max_driver_temp_used;
334 /* needed for evergreen interpolation */
335 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
336 /* evergreen/cayman also store sample mask in face register */
337 int face_gpr;
338 /* sample id is .w component stored in fixed point position register */
339 int fixed_pt_position_gpr;
340 int colors_used;
341 boolean clip_vertex_write;
342 unsigned cv_output;
343 unsigned edgeflag_output;
344 int fragcoord_input;
345 int native_integers;
346 int next_ring_offset;
347 int gs_out_ring_offset;
348 int gs_next_vertex;
349 struct r600_shader *gs_for_vs;
350 int gs_export_gpr_tregs[4];
351 int gs_rotated_input[2];
352 const struct pipe_stream_output_info *gs_stream_output_info;
353 unsigned enabled_stream_buffers_mask;
354 unsigned tess_input_info; /* temp with tess input offsets */
355 unsigned tess_output_info; /* temp with tess input offsets */
356 };
357
358 struct r600_shader_tgsi_instruction {
359 unsigned op;
360 int (*process)(struct r600_shader_ctx *ctx);
361 };
362
363 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
364 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
365 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
366 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
367 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
368 static int tgsi_else(struct r600_shader_ctx *ctx);
369 static int tgsi_endif(struct r600_shader_ctx *ctx);
370 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
371 static int tgsi_endloop(struct r600_shader_ctx *ctx);
372 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
373 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
374 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
375 unsigned int dst_reg);
376 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
377 const struct r600_shader_src *shader_src,
378 unsigned chan);
379 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
380 unsigned dst_reg);
381
382 static int tgsi_last_instruction(unsigned writemask)
383 {
384 int i, lasti = 0;
385
386 for (i = 0; i < 4; i++) {
387 if (writemask & (1 << i)) {
388 lasti = i;
389 }
390 }
391 return lasti;
392 }
393
394 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
395 {
396 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
397 unsigned j;
398
399 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
400 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
401 return -EINVAL;
402 }
403 #if 0
404 if (i->Instruction.Label) {
405 R600_ERR("label unsupported\n");
406 return -EINVAL;
407 }
408 #endif
409 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
410 if (i->Src[j].Register.Dimension) {
411 switch (i->Src[j].Register.File) {
412 case TGSI_FILE_CONSTANT:
413 case TGSI_FILE_HW_ATOMIC:
414 break;
415 case TGSI_FILE_INPUT:
416 if (ctx->type == PIPE_SHADER_GEOMETRY ||
417 ctx->type == PIPE_SHADER_TESS_CTRL ||
418 ctx->type == PIPE_SHADER_TESS_EVAL)
419 break;
420 case TGSI_FILE_OUTPUT:
421 if (ctx->type == PIPE_SHADER_TESS_CTRL)
422 break;
423 default:
424 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
425 i->Src[j].Register.File,
426 i->Src[j].Register.Dimension);
427 return -EINVAL;
428 }
429 }
430 }
431 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
432 if (i->Dst[j].Register.Dimension) {
433 if (ctx->type == PIPE_SHADER_TESS_CTRL)
434 continue;
435 R600_ERR("unsupported dst (dimension)\n");
436 return -EINVAL;
437 }
438 }
439 return 0;
440 }
441
442 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
443 {
444 if (interpolate == TGSI_INTERPOLATE_COLOR ||
445 interpolate == TGSI_INTERPOLATE_LINEAR ||
446 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
447 {
448 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
449 int loc;
450
451 switch(location) {
452 case TGSI_INTERPOLATE_LOC_CENTER:
453 loc = 1;
454 break;
455 case TGSI_INTERPOLATE_LOC_CENTROID:
456 loc = 2;
457 break;
458 case TGSI_INTERPOLATE_LOC_SAMPLE:
459 default:
460 loc = 0; break;
461 }
462
463 return is_linear * 3 + loc;
464 }
465
466 return -1;
467 }
468
469 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
470 int input)
471 {
472 int i = eg_get_interpolator_index(
473 ctx->shader->input[input].interpolate,
474 ctx->shader->input[input].interpolate_location);
475 assert(i >= 0);
476 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
477 }
478
479 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
480 {
481 int i, r;
482 struct r600_bytecode_alu alu;
483 int gpr = 0, base_chan = 0;
484 int ij_index = ctx->shader->input[input].ij_index;
485
486 /* work out gpr and base_chan from index */
487 gpr = ij_index / 2;
488 base_chan = (2 * (ij_index % 2)) + 1;
489
490 for (i = 0; i < 8; i++) {
491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
492
493 if (i < 4)
494 alu.op = ALU_OP2_INTERP_ZW;
495 else
496 alu.op = ALU_OP2_INTERP_XY;
497
498 if ((i > 1) && (i < 6)) {
499 alu.dst.sel = ctx->shader->input[input].gpr;
500 alu.dst.write = 1;
501 }
502
503 alu.dst.chan = i % 4;
504
505 alu.src[0].sel = gpr;
506 alu.src[0].chan = (base_chan - (i % 2));
507
508 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
509
510 alu.bank_swizzle_force = SQ_ALU_VEC_210;
511 if ((i % 4) == 3)
512 alu.last = 1;
513 r = r600_bytecode_add_alu(ctx->bc, &alu);
514 if (r)
515 return r;
516 }
517 return 0;
518 }
519
520 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
521 {
522 int i, r;
523 struct r600_bytecode_alu alu;
524
525 for (i = 0; i < 4; i++) {
526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
527
528 alu.op = ALU_OP1_INTERP_LOAD_P0;
529
530 alu.dst.sel = ctx->shader->input[input].gpr;
531 alu.dst.write = 1;
532
533 alu.dst.chan = i;
534
535 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
536 alu.src[0].chan = i;
537
538 if (i == 3)
539 alu.last = 1;
540 r = r600_bytecode_add_alu(ctx->bc, &alu);
541 if (r)
542 return r;
543 }
544 return 0;
545 }
546
547 /*
548 * Special export handling in shaders
549 *
550 * shader export ARRAY_BASE for EXPORT_POS:
551 * 60 is position
552 * 61 is misc vector
553 * 62, 63 are clip distance vectors
554 *
555 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
556 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
557 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
558 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
559 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
560 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
561 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
562 * exclusive from render target index)
563 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
564 *
565 *
566 * shader export ARRAY_BASE for EXPORT_PIXEL:
567 * 0-7 CB targets
568 * 61 computed Z vector
569 *
570 * The use of the values exported in the computed Z vector are controlled
571 * by DB_SHADER_CONTROL:
572 * Z_EXPORT_ENABLE - Z as a float in RED
573 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
574 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
575 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
576 * DB_SOURCE_FORMAT - export control restrictions
577 *
578 */
579
580
581 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
582 static int r600_spi_sid(struct r600_shader_io * io)
583 {
584 int index, name = io->name;
585
586 /* These params are handled differently, they don't need
587 * semantic indices, so we'll use 0 for them.
588 */
589 if (name == TGSI_SEMANTIC_POSITION ||
590 name == TGSI_SEMANTIC_PSIZE ||
591 name == TGSI_SEMANTIC_EDGEFLAG ||
592 name == TGSI_SEMANTIC_FACE ||
593 name == TGSI_SEMANTIC_SAMPLEMASK)
594 index = 0;
595 else {
596 if (name == TGSI_SEMANTIC_GENERIC) {
597 /* For generic params simply use sid from tgsi */
598 index = io->sid;
599 } else {
600 /* For non-generic params - pack name and sid into 8 bits */
601 index = 0x80 | (name<<3) | (io->sid);
602 }
603
604 /* Make sure that all really used indices have nonzero value, so
605 * we can just compare it to 0 later instead of comparing the name
606 * with different values to detect special cases. */
607 index++;
608 }
609
610 return index;
611 };
612
613 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
614 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
615 {
616 switch (semantic_name) {
617 case TGSI_SEMANTIC_POSITION:
618 return 0;
619 case TGSI_SEMANTIC_PSIZE:
620 return 1;
621 case TGSI_SEMANTIC_CLIPDIST:
622 assert(index <= 1);
623 return 2 + index;
624 case TGSI_SEMANTIC_GENERIC:
625 if (index <= 63-4)
626 return 4 + index - 9;
627 else
628 /* same explanation as in the default statement,
629 * the only user hitting this is st/nine.
630 */
631 return 0;
632
633 /* patch indices are completely separate and thus start from 0 */
634 case TGSI_SEMANTIC_TESSOUTER:
635 return 0;
636 case TGSI_SEMANTIC_TESSINNER:
637 return 1;
638 case TGSI_SEMANTIC_PATCH:
639 return 2 + index;
640
641 default:
642 /* Don't fail here. The result of this function is only used
643 * for LS, TCS, TES, and GS, where legacy GL semantics can't
644 * occur, but this function is called for all vertex shaders
645 * before it's known whether LS will be compiled or not.
646 */
647 return 0;
648 }
649 }
650
651 /* turn input into interpolate on EG */
652 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
653 {
654 int r = 0;
655
656 if (ctx->shader->input[index].spi_sid) {
657 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
658 if (ctx->shader->input[index].interpolate > 0) {
659 evergreen_interp_assign_ij_index(ctx, index);
660 r = evergreen_interp_alu(ctx, index);
661 } else {
662 r = evergreen_interp_flat(ctx, index);
663 }
664 }
665 return r;
666 }
667
668 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
669 {
670 struct r600_bytecode_alu alu;
671 int i, r;
672 int gpr_front = ctx->shader->input[front].gpr;
673 int gpr_back = ctx->shader->input[back].gpr;
674
675 for (i = 0; i < 4; i++) {
676 memset(&alu, 0, sizeof(alu));
677 alu.op = ALU_OP3_CNDGT;
678 alu.is_op3 = 1;
679 alu.dst.write = 1;
680 alu.dst.sel = gpr_front;
681 alu.src[0].sel = ctx->face_gpr;
682 alu.src[1].sel = gpr_front;
683 alu.src[2].sel = gpr_back;
684
685 alu.dst.chan = i;
686 alu.src[1].chan = i;
687 alu.src[2].chan = i;
688 alu.last = (i==3);
689
690 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
691 return r;
692 }
693
694 return 0;
695 }
696
697 /* execute a single slot ALU calculation */
698 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
699 int dst_sel, int dst_chan,
700 int src0_sel, unsigned src0_chan_val,
701 int src1_sel, unsigned src1_chan_val)
702 {
703 struct r600_bytecode_alu alu;
704 int r, i;
705
706 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
707 for (i = 0; i < 4; i++) {
708 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
709 alu.op = op;
710 alu.src[0].sel = src0_sel;
711 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
712 alu.src[0].value = src0_chan_val;
713 else
714 alu.src[0].chan = src0_chan_val;
715 alu.src[1].sel = src1_sel;
716 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
717 alu.src[1].value = src1_chan_val;
718 else
719 alu.src[1].chan = src1_chan_val;
720 alu.dst.sel = dst_sel;
721 alu.dst.chan = i;
722 alu.dst.write = i == dst_chan;
723 alu.last = (i == 3);
724 r = r600_bytecode_add_alu(ctx->bc, &alu);
725 if (r)
726 return r;
727 }
728 return 0;
729 }
730
731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
732 alu.op = op;
733 alu.src[0].sel = src0_sel;
734 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
735 alu.src[0].value = src0_chan_val;
736 else
737 alu.src[0].chan = src0_chan_val;
738 alu.src[1].sel = src1_sel;
739 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
740 alu.src[1].value = src1_chan_val;
741 else
742 alu.src[1].chan = src1_chan_val;
743 alu.dst.sel = dst_sel;
744 alu.dst.chan = dst_chan;
745 alu.dst.write = 1;
746 alu.last = 1;
747 r = r600_bytecode_add_alu(ctx->bc, &alu);
748 if (r)
749 return r;
750 return 0;
751 }
752
753 /* execute a single slot ALU calculation */
754 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
755 int dst_sel, int dst_chan,
756 int src0_sel, unsigned src0_chan_val,
757 int src1_sel, unsigned src1_chan_val,
758 int src2_sel, unsigned src2_chan_val)
759 {
760 struct r600_bytecode_alu alu;
761 int r;
762
763 /* validate this for other ops */
764 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
766 alu.op = op;
767 alu.src[0].sel = src0_sel;
768 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
769 alu.src[0].value = src0_chan_val;
770 else
771 alu.src[0].chan = src0_chan_val;
772 alu.src[1].sel = src1_sel;
773 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
774 alu.src[1].value = src1_chan_val;
775 else
776 alu.src[1].chan = src1_chan_val;
777 alu.src[2].sel = src2_sel;
778 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
779 alu.src[2].value = src2_chan_val;
780 else
781 alu.src[2].chan = src2_chan_val;
782 alu.dst.sel = dst_sel;
783 alu.dst.chan = dst_chan;
784 alu.is_op3 = 1;
785 alu.last = 1;
786 r = r600_bytecode_add_alu(ctx->bc, &alu);
787 if (r)
788 return r;
789 return 0;
790 }
791
792 /* put it in temp_reg.x */
793 static int get_lds_offset0(struct r600_shader_ctx *ctx,
794 int rel_patch_chan,
795 int temp_reg, bool is_patch_var)
796 {
797 int r;
798
799 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
800 /* ADD
801 Dimension - patch0_offset (input_vals.z),
802 Non-dim - patch0_data_offset (input_vals.w)
803 */
804 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
805 temp_reg, 0,
806 ctx->tess_output_info, 0,
807 0, rel_patch_chan,
808 ctx->tess_output_info, is_patch_var ? 3 : 2);
809 if (r)
810 return r;
811 return 0;
812 }
813
814 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
815 {
816 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
817 }
818
819 static int r600_get_temp(struct r600_shader_ctx *ctx)
820 {
821 return ctx->temp_reg + ctx->max_driver_temp_used++;
822 }
823
824 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
825 {
826 int i;
827 i = ctx->shader->noutput++;
828 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
829 ctx->shader->output[i].sid = 0;
830 ctx->shader->output[i].gpr = 0;
831 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
832 ctx->shader->output[i].write_mask = 0x4;
833 ctx->shader->output[i].spi_sid = prim_id_sid;
834
835 return 0;
836 }
837
838 static int tgsi_barrier(struct r600_shader_ctx *ctx)
839 {
840 struct r600_bytecode_alu alu;
841 int r;
842
843 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
844 alu.op = ctx->inst_info->op;
845 alu.last = 1;
846
847 r = r600_bytecode_add_alu(ctx->bc, &alu);
848 if (r)
849 return r;
850 return 0;
851 }
852
853 static int tgsi_declaration(struct r600_shader_ctx *ctx)
854 {
855 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
856 int r, i, j, count = d->Range.Last - d->Range.First + 1;
857
858 switch (d->Declaration.File) {
859 case TGSI_FILE_INPUT:
860 for (j = 0; j < count; j++) {
861 i = ctx->shader->ninput + j;
862 assert(i < ARRAY_SIZE(ctx->shader->input));
863 ctx->shader->input[i].name = d->Semantic.Name;
864 ctx->shader->input[i].sid = d->Semantic.Index + j;
865 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
866 ctx->shader->input[i].interpolate_location = d->Interp.Location;
867 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
868 if (ctx->type == PIPE_SHADER_FRAGMENT) {
869 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
870 switch (ctx->shader->input[i].name) {
871 case TGSI_SEMANTIC_FACE:
872 if (ctx->face_gpr != -1)
873 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
874 else
875 ctx->face_gpr = ctx->shader->input[i].gpr;
876 break;
877 case TGSI_SEMANTIC_COLOR:
878 ctx->colors_used++;
879 break;
880 case TGSI_SEMANTIC_POSITION:
881 ctx->fragcoord_input = i;
882 break;
883 case TGSI_SEMANTIC_PRIMID:
884 /* set this for now */
885 ctx->shader->gs_prim_id_input = true;
886 ctx->shader->ps_prim_id_input = i;
887 break;
888 }
889 if (ctx->bc->chip_class >= EVERGREEN) {
890 if ((r = evergreen_interp_input(ctx, i)))
891 return r;
892 }
893 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
894 /* FIXME probably skip inputs if they aren't passed in the ring */
895 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
896 ctx->next_ring_offset += 16;
897 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
898 ctx->shader->gs_prim_id_input = true;
899 }
900 }
901 ctx->shader->ninput += count;
902 break;
903 case TGSI_FILE_OUTPUT:
904 for (j = 0; j < count; j++) {
905 i = ctx->shader->noutput + j;
906 assert(i < ARRAY_SIZE(ctx->shader->output));
907 ctx->shader->output[i].name = d->Semantic.Name;
908 ctx->shader->output[i].sid = d->Semantic.Index + j;
909 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
910 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
911 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
912 if (ctx->type == PIPE_SHADER_VERTEX ||
913 ctx->type == PIPE_SHADER_GEOMETRY ||
914 ctx->type == PIPE_SHADER_TESS_EVAL) {
915 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
916 switch (d->Semantic.Name) {
917 case TGSI_SEMANTIC_CLIPDIST:
918 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
919 ((d->Semantic.Index + j) << 2);
920 break;
921 case TGSI_SEMANTIC_PSIZE:
922 ctx->shader->vs_out_misc_write = 1;
923 ctx->shader->vs_out_point_size = 1;
924 break;
925 case TGSI_SEMANTIC_EDGEFLAG:
926 ctx->shader->vs_out_misc_write = 1;
927 ctx->shader->vs_out_edgeflag = 1;
928 ctx->edgeflag_output = i;
929 break;
930 case TGSI_SEMANTIC_VIEWPORT_INDEX:
931 ctx->shader->vs_out_misc_write = 1;
932 ctx->shader->vs_out_viewport = 1;
933 break;
934 case TGSI_SEMANTIC_LAYER:
935 ctx->shader->vs_out_misc_write = 1;
936 ctx->shader->vs_out_layer = 1;
937 break;
938 case TGSI_SEMANTIC_CLIPVERTEX:
939 ctx->clip_vertex_write = TRUE;
940 ctx->cv_output = i;
941 break;
942 }
943 if (ctx->type == PIPE_SHADER_GEOMETRY) {
944 ctx->gs_out_ring_offset += 16;
945 }
946 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
947 switch (d->Semantic.Name) {
948 case TGSI_SEMANTIC_COLOR:
949 ctx->shader->nr_ps_max_color_exports++;
950 break;
951 }
952 }
953 }
954 ctx->shader->noutput += count;
955 break;
956 case TGSI_FILE_TEMPORARY:
957 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
958 if (d->Array.ArrayID) {
959 r600_add_gpr_array(ctx->shader,
960 ctx->file_offset[TGSI_FILE_TEMPORARY] +
961 d->Range.First,
962 d->Range.Last - d->Range.First + 1, 0x0F);
963 }
964 }
965 break;
966
967 case TGSI_FILE_CONSTANT:
968 case TGSI_FILE_SAMPLER:
969 case TGSI_FILE_SAMPLER_VIEW:
970 case TGSI_FILE_ADDRESS:
971 break;
972
973 case TGSI_FILE_HW_ATOMIC:
974 i = ctx->shader->nhwatomic_ranges;
975 ctx->shader->atomics[i].start = d->Range.First;
976 ctx->shader->atomics[i].end = d->Range.Last;
977 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
978 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
979 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
980 ctx->shader->nhwatomic_ranges++;
981 ctx->shader->nhwatomic += count;
982 break;
983
984 case TGSI_FILE_SYSTEM_VALUE:
985 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
986 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
987 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
988 break; /* Already handled from allocate_system_value_inputs */
989 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
990 if (!ctx->native_integers) {
991 struct r600_bytecode_alu alu;
992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
993
994 alu.op = ALU_OP1_INT_TO_FLT;
995 alu.src[0].sel = 0;
996 alu.src[0].chan = 3;
997
998 alu.dst.sel = 0;
999 alu.dst.chan = 3;
1000 alu.dst.write = 1;
1001 alu.last = 1;
1002
1003 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1004 return r;
1005 }
1006 break;
1007 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1008 break;
1009 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1010 break;
1011 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1012 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1013 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1014 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1015 unsigned temp_reg = r600_get_temp(ctx);
1016
1017 r = get_lds_offset0(ctx, 2, temp_reg, true);
1018 if (r)
1019 return r;
1020
1021 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1022 temp_reg, 0,
1023 temp_reg, 0,
1024 V_SQ_ALU_SRC_LITERAL, param * 16);
1025 if (r)
1026 return r;
1027
1028 do_lds_fetch_values(ctx, temp_reg, dreg);
1029 }
1030 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1031 /* MOV r1.x, r0.x;
1032 MOV r1.y, r0.y;
1033 */
1034 for (i = 0; i < 2; i++) {
1035 struct r600_bytecode_alu alu;
1036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1037 alu.op = ALU_OP1_MOV;
1038 alu.src[0].sel = 0;
1039 alu.src[0].chan = 0 + i;
1040 alu.dst.sel = 1;
1041 alu.dst.chan = 0 + i;
1042 alu.dst.write = 1;
1043 alu.last = (i == 1) ? 1 : 0;
1044 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1045 return r;
1046 }
1047 /* ADD r1.z, 1.0f, -r0.x */
1048 struct r600_bytecode_alu alu;
1049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1050 alu.op = ALU_OP2_ADD;
1051 alu.src[0].sel = V_SQ_ALU_SRC_1;
1052 alu.src[1].sel = 1;
1053 alu.src[1].chan = 0;
1054 alu.src[1].neg = 1;
1055 alu.dst.sel = 1;
1056 alu.dst.chan = 2;
1057 alu.dst.write = 1;
1058 alu.last = 1;
1059 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1060 return r;
1061
1062 /* ADD r1.z, r1.z, -r1.y */
1063 alu.op = ALU_OP2_ADD;
1064 alu.src[0].sel = 1;
1065 alu.src[0].chan = 2;
1066 alu.src[1].sel = 1;
1067 alu.src[1].chan = 1;
1068 alu.src[1].neg = 1;
1069 alu.dst.sel = 1;
1070 alu.dst.chan = 2;
1071 alu.dst.write = 1;
1072 alu.last = 1;
1073 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1074 return r;
1075 break;
1076 }
1077 break;
1078 default:
1079 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1080 return -EINVAL;
1081 }
1082 return 0;
1083 }
1084
1085 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1086 {
1087 struct tgsi_parse_context parse;
1088 struct {
1089 boolean enabled;
1090 int *reg;
1091 unsigned name, alternate_name;
1092 } inputs[2] = {
1093 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1094
1095 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1096 };
1097 int i, k, num_regs = 0;
1098
1099 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1100 return 0;
1101 }
1102
1103 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1104 while (!tgsi_parse_end_of_tokens(&parse)) {
1105 tgsi_parse_token(&parse);
1106
1107 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1108 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1109 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1110 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1111 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1112 {
1113 int interpolate, location, k;
1114
1115 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1116 location = TGSI_INTERPOLATE_LOC_CENTER;
1117 inputs[1].enabled = true; /* needs SAMPLEID */
1118 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1119 location = TGSI_INTERPOLATE_LOC_CENTER;
1120 /* Needs sample positions, currently those are always available */
1121 } else {
1122 location = TGSI_INTERPOLATE_LOC_CENTROID;
1123 }
1124
1125 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1126 k = eg_get_interpolator_index(interpolate, location);
1127 if (k >= 0)
1128 ctx->eg_interpolators[k].enabled = true;
1129 }
1130 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1131 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1132 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1133 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1134 if (d->Semantic.Name == inputs[k].name ||
1135 d->Semantic.Name == inputs[k].alternate_name) {
1136 inputs[k].enabled = true;
1137 }
1138 }
1139 }
1140 }
1141 }
1142
1143 tgsi_parse_free(&parse);
1144
1145 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1146 boolean enabled = inputs[i].enabled;
1147 int *reg = inputs[i].reg;
1148 unsigned name = inputs[i].name;
1149
1150 if (enabled) {
1151 int gpr = gpr_offset + num_regs++;
1152 ctx->shader->nsys_inputs++;
1153
1154 // add to inputs, allocate a gpr
1155 k = ctx->shader->ninput++;
1156 ctx->shader->input[k].name = name;
1157 ctx->shader->input[k].sid = 0;
1158 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1159 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1160 *reg = ctx->shader->input[k].gpr = gpr;
1161 }
1162 }
1163
1164 return gpr_offset + num_regs;
1165 }
1166
1167 /*
1168 * for evergreen we need to scan the shader to find the number of GPRs we need to
1169 * reserve for interpolation and system values
1170 *
1171 * we need to know if we are going to emit
1172 * any sample or centroid inputs
1173 * if perspective and linear are required
1174 */
1175 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1176 {
1177 unsigned i;
1178 int num_baryc;
1179 struct tgsi_parse_context parse;
1180
1181 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1182
1183 for (i = 0; i < ctx->info.num_inputs; i++) {
1184 int k;
1185 /* skip position/face/mask/sampleid */
1186 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1187 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1188 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1189 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1190 continue;
1191
1192 k = eg_get_interpolator_index(
1193 ctx->info.input_interpolate[i],
1194 ctx->info.input_interpolate_loc[i]);
1195 if (k >= 0)
1196 ctx->eg_interpolators[k].enabled = TRUE;
1197 }
1198
1199 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1200 return 0;
1201 }
1202
1203 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1204 while (!tgsi_parse_end_of_tokens(&parse)) {
1205 tgsi_parse_token(&parse);
1206
1207 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1208 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1209 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1210 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1211 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1212 {
1213 int interpolate, location, k;
1214
1215 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1216 location = TGSI_INTERPOLATE_LOC_CENTER;
1217 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1218 location = TGSI_INTERPOLATE_LOC_CENTER;
1219 } else {
1220 location = TGSI_INTERPOLATE_LOC_CENTROID;
1221 }
1222
1223 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1224 k = eg_get_interpolator_index(interpolate, location);
1225 if (k >= 0)
1226 ctx->eg_interpolators[k].enabled = true;
1227 }
1228 }
1229 }
1230
1231 tgsi_parse_free(&parse);
1232
1233 /* assign gpr to each interpolator according to priority */
1234 num_baryc = 0;
1235 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1236 if (ctx->eg_interpolators[i].enabled) {
1237 ctx->eg_interpolators[i].ij_index = num_baryc;
1238 num_baryc ++;
1239 }
1240 }
1241
1242 /* XXX PULL MODEL and LINE STIPPLE */
1243
1244 num_baryc = (num_baryc + 1) >> 1;
1245 return allocate_system_value_inputs(ctx, num_baryc);
1246 }
1247
1248 /* sample_id_sel == NULL means fetch for current sample */
1249 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1250 {
1251 struct r600_bytecode_vtx vtx;
1252 int r, t1;
1253
1254 assert(ctx->fixed_pt_position_gpr != -1);
1255
1256 t1 = r600_get_temp(ctx);
1257
1258 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1259 vtx.op = FETCH_OP_VFETCH;
1260 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1261 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1262 if (sample_id == NULL) {
1263 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1264 vtx.src_sel_x = 3;
1265 }
1266 else {
1267 struct r600_bytecode_alu alu;
1268
1269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1270 alu.op = ALU_OP1_MOV;
1271 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1272 alu.dst.sel = t1;
1273 alu.dst.write = 1;
1274 alu.last = 1;
1275 r = r600_bytecode_add_alu(ctx->bc, &alu);
1276 if (r)
1277 return r;
1278
1279 vtx.src_gpr = t1;
1280 vtx.src_sel_x = 0;
1281 }
1282 vtx.mega_fetch_count = 16;
1283 vtx.dst_gpr = t1;
1284 vtx.dst_sel_x = 0;
1285 vtx.dst_sel_y = 1;
1286 vtx.dst_sel_z = 2;
1287 vtx.dst_sel_w = 3;
1288 vtx.data_format = FMT_32_32_32_32_FLOAT;
1289 vtx.num_format_all = 2;
1290 vtx.format_comp_all = 1;
1291 vtx.use_const_fields = 0;
1292 vtx.offset = 1; // first element is size of buffer
1293 vtx.endian = r600_endian_swap(32);
1294 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1295
1296 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1297 if (r)
1298 return r;
1299
1300 return t1;
1301 }
1302
1303 static void tgsi_src(struct r600_shader_ctx *ctx,
1304 const struct tgsi_full_src_register *tgsi_src,
1305 struct r600_shader_src *r600_src)
1306 {
1307 memset(r600_src, 0, sizeof(*r600_src));
1308 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1309 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1310 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1311 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1312 r600_src->neg = tgsi_src->Register.Negate;
1313 r600_src->abs = tgsi_src->Register.Absolute;
1314
1315 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1316 int index;
1317 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1318 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1319 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1320
1321 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1322 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1323 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1324 return;
1325 }
1326 index = tgsi_src->Register.Index;
1327 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1328 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1329 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1330 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1331 r600_src->swizzle[0] = 2; // Z value
1332 r600_src->swizzle[1] = 2;
1333 r600_src->swizzle[2] = 2;
1334 r600_src->swizzle[3] = 2;
1335 r600_src->sel = ctx->face_gpr;
1336 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1337 r600_src->swizzle[0] = 3; // W value
1338 r600_src->swizzle[1] = 3;
1339 r600_src->swizzle[2] = 3;
1340 r600_src->swizzle[3] = 3;
1341 r600_src->sel = ctx->fixed_pt_position_gpr;
1342 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1343 r600_src->swizzle[0] = 0;
1344 r600_src->swizzle[1] = 1;
1345 r600_src->swizzle[2] = 4;
1346 r600_src->swizzle[3] = 4;
1347 r600_src->sel = load_sample_position(ctx, NULL, -1);
1348 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1349 r600_src->swizzle[0] = 3;
1350 r600_src->swizzle[1] = 3;
1351 r600_src->swizzle[2] = 3;
1352 r600_src->swizzle[3] = 3;
1353 r600_src->sel = 0;
1354 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1355 r600_src->swizzle[0] = 0;
1356 r600_src->swizzle[1] = 0;
1357 r600_src->swizzle[2] = 0;
1358 r600_src->swizzle[3] = 0;
1359 r600_src->sel = 0;
1360 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1361 r600_src->swizzle[0] = 3;
1362 r600_src->swizzle[1] = 3;
1363 r600_src->swizzle[2] = 3;
1364 r600_src->swizzle[3] = 3;
1365 r600_src->sel = 1;
1366 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1367 r600_src->swizzle[0] = 2;
1368 r600_src->swizzle[1] = 2;
1369 r600_src->swizzle[2] = 2;
1370 r600_src->swizzle[3] = 2;
1371 r600_src->sel = 0;
1372 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1373 r600_src->sel = 1;
1374 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1375 r600_src->sel = 3;
1376 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1377 r600_src->sel = 2;
1378 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1379 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1380 r600_src->sel = ctx->tess_input_info;
1381 r600_src->swizzle[0] = 2;
1382 r600_src->swizzle[1] = 2;
1383 r600_src->swizzle[2] = 2;
1384 r600_src->swizzle[3] = 2;
1385 } else {
1386 r600_src->sel = ctx->tess_input_info;
1387 r600_src->swizzle[0] = 3;
1388 r600_src->swizzle[1] = 3;
1389 r600_src->swizzle[2] = 3;
1390 r600_src->swizzle[3] = 3;
1391 }
1392 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1393 r600_src->sel = 0;
1394 r600_src->swizzle[0] = 0;
1395 r600_src->swizzle[1] = 0;
1396 r600_src->swizzle[2] = 0;
1397 r600_src->swizzle[3] = 0;
1398 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1399 r600_src->sel = 0;
1400 r600_src->swizzle[0] = 3;
1401 r600_src->swizzle[1] = 3;
1402 r600_src->swizzle[2] = 3;
1403 r600_src->swizzle[3] = 3;
1404 }
1405 } else {
1406 if (tgsi_src->Register.Indirect)
1407 r600_src->rel = V_SQ_REL_RELATIVE;
1408 r600_src->sel = tgsi_src->Register.Index;
1409 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1410 }
1411 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1412 if (tgsi_src->Register.Dimension) {
1413 r600_src->kc_bank = tgsi_src->Dimension.Index;
1414 if (tgsi_src->Dimension.Indirect) {
1415 r600_src->kc_rel = 1;
1416 }
1417 }
1418 }
1419 }
1420
1421 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1422 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1423 unsigned int dst_reg)
1424 {
1425 struct r600_bytecode_vtx vtx;
1426 unsigned int ar_reg;
1427 int r;
1428
1429 if (offset) {
1430 struct r600_bytecode_alu alu;
1431
1432 memset(&alu, 0, sizeof(alu));
1433
1434 alu.op = ALU_OP2_ADD_INT;
1435 alu.src[0].sel = ctx->bc->ar_reg;
1436 alu.src[0].chan = ar_chan;
1437
1438 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1439 alu.src[1].value = offset;
1440
1441 alu.dst.sel = dst_reg;
1442 alu.dst.chan = ar_chan;
1443 alu.dst.write = 1;
1444 alu.last = 1;
1445
1446 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1447 return r;
1448
1449 ar_reg = dst_reg;
1450 } else {
1451 ar_reg = ctx->bc->ar_reg;
1452 }
1453
1454 memset(&vtx, 0, sizeof(vtx));
1455 vtx.buffer_id = cb_idx;
1456 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1457 vtx.src_gpr = ar_reg;
1458 vtx.src_sel_x = ar_chan;
1459 vtx.mega_fetch_count = 16;
1460 vtx.dst_gpr = dst_reg;
1461 vtx.dst_sel_x = 0; /* SEL_X */
1462 vtx.dst_sel_y = 1; /* SEL_Y */
1463 vtx.dst_sel_z = 2; /* SEL_Z */
1464 vtx.dst_sel_w = 3; /* SEL_W */
1465 vtx.data_format = FMT_32_32_32_32_FLOAT;
1466 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1467 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1468 vtx.endian = r600_endian_swap(32);
1469 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1470
1471 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1472 return r;
1473
1474 return 0;
1475 }
1476
1477 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1478 {
1479 struct r600_bytecode_vtx vtx;
1480 int r;
1481 unsigned index = src->Register.Index;
1482 unsigned vtx_id = src->Dimension.Index;
1483 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1484 int offset_chan = vtx_id % 3;
1485 int t2 = 0;
1486
1487 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1488 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1489
1490 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1491 offset_chan = 3;
1492
1493 if (src->Dimension.Indirect || src->Register.Indirect)
1494 t2 = r600_get_temp(ctx);
1495
1496 if (src->Dimension.Indirect) {
1497 int treg[3];
1498 struct r600_bytecode_alu alu;
1499 int r, i;
1500 unsigned addr_reg;
1501 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1502 if (src->DimIndirect.Index > 0) {
1503 r = single_alu_op2(ctx, ALU_OP1_MOV,
1504 ctx->bc->ar_reg, 0,
1505 addr_reg, 0,
1506 0, 0);
1507 if (r)
1508 return r;
1509 }
1510 /*
1511 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1512 at least this is what fglrx seems to do. */
1513 for (i = 0; i < 3; i++) {
1514 treg[i] = r600_get_temp(ctx);
1515 }
1516 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1517
1518 for (i = 0; i < 3; i++) {
1519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1520 alu.op = ALU_OP1_MOV;
1521 alu.src[0].sel = ctx->gs_rotated_input[0];
1522 alu.src[0].chan = i == 2 ? 3 : i;
1523 alu.dst.sel = treg[i];
1524 alu.dst.chan = 0;
1525 alu.dst.write = 1;
1526 alu.last = 1;
1527 r = r600_bytecode_add_alu(ctx->bc, &alu);
1528 if (r)
1529 return r;
1530 }
1531 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1532 alu.op = ALU_OP1_MOV;
1533 alu.src[0].sel = treg[0];
1534 alu.src[0].rel = 1;
1535 alu.dst.sel = t2;
1536 alu.dst.write = 1;
1537 alu.last = 1;
1538 r = r600_bytecode_add_alu(ctx->bc, &alu);
1539 if (r)
1540 return r;
1541 offset_reg = t2;
1542 offset_chan = 0;
1543 }
1544
1545 if (src->Register.Indirect) {
1546 int addr_reg;
1547 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1548
1549 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1550
1551 /* pull the value from index_reg */
1552 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1553 t2, 1,
1554 addr_reg, 0,
1555 V_SQ_ALU_SRC_LITERAL, first);
1556 if (r)
1557 return r;
1558 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1559 t2, 0,
1560 t2, 1,
1561 V_SQ_ALU_SRC_LITERAL, 4,
1562 offset_reg, offset_chan);
1563 if (r)
1564 return r;
1565 offset_reg = t2;
1566 offset_chan = 0;
1567 index = src->Register.Index - first;
1568 }
1569
1570 memset(&vtx, 0, sizeof(vtx));
1571 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1572 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1573 vtx.src_gpr = offset_reg;
1574 vtx.src_sel_x = offset_chan;
1575 vtx.offset = index * 16; /*bytes*/
1576 vtx.mega_fetch_count = 16;
1577 vtx.dst_gpr = dst_reg;
1578 vtx.dst_sel_x = 0; /* SEL_X */
1579 vtx.dst_sel_y = 1; /* SEL_Y */
1580 vtx.dst_sel_z = 2; /* SEL_Z */
1581 vtx.dst_sel_w = 3; /* SEL_W */
1582 if (ctx->bc->chip_class >= EVERGREEN) {
1583 vtx.use_const_fields = 1;
1584 } else {
1585 vtx.data_format = FMT_32_32_32_32_FLOAT;
1586 }
1587
1588 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1589 return r;
1590
1591 return 0;
1592 }
1593
1594 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1595 {
1596 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1597 unsigned i;
1598
1599 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1600 struct tgsi_full_src_register *src = &inst->Src[i];
1601
1602 if (src->Register.File == TGSI_FILE_INPUT) {
1603 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1604 /* primitive id is in R0.z */
1605 ctx->src[i].sel = 0;
1606 ctx->src[i].swizzle[0] = 2;
1607 }
1608 }
1609 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1610 int treg = r600_get_temp(ctx);
1611
1612 fetch_gs_input(ctx, src, treg);
1613 ctx->src[i].sel = treg;
1614 ctx->src[i].rel = 0;
1615 }
1616 }
1617 return 0;
1618 }
1619
1620
1621 /* Tessellation shaders pass outputs to the next shader using LDS.
1622 *
1623 * LS outputs = TCS(HS) inputs
1624 * TCS(HS) outputs = TES(DS) inputs
1625 *
1626 * The LDS layout is:
1627 * - TCS inputs for patch 0
1628 * - TCS inputs for patch 1
1629 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1630 * - ...
1631 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1632 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1633 * - TCS outputs for patch 1
1634 * - Per-patch TCS outputs for patch 1
1635 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1636 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1637 * - ...
1638 *
1639 * All three shaders VS(LS), TCS, TES share the same LDS space.
1640 */
1641 /* this will return with the dw address in temp_reg.x */
1642 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1643 const struct tgsi_full_dst_register *dst,
1644 const struct tgsi_full_src_register *src,
1645 int stride_bytes_reg, int stride_bytes_chan)
1646 {
1647 struct tgsi_full_dst_register reg;
1648 ubyte *name, *index, *array_first;
1649 int r;
1650 int param;
1651 struct tgsi_shader_info *info = &ctx->info;
1652 /* Set the register description. The address computation is the same
1653 * for sources and destinations. */
1654 if (src) {
1655 reg.Register.File = src->Register.File;
1656 reg.Register.Index = src->Register.Index;
1657 reg.Register.Indirect = src->Register.Indirect;
1658 reg.Register.Dimension = src->Register.Dimension;
1659 reg.Indirect = src->Indirect;
1660 reg.Dimension = src->Dimension;
1661 reg.DimIndirect = src->DimIndirect;
1662 } else
1663 reg = *dst;
1664
1665 /* If the register is 2-dimensional (e.g. an array of vertices
1666 * in a primitive), calculate the base address of the vertex. */
1667 if (reg.Register.Dimension) {
1668 int sel, chan;
1669 if (reg.Dimension.Indirect) {
1670 unsigned addr_reg;
1671 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1672
1673 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1674 /* pull the value from index_reg */
1675 sel = addr_reg;
1676 chan = 0;
1677 } else {
1678 sel = V_SQ_ALU_SRC_LITERAL;
1679 chan = reg.Dimension.Index;
1680 }
1681
1682 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1683 temp_reg, 0,
1684 stride_bytes_reg, stride_bytes_chan,
1685 sel, chan,
1686 temp_reg, 0);
1687 if (r)
1688 return r;
1689 }
1690
1691 if (reg.Register.File == TGSI_FILE_INPUT) {
1692 name = info->input_semantic_name;
1693 index = info->input_semantic_index;
1694 array_first = info->input_array_first;
1695 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1696 name = info->output_semantic_name;
1697 index = info->output_semantic_index;
1698 array_first = info->output_array_first;
1699 } else {
1700 assert(0);
1701 return -1;
1702 }
1703 if (reg.Register.Indirect) {
1704 int addr_reg;
1705 int first;
1706 /* Add the relative address of the element. */
1707 if (reg.Indirect.ArrayID)
1708 first = array_first[reg.Indirect.ArrayID];
1709 else
1710 first = reg.Register.Index;
1711
1712 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1713
1714 /* pull the value from index_reg */
1715 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1716 temp_reg, 0,
1717 V_SQ_ALU_SRC_LITERAL, 16,
1718 addr_reg, 0,
1719 temp_reg, 0);
1720 if (r)
1721 return r;
1722
1723 param = r600_get_lds_unique_index(name[first],
1724 index[first]);
1725
1726 } else {
1727 param = r600_get_lds_unique_index(name[reg.Register.Index],
1728 index[reg.Register.Index]);
1729 }
1730
1731 /* add to base_addr - passed in temp_reg.x */
1732 if (param) {
1733 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1734 temp_reg, 0,
1735 temp_reg, 0,
1736 V_SQ_ALU_SRC_LITERAL, param * 16);
1737 if (r)
1738 return r;
1739
1740 }
1741 return 0;
1742 }
1743
1744 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1745 unsigned dst_reg)
1746 {
1747 struct r600_bytecode_alu alu;
1748 int r, i;
1749
1750 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1751 ctx->bc->force_add_cf = 1;
1752 for (i = 1; i < 4; i++) {
1753 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1754 temp_reg, i,
1755 temp_reg, 0,
1756 V_SQ_ALU_SRC_LITERAL, 4 * i);
1757 if (r)
1758 return r;
1759 }
1760 for (i = 0; i < 4; i++) {
1761 /* emit an LDS_READ_RET */
1762 memset(&alu, 0, sizeof(alu));
1763 alu.op = LDS_OP1_LDS_READ_RET;
1764 alu.src[0].sel = temp_reg;
1765 alu.src[0].chan = i;
1766 alu.src[1].sel = V_SQ_ALU_SRC_0;
1767 alu.src[2].sel = V_SQ_ALU_SRC_0;
1768 alu.dst.chan = 0;
1769 alu.is_lds_idx_op = true;
1770 alu.last = 1;
1771 r = r600_bytecode_add_alu(ctx->bc, &alu);
1772 if (r)
1773 return r;
1774 }
1775 for (i = 0; i < 4; i++) {
1776 /* then read from LDS_OQ_A_POP */
1777 memset(&alu, 0, sizeof(alu));
1778
1779 alu.op = ALU_OP1_MOV;
1780 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1781 alu.src[0].chan = 0;
1782 alu.dst.sel = dst_reg;
1783 alu.dst.chan = i;
1784 alu.dst.write = 1;
1785 alu.last = 1;
1786 r = r600_bytecode_add_alu(ctx->bc, &alu);
1787 if (r)
1788 return r;
1789 }
1790 return 0;
1791 }
1792
1793 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1794 {
1795 int r;
1796 unsigned temp_reg = r600_get_temp(ctx);
1797
1798 r = get_lds_offset0(ctx, 2, temp_reg,
1799 src->Register.Dimension ? false : true);
1800 if (r)
1801 return r;
1802
1803 /* the base address is now in temp.x */
1804 r = r600_get_byte_address(ctx, temp_reg,
1805 NULL, src, ctx->tess_output_info, 1);
1806 if (r)
1807 return r;
1808
1809 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1810 if (r)
1811 return r;
1812 return 0;
1813 }
1814
1815 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1816 {
1817 int r;
1818 unsigned temp_reg = r600_get_temp(ctx);
1819
1820 /* t.x = ips * r0.y */
1821 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1822 temp_reg, 0,
1823 ctx->tess_input_info, 0,
1824 0, 1);
1825
1826 if (r)
1827 return r;
1828
1829 /* the base address is now in temp.x */
1830 r = r600_get_byte_address(ctx, temp_reg,
1831 NULL, src, ctx->tess_input_info, 1);
1832 if (r)
1833 return r;
1834
1835 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1836 if (r)
1837 return r;
1838 return 0;
1839 }
1840
1841 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1842 {
1843 int r;
1844 unsigned temp_reg = r600_get_temp(ctx);
1845
1846 r = get_lds_offset0(ctx, 1, temp_reg,
1847 src->Register.Dimension ? false : true);
1848 if (r)
1849 return r;
1850 /* the base address is now in temp.x */
1851 r = r600_get_byte_address(ctx, temp_reg,
1852 NULL, src,
1853 ctx->tess_output_info, 1);
1854 if (r)
1855 return r;
1856
1857 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1858 if (r)
1859 return r;
1860 return 0;
1861 }
1862
1863 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1864 {
1865 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1866 unsigned i;
1867
1868 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1869 struct tgsi_full_src_register *src = &inst->Src[i];
1870
1871 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1872 int treg = r600_get_temp(ctx);
1873 fetch_tes_input(ctx, src, treg);
1874 ctx->src[i].sel = treg;
1875 ctx->src[i].rel = 0;
1876 }
1877 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1878 int treg = r600_get_temp(ctx);
1879 fetch_tcs_input(ctx, src, treg);
1880 ctx->src[i].sel = treg;
1881 ctx->src[i].rel = 0;
1882 }
1883 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1884 int treg = r600_get_temp(ctx);
1885 fetch_tcs_output(ctx, src, treg);
1886 ctx->src[i].sel = treg;
1887 ctx->src[i].rel = 0;
1888 }
1889 }
1890 return 0;
1891 }
1892
1893 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1894 {
1895 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1896 struct r600_bytecode_alu alu;
1897 int i, j, k, nconst, r;
1898
1899 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1900 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1901 nconst++;
1902 }
1903 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1904 }
1905 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1906 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1907 continue;
1908 }
1909
1910 if (ctx->src[i].rel) {
1911 int chan = inst->Src[i].Indirect.Swizzle;
1912 int treg = r600_get_temp(ctx);
1913 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1914 return r;
1915
1916 ctx->src[i].kc_bank = 0;
1917 ctx->src[i].kc_rel = 0;
1918 ctx->src[i].sel = treg;
1919 ctx->src[i].rel = 0;
1920 j--;
1921 } else if (j > 0) {
1922 int treg = r600_get_temp(ctx);
1923 for (k = 0; k < 4; k++) {
1924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1925 alu.op = ALU_OP1_MOV;
1926 alu.src[0].sel = ctx->src[i].sel;
1927 alu.src[0].chan = k;
1928 alu.src[0].rel = ctx->src[i].rel;
1929 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1930 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1931 alu.dst.sel = treg;
1932 alu.dst.chan = k;
1933 alu.dst.write = 1;
1934 if (k == 3)
1935 alu.last = 1;
1936 r = r600_bytecode_add_alu(ctx->bc, &alu);
1937 if (r)
1938 return r;
1939 }
1940 ctx->src[i].sel = treg;
1941 ctx->src[i].rel =0;
1942 j--;
1943 }
1944 }
1945 return 0;
1946 }
1947
1948 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1949 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1950 {
1951 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1952 struct r600_bytecode_alu alu;
1953 int i, j, k, nliteral, r;
1954
1955 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1956 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1957 nliteral++;
1958 }
1959 }
1960 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1961 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1962 int treg = r600_get_temp(ctx);
1963 for (k = 0; k < 4; k++) {
1964 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1965 alu.op = ALU_OP1_MOV;
1966 alu.src[0].sel = ctx->src[i].sel;
1967 alu.src[0].chan = k;
1968 alu.src[0].value = ctx->src[i].value[k];
1969 alu.dst.sel = treg;
1970 alu.dst.chan = k;
1971 alu.dst.write = 1;
1972 if (k == 3)
1973 alu.last = 1;
1974 r = r600_bytecode_add_alu(ctx->bc, &alu);
1975 if (r)
1976 return r;
1977 }
1978 ctx->src[i].sel = treg;
1979 j--;
1980 }
1981 }
1982 return 0;
1983 }
1984
1985 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1986 {
1987 int i, r, count = ctx->shader->ninput;
1988
1989 for (i = 0; i < count; i++) {
1990 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1991 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1992 if (r)
1993 return r;
1994 }
1995 }
1996 return 0;
1997 }
1998
1999 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2000 int stream, unsigned *stream_item_size)
2001 {
2002 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2003 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2004 int i, j, r;
2005
2006 /* Sanity checking. */
2007 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2008 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2009 r = -EINVAL;
2010 goto out_err;
2011 }
2012 for (i = 0; i < so->num_outputs; i++) {
2013 if (so->output[i].output_buffer >= 4) {
2014 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2015 so->output[i].output_buffer);
2016 r = -EINVAL;
2017 goto out_err;
2018 }
2019 }
2020
2021 /* Initialize locations where the outputs are stored. */
2022 for (i = 0; i < so->num_outputs; i++) {
2023
2024 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2025 start_comp[i] = so->output[i].start_component;
2026 /* Lower outputs with dst_offset < start_component.
2027 *
2028 * We can only output 4D vectors with a write mask, e.g. we can
2029 * only output the W component at offset 3, etc. If we want
2030 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2031 * to move it to X and output X. */
2032 if (so->output[i].dst_offset < so->output[i].start_component) {
2033 unsigned tmp = r600_get_temp(ctx);
2034
2035 for (j = 0; j < so->output[i].num_components; j++) {
2036 struct r600_bytecode_alu alu;
2037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2038 alu.op = ALU_OP1_MOV;
2039 alu.src[0].sel = so_gpr[i];
2040 alu.src[0].chan = so->output[i].start_component + j;
2041
2042 alu.dst.sel = tmp;
2043 alu.dst.chan = j;
2044 alu.dst.write = 1;
2045 if (j == so->output[i].num_components - 1)
2046 alu.last = 1;
2047 r = r600_bytecode_add_alu(ctx->bc, &alu);
2048 if (r)
2049 return r;
2050 }
2051 start_comp[i] = 0;
2052 so_gpr[i] = tmp;
2053 }
2054 }
2055
2056 /* Write outputs to buffers. */
2057 for (i = 0; i < so->num_outputs; i++) {
2058 struct r600_bytecode_output output;
2059
2060 if (stream != -1 && stream != so->output[i].output_buffer)
2061 continue;
2062
2063 memset(&output, 0, sizeof(struct r600_bytecode_output));
2064 output.gpr = so_gpr[i];
2065 output.elem_size = so->output[i].num_components - 1;
2066 if (output.elem_size == 2)
2067 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2068 output.array_base = so->output[i].dst_offset - start_comp[i];
2069 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2070 output.burst_count = 1;
2071 /* array_size is an upper limit for the burst_count
2072 * with MEM_STREAM instructions */
2073 output.array_size = 0xFFF;
2074 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2075
2076 if (ctx->bc->chip_class >= EVERGREEN) {
2077 switch (so->output[i].output_buffer) {
2078 case 0:
2079 output.op = CF_OP_MEM_STREAM0_BUF0;
2080 break;
2081 case 1:
2082 output.op = CF_OP_MEM_STREAM0_BUF1;
2083 break;
2084 case 2:
2085 output.op = CF_OP_MEM_STREAM0_BUF2;
2086 break;
2087 case 3:
2088 output.op = CF_OP_MEM_STREAM0_BUF3;
2089 break;
2090 }
2091 output.op += so->output[i].stream * 4;
2092 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2093 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2094 } else {
2095 switch (so->output[i].output_buffer) {
2096 case 0:
2097 output.op = CF_OP_MEM_STREAM0;
2098 break;
2099 case 1:
2100 output.op = CF_OP_MEM_STREAM1;
2101 break;
2102 case 2:
2103 output.op = CF_OP_MEM_STREAM2;
2104 break;
2105 case 3:
2106 output.op = CF_OP_MEM_STREAM3;
2107 break;
2108 }
2109 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2110 }
2111 r = r600_bytecode_add_output(ctx->bc, &output);
2112 if (r)
2113 goto out_err;
2114 }
2115 return 0;
2116 out_err:
2117 return r;
2118 }
2119
2120 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2121 {
2122 struct r600_bytecode_alu alu;
2123 unsigned reg;
2124
2125 if (!ctx->shader->vs_out_edgeflag)
2126 return;
2127
2128 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2129
2130 /* clamp(x, 0, 1) */
2131 memset(&alu, 0, sizeof(alu));
2132 alu.op = ALU_OP1_MOV;
2133 alu.src[0].sel = reg;
2134 alu.dst.sel = reg;
2135 alu.dst.write = 1;
2136 alu.dst.clamp = 1;
2137 alu.last = 1;
2138 r600_bytecode_add_alu(ctx->bc, &alu);
2139
2140 memset(&alu, 0, sizeof(alu));
2141 alu.op = ALU_OP1_FLT_TO_INT;
2142 alu.src[0].sel = reg;
2143 alu.dst.sel = reg;
2144 alu.dst.write = 1;
2145 alu.last = 1;
2146 r600_bytecode_add_alu(ctx->bc, &alu);
2147 }
2148
2149 static int generate_gs_copy_shader(struct r600_context *rctx,
2150 struct r600_pipe_shader *gs,
2151 struct pipe_stream_output_info *so)
2152 {
2153 struct r600_shader_ctx ctx = {};
2154 struct r600_shader *gs_shader = &gs->shader;
2155 struct r600_pipe_shader *cshader;
2156 int ocnt = gs_shader->noutput;
2157 struct r600_bytecode_alu alu;
2158 struct r600_bytecode_vtx vtx;
2159 struct r600_bytecode_output output;
2160 struct r600_bytecode_cf *cf_jump, *cf_pop,
2161 *last_exp_pos = NULL, *last_exp_param = NULL;
2162 int i, j, next_clip_pos = 61, next_param = 0;
2163 int ring;
2164 bool only_ring_0 = true;
2165 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2166 if (!cshader)
2167 return 0;
2168
2169 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2170 sizeof(struct r600_shader_io));
2171
2172 cshader->shader.noutput = ocnt;
2173
2174 ctx.shader = &cshader->shader;
2175 ctx.bc = &ctx.shader->bc;
2176 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2177
2178 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2179 rctx->screen->has_compressed_msaa_texturing);
2180
2181 ctx.bc->isa = rctx->isa;
2182
2183 cf_jump = NULL;
2184 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2185
2186 /* R0.x = R0.x & 0x3fffffff */
2187 memset(&alu, 0, sizeof(alu));
2188 alu.op = ALU_OP2_AND_INT;
2189 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2190 alu.src[1].value = 0x3fffffff;
2191 alu.dst.write = 1;
2192 r600_bytecode_add_alu(ctx.bc, &alu);
2193
2194 /* R0.y = R0.x >> 30 */
2195 memset(&alu, 0, sizeof(alu));
2196 alu.op = ALU_OP2_LSHR_INT;
2197 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2198 alu.src[1].value = 0x1e;
2199 alu.dst.chan = 1;
2200 alu.dst.write = 1;
2201 alu.last = 1;
2202 r600_bytecode_add_alu(ctx.bc, &alu);
2203
2204 /* fetch vertex data from GSVS ring */
2205 for (i = 0; i < ocnt; ++i) {
2206 struct r600_shader_io *out = &ctx.shader->output[i];
2207
2208 out->gpr = i + 1;
2209 out->ring_offset = i * 16;
2210
2211 memset(&vtx, 0, sizeof(vtx));
2212 vtx.op = FETCH_OP_VFETCH;
2213 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2214 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2215 vtx.mega_fetch_count = 16;
2216 vtx.offset = out->ring_offset;
2217 vtx.dst_gpr = out->gpr;
2218 vtx.src_gpr = 0;
2219 vtx.dst_sel_x = 0;
2220 vtx.dst_sel_y = 1;
2221 vtx.dst_sel_z = 2;
2222 vtx.dst_sel_w = 3;
2223 if (rctx->b.chip_class >= EVERGREEN) {
2224 vtx.use_const_fields = 1;
2225 } else {
2226 vtx.data_format = FMT_32_32_32_32_FLOAT;
2227 }
2228
2229 r600_bytecode_add_vtx(ctx.bc, &vtx);
2230 }
2231 ctx.temp_reg = i + 1;
2232 for (ring = 3; ring >= 0; --ring) {
2233 bool enabled = false;
2234 for (i = 0; i < so->num_outputs; i++) {
2235 if (so->output[i].stream == ring) {
2236 enabled = true;
2237 if (ring > 0)
2238 only_ring_0 = false;
2239 break;
2240 }
2241 }
2242 if (ring != 0 && !enabled) {
2243 cshader->shader.ring_item_sizes[ring] = 0;
2244 continue;
2245 }
2246
2247 if (cf_jump) {
2248 // Patch up jump label
2249 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2250 cf_pop = ctx.bc->cf_last;
2251
2252 cf_jump->cf_addr = cf_pop->id + 2;
2253 cf_jump->pop_count = 1;
2254 cf_pop->cf_addr = cf_pop->id + 2;
2255 cf_pop->pop_count = 1;
2256 }
2257
2258 /* PRED_SETE_INT __, R0.y, ring */
2259 memset(&alu, 0, sizeof(alu));
2260 alu.op = ALU_OP2_PRED_SETE_INT;
2261 alu.src[0].chan = 1;
2262 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2263 alu.src[1].value = ring;
2264 alu.execute_mask = 1;
2265 alu.update_pred = 1;
2266 alu.last = 1;
2267 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2268
2269 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2270 cf_jump = ctx.bc->cf_last;
2271
2272 if (enabled)
2273 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2274 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2275 }
2276
2277 /* bc adds nops - copy it */
2278 if (ctx.bc->chip_class == R600) {
2279 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2280 alu.op = ALU_OP0_NOP;
2281 alu.last = 1;
2282 r600_bytecode_add_alu(ctx.bc, &alu);
2283
2284 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2285 }
2286
2287 /* export vertex data */
2288 /* XXX factor out common code with r600_shader_from_tgsi ? */
2289 for (i = 0; i < ocnt; ++i) {
2290 struct r600_shader_io *out = &ctx.shader->output[i];
2291 bool instream0 = true;
2292 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2293 continue;
2294
2295 for (j = 0; j < so->num_outputs; j++) {
2296 if (so->output[j].register_index == i) {
2297 if (so->output[j].stream == 0)
2298 break;
2299 if (so->output[j].stream > 0)
2300 instream0 = false;
2301 }
2302 }
2303 if (!instream0)
2304 continue;
2305 memset(&output, 0, sizeof(output));
2306 output.gpr = out->gpr;
2307 output.elem_size = 3;
2308 output.swizzle_x = 0;
2309 output.swizzle_y = 1;
2310 output.swizzle_z = 2;
2311 output.swizzle_w = 3;
2312 output.burst_count = 1;
2313 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2314 output.op = CF_OP_EXPORT;
2315 switch (out->name) {
2316 case TGSI_SEMANTIC_POSITION:
2317 output.array_base = 60;
2318 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2319 break;
2320
2321 case TGSI_SEMANTIC_PSIZE:
2322 output.array_base = 61;
2323 if (next_clip_pos == 61)
2324 next_clip_pos = 62;
2325 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2326 output.swizzle_y = 7;
2327 output.swizzle_z = 7;
2328 output.swizzle_w = 7;
2329 ctx.shader->vs_out_misc_write = 1;
2330 ctx.shader->vs_out_point_size = 1;
2331 break;
2332 case TGSI_SEMANTIC_LAYER:
2333 if (out->spi_sid) {
2334 /* duplicate it as PARAM to pass to the pixel shader */
2335 output.array_base = next_param++;
2336 r600_bytecode_add_output(ctx.bc, &output);
2337 last_exp_param = ctx.bc->cf_last;
2338 }
2339 output.array_base = 61;
2340 if (next_clip_pos == 61)
2341 next_clip_pos = 62;
2342 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2343 output.swizzle_x = 7;
2344 output.swizzle_y = 7;
2345 output.swizzle_z = 0;
2346 output.swizzle_w = 7;
2347 ctx.shader->vs_out_misc_write = 1;
2348 ctx.shader->vs_out_layer = 1;
2349 break;
2350 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2351 if (out->spi_sid) {
2352 /* duplicate it as PARAM to pass to the pixel shader */
2353 output.array_base = next_param++;
2354 r600_bytecode_add_output(ctx.bc, &output);
2355 last_exp_param = ctx.bc->cf_last;
2356 }
2357 output.array_base = 61;
2358 if (next_clip_pos == 61)
2359 next_clip_pos = 62;
2360 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2361 ctx.shader->vs_out_misc_write = 1;
2362 ctx.shader->vs_out_viewport = 1;
2363 output.swizzle_x = 7;
2364 output.swizzle_y = 7;
2365 output.swizzle_z = 7;
2366 output.swizzle_w = 0;
2367 break;
2368 case TGSI_SEMANTIC_CLIPDIST:
2369 /* spi_sid is 0 for clipdistance outputs that were generated
2370 * for clipvertex - we don't need to pass them to PS */
2371 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2372 if (out->spi_sid) {
2373 /* duplicate it as PARAM to pass to the pixel shader */
2374 output.array_base = next_param++;
2375 r600_bytecode_add_output(ctx.bc, &output);
2376 last_exp_param = ctx.bc->cf_last;
2377 }
2378 output.array_base = next_clip_pos++;
2379 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2380 break;
2381 case TGSI_SEMANTIC_FOG:
2382 output.swizzle_y = 4; /* 0 */
2383 output.swizzle_z = 4; /* 0 */
2384 output.swizzle_w = 5; /* 1 */
2385 break;
2386 default:
2387 output.array_base = next_param++;
2388 break;
2389 }
2390 r600_bytecode_add_output(ctx.bc, &output);
2391 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2392 last_exp_param = ctx.bc->cf_last;
2393 else
2394 last_exp_pos = ctx.bc->cf_last;
2395 }
2396
2397 if (!last_exp_pos) {
2398 memset(&output, 0, sizeof(output));
2399 output.gpr = 0;
2400 output.elem_size = 3;
2401 output.swizzle_x = 7;
2402 output.swizzle_y = 7;
2403 output.swizzle_z = 7;
2404 output.swizzle_w = 7;
2405 output.burst_count = 1;
2406 output.type = 2;
2407 output.op = CF_OP_EXPORT;
2408 output.array_base = 60;
2409 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2410 r600_bytecode_add_output(ctx.bc, &output);
2411 last_exp_pos = ctx.bc->cf_last;
2412 }
2413
2414 if (!last_exp_param) {
2415 memset(&output, 0, sizeof(output));
2416 output.gpr = 0;
2417 output.elem_size = 3;
2418 output.swizzle_x = 7;
2419 output.swizzle_y = 7;
2420 output.swizzle_z = 7;
2421 output.swizzle_w = 7;
2422 output.burst_count = 1;
2423 output.type = 2;
2424 output.op = CF_OP_EXPORT;
2425 output.array_base = next_param++;
2426 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2427 r600_bytecode_add_output(ctx.bc, &output);
2428 last_exp_param = ctx.bc->cf_last;
2429 }
2430
2431 last_exp_pos->op = CF_OP_EXPORT_DONE;
2432 last_exp_param->op = CF_OP_EXPORT_DONE;
2433
2434 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2435 cf_pop = ctx.bc->cf_last;
2436
2437 cf_jump->cf_addr = cf_pop->id + 2;
2438 cf_jump->pop_count = 1;
2439 cf_pop->cf_addr = cf_pop->id + 2;
2440 cf_pop->pop_count = 1;
2441
2442 if (ctx.bc->chip_class == CAYMAN)
2443 cm_bytecode_add_cf_end(ctx.bc);
2444 else {
2445 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2446 ctx.bc->cf_last->end_of_program = 1;
2447 }
2448
2449 gs->gs_copy_shader = cshader;
2450 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2451
2452 ctx.bc->nstack = 1;
2453
2454 return r600_bytecode_build(ctx.bc);
2455 }
2456
2457 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2458 {
2459 if (ind) {
2460 struct r600_bytecode_alu alu;
2461 int r;
2462
2463 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2464 alu.op = ALU_OP2_ADD_INT;
2465 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2466 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2467 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2468 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2469 alu.dst.write = 1;
2470 alu.last = 1;
2471 r = r600_bytecode_add_alu(ctx->bc, &alu);
2472 if (r)
2473 return r;
2474 }
2475 return 0;
2476 }
2477
2478 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2479 {
2480 struct r600_bytecode_output output;
2481 int i, k, ring_offset;
2482 int effective_stream = stream == -1 ? 0 : stream;
2483 int idx = 0;
2484
2485 for (i = 0; i < ctx->shader->noutput; i++) {
2486 if (ctx->gs_for_vs) {
2487 /* for ES we need to lookup corresponding ring offset expected by GS
2488 * (map this output to GS input by name and sid) */
2489 /* FIXME precompute offsets */
2490 ring_offset = -1;
2491 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2492 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2493 struct r600_shader_io *out = &ctx->shader->output[i];
2494 if (in->name == out->name && in->sid == out->sid)
2495 ring_offset = in->ring_offset;
2496 }
2497
2498 if (ring_offset == -1)
2499 continue;
2500 } else {
2501 ring_offset = idx * 16;
2502 idx++;
2503 }
2504
2505 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2506 continue;
2507 /* next_ring_offset after parsing input decls contains total size of
2508 * single vertex data, gs_next_vertex - current vertex index */
2509 if (!ind)
2510 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2511
2512 memset(&output, 0, sizeof(struct r600_bytecode_output));
2513 output.gpr = ctx->shader->output[i].gpr;
2514 output.elem_size = 3;
2515 output.comp_mask = 0xF;
2516 output.burst_count = 1;
2517
2518 if (ind)
2519 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2520 else
2521 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2522
2523 switch (stream) {
2524 default:
2525 case 0:
2526 output.op = CF_OP_MEM_RING; break;
2527 case 1:
2528 output.op = CF_OP_MEM_RING1; break;
2529 case 2:
2530 output.op = CF_OP_MEM_RING2; break;
2531 case 3:
2532 output.op = CF_OP_MEM_RING3; break;
2533 }
2534
2535 if (ind) {
2536 output.array_base = ring_offset >> 2; /* in dwords */
2537 output.array_size = 0xfff;
2538 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2539 } else
2540 output.array_base = ring_offset >> 2; /* in dwords */
2541 r600_bytecode_add_output(ctx->bc, &output);
2542 }
2543
2544 ++ctx->gs_next_vertex;
2545 return 0;
2546 }
2547
2548
2549 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2550 {
2551 int r;
2552 struct r600_bytecode_vtx vtx;
2553 int temp_val = ctx->temp_reg;
2554 /* need to store the TCS output somewhere */
2555 r = single_alu_op2(ctx, ALU_OP1_MOV,
2556 temp_val, 0,
2557 V_SQ_ALU_SRC_LITERAL, 0,
2558 0, 0);
2559 if (r)
2560 return r;
2561
2562 /* used by VS/TCS */
2563 if (ctx->tess_input_info) {
2564 /* fetch tcs input values into resv space */
2565 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2566 vtx.op = FETCH_OP_VFETCH;
2567 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2568 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2569 vtx.mega_fetch_count = 16;
2570 vtx.data_format = FMT_32_32_32_32;
2571 vtx.num_format_all = 2;
2572 vtx.format_comp_all = 1;
2573 vtx.use_const_fields = 0;
2574 vtx.endian = r600_endian_swap(32);
2575 vtx.srf_mode_all = 1;
2576 vtx.offset = 0;
2577 vtx.dst_gpr = ctx->tess_input_info;
2578 vtx.dst_sel_x = 0;
2579 vtx.dst_sel_y = 1;
2580 vtx.dst_sel_z = 2;
2581 vtx.dst_sel_w = 3;
2582 vtx.src_gpr = temp_val;
2583 vtx.src_sel_x = 0;
2584
2585 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2586 if (r)
2587 return r;
2588 }
2589
2590 /* used by TCS/TES */
2591 if (ctx->tess_output_info) {
2592 /* fetch tcs output values into resv space */
2593 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2594 vtx.op = FETCH_OP_VFETCH;
2595 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2596 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2597 vtx.mega_fetch_count = 16;
2598 vtx.data_format = FMT_32_32_32_32;
2599 vtx.num_format_all = 2;
2600 vtx.format_comp_all = 1;
2601 vtx.use_const_fields = 0;
2602 vtx.endian = r600_endian_swap(32);
2603 vtx.srf_mode_all = 1;
2604 vtx.offset = 16;
2605 vtx.dst_gpr = ctx->tess_output_info;
2606 vtx.dst_sel_x = 0;
2607 vtx.dst_sel_y = 1;
2608 vtx.dst_sel_z = 2;
2609 vtx.dst_sel_w = 3;
2610 vtx.src_gpr = temp_val;
2611 vtx.src_sel_x = 0;
2612
2613 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2614 if (r)
2615 return r;
2616 }
2617 return 0;
2618 }
2619
2620 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2621 {
2622 int i, j, r;
2623 int temp_reg;
2624
2625 /* fetch tcs input values into input_vals */
2626 ctx->tess_input_info = r600_get_temp(ctx);
2627 ctx->tess_output_info = 0;
2628 r = r600_fetch_tess_io_info(ctx);
2629 if (r)
2630 return r;
2631
2632 temp_reg = r600_get_temp(ctx);
2633 /* dst reg contains LDS address stride * idx */
2634 /* MUL vertexID, vertex_dw_stride */
2635 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2636 temp_reg, 0,
2637 ctx->tess_input_info, 1,
2638 0, 1); /* rel id in r0.y? */
2639 if (r)
2640 return r;
2641
2642 for (i = 0; i < ctx->shader->noutput; i++) {
2643 struct r600_bytecode_alu alu;
2644 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2645
2646 if (param) {
2647 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2648 temp_reg, 1,
2649 temp_reg, 0,
2650 V_SQ_ALU_SRC_LITERAL, param * 16);
2651 if (r)
2652 return r;
2653 }
2654
2655 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2656 temp_reg, 2,
2657 temp_reg, param ? 1 : 0,
2658 V_SQ_ALU_SRC_LITERAL, 8);
2659 if (r)
2660 return r;
2661
2662
2663 for (j = 0; j < 2; j++) {
2664 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2665 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2666 alu.op = LDS_OP3_LDS_WRITE_REL;
2667 alu.src[0].sel = temp_reg;
2668 alu.src[0].chan = chan;
2669 alu.src[1].sel = ctx->shader->output[i].gpr;
2670 alu.src[1].chan = j * 2;
2671 alu.src[2].sel = ctx->shader->output[i].gpr;
2672 alu.src[2].chan = (j * 2) + 1;
2673 alu.last = 1;
2674 alu.dst.chan = 0;
2675 alu.lds_idx = 1;
2676 alu.is_lds_idx_op = true;
2677 r = r600_bytecode_add_alu(ctx->bc, &alu);
2678 if (r)
2679 return r;
2680 }
2681 }
2682 return 0;
2683 }
2684
2685 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2686 {
2687 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2688 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2689 int i, r, lasti;
2690 int temp_reg = r600_get_temp(ctx);
2691 struct r600_bytecode_alu alu;
2692 unsigned write_mask = dst->Register.WriteMask;
2693
2694 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2695 return 0;
2696
2697 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2698 if (r)
2699 return r;
2700
2701 /* the base address is now in temp.x */
2702 r = r600_get_byte_address(ctx, temp_reg,
2703 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2704 if (r)
2705 return r;
2706
2707 /* LDS write */
2708 lasti = tgsi_last_instruction(write_mask);
2709 for (i = 1; i <= lasti; i++) {
2710
2711 if (!(write_mask & (1 << i)))
2712 continue;
2713 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2714 temp_reg, i,
2715 temp_reg, 0,
2716 V_SQ_ALU_SRC_LITERAL, 4 * i);
2717 if (r)
2718 return r;
2719 }
2720
2721 for (i = 0; i <= lasti; i++) {
2722 if (!(write_mask & (1 << i)))
2723 continue;
2724
2725 if ((i == 0 && ((write_mask & 3) == 3)) ||
2726 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2727 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2728 alu.op = LDS_OP3_LDS_WRITE_REL;
2729 alu.src[0].sel = temp_reg;
2730 alu.src[0].chan = i;
2731
2732 alu.src[1].sel = dst->Register.Index;
2733 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2734 alu.src[1].chan = i;
2735
2736 alu.src[2].sel = dst->Register.Index;
2737 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2738 alu.src[2].chan = i + 1;
2739 alu.lds_idx = 1;
2740 alu.dst.chan = 0;
2741 alu.last = 1;
2742 alu.is_lds_idx_op = true;
2743 r = r600_bytecode_add_alu(ctx->bc, &alu);
2744 if (r)
2745 return r;
2746 i += 1;
2747 continue;
2748 }
2749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2750 alu.op = LDS_OP2_LDS_WRITE;
2751 alu.src[0].sel = temp_reg;
2752 alu.src[0].chan = i;
2753
2754 alu.src[1].sel = dst->Register.Index;
2755 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2756 alu.src[1].chan = i;
2757
2758 alu.src[2].sel = V_SQ_ALU_SRC_0;
2759 alu.dst.chan = 0;
2760 alu.last = 1;
2761 alu.is_lds_idx_op = true;
2762 r = r600_bytecode_add_alu(ctx->bc, &alu);
2763 if (r)
2764 return r;
2765 }
2766 return 0;
2767 }
2768
2769 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2770 int output_idx)
2771 {
2772 int param;
2773 unsigned temp_reg = r600_get_temp(ctx);
2774 unsigned name = ctx->shader->output[output_idx].name;
2775 int dreg = ctx->shader->output[output_idx].gpr;
2776 int r;
2777
2778 param = r600_get_lds_unique_index(name, 0);
2779 r = get_lds_offset0(ctx, 1, temp_reg, true);
2780 if (r)
2781 return r;
2782
2783 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2784 temp_reg, 0,
2785 temp_reg, 0,
2786 V_SQ_ALU_SRC_LITERAL, param * 16);
2787 if (r)
2788 return r;
2789
2790 do_lds_fetch_values(ctx, temp_reg, dreg);
2791 return 0;
2792 }
2793
2794 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2795 {
2796 unsigned i;
2797 int stride, outer_comps, inner_comps;
2798 int tessinner_idx = -1, tessouter_idx = -1;
2799 int r;
2800 int temp_reg = r600_get_temp(ctx);
2801 int treg[3] = {-1, -1, -1};
2802 struct r600_bytecode_alu alu;
2803 struct r600_bytecode_cf *cf_jump, *cf_pop;
2804
2805 /* only execute factor emission for invocation 0 */
2806 /* PRED_SETE_INT __, R0.x, 0 */
2807 memset(&alu, 0, sizeof(alu));
2808 alu.op = ALU_OP2_PRED_SETE_INT;
2809 alu.src[0].chan = 2;
2810 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2811 alu.execute_mask = 1;
2812 alu.update_pred = 1;
2813 alu.last = 1;
2814 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2815
2816 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2817 cf_jump = ctx->bc->cf_last;
2818
2819 treg[0] = r600_get_temp(ctx);
2820 switch (ctx->shader->tcs_prim_mode) {
2821 case PIPE_PRIM_LINES:
2822 stride = 8; /* 2 dwords, 1 vec2 store */
2823 outer_comps = 2;
2824 inner_comps = 0;
2825 break;
2826 case PIPE_PRIM_TRIANGLES:
2827 stride = 16; /* 4 dwords, 1 vec4 store */
2828 outer_comps = 3;
2829 inner_comps = 1;
2830 treg[1] = r600_get_temp(ctx);
2831 break;
2832 case PIPE_PRIM_QUADS:
2833 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2834 outer_comps = 4;
2835 inner_comps = 2;
2836 treg[1] = r600_get_temp(ctx);
2837 treg[2] = r600_get_temp(ctx);
2838 break;
2839 default:
2840 assert(0);
2841 return -1;
2842 }
2843
2844 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2845 /* TF_WRITE takes index in R.x, value in R.y */
2846 for (i = 0; i < ctx->shader->noutput; i++) {
2847 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2848 tessinner_idx = i;
2849 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2850 tessouter_idx = i;
2851 }
2852
2853 if (tessouter_idx == -1)
2854 return -1;
2855
2856 if (tessinner_idx == -1 && inner_comps)
2857 return -1;
2858
2859 if (tessouter_idx != -1) {
2860 r = r600_tess_factor_read(ctx, tessouter_idx);
2861 if (r)
2862 return r;
2863 }
2864
2865 if (tessinner_idx != -1) {
2866 r = r600_tess_factor_read(ctx, tessinner_idx);
2867 if (r)
2868 return r;
2869 }
2870
2871 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2872 /* r.x = relpatchid(r0.y) * tf_stride */
2873
2874 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2875 /* add incoming r0.w to it: t.x = t.x + r0.w */
2876 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2877 temp_reg, 0,
2878 0, 1,
2879 V_SQ_ALU_SRC_LITERAL, stride,
2880 0, 3);
2881 if (r)
2882 return r;
2883
2884 for (i = 0; i < outer_comps + inner_comps; i++) {
2885 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2886 int out_comp = i >= outer_comps ? i - outer_comps : i;
2887
2888 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2889 if (out_comp == 1)
2890 out_comp = 0;
2891 else if (out_comp == 0)
2892 out_comp = 1;
2893 }
2894
2895 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2896 treg[i / 2], (2 * (i % 2)),
2897 temp_reg, 0,
2898 V_SQ_ALU_SRC_LITERAL, 4 * i);
2899 if (r)
2900 return r;
2901 r = single_alu_op2(ctx, ALU_OP1_MOV,
2902 treg[i / 2], 1 + (2 * (i%2)),
2903 ctx->shader->output[out_idx].gpr, out_comp,
2904 0, 0);
2905 if (r)
2906 return r;
2907 }
2908 for (i = 0; i < outer_comps + inner_comps; i++) {
2909 struct r600_bytecode_gds gds;
2910
2911 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2912 gds.src_gpr = treg[i / 2];
2913 gds.src_sel_x = 2 * (i % 2);
2914 gds.src_sel_y = 1 + (2 * (i % 2));
2915 gds.src_sel_z = 4;
2916 gds.dst_sel_x = 7;
2917 gds.dst_sel_y = 7;
2918 gds.dst_sel_z = 7;
2919 gds.dst_sel_w = 7;
2920 gds.op = FETCH_OP_TF_WRITE;
2921 r = r600_bytecode_add_gds(ctx->bc, &gds);
2922 if (r)
2923 return r;
2924 }
2925
2926 // Patch up jump label
2927 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2928 cf_pop = ctx->bc->cf_last;
2929
2930 cf_jump->cf_addr = cf_pop->id + 2;
2931 cf_jump->pop_count = 1;
2932 cf_pop->cf_addr = cf_pop->id + 2;
2933 cf_pop->pop_count = 1;
2934
2935 return 0;
2936 }
2937
2938 static int r600_shader_from_tgsi(struct r600_context *rctx,
2939 struct r600_pipe_shader *pipeshader,
2940 union r600_shader_key key)
2941 {
2942 struct r600_screen *rscreen = rctx->screen;
2943 struct r600_shader *shader = &pipeshader->shader;
2944 struct tgsi_token *tokens = pipeshader->selector->tokens;
2945 struct pipe_stream_output_info so = pipeshader->selector->so;
2946 struct tgsi_full_immediate *immediate;
2947 struct r600_shader_ctx ctx;
2948 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
2949 unsigned output_done, noutput;
2950 unsigned opcode;
2951 int i, j, k, r = 0;
2952 int next_param_base = 0, next_clip_base;
2953 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2954 bool indirect_gprs;
2955 bool ring_outputs = false;
2956 bool lds_outputs = false;
2957 bool lds_inputs = false;
2958 bool pos_emitted = false;
2959
2960 ctx.bc = &shader->bc;
2961 ctx.shader = shader;
2962 ctx.native_integers = true;
2963
2964 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2965 rscreen->has_compressed_msaa_texturing);
2966 ctx.tokens = tokens;
2967 tgsi_scan_shader(tokens, &ctx.info);
2968 shader->indirect_files = ctx.info.indirect_files;
2969
2970 shader->uses_doubles = ctx.info.uses_doubles;
2971 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
2972 shader->nsys_inputs = 0;
2973
2974 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2975 tgsi_parse_init(&ctx.parse, tokens);
2976 ctx.type = ctx.info.processor;
2977 shader->processor_type = ctx.type;
2978 ctx.bc->type = shader->processor_type;
2979
2980 switch (ctx.type) {
2981 case PIPE_SHADER_VERTEX:
2982 shader->vs_as_gs_a = key.vs.as_gs_a;
2983 shader->vs_as_es = key.vs.as_es;
2984 shader->vs_as_ls = key.vs.as_ls;
2985 shader->atomic_base = key.vs.first_atomic_counter;
2986 if (shader->vs_as_es)
2987 ring_outputs = true;
2988 if (shader->vs_as_ls)
2989 lds_outputs = true;
2990 break;
2991 case PIPE_SHADER_GEOMETRY:
2992 ring_outputs = true;
2993 shader->atomic_base = key.gs.first_atomic_counter;
2994 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
2995 break;
2996 case PIPE_SHADER_TESS_CTRL:
2997 shader->tcs_prim_mode = key.tcs.prim_mode;
2998 shader->atomic_base = key.tcs.first_atomic_counter;
2999 lds_outputs = true;
3000 lds_inputs = true;
3001 break;
3002 case PIPE_SHADER_TESS_EVAL:
3003 shader->tes_as_es = key.tes.as_es;
3004 shader->atomic_base = key.tes.first_atomic_counter;
3005 lds_inputs = true;
3006 if (shader->tes_as_es)
3007 ring_outputs = true;
3008 break;
3009 case PIPE_SHADER_FRAGMENT:
3010 shader->two_side = key.ps.color_two_side;
3011 shader->atomic_base = key.ps.first_atomic_counter;
3012 break;
3013 default:
3014 break;
3015 }
3016
3017 if (shader->vs_as_es || shader->tes_as_es) {
3018 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3019 } else {
3020 ctx.gs_for_vs = NULL;
3021 }
3022
3023 ctx.next_ring_offset = 0;
3024 ctx.gs_out_ring_offset = 0;
3025 ctx.gs_next_vertex = 0;
3026 ctx.gs_stream_output_info = &so;
3027
3028 ctx.face_gpr = -1;
3029 ctx.fixed_pt_position_gpr = -1;
3030 ctx.fragcoord_input = -1;
3031 ctx.colors_used = 0;
3032 ctx.clip_vertex_write = 0;
3033
3034 shader->nr_ps_color_exports = 0;
3035 shader->nr_ps_max_color_exports = 0;
3036
3037
3038 /* register allocations */
3039 /* Values [0,127] correspond to GPR[0..127].
3040 * Values [128,159] correspond to constant buffer bank 0
3041 * Values [160,191] correspond to constant buffer bank 1
3042 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3043 * Values [256,287] correspond to constant buffer bank 2 (EG)
3044 * Values [288,319] correspond to constant buffer bank 3 (EG)
3045 * Other special values are shown in the list below.
3046 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3047 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3048 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3049 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3050 * 248 SQ_ALU_SRC_0: special constant 0.0.
3051 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3052 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3053 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3054 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3055 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3056 * 254 SQ_ALU_SRC_PV: previous vector result.
3057 * 255 SQ_ALU_SRC_PS: previous scalar result.
3058 */
3059 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3060 ctx.file_offset[i] = 0;
3061 }
3062
3063 if (ctx.type == PIPE_SHADER_VERTEX) {
3064
3065 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3066 if (ctx.info.num_inputs)
3067 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3068 }
3069 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3070 if (ctx.bc->chip_class >= EVERGREEN)
3071 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3072 else
3073 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3074 }
3075 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3076 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3077 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3078 }
3079 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3080 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3081 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3082 bool add_tesscoord = false, add_tess_inout = false;
3083 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3084 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3085 /* if we have tesscoord save one reg */
3086 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3087 add_tesscoord = true;
3088 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3089 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3090 add_tess_inout = true;
3091 }
3092 if (add_tesscoord || add_tess_inout)
3093 ctx.file_offset[TGSI_FILE_INPUT]++;
3094 if (add_tess_inout)
3095 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3096 }
3097
3098 ctx.file_offset[TGSI_FILE_OUTPUT] =
3099 ctx.file_offset[TGSI_FILE_INPUT] +
3100 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3101 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3102 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3103
3104 /* Outside the GPR range. This will be translated to one of the
3105 * kcache banks later. */
3106 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3107
3108 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3109 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3110 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3111 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3112 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3113
3114 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3115 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3116 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3117 ctx.temp_reg = ctx.bc->ar_reg + 5;
3118 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3119 ctx.tess_input_info = 0;
3120 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3121 ctx.temp_reg = ctx.bc->ar_reg + 4;
3122 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3123 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3124 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3125 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3126 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3127 ctx.temp_reg = ctx.bc->ar_reg + 7;
3128 if (ctx.shader->gs_tri_strip_adj_fix) {
3129 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3130 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3131 ctx.temp_reg += 2;
3132 } else {
3133 ctx.gs_rotated_input[0] = 0;
3134 ctx.gs_rotated_input[1] = 1;
3135 }
3136 } else {
3137 ctx.temp_reg = ctx.bc->ar_reg + 3;
3138 }
3139
3140 shader->max_arrays = 0;
3141 shader->num_arrays = 0;
3142 if (indirect_gprs) {
3143
3144 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3145 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3146 ctx.file_offset[TGSI_FILE_OUTPUT] -
3147 ctx.file_offset[TGSI_FILE_INPUT],
3148 0x0F);
3149 }
3150 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3151 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3152 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3153 ctx.file_offset[TGSI_FILE_OUTPUT],
3154 0x0F);
3155 }
3156 }
3157
3158 ctx.nliterals = 0;
3159 ctx.literals = NULL;
3160
3161 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3162 ctx.info.colors_written == 1;
3163 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3164 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3165
3166 if (shader->vs_as_gs_a)
3167 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3168
3169 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3170 r600_fetch_tess_io_info(&ctx);
3171
3172 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3173 tgsi_parse_token(&ctx.parse);
3174 switch (ctx.parse.FullToken.Token.Type) {
3175 case TGSI_TOKEN_TYPE_IMMEDIATE:
3176 immediate = &ctx.parse.FullToken.FullImmediate;
3177 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3178 if(ctx.literals == NULL) {
3179 r = -ENOMEM;
3180 goto out_err;
3181 }
3182 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3183 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3184 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3185 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3186 ctx.nliterals++;
3187 break;
3188 case TGSI_TOKEN_TYPE_DECLARATION:
3189 r = tgsi_declaration(&ctx);
3190 if (r)
3191 goto out_err;
3192 break;
3193 case TGSI_TOKEN_TYPE_INSTRUCTION:
3194 case TGSI_TOKEN_TYPE_PROPERTY:
3195 break;
3196 default:
3197 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3198 r = -EINVAL;
3199 goto out_err;
3200 }
3201 }
3202
3203 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3204 shader->ring_item_sizes[1] = 0;
3205 shader->ring_item_sizes[2] = 0;
3206 shader->ring_item_sizes[3] = 0;
3207
3208 /* Process two side if needed */
3209 if (shader->two_side && ctx.colors_used) {
3210 int i, count = ctx.shader->ninput;
3211 unsigned next_lds_loc = ctx.shader->nlds;
3212
3213 /* additional inputs will be allocated right after the existing inputs,
3214 * we won't need them after the color selection, so we don't need to
3215 * reserve these gprs for the rest of the shader code and to adjust
3216 * output offsets etc. */
3217 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3218 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3219
3220 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3221 if (ctx.face_gpr == -1) {
3222 i = ctx.shader->ninput++;
3223 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3224 ctx.shader->input[i].spi_sid = 0;
3225 ctx.shader->input[i].gpr = gpr++;
3226 ctx.face_gpr = ctx.shader->input[i].gpr;
3227 }
3228
3229 for (i = 0; i < count; i++) {
3230 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3231 int ni = ctx.shader->ninput++;
3232 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3233 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3234 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3235 ctx.shader->input[ni].gpr = gpr++;
3236 // TGSI to LLVM needs to know the lds position of inputs.
3237 // Non LLVM path computes it later (in process_twoside_color)
3238 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3239 ctx.shader->input[i].back_color_input = ni;
3240 if (ctx.bc->chip_class >= EVERGREEN) {
3241 if ((r = evergreen_interp_input(&ctx, ni)))
3242 return r;
3243 }
3244 }
3245 }
3246 }
3247
3248 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3249 shader->nr_ps_max_color_exports = 8;
3250
3251 if (ctx.fragcoord_input >= 0) {
3252 if (ctx.bc->chip_class == CAYMAN) {
3253 for (j = 0 ; j < 4; j++) {
3254 struct r600_bytecode_alu alu;
3255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3256 alu.op = ALU_OP1_RECIP_IEEE;
3257 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3258 alu.src[0].chan = 3;
3259
3260 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3261 alu.dst.chan = j;
3262 alu.dst.write = (j == 3);
3263 alu.last = 1;
3264 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3265 return r;
3266 }
3267 } else {
3268 struct r600_bytecode_alu alu;
3269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3270 alu.op = ALU_OP1_RECIP_IEEE;
3271 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3272 alu.src[0].chan = 3;
3273
3274 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3275 alu.dst.chan = 3;
3276 alu.dst.write = 1;
3277 alu.last = 1;
3278 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3279 return r;
3280 }
3281 }
3282
3283 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3284 struct r600_bytecode_alu alu;
3285 int r;
3286
3287 /* GS thread with no output workaround - emit a cut at start of GS */
3288 if (ctx.bc->chip_class == R600)
3289 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3290
3291 for (j = 0; j < 4; j++) {
3292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3293 alu.op = ALU_OP1_MOV;
3294 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3295 alu.src[0].value = 0;
3296 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3297 alu.dst.write = 1;
3298 alu.last = 1;
3299 r = r600_bytecode_add_alu(ctx.bc, &alu);
3300 if (r)
3301 return r;
3302 }
3303
3304 if (ctx.shader->gs_tri_strip_adj_fix) {
3305 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3306 ctx.gs_rotated_input[0], 2,
3307 0, 2,
3308 V_SQ_ALU_SRC_LITERAL, 1);
3309 if (r)
3310 return r;
3311
3312 for (i = 0; i < 6; i++) {
3313 int rotated = (i + 4) % 6;
3314 int offset_reg = i / 3;
3315 int offset_chan = i % 3;
3316 int rotated_offset_reg = rotated / 3;
3317 int rotated_offset_chan = rotated % 3;
3318
3319 if (offset_reg == 0 && offset_chan == 2)
3320 offset_chan = 3;
3321 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3322 rotated_offset_chan = 3;
3323
3324 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3325 ctx.gs_rotated_input[offset_reg], offset_chan,
3326 ctx.gs_rotated_input[0], 2,
3327 offset_reg, offset_chan,
3328 rotated_offset_reg, rotated_offset_chan);
3329 if (r)
3330 return r;
3331 }
3332 }
3333 }
3334
3335 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3336 r600_fetch_tess_io_info(&ctx);
3337
3338 if (shader->two_side && ctx.colors_used) {
3339 if ((r = process_twoside_color_inputs(&ctx)))
3340 return r;
3341 }
3342
3343 tgsi_parse_init(&ctx.parse, tokens);
3344 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3345 tgsi_parse_token(&ctx.parse);
3346 switch (ctx.parse.FullToken.Token.Type) {
3347 case TGSI_TOKEN_TYPE_INSTRUCTION:
3348 r = tgsi_is_supported(&ctx);
3349 if (r)
3350 goto out_err;
3351 ctx.max_driver_temp_used = 0;
3352 /* reserve first tmp for everyone */
3353 r600_get_temp(&ctx);
3354
3355 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3356 if ((r = tgsi_split_constant(&ctx)))
3357 goto out_err;
3358 if ((r = tgsi_split_literal_constant(&ctx)))
3359 goto out_err;
3360 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3361 if ((r = tgsi_split_gs_inputs(&ctx)))
3362 goto out_err;
3363 } else if (lds_inputs) {
3364 if ((r = tgsi_split_lds_inputs(&ctx)))
3365 goto out_err;
3366 }
3367 if (ctx.bc->chip_class == CAYMAN)
3368 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3369 else if (ctx.bc->chip_class >= EVERGREEN)
3370 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3371 else
3372 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3373 r = ctx.inst_info->process(&ctx);
3374 if (r)
3375 goto out_err;
3376
3377 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3378 r = r600_store_tcs_output(&ctx);
3379 if (r)
3380 goto out_err;
3381 }
3382 break;
3383 default:
3384 break;
3385 }
3386 }
3387
3388 /* Reset the temporary register counter. */
3389 ctx.max_driver_temp_used = 0;
3390
3391 noutput = shader->noutput;
3392
3393 if (!ring_outputs && ctx.clip_vertex_write) {
3394 unsigned clipdist_temp[2];
3395
3396 clipdist_temp[0] = r600_get_temp(&ctx);
3397 clipdist_temp[1] = r600_get_temp(&ctx);
3398
3399 /* need to convert a clipvertex write into clipdistance writes and not export
3400 the clip vertex anymore */
3401
3402 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3403 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3404 shader->output[noutput].gpr = clipdist_temp[0];
3405 noutput++;
3406 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3407 shader->output[noutput].gpr = clipdist_temp[1];
3408 noutput++;
3409
3410 /* reset spi_sid for clipvertex output to avoid confusing spi */
3411 shader->output[ctx.cv_output].spi_sid = 0;
3412
3413 shader->clip_dist_write = 0xFF;
3414
3415 for (i = 0; i < 8; i++) {
3416 int oreg = i >> 2;
3417 int ochan = i & 3;
3418
3419 for (j = 0; j < 4; j++) {
3420 struct r600_bytecode_alu alu;
3421 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3422 alu.op = ALU_OP2_DOT4;
3423 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3424 alu.src[0].chan = j;
3425
3426 alu.src[1].sel = 512 + i;
3427 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3428 alu.src[1].chan = j;
3429
3430 alu.dst.sel = clipdist_temp[oreg];
3431 alu.dst.chan = j;
3432 alu.dst.write = (j == ochan);
3433 if (j == 3)
3434 alu.last = 1;
3435 r = r600_bytecode_add_alu(ctx.bc, &alu);
3436 if (r)
3437 return r;
3438 }
3439 }
3440 }
3441
3442 /* Add stream outputs. */
3443 if (so.num_outputs) {
3444 bool emit = false;
3445 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3446 emit = true;
3447 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3448 emit = true;
3449 if (emit)
3450 emit_streamout(&ctx, &so, -1, NULL);
3451 }
3452 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3453 convert_edgeflag_to_int(&ctx);
3454
3455 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3456 r600_emit_tess_factor(&ctx);
3457
3458 if (lds_outputs) {
3459 if (ctx.type == PIPE_SHADER_VERTEX) {
3460 if (ctx.shader->noutput)
3461 emit_lds_vs_writes(&ctx);
3462 }
3463 } else if (ring_outputs) {
3464 if (shader->vs_as_es || shader->tes_as_es) {
3465 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3466 ctx.gs_export_gpr_tregs[1] = -1;
3467 ctx.gs_export_gpr_tregs[2] = -1;
3468 ctx.gs_export_gpr_tregs[3] = -1;
3469
3470 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3471 }
3472 } else {
3473 /* Export output */
3474 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3475
3476 for (i = 0, j = 0; i < noutput; i++, j++) {
3477 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3478 output[j].gpr = shader->output[i].gpr;
3479 output[j].elem_size = 3;
3480 output[j].swizzle_x = 0;
3481 output[j].swizzle_y = 1;
3482 output[j].swizzle_z = 2;
3483 output[j].swizzle_w = 3;
3484 output[j].burst_count = 1;
3485 output[j].type = -1;
3486 output[j].op = CF_OP_EXPORT;
3487 switch (ctx.type) {
3488 case PIPE_SHADER_VERTEX:
3489 case PIPE_SHADER_TESS_EVAL:
3490 switch (shader->output[i].name) {
3491 case TGSI_SEMANTIC_POSITION:
3492 output[j].array_base = 60;
3493 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3494 pos_emitted = true;
3495 break;
3496
3497 case TGSI_SEMANTIC_PSIZE:
3498 output[j].array_base = 61;
3499 output[j].swizzle_y = 7;
3500 output[j].swizzle_z = 7;
3501 output[j].swizzle_w = 7;
3502 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3503 pos_emitted = true;
3504 break;
3505 case TGSI_SEMANTIC_EDGEFLAG:
3506 output[j].array_base = 61;
3507 output[j].swizzle_x = 7;
3508 output[j].swizzle_y = 0;
3509 output[j].swizzle_z = 7;
3510 output[j].swizzle_w = 7;
3511 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3512 pos_emitted = true;
3513 break;
3514 case TGSI_SEMANTIC_LAYER:
3515 /* spi_sid is 0 for outputs that are
3516 * not consumed by PS */
3517 if (shader->output[i].spi_sid) {
3518 output[j].array_base = next_param_base++;
3519 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3520 j++;
3521 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3522 }
3523 output[j].array_base = 61;
3524 output[j].swizzle_x = 7;
3525 output[j].swizzle_y = 7;
3526 output[j].swizzle_z = 0;
3527 output[j].swizzle_w = 7;
3528 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3529 pos_emitted = true;
3530 break;
3531 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3532 /* spi_sid is 0 for outputs that are
3533 * not consumed by PS */
3534 if (shader->output[i].spi_sid) {
3535 output[j].array_base = next_param_base++;
3536 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3537 j++;
3538 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3539 }
3540 output[j].array_base = 61;
3541 output[j].swizzle_x = 7;
3542 output[j].swizzle_y = 7;
3543 output[j].swizzle_z = 7;
3544 output[j].swizzle_w = 0;
3545 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3546 pos_emitted = true;
3547 break;
3548 case TGSI_SEMANTIC_CLIPVERTEX:
3549 j--;
3550 break;
3551 case TGSI_SEMANTIC_CLIPDIST:
3552 output[j].array_base = next_clip_base++;
3553 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3554 pos_emitted = true;
3555 /* spi_sid is 0 for clipdistance outputs that were generated
3556 * for clipvertex - we don't need to pass them to PS */
3557 if (shader->output[i].spi_sid) {
3558 j++;
3559 /* duplicate it as PARAM to pass to the pixel shader */
3560 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3561 output[j].array_base = next_param_base++;
3562 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3563 }
3564 break;
3565 case TGSI_SEMANTIC_FOG:
3566 output[j].swizzle_y = 4; /* 0 */
3567 output[j].swizzle_z = 4; /* 0 */
3568 output[j].swizzle_w = 5; /* 1 */
3569 break;
3570 case TGSI_SEMANTIC_PRIMID:
3571 output[j].swizzle_x = 2;
3572 output[j].swizzle_y = 4; /* 0 */
3573 output[j].swizzle_z = 4; /* 0 */
3574 output[j].swizzle_w = 4; /* 0 */
3575 break;
3576 }
3577
3578 break;
3579 case PIPE_SHADER_FRAGMENT:
3580 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3581 /* never export more colors than the number of CBs */
3582 if (shader->output[i].sid >= max_color_exports) {
3583 /* skip export */
3584 j--;
3585 continue;
3586 }
3587 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3588 output[j].array_base = shader->output[i].sid;
3589 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3590 shader->nr_ps_color_exports++;
3591 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3592 for (k = 1; k < max_color_exports; k++) {
3593 j++;
3594 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3595 output[j].gpr = shader->output[i].gpr;
3596 output[j].elem_size = 3;
3597 output[j].swizzle_x = 0;
3598 output[j].swizzle_y = 1;
3599 output[j].swizzle_z = 2;
3600 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3601 output[j].burst_count = 1;
3602 output[j].array_base = k;
3603 output[j].op = CF_OP_EXPORT;
3604 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3605 shader->nr_ps_color_exports++;
3606 }
3607 }
3608 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3609 output[j].array_base = 61;
3610 output[j].swizzle_x = 2;
3611 output[j].swizzle_y = 7;
3612 output[j].swizzle_z = output[j].swizzle_w = 7;
3613 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3614 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3615 output[j].array_base = 61;
3616 output[j].swizzle_x = 7;
3617 output[j].swizzle_y = 1;
3618 output[j].swizzle_z = output[j].swizzle_w = 7;
3619 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3620 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3621 output[j].array_base = 61;
3622 output[j].swizzle_x = 7;
3623 output[j].swizzle_y = 7;
3624 output[j].swizzle_z = 0;
3625 output[j].swizzle_w = 7;
3626 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3627 } else {
3628 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3629 r = -EINVAL;
3630 goto out_err;
3631 }
3632 break;
3633 case PIPE_SHADER_TESS_CTRL:
3634 break;
3635 default:
3636 R600_ERR("unsupported processor type %d\n", ctx.type);
3637 r = -EINVAL;
3638 goto out_err;
3639 }
3640
3641 if (output[j].type==-1) {
3642 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3643 output[j].array_base = next_param_base++;
3644 }
3645 }
3646
3647 /* add fake position export */
3648 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3649 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3650 output[j].gpr = 0;
3651 output[j].elem_size = 3;
3652 output[j].swizzle_x = 7;
3653 output[j].swizzle_y = 7;
3654 output[j].swizzle_z = 7;
3655 output[j].swizzle_w = 7;
3656 output[j].burst_count = 1;
3657 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3658 output[j].array_base = 60;
3659 output[j].op = CF_OP_EXPORT;
3660 j++;
3661 }
3662
3663 /* add fake param output for vertex shader if no param is exported */
3664 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3665 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3666 output[j].gpr = 0;
3667 output[j].elem_size = 3;
3668 output[j].swizzle_x = 7;
3669 output[j].swizzle_y = 7;
3670 output[j].swizzle_z = 7;
3671 output[j].swizzle_w = 7;
3672 output[j].burst_count = 1;
3673 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3674 output[j].array_base = 0;
3675 output[j].op = CF_OP_EXPORT;
3676 j++;
3677 }
3678
3679 /* add fake pixel export */
3680 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3681 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3682 output[j].gpr = 0;
3683 output[j].elem_size = 3;
3684 output[j].swizzle_x = 7;
3685 output[j].swizzle_y = 7;
3686 output[j].swizzle_z = 7;
3687 output[j].swizzle_w = 7;
3688 output[j].burst_count = 1;
3689 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3690 output[j].array_base = 0;
3691 output[j].op = CF_OP_EXPORT;
3692 j++;
3693 shader->nr_ps_color_exports++;
3694 }
3695
3696 noutput = j;
3697
3698 /* set export done on last export of each type */
3699 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3700 if (!(output_done & (1 << output[i].type))) {
3701 output_done |= (1 << output[i].type);
3702 output[i].op = CF_OP_EXPORT_DONE;
3703 }
3704 }
3705 /* add output to bytecode */
3706 for (i = 0; i < noutput; i++) {
3707 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3708 if (r)
3709 goto out_err;
3710 }
3711 }
3712
3713 /* add program end */
3714 if (ctx.bc->chip_class == CAYMAN)
3715 cm_bytecode_add_cf_end(ctx.bc);
3716 else {
3717 const struct cf_op_info *last = NULL;
3718
3719 if (ctx.bc->cf_last)
3720 last = r600_isa_cf(ctx.bc->cf_last->op);
3721
3722 /* alu clause instructions don't have EOP bit, so add NOP */
3723 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3724 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3725
3726 ctx.bc->cf_last->end_of_program = 1;
3727 }
3728
3729 /* check GPR limit - we have 124 = 128 - 4
3730 * (4 are reserved as alu clause temporary registers) */
3731 if (ctx.bc->ngpr > 124) {
3732 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3733 r = -ENOMEM;
3734 goto out_err;
3735 }
3736
3737 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3738 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3739 return r;
3740 }
3741
3742 free(ctx.literals);
3743 tgsi_parse_free(&ctx.parse);
3744 return 0;
3745 out_err:
3746 free(ctx.literals);
3747 tgsi_parse_free(&ctx.parse);
3748 return r;
3749 }
3750
3751 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3752 {
3753 const unsigned tgsi_opcode =
3754 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3755 R600_ERR("%s tgsi opcode unsupported\n",
3756 tgsi_get_opcode_name(tgsi_opcode));
3757 return -EINVAL;
3758 }
3759
3760 static int tgsi_end(struct r600_shader_ctx *ctx)
3761 {
3762 return 0;
3763 }
3764
3765 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3766 const struct r600_shader_src *shader_src,
3767 unsigned chan)
3768 {
3769 bc_src->sel = shader_src->sel;
3770 bc_src->chan = shader_src->swizzle[chan];
3771 bc_src->neg = shader_src->neg;
3772 bc_src->abs = shader_src->abs;
3773 bc_src->rel = shader_src->rel;
3774 bc_src->value = shader_src->value[bc_src->chan];
3775 bc_src->kc_bank = shader_src->kc_bank;
3776 bc_src->kc_rel = shader_src->kc_rel;
3777 }
3778
3779 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3780 {
3781 bc_src->abs = 1;
3782 bc_src->neg = 0;
3783 }
3784
3785 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3786 {
3787 bc_src->neg = !bc_src->neg;
3788 }
3789
3790 static void tgsi_dst(struct r600_shader_ctx *ctx,
3791 const struct tgsi_full_dst_register *tgsi_dst,
3792 unsigned swizzle,
3793 struct r600_bytecode_alu_dst *r600_dst)
3794 {
3795 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3796
3797 r600_dst->sel = tgsi_dst->Register.Index;
3798 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3799 r600_dst->chan = swizzle;
3800 r600_dst->write = 1;
3801 if (inst->Instruction.Saturate) {
3802 r600_dst->clamp = 1;
3803 }
3804 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3805 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3806 return;
3807 }
3808 }
3809 if (tgsi_dst->Register.Indirect)
3810 r600_dst->rel = V_SQ_REL_RELATIVE;
3811
3812 }
3813
3814 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3815 {
3816 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3817 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3818 struct r600_bytecode_alu alu;
3819 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3820 int use_tmp = 0;
3821
3822 if (singledest) {
3823 switch (write_mask) {
3824 case 0x1:
3825 write_mask = 0x3;
3826 break;
3827 case 0x2:
3828 use_tmp = 1;
3829 write_mask = 0x3;
3830 break;
3831 case 0x4:
3832 write_mask = 0xc;
3833 break;
3834 case 0x8:
3835 write_mask = 0xc;
3836 use_tmp = 3;
3837 break;
3838 }
3839 }
3840
3841 lasti = tgsi_last_instruction(write_mask);
3842 for (i = 0; i <= lasti; i++) {
3843
3844 if (!(write_mask & (1 << i)))
3845 continue;
3846
3847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3848
3849 if (singledest) {
3850 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3851 if (use_tmp) {
3852 alu.dst.sel = ctx->temp_reg;
3853 alu.dst.chan = i;
3854 alu.dst.write = 1;
3855 }
3856 if (i == 1 || i == 3)
3857 alu.dst.write = 0;
3858 } else
3859 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3860
3861 alu.op = ctx->inst_info->op;
3862 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3863 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3864 } else if (!swap) {
3865 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3866 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3867 }
3868 } else {
3869 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3870 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3871 }
3872
3873 /* handle some special cases */
3874 if (i == 1 || i == 3) {
3875 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3876 case TGSI_OPCODE_DABS:
3877 r600_bytecode_src_set_abs(&alu.src[0]);
3878 break;
3879 default:
3880 break;
3881 }
3882 }
3883 if (i == lasti) {
3884 alu.last = 1;
3885 }
3886 r = r600_bytecode_add_alu(ctx->bc, &alu);
3887 if (r)
3888 return r;
3889 }
3890
3891 if (use_tmp) {
3892 write_mask = inst->Dst[0].Register.WriteMask;
3893
3894 /* move result from temp to dst */
3895 for (i = 0; i <= lasti; i++) {
3896 if (!(write_mask & (1 << i)))
3897 continue;
3898
3899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3900 alu.op = ALU_OP1_MOV;
3901 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3902 alu.src[0].sel = ctx->temp_reg;
3903 alu.src[0].chan = use_tmp - 1;
3904 alu.last = (i == lasti);
3905
3906 r = r600_bytecode_add_alu(ctx->bc, &alu);
3907 if (r)
3908 return r;
3909 }
3910 }
3911 return 0;
3912 }
3913
3914 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3915 {
3916 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3917 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3918 /* confirm writemasking */
3919 if ((write_mask & 0x3) != 0x3 &&
3920 (write_mask & 0xc) != 0xc) {
3921 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3922 return -1;
3923 }
3924 return tgsi_op2_64_params(ctx, false, false);
3925 }
3926
3927 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
3928 {
3929 return tgsi_op2_64_params(ctx, true, false);
3930 }
3931
3932 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
3933 {
3934 return tgsi_op2_64_params(ctx, true, true);
3935 }
3936
3937 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3938 {
3939 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3940 struct r600_bytecode_alu alu;
3941 int i, j, r;
3942 int lasti = 3;
3943 int tmp = r600_get_temp(ctx);
3944
3945 for (i = 0; i < lasti + 1; i++) {
3946
3947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3948 alu.op = ctx->inst_info->op;
3949 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3950 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3951 }
3952
3953 if (inst->Dst[0].Register.WriteMask & (1 << i))
3954 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3955 else
3956 alu.dst.sel = tmp;
3957
3958 alu.dst.chan = i;
3959 alu.is_op3 = 1;
3960 if (i == lasti) {
3961 alu.last = 1;
3962 }
3963 r = r600_bytecode_add_alu(ctx->bc, &alu);
3964 if (r)
3965 return r;
3966 }
3967 return 0;
3968 }
3969
3970 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3971 {
3972 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3973 struct r600_bytecode_alu alu;
3974 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3975 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3976 /* use temp register if trans_only and more than one dst component */
3977 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3978 unsigned op = ctx->inst_info->op;
3979
3980 if (op == ALU_OP2_MUL_IEEE &&
3981 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
3982 op = ALU_OP2_MUL;
3983
3984 for (i = 0; i <= lasti; i++) {
3985 if (!(write_mask & (1 << i)))
3986 continue;
3987
3988 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3989 if (use_tmp) {
3990 alu.dst.sel = ctx->temp_reg;
3991 alu.dst.chan = i;
3992 alu.dst.write = 1;
3993 } else
3994 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3995
3996 alu.op = op;
3997 if (!swap) {
3998 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3999 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4000 }
4001 } else {
4002 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4003 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4004 }
4005 if (i == lasti || trans_only) {
4006 alu.last = 1;
4007 }
4008 r = r600_bytecode_add_alu(ctx->bc, &alu);
4009 if (r)
4010 return r;
4011 }
4012
4013 if (use_tmp) {
4014 /* move result from temp to dst */
4015 for (i = 0; i <= lasti; i++) {
4016 if (!(write_mask & (1 << i)))
4017 continue;
4018
4019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4020 alu.op = ALU_OP1_MOV;
4021 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4022 alu.src[0].sel = ctx->temp_reg;
4023 alu.src[0].chan = i;
4024 alu.last = (i == lasti);
4025
4026 r = r600_bytecode_add_alu(ctx->bc, &alu);
4027 if (r)
4028 return r;
4029 }
4030 }
4031 return 0;
4032 }
4033
4034 static int tgsi_op2(struct r600_shader_ctx *ctx)
4035 {
4036 return tgsi_op2_s(ctx, 0, 0);
4037 }
4038
4039 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4040 {
4041 return tgsi_op2_s(ctx, 1, 0);
4042 }
4043
4044 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4045 {
4046 return tgsi_op2_s(ctx, 0, 1);
4047 }
4048
4049 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4050 {
4051 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4052 struct r600_bytecode_alu alu;
4053 int i, r;
4054 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4055
4056 for (i = 0; i < lasti + 1; i++) {
4057
4058 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4059 continue;
4060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4061 alu.op = ctx->inst_info->op;
4062
4063 alu.src[0].sel = V_SQ_ALU_SRC_0;
4064
4065 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4066
4067 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4068
4069 if (i == lasti) {
4070 alu.last = 1;
4071 }
4072 r = r600_bytecode_add_alu(ctx->bc, &alu);
4073 if (r)
4074 return r;
4075 }
4076 return 0;
4077
4078 }
4079
4080 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4081 {
4082 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4083 struct r600_bytecode_alu alu;
4084 int i, r;
4085 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4086
4087 for (i = 0; i < lasti + 1; i++) {
4088
4089 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4090 continue;
4091 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4092 alu.op = ALU_OP1_MOV;
4093
4094 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4095
4096 if (i == 1 || i == 3)
4097 r600_bytecode_src_toggle_neg(&alu.src[0]);
4098 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4099
4100 if (i == lasti) {
4101 alu.last = 1;
4102 }
4103 r = r600_bytecode_add_alu(ctx->bc, &alu);
4104 if (r)
4105 return r;
4106 }
4107 return 0;
4108
4109 }
4110
4111 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4112 {
4113 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4114 struct r600_bytecode_alu alu;
4115 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4116 int i, j, r;
4117
4118 for (i = 0; i <= 3; i++) {
4119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4120 alu.op = ctx->inst_info->op;
4121
4122 alu.dst.sel = ctx->temp_reg;
4123 alu.dst.chan = i;
4124 alu.dst.write = 1;
4125 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4126 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4127 }
4128
4129 if (i == 3)
4130 alu.last = 1;
4131
4132 r = r600_bytecode_add_alu(ctx->bc, &alu);
4133 if (r)
4134 return r;
4135 }
4136
4137 /* Replicate significand result across channels. */
4138 for (i = 0; i <= 3; i++) {
4139 if (!(write_mask & (1 << i)))
4140 continue;
4141
4142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4143 alu.op = ALU_OP1_MOV;
4144 alu.src[0].chan = (i & 1) + 2;
4145 alu.src[0].sel = ctx->temp_reg;
4146
4147 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4148 alu.dst.write = 1;
4149 alu.last = 1;
4150 r = r600_bytecode_add_alu(ctx->bc, &alu);
4151 if (r)
4152 return r;
4153 }
4154
4155 for (i = 0; i <= 3; i++) {
4156 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4157 /* MOV third channels to writemask dst1 */
4158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4159 alu.op = ALU_OP1_MOV;
4160 alu.src[0].chan = 1;
4161 alu.src[0].sel = ctx->temp_reg;
4162
4163 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4164 alu.last = 1;
4165 r = r600_bytecode_add_alu(ctx->bc, &alu);
4166 if (r)
4167 return r;
4168 break;
4169 }
4170 }
4171 return 0;
4172 }
4173
4174
4175 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4176 {
4177 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4178 struct r600_bytecode_alu alu;
4179 int i, r;
4180 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4181
4182 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4183 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4184
4185 for (i = 0; i <= (lasti+1)/2; i++) {
4186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4187 alu.op = ctx->inst_info->op;
4188
4189 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4190 alu.dst.sel = ctx->temp_reg;
4191 alu.dst.chan = i;
4192 alu.dst.write = 1;
4193 alu.last = 1;
4194
4195 r = r600_bytecode_add_alu(ctx->bc, &alu);
4196 if (r)
4197 return r;
4198 }
4199
4200 for (i = 0; i <= lasti; i++) {
4201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4202 alu.op = ALU_OP1_FLT32_TO_FLT64;
4203
4204 alu.src[0].chan = i/2;
4205 if (i%2 == 0)
4206 alu.src[0].sel = ctx->temp_reg;
4207 else {
4208 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4209 alu.src[0].value = 0x0;
4210 }
4211 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4212 alu.last = i == lasti;
4213
4214 r = r600_bytecode_add_alu(ctx->bc, &alu);
4215 if (r)
4216 return r;
4217 }
4218
4219 return 0;
4220 }
4221
4222 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4223 {
4224 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4225 struct r600_bytecode_alu alu;
4226 int i, r;
4227 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4228
4229 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4230 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4231
4232 for (i = 0; i <= lasti; i++) {
4233 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4234 alu.op = ALU_OP1_FLT64_TO_FLT32;
4235
4236 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4237 alu.dst.chan = i;
4238 alu.dst.sel = ctx->temp_reg;
4239 alu.dst.write = i%2 == 0;
4240 alu.last = i == lasti;
4241
4242 r = r600_bytecode_add_alu(ctx->bc, &alu);
4243 if (r)
4244 return r;
4245 }
4246
4247 for (i = 0; i <= (lasti+1)/2; i++) {
4248 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4249 alu.op = ctx->inst_info->op;
4250
4251 alu.src[0].chan = i*2;
4252 alu.src[0].sel = ctx->temp_reg;
4253 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4254 alu.last = 1;
4255
4256 r = r600_bytecode_add_alu(ctx->bc, &alu);
4257 if (r)
4258 return r;
4259 }
4260
4261 return 0;
4262 }
4263
4264 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4265 unsigned op,
4266 int dst_reg,
4267 struct r600_shader_src *src,
4268 bool abs)
4269 {
4270 struct r600_bytecode_alu alu;
4271 const int last_slot = 3;
4272 int r;
4273
4274 /* these have to write the result to X/Y by the looks of it */
4275 for (int i = 0 ; i < last_slot; i++) {
4276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4277 alu.op = op;
4278
4279 r600_bytecode_src(&alu.src[0], src, 1);
4280 r600_bytecode_src(&alu.src[1], src, 0);
4281
4282 if (abs)
4283 r600_bytecode_src_set_abs(&alu.src[1]);
4284
4285 alu.dst.sel = dst_reg;
4286 alu.dst.chan = i;
4287 alu.dst.write = (i == 0 || i == 1);
4288
4289 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4290 alu.last = 1;
4291 r = r600_bytecode_add_alu(bc, &alu);
4292 if (r)
4293 return r;
4294 }
4295
4296 return 0;
4297 }
4298
4299 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4300 {
4301 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4302 int i, r;
4303 struct r600_bytecode_alu alu;
4304 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4305 int t1 = ctx->temp_reg;
4306
4307 /* should only be one src regs */
4308 assert(inst->Instruction.NumSrcRegs == 1);
4309
4310 /* only support one double at a time */
4311 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4312 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4313
4314 r = cayman_emit_unary_double_raw(
4315 ctx->bc, ctx->inst_info->op, t1,
4316 &ctx->src[0],
4317 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4318 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4319 if (r)
4320 return r;
4321
4322 for (i = 0 ; i <= lasti; i++) {
4323 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4324 continue;
4325 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4326 alu.op = ALU_OP1_MOV;
4327 alu.src[0].sel = t1;
4328 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4329 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4330 alu.dst.write = 1;
4331 if (i == lasti)
4332 alu.last = 1;
4333 r = r600_bytecode_add_alu(ctx->bc, &alu);
4334 if (r)
4335 return r;
4336 }
4337 return 0;
4338 }
4339
4340 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4341 {
4342 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4343 int i, j, r;
4344 struct r600_bytecode_alu alu;
4345 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4346
4347 for (i = 0 ; i < last_slot; i++) {
4348 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4349 alu.op = ctx->inst_info->op;
4350 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4351 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4352
4353 /* RSQ should take the absolute value of src */
4354 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4355 r600_bytecode_src_set_abs(&alu.src[j]);
4356 }
4357 }
4358 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4359 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4360
4361 if (i == last_slot - 1)
4362 alu.last = 1;
4363 r = r600_bytecode_add_alu(ctx->bc, &alu);
4364 if (r)
4365 return r;
4366 }
4367 return 0;
4368 }
4369
4370 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4371 {
4372 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4373 int i, j, k, r;
4374 struct r600_bytecode_alu alu;
4375 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4376 int t1 = ctx->temp_reg;
4377
4378 for (k = 0; k <= lasti; k++) {
4379 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4380 continue;
4381
4382 for (i = 0 ; i < 4; i++) {
4383 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4384 alu.op = ctx->inst_info->op;
4385 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4386 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4387 }
4388 alu.dst.sel = t1;
4389 alu.dst.chan = i;
4390 alu.dst.write = (i == k);
4391 if (i == 3)
4392 alu.last = 1;
4393 r = r600_bytecode_add_alu(ctx->bc, &alu);
4394 if (r)
4395 return r;
4396 }
4397 }
4398
4399 for (i = 0 ; i <= lasti; i++) {
4400 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4401 continue;
4402 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4403 alu.op = ALU_OP1_MOV;
4404 alu.src[0].sel = t1;
4405 alu.src[0].chan = i;
4406 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4407 alu.dst.write = 1;
4408 if (i == lasti)
4409 alu.last = 1;
4410 r = r600_bytecode_add_alu(ctx->bc, &alu);
4411 if (r)
4412 return r;
4413 }
4414
4415 return 0;
4416 }
4417
4418
4419 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4420 {
4421 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4422 int i, j, k, r;
4423 struct r600_bytecode_alu alu;
4424 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4425 int t1 = ctx->temp_reg;
4426
4427 /* t1 would get overwritten below if we actually tried to
4428 * multiply two pairs of doubles at a time. */
4429 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4430 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4431
4432 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4433
4434 for (i = 0; i < 4; i++) {
4435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4436 alu.op = ctx->inst_info->op;
4437 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4438 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4439 }
4440 alu.dst.sel = t1;
4441 alu.dst.chan = i;
4442 alu.dst.write = 1;
4443 if (i == 3)
4444 alu.last = 1;
4445 r = r600_bytecode_add_alu(ctx->bc, &alu);
4446 if (r)
4447 return r;
4448 }
4449
4450 for (i = 0; i <= lasti; i++) {
4451 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4452 continue;
4453 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4454 alu.op = ALU_OP1_MOV;
4455 alu.src[0].sel = t1;
4456 alu.src[0].chan = i;
4457 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4458 alu.dst.write = 1;
4459 if (i == lasti)
4460 alu.last = 1;
4461 r = r600_bytecode_add_alu(ctx->bc, &alu);
4462 if (r)
4463 return r;
4464 }
4465
4466 return 0;
4467 }
4468
4469 /*
4470 * Emit RECIP_64 + MUL_64 to implement division.
4471 */
4472 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4473 {
4474 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4475 int r;
4476 struct r600_bytecode_alu alu;
4477 int t1 = ctx->temp_reg;
4478 int k;
4479
4480 /* Only support one double at a time. This is the same constraint as
4481 * in DMUL lowering. */
4482 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4483 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4484
4485 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4486
4487 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4488 if (r)
4489 return r;
4490
4491 for (int i = 0; i < 4; i++) {
4492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4493 alu.op = ALU_OP2_MUL_64;
4494
4495 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4496
4497 alu.src[1].sel = t1;
4498 alu.src[1].chan = (i == 3) ? 0 : 1;
4499
4500 alu.dst.sel = t1;
4501 alu.dst.chan = i;
4502 alu.dst.write = 1;
4503 if (i == 3)
4504 alu.last = 1;
4505 r = r600_bytecode_add_alu(ctx->bc, &alu);
4506 if (r)
4507 return r;
4508 }
4509
4510 for (int i = 0; i < 2; i++) {
4511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4512 alu.op = ALU_OP1_MOV;
4513 alu.src[0].sel = t1;
4514 alu.src[0].chan = i;
4515 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4516 alu.dst.write = 1;
4517 if (i == 1)
4518 alu.last = 1;
4519 r = r600_bytecode_add_alu(ctx->bc, &alu);
4520 if (r)
4521 return r;
4522 }
4523 return 0;
4524 }
4525
4526 /*
4527 * r600 - trunc to -PI..PI range
4528 * r700 - normalize by dividing by 2PI
4529 * see fdo bug 27901
4530 */
4531 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4532 {
4533 int r;
4534 struct r600_bytecode_alu alu;
4535
4536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4537 alu.op = ALU_OP3_MULADD;
4538 alu.is_op3 = 1;
4539
4540 alu.dst.chan = 0;
4541 alu.dst.sel = ctx->temp_reg;
4542 alu.dst.write = 1;
4543
4544 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4545
4546 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4547 alu.src[1].chan = 0;
4548 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4549 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4550 alu.src[2].chan = 0;
4551 alu.last = 1;
4552 r = r600_bytecode_add_alu(ctx->bc, &alu);
4553 if (r)
4554 return r;
4555
4556 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4557 alu.op = ALU_OP1_FRACT;
4558
4559 alu.dst.chan = 0;
4560 alu.dst.sel = ctx->temp_reg;
4561 alu.dst.write = 1;
4562
4563 alu.src[0].sel = ctx->temp_reg;
4564 alu.src[0].chan = 0;
4565 alu.last = 1;
4566 r = r600_bytecode_add_alu(ctx->bc, &alu);
4567 if (r)
4568 return r;
4569
4570 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4571 alu.op = ALU_OP3_MULADD;
4572 alu.is_op3 = 1;
4573
4574 alu.dst.chan = 0;
4575 alu.dst.sel = ctx->temp_reg;
4576 alu.dst.write = 1;
4577
4578 alu.src[0].sel = ctx->temp_reg;
4579 alu.src[0].chan = 0;
4580
4581 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4582 alu.src[1].chan = 0;
4583 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4584 alu.src[2].chan = 0;
4585
4586 if (ctx->bc->chip_class == R600) {
4587 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4588 alu.src[2].value = u_bitcast_f2u(-M_PI);
4589 } else {
4590 alu.src[1].sel = V_SQ_ALU_SRC_1;
4591 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4592 alu.src[2].neg = 1;
4593 }
4594
4595 alu.last = 1;
4596 r = r600_bytecode_add_alu(ctx->bc, &alu);
4597 if (r)
4598 return r;
4599 return 0;
4600 }
4601
4602 static int cayman_trig(struct r600_shader_ctx *ctx)
4603 {
4604 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4605 struct r600_bytecode_alu alu;
4606 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4607 int i, r;
4608
4609 r = tgsi_setup_trig(ctx);
4610 if (r)
4611 return r;
4612
4613
4614 for (i = 0; i < last_slot; i++) {
4615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4616 alu.op = ctx->inst_info->op;
4617 alu.dst.chan = i;
4618
4619 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4620 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4621
4622 alu.src[0].sel = ctx->temp_reg;
4623 alu.src[0].chan = 0;
4624 if (i == last_slot - 1)
4625 alu.last = 1;
4626 r = r600_bytecode_add_alu(ctx->bc, &alu);
4627 if (r)
4628 return r;
4629 }
4630 return 0;
4631 }
4632
4633 static int tgsi_trig(struct r600_shader_ctx *ctx)
4634 {
4635 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4636 struct r600_bytecode_alu alu;
4637 int i, r;
4638 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4639
4640 r = tgsi_setup_trig(ctx);
4641 if (r)
4642 return r;
4643
4644 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4645 alu.op = ctx->inst_info->op;
4646 alu.dst.chan = 0;
4647 alu.dst.sel = ctx->temp_reg;
4648 alu.dst.write = 1;
4649
4650 alu.src[0].sel = ctx->temp_reg;
4651 alu.src[0].chan = 0;
4652 alu.last = 1;
4653 r = r600_bytecode_add_alu(ctx->bc, &alu);
4654 if (r)
4655 return r;
4656
4657 /* replicate result */
4658 for (i = 0; i < lasti + 1; i++) {
4659 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4660 continue;
4661
4662 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4663 alu.op = ALU_OP1_MOV;
4664
4665 alu.src[0].sel = ctx->temp_reg;
4666 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4667 if (i == lasti)
4668 alu.last = 1;
4669 r = r600_bytecode_add_alu(ctx->bc, &alu);
4670 if (r)
4671 return r;
4672 }
4673 return 0;
4674 }
4675
4676 static int tgsi_kill(struct r600_shader_ctx *ctx)
4677 {
4678 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4679 struct r600_bytecode_alu alu;
4680 int i, r;
4681
4682 for (i = 0; i < 4; i++) {
4683 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4684 alu.op = ctx->inst_info->op;
4685
4686 alu.dst.chan = i;
4687
4688 alu.src[0].sel = V_SQ_ALU_SRC_0;
4689
4690 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4691 alu.src[1].sel = V_SQ_ALU_SRC_1;
4692 alu.src[1].neg = 1;
4693 } else {
4694 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4695 }
4696 if (i == 3) {
4697 alu.last = 1;
4698 }
4699 r = r600_bytecode_add_alu(ctx->bc, &alu);
4700 if (r)
4701 return r;
4702 }
4703
4704 /* kill must be last in ALU */
4705 ctx->bc->force_add_cf = 1;
4706 ctx->shader->uses_kill = TRUE;
4707 return 0;
4708 }
4709
4710 static int tgsi_lit(struct r600_shader_ctx *ctx)
4711 {
4712 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4713 struct r600_bytecode_alu alu;
4714 int r;
4715
4716 /* tmp.x = max(src.y, 0.0) */
4717 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4718 alu.op = ALU_OP2_MAX;
4719 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4720 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4721 alu.src[1].chan = 1;
4722
4723 alu.dst.sel = ctx->temp_reg;
4724 alu.dst.chan = 0;
4725 alu.dst.write = 1;
4726
4727 alu.last = 1;
4728 r = r600_bytecode_add_alu(ctx->bc, &alu);
4729 if (r)
4730 return r;
4731
4732 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4733 {
4734 int chan;
4735 int sel;
4736 unsigned i;
4737
4738 if (ctx->bc->chip_class == CAYMAN) {
4739 for (i = 0; i < 3; i++) {
4740 /* tmp.z = log(tmp.x) */
4741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4742 alu.op = ALU_OP1_LOG_CLAMPED;
4743 alu.src[0].sel = ctx->temp_reg;
4744 alu.src[0].chan = 0;
4745 alu.dst.sel = ctx->temp_reg;
4746 alu.dst.chan = i;
4747 if (i == 2) {
4748 alu.dst.write = 1;
4749 alu.last = 1;
4750 } else
4751 alu.dst.write = 0;
4752
4753 r = r600_bytecode_add_alu(ctx->bc, &alu);
4754 if (r)
4755 return r;
4756 }
4757 } else {
4758 /* tmp.z = log(tmp.x) */
4759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4760 alu.op = ALU_OP1_LOG_CLAMPED;
4761 alu.src[0].sel = ctx->temp_reg;
4762 alu.src[0].chan = 0;
4763 alu.dst.sel = ctx->temp_reg;
4764 alu.dst.chan = 2;
4765 alu.dst.write = 1;
4766 alu.last = 1;
4767 r = r600_bytecode_add_alu(ctx->bc, &alu);
4768 if (r)
4769 return r;
4770 }
4771
4772 chan = alu.dst.chan;
4773 sel = alu.dst.sel;
4774
4775 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4776 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4777 alu.op = ALU_OP3_MUL_LIT;
4778 alu.src[0].sel = sel;
4779 alu.src[0].chan = chan;
4780 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4781 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4782 alu.dst.sel = ctx->temp_reg;
4783 alu.dst.chan = 0;
4784 alu.dst.write = 1;
4785 alu.is_op3 = 1;
4786 alu.last = 1;
4787 r = r600_bytecode_add_alu(ctx->bc, &alu);
4788 if (r)
4789 return r;
4790
4791 if (ctx->bc->chip_class == CAYMAN) {
4792 for (i = 0; i < 3; i++) {
4793 /* dst.z = exp(tmp.x) */
4794 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4795 alu.op = ALU_OP1_EXP_IEEE;
4796 alu.src[0].sel = ctx->temp_reg;
4797 alu.src[0].chan = 0;
4798 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4799 if (i == 2) {
4800 alu.dst.write = 1;
4801 alu.last = 1;
4802 } else
4803 alu.dst.write = 0;
4804 r = r600_bytecode_add_alu(ctx->bc, &alu);
4805 if (r)
4806 return r;
4807 }
4808 } else {
4809 /* dst.z = exp(tmp.x) */
4810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4811 alu.op = ALU_OP1_EXP_IEEE;
4812 alu.src[0].sel = ctx->temp_reg;
4813 alu.src[0].chan = 0;
4814 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4815 alu.last = 1;
4816 r = r600_bytecode_add_alu(ctx->bc, &alu);
4817 if (r)
4818 return r;
4819 }
4820 }
4821
4822 /* dst.x, <- 1.0 */
4823 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4824 alu.op = ALU_OP1_MOV;
4825 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4826 alu.src[0].chan = 0;
4827 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4828 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4829 r = r600_bytecode_add_alu(ctx->bc, &alu);
4830 if (r)
4831 return r;
4832
4833 /* dst.y = max(src.x, 0.0) */
4834 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4835 alu.op = ALU_OP2_MAX;
4836 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4837 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4838 alu.src[1].chan = 0;
4839 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4840 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4841 r = r600_bytecode_add_alu(ctx->bc, &alu);
4842 if (r)
4843 return r;
4844
4845 /* dst.w, <- 1.0 */
4846 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4847 alu.op = ALU_OP1_MOV;
4848 alu.src[0].sel = V_SQ_ALU_SRC_1;
4849 alu.src[0].chan = 0;
4850 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4851 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4852 alu.last = 1;
4853 r = r600_bytecode_add_alu(ctx->bc, &alu);
4854 if (r)
4855 return r;
4856
4857 return 0;
4858 }
4859
4860 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4861 {
4862 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4863 struct r600_bytecode_alu alu;
4864 int i, r;
4865
4866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4867
4868 /* XXX:
4869 * For state trackers other than OpenGL, we'll want to use
4870 * _RECIPSQRT_IEEE instead.
4871 */
4872 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
4873
4874 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4875 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4876 r600_bytecode_src_set_abs(&alu.src[i]);
4877 }
4878 alu.dst.sel = ctx->temp_reg;
4879 alu.dst.write = 1;
4880 alu.last = 1;
4881 r = r600_bytecode_add_alu(ctx->bc, &alu);
4882 if (r)
4883 return r;
4884 /* replicate result */
4885 return tgsi_helper_tempx_replicate(ctx);
4886 }
4887
4888 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4889 {
4890 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4891 struct r600_bytecode_alu alu;
4892 int i, r;
4893
4894 for (i = 0; i < 4; i++) {
4895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4896 alu.src[0].sel = ctx->temp_reg;
4897 alu.op = ALU_OP1_MOV;
4898 alu.dst.chan = i;
4899 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4900 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4901 if (i == 3)
4902 alu.last = 1;
4903 r = r600_bytecode_add_alu(ctx->bc, &alu);
4904 if (r)
4905 return r;
4906 }
4907 return 0;
4908 }
4909
4910 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4911 {
4912 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4913 struct r600_bytecode_alu alu;
4914 int i, r;
4915
4916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4917 alu.op = ctx->inst_info->op;
4918 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4919 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4920 }
4921 alu.dst.sel = ctx->temp_reg;
4922 alu.dst.write = 1;
4923 alu.last = 1;
4924 r = r600_bytecode_add_alu(ctx->bc, &alu);
4925 if (r)
4926 return r;
4927 /* replicate result */
4928 return tgsi_helper_tempx_replicate(ctx);
4929 }
4930
4931 static int cayman_pow(struct r600_shader_ctx *ctx)
4932 {
4933 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4934 int i, r;
4935 struct r600_bytecode_alu alu;
4936 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4937
4938 for (i = 0; i < 3; i++) {
4939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4940 alu.op = ALU_OP1_LOG_IEEE;
4941 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4942 alu.dst.sel = ctx->temp_reg;
4943 alu.dst.chan = i;
4944 alu.dst.write = 1;
4945 if (i == 2)
4946 alu.last = 1;
4947 r = r600_bytecode_add_alu(ctx->bc, &alu);
4948 if (r)
4949 return r;
4950 }
4951
4952 /* b * LOG2(a) */
4953 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4954 alu.op = ALU_OP2_MUL;
4955 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4956 alu.src[1].sel = ctx->temp_reg;
4957 alu.dst.sel = ctx->temp_reg;
4958 alu.dst.write = 1;
4959 alu.last = 1;
4960 r = r600_bytecode_add_alu(ctx->bc, &alu);
4961 if (r)
4962 return r;
4963
4964 for (i = 0; i < last_slot; i++) {
4965 /* POW(a,b) = EXP2(b * LOG2(a))*/
4966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4967 alu.op = ALU_OP1_EXP_IEEE;
4968 alu.src[0].sel = ctx->temp_reg;
4969
4970 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4971 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4972 if (i == last_slot - 1)
4973 alu.last = 1;
4974 r = r600_bytecode_add_alu(ctx->bc, &alu);
4975 if (r)
4976 return r;
4977 }
4978 return 0;
4979 }
4980
4981 static int tgsi_pow(struct r600_shader_ctx *ctx)
4982 {
4983 struct r600_bytecode_alu alu;
4984 int r;
4985
4986 /* LOG2(a) */
4987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4988 alu.op = ALU_OP1_LOG_IEEE;
4989 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4990 alu.dst.sel = ctx->temp_reg;
4991 alu.dst.write = 1;
4992 alu.last = 1;
4993 r = r600_bytecode_add_alu(ctx->bc, &alu);
4994 if (r)
4995 return r;
4996 /* b * LOG2(a) */
4997 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4998 alu.op = ALU_OP2_MUL;
4999 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5000 alu.src[1].sel = ctx->temp_reg;
5001 alu.dst.sel = ctx->temp_reg;
5002 alu.dst.write = 1;
5003 alu.last = 1;
5004 r = r600_bytecode_add_alu(ctx->bc, &alu);
5005 if (r)
5006 return r;
5007 /* POW(a,b) = EXP2(b * LOG2(a))*/
5008 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5009 alu.op = ALU_OP1_EXP_IEEE;
5010 alu.src[0].sel = ctx->temp_reg;
5011 alu.dst.sel = ctx->temp_reg;
5012 alu.dst.write = 1;
5013 alu.last = 1;
5014 r = r600_bytecode_add_alu(ctx->bc, &alu);
5015 if (r)
5016 return r;
5017 return tgsi_helper_tempx_replicate(ctx);
5018 }
5019
5020 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5021 {
5022 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5023 struct r600_bytecode_alu alu;
5024 int i, r, j;
5025 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5026 int tmp0 = ctx->temp_reg;
5027 int tmp1 = r600_get_temp(ctx);
5028 int tmp2 = r600_get_temp(ctx);
5029 int tmp3 = r600_get_temp(ctx);
5030 /* Unsigned path:
5031 *
5032 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5033 *
5034 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5035 * 2. tmp0.z = lo (tmp0.x * src2)
5036 * 3. tmp0.w = -tmp0.z
5037 * 4. tmp0.y = hi (tmp0.x * src2)
5038 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5039 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5040 * 7. tmp1.x = tmp0.x - tmp0.w
5041 * 8. tmp1.y = tmp0.x + tmp0.w
5042 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5043 * 10. tmp0.z = hi(tmp0.x * src1) = q
5044 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5045 *
5046 * 12. tmp0.w = src1 - tmp0.y = r
5047 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5048 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5049 *
5050 * if DIV
5051 *
5052 * 15. tmp1.z = tmp0.z + 1 = q + 1
5053 * 16. tmp1.w = tmp0.z - 1 = q - 1
5054 *
5055 * else MOD
5056 *
5057 * 15. tmp1.z = tmp0.w - src2 = r - src2
5058 * 16. tmp1.w = tmp0.w + src2 = r + src2
5059 *
5060 * endif
5061 *
5062 * 17. tmp1.x = tmp1.x & tmp1.y
5063 *
5064 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5065 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5066 *
5067 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5068 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5069 *
5070 * Signed path:
5071 *
5072 * Same as unsigned, using abs values of the operands,
5073 * and fixing the sign of the result in the end.
5074 */
5075
5076 for (i = 0; i < 4; i++) {
5077 if (!(write_mask & (1<<i)))
5078 continue;
5079
5080 if (signed_op) {
5081
5082 /* tmp2.x = -src0 */
5083 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5084 alu.op = ALU_OP2_SUB_INT;
5085
5086 alu.dst.sel = tmp2;
5087 alu.dst.chan = 0;
5088 alu.dst.write = 1;
5089
5090 alu.src[0].sel = V_SQ_ALU_SRC_0;
5091
5092 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5093
5094 alu.last = 1;
5095 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5096 return r;
5097
5098 /* tmp2.y = -src1 */
5099 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5100 alu.op = ALU_OP2_SUB_INT;
5101
5102 alu.dst.sel = tmp2;
5103 alu.dst.chan = 1;
5104 alu.dst.write = 1;
5105
5106 alu.src[0].sel = V_SQ_ALU_SRC_0;
5107
5108 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5109
5110 alu.last = 1;
5111 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5112 return r;
5113
5114 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5115 /* it will be a sign of the quotient */
5116 if (!mod) {
5117
5118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5119 alu.op = ALU_OP2_XOR_INT;
5120
5121 alu.dst.sel = tmp2;
5122 alu.dst.chan = 2;
5123 alu.dst.write = 1;
5124
5125 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5126 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5127
5128 alu.last = 1;
5129 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5130 return r;
5131 }
5132
5133 /* tmp2.x = |src0| */
5134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5135 alu.op = ALU_OP3_CNDGE_INT;
5136 alu.is_op3 = 1;
5137
5138 alu.dst.sel = tmp2;
5139 alu.dst.chan = 0;
5140 alu.dst.write = 1;
5141
5142 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5143 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5144 alu.src[2].sel = tmp2;
5145 alu.src[2].chan = 0;
5146
5147 alu.last = 1;
5148 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5149 return r;
5150
5151 /* tmp2.y = |src1| */
5152 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5153 alu.op = ALU_OP3_CNDGE_INT;
5154 alu.is_op3 = 1;
5155
5156 alu.dst.sel = tmp2;
5157 alu.dst.chan = 1;
5158 alu.dst.write = 1;
5159
5160 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5161 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5162 alu.src[2].sel = tmp2;
5163 alu.src[2].chan = 1;
5164
5165 alu.last = 1;
5166 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5167 return r;
5168
5169 }
5170
5171 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5172 if (ctx->bc->chip_class == CAYMAN) {
5173 /* tmp3.x = u2f(src2) */
5174 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5175 alu.op = ALU_OP1_UINT_TO_FLT;
5176
5177 alu.dst.sel = tmp3;
5178 alu.dst.chan = 0;
5179 alu.dst.write = 1;
5180
5181 if (signed_op) {
5182 alu.src[0].sel = tmp2;
5183 alu.src[0].chan = 1;
5184 } else {
5185 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5186 }
5187
5188 alu.last = 1;
5189 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5190 return r;
5191
5192 /* tmp0.x = recip(tmp3.x) */
5193 for (j = 0 ; j < 3; j++) {
5194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5195 alu.op = ALU_OP1_RECIP_IEEE;
5196
5197 alu.dst.sel = tmp0;
5198 alu.dst.chan = j;
5199 alu.dst.write = (j == 0);
5200
5201 alu.src[0].sel = tmp3;
5202 alu.src[0].chan = 0;
5203
5204 if (j == 2)
5205 alu.last = 1;
5206 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5207 return r;
5208 }
5209
5210 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5211 alu.op = ALU_OP2_MUL;
5212
5213 alu.src[0].sel = tmp0;
5214 alu.src[0].chan = 0;
5215
5216 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5217 alu.src[1].value = 0x4f800000;
5218
5219 alu.dst.sel = tmp3;
5220 alu.dst.write = 1;
5221 alu.last = 1;
5222 r = r600_bytecode_add_alu(ctx->bc, &alu);
5223 if (r)
5224 return r;
5225
5226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5227 alu.op = ALU_OP1_FLT_TO_UINT;
5228
5229 alu.dst.sel = tmp0;
5230 alu.dst.chan = 0;
5231 alu.dst.write = 1;
5232
5233 alu.src[0].sel = tmp3;
5234 alu.src[0].chan = 0;
5235
5236 alu.last = 1;
5237 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5238 return r;
5239
5240 } else {
5241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5242 alu.op = ALU_OP1_RECIP_UINT;
5243
5244 alu.dst.sel = tmp0;
5245 alu.dst.chan = 0;
5246 alu.dst.write = 1;
5247
5248 if (signed_op) {
5249 alu.src[0].sel = tmp2;
5250 alu.src[0].chan = 1;
5251 } else {
5252 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5253 }
5254
5255 alu.last = 1;
5256 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5257 return r;
5258 }
5259
5260 /* 2. tmp0.z = lo (tmp0.x * src2) */
5261 if (ctx->bc->chip_class == CAYMAN) {
5262 for (j = 0 ; j < 4; j++) {
5263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5264 alu.op = ALU_OP2_MULLO_UINT;
5265
5266 alu.dst.sel = tmp0;
5267 alu.dst.chan = j;
5268 alu.dst.write = (j == 2);
5269
5270 alu.src[0].sel = tmp0;
5271 alu.src[0].chan = 0;
5272 if (signed_op) {
5273 alu.src[1].sel = tmp2;
5274 alu.src[1].chan = 1;
5275 } else {
5276 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5277 }
5278
5279 alu.last = (j == 3);
5280 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5281 return r;
5282 }
5283 } else {
5284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5285 alu.op = ALU_OP2_MULLO_UINT;
5286
5287 alu.dst.sel = tmp0;
5288 alu.dst.chan = 2;
5289 alu.dst.write = 1;
5290
5291 alu.src[0].sel = tmp0;
5292 alu.src[0].chan = 0;
5293 if (signed_op) {
5294 alu.src[1].sel = tmp2;
5295 alu.src[1].chan = 1;
5296 } else {
5297 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5298 }
5299
5300 alu.last = 1;
5301 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5302 return r;
5303 }
5304
5305 /* 3. tmp0.w = -tmp0.z */
5306 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5307 alu.op = ALU_OP2_SUB_INT;
5308
5309 alu.dst.sel = tmp0;
5310 alu.dst.chan = 3;
5311 alu.dst.write = 1;
5312
5313 alu.src[0].sel = V_SQ_ALU_SRC_0;
5314 alu.src[1].sel = tmp0;
5315 alu.src[1].chan = 2;
5316
5317 alu.last = 1;
5318 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5319 return r;
5320
5321 /* 4. tmp0.y = hi (tmp0.x * src2) */
5322 if (ctx->bc->chip_class == CAYMAN) {
5323 for (j = 0 ; j < 4; j++) {
5324 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5325 alu.op = ALU_OP2_MULHI_UINT;
5326
5327 alu.dst.sel = tmp0;
5328 alu.dst.chan = j;
5329 alu.dst.write = (j == 1);
5330
5331 alu.src[0].sel = tmp0;
5332 alu.src[0].chan = 0;
5333
5334 if (signed_op) {
5335 alu.src[1].sel = tmp2;
5336 alu.src[1].chan = 1;
5337 } else {
5338 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5339 }
5340 alu.last = (j == 3);
5341 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5342 return r;
5343 }
5344 } else {
5345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5346 alu.op = ALU_OP2_MULHI_UINT;
5347
5348 alu.dst.sel = tmp0;
5349 alu.dst.chan = 1;
5350 alu.dst.write = 1;
5351
5352 alu.src[0].sel = tmp0;
5353 alu.src[0].chan = 0;
5354
5355 if (signed_op) {
5356 alu.src[1].sel = tmp2;
5357 alu.src[1].chan = 1;
5358 } else {
5359 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5360 }
5361
5362 alu.last = 1;
5363 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5364 return r;
5365 }
5366
5367 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5368 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5369 alu.op = ALU_OP3_CNDE_INT;
5370 alu.is_op3 = 1;
5371
5372 alu.dst.sel = tmp0;
5373 alu.dst.chan = 2;
5374 alu.dst.write = 1;
5375
5376 alu.src[0].sel = tmp0;
5377 alu.src[0].chan = 1;
5378 alu.src[1].sel = tmp0;
5379 alu.src[1].chan = 3;
5380 alu.src[2].sel = tmp0;
5381 alu.src[2].chan = 2;
5382
5383 alu.last = 1;
5384 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5385 return r;
5386
5387 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5388 if (ctx->bc->chip_class == CAYMAN) {
5389 for (j = 0 ; j < 4; j++) {
5390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5391 alu.op = ALU_OP2_MULHI_UINT;
5392
5393 alu.dst.sel = tmp0;
5394 alu.dst.chan = j;
5395 alu.dst.write = (j == 3);
5396
5397 alu.src[0].sel = tmp0;
5398 alu.src[0].chan = 2;
5399
5400 alu.src[1].sel = tmp0;
5401 alu.src[1].chan = 0;
5402
5403 alu.last = (j == 3);
5404 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5405 return r;
5406 }
5407 } else {
5408 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5409 alu.op = ALU_OP2_MULHI_UINT;
5410
5411 alu.dst.sel = tmp0;
5412 alu.dst.chan = 3;
5413 alu.dst.write = 1;
5414
5415 alu.src[0].sel = tmp0;
5416 alu.src[0].chan = 2;
5417
5418 alu.src[1].sel = tmp0;
5419 alu.src[1].chan = 0;
5420
5421 alu.last = 1;
5422 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5423 return r;
5424 }
5425
5426 /* 7. tmp1.x = tmp0.x - tmp0.w */
5427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5428 alu.op = ALU_OP2_SUB_INT;
5429
5430 alu.dst.sel = tmp1;
5431 alu.dst.chan = 0;
5432 alu.dst.write = 1;
5433
5434 alu.src[0].sel = tmp0;
5435 alu.src[0].chan = 0;
5436 alu.src[1].sel = tmp0;
5437 alu.src[1].chan = 3;
5438
5439 alu.last = 1;
5440 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5441 return r;
5442
5443 /* 8. tmp1.y = tmp0.x + tmp0.w */
5444 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5445 alu.op = ALU_OP2_ADD_INT;
5446
5447 alu.dst.sel = tmp1;
5448 alu.dst.chan = 1;
5449 alu.dst.write = 1;
5450
5451 alu.src[0].sel = tmp0;
5452 alu.src[0].chan = 0;
5453 alu.src[1].sel = tmp0;
5454 alu.src[1].chan = 3;
5455
5456 alu.last = 1;
5457 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5458 return r;
5459
5460 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5462 alu.op = ALU_OP3_CNDE_INT;
5463 alu.is_op3 = 1;
5464
5465 alu.dst.sel = tmp0;
5466 alu.dst.chan = 0;
5467 alu.dst.write = 1;
5468
5469 alu.src[0].sel = tmp0;
5470 alu.src[0].chan = 1;
5471 alu.src[1].sel = tmp1;
5472 alu.src[1].chan = 1;
5473 alu.src[2].sel = tmp1;
5474 alu.src[2].chan = 0;
5475
5476 alu.last = 1;
5477 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5478 return r;
5479
5480 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5481 if (ctx->bc->chip_class == CAYMAN) {
5482 for (j = 0 ; j < 4; j++) {
5483 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5484 alu.op = ALU_OP2_MULHI_UINT;
5485
5486 alu.dst.sel = tmp0;
5487 alu.dst.chan = j;
5488 alu.dst.write = (j == 2);
5489
5490 alu.src[0].sel = tmp0;
5491 alu.src[0].chan = 0;
5492
5493 if (signed_op) {
5494 alu.src[1].sel = tmp2;
5495 alu.src[1].chan = 0;
5496 } else {
5497 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5498 }
5499
5500 alu.last = (j == 3);
5501 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5502 return r;
5503 }
5504 } else {
5505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5506 alu.op = ALU_OP2_MULHI_UINT;
5507
5508 alu.dst.sel = tmp0;
5509 alu.dst.chan = 2;
5510 alu.dst.write = 1;
5511
5512 alu.src[0].sel = tmp0;
5513 alu.src[0].chan = 0;
5514
5515 if (signed_op) {
5516 alu.src[1].sel = tmp2;
5517 alu.src[1].chan = 0;
5518 } else {
5519 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5520 }
5521
5522 alu.last = 1;
5523 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5524 return r;
5525 }
5526
5527 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5528 if (ctx->bc->chip_class == CAYMAN) {
5529 for (j = 0 ; j < 4; j++) {
5530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5531 alu.op = ALU_OP2_MULLO_UINT;
5532
5533 alu.dst.sel = tmp0;
5534 alu.dst.chan = j;
5535 alu.dst.write = (j == 1);
5536
5537 if (signed_op) {
5538 alu.src[0].sel = tmp2;
5539 alu.src[0].chan = 1;
5540 } else {
5541 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5542 }
5543
5544 alu.src[1].sel = tmp0;
5545 alu.src[1].chan = 2;
5546
5547 alu.last = (j == 3);
5548 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5549 return r;
5550 }
5551 } else {
5552 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5553 alu.op = ALU_OP2_MULLO_UINT;
5554
5555 alu.dst.sel = tmp0;
5556 alu.dst.chan = 1;
5557 alu.dst.write = 1;
5558
5559 if (signed_op) {
5560 alu.src[0].sel = tmp2;
5561 alu.src[0].chan = 1;
5562 } else {
5563 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5564 }
5565
5566 alu.src[1].sel = tmp0;
5567 alu.src[1].chan = 2;
5568
5569 alu.last = 1;
5570 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5571 return r;
5572 }
5573
5574 /* 12. tmp0.w = src1 - tmp0.y = r */
5575 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5576 alu.op = ALU_OP2_SUB_INT;
5577
5578 alu.dst.sel = tmp0;
5579 alu.dst.chan = 3;
5580 alu.dst.write = 1;
5581
5582 if (signed_op) {
5583 alu.src[0].sel = tmp2;
5584 alu.src[0].chan = 0;
5585 } else {
5586 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5587 }
5588
5589 alu.src[1].sel = tmp0;
5590 alu.src[1].chan = 1;
5591
5592 alu.last = 1;
5593 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5594 return r;
5595
5596 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5597 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5598 alu.op = ALU_OP2_SETGE_UINT;
5599
5600 alu.dst.sel = tmp1;
5601 alu.dst.chan = 0;
5602 alu.dst.write = 1;
5603
5604 alu.src[0].sel = tmp0;
5605 alu.src[0].chan = 3;
5606 if (signed_op) {
5607 alu.src[1].sel = tmp2;
5608 alu.src[1].chan = 1;
5609 } else {
5610 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5611 }
5612
5613 alu.last = 1;
5614 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5615 return r;
5616
5617 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5618 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5619 alu.op = ALU_OP2_SETGE_UINT;
5620
5621 alu.dst.sel = tmp1;
5622 alu.dst.chan = 1;
5623 alu.dst.write = 1;
5624
5625 if (signed_op) {
5626 alu.src[0].sel = tmp2;
5627 alu.src[0].chan = 0;
5628 } else {
5629 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5630 }
5631
5632 alu.src[1].sel = tmp0;
5633 alu.src[1].chan = 1;
5634
5635 alu.last = 1;
5636 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5637 return r;
5638
5639 if (mod) { /* UMOD */
5640
5641 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5642 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5643 alu.op = ALU_OP2_SUB_INT;
5644
5645 alu.dst.sel = tmp1;
5646 alu.dst.chan = 2;
5647 alu.dst.write = 1;
5648
5649 alu.src[0].sel = tmp0;
5650 alu.src[0].chan = 3;
5651
5652 if (signed_op) {
5653 alu.src[1].sel = tmp2;
5654 alu.src[1].chan = 1;
5655 } else {
5656 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5657 }
5658
5659 alu.last = 1;
5660 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5661 return r;
5662
5663 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5665 alu.op = ALU_OP2_ADD_INT;
5666
5667 alu.dst.sel = tmp1;
5668 alu.dst.chan = 3;
5669 alu.dst.write = 1;
5670
5671 alu.src[0].sel = tmp0;
5672 alu.src[0].chan = 3;
5673 if (signed_op) {
5674 alu.src[1].sel = tmp2;
5675 alu.src[1].chan = 1;
5676 } else {
5677 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5678 }
5679
5680 alu.last = 1;
5681 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5682 return r;
5683
5684 } else { /* UDIV */
5685
5686 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5688 alu.op = ALU_OP2_ADD_INT;
5689
5690 alu.dst.sel = tmp1;
5691 alu.dst.chan = 2;
5692 alu.dst.write = 1;
5693
5694 alu.src[0].sel = tmp0;
5695 alu.src[0].chan = 2;
5696 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5697
5698 alu.last = 1;
5699 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5700 return r;
5701
5702 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5704 alu.op = ALU_OP2_ADD_INT;
5705
5706 alu.dst.sel = tmp1;
5707 alu.dst.chan = 3;
5708 alu.dst.write = 1;
5709
5710 alu.src[0].sel = tmp0;
5711 alu.src[0].chan = 2;
5712 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5713
5714 alu.last = 1;
5715 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5716 return r;
5717
5718 }
5719
5720 /* 17. tmp1.x = tmp1.x & tmp1.y */
5721 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5722 alu.op = ALU_OP2_AND_INT;
5723
5724 alu.dst.sel = tmp1;
5725 alu.dst.chan = 0;
5726 alu.dst.write = 1;
5727
5728 alu.src[0].sel = tmp1;
5729 alu.src[0].chan = 0;
5730 alu.src[1].sel = tmp1;
5731 alu.src[1].chan = 1;
5732
5733 alu.last = 1;
5734 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5735 return r;
5736
5737 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5738 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5739 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5740 alu.op = ALU_OP3_CNDE_INT;
5741 alu.is_op3 = 1;
5742
5743 alu.dst.sel = tmp0;
5744 alu.dst.chan = 2;
5745 alu.dst.write = 1;
5746
5747 alu.src[0].sel = tmp1;
5748 alu.src[0].chan = 0;
5749 alu.src[1].sel = tmp0;
5750 alu.src[1].chan = mod ? 3 : 2;
5751 alu.src[2].sel = tmp1;
5752 alu.src[2].chan = 2;
5753
5754 alu.last = 1;
5755 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5756 return r;
5757
5758 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5760 alu.op = ALU_OP3_CNDE_INT;
5761 alu.is_op3 = 1;
5762
5763 if (signed_op) {
5764 alu.dst.sel = tmp0;
5765 alu.dst.chan = 2;
5766 alu.dst.write = 1;
5767 } else {
5768 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5769 }
5770
5771 alu.src[0].sel = tmp1;
5772 alu.src[0].chan = 1;
5773 alu.src[1].sel = tmp1;
5774 alu.src[1].chan = 3;
5775 alu.src[2].sel = tmp0;
5776 alu.src[2].chan = 2;
5777
5778 alu.last = 1;
5779 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5780 return r;
5781
5782 if (signed_op) {
5783
5784 /* fix the sign of the result */
5785
5786 if (mod) {
5787
5788 /* tmp0.x = -tmp0.z */
5789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5790 alu.op = ALU_OP2_SUB_INT;
5791
5792 alu.dst.sel = tmp0;
5793 alu.dst.chan = 0;
5794 alu.dst.write = 1;
5795
5796 alu.src[0].sel = V_SQ_ALU_SRC_0;
5797 alu.src[1].sel = tmp0;
5798 alu.src[1].chan = 2;
5799
5800 alu.last = 1;
5801 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5802 return r;
5803
5804 /* sign of the remainder is the same as the sign of src0 */
5805 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5806 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5807 alu.op = ALU_OP3_CNDGE_INT;
5808 alu.is_op3 = 1;
5809
5810 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5811
5812 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5813 alu.src[1].sel = tmp0;
5814 alu.src[1].chan = 2;
5815 alu.src[2].sel = tmp0;
5816 alu.src[2].chan = 0;
5817
5818 alu.last = 1;
5819 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5820 return r;
5821
5822 } else {
5823
5824 /* tmp0.x = -tmp0.z */
5825 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5826 alu.op = ALU_OP2_SUB_INT;
5827
5828 alu.dst.sel = tmp0;
5829 alu.dst.chan = 0;
5830 alu.dst.write = 1;
5831
5832 alu.src[0].sel = V_SQ_ALU_SRC_0;
5833 alu.src[1].sel = tmp0;
5834 alu.src[1].chan = 2;
5835
5836 alu.last = 1;
5837 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5838 return r;
5839
5840 /* fix the quotient sign (same as the sign of src0*src1) */
5841 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5842 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5843 alu.op = ALU_OP3_CNDGE_INT;
5844 alu.is_op3 = 1;
5845
5846 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5847
5848 alu.src[0].sel = tmp2;
5849 alu.src[0].chan = 2;
5850 alu.src[1].sel = tmp0;
5851 alu.src[1].chan = 2;
5852 alu.src[2].sel = tmp0;
5853 alu.src[2].chan = 0;
5854
5855 alu.last = 1;
5856 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5857 return r;
5858 }
5859 }
5860 }
5861 return 0;
5862 }
5863
5864 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5865 {
5866 return tgsi_divmod(ctx, 0, 0);
5867 }
5868
5869 static int tgsi_umod(struct r600_shader_ctx *ctx)
5870 {
5871 return tgsi_divmod(ctx, 1, 0);
5872 }
5873
5874 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5875 {
5876 return tgsi_divmod(ctx, 0, 1);
5877 }
5878
5879 static int tgsi_imod(struct r600_shader_ctx *ctx)
5880 {
5881 return tgsi_divmod(ctx, 1, 1);
5882 }
5883
5884
5885 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5886 {
5887 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5888 struct r600_bytecode_alu alu;
5889 int i, r;
5890 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5891 int last_inst = tgsi_last_instruction(write_mask);
5892
5893 for (i = 0; i < 4; i++) {
5894 if (!(write_mask & (1<<i)))
5895 continue;
5896
5897 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5898 alu.op = ALU_OP1_TRUNC;
5899
5900 alu.dst.sel = ctx->temp_reg;
5901 alu.dst.chan = i;
5902 alu.dst.write = 1;
5903
5904 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5905 if (i == last_inst)
5906 alu.last = 1;
5907 r = r600_bytecode_add_alu(ctx->bc, &alu);
5908 if (r)
5909 return r;
5910 }
5911
5912 for (i = 0; i < 4; i++) {
5913 if (!(write_mask & (1<<i)))
5914 continue;
5915
5916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5917 alu.op = ctx->inst_info->op;
5918
5919 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5920
5921 alu.src[0].sel = ctx->temp_reg;
5922 alu.src[0].chan = i;
5923
5924 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5925 alu.last = 1;
5926 r = r600_bytecode_add_alu(ctx->bc, &alu);
5927 if (r)
5928 return r;
5929 }
5930
5931 return 0;
5932 }
5933
5934 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5935 {
5936 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5937 struct r600_bytecode_alu alu;
5938 int i, r;
5939 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5940 int last_inst = tgsi_last_instruction(write_mask);
5941
5942 /* tmp = -src */
5943 for (i = 0; i < 4; i++) {
5944 if (!(write_mask & (1<<i)))
5945 continue;
5946
5947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5948 alu.op = ALU_OP2_SUB_INT;
5949
5950 alu.dst.sel = ctx->temp_reg;
5951 alu.dst.chan = i;
5952 alu.dst.write = 1;
5953
5954 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5955 alu.src[0].sel = V_SQ_ALU_SRC_0;
5956
5957 if (i == last_inst)
5958 alu.last = 1;
5959 r = r600_bytecode_add_alu(ctx->bc, &alu);
5960 if (r)
5961 return r;
5962 }
5963
5964 /* dst = (src >= 0 ? src : tmp) */
5965 for (i = 0; i < 4; i++) {
5966 if (!(write_mask & (1<<i)))
5967 continue;
5968
5969 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5970 alu.op = ALU_OP3_CNDGE_INT;
5971 alu.is_op3 = 1;
5972 alu.dst.write = 1;
5973
5974 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5975
5976 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5977 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5978 alu.src[2].sel = ctx->temp_reg;
5979 alu.src[2].chan = i;
5980
5981 if (i == last_inst)
5982 alu.last = 1;
5983 r = r600_bytecode_add_alu(ctx->bc, &alu);
5984 if (r)
5985 return r;
5986 }
5987 return 0;
5988 }
5989
5990 static int tgsi_issg(struct r600_shader_ctx *ctx)
5991 {
5992 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5993 struct r600_bytecode_alu alu;
5994 int i, r;
5995 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5996 int last_inst = tgsi_last_instruction(write_mask);
5997
5998 /* tmp = (src >= 0 ? src : -1) */
5999 for (i = 0; i < 4; i++) {
6000 if (!(write_mask & (1<<i)))
6001 continue;
6002
6003 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6004 alu.op = ALU_OP3_CNDGE_INT;
6005 alu.is_op3 = 1;
6006
6007 alu.dst.sel = ctx->temp_reg;
6008 alu.dst.chan = i;
6009 alu.dst.write = 1;
6010
6011 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6012 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6013 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6014
6015 if (i == last_inst)
6016 alu.last = 1;
6017 r = r600_bytecode_add_alu(ctx->bc, &alu);
6018 if (r)
6019 return r;
6020 }
6021
6022 /* dst = (tmp > 0 ? 1 : tmp) */
6023 for (i = 0; i < 4; i++) {
6024 if (!(write_mask & (1<<i)))
6025 continue;
6026
6027 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6028 alu.op = ALU_OP3_CNDGT_INT;
6029 alu.is_op3 = 1;
6030 alu.dst.write = 1;
6031
6032 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6033
6034 alu.src[0].sel = ctx->temp_reg;
6035 alu.src[0].chan = i;
6036
6037 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6038
6039 alu.src[2].sel = ctx->temp_reg;
6040 alu.src[2].chan = i;
6041
6042 if (i == last_inst)
6043 alu.last = 1;
6044 r = r600_bytecode_add_alu(ctx->bc, &alu);
6045 if (r)
6046 return r;
6047 }
6048 return 0;
6049 }
6050
6051
6052
6053 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6054 {
6055 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6056 struct r600_bytecode_alu alu;
6057 int i, r;
6058
6059 /* tmp = (src > 0 ? 1 : src) */
6060 for (i = 0; i < 4; i++) {
6061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6062 alu.op = ALU_OP3_CNDGT;
6063 alu.is_op3 = 1;
6064
6065 alu.dst.sel = ctx->temp_reg;
6066 alu.dst.chan = i;
6067
6068 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6069 alu.src[1].sel = V_SQ_ALU_SRC_1;
6070 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6071
6072 if (i == 3)
6073 alu.last = 1;
6074 r = r600_bytecode_add_alu(ctx->bc, &alu);
6075 if (r)
6076 return r;
6077 }
6078
6079 /* dst = (-tmp > 0 ? -1 : tmp) */
6080 for (i = 0; i < 4; i++) {
6081 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6082 alu.op = ALU_OP3_CNDGT;
6083 alu.is_op3 = 1;
6084 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6085
6086 alu.src[0].sel = ctx->temp_reg;
6087 alu.src[0].chan = i;
6088 alu.src[0].neg = 1;
6089
6090 alu.src[1].sel = V_SQ_ALU_SRC_1;
6091 alu.src[1].neg = 1;
6092
6093 alu.src[2].sel = ctx->temp_reg;
6094 alu.src[2].chan = i;
6095
6096 if (i == 3)
6097 alu.last = 1;
6098 r = r600_bytecode_add_alu(ctx->bc, &alu);
6099 if (r)
6100 return r;
6101 }
6102 return 0;
6103 }
6104
6105 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6106 {
6107 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6108 struct r600_bytecode_alu alu;
6109 int i, r, t1, t2;
6110
6111 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6112 int last_inst = tgsi_last_instruction(write_mask);
6113
6114 t1 = ctx->temp_reg;
6115
6116 for (i = 0; i < 4; i++) {
6117 if (!(write_mask & (1<<i)))
6118 continue;
6119
6120 /* create mask tmp */
6121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6122 alu.op = ALU_OP2_BFM_INT;
6123 alu.dst.sel = t1;
6124 alu.dst.chan = i;
6125 alu.dst.write = 1;
6126 alu.last = i == last_inst;
6127
6128 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6129 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6130
6131 r = r600_bytecode_add_alu(ctx->bc, &alu);
6132 if (r)
6133 return r;
6134 }
6135
6136 t2 = r600_get_temp(ctx);
6137
6138 for (i = 0; i < 4; i++) {
6139 if (!(write_mask & (1<<i)))
6140 continue;
6141
6142 /* shift insert left */
6143 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6144 alu.op = ALU_OP2_LSHL_INT;
6145 alu.dst.sel = t2;
6146 alu.dst.chan = i;
6147 alu.dst.write = 1;
6148 alu.last = i == last_inst;
6149
6150 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6151 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6152
6153 r = r600_bytecode_add_alu(ctx->bc, &alu);
6154 if (r)
6155 return r;
6156 }
6157
6158 for (i = 0; i < 4; i++) {
6159 if (!(write_mask & (1<<i)))
6160 continue;
6161
6162 /* actual bitfield insert */
6163 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6164 alu.op = ALU_OP3_BFI_INT;
6165 alu.is_op3 = 1;
6166 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6167 alu.dst.chan = i;
6168 alu.dst.write = 1;
6169 alu.last = i == last_inst;
6170
6171 alu.src[0].sel = t1;
6172 alu.src[0].chan = i;
6173 alu.src[1].sel = t2;
6174 alu.src[1].chan = i;
6175 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6176
6177 r = r600_bytecode_add_alu(ctx->bc, &alu);
6178 if (r)
6179 return r;
6180 }
6181
6182 return 0;
6183 }
6184
6185 static int tgsi_msb(struct r600_shader_ctx *ctx)
6186 {
6187 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6188 struct r600_bytecode_alu alu;
6189 int i, r, t1, t2;
6190
6191 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6192 int last_inst = tgsi_last_instruction(write_mask);
6193
6194 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6195 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6196
6197 t1 = ctx->temp_reg;
6198
6199 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6200 for (i = 0; i < 4; i++) {
6201 if (!(write_mask & (1<<i)))
6202 continue;
6203
6204 /* t1 = FFBH_INT / FFBH_UINT */
6205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6206 alu.op = ctx->inst_info->op;
6207 alu.dst.sel = t1;
6208 alu.dst.chan = i;
6209 alu.dst.write = 1;
6210 alu.last = i == last_inst;
6211
6212 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6213
6214 r = r600_bytecode_add_alu(ctx->bc, &alu);
6215 if (r)
6216 return r;
6217 }
6218
6219 t2 = r600_get_temp(ctx);
6220
6221 for (i = 0; i < 4; i++) {
6222 if (!(write_mask & (1<<i)))
6223 continue;
6224
6225 /* t2 = 31 - t1 */
6226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6227 alu.op = ALU_OP2_SUB_INT;
6228 alu.dst.sel = t2;
6229 alu.dst.chan = i;
6230 alu.dst.write = 1;
6231 alu.last = i == last_inst;
6232
6233 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6234 alu.src[0].value = 31;
6235 alu.src[1].sel = t1;
6236 alu.src[1].chan = i;
6237
6238 r = r600_bytecode_add_alu(ctx->bc, &alu);
6239 if (r)
6240 return r;
6241 }
6242
6243 for (i = 0; i < 4; i++) {
6244 if (!(write_mask & (1<<i)))
6245 continue;
6246
6247 /* result = t1 >= 0 ? t2 : t1 */
6248 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6249 alu.op = ALU_OP3_CNDGE_INT;
6250 alu.is_op3 = 1;
6251 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6252 alu.dst.chan = i;
6253 alu.dst.write = 1;
6254 alu.last = i == last_inst;
6255
6256 alu.src[0].sel = t1;
6257 alu.src[0].chan = i;
6258 alu.src[1].sel = t2;
6259 alu.src[1].chan = i;
6260 alu.src[2].sel = t1;
6261 alu.src[2].chan = i;
6262
6263 r = r600_bytecode_add_alu(ctx->bc, &alu);
6264 if (r)
6265 return r;
6266 }
6267
6268 return 0;
6269 }
6270
6271 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6272 {
6273 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6274 struct r600_bytecode_alu alu;
6275 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6276 unsigned location;
6277 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6278
6279 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6280
6281 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6282 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6283 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6284 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6285 }
6286 else {
6287 location = TGSI_INTERPOLATE_LOC_CENTROID;
6288 }
6289
6290 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6291 if (k < 0)
6292 k = 0;
6293 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6294 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6295
6296 /* NOTE: currently offset is not perspective correct */
6297 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6298 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6299 int sample_gpr = -1;
6300 int gradientsH, gradientsV;
6301 struct r600_bytecode_tex tex;
6302
6303 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6304 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6305 }
6306
6307 gradientsH = r600_get_temp(ctx);
6308 gradientsV = r600_get_temp(ctx);
6309 for (i = 0; i < 2; i++) {
6310 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6311 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6312 tex.src_gpr = interp_gpr;
6313 tex.src_sel_x = interp_base_chan + 0;
6314 tex.src_sel_y = interp_base_chan + 1;
6315 tex.src_sel_z = 0;
6316 tex.src_sel_w = 0;
6317 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6318 tex.dst_sel_x = 0;
6319 tex.dst_sel_y = 1;
6320 tex.dst_sel_z = 7;
6321 tex.dst_sel_w = 7;
6322 tex.inst_mod = 1; // Use per pixel gradient calculation
6323 tex.sampler_id = 0;
6324 tex.resource_id = tex.sampler_id;
6325 r = r600_bytecode_add_tex(ctx->bc, &tex);
6326 if (r)
6327 return r;
6328 }
6329
6330 for (i = 0; i < 2; i++) {
6331 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6332 alu.op = ALU_OP3_MULADD;
6333 alu.is_op3 = 1;
6334 alu.src[0].sel = gradientsH;
6335 alu.src[0].chan = i;
6336 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6337 alu.src[1].sel = sample_gpr;
6338 alu.src[1].chan = 2;
6339 }
6340 else {
6341 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6342 }
6343 alu.src[2].sel = interp_gpr;
6344 alu.src[2].chan = interp_base_chan + i;
6345 alu.dst.sel = ctx->temp_reg;
6346 alu.dst.chan = i;
6347 alu.last = i == 1;
6348
6349 r = r600_bytecode_add_alu(ctx->bc, &alu);
6350 if (r)
6351 return r;
6352 }
6353
6354 for (i = 0; i < 2; i++) {
6355 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6356 alu.op = ALU_OP3_MULADD;
6357 alu.is_op3 = 1;
6358 alu.src[0].sel = gradientsV;
6359 alu.src[0].chan = i;
6360 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6361 alu.src[1].sel = sample_gpr;
6362 alu.src[1].chan = 3;
6363 }
6364 else {
6365 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6366 }
6367 alu.src[2].sel = ctx->temp_reg;
6368 alu.src[2].chan = i;
6369 alu.dst.sel = ctx->temp_reg;
6370 alu.dst.chan = i;
6371 alu.last = i == 1;
6372
6373 r = r600_bytecode_add_alu(ctx->bc, &alu);
6374 if (r)
6375 return r;
6376 }
6377 }
6378
6379 tmp = r600_get_temp(ctx);
6380 for (i = 0; i < 8; i++) {
6381 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6382 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6383
6384 alu.dst.sel = tmp;
6385 if ((i > 1 && i < 6)) {
6386 alu.dst.write = 1;
6387 }
6388 else {
6389 alu.dst.write = 0;
6390 }
6391 alu.dst.chan = i % 4;
6392
6393 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6394 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6395 alu.src[0].sel = ctx->temp_reg;
6396 alu.src[0].chan = 1 - (i % 2);
6397 } else {
6398 alu.src[0].sel = interp_gpr;
6399 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6400 }
6401 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6402 alu.src[1].chan = 0;
6403
6404 alu.last = i % 4 == 3;
6405 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6406
6407 r = r600_bytecode_add_alu(ctx->bc, &alu);
6408 if (r)
6409 return r;
6410 }
6411
6412 // INTERP can't swizzle dst
6413 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6414 for (i = 0; i <= lasti; i++) {
6415 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6416 continue;
6417
6418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6419 alu.op = ALU_OP1_MOV;
6420 alu.src[0].sel = tmp;
6421 alu.src[0].chan = ctx->src[0].swizzle[i];
6422 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6423 alu.dst.write = 1;
6424 alu.last = i == lasti;
6425 r = r600_bytecode_add_alu(ctx->bc, &alu);
6426 if (r)
6427 return r;
6428 }
6429
6430 return 0;
6431 }
6432
6433
6434 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6435 {
6436 struct r600_bytecode_alu alu;
6437 int i, r;
6438
6439 for (i = 0; i < 4; i++) {
6440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6441 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6442 alu.op = ALU_OP0_NOP;
6443 alu.dst.chan = i;
6444 } else {
6445 alu.op = ALU_OP1_MOV;
6446 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6447 alu.src[0].sel = ctx->temp_reg;
6448 alu.src[0].chan = i;
6449 }
6450 if (i == 3) {
6451 alu.last = 1;
6452 }
6453 r = r600_bytecode_add_alu(ctx->bc, &alu);
6454 if (r)
6455 return r;
6456 }
6457 return 0;
6458 }
6459
6460 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6461 unsigned temp, int chan,
6462 struct r600_bytecode_alu_src *bc_src,
6463 const struct r600_shader_src *shader_src)
6464 {
6465 struct r600_bytecode_alu alu;
6466 int r;
6467
6468 r600_bytecode_src(bc_src, shader_src, chan);
6469
6470 /* op3 operands don't support abs modifier */
6471 if (bc_src->abs) {
6472 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6473 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6474 alu.op = ALU_OP1_MOV;
6475 alu.dst.sel = temp;
6476 alu.dst.chan = chan;
6477 alu.dst.write = 1;
6478
6479 alu.src[0] = *bc_src;
6480 alu.last = true; // sufficient?
6481 r = r600_bytecode_add_alu(ctx->bc, &alu);
6482 if (r)
6483 return r;
6484
6485 memset(bc_src, 0, sizeof(*bc_src));
6486 bc_src->sel = temp;
6487 bc_src->chan = chan;
6488 }
6489 return 0;
6490 }
6491
6492 static int tgsi_op3(struct r600_shader_ctx *ctx)
6493 {
6494 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6495 struct r600_bytecode_alu alu;
6496 int i, j, r;
6497 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6498 int temp_regs[4];
6499 unsigned op = ctx->inst_info->op;
6500
6501 if (op == ALU_OP3_MULADD_IEEE &&
6502 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6503 op = ALU_OP3_MULADD;
6504
6505 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6506 temp_regs[j] = 0;
6507 if (ctx->src[j].abs)
6508 temp_regs[j] = r600_get_temp(ctx);
6509 }
6510 for (i = 0; i < lasti + 1; i++) {
6511 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6512 continue;
6513
6514 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6515 alu.op = op;
6516 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6517 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6518 if (r)
6519 return r;
6520 }
6521
6522 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6523 alu.dst.chan = i;
6524 alu.dst.write = 1;
6525 alu.is_op3 = 1;
6526 if (i == lasti) {
6527 alu.last = 1;
6528 }
6529 r = r600_bytecode_add_alu(ctx->bc, &alu);
6530 if (r)
6531 return r;
6532 }
6533 return 0;
6534 }
6535
6536 static int tgsi_dp(struct r600_shader_ctx *ctx)
6537 {
6538 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6539 struct r600_bytecode_alu alu;
6540 int i, j, r;
6541 unsigned op = ctx->inst_info->op;
6542 if (op == ALU_OP2_DOT4_IEEE &&
6543 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6544 op = ALU_OP2_DOT4;
6545
6546 for (i = 0; i < 4; i++) {
6547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6548 alu.op = op;
6549 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6550 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6551 }
6552
6553 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6554 alu.dst.chan = i;
6555 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6556 /* handle some special cases */
6557 switch (inst->Instruction.Opcode) {
6558 case TGSI_OPCODE_DP2:
6559 if (i > 1) {
6560 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6561 alu.src[0].chan = alu.src[1].chan = 0;
6562 }
6563 break;
6564 case TGSI_OPCODE_DP3:
6565 if (i > 2) {
6566 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6567 alu.src[0].chan = alu.src[1].chan = 0;
6568 }
6569 break;
6570 default:
6571 break;
6572 }
6573 if (i == 3) {
6574 alu.last = 1;
6575 }
6576 r = r600_bytecode_add_alu(ctx->bc, &alu);
6577 if (r)
6578 return r;
6579 }
6580 return 0;
6581 }
6582
6583 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6584 unsigned index)
6585 {
6586 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6587 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6588 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6589 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6590 ctx->src[index].neg || ctx->src[index].abs ||
6591 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6592 }
6593
6594 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6595 unsigned index)
6596 {
6597 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6598 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6599 }
6600
6601 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6602 {
6603 struct r600_bytecode_vtx vtx;
6604 struct r600_bytecode_alu alu;
6605 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6606 int src_gpr, r, i;
6607 int id = tgsi_tex_get_src_gpr(ctx, 1);
6608
6609 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6610 if (src_requires_loading) {
6611 for (i = 0; i < 4; i++) {
6612 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6613 alu.op = ALU_OP1_MOV;
6614 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6615 alu.dst.sel = ctx->temp_reg;
6616 alu.dst.chan = i;
6617 if (i == 3)
6618 alu.last = 1;
6619 alu.dst.write = 1;
6620 r = r600_bytecode_add_alu(ctx->bc, &alu);
6621 if (r)
6622 return r;
6623 }
6624 src_gpr = ctx->temp_reg;
6625 }
6626
6627 memset(&vtx, 0, sizeof(vtx));
6628 vtx.op = FETCH_OP_VFETCH;
6629 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6630 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6631 vtx.src_gpr = src_gpr;
6632 vtx.mega_fetch_count = 16;
6633 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6634 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6635 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6636 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6637 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6638 vtx.use_const_fields = 1;
6639
6640 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6641 return r;
6642
6643 if (ctx->bc->chip_class >= EVERGREEN)
6644 return 0;
6645
6646 for (i = 0; i < 4; i++) {
6647 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6648 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6649 continue;
6650
6651 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6652 alu.op = ALU_OP2_AND_INT;
6653
6654 alu.dst.chan = i;
6655 alu.dst.sel = vtx.dst_gpr;
6656 alu.dst.write = 1;
6657
6658 alu.src[0].sel = vtx.dst_gpr;
6659 alu.src[0].chan = i;
6660
6661 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6662 alu.src[1].sel += (id * 2);
6663 alu.src[1].chan = i % 4;
6664 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6665
6666 if (i == lasti)
6667 alu.last = 1;
6668 r = r600_bytecode_add_alu(ctx->bc, &alu);
6669 if (r)
6670 return r;
6671 }
6672
6673 if (inst->Dst[0].Register.WriteMask & 3) {
6674 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6675 alu.op = ALU_OP2_OR_INT;
6676
6677 alu.dst.chan = 3;
6678 alu.dst.sel = vtx.dst_gpr;
6679 alu.dst.write = 1;
6680
6681 alu.src[0].sel = vtx.dst_gpr;
6682 alu.src[0].chan = 3;
6683
6684 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6685 alu.src[1].chan = 0;
6686 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6687
6688 alu.last = 1;
6689 r = r600_bytecode_add_alu(ctx->bc, &alu);
6690 if (r)
6691 return r;
6692 }
6693 return 0;
6694 }
6695
6696 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6697 {
6698 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6699 struct r600_bytecode_alu alu;
6700 int r;
6701 int id = tgsi_tex_get_src_gpr(ctx, 1);
6702
6703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6704 alu.op = ALU_OP1_MOV;
6705 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6706 if (ctx->bc->chip_class >= EVERGREEN) {
6707 /* channel 0 or 2 of each word */
6708 alu.src[0].sel += (id / 2);
6709 alu.src[0].chan = (id % 2) * 2;
6710 } else {
6711 /* r600 we have them at channel 2 of the second dword */
6712 alu.src[0].sel += (id * 2) + 1;
6713 alu.src[0].chan = 1;
6714 }
6715 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6716 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6717 alu.last = 1;
6718 r = r600_bytecode_add_alu(ctx->bc, &alu);
6719 if (r)
6720 return r;
6721 return 0;
6722 }
6723
6724 static int tgsi_tex(struct r600_shader_ctx *ctx)
6725 {
6726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6727 struct r600_bytecode_tex tex;
6728 struct r600_bytecode_alu alu;
6729 unsigned src_gpr;
6730 int r, i, j;
6731 int opcode;
6732 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6733 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6734 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6735 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6736
6737 bool txf_add_offsets = inst->Texture.NumOffsets &&
6738 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6739 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6740
6741 /* Texture fetch instructions can only use gprs as source.
6742 * Also they cannot negate the source or take the absolute value */
6743 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6744 tgsi_tex_src_requires_loading(ctx, 0)) ||
6745 read_compressed_msaa || txf_add_offsets;
6746
6747 boolean src_loaded = FALSE;
6748 unsigned sampler_src_reg = 1;
6749 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6750 boolean has_txq_cube_array_z = false;
6751 unsigned sampler_index_mode;
6752
6753 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6754 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6755 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6756 if (inst->Dst[0].Register.WriteMask & 4) {
6757 ctx->shader->has_txq_cube_array_z_comp = true;
6758 has_txq_cube_array_z = true;
6759 }
6760
6761 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6762 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6763 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6764 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6765 sampler_src_reg = 2;
6766
6767 /* TGSI moves the sampler to src reg 3 for TXD */
6768 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6769 sampler_src_reg = 3;
6770
6771 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6772
6773 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6774
6775 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6776 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6777 ctx->shader->uses_tex_buffers = true;
6778 return r600_do_buffer_txq(ctx);
6779 }
6780 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6781 if (ctx->bc->chip_class < EVERGREEN)
6782 ctx->shader->uses_tex_buffers = true;
6783 return do_vtx_fetch_inst(ctx, src_requires_loading);
6784 }
6785 }
6786
6787 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6788 int out_chan;
6789 /* Add perspective divide */
6790 if (ctx->bc->chip_class == CAYMAN) {
6791 out_chan = 2;
6792 for (i = 0; i < 3; i++) {
6793 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6794 alu.op = ALU_OP1_RECIP_IEEE;
6795 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6796
6797 alu.dst.sel = ctx->temp_reg;
6798 alu.dst.chan = i;
6799 if (i == 2)
6800 alu.last = 1;
6801 if (out_chan == i)
6802 alu.dst.write = 1;
6803 r = r600_bytecode_add_alu(ctx->bc, &alu);
6804 if (r)
6805 return r;
6806 }
6807
6808 } else {
6809 out_chan = 3;
6810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6811 alu.op = ALU_OP1_RECIP_IEEE;
6812 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6813
6814 alu.dst.sel = ctx->temp_reg;
6815 alu.dst.chan = out_chan;
6816 alu.last = 1;
6817 alu.dst.write = 1;
6818 r = r600_bytecode_add_alu(ctx->bc, &alu);
6819 if (r)
6820 return r;
6821 }
6822
6823 for (i = 0; i < 3; i++) {
6824 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6825 alu.op = ALU_OP2_MUL;
6826 alu.src[0].sel = ctx->temp_reg;
6827 alu.src[0].chan = out_chan;
6828 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6829 alu.dst.sel = ctx->temp_reg;
6830 alu.dst.chan = i;
6831 alu.dst.write = 1;
6832 r = r600_bytecode_add_alu(ctx->bc, &alu);
6833 if (r)
6834 return r;
6835 }
6836 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6837 alu.op = ALU_OP1_MOV;
6838 alu.src[0].sel = V_SQ_ALU_SRC_1;
6839 alu.src[0].chan = 0;
6840 alu.dst.sel = ctx->temp_reg;
6841 alu.dst.chan = 3;
6842 alu.last = 1;
6843 alu.dst.write = 1;
6844 r = r600_bytecode_add_alu(ctx->bc, &alu);
6845 if (r)
6846 return r;
6847 src_loaded = TRUE;
6848 src_gpr = ctx->temp_reg;
6849 }
6850
6851
6852 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6853 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6854 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6855 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6856 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
6857
6858 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6859 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6860
6861 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6862 for (i = 0; i < 4; i++) {
6863 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6864 alu.op = ALU_OP2_CUBE;
6865 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6866 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6867 alu.dst.sel = ctx->temp_reg;
6868 alu.dst.chan = i;
6869 if (i == 3)
6870 alu.last = 1;
6871 alu.dst.write = 1;
6872 r = r600_bytecode_add_alu(ctx->bc, &alu);
6873 if (r)
6874 return r;
6875 }
6876
6877 /* tmp1.z = RCP_e(|tmp1.z|) */
6878 if (ctx->bc->chip_class == CAYMAN) {
6879 for (i = 0; i < 3; i++) {
6880 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6881 alu.op = ALU_OP1_RECIP_IEEE;
6882 alu.src[0].sel = ctx->temp_reg;
6883 alu.src[0].chan = 2;
6884 alu.src[0].abs = 1;
6885 alu.dst.sel = ctx->temp_reg;
6886 alu.dst.chan = i;
6887 if (i == 2)
6888 alu.dst.write = 1;
6889 if (i == 2)
6890 alu.last = 1;
6891 r = r600_bytecode_add_alu(ctx->bc, &alu);
6892 if (r)
6893 return r;
6894 }
6895 } else {
6896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6897 alu.op = ALU_OP1_RECIP_IEEE;
6898 alu.src[0].sel = ctx->temp_reg;
6899 alu.src[0].chan = 2;
6900 alu.src[0].abs = 1;
6901 alu.dst.sel = ctx->temp_reg;
6902 alu.dst.chan = 2;
6903 alu.dst.write = 1;
6904 alu.last = 1;
6905 r = r600_bytecode_add_alu(ctx->bc, &alu);
6906 if (r)
6907 return r;
6908 }
6909
6910 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6911 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6912 * muladd has no writemask, have to use another temp
6913 */
6914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6915 alu.op = ALU_OP3_MULADD;
6916 alu.is_op3 = 1;
6917
6918 alu.src[0].sel = ctx->temp_reg;
6919 alu.src[0].chan = 0;
6920 alu.src[1].sel = ctx->temp_reg;
6921 alu.src[1].chan = 2;
6922
6923 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6924 alu.src[2].chan = 0;
6925 alu.src[2].value = u_bitcast_f2u(1.5f);
6926
6927 alu.dst.sel = ctx->temp_reg;
6928 alu.dst.chan = 0;
6929 alu.dst.write = 1;
6930
6931 r = r600_bytecode_add_alu(ctx->bc, &alu);
6932 if (r)
6933 return r;
6934
6935 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6936 alu.op = ALU_OP3_MULADD;
6937 alu.is_op3 = 1;
6938
6939 alu.src[0].sel = ctx->temp_reg;
6940 alu.src[0].chan = 1;
6941 alu.src[1].sel = ctx->temp_reg;
6942 alu.src[1].chan = 2;
6943
6944 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6945 alu.src[2].chan = 0;
6946 alu.src[2].value = u_bitcast_f2u(1.5f);
6947
6948 alu.dst.sel = ctx->temp_reg;
6949 alu.dst.chan = 1;
6950 alu.dst.write = 1;
6951
6952 alu.last = 1;
6953 r = r600_bytecode_add_alu(ctx->bc, &alu);
6954 if (r)
6955 return r;
6956 /* write initial compare value into Z component
6957 - W src 0 for shadow cube
6958 - X src 1 for shadow cube array */
6959 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6960 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6961 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6962 alu.op = ALU_OP1_MOV;
6963 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
6964 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
6965 else
6966 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6967 alu.dst.sel = ctx->temp_reg;
6968 alu.dst.chan = 2;
6969 alu.dst.write = 1;
6970 alu.last = 1;
6971 r = r600_bytecode_add_alu(ctx->bc, &alu);
6972 if (r)
6973 return r;
6974 }
6975
6976 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6977 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6978 if (ctx->bc->chip_class >= EVERGREEN) {
6979 int mytmp = r600_get_temp(ctx);
6980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6981 alu.op = ALU_OP1_MOV;
6982 alu.src[0].sel = ctx->temp_reg;
6983 alu.src[0].chan = 3;
6984 alu.dst.sel = mytmp;
6985 alu.dst.chan = 0;
6986 alu.dst.write = 1;
6987 alu.last = 1;
6988 r = r600_bytecode_add_alu(ctx->bc, &alu);
6989 if (r)
6990 return r;
6991
6992 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
6993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6994 alu.op = ALU_OP3_MULADD;
6995 alu.is_op3 = 1;
6996 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6997 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6998 alu.src[1].chan = 0;
6999 alu.src[1].value = u_bitcast_f2u(8.0f);
7000 alu.src[2].sel = mytmp;
7001 alu.src[2].chan = 0;
7002 alu.dst.sel = ctx->temp_reg;
7003 alu.dst.chan = 3;
7004 alu.dst.write = 1;
7005 alu.last = 1;
7006 r = r600_bytecode_add_alu(ctx->bc, &alu);
7007 if (r)
7008 return r;
7009 } else if (ctx->bc->chip_class < EVERGREEN) {
7010 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7011 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7012 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7013 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7014 tex.src_gpr = r600_get_temp(ctx);
7015 tex.src_sel_x = 0;
7016 tex.src_sel_y = 0;
7017 tex.src_sel_z = 0;
7018 tex.src_sel_w = 0;
7019 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7020 tex.coord_type_x = 1;
7021 tex.coord_type_y = 1;
7022 tex.coord_type_z = 1;
7023 tex.coord_type_w = 1;
7024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7025 alu.op = ALU_OP1_MOV;
7026 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7027 alu.dst.sel = tex.src_gpr;
7028 alu.dst.chan = 0;
7029 alu.last = 1;
7030 alu.dst.write = 1;
7031 r = r600_bytecode_add_alu(ctx->bc, &alu);
7032 if (r)
7033 return r;
7034
7035 r = r600_bytecode_add_tex(ctx->bc, &tex);
7036 if (r)
7037 return r;
7038 }
7039
7040 }
7041
7042 /* for cube forms of lod and bias we need to route things */
7043 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7044 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7045 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7046 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7048 alu.op = ALU_OP1_MOV;
7049 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7050 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7051 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7052 else
7053 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7054 alu.dst.sel = ctx->temp_reg;
7055 alu.dst.chan = 2;
7056 alu.last = 1;
7057 alu.dst.write = 1;
7058 r = r600_bytecode_add_alu(ctx->bc, &alu);
7059 if (r)
7060 return r;
7061 }
7062
7063 src_loaded = TRUE;
7064 src_gpr = ctx->temp_reg;
7065 }
7066
7067 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7068 int temp_h = 0, temp_v = 0;
7069 int start_val = 0;
7070
7071 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7072 if (src_loaded == TRUE)
7073 start_val = 1;
7074 else
7075 src_loaded = TRUE;
7076 for (i = start_val; i < 3; i++) {
7077 int treg = r600_get_temp(ctx);
7078
7079 if (i == 0)
7080 src_gpr = treg;
7081 else if (i == 1)
7082 temp_h = treg;
7083 else
7084 temp_v = treg;
7085
7086 for (j = 0; j < 4; j++) {
7087 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7088 alu.op = ALU_OP1_MOV;
7089 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7090 alu.dst.sel = treg;
7091 alu.dst.chan = j;
7092 if (j == 3)
7093 alu.last = 1;
7094 alu.dst.write = 1;
7095 r = r600_bytecode_add_alu(ctx->bc, &alu);
7096 if (r)
7097 return r;
7098 }
7099 }
7100 for (i = 1; i < 3; i++) {
7101 /* set gradients h/v */
7102 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7103 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7104 FETCH_OP_SET_GRADIENTS_V;
7105 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7106 tex.sampler_index_mode = sampler_index_mode;
7107 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7108 tex.resource_index_mode = sampler_index_mode;
7109
7110 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7111 tex.src_sel_x = 0;
7112 tex.src_sel_y = 1;
7113 tex.src_sel_z = 2;
7114 tex.src_sel_w = 3;
7115
7116 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7117 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7118 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7119 tex.coord_type_x = 1;
7120 tex.coord_type_y = 1;
7121 tex.coord_type_z = 1;
7122 tex.coord_type_w = 1;
7123 }
7124 r = r600_bytecode_add_tex(ctx->bc, &tex);
7125 if (r)
7126 return r;
7127 }
7128 }
7129
7130 if (src_requires_loading && !src_loaded) {
7131 for (i = 0; i < 4; i++) {
7132 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7133 alu.op = ALU_OP1_MOV;
7134 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7135 alu.dst.sel = ctx->temp_reg;
7136 alu.dst.chan = i;
7137 if (i == 3)
7138 alu.last = 1;
7139 alu.dst.write = 1;
7140 r = r600_bytecode_add_alu(ctx->bc, &alu);
7141 if (r)
7142 return r;
7143 }
7144 src_loaded = TRUE;
7145 src_gpr = ctx->temp_reg;
7146 }
7147
7148 /* get offset values */
7149 if (inst->Texture.NumOffsets) {
7150 assert(inst->Texture.NumOffsets == 1);
7151
7152 /* The texture offset feature doesn't work with the TXF instruction
7153 * and must be emulated by adding the offset to the texture coordinates. */
7154 if (txf_add_offsets) {
7155 const struct tgsi_texture_offset *off = inst->TexOffsets;
7156
7157 switch (inst->Texture.Texture) {
7158 case TGSI_TEXTURE_3D:
7159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7160 alu.op = ALU_OP2_ADD_INT;
7161 alu.src[0].sel = src_gpr;
7162 alu.src[0].chan = 2;
7163 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7164 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7165 alu.dst.sel = src_gpr;
7166 alu.dst.chan = 2;
7167 alu.dst.write = 1;
7168 alu.last = 1;
7169 r = r600_bytecode_add_alu(ctx->bc, &alu);
7170 if (r)
7171 return r;
7172 /* fall through */
7173
7174 case TGSI_TEXTURE_2D:
7175 case TGSI_TEXTURE_SHADOW2D:
7176 case TGSI_TEXTURE_RECT:
7177 case TGSI_TEXTURE_SHADOWRECT:
7178 case TGSI_TEXTURE_2D_ARRAY:
7179 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7180 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7181 alu.op = ALU_OP2_ADD_INT;
7182 alu.src[0].sel = src_gpr;
7183 alu.src[0].chan = 1;
7184 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7185 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7186 alu.dst.sel = src_gpr;
7187 alu.dst.chan = 1;
7188 alu.dst.write = 1;
7189 alu.last = 1;
7190 r = r600_bytecode_add_alu(ctx->bc, &alu);
7191 if (r)
7192 return r;
7193 /* fall through */
7194
7195 case TGSI_TEXTURE_1D:
7196 case TGSI_TEXTURE_SHADOW1D:
7197 case TGSI_TEXTURE_1D_ARRAY:
7198 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7199 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7200 alu.op = ALU_OP2_ADD_INT;
7201 alu.src[0].sel = src_gpr;
7202 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7203 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7204 alu.dst.sel = src_gpr;
7205 alu.dst.write = 1;
7206 alu.last = 1;
7207 r = r600_bytecode_add_alu(ctx->bc, &alu);
7208 if (r)
7209 return r;
7210 break;
7211 /* texture offsets do not apply to other texture targets */
7212 }
7213 } else {
7214 switch (inst->Texture.Texture) {
7215 case TGSI_TEXTURE_3D:
7216 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7217 /* fallthrough */
7218 case TGSI_TEXTURE_2D:
7219 case TGSI_TEXTURE_SHADOW2D:
7220 case TGSI_TEXTURE_RECT:
7221 case TGSI_TEXTURE_SHADOWRECT:
7222 case TGSI_TEXTURE_2D_ARRAY:
7223 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7224 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7225 /* fallthrough */
7226 case TGSI_TEXTURE_1D:
7227 case TGSI_TEXTURE_SHADOW1D:
7228 case TGSI_TEXTURE_1D_ARRAY:
7229 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7230 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7231 }
7232 }
7233 }
7234
7235 /* Obtain the sample index for reading a compressed MSAA color texture.
7236 * To read the FMASK, we use the ldfptr instruction, which tells us
7237 * where the samples are stored.
7238 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7239 * which is the identity mapping. Each nibble says which physical sample
7240 * should be fetched to get that sample.
7241 *
7242 * Assume src.z contains the sample index. It should be modified like this:
7243 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7244 * Then fetch the texel with src.
7245 */
7246 if (read_compressed_msaa) {
7247 unsigned sample_chan = 3;
7248 unsigned temp = r600_get_temp(ctx);
7249 assert(src_loaded);
7250
7251 /* temp.w = ldfptr() */
7252 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7253 tex.op = FETCH_OP_LD;
7254 tex.inst_mod = 1; /* to indicate this is ldfptr */
7255 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7256 tex.sampler_index_mode = sampler_index_mode;
7257 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7258 tex.resource_index_mode = sampler_index_mode;
7259 tex.src_gpr = src_gpr;
7260 tex.dst_gpr = temp;
7261 tex.dst_sel_x = 7; /* mask out these components */
7262 tex.dst_sel_y = 7;
7263 tex.dst_sel_z = 7;
7264 tex.dst_sel_w = 0; /* store X */
7265 tex.src_sel_x = 0;
7266 tex.src_sel_y = 1;
7267 tex.src_sel_z = 2;
7268 tex.src_sel_w = 3;
7269 tex.offset_x = offset_x;
7270 tex.offset_y = offset_y;
7271 tex.offset_z = offset_z;
7272 r = r600_bytecode_add_tex(ctx->bc, &tex);
7273 if (r)
7274 return r;
7275
7276 /* temp.x = sample_index*4 */
7277 if (ctx->bc->chip_class == CAYMAN) {
7278 for (i = 0 ; i < 4; i++) {
7279 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7280 alu.op = ALU_OP2_MULLO_INT;
7281 alu.src[0].sel = src_gpr;
7282 alu.src[0].chan = sample_chan;
7283 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7284 alu.src[1].value = 4;
7285 alu.dst.sel = temp;
7286 alu.dst.chan = i;
7287 alu.dst.write = i == 0;
7288 if (i == 3)
7289 alu.last = 1;
7290 r = r600_bytecode_add_alu(ctx->bc, &alu);
7291 if (r)
7292 return r;
7293 }
7294 } else {
7295 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7296 alu.op = ALU_OP2_MULLO_INT;
7297 alu.src[0].sel = src_gpr;
7298 alu.src[0].chan = sample_chan;
7299 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7300 alu.src[1].value = 4;
7301 alu.dst.sel = temp;
7302 alu.dst.chan = 0;
7303 alu.dst.write = 1;
7304 alu.last = 1;
7305 r = r600_bytecode_add_alu(ctx->bc, &alu);
7306 if (r)
7307 return r;
7308 }
7309
7310 /* sample_index = temp.w >> temp.x */
7311 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7312 alu.op = ALU_OP2_LSHR_INT;
7313 alu.src[0].sel = temp;
7314 alu.src[0].chan = 3;
7315 alu.src[1].sel = temp;
7316 alu.src[1].chan = 0;
7317 alu.dst.sel = src_gpr;
7318 alu.dst.chan = sample_chan;
7319 alu.dst.write = 1;
7320 alu.last = 1;
7321 r = r600_bytecode_add_alu(ctx->bc, &alu);
7322 if (r)
7323 return r;
7324
7325 /* sample_index & 0xF */
7326 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7327 alu.op = ALU_OP2_AND_INT;
7328 alu.src[0].sel = src_gpr;
7329 alu.src[0].chan = sample_chan;
7330 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7331 alu.src[1].value = 0xF;
7332 alu.dst.sel = src_gpr;
7333 alu.dst.chan = sample_chan;
7334 alu.dst.write = 1;
7335 alu.last = 1;
7336 r = r600_bytecode_add_alu(ctx->bc, &alu);
7337 if (r)
7338 return r;
7339 #if 0
7340 /* visualize the FMASK */
7341 for (i = 0; i < 4; i++) {
7342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7343 alu.op = ALU_OP1_INT_TO_FLT;
7344 alu.src[0].sel = src_gpr;
7345 alu.src[0].chan = sample_chan;
7346 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7347 alu.dst.chan = i;
7348 alu.dst.write = 1;
7349 alu.last = 1;
7350 r = r600_bytecode_add_alu(ctx->bc, &alu);
7351 if (r)
7352 return r;
7353 }
7354 return 0;
7355 #endif
7356 }
7357
7358 /* does this shader want a num layers from TXQ for a cube array? */
7359 if (has_txq_cube_array_z) {
7360 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7361
7362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7363 alu.op = ALU_OP1_MOV;
7364
7365 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7366 if (ctx->bc->chip_class >= EVERGREEN) {
7367 /* channel 1 or 3 of each word */
7368 alu.src[0].sel += (id / 2);
7369 alu.src[0].chan = ((id % 2) * 2) + 1;
7370 } else {
7371 /* r600 we have them at channel 2 of the second dword */
7372 alu.src[0].sel += (id * 2) + 1;
7373 alu.src[0].chan = 2;
7374 }
7375 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7376 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7377 alu.last = 1;
7378 r = r600_bytecode_add_alu(ctx->bc, &alu);
7379 if (r)
7380 return r;
7381 /* disable writemask from texture instruction */
7382 inst->Dst[0].Register.WriteMask &= ~4;
7383 }
7384
7385 opcode = ctx->inst_info->op;
7386 if (opcode == FETCH_OP_GATHER4 &&
7387 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7388 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7389 opcode = FETCH_OP_GATHER4_O;
7390
7391 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7392 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7393 encoded in the instruction are ignored. */
7394 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7395 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7396 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7397 tex.sampler_index_mode = sampler_index_mode;
7398 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7399 tex.resource_index_mode = sampler_index_mode;
7400
7401 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7402 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7403 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7404 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7405 tex.src_sel_w = 4;
7406
7407 tex.dst_sel_x = 7;
7408 tex.dst_sel_y = 7;
7409 tex.dst_sel_z = 7;
7410 tex.dst_sel_w = 7;
7411
7412 r = r600_bytecode_add_tex(ctx->bc, &tex);
7413 if (r)
7414 return r;
7415 }
7416
7417 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7418 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7419 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7420 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7421 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7422 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7423 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7424 switch (opcode) {
7425 case FETCH_OP_SAMPLE:
7426 opcode = FETCH_OP_SAMPLE_C;
7427 break;
7428 case FETCH_OP_SAMPLE_L:
7429 opcode = FETCH_OP_SAMPLE_C_L;
7430 break;
7431 case FETCH_OP_SAMPLE_LB:
7432 opcode = FETCH_OP_SAMPLE_C_LB;
7433 break;
7434 case FETCH_OP_SAMPLE_G:
7435 opcode = FETCH_OP_SAMPLE_C_G;
7436 break;
7437 /* Texture gather variants */
7438 case FETCH_OP_GATHER4:
7439 opcode = FETCH_OP_GATHER4_C;
7440 break;
7441 case FETCH_OP_GATHER4_O:
7442 opcode = FETCH_OP_GATHER4_C_O;
7443 break;
7444 }
7445 }
7446
7447 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7448 tex.op = opcode;
7449
7450 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7451 tex.sampler_index_mode = sampler_index_mode;
7452 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7453 tex.resource_index_mode = sampler_index_mode;
7454 tex.src_gpr = src_gpr;
7455 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7456
7457 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7458 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7459 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7460 }
7461
7462 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7463 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7464 tex.inst_mod = texture_component_select;
7465
7466 if (ctx->bc->chip_class == CAYMAN) {
7467 /* GATHER4 result order is different from TGSI TG4 */
7468 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7469 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7470 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7471 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7472 } else {
7473 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7474 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7475 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7476 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7477 }
7478 }
7479 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7480 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7481 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7482 tex.dst_sel_z = 7;
7483 tex.dst_sel_w = 7;
7484 }
7485 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7486 tex.dst_sel_x = 3;
7487 tex.dst_sel_y = 7;
7488 tex.dst_sel_z = 7;
7489 tex.dst_sel_w = 7;
7490 }
7491 else {
7492 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7493 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7494 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7495 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7496 }
7497
7498
7499 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7500 tex.src_sel_x = 4;
7501 tex.src_sel_y = 4;
7502 tex.src_sel_z = 4;
7503 tex.src_sel_w = 4;
7504 } else if (src_loaded) {
7505 tex.src_sel_x = 0;
7506 tex.src_sel_y = 1;
7507 tex.src_sel_z = 2;
7508 tex.src_sel_w = 3;
7509 } else {
7510 tex.src_sel_x = ctx->src[0].swizzle[0];
7511 tex.src_sel_y = ctx->src[0].swizzle[1];
7512 tex.src_sel_z = ctx->src[0].swizzle[2];
7513 tex.src_sel_w = ctx->src[0].swizzle[3];
7514 tex.src_rel = ctx->src[0].rel;
7515 }
7516
7517 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7518 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7519 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7520 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7521 tex.src_sel_x = 1;
7522 tex.src_sel_y = 0;
7523 tex.src_sel_z = 3;
7524 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7525 }
7526
7527 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7528 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7529 tex.coord_type_x = 1;
7530 tex.coord_type_y = 1;
7531 }
7532 tex.coord_type_z = 1;
7533 tex.coord_type_w = 1;
7534
7535 tex.offset_x = offset_x;
7536 tex.offset_y = offset_y;
7537 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7538 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7539 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7540 tex.offset_z = 0;
7541 }
7542 else {
7543 tex.offset_z = offset_z;
7544 }
7545
7546 /* Put the depth for comparison in W.
7547 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7548 * Some instructions expect the depth in Z. */
7549 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7550 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7551 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7552 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7553 opcode != FETCH_OP_SAMPLE_C_L &&
7554 opcode != FETCH_OP_SAMPLE_C_LB) {
7555 tex.src_sel_w = tex.src_sel_z;
7556 }
7557
7558 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7559 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7560 if (opcode == FETCH_OP_SAMPLE_C_L ||
7561 opcode == FETCH_OP_SAMPLE_C_LB) {
7562 /* the array index is read from Y */
7563 tex.coord_type_y = 0;
7564 } else {
7565 /* the array index is read from Z */
7566 tex.coord_type_z = 0;
7567 tex.src_sel_z = tex.src_sel_y;
7568 }
7569 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7570 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7571 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7572 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7573 (ctx->bc->chip_class >= EVERGREEN)))
7574 /* the array index is read from Z */
7575 tex.coord_type_z = 0;
7576
7577 /* mask unused source components */
7578 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7579 switch (inst->Texture.Texture) {
7580 case TGSI_TEXTURE_2D:
7581 case TGSI_TEXTURE_RECT:
7582 tex.src_sel_z = 7;
7583 tex.src_sel_w = 7;
7584 break;
7585 case TGSI_TEXTURE_1D_ARRAY:
7586 tex.src_sel_y = 7;
7587 tex.src_sel_w = 7;
7588 break;
7589 case TGSI_TEXTURE_1D:
7590 tex.src_sel_y = 7;
7591 tex.src_sel_z = 7;
7592 tex.src_sel_w = 7;
7593 break;
7594 }
7595 }
7596
7597 r = r600_bytecode_add_tex(ctx->bc, &tex);
7598 if (r)
7599 return r;
7600
7601 /* add shadow ambient support - gallium doesn't do it yet */
7602 return 0;
7603 }
7604
7605 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7606 struct tgsi_full_src_register *src)
7607 {
7608 int i;
7609
7610 if (src->Register.Indirect) {
7611 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7612 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7613 return ctx->shader->atomics[i].hw_idx;
7614 }
7615 } else {
7616 uint32_t index = src->Register.Index;
7617 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7618 if (ctx->shader->atomics[i].buffer_id != src->Dimension.Index)
7619 continue;
7620 if (index > ctx->shader->atomics[i].end)
7621 continue;
7622 if (index < ctx->shader->atomics[i].start)
7623 continue;
7624 uint32_t offset = (index - ctx->shader->atomics[i].start);
7625 return ctx->shader->atomics[i].hw_idx + offset;
7626 }
7627 }
7628 assert(0);
7629 return -1;
7630 }
7631
7632
7633 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7634 {
7635 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7636 int r;
7637 struct r600_bytecode_gds gds;
7638 int uav_id = 0;
7639 int uav_index_mode = 0;
7640
7641 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7642
7643 if (inst->Src[0].Register.Indirect)
7644 uav_index_mode = 2;
7645
7646 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7647 gds.op = FETCH_OP_GDS_READ_RET;
7648 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7649 gds.uav_id = uav_id;
7650 gds.uav_index_mode = uav_index_mode;
7651 gds.src_gpr = ctx->temp_reg;
7652 gds.src_sel_x = 4;
7653 gds.src_sel_y = 4;
7654 gds.src_sel_z = 4;
7655 gds.dst_sel_x = 0;
7656 gds.dst_sel_y = 7;
7657 gds.dst_sel_z = 7;
7658 gds.dst_sel_w = 7;
7659 gds.src_gpr2 = ctx->temp_reg;
7660 gds.alloc_consume = 1;
7661 r = r600_bytecode_add_gds(ctx->bc, &gds);
7662 if (r)
7663 return r;
7664
7665 ctx->bc->cf_last->vpm = 1;
7666 return 0;
7667 }
7668
7669 static int tgsi_load(struct r600_shader_ctx *ctx)
7670 {
7671 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7672 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7673 return tgsi_load_gds(ctx);
7674 return 0;
7675 }
7676
7677 static int get_gds_op(int opcode)
7678 {
7679 switch (opcode) {
7680 case TGSI_OPCODE_ATOMUADD:
7681 return FETCH_OP_GDS_ADD_RET;
7682 case TGSI_OPCODE_ATOMAND:
7683 return FETCH_OP_GDS_AND_RET;
7684 case TGSI_OPCODE_ATOMOR:
7685 return FETCH_OP_GDS_OR_RET;
7686 case TGSI_OPCODE_ATOMXOR:
7687 return FETCH_OP_GDS_XOR_RET;
7688 case TGSI_OPCODE_ATOMUMIN:
7689 return FETCH_OP_GDS_MIN_UINT_RET;
7690 case TGSI_OPCODE_ATOMUMAX:
7691 return FETCH_OP_GDS_MAX_UINT_RET;
7692 case TGSI_OPCODE_ATOMXCHG:
7693 return FETCH_OP_GDS_XCHG_RET;
7694 case TGSI_OPCODE_ATOMCAS:
7695 return FETCH_OP_GDS_CMP_XCHG_RET;
7696 default:
7697 return -1;
7698 }
7699 }
7700
7701 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
7702 {
7703 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7704 struct r600_bytecode_gds gds;
7705 struct r600_bytecode_alu alu;
7706 int gds_op = get_gds_op(inst->Instruction.Opcode);
7707 int r;
7708 int uav_id = 0;
7709 int uav_index_mode = 0;
7710
7711 if (gds_op == -1) {
7712 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
7713 return -1;
7714 }
7715
7716 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7717
7718 if (inst->Src[0].Register.Indirect)
7719 uav_index_mode = 2;
7720
7721 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
7722 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
7723 int abs_value = abs(value);
7724 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
7725 gds_op = FETCH_OP_GDS_SUB_RET;
7726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7727 alu.op = ALU_OP1_MOV;
7728 alu.dst.sel = ctx->temp_reg;
7729 alu.dst.chan = 0;
7730 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
7731 alu.src[0].value = abs_value;
7732 alu.last = 1;
7733 alu.dst.write = 1;
7734 r = r600_bytecode_add_alu(ctx->bc, &alu);
7735 if (r)
7736 return r;
7737 } else {
7738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7739 alu.op = ALU_OP1_MOV;
7740 alu.dst.sel = ctx->temp_reg;
7741 alu.dst.chan = 0;
7742 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
7743 alu.last = 1;
7744 alu.dst.write = 1;
7745 r = r600_bytecode_add_alu(ctx->bc, &alu);
7746 if (r)
7747 return r;
7748 }
7749
7750 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7751 gds.op = gds_op;
7752 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7753 gds.uav_id = uav_id;
7754 gds.uav_index_mode = uav_index_mode;
7755 gds.src_gpr = ctx->temp_reg;
7756 gds.src_gpr2 = ctx->temp_reg;
7757 gds.src_sel_x = 4;
7758 gds.src_sel_y = 0;
7759 gds.src_sel_z = 4;
7760 gds.dst_sel_x = 0;
7761 gds.dst_sel_y = 7;
7762 gds.dst_sel_z = 7;
7763 gds.dst_sel_w = 7;
7764 gds.alloc_consume = 1;
7765 r = r600_bytecode_add_gds(ctx->bc, &gds);
7766 if (r)
7767 return r;
7768 ctx->bc->cf_last->vpm = 1;
7769 return 0;
7770 }
7771
7772 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
7773 {
7774 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7775 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7776 return tgsi_atomic_op_gds(ctx);
7777 return 0;
7778 }
7779
7780 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7781 {
7782 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7783 struct r600_bytecode_alu alu;
7784 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7785 unsigned i, temp_regs[2];
7786 int r;
7787
7788 /* optimize if it's just an equal balance */
7789 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7790 for (i = 0; i < lasti + 1; i++) {
7791 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7792 continue;
7793
7794 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7795 alu.op = ALU_OP2_ADD;
7796 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7797 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7798 alu.omod = 3;
7799 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7800 alu.dst.chan = i;
7801 if (i == lasti) {
7802 alu.last = 1;
7803 }
7804 r = r600_bytecode_add_alu(ctx->bc, &alu);
7805 if (r)
7806 return r;
7807 }
7808 return 0;
7809 }
7810
7811 /* 1 - src0 */
7812 for (i = 0; i < lasti + 1; i++) {
7813 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7814 continue;
7815
7816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7817 alu.op = ALU_OP2_ADD;
7818 alu.src[0].sel = V_SQ_ALU_SRC_1;
7819 alu.src[0].chan = 0;
7820 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7821 r600_bytecode_src_toggle_neg(&alu.src[1]);
7822 alu.dst.sel = ctx->temp_reg;
7823 alu.dst.chan = i;
7824 if (i == lasti) {
7825 alu.last = 1;
7826 }
7827 alu.dst.write = 1;
7828 r = r600_bytecode_add_alu(ctx->bc, &alu);
7829 if (r)
7830 return r;
7831 }
7832
7833 /* (1 - src0) * src2 */
7834 for (i = 0; i < lasti + 1; i++) {
7835 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7836 continue;
7837
7838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7839 alu.op = ALU_OP2_MUL;
7840 alu.src[0].sel = ctx->temp_reg;
7841 alu.src[0].chan = i;
7842 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7843 alu.dst.sel = ctx->temp_reg;
7844 alu.dst.chan = i;
7845 if (i == lasti) {
7846 alu.last = 1;
7847 }
7848 alu.dst.write = 1;
7849 r = r600_bytecode_add_alu(ctx->bc, &alu);
7850 if (r)
7851 return r;
7852 }
7853
7854 /* src0 * src1 + (1 - src0) * src2 */
7855 if (ctx->src[0].abs)
7856 temp_regs[0] = r600_get_temp(ctx);
7857 else
7858 temp_regs[0] = 0;
7859 if (ctx->src[1].abs)
7860 temp_regs[1] = r600_get_temp(ctx);
7861 else
7862 temp_regs[1] = 0;
7863
7864 for (i = 0; i < lasti + 1; i++) {
7865 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7866 continue;
7867
7868 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7869 alu.op = ALU_OP3_MULADD;
7870 alu.is_op3 = 1;
7871 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7872 if (r)
7873 return r;
7874 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7875 if (r)
7876 return r;
7877 alu.src[2].sel = ctx->temp_reg;
7878 alu.src[2].chan = i;
7879
7880 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7881 alu.dst.chan = i;
7882 if (i == lasti) {
7883 alu.last = 1;
7884 }
7885 r = r600_bytecode_add_alu(ctx->bc, &alu);
7886 if (r)
7887 return r;
7888 }
7889 return 0;
7890 }
7891
7892 static int tgsi_cmp(struct r600_shader_ctx *ctx)
7893 {
7894 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7895 struct r600_bytecode_alu alu;
7896 int i, r, j;
7897 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7898 int temp_regs[3];
7899 unsigned op;
7900
7901 if (ctx->src[0].abs && ctx->src[0].neg) {
7902 op = ALU_OP3_CNDE;
7903 ctx->src[0].abs = 0;
7904 ctx->src[0].neg = 0;
7905 } else {
7906 op = ALU_OP3_CNDGE;
7907 }
7908
7909 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7910 temp_regs[j] = 0;
7911 if (ctx->src[j].abs)
7912 temp_regs[j] = r600_get_temp(ctx);
7913 }
7914
7915 for (i = 0; i < lasti + 1; i++) {
7916 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7917 continue;
7918
7919 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7920 alu.op = op;
7921 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7922 if (r)
7923 return r;
7924 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
7925 if (r)
7926 return r;
7927 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
7928 if (r)
7929 return r;
7930 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7931 alu.dst.chan = i;
7932 alu.dst.write = 1;
7933 alu.is_op3 = 1;
7934 if (i == lasti)
7935 alu.last = 1;
7936 r = r600_bytecode_add_alu(ctx->bc, &alu);
7937 if (r)
7938 return r;
7939 }
7940 return 0;
7941 }
7942
7943 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
7944 {
7945 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7946 struct r600_bytecode_alu alu;
7947 int i, r;
7948 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7949
7950 for (i = 0; i < lasti + 1; i++) {
7951 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7952 continue;
7953
7954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7955 alu.op = ALU_OP3_CNDE_INT;
7956 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7957 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7958 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
7959 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7960 alu.dst.chan = i;
7961 alu.dst.write = 1;
7962 alu.is_op3 = 1;
7963 if (i == lasti)
7964 alu.last = 1;
7965 r = r600_bytecode_add_alu(ctx->bc, &alu);
7966 if (r)
7967 return r;
7968 }
7969 return 0;
7970 }
7971
7972 static int tgsi_exp(struct r600_shader_ctx *ctx)
7973 {
7974 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7975 struct r600_bytecode_alu alu;
7976 int r;
7977 unsigned i;
7978
7979 /* result.x = 2^floor(src); */
7980 if (inst->Dst[0].Register.WriteMask & 1) {
7981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7982
7983 alu.op = ALU_OP1_FLOOR;
7984 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7985
7986 alu.dst.sel = ctx->temp_reg;
7987 alu.dst.chan = 0;
7988 alu.dst.write = 1;
7989 alu.last = 1;
7990 r = r600_bytecode_add_alu(ctx->bc, &alu);
7991 if (r)
7992 return r;
7993
7994 if (ctx->bc->chip_class == CAYMAN) {
7995 for (i = 0; i < 3; i++) {
7996 alu.op = ALU_OP1_EXP_IEEE;
7997 alu.src[0].sel = ctx->temp_reg;
7998 alu.src[0].chan = 0;
7999
8000 alu.dst.sel = ctx->temp_reg;
8001 alu.dst.chan = i;
8002 alu.dst.write = i == 0;
8003 alu.last = i == 2;
8004 r = r600_bytecode_add_alu(ctx->bc, &alu);
8005 if (r)
8006 return r;
8007 }
8008 } else {
8009 alu.op = ALU_OP1_EXP_IEEE;
8010 alu.src[0].sel = ctx->temp_reg;
8011 alu.src[0].chan = 0;
8012
8013 alu.dst.sel = ctx->temp_reg;
8014 alu.dst.chan = 0;
8015 alu.dst.write = 1;
8016 alu.last = 1;
8017 r = r600_bytecode_add_alu(ctx->bc, &alu);
8018 if (r)
8019 return r;
8020 }
8021 }
8022
8023 /* result.y = tmp - floor(tmp); */
8024 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8026
8027 alu.op = ALU_OP1_FRACT;
8028 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8029
8030 alu.dst.sel = ctx->temp_reg;
8031 #if 0
8032 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8033 if (r)
8034 return r;
8035 #endif
8036 alu.dst.write = 1;
8037 alu.dst.chan = 1;
8038
8039 alu.last = 1;
8040
8041 r = r600_bytecode_add_alu(ctx->bc, &alu);
8042 if (r)
8043 return r;
8044 }
8045
8046 /* result.z = RoughApprox2ToX(tmp);*/
8047 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8048 if (ctx->bc->chip_class == CAYMAN) {
8049 for (i = 0; i < 3; i++) {
8050 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8051 alu.op = ALU_OP1_EXP_IEEE;
8052 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8053
8054 alu.dst.sel = ctx->temp_reg;
8055 alu.dst.chan = i;
8056 if (i == 2) {
8057 alu.dst.write = 1;
8058 alu.last = 1;
8059 }
8060
8061 r = r600_bytecode_add_alu(ctx->bc, &alu);
8062 if (r)
8063 return r;
8064 }
8065 } else {
8066 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8067 alu.op = ALU_OP1_EXP_IEEE;
8068 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8069
8070 alu.dst.sel = ctx->temp_reg;
8071 alu.dst.write = 1;
8072 alu.dst.chan = 2;
8073
8074 alu.last = 1;
8075
8076 r = r600_bytecode_add_alu(ctx->bc, &alu);
8077 if (r)
8078 return r;
8079 }
8080 }
8081
8082 /* result.w = 1.0;*/
8083 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8084 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8085
8086 alu.op = ALU_OP1_MOV;
8087 alu.src[0].sel = V_SQ_ALU_SRC_1;
8088 alu.src[0].chan = 0;
8089
8090 alu.dst.sel = ctx->temp_reg;
8091 alu.dst.chan = 3;
8092 alu.dst.write = 1;
8093 alu.last = 1;
8094 r = r600_bytecode_add_alu(ctx->bc, &alu);
8095 if (r)
8096 return r;
8097 }
8098 return tgsi_helper_copy(ctx, inst);
8099 }
8100
8101 static int tgsi_log(struct r600_shader_ctx *ctx)
8102 {
8103 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8104 struct r600_bytecode_alu alu;
8105 int r;
8106 unsigned i;
8107
8108 /* result.x = floor(log2(|src|)); */
8109 if (inst->Dst[0].Register.WriteMask & 1) {
8110 if (ctx->bc->chip_class == CAYMAN) {
8111 for (i = 0; i < 3; i++) {
8112 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8113
8114 alu.op = ALU_OP1_LOG_IEEE;
8115 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8116 r600_bytecode_src_set_abs(&alu.src[0]);
8117
8118 alu.dst.sel = ctx->temp_reg;
8119 alu.dst.chan = i;
8120 if (i == 0)
8121 alu.dst.write = 1;
8122 if (i == 2)
8123 alu.last = 1;
8124 r = r600_bytecode_add_alu(ctx->bc, &alu);
8125 if (r)
8126 return r;
8127 }
8128
8129 } else {
8130 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8131
8132 alu.op = ALU_OP1_LOG_IEEE;
8133 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8134 r600_bytecode_src_set_abs(&alu.src[0]);
8135
8136 alu.dst.sel = ctx->temp_reg;
8137 alu.dst.chan = 0;
8138 alu.dst.write = 1;
8139 alu.last = 1;
8140 r = r600_bytecode_add_alu(ctx->bc, &alu);
8141 if (r)
8142 return r;
8143 }
8144
8145 alu.op = ALU_OP1_FLOOR;
8146 alu.src[0].sel = ctx->temp_reg;
8147 alu.src[0].chan = 0;
8148
8149 alu.dst.sel = ctx->temp_reg;
8150 alu.dst.chan = 0;
8151 alu.dst.write = 1;
8152 alu.last = 1;
8153
8154 r = r600_bytecode_add_alu(ctx->bc, &alu);
8155 if (r)
8156 return r;
8157 }
8158
8159 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8160 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8161
8162 if (ctx->bc->chip_class == CAYMAN) {
8163 for (i = 0; i < 3; i++) {
8164 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8165
8166 alu.op = ALU_OP1_LOG_IEEE;
8167 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8168 r600_bytecode_src_set_abs(&alu.src[0]);
8169
8170 alu.dst.sel = ctx->temp_reg;
8171 alu.dst.chan = i;
8172 if (i == 1)
8173 alu.dst.write = 1;
8174 if (i == 2)
8175 alu.last = 1;
8176
8177 r = r600_bytecode_add_alu(ctx->bc, &alu);
8178 if (r)
8179 return r;
8180 }
8181 } else {
8182 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8183
8184 alu.op = ALU_OP1_LOG_IEEE;
8185 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8186 r600_bytecode_src_set_abs(&alu.src[0]);
8187
8188 alu.dst.sel = ctx->temp_reg;
8189 alu.dst.chan = 1;
8190 alu.dst.write = 1;
8191 alu.last = 1;
8192
8193 r = r600_bytecode_add_alu(ctx->bc, &alu);
8194 if (r)
8195 return r;
8196 }
8197
8198 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8199
8200 alu.op = ALU_OP1_FLOOR;
8201 alu.src[0].sel = ctx->temp_reg;
8202 alu.src[0].chan = 1;
8203
8204 alu.dst.sel = ctx->temp_reg;
8205 alu.dst.chan = 1;
8206 alu.dst.write = 1;
8207 alu.last = 1;
8208
8209 r = r600_bytecode_add_alu(ctx->bc, &alu);
8210 if (r)
8211 return r;
8212
8213 if (ctx->bc->chip_class == CAYMAN) {
8214 for (i = 0; i < 3; i++) {
8215 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8216 alu.op = ALU_OP1_EXP_IEEE;
8217 alu.src[0].sel = ctx->temp_reg;
8218 alu.src[0].chan = 1;
8219
8220 alu.dst.sel = ctx->temp_reg;
8221 alu.dst.chan = i;
8222 if (i == 1)
8223 alu.dst.write = 1;
8224 if (i == 2)
8225 alu.last = 1;
8226
8227 r = r600_bytecode_add_alu(ctx->bc, &alu);
8228 if (r)
8229 return r;
8230 }
8231 } else {
8232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8233 alu.op = ALU_OP1_EXP_IEEE;
8234 alu.src[0].sel = ctx->temp_reg;
8235 alu.src[0].chan = 1;
8236
8237 alu.dst.sel = ctx->temp_reg;
8238 alu.dst.chan = 1;
8239 alu.dst.write = 1;
8240 alu.last = 1;
8241
8242 r = r600_bytecode_add_alu(ctx->bc, &alu);
8243 if (r)
8244 return r;
8245 }
8246
8247 if (ctx->bc->chip_class == CAYMAN) {
8248 for (i = 0; i < 3; i++) {
8249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8250 alu.op = ALU_OP1_RECIP_IEEE;
8251 alu.src[0].sel = ctx->temp_reg;
8252 alu.src[0].chan = 1;
8253
8254 alu.dst.sel = ctx->temp_reg;
8255 alu.dst.chan = i;
8256 if (i == 1)
8257 alu.dst.write = 1;
8258 if (i == 2)
8259 alu.last = 1;
8260
8261 r = r600_bytecode_add_alu(ctx->bc, &alu);
8262 if (r)
8263 return r;
8264 }
8265 } else {
8266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8267 alu.op = ALU_OP1_RECIP_IEEE;
8268 alu.src[0].sel = ctx->temp_reg;
8269 alu.src[0].chan = 1;
8270
8271 alu.dst.sel = ctx->temp_reg;
8272 alu.dst.chan = 1;
8273 alu.dst.write = 1;
8274 alu.last = 1;
8275
8276 r = r600_bytecode_add_alu(ctx->bc, &alu);
8277 if (r)
8278 return r;
8279 }
8280
8281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8282
8283 alu.op = ALU_OP2_MUL;
8284
8285 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8286 r600_bytecode_src_set_abs(&alu.src[0]);
8287
8288 alu.src[1].sel = ctx->temp_reg;
8289 alu.src[1].chan = 1;
8290
8291 alu.dst.sel = ctx->temp_reg;
8292 alu.dst.chan = 1;
8293 alu.dst.write = 1;
8294 alu.last = 1;
8295
8296 r = r600_bytecode_add_alu(ctx->bc, &alu);
8297 if (r)
8298 return r;
8299 }
8300
8301 /* result.z = log2(|src|);*/
8302 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8303 if (ctx->bc->chip_class == CAYMAN) {
8304 for (i = 0; i < 3; i++) {
8305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8306
8307 alu.op = ALU_OP1_LOG_IEEE;
8308 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8309 r600_bytecode_src_set_abs(&alu.src[0]);
8310
8311 alu.dst.sel = ctx->temp_reg;
8312 if (i == 2)
8313 alu.dst.write = 1;
8314 alu.dst.chan = i;
8315 if (i == 2)
8316 alu.last = 1;
8317
8318 r = r600_bytecode_add_alu(ctx->bc, &alu);
8319 if (r)
8320 return r;
8321 }
8322 } else {
8323 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8324
8325 alu.op = ALU_OP1_LOG_IEEE;
8326 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8327 r600_bytecode_src_set_abs(&alu.src[0]);
8328
8329 alu.dst.sel = ctx->temp_reg;
8330 alu.dst.write = 1;
8331 alu.dst.chan = 2;
8332 alu.last = 1;
8333
8334 r = r600_bytecode_add_alu(ctx->bc, &alu);
8335 if (r)
8336 return r;
8337 }
8338 }
8339
8340 /* result.w = 1.0; */
8341 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8343
8344 alu.op = ALU_OP1_MOV;
8345 alu.src[0].sel = V_SQ_ALU_SRC_1;
8346 alu.src[0].chan = 0;
8347
8348 alu.dst.sel = ctx->temp_reg;
8349 alu.dst.chan = 3;
8350 alu.dst.write = 1;
8351 alu.last = 1;
8352
8353 r = r600_bytecode_add_alu(ctx->bc, &alu);
8354 if (r)
8355 return r;
8356 }
8357
8358 return tgsi_helper_copy(ctx, inst);
8359 }
8360
8361 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8362 {
8363 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8364 struct r600_bytecode_alu alu;
8365 int r;
8366 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8367 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8368
8369 assert(inst->Dst[0].Register.Index < 3);
8370 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8371
8372 switch (inst->Instruction.Opcode) {
8373 case TGSI_OPCODE_ARL:
8374 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8375 break;
8376 case TGSI_OPCODE_ARR:
8377 alu.op = ALU_OP1_FLT_TO_INT;
8378 break;
8379 case TGSI_OPCODE_UARL:
8380 alu.op = ALU_OP1_MOV;
8381 break;
8382 default:
8383 assert(0);
8384 return -1;
8385 }
8386
8387 for (i = 0; i <= lasti; ++i) {
8388 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8389 continue;
8390 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8391 alu.last = i == lasti;
8392 alu.dst.sel = reg;
8393 alu.dst.chan = i;
8394 alu.dst.write = 1;
8395 r = r600_bytecode_add_alu(ctx->bc, &alu);
8396 if (r)
8397 return r;
8398 }
8399
8400 if (inst->Dst[0].Register.Index > 0)
8401 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8402 else
8403 ctx->bc->ar_loaded = 0;
8404
8405 return 0;
8406 }
8407 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8408 {
8409 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8410 struct r600_bytecode_alu alu;
8411 int r;
8412 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8413
8414 switch (inst->Instruction.Opcode) {
8415 case TGSI_OPCODE_ARL:
8416 memset(&alu, 0, sizeof(alu));
8417 alu.op = ALU_OP1_FLOOR;
8418 alu.dst.sel = ctx->bc->ar_reg;
8419 alu.dst.write = 1;
8420 for (i = 0; i <= lasti; ++i) {
8421 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8422 alu.dst.chan = i;
8423 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8424 alu.last = i == lasti;
8425 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8426 return r;
8427 }
8428 }
8429
8430 memset(&alu, 0, sizeof(alu));
8431 alu.op = ALU_OP1_FLT_TO_INT;
8432 alu.src[0].sel = ctx->bc->ar_reg;
8433 alu.dst.sel = ctx->bc->ar_reg;
8434 alu.dst.write = 1;
8435 /* FLT_TO_INT is trans-only on r600/r700 */
8436 alu.last = TRUE;
8437 for (i = 0; i <= lasti; ++i) {
8438 alu.dst.chan = i;
8439 alu.src[0].chan = i;
8440 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8441 return r;
8442 }
8443 break;
8444 case TGSI_OPCODE_ARR:
8445 memset(&alu, 0, sizeof(alu));
8446 alu.op = ALU_OP1_FLT_TO_INT;
8447 alu.dst.sel = ctx->bc->ar_reg;
8448 alu.dst.write = 1;
8449 /* FLT_TO_INT is trans-only on r600/r700 */
8450 alu.last = TRUE;
8451 for (i = 0; i <= lasti; ++i) {
8452 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8453 alu.dst.chan = i;
8454 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8455 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8456 return r;
8457 }
8458 }
8459 break;
8460 case TGSI_OPCODE_UARL:
8461 memset(&alu, 0, sizeof(alu));
8462 alu.op = ALU_OP1_MOV;
8463 alu.dst.sel = ctx->bc->ar_reg;
8464 alu.dst.write = 1;
8465 for (i = 0; i <= lasti; ++i) {
8466 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8467 alu.dst.chan = i;
8468 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8469 alu.last = i == lasti;
8470 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8471 return r;
8472 }
8473 }
8474 break;
8475 default:
8476 assert(0);
8477 return -1;
8478 }
8479
8480 ctx->bc->ar_loaded = 0;
8481 return 0;
8482 }
8483
8484 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8485 {
8486 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8487 struct r600_bytecode_alu alu;
8488 int i, r = 0;
8489
8490 for (i = 0; i < 4; i++) {
8491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8492
8493 alu.op = ALU_OP2_MUL;
8494 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8495
8496 if (i == 0 || i == 3) {
8497 alu.src[0].sel = V_SQ_ALU_SRC_1;
8498 } else {
8499 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8500 }
8501
8502 if (i == 0 || i == 2) {
8503 alu.src[1].sel = V_SQ_ALU_SRC_1;
8504 } else {
8505 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8506 }
8507 if (i == 3)
8508 alu.last = 1;
8509 r = r600_bytecode_add_alu(ctx->bc, &alu);
8510 if (r)
8511 return r;
8512 }
8513 return 0;
8514 }
8515
8516 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8517 {
8518 struct r600_bytecode_alu alu;
8519 int r;
8520
8521 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8522 alu.op = opcode;
8523 alu.execute_mask = 1;
8524 alu.update_pred = 1;
8525
8526 alu.dst.sel = ctx->temp_reg;
8527 alu.dst.write = 1;
8528 alu.dst.chan = 0;
8529
8530 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8531 alu.src[1].sel = V_SQ_ALU_SRC_0;
8532 alu.src[1].chan = 0;
8533
8534 alu.last = 1;
8535
8536 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8537 if (r)
8538 return r;
8539 return 0;
8540 }
8541
8542 static int pops(struct r600_shader_ctx *ctx, int pops)
8543 {
8544 unsigned force_pop = ctx->bc->force_add_cf;
8545
8546 if (!force_pop) {
8547 int alu_pop = 3;
8548 if (ctx->bc->cf_last) {
8549 if (ctx->bc->cf_last->op == CF_OP_ALU)
8550 alu_pop = 0;
8551 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8552 alu_pop = 1;
8553 }
8554 alu_pop += pops;
8555 if (alu_pop == 1) {
8556 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8557 ctx->bc->force_add_cf = 1;
8558 } else if (alu_pop == 2) {
8559 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8560 ctx->bc->force_add_cf = 1;
8561 } else {
8562 force_pop = 1;
8563 }
8564 }
8565
8566 if (force_pop) {
8567 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8568 ctx->bc->cf_last->pop_count = pops;
8569 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8570 }
8571
8572 return 0;
8573 }
8574
8575 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8576 unsigned reason)
8577 {
8578 struct r600_stack_info *stack = &ctx->bc->stack;
8579 unsigned elements, entries;
8580
8581 unsigned entry_size = stack->entry_size;
8582
8583 elements = (stack->loop + stack->push_wqm ) * entry_size;
8584 elements += stack->push;
8585
8586 switch (ctx->bc->chip_class) {
8587 case R600:
8588 case R700:
8589 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8590 * the stack must be reserved to hold the current active/continue
8591 * masks */
8592 if (reason == FC_PUSH_VPM) {
8593 elements += 2;
8594 }
8595 break;
8596
8597 case CAYMAN:
8598 /* r9xx: any stack operation on empty stack consumes 2 additional
8599 * elements */
8600 elements += 2;
8601
8602 /* fallthrough */
8603 /* FIXME: do the two elements added above cover the cases for the
8604 * r8xx+ below? */
8605
8606 case EVERGREEN:
8607 /* r8xx+: 2 extra elements are not always required, but one extra
8608 * element must be added for each of the following cases:
8609 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8610 * stack usage.
8611 * (Currently we don't use ALU_ELSE_AFTER.)
8612 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8613 * PUSH instruction executed.
8614 *
8615 * NOTE: it seems we also need to reserve additional element in some
8616 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8617 * then STACK_SIZE should be 2 instead of 1 */
8618 if (reason == FC_PUSH_VPM) {
8619 elements += 1;
8620 }
8621 break;
8622
8623 default:
8624 assert(0);
8625 break;
8626 }
8627
8628 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8629 * for all chips, so we use 4 in the final formula, not the real entry_size
8630 * for the chip */
8631 entry_size = 4;
8632
8633 entries = (elements + (entry_size - 1)) / entry_size;
8634
8635 if (entries > stack->max_entries)
8636 stack->max_entries = entries;
8637 }
8638
8639 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8640 {
8641 switch(reason) {
8642 case FC_PUSH_VPM:
8643 --ctx->bc->stack.push;
8644 assert(ctx->bc->stack.push >= 0);
8645 break;
8646 case FC_PUSH_WQM:
8647 --ctx->bc->stack.push_wqm;
8648 assert(ctx->bc->stack.push_wqm >= 0);
8649 break;
8650 case FC_LOOP:
8651 --ctx->bc->stack.loop;
8652 assert(ctx->bc->stack.loop >= 0);
8653 break;
8654 default:
8655 assert(0);
8656 break;
8657 }
8658 }
8659
8660 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8661 {
8662 switch (reason) {
8663 case FC_PUSH_VPM:
8664 ++ctx->bc->stack.push;
8665 break;
8666 case FC_PUSH_WQM:
8667 ++ctx->bc->stack.push_wqm;
8668 case FC_LOOP:
8669 ++ctx->bc->stack.loop;
8670 break;
8671 default:
8672 assert(0);
8673 }
8674
8675 callstack_update_max_depth(ctx, reason);
8676 }
8677
8678 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8679 {
8680 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8681
8682 sp->mid = realloc((void *)sp->mid,
8683 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8684 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8685 sp->num_mid++;
8686 }
8687
8688 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8689 {
8690 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
8691 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8692 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8693 ctx->bc->fc_sp++;
8694 }
8695
8696 static void fc_poplevel(struct r600_shader_ctx *ctx)
8697 {
8698 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
8699 free(sp->mid);
8700 sp->mid = NULL;
8701 sp->num_mid = 0;
8702 sp->start = NULL;
8703 sp->type = 0;
8704 ctx->bc->fc_sp--;
8705 }
8706
8707 #if 0
8708 static int emit_return(struct r600_shader_ctx *ctx)
8709 {
8710 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8711 return 0;
8712 }
8713
8714 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8715 {
8716
8717 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8718 ctx->bc->cf_last->pop_count = pops;
8719 /* XXX work out offset */
8720 return 0;
8721 }
8722
8723 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8724 {
8725 return 0;
8726 }
8727
8728 static void emit_testflag(struct r600_shader_ctx *ctx)
8729 {
8730
8731 }
8732
8733 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8734 {
8735 emit_testflag(ctx);
8736 emit_jump_to_offset(ctx, 1, 4);
8737 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8738 pops(ctx, ifidx + 1);
8739 emit_return(ctx);
8740 }
8741
8742 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8743 {
8744 emit_testflag(ctx);
8745
8746 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8747 ctx->bc->cf_last->pop_count = 1;
8748
8749 fc_set_mid(ctx, fc_sp);
8750
8751 pops(ctx, 1);
8752 }
8753 #endif
8754
8755 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8756 {
8757 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8758
8759 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8760 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8761 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8762 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8763 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8764 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8765 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8766 alu_type = CF_OP_ALU;
8767 }
8768
8769 emit_logic_pred(ctx, opcode, alu_type);
8770
8771 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8772
8773 fc_pushlevel(ctx, FC_IF);
8774
8775 callstack_push(ctx, FC_PUSH_VPM);
8776 return 0;
8777 }
8778
8779 static int tgsi_if(struct r600_shader_ctx *ctx)
8780 {
8781 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8782 }
8783
8784 static int tgsi_uif(struct r600_shader_ctx *ctx)
8785 {
8786 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8787 }
8788
8789 static int tgsi_else(struct r600_shader_ctx *ctx)
8790 {
8791 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8792 ctx->bc->cf_last->pop_count = 1;
8793
8794 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
8795 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
8796 return 0;
8797 }
8798
8799 static int tgsi_endif(struct r600_shader_ctx *ctx)
8800 {
8801 pops(ctx, 1);
8802 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
8803 R600_ERR("if/endif unbalanced in shader\n");
8804 return -1;
8805 }
8806
8807 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
8808 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8809 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
8810 } else {
8811 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8812 }
8813 fc_poplevel(ctx);
8814
8815 callstack_pop(ctx, FC_PUSH_VPM);
8816 return 0;
8817 }
8818
8819 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8820 {
8821 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8822 * limited to 4096 iterations, like the other LOOP_* instructions. */
8823 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8824
8825 fc_pushlevel(ctx, FC_LOOP);
8826
8827 /* check stack depth */
8828 callstack_push(ctx, FC_LOOP);
8829 return 0;
8830 }
8831
8832 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8833 {
8834 unsigned i;
8835
8836 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8837
8838 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
8839 R600_ERR("loop/endloop in shader code are not paired.\n");
8840 return -EINVAL;
8841 }
8842
8843 /* fixup loop pointers - from r600isa
8844 LOOP END points to CF after LOOP START,
8845 LOOP START point to CF after LOOP END
8846 BRK/CONT point to LOOP END CF
8847 */
8848 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
8849
8850 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8851
8852 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
8853 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
8854 }
8855 /* XXX add LOOPRET support */
8856 fc_poplevel(ctx);
8857 callstack_pop(ctx, FC_LOOP);
8858 return 0;
8859 }
8860
8861 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8862 {
8863 unsigned int fscp;
8864
8865 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8866 {
8867 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
8868 break;
8869 }
8870
8871 if (fscp == 0) {
8872 R600_ERR("Break not inside loop/endloop pair\n");
8873 return -EINVAL;
8874 }
8875
8876 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8877
8878 fc_set_mid(ctx, fscp - 1);
8879
8880 return 0;
8881 }
8882
8883 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8884 {
8885 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8886 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8887 int r;
8888
8889 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8890 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
8891
8892 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8893 if (!r) {
8894 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
8895 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8896 return emit_inc_ring_offset(ctx, stream, TRUE);
8897 }
8898 return r;
8899 }
8900
8901 static int tgsi_umad(struct r600_shader_ctx *ctx)
8902 {
8903 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8904 struct r600_bytecode_alu alu;
8905 int i, j, k, r;
8906 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8907
8908 /* src0 * src1 */
8909 for (i = 0; i < lasti + 1; i++) {
8910 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8911 continue;
8912
8913 if (ctx->bc->chip_class == CAYMAN) {
8914 for (j = 0 ; j < 4; j++) {
8915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8916
8917 alu.op = ALU_OP2_MULLO_UINT;
8918 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
8919 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
8920 }
8921 alu.dst.chan = j;
8922 alu.dst.sel = ctx->temp_reg;
8923 alu.dst.write = (j == i);
8924 if (j == 3)
8925 alu.last = 1;
8926 r = r600_bytecode_add_alu(ctx->bc, &alu);
8927 if (r)
8928 return r;
8929 }
8930 } else {
8931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8932
8933 alu.dst.chan = i;
8934 alu.dst.sel = ctx->temp_reg;
8935 alu.dst.write = 1;
8936
8937 alu.op = ALU_OP2_MULLO_UINT;
8938 for (j = 0; j < 2; j++) {
8939 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
8940 }
8941
8942 alu.last = 1;
8943 r = r600_bytecode_add_alu(ctx->bc, &alu);
8944 if (r)
8945 return r;
8946 }
8947 }
8948
8949
8950 for (i = 0; i < lasti + 1; i++) {
8951 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8952 continue;
8953
8954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8955 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8956
8957 alu.op = ALU_OP2_ADD_INT;
8958
8959 alu.src[0].sel = ctx->temp_reg;
8960 alu.src[0].chan = i;
8961
8962 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8963 if (i == lasti) {
8964 alu.last = 1;
8965 }
8966 r = r600_bytecode_add_alu(ctx->bc, &alu);
8967 if (r)
8968 return r;
8969 }
8970 return 0;
8971 }
8972
8973 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
8974 {
8975 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8976 struct r600_bytecode_alu alu;
8977 int r, i;
8978 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8979
8980 /* temp.xy = f32_to_f16(src) */
8981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8982 alu.op = ALU_OP1_FLT32_TO_FLT16;
8983 alu.dst.chan = 0;
8984 alu.dst.sel = ctx->temp_reg;
8985 alu.dst.write = 1;
8986 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8987 r = r600_bytecode_add_alu(ctx->bc, &alu);
8988 if (r)
8989 return r;
8990 alu.dst.chan = 1;
8991 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
8992 alu.last = 1;
8993 r = r600_bytecode_add_alu(ctx->bc, &alu);
8994 if (r)
8995 return r;
8996
8997 /* dst.x = temp.y * 0x10000 + temp.x */
8998 for (i = 0; i < lasti + 1; i++) {
8999 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9000 continue;
9001
9002 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9003 alu.op = ALU_OP3_MULADD_UINT24;
9004 alu.is_op3 = 1;
9005 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9006 alu.last = i == lasti;
9007 alu.src[0].sel = ctx->temp_reg;
9008 alu.src[0].chan = 1;
9009 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9010 alu.src[1].value = 0x10000;
9011 alu.src[2].sel = ctx->temp_reg;
9012 alu.src[2].chan = 0;
9013 r = r600_bytecode_add_alu(ctx->bc, &alu);
9014 if (r)
9015 return r;
9016 }
9017
9018 return 0;
9019 }
9020
9021 static int tgsi_up2h(struct r600_shader_ctx *ctx)
9022 {
9023 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9024 struct r600_bytecode_alu alu;
9025 int r, i;
9026 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9027
9028 /* temp.x = src.x */
9029 /* note: no need to mask out the high bits */
9030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9031 alu.op = ALU_OP1_MOV;
9032 alu.dst.chan = 0;
9033 alu.dst.sel = ctx->temp_reg;
9034 alu.dst.write = 1;
9035 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9036 r = r600_bytecode_add_alu(ctx->bc, &alu);
9037 if (r)
9038 return r;
9039
9040 /* temp.y = src.x >> 16 */
9041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9042 alu.op = ALU_OP2_LSHR_INT;
9043 alu.dst.chan = 1;
9044 alu.dst.sel = ctx->temp_reg;
9045 alu.dst.write = 1;
9046 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9047 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9048 alu.src[1].value = 16;
9049 alu.last = 1;
9050 r = r600_bytecode_add_alu(ctx->bc, &alu);
9051 if (r)
9052 return r;
9053
9054 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9055 for (i = 0; i < lasti + 1; i++) {
9056 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9057 continue;
9058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9059 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9060 alu.op = ALU_OP1_FLT16_TO_FLT32;
9061 alu.src[0].sel = ctx->temp_reg;
9062 alu.src[0].chan = i % 2;
9063 alu.last = i == lasti;
9064 r = r600_bytecode_add_alu(ctx->bc, &alu);
9065 if (r)
9066 return r;
9067 }
9068
9069 return 0;
9070 }
9071
9072 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
9073 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
9074 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9075 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9076
9077 /* XXX:
9078 * For state trackers other than OpenGL, we'll want to use
9079 * _RECIP_IEEE instead.
9080 */
9081 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
9082
9083 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9084 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9085 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9086 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9087 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9088 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9089 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9090 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9091 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9092 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9093 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9094 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9095 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9096 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9097 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9098 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9099 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9100 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9101 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9102 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9103 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9104 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9105 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9106 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9107 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9108 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9109 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9110 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9111 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9112 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9113 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9114 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9115 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9116 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9117 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9118 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9119 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9120 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9121 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9122 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9123 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9124 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9125 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9126 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9127 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9128 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9129 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9130 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9131 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9132 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9133 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9134 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9135 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9136 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9137 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9138 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9139 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9140 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9141 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9142 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9143 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9144 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9145 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9146 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9147 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9148 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9149 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9150 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9151 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9152 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9153 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9154 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9155 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9156 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9157 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9158 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9159 [81] = { ALU_OP0_NOP, tgsi_unsupported},
9160 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9161 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9162 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9163 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9164 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9165 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9166 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9167 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9168 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9169 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9170 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9171 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9172 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9173 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9174 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9175 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9176 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9177 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9178 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9179 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9180 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9181 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9182 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9183 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9184 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9185 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9186 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9187 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9188 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9189 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9190 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9191 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9192 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9193 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9194 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9195 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9196 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9197 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9198 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9199 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9200 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9201 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9202 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9203 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9204 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9205 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9206 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9207 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9208 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9209 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9210 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9211 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9212 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9213 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9214 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9215 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9216 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9217 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9218 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9219 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9220 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9221 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9222 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9223 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9224 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9225 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9226 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9227 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9228 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9229 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9230 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9231 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9232 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9233 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9234 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9235 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9236 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9237 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9238 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9239 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9240 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9241 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9242 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9243 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9244 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9245 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9246 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9247 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9248 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9249 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9250 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9251 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9252 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9253 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9254 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9255 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9256 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9257 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9258 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9259 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9260 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9261 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9262 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9263 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9264 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9265 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9266 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9267 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9268 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9269 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9270 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9271 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9272 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9273 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9274 };
9275
9276 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9277 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9278 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9279 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9280 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9281 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
9282 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9283 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9284 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9285 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9286 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9287 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9288 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9289 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9290 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9291 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9292 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9293 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9294 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9295 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9296 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9297 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9298 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9299 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9300 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9301 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9302 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9303 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9304 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9305 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9306 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9307 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9308 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9309 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9310 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9311 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9312 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9313 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9314 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9315 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9316 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9317 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9318 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9319 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9320 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9321 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9322 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9323 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9324 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9325 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9326 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9327 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9328 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9329 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9330 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9331 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9332 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9333 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9334 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9335 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9336 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9337 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9338 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9339 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9340 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9341 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9342 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9343 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9344 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9345 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9346 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9347 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9348 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9349 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9350 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9351 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9352 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9353 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9354 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9355 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9356 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9357 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9358 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9359 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9360 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9361 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9362 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9363 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9364 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9365 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9366 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9367 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9368 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9369 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9370 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9371 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9372 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9373 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9374 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9375 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9376 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9377 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9378 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9379 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9380 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9381 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9382 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9383 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9384 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9385 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9386 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9387 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9388 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9389 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9390 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9391 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9392 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9393 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9394 /* Refer below for TGSI_OPCODE_DFMA */
9395 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9396 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9397 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9398 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9399 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9400 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9401 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9402 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9403 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9404 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9405 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9406 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9407 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9408 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9409 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9410 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9411 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9412 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9413 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9414 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9415 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9416 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9417 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9418 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9419 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9420 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9421 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9422 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9423 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9424 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9425 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9426 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9427 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9428 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9429 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9430 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9431 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9432 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9433 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9434 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9435 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9436 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9437 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9438 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9439 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9440 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9441 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9442 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9443 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9444 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9445 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9446 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9447 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9448 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9449 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9450 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9451 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9452 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9453 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9454 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9455 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9456 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9457 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9458 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9459 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9460 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9461 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9462 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9463 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9464 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9465 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9466 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9467 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9468 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9469 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9470 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9471 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9472 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9473 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9474 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9475 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9476 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9477 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9478 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9479 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9480 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9481 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9482 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9483 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9484 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9485 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9486 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9487 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9488 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9489 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9490 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9491 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9492 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9493 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9494 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9495 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9496 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9497 };
9498
9499 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9500 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9501 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9502 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9503 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9504 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9505 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9506 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9507 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9508 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9509 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9510 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9511 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9512 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9513 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9514 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9515 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9516 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9517 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9518 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9519 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9520 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9521 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9522 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9523 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9524 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9525 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9526 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9527 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9528 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9529 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9530 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9531 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9532 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9533 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9534 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9535 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9536 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9537 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9538 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9539 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9540 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9541 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9542 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9543 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9544 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9545 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9546 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9547 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9548 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9549 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9550 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9551 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9552 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9553 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9554 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9555 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9556 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9557 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9558 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9559 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9560 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9561 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9562 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9563 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9564 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9565 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9566 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9567 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9568 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9569 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9570 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9571 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9572 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9573 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9574 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9575 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9576 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9577 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9578 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9579 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9580 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9581 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9582 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9583 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9584 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9585 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9586 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9587 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9588 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9589 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9590 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9591 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9592 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9593 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9594 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9595 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9596 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9597 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9598 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9599 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9600 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9601 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9602 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9603 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9604 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9605 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9606 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9607 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9608 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9609 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9610 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9611 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9612 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9613 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9614 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9615 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9616 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9617 /* Refer below for TGSI_OPCODE_DFMA */
9618 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9619 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9620 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9621 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9622 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9623 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9624 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9625 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9626 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9627 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9628 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9629 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9630 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9631 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9632 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9633 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9634 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9635 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9636 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9637 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9638 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9639 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9640 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9641 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9642 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9643 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9644 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9645 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9646 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9647 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9648 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9649 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9650 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9651 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9652 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9653 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9654 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9655 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9656 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9657 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9658 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9659 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9660 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9661 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9662 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9663 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9664 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9665 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9666 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9667 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9668 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9669 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9670 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9671 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9672 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9673 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9674 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9675 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9676 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9677 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9678 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9679 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9680 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9681 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9682 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9683 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9684 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9685 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9686 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9687 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9688 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9689 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9690 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9691 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9692 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9693 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9694 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9695 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9696 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9697 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9698 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9699 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9700 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9701 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9702 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9703 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9704 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9705 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9706 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9707 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9708 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9709 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9710 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9711 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9712 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9713 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9714 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9715 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9716 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9717 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9718 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9719 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9720 };