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r600/shader: implement getting thread id.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 use_sb &= !shader->shader.uses_atomics;
198
199 /* Check if the bytecode has already been built. */
200 if (!shader->shader.bc.bytecode) {
201 r = r600_bytecode_build(&shader->shader.bc);
202 if (r) {
203 R600_ERR("building bytecode failed !\n");
204 goto error;
205 }
206 }
207
208 if (dump && !sb_disasm) {
209 fprintf(stderr, "--------------------------------------------------------------\n");
210 r600_bytecode_disasm(&shader->shader.bc);
211 fprintf(stderr, "______________________________________________________________\n");
212 } else if ((dump && sb_disasm) || use_sb) {
213 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
214 dump, use_sb);
215 if (r) {
216 R600_ERR("r600_sb_bytecode_process failed !\n");
217 goto error;
218 }
219 }
220
221 if (shader->gs_copy_shader) {
222 if (dump) {
223 // dump copy shader
224 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
225 &shader->gs_copy_shader->shader, dump, 0);
226 if (r)
227 goto error;
228 }
229
230 if ((r = store_shader(ctx, shader->gs_copy_shader)))
231 goto error;
232 }
233
234 /* Store the shader in a buffer. */
235 if ((r = store_shader(ctx, shader)))
236 goto error;
237
238 /* Build state. */
239 switch (shader->shader.processor_type) {
240 case PIPE_SHADER_TESS_CTRL:
241 evergreen_update_hs_state(ctx, shader);
242 break;
243 case PIPE_SHADER_TESS_EVAL:
244 if (key.tes.as_es)
245 evergreen_update_es_state(ctx, shader);
246 else
247 evergreen_update_vs_state(ctx, shader);
248 break;
249 case PIPE_SHADER_GEOMETRY:
250 if (rctx->b.chip_class >= EVERGREEN) {
251 evergreen_update_gs_state(ctx, shader);
252 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
253 } else {
254 r600_update_gs_state(ctx, shader);
255 r600_update_vs_state(ctx, shader->gs_copy_shader);
256 }
257 break;
258 case PIPE_SHADER_VERTEX:
259 export_shader = key.vs.as_es;
260 if (rctx->b.chip_class >= EVERGREEN) {
261 if (key.vs.as_ls)
262 evergreen_update_ls_state(ctx, shader);
263 else if (key.vs.as_es)
264 evergreen_update_es_state(ctx, shader);
265 else
266 evergreen_update_vs_state(ctx, shader);
267 } else {
268 if (export_shader)
269 r600_update_es_state(ctx, shader);
270 else
271 r600_update_vs_state(ctx, shader);
272 }
273 break;
274 case PIPE_SHADER_FRAGMENT:
275 if (rctx->b.chip_class >= EVERGREEN) {
276 evergreen_update_ps_state(ctx, shader);
277 } else {
278 r600_update_ps_state(ctx, shader);
279 }
280 break;
281 default:
282 r = -EINVAL;
283 goto error;
284 }
285 return 0;
286
287 error:
288 r600_pipe_shader_destroy(ctx, shader);
289 return r;
290 }
291
292 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
293 {
294 r600_resource_reference(&shader->bo, NULL);
295 r600_bytecode_clear(&shader->shader.bc);
296 r600_release_command_buffer(&shader->command_buffer);
297 }
298
299 /*
300 * tgsi -> r600 shader
301 */
302 struct r600_shader_tgsi_instruction;
303
304 struct r600_shader_src {
305 unsigned sel;
306 unsigned swizzle[4];
307 unsigned neg;
308 unsigned abs;
309 unsigned rel;
310 unsigned kc_bank;
311 boolean kc_rel; /* true if cache bank is indexed */
312 uint32_t value[4];
313 };
314
315 struct eg_interp {
316 boolean enabled;
317 unsigned ij_index;
318 };
319
320 struct r600_shader_ctx {
321 struct tgsi_shader_info info;
322 struct tgsi_parse_context parse;
323 const struct tgsi_token *tokens;
324 unsigned type;
325 unsigned file_offset[TGSI_FILE_COUNT];
326 unsigned temp_reg;
327 const struct r600_shader_tgsi_instruction *inst_info;
328 struct r600_bytecode *bc;
329 struct r600_shader *shader;
330 struct r600_shader_src src[4];
331 uint32_t *literals;
332 uint32_t nliterals;
333 uint32_t max_driver_temp_used;
334 /* needed for evergreen interpolation */
335 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
336 /* evergreen/cayman also store sample mask in face register */
337 int face_gpr;
338 /* sample id is .w component stored in fixed point position register */
339 int fixed_pt_position_gpr;
340 int colors_used;
341 boolean clip_vertex_write;
342 unsigned cv_output;
343 unsigned edgeflag_output;
344 int fragcoord_input;
345 int native_integers;
346 int next_ring_offset;
347 int gs_out_ring_offset;
348 int gs_next_vertex;
349 struct r600_shader *gs_for_vs;
350 int gs_export_gpr_tregs[4];
351 int gs_rotated_input[2];
352 const struct pipe_stream_output_info *gs_stream_output_info;
353 unsigned enabled_stream_buffers_mask;
354 unsigned tess_input_info; /* temp with tess input offsets */
355 unsigned tess_output_info; /* temp with tess input offsets */
356 unsigned thread_id_gpr; /* temp with thread id calculated for images */
357 };
358
359 struct r600_shader_tgsi_instruction {
360 unsigned op;
361 int (*process)(struct r600_shader_ctx *ctx);
362 };
363
364 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
365 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
366 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
367 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
368 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
369 static int tgsi_else(struct r600_shader_ctx *ctx);
370 static int tgsi_endif(struct r600_shader_ctx *ctx);
371 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
372 static int tgsi_endloop(struct r600_shader_ctx *ctx);
373 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
374 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
375 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
376 unsigned int dst_reg);
377 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
378 const struct r600_shader_src *shader_src,
379 unsigned chan);
380 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
381 unsigned dst_reg);
382
383 static int tgsi_last_instruction(unsigned writemask)
384 {
385 int i, lasti = 0;
386
387 for (i = 0; i < 4; i++) {
388 if (writemask & (1 << i)) {
389 lasti = i;
390 }
391 }
392 return lasti;
393 }
394
395 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
396 {
397 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
398 unsigned j;
399
400 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
401 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
402 return -EINVAL;
403 }
404 #if 0
405 if (i->Instruction.Label) {
406 R600_ERR("label unsupported\n");
407 return -EINVAL;
408 }
409 #endif
410 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
411 if (i->Src[j].Register.Dimension) {
412 switch (i->Src[j].Register.File) {
413 case TGSI_FILE_CONSTANT:
414 case TGSI_FILE_HW_ATOMIC:
415 break;
416 case TGSI_FILE_INPUT:
417 if (ctx->type == PIPE_SHADER_GEOMETRY ||
418 ctx->type == PIPE_SHADER_TESS_CTRL ||
419 ctx->type == PIPE_SHADER_TESS_EVAL)
420 break;
421 case TGSI_FILE_OUTPUT:
422 if (ctx->type == PIPE_SHADER_TESS_CTRL)
423 break;
424 default:
425 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
426 i->Src[j].Register.File,
427 i->Src[j].Register.Dimension);
428 return -EINVAL;
429 }
430 }
431 }
432 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
433 if (i->Dst[j].Register.Dimension) {
434 if (ctx->type == PIPE_SHADER_TESS_CTRL)
435 continue;
436 R600_ERR("unsupported dst (dimension)\n");
437 return -EINVAL;
438 }
439 }
440 return 0;
441 }
442
443 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
444 {
445 if (interpolate == TGSI_INTERPOLATE_COLOR ||
446 interpolate == TGSI_INTERPOLATE_LINEAR ||
447 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
448 {
449 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
450 int loc;
451
452 switch(location) {
453 case TGSI_INTERPOLATE_LOC_CENTER:
454 loc = 1;
455 break;
456 case TGSI_INTERPOLATE_LOC_CENTROID:
457 loc = 2;
458 break;
459 case TGSI_INTERPOLATE_LOC_SAMPLE:
460 default:
461 loc = 0; break;
462 }
463
464 return is_linear * 3 + loc;
465 }
466
467 return -1;
468 }
469
470 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
471 int input)
472 {
473 int i = eg_get_interpolator_index(
474 ctx->shader->input[input].interpolate,
475 ctx->shader->input[input].interpolate_location);
476 assert(i >= 0);
477 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
478 }
479
480 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
481 {
482 int i, r;
483 struct r600_bytecode_alu alu;
484 int gpr = 0, base_chan = 0;
485 int ij_index = ctx->shader->input[input].ij_index;
486
487 /* work out gpr and base_chan from index */
488 gpr = ij_index / 2;
489 base_chan = (2 * (ij_index % 2)) + 1;
490
491 for (i = 0; i < 8; i++) {
492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
493
494 if (i < 4)
495 alu.op = ALU_OP2_INTERP_ZW;
496 else
497 alu.op = ALU_OP2_INTERP_XY;
498
499 if ((i > 1) && (i < 6)) {
500 alu.dst.sel = ctx->shader->input[input].gpr;
501 alu.dst.write = 1;
502 }
503
504 alu.dst.chan = i % 4;
505
506 alu.src[0].sel = gpr;
507 alu.src[0].chan = (base_chan - (i % 2));
508
509 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
510
511 alu.bank_swizzle_force = SQ_ALU_VEC_210;
512 if ((i % 4) == 3)
513 alu.last = 1;
514 r = r600_bytecode_add_alu(ctx->bc, &alu);
515 if (r)
516 return r;
517 }
518 return 0;
519 }
520
521 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
522 {
523 int i, r;
524 struct r600_bytecode_alu alu;
525
526 for (i = 0; i < 4; i++) {
527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
528
529 alu.op = ALU_OP1_INTERP_LOAD_P0;
530
531 alu.dst.sel = ctx->shader->input[input].gpr;
532 alu.dst.write = 1;
533
534 alu.dst.chan = i;
535
536 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
537 alu.src[0].chan = i;
538
539 if (i == 3)
540 alu.last = 1;
541 r = r600_bytecode_add_alu(ctx->bc, &alu);
542 if (r)
543 return r;
544 }
545 return 0;
546 }
547
548 /*
549 * Special export handling in shaders
550 *
551 * shader export ARRAY_BASE for EXPORT_POS:
552 * 60 is position
553 * 61 is misc vector
554 * 62, 63 are clip distance vectors
555 *
556 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
557 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
558 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
559 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
560 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
561 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
562 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
563 * exclusive from render target index)
564 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
565 *
566 *
567 * shader export ARRAY_BASE for EXPORT_PIXEL:
568 * 0-7 CB targets
569 * 61 computed Z vector
570 *
571 * The use of the values exported in the computed Z vector are controlled
572 * by DB_SHADER_CONTROL:
573 * Z_EXPORT_ENABLE - Z as a float in RED
574 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
575 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
576 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
577 * DB_SOURCE_FORMAT - export control restrictions
578 *
579 */
580
581
582 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
583 static int r600_spi_sid(struct r600_shader_io * io)
584 {
585 int index, name = io->name;
586
587 /* These params are handled differently, they don't need
588 * semantic indices, so we'll use 0 for them.
589 */
590 if (name == TGSI_SEMANTIC_POSITION ||
591 name == TGSI_SEMANTIC_PSIZE ||
592 name == TGSI_SEMANTIC_EDGEFLAG ||
593 name == TGSI_SEMANTIC_FACE ||
594 name == TGSI_SEMANTIC_SAMPLEMASK)
595 index = 0;
596 else {
597 if (name == TGSI_SEMANTIC_GENERIC) {
598 /* For generic params simply use sid from tgsi */
599 index = io->sid;
600 } else {
601 /* For non-generic params - pack name and sid into 8 bits */
602 index = 0x80 | (name<<3) | (io->sid);
603 }
604
605 /* Make sure that all really used indices have nonzero value, so
606 * we can just compare it to 0 later instead of comparing the name
607 * with different values to detect special cases. */
608 index++;
609 }
610
611 return index;
612 };
613
614 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
615 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
616 {
617 switch (semantic_name) {
618 case TGSI_SEMANTIC_POSITION:
619 return 0;
620 case TGSI_SEMANTIC_PSIZE:
621 return 1;
622 case TGSI_SEMANTIC_CLIPDIST:
623 assert(index <= 1);
624 return 2 + index;
625 case TGSI_SEMANTIC_GENERIC:
626 if (index <= 63-4)
627 return 4 + index - 9;
628 else
629 /* same explanation as in the default statement,
630 * the only user hitting this is st/nine.
631 */
632 return 0;
633
634 /* patch indices are completely separate and thus start from 0 */
635 case TGSI_SEMANTIC_TESSOUTER:
636 return 0;
637 case TGSI_SEMANTIC_TESSINNER:
638 return 1;
639 case TGSI_SEMANTIC_PATCH:
640 return 2 + index;
641
642 default:
643 /* Don't fail here. The result of this function is only used
644 * for LS, TCS, TES, and GS, where legacy GL semantics can't
645 * occur, but this function is called for all vertex shaders
646 * before it's known whether LS will be compiled or not.
647 */
648 return 0;
649 }
650 }
651
652 /* turn input into interpolate on EG */
653 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
654 {
655 int r = 0;
656
657 if (ctx->shader->input[index].spi_sid) {
658 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
659 if (ctx->shader->input[index].interpolate > 0) {
660 evergreen_interp_assign_ij_index(ctx, index);
661 r = evergreen_interp_alu(ctx, index);
662 } else {
663 r = evergreen_interp_flat(ctx, index);
664 }
665 }
666 return r;
667 }
668
669 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
670 {
671 struct r600_bytecode_alu alu;
672 int i, r;
673 int gpr_front = ctx->shader->input[front].gpr;
674 int gpr_back = ctx->shader->input[back].gpr;
675
676 for (i = 0; i < 4; i++) {
677 memset(&alu, 0, sizeof(alu));
678 alu.op = ALU_OP3_CNDGT;
679 alu.is_op3 = 1;
680 alu.dst.write = 1;
681 alu.dst.sel = gpr_front;
682 alu.src[0].sel = ctx->face_gpr;
683 alu.src[1].sel = gpr_front;
684 alu.src[2].sel = gpr_back;
685
686 alu.dst.chan = i;
687 alu.src[1].chan = i;
688 alu.src[2].chan = i;
689 alu.last = (i==3);
690
691 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
692 return r;
693 }
694
695 return 0;
696 }
697
698 /* execute a single slot ALU calculation */
699 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
700 int dst_sel, int dst_chan,
701 int src0_sel, unsigned src0_chan_val,
702 int src1_sel, unsigned src1_chan_val)
703 {
704 struct r600_bytecode_alu alu;
705 int r, i;
706
707 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
708 for (i = 0; i < 4; i++) {
709 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
710 alu.op = op;
711 alu.src[0].sel = src0_sel;
712 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
713 alu.src[0].value = src0_chan_val;
714 else
715 alu.src[0].chan = src0_chan_val;
716 alu.src[1].sel = src1_sel;
717 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
718 alu.src[1].value = src1_chan_val;
719 else
720 alu.src[1].chan = src1_chan_val;
721 alu.dst.sel = dst_sel;
722 alu.dst.chan = i;
723 alu.dst.write = i == dst_chan;
724 alu.last = (i == 3);
725 r = r600_bytecode_add_alu(ctx->bc, &alu);
726 if (r)
727 return r;
728 }
729 return 0;
730 }
731
732 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
733 alu.op = op;
734 alu.src[0].sel = src0_sel;
735 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
736 alu.src[0].value = src0_chan_val;
737 else
738 alu.src[0].chan = src0_chan_val;
739 alu.src[1].sel = src1_sel;
740 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
741 alu.src[1].value = src1_chan_val;
742 else
743 alu.src[1].chan = src1_chan_val;
744 alu.dst.sel = dst_sel;
745 alu.dst.chan = dst_chan;
746 alu.dst.write = 1;
747 alu.last = 1;
748 r = r600_bytecode_add_alu(ctx->bc, &alu);
749 if (r)
750 return r;
751 return 0;
752 }
753
754 /* execute a single slot ALU calculation */
755 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
756 int dst_sel, int dst_chan,
757 int src0_sel, unsigned src0_chan_val,
758 int src1_sel, unsigned src1_chan_val,
759 int src2_sel, unsigned src2_chan_val)
760 {
761 struct r600_bytecode_alu alu;
762 int r;
763
764 /* validate this for other ops */
765 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
766 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
767 alu.op = op;
768 alu.src[0].sel = src0_sel;
769 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
770 alu.src[0].value = src0_chan_val;
771 else
772 alu.src[0].chan = src0_chan_val;
773 alu.src[1].sel = src1_sel;
774 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
775 alu.src[1].value = src1_chan_val;
776 else
777 alu.src[1].chan = src1_chan_val;
778 alu.src[2].sel = src2_sel;
779 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
780 alu.src[2].value = src2_chan_val;
781 else
782 alu.src[2].chan = src2_chan_val;
783 alu.dst.sel = dst_sel;
784 alu.dst.chan = dst_chan;
785 alu.is_op3 = 1;
786 alu.last = 1;
787 r = r600_bytecode_add_alu(ctx->bc, &alu);
788 if (r)
789 return r;
790 return 0;
791 }
792
793 /* put it in temp_reg.x */
794 static int get_lds_offset0(struct r600_shader_ctx *ctx,
795 int rel_patch_chan,
796 int temp_reg, bool is_patch_var)
797 {
798 int r;
799
800 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
801 /* ADD
802 Dimension - patch0_offset (input_vals.z),
803 Non-dim - patch0_data_offset (input_vals.w)
804 */
805 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
806 temp_reg, 0,
807 ctx->tess_output_info, 0,
808 0, rel_patch_chan,
809 ctx->tess_output_info, is_patch_var ? 3 : 2);
810 if (r)
811 return r;
812 return 0;
813 }
814
815 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
816 {
817 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
818 }
819
820 static int r600_get_temp(struct r600_shader_ctx *ctx)
821 {
822 return ctx->temp_reg + ctx->max_driver_temp_used++;
823 }
824
825 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
826 {
827 int i;
828 i = ctx->shader->noutput++;
829 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
830 ctx->shader->output[i].sid = 0;
831 ctx->shader->output[i].gpr = 0;
832 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
833 ctx->shader->output[i].write_mask = 0x4;
834 ctx->shader->output[i].spi_sid = prim_id_sid;
835
836 return 0;
837 }
838
839 static int tgsi_barrier(struct r600_shader_ctx *ctx)
840 {
841 struct r600_bytecode_alu alu;
842 int r;
843
844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
845 alu.op = ctx->inst_info->op;
846 alu.last = 1;
847
848 r = r600_bytecode_add_alu(ctx->bc, &alu);
849 if (r)
850 return r;
851 return 0;
852 }
853
854 static int tgsi_declaration(struct r600_shader_ctx *ctx)
855 {
856 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
857 int r, i, j, count = d->Range.Last - d->Range.First + 1;
858
859 switch (d->Declaration.File) {
860 case TGSI_FILE_INPUT:
861 for (j = 0; j < count; j++) {
862 i = ctx->shader->ninput + j;
863 assert(i < ARRAY_SIZE(ctx->shader->input));
864 ctx->shader->input[i].name = d->Semantic.Name;
865 ctx->shader->input[i].sid = d->Semantic.Index + j;
866 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
867 ctx->shader->input[i].interpolate_location = d->Interp.Location;
868 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
869 if (ctx->type == PIPE_SHADER_FRAGMENT) {
870 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
871 switch (ctx->shader->input[i].name) {
872 case TGSI_SEMANTIC_FACE:
873 if (ctx->face_gpr != -1)
874 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
875 else
876 ctx->face_gpr = ctx->shader->input[i].gpr;
877 break;
878 case TGSI_SEMANTIC_COLOR:
879 ctx->colors_used++;
880 break;
881 case TGSI_SEMANTIC_POSITION:
882 ctx->fragcoord_input = i;
883 break;
884 case TGSI_SEMANTIC_PRIMID:
885 /* set this for now */
886 ctx->shader->gs_prim_id_input = true;
887 ctx->shader->ps_prim_id_input = i;
888 break;
889 }
890 if (ctx->bc->chip_class >= EVERGREEN) {
891 if ((r = evergreen_interp_input(ctx, i)))
892 return r;
893 }
894 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
895 /* FIXME probably skip inputs if they aren't passed in the ring */
896 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
897 ctx->next_ring_offset += 16;
898 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
899 ctx->shader->gs_prim_id_input = true;
900 }
901 }
902 ctx->shader->ninput += count;
903 break;
904 case TGSI_FILE_OUTPUT:
905 for (j = 0; j < count; j++) {
906 i = ctx->shader->noutput + j;
907 assert(i < ARRAY_SIZE(ctx->shader->output));
908 ctx->shader->output[i].name = d->Semantic.Name;
909 ctx->shader->output[i].sid = d->Semantic.Index + j;
910 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
911 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
912 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
913 if (ctx->type == PIPE_SHADER_VERTEX ||
914 ctx->type == PIPE_SHADER_GEOMETRY ||
915 ctx->type == PIPE_SHADER_TESS_EVAL) {
916 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
917 switch (d->Semantic.Name) {
918 case TGSI_SEMANTIC_CLIPDIST:
919 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
920 ((d->Semantic.Index + j) << 2);
921 break;
922 case TGSI_SEMANTIC_PSIZE:
923 ctx->shader->vs_out_misc_write = 1;
924 ctx->shader->vs_out_point_size = 1;
925 break;
926 case TGSI_SEMANTIC_EDGEFLAG:
927 ctx->shader->vs_out_misc_write = 1;
928 ctx->shader->vs_out_edgeflag = 1;
929 ctx->edgeflag_output = i;
930 break;
931 case TGSI_SEMANTIC_VIEWPORT_INDEX:
932 ctx->shader->vs_out_misc_write = 1;
933 ctx->shader->vs_out_viewport = 1;
934 break;
935 case TGSI_SEMANTIC_LAYER:
936 ctx->shader->vs_out_misc_write = 1;
937 ctx->shader->vs_out_layer = 1;
938 break;
939 case TGSI_SEMANTIC_CLIPVERTEX:
940 ctx->clip_vertex_write = TRUE;
941 ctx->cv_output = i;
942 break;
943 }
944 if (ctx->type == PIPE_SHADER_GEOMETRY) {
945 ctx->gs_out_ring_offset += 16;
946 }
947 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
948 switch (d->Semantic.Name) {
949 case TGSI_SEMANTIC_COLOR:
950 ctx->shader->nr_ps_max_color_exports++;
951 break;
952 }
953 }
954 }
955 ctx->shader->noutput += count;
956 break;
957 case TGSI_FILE_TEMPORARY:
958 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
959 if (d->Array.ArrayID) {
960 r600_add_gpr_array(ctx->shader,
961 ctx->file_offset[TGSI_FILE_TEMPORARY] +
962 d->Range.First,
963 d->Range.Last - d->Range.First + 1, 0x0F);
964 }
965 }
966 break;
967
968 case TGSI_FILE_CONSTANT:
969 case TGSI_FILE_SAMPLER:
970 case TGSI_FILE_SAMPLER_VIEW:
971 case TGSI_FILE_ADDRESS:
972 break;
973
974 case TGSI_FILE_HW_ATOMIC:
975 i = ctx->shader->nhwatomic_ranges;
976 ctx->shader->atomics[i].start = d->Range.First;
977 ctx->shader->atomics[i].end = d->Range.Last;
978 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
979 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
980 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
981 ctx->shader->nhwatomic_ranges++;
982 ctx->shader->nhwatomic += count;
983 break;
984
985 case TGSI_FILE_SYSTEM_VALUE:
986 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
987 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
988 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
989 break; /* Already handled from allocate_system_value_inputs */
990 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
991 if (!ctx->native_integers) {
992 struct r600_bytecode_alu alu;
993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
994
995 alu.op = ALU_OP1_INT_TO_FLT;
996 alu.src[0].sel = 0;
997 alu.src[0].chan = 3;
998
999 alu.dst.sel = 0;
1000 alu.dst.chan = 3;
1001 alu.dst.write = 1;
1002 alu.last = 1;
1003
1004 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1005 return r;
1006 }
1007 break;
1008 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1009 break;
1010 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1011 break;
1012 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1013 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1014 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1015 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1016 unsigned temp_reg = r600_get_temp(ctx);
1017
1018 r = get_lds_offset0(ctx, 2, temp_reg, true);
1019 if (r)
1020 return r;
1021
1022 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1023 temp_reg, 0,
1024 temp_reg, 0,
1025 V_SQ_ALU_SRC_LITERAL, param * 16);
1026 if (r)
1027 return r;
1028
1029 do_lds_fetch_values(ctx, temp_reg, dreg);
1030 }
1031 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1032 /* MOV r1.x, r0.x;
1033 MOV r1.y, r0.y;
1034 */
1035 for (i = 0; i < 2; i++) {
1036 struct r600_bytecode_alu alu;
1037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1038 alu.op = ALU_OP1_MOV;
1039 alu.src[0].sel = 0;
1040 alu.src[0].chan = 0 + i;
1041 alu.dst.sel = 1;
1042 alu.dst.chan = 0 + i;
1043 alu.dst.write = 1;
1044 alu.last = (i == 1) ? 1 : 0;
1045 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1046 return r;
1047 }
1048 /* ADD r1.z, 1.0f, -r0.x */
1049 struct r600_bytecode_alu alu;
1050 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1051 alu.op = ALU_OP2_ADD;
1052 alu.src[0].sel = V_SQ_ALU_SRC_1;
1053 alu.src[1].sel = 1;
1054 alu.src[1].chan = 0;
1055 alu.src[1].neg = 1;
1056 alu.dst.sel = 1;
1057 alu.dst.chan = 2;
1058 alu.dst.write = 1;
1059 alu.last = 1;
1060 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1061 return r;
1062
1063 /* ADD r1.z, r1.z, -r1.y */
1064 alu.op = ALU_OP2_ADD;
1065 alu.src[0].sel = 1;
1066 alu.src[0].chan = 2;
1067 alu.src[1].sel = 1;
1068 alu.src[1].chan = 1;
1069 alu.src[1].neg = 1;
1070 alu.dst.sel = 1;
1071 alu.dst.chan = 2;
1072 alu.dst.write = 1;
1073 alu.last = 1;
1074 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1075 return r;
1076 break;
1077 }
1078 break;
1079 default:
1080 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1081 return -EINVAL;
1082 }
1083 return 0;
1084 }
1085
1086 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1087 {
1088 struct tgsi_parse_context parse;
1089 struct {
1090 boolean enabled;
1091 int *reg;
1092 unsigned name, alternate_name;
1093 } inputs[2] = {
1094 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1095
1096 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1097 };
1098 int i, k, num_regs = 0;
1099
1100 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1101 return 0;
1102 }
1103
1104 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1105 while (!tgsi_parse_end_of_tokens(&parse)) {
1106 tgsi_parse_token(&parse);
1107
1108 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1109 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1110 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1111 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1112 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1113 {
1114 int interpolate, location, k;
1115
1116 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1117 location = TGSI_INTERPOLATE_LOC_CENTER;
1118 inputs[1].enabled = true; /* needs SAMPLEID */
1119 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1120 location = TGSI_INTERPOLATE_LOC_CENTER;
1121 /* Needs sample positions, currently those are always available */
1122 } else {
1123 location = TGSI_INTERPOLATE_LOC_CENTROID;
1124 }
1125
1126 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1127 k = eg_get_interpolator_index(interpolate, location);
1128 if (k >= 0)
1129 ctx->eg_interpolators[k].enabled = true;
1130 }
1131 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1132 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1133 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1134 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1135 if (d->Semantic.Name == inputs[k].name ||
1136 d->Semantic.Name == inputs[k].alternate_name) {
1137 inputs[k].enabled = true;
1138 }
1139 }
1140 }
1141 }
1142 }
1143
1144 tgsi_parse_free(&parse);
1145
1146 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1147 boolean enabled = inputs[i].enabled;
1148 int *reg = inputs[i].reg;
1149 unsigned name = inputs[i].name;
1150
1151 if (enabled) {
1152 int gpr = gpr_offset + num_regs++;
1153 ctx->shader->nsys_inputs++;
1154
1155 // add to inputs, allocate a gpr
1156 k = ctx->shader->ninput++;
1157 ctx->shader->input[k].name = name;
1158 ctx->shader->input[k].sid = 0;
1159 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1160 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1161 *reg = ctx->shader->input[k].gpr = gpr;
1162 }
1163 }
1164
1165 return gpr_offset + num_regs;
1166 }
1167
1168 /*
1169 * for evergreen we need to scan the shader to find the number of GPRs we need to
1170 * reserve for interpolation and system values
1171 *
1172 * we need to know if we are going to emit
1173 * any sample or centroid inputs
1174 * if perspective and linear are required
1175 */
1176 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1177 {
1178 unsigned i;
1179 int num_baryc;
1180 struct tgsi_parse_context parse;
1181
1182 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1183
1184 for (i = 0; i < ctx->info.num_inputs; i++) {
1185 int k;
1186 /* skip position/face/mask/sampleid */
1187 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1188 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1189 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1190 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1191 continue;
1192
1193 k = eg_get_interpolator_index(
1194 ctx->info.input_interpolate[i],
1195 ctx->info.input_interpolate_loc[i]);
1196 if (k >= 0)
1197 ctx->eg_interpolators[k].enabled = TRUE;
1198 }
1199
1200 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1201 return 0;
1202 }
1203
1204 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1205 while (!tgsi_parse_end_of_tokens(&parse)) {
1206 tgsi_parse_token(&parse);
1207
1208 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1209 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1210 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1211 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1212 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1213 {
1214 int interpolate, location, k;
1215
1216 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1217 location = TGSI_INTERPOLATE_LOC_CENTER;
1218 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1219 location = TGSI_INTERPOLATE_LOC_CENTER;
1220 } else {
1221 location = TGSI_INTERPOLATE_LOC_CENTROID;
1222 }
1223
1224 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1225 k = eg_get_interpolator_index(interpolate, location);
1226 if (k >= 0)
1227 ctx->eg_interpolators[k].enabled = true;
1228 }
1229 }
1230 }
1231
1232 tgsi_parse_free(&parse);
1233
1234 /* assign gpr to each interpolator according to priority */
1235 num_baryc = 0;
1236 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1237 if (ctx->eg_interpolators[i].enabled) {
1238 ctx->eg_interpolators[i].ij_index = num_baryc;
1239 num_baryc ++;
1240 }
1241 }
1242
1243 /* XXX PULL MODEL and LINE STIPPLE */
1244
1245 num_baryc = (num_baryc + 1) >> 1;
1246 return allocate_system_value_inputs(ctx, num_baryc);
1247 }
1248
1249 /* sample_id_sel == NULL means fetch for current sample */
1250 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1251 {
1252 struct r600_bytecode_vtx vtx;
1253 int r, t1;
1254
1255 assert(ctx->fixed_pt_position_gpr != -1);
1256
1257 t1 = r600_get_temp(ctx);
1258
1259 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1260 vtx.op = FETCH_OP_VFETCH;
1261 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1262 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1263 if (sample_id == NULL) {
1264 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1265 vtx.src_sel_x = 3;
1266 }
1267 else {
1268 struct r600_bytecode_alu alu;
1269
1270 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1271 alu.op = ALU_OP1_MOV;
1272 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1273 alu.dst.sel = t1;
1274 alu.dst.write = 1;
1275 alu.last = 1;
1276 r = r600_bytecode_add_alu(ctx->bc, &alu);
1277 if (r)
1278 return r;
1279
1280 vtx.src_gpr = t1;
1281 vtx.src_sel_x = 0;
1282 }
1283 vtx.mega_fetch_count = 16;
1284 vtx.dst_gpr = t1;
1285 vtx.dst_sel_x = 0;
1286 vtx.dst_sel_y = 1;
1287 vtx.dst_sel_z = 2;
1288 vtx.dst_sel_w = 3;
1289 vtx.data_format = FMT_32_32_32_32_FLOAT;
1290 vtx.num_format_all = 2;
1291 vtx.format_comp_all = 1;
1292 vtx.use_const_fields = 0;
1293 vtx.offset = 1; // first element is size of buffer
1294 vtx.endian = r600_endian_swap(32);
1295 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1296
1297 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1298 if (r)
1299 return r;
1300
1301 return t1;
1302 }
1303
1304 static void tgsi_src(struct r600_shader_ctx *ctx,
1305 const struct tgsi_full_src_register *tgsi_src,
1306 struct r600_shader_src *r600_src)
1307 {
1308 memset(r600_src, 0, sizeof(*r600_src));
1309 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1310 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1311 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1312 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1313 r600_src->neg = tgsi_src->Register.Negate;
1314 r600_src->abs = tgsi_src->Register.Absolute;
1315
1316 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1317 int index;
1318 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1319 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1320 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1321
1322 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1323 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1324 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1325 return;
1326 }
1327 index = tgsi_src->Register.Index;
1328 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1329 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1330 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1331 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1332 r600_src->swizzle[0] = 2; // Z value
1333 r600_src->swizzle[1] = 2;
1334 r600_src->swizzle[2] = 2;
1335 r600_src->swizzle[3] = 2;
1336 r600_src->sel = ctx->face_gpr;
1337 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1338 r600_src->swizzle[0] = 3; // W value
1339 r600_src->swizzle[1] = 3;
1340 r600_src->swizzle[2] = 3;
1341 r600_src->swizzle[3] = 3;
1342 r600_src->sel = ctx->fixed_pt_position_gpr;
1343 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1344 r600_src->swizzle[0] = 0;
1345 r600_src->swizzle[1] = 1;
1346 r600_src->swizzle[2] = 4;
1347 r600_src->swizzle[3] = 4;
1348 r600_src->sel = load_sample_position(ctx, NULL, -1);
1349 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1350 r600_src->swizzle[0] = 3;
1351 r600_src->swizzle[1] = 3;
1352 r600_src->swizzle[2] = 3;
1353 r600_src->swizzle[3] = 3;
1354 r600_src->sel = 0;
1355 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1356 r600_src->swizzle[0] = 0;
1357 r600_src->swizzle[1] = 0;
1358 r600_src->swizzle[2] = 0;
1359 r600_src->swizzle[3] = 0;
1360 r600_src->sel = 0;
1361 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1362 r600_src->swizzle[0] = 3;
1363 r600_src->swizzle[1] = 3;
1364 r600_src->swizzle[2] = 3;
1365 r600_src->swizzle[3] = 3;
1366 r600_src->sel = 1;
1367 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1368 r600_src->swizzle[0] = 2;
1369 r600_src->swizzle[1] = 2;
1370 r600_src->swizzle[2] = 2;
1371 r600_src->swizzle[3] = 2;
1372 r600_src->sel = 0;
1373 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1374 r600_src->sel = 1;
1375 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1376 r600_src->sel = 3;
1377 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1378 r600_src->sel = 2;
1379 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1380 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1381 r600_src->sel = ctx->tess_input_info;
1382 r600_src->swizzle[0] = 2;
1383 r600_src->swizzle[1] = 2;
1384 r600_src->swizzle[2] = 2;
1385 r600_src->swizzle[3] = 2;
1386 } else {
1387 r600_src->sel = ctx->tess_input_info;
1388 r600_src->swizzle[0] = 3;
1389 r600_src->swizzle[1] = 3;
1390 r600_src->swizzle[2] = 3;
1391 r600_src->swizzle[3] = 3;
1392 }
1393 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1394 r600_src->sel = 0;
1395 r600_src->swizzle[0] = 0;
1396 r600_src->swizzle[1] = 0;
1397 r600_src->swizzle[2] = 0;
1398 r600_src->swizzle[3] = 0;
1399 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1400 r600_src->sel = 0;
1401 r600_src->swizzle[0] = 3;
1402 r600_src->swizzle[1] = 3;
1403 r600_src->swizzle[2] = 3;
1404 r600_src->swizzle[3] = 3;
1405 }
1406 } else {
1407 if (tgsi_src->Register.Indirect)
1408 r600_src->rel = V_SQ_REL_RELATIVE;
1409 r600_src->sel = tgsi_src->Register.Index;
1410 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1411 }
1412 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1413 if (tgsi_src->Register.Dimension) {
1414 r600_src->kc_bank = tgsi_src->Dimension.Index;
1415 if (tgsi_src->Dimension.Indirect) {
1416 r600_src->kc_rel = 1;
1417 }
1418 }
1419 }
1420 }
1421
1422 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1423 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1424 unsigned int dst_reg)
1425 {
1426 struct r600_bytecode_vtx vtx;
1427 unsigned int ar_reg;
1428 int r;
1429
1430 if (offset) {
1431 struct r600_bytecode_alu alu;
1432
1433 memset(&alu, 0, sizeof(alu));
1434
1435 alu.op = ALU_OP2_ADD_INT;
1436 alu.src[0].sel = ctx->bc->ar_reg;
1437 alu.src[0].chan = ar_chan;
1438
1439 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1440 alu.src[1].value = offset;
1441
1442 alu.dst.sel = dst_reg;
1443 alu.dst.chan = ar_chan;
1444 alu.dst.write = 1;
1445 alu.last = 1;
1446
1447 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1448 return r;
1449
1450 ar_reg = dst_reg;
1451 } else {
1452 ar_reg = ctx->bc->ar_reg;
1453 }
1454
1455 memset(&vtx, 0, sizeof(vtx));
1456 vtx.buffer_id = cb_idx;
1457 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1458 vtx.src_gpr = ar_reg;
1459 vtx.src_sel_x = ar_chan;
1460 vtx.mega_fetch_count = 16;
1461 vtx.dst_gpr = dst_reg;
1462 vtx.dst_sel_x = 0; /* SEL_X */
1463 vtx.dst_sel_y = 1; /* SEL_Y */
1464 vtx.dst_sel_z = 2; /* SEL_Z */
1465 vtx.dst_sel_w = 3; /* SEL_W */
1466 vtx.data_format = FMT_32_32_32_32_FLOAT;
1467 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1468 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1469 vtx.endian = r600_endian_swap(32);
1470 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1471
1472 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1473 return r;
1474
1475 return 0;
1476 }
1477
1478 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1479 {
1480 struct r600_bytecode_vtx vtx;
1481 int r;
1482 unsigned index = src->Register.Index;
1483 unsigned vtx_id = src->Dimension.Index;
1484 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1485 int offset_chan = vtx_id % 3;
1486 int t2 = 0;
1487
1488 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1489 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1490
1491 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1492 offset_chan = 3;
1493
1494 if (src->Dimension.Indirect || src->Register.Indirect)
1495 t2 = r600_get_temp(ctx);
1496
1497 if (src->Dimension.Indirect) {
1498 int treg[3];
1499 struct r600_bytecode_alu alu;
1500 int r, i;
1501 unsigned addr_reg;
1502 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1503 if (src->DimIndirect.Index > 0) {
1504 r = single_alu_op2(ctx, ALU_OP1_MOV,
1505 ctx->bc->ar_reg, 0,
1506 addr_reg, 0,
1507 0, 0);
1508 if (r)
1509 return r;
1510 }
1511 /*
1512 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1513 at least this is what fglrx seems to do. */
1514 for (i = 0; i < 3; i++) {
1515 treg[i] = r600_get_temp(ctx);
1516 }
1517 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1518
1519 for (i = 0; i < 3; i++) {
1520 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1521 alu.op = ALU_OP1_MOV;
1522 alu.src[0].sel = ctx->gs_rotated_input[0];
1523 alu.src[0].chan = i == 2 ? 3 : i;
1524 alu.dst.sel = treg[i];
1525 alu.dst.chan = 0;
1526 alu.dst.write = 1;
1527 alu.last = 1;
1528 r = r600_bytecode_add_alu(ctx->bc, &alu);
1529 if (r)
1530 return r;
1531 }
1532 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1533 alu.op = ALU_OP1_MOV;
1534 alu.src[0].sel = treg[0];
1535 alu.src[0].rel = 1;
1536 alu.dst.sel = t2;
1537 alu.dst.write = 1;
1538 alu.last = 1;
1539 r = r600_bytecode_add_alu(ctx->bc, &alu);
1540 if (r)
1541 return r;
1542 offset_reg = t2;
1543 offset_chan = 0;
1544 }
1545
1546 if (src->Register.Indirect) {
1547 int addr_reg;
1548 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1549
1550 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1551
1552 /* pull the value from index_reg */
1553 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1554 t2, 1,
1555 addr_reg, 0,
1556 V_SQ_ALU_SRC_LITERAL, first);
1557 if (r)
1558 return r;
1559 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1560 t2, 0,
1561 t2, 1,
1562 V_SQ_ALU_SRC_LITERAL, 4,
1563 offset_reg, offset_chan);
1564 if (r)
1565 return r;
1566 offset_reg = t2;
1567 offset_chan = 0;
1568 index = src->Register.Index - first;
1569 }
1570
1571 memset(&vtx, 0, sizeof(vtx));
1572 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1573 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1574 vtx.src_gpr = offset_reg;
1575 vtx.src_sel_x = offset_chan;
1576 vtx.offset = index * 16; /*bytes*/
1577 vtx.mega_fetch_count = 16;
1578 vtx.dst_gpr = dst_reg;
1579 vtx.dst_sel_x = 0; /* SEL_X */
1580 vtx.dst_sel_y = 1; /* SEL_Y */
1581 vtx.dst_sel_z = 2; /* SEL_Z */
1582 vtx.dst_sel_w = 3; /* SEL_W */
1583 if (ctx->bc->chip_class >= EVERGREEN) {
1584 vtx.use_const_fields = 1;
1585 } else {
1586 vtx.data_format = FMT_32_32_32_32_FLOAT;
1587 }
1588
1589 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1590 return r;
1591
1592 return 0;
1593 }
1594
1595 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1596 {
1597 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1598 unsigned i;
1599
1600 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1601 struct tgsi_full_src_register *src = &inst->Src[i];
1602
1603 if (src->Register.File == TGSI_FILE_INPUT) {
1604 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1605 /* primitive id is in R0.z */
1606 ctx->src[i].sel = 0;
1607 ctx->src[i].swizzle[0] = 2;
1608 }
1609 }
1610 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1611 int treg = r600_get_temp(ctx);
1612
1613 fetch_gs_input(ctx, src, treg);
1614 ctx->src[i].sel = treg;
1615 ctx->src[i].rel = 0;
1616 }
1617 }
1618 return 0;
1619 }
1620
1621
1622 /* Tessellation shaders pass outputs to the next shader using LDS.
1623 *
1624 * LS outputs = TCS(HS) inputs
1625 * TCS(HS) outputs = TES(DS) inputs
1626 *
1627 * The LDS layout is:
1628 * - TCS inputs for patch 0
1629 * - TCS inputs for patch 1
1630 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1631 * - ...
1632 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1633 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1634 * - TCS outputs for patch 1
1635 * - Per-patch TCS outputs for patch 1
1636 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1637 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1638 * - ...
1639 *
1640 * All three shaders VS(LS), TCS, TES share the same LDS space.
1641 */
1642 /* this will return with the dw address in temp_reg.x */
1643 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1644 const struct tgsi_full_dst_register *dst,
1645 const struct tgsi_full_src_register *src,
1646 int stride_bytes_reg, int stride_bytes_chan)
1647 {
1648 struct tgsi_full_dst_register reg;
1649 ubyte *name, *index, *array_first;
1650 int r;
1651 int param;
1652 struct tgsi_shader_info *info = &ctx->info;
1653 /* Set the register description. The address computation is the same
1654 * for sources and destinations. */
1655 if (src) {
1656 reg.Register.File = src->Register.File;
1657 reg.Register.Index = src->Register.Index;
1658 reg.Register.Indirect = src->Register.Indirect;
1659 reg.Register.Dimension = src->Register.Dimension;
1660 reg.Indirect = src->Indirect;
1661 reg.Dimension = src->Dimension;
1662 reg.DimIndirect = src->DimIndirect;
1663 } else
1664 reg = *dst;
1665
1666 /* If the register is 2-dimensional (e.g. an array of vertices
1667 * in a primitive), calculate the base address of the vertex. */
1668 if (reg.Register.Dimension) {
1669 int sel, chan;
1670 if (reg.Dimension.Indirect) {
1671 unsigned addr_reg;
1672 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1673
1674 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1675 /* pull the value from index_reg */
1676 sel = addr_reg;
1677 chan = 0;
1678 } else {
1679 sel = V_SQ_ALU_SRC_LITERAL;
1680 chan = reg.Dimension.Index;
1681 }
1682
1683 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1684 temp_reg, 0,
1685 stride_bytes_reg, stride_bytes_chan,
1686 sel, chan,
1687 temp_reg, 0);
1688 if (r)
1689 return r;
1690 }
1691
1692 if (reg.Register.File == TGSI_FILE_INPUT) {
1693 name = info->input_semantic_name;
1694 index = info->input_semantic_index;
1695 array_first = info->input_array_first;
1696 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1697 name = info->output_semantic_name;
1698 index = info->output_semantic_index;
1699 array_first = info->output_array_first;
1700 } else {
1701 assert(0);
1702 return -1;
1703 }
1704 if (reg.Register.Indirect) {
1705 int addr_reg;
1706 int first;
1707 /* Add the relative address of the element. */
1708 if (reg.Indirect.ArrayID)
1709 first = array_first[reg.Indirect.ArrayID];
1710 else
1711 first = reg.Register.Index;
1712
1713 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1714
1715 /* pull the value from index_reg */
1716 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1717 temp_reg, 0,
1718 V_SQ_ALU_SRC_LITERAL, 16,
1719 addr_reg, 0,
1720 temp_reg, 0);
1721 if (r)
1722 return r;
1723
1724 param = r600_get_lds_unique_index(name[first],
1725 index[first]);
1726
1727 } else {
1728 param = r600_get_lds_unique_index(name[reg.Register.Index],
1729 index[reg.Register.Index]);
1730 }
1731
1732 /* add to base_addr - passed in temp_reg.x */
1733 if (param) {
1734 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1735 temp_reg, 0,
1736 temp_reg, 0,
1737 V_SQ_ALU_SRC_LITERAL, param * 16);
1738 if (r)
1739 return r;
1740
1741 }
1742 return 0;
1743 }
1744
1745 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1746 unsigned dst_reg)
1747 {
1748 struct r600_bytecode_alu alu;
1749 int r, i;
1750
1751 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1752 ctx->bc->force_add_cf = 1;
1753 for (i = 1; i < 4; i++) {
1754 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1755 temp_reg, i,
1756 temp_reg, 0,
1757 V_SQ_ALU_SRC_LITERAL, 4 * i);
1758 if (r)
1759 return r;
1760 }
1761 for (i = 0; i < 4; i++) {
1762 /* emit an LDS_READ_RET */
1763 memset(&alu, 0, sizeof(alu));
1764 alu.op = LDS_OP1_LDS_READ_RET;
1765 alu.src[0].sel = temp_reg;
1766 alu.src[0].chan = i;
1767 alu.src[1].sel = V_SQ_ALU_SRC_0;
1768 alu.src[2].sel = V_SQ_ALU_SRC_0;
1769 alu.dst.chan = 0;
1770 alu.is_lds_idx_op = true;
1771 alu.last = 1;
1772 r = r600_bytecode_add_alu(ctx->bc, &alu);
1773 if (r)
1774 return r;
1775 }
1776 for (i = 0; i < 4; i++) {
1777 /* then read from LDS_OQ_A_POP */
1778 memset(&alu, 0, sizeof(alu));
1779
1780 alu.op = ALU_OP1_MOV;
1781 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1782 alu.src[0].chan = 0;
1783 alu.dst.sel = dst_reg;
1784 alu.dst.chan = i;
1785 alu.dst.write = 1;
1786 alu.last = 1;
1787 r = r600_bytecode_add_alu(ctx->bc, &alu);
1788 if (r)
1789 return r;
1790 }
1791 return 0;
1792 }
1793
1794 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1795 {
1796 int r;
1797 unsigned temp_reg = r600_get_temp(ctx);
1798
1799 r = get_lds_offset0(ctx, 2, temp_reg,
1800 src->Register.Dimension ? false : true);
1801 if (r)
1802 return r;
1803
1804 /* the base address is now in temp.x */
1805 r = r600_get_byte_address(ctx, temp_reg,
1806 NULL, src, ctx->tess_output_info, 1);
1807 if (r)
1808 return r;
1809
1810 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1811 if (r)
1812 return r;
1813 return 0;
1814 }
1815
1816 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1817 {
1818 int r;
1819 unsigned temp_reg = r600_get_temp(ctx);
1820
1821 /* t.x = ips * r0.y */
1822 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1823 temp_reg, 0,
1824 ctx->tess_input_info, 0,
1825 0, 1);
1826
1827 if (r)
1828 return r;
1829
1830 /* the base address is now in temp.x */
1831 r = r600_get_byte_address(ctx, temp_reg,
1832 NULL, src, ctx->tess_input_info, 1);
1833 if (r)
1834 return r;
1835
1836 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1837 if (r)
1838 return r;
1839 return 0;
1840 }
1841
1842 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1843 {
1844 int r;
1845 unsigned temp_reg = r600_get_temp(ctx);
1846
1847 r = get_lds_offset0(ctx, 1, temp_reg,
1848 src->Register.Dimension ? false : true);
1849 if (r)
1850 return r;
1851 /* the base address is now in temp.x */
1852 r = r600_get_byte_address(ctx, temp_reg,
1853 NULL, src,
1854 ctx->tess_output_info, 1);
1855 if (r)
1856 return r;
1857
1858 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1859 if (r)
1860 return r;
1861 return 0;
1862 }
1863
1864 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1865 {
1866 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1867 unsigned i;
1868
1869 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1870 struct tgsi_full_src_register *src = &inst->Src[i];
1871
1872 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1873 int treg = r600_get_temp(ctx);
1874 fetch_tes_input(ctx, src, treg);
1875 ctx->src[i].sel = treg;
1876 ctx->src[i].rel = 0;
1877 }
1878 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1879 int treg = r600_get_temp(ctx);
1880 fetch_tcs_input(ctx, src, treg);
1881 ctx->src[i].sel = treg;
1882 ctx->src[i].rel = 0;
1883 }
1884 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1885 int treg = r600_get_temp(ctx);
1886 fetch_tcs_output(ctx, src, treg);
1887 ctx->src[i].sel = treg;
1888 ctx->src[i].rel = 0;
1889 }
1890 }
1891 return 0;
1892 }
1893
1894 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1895 {
1896 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1897 struct r600_bytecode_alu alu;
1898 int i, j, k, nconst, r;
1899
1900 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1901 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1902 nconst++;
1903 }
1904 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1905 }
1906 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1907 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1908 continue;
1909 }
1910
1911 if (ctx->src[i].rel) {
1912 int chan = inst->Src[i].Indirect.Swizzle;
1913 int treg = r600_get_temp(ctx);
1914 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1915 return r;
1916
1917 ctx->src[i].kc_bank = 0;
1918 ctx->src[i].kc_rel = 0;
1919 ctx->src[i].sel = treg;
1920 ctx->src[i].rel = 0;
1921 j--;
1922 } else if (j > 0) {
1923 int treg = r600_get_temp(ctx);
1924 for (k = 0; k < 4; k++) {
1925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1926 alu.op = ALU_OP1_MOV;
1927 alu.src[0].sel = ctx->src[i].sel;
1928 alu.src[0].chan = k;
1929 alu.src[0].rel = ctx->src[i].rel;
1930 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1931 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1932 alu.dst.sel = treg;
1933 alu.dst.chan = k;
1934 alu.dst.write = 1;
1935 if (k == 3)
1936 alu.last = 1;
1937 r = r600_bytecode_add_alu(ctx->bc, &alu);
1938 if (r)
1939 return r;
1940 }
1941 ctx->src[i].sel = treg;
1942 ctx->src[i].rel =0;
1943 j--;
1944 }
1945 }
1946 return 0;
1947 }
1948
1949 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1950 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1951 {
1952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1953 struct r600_bytecode_alu alu;
1954 int i, j, k, nliteral, r;
1955
1956 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1957 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1958 nliteral++;
1959 }
1960 }
1961 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1962 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1963 int treg = r600_get_temp(ctx);
1964 for (k = 0; k < 4; k++) {
1965 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1966 alu.op = ALU_OP1_MOV;
1967 alu.src[0].sel = ctx->src[i].sel;
1968 alu.src[0].chan = k;
1969 alu.src[0].value = ctx->src[i].value[k];
1970 alu.dst.sel = treg;
1971 alu.dst.chan = k;
1972 alu.dst.write = 1;
1973 if (k == 3)
1974 alu.last = 1;
1975 r = r600_bytecode_add_alu(ctx->bc, &alu);
1976 if (r)
1977 return r;
1978 }
1979 ctx->src[i].sel = treg;
1980 j--;
1981 }
1982 }
1983 return 0;
1984 }
1985
1986 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1987 {
1988 int i, r, count = ctx->shader->ninput;
1989
1990 for (i = 0; i < count; i++) {
1991 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1992 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1993 if (r)
1994 return r;
1995 }
1996 }
1997 return 0;
1998 }
1999
2000 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2001 int stream, unsigned *stream_item_size)
2002 {
2003 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2004 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2005 int i, j, r;
2006
2007 /* Sanity checking. */
2008 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2009 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2010 r = -EINVAL;
2011 goto out_err;
2012 }
2013 for (i = 0; i < so->num_outputs; i++) {
2014 if (so->output[i].output_buffer >= 4) {
2015 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2016 so->output[i].output_buffer);
2017 r = -EINVAL;
2018 goto out_err;
2019 }
2020 }
2021
2022 /* Initialize locations where the outputs are stored. */
2023 for (i = 0; i < so->num_outputs; i++) {
2024
2025 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2026 start_comp[i] = so->output[i].start_component;
2027 /* Lower outputs with dst_offset < start_component.
2028 *
2029 * We can only output 4D vectors with a write mask, e.g. we can
2030 * only output the W component at offset 3, etc. If we want
2031 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2032 * to move it to X and output X. */
2033 if (so->output[i].dst_offset < so->output[i].start_component) {
2034 unsigned tmp = r600_get_temp(ctx);
2035
2036 for (j = 0; j < so->output[i].num_components; j++) {
2037 struct r600_bytecode_alu alu;
2038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2039 alu.op = ALU_OP1_MOV;
2040 alu.src[0].sel = so_gpr[i];
2041 alu.src[0].chan = so->output[i].start_component + j;
2042
2043 alu.dst.sel = tmp;
2044 alu.dst.chan = j;
2045 alu.dst.write = 1;
2046 if (j == so->output[i].num_components - 1)
2047 alu.last = 1;
2048 r = r600_bytecode_add_alu(ctx->bc, &alu);
2049 if (r)
2050 return r;
2051 }
2052 start_comp[i] = 0;
2053 so_gpr[i] = tmp;
2054 }
2055 }
2056
2057 /* Write outputs to buffers. */
2058 for (i = 0; i < so->num_outputs; i++) {
2059 struct r600_bytecode_output output;
2060
2061 if (stream != -1 && stream != so->output[i].output_buffer)
2062 continue;
2063
2064 memset(&output, 0, sizeof(struct r600_bytecode_output));
2065 output.gpr = so_gpr[i];
2066 output.elem_size = so->output[i].num_components - 1;
2067 if (output.elem_size == 2)
2068 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2069 output.array_base = so->output[i].dst_offset - start_comp[i];
2070 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2071 output.burst_count = 1;
2072 /* array_size is an upper limit for the burst_count
2073 * with MEM_STREAM instructions */
2074 output.array_size = 0xFFF;
2075 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2076
2077 if (ctx->bc->chip_class >= EVERGREEN) {
2078 switch (so->output[i].output_buffer) {
2079 case 0:
2080 output.op = CF_OP_MEM_STREAM0_BUF0;
2081 break;
2082 case 1:
2083 output.op = CF_OP_MEM_STREAM0_BUF1;
2084 break;
2085 case 2:
2086 output.op = CF_OP_MEM_STREAM0_BUF2;
2087 break;
2088 case 3:
2089 output.op = CF_OP_MEM_STREAM0_BUF3;
2090 break;
2091 }
2092 output.op += so->output[i].stream * 4;
2093 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2094 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2095 } else {
2096 switch (so->output[i].output_buffer) {
2097 case 0:
2098 output.op = CF_OP_MEM_STREAM0;
2099 break;
2100 case 1:
2101 output.op = CF_OP_MEM_STREAM1;
2102 break;
2103 case 2:
2104 output.op = CF_OP_MEM_STREAM2;
2105 break;
2106 case 3:
2107 output.op = CF_OP_MEM_STREAM3;
2108 break;
2109 }
2110 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2111 }
2112 r = r600_bytecode_add_output(ctx->bc, &output);
2113 if (r)
2114 goto out_err;
2115 }
2116 return 0;
2117 out_err:
2118 return r;
2119 }
2120
2121 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2122 {
2123 struct r600_bytecode_alu alu;
2124 unsigned reg;
2125
2126 if (!ctx->shader->vs_out_edgeflag)
2127 return;
2128
2129 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2130
2131 /* clamp(x, 0, 1) */
2132 memset(&alu, 0, sizeof(alu));
2133 alu.op = ALU_OP1_MOV;
2134 alu.src[0].sel = reg;
2135 alu.dst.sel = reg;
2136 alu.dst.write = 1;
2137 alu.dst.clamp = 1;
2138 alu.last = 1;
2139 r600_bytecode_add_alu(ctx->bc, &alu);
2140
2141 memset(&alu, 0, sizeof(alu));
2142 alu.op = ALU_OP1_FLT_TO_INT;
2143 alu.src[0].sel = reg;
2144 alu.dst.sel = reg;
2145 alu.dst.write = 1;
2146 alu.last = 1;
2147 r600_bytecode_add_alu(ctx->bc, &alu);
2148 }
2149
2150 static int generate_gs_copy_shader(struct r600_context *rctx,
2151 struct r600_pipe_shader *gs,
2152 struct pipe_stream_output_info *so)
2153 {
2154 struct r600_shader_ctx ctx = {};
2155 struct r600_shader *gs_shader = &gs->shader;
2156 struct r600_pipe_shader *cshader;
2157 int ocnt = gs_shader->noutput;
2158 struct r600_bytecode_alu alu;
2159 struct r600_bytecode_vtx vtx;
2160 struct r600_bytecode_output output;
2161 struct r600_bytecode_cf *cf_jump, *cf_pop,
2162 *last_exp_pos = NULL, *last_exp_param = NULL;
2163 int i, j, next_clip_pos = 61, next_param = 0;
2164 int ring;
2165 bool only_ring_0 = true;
2166 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2167 if (!cshader)
2168 return 0;
2169
2170 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2171 sizeof(struct r600_shader_io));
2172
2173 cshader->shader.noutput = ocnt;
2174
2175 ctx.shader = &cshader->shader;
2176 ctx.bc = &ctx.shader->bc;
2177 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2178
2179 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2180 rctx->screen->has_compressed_msaa_texturing);
2181
2182 ctx.bc->isa = rctx->isa;
2183
2184 cf_jump = NULL;
2185 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2186
2187 /* R0.x = R0.x & 0x3fffffff */
2188 memset(&alu, 0, sizeof(alu));
2189 alu.op = ALU_OP2_AND_INT;
2190 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2191 alu.src[1].value = 0x3fffffff;
2192 alu.dst.write = 1;
2193 r600_bytecode_add_alu(ctx.bc, &alu);
2194
2195 /* R0.y = R0.x >> 30 */
2196 memset(&alu, 0, sizeof(alu));
2197 alu.op = ALU_OP2_LSHR_INT;
2198 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2199 alu.src[1].value = 0x1e;
2200 alu.dst.chan = 1;
2201 alu.dst.write = 1;
2202 alu.last = 1;
2203 r600_bytecode_add_alu(ctx.bc, &alu);
2204
2205 /* fetch vertex data from GSVS ring */
2206 for (i = 0; i < ocnt; ++i) {
2207 struct r600_shader_io *out = &ctx.shader->output[i];
2208
2209 out->gpr = i + 1;
2210 out->ring_offset = i * 16;
2211
2212 memset(&vtx, 0, sizeof(vtx));
2213 vtx.op = FETCH_OP_VFETCH;
2214 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2215 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2216 vtx.mega_fetch_count = 16;
2217 vtx.offset = out->ring_offset;
2218 vtx.dst_gpr = out->gpr;
2219 vtx.src_gpr = 0;
2220 vtx.dst_sel_x = 0;
2221 vtx.dst_sel_y = 1;
2222 vtx.dst_sel_z = 2;
2223 vtx.dst_sel_w = 3;
2224 if (rctx->b.chip_class >= EVERGREEN) {
2225 vtx.use_const_fields = 1;
2226 } else {
2227 vtx.data_format = FMT_32_32_32_32_FLOAT;
2228 }
2229
2230 r600_bytecode_add_vtx(ctx.bc, &vtx);
2231 }
2232 ctx.temp_reg = i + 1;
2233 for (ring = 3; ring >= 0; --ring) {
2234 bool enabled = false;
2235 for (i = 0; i < so->num_outputs; i++) {
2236 if (so->output[i].stream == ring) {
2237 enabled = true;
2238 if (ring > 0)
2239 only_ring_0 = false;
2240 break;
2241 }
2242 }
2243 if (ring != 0 && !enabled) {
2244 cshader->shader.ring_item_sizes[ring] = 0;
2245 continue;
2246 }
2247
2248 if (cf_jump) {
2249 // Patch up jump label
2250 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2251 cf_pop = ctx.bc->cf_last;
2252
2253 cf_jump->cf_addr = cf_pop->id + 2;
2254 cf_jump->pop_count = 1;
2255 cf_pop->cf_addr = cf_pop->id + 2;
2256 cf_pop->pop_count = 1;
2257 }
2258
2259 /* PRED_SETE_INT __, R0.y, ring */
2260 memset(&alu, 0, sizeof(alu));
2261 alu.op = ALU_OP2_PRED_SETE_INT;
2262 alu.src[0].chan = 1;
2263 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2264 alu.src[1].value = ring;
2265 alu.execute_mask = 1;
2266 alu.update_pred = 1;
2267 alu.last = 1;
2268 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2269
2270 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2271 cf_jump = ctx.bc->cf_last;
2272
2273 if (enabled)
2274 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2275 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2276 }
2277
2278 /* bc adds nops - copy it */
2279 if (ctx.bc->chip_class == R600) {
2280 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2281 alu.op = ALU_OP0_NOP;
2282 alu.last = 1;
2283 r600_bytecode_add_alu(ctx.bc, &alu);
2284
2285 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2286 }
2287
2288 /* export vertex data */
2289 /* XXX factor out common code with r600_shader_from_tgsi ? */
2290 for (i = 0; i < ocnt; ++i) {
2291 struct r600_shader_io *out = &ctx.shader->output[i];
2292 bool instream0 = true;
2293 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2294 continue;
2295
2296 for (j = 0; j < so->num_outputs; j++) {
2297 if (so->output[j].register_index == i) {
2298 if (so->output[j].stream == 0)
2299 break;
2300 if (so->output[j].stream > 0)
2301 instream0 = false;
2302 }
2303 }
2304 if (!instream0)
2305 continue;
2306 memset(&output, 0, sizeof(output));
2307 output.gpr = out->gpr;
2308 output.elem_size = 3;
2309 output.swizzle_x = 0;
2310 output.swizzle_y = 1;
2311 output.swizzle_z = 2;
2312 output.swizzle_w = 3;
2313 output.burst_count = 1;
2314 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2315 output.op = CF_OP_EXPORT;
2316 switch (out->name) {
2317 case TGSI_SEMANTIC_POSITION:
2318 output.array_base = 60;
2319 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2320 break;
2321
2322 case TGSI_SEMANTIC_PSIZE:
2323 output.array_base = 61;
2324 if (next_clip_pos == 61)
2325 next_clip_pos = 62;
2326 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2327 output.swizzle_y = 7;
2328 output.swizzle_z = 7;
2329 output.swizzle_w = 7;
2330 ctx.shader->vs_out_misc_write = 1;
2331 ctx.shader->vs_out_point_size = 1;
2332 break;
2333 case TGSI_SEMANTIC_LAYER:
2334 if (out->spi_sid) {
2335 /* duplicate it as PARAM to pass to the pixel shader */
2336 output.array_base = next_param++;
2337 r600_bytecode_add_output(ctx.bc, &output);
2338 last_exp_param = ctx.bc->cf_last;
2339 }
2340 output.array_base = 61;
2341 if (next_clip_pos == 61)
2342 next_clip_pos = 62;
2343 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2344 output.swizzle_x = 7;
2345 output.swizzle_y = 7;
2346 output.swizzle_z = 0;
2347 output.swizzle_w = 7;
2348 ctx.shader->vs_out_misc_write = 1;
2349 ctx.shader->vs_out_layer = 1;
2350 break;
2351 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2352 if (out->spi_sid) {
2353 /* duplicate it as PARAM to pass to the pixel shader */
2354 output.array_base = next_param++;
2355 r600_bytecode_add_output(ctx.bc, &output);
2356 last_exp_param = ctx.bc->cf_last;
2357 }
2358 output.array_base = 61;
2359 if (next_clip_pos == 61)
2360 next_clip_pos = 62;
2361 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2362 ctx.shader->vs_out_misc_write = 1;
2363 ctx.shader->vs_out_viewport = 1;
2364 output.swizzle_x = 7;
2365 output.swizzle_y = 7;
2366 output.swizzle_z = 7;
2367 output.swizzle_w = 0;
2368 break;
2369 case TGSI_SEMANTIC_CLIPDIST:
2370 /* spi_sid is 0 for clipdistance outputs that were generated
2371 * for clipvertex - we don't need to pass them to PS */
2372 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2373 if (out->spi_sid) {
2374 /* duplicate it as PARAM to pass to the pixel shader */
2375 output.array_base = next_param++;
2376 r600_bytecode_add_output(ctx.bc, &output);
2377 last_exp_param = ctx.bc->cf_last;
2378 }
2379 output.array_base = next_clip_pos++;
2380 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2381 break;
2382 case TGSI_SEMANTIC_FOG:
2383 output.swizzle_y = 4; /* 0 */
2384 output.swizzle_z = 4; /* 0 */
2385 output.swizzle_w = 5; /* 1 */
2386 break;
2387 default:
2388 output.array_base = next_param++;
2389 break;
2390 }
2391 r600_bytecode_add_output(ctx.bc, &output);
2392 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2393 last_exp_param = ctx.bc->cf_last;
2394 else
2395 last_exp_pos = ctx.bc->cf_last;
2396 }
2397
2398 if (!last_exp_pos) {
2399 memset(&output, 0, sizeof(output));
2400 output.gpr = 0;
2401 output.elem_size = 3;
2402 output.swizzle_x = 7;
2403 output.swizzle_y = 7;
2404 output.swizzle_z = 7;
2405 output.swizzle_w = 7;
2406 output.burst_count = 1;
2407 output.type = 2;
2408 output.op = CF_OP_EXPORT;
2409 output.array_base = 60;
2410 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2411 r600_bytecode_add_output(ctx.bc, &output);
2412 last_exp_pos = ctx.bc->cf_last;
2413 }
2414
2415 if (!last_exp_param) {
2416 memset(&output, 0, sizeof(output));
2417 output.gpr = 0;
2418 output.elem_size = 3;
2419 output.swizzle_x = 7;
2420 output.swizzle_y = 7;
2421 output.swizzle_z = 7;
2422 output.swizzle_w = 7;
2423 output.burst_count = 1;
2424 output.type = 2;
2425 output.op = CF_OP_EXPORT;
2426 output.array_base = next_param++;
2427 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2428 r600_bytecode_add_output(ctx.bc, &output);
2429 last_exp_param = ctx.bc->cf_last;
2430 }
2431
2432 last_exp_pos->op = CF_OP_EXPORT_DONE;
2433 last_exp_param->op = CF_OP_EXPORT_DONE;
2434
2435 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2436 cf_pop = ctx.bc->cf_last;
2437
2438 cf_jump->cf_addr = cf_pop->id + 2;
2439 cf_jump->pop_count = 1;
2440 cf_pop->cf_addr = cf_pop->id + 2;
2441 cf_pop->pop_count = 1;
2442
2443 if (ctx.bc->chip_class == CAYMAN)
2444 cm_bytecode_add_cf_end(ctx.bc);
2445 else {
2446 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2447 ctx.bc->cf_last->end_of_program = 1;
2448 }
2449
2450 gs->gs_copy_shader = cshader;
2451 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2452
2453 ctx.bc->nstack = 1;
2454
2455 return r600_bytecode_build(ctx.bc);
2456 }
2457
2458 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2459 {
2460 if (ind) {
2461 struct r600_bytecode_alu alu;
2462 int r;
2463
2464 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2465 alu.op = ALU_OP2_ADD_INT;
2466 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2467 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2468 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2469 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2470 alu.dst.write = 1;
2471 alu.last = 1;
2472 r = r600_bytecode_add_alu(ctx->bc, &alu);
2473 if (r)
2474 return r;
2475 }
2476 return 0;
2477 }
2478
2479 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2480 {
2481 struct r600_bytecode_output output;
2482 int i, k, ring_offset;
2483 int effective_stream = stream == -1 ? 0 : stream;
2484 int idx = 0;
2485
2486 for (i = 0; i < ctx->shader->noutput; i++) {
2487 if (ctx->gs_for_vs) {
2488 /* for ES we need to lookup corresponding ring offset expected by GS
2489 * (map this output to GS input by name and sid) */
2490 /* FIXME precompute offsets */
2491 ring_offset = -1;
2492 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2493 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2494 struct r600_shader_io *out = &ctx->shader->output[i];
2495 if (in->name == out->name && in->sid == out->sid)
2496 ring_offset = in->ring_offset;
2497 }
2498
2499 if (ring_offset == -1)
2500 continue;
2501 } else {
2502 ring_offset = idx * 16;
2503 idx++;
2504 }
2505
2506 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2507 continue;
2508 /* next_ring_offset after parsing input decls contains total size of
2509 * single vertex data, gs_next_vertex - current vertex index */
2510 if (!ind)
2511 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2512
2513 memset(&output, 0, sizeof(struct r600_bytecode_output));
2514 output.gpr = ctx->shader->output[i].gpr;
2515 output.elem_size = 3;
2516 output.comp_mask = 0xF;
2517 output.burst_count = 1;
2518
2519 if (ind)
2520 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2521 else
2522 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2523
2524 switch (stream) {
2525 default:
2526 case 0:
2527 output.op = CF_OP_MEM_RING; break;
2528 case 1:
2529 output.op = CF_OP_MEM_RING1; break;
2530 case 2:
2531 output.op = CF_OP_MEM_RING2; break;
2532 case 3:
2533 output.op = CF_OP_MEM_RING3; break;
2534 }
2535
2536 if (ind) {
2537 output.array_base = ring_offset >> 2; /* in dwords */
2538 output.array_size = 0xfff;
2539 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2540 } else
2541 output.array_base = ring_offset >> 2; /* in dwords */
2542 r600_bytecode_add_output(ctx->bc, &output);
2543 }
2544
2545 ++ctx->gs_next_vertex;
2546 return 0;
2547 }
2548
2549
2550 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2551 {
2552 int r;
2553 struct r600_bytecode_vtx vtx;
2554 int temp_val = ctx->temp_reg;
2555 /* need to store the TCS output somewhere */
2556 r = single_alu_op2(ctx, ALU_OP1_MOV,
2557 temp_val, 0,
2558 V_SQ_ALU_SRC_LITERAL, 0,
2559 0, 0);
2560 if (r)
2561 return r;
2562
2563 /* used by VS/TCS */
2564 if (ctx->tess_input_info) {
2565 /* fetch tcs input values into resv space */
2566 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2567 vtx.op = FETCH_OP_VFETCH;
2568 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2569 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2570 vtx.mega_fetch_count = 16;
2571 vtx.data_format = FMT_32_32_32_32;
2572 vtx.num_format_all = 2;
2573 vtx.format_comp_all = 1;
2574 vtx.use_const_fields = 0;
2575 vtx.endian = r600_endian_swap(32);
2576 vtx.srf_mode_all = 1;
2577 vtx.offset = 0;
2578 vtx.dst_gpr = ctx->tess_input_info;
2579 vtx.dst_sel_x = 0;
2580 vtx.dst_sel_y = 1;
2581 vtx.dst_sel_z = 2;
2582 vtx.dst_sel_w = 3;
2583 vtx.src_gpr = temp_val;
2584 vtx.src_sel_x = 0;
2585
2586 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2587 if (r)
2588 return r;
2589 }
2590
2591 /* used by TCS/TES */
2592 if (ctx->tess_output_info) {
2593 /* fetch tcs output values into resv space */
2594 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2595 vtx.op = FETCH_OP_VFETCH;
2596 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2597 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2598 vtx.mega_fetch_count = 16;
2599 vtx.data_format = FMT_32_32_32_32;
2600 vtx.num_format_all = 2;
2601 vtx.format_comp_all = 1;
2602 vtx.use_const_fields = 0;
2603 vtx.endian = r600_endian_swap(32);
2604 vtx.srf_mode_all = 1;
2605 vtx.offset = 16;
2606 vtx.dst_gpr = ctx->tess_output_info;
2607 vtx.dst_sel_x = 0;
2608 vtx.dst_sel_y = 1;
2609 vtx.dst_sel_z = 2;
2610 vtx.dst_sel_w = 3;
2611 vtx.src_gpr = temp_val;
2612 vtx.src_sel_x = 0;
2613
2614 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2615 if (r)
2616 return r;
2617 }
2618 return 0;
2619 }
2620
2621 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2622 {
2623 int i, j, r;
2624 int temp_reg;
2625
2626 /* fetch tcs input values into input_vals */
2627 ctx->tess_input_info = r600_get_temp(ctx);
2628 ctx->tess_output_info = 0;
2629 r = r600_fetch_tess_io_info(ctx);
2630 if (r)
2631 return r;
2632
2633 temp_reg = r600_get_temp(ctx);
2634 /* dst reg contains LDS address stride * idx */
2635 /* MUL vertexID, vertex_dw_stride */
2636 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2637 temp_reg, 0,
2638 ctx->tess_input_info, 1,
2639 0, 1); /* rel id in r0.y? */
2640 if (r)
2641 return r;
2642
2643 for (i = 0; i < ctx->shader->noutput; i++) {
2644 struct r600_bytecode_alu alu;
2645 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2646
2647 if (param) {
2648 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2649 temp_reg, 1,
2650 temp_reg, 0,
2651 V_SQ_ALU_SRC_LITERAL, param * 16);
2652 if (r)
2653 return r;
2654 }
2655
2656 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2657 temp_reg, 2,
2658 temp_reg, param ? 1 : 0,
2659 V_SQ_ALU_SRC_LITERAL, 8);
2660 if (r)
2661 return r;
2662
2663
2664 for (j = 0; j < 2; j++) {
2665 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2667 alu.op = LDS_OP3_LDS_WRITE_REL;
2668 alu.src[0].sel = temp_reg;
2669 alu.src[0].chan = chan;
2670 alu.src[1].sel = ctx->shader->output[i].gpr;
2671 alu.src[1].chan = j * 2;
2672 alu.src[2].sel = ctx->shader->output[i].gpr;
2673 alu.src[2].chan = (j * 2) + 1;
2674 alu.last = 1;
2675 alu.dst.chan = 0;
2676 alu.lds_idx = 1;
2677 alu.is_lds_idx_op = true;
2678 r = r600_bytecode_add_alu(ctx->bc, &alu);
2679 if (r)
2680 return r;
2681 }
2682 }
2683 return 0;
2684 }
2685
2686 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2687 {
2688 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2689 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2690 int i, r, lasti;
2691 int temp_reg = r600_get_temp(ctx);
2692 struct r600_bytecode_alu alu;
2693 unsigned write_mask = dst->Register.WriteMask;
2694
2695 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2696 return 0;
2697
2698 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2699 if (r)
2700 return r;
2701
2702 /* the base address is now in temp.x */
2703 r = r600_get_byte_address(ctx, temp_reg,
2704 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2705 if (r)
2706 return r;
2707
2708 /* LDS write */
2709 lasti = tgsi_last_instruction(write_mask);
2710 for (i = 1; i <= lasti; i++) {
2711
2712 if (!(write_mask & (1 << i)))
2713 continue;
2714 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2715 temp_reg, i,
2716 temp_reg, 0,
2717 V_SQ_ALU_SRC_LITERAL, 4 * i);
2718 if (r)
2719 return r;
2720 }
2721
2722 for (i = 0; i <= lasti; i++) {
2723 if (!(write_mask & (1 << i)))
2724 continue;
2725
2726 if ((i == 0 && ((write_mask & 3) == 3)) ||
2727 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2728 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2729 alu.op = LDS_OP3_LDS_WRITE_REL;
2730 alu.src[0].sel = temp_reg;
2731 alu.src[0].chan = i;
2732
2733 alu.src[1].sel = dst->Register.Index;
2734 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2735 alu.src[1].chan = i;
2736
2737 alu.src[2].sel = dst->Register.Index;
2738 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2739 alu.src[2].chan = i + 1;
2740 alu.lds_idx = 1;
2741 alu.dst.chan = 0;
2742 alu.last = 1;
2743 alu.is_lds_idx_op = true;
2744 r = r600_bytecode_add_alu(ctx->bc, &alu);
2745 if (r)
2746 return r;
2747 i += 1;
2748 continue;
2749 }
2750 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2751 alu.op = LDS_OP2_LDS_WRITE;
2752 alu.src[0].sel = temp_reg;
2753 alu.src[0].chan = i;
2754
2755 alu.src[1].sel = dst->Register.Index;
2756 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2757 alu.src[1].chan = i;
2758
2759 alu.src[2].sel = V_SQ_ALU_SRC_0;
2760 alu.dst.chan = 0;
2761 alu.last = 1;
2762 alu.is_lds_idx_op = true;
2763 r = r600_bytecode_add_alu(ctx->bc, &alu);
2764 if (r)
2765 return r;
2766 }
2767 return 0;
2768 }
2769
2770 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2771 int output_idx)
2772 {
2773 int param;
2774 unsigned temp_reg = r600_get_temp(ctx);
2775 unsigned name = ctx->shader->output[output_idx].name;
2776 int dreg = ctx->shader->output[output_idx].gpr;
2777 int r;
2778
2779 param = r600_get_lds_unique_index(name, 0);
2780 r = get_lds_offset0(ctx, 1, temp_reg, true);
2781 if (r)
2782 return r;
2783
2784 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2785 temp_reg, 0,
2786 temp_reg, 0,
2787 V_SQ_ALU_SRC_LITERAL, param * 16);
2788 if (r)
2789 return r;
2790
2791 do_lds_fetch_values(ctx, temp_reg, dreg);
2792 return 0;
2793 }
2794
2795 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2796 {
2797 unsigned i;
2798 int stride, outer_comps, inner_comps;
2799 int tessinner_idx = -1, tessouter_idx = -1;
2800 int r;
2801 int temp_reg = r600_get_temp(ctx);
2802 int treg[3] = {-1, -1, -1};
2803 struct r600_bytecode_alu alu;
2804 struct r600_bytecode_cf *cf_jump, *cf_pop;
2805
2806 /* only execute factor emission for invocation 0 */
2807 /* PRED_SETE_INT __, R0.x, 0 */
2808 memset(&alu, 0, sizeof(alu));
2809 alu.op = ALU_OP2_PRED_SETE_INT;
2810 alu.src[0].chan = 2;
2811 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2812 alu.execute_mask = 1;
2813 alu.update_pred = 1;
2814 alu.last = 1;
2815 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2816
2817 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2818 cf_jump = ctx->bc->cf_last;
2819
2820 treg[0] = r600_get_temp(ctx);
2821 switch (ctx->shader->tcs_prim_mode) {
2822 case PIPE_PRIM_LINES:
2823 stride = 8; /* 2 dwords, 1 vec2 store */
2824 outer_comps = 2;
2825 inner_comps = 0;
2826 break;
2827 case PIPE_PRIM_TRIANGLES:
2828 stride = 16; /* 4 dwords, 1 vec4 store */
2829 outer_comps = 3;
2830 inner_comps = 1;
2831 treg[1] = r600_get_temp(ctx);
2832 break;
2833 case PIPE_PRIM_QUADS:
2834 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2835 outer_comps = 4;
2836 inner_comps = 2;
2837 treg[1] = r600_get_temp(ctx);
2838 treg[2] = r600_get_temp(ctx);
2839 break;
2840 default:
2841 assert(0);
2842 return -1;
2843 }
2844
2845 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2846 /* TF_WRITE takes index in R.x, value in R.y */
2847 for (i = 0; i < ctx->shader->noutput; i++) {
2848 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2849 tessinner_idx = i;
2850 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2851 tessouter_idx = i;
2852 }
2853
2854 if (tessouter_idx == -1)
2855 return -1;
2856
2857 if (tessinner_idx == -1 && inner_comps)
2858 return -1;
2859
2860 if (tessouter_idx != -1) {
2861 r = r600_tess_factor_read(ctx, tessouter_idx);
2862 if (r)
2863 return r;
2864 }
2865
2866 if (tessinner_idx != -1) {
2867 r = r600_tess_factor_read(ctx, tessinner_idx);
2868 if (r)
2869 return r;
2870 }
2871
2872 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2873 /* r.x = relpatchid(r0.y) * tf_stride */
2874
2875 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2876 /* add incoming r0.w to it: t.x = t.x + r0.w */
2877 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2878 temp_reg, 0,
2879 0, 1,
2880 V_SQ_ALU_SRC_LITERAL, stride,
2881 0, 3);
2882 if (r)
2883 return r;
2884
2885 for (i = 0; i < outer_comps + inner_comps; i++) {
2886 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2887 int out_comp = i >= outer_comps ? i - outer_comps : i;
2888
2889 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2890 if (out_comp == 1)
2891 out_comp = 0;
2892 else if (out_comp == 0)
2893 out_comp = 1;
2894 }
2895
2896 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2897 treg[i / 2], (2 * (i % 2)),
2898 temp_reg, 0,
2899 V_SQ_ALU_SRC_LITERAL, 4 * i);
2900 if (r)
2901 return r;
2902 r = single_alu_op2(ctx, ALU_OP1_MOV,
2903 treg[i / 2], 1 + (2 * (i%2)),
2904 ctx->shader->output[out_idx].gpr, out_comp,
2905 0, 0);
2906 if (r)
2907 return r;
2908 }
2909 for (i = 0; i < outer_comps + inner_comps; i++) {
2910 struct r600_bytecode_gds gds;
2911
2912 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2913 gds.src_gpr = treg[i / 2];
2914 gds.src_sel_x = 2 * (i % 2);
2915 gds.src_sel_y = 1 + (2 * (i % 2));
2916 gds.src_sel_z = 4;
2917 gds.dst_sel_x = 7;
2918 gds.dst_sel_y = 7;
2919 gds.dst_sel_z = 7;
2920 gds.dst_sel_w = 7;
2921 gds.op = FETCH_OP_TF_WRITE;
2922 r = r600_bytecode_add_gds(ctx->bc, &gds);
2923 if (r)
2924 return r;
2925 }
2926
2927 // Patch up jump label
2928 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2929 cf_pop = ctx->bc->cf_last;
2930
2931 cf_jump->cf_addr = cf_pop->id + 2;
2932 cf_jump->pop_count = 1;
2933 cf_pop->cf_addr = cf_pop->id + 2;
2934 cf_pop->pop_count = 1;
2935
2936 return 0;
2937 }
2938
2939 /*
2940 * We have to work out the thread ID for load and atomic
2941 * operations, which store the returned value to an index
2942 * in an intermediate buffer.
2943 * The index is calculated by taking the thread id,
2944 * calculated from the MBCNT instructions.
2945 * Then the shader engine ID is multiplied by 256,
2946 * and the wave id is added.
2947 * Then the result is multipled by 64 and thread id is
2948 * added.
2949 */
2950 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
2951 {
2952 struct r600_bytecode_alu alu;
2953 int r;
2954
2955 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2956 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
2957 alu.dst.sel = ctx->temp_reg;
2958 alu.dst.chan = 0;
2959 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2960 alu.src[0].value = 0xffffffff;
2961 alu.dst.write = 1;
2962 r = r600_bytecode_add_alu(ctx->bc, &alu);
2963 if (r)
2964 return r;
2965
2966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2967 alu.op = ALU_OP1_MBCNT_32HI_INT;
2968 alu.dst.sel = ctx->temp_reg;
2969 alu.dst.chan = 1;
2970 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2971 alu.src[0].value = 0xffffffff;
2972 alu.dst.write = 1;
2973 r = r600_bytecode_add_alu(ctx->bc, &alu);
2974 if (r)
2975 return r;
2976
2977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2978 alu.op = ALU_OP3_MULADD_UINT24;
2979 alu.dst.sel = ctx->temp_reg;
2980 alu.dst.chan = 2;
2981 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
2982 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2983 alu.src[1].value = 256;
2984 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
2985 alu.dst.write = 1;
2986 alu.is_op3 = 1;
2987 alu.last = 1;
2988 r = r600_bytecode_add_alu(ctx->bc, &alu);
2989 if (r)
2990 return r;
2991
2992 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2993 ctx->thread_id_gpr, 1,
2994 ctx->temp_reg, 2,
2995 V_SQ_ALU_SRC_LITERAL, 0x40,
2996 ctx->temp_reg, 0);
2997 if (r)
2998 return r;
2999 return 0;
3000 }
3001
3002 static int r600_shader_from_tgsi(struct r600_context *rctx,
3003 struct r600_pipe_shader *pipeshader,
3004 union r600_shader_key key)
3005 {
3006 struct r600_screen *rscreen = rctx->screen;
3007 struct r600_shader *shader = &pipeshader->shader;
3008 struct tgsi_token *tokens = pipeshader->selector->tokens;
3009 struct pipe_stream_output_info so = pipeshader->selector->so;
3010 struct tgsi_full_immediate *immediate;
3011 struct r600_shader_ctx ctx;
3012 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3013 unsigned output_done, noutput;
3014 unsigned opcode;
3015 int i, j, k, r = 0;
3016 int next_param_base = 0, next_clip_base;
3017 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3018 bool indirect_gprs;
3019 bool ring_outputs = false;
3020 bool lds_outputs = false;
3021 bool lds_inputs = false;
3022 bool pos_emitted = false;
3023
3024 ctx.bc = &shader->bc;
3025 ctx.shader = shader;
3026 ctx.native_integers = true;
3027
3028 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3029 rscreen->has_compressed_msaa_texturing);
3030 ctx.tokens = tokens;
3031 tgsi_scan_shader(tokens, &ctx.info);
3032 shader->indirect_files = ctx.info.indirect_files;
3033
3034 shader->uses_doubles = ctx.info.uses_doubles;
3035 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3036 shader->nsys_inputs = 0;
3037
3038 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0;
3039 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3040 tgsi_parse_init(&ctx.parse, tokens);
3041 ctx.type = ctx.info.processor;
3042 shader->processor_type = ctx.type;
3043 ctx.bc->type = shader->processor_type;
3044
3045 switch (ctx.type) {
3046 case PIPE_SHADER_VERTEX:
3047 shader->vs_as_gs_a = key.vs.as_gs_a;
3048 shader->vs_as_es = key.vs.as_es;
3049 shader->vs_as_ls = key.vs.as_ls;
3050 shader->atomic_base = key.vs.first_atomic_counter;
3051 if (shader->vs_as_es)
3052 ring_outputs = true;
3053 if (shader->vs_as_ls)
3054 lds_outputs = true;
3055 break;
3056 case PIPE_SHADER_GEOMETRY:
3057 ring_outputs = true;
3058 shader->atomic_base = key.gs.first_atomic_counter;
3059 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3060 break;
3061 case PIPE_SHADER_TESS_CTRL:
3062 shader->tcs_prim_mode = key.tcs.prim_mode;
3063 shader->atomic_base = key.tcs.first_atomic_counter;
3064 lds_outputs = true;
3065 lds_inputs = true;
3066 break;
3067 case PIPE_SHADER_TESS_EVAL:
3068 shader->tes_as_es = key.tes.as_es;
3069 shader->atomic_base = key.tes.first_atomic_counter;
3070 lds_inputs = true;
3071 if (shader->tes_as_es)
3072 ring_outputs = true;
3073 break;
3074 case PIPE_SHADER_FRAGMENT:
3075 shader->two_side = key.ps.color_two_side;
3076 shader->atomic_base = key.ps.first_atomic_counter;
3077 break;
3078 default:
3079 break;
3080 }
3081
3082 if (shader->vs_as_es || shader->tes_as_es) {
3083 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3084 } else {
3085 ctx.gs_for_vs = NULL;
3086 }
3087
3088 ctx.next_ring_offset = 0;
3089 ctx.gs_out_ring_offset = 0;
3090 ctx.gs_next_vertex = 0;
3091 ctx.gs_stream_output_info = &so;
3092
3093 ctx.face_gpr = -1;
3094 ctx.fixed_pt_position_gpr = -1;
3095 ctx.fragcoord_input = -1;
3096 ctx.colors_used = 0;
3097 ctx.clip_vertex_write = 0;
3098
3099 shader->nr_ps_color_exports = 0;
3100 shader->nr_ps_max_color_exports = 0;
3101
3102
3103 /* register allocations */
3104 /* Values [0,127] correspond to GPR[0..127].
3105 * Values [128,159] correspond to constant buffer bank 0
3106 * Values [160,191] correspond to constant buffer bank 1
3107 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3108 * Values [256,287] correspond to constant buffer bank 2 (EG)
3109 * Values [288,319] correspond to constant buffer bank 3 (EG)
3110 * Other special values are shown in the list below.
3111 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3112 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3113 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3114 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3115 * 248 SQ_ALU_SRC_0: special constant 0.0.
3116 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3117 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3118 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3119 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3120 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3121 * 254 SQ_ALU_SRC_PV: previous vector result.
3122 * 255 SQ_ALU_SRC_PS: previous scalar result.
3123 */
3124 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3125 ctx.file_offset[i] = 0;
3126 }
3127
3128 if (ctx.type == PIPE_SHADER_VERTEX) {
3129
3130 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3131 if (ctx.info.num_inputs)
3132 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3133 }
3134 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3135 if (ctx.bc->chip_class >= EVERGREEN)
3136 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3137 else
3138 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3139 }
3140 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3141 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3142 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3143 }
3144 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3145 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3146 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3147 bool add_tesscoord = false, add_tess_inout = false;
3148 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3149 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3150 /* if we have tesscoord save one reg */
3151 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3152 add_tesscoord = true;
3153 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3154 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3155 add_tess_inout = true;
3156 }
3157 if (add_tesscoord || add_tess_inout)
3158 ctx.file_offset[TGSI_FILE_INPUT]++;
3159 if (add_tess_inout)
3160 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3161 }
3162
3163 ctx.file_offset[TGSI_FILE_OUTPUT] =
3164 ctx.file_offset[TGSI_FILE_INPUT] +
3165 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3166 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3167 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3168
3169 /* Outside the GPR range. This will be translated to one of the
3170 * kcache banks later. */
3171 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3172
3173 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3174 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3175 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3176 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3177 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3178
3179 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3180 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3181 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3182 ctx.temp_reg = ctx.bc->ar_reg + 5;
3183 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3184 ctx.tess_input_info = 0;
3185 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3186 ctx.temp_reg = ctx.bc->ar_reg + 4;
3187 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3188 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3189 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3190 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3191 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3192 ctx.temp_reg = ctx.bc->ar_reg + 7;
3193 if (ctx.shader->gs_tri_strip_adj_fix) {
3194 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3195 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3196 ctx.temp_reg += 2;
3197 } else {
3198 ctx.gs_rotated_input[0] = 0;
3199 ctx.gs_rotated_input[1] = 1;
3200 }
3201 } else {
3202 ctx.temp_reg = ctx.bc->ar_reg + 3;
3203 }
3204
3205 if (shader->uses_images && ctx.type == PIPE_SHADER_FRAGMENT) {
3206 ctx.thread_id_gpr = ctx.temp_reg;
3207 ctx.temp_reg++;
3208 } else
3209 ctx.thread_id_gpr = 0;
3210
3211 shader->max_arrays = 0;
3212 shader->num_arrays = 0;
3213 if (indirect_gprs) {
3214
3215 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3216 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3217 ctx.file_offset[TGSI_FILE_OUTPUT] -
3218 ctx.file_offset[TGSI_FILE_INPUT],
3219 0x0F);
3220 }
3221 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3222 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3223 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3224 ctx.file_offset[TGSI_FILE_OUTPUT],
3225 0x0F);
3226 }
3227 }
3228
3229 ctx.nliterals = 0;
3230 ctx.literals = NULL;
3231
3232 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3233 ctx.info.colors_written == 1;
3234 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3235 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3236
3237 if (shader->vs_as_gs_a)
3238 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3239
3240 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3241 r600_fetch_tess_io_info(&ctx);
3242
3243 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3244 tgsi_parse_token(&ctx.parse);
3245 switch (ctx.parse.FullToken.Token.Type) {
3246 case TGSI_TOKEN_TYPE_IMMEDIATE:
3247 immediate = &ctx.parse.FullToken.FullImmediate;
3248 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3249 if(ctx.literals == NULL) {
3250 r = -ENOMEM;
3251 goto out_err;
3252 }
3253 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3254 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3255 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3256 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3257 ctx.nliterals++;
3258 break;
3259 case TGSI_TOKEN_TYPE_DECLARATION:
3260 r = tgsi_declaration(&ctx);
3261 if (r)
3262 goto out_err;
3263 break;
3264 case TGSI_TOKEN_TYPE_INSTRUCTION:
3265 case TGSI_TOKEN_TYPE_PROPERTY:
3266 break;
3267 default:
3268 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3269 r = -EINVAL;
3270 goto out_err;
3271 }
3272 }
3273
3274 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3275 shader->ring_item_sizes[1] = 0;
3276 shader->ring_item_sizes[2] = 0;
3277 shader->ring_item_sizes[3] = 0;
3278
3279 /* Process two side if needed */
3280 if (shader->two_side && ctx.colors_used) {
3281 int i, count = ctx.shader->ninput;
3282 unsigned next_lds_loc = ctx.shader->nlds;
3283
3284 /* additional inputs will be allocated right after the existing inputs,
3285 * we won't need them after the color selection, so we don't need to
3286 * reserve these gprs for the rest of the shader code and to adjust
3287 * output offsets etc. */
3288 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3289 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3290
3291 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3292 if (ctx.face_gpr == -1) {
3293 i = ctx.shader->ninput++;
3294 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3295 ctx.shader->input[i].spi_sid = 0;
3296 ctx.shader->input[i].gpr = gpr++;
3297 ctx.face_gpr = ctx.shader->input[i].gpr;
3298 }
3299
3300 for (i = 0; i < count; i++) {
3301 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3302 int ni = ctx.shader->ninput++;
3303 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3304 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3305 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3306 ctx.shader->input[ni].gpr = gpr++;
3307 // TGSI to LLVM needs to know the lds position of inputs.
3308 // Non LLVM path computes it later (in process_twoside_color)
3309 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3310 ctx.shader->input[i].back_color_input = ni;
3311 if (ctx.bc->chip_class >= EVERGREEN) {
3312 if ((r = evergreen_interp_input(&ctx, ni)))
3313 return r;
3314 }
3315 }
3316 }
3317 }
3318
3319 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3320 shader->nr_ps_max_color_exports = 8;
3321
3322 if (ctx.fragcoord_input >= 0) {
3323 if (ctx.bc->chip_class == CAYMAN) {
3324 for (j = 0 ; j < 4; j++) {
3325 struct r600_bytecode_alu alu;
3326 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3327 alu.op = ALU_OP1_RECIP_IEEE;
3328 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3329 alu.src[0].chan = 3;
3330
3331 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3332 alu.dst.chan = j;
3333 alu.dst.write = (j == 3);
3334 alu.last = 1;
3335 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3336 return r;
3337 }
3338 } else {
3339 struct r600_bytecode_alu alu;
3340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3341 alu.op = ALU_OP1_RECIP_IEEE;
3342 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3343 alu.src[0].chan = 3;
3344
3345 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3346 alu.dst.chan = 3;
3347 alu.dst.write = 1;
3348 alu.last = 1;
3349 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3350 return r;
3351 }
3352 }
3353
3354 if (ctx.thread_id_gpr) {
3355 load_thread_id_gpr(&ctx);
3356 }
3357
3358 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3359 struct r600_bytecode_alu alu;
3360 int r;
3361
3362 /* GS thread with no output workaround - emit a cut at start of GS */
3363 if (ctx.bc->chip_class == R600)
3364 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3365
3366 for (j = 0; j < 4; j++) {
3367 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3368 alu.op = ALU_OP1_MOV;
3369 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3370 alu.src[0].value = 0;
3371 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3372 alu.dst.write = 1;
3373 alu.last = 1;
3374 r = r600_bytecode_add_alu(ctx.bc, &alu);
3375 if (r)
3376 return r;
3377 }
3378
3379 if (ctx.shader->gs_tri_strip_adj_fix) {
3380 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3381 ctx.gs_rotated_input[0], 2,
3382 0, 2,
3383 V_SQ_ALU_SRC_LITERAL, 1);
3384 if (r)
3385 return r;
3386
3387 for (i = 0; i < 6; i++) {
3388 int rotated = (i + 4) % 6;
3389 int offset_reg = i / 3;
3390 int offset_chan = i % 3;
3391 int rotated_offset_reg = rotated / 3;
3392 int rotated_offset_chan = rotated % 3;
3393
3394 if (offset_reg == 0 && offset_chan == 2)
3395 offset_chan = 3;
3396 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3397 rotated_offset_chan = 3;
3398
3399 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3400 ctx.gs_rotated_input[offset_reg], offset_chan,
3401 ctx.gs_rotated_input[0], 2,
3402 offset_reg, offset_chan,
3403 rotated_offset_reg, rotated_offset_chan);
3404 if (r)
3405 return r;
3406 }
3407 }
3408 }
3409
3410 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3411 r600_fetch_tess_io_info(&ctx);
3412
3413 if (shader->two_side && ctx.colors_used) {
3414 if ((r = process_twoside_color_inputs(&ctx)))
3415 return r;
3416 }
3417
3418 tgsi_parse_init(&ctx.parse, tokens);
3419 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3420 tgsi_parse_token(&ctx.parse);
3421 switch (ctx.parse.FullToken.Token.Type) {
3422 case TGSI_TOKEN_TYPE_INSTRUCTION:
3423 r = tgsi_is_supported(&ctx);
3424 if (r)
3425 goto out_err;
3426 ctx.max_driver_temp_used = 0;
3427 /* reserve first tmp for everyone */
3428 r600_get_temp(&ctx);
3429
3430 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3431 if ((r = tgsi_split_constant(&ctx)))
3432 goto out_err;
3433 if ((r = tgsi_split_literal_constant(&ctx)))
3434 goto out_err;
3435 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3436 if ((r = tgsi_split_gs_inputs(&ctx)))
3437 goto out_err;
3438 } else if (lds_inputs) {
3439 if ((r = tgsi_split_lds_inputs(&ctx)))
3440 goto out_err;
3441 }
3442 if (ctx.bc->chip_class == CAYMAN)
3443 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3444 else if (ctx.bc->chip_class >= EVERGREEN)
3445 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3446 else
3447 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3448 r = ctx.inst_info->process(&ctx);
3449 if (r)
3450 goto out_err;
3451
3452 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3453 r = r600_store_tcs_output(&ctx);
3454 if (r)
3455 goto out_err;
3456 }
3457 break;
3458 default:
3459 break;
3460 }
3461 }
3462
3463 /* Reset the temporary register counter. */
3464 ctx.max_driver_temp_used = 0;
3465
3466 noutput = shader->noutput;
3467
3468 if (!ring_outputs && ctx.clip_vertex_write) {
3469 unsigned clipdist_temp[2];
3470
3471 clipdist_temp[0] = r600_get_temp(&ctx);
3472 clipdist_temp[1] = r600_get_temp(&ctx);
3473
3474 /* need to convert a clipvertex write into clipdistance writes and not export
3475 the clip vertex anymore */
3476
3477 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3478 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3479 shader->output[noutput].gpr = clipdist_temp[0];
3480 noutput++;
3481 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3482 shader->output[noutput].gpr = clipdist_temp[1];
3483 noutput++;
3484
3485 /* reset spi_sid for clipvertex output to avoid confusing spi */
3486 shader->output[ctx.cv_output].spi_sid = 0;
3487
3488 shader->clip_dist_write = 0xFF;
3489
3490 for (i = 0; i < 8; i++) {
3491 int oreg = i >> 2;
3492 int ochan = i & 3;
3493
3494 for (j = 0; j < 4; j++) {
3495 struct r600_bytecode_alu alu;
3496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3497 alu.op = ALU_OP2_DOT4;
3498 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3499 alu.src[0].chan = j;
3500
3501 alu.src[1].sel = 512 + i;
3502 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3503 alu.src[1].chan = j;
3504
3505 alu.dst.sel = clipdist_temp[oreg];
3506 alu.dst.chan = j;
3507 alu.dst.write = (j == ochan);
3508 if (j == 3)
3509 alu.last = 1;
3510 r = r600_bytecode_add_alu(ctx.bc, &alu);
3511 if (r)
3512 return r;
3513 }
3514 }
3515 }
3516
3517 /* Add stream outputs. */
3518 if (so.num_outputs) {
3519 bool emit = false;
3520 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3521 emit = true;
3522 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3523 emit = true;
3524 if (emit)
3525 emit_streamout(&ctx, &so, -1, NULL);
3526 }
3527 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3528 convert_edgeflag_to_int(&ctx);
3529
3530 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3531 r600_emit_tess_factor(&ctx);
3532
3533 if (lds_outputs) {
3534 if (ctx.type == PIPE_SHADER_VERTEX) {
3535 if (ctx.shader->noutput)
3536 emit_lds_vs_writes(&ctx);
3537 }
3538 } else if (ring_outputs) {
3539 if (shader->vs_as_es || shader->tes_as_es) {
3540 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3541 ctx.gs_export_gpr_tregs[1] = -1;
3542 ctx.gs_export_gpr_tregs[2] = -1;
3543 ctx.gs_export_gpr_tregs[3] = -1;
3544
3545 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3546 }
3547 } else {
3548 /* Export output */
3549 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3550
3551 for (i = 0, j = 0; i < noutput; i++, j++) {
3552 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3553 output[j].gpr = shader->output[i].gpr;
3554 output[j].elem_size = 3;
3555 output[j].swizzle_x = 0;
3556 output[j].swizzle_y = 1;
3557 output[j].swizzle_z = 2;
3558 output[j].swizzle_w = 3;
3559 output[j].burst_count = 1;
3560 output[j].type = -1;
3561 output[j].op = CF_OP_EXPORT;
3562 switch (ctx.type) {
3563 case PIPE_SHADER_VERTEX:
3564 case PIPE_SHADER_TESS_EVAL:
3565 switch (shader->output[i].name) {
3566 case TGSI_SEMANTIC_POSITION:
3567 output[j].array_base = 60;
3568 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3569 pos_emitted = true;
3570 break;
3571
3572 case TGSI_SEMANTIC_PSIZE:
3573 output[j].array_base = 61;
3574 output[j].swizzle_y = 7;
3575 output[j].swizzle_z = 7;
3576 output[j].swizzle_w = 7;
3577 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3578 pos_emitted = true;
3579 break;
3580 case TGSI_SEMANTIC_EDGEFLAG:
3581 output[j].array_base = 61;
3582 output[j].swizzle_x = 7;
3583 output[j].swizzle_y = 0;
3584 output[j].swizzle_z = 7;
3585 output[j].swizzle_w = 7;
3586 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3587 pos_emitted = true;
3588 break;
3589 case TGSI_SEMANTIC_LAYER:
3590 /* spi_sid is 0 for outputs that are
3591 * not consumed by PS */
3592 if (shader->output[i].spi_sid) {
3593 output[j].array_base = next_param_base++;
3594 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3595 j++;
3596 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3597 }
3598 output[j].array_base = 61;
3599 output[j].swizzle_x = 7;
3600 output[j].swizzle_y = 7;
3601 output[j].swizzle_z = 0;
3602 output[j].swizzle_w = 7;
3603 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3604 pos_emitted = true;
3605 break;
3606 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3607 /* spi_sid is 0 for outputs that are
3608 * not consumed by PS */
3609 if (shader->output[i].spi_sid) {
3610 output[j].array_base = next_param_base++;
3611 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3612 j++;
3613 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3614 }
3615 output[j].array_base = 61;
3616 output[j].swizzle_x = 7;
3617 output[j].swizzle_y = 7;
3618 output[j].swizzle_z = 7;
3619 output[j].swizzle_w = 0;
3620 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3621 pos_emitted = true;
3622 break;
3623 case TGSI_SEMANTIC_CLIPVERTEX:
3624 j--;
3625 break;
3626 case TGSI_SEMANTIC_CLIPDIST:
3627 output[j].array_base = next_clip_base++;
3628 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3629 pos_emitted = true;
3630 /* spi_sid is 0 for clipdistance outputs that were generated
3631 * for clipvertex - we don't need to pass them to PS */
3632 if (shader->output[i].spi_sid) {
3633 j++;
3634 /* duplicate it as PARAM to pass to the pixel shader */
3635 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3636 output[j].array_base = next_param_base++;
3637 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3638 }
3639 break;
3640 case TGSI_SEMANTIC_FOG:
3641 output[j].swizzle_y = 4; /* 0 */
3642 output[j].swizzle_z = 4; /* 0 */
3643 output[j].swizzle_w = 5; /* 1 */
3644 break;
3645 case TGSI_SEMANTIC_PRIMID:
3646 output[j].swizzle_x = 2;
3647 output[j].swizzle_y = 4; /* 0 */
3648 output[j].swizzle_z = 4; /* 0 */
3649 output[j].swizzle_w = 4; /* 0 */
3650 break;
3651 }
3652
3653 break;
3654 case PIPE_SHADER_FRAGMENT:
3655 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3656 /* never export more colors than the number of CBs */
3657 if (shader->output[i].sid >= max_color_exports) {
3658 /* skip export */
3659 j--;
3660 continue;
3661 }
3662 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3663 output[j].array_base = shader->output[i].sid;
3664 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3665 shader->nr_ps_color_exports++;
3666 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3667 for (k = 1; k < max_color_exports; k++) {
3668 j++;
3669 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3670 output[j].gpr = shader->output[i].gpr;
3671 output[j].elem_size = 3;
3672 output[j].swizzle_x = 0;
3673 output[j].swizzle_y = 1;
3674 output[j].swizzle_z = 2;
3675 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3676 output[j].burst_count = 1;
3677 output[j].array_base = k;
3678 output[j].op = CF_OP_EXPORT;
3679 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3680 shader->nr_ps_color_exports++;
3681 }
3682 }
3683 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3684 output[j].array_base = 61;
3685 output[j].swizzle_x = 2;
3686 output[j].swizzle_y = 7;
3687 output[j].swizzle_z = output[j].swizzle_w = 7;
3688 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3689 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3690 output[j].array_base = 61;
3691 output[j].swizzle_x = 7;
3692 output[j].swizzle_y = 1;
3693 output[j].swizzle_z = output[j].swizzle_w = 7;
3694 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3695 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3696 output[j].array_base = 61;
3697 output[j].swizzle_x = 7;
3698 output[j].swizzle_y = 7;
3699 output[j].swizzle_z = 0;
3700 output[j].swizzle_w = 7;
3701 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3702 } else {
3703 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3704 r = -EINVAL;
3705 goto out_err;
3706 }
3707 break;
3708 case PIPE_SHADER_TESS_CTRL:
3709 break;
3710 default:
3711 R600_ERR("unsupported processor type %d\n", ctx.type);
3712 r = -EINVAL;
3713 goto out_err;
3714 }
3715
3716 if (output[j].type==-1) {
3717 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3718 output[j].array_base = next_param_base++;
3719 }
3720 }
3721
3722 /* add fake position export */
3723 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3724 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3725 output[j].gpr = 0;
3726 output[j].elem_size = 3;
3727 output[j].swizzle_x = 7;
3728 output[j].swizzle_y = 7;
3729 output[j].swizzle_z = 7;
3730 output[j].swizzle_w = 7;
3731 output[j].burst_count = 1;
3732 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3733 output[j].array_base = 60;
3734 output[j].op = CF_OP_EXPORT;
3735 j++;
3736 }
3737
3738 /* add fake param output for vertex shader if no param is exported */
3739 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3740 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3741 output[j].gpr = 0;
3742 output[j].elem_size = 3;
3743 output[j].swizzle_x = 7;
3744 output[j].swizzle_y = 7;
3745 output[j].swizzle_z = 7;
3746 output[j].swizzle_w = 7;
3747 output[j].burst_count = 1;
3748 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3749 output[j].array_base = 0;
3750 output[j].op = CF_OP_EXPORT;
3751 j++;
3752 }
3753
3754 /* add fake pixel export */
3755 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3756 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3757 output[j].gpr = 0;
3758 output[j].elem_size = 3;
3759 output[j].swizzle_x = 7;
3760 output[j].swizzle_y = 7;
3761 output[j].swizzle_z = 7;
3762 output[j].swizzle_w = 7;
3763 output[j].burst_count = 1;
3764 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3765 output[j].array_base = 0;
3766 output[j].op = CF_OP_EXPORT;
3767 j++;
3768 shader->nr_ps_color_exports++;
3769 }
3770
3771 noutput = j;
3772
3773 /* set export done on last export of each type */
3774 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3775 if (!(output_done & (1 << output[i].type))) {
3776 output_done |= (1 << output[i].type);
3777 output[i].op = CF_OP_EXPORT_DONE;
3778 }
3779 }
3780 /* add output to bytecode */
3781 for (i = 0; i < noutput; i++) {
3782 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3783 if (r)
3784 goto out_err;
3785 }
3786 }
3787
3788 /* add program end */
3789 if (ctx.bc->chip_class == CAYMAN)
3790 cm_bytecode_add_cf_end(ctx.bc);
3791 else {
3792 const struct cf_op_info *last = NULL;
3793
3794 if (ctx.bc->cf_last)
3795 last = r600_isa_cf(ctx.bc->cf_last->op);
3796
3797 /* alu clause instructions don't have EOP bit, so add NOP */
3798 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3799 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3800
3801 ctx.bc->cf_last->end_of_program = 1;
3802 }
3803
3804 /* check GPR limit - we have 124 = 128 - 4
3805 * (4 are reserved as alu clause temporary registers) */
3806 if (ctx.bc->ngpr > 124) {
3807 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3808 r = -ENOMEM;
3809 goto out_err;
3810 }
3811
3812 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3813 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3814 return r;
3815 }
3816
3817 free(ctx.literals);
3818 tgsi_parse_free(&ctx.parse);
3819 return 0;
3820 out_err:
3821 free(ctx.literals);
3822 tgsi_parse_free(&ctx.parse);
3823 return r;
3824 }
3825
3826 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3827 {
3828 const unsigned tgsi_opcode =
3829 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3830 R600_ERR("%s tgsi opcode unsupported\n",
3831 tgsi_get_opcode_name(tgsi_opcode));
3832 return -EINVAL;
3833 }
3834
3835 static int tgsi_end(struct r600_shader_ctx *ctx)
3836 {
3837 return 0;
3838 }
3839
3840 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3841 const struct r600_shader_src *shader_src,
3842 unsigned chan)
3843 {
3844 bc_src->sel = shader_src->sel;
3845 bc_src->chan = shader_src->swizzle[chan];
3846 bc_src->neg = shader_src->neg;
3847 bc_src->abs = shader_src->abs;
3848 bc_src->rel = shader_src->rel;
3849 bc_src->value = shader_src->value[bc_src->chan];
3850 bc_src->kc_bank = shader_src->kc_bank;
3851 bc_src->kc_rel = shader_src->kc_rel;
3852 }
3853
3854 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3855 {
3856 bc_src->abs = 1;
3857 bc_src->neg = 0;
3858 }
3859
3860 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3861 {
3862 bc_src->neg = !bc_src->neg;
3863 }
3864
3865 static void tgsi_dst(struct r600_shader_ctx *ctx,
3866 const struct tgsi_full_dst_register *tgsi_dst,
3867 unsigned swizzle,
3868 struct r600_bytecode_alu_dst *r600_dst)
3869 {
3870 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3871
3872 r600_dst->sel = tgsi_dst->Register.Index;
3873 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3874 r600_dst->chan = swizzle;
3875 r600_dst->write = 1;
3876 if (inst->Instruction.Saturate) {
3877 r600_dst->clamp = 1;
3878 }
3879 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3880 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3881 return;
3882 }
3883 }
3884 if (tgsi_dst->Register.Indirect)
3885 r600_dst->rel = V_SQ_REL_RELATIVE;
3886
3887 }
3888
3889 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3890 {
3891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3892 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3893 struct r600_bytecode_alu alu;
3894 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3895 int use_tmp = 0;
3896
3897 if (singledest) {
3898 switch (write_mask) {
3899 case 0x1:
3900 write_mask = 0x3;
3901 break;
3902 case 0x2:
3903 use_tmp = 1;
3904 write_mask = 0x3;
3905 break;
3906 case 0x4:
3907 write_mask = 0xc;
3908 break;
3909 case 0x8:
3910 write_mask = 0xc;
3911 use_tmp = 3;
3912 break;
3913 }
3914 }
3915
3916 lasti = tgsi_last_instruction(write_mask);
3917 for (i = 0; i <= lasti; i++) {
3918
3919 if (!(write_mask & (1 << i)))
3920 continue;
3921
3922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3923
3924 if (singledest) {
3925 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3926 if (use_tmp) {
3927 alu.dst.sel = ctx->temp_reg;
3928 alu.dst.chan = i;
3929 alu.dst.write = 1;
3930 }
3931 if (i == 1 || i == 3)
3932 alu.dst.write = 0;
3933 } else
3934 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3935
3936 alu.op = ctx->inst_info->op;
3937 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3938 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3939 } else if (!swap) {
3940 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3941 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3942 }
3943 } else {
3944 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3945 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3946 }
3947
3948 /* handle some special cases */
3949 if (i == 1 || i == 3) {
3950 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3951 case TGSI_OPCODE_DABS:
3952 r600_bytecode_src_set_abs(&alu.src[0]);
3953 break;
3954 default:
3955 break;
3956 }
3957 }
3958 if (i == lasti) {
3959 alu.last = 1;
3960 }
3961 r = r600_bytecode_add_alu(ctx->bc, &alu);
3962 if (r)
3963 return r;
3964 }
3965
3966 if (use_tmp) {
3967 write_mask = inst->Dst[0].Register.WriteMask;
3968
3969 /* move result from temp to dst */
3970 for (i = 0; i <= lasti; i++) {
3971 if (!(write_mask & (1 << i)))
3972 continue;
3973
3974 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3975 alu.op = ALU_OP1_MOV;
3976 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3977 alu.src[0].sel = ctx->temp_reg;
3978 alu.src[0].chan = use_tmp - 1;
3979 alu.last = (i == lasti);
3980
3981 r = r600_bytecode_add_alu(ctx->bc, &alu);
3982 if (r)
3983 return r;
3984 }
3985 }
3986 return 0;
3987 }
3988
3989 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3990 {
3991 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3992 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3993 /* confirm writemasking */
3994 if ((write_mask & 0x3) != 0x3 &&
3995 (write_mask & 0xc) != 0xc) {
3996 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3997 return -1;
3998 }
3999 return tgsi_op2_64_params(ctx, false, false);
4000 }
4001
4002 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4003 {
4004 return tgsi_op2_64_params(ctx, true, false);
4005 }
4006
4007 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4008 {
4009 return tgsi_op2_64_params(ctx, true, true);
4010 }
4011
4012 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4013 {
4014 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4015 struct r600_bytecode_alu alu;
4016 int i, j, r;
4017 int lasti = 3;
4018 int tmp = r600_get_temp(ctx);
4019
4020 for (i = 0; i < lasti + 1; i++) {
4021
4022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4023 alu.op = ctx->inst_info->op;
4024 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4025 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4026 }
4027
4028 if (inst->Dst[0].Register.WriteMask & (1 << i))
4029 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4030 else
4031 alu.dst.sel = tmp;
4032
4033 alu.dst.chan = i;
4034 alu.is_op3 = 1;
4035 if (i == lasti) {
4036 alu.last = 1;
4037 }
4038 r = r600_bytecode_add_alu(ctx->bc, &alu);
4039 if (r)
4040 return r;
4041 }
4042 return 0;
4043 }
4044
4045 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4046 {
4047 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4048 struct r600_bytecode_alu alu;
4049 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4050 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4051 /* use temp register if trans_only and more than one dst component */
4052 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4053 unsigned op = ctx->inst_info->op;
4054
4055 if (op == ALU_OP2_MUL_IEEE &&
4056 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4057 op = ALU_OP2_MUL;
4058
4059 for (i = 0; i <= lasti; i++) {
4060 if (!(write_mask & (1 << i)))
4061 continue;
4062
4063 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4064 if (use_tmp) {
4065 alu.dst.sel = ctx->temp_reg;
4066 alu.dst.chan = i;
4067 alu.dst.write = 1;
4068 } else
4069 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4070
4071 alu.op = op;
4072 if (!swap) {
4073 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4074 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4075 }
4076 } else {
4077 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4078 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4079 }
4080 if (i == lasti || trans_only) {
4081 alu.last = 1;
4082 }
4083 r = r600_bytecode_add_alu(ctx->bc, &alu);
4084 if (r)
4085 return r;
4086 }
4087
4088 if (use_tmp) {
4089 /* move result from temp to dst */
4090 for (i = 0; i <= lasti; i++) {
4091 if (!(write_mask & (1 << i)))
4092 continue;
4093
4094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4095 alu.op = ALU_OP1_MOV;
4096 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4097 alu.src[0].sel = ctx->temp_reg;
4098 alu.src[0].chan = i;
4099 alu.last = (i == lasti);
4100
4101 r = r600_bytecode_add_alu(ctx->bc, &alu);
4102 if (r)
4103 return r;
4104 }
4105 }
4106 return 0;
4107 }
4108
4109 static int tgsi_op2(struct r600_shader_ctx *ctx)
4110 {
4111 return tgsi_op2_s(ctx, 0, 0);
4112 }
4113
4114 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4115 {
4116 return tgsi_op2_s(ctx, 1, 0);
4117 }
4118
4119 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4120 {
4121 return tgsi_op2_s(ctx, 0, 1);
4122 }
4123
4124 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4125 {
4126 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4127 struct r600_bytecode_alu alu;
4128 int i, r;
4129 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4130
4131 for (i = 0; i < lasti + 1; i++) {
4132
4133 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4134 continue;
4135 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4136 alu.op = ctx->inst_info->op;
4137
4138 alu.src[0].sel = V_SQ_ALU_SRC_0;
4139
4140 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4141
4142 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4143
4144 if (i == lasti) {
4145 alu.last = 1;
4146 }
4147 r = r600_bytecode_add_alu(ctx->bc, &alu);
4148 if (r)
4149 return r;
4150 }
4151 return 0;
4152
4153 }
4154
4155 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4156 {
4157 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4158 struct r600_bytecode_alu alu;
4159 int i, r;
4160 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4161
4162 for (i = 0; i < lasti + 1; i++) {
4163
4164 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4165 continue;
4166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4167 alu.op = ALU_OP1_MOV;
4168
4169 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4170
4171 if (i == 1 || i == 3)
4172 r600_bytecode_src_toggle_neg(&alu.src[0]);
4173 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4174
4175 if (i == lasti) {
4176 alu.last = 1;
4177 }
4178 r = r600_bytecode_add_alu(ctx->bc, &alu);
4179 if (r)
4180 return r;
4181 }
4182 return 0;
4183
4184 }
4185
4186 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4187 {
4188 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4189 struct r600_bytecode_alu alu;
4190 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4191 int i, j, r;
4192
4193 for (i = 0; i <= 3; i++) {
4194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4195 alu.op = ctx->inst_info->op;
4196
4197 alu.dst.sel = ctx->temp_reg;
4198 alu.dst.chan = i;
4199 alu.dst.write = 1;
4200 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4201 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4202 }
4203
4204 if (i == 3)
4205 alu.last = 1;
4206
4207 r = r600_bytecode_add_alu(ctx->bc, &alu);
4208 if (r)
4209 return r;
4210 }
4211
4212 /* Replicate significand result across channels. */
4213 for (i = 0; i <= 3; i++) {
4214 if (!(write_mask & (1 << i)))
4215 continue;
4216
4217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4218 alu.op = ALU_OP1_MOV;
4219 alu.src[0].chan = (i & 1) + 2;
4220 alu.src[0].sel = ctx->temp_reg;
4221
4222 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4223 alu.dst.write = 1;
4224 alu.last = 1;
4225 r = r600_bytecode_add_alu(ctx->bc, &alu);
4226 if (r)
4227 return r;
4228 }
4229
4230 for (i = 0; i <= 3; i++) {
4231 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4232 /* MOV third channels to writemask dst1 */
4233 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4234 alu.op = ALU_OP1_MOV;
4235 alu.src[0].chan = 1;
4236 alu.src[0].sel = ctx->temp_reg;
4237
4238 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4239 alu.last = 1;
4240 r = r600_bytecode_add_alu(ctx->bc, &alu);
4241 if (r)
4242 return r;
4243 break;
4244 }
4245 }
4246 return 0;
4247 }
4248
4249
4250 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4251 {
4252 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4253 struct r600_bytecode_alu alu;
4254 int i, r;
4255 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4256
4257 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4258 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4259
4260 for (i = 0; i <= (lasti+1)/2; i++) {
4261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4262 alu.op = ctx->inst_info->op;
4263
4264 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4265 alu.dst.sel = ctx->temp_reg;
4266 alu.dst.chan = i;
4267 alu.dst.write = 1;
4268 alu.last = 1;
4269
4270 r = r600_bytecode_add_alu(ctx->bc, &alu);
4271 if (r)
4272 return r;
4273 }
4274
4275 for (i = 0; i <= lasti; i++) {
4276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4277 alu.op = ALU_OP1_FLT32_TO_FLT64;
4278
4279 alu.src[0].chan = i/2;
4280 if (i%2 == 0)
4281 alu.src[0].sel = ctx->temp_reg;
4282 else {
4283 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4284 alu.src[0].value = 0x0;
4285 }
4286 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4287 alu.last = i == lasti;
4288
4289 r = r600_bytecode_add_alu(ctx->bc, &alu);
4290 if (r)
4291 return r;
4292 }
4293
4294 return 0;
4295 }
4296
4297 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4298 {
4299 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4300 struct r600_bytecode_alu alu;
4301 int i, r;
4302 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4303
4304 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4305 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4306
4307 for (i = 0; i <= lasti; i++) {
4308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4309 alu.op = ALU_OP1_FLT64_TO_FLT32;
4310
4311 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4312 alu.dst.chan = i;
4313 alu.dst.sel = ctx->temp_reg;
4314 alu.dst.write = i%2 == 0;
4315 alu.last = i == lasti;
4316
4317 r = r600_bytecode_add_alu(ctx->bc, &alu);
4318 if (r)
4319 return r;
4320 }
4321
4322 for (i = 0; i <= (lasti+1)/2; i++) {
4323 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4324 alu.op = ctx->inst_info->op;
4325
4326 alu.src[0].chan = i*2;
4327 alu.src[0].sel = ctx->temp_reg;
4328 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4329 alu.last = 1;
4330
4331 r = r600_bytecode_add_alu(ctx->bc, &alu);
4332 if (r)
4333 return r;
4334 }
4335
4336 return 0;
4337 }
4338
4339 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4340 unsigned op,
4341 int dst_reg,
4342 struct r600_shader_src *src,
4343 bool abs)
4344 {
4345 struct r600_bytecode_alu alu;
4346 const int last_slot = 3;
4347 int r;
4348
4349 /* these have to write the result to X/Y by the looks of it */
4350 for (int i = 0 ; i < last_slot; i++) {
4351 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4352 alu.op = op;
4353
4354 r600_bytecode_src(&alu.src[0], src, 1);
4355 r600_bytecode_src(&alu.src[1], src, 0);
4356
4357 if (abs)
4358 r600_bytecode_src_set_abs(&alu.src[1]);
4359
4360 alu.dst.sel = dst_reg;
4361 alu.dst.chan = i;
4362 alu.dst.write = (i == 0 || i == 1);
4363
4364 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4365 alu.last = 1;
4366 r = r600_bytecode_add_alu(bc, &alu);
4367 if (r)
4368 return r;
4369 }
4370
4371 return 0;
4372 }
4373
4374 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4375 {
4376 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4377 int i, r;
4378 struct r600_bytecode_alu alu;
4379 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4380 int t1 = ctx->temp_reg;
4381
4382 /* should only be one src regs */
4383 assert(inst->Instruction.NumSrcRegs == 1);
4384
4385 /* only support one double at a time */
4386 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4387 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4388
4389 r = cayman_emit_unary_double_raw(
4390 ctx->bc, ctx->inst_info->op, t1,
4391 &ctx->src[0],
4392 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4393 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4394 if (r)
4395 return r;
4396
4397 for (i = 0 ; i <= lasti; i++) {
4398 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4399 continue;
4400 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4401 alu.op = ALU_OP1_MOV;
4402 alu.src[0].sel = t1;
4403 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4404 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4405 alu.dst.write = 1;
4406 if (i == lasti)
4407 alu.last = 1;
4408 r = r600_bytecode_add_alu(ctx->bc, &alu);
4409 if (r)
4410 return r;
4411 }
4412 return 0;
4413 }
4414
4415 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4416 {
4417 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4418 int i, j, r;
4419 struct r600_bytecode_alu alu;
4420 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4421
4422 for (i = 0 ; i < last_slot; i++) {
4423 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4424 alu.op = ctx->inst_info->op;
4425 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4426 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4427
4428 /* RSQ should take the absolute value of src */
4429 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4430 r600_bytecode_src_set_abs(&alu.src[j]);
4431 }
4432 }
4433 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4434 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4435
4436 if (i == last_slot - 1)
4437 alu.last = 1;
4438 r = r600_bytecode_add_alu(ctx->bc, &alu);
4439 if (r)
4440 return r;
4441 }
4442 return 0;
4443 }
4444
4445 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4446 {
4447 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4448 int i, j, k, r;
4449 struct r600_bytecode_alu alu;
4450 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4451 int t1 = ctx->temp_reg;
4452
4453 for (k = 0; k <= lasti; k++) {
4454 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4455 continue;
4456
4457 for (i = 0 ; i < 4; i++) {
4458 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4459 alu.op = ctx->inst_info->op;
4460 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4461 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4462 }
4463 alu.dst.sel = t1;
4464 alu.dst.chan = i;
4465 alu.dst.write = (i == k);
4466 if (i == 3)
4467 alu.last = 1;
4468 r = r600_bytecode_add_alu(ctx->bc, &alu);
4469 if (r)
4470 return r;
4471 }
4472 }
4473
4474 for (i = 0 ; i <= lasti; i++) {
4475 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4476 continue;
4477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4478 alu.op = ALU_OP1_MOV;
4479 alu.src[0].sel = t1;
4480 alu.src[0].chan = i;
4481 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4482 alu.dst.write = 1;
4483 if (i == lasti)
4484 alu.last = 1;
4485 r = r600_bytecode_add_alu(ctx->bc, &alu);
4486 if (r)
4487 return r;
4488 }
4489
4490 return 0;
4491 }
4492
4493
4494 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4495 {
4496 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4497 int i, j, k, r;
4498 struct r600_bytecode_alu alu;
4499 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4500 int t1 = ctx->temp_reg;
4501
4502 /* t1 would get overwritten below if we actually tried to
4503 * multiply two pairs of doubles at a time. */
4504 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4505 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4506
4507 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4508
4509 for (i = 0; i < 4; i++) {
4510 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4511 alu.op = ctx->inst_info->op;
4512 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4513 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4514 }
4515 alu.dst.sel = t1;
4516 alu.dst.chan = i;
4517 alu.dst.write = 1;
4518 if (i == 3)
4519 alu.last = 1;
4520 r = r600_bytecode_add_alu(ctx->bc, &alu);
4521 if (r)
4522 return r;
4523 }
4524
4525 for (i = 0; i <= lasti; i++) {
4526 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4527 continue;
4528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4529 alu.op = ALU_OP1_MOV;
4530 alu.src[0].sel = t1;
4531 alu.src[0].chan = i;
4532 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4533 alu.dst.write = 1;
4534 if (i == lasti)
4535 alu.last = 1;
4536 r = r600_bytecode_add_alu(ctx->bc, &alu);
4537 if (r)
4538 return r;
4539 }
4540
4541 return 0;
4542 }
4543
4544 /*
4545 * Emit RECIP_64 + MUL_64 to implement division.
4546 */
4547 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4548 {
4549 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4550 int r;
4551 struct r600_bytecode_alu alu;
4552 int t1 = ctx->temp_reg;
4553 int k;
4554
4555 /* Only support one double at a time. This is the same constraint as
4556 * in DMUL lowering. */
4557 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4558 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4559
4560 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4561
4562 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4563 if (r)
4564 return r;
4565
4566 for (int i = 0; i < 4; i++) {
4567 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4568 alu.op = ALU_OP2_MUL_64;
4569
4570 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4571
4572 alu.src[1].sel = t1;
4573 alu.src[1].chan = (i == 3) ? 0 : 1;
4574
4575 alu.dst.sel = t1;
4576 alu.dst.chan = i;
4577 alu.dst.write = 1;
4578 if (i == 3)
4579 alu.last = 1;
4580 r = r600_bytecode_add_alu(ctx->bc, &alu);
4581 if (r)
4582 return r;
4583 }
4584
4585 for (int i = 0; i < 2; i++) {
4586 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4587 alu.op = ALU_OP1_MOV;
4588 alu.src[0].sel = t1;
4589 alu.src[0].chan = i;
4590 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4591 alu.dst.write = 1;
4592 if (i == 1)
4593 alu.last = 1;
4594 r = r600_bytecode_add_alu(ctx->bc, &alu);
4595 if (r)
4596 return r;
4597 }
4598 return 0;
4599 }
4600
4601 /*
4602 * r600 - trunc to -PI..PI range
4603 * r700 - normalize by dividing by 2PI
4604 * see fdo bug 27901
4605 */
4606 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4607 {
4608 int r;
4609 struct r600_bytecode_alu alu;
4610
4611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4612 alu.op = ALU_OP3_MULADD;
4613 alu.is_op3 = 1;
4614
4615 alu.dst.chan = 0;
4616 alu.dst.sel = ctx->temp_reg;
4617 alu.dst.write = 1;
4618
4619 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4620
4621 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4622 alu.src[1].chan = 0;
4623 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4624 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4625 alu.src[2].chan = 0;
4626 alu.last = 1;
4627 r = r600_bytecode_add_alu(ctx->bc, &alu);
4628 if (r)
4629 return r;
4630
4631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4632 alu.op = ALU_OP1_FRACT;
4633
4634 alu.dst.chan = 0;
4635 alu.dst.sel = ctx->temp_reg;
4636 alu.dst.write = 1;
4637
4638 alu.src[0].sel = ctx->temp_reg;
4639 alu.src[0].chan = 0;
4640 alu.last = 1;
4641 r = r600_bytecode_add_alu(ctx->bc, &alu);
4642 if (r)
4643 return r;
4644
4645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4646 alu.op = ALU_OP3_MULADD;
4647 alu.is_op3 = 1;
4648
4649 alu.dst.chan = 0;
4650 alu.dst.sel = ctx->temp_reg;
4651 alu.dst.write = 1;
4652
4653 alu.src[0].sel = ctx->temp_reg;
4654 alu.src[0].chan = 0;
4655
4656 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4657 alu.src[1].chan = 0;
4658 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4659 alu.src[2].chan = 0;
4660
4661 if (ctx->bc->chip_class == R600) {
4662 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4663 alu.src[2].value = u_bitcast_f2u(-M_PI);
4664 } else {
4665 alu.src[1].sel = V_SQ_ALU_SRC_1;
4666 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4667 alu.src[2].neg = 1;
4668 }
4669
4670 alu.last = 1;
4671 r = r600_bytecode_add_alu(ctx->bc, &alu);
4672 if (r)
4673 return r;
4674 return 0;
4675 }
4676
4677 static int cayman_trig(struct r600_shader_ctx *ctx)
4678 {
4679 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4680 struct r600_bytecode_alu alu;
4681 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4682 int i, r;
4683
4684 r = tgsi_setup_trig(ctx);
4685 if (r)
4686 return r;
4687
4688
4689 for (i = 0; i < last_slot; i++) {
4690 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4691 alu.op = ctx->inst_info->op;
4692 alu.dst.chan = i;
4693
4694 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4695 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4696
4697 alu.src[0].sel = ctx->temp_reg;
4698 alu.src[0].chan = 0;
4699 if (i == last_slot - 1)
4700 alu.last = 1;
4701 r = r600_bytecode_add_alu(ctx->bc, &alu);
4702 if (r)
4703 return r;
4704 }
4705 return 0;
4706 }
4707
4708 static int tgsi_trig(struct r600_shader_ctx *ctx)
4709 {
4710 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4711 struct r600_bytecode_alu alu;
4712 int i, r;
4713 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4714
4715 r = tgsi_setup_trig(ctx);
4716 if (r)
4717 return r;
4718
4719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4720 alu.op = ctx->inst_info->op;
4721 alu.dst.chan = 0;
4722 alu.dst.sel = ctx->temp_reg;
4723 alu.dst.write = 1;
4724
4725 alu.src[0].sel = ctx->temp_reg;
4726 alu.src[0].chan = 0;
4727 alu.last = 1;
4728 r = r600_bytecode_add_alu(ctx->bc, &alu);
4729 if (r)
4730 return r;
4731
4732 /* replicate result */
4733 for (i = 0; i < lasti + 1; i++) {
4734 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4735 continue;
4736
4737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4738 alu.op = ALU_OP1_MOV;
4739
4740 alu.src[0].sel = ctx->temp_reg;
4741 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4742 if (i == lasti)
4743 alu.last = 1;
4744 r = r600_bytecode_add_alu(ctx->bc, &alu);
4745 if (r)
4746 return r;
4747 }
4748 return 0;
4749 }
4750
4751 static int tgsi_kill(struct r600_shader_ctx *ctx)
4752 {
4753 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4754 struct r600_bytecode_alu alu;
4755 int i, r;
4756
4757 for (i = 0; i < 4; i++) {
4758 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4759 alu.op = ctx->inst_info->op;
4760
4761 alu.dst.chan = i;
4762
4763 alu.src[0].sel = V_SQ_ALU_SRC_0;
4764
4765 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4766 alu.src[1].sel = V_SQ_ALU_SRC_1;
4767 alu.src[1].neg = 1;
4768 } else {
4769 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4770 }
4771 if (i == 3) {
4772 alu.last = 1;
4773 }
4774 r = r600_bytecode_add_alu(ctx->bc, &alu);
4775 if (r)
4776 return r;
4777 }
4778
4779 /* kill must be last in ALU */
4780 ctx->bc->force_add_cf = 1;
4781 ctx->shader->uses_kill = TRUE;
4782 return 0;
4783 }
4784
4785 static int tgsi_lit(struct r600_shader_ctx *ctx)
4786 {
4787 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4788 struct r600_bytecode_alu alu;
4789 int r;
4790
4791 /* tmp.x = max(src.y, 0.0) */
4792 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4793 alu.op = ALU_OP2_MAX;
4794 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4795 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4796 alu.src[1].chan = 1;
4797
4798 alu.dst.sel = ctx->temp_reg;
4799 alu.dst.chan = 0;
4800 alu.dst.write = 1;
4801
4802 alu.last = 1;
4803 r = r600_bytecode_add_alu(ctx->bc, &alu);
4804 if (r)
4805 return r;
4806
4807 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4808 {
4809 int chan;
4810 int sel;
4811 unsigned i;
4812
4813 if (ctx->bc->chip_class == CAYMAN) {
4814 for (i = 0; i < 3; i++) {
4815 /* tmp.z = log(tmp.x) */
4816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4817 alu.op = ALU_OP1_LOG_CLAMPED;
4818 alu.src[0].sel = ctx->temp_reg;
4819 alu.src[0].chan = 0;
4820 alu.dst.sel = ctx->temp_reg;
4821 alu.dst.chan = i;
4822 if (i == 2) {
4823 alu.dst.write = 1;
4824 alu.last = 1;
4825 } else
4826 alu.dst.write = 0;
4827
4828 r = r600_bytecode_add_alu(ctx->bc, &alu);
4829 if (r)
4830 return r;
4831 }
4832 } else {
4833 /* tmp.z = log(tmp.x) */
4834 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4835 alu.op = ALU_OP1_LOG_CLAMPED;
4836 alu.src[0].sel = ctx->temp_reg;
4837 alu.src[0].chan = 0;
4838 alu.dst.sel = ctx->temp_reg;
4839 alu.dst.chan = 2;
4840 alu.dst.write = 1;
4841 alu.last = 1;
4842 r = r600_bytecode_add_alu(ctx->bc, &alu);
4843 if (r)
4844 return r;
4845 }
4846
4847 chan = alu.dst.chan;
4848 sel = alu.dst.sel;
4849
4850 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4852 alu.op = ALU_OP3_MUL_LIT;
4853 alu.src[0].sel = sel;
4854 alu.src[0].chan = chan;
4855 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4856 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4857 alu.dst.sel = ctx->temp_reg;
4858 alu.dst.chan = 0;
4859 alu.dst.write = 1;
4860 alu.is_op3 = 1;
4861 alu.last = 1;
4862 r = r600_bytecode_add_alu(ctx->bc, &alu);
4863 if (r)
4864 return r;
4865
4866 if (ctx->bc->chip_class == CAYMAN) {
4867 for (i = 0; i < 3; i++) {
4868 /* dst.z = exp(tmp.x) */
4869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4870 alu.op = ALU_OP1_EXP_IEEE;
4871 alu.src[0].sel = ctx->temp_reg;
4872 alu.src[0].chan = 0;
4873 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4874 if (i == 2) {
4875 alu.dst.write = 1;
4876 alu.last = 1;
4877 } else
4878 alu.dst.write = 0;
4879 r = r600_bytecode_add_alu(ctx->bc, &alu);
4880 if (r)
4881 return r;
4882 }
4883 } else {
4884 /* dst.z = exp(tmp.x) */
4885 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4886 alu.op = ALU_OP1_EXP_IEEE;
4887 alu.src[0].sel = ctx->temp_reg;
4888 alu.src[0].chan = 0;
4889 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4890 alu.last = 1;
4891 r = r600_bytecode_add_alu(ctx->bc, &alu);
4892 if (r)
4893 return r;
4894 }
4895 }
4896
4897 /* dst.x, <- 1.0 */
4898 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4899 alu.op = ALU_OP1_MOV;
4900 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4901 alu.src[0].chan = 0;
4902 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4903 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4904 r = r600_bytecode_add_alu(ctx->bc, &alu);
4905 if (r)
4906 return r;
4907
4908 /* dst.y = max(src.x, 0.0) */
4909 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4910 alu.op = ALU_OP2_MAX;
4911 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4912 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4913 alu.src[1].chan = 0;
4914 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4915 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4916 r = r600_bytecode_add_alu(ctx->bc, &alu);
4917 if (r)
4918 return r;
4919
4920 /* dst.w, <- 1.0 */
4921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4922 alu.op = ALU_OP1_MOV;
4923 alu.src[0].sel = V_SQ_ALU_SRC_1;
4924 alu.src[0].chan = 0;
4925 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4926 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4927 alu.last = 1;
4928 r = r600_bytecode_add_alu(ctx->bc, &alu);
4929 if (r)
4930 return r;
4931
4932 return 0;
4933 }
4934
4935 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4936 {
4937 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4938 struct r600_bytecode_alu alu;
4939 int i, r;
4940
4941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4942
4943 alu.op = ALU_OP1_RECIPSQRT_IEEE;
4944
4945 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4946 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4947 r600_bytecode_src_set_abs(&alu.src[i]);
4948 }
4949 alu.dst.sel = ctx->temp_reg;
4950 alu.dst.write = 1;
4951 alu.last = 1;
4952 r = r600_bytecode_add_alu(ctx->bc, &alu);
4953 if (r)
4954 return r;
4955 /* replicate result */
4956 return tgsi_helper_tempx_replicate(ctx);
4957 }
4958
4959 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4960 {
4961 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4962 struct r600_bytecode_alu alu;
4963 int i, r;
4964
4965 for (i = 0; i < 4; i++) {
4966 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4967 alu.src[0].sel = ctx->temp_reg;
4968 alu.op = ALU_OP1_MOV;
4969 alu.dst.chan = i;
4970 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4971 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4972 if (i == 3)
4973 alu.last = 1;
4974 r = r600_bytecode_add_alu(ctx->bc, &alu);
4975 if (r)
4976 return r;
4977 }
4978 return 0;
4979 }
4980
4981 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4982 {
4983 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4984 struct r600_bytecode_alu alu;
4985 int i, r;
4986
4987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4988 alu.op = ctx->inst_info->op;
4989 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4990 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4991 }
4992 alu.dst.sel = ctx->temp_reg;
4993 alu.dst.write = 1;
4994 alu.last = 1;
4995 r = r600_bytecode_add_alu(ctx->bc, &alu);
4996 if (r)
4997 return r;
4998 /* replicate result */
4999 return tgsi_helper_tempx_replicate(ctx);
5000 }
5001
5002 static int cayman_pow(struct r600_shader_ctx *ctx)
5003 {
5004 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5005 int i, r;
5006 struct r600_bytecode_alu alu;
5007 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5008
5009 for (i = 0; i < 3; i++) {
5010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5011 alu.op = ALU_OP1_LOG_IEEE;
5012 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5013 alu.dst.sel = ctx->temp_reg;
5014 alu.dst.chan = i;
5015 alu.dst.write = 1;
5016 if (i == 2)
5017 alu.last = 1;
5018 r = r600_bytecode_add_alu(ctx->bc, &alu);
5019 if (r)
5020 return r;
5021 }
5022
5023 /* b * LOG2(a) */
5024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5025 alu.op = ALU_OP2_MUL;
5026 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5027 alu.src[1].sel = ctx->temp_reg;
5028 alu.dst.sel = ctx->temp_reg;
5029 alu.dst.write = 1;
5030 alu.last = 1;
5031 r = r600_bytecode_add_alu(ctx->bc, &alu);
5032 if (r)
5033 return r;
5034
5035 for (i = 0; i < last_slot; i++) {
5036 /* POW(a,b) = EXP2(b * LOG2(a))*/
5037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5038 alu.op = ALU_OP1_EXP_IEEE;
5039 alu.src[0].sel = ctx->temp_reg;
5040
5041 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5042 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5043 if (i == last_slot - 1)
5044 alu.last = 1;
5045 r = r600_bytecode_add_alu(ctx->bc, &alu);
5046 if (r)
5047 return r;
5048 }
5049 return 0;
5050 }
5051
5052 static int tgsi_pow(struct r600_shader_ctx *ctx)
5053 {
5054 struct r600_bytecode_alu alu;
5055 int r;
5056
5057 /* LOG2(a) */
5058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5059 alu.op = ALU_OP1_LOG_IEEE;
5060 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5061 alu.dst.sel = ctx->temp_reg;
5062 alu.dst.write = 1;
5063 alu.last = 1;
5064 r = r600_bytecode_add_alu(ctx->bc, &alu);
5065 if (r)
5066 return r;
5067 /* b * LOG2(a) */
5068 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5069 alu.op = ALU_OP2_MUL;
5070 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5071 alu.src[1].sel = ctx->temp_reg;
5072 alu.dst.sel = ctx->temp_reg;
5073 alu.dst.write = 1;
5074 alu.last = 1;
5075 r = r600_bytecode_add_alu(ctx->bc, &alu);
5076 if (r)
5077 return r;
5078 /* POW(a,b) = EXP2(b * LOG2(a))*/
5079 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5080 alu.op = ALU_OP1_EXP_IEEE;
5081 alu.src[0].sel = ctx->temp_reg;
5082 alu.dst.sel = ctx->temp_reg;
5083 alu.dst.write = 1;
5084 alu.last = 1;
5085 r = r600_bytecode_add_alu(ctx->bc, &alu);
5086 if (r)
5087 return r;
5088 return tgsi_helper_tempx_replicate(ctx);
5089 }
5090
5091 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5092 {
5093 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5094 struct r600_bytecode_alu alu;
5095 int i, r, j;
5096 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5097 int tmp0 = ctx->temp_reg;
5098 int tmp1 = r600_get_temp(ctx);
5099 int tmp2 = r600_get_temp(ctx);
5100 int tmp3 = r600_get_temp(ctx);
5101 /* Unsigned path:
5102 *
5103 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5104 *
5105 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5106 * 2. tmp0.z = lo (tmp0.x * src2)
5107 * 3. tmp0.w = -tmp0.z
5108 * 4. tmp0.y = hi (tmp0.x * src2)
5109 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5110 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5111 * 7. tmp1.x = tmp0.x - tmp0.w
5112 * 8. tmp1.y = tmp0.x + tmp0.w
5113 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5114 * 10. tmp0.z = hi(tmp0.x * src1) = q
5115 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5116 *
5117 * 12. tmp0.w = src1 - tmp0.y = r
5118 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5119 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5120 *
5121 * if DIV
5122 *
5123 * 15. tmp1.z = tmp0.z + 1 = q + 1
5124 * 16. tmp1.w = tmp0.z - 1 = q - 1
5125 *
5126 * else MOD
5127 *
5128 * 15. tmp1.z = tmp0.w - src2 = r - src2
5129 * 16. tmp1.w = tmp0.w + src2 = r + src2
5130 *
5131 * endif
5132 *
5133 * 17. tmp1.x = tmp1.x & tmp1.y
5134 *
5135 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5136 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5137 *
5138 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5139 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5140 *
5141 * Signed path:
5142 *
5143 * Same as unsigned, using abs values of the operands,
5144 * and fixing the sign of the result in the end.
5145 */
5146
5147 for (i = 0; i < 4; i++) {
5148 if (!(write_mask & (1<<i)))
5149 continue;
5150
5151 if (signed_op) {
5152
5153 /* tmp2.x = -src0 */
5154 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5155 alu.op = ALU_OP2_SUB_INT;
5156
5157 alu.dst.sel = tmp2;
5158 alu.dst.chan = 0;
5159 alu.dst.write = 1;
5160
5161 alu.src[0].sel = V_SQ_ALU_SRC_0;
5162
5163 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5164
5165 alu.last = 1;
5166 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5167 return r;
5168
5169 /* tmp2.y = -src1 */
5170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5171 alu.op = ALU_OP2_SUB_INT;
5172
5173 alu.dst.sel = tmp2;
5174 alu.dst.chan = 1;
5175 alu.dst.write = 1;
5176
5177 alu.src[0].sel = V_SQ_ALU_SRC_0;
5178
5179 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5180
5181 alu.last = 1;
5182 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5183 return r;
5184
5185 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5186 /* it will be a sign of the quotient */
5187 if (!mod) {
5188
5189 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5190 alu.op = ALU_OP2_XOR_INT;
5191
5192 alu.dst.sel = tmp2;
5193 alu.dst.chan = 2;
5194 alu.dst.write = 1;
5195
5196 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5197 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5198
5199 alu.last = 1;
5200 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5201 return r;
5202 }
5203
5204 /* tmp2.x = |src0| */
5205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5206 alu.op = ALU_OP3_CNDGE_INT;
5207 alu.is_op3 = 1;
5208
5209 alu.dst.sel = tmp2;
5210 alu.dst.chan = 0;
5211 alu.dst.write = 1;
5212
5213 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5214 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5215 alu.src[2].sel = tmp2;
5216 alu.src[2].chan = 0;
5217
5218 alu.last = 1;
5219 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5220 return r;
5221
5222 /* tmp2.y = |src1| */
5223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5224 alu.op = ALU_OP3_CNDGE_INT;
5225 alu.is_op3 = 1;
5226
5227 alu.dst.sel = tmp2;
5228 alu.dst.chan = 1;
5229 alu.dst.write = 1;
5230
5231 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5232 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5233 alu.src[2].sel = tmp2;
5234 alu.src[2].chan = 1;
5235
5236 alu.last = 1;
5237 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5238 return r;
5239
5240 }
5241
5242 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5243 if (ctx->bc->chip_class == CAYMAN) {
5244 /* tmp3.x = u2f(src2) */
5245 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5246 alu.op = ALU_OP1_UINT_TO_FLT;
5247
5248 alu.dst.sel = tmp3;
5249 alu.dst.chan = 0;
5250 alu.dst.write = 1;
5251
5252 if (signed_op) {
5253 alu.src[0].sel = tmp2;
5254 alu.src[0].chan = 1;
5255 } else {
5256 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5257 }
5258
5259 alu.last = 1;
5260 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5261 return r;
5262
5263 /* tmp0.x = recip(tmp3.x) */
5264 for (j = 0 ; j < 3; j++) {
5265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5266 alu.op = ALU_OP1_RECIP_IEEE;
5267
5268 alu.dst.sel = tmp0;
5269 alu.dst.chan = j;
5270 alu.dst.write = (j == 0);
5271
5272 alu.src[0].sel = tmp3;
5273 alu.src[0].chan = 0;
5274
5275 if (j == 2)
5276 alu.last = 1;
5277 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5278 return r;
5279 }
5280
5281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5282 alu.op = ALU_OP2_MUL;
5283
5284 alu.src[0].sel = tmp0;
5285 alu.src[0].chan = 0;
5286
5287 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5288 alu.src[1].value = 0x4f800000;
5289
5290 alu.dst.sel = tmp3;
5291 alu.dst.write = 1;
5292 alu.last = 1;
5293 r = r600_bytecode_add_alu(ctx->bc, &alu);
5294 if (r)
5295 return r;
5296
5297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5298 alu.op = ALU_OP1_FLT_TO_UINT;
5299
5300 alu.dst.sel = tmp0;
5301 alu.dst.chan = 0;
5302 alu.dst.write = 1;
5303
5304 alu.src[0].sel = tmp3;
5305 alu.src[0].chan = 0;
5306
5307 alu.last = 1;
5308 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5309 return r;
5310
5311 } else {
5312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5313 alu.op = ALU_OP1_RECIP_UINT;
5314
5315 alu.dst.sel = tmp0;
5316 alu.dst.chan = 0;
5317 alu.dst.write = 1;
5318
5319 if (signed_op) {
5320 alu.src[0].sel = tmp2;
5321 alu.src[0].chan = 1;
5322 } else {
5323 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5324 }
5325
5326 alu.last = 1;
5327 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5328 return r;
5329 }
5330
5331 /* 2. tmp0.z = lo (tmp0.x * src2) */
5332 if (ctx->bc->chip_class == CAYMAN) {
5333 for (j = 0 ; j < 4; j++) {
5334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5335 alu.op = ALU_OP2_MULLO_UINT;
5336
5337 alu.dst.sel = tmp0;
5338 alu.dst.chan = j;
5339 alu.dst.write = (j == 2);
5340
5341 alu.src[0].sel = tmp0;
5342 alu.src[0].chan = 0;
5343 if (signed_op) {
5344 alu.src[1].sel = tmp2;
5345 alu.src[1].chan = 1;
5346 } else {
5347 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5348 }
5349
5350 alu.last = (j == 3);
5351 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5352 return r;
5353 }
5354 } else {
5355 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5356 alu.op = ALU_OP2_MULLO_UINT;
5357
5358 alu.dst.sel = tmp0;
5359 alu.dst.chan = 2;
5360 alu.dst.write = 1;
5361
5362 alu.src[0].sel = tmp0;
5363 alu.src[0].chan = 0;
5364 if (signed_op) {
5365 alu.src[1].sel = tmp2;
5366 alu.src[1].chan = 1;
5367 } else {
5368 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5369 }
5370
5371 alu.last = 1;
5372 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5373 return r;
5374 }
5375
5376 /* 3. tmp0.w = -tmp0.z */
5377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5378 alu.op = ALU_OP2_SUB_INT;
5379
5380 alu.dst.sel = tmp0;
5381 alu.dst.chan = 3;
5382 alu.dst.write = 1;
5383
5384 alu.src[0].sel = V_SQ_ALU_SRC_0;
5385 alu.src[1].sel = tmp0;
5386 alu.src[1].chan = 2;
5387
5388 alu.last = 1;
5389 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5390 return r;
5391
5392 /* 4. tmp0.y = hi (tmp0.x * src2) */
5393 if (ctx->bc->chip_class == CAYMAN) {
5394 for (j = 0 ; j < 4; j++) {
5395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5396 alu.op = ALU_OP2_MULHI_UINT;
5397
5398 alu.dst.sel = tmp0;
5399 alu.dst.chan = j;
5400 alu.dst.write = (j == 1);
5401
5402 alu.src[0].sel = tmp0;
5403 alu.src[0].chan = 0;
5404
5405 if (signed_op) {
5406 alu.src[1].sel = tmp2;
5407 alu.src[1].chan = 1;
5408 } else {
5409 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5410 }
5411 alu.last = (j == 3);
5412 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5413 return r;
5414 }
5415 } else {
5416 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5417 alu.op = ALU_OP2_MULHI_UINT;
5418
5419 alu.dst.sel = tmp0;
5420 alu.dst.chan = 1;
5421 alu.dst.write = 1;
5422
5423 alu.src[0].sel = tmp0;
5424 alu.src[0].chan = 0;
5425
5426 if (signed_op) {
5427 alu.src[1].sel = tmp2;
5428 alu.src[1].chan = 1;
5429 } else {
5430 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5431 }
5432
5433 alu.last = 1;
5434 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5435 return r;
5436 }
5437
5438 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5439 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5440 alu.op = ALU_OP3_CNDE_INT;
5441 alu.is_op3 = 1;
5442
5443 alu.dst.sel = tmp0;
5444 alu.dst.chan = 2;
5445 alu.dst.write = 1;
5446
5447 alu.src[0].sel = tmp0;
5448 alu.src[0].chan = 1;
5449 alu.src[1].sel = tmp0;
5450 alu.src[1].chan = 3;
5451 alu.src[2].sel = tmp0;
5452 alu.src[2].chan = 2;
5453
5454 alu.last = 1;
5455 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5456 return r;
5457
5458 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5459 if (ctx->bc->chip_class == CAYMAN) {
5460 for (j = 0 ; j < 4; j++) {
5461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5462 alu.op = ALU_OP2_MULHI_UINT;
5463
5464 alu.dst.sel = tmp0;
5465 alu.dst.chan = j;
5466 alu.dst.write = (j == 3);
5467
5468 alu.src[0].sel = tmp0;
5469 alu.src[0].chan = 2;
5470
5471 alu.src[1].sel = tmp0;
5472 alu.src[1].chan = 0;
5473
5474 alu.last = (j == 3);
5475 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5476 return r;
5477 }
5478 } else {
5479 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5480 alu.op = ALU_OP2_MULHI_UINT;
5481
5482 alu.dst.sel = tmp0;
5483 alu.dst.chan = 3;
5484 alu.dst.write = 1;
5485
5486 alu.src[0].sel = tmp0;
5487 alu.src[0].chan = 2;
5488
5489 alu.src[1].sel = tmp0;
5490 alu.src[1].chan = 0;
5491
5492 alu.last = 1;
5493 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5494 return r;
5495 }
5496
5497 /* 7. tmp1.x = tmp0.x - tmp0.w */
5498 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5499 alu.op = ALU_OP2_SUB_INT;
5500
5501 alu.dst.sel = tmp1;
5502 alu.dst.chan = 0;
5503 alu.dst.write = 1;
5504
5505 alu.src[0].sel = tmp0;
5506 alu.src[0].chan = 0;
5507 alu.src[1].sel = tmp0;
5508 alu.src[1].chan = 3;
5509
5510 alu.last = 1;
5511 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5512 return r;
5513
5514 /* 8. tmp1.y = tmp0.x + tmp0.w */
5515 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5516 alu.op = ALU_OP2_ADD_INT;
5517
5518 alu.dst.sel = tmp1;
5519 alu.dst.chan = 1;
5520 alu.dst.write = 1;
5521
5522 alu.src[0].sel = tmp0;
5523 alu.src[0].chan = 0;
5524 alu.src[1].sel = tmp0;
5525 alu.src[1].chan = 3;
5526
5527 alu.last = 1;
5528 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5529 return r;
5530
5531 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5532 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5533 alu.op = ALU_OP3_CNDE_INT;
5534 alu.is_op3 = 1;
5535
5536 alu.dst.sel = tmp0;
5537 alu.dst.chan = 0;
5538 alu.dst.write = 1;
5539
5540 alu.src[0].sel = tmp0;
5541 alu.src[0].chan = 1;
5542 alu.src[1].sel = tmp1;
5543 alu.src[1].chan = 1;
5544 alu.src[2].sel = tmp1;
5545 alu.src[2].chan = 0;
5546
5547 alu.last = 1;
5548 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5549 return r;
5550
5551 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5552 if (ctx->bc->chip_class == CAYMAN) {
5553 for (j = 0 ; j < 4; j++) {
5554 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5555 alu.op = ALU_OP2_MULHI_UINT;
5556
5557 alu.dst.sel = tmp0;
5558 alu.dst.chan = j;
5559 alu.dst.write = (j == 2);
5560
5561 alu.src[0].sel = tmp0;
5562 alu.src[0].chan = 0;
5563
5564 if (signed_op) {
5565 alu.src[1].sel = tmp2;
5566 alu.src[1].chan = 0;
5567 } else {
5568 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5569 }
5570
5571 alu.last = (j == 3);
5572 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5573 return r;
5574 }
5575 } else {
5576 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5577 alu.op = ALU_OP2_MULHI_UINT;
5578
5579 alu.dst.sel = tmp0;
5580 alu.dst.chan = 2;
5581 alu.dst.write = 1;
5582
5583 alu.src[0].sel = tmp0;
5584 alu.src[0].chan = 0;
5585
5586 if (signed_op) {
5587 alu.src[1].sel = tmp2;
5588 alu.src[1].chan = 0;
5589 } else {
5590 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5591 }
5592
5593 alu.last = 1;
5594 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5595 return r;
5596 }
5597
5598 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5599 if (ctx->bc->chip_class == CAYMAN) {
5600 for (j = 0 ; j < 4; j++) {
5601 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5602 alu.op = ALU_OP2_MULLO_UINT;
5603
5604 alu.dst.sel = tmp0;
5605 alu.dst.chan = j;
5606 alu.dst.write = (j == 1);
5607
5608 if (signed_op) {
5609 alu.src[0].sel = tmp2;
5610 alu.src[0].chan = 1;
5611 } else {
5612 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5613 }
5614
5615 alu.src[1].sel = tmp0;
5616 alu.src[1].chan = 2;
5617
5618 alu.last = (j == 3);
5619 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5620 return r;
5621 }
5622 } else {
5623 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5624 alu.op = ALU_OP2_MULLO_UINT;
5625
5626 alu.dst.sel = tmp0;
5627 alu.dst.chan = 1;
5628 alu.dst.write = 1;
5629
5630 if (signed_op) {
5631 alu.src[0].sel = tmp2;
5632 alu.src[0].chan = 1;
5633 } else {
5634 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5635 }
5636
5637 alu.src[1].sel = tmp0;
5638 alu.src[1].chan = 2;
5639
5640 alu.last = 1;
5641 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5642 return r;
5643 }
5644
5645 /* 12. tmp0.w = src1 - tmp0.y = r */
5646 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5647 alu.op = ALU_OP2_SUB_INT;
5648
5649 alu.dst.sel = tmp0;
5650 alu.dst.chan = 3;
5651 alu.dst.write = 1;
5652
5653 if (signed_op) {
5654 alu.src[0].sel = tmp2;
5655 alu.src[0].chan = 0;
5656 } else {
5657 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5658 }
5659
5660 alu.src[1].sel = tmp0;
5661 alu.src[1].chan = 1;
5662
5663 alu.last = 1;
5664 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5665 return r;
5666
5667 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5668 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5669 alu.op = ALU_OP2_SETGE_UINT;
5670
5671 alu.dst.sel = tmp1;
5672 alu.dst.chan = 0;
5673 alu.dst.write = 1;
5674
5675 alu.src[0].sel = tmp0;
5676 alu.src[0].chan = 3;
5677 if (signed_op) {
5678 alu.src[1].sel = tmp2;
5679 alu.src[1].chan = 1;
5680 } else {
5681 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5682 }
5683
5684 alu.last = 1;
5685 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5686 return r;
5687
5688 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5689 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5690 alu.op = ALU_OP2_SETGE_UINT;
5691
5692 alu.dst.sel = tmp1;
5693 alu.dst.chan = 1;
5694 alu.dst.write = 1;
5695
5696 if (signed_op) {
5697 alu.src[0].sel = tmp2;
5698 alu.src[0].chan = 0;
5699 } else {
5700 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5701 }
5702
5703 alu.src[1].sel = tmp0;
5704 alu.src[1].chan = 1;
5705
5706 alu.last = 1;
5707 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5708 return r;
5709
5710 if (mod) { /* UMOD */
5711
5712 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5713 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5714 alu.op = ALU_OP2_SUB_INT;
5715
5716 alu.dst.sel = tmp1;
5717 alu.dst.chan = 2;
5718 alu.dst.write = 1;
5719
5720 alu.src[0].sel = tmp0;
5721 alu.src[0].chan = 3;
5722
5723 if (signed_op) {
5724 alu.src[1].sel = tmp2;
5725 alu.src[1].chan = 1;
5726 } else {
5727 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5728 }
5729
5730 alu.last = 1;
5731 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5732 return r;
5733
5734 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5736 alu.op = ALU_OP2_ADD_INT;
5737
5738 alu.dst.sel = tmp1;
5739 alu.dst.chan = 3;
5740 alu.dst.write = 1;
5741
5742 alu.src[0].sel = tmp0;
5743 alu.src[0].chan = 3;
5744 if (signed_op) {
5745 alu.src[1].sel = tmp2;
5746 alu.src[1].chan = 1;
5747 } else {
5748 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5749 }
5750
5751 alu.last = 1;
5752 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5753 return r;
5754
5755 } else { /* UDIV */
5756
5757 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5758 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5759 alu.op = ALU_OP2_ADD_INT;
5760
5761 alu.dst.sel = tmp1;
5762 alu.dst.chan = 2;
5763 alu.dst.write = 1;
5764
5765 alu.src[0].sel = tmp0;
5766 alu.src[0].chan = 2;
5767 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5768
5769 alu.last = 1;
5770 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5771 return r;
5772
5773 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5775 alu.op = ALU_OP2_ADD_INT;
5776
5777 alu.dst.sel = tmp1;
5778 alu.dst.chan = 3;
5779 alu.dst.write = 1;
5780
5781 alu.src[0].sel = tmp0;
5782 alu.src[0].chan = 2;
5783 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5784
5785 alu.last = 1;
5786 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5787 return r;
5788
5789 }
5790
5791 /* 17. tmp1.x = tmp1.x & tmp1.y */
5792 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5793 alu.op = ALU_OP2_AND_INT;
5794
5795 alu.dst.sel = tmp1;
5796 alu.dst.chan = 0;
5797 alu.dst.write = 1;
5798
5799 alu.src[0].sel = tmp1;
5800 alu.src[0].chan = 0;
5801 alu.src[1].sel = tmp1;
5802 alu.src[1].chan = 1;
5803
5804 alu.last = 1;
5805 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5806 return r;
5807
5808 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5809 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5811 alu.op = ALU_OP3_CNDE_INT;
5812 alu.is_op3 = 1;
5813
5814 alu.dst.sel = tmp0;
5815 alu.dst.chan = 2;
5816 alu.dst.write = 1;
5817
5818 alu.src[0].sel = tmp1;
5819 alu.src[0].chan = 0;
5820 alu.src[1].sel = tmp0;
5821 alu.src[1].chan = mod ? 3 : 2;
5822 alu.src[2].sel = tmp1;
5823 alu.src[2].chan = 2;
5824
5825 alu.last = 1;
5826 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5827 return r;
5828
5829 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5831 alu.op = ALU_OP3_CNDE_INT;
5832 alu.is_op3 = 1;
5833
5834 if (signed_op) {
5835 alu.dst.sel = tmp0;
5836 alu.dst.chan = 2;
5837 alu.dst.write = 1;
5838 } else {
5839 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5840 }
5841
5842 alu.src[0].sel = tmp1;
5843 alu.src[0].chan = 1;
5844 alu.src[1].sel = tmp1;
5845 alu.src[1].chan = 3;
5846 alu.src[2].sel = tmp0;
5847 alu.src[2].chan = 2;
5848
5849 alu.last = 1;
5850 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5851 return r;
5852
5853 if (signed_op) {
5854
5855 /* fix the sign of the result */
5856
5857 if (mod) {
5858
5859 /* tmp0.x = -tmp0.z */
5860 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5861 alu.op = ALU_OP2_SUB_INT;
5862
5863 alu.dst.sel = tmp0;
5864 alu.dst.chan = 0;
5865 alu.dst.write = 1;
5866
5867 alu.src[0].sel = V_SQ_ALU_SRC_0;
5868 alu.src[1].sel = tmp0;
5869 alu.src[1].chan = 2;
5870
5871 alu.last = 1;
5872 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5873 return r;
5874
5875 /* sign of the remainder is the same as the sign of src0 */
5876 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5877 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5878 alu.op = ALU_OP3_CNDGE_INT;
5879 alu.is_op3 = 1;
5880
5881 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5882
5883 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5884 alu.src[1].sel = tmp0;
5885 alu.src[1].chan = 2;
5886 alu.src[2].sel = tmp0;
5887 alu.src[2].chan = 0;
5888
5889 alu.last = 1;
5890 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5891 return r;
5892
5893 } else {
5894
5895 /* tmp0.x = -tmp0.z */
5896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5897 alu.op = ALU_OP2_SUB_INT;
5898
5899 alu.dst.sel = tmp0;
5900 alu.dst.chan = 0;
5901 alu.dst.write = 1;
5902
5903 alu.src[0].sel = V_SQ_ALU_SRC_0;
5904 alu.src[1].sel = tmp0;
5905 alu.src[1].chan = 2;
5906
5907 alu.last = 1;
5908 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5909 return r;
5910
5911 /* fix the quotient sign (same as the sign of src0*src1) */
5912 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5913 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5914 alu.op = ALU_OP3_CNDGE_INT;
5915 alu.is_op3 = 1;
5916
5917 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5918
5919 alu.src[0].sel = tmp2;
5920 alu.src[0].chan = 2;
5921 alu.src[1].sel = tmp0;
5922 alu.src[1].chan = 2;
5923 alu.src[2].sel = tmp0;
5924 alu.src[2].chan = 0;
5925
5926 alu.last = 1;
5927 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5928 return r;
5929 }
5930 }
5931 }
5932 return 0;
5933 }
5934
5935 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5936 {
5937 return tgsi_divmod(ctx, 0, 0);
5938 }
5939
5940 static int tgsi_umod(struct r600_shader_ctx *ctx)
5941 {
5942 return tgsi_divmod(ctx, 1, 0);
5943 }
5944
5945 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5946 {
5947 return tgsi_divmod(ctx, 0, 1);
5948 }
5949
5950 static int tgsi_imod(struct r600_shader_ctx *ctx)
5951 {
5952 return tgsi_divmod(ctx, 1, 1);
5953 }
5954
5955
5956 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5957 {
5958 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5959 struct r600_bytecode_alu alu;
5960 int i, r;
5961 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5962 int last_inst = tgsi_last_instruction(write_mask);
5963
5964 for (i = 0; i < 4; i++) {
5965 if (!(write_mask & (1<<i)))
5966 continue;
5967
5968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5969 alu.op = ALU_OP1_TRUNC;
5970
5971 alu.dst.sel = ctx->temp_reg;
5972 alu.dst.chan = i;
5973 alu.dst.write = 1;
5974
5975 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5976 if (i == last_inst)
5977 alu.last = 1;
5978 r = r600_bytecode_add_alu(ctx->bc, &alu);
5979 if (r)
5980 return r;
5981 }
5982
5983 for (i = 0; i < 4; i++) {
5984 if (!(write_mask & (1<<i)))
5985 continue;
5986
5987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5988 alu.op = ctx->inst_info->op;
5989
5990 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5991
5992 alu.src[0].sel = ctx->temp_reg;
5993 alu.src[0].chan = i;
5994
5995 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5996 alu.last = 1;
5997 r = r600_bytecode_add_alu(ctx->bc, &alu);
5998 if (r)
5999 return r;
6000 }
6001
6002 return 0;
6003 }
6004
6005 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6006 {
6007 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6008 struct r600_bytecode_alu alu;
6009 int i, r;
6010 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6011 int last_inst = tgsi_last_instruction(write_mask);
6012
6013 /* tmp = -src */
6014 for (i = 0; i < 4; i++) {
6015 if (!(write_mask & (1<<i)))
6016 continue;
6017
6018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6019 alu.op = ALU_OP2_SUB_INT;
6020
6021 alu.dst.sel = ctx->temp_reg;
6022 alu.dst.chan = i;
6023 alu.dst.write = 1;
6024
6025 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6026 alu.src[0].sel = V_SQ_ALU_SRC_0;
6027
6028 if (i == last_inst)
6029 alu.last = 1;
6030 r = r600_bytecode_add_alu(ctx->bc, &alu);
6031 if (r)
6032 return r;
6033 }
6034
6035 /* dst = (src >= 0 ? src : tmp) */
6036 for (i = 0; i < 4; i++) {
6037 if (!(write_mask & (1<<i)))
6038 continue;
6039
6040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6041 alu.op = ALU_OP3_CNDGE_INT;
6042 alu.is_op3 = 1;
6043 alu.dst.write = 1;
6044
6045 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6046
6047 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6048 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6049 alu.src[2].sel = ctx->temp_reg;
6050 alu.src[2].chan = i;
6051
6052 if (i == last_inst)
6053 alu.last = 1;
6054 r = r600_bytecode_add_alu(ctx->bc, &alu);
6055 if (r)
6056 return r;
6057 }
6058 return 0;
6059 }
6060
6061 static int tgsi_issg(struct r600_shader_ctx *ctx)
6062 {
6063 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6064 struct r600_bytecode_alu alu;
6065 int i, r;
6066 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6067 int last_inst = tgsi_last_instruction(write_mask);
6068
6069 /* tmp = (src >= 0 ? src : -1) */
6070 for (i = 0; i < 4; i++) {
6071 if (!(write_mask & (1<<i)))
6072 continue;
6073
6074 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6075 alu.op = ALU_OP3_CNDGE_INT;
6076 alu.is_op3 = 1;
6077
6078 alu.dst.sel = ctx->temp_reg;
6079 alu.dst.chan = i;
6080 alu.dst.write = 1;
6081
6082 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6083 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6084 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6085
6086 if (i == last_inst)
6087 alu.last = 1;
6088 r = r600_bytecode_add_alu(ctx->bc, &alu);
6089 if (r)
6090 return r;
6091 }
6092
6093 /* dst = (tmp > 0 ? 1 : tmp) */
6094 for (i = 0; i < 4; i++) {
6095 if (!(write_mask & (1<<i)))
6096 continue;
6097
6098 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6099 alu.op = ALU_OP3_CNDGT_INT;
6100 alu.is_op3 = 1;
6101 alu.dst.write = 1;
6102
6103 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6104
6105 alu.src[0].sel = ctx->temp_reg;
6106 alu.src[0].chan = i;
6107
6108 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6109
6110 alu.src[2].sel = ctx->temp_reg;
6111 alu.src[2].chan = i;
6112
6113 if (i == last_inst)
6114 alu.last = 1;
6115 r = r600_bytecode_add_alu(ctx->bc, &alu);
6116 if (r)
6117 return r;
6118 }
6119 return 0;
6120 }
6121
6122
6123
6124 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6125 {
6126 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6127 struct r600_bytecode_alu alu;
6128 int i, r;
6129
6130 /* tmp = (src > 0 ? 1 : src) */
6131 for (i = 0; i < 4; i++) {
6132 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6133 alu.op = ALU_OP3_CNDGT;
6134 alu.is_op3 = 1;
6135
6136 alu.dst.sel = ctx->temp_reg;
6137 alu.dst.chan = i;
6138
6139 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6140 alu.src[1].sel = V_SQ_ALU_SRC_1;
6141 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6142
6143 if (i == 3)
6144 alu.last = 1;
6145 r = r600_bytecode_add_alu(ctx->bc, &alu);
6146 if (r)
6147 return r;
6148 }
6149
6150 /* dst = (-tmp > 0 ? -1 : tmp) */
6151 for (i = 0; i < 4; i++) {
6152 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6153 alu.op = ALU_OP3_CNDGT;
6154 alu.is_op3 = 1;
6155 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6156
6157 alu.src[0].sel = ctx->temp_reg;
6158 alu.src[0].chan = i;
6159 alu.src[0].neg = 1;
6160
6161 alu.src[1].sel = V_SQ_ALU_SRC_1;
6162 alu.src[1].neg = 1;
6163
6164 alu.src[2].sel = ctx->temp_reg;
6165 alu.src[2].chan = i;
6166
6167 if (i == 3)
6168 alu.last = 1;
6169 r = r600_bytecode_add_alu(ctx->bc, &alu);
6170 if (r)
6171 return r;
6172 }
6173 return 0;
6174 }
6175
6176 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6177 {
6178 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6179 struct r600_bytecode_alu alu;
6180 int i, r, t1, t2;
6181
6182 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6183 int last_inst = tgsi_last_instruction(write_mask);
6184
6185 t1 = r600_get_temp(ctx);
6186
6187 for (i = 0; i < 4; i++) {
6188 if (!(write_mask & (1<<i)))
6189 continue;
6190
6191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6192 alu.op = ALU_OP2_SETGE_INT;
6193 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6194 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6195 alu.src[1].value = 32;
6196 alu.dst.sel = ctx->temp_reg;
6197 alu.dst.chan = i;
6198 alu.dst.write = 1;
6199 alu.last = i == last_inst;
6200 r = r600_bytecode_add_alu(ctx->bc, &alu);
6201 if (r)
6202 return r;
6203 }
6204
6205 for (i = 0; i < 4; i++) {
6206 if (!(write_mask & (1<<i)))
6207 continue;
6208
6209 /* create mask tmp */
6210 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6211 alu.op = ALU_OP2_BFM_INT;
6212 alu.dst.sel = t1;
6213 alu.dst.chan = i;
6214 alu.dst.write = 1;
6215 alu.last = i == last_inst;
6216
6217 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6218 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6219
6220 r = r600_bytecode_add_alu(ctx->bc, &alu);
6221 if (r)
6222 return r;
6223 }
6224
6225 t2 = r600_get_temp(ctx);
6226
6227 for (i = 0; i < 4; i++) {
6228 if (!(write_mask & (1<<i)))
6229 continue;
6230
6231 /* shift insert left */
6232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6233 alu.op = ALU_OP2_LSHL_INT;
6234 alu.dst.sel = t2;
6235 alu.dst.chan = i;
6236 alu.dst.write = 1;
6237 alu.last = i == last_inst;
6238
6239 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6240 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6241
6242 r = r600_bytecode_add_alu(ctx->bc, &alu);
6243 if (r)
6244 return r;
6245 }
6246
6247 for (i = 0; i < 4; i++) {
6248 if (!(write_mask & (1<<i)))
6249 continue;
6250
6251 /* actual bitfield insert */
6252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6253 alu.op = ALU_OP3_BFI_INT;
6254 alu.is_op3 = 1;
6255 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6256 alu.dst.chan = i;
6257 alu.dst.write = 1;
6258 alu.last = i == last_inst;
6259
6260 alu.src[0].sel = t1;
6261 alu.src[0].chan = i;
6262 alu.src[1].sel = t2;
6263 alu.src[1].chan = i;
6264 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6265
6266 r = r600_bytecode_add_alu(ctx->bc, &alu);
6267 if (r)
6268 return r;
6269 }
6270
6271 for (i = 0; i < 4; i++) {
6272 if (!(write_mask & (1<<i)))
6273 continue;
6274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6275 alu.op = ALU_OP3_CNDE_INT;
6276 alu.is_op3 = 1;
6277 alu.src[0].sel = ctx->temp_reg;
6278 alu.src[0].chan = i;
6279 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6280
6281 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6282
6283 alu.src[1].sel = alu.dst.sel;
6284 alu.src[1].chan = i;
6285
6286 alu.last = i == last_inst;
6287 r = r600_bytecode_add_alu(ctx->bc, &alu);
6288 if (r)
6289 return r;
6290 }
6291 return 0;
6292 }
6293
6294 static int tgsi_msb(struct r600_shader_ctx *ctx)
6295 {
6296 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6297 struct r600_bytecode_alu alu;
6298 int i, r, t1, t2;
6299
6300 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6301 int last_inst = tgsi_last_instruction(write_mask);
6302
6303 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6304 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6305
6306 t1 = ctx->temp_reg;
6307
6308 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6309 for (i = 0; i < 4; i++) {
6310 if (!(write_mask & (1<<i)))
6311 continue;
6312
6313 /* t1 = FFBH_INT / FFBH_UINT */
6314 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6315 alu.op = ctx->inst_info->op;
6316 alu.dst.sel = t1;
6317 alu.dst.chan = i;
6318 alu.dst.write = 1;
6319 alu.last = i == last_inst;
6320
6321 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6322
6323 r = r600_bytecode_add_alu(ctx->bc, &alu);
6324 if (r)
6325 return r;
6326 }
6327
6328 t2 = r600_get_temp(ctx);
6329
6330 for (i = 0; i < 4; i++) {
6331 if (!(write_mask & (1<<i)))
6332 continue;
6333
6334 /* t2 = 31 - t1 */
6335 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6336 alu.op = ALU_OP2_SUB_INT;
6337 alu.dst.sel = t2;
6338 alu.dst.chan = i;
6339 alu.dst.write = 1;
6340 alu.last = i == last_inst;
6341
6342 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6343 alu.src[0].value = 31;
6344 alu.src[1].sel = t1;
6345 alu.src[1].chan = i;
6346
6347 r = r600_bytecode_add_alu(ctx->bc, &alu);
6348 if (r)
6349 return r;
6350 }
6351
6352 for (i = 0; i < 4; i++) {
6353 if (!(write_mask & (1<<i)))
6354 continue;
6355
6356 /* result = t1 >= 0 ? t2 : t1 */
6357 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6358 alu.op = ALU_OP3_CNDGE_INT;
6359 alu.is_op3 = 1;
6360 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6361 alu.dst.chan = i;
6362 alu.dst.write = 1;
6363 alu.last = i == last_inst;
6364
6365 alu.src[0].sel = t1;
6366 alu.src[0].chan = i;
6367 alu.src[1].sel = t2;
6368 alu.src[1].chan = i;
6369 alu.src[2].sel = t1;
6370 alu.src[2].chan = i;
6371
6372 r = r600_bytecode_add_alu(ctx->bc, &alu);
6373 if (r)
6374 return r;
6375 }
6376
6377 return 0;
6378 }
6379
6380 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6381 {
6382 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6383 struct r600_bytecode_alu alu;
6384 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6385 unsigned location;
6386 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6387
6388 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6389
6390 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6391 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6392 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6393 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6394 }
6395 else {
6396 location = TGSI_INTERPOLATE_LOC_CENTROID;
6397 }
6398
6399 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6400 if (k < 0)
6401 k = 0;
6402 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6403 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6404
6405 /* NOTE: currently offset is not perspective correct */
6406 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6407 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6408 int sample_gpr = -1;
6409 int gradientsH, gradientsV;
6410 struct r600_bytecode_tex tex;
6411
6412 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6413 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6414 }
6415
6416 gradientsH = r600_get_temp(ctx);
6417 gradientsV = r600_get_temp(ctx);
6418 for (i = 0; i < 2; i++) {
6419 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6420 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6421 tex.src_gpr = interp_gpr;
6422 tex.src_sel_x = interp_base_chan + 0;
6423 tex.src_sel_y = interp_base_chan + 1;
6424 tex.src_sel_z = 0;
6425 tex.src_sel_w = 0;
6426 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6427 tex.dst_sel_x = 0;
6428 tex.dst_sel_y = 1;
6429 tex.dst_sel_z = 7;
6430 tex.dst_sel_w = 7;
6431 tex.inst_mod = 1; // Use per pixel gradient calculation
6432 tex.sampler_id = 0;
6433 tex.resource_id = tex.sampler_id;
6434 r = r600_bytecode_add_tex(ctx->bc, &tex);
6435 if (r)
6436 return r;
6437 }
6438
6439 for (i = 0; i < 2; i++) {
6440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6441 alu.op = ALU_OP3_MULADD;
6442 alu.is_op3 = 1;
6443 alu.src[0].sel = gradientsH;
6444 alu.src[0].chan = i;
6445 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6446 alu.src[1].sel = sample_gpr;
6447 alu.src[1].chan = 2;
6448 }
6449 else {
6450 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6451 }
6452 alu.src[2].sel = interp_gpr;
6453 alu.src[2].chan = interp_base_chan + i;
6454 alu.dst.sel = ctx->temp_reg;
6455 alu.dst.chan = i;
6456 alu.last = i == 1;
6457
6458 r = r600_bytecode_add_alu(ctx->bc, &alu);
6459 if (r)
6460 return r;
6461 }
6462
6463 for (i = 0; i < 2; i++) {
6464 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6465 alu.op = ALU_OP3_MULADD;
6466 alu.is_op3 = 1;
6467 alu.src[0].sel = gradientsV;
6468 alu.src[0].chan = i;
6469 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6470 alu.src[1].sel = sample_gpr;
6471 alu.src[1].chan = 3;
6472 }
6473 else {
6474 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6475 }
6476 alu.src[2].sel = ctx->temp_reg;
6477 alu.src[2].chan = i;
6478 alu.dst.sel = ctx->temp_reg;
6479 alu.dst.chan = i;
6480 alu.last = i == 1;
6481
6482 r = r600_bytecode_add_alu(ctx->bc, &alu);
6483 if (r)
6484 return r;
6485 }
6486 }
6487
6488 tmp = r600_get_temp(ctx);
6489 for (i = 0; i < 8; i++) {
6490 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6491 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6492
6493 alu.dst.sel = tmp;
6494 if ((i > 1 && i < 6)) {
6495 alu.dst.write = 1;
6496 }
6497 else {
6498 alu.dst.write = 0;
6499 }
6500 alu.dst.chan = i % 4;
6501
6502 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6503 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6504 alu.src[0].sel = ctx->temp_reg;
6505 alu.src[0].chan = 1 - (i % 2);
6506 } else {
6507 alu.src[0].sel = interp_gpr;
6508 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6509 }
6510 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6511 alu.src[1].chan = 0;
6512
6513 alu.last = i % 4 == 3;
6514 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6515
6516 r = r600_bytecode_add_alu(ctx->bc, &alu);
6517 if (r)
6518 return r;
6519 }
6520
6521 // INTERP can't swizzle dst
6522 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6523 for (i = 0; i <= lasti; i++) {
6524 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6525 continue;
6526
6527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6528 alu.op = ALU_OP1_MOV;
6529 alu.src[0].sel = tmp;
6530 alu.src[0].chan = ctx->src[0].swizzle[i];
6531 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6532 alu.dst.write = 1;
6533 alu.last = i == lasti;
6534 r = r600_bytecode_add_alu(ctx->bc, &alu);
6535 if (r)
6536 return r;
6537 }
6538
6539 return 0;
6540 }
6541
6542
6543 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6544 {
6545 struct r600_bytecode_alu alu;
6546 int i, r;
6547
6548 for (i = 0; i < 4; i++) {
6549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6550 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6551 alu.op = ALU_OP0_NOP;
6552 alu.dst.chan = i;
6553 } else {
6554 alu.op = ALU_OP1_MOV;
6555 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6556 alu.src[0].sel = ctx->temp_reg;
6557 alu.src[0].chan = i;
6558 }
6559 if (i == 3) {
6560 alu.last = 1;
6561 }
6562 r = r600_bytecode_add_alu(ctx->bc, &alu);
6563 if (r)
6564 return r;
6565 }
6566 return 0;
6567 }
6568
6569 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6570 unsigned temp, int chan,
6571 struct r600_bytecode_alu_src *bc_src,
6572 const struct r600_shader_src *shader_src)
6573 {
6574 struct r600_bytecode_alu alu;
6575 int r;
6576
6577 r600_bytecode_src(bc_src, shader_src, chan);
6578
6579 /* op3 operands don't support abs modifier */
6580 if (bc_src->abs) {
6581 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6583 alu.op = ALU_OP1_MOV;
6584 alu.dst.sel = temp;
6585 alu.dst.chan = chan;
6586 alu.dst.write = 1;
6587
6588 alu.src[0] = *bc_src;
6589 alu.last = true; // sufficient?
6590 r = r600_bytecode_add_alu(ctx->bc, &alu);
6591 if (r)
6592 return r;
6593
6594 memset(bc_src, 0, sizeof(*bc_src));
6595 bc_src->sel = temp;
6596 bc_src->chan = chan;
6597 }
6598 return 0;
6599 }
6600
6601 static int tgsi_op3(struct r600_shader_ctx *ctx)
6602 {
6603 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6604 struct r600_bytecode_alu alu;
6605 int i, j, r;
6606 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6607 int temp_regs[4];
6608 unsigned op = ctx->inst_info->op;
6609
6610 if (op == ALU_OP3_MULADD_IEEE &&
6611 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6612 op = ALU_OP3_MULADD;
6613
6614 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6615 temp_regs[j] = 0;
6616 if (ctx->src[j].abs)
6617 temp_regs[j] = r600_get_temp(ctx);
6618 }
6619 for (i = 0; i < lasti + 1; i++) {
6620 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6621 continue;
6622
6623 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6624 alu.op = op;
6625 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6626 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6627 if (r)
6628 return r;
6629 }
6630
6631 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6632 alu.dst.chan = i;
6633 alu.dst.write = 1;
6634 alu.is_op3 = 1;
6635 if (i == lasti) {
6636 alu.last = 1;
6637 }
6638 r = r600_bytecode_add_alu(ctx->bc, &alu);
6639 if (r)
6640 return r;
6641 }
6642 return 0;
6643 }
6644
6645 static int tgsi_dp(struct r600_shader_ctx *ctx)
6646 {
6647 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6648 struct r600_bytecode_alu alu;
6649 int i, j, r;
6650 unsigned op = ctx->inst_info->op;
6651 if (op == ALU_OP2_DOT4_IEEE &&
6652 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6653 op = ALU_OP2_DOT4;
6654
6655 for (i = 0; i < 4; i++) {
6656 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6657 alu.op = op;
6658 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6659 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6660 }
6661
6662 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6663 alu.dst.chan = i;
6664 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6665 /* handle some special cases */
6666 switch (inst->Instruction.Opcode) {
6667 case TGSI_OPCODE_DP2:
6668 if (i > 1) {
6669 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6670 alu.src[0].chan = alu.src[1].chan = 0;
6671 }
6672 break;
6673 case TGSI_OPCODE_DP3:
6674 if (i > 2) {
6675 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6676 alu.src[0].chan = alu.src[1].chan = 0;
6677 }
6678 break;
6679 default:
6680 break;
6681 }
6682 if (i == 3) {
6683 alu.last = 1;
6684 }
6685 r = r600_bytecode_add_alu(ctx->bc, &alu);
6686 if (r)
6687 return r;
6688 }
6689 return 0;
6690 }
6691
6692 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6693 unsigned index)
6694 {
6695 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6696 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6697 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6698 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6699 ctx->src[index].neg || ctx->src[index].abs ||
6700 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6701 }
6702
6703 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6704 unsigned index)
6705 {
6706 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6707 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6708 }
6709
6710 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6711 {
6712 struct r600_bytecode_vtx vtx;
6713 struct r600_bytecode_alu alu;
6714 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6715 int src_gpr, r, i;
6716 int id = tgsi_tex_get_src_gpr(ctx, 1);
6717
6718 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6719 if (src_requires_loading) {
6720 for (i = 0; i < 4; i++) {
6721 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6722 alu.op = ALU_OP1_MOV;
6723 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6724 alu.dst.sel = ctx->temp_reg;
6725 alu.dst.chan = i;
6726 if (i == 3)
6727 alu.last = 1;
6728 alu.dst.write = 1;
6729 r = r600_bytecode_add_alu(ctx->bc, &alu);
6730 if (r)
6731 return r;
6732 }
6733 src_gpr = ctx->temp_reg;
6734 }
6735
6736 memset(&vtx, 0, sizeof(vtx));
6737 vtx.op = FETCH_OP_VFETCH;
6738 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6739 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6740 vtx.src_gpr = src_gpr;
6741 vtx.mega_fetch_count = 16;
6742 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6743 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6744 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6745 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6746 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6747 vtx.use_const_fields = 1;
6748
6749 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6750 return r;
6751
6752 if (ctx->bc->chip_class >= EVERGREEN)
6753 return 0;
6754
6755 for (i = 0; i < 4; i++) {
6756 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6757 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6758 continue;
6759
6760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6761 alu.op = ALU_OP2_AND_INT;
6762
6763 alu.dst.chan = i;
6764 alu.dst.sel = vtx.dst_gpr;
6765 alu.dst.write = 1;
6766
6767 alu.src[0].sel = vtx.dst_gpr;
6768 alu.src[0].chan = i;
6769
6770 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6771 alu.src[1].sel += (id * 2);
6772 alu.src[1].chan = i % 4;
6773 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6774
6775 if (i == lasti)
6776 alu.last = 1;
6777 r = r600_bytecode_add_alu(ctx->bc, &alu);
6778 if (r)
6779 return r;
6780 }
6781
6782 if (inst->Dst[0].Register.WriteMask & 3) {
6783 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6784 alu.op = ALU_OP2_OR_INT;
6785
6786 alu.dst.chan = 3;
6787 alu.dst.sel = vtx.dst_gpr;
6788 alu.dst.write = 1;
6789
6790 alu.src[0].sel = vtx.dst_gpr;
6791 alu.src[0].chan = 3;
6792
6793 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6794 alu.src[1].chan = 0;
6795 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6796
6797 alu.last = 1;
6798 r = r600_bytecode_add_alu(ctx->bc, &alu);
6799 if (r)
6800 return r;
6801 }
6802 return 0;
6803 }
6804
6805 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6806 {
6807 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6808 struct r600_bytecode_alu alu;
6809 int r;
6810 int id = tgsi_tex_get_src_gpr(ctx, 1);
6811
6812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6813 alu.op = ALU_OP1_MOV;
6814 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6815 if (ctx->bc->chip_class >= EVERGREEN) {
6816 /* channel 0 or 2 of each word */
6817 alu.src[0].sel += (id / 2);
6818 alu.src[0].chan = (id % 2) * 2;
6819 } else {
6820 /* r600 we have them at channel 2 of the second dword */
6821 alu.src[0].sel += (id * 2) + 1;
6822 alu.src[0].chan = 1;
6823 }
6824 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6825 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6826 alu.last = 1;
6827 r = r600_bytecode_add_alu(ctx->bc, &alu);
6828 if (r)
6829 return r;
6830 return 0;
6831 }
6832
6833 static int tgsi_tex(struct r600_shader_ctx *ctx)
6834 {
6835 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6836 struct r600_bytecode_tex tex;
6837 struct r600_bytecode_alu alu;
6838 unsigned src_gpr;
6839 int r, i, j;
6840 int opcode;
6841 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6842 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6843 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6844 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6845
6846 bool txf_add_offsets = inst->Texture.NumOffsets &&
6847 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6848 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6849
6850 /* Texture fetch instructions can only use gprs as source.
6851 * Also they cannot negate the source or take the absolute value */
6852 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6853 tgsi_tex_src_requires_loading(ctx, 0)) ||
6854 read_compressed_msaa || txf_add_offsets;
6855
6856 boolean src_loaded = FALSE;
6857 unsigned sampler_src_reg = 1;
6858 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6859 boolean has_txq_cube_array_z = false;
6860 unsigned sampler_index_mode;
6861
6862 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6863 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6864 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6865 if (inst->Dst[0].Register.WriteMask & 4) {
6866 ctx->shader->has_txq_cube_array_z_comp = true;
6867 has_txq_cube_array_z = true;
6868 }
6869
6870 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6871 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6872 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6873 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6874 sampler_src_reg = 2;
6875
6876 /* TGSI moves the sampler to src reg 3 for TXD */
6877 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6878 sampler_src_reg = 3;
6879
6880 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6881
6882 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6883
6884 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6885 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6886 ctx->shader->uses_tex_buffers = true;
6887 return r600_do_buffer_txq(ctx);
6888 }
6889 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6890 if (ctx->bc->chip_class < EVERGREEN)
6891 ctx->shader->uses_tex_buffers = true;
6892 return do_vtx_fetch_inst(ctx, src_requires_loading);
6893 }
6894 }
6895
6896 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6897 int out_chan;
6898 /* Add perspective divide */
6899 if (ctx->bc->chip_class == CAYMAN) {
6900 out_chan = 2;
6901 for (i = 0; i < 3; i++) {
6902 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6903 alu.op = ALU_OP1_RECIP_IEEE;
6904 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6905
6906 alu.dst.sel = ctx->temp_reg;
6907 alu.dst.chan = i;
6908 if (i == 2)
6909 alu.last = 1;
6910 if (out_chan == i)
6911 alu.dst.write = 1;
6912 r = r600_bytecode_add_alu(ctx->bc, &alu);
6913 if (r)
6914 return r;
6915 }
6916
6917 } else {
6918 out_chan = 3;
6919 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6920 alu.op = ALU_OP1_RECIP_IEEE;
6921 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6922
6923 alu.dst.sel = ctx->temp_reg;
6924 alu.dst.chan = out_chan;
6925 alu.last = 1;
6926 alu.dst.write = 1;
6927 r = r600_bytecode_add_alu(ctx->bc, &alu);
6928 if (r)
6929 return r;
6930 }
6931
6932 for (i = 0; i < 3; i++) {
6933 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6934 alu.op = ALU_OP2_MUL;
6935 alu.src[0].sel = ctx->temp_reg;
6936 alu.src[0].chan = out_chan;
6937 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6938 alu.dst.sel = ctx->temp_reg;
6939 alu.dst.chan = i;
6940 alu.dst.write = 1;
6941 r = r600_bytecode_add_alu(ctx->bc, &alu);
6942 if (r)
6943 return r;
6944 }
6945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6946 alu.op = ALU_OP1_MOV;
6947 alu.src[0].sel = V_SQ_ALU_SRC_1;
6948 alu.src[0].chan = 0;
6949 alu.dst.sel = ctx->temp_reg;
6950 alu.dst.chan = 3;
6951 alu.last = 1;
6952 alu.dst.write = 1;
6953 r = r600_bytecode_add_alu(ctx->bc, &alu);
6954 if (r)
6955 return r;
6956 src_loaded = TRUE;
6957 src_gpr = ctx->temp_reg;
6958 }
6959
6960
6961 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6962 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6963 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6964 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6965 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
6966
6967 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6968 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6969
6970 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6971 for (i = 0; i < 4; i++) {
6972 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6973 alu.op = ALU_OP2_CUBE;
6974 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6975 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6976 alu.dst.sel = ctx->temp_reg;
6977 alu.dst.chan = i;
6978 if (i == 3)
6979 alu.last = 1;
6980 alu.dst.write = 1;
6981 r = r600_bytecode_add_alu(ctx->bc, &alu);
6982 if (r)
6983 return r;
6984 }
6985
6986 /* tmp1.z = RCP_e(|tmp1.z|) */
6987 if (ctx->bc->chip_class == CAYMAN) {
6988 for (i = 0; i < 3; i++) {
6989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6990 alu.op = ALU_OP1_RECIP_IEEE;
6991 alu.src[0].sel = ctx->temp_reg;
6992 alu.src[0].chan = 2;
6993 alu.src[0].abs = 1;
6994 alu.dst.sel = ctx->temp_reg;
6995 alu.dst.chan = i;
6996 if (i == 2)
6997 alu.dst.write = 1;
6998 if (i == 2)
6999 alu.last = 1;
7000 r = r600_bytecode_add_alu(ctx->bc, &alu);
7001 if (r)
7002 return r;
7003 }
7004 } else {
7005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7006 alu.op = ALU_OP1_RECIP_IEEE;
7007 alu.src[0].sel = ctx->temp_reg;
7008 alu.src[0].chan = 2;
7009 alu.src[0].abs = 1;
7010 alu.dst.sel = ctx->temp_reg;
7011 alu.dst.chan = 2;
7012 alu.dst.write = 1;
7013 alu.last = 1;
7014 r = r600_bytecode_add_alu(ctx->bc, &alu);
7015 if (r)
7016 return r;
7017 }
7018
7019 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7020 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7021 * muladd has no writemask, have to use another temp
7022 */
7023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7024 alu.op = ALU_OP3_MULADD;
7025 alu.is_op3 = 1;
7026
7027 alu.src[0].sel = ctx->temp_reg;
7028 alu.src[0].chan = 0;
7029 alu.src[1].sel = ctx->temp_reg;
7030 alu.src[1].chan = 2;
7031
7032 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7033 alu.src[2].chan = 0;
7034 alu.src[2].value = u_bitcast_f2u(1.5f);
7035
7036 alu.dst.sel = ctx->temp_reg;
7037 alu.dst.chan = 0;
7038 alu.dst.write = 1;
7039
7040 r = r600_bytecode_add_alu(ctx->bc, &alu);
7041 if (r)
7042 return r;
7043
7044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7045 alu.op = ALU_OP3_MULADD;
7046 alu.is_op3 = 1;
7047
7048 alu.src[0].sel = ctx->temp_reg;
7049 alu.src[0].chan = 1;
7050 alu.src[1].sel = ctx->temp_reg;
7051 alu.src[1].chan = 2;
7052
7053 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7054 alu.src[2].chan = 0;
7055 alu.src[2].value = u_bitcast_f2u(1.5f);
7056
7057 alu.dst.sel = ctx->temp_reg;
7058 alu.dst.chan = 1;
7059 alu.dst.write = 1;
7060
7061 alu.last = 1;
7062 r = r600_bytecode_add_alu(ctx->bc, &alu);
7063 if (r)
7064 return r;
7065 /* write initial compare value into Z component
7066 - W src 0 for shadow cube
7067 - X src 1 for shadow cube array */
7068 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7069 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7070 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7071 alu.op = ALU_OP1_MOV;
7072 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7073 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7074 else
7075 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7076 alu.dst.sel = ctx->temp_reg;
7077 alu.dst.chan = 2;
7078 alu.dst.write = 1;
7079 alu.last = 1;
7080 r = r600_bytecode_add_alu(ctx->bc, &alu);
7081 if (r)
7082 return r;
7083 }
7084
7085 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7086 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7087 if (ctx->bc->chip_class >= EVERGREEN) {
7088 int mytmp = r600_get_temp(ctx);
7089 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7090 alu.op = ALU_OP1_MOV;
7091 alu.src[0].sel = ctx->temp_reg;
7092 alu.src[0].chan = 3;
7093 alu.dst.sel = mytmp;
7094 alu.dst.chan = 0;
7095 alu.dst.write = 1;
7096 alu.last = 1;
7097 r = r600_bytecode_add_alu(ctx->bc, &alu);
7098 if (r)
7099 return r;
7100
7101 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7102 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7103 alu.op = ALU_OP3_MULADD;
7104 alu.is_op3 = 1;
7105 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7106 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7107 alu.src[1].chan = 0;
7108 alu.src[1].value = u_bitcast_f2u(8.0f);
7109 alu.src[2].sel = mytmp;
7110 alu.src[2].chan = 0;
7111 alu.dst.sel = ctx->temp_reg;
7112 alu.dst.chan = 3;
7113 alu.dst.write = 1;
7114 alu.last = 1;
7115 r = r600_bytecode_add_alu(ctx->bc, &alu);
7116 if (r)
7117 return r;
7118 } else if (ctx->bc->chip_class < EVERGREEN) {
7119 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7120 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7121 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7122 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7123 tex.src_gpr = r600_get_temp(ctx);
7124 tex.src_sel_x = 0;
7125 tex.src_sel_y = 0;
7126 tex.src_sel_z = 0;
7127 tex.src_sel_w = 0;
7128 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7129 tex.coord_type_x = 1;
7130 tex.coord_type_y = 1;
7131 tex.coord_type_z = 1;
7132 tex.coord_type_w = 1;
7133 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7134 alu.op = ALU_OP1_MOV;
7135 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7136 alu.dst.sel = tex.src_gpr;
7137 alu.dst.chan = 0;
7138 alu.last = 1;
7139 alu.dst.write = 1;
7140 r = r600_bytecode_add_alu(ctx->bc, &alu);
7141 if (r)
7142 return r;
7143
7144 r = r600_bytecode_add_tex(ctx->bc, &tex);
7145 if (r)
7146 return r;
7147 }
7148
7149 }
7150
7151 /* for cube forms of lod and bias we need to route things */
7152 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7153 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7154 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7155 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7156 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7157 alu.op = ALU_OP1_MOV;
7158 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7159 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7160 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7161 else
7162 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7163 alu.dst.sel = ctx->temp_reg;
7164 alu.dst.chan = 2;
7165 alu.last = 1;
7166 alu.dst.write = 1;
7167 r = r600_bytecode_add_alu(ctx->bc, &alu);
7168 if (r)
7169 return r;
7170 }
7171
7172 src_loaded = TRUE;
7173 src_gpr = ctx->temp_reg;
7174 }
7175
7176 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7177 int temp_h = 0, temp_v = 0;
7178 int start_val = 0;
7179
7180 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7181 if (src_loaded == TRUE)
7182 start_val = 1;
7183 else
7184 src_loaded = TRUE;
7185 for (i = start_val; i < 3; i++) {
7186 int treg = r600_get_temp(ctx);
7187
7188 if (i == 0)
7189 src_gpr = treg;
7190 else if (i == 1)
7191 temp_h = treg;
7192 else
7193 temp_v = treg;
7194
7195 for (j = 0; j < 4; j++) {
7196 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7197 alu.op = ALU_OP1_MOV;
7198 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7199 alu.dst.sel = treg;
7200 alu.dst.chan = j;
7201 if (j == 3)
7202 alu.last = 1;
7203 alu.dst.write = 1;
7204 r = r600_bytecode_add_alu(ctx->bc, &alu);
7205 if (r)
7206 return r;
7207 }
7208 }
7209 for (i = 1; i < 3; i++) {
7210 /* set gradients h/v */
7211 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7212 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7213 FETCH_OP_SET_GRADIENTS_V;
7214 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7215 tex.sampler_index_mode = sampler_index_mode;
7216 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7217 tex.resource_index_mode = sampler_index_mode;
7218
7219 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7220 tex.src_sel_x = 0;
7221 tex.src_sel_y = 1;
7222 tex.src_sel_z = 2;
7223 tex.src_sel_w = 3;
7224
7225 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7226 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7227 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7228 tex.coord_type_x = 1;
7229 tex.coord_type_y = 1;
7230 tex.coord_type_z = 1;
7231 tex.coord_type_w = 1;
7232 }
7233 r = r600_bytecode_add_tex(ctx->bc, &tex);
7234 if (r)
7235 return r;
7236 }
7237 }
7238
7239 if (src_requires_loading && !src_loaded) {
7240 for (i = 0; i < 4; i++) {
7241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7242 alu.op = ALU_OP1_MOV;
7243 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7244 alu.dst.sel = ctx->temp_reg;
7245 alu.dst.chan = i;
7246 if (i == 3)
7247 alu.last = 1;
7248 alu.dst.write = 1;
7249 r = r600_bytecode_add_alu(ctx->bc, &alu);
7250 if (r)
7251 return r;
7252 }
7253 src_loaded = TRUE;
7254 src_gpr = ctx->temp_reg;
7255 }
7256
7257 /* get offset values */
7258 if (inst->Texture.NumOffsets) {
7259 assert(inst->Texture.NumOffsets == 1);
7260
7261 /* The texture offset feature doesn't work with the TXF instruction
7262 * and must be emulated by adding the offset to the texture coordinates. */
7263 if (txf_add_offsets) {
7264 const struct tgsi_texture_offset *off = inst->TexOffsets;
7265
7266 switch (inst->Texture.Texture) {
7267 case TGSI_TEXTURE_3D:
7268 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7269 alu.op = ALU_OP2_ADD_INT;
7270 alu.src[0].sel = src_gpr;
7271 alu.src[0].chan = 2;
7272 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7273 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7274 alu.dst.sel = src_gpr;
7275 alu.dst.chan = 2;
7276 alu.dst.write = 1;
7277 alu.last = 1;
7278 r = r600_bytecode_add_alu(ctx->bc, &alu);
7279 if (r)
7280 return r;
7281 /* fall through */
7282
7283 case TGSI_TEXTURE_2D:
7284 case TGSI_TEXTURE_SHADOW2D:
7285 case TGSI_TEXTURE_RECT:
7286 case TGSI_TEXTURE_SHADOWRECT:
7287 case TGSI_TEXTURE_2D_ARRAY:
7288 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7290 alu.op = ALU_OP2_ADD_INT;
7291 alu.src[0].sel = src_gpr;
7292 alu.src[0].chan = 1;
7293 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7294 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7295 alu.dst.sel = src_gpr;
7296 alu.dst.chan = 1;
7297 alu.dst.write = 1;
7298 alu.last = 1;
7299 r = r600_bytecode_add_alu(ctx->bc, &alu);
7300 if (r)
7301 return r;
7302 /* fall through */
7303
7304 case TGSI_TEXTURE_1D:
7305 case TGSI_TEXTURE_SHADOW1D:
7306 case TGSI_TEXTURE_1D_ARRAY:
7307 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7309 alu.op = ALU_OP2_ADD_INT;
7310 alu.src[0].sel = src_gpr;
7311 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7312 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7313 alu.dst.sel = src_gpr;
7314 alu.dst.write = 1;
7315 alu.last = 1;
7316 r = r600_bytecode_add_alu(ctx->bc, &alu);
7317 if (r)
7318 return r;
7319 break;
7320 /* texture offsets do not apply to other texture targets */
7321 }
7322 } else {
7323 switch (inst->Texture.Texture) {
7324 case TGSI_TEXTURE_3D:
7325 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7326 /* fallthrough */
7327 case TGSI_TEXTURE_2D:
7328 case TGSI_TEXTURE_SHADOW2D:
7329 case TGSI_TEXTURE_RECT:
7330 case TGSI_TEXTURE_SHADOWRECT:
7331 case TGSI_TEXTURE_2D_ARRAY:
7332 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7333 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7334 /* fallthrough */
7335 case TGSI_TEXTURE_1D:
7336 case TGSI_TEXTURE_SHADOW1D:
7337 case TGSI_TEXTURE_1D_ARRAY:
7338 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7339 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7340 }
7341 }
7342 }
7343
7344 /* Obtain the sample index for reading a compressed MSAA color texture.
7345 * To read the FMASK, we use the ldfptr instruction, which tells us
7346 * where the samples are stored.
7347 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7348 * which is the identity mapping. Each nibble says which physical sample
7349 * should be fetched to get that sample.
7350 *
7351 * Assume src.z contains the sample index. It should be modified like this:
7352 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7353 * Then fetch the texel with src.
7354 */
7355 if (read_compressed_msaa) {
7356 unsigned sample_chan = 3;
7357 unsigned temp = r600_get_temp(ctx);
7358 assert(src_loaded);
7359
7360 /* temp.w = ldfptr() */
7361 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7362 tex.op = FETCH_OP_LD;
7363 tex.inst_mod = 1; /* to indicate this is ldfptr */
7364 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7365 tex.sampler_index_mode = sampler_index_mode;
7366 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7367 tex.resource_index_mode = sampler_index_mode;
7368 tex.src_gpr = src_gpr;
7369 tex.dst_gpr = temp;
7370 tex.dst_sel_x = 7; /* mask out these components */
7371 tex.dst_sel_y = 7;
7372 tex.dst_sel_z = 7;
7373 tex.dst_sel_w = 0; /* store X */
7374 tex.src_sel_x = 0;
7375 tex.src_sel_y = 1;
7376 tex.src_sel_z = 2;
7377 tex.src_sel_w = 3;
7378 tex.offset_x = offset_x;
7379 tex.offset_y = offset_y;
7380 tex.offset_z = offset_z;
7381 r = r600_bytecode_add_tex(ctx->bc, &tex);
7382 if (r)
7383 return r;
7384
7385 /* temp.x = sample_index*4 */
7386 if (ctx->bc->chip_class == CAYMAN) {
7387 for (i = 0 ; i < 4; i++) {
7388 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7389 alu.op = ALU_OP2_MULLO_INT;
7390 alu.src[0].sel = src_gpr;
7391 alu.src[0].chan = sample_chan;
7392 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7393 alu.src[1].value = 4;
7394 alu.dst.sel = temp;
7395 alu.dst.chan = i;
7396 alu.dst.write = i == 0;
7397 if (i == 3)
7398 alu.last = 1;
7399 r = r600_bytecode_add_alu(ctx->bc, &alu);
7400 if (r)
7401 return r;
7402 }
7403 } else {
7404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7405 alu.op = ALU_OP2_MULLO_INT;
7406 alu.src[0].sel = src_gpr;
7407 alu.src[0].chan = sample_chan;
7408 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7409 alu.src[1].value = 4;
7410 alu.dst.sel = temp;
7411 alu.dst.chan = 0;
7412 alu.dst.write = 1;
7413 alu.last = 1;
7414 r = r600_bytecode_add_alu(ctx->bc, &alu);
7415 if (r)
7416 return r;
7417 }
7418
7419 /* sample_index = temp.w >> temp.x */
7420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7421 alu.op = ALU_OP2_LSHR_INT;
7422 alu.src[0].sel = temp;
7423 alu.src[0].chan = 3;
7424 alu.src[1].sel = temp;
7425 alu.src[1].chan = 0;
7426 alu.dst.sel = src_gpr;
7427 alu.dst.chan = sample_chan;
7428 alu.dst.write = 1;
7429 alu.last = 1;
7430 r = r600_bytecode_add_alu(ctx->bc, &alu);
7431 if (r)
7432 return r;
7433
7434 /* sample_index & 0xF */
7435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7436 alu.op = ALU_OP2_AND_INT;
7437 alu.src[0].sel = src_gpr;
7438 alu.src[0].chan = sample_chan;
7439 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7440 alu.src[1].value = 0xF;
7441 alu.dst.sel = src_gpr;
7442 alu.dst.chan = sample_chan;
7443 alu.dst.write = 1;
7444 alu.last = 1;
7445 r = r600_bytecode_add_alu(ctx->bc, &alu);
7446 if (r)
7447 return r;
7448 #if 0
7449 /* visualize the FMASK */
7450 for (i = 0; i < 4; i++) {
7451 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7452 alu.op = ALU_OP1_INT_TO_FLT;
7453 alu.src[0].sel = src_gpr;
7454 alu.src[0].chan = sample_chan;
7455 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7456 alu.dst.chan = i;
7457 alu.dst.write = 1;
7458 alu.last = 1;
7459 r = r600_bytecode_add_alu(ctx->bc, &alu);
7460 if (r)
7461 return r;
7462 }
7463 return 0;
7464 #endif
7465 }
7466
7467 /* does this shader want a num layers from TXQ for a cube array? */
7468 if (has_txq_cube_array_z) {
7469 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7470
7471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7472 alu.op = ALU_OP1_MOV;
7473
7474 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7475 if (ctx->bc->chip_class >= EVERGREEN) {
7476 /* channel 1 or 3 of each word */
7477 alu.src[0].sel += (id / 2);
7478 alu.src[0].chan = ((id % 2) * 2) + 1;
7479 } else {
7480 /* r600 we have them at channel 2 of the second dword */
7481 alu.src[0].sel += (id * 2) + 1;
7482 alu.src[0].chan = 2;
7483 }
7484 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7485 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7486 alu.last = 1;
7487 r = r600_bytecode_add_alu(ctx->bc, &alu);
7488 if (r)
7489 return r;
7490 /* disable writemask from texture instruction */
7491 inst->Dst[0].Register.WriteMask &= ~4;
7492 }
7493
7494 opcode = ctx->inst_info->op;
7495 if (opcode == FETCH_OP_GATHER4 &&
7496 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7497 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7498 opcode = FETCH_OP_GATHER4_O;
7499
7500 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7501 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7502 encoded in the instruction are ignored. */
7503 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7504 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7505 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7506 tex.sampler_index_mode = sampler_index_mode;
7507 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7508 tex.resource_index_mode = sampler_index_mode;
7509
7510 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7511 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7512 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7513 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7514 tex.src_sel_w = 4;
7515
7516 tex.dst_sel_x = 7;
7517 tex.dst_sel_y = 7;
7518 tex.dst_sel_z = 7;
7519 tex.dst_sel_w = 7;
7520
7521 r = r600_bytecode_add_tex(ctx->bc, &tex);
7522 if (r)
7523 return r;
7524 }
7525
7526 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7527 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7528 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7529 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7530 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7531 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7532 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7533 switch (opcode) {
7534 case FETCH_OP_SAMPLE:
7535 opcode = FETCH_OP_SAMPLE_C;
7536 break;
7537 case FETCH_OP_SAMPLE_L:
7538 opcode = FETCH_OP_SAMPLE_C_L;
7539 break;
7540 case FETCH_OP_SAMPLE_LB:
7541 opcode = FETCH_OP_SAMPLE_C_LB;
7542 break;
7543 case FETCH_OP_SAMPLE_G:
7544 opcode = FETCH_OP_SAMPLE_C_G;
7545 break;
7546 /* Texture gather variants */
7547 case FETCH_OP_GATHER4:
7548 opcode = FETCH_OP_GATHER4_C;
7549 break;
7550 case FETCH_OP_GATHER4_O:
7551 opcode = FETCH_OP_GATHER4_C_O;
7552 break;
7553 }
7554 }
7555
7556 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7557 tex.op = opcode;
7558
7559 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7560 tex.sampler_index_mode = sampler_index_mode;
7561 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7562 tex.resource_index_mode = sampler_index_mode;
7563 tex.src_gpr = src_gpr;
7564 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7565
7566 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7567 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7568 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7569 }
7570
7571 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7572 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7573 tex.inst_mod = texture_component_select;
7574
7575 if (ctx->bc->chip_class == CAYMAN) {
7576 /* GATHER4 result order is different from TGSI TG4 */
7577 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7578 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7579 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7580 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7581 } else {
7582 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7583 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7584 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7585 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7586 }
7587 }
7588 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7589 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7590 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7591 tex.dst_sel_z = 7;
7592 tex.dst_sel_w = 7;
7593 }
7594 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7595 tex.dst_sel_x = 3;
7596 tex.dst_sel_y = 7;
7597 tex.dst_sel_z = 7;
7598 tex.dst_sel_w = 7;
7599 }
7600 else {
7601 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7602 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7603 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7604 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7605 }
7606
7607
7608 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7609 tex.src_sel_x = 4;
7610 tex.src_sel_y = 4;
7611 tex.src_sel_z = 4;
7612 tex.src_sel_w = 4;
7613 } else if (src_loaded) {
7614 tex.src_sel_x = 0;
7615 tex.src_sel_y = 1;
7616 tex.src_sel_z = 2;
7617 tex.src_sel_w = 3;
7618 } else {
7619 tex.src_sel_x = ctx->src[0].swizzle[0];
7620 tex.src_sel_y = ctx->src[0].swizzle[1];
7621 tex.src_sel_z = ctx->src[0].swizzle[2];
7622 tex.src_sel_w = ctx->src[0].swizzle[3];
7623 tex.src_rel = ctx->src[0].rel;
7624 }
7625
7626 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7627 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7628 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7629 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7630 tex.src_sel_x = 1;
7631 tex.src_sel_y = 0;
7632 tex.src_sel_z = 3;
7633 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7634 }
7635
7636 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7637 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7638 tex.coord_type_x = 1;
7639 tex.coord_type_y = 1;
7640 }
7641 tex.coord_type_z = 1;
7642 tex.coord_type_w = 1;
7643
7644 tex.offset_x = offset_x;
7645 tex.offset_y = offset_y;
7646 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7647 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7648 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7649 tex.offset_z = 0;
7650 }
7651 else {
7652 tex.offset_z = offset_z;
7653 }
7654
7655 /* Put the depth for comparison in W.
7656 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7657 * Some instructions expect the depth in Z. */
7658 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7659 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7660 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7661 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7662 opcode != FETCH_OP_SAMPLE_C_L &&
7663 opcode != FETCH_OP_SAMPLE_C_LB) {
7664 tex.src_sel_w = tex.src_sel_z;
7665 }
7666
7667 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7668 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7669 if (opcode == FETCH_OP_SAMPLE_C_L ||
7670 opcode == FETCH_OP_SAMPLE_C_LB) {
7671 /* the array index is read from Y */
7672 tex.coord_type_y = 0;
7673 } else {
7674 /* the array index is read from Z */
7675 tex.coord_type_z = 0;
7676 tex.src_sel_z = tex.src_sel_y;
7677 }
7678 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7679 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7680 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7681 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7682 (ctx->bc->chip_class >= EVERGREEN)))
7683 /* the array index is read from Z */
7684 tex.coord_type_z = 0;
7685
7686 /* mask unused source components */
7687 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7688 switch (inst->Texture.Texture) {
7689 case TGSI_TEXTURE_2D:
7690 case TGSI_TEXTURE_RECT:
7691 tex.src_sel_z = 7;
7692 tex.src_sel_w = 7;
7693 break;
7694 case TGSI_TEXTURE_1D_ARRAY:
7695 tex.src_sel_y = 7;
7696 tex.src_sel_w = 7;
7697 break;
7698 case TGSI_TEXTURE_1D:
7699 tex.src_sel_y = 7;
7700 tex.src_sel_z = 7;
7701 tex.src_sel_w = 7;
7702 break;
7703 }
7704 }
7705
7706 r = r600_bytecode_add_tex(ctx->bc, &tex);
7707 if (r)
7708 return r;
7709
7710 /* add shadow ambient support - gallium doesn't do it yet */
7711 return 0;
7712 }
7713
7714 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7715 struct tgsi_full_src_register *src)
7716 {
7717 int i;
7718
7719 if (src->Register.Indirect) {
7720 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7721 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7722 return ctx->shader->atomics[i].hw_idx;
7723 }
7724 } else {
7725 uint32_t index = src->Register.Index;
7726 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7727 if (ctx->shader->atomics[i].buffer_id != src->Dimension.Index)
7728 continue;
7729 if (index > ctx->shader->atomics[i].end)
7730 continue;
7731 if (index < ctx->shader->atomics[i].start)
7732 continue;
7733 uint32_t offset = (index - ctx->shader->atomics[i].start);
7734 return ctx->shader->atomics[i].hw_idx + offset;
7735 }
7736 }
7737 assert(0);
7738 return -1;
7739 }
7740
7741
7742 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7743 {
7744 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7745 int r;
7746 struct r600_bytecode_gds gds;
7747 int uav_id = 0;
7748 int uav_index_mode = 0;
7749
7750 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7751
7752 if (inst->Src[0].Register.Indirect)
7753 uav_index_mode = 2;
7754
7755 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7756 gds.op = FETCH_OP_GDS_READ_RET;
7757 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7758 gds.uav_id = uav_id;
7759 gds.uav_index_mode = uav_index_mode;
7760 gds.src_gpr = ctx->temp_reg;
7761 gds.src_sel_x = 4;
7762 gds.src_sel_y = 4;
7763 gds.src_sel_z = 4;
7764 gds.dst_sel_x = 0;
7765 gds.dst_sel_y = 7;
7766 gds.dst_sel_z = 7;
7767 gds.dst_sel_w = 7;
7768 gds.src_gpr2 = ctx->temp_reg;
7769 gds.alloc_consume = 1;
7770 r = r600_bytecode_add_gds(ctx->bc, &gds);
7771 if (r)
7772 return r;
7773
7774 ctx->bc->cf_last->vpm = 1;
7775 return 0;
7776 }
7777
7778 static int tgsi_load(struct r600_shader_ctx *ctx)
7779 {
7780 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7781 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7782 return tgsi_load_gds(ctx);
7783 return 0;
7784 }
7785
7786 static int get_gds_op(int opcode)
7787 {
7788 switch (opcode) {
7789 case TGSI_OPCODE_ATOMUADD:
7790 return FETCH_OP_GDS_ADD_RET;
7791 case TGSI_OPCODE_ATOMAND:
7792 return FETCH_OP_GDS_AND_RET;
7793 case TGSI_OPCODE_ATOMOR:
7794 return FETCH_OP_GDS_OR_RET;
7795 case TGSI_OPCODE_ATOMXOR:
7796 return FETCH_OP_GDS_XOR_RET;
7797 case TGSI_OPCODE_ATOMUMIN:
7798 return FETCH_OP_GDS_MIN_UINT_RET;
7799 case TGSI_OPCODE_ATOMUMAX:
7800 return FETCH_OP_GDS_MAX_UINT_RET;
7801 case TGSI_OPCODE_ATOMXCHG:
7802 return FETCH_OP_GDS_XCHG_RET;
7803 case TGSI_OPCODE_ATOMCAS:
7804 return FETCH_OP_GDS_CMP_XCHG_RET;
7805 default:
7806 return -1;
7807 }
7808 }
7809
7810 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
7811 {
7812 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7813 struct r600_bytecode_gds gds;
7814 struct r600_bytecode_alu alu;
7815 int gds_op = get_gds_op(inst->Instruction.Opcode);
7816 int r;
7817 int uav_id = 0;
7818 int uav_index_mode = 0;
7819
7820 if (gds_op == -1) {
7821 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
7822 return -1;
7823 }
7824
7825 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7826
7827 if (inst->Src[0].Register.Indirect)
7828 uav_index_mode = 2;
7829
7830 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
7831 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
7832 int abs_value = abs(value);
7833 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
7834 gds_op = FETCH_OP_GDS_SUB_RET;
7835 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7836 alu.op = ALU_OP1_MOV;
7837 alu.dst.sel = ctx->temp_reg;
7838 alu.dst.chan = 0;
7839 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
7840 alu.src[0].value = abs_value;
7841 alu.last = 1;
7842 alu.dst.write = 1;
7843 r = r600_bytecode_add_alu(ctx->bc, &alu);
7844 if (r)
7845 return r;
7846 } else {
7847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7848 alu.op = ALU_OP1_MOV;
7849 alu.dst.sel = ctx->temp_reg;
7850 alu.dst.chan = 0;
7851 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
7852 alu.last = 1;
7853 alu.dst.write = 1;
7854 r = r600_bytecode_add_alu(ctx->bc, &alu);
7855 if (r)
7856 return r;
7857 }
7858
7859 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7860 gds.op = gds_op;
7861 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7862 gds.uav_id = uav_id;
7863 gds.uav_index_mode = uav_index_mode;
7864 gds.src_gpr = ctx->temp_reg;
7865 gds.src_gpr2 = ctx->temp_reg;
7866 gds.src_sel_x = 4;
7867 gds.src_sel_y = 0;
7868 gds.src_sel_z = 4;
7869 gds.dst_sel_x = 0;
7870 gds.dst_sel_y = 7;
7871 gds.dst_sel_z = 7;
7872 gds.dst_sel_w = 7;
7873 gds.alloc_consume = 1;
7874 r = r600_bytecode_add_gds(ctx->bc, &gds);
7875 if (r)
7876 return r;
7877 ctx->bc->cf_last->vpm = 1;
7878 return 0;
7879 }
7880
7881 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
7882 {
7883 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7884 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7885 return tgsi_atomic_op_gds(ctx);
7886 return 0;
7887 }
7888
7889 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7890 {
7891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7892 struct r600_bytecode_alu alu;
7893 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7894 unsigned i, temp_regs[2];
7895 int r;
7896
7897 /* optimize if it's just an equal balance */
7898 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7899 for (i = 0; i < lasti + 1; i++) {
7900 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7901 continue;
7902
7903 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7904 alu.op = ALU_OP2_ADD;
7905 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7906 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7907 alu.omod = 3;
7908 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7909 alu.dst.chan = i;
7910 if (i == lasti) {
7911 alu.last = 1;
7912 }
7913 r = r600_bytecode_add_alu(ctx->bc, &alu);
7914 if (r)
7915 return r;
7916 }
7917 return 0;
7918 }
7919
7920 /* 1 - src0 */
7921 for (i = 0; i < lasti + 1; i++) {
7922 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7923 continue;
7924
7925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7926 alu.op = ALU_OP2_ADD;
7927 alu.src[0].sel = V_SQ_ALU_SRC_1;
7928 alu.src[0].chan = 0;
7929 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7930 r600_bytecode_src_toggle_neg(&alu.src[1]);
7931 alu.dst.sel = ctx->temp_reg;
7932 alu.dst.chan = i;
7933 if (i == lasti) {
7934 alu.last = 1;
7935 }
7936 alu.dst.write = 1;
7937 r = r600_bytecode_add_alu(ctx->bc, &alu);
7938 if (r)
7939 return r;
7940 }
7941
7942 /* (1 - src0) * src2 */
7943 for (i = 0; i < lasti + 1; i++) {
7944 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7945 continue;
7946
7947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7948 alu.op = ALU_OP2_MUL;
7949 alu.src[0].sel = ctx->temp_reg;
7950 alu.src[0].chan = i;
7951 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7952 alu.dst.sel = ctx->temp_reg;
7953 alu.dst.chan = i;
7954 if (i == lasti) {
7955 alu.last = 1;
7956 }
7957 alu.dst.write = 1;
7958 r = r600_bytecode_add_alu(ctx->bc, &alu);
7959 if (r)
7960 return r;
7961 }
7962
7963 /* src0 * src1 + (1 - src0) * src2 */
7964 if (ctx->src[0].abs)
7965 temp_regs[0] = r600_get_temp(ctx);
7966 else
7967 temp_regs[0] = 0;
7968 if (ctx->src[1].abs)
7969 temp_regs[1] = r600_get_temp(ctx);
7970 else
7971 temp_regs[1] = 0;
7972
7973 for (i = 0; i < lasti + 1; i++) {
7974 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7975 continue;
7976
7977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7978 alu.op = ALU_OP3_MULADD;
7979 alu.is_op3 = 1;
7980 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7981 if (r)
7982 return r;
7983 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7984 if (r)
7985 return r;
7986 alu.src[2].sel = ctx->temp_reg;
7987 alu.src[2].chan = i;
7988
7989 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7990 alu.dst.chan = i;
7991 if (i == lasti) {
7992 alu.last = 1;
7993 }
7994 r = r600_bytecode_add_alu(ctx->bc, &alu);
7995 if (r)
7996 return r;
7997 }
7998 return 0;
7999 }
8000
8001 static int tgsi_cmp(struct r600_shader_ctx *ctx)
8002 {
8003 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8004 struct r600_bytecode_alu alu;
8005 int i, r, j;
8006 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8007 int temp_regs[3];
8008 unsigned op;
8009
8010 if (ctx->src[0].abs && ctx->src[0].neg) {
8011 op = ALU_OP3_CNDE;
8012 ctx->src[0].abs = 0;
8013 ctx->src[0].neg = 0;
8014 } else {
8015 op = ALU_OP3_CNDGE;
8016 }
8017
8018 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
8019 temp_regs[j] = 0;
8020 if (ctx->src[j].abs)
8021 temp_regs[j] = r600_get_temp(ctx);
8022 }
8023
8024 for (i = 0; i < lasti + 1; i++) {
8025 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8026 continue;
8027
8028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8029 alu.op = op;
8030 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8031 if (r)
8032 return r;
8033 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
8034 if (r)
8035 return r;
8036 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
8037 if (r)
8038 return r;
8039 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8040 alu.dst.chan = i;
8041 alu.dst.write = 1;
8042 alu.is_op3 = 1;
8043 if (i == lasti)
8044 alu.last = 1;
8045 r = r600_bytecode_add_alu(ctx->bc, &alu);
8046 if (r)
8047 return r;
8048 }
8049 return 0;
8050 }
8051
8052 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
8053 {
8054 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8055 struct r600_bytecode_alu alu;
8056 int i, r;
8057 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8058
8059 for (i = 0; i < lasti + 1; i++) {
8060 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8061 continue;
8062
8063 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8064 alu.op = ALU_OP3_CNDE_INT;
8065 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8066 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8067 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
8068 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8069 alu.dst.chan = i;
8070 alu.dst.write = 1;
8071 alu.is_op3 = 1;
8072 if (i == lasti)
8073 alu.last = 1;
8074 r = r600_bytecode_add_alu(ctx->bc, &alu);
8075 if (r)
8076 return r;
8077 }
8078 return 0;
8079 }
8080
8081 static int tgsi_exp(struct r600_shader_ctx *ctx)
8082 {
8083 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8084 struct r600_bytecode_alu alu;
8085 int r;
8086 unsigned i;
8087
8088 /* result.x = 2^floor(src); */
8089 if (inst->Dst[0].Register.WriteMask & 1) {
8090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8091
8092 alu.op = ALU_OP1_FLOOR;
8093 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8094
8095 alu.dst.sel = ctx->temp_reg;
8096 alu.dst.chan = 0;
8097 alu.dst.write = 1;
8098 alu.last = 1;
8099 r = r600_bytecode_add_alu(ctx->bc, &alu);
8100 if (r)
8101 return r;
8102
8103 if (ctx->bc->chip_class == CAYMAN) {
8104 for (i = 0; i < 3; i++) {
8105 alu.op = ALU_OP1_EXP_IEEE;
8106 alu.src[0].sel = ctx->temp_reg;
8107 alu.src[0].chan = 0;
8108
8109 alu.dst.sel = ctx->temp_reg;
8110 alu.dst.chan = i;
8111 alu.dst.write = i == 0;
8112 alu.last = i == 2;
8113 r = r600_bytecode_add_alu(ctx->bc, &alu);
8114 if (r)
8115 return r;
8116 }
8117 } else {
8118 alu.op = ALU_OP1_EXP_IEEE;
8119 alu.src[0].sel = ctx->temp_reg;
8120 alu.src[0].chan = 0;
8121
8122 alu.dst.sel = ctx->temp_reg;
8123 alu.dst.chan = 0;
8124 alu.dst.write = 1;
8125 alu.last = 1;
8126 r = r600_bytecode_add_alu(ctx->bc, &alu);
8127 if (r)
8128 return r;
8129 }
8130 }
8131
8132 /* result.y = tmp - floor(tmp); */
8133 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8135
8136 alu.op = ALU_OP1_FRACT;
8137 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8138
8139 alu.dst.sel = ctx->temp_reg;
8140 #if 0
8141 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8142 if (r)
8143 return r;
8144 #endif
8145 alu.dst.write = 1;
8146 alu.dst.chan = 1;
8147
8148 alu.last = 1;
8149
8150 r = r600_bytecode_add_alu(ctx->bc, &alu);
8151 if (r)
8152 return r;
8153 }
8154
8155 /* result.z = RoughApprox2ToX(tmp);*/
8156 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8157 if (ctx->bc->chip_class == CAYMAN) {
8158 for (i = 0; i < 3; i++) {
8159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8160 alu.op = ALU_OP1_EXP_IEEE;
8161 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8162
8163 alu.dst.sel = ctx->temp_reg;
8164 alu.dst.chan = i;
8165 if (i == 2) {
8166 alu.dst.write = 1;
8167 alu.last = 1;
8168 }
8169
8170 r = r600_bytecode_add_alu(ctx->bc, &alu);
8171 if (r)
8172 return r;
8173 }
8174 } else {
8175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8176 alu.op = ALU_OP1_EXP_IEEE;
8177 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8178
8179 alu.dst.sel = ctx->temp_reg;
8180 alu.dst.write = 1;
8181 alu.dst.chan = 2;
8182
8183 alu.last = 1;
8184
8185 r = r600_bytecode_add_alu(ctx->bc, &alu);
8186 if (r)
8187 return r;
8188 }
8189 }
8190
8191 /* result.w = 1.0;*/
8192 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8194
8195 alu.op = ALU_OP1_MOV;
8196 alu.src[0].sel = V_SQ_ALU_SRC_1;
8197 alu.src[0].chan = 0;
8198
8199 alu.dst.sel = ctx->temp_reg;
8200 alu.dst.chan = 3;
8201 alu.dst.write = 1;
8202 alu.last = 1;
8203 r = r600_bytecode_add_alu(ctx->bc, &alu);
8204 if (r)
8205 return r;
8206 }
8207 return tgsi_helper_copy(ctx, inst);
8208 }
8209
8210 static int tgsi_log(struct r600_shader_ctx *ctx)
8211 {
8212 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8213 struct r600_bytecode_alu alu;
8214 int r;
8215 unsigned i;
8216
8217 /* result.x = floor(log2(|src|)); */
8218 if (inst->Dst[0].Register.WriteMask & 1) {
8219 if (ctx->bc->chip_class == CAYMAN) {
8220 for (i = 0; i < 3; i++) {
8221 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8222
8223 alu.op = ALU_OP1_LOG_IEEE;
8224 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8225 r600_bytecode_src_set_abs(&alu.src[0]);
8226
8227 alu.dst.sel = ctx->temp_reg;
8228 alu.dst.chan = i;
8229 if (i == 0)
8230 alu.dst.write = 1;
8231 if (i == 2)
8232 alu.last = 1;
8233 r = r600_bytecode_add_alu(ctx->bc, &alu);
8234 if (r)
8235 return r;
8236 }
8237
8238 } else {
8239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8240
8241 alu.op = ALU_OP1_LOG_IEEE;
8242 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8243 r600_bytecode_src_set_abs(&alu.src[0]);
8244
8245 alu.dst.sel = ctx->temp_reg;
8246 alu.dst.chan = 0;
8247 alu.dst.write = 1;
8248 alu.last = 1;
8249 r = r600_bytecode_add_alu(ctx->bc, &alu);
8250 if (r)
8251 return r;
8252 }
8253
8254 alu.op = ALU_OP1_FLOOR;
8255 alu.src[0].sel = ctx->temp_reg;
8256 alu.src[0].chan = 0;
8257
8258 alu.dst.sel = ctx->temp_reg;
8259 alu.dst.chan = 0;
8260 alu.dst.write = 1;
8261 alu.last = 1;
8262
8263 r = r600_bytecode_add_alu(ctx->bc, &alu);
8264 if (r)
8265 return r;
8266 }
8267
8268 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8269 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8270
8271 if (ctx->bc->chip_class == CAYMAN) {
8272 for (i = 0; i < 3; i++) {
8273 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8274
8275 alu.op = ALU_OP1_LOG_IEEE;
8276 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8277 r600_bytecode_src_set_abs(&alu.src[0]);
8278
8279 alu.dst.sel = ctx->temp_reg;
8280 alu.dst.chan = i;
8281 if (i == 1)
8282 alu.dst.write = 1;
8283 if (i == 2)
8284 alu.last = 1;
8285
8286 r = r600_bytecode_add_alu(ctx->bc, &alu);
8287 if (r)
8288 return r;
8289 }
8290 } else {
8291 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8292
8293 alu.op = ALU_OP1_LOG_IEEE;
8294 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8295 r600_bytecode_src_set_abs(&alu.src[0]);
8296
8297 alu.dst.sel = ctx->temp_reg;
8298 alu.dst.chan = 1;
8299 alu.dst.write = 1;
8300 alu.last = 1;
8301
8302 r = r600_bytecode_add_alu(ctx->bc, &alu);
8303 if (r)
8304 return r;
8305 }
8306
8307 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8308
8309 alu.op = ALU_OP1_FLOOR;
8310 alu.src[0].sel = ctx->temp_reg;
8311 alu.src[0].chan = 1;
8312
8313 alu.dst.sel = ctx->temp_reg;
8314 alu.dst.chan = 1;
8315 alu.dst.write = 1;
8316 alu.last = 1;
8317
8318 r = r600_bytecode_add_alu(ctx->bc, &alu);
8319 if (r)
8320 return r;
8321
8322 if (ctx->bc->chip_class == CAYMAN) {
8323 for (i = 0; i < 3; i++) {
8324 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8325 alu.op = ALU_OP1_EXP_IEEE;
8326 alu.src[0].sel = ctx->temp_reg;
8327 alu.src[0].chan = 1;
8328
8329 alu.dst.sel = ctx->temp_reg;
8330 alu.dst.chan = i;
8331 if (i == 1)
8332 alu.dst.write = 1;
8333 if (i == 2)
8334 alu.last = 1;
8335
8336 r = r600_bytecode_add_alu(ctx->bc, &alu);
8337 if (r)
8338 return r;
8339 }
8340 } else {
8341 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8342 alu.op = ALU_OP1_EXP_IEEE;
8343 alu.src[0].sel = ctx->temp_reg;
8344 alu.src[0].chan = 1;
8345
8346 alu.dst.sel = ctx->temp_reg;
8347 alu.dst.chan = 1;
8348 alu.dst.write = 1;
8349 alu.last = 1;
8350
8351 r = r600_bytecode_add_alu(ctx->bc, &alu);
8352 if (r)
8353 return r;
8354 }
8355
8356 if (ctx->bc->chip_class == CAYMAN) {
8357 for (i = 0; i < 3; i++) {
8358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8359 alu.op = ALU_OP1_RECIP_IEEE;
8360 alu.src[0].sel = ctx->temp_reg;
8361 alu.src[0].chan = 1;
8362
8363 alu.dst.sel = ctx->temp_reg;
8364 alu.dst.chan = i;
8365 if (i == 1)
8366 alu.dst.write = 1;
8367 if (i == 2)
8368 alu.last = 1;
8369
8370 r = r600_bytecode_add_alu(ctx->bc, &alu);
8371 if (r)
8372 return r;
8373 }
8374 } else {
8375 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8376 alu.op = ALU_OP1_RECIP_IEEE;
8377 alu.src[0].sel = ctx->temp_reg;
8378 alu.src[0].chan = 1;
8379
8380 alu.dst.sel = ctx->temp_reg;
8381 alu.dst.chan = 1;
8382 alu.dst.write = 1;
8383 alu.last = 1;
8384
8385 r = r600_bytecode_add_alu(ctx->bc, &alu);
8386 if (r)
8387 return r;
8388 }
8389
8390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8391
8392 alu.op = ALU_OP2_MUL;
8393
8394 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8395 r600_bytecode_src_set_abs(&alu.src[0]);
8396
8397 alu.src[1].sel = ctx->temp_reg;
8398 alu.src[1].chan = 1;
8399
8400 alu.dst.sel = ctx->temp_reg;
8401 alu.dst.chan = 1;
8402 alu.dst.write = 1;
8403 alu.last = 1;
8404
8405 r = r600_bytecode_add_alu(ctx->bc, &alu);
8406 if (r)
8407 return r;
8408 }
8409
8410 /* result.z = log2(|src|);*/
8411 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8412 if (ctx->bc->chip_class == CAYMAN) {
8413 for (i = 0; i < 3; i++) {
8414 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8415
8416 alu.op = ALU_OP1_LOG_IEEE;
8417 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8418 r600_bytecode_src_set_abs(&alu.src[0]);
8419
8420 alu.dst.sel = ctx->temp_reg;
8421 if (i == 2)
8422 alu.dst.write = 1;
8423 alu.dst.chan = i;
8424 if (i == 2)
8425 alu.last = 1;
8426
8427 r = r600_bytecode_add_alu(ctx->bc, &alu);
8428 if (r)
8429 return r;
8430 }
8431 } else {
8432 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8433
8434 alu.op = ALU_OP1_LOG_IEEE;
8435 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8436 r600_bytecode_src_set_abs(&alu.src[0]);
8437
8438 alu.dst.sel = ctx->temp_reg;
8439 alu.dst.write = 1;
8440 alu.dst.chan = 2;
8441 alu.last = 1;
8442
8443 r = r600_bytecode_add_alu(ctx->bc, &alu);
8444 if (r)
8445 return r;
8446 }
8447 }
8448
8449 /* result.w = 1.0; */
8450 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8451 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8452
8453 alu.op = ALU_OP1_MOV;
8454 alu.src[0].sel = V_SQ_ALU_SRC_1;
8455 alu.src[0].chan = 0;
8456
8457 alu.dst.sel = ctx->temp_reg;
8458 alu.dst.chan = 3;
8459 alu.dst.write = 1;
8460 alu.last = 1;
8461
8462 r = r600_bytecode_add_alu(ctx->bc, &alu);
8463 if (r)
8464 return r;
8465 }
8466
8467 return tgsi_helper_copy(ctx, inst);
8468 }
8469
8470 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8471 {
8472 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8473 struct r600_bytecode_alu alu;
8474 int r;
8475 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8476 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8477
8478 assert(inst->Dst[0].Register.Index < 3);
8479 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8480
8481 switch (inst->Instruction.Opcode) {
8482 case TGSI_OPCODE_ARL:
8483 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8484 break;
8485 case TGSI_OPCODE_ARR:
8486 alu.op = ALU_OP1_FLT_TO_INT;
8487 break;
8488 case TGSI_OPCODE_UARL:
8489 alu.op = ALU_OP1_MOV;
8490 break;
8491 default:
8492 assert(0);
8493 return -1;
8494 }
8495
8496 for (i = 0; i <= lasti; ++i) {
8497 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8498 continue;
8499 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8500 alu.last = i == lasti;
8501 alu.dst.sel = reg;
8502 alu.dst.chan = i;
8503 alu.dst.write = 1;
8504 r = r600_bytecode_add_alu(ctx->bc, &alu);
8505 if (r)
8506 return r;
8507 }
8508
8509 if (inst->Dst[0].Register.Index > 0)
8510 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8511 else
8512 ctx->bc->ar_loaded = 0;
8513
8514 return 0;
8515 }
8516 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8517 {
8518 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8519 struct r600_bytecode_alu alu;
8520 int r;
8521 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8522
8523 switch (inst->Instruction.Opcode) {
8524 case TGSI_OPCODE_ARL:
8525 memset(&alu, 0, sizeof(alu));
8526 alu.op = ALU_OP1_FLOOR;
8527 alu.dst.sel = ctx->bc->ar_reg;
8528 alu.dst.write = 1;
8529 for (i = 0; i <= lasti; ++i) {
8530 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8531 alu.dst.chan = i;
8532 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8533 alu.last = i == lasti;
8534 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8535 return r;
8536 }
8537 }
8538
8539 memset(&alu, 0, sizeof(alu));
8540 alu.op = ALU_OP1_FLT_TO_INT;
8541 alu.src[0].sel = ctx->bc->ar_reg;
8542 alu.dst.sel = ctx->bc->ar_reg;
8543 alu.dst.write = 1;
8544 /* FLT_TO_INT is trans-only on r600/r700 */
8545 alu.last = TRUE;
8546 for (i = 0; i <= lasti; ++i) {
8547 alu.dst.chan = i;
8548 alu.src[0].chan = i;
8549 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8550 return r;
8551 }
8552 break;
8553 case TGSI_OPCODE_ARR:
8554 memset(&alu, 0, sizeof(alu));
8555 alu.op = ALU_OP1_FLT_TO_INT;
8556 alu.dst.sel = ctx->bc->ar_reg;
8557 alu.dst.write = 1;
8558 /* FLT_TO_INT is trans-only on r600/r700 */
8559 alu.last = TRUE;
8560 for (i = 0; i <= lasti; ++i) {
8561 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8562 alu.dst.chan = i;
8563 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8564 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8565 return r;
8566 }
8567 }
8568 break;
8569 case TGSI_OPCODE_UARL:
8570 memset(&alu, 0, sizeof(alu));
8571 alu.op = ALU_OP1_MOV;
8572 alu.dst.sel = ctx->bc->ar_reg;
8573 alu.dst.write = 1;
8574 for (i = 0; i <= lasti; ++i) {
8575 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8576 alu.dst.chan = i;
8577 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8578 alu.last = i == lasti;
8579 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8580 return r;
8581 }
8582 }
8583 break;
8584 default:
8585 assert(0);
8586 return -1;
8587 }
8588
8589 ctx->bc->ar_loaded = 0;
8590 return 0;
8591 }
8592
8593 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8594 {
8595 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8596 struct r600_bytecode_alu alu;
8597 int i, r = 0;
8598
8599 for (i = 0; i < 4; i++) {
8600 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8601
8602 alu.op = ALU_OP2_MUL;
8603 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8604
8605 if (i == 0 || i == 3) {
8606 alu.src[0].sel = V_SQ_ALU_SRC_1;
8607 } else {
8608 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8609 }
8610
8611 if (i == 0 || i == 2) {
8612 alu.src[1].sel = V_SQ_ALU_SRC_1;
8613 } else {
8614 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8615 }
8616 if (i == 3)
8617 alu.last = 1;
8618 r = r600_bytecode_add_alu(ctx->bc, &alu);
8619 if (r)
8620 return r;
8621 }
8622 return 0;
8623 }
8624
8625 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8626 {
8627 struct r600_bytecode_alu alu;
8628 int r;
8629
8630 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8631 alu.op = opcode;
8632 alu.execute_mask = 1;
8633 alu.update_pred = 1;
8634
8635 alu.dst.sel = ctx->temp_reg;
8636 alu.dst.write = 1;
8637 alu.dst.chan = 0;
8638
8639 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8640 alu.src[1].sel = V_SQ_ALU_SRC_0;
8641 alu.src[1].chan = 0;
8642
8643 alu.last = 1;
8644
8645 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8646 if (r)
8647 return r;
8648 return 0;
8649 }
8650
8651 static int pops(struct r600_shader_ctx *ctx, int pops)
8652 {
8653 unsigned force_pop = ctx->bc->force_add_cf;
8654
8655 if (!force_pop) {
8656 int alu_pop = 3;
8657 if (ctx->bc->cf_last) {
8658 if (ctx->bc->cf_last->op == CF_OP_ALU)
8659 alu_pop = 0;
8660 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8661 alu_pop = 1;
8662 }
8663 alu_pop += pops;
8664 if (alu_pop == 1) {
8665 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8666 ctx->bc->force_add_cf = 1;
8667 } else if (alu_pop == 2) {
8668 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8669 ctx->bc->force_add_cf = 1;
8670 } else {
8671 force_pop = 1;
8672 }
8673 }
8674
8675 if (force_pop) {
8676 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8677 ctx->bc->cf_last->pop_count = pops;
8678 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8679 }
8680
8681 return 0;
8682 }
8683
8684 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8685 unsigned reason)
8686 {
8687 struct r600_stack_info *stack = &ctx->bc->stack;
8688 unsigned elements, entries;
8689
8690 unsigned entry_size = stack->entry_size;
8691
8692 elements = (stack->loop + stack->push_wqm ) * entry_size;
8693 elements += stack->push;
8694
8695 switch (ctx->bc->chip_class) {
8696 case R600:
8697 case R700:
8698 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8699 * the stack must be reserved to hold the current active/continue
8700 * masks */
8701 if (reason == FC_PUSH_VPM) {
8702 elements += 2;
8703 }
8704 break;
8705
8706 case CAYMAN:
8707 /* r9xx: any stack operation on empty stack consumes 2 additional
8708 * elements */
8709 elements += 2;
8710
8711 /* fallthrough */
8712 /* FIXME: do the two elements added above cover the cases for the
8713 * r8xx+ below? */
8714
8715 case EVERGREEN:
8716 /* r8xx+: 2 extra elements are not always required, but one extra
8717 * element must be added for each of the following cases:
8718 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8719 * stack usage.
8720 * (Currently we don't use ALU_ELSE_AFTER.)
8721 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8722 * PUSH instruction executed.
8723 *
8724 * NOTE: it seems we also need to reserve additional element in some
8725 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8726 * then STACK_SIZE should be 2 instead of 1 */
8727 if (reason == FC_PUSH_VPM) {
8728 elements += 1;
8729 }
8730 break;
8731
8732 default:
8733 assert(0);
8734 break;
8735 }
8736
8737 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8738 * for all chips, so we use 4 in the final formula, not the real entry_size
8739 * for the chip */
8740 entry_size = 4;
8741
8742 entries = (elements + (entry_size - 1)) / entry_size;
8743
8744 if (entries > stack->max_entries)
8745 stack->max_entries = entries;
8746 }
8747
8748 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8749 {
8750 switch(reason) {
8751 case FC_PUSH_VPM:
8752 --ctx->bc->stack.push;
8753 assert(ctx->bc->stack.push >= 0);
8754 break;
8755 case FC_PUSH_WQM:
8756 --ctx->bc->stack.push_wqm;
8757 assert(ctx->bc->stack.push_wqm >= 0);
8758 break;
8759 case FC_LOOP:
8760 --ctx->bc->stack.loop;
8761 assert(ctx->bc->stack.loop >= 0);
8762 break;
8763 default:
8764 assert(0);
8765 break;
8766 }
8767 }
8768
8769 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8770 {
8771 switch (reason) {
8772 case FC_PUSH_VPM:
8773 ++ctx->bc->stack.push;
8774 break;
8775 case FC_PUSH_WQM:
8776 ++ctx->bc->stack.push_wqm;
8777 case FC_LOOP:
8778 ++ctx->bc->stack.loop;
8779 break;
8780 default:
8781 assert(0);
8782 }
8783
8784 callstack_update_max_depth(ctx, reason);
8785 }
8786
8787 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8788 {
8789 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8790
8791 sp->mid = realloc((void *)sp->mid,
8792 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8793 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8794 sp->num_mid++;
8795 }
8796
8797 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8798 {
8799 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
8800 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8801 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8802 ctx->bc->fc_sp++;
8803 }
8804
8805 static void fc_poplevel(struct r600_shader_ctx *ctx)
8806 {
8807 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
8808 free(sp->mid);
8809 sp->mid = NULL;
8810 sp->num_mid = 0;
8811 sp->start = NULL;
8812 sp->type = 0;
8813 ctx->bc->fc_sp--;
8814 }
8815
8816 #if 0
8817 static int emit_return(struct r600_shader_ctx *ctx)
8818 {
8819 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8820 return 0;
8821 }
8822
8823 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8824 {
8825
8826 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8827 ctx->bc->cf_last->pop_count = pops;
8828 /* XXX work out offset */
8829 return 0;
8830 }
8831
8832 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8833 {
8834 return 0;
8835 }
8836
8837 static void emit_testflag(struct r600_shader_ctx *ctx)
8838 {
8839
8840 }
8841
8842 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8843 {
8844 emit_testflag(ctx);
8845 emit_jump_to_offset(ctx, 1, 4);
8846 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8847 pops(ctx, ifidx + 1);
8848 emit_return(ctx);
8849 }
8850
8851 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8852 {
8853 emit_testflag(ctx);
8854
8855 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8856 ctx->bc->cf_last->pop_count = 1;
8857
8858 fc_set_mid(ctx, fc_sp);
8859
8860 pops(ctx, 1);
8861 }
8862 #endif
8863
8864 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8865 {
8866 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8867
8868 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8869 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8870 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8871 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8872 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8873 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8874 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8875 alu_type = CF_OP_ALU;
8876 }
8877
8878 emit_logic_pred(ctx, opcode, alu_type);
8879
8880 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8881
8882 fc_pushlevel(ctx, FC_IF);
8883
8884 callstack_push(ctx, FC_PUSH_VPM);
8885 return 0;
8886 }
8887
8888 static int tgsi_if(struct r600_shader_ctx *ctx)
8889 {
8890 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8891 }
8892
8893 static int tgsi_uif(struct r600_shader_ctx *ctx)
8894 {
8895 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8896 }
8897
8898 static int tgsi_else(struct r600_shader_ctx *ctx)
8899 {
8900 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8901 ctx->bc->cf_last->pop_count = 1;
8902
8903 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
8904 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
8905 return 0;
8906 }
8907
8908 static int tgsi_endif(struct r600_shader_ctx *ctx)
8909 {
8910 pops(ctx, 1);
8911 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
8912 R600_ERR("if/endif unbalanced in shader\n");
8913 return -1;
8914 }
8915
8916 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
8917 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8918 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
8919 } else {
8920 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8921 }
8922 fc_poplevel(ctx);
8923
8924 callstack_pop(ctx, FC_PUSH_VPM);
8925 return 0;
8926 }
8927
8928 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8929 {
8930 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8931 * limited to 4096 iterations, like the other LOOP_* instructions. */
8932 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8933
8934 fc_pushlevel(ctx, FC_LOOP);
8935
8936 /* check stack depth */
8937 callstack_push(ctx, FC_LOOP);
8938 return 0;
8939 }
8940
8941 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8942 {
8943 unsigned i;
8944
8945 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8946
8947 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
8948 R600_ERR("loop/endloop in shader code are not paired.\n");
8949 return -EINVAL;
8950 }
8951
8952 /* fixup loop pointers - from r600isa
8953 LOOP END points to CF after LOOP START,
8954 LOOP START point to CF after LOOP END
8955 BRK/CONT point to LOOP END CF
8956 */
8957 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
8958
8959 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8960
8961 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
8962 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
8963 }
8964 /* XXX add LOOPRET support */
8965 fc_poplevel(ctx);
8966 callstack_pop(ctx, FC_LOOP);
8967 return 0;
8968 }
8969
8970 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8971 {
8972 unsigned int fscp;
8973
8974 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8975 {
8976 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
8977 break;
8978 }
8979
8980 if (fscp == 0) {
8981 R600_ERR("Break not inside loop/endloop pair\n");
8982 return -EINVAL;
8983 }
8984
8985 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8986
8987 fc_set_mid(ctx, fscp - 1);
8988
8989 return 0;
8990 }
8991
8992 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8993 {
8994 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8995 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8996 int r;
8997
8998 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8999 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
9000
9001 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9002 if (!r) {
9003 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
9004 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9005 return emit_inc_ring_offset(ctx, stream, TRUE);
9006 }
9007 return r;
9008 }
9009
9010 static int tgsi_umad(struct r600_shader_ctx *ctx)
9011 {
9012 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9013 struct r600_bytecode_alu alu;
9014 int i, j, k, r;
9015 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9016
9017 /* src0 * src1 */
9018 for (i = 0; i < lasti + 1; i++) {
9019 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9020 continue;
9021
9022 if (ctx->bc->chip_class == CAYMAN) {
9023 for (j = 0 ; j < 4; j++) {
9024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9025
9026 alu.op = ALU_OP2_MULLO_UINT;
9027 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
9028 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
9029 }
9030 alu.dst.chan = j;
9031 alu.dst.sel = ctx->temp_reg;
9032 alu.dst.write = (j == i);
9033 if (j == 3)
9034 alu.last = 1;
9035 r = r600_bytecode_add_alu(ctx->bc, &alu);
9036 if (r)
9037 return r;
9038 }
9039 } else {
9040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9041
9042 alu.dst.chan = i;
9043 alu.dst.sel = ctx->temp_reg;
9044 alu.dst.write = 1;
9045
9046 alu.op = ALU_OP2_MULLO_UINT;
9047 for (j = 0; j < 2; j++) {
9048 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
9049 }
9050
9051 alu.last = 1;
9052 r = r600_bytecode_add_alu(ctx->bc, &alu);
9053 if (r)
9054 return r;
9055 }
9056 }
9057
9058
9059 for (i = 0; i < lasti + 1; i++) {
9060 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9061 continue;
9062
9063 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9064 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9065
9066 alu.op = ALU_OP2_ADD_INT;
9067
9068 alu.src[0].sel = ctx->temp_reg;
9069 alu.src[0].chan = i;
9070
9071 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9072 if (i == lasti) {
9073 alu.last = 1;
9074 }
9075 r = r600_bytecode_add_alu(ctx->bc, &alu);
9076 if (r)
9077 return r;
9078 }
9079 return 0;
9080 }
9081
9082 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
9083 {
9084 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9085 struct r600_bytecode_alu alu;
9086 int r, i;
9087 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9088
9089 /* temp.xy = f32_to_f16(src) */
9090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9091 alu.op = ALU_OP1_FLT32_TO_FLT16;
9092 alu.dst.chan = 0;
9093 alu.dst.sel = ctx->temp_reg;
9094 alu.dst.write = 1;
9095 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9096 r = r600_bytecode_add_alu(ctx->bc, &alu);
9097 if (r)
9098 return r;
9099 alu.dst.chan = 1;
9100 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
9101 alu.last = 1;
9102 r = r600_bytecode_add_alu(ctx->bc, &alu);
9103 if (r)
9104 return r;
9105
9106 /* dst.x = temp.y * 0x10000 + temp.x */
9107 for (i = 0; i < lasti + 1; i++) {
9108 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9109 continue;
9110
9111 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9112 alu.op = ALU_OP3_MULADD_UINT24;
9113 alu.is_op3 = 1;
9114 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9115 alu.last = i == lasti;
9116 alu.src[0].sel = ctx->temp_reg;
9117 alu.src[0].chan = 1;
9118 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9119 alu.src[1].value = 0x10000;
9120 alu.src[2].sel = ctx->temp_reg;
9121 alu.src[2].chan = 0;
9122 r = r600_bytecode_add_alu(ctx->bc, &alu);
9123 if (r)
9124 return r;
9125 }
9126
9127 return 0;
9128 }
9129
9130 static int tgsi_up2h(struct r600_shader_ctx *ctx)
9131 {
9132 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9133 struct r600_bytecode_alu alu;
9134 int r, i;
9135 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9136
9137 /* temp.x = src.x */
9138 /* note: no need to mask out the high bits */
9139 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9140 alu.op = ALU_OP1_MOV;
9141 alu.dst.chan = 0;
9142 alu.dst.sel = ctx->temp_reg;
9143 alu.dst.write = 1;
9144 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9145 r = r600_bytecode_add_alu(ctx->bc, &alu);
9146 if (r)
9147 return r;
9148
9149 /* temp.y = src.x >> 16 */
9150 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9151 alu.op = ALU_OP2_LSHR_INT;
9152 alu.dst.chan = 1;
9153 alu.dst.sel = ctx->temp_reg;
9154 alu.dst.write = 1;
9155 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9156 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9157 alu.src[1].value = 16;
9158 alu.last = 1;
9159 r = r600_bytecode_add_alu(ctx->bc, &alu);
9160 if (r)
9161 return r;
9162
9163 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9164 for (i = 0; i < lasti + 1; i++) {
9165 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9166 continue;
9167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9168 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9169 alu.op = ALU_OP1_FLT16_TO_FLT32;
9170 alu.src[0].sel = ctx->temp_reg;
9171 alu.src[0].chan = i % 2;
9172 alu.last = i == lasti;
9173 r = r600_bytecode_add_alu(ctx->bc, &alu);
9174 if (r)
9175 return r;
9176 }
9177
9178 return 0;
9179 }
9180
9181 static int tgsi_bfe(struct r600_shader_ctx *ctx)
9182 {
9183 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9184 struct r600_bytecode_alu alu;
9185 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9186 int r, i;
9187
9188 r = tgsi_op3(ctx);
9189 if (r)
9190 return r;
9191
9192 for (i = 0; i < lasti + 1; i++) {
9193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9194 alu.op = ALU_OP2_SETGE_INT;
9195 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
9196 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9197 alu.src[1].value = 32;
9198 alu.dst.sel = ctx->temp_reg;
9199 alu.dst.chan = i;
9200 alu.dst.write = 1;
9201 if (i == lasti)
9202 alu.last = 1;
9203 r = r600_bytecode_add_alu(ctx->bc, &alu);
9204 if (r)
9205 return r;
9206 }
9207
9208 for (i = 0; i < lasti + 1; i++) {
9209 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9210 alu.op = ALU_OP3_CNDE_INT;
9211 alu.is_op3 = 1;
9212 alu.src[0].sel = ctx->temp_reg;
9213 alu.src[1].chan = i;
9214
9215 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9216 alu.src[1].sel = alu.dst.sel;
9217 alu.src[1].chan = i;
9218 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
9219 alu.dst.write = 1;
9220 if (i == lasti)
9221 alu.last = 1;
9222 r = r600_bytecode_add_alu(ctx->bc, &alu);
9223 if (r)
9224 return r;
9225 }
9226
9227 return 0;
9228 }
9229
9230 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
9231 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
9232 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9233 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9234
9235 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9236
9237 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9238 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9239 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9240 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9241 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9242 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9243 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9244 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9245 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
9246 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9247 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9248 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9249 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9250 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9251 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9252 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9253 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9254 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9255 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9256 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9257 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9258 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9259 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9260 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9261 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9262 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9263 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9264 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9265 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9266 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9267 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9268 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9269 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9270 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9271 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9272 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9273 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9274 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9275 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9276 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9277 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9278 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9279 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9280 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9281 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9282 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9283 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9284 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9285 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9286 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9287 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9288 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9289 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9290 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9291 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9292 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9293 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9294 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9295 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9296 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9297 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9298 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9299 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9300 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9301 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9302 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9303 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9304 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9305 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9306 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9307 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9308 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9309 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9310 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9311 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9312 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9313 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9314 [81] = { ALU_OP0_NOP, tgsi_unsupported},
9315 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9316 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9317 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9318 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9319 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9320 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9321 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9322 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9323 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9324 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9325 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9326 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9327 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9328 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9329 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9330 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9331 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9332 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9333 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9334 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9335 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9336 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9337 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9338 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9339 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9340 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9341 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9342 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9343 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9344 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9345 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9346 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9347 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9348 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9349 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9350 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9351 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9352 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9353 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9354 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9355 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9356 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9357 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9358 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9359 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9360 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9361 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9362 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9363 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9364 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9365 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9366 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9367 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9368 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9369 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9370 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9371 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9372 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9373 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9374 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9375 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9376 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9377 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9378 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9379 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9380 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9381 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9382 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9383 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9384 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9385 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9386 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9387 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9388 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9389 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9390 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9391 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9392 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9393 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9394 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9395 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9396 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9397 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9398 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9399 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9400 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9401 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9402 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9403 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9404 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9405 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9406 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9407 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9408 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9409 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9410 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9411 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9412 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9413 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9414 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9415 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9416 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9417 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9418 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9419 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9420 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9421 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9422 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9423 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9424 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9425 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9426 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9427 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9428 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9429 };
9430
9431 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9432 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9433 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9434 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9435 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9436 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9437 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9438 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9439 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9440 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9441 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9442 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9443 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9444 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9445 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9446 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9447 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9448 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9449 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9450 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9451 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9452 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9453 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9454 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9455 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9456 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9457 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9458 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9459 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9460 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9461 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9462 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9463 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9464 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9465 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9466 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9467 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9468 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9469 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9470 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9471 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9472 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9473 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9474 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9475 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9476 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9477 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9478 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9479 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9480 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9481 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9482 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9483 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9484 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9485 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9486 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9487 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9488 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9489 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9490 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9491 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9492 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9493 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9494 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9495 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9496 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9497 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9498 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9499 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9500 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9501 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9502 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9503 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9504 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9505 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9506 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9507 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9508 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9509 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9510 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9511 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9512 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9513 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9514 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9515 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9516 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9517 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9518 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9519 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9520 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9521 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9522 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9523 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9524 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9525 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9526 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9527 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9528 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9529 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9530 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9531 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9532 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9533 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9534 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9535 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9536 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9537 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9538 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9539 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9540 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9541 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9542 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9543 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9544 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9545 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9546 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9547 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9548 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9549 /* Refer below for TGSI_OPCODE_DFMA */
9550 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9551 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9552 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9553 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9554 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9555 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9556 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9557 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9558 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9559 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9560 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9561 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9562 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9563 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9564 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9565 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9566 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9567 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9568 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9569 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9570 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9571 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9572 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9573 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9574 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9575 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9576 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9577 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9578 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9579 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9580 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9581 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9582 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9583 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9584 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9585 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9586 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9587 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9588 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9589 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9590 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9591 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9592 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9593 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9594 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9595 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9596 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9597 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9598 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9599 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9600 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9601 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9602 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9603 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9604 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9605 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9606 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9607 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9608 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9609 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9610 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9611 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9612 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9613 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9614 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9615 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
9616 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
9617 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9618 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9619 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9620 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9621 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9622 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9623 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9624 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9625 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9626 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9627 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9628 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9629 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9630 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9631 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9632 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9633 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9634 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9635 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9636 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9637 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9638 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9639 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9640 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9641 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9642 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9643 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9644 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9645 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9646 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9647 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9648 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9649 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9650 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9651 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9652 };
9653
9654 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9655 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9656 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9657 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9658 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9659 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9660 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9661 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9662 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9663 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9664 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9665 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9666 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9667 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9668 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9669 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9670 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9671 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9672 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9673 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9674 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9675 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9676 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9677 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9678 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9679 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9680 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9681 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9682 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9683 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9684 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9685 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9686 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9687 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9688 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9689 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9690 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9691 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9692 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9693 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9694 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9695 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9696 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9697 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9698 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9699 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9700 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9701 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9702 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9703 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9704 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9705 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9706 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9707 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9708 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9709 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9710 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9711 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9712 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9713 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9714 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9715 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9716 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9717 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9718 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9719 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9720 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9721 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9722 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9723 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9724 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9725 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9726 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9727 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9728 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9729 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9730 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9731 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9732 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9733 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9734 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9735 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9736 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9737 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9738 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9739 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9740 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9741 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9742 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9743 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9744 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9745 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9746 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9747 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9748 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9749 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9750 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9751 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9752 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9753 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9754 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9755 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9756 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9757 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9758 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9759 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9760 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9761 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9762 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9763 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9764 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9765 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9766 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9767 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9768 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9769 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9770 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9771 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9772 /* Refer below for TGSI_OPCODE_DFMA */
9773 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9774 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9775 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9776 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9777 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9778 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9779 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9780 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9781 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9782 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9783 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9784 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9785 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9786 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9787 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9788 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9789 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9790 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9791 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9792 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9793 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9794 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9795 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9796 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9797 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9798 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9799 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9800 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9801 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9802 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9803 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9804 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9805 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9806 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9807 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9808 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9809 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9810 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9811 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9812 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9813 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9814 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9815 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9816 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9817 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9818 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9819 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9820 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9821 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9822 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9823 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9824 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9825 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9826 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9827 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9828 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9829 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9830 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9831 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9832 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9833 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9834 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9835 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9836 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9837 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9838 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
9839 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
9840 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9841 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9842 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9843 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9844 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9845 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9846 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9847 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9848 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9849 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9850 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9851 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9852 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9853 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9854 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9855 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9856 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9857 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9858 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9859 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9860 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9861 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9862 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9863 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9864 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9865 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9866 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9867 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9868 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9869 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9870 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9871 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9872 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9873 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9874 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9875 };