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r600: fix loop overrun in cayman_mul_double_instr
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_context *rctx,
64 struct r600_pipe_shader *pipeshader,
65 union r600_shader_key key);
66
67
68 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
69 int size, unsigned comp_mask) {
70
71 if (!size)
72 return;
73
74 if (ps->num_arrays == ps->max_arrays) {
75 ps->max_arrays += 64;
76 ps->arrays = realloc(ps->arrays, ps->max_arrays *
77 sizeof(struct r600_shader_array));
78 }
79
80 int n = ps->num_arrays;
81 ++ps->num_arrays;
82
83 ps->arrays[n].comp_mask = comp_mask;
84 ps->arrays[n].gpr_start = start_gpr;
85 ps->arrays[n].gpr_count = size;
86 }
87
88 static void r600_dump_streamout(struct pipe_stream_output_info *so)
89 {
90 unsigned i;
91
92 fprintf(stderr, "STREAMOUT\n");
93 for (i = 0; i < so->num_outputs; i++) {
94 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
95 so->output[i].start_component;
96 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
97 i,
98 so->output[i].stream,
99 so->output[i].output_buffer,
100 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
101 so->output[i].register_index,
102 mask & 1 ? "x" : "",
103 mask & 2 ? "y" : "",
104 mask & 4 ? "z" : "",
105 mask & 8 ? "w" : "",
106 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
107 }
108 }
109
110 static int store_shader(struct pipe_context *ctx,
111 struct r600_pipe_shader *shader)
112 {
113 struct r600_context *rctx = (struct r600_context *)ctx;
114 uint32_t *ptr, i;
115
116 if (shader->bo == NULL) {
117 shader->bo = (struct r600_resource*)
118 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
119 if (shader->bo == NULL) {
120 return -ENOMEM;
121 }
122 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
123 if (R600_BIG_ENDIAN) {
124 for (i = 0; i < shader->shader.bc.ndw; ++i) {
125 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
126 }
127 } else {
128 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
129 }
130 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
131 }
132
133 return 0;
134 }
135
136 int r600_pipe_shader_create(struct pipe_context *ctx,
137 struct r600_pipe_shader *shader,
138 union r600_shader_key key)
139 {
140 struct r600_context *rctx = (struct r600_context *)ctx;
141 struct r600_pipe_shader_selector *sel = shader->selector;
142 int r;
143 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
144 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
145 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
146 unsigned export_shader = key.vs.as_es;
147
148 shader->shader.bc.isa = rctx->isa;
149
150 if (dump) {
151 fprintf(stderr, "--------------------------------------------------------------\n");
152 tgsi_dump(sel->tokens, 0);
153
154 if (sel->so.num_outputs) {
155 r600_dump_streamout(&sel->so);
156 }
157 }
158 r = r600_shader_from_tgsi(rctx, shader, key);
159 if (r) {
160 R600_ERR("translation from TGSI failed !\n");
161 goto error;
162 }
163
164 /* disable SB for geom shaders on R6xx/R7xx due to some mysterious gs piglit regressions with it enabled. */
165 if (rctx->b.chip_class <= R700) {
166 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_GEOMETRY);
167 }
168 /* disable SB for shaders using CF_INDEX_0/1 (sampler/ubo array indexing) as it doesn't handle those currently */
169 use_sb &= !shader->shader.uses_index_registers;
170 /* disable SB for shaders using doubles */
171 use_sb &= !shader->shader.uses_doubles;
172
173 /* Check if the bytecode has already been built. When using the llvm
174 * backend, r600_shader_from_tgsi() will take care of building the
175 * bytecode.
176 */
177 if (!shader->shader.bc.bytecode) {
178 r = r600_bytecode_build(&shader->shader.bc);
179 if (r) {
180 R600_ERR("building bytecode failed !\n");
181 goto error;
182 }
183 }
184
185 if (dump && !sb_disasm) {
186 fprintf(stderr, "--------------------------------------------------------------\n");
187 r600_bytecode_disasm(&shader->shader.bc);
188 fprintf(stderr, "______________________________________________________________\n");
189 } else if ((dump && sb_disasm) || use_sb) {
190 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
191 dump, use_sb);
192 if (r) {
193 R600_ERR("r600_sb_bytecode_process failed !\n");
194 goto error;
195 }
196 }
197
198 if (shader->gs_copy_shader) {
199 if (dump) {
200 // dump copy shader
201 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
202 &shader->gs_copy_shader->shader, dump, 0);
203 if (r)
204 goto error;
205 }
206
207 if ((r = store_shader(ctx, shader->gs_copy_shader)))
208 goto error;
209 }
210
211 /* Store the shader in a buffer. */
212 if ((r = store_shader(ctx, shader)))
213 goto error;
214
215 /* Build state. */
216 switch (shader->shader.processor_type) {
217 case TGSI_PROCESSOR_GEOMETRY:
218 if (rctx->b.chip_class >= EVERGREEN) {
219 evergreen_update_gs_state(ctx, shader);
220 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
221 } else {
222 r600_update_gs_state(ctx, shader);
223 r600_update_vs_state(ctx, shader->gs_copy_shader);
224 }
225 break;
226 case TGSI_PROCESSOR_VERTEX:
227 if (rctx->b.chip_class >= EVERGREEN) {
228 if (export_shader)
229 evergreen_update_es_state(ctx, shader);
230 else
231 evergreen_update_vs_state(ctx, shader);
232 } else {
233 if (export_shader)
234 r600_update_es_state(ctx, shader);
235 else
236 r600_update_vs_state(ctx, shader);
237 }
238 break;
239 case TGSI_PROCESSOR_FRAGMENT:
240 if (rctx->b.chip_class >= EVERGREEN) {
241 evergreen_update_ps_state(ctx, shader);
242 } else {
243 r600_update_ps_state(ctx, shader);
244 }
245 break;
246 default:
247 r = -EINVAL;
248 goto error;
249 }
250 return 0;
251
252 error:
253 r600_pipe_shader_destroy(ctx, shader);
254 return r;
255 }
256
257 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
258 {
259 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
260 r600_bytecode_clear(&shader->shader.bc);
261 r600_release_command_buffer(&shader->command_buffer);
262 }
263
264 /*
265 * tgsi -> r600 shader
266 */
267 struct r600_shader_tgsi_instruction;
268
269 struct r600_shader_src {
270 unsigned sel;
271 unsigned swizzle[4];
272 unsigned neg;
273 unsigned abs;
274 unsigned rel;
275 unsigned kc_bank;
276 boolean kc_rel; /* true if cache bank is indexed */
277 uint32_t value[4];
278 };
279
280 struct eg_interp {
281 boolean enabled;
282 unsigned ij_index;
283 };
284
285 struct r600_shader_ctx {
286 struct tgsi_shader_info info;
287 struct tgsi_parse_context parse;
288 const struct tgsi_token *tokens;
289 unsigned type;
290 unsigned file_offset[TGSI_FILE_COUNT];
291 unsigned temp_reg;
292 const struct r600_shader_tgsi_instruction *inst_info;
293 struct r600_bytecode *bc;
294 struct r600_shader *shader;
295 struct r600_shader_src src[4];
296 uint32_t *literals;
297 uint32_t nliterals;
298 uint32_t max_driver_temp_used;
299 boolean use_llvm;
300 /* needed for evergreen interpolation */
301 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
302 /* evergreen/cayman also store sample mask in face register */
303 int face_gpr;
304 /* sample id is .w component stored in fixed point position register */
305 int fixed_pt_position_gpr;
306 int colors_used;
307 boolean clip_vertex_write;
308 unsigned cv_output;
309 unsigned edgeflag_output;
310 int fragcoord_input;
311 int native_integers;
312 int next_ring_offset;
313 int gs_out_ring_offset;
314 int gs_next_vertex;
315 struct r600_shader *gs_for_vs;
316 int gs_export_gpr_tregs[4];
317 const struct pipe_stream_output_info *gs_stream_output_info;
318 unsigned enabled_stream_buffers_mask;
319 };
320
321 struct r600_shader_tgsi_instruction {
322 unsigned op;
323 int (*process)(struct r600_shader_ctx *ctx);
324 };
325
326 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
327 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
328 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
329 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
330 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
331 static int tgsi_else(struct r600_shader_ctx *ctx);
332 static int tgsi_endif(struct r600_shader_ctx *ctx);
333 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
334 static int tgsi_endloop(struct r600_shader_ctx *ctx);
335 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
336 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
337 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
338 unsigned int dst_reg);
339 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
340 const struct r600_shader_src *shader_src,
341 unsigned chan);
342
343 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
344 {
345 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
346 int j;
347
348 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
349 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
350 return -EINVAL;
351 }
352 if (i->Instruction.Predicate) {
353 R600_ERR("predicate unsupported\n");
354 return -EINVAL;
355 }
356 #if 0
357 if (i->Instruction.Label) {
358 R600_ERR("label unsupported\n");
359 return -EINVAL;
360 }
361 #endif
362 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
363 if (i->Src[j].Register.Dimension) {
364 switch (i->Src[j].Register.File) {
365 case TGSI_FILE_CONSTANT:
366 break;
367 case TGSI_FILE_INPUT:
368 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
369 break;
370 default:
371 R600_ERR("unsupported src %d (dimension %d)\n", j,
372 i->Src[j].Register.Dimension);
373 return -EINVAL;
374 }
375 }
376 }
377 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
378 if (i->Dst[j].Register.Dimension) {
379 R600_ERR("unsupported dst (dimension)\n");
380 return -EINVAL;
381 }
382 }
383 return 0;
384 }
385
386 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
387 {
388 if (interpolate == TGSI_INTERPOLATE_COLOR ||
389 interpolate == TGSI_INTERPOLATE_LINEAR ||
390 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
391 {
392 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
393 int loc;
394
395 switch(location) {
396 case TGSI_INTERPOLATE_LOC_CENTER:
397 loc = 1;
398 break;
399 case TGSI_INTERPOLATE_LOC_CENTROID:
400 loc = 2;
401 break;
402 case TGSI_INTERPOLATE_LOC_SAMPLE:
403 default:
404 loc = 0; break;
405 }
406
407 return is_linear * 3 + loc;
408 }
409
410 return -1;
411 }
412
413 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
414 int input)
415 {
416 int i = eg_get_interpolator_index(
417 ctx->shader->input[input].interpolate,
418 ctx->shader->input[input].interpolate_location);
419 assert(i >= 0);
420 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
421 }
422
423 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
424 {
425 int i, r;
426 struct r600_bytecode_alu alu;
427 int gpr = 0, base_chan = 0;
428 int ij_index = ctx->shader->input[input].ij_index;
429
430 /* work out gpr and base_chan from index */
431 gpr = ij_index / 2;
432 base_chan = (2 * (ij_index % 2)) + 1;
433
434 for (i = 0; i < 8; i++) {
435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
436
437 if (i < 4)
438 alu.op = ALU_OP2_INTERP_ZW;
439 else
440 alu.op = ALU_OP2_INTERP_XY;
441
442 if ((i > 1) && (i < 6)) {
443 alu.dst.sel = ctx->shader->input[input].gpr;
444 alu.dst.write = 1;
445 }
446
447 alu.dst.chan = i % 4;
448
449 alu.src[0].sel = gpr;
450 alu.src[0].chan = (base_chan - (i % 2));
451
452 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
453
454 alu.bank_swizzle_force = SQ_ALU_VEC_210;
455 if ((i % 4) == 3)
456 alu.last = 1;
457 r = r600_bytecode_add_alu(ctx->bc, &alu);
458 if (r)
459 return r;
460 }
461 return 0;
462 }
463
464 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
465 {
466 int i, r;
467 struct r600_bytecode_alu alu;
468
469 for (i = 0; i < 4; i++) {
470 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
471
472 alu.op = ALU_OP1_INTERP_LOAD_P0;
473
474 alu.dst.sel = ctx->shader->input[input].gpr;
475 alu.dst.write = 1;
476
477 alu.dst.chan = i;
478
479 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
480 alu.src[0].chan = i;
481
482 if (i == 3)
483 alu.last = 1;
484 r = r600_bytecode_add_alu(ctx->bc, &alu);
485 if (r)
486 return r;
487 }
488 return 0;
489 }
490
491 /*
492 * Special export handling in shaders
493 *
494 * shader export ARRAY_BASE for EXPORT_POS:
495 * 60 is position
496 * 61 is misc vector
497 * 62, 63 are clip distance vectors
498 *
499 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
500 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
501 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
502 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
503 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
504 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
505 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
506 * exclusive from render target index)
507 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
508 *
509 *
510 * shader export ARRAY_BASE for EXPORT_PIXEL:
511 * 0-7 CB targets
512 * 61 computed Z vector
513 *
514 * The use of the values exported in the computed Z vector are controlled
515 * by DB_SHADER_CONTROL:
516 * Z_EXPORT_ENABLE - Z as a float in RED
517 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
518 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
519 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
520 * DB_SOURCE_FORMAT - export control restrictions
521 *
522 */
523
524
525 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
526 static int r600_spi_sid(struct r600_shader_io * io)
527 {
528 int index, name = io->name;
529
530 /* These params are handled differently, they don't need
531 * semantic indices, so we'll use 0 for them.
532 */
533 if (name == TGSI_SEMANTIC_POSITION ||
534 name == TGSI_SEMANTIC_PSIZE ||
535 name == TGSI_SEMANTIC_EDGEFLAG ||
536 name == TGSI_SEMANTIC_FACE ||
537 name == TGSI_SEMANTIC_SAMPLEMASK)
538 index = 0;
539 else {
540 if (name == TGSI_SEMANTIC_GENERIC) {
541 /* For generic params simply use sid from tgsi */
542 index = io->sid;
543 } else {
544 /* For non-generic params - pack name and sid into 8 bits */
545 index = 0x80 | (name<<3) | (io->sid);
546 }
547
548 /* Make sure that all really used indices have nonzero value, so
549 * we can just compare it to 0 later instead of comparing the name
550 * with different values to detect special cases. */
551 index++;
552 }
553
554 return index;
555 };
556
557 /* turn input into interpolate on EG */
558 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
559 {
560 int r = 0;
561
562 if (ctx->shader->input[index].spi_sid) {
563 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
564 if (ctx->shader->input[index].interpolate > 0) {
565 evergreen_interp_assign_ij_index(ctx, index);
566 if (!ctx->use_llvm)
567 r = evergreen_interp_alu(ctx, index);
568 } else {
569 if (!ctx->use_llvm)
570 r = evergreen_interp_flat(ctx, index);
571 }
572 }
573 return r;
574 }
575
576 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
577 {
578 struct r600_bytecode_alu alu;
579 int i, r;
580 int gpr_front = ctx->shader->input[front].gpr;
581 int gpr_back = ctx->shader->input[back].gpr;
582
583 for (i = 0; i < 4; i++) {
584 memset(&alu, 0, sizeof(alu));
585 alu.op = ALU_OP3_CNDGT;
586 alu.is_op3 = 1;
587 alu.dst.write = 1;
588 alu.dst.sel = gpr_front;
589 alu.src[0].sel = ctx->face_gpr;
590 alu.src[1].sel = gpr_front;
591 alu.src[2].sel = gpr_back;
592
593 alu.dst.chan = i;
594 alu.src[1].chan = i;
595 alu.src[2].chan = i;
596 alu.last = (i==3);
597
598 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
599 return r;
600 }
601
602 return 0;
603 }
604
605 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
606 {
607 int i;
608 i = ctx->shader->noutput++;
609 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
610 ctx->shader->output[i].sid = 0;
611 ctx->shader->output[i].gpr = 0;
612 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
613 ctx->shader->output[i].write_mask = 0x4;
614 ctx->shader->output[i].spi_sid = prim_id_sid;
615
616 return 0;
617 }
618
619 static int tgsi_declaration(struct r600_shader_ctx *ctx)
620 {
621 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
622 int r, i, j, count = d->Range.Last - d->Range.First + 1;
623
624 switch (d->Declaration.File) {
625 case TGSI_FILE_INPUT:
626 for (j = 0; j < count; j++) {
627 i = ctx->shader->ninput + j;
628 assert(i < Elements(ctx->shader->input));
629 ctx->shader->input[i].name = d->Semantic.Name;
630 ctx->shader->input[i].sid = d->Semantic.Index + j;
631 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
632 ctx->shader->input[i].interpolate_location = d->Interp.Location;
633 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
634 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
635 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
636 switch (ctx->shader->input[i].name) {
637 case TGSI_SEMANTIC_FACE:
638 if (ctx->face_gpr != -1)
639 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
640 else
641 ctx->face_gpr = ctx->shader->input[i].gpr;
642 break;
643 case TGSI_SEMANTIC_COLOR:
644 ctx->colors_used++;
645 break;
646 case TGSI_SEMANTIC_POSITION:
647 ctx->fragcoord_input = i;
648 break;
649 case TGSI_SEMANTIC_PRIMID:
650 /* set this for now */
651 ctx->shader->gs_prim_id_input = true;
652 ctx->shader->ps_prim_id_input = i;
653 break;
654 }
655 if (ctx->bc->chip_class >= EVERGREEN) {
656 if ((r = evergreen_interp_input(ctx, i)))
657 return r;
658 }
659 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
660 /* FIXME probably skip inputs if they aren't passed in the ring */
661 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
662 ctx->next_ring_offset += 16;
663 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
664 ctx->shader->gs_prim_id_input = true;
665 }
666 }
667 ctx->shader->ninput += count;
668 break;
669 case TGSI_FILE_OUTPUT:
670 for (j = 0; j < count; j++) {
671 i = ctx->shader->noutput + j;
672 assert(i < Elements(ctx->shader->output));
673 ctx->shader->output[i].name = d->Semantic.Name;
674 ctx->shader->output[i].sid = d->Semantic.Index + j;
675 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
676 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
677 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
678 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
679 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
680 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
681 switch (d->Semantic.Name) {
682 case TGSI_SEMANTIC_CLIPDIST:
683 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
684 ((d->Semantic.Index + j) << 2);
685 break;
686 case TGSI_SEMANTIC_PSIZE:
687 ctx->shader->vs_out_misc_write = 1;
688 ctx->shader->vs_out_point_size = 1;
689 break;
690 case TGSI_SEMANTIC_EDGEFLAG:
691 ctx->shader->vs_out_misc_write = 1;
692 ctx->shader->vs_out_edgeflag = 1;
693 ctx->edgeflag_output = i;
694 break;
695 case TGSI_SEMANTIC_VIEWPORT_INDEX:
696 ctx->shader->vs_out_misc_write = 1;
697 ctx->shader->vs_out_viewport = 1;
698 break;
699 case TGSI_SEMANTIC_LAYER:
700 ctx->shader->vs_out_misc_write = 1;
701 ctx->shader->vs_out_layer = 1;
702 break;
703 case TGSI_SEMANTIC_CLIPVERTEX:
704 ctx->clip_vertex_write = TRUE;
705 ctx->cv_output = i;
706 break;
707 }
708 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
709 ctx->gs_out_ring_offset += 16;
710 }
711 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
712 switch (d->Semantic.Name) {
713 case TGSI_SEMANTIC_COLOR:
714 ctx->shader->nr_ps_max_color_exports++;
715 break;
716 }
717 }
718 }
719 ctx->shader->noutput += count;
720 break;
721 case TGSI_FILE_TEMPORARY:
722 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
723 if (d->Array.ArrayID) {
724 r600_add_gpr_array(ctx->shader,
725 ctx->file_offset[TGSI_FILE_TEMPORARY] +
726 d->Range.First,
727 d->Range.Last - d->Range.First + 1, 0x0F);
728 }
729 }
730 break;
731
732 case TGSI_FILE_CONSTANT:
733 case TGSI_FILE_SAMPLER:
734 case TGSI_FILE_SAMPLER_VIEW:
735 case TGSI_FILE_ADDRESS:
736 break;
737
738 case TGSI_FILE_SYSTEM_VALUE:
739 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
740 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
741 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
742 break; /* Already handled from allocate_system_value_inputs */
743 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
744 if (!ctx->native_integers) {
745 struct r600_bytecode_alu alu;
746 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
747
748 alu.op = ALU_OP1_INT_TO_FLT;
749 alu.src[0].sel = 0;
750 alu.src[0].chan = 3;
751
752 alu.dst.sel = 0;
753 alu.dst.chan = 3;
754 alu.dst.write = 1;
755 alu.last = 1;
756
757 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
758 return r;
759 }
760 break;
761 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
762 break;
763 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
764 break;
765 default:
766 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
767 return -EINVAL;
768 }
769 return 0;
770 }
771
772 static int r600_get_temp(struct r600_shader_ctx *ctx)
773 {
774 return ctx->temp_reg + ctx->max_driver_temp_used++;
775 }
776
777 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
778 {
779 struct tgsi_parse_context parse;
780 struct {
781 boolean enabled;
782 int *reg;
783 unsigned name, alternate_name;
784 } inputs[2] = {
785 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
786
787 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
788 };
789 int i, k, num_regs = 0;
790
791 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
792 return 0;
793 }
794
795 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
796 while (!tgsi_parse_end_of_tokens(&parse)) {
797 tgsi_parse_token(&parse);
798
799 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
800 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
801 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
802 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
803 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
804 {
805 int interpolate, location, k;
806
807 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
808 location = TGSI_INTERPOLATE_LOC_CENTER;
809 inputs[1].enabled = true; /* needs SAMPLEID */
810 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
811 location = TGSI_INTERPOLATE_LOC_CENTER;
812 /* Needs sample positions, currently those are always available */
813 } else {
814 location = TGSI_INTERPOLATE_LOC_CENTROID;
815 }
816
817 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
818 k = eg_get_interpolator_index(interpolate, location);
819 ctx->eg_interpolators[k].enabled = true;
820 }
821 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
822 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
823 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
824 for (k = 0; k < Elements(inputs); k++) {
825 if (d->Semantic.Name == inputs[k].name ||
826 d->Semantic.Name == inputs[k].alternate_name) {
827 inputs[k].enabled = true;
828 }
829 }
830 }
831 }
832 }
833
834 tgsi_parse_free(&parse);
835
836 for (i = 0; i < Elements(inputs); i++) {
837 boolean enabled = inputs[i].enabled;
838 int *reg = inputs[i].reg;
839 unsigned name = inputs[i].name;
840
841 if (enabled) {
842 int gpr = gpr_offset + num_regs++;
843
844 // add to inputs, allocate a gpr
845 k = ctx->shader->ninput ++;
846 ctx->shader->input[k].name = name;
847 ctx->shader->input[k].sid = 0;
848 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
849 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
850 *reg = ctx->shader->input[k].gpr = gpr;
851 }
852 }
853
854 return gpr_offset + num_regs;
855 }
856
857 /*
858 * for evergreen we need to scan the shader to find the number of GPRs we need to
859 * reserve for interpolation and system values
860 *
861 * we need to know if we are going to emit
862 * any sample or centroid inputs
863 * if perspective and linear are required
864 */
865 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
866 {
867 int i;
868 int num_baryc;
869 struct tgsi_parse_context parse;
870
871 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
872
873 for (i = 0; i < ctx->info.num_inputs; i++) {
874 int k;
875 /* skip position/face/mask/sampleid */
876 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
877 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
878 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
879 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
880 continue;
881
882 k = eg_get_interpolator_index(
883 ctx->info.input_interpolate[i],
884 ctx->info.input_interpolate_loc[i]);
885 if (k >= 0)
886 ctx->eg_interpolators[k].enabled = TRUE;
887 }
888
889 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
890 return 0;
891 }
892
893 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
894 while (!tgsi_parse_end_of_tokens(&parse)) {
895 tgsi_parse_token(&parse);
896
897 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
898 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
899 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
900 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
901 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
902 {
903 int interpolate, location, k;
904
905 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
906 location = TGSI_INTERPOLATE_LOC_CENTER;
907 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
908 location = TGSI_INTERPOLATE_LOC_CENTER;
909 } else {
910 location = TGSI_INTERPOLATE_LOC_CENTROID;
911 }
912
913 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
914 k = eg_get_interpolator_index(interpolate, location);
915 ctx->eg_interpolators[k].enabled = true;
916 }
917 }
918 }
919
920 tgsi_parse_free(&parse);
921
922 /* assign gpr to each interpolator according to priority */
923 num_baryc = 0;
924 for (i = 0; i < Elements(ctx->eg_interpolators); i++) {
925 if (ctx->eg_interpolators[i].enabled) {
926 ctx->eg_interpolators[i].ij_index = num_baryc;
927 num_baryc ++;
928 }
929 }
930
931 /* XXX PULL MODEL and LINE STIPPLE */
932
933 num_baryc = (num_baryc + 1) >> 1;
934 return allocate_system_value_inputs(ctx, num_baryc);
935 }
936
937 /* sample_id_sel == NULL means fetch for current sample */
938 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
939 {
940 struct r600_bytecode_vtx vtx;
941 int r, t1;
942
943 assert(ctx->fixed_pt_position_gpr != -1);
944
945 t1 = r600_get_temp(ctx);
946
947 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
948 vtx.op = FETCH_OP_VFETCH;
949 vtx.buffer_id = R600_SAMPLE_POSITIONS_CONST_BUFFER;
950 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
951 if (sample_id == NULL) {
952 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
953 vtx.src_sel_x = 3;
954 }
955 else {
956 struct r600_bytecode_alu alu;
957
958 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
959 alu.op = ALU_OP1_MOV;
960 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
961 alu.dst.sel = t1;
962 alu.dst.write = 1;
963 alu.last = 1;
964 r = r600_bytecode_add_alu(ctx->bc, &alu);
965 if (r)
966 return r;
967
968 vtx.src_gpr = t1;
969 vtx.src_sel_x = 0;
970 }
971 vtx.mega_fetch_count = 16;
972 vtx.dst_gpr = t1;
973 vtx.dst_sel_x = 0;
974 vtx.dst_sel_y = 1;
975 vtx.dst_sel_z = 2;
976 vtx.dst_sel_w = 3;
977 vtx.data_format = FMT_32_32_32_32_FLOAT;
978 vtx.num_format_all = 2;
979 vtx.format_comp_all = 1;
980 vtx.use_const_fields = 0;
981 vtx.offset = 1; // first element is size of buffer
982 vtx.endian = r600_endian_swap(32);
983 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
984
985 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
986 if (r)
987 return r;
988
989 return t1;
990 }
991
992 static void tgsi_src(struct r600_shader_ctx *ctx,
993 const struct tgsi_full_src_register *tgsi_src,
994 struct r600_shader_src *r600_src)
995 {
996 memset(r600_src, 0, sizeof(*r600_src));
997 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
998 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
999 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1000 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1001 r600_src->neg = tgsi_src->Register.Negate;
1002 r600_src->abs = tgsi_src->Register.Absolute;
1003
1004 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1005 int index;
1006 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1007 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1008 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1009
1010 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1011 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
1012 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1013 return;
1014 }
1015 index = tgsi_src->Register.Index;
1016 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1017 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1018 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1019 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1020 r600_src->swizzle[0] = 2; // Z value
1021 r600_src->swizzle[1] = 2;
1022 r600_src->swizzle[2] = 2;
1023 r600_src->swizzle[3] = 2;
1024 r600_src->sel = ctx->face_gpr;
1025 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1026 r600_src->swizzle[0] = 3; // W value
1027 r600_src->swizzle[1] = 3;
1028 r600_src->swizzle[2] = 3;
1029 r600_src->swizzle[3] = 3;
1030 r600_src->sel = ctx->fixed_pt_position_gpr;
1031 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1032 r600_src->swizzle[0] = 0;
1033 r600_src->swizzle[1] = 1;
1034 r600_src->swizzle[2] = 4;
1035 r600_src->swizzle[3] = 4;
1036 r600_src->sel = load_sample_position(ctx, NULL, -1);
1037 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1038 r600_src->swizzle[0] = 3;
1039 r600_src->swizzle[1] = 3;
1040 r600_src->swizzle[2] = 3;
1041 r600_src->swizzle[3] = 3;
1042 r600_src->sel = 0;
1043 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1044 r600_src->swizzle[0] = 0;
1045 r600_src->swizzle[1] = 0;
1046 r600_src->swizzle[2] = 0;
1047 r600_src->swizzle[3] = 0;
1048 r600_src->sel = 0;
1049 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1050 r600_src->swizzle[0] = 3;
1051 r600_src->swizzle[1] = 3;
1052 r600_src->swizzle[2] = 3;
1053 r600_src->swizzle[3] = 3;
1054 r600_src->sel = 1;
1055 }
1056 } else {
1057 if (tgsi_src->Register.Indirect)
1058 r600_src->rel = V_SQ_REL_RELATIVE;
1059 r600_src->sel = tgsi_src->Register.Index;
1060 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1061 }
1062 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1063 if (tgsi_src->Register.Dimension) {
1064 r600_src->kc_bank = tgsi_src->Dimension.Index;
1065 if (tgsi_src->Dimension.Indirect) {
1066 r600_src->kc_rel = 1;
1067 }
1068 }
1069 }
1070 }
1071
1072 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1073 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1074 unsigned int dst_reg)
1075 {
1076 struct r600_bytecode_vtx vtx;
1077 unsigned int ar_reg;
1078 int r;
1079
1080 if (offset) {
1081 struct r600_bytecode_alu alu;
1082
1083 memset(&alu, 0, sizeof(alu));
1084
1085 alu.op = ALU_OP2_ADD_INT;
1086 alu.src[0].sel = ctx->bc->ar_reg;
1087 alu.src[0].chan = ar_chan;
1088
1089 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1090 alu.src[1].value = offset;
1091
1092 alu.dst.sel = dst_reg;
1093 alu.dst.chan = ar_chan;
1094 alu.dst.write = 1;
1095 alu.last = 1;
1096
1097 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1098 return r;
1099
1100 ar_reg = dst_reg;
1101 } else {
1102 ar_reg = ctx->bc->ar_reg;
1103 }
1104
1105 memset(&vtx, 0, sizeof(vtx));
1106 vtx.buffer_id = cb_idx;
1107 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1108 vtx.src_gpr = ar_reg;
1109 vtx.src_sel_x = ar_chan;
1110 vtx.mega_fetch_count = 16;
1111 vtx.dst_gpr = dst_reg;
1112 vtx.dst_sel_x = 0; /* SEL_X */
1113 vtx.dst_sel_y = 1; /* SEL_Y */
1114 vtx.dst_sel_z = 2; /* SEL_Z */
1115 vtx.dst_sel_w = 3; /* SEL_W */
1116 vtx.data_format = FMT_32_32_32_32_FLOAT;
1117 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1118 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1119 vtx.endian = r600_endian_swap(32);
1120 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1121
1122 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1123 return r;
1124
1125 return 0;
1126 }
1127
1128 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1129 {
1130 struct r600_bytecode_vtx vtx;
1131 int r;
1132 unsigned index = src->Register.Index;
1133 unsigned vtx_id = src->Dimension.Index;
1134 int offset_reg = vtx_id / 3;
1135 int offset_chan = vtx_id % 3;
1136
1137 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1138 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1139
1140 if (offset_reg == 0 && offset_chan == 2)
1141 offset_chan = 3;
1142
1143 if (src->Dimension.Indirect) {
1144 int treg[3];
1145 int t2;
1146 struct r600_bytecode_alu alu;
1147 int r, i;
1148
1149 /* you have got to be shitting me -
1150 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1151 at least this is what fglrx seems to do. */
1152 for (i = 0; i < 3; i++) {
1153 treg[i] = r600_get_temp(ctx);
1154 }
1155 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1156
1157 t2 = r600_get_temp(ctx);
1158 for (i = 0; i < 3; i++) {
1159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1160 alu.op = ALU_OP1_MOV;
1161 alu.src[0].sel = 0;
1162 alu.src[0].chan = i == 2 ? 3 : i;
1163 alu.dst.sel = treg[i];
1164 alu.dst.chan = 0;
1165 alu.dst.write = 1;
1166 alu.last = 1;
1167 r = r600_bytecode_add_alu(ctx->bc, &alu);
1168 if (r)
1169 return r;
1170 }
1171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1172 alu.op = ALU_OP1_MOV;
1173 alu.src[0].sel = treg[0];
1174 alu.src[0].rel = 1;
1175 alu.dst.sel = t2;
1176 alu.dst.write = 1;
1177 alu.last = 1;
1178 r = r600_bytecode_add_alu(ctx->bc, &alu);
1179 if (r)
1180 return r;
1181 offset_reg = t2;
1182 }
1183
1184
1185 memset(&vtx, 0, sizeof(vtx));
1186 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1187 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1188 vtx.src_gpr = offset_reg;
1189 vtx.src_sel_x = offset_chan;
1190 vtx.offset = index * 16; /*bytes*/
1191 vtx.mega_fetch_count = 16;
1192 vtx.dst_gpr = dst_reg;
1193 vtx.dst_sel_x = 0; /* SEL_X */
1194 vtx.dst_sel_y = 1; /* SEL_Y */
1195 vtx.dst_sel_z = 2; /* SEL_Z */
1196 vtx.dst_sel_w = 3; /* SEL_W */
1197 if (ctx->bc->chip_class >= EVERGREEN) {
1198 vtx.use_const_fields = 1;
1199 } else {
1200 vtx.data_format = FMT_32_32_32_32_FLOAT;
1201 }
1202
1203 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1204 return r;
1205
1206 return 0;
1207 }
1208
1209 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1210 {
1211 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1212 int i;
1213
1214 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1215 struct tgsi_full_src_register *src = &inst->Src[i];
1216
1217 if (src->Register.File == TGSI_FILE_INPUT) {
1218 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1219 /* primitive id is in R0.z */
1220 ctx->src[i].sel = 0;
1221 ctx->src[i].swizzle[0] = 2;
1222 }
1223 }
1224 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1225 int treg = r600_get_temp(ctx);
1226
1227 fetch_gs_input(ctx, src, treg);
1228 ctx->src[i].sel = treg;
1229 }
1230 }
1231 return 0;
1232 }
1233
1234 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1235 {
1236 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1237 struct r600_bytecode_alu alu;
1238 int i, j, k, nconst, r;
1239
1240 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1241 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1242 nconst++;
1243 }
1244 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1245 }
1246 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1247 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1248 continue;
1249 }
1250
1251 if (ctx->src[i].kc_rel)
1252 ctx->shader->uses_index_registers = true;
1253
1254 if (ctx->src[i].rel) {
1255 int chan = inst->Src[i].Indirect.Swizzle;
1256 int treg = r600_get_temp(ctx);
1257 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1258 return r;
1259
1260 ctx->src[i].kc_bank = 0;
1261 ctx->src[i].kc_rel = 0;
1262 ctx->src[i].sel = treg;
1263 ctx->src[i].rel = 0;
1264 j--;
1265 } else if (j > 0) {
1266 int treg = r600_get_temp(ctx);
1267 for (k = 0; k < 4; k++) {
1268 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1269 alu.op = ALU_OP1_MOV;
1270 alu.src[0].sel = ctx->src[i].sel;
1271 alu.src[0].chan = k;
1272 alu.src[0].rel = ctx->src[i].rel;
1273 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1274 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1275 alu.dst.sel = treg;
1276 alu.dst.chan = k;
1277 alu.dst.write = 1;
1278 if (k == 3)
1279 alu.last = 1;
1280 r = r600_bytecode_add_alu(ctx->bc, &alu);
1281 if (r)
1282 return r;
1283 }
1284 ctx->src[i].sel = treg;
1285 ctx->src[i].rel =0;
1286 j--;
1287 }
1288 }
1289 return 0;
1290 }
1291
1292 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1293 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1294 {
1295 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1296 struct r600_bytecode_alu alu;
1297 int i, j, k, nliteral, r;
1298
1299 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1300 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1301 nliteral++;
1302 }
1303 }
1304 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1305 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1306 int treg = r600_get_temp(ctx);
1307 for (k = 0; k < 4; k++) {
1308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1309 alu.op = ALU_OP1_MOV;
1310 alu.src[0].sel = ctx->src[i].sel;
1311 alu.src[0].chan = k;
1312 alu.src[0].value = ctx->src[i].value[k];
1313 alu.dst.sel = treg;
1314 alu.dst.chan = k;
1315 alu.dst.write = 1;
1316 if (k == 3)
1317 alu.last = 1;
1318 r = r600_bytecode_add_alu(ctx->bc, &alu);
1319 if (r)
1320 return r;
1321 }
1322 ctx->src[i].sel = treg;
1323 j--;
1324 }
1325 }
1326 return 0;
1327 }
1328
1329 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1330 {
1331 int i, r, count = ctx->shader->ninput;
1332
1333 for (i = 0; i < count; i++) {
1334 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1335 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1336 if (r)
1337 return r;
1338 }
1339 }
1340 return 0;
1341 }
1342
1343 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1344 int stream, unsigned *stream_item_size)
1345 {
1346 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1347 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1348 int i, j, r;
1349
1350 /* Sanity checking. */
1351 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1352 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1353 r = -EINVAL;
1354 goto out_err;
1355 }
1356 for (i = 0; i < so->num_outputs; i++) {
1357 if (so->output[i].output_buffer >= 4) {
1358 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1359 so->output[i].output_buffer);
1360 r = -EINVAL;
1361 goto out_err;
1362 }
1363 }
1364
1365 /* Initialize locations where the outputs are stored. */
1366 for (i = 0; i < so->num_outputs; i++) {
1367
1368 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1369 start_comp[i] = so->output[i].start_component;
1370 /* Lower outputs with dst_offset < start_component.
1371 *
1372 * We can only output 4D vectors with a write mask, e.g. we can
1373 * only output the W component at offset 3, etc. If we want
1374 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1375 * to move it to X and output X. */
1376 if (so->output[i].dst_offset < so->output[i].start_component) {
1377 unsigned tmp = r600_get_temp(ctx);
1378
1379 for (j = 0; j < so->output[i].num_components; j++) {
1380 struct r600_bytecode_alu alu;
1381 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1382 alu.op = ALU_OP1_MOV;
1383 alu.src[0].sel = so_gpr[i];
1384 alu.src[0].chan = so->output[i].start_component + j;
1385
1386 alu.dst.sel = tmp;
1387 alu.dst.chan = j;
1388 alu.dst.write = 1;
1389 if (j == so->output[i].num_components - 1)
1390 alu.last = 1;
1391 r = r600_bytecode_add_alu(ctx->bc, &alu);
1392 if (r)
1393 return r;
1394 }
1395 start_comp[i] = 0;
1396 so_gpr[i] = tmp;
1397 }
1398 }
1399
1400 /* Write outputs to buffers. */
1401 for (i = 0; i < so->num_outputs; i++) {
1402 struct r600_bytecode_output output;
1403
1404 if (stream != -1 && stream != so->output[i].output_buffer)
1405 continue;
1406
1407 memset(&output, 0, sizeof(struct r600_bytecode_output));
1408 output.gpr = so_gpr[i];
1409 output.elem_size = so->output[i].num_components - 1;
1410 if (output.elem_size == 2)
1411 output.elem_size = 3; // 3 not supported, write 4 with junk at end
1412 output.array_base = so->output[i].dst_offset - start_comp[i];
1413 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1414 output.burst_count = 1;
1415 /* array_size is an upper limit for the burst_count
1416 * with MEM_STREAM instructions */
1417 output.array_size = 0xFFF;
1418 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
1419
1420 if (ctx->bc->chip_class >= EVERGREEN) {
1421 switch (so->output[i].output_buffer) {
1422 case 0:
1423 output.op = CF_OP_MEM_STREAM0_BUF0;
1424 break;
1425 case 1:
1426 output.op = CF_OP_MEM_STREAM0_BUF1;
1427 break;
1428 case 2:
1429 output.op = CF_OP_MEM_STREAM0_BUF2;
1430 break;
1431 case 3:
1432 output.op = CF_OP_MEM_STREAM0_BUF3;
1433 break;
1434 }
1435 output.op += so->output[i].stream * 4;
1436 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
1437 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
1438 } else {
1439 switch (so->output[i].output_buffer) {
1440 case 0:
1441 output.op = CF_OP_MEM_STREAM0;
1442 break;
1443 case 1:
1444 output.op = CF_OP_MEM_STREAM1;
1445 break;
1446 case 2:
1447 output.op = CF_OP_MEM_STREAM2;
1448 break;
1449 case 3:
1450 output.op = CF_OP_MEM_STREAM3;
1451 break;
1452 }
1453 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
1454 }
1455 r = r600_bytecode_add_output(ctx->bc, &output);
1456 if (r)
1457 goto out_err;
1458 }
1459 return 0;
1460 out_err:
1461 return r;
1462 }
1463
1464 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
1465 {
1466 struct r600_bytecode_alu alu;
1467 unsigned reg;
1468
1469 if (!ctx->shader->vs_out_edgeflag)
1470 return;
1471
1472 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
1473
1474 /* clamp(x, 0, 1) */
1475 memset(&alu, 0, sizeof(alu));
1476 alu.op = ALU_OP1_MOV;
1477 alu.src[0].sel = reg;
1478 alu.dst.sel = reg;
1479 alu.dst.write = 1;
1480 alu.dst.clamp = 1;
1481 alu.last = 1;
1482 r600_bytecode_add_alu(ctx->bc, &alu);
1483
1484 memset(&alu, 0, sizeof(alu));
1485 alu.op = ALU_OP1_FLT_TO_INT;
1486 alu.src[0].sel = reg;
1487 alu.dst.sel = reg;
1488 alu.dst.write = 1;
1489 alu.last = 1;
1490 r600_bytecode_add_alu(ctx->bc, &alu);
1491 }
1492
1493 static int generate_gs_copy_shader(struct r600_context *rctx,
1494 struct r600_pipe_shader *gs,
1495 struct pipe_stream_output_info *so)
1496 {
1497 struct r600_shader_ctx ctx = {};
1498 struct r600_shader *gs_shader = &gs->shader;
1499 struct r600_pipe_shader *cshader;
1500 int ocnt = gs_shader->noutput;
1501 struct r600_bytecode_alu alu;
1502 struct r600_bytecode_vtx vtx;
1503 struct r600_bytecode_output output;
1504 struct r600_bytecode_cf *cf_jump, *cf_pop,
1505 *last_exp_pos = NULL, *last_exp_param = NULL;
1506 int i, j, next_clip_pos = 61, next_param = 0;
1507 int ring;
1508
1509 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1510 if (!cshader)
1511 return 0;
1512
1513 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1514 sizeof(struct r600_shader_io));
1515
1516 cshader->shader.noutput = ocnt;
1517
1518 ctx.shader = &cshader->shader;
1519 ctx.bc = &ctx.shader->bc;
1520 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1521
1522 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1523 rctx->screen->has_compressed_msaa_texturing);
1524
1525 ctx.bc->isa = rctx->isa;
1526
1527 cf_jump = NULL;
1528 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
1529
1530 /* R0.x = R0.x & 0x3fffffff */
1531 memset(&alu, 0, sizeof(alu));
1532 alu.op = ALU_OP2_AND_INT;
1533 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1534 alu.src[1].value = 0x3fffffff;
1535 alu.dst.write = 1;
1536 r600_bytecode_add_alu(ctx.bc, &alu);
1537
1538 /* R0.y = R0.x >> 30 */
1539 memset(&alu, 0, sizeof(alu));
1540 alu.op = ALU_OP2_LSHR_INT;
1541 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1542 alu.src[1].value = 0x1e;
1543 alu.dst.chan = 1;
1544 alu.dst.write = 1;
1545 alu.last = 1;
1546 r600_bytecode_add_alu(ctx.bc, &alu);
1547
1548 /* fetch vertex data from GSVS ring */
1549 for (i = 0; i < ocnt; ++i) {
1550 struct r600_shader_io *out = &ctx.shader->output[i];
1551
1552 out->gpr = i + 1;
1553 out->ring_offset = i * 16;
1554
1555 memset(&vtx, 0, sizeof(vtx));
1556 vtx.op = FETCH_OP_VFETCH;
1557 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1558 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1559 vtx.offset = out->ring_offset;
1560 vtx.dst_gpr = out->gpr;
1561 vtx.src_gpr = 0;
1562 vtx.dst_sel_x = 0;
1563 vtx.dst_sel_y = 1;
1564 vtx.dst_sel_z = 2;
1565 vtx.dst_sel_w = 3;
1566 if (rctx->b.chip_class >= EVERGREEN) {
1567 vtx.use_const_fields = 1;
1568 } else {
1569 vtx.data_format = FMT_32_32_32_32_FLOAT;
1570 }
1571
1572 r600_bytecode_add_vtx(ctx.bc, &vtx);
1573 }
1574 ctx.temp_reg = i + 1;
1575 for (ring = 3; ring >= 0; --ring) {
1576 bool enabled = false;
1577 for (i = 0; i < so->num_outputs; i++) {
1578 if (so->output[i].stream == ring) {
1579 enabled = true;
1580 break;
1581 }
1582 }
1583 if (ring != 0 && !enabled) {
1584 cshader->shader.ring_item_sizes[ring] = 0;
1585 continue;
1586 }
1587
1588 if (cf_jump) {
1589 // Patch up jump label
1590 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1591 cf_pop = ctx.bc->cf_last;
1592
1593 cf_jump->cf_addr = cf_pop->id + 2;
1594 cf_jump->pop_count = 1;
1595 cf_pop->cf_addr = cf_pop->id + 2;
1596 cf_pop->pop_count = 1;
1597 }
1598
1599 /* PRED_SETE_INT __, R0.y, ring */
1600 memset(&alu, 0, sizeof(alu));
1601 alu.op = ALU_OP2_PRED_SETE_INT;
1602 alu.src[0].chan = 1;
1603 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1604 alu.src[1].value = ring;
1605 alu.execute_mask = 1;
1606 alu.update_pred = 1;
1607 alu.last = 1;
1608 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1609
1610 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1611 cf_jump = ctx.bc->cf_last;
1612
1613 if (enabled)
1614 emit_streamout(&ctx, so, ring, &cshader->shader.ring_item_sizes[ring]);
1615 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
1616 }
1617
1618 /* export vertex data */
1619 /* XXX factor out common code with r600_shader_from_tgsi ? */
1620 for (i = 0; i < ocnt; ++i) {
1621 struct r600_shader_io *out = &ctx.shader->output[i];
1622 bool instream0 = true;
1623 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1624 continue;
1625
1626 for (j = 0; j < so->num_outputs; j++) {
1627 if (so->output[j].register_index == i) {
1628 if (so->output[j].stream == 0)
1629 break;
1630 if (so->output[j].stream > 0)
1631 instream0 = false;
1632 }
1633 }
1634 if (!instream0)
1635 continue;
1636 memset(&output, 0, sizeof(output));
1637 output.gpr = out->gpr;
1638 output.elem_size = 3;
1639 output.swizzle_x = 0;
1640 output.swizzle_y = 1;
1641 output.swizzle_z = 2;
1642 output.swizzle_w = 3;
1643 output.burst_count = 1;
1644 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1645 output.op = CF_OP_EXPORT;
1646 switch (out->name) {
1647 case TGSI_SEMANTIC_POSITION:
1648 output.array_base = 60;
1649 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1650 break;
1651
1652 case TGSI_SEMANTIC_PSIZE:
1653 output.array_base = 61;
1654 if (next_clip_pos == 61)
1655 next_clip_pos = 62;
1656 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1657 output.swizzle_y = 7;
1658 output.swizzle_z = 7;
1659 output.swizzle_w = 7;
1660 ctx.shader->vs_out_misc_write = 1;
1661 ctx.shader->vs_out_point_size = 1;
1662 break;
1663 case TGSI_SEMANTIC_LAYER:
1664 if (out->spi_sid) {
1665 /* duplicate it as PARAM to pass to the pixel shader */
1666 output.array_base = next_param++;
1667 r600_bytecode_add_output(ctx.bc, &output);
1668 last_exp_param = ctx.bc->cf_last;
1669 }
1670 output.array_base = 61;
1671 if (next_clip_pos == 61)
1672 next_clip_pos = 62;
1673 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1674 output.swizzle_x = 7;
1675 output.swizzle_y = 7;
1676 output.swizzle_z = 0;
1677 output.swizzle_w = 7;
1678 ctx.shader->vs_out_misc_write = 1;
1679 ctx.shader->vs_out_layer = 1;
1680 break;
1681 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1682 if (out->spi_sid) {
1683 /* duplicate it as PARAM to pass to the pixel shader */
1684 output.array_base = next_param++;
1685 r600_bytecode_add_output(ctx.bc, &output);
1686 last_exp_param = ctx.bc->cf_last;
1687 }
1688 output.array_base = 61;
1689 if (next_clip_pos == 61)
1690 next_clip_pos = 62;
1691 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1692 ctx.shader->vs_out_misc_write = 1;
1693 ctx.shader->vs_out_viewport = 1;
1694 output.swizzle_x = 7;
1695 output.swizzle_y = 7;
1696 output.swizzle_z = 7;
1697 output.swizzle_w = 0;
1698 break;
1699 case TGSI_SEMANTIC_CLIPDIST:
1700 /* spi_sid is 0 for clipdistance outputs that were generated
1701 * for clipvertex - we don't need to pass them to PS */
1702 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
1703 if (out->spi_sid) {
1704 /* duplicate it as PARAM to pass to the pixel shader */
1705 output.array_base = next_param++;
1706 r600_bytecode_add_output(ctx.bc, &output);
1707 last_exp_param = ctx.bc->cf_last;
1708 }
1709 output.array_base = next_clip_pos++;
1710 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1711 break;
1712 case TGSI_SEMANTIC_FOG:
1713 output.swizzle_y = 4; /* 0 */
1714 output.swizzle_z = 4; /* 0 */
1715 output.swizzle_w = 5; /* 1 */
1716 break;
1717 default:
1718 output.array_base = next_param++;
1719 break;
1720 }
1721 r600_bytecode_add_output(ctx.bc, &output);
1722 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1723 last_exp_param = ctx.bc->cf_last;
1724 else
1725 last_exp_pos = ctx.bc->cf_last;
1726 }
1727
1728 if (!last_exp_pos) {
1729 memset(&output, 0, sizeof(output));
1730 output.gpr = 0;
1731 output.elem_size = 3;
1732 output.swizzle_x = 7;
1733 output.swizzle_y = 7;
1734 output.swizzle_z = 7;
1735 output.swizzle_w = 7;
1736 output.burst_count = 1;
1737 output.type = 2;
1738 output.op = CF_OP_EXPORT;
1739 output.array_base = 60;
1740 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1741 r600_bytecode_add_output(ctx.bc, &output);
1742 last_exp_pos = ctx.bc->cf_last;
1743 }
1744
1745 if (!last_exp_param) {
1746 memset(&output, 0, sizeof(output));
1747 output.gpr = 0;
1748 output.elem_size = 3;
1749 output.swizzle_x = 7;
1750 output.swizzle_y = 7;
1751 output.swizzle_z = 7;
1752 output.swizzle_w = 7;
1753 output.burst_count = 1;
1754 output.type = 2;
1755 output.op = CF_OP_EXPORT;
1756 output.array_base = next_param++;
1757 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1758 r600_bytecode_add_output(ctx.bc, &output);
1759 last_exp_param = ctx.bc->cf_last;
1760 }
1761
1762 last_exp_pos->op = CF_OP_EXPORT_DONE;
1763 last_exp_param->op = CF_OP_EXPORT_DONE;
1764
1765 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1766 cf_pop = ctx.bc->cf_last;
1767
1768 cf_jump->cf_addr = cf_pop->id + 2;
1769 cf_jump->pop_count = 1;
1770 cf_pop->cf_addr = cf_pop->id + 2;
1771 cf_pop->pop_count = 1;
1772
1773 if (ctx.bc->chip_class == CAYMAN)
1774 cm_bytecode_add_cf_end(ctx.bc);
1775 else {
1776 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1777 ctx.bc->cf_last->end_of_program = 1;
1778 }
1779
1780 gs->gs_copy_shader = cshader;
1781 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
1782
1783 ctx.bc->nstack = 1;
1784
1785 return r600_bytecode_build(ctx.bc);
1786 }
1787
1788 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
1789 {
1790 struct r600_bytecode_output output;
1791 int i, k, ring_offset;
1792 int effective_stream = stream == -1 ? 0 : stream;
1793 int idx = 0;
1794
1795 for (i = 0; i < ctx->shader->noutput; i++) {
1796 if (ctx->gs_for_vs) {
1797 /* for ES we need to lookup corresponding ring offset expected by GS
1798 * (map this output to GS input by name and sid) */
1799 /* FIXME precompute offsets */
1800 ring_offset = -1;
1801 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1802 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1803 struct r600_shader_io *out = &ctx->shader->output[i];
1804 if (in->name == out->name && in->sid == out->sid)
1805 ring_offset = in->ring_offset;
1806 }
1807
1808 if (ring_offset == -1)
1809 continue;
1810 } else {
1811 ring_offset = idx * 16;
1812 idx++;
1813 }
1814
1815 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
1816 continue;
1817 /* next_ring_offset after parsing input decls contains total size of
1818 * single vertex data, gs_next_vertex - current vertex index */
1819 if (!ind)
1820 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
1821
1822 memset(&output, 0, sizeof(struct r600_bytecode_output));
1823 output.gpr = ctx->shader->output[i].gpr;
1824 output.elem_size = 3;
1825 output.comp_mask = 0xF;
1826 output.burst_count = 1;
1827
1828 if (ind)
1829 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
1830 else
1831 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1832
1833 switch (stream) {
1834 default:
1835 case 0:
1836 output.op = CF_OP_MEM_RING; break;
1837 case 1:
1838 output.op = CF_OP_MEM_RING1; break;
1839 case 2:
1840 output.op = CF_OP_MEM_RING2; break;
1841 case 3:
1842 output.op = CF_OP_MEM_RING3; break;
1843 }
1844
1845 if (ind) {
1846 output.array_base = ring_offset >> 2; /* in dwords */
1847 output.array_size = 0xfff;
1848 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
1849 } else
1850 output.array_base = ring_offset >> 2; /* in dwords */
1851 r600_bytecode_add_output(ctx->bc, &output);
1852 }
1853
1854 if (ind) {
1855 /* get a temp and add the ring offset to the next vertex base in the shader */
1856 struct r600_bytecode_alu alu;
1857 int r;
1858
1859 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1860 alu.op = ALU_OP2_ADD_INT;
1861 alu.src[0].sel = ctx->gs_export_gpr_tregs[effective_stream];
1862 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1863 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
1864 alu.dst.sel = ctx->gs_export_gpr_tregs[effective_stream];
1865 alu.dst.write = 1;
1866 alu.last = 1;
1867 r = r600_bytecode_add_alu(ctx->bc, &alu);
1868 if (r)
1869 return r;
1870 }
1871 ++ctx->gs_next_vertex;
1872 return 0;
1873 }
1874
1875 static int r600_shader_from_tgsi(struct r600_context *rctx,
1876 struct r600_pipe_shader *pipeshader,
1877 union r600_shader_key key)
1878 {
1879 struct r600_screen *rscreen = rctx->screen;
1880 struct r600_shader *shader = &pipeshader->shader;
1881 struct tgsi_token *tokens = pipeshader->selector->tokens;
1882 struct pipe_stream_output_info so = pipeshader->selector->so;
1883 struct tgsi_full_immediate *immediate;
1884 struct r600_shader_ctx ctx;
1885 struct r600_bytecode_output output[32];
1886 unsigned output_done, noutput;
1887 unsigned opcode;
1888 int i, j, k, r = 0;
1889 int next_param_base = 0, next_clip_base;
1890 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
1891 /* Declarations used by llvm code */
1892 bool use_llvm = false;
1893 bool indirect_gprs;
1894 bool ring_outputs = false;
1895 bool pos_emitted = false;
1896
1897 #ifdef R600_USE_LLVM
1898 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
1899 #endif
1900 ctx.bc = &shader->bc;
1901 ctx.shader = shader;
1902 ctx.native_integers = true;
1903
1904 shader->vs_as_gs_a = key.vs.as_gs_a;
1905 shader->vs_as_es = key.vs.as_es;
1906
1907 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
1908 rscreen->has_compressed_msaa_texturing);
1909 ctx.tokens = tokens;
1910 tgsi_scan_shader(tokens, &ctx.info);
1911 shader->indirect_files = ctx.info.indirect_files;
1912
1913 shader->uses_doubles = ctx.info.uses_doubles;
1914
1915 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
1916 tgsi_parse_init(&ctx.parse, tokens);
1917 ctx.type = ctx.info.processor;
1918 shader->processor_type = ctx.type;
1919 ctx.bc->type = shader->processor_type;
1920
1921 ring_outputs = key.vs.as_es || (ctx.type == TGSI_PROCESSOR_GEOMETRY);
1922
1923 if (key.vs.as_es) {
1924 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
1925 } else {
1926 ctx.gs_for_vs = NULL;
1927 }
1928
1929 ctx.next_ring_offset = 0;
1930 ctx.gs_out_ring_offset = 0;
1931 ctx.gs_next_vertex = 0;
1932 ctx.gs_stream_output_info = &so;
1933
1934 shader->uses_index_registers = false;
1935 ctx.face_gpr = -1;
1936 ctx.fixed_pt_position_gpr = -1;
1937 ctx.fragcoord_input = -1;
1938 ctx.colors_used = 0;
1939 ctx.clip_vertex_write = 0;
1940
1941 shader->nr_ps_color_exports = 0;
1942 shader->nr_ps_max_color_exports = 0;
1943
1944 shader->two_side = key.ps.color_two_side;
1945
1946 /* register allocations */
1947 /* Values [0,127] correspond to GPR[0..127].
1948 * Values [128,159] correspond to constant buffer bank 0
1949 * Values [160,191] correspond to constant buffer bank 1
1950 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1951 * Values [256,287] correspond to constant buffer bank 2 (EG)
1952 * Values [288,319] correspond to constant buffer bank 3 (EG)
1953 * Other special values are shown in the list below.
1954 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1955 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1956 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1957 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1958 * 248 SQ_ALU_SRC_0: special constant 0.0.
1959 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1960 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1961 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1962 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1963 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1964 * 254 SQ_ALU_SRC_PV: previous vector result.
1965 * 255 SQ_ALU_SRC_PS: previous scalar result.
1966 */
1967 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1968 ctx.file_offset[i] = 0;
1969 }
1970
1971 #ifdef R600_USE_LLVM
1972 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1973 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1974 "indirect adressing. Falling back to TGSI "
1975 "backend.\n");
1976 use_llvm = 0;
1977 }
1978 #endif
1979 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1980 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1981 if (!use_llvm) {
1982 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1983 }
1984 }
1985 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
1986 if (ctx.bc->chip_class >= EVERGREEN)
1987 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1988 else
1989 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
1990 }
1991 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1992 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
1993 ctx.file_offset[TGSI_FILE_INPUT] = 2;
1994 }
1995 ctx.use_llvm = use_llvm;
1996
1997 if (use_llvm) {
1998 ctx.file_offset[TGSI_FILE_OUTPUT] =
1999 ctx.file_offset[TGSI_FILE_INPUT];
2000 } else {
2001 ctx.file_offset[TGSI_FILE_OUTPUT] =
2002 ctx.file_offset[TGSI_FILE_INPUT] +
2003 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2004 }
2005 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
2006 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
2007
2008 /* Outside the GPR range. This will be translated to one of the
2009 * kcache banks later. */
2010 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
2011
2012 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
2013 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
2014 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
2015 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
2016 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
2017
2018 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2019 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
2020 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
2021 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
2022 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
2023 ctx.temp_reg = ctx.bc->ar_reg + 7;
2024 } else {
2025 ctx.temp_reg = ctx.bc->ar_reg + 3;
2026 }
2027
2028 shader->max_arrays = 0;
2029 shader->num_arrays = 0;
2030 if (indirect_gprs) {
2031
2032 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
2033 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
2034 ctx.file_offset[TGSI_FILE_OUTPUT] -
2035 ctx.file_offset[TGSI_FILE_INPUT],
2036 0x0F);
2037 }
2038 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
2039 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
2040 ctx.file_offset[TGSI_FILE_TEMPORARY] -
2041 ctx.file_offset[TGSI_FILE_OUTPUT],
2042 0x0F);
2043 }
2044 }
2045
2046 ctx.nliterals = 0;
2047 ctx.literals = NULL;
2048
2049 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS];
2050 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2051
2052 if (shader->vs_as_gs_a)
2053 vs_add_primid_output(&ctx, key.vs.prim_id_out);
2054
2055 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2056 tgsi_parse_token(&ctx.parse);
2057 switch (ctx.parse.FullToken.Token.Type) {
2058 case TGSI_TOKEN_TYPE_IMMEDIATE:
2059 immediate = &ctx.parse.FullToken.FullImmediate;
2060 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
2061 if(ctx.literals == NULL) {
2062 r = -ENOMEM;
2063 goto out_err;
2064 }
2065 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
2066 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
2067 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
2068 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
2069 ctx.nliterals++;
2070 break;
2071 case TGSI_TOKEN_TYPE_DECLARATION:
2072 r = tgsi_declaration(&ctx);
2073 if (r)
2074 goto out_err;
2075 break;
2076 case TGSI_TOKEN_TYPE_INSTRUCTION:
2077 case TGSI_TOKEN_TYPE_PROPERTY:
2078 break;
2079 default:
2080 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
2081 r = -EINVAL;
2082 goto out_err;
2083 }
2084 }
2085
2086 shader->ring_item_sizes[0] = ctx.next_ring_offset;
2087 shader->ring_item_sizes[1] = 0;
2088 shader->ring_item_sizes[2] = 0;
2089 shader->ring_item_sizes[3] = 0;
2090
2091 /* Process two side if needed */
2092 if (shader->two_side && ctx.colors_used) {
2093 int i, count = ctx.shader->ninput;
2094 unsigned next_lds_loc = ctx.shader->nlds;
2095
2096 /* additional inputs will be allocated right after the existing inputs,
2097 * we won't need them after the color selection, so we don't need to
2098 * reserve these gprs for the rest of the shader code and to adjust
2099 * output offsets etc. */
2100 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
2101 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2102
2103 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
2104 if (ctx.face_gpr == -1) {
2105 i = ctx.shader->ninput++;
2106 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
2107 ctx.shader->input[i].spi_sid = 0;
2108 ctx.shader->input[i].gpr = gpr++;
2109 ctx.face_gpr = ctx.shader->input[i].gpr;
2110 }
2111
2112 for (i = 0; i < count; i++) {
2113 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2114 int ni = ctx.shader->ninput++;
2115 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
2116 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
2117 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
2118 ctx.shader->input[ni].gpr = gpr++;
2119 // TGSI to LLVM needs to know the lds position of inputs.
2120 // Non LLVM path computes it later (in process_twoside_color)
2121 ctx.shader->input[ni].lds_pos = next_lds_loc++;
2122 ctx.shader->input[i].back_color_input = ni;
2123 if (ctx.bc->chip_class >= EVERGREEN) {
2124 if ((r = evergreen_interp_input(&ctx, ni)))
2125 return r;
2126 }
2127 }
2128 }
2129 }
2130
2131 /* LLVM backend setup */
2132 #ifdef R600_USE_LLVM
2133 if (use_llvm) {
2134 struct radeon_llvm_context radeon_llvm_ctx;
2135 LLVMModuleRef mod;
2136 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
2137 boolean use_kill = false;
2138
2139 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
2140 radeon_llvm_ctx.type = ctx.type;
2141 radeon_llvm_ctx.two_side = shader->two_side;
2142 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
2143 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
2144 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
2145 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
2146 radeon_llvm_ctx.color_buffer_count = max_color_exports;
2147 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
2148 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
2149 radeon_llvm_ctx.stream_outputs = &so;
2150 radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
2151 radeon_llvm_ctx.has_compressed_msaa_texturing =
2152 ctx.bc->has_compressed_msaa_texturing;
2153 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
2154 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
2155 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
2156
2157 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
2158 radeon_llvm_dispose(&radeon_llvm_ctx);
2159 use_llvm = 0;
2160 fprintf(stderr, "R600 LLVM backend failed to compile "
2161 "shader. Falling back to TGSI\n");
2162 } else {
2163 ctx.file_offset[TGSI_FILE_OUTPUT] =
2164 ctx.file_offset[TGSI_FILE_INPUT];
2165 }
2166 if (use_kill)
2167 ctx.shader->uses_kill = use_kill;
2168 radeon_llvm_dispose(&radeon_llvm_ctx);
2169 }
2170 #endif
2171 /* End of LLVM backend setup */
2172
2173 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
2174 shader->nr_ps_max_color_exports = 8;
2175
2176 if (!use_llvm) {
2177 if (ctx.fragcoord_input >= 0) {
2178 if (ctx.bc->chip_class == CAYMAN) {
2179 for (j = 0 ; j < 4; j++) {
2180 struct r600_bytecode_alu alu;
2181 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2182 alu.op = ALU_OP1_RECIP_IEEE;
2183 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2184 alu.src[0].chan = 3;
2185
2186 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2187 alu.dst.chan = j;
2188 alu.dst.write = (j == 3);
2189 alu.last = 1;
2190 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2191 return r;
2192 }
2193 } else {
2194 struct r600_bytecode_alu alu;
2195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2196 alu.op = ALU_OP1_RECIP_IEEE;
2197 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2198 alu.src[0].chan = 3;
2199
2200 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2201 alu.dst.chan = 3;
2202 alu.dst.write = 1;
2203 alu.last = 1;
2204 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2205 return r;
2206 }
2207 }
2208
2209 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2210 struct r600_bytecode_alu alu;
2211 int r;
2212 for (j = 0; j < 4; j++) {
2213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2214 alu.op = ALU_OP1_MOV;
2215 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2216 alu.src[0].value = 0;
2217 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
2218 alu.dst.write = 1;
2219 alu.last = 1;
2220 r = r600_bytecode_add_alu(ctx.bc, &alu);
2221 if (r)
2222 return r;
2223 }
2224 }
2225 if (shader->two_side && ctx.colors_used) {
2226 if ((r = process_twoside_color_inputs(&ctx)))
2227 return r;
2228 }
2229
2230 tgsi_parse_init(&ctx.parse, tokens);
2231 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2232 tgsi_parse_token(&ctx.parse);
2233 switch (ctx.parse.FullToken.Token.Type) {
2234 case TGSI_TOKEN_TYPE_INSTRUCTION:
2235 r = tgsi_is_supported(&ctx);
2236 if (r)
2237 goto out_err;
2238 ctx.max_driver_temp_used = 0;
2239 /* reserve first tmp for everyone */
2240 r600_get_temp(&ctx);
2241
2242 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
2243 if ((r = tgsi_split_constant(&ctx)))
2244 goto out_err;
2245 if ((r = tgsi_split_literal_constant(&ctx)))
2246 goto out_err;
2247 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
2248 if ((r = tgsi_split_gs_inputs(&ctx)))
2249 goto out_err;
2250 if (ctx.bc->chip_class == CAYMAN)
2251 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
2252 else if (ctx.bc->chip_class >= EVERGREEN)
2253 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
2254 else
2255 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
2256 r = ctx.inst_info->process(&ctx);
2257 if (r)
2258 goto out_err;
2259 break;
2260 default:
2261 break;
2262 }
2263 }
2264 }
2265
2266 /* Reset the temporary register counter. */
2267 ctx.max_driver_temp_used = 0;
2268
2269 noutput = shader->noutput;
2270
2271 if (!ring_outputs && ctx.clip_vertex_write) {
2272 unsigned clipdist_temp[2];
2273
2274 clipdist_temp[0] = r600_get_temp(&ctx);
2275 clipdist_temp[1] = r600_get_temp(&ctx);
2276
2277 /* need to convert a clipvertex write into clipdistance writes and not export
2278 the clip vertex anymore */
2279
2280 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
2281 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2282 shader->output[noutput].gpr = clipdist_temp[0];
2283 noutput++;
2284 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2285 shader->output[noutput].gpr = clipdist_temp[1];
2286 noutput++;
2287
2288 /* reset spi_sid for clipvertex output to avoid confusing spi */
2289 shader->output[ctx.cv_output].spi_sid = 0;
2290
2291 shader->clip_dist_write = 0xFF;
2292
2293 for (i = 0; i < 8; i++) {
2294 int oreg = i >> 2;
2295 int ochan = i & 3;
2296
2297 for (j = 0; j < 4; j++) {
2298 struct r600_bytecode_alu alu;
2299 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2300 alu.op = ALU_OP2_DOT4;
2301 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
2302 alu.src[0].chan = j;
2303
2304 alu.src[1].sel = 512 + i;
2305 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
2306 alu.src[1].chan = j;
2307
2308 alu.dst.sel = clipdist_temp[oreg];
2309 alu.dst.chan = j;
2310 alu.dst.write = (j == ochan);
2311 if (j == 3)
2312 alu.last = 1;
2313 if (!use_llvm)
2314 r = r600_bytecode_add_alu(ctx.bc, &alu);
2315 if (r)
2316 return r;
2317 }
2318 }
2319 }
2320
2321 /* Add stream outputs. */
2322 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
2323 so.num_outputs && !use_llvm)
2324 emit_streamout(&ctx, &so, -1, NULL);
2325
2326 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2327 convert_edgeflag_to_int(&ctx);
2328
2329 if (ring_outputs) {
2330 if (key.vs.as_es) {
2331 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
2332 ctx.gs_export_gpr_tregs[1] = -1;
2333 ctx.gs_export_gpr_tregs[2] = -1;
2334 ctx.gs_export_gpr_tregs[3] = -1;
2335
2336 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
2337 }
2338 } else {
2339 /* Export output */
2340 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
2341
2342 for (i = 0, j = 0; i < noutput; i++, j++) {
2343 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2344 output[j].gpr = shader->output[i].gpr;
2345 output[j].elem_size = 3;
2346 output[j].swizzle_x = 0;
2347 output[j].swizzle_y = 1;
2348 output[j].swizzle_z = 2;
2349 output[j].swizzle_w = 3;
2350 output[j].burst_count = 1;
2351 output[j].type = -1;
2352 output[j].op = CF_OP_EXPORT;
2353 switch (ctx.type) {
2354 case TGSI_PROCESSOR_VERTEX:
2355 switch (shader->output[i].name) {
2356 case TGSI_SEMANTIC_POSITION:
2357 output[j].array_base = 60;
2358 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2359 pos_emitted = true;
2360 break;
2361
2362 case TGSI_SEMANTIC_PSIZE:
2363 output[j].array_base = 61;
2364 output[j].swizzle_y = 7;
2365 output[j].swizzle_z = 7;
2366 output[j].swizzle_w = 7;
2367 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2368 pos_emitted = true;
2369 break;
2370 case TGSI_SEMANTIC_EDGEFLAG:
2371 output[j].array_base = 61;
2372 output[j].swizzle_x = 7;
2373 output[j].swizzle_y = 0;
2374 output[j].swizzle_z = 7;
2375 output[j].swizzle_w = 7;
2376 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2377 pos_emitted = true;
2378 break;
2379 case TGSI_SEMANTIC_LAYER:
2380 /* spi_sid is 0 for outputs that are
2381 * not consumed by PS */
2382 if (shader->output[i].spi_sid) {
2383 output[j].array_base = next_param_base++;
2384 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2385 j++;
2386 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2387 }
2388 output[j].array_base = 61;
2389 output[j].swizzle_x = 7;
2390 output[j].swizzle_y = 7;
2391 output[j].swizzle_z = 0;
2392 output[j].swizzle_w = 7;
2393 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2394 pos_emitted = true;
2395 break;
2396 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2397 /* spi_sid is 0 for outputs that are
2398 * not consumed by PS */
2399 if (shader->output[i].spi_sid) {
2400 output[j].array_base = next_param_base++;
2401 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2402 j++;
2403 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2404 }
2405 output[j].array_base = 61;
2406 output[j].swizzle_x = 7;
2407 output[j].swizzle_y = 7;
2408 output[j].swizzle_z = 7;
2409 output[j].swizzle_w = 0;
2410 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2411 pos_emitted = true;
2412 break;
2413 case TGSI_SEMANTIC_CLIPVERTEX:
2414 j--;
2415 break;
2416 case TGSI_SEMANTIC_CLIPDIST:
2417 output[j].array_base = next_clip_base++;
2418 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2419 pos_emitted = true;
2420 /* spi_sid is 0 for clipdistance outputs that were generated
2421 * for clipvertex - we don't need to pass them to PS */
2422 if (shader->output[i].spi_sid) {
2423 j++;
2424 /* duplicate it as PARAM to pass to the pixel shader */
2425 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2426 output[j].array_base = next_param_base++;
2427 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2428 }
2429 break;
2430 case TGSI_SEMANTIC_FOG:
2431 output[j].swizzle_y = 4; /* 0 */
2432 output[j].swizzle_z = 4; /* 0 */
2433 output[j].swizzle_w = 5; /* 1 */
2434 break;
2435 case TGSI_SEMANTIC_PRIMID:
2436 output[j].swizzle_x = 2;
2437 output[j].swizzle_y = 4; /* 0 */
2438 output[j].swizzle_z = 4; /* 0 */
2439 output[j].swizzle_w = 4; /* 0 */
2440 break;
2441 }
2442
2443 break;
2444 case TGSI_PROCESSOR_FRAGMENT:
2445 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
2446 /* never export more colors than the number of CBs */
2447 if (shader->output[i].sid >= max_color_exports) {
2448 /* skip export */
2449 j--;
2450 continue;
2451 }
2452 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2453 output[j].array_base = shader->output[i].sid;
2454 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2455 shader->nr_ps_color_exports++;
2456 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
2457 for (k = 1; k < max_color_exports; k++) {
2458 j++;
2459 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2460 output[j].gpr = shader->output[i].gpr;
2461 output[j].elem_size = 3;
2462 output[j].swizzle_x = 0;
2463 output[j].swizzle_y = 1;
2464 output[j].swizzle_z = 2;
2465 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2466 output[j].burst_count = 1;
2467 output[j].array_base = k;
2468 output[j].op = CF_OP_EXPORT;
2469 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2470 shader->nr_ps_color_exports++;
2471 }
2472 }
2473 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
2474 output[j].array_base = 61;
2475 output[j].swizzle_x = 2;
2476 output[j].swizzle_y = 7;
2477 output[j].swizzle_z = output[j].swizzle_w = 7;
2478 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2479 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2480 output[j].array_base = 61;
2481 output[j].swizzle_x = 7;
2482 output[j].swizzle_y = 1;
2483 output[j].swizzle_z = output[j].swizzle_w = 7;
2484 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2485 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2486 output[j].array_base = 61;
2487 output[j].swizzle_x = 7;
2488 output[j].swizzle_y = 7;
2489 output[j].swizzle_z = 0;
2490 output[j].swizzle_w = 7;
2491 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2492 } else {
2493 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
2494 r = -EINVAL;
2495 goto out_err;
2496 }
2497 break;
2498 default:
2499 R600_ERR("unsupported processor type %d\n", ctx.type);
2500 r = -EINVAL;
2501 goto out_err;
2502 }
2503
2504 if (output[j].type==-1) {
2505 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2506 output[j].array_base = next_param_base++;
2507 }
2508 }
2509
2510 /* add fake position export */
2511 if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
2512 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2513 output[j].gpr = 0;
2514 output[j].elem_size = 3;
2515 output[j].swizzle_x = 7;
2516 output[j].swizzle_y = 7;
2517 output[j].swizzle_z = 7;
2518 output[j].swizzle_w = 7;
2519 output[j].burst_count = 1;
2520 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2521 output[j].array_base = 60;
2522 output[j].op = CF_OP_EXPORT;
2523 j++;
2524 }
2525
2526 /* add fake param output for vertex shader if no param is exported */
2527 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
2528 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2529 output[j].gpr = 0;
2530 output[j].elem_size = 3;
2531 output[j].swizzle_x = 7;
2532 output[j].swizzle_y = 7;
2533 output[j].swizzle_z = 7;
2534 output[j].swizzle_w = 7;
2535 output[j].burst_count = 1;
2536 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2537 output[j].array_base = 0;
2538 output[j].op = CF_OP_EXPORT;
2539 j++;
2540 }
2541
2542 /* add fake pixel export */
2543 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
2544 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2545 output[j].gpr = 0;
2546 output[j].elem_size = 3;
2547 output[j].swizzle_x = 7;
2548 output[j].swizzle_y = 7;
2549 output[j].swizzle_z = 7;
2550 output[j].swizzle_w = 7;
2551 output[j].burst_count = 1;
2552 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2553 output[j].array_base = 0;
2554 output[j].op = CF_OP_EXPORT;
2555 j++;
2556 shader->nr_ps_color_exports++;
2557 }
2558
2559 noutput = j;
2560
2561 /* set export done on last export of each type */
2562 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
2563 if (!(output_done & (1 << output[i].type))) {
2564 output_done |= (1 << output[i].type);
2565 output[i].op = CF_OP_EXPORT_DONE;
2566 }
2567 }
2568 /* add output to bytecode */
2569 if (!use_llvm) {
2570 for (i = 0; i < noutput; i++) {
2571 r = r600_bytecode_add_output(ctx.bc, &output[i]);
2572 if (r)
2573 goto out_err;
2574 }
2575 }
2576 }
2577
2578 /* add program end */
2579 if (!use_llvm) {
2580 if (ctx.bc->chip_class == CAYMAN)
2581 cm_bytecode_add_cf_end(ctx.bc);
2582 else {
2583 const struct cf_op_info *last = NULL;
2584
2585 if (ctx.bc->cf_last)
2586 last = r600_isa_cf(ctx.bc->cf_last->op);
2587
2588 /* alu clause instructions don't have EOP bit, so add NOP */
2589 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
2590 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2591
2592 ctx.bc->cf_last->end_of_program = 1;
2593 }
2594 }
2595
2596 /* check GPR limit - we have 124 = 128 - 4
2597 * (4 are reserved as alu clause temporary registers) */
2598 if (ctx.bc->ngpr > 124) {
2599 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
2600 r = -ENOMEM;
2601 goto out_err;
2602 }
2603
2604 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2605 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
2606 return r;
2607 }
2608
2609 free(ctx.literals);
2610 tgsi_parse_free(&ctx.parse);
2611 return 0;
2612 out_err:
2613 free(ctx.literals);
2614 tgsi_parse_free(&ctx.parse);
2615 return r;
2616 }
2617
2618 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
2619 {
2620 const unsigned tgsi_opcode =
2621 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
2622 R600_ERR("%s tgsi opcode unsupported\n",
2623 tgsi_get_opcode_name(tgsi_opcode));
2624 return -EINVAL;
2625 }
2626
2627 static int tgsi_end(struct r600_shader_ctx *ctx)
2628 {
2629 return 0;
2630 }
2631
2632 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
2633 const struct r600_shader_src *shader_src,
2634 unsigned chan)
2635 {
2636 bc_src->sel = shader_src->sel;
2637 bc_src->chan = shader_src->swizzle[chan];
2638 bc_src->neg = shader_src->neg;
2639 bc_src->abs = shader_src->abs;
2640 bc_src->rel = shader_src->rel;
2641 bc_src->value = shader_src->value[bc_src->chan];
2642 bc_src->kc_bank = shader_src->kc_bank;
2643 bc_src->kc_rel = shader_src->kc_rel;
2644 }
2645
2646 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
2647 {
2648 bc_src->abs = 1;
2649 bc_src->neg = 0;
2650 }
2651
2652 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2653 {
2654 bc_src->neg = !bc_src->neg;
2655 }
2656
2657 static void tgsi_dst(struct r600_shader_ctx *ctx,
2658 const struct tgsi_full_dst_register *tgsi_dst,
2659 unsigned swizzle,
2660 struct r600_bytecode_alu_dst *r600_dst)
2661 {
2662 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2663
2664 r600_dst->sel = tgsi_dst->Register.Index;
2665 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2666 r600_dst->chan = swizzle;
2667 r600_dst->write = 1;
2668 if (tgsi_dst->Register.Indirect)
2669 r600_dst->rel = V_SQ_REL_RELATIVE;
2670 if (inst->Instruction.Saturate) {
2671 r600_dst->clamp = 1;
2672 }
2673 }
2674
2675 static int tgsi_last_instruction(unsigned writemask)
2676 {
2677 int i, lasti = 0;
2678
2679 for (i = 0; i < 4; i++) {
2680 if (writemask & (1 << i)) {
2681 lasti = i;
2682 }
2683 }
2684 return lasti;
2685 }
2686
2687
2688
2689 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
2690 {
2691 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2692 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2693 struct r600_bytecode_alu alu;
2694 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2695 int use_tmp = 0;
2696
2697 if (singledest) {
2698 switch (write_mask) {
2699 case 0x1:
2700 write_mask = 0x3;
2701 break;
2702 case 0x2:
2703 use_tmp = 1;
2704 write_mask = 0x3;
2705 break;
2706 case 0x4:
2707 write_mask = 0xc;
2708 break;
2709 case 0x8:
2710 write_mask = 0xc;
2711 use_tmp = 3;
2712 break;
2713 }
2714 }
2715
2716 lasti = tgsi_last_instruction(write_mask);
2717 for (i = 0; i <= lasti; i++) {
2718
2719 if (!(write_mask & (1 << i)))
2720 continue;
2721
2722 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2723
2724 if (singledest) {
2725 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2726 if (use_tmp) {
2727 alu.dst.sel = ctx->temp_reg;
2728 alu.dst.chan = i;
2729 alu.dst.write = 1;
2730 }
2731 if (i == 1 || i == 3)
2732 alu.dst.write = 0;
2733 } else
2734 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2735
2736 alu.op = ctx->inst_info->op;
2737 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
2738 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2739 } else if (!swap) {
2740 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2741 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
2742 }
2743 } else {
2744 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
2745 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
2746 }
2747
2748 /* handle some special cases */
2749 if (i == 1 || i == 3) {
2750 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
2751 case TGSI_OPCODE_SUB:
2752 r600_bytecode_src_toggle_neg(&alu.src[1]);
2753 break;
2754 case TGSI_OPCODE_DABS:
2755 r600_bytecode_src_set_abs(&alu.src[0]);
2756 break;
2757 default:
2758 break;
2759 }
2760 }
2761 if (i == lasti) {
2762 alu.last = 1;
2763 }
2764 r = r600_bytecode_add_alu(ctx->bc, &alu);
2765 if (r)
2766 return r;
2767 }
2768
2769 if (use_tmp) {
2770 write_mask = inst->Dst[0].Register.WriteMask;
2771
2772 /* move result from temp to dst */
2773 for (i = 0; i <= lasti; i++) {
2774 if (!(write_mask & (1 << i)))
2775 continue;
2776
2777 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2778 alu.op = ALU_OP1_MOV;
2779 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2780 alu.src[0].sel = ctx->temp_reg;
2781 alu.src[0].chan = use_tmp - 1;
2782 alu.last = (i == lasti);
2783
2784 r = r600_bytecode_add_alu(ctx->bc, &alu);
2785 if (r)
2786 return r;
2787 }
2788 }
2789 return 0;
2790 }
2791
2792 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
2793 {
2794 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2795 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2796 /* confirm writemasking */
2797 if ((write_mask & 0x3) != 0x3 &&
2798 (write_mask & 0xc) != 0xc) {
2799 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
2800 return -1;
2801 }
2802 return tgsi_op2_64_params(ctx, false, false);
2803 }
2804
2805 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
2806 {
2807 return tgsi_op2_64_params(ctx, true, false);
2808 }
2809
2810 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
2811 {
2812 return tgsi_op2_64_params(ctx, true, true);
2813 }
2814
2815 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
2816 {
2817 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2818 struct r600_bytecode_alu alu;
2819 int i, j, r;
2820 int lasti = 3;
2821 int tmp = r600_get_temp(ctx);
2822
2823 for (i = 0; i < lasti + 1; i++) {
2824
2825 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2826 alu.op = ctx->inst_info->op;
2827 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2828 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
2829 }
2830
2831 if (inst->Dst[0].Register.WriteMask & (1 << i))
2832 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2833 else
2834 alu.dst.sel = tmp;
2835
2836 alu.dst.chan = i;
2837 alu.is_op3 = 1;
2838 if (i == lasti) {
2839 alu.last = 1;
2840 }
2841 r = r600_bytecode_add_alu(ctx->bc, &alu);
2842 if (r)
2843 return r;
2844 }
2845 return 0;
2846 }
2847
2848 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
2849 {
2850 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2851 struct r600_bytecode_alu alu;
2852 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2853 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2854 /* use temp register if trans_only and more than one dst component */
2855 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
2856
2857 for (i = 0; i <= lasti; i++) {
2858 if (!(write_mask & (1 << i)))
2859 continue;
2860
2861 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2862 if (use_tmp) {
2863 alu.dst.sel = ctx->temp_reg;
2864 alu.dst.chan = i;
2865 alu.dst.write = 1;
2866 } else
2867 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2868
2869 alu.op = ctx->inst_info->op;
2870 if (!swap) {
2871 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2872 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2873 }
2874 } else {
2875 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2876 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2877 }
2878 /* handle some special cases */
2879 switch (inst->Instruction.Opcode) {
2880 case TGSI_OPCODE_SUB:
2881 r600_bytecode_src_toggle_neg(&alu.src[1]);
2882 break;
2883 case TGSI_OPCODE_ABS:
2884 r600_bytecode_src_set_abs(&alu.src[0]);
2885 break;
2886 default:
2887 break;
2888 }
2889 if (i == lasti || trans_only) {
2890 alu.last = 1;
2891 }
2892 r = r600_bytecode_add_alu(ctx->bc, &alu);
2893 if (r)
2894 return r;
2895 }
2896
2897 if (use_tmp) {
2898 /* move result from temp to dst */
2899 for (i = 0; i <= lasti; i++) {
2900 if (!(write_mask & (1 << i)))
2901 continue;
2902
2903 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2904 alu.op = ALU_OP1_MOV;
2905 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2906 alu.src[0].sel = ctx->temp_reg;
2907 alu.src[0].chan = i;
2908 alu.last = (i == lasti);
2909
2910 r = r600_bytecode_add_alu(ctx->bc, &alu);
2911 if (r)
2912 return r;
2913 }
2914 }
2915 return 0;
2916 }
2917
2918 static int tgsi_op2(struct r600_shader_ctx *ctx)
2919 {
2920 return tgsi_op2_s(ctx, 0, 0);
2921 }
2922
2923 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2924 {
2925 return tgsi_op2_s(ctx, 1, 0);
2926 }
2927
2928 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2929 {
2930 return tgsi_op2_s(ctx, 0, 1);
2931 }
2932
2933 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2934 {
2935 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2936 struct r600_bytecode_alu alu;
2937 int i, r;
2938 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2939
2940 for (i = 0; i < lasti + 1; i++) {
2941
2942 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2943 continue;
2944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2945 alu.op = ctx->inst_info->op;
2946
2947 alu.src[0].sel = V_SQ_ALU_SRC_0;
2948
2949 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2950
2951 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2952
2953 if (i == lasti) {
2954 alu.last = 1;
2955 }
2956 r = r600_bytecode_add_alu(ctx->bc, &alu);
2957 if (r)
2958 return r;
2959 }
2960 return 0;
2961
2962 }
2963
2964 static int tgsi_dneg(struct r600_shader_ctx *ctx)
2965 {
2966 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2967 struct r600_bytecode_alu alu;
2968 int i, r;
2969 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2970
2971 for (i = 0; i < lasti + 1; i++) {
2972
2973 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2974 continue;
2975 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2976 alu.op = ALU_OP1_MOV;
2977
2978 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2979
2980 if (i == 1 || i == 3)
2981 r600_bytecode_src_toggle_neg(&alu.src[0]);
2982 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2983
2984 if (i == lasti) {
2985 alu.last = 1;
2986 }
2987 r = r600_bytecode_add_alu(ctx->bc, &alu);
2988 if (r)
2989 return r;
2990 }
2991 return 0;
2992
2993 }
2994
2995 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
2996 {
2997 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2998 struct r600_bytecode_alu alu;
2999 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3000 int i, j, r;
3001 int firsti = write_mask == 0xc ? 2 : 0;
3002
3003 for (i = 0; i <= 3; i++) {
3004 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3005 alu.op = ctx->inst_info->op;
3006
3007 alu.dst.sel = ctx->temp_reg;
3008 alu.dst.chan = i;
3009 alu.dst.write = 1;
3010 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3011 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3012 }
3013
3014 if (i == 3)
3015 alu.last = 1;
3016
3017 r = r600_bytecode_add_alu(ctx->bc, &alu);
3018 if (r)
3019 return r;
3020 }
3021
3022 /* MOV first two channels to writemask dst0 */
3023 for (i = 0; i <= 1; i++) {
3024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3025 alu.op = ALU_OP1_MOV;
3026 alu.src[0].chan = i + 2;
3027 alu.src[0].sel = ctx->temp_reg;
3028
3029 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
3030 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
3031 alu.last = 1;
3032 r = r600_bytecode_add_alu(ctx->bc, &alu);
3033 if (r)
3034 return r;
3035 }
3036
3037 for (i = 0; i <= 3; i++) {
3038 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
3039 /* MOV third channels to writemask dst1 */
3040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3041 alu.op = ALU_OP1_MOV;
3042 alu.src[0].chan = 1;
3043 alu.src[0].sel = ctx->temp_reg;
3044
3045 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
3046 alu.last = 1;
3047 r = r600_bytecode_add_alu(ctx->bc, &alu);
3048 if (r)
3049 return r;
3050 break;
3051 }
3052 }
3053 return 0;
3054 }
3055
3056 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
3057 {
3058 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3059 int i, r;
3060 struct r600_bytecode_alu alu;
3061 int last_slot = 3;
3062 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3063 int t1 = ctx->temp_reg;
3064
3065 /* these have to write the result to X/Y by the looks of it */
3066 for (i = 0 ; i < last_slot; i++) {
3067 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3068 alu.op = ctx->inst_info->op;
3069
3070 /* should only be one src regs */
3071 assert (inst->Instruction.NumSrcRegs == 1);
3072
3073 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3074 r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
3075
3076 /* RSQ should take the absolute value of src */
3077 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
3078 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT) {
3079 r600_bytecode_src_set_abs(&alu.src[1]);
3080 }
3081 alu.dst.sel = t1;
3082 alu.dst.chan = i;
3083 alu.dst.write = (i == 0 || i == 1);
3084
3085 if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
3086 alu.last = 1;
3087 r = r600_bytecode_add_alu(ctx->bc, &alu);
3088 if (r)
3089 return r;
3090 }
3091
3092 for (i = 0 ; i <= lasti; i++) {
3093 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3094 continue;
3095 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3096 alu.op = ALU_OP1_MOV;
3097 alu.src[0].sel = t1;
3098 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
3099 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3100 alu.dst.write = 1;
3101 if (i == lasti)
3102 alu.last = 1;
3103 r = r600_bytecode_add_alu(ctx->bc, &alu);
3104 if (r)
3105 return r;
3106 }
3107 return 0;
3108 }
3109
3110 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
3111 {
3112 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3113 int i, j, r;
3114 struct r600_bytecode_alu alu;
3115 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3116
3117 for (i = 0 ; i < last_slot; i++) {
3118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3119 alu.op = ctx->inst_info->op;
3120 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3121 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
3122
3123 /* RSQ should take the absolute value of src */
3124 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
3125 r600_bytecode_src_set_abs(&alu.src[j]);
3126 }
3127 }
3128 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3129 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3130
3131 if (i == last_slot - 1)
3132 alu.last = 1;
3133 r = r600_bytecode_add_alu(ctx->bc, &alu);
3134 if (r)
3135 return r;
3136 }
3137 return 0;
3138 }
3139
3140 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
3141 {
3142 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3143 int i, j, k, r;
3144 struct r600_bytecode_alu alu;
3145 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3146 int t1 = ctx->temp_reg;
3147
3148 for (k = 0; k <= lasti; k++) {
3149 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
3150 continue;
3151
3152 for (i = 0 ; i < 4; i++) {
3153 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3154 alu.op = ctx->inst_info->op;
3155 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3156 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
3157 }
3158 alu.dst.sel = t1;
3159 alu.dst.chan = i;
3160 alu.dst.write = (i == k);
3161 if (i == 3)
3162 alu.last = 1;
3163 r = r600_bytecode_add_alu(ctx->bc, &alu);
3164 if (r)
3165 return r;
3166 }
3167 }
3168
3169 for (i = 0 ; i <= lasti; i++) {
3170 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3171 continue;
3172 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3173 alu.op = ALU_OP1_MOV;
3174 alu.src[0].sel = t1;
3175 alu.src[0].chan = i;
3176 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3177 alu.dst.write = 1;
3178 if (i == lasti)
3179 alu.last = 1;
3180 r = r600_bytecode_add_alu(ctx->bc, &alu);
3181 if (r)
3182 return r;
3183 }
3184
3185 return 0;
3186 }
3187
3188
3189 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
3190 {
3191 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3192 int i, j, k, r;
3193 struct r600_bytecode_alu alu;
3194 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3195 int t1 = ctx->temp_reg;
3196
3197 for (k = 0; k < 2; k++) {
3198 if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2))))
3199 continue;
3200
3201 for (i = 0; i < 4; i++) {
3202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3203 alu.op = ctx->inst_info->op;
3204 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3205 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));;
3206 }
3207 alu.dst.sel = t1;
3208 alu.dst.chan = i;
3209 alu.dst.write = 1;
3210 if (i == 3)
3211 alu.last = 1;
3212 r = r600_bytecode_add_alu(ctx->bc, &alu);
3213 if (r)
3214 return r;
3215 }
3216 }
3217
3218 for (i = 0; i <= lasti; i++) {
3219 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3220 continue;
3221 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3222 alu.op = ALU_OP1_MOV;
3223 alu.src[0].sel = t1;
3224 alu.src[0].chan = i;
3225 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3226 alu.dst.write = 1;
3227 if (i == lasti)
3228 alu.last = 1;
3229 r = r600_bytecode_add_alu(ctx->bc, &alu);
3230 if (r)
3231 return r;
3232 }
3233
3234 return 0;
3235 }
3236
3237 /*
3238 * r600 - trunc to -PI..PI range
3239 * r700 - normalize by dividing by 2PI
3240 * see fdo bug 27901
3241 */
3242 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
3243 {
3244 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
3245 static float double_pi = 3.1415926535 * 2;
3246 static float neg_pi = -3.1415926535;
3247
3248 int r;
3249 struct r600_bytecode_alu alu;
3250
3251 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3252 alu.op = ALU_OP3_MULADD;
3253 alu.is_op3 = 1;
3254
3255 alu.dst.chan = 0;
3256 alu.dst.sel = ctx->temp_reg;
3257 alu.dst.write = 1;
3258
3259 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3260
3261 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3262 alu.src[1].chan = 0;
3263 alu.src[1].value = *(uint32_t *)&half_inv_pi;
3264 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3265 alu.src[2].chan = 0;
3266 alu.last = 1;
3267 r = r600_bytecode_add_alu(ctx->bc, &alu);
3268 if (r)
3269 return r;
3270
3271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3272 alu.op = ALU_OP1_FRACT;
3273
3274 alu.dst.chan = 0;
3275 alu.dst.sel = ctx->temp_reg;
3276 alu.dst.write = 1;
3277
3278 alu.src[0].sel = ctx->temp_reg;
3279 alu.src[0].chan = 0;
3280 alu.last = 1;
3281 r = r600_bytecode_add_alu(ctx->bc, &alu);
3282 if (r)
3283 return r;
3284
3285 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3286 alu.op = ALU_OP3_MULADD;
3287 alu.is_op3 = 1;
3288
3289 alu.dst.chan = 0;
3290 alu.dst.sel = ctx->temp_reg;
3291 alu.dst.write = 1;
3292
3293 alu.src[0].sel = ctx->temp_reg;
3294 alu.src[0].chan = 0;
3295
3296 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3297 alu.src[1].chan = 0;
3298 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3299 alu.src[2].chan = 0;
3300
3301 if (ctx->bc->chip_class == R600) {
3302 alu.src[1].value = *(uint32_t *)&double_pi;
3303 alu.src[2].value = *(uint32_t *)&neg_pi;
3304 } else {
3305 alu.src[1].sel = V_SQ_ALU_SRC_1;
3306 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3307 alu.src[2].neg = 1;
3308 }
3309
3310 alu.last = 1;
3311 r = r600_bytecode_add_alu(ctx->bc, &alu);
3312 if (r)
3313 return r;
3314 return 0;
3315 }
3316
3317 static int cayman_trig(struct r600_shader_ctx *ctx)
3318 {
3319 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3320 struct r600_bytecode_alu alu;
3321 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3322 int i, r;
3323
3324 r = tgsi_setup_trig(ctx);
3325 if (r)
3326 return r;
3327
3328
3329 for (i = 0; i < last_slot; i++) {
3330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3331 alu.op = ctx->inst_info->op;
3332 alu.dst.chan = i;
3333
3334 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3335 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3336
3337 alu.src[0].sel = ctx->temp_reg;
3338 alu.src[0].chan = 0;
3339 if (i == last_slot - 1)
3340 alu.last = 1;
3341 r = r600_bytecode_add_alu(ctx->bc, &alu);
3342 if (r)
3343 return r;
3344 }
3345 return 0;
3346 }
3347
3348 static int tgsi_trig(struct r600_shader_ctx *ctx)
3349 {
3350 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3351 struct r600_bytecode_alu alu;
3352 int i, r;
3353 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3354
3355 r = tgsi_setup_trig(ctx);
3356 if (r)
3357 return r;
3358
3359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3360 alu.op = ctx->inst_info->op;
3361 alu.dst.chan = 0;
3362 alu.dst.sel = ctx->temp_reg;
3363 alu.dst.write = 1;
3364
3365 alu.src[0].sel = ctx->temp_reg;
3366 alu.src[0].chan = 0;
3367 alu.last = 1;
3368 r = r600_bytecode_add_alu(ctx->bc, &alu);
3369 if (r)
3370 return r;
3371
3372 /* replicate result */
3373 for (i = 0; i < lasti + 1; i++) {
3374 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3375 continue;
3376
3377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3378 alu.op = ALU_OP1_MOV;
3379
3380 alu.src[0].sel = ctx->temp_reg;
3381 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3382 if (i == lasti)
3383 alu.last = 1;
3384 r = r600_bytecode_add_alu(ctx->bc, &alu);
3385 if (r)
3386 return r;
3387 }
3388 return 0;
3389 }
3390
3391 static int tgsi_scs(struct r600_shader_ctx *ctx)
3392 {
3393 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3394 struct r600_bytecode_alu alu;
3395 int i, r;
3396
3397 /* We'll only need the trig stuff if we are going to write to the
3398 * X or Y components of the destination vector.
3399 */
3400 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
3401 r = tgsi_setup_trig(ctx);
3402 if (r)
3403 return r;
3404 }
3405
3406 /* dst.x = COS */
3407 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3408 if (ctx->bc->chip_class == CAYMAN) {
3409 for (i = 0 ; i < 3; i++) {
3410 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3411 alu.op = ALU_OP1_COS;
3412 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3413
3414 if (i == 0)
3415 alu.dst.write = 1;
3416 else
3417 alu.dst.write = 0;
3418 alu.src[0].sel = ctx->temp_reg;
3419 alu.src[0].chan = 0;
3420 if (i == 2)
3421 alu.last = 1;
3422 r = r600_bytecode_add_alu(ctx->bc, &alu);
3423 if (r)
3424 return r;
3425 }
3426 } else {
3427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3428 alu.op = ALU_OP1_COS;
3429 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3430
3431 alu.src[0].sel = ctx->temp_reg;
3432 alu.src[0].chan = 0;
3433 alu.last = 1;
3434 r = r600_bytecode_add_alu(ctx->bc, &alu);
3435 if (r)
3436 return r;
3437 }
3438 }
3439
3440 /* dst.y = SIN */
3441 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3442 if (ctx->bc->chip_class == CAYMAN) {
3443 for (i = 0 ; i < 3; i++) {
3444 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3445 alu.op = ALU_OP1_SIN;
3446 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3447 if (i == 1)
3448 alu.dst.write = 1;
3449 else
3450 alu.dst.write = 0;
3451 alu.src[0].sel = ctx->temp_reg;
3452 alu.src[0].chan = 0;
3453 if (i == 2)
3454 alu.last = 1;
3455 r = r600_bytecode_add_alu(ctx->bc, &alu);
3456 if (r)
3457 return r;
3458 }
3459 } else {
3460 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3461 alu.op = ALU_OP1_SIN;
3462 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3463
3464 alu.src[0].sel = ctx->temp_reg;
3465 alu.src[0].chan = 0;
3466 alu.last = 1;
3467 r = r600_bytecode_add_alu(ctx->bc, &alu);
3468 if (r)
3469 return r;
3470 }
3471 }
3472
3473 /* dst.z = 0.0; */
3474 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3475 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3476
3477 alu.op = ALU_OP1_MOV;
3478
3479 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3480
3481 alu.src[0].sel = V_SQ_ALU_SRC_0;
3482 alu.src[0].chan = 0;
3483
3484 alu.last = 1;
3485
3486 r = r600_bytecode_add_alu(ctx->bc, &alu);
3487 if (r)
3488 return r;
3489 }
3490
3491 /* dst.w = 1.0; */
3492 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3494
3495 alu.op = ALU_OP1_MOV;
3496
3497 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3498
3499 alu.src[0].sel = V_SQ_ALU_SRC_1;
3500 alu.src[0].chan = 0;
3501
3502 alu.last = 1;
3503
3504 r = r600_bytecode_add_alu(ctx->bc, &alu);
3505 if (r)
3506 return r;
3507 }
3508
3509 return 0;
3510 }
3511
3512 static int tgsi_kill(struct r600_shader_ctx *ctx)
3513 {
3514 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3515 struct r600_bytecode_alu alu;
3516 int i, r;
3517
3518 for (i = 0; i < 4; i++) {
3519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3520 alu.op = ctx->inst_info->op;
3521
3522 alu.dst.chan = i;
3523
3524 alu.src[0].sel = V_SQ_ALU_SRC_0;
3525
3526 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
3527 alu.src[1].sel = V_SQ_ALU_SRC_1;
3528 alu.src[1].neg = 1;
3529 } else {
3530 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3531 }
3532 if (i == 3) {
3533 alu.last = 1;
3534 }
3535 r = r600_bytecode_add_alu(ctx->bc, &alu);
3536 if (r)
3537 return r;
3538 }
3539
3540 /* kill must be last in ALU */
3541 ctx->bc->force_add_cf = 1;
3542 ctx->shader->uses_kill = TRUE;
3543 return 0;
3544 }
3545
3546 static int tgsi_lit(struct r600_shader_ctx *ctx)
3547 {
3548 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3549 struct r600_bytecode_alu alu;
3550 int r;
3551
3552 /* tmp.x = max(src.y, 0.0) */
3553 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3554 alu.op = ALU_OP2_MAX;
3555 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3556 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3557 alu.src[1].chan = 1;
3558
3559 alu.dst.sel = ctx->temp_reg;
3560 alu.dst.chan = 0;
3561 alu.dst.write = 1;
3562
3563 alu.last = 1;
3564 r = r600_bytecode_add_alu(ctx->bc, &alu);
3565 if (r)
3566 return r;
3567
3568 if (inst->Dst[0].Register.WriteMask & (1 << 2))
3569 {
3570 int chan;
3571 int sel;
3572 int i;
3573
3574 if (ctx->bc->chip_class == CAYMAN) {
3575 for (i = 0; i < 3; i++) {
3576 /* tmp.z = log(tmp.x) */
3577 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3578 alu.op = ALU_OP1_LOG_CLAMPED;
3579 alu.src[0].sel = ctx->temp_reg;
3580 alu.src[0].chan = 0;
3581 alu.dst.sel = ctx->temp_reg;
3582 alu.dst.chan = i;
3583 if (i == 2) {
3584 alu.dst.write = 1;
3585 alu.last = 1;
3586 } else
3587 alu.dst.write = 0;
3588
3589 r = r600_bytecode_add_alu(ctx->bc, &alu);
3590 if (r)
3591 return r;
3592 }
3593 } else {
3594 /* tmp.z = log(tmp.x) */
3595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3596 alu.op = ALU_OP1_LOG_CLAMPED;
3597 alu.src[0].sel = ctx->temp_reg;
3598 alu.src[0].chan = 0;
3599 alu.dst.sel = ctx->temp_reg;
3600 alu.dst.chan = 2;
3601 alu.dst.write = 1;
3602 alu.last = 1;
3603 r = r600_bytecode_add_alu(ctx->bc, &alu);
3604 if (r)
3605 return r;
3606 }
3607
3608 chan = alu.dst.chan;
3609 sel = alu.dst.sel;
3610
3611 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
3612 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3613 alu.op = ALU_OP3_MUL_LIT;
3614 alu.src[0].sel = sel;
3615 alu.src[0].chan = chan;
3616 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
3617 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
3618 alu.dst.sel = ctx->temp_reg;
3619 alu.dst.chan = 0;
3620 alu.dst.write = 1;
3621 alu.is_op3 = 1;
3622 alu.last = 1;
3623 r = r600_bytecode_add_alu(ctx->bc, &alu);
3624 if (r)
3625 return r;
3626
3627 if (ctx->bc->chip_class == CAYMAN) {
3628 for (i = 0; i < 3; i++) {
3629 /* dst.z = exp(tmp.x) */
3630 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3631 alu.op = ALU_OP1_EXP_IEEE;
3632 alu.src[0].sel = ctx->temp_reg;
3633 alu.src[0].chan = 0;
3634 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3635 if (i == 2) {
3636 alu.dst.write = 1;
3637 alu.last = 1;
3638 } else
3639 alu.dst.write = 0;
3640 r = r600_bytecode_add_alu(ctx->bc, &alu);
3641 if (r)
3642 return r;
3643 }
3644 } else {
3645 /* dst.z = exp(tmp.x) */
3646 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3647 alu.op = ALU_OP1_EXP_IEEE;
3648 alu.src[0].sel = ctx->temp_reg;
3649 alu.src[0].chan = 0;
3650 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3651 alu.last = 1;
3652 r = r600_bytecode_add_alu(ctx->bc, &alu);
3653 if (r)
3654 return r;
3655 }
3656 }
3657
3658 /* dst.x, <- 1.0 */
3659 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3660 alu.op = ALU_OP1_MOV;
3661 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
3662 alu.src[0].chan = 0;
3663 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3664 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
3665 r = r600_bytecode_add_alu(ctx->bc, &alu);
3666 if (r)
3667 return r;
3668
3669 /* dst.y = max(src.x, 0.0) */
3670 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3671 alu.op = ALU_OP2_MAX;
3672 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3673 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3674 alu.src[1].chan = 0;
3675 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3676 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
3677 r = r600_bytecode_add_alu(ctx->bc, &alu);
3678 if (r)
3679 return r;
3680
3681 /* dst.w, <- 1.0 */
3682 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3683 alu.op = ALU_OP1_MOV;
3684 alu.src[0].sel = V_SQ_ALU_SRC_1;
3685 alu.src[0].chan = 0;
3686 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3687 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
3688 alu.last = 1;
3689 r = r600_bytecode_add_alu(ctx->bc, &alu);
3690 if (r)
3691 return r;
3692
3693 return 0;
3694 }
3695
3696 static int tgsi_rsq(struct r600_shader_ctx *ctx)
3697 {
3698 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3699 struct r600_bytecode_alu alu;
3700 int i, r;
3701
3702 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3703
3704 /* XXX:
3705 * For state trackers other than OpenGL, we'll want to use
3706 * _RECIPSQRT_IEEE instead.
3707 */
3708 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
3709
3710 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3711 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3712 r600_bytecode_src_set_abs(&alu.src[i]);
3713 }
3714 alu.dst.sel = ctx->temp_reg;
3715 alu.dst.write = 1;
3716 alu.last = 1;
3717 r = r600_bytecode_add_alu(ctx->bc, &alu);
3718 if (r)
3719 return r;
3720 /* replicate result */
3721 return tgsi_helper_tempx_replicate(ctx);
3722 }
3723
3724 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
3725 {
3726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3727 struct r600_bytecode_alu alu;
3728 int i, r;
3729
3730 for (i = 0; i < 4; i++) {
3731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3732 alu.src[0].sel = ctx->temp_reg;
3733 alu.op = ALU_OP1_MOV;
3734 alu.dst.chan = i;
3735 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3736 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3737 if (i == 3)
3738 alu.last = 1;
3739 r = r600_bytecode_add_alu(ctx->bc, &alu);
3740 if (r)
3741 return r;
3742 }
3743 return 0;
3744 }
3745
3746 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
3747 {
3748 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3749 struct r600_bytecode_alu alu;
3750 int i, r;
3751
3752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3753 alu.op = ctx->inst_info->op;
3754 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3755 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3756 }
3757 alu.dst.sel = ctx->temp_reg;
3758 alu.dst.write = 1;
3759 alu.last = 1;
3760 r = r600_bytecode_add_alu(ctx->bc, &alu);
3761 if (r)
3762 return r;
3763 /* replicate result */
3764 return tgsi_helper_tempx_replicate(ctx);
3765 }
3766
3767 static int cayman_pow(struct r600_shader_ctx *ctx)
3768 {
3769 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3770 int i, r;
3771 struct r600_bytecode_alu alu;
3772 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3773
3774 for (i = 0; i < 3; i++) {
3775 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3776 alu.op = ALU_OP1_LOG_IEEE;
3777 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3778 alu.dst.sel = ctx->temp_reg;
3779 alu.dst.chan = i;
3780 alu.dst.write = 1;
3781 if (i == 2)
3782 alu.last = 1;
3783 r = r600_bytecode_add_alu(ctx->bc, &alu);
3784 if (r)
3785 return r;
3786 }
3787
3788 /* b * LOG2(a) */
3789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3790 alu.op = ALU_OP2_MUL;
3791 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3792 alu.src[1].sel = ctx->temp_reg;
3793 alu.dst.sel = ctx->temp_reg;
3794 alu.dst.write = 1;
3795 alu.last = 1;
3796 r = r600_bytecode_add_alu(ctx->bc, &alu);
3797 if (r)
3798 return r;
3799
3800 for (i = 0; i < last_slot; i++) {
3801 /* POW(a,b) = EXP2(b * LOG2(a))*/
3802 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3803 alu.op = ALU_OP1_EXP_IEEE;
3804 alu.src[0].sel = ctx->temp_reg;
3805
3806 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3807 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3808 if (i == last_slot - 1)
3809 alu.last = 1;
3810 r = r600_bytecode_add_alu(ctx->bc, &alu);
3811 if (r)
3812 return r;
3813 }
3814 return 0;
3815 }
3816
3817 static int tgsi_pow(struct r600_shader_ctx *ctx)
3818 {
3819 struct r600_bytecode_alu alu;
3820 int r;
3821
3822 /* LOG2(a) */
3823 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3824 alu.op = ALU_OP1_LOG_IEEE;
3825 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3826 alu.dst.sel = ctx->temp_reg;
3827 alu.dst.write = 1;
3828 alu.last = 1;
3829 r = r600_bytecode_add_alu(ctx->bc, &alu);
3830 if (r)
3831 return r;
3832 /* b * LOG2(a) */
3833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3834 alu.op = ALU_OP2_MUL;
3835 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3836 alu.src[1].sel = ctx->temp_reg;
3837 alu.dst.sel = ctx->temp_reg;
3838 alu.dst.write = 1;
3839 alu.last = 1;
3840 r = r600_bytecode_add_alu(ctx->bc, &alu);
3841 if (r)
3842 return r;
3843 /* POW(a,b) = EXP2(b * LOG2(a))*/
3844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3845 alu.op = ALU_OP1_EXP_IEEE;
3846 alu.src[0].sel = ctx->temp_reg;
3847 alu.dst.sel = ctx->temp_reg;
3848 alu.dst.write = 1;
3849 alu.last = 1;
3850 r = r600_bytecode_add_alu(ctx->bc, &alu);
3851 if (r)
3852 return r;
3853 return tgsi_helper_tempx_replicate(ctx);
3854 }
3855
3856 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
3857 {
3858 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3859 struct r600_bytecode_alu alu;
3860 int i, r, j;
3861 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3862 int tmp0 = ctx->temp_reg;
3863 int tmp1 = r600_get_temp(ctx);
3864 int tmp2 = r600_get_temp(ctx);
3865 int tmp3 = r600_get_temp(ctx);
3866 /* Unsigned path:
3867 *
3868 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
3869 *
3870 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
3871 * 2. tmp0.z = lo (tmp0.x * src2)
3872 * 3. tmp0.w = -tmp0.z
3873 * 4. tmp0.y = hi (tmp0.x * src2)
3874 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
3875 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
3876 * 7. tmp1.x = tmp0.x - tmp0.w
3877 * 8. tmp1.y = tmp0.x + tmp0.w
3878 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
3879 * 10. tmp0.z = hi(tmp0.x * src1) = q
3880 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
3881 *
3882 * 12. tmp0.w = src1 - tmp0.y = r
3883 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
3884 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
3885 *
3886 * if DIV
3887 *
3888 * 15. tmp1.z = tmp0.z + 1 = q + 1
3889 * 16. tmp1.w = tmp0.z - 1 = q - 1
3890 *
3891 * else MOD
3892 *
3893 * 15. tmp1.z = tmp0.w - src2 = r - src2
3894 * 16. tmp1.w = tmp0.w + src2 = r + src2
3895 *
3896 * endif
3897 *
3898 * 17. tmp1.x = tmp1.x & tmp1.y
3899 *
3900 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
3901 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
3902 *
3903 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
3904 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
3905 *
3906 * Signed path:
3907 *
3908 * Same as unsigned, using abs values of the operands,
3909 * and fixing the sign of the result in the end.
3910 */
3911
3912 for (i = 0; i < 4; i++) {
3913 if (!(write_mask & (1<<i)))
3914 continue;
3915
3916 if (signed_op) {
3917
3918 /* tmp2.x = -src0 */
3919 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3920 alu.op = ALU_OP2_SUB_INT;
3921
3922 alu.dst.sel = tmp2;
3923 alu.dst.chan = 0;
3924 alu.dst.write = 1;
3925
3926 alu.src[0].sel = V_SQ_ALU_SRC_0;
3927
3928 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3929
3930 alu.last = 1;
3931 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3932 return r;
3933
3934 /* tmp2.y = -src1 */
3935 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3936 alu.op = ALU_OP2_SUB_INT;
3937
3938 alu.dst.sel = tmp2;
3939 alu.dst.chan = 1;
3940 alu.dst.write = 1;
3941
3942 alu.src[0].sel = V_SQ_ALU_SRC_0;
3943
3944 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3945
3946 alu.last = 1;
3947 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3948 return r;
3949
3950 /* tmp2.z sign bit is set if src0 and src2 signs are different */
3951 /* it will be a sign of the quotient */
3952 if (!mod) {
3953
3954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3955 alu.op = ALU_OP2_XOR_INT;
3956
3957 alu.dst.sel = tmp2;
3958 alu.dst.chan = 2;
3959 alu.dst.write = 1;
3960
3961 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3962 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3963
3964 alu.last = 1;
3965 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3966 return r;
3967 }
3968
3969 /* tmp2.x = |src0| */
3970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3971 alu.op = ALU_OP3_CNDGE_INT;
3972 alu.is_op3 = 1;
3973
3974 alu.dst.sel = tmp2;
3975 alu.dst.chan = 0;
3976 alu.dst.write = 1;
3977
3978 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3979 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3980 alu.src[2].sel = tmp2;
3981 alu.src[2].chan = 0;
3982
3983 alu.last = 1;
3984 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3985 return r;
3986
3987 /* tmp2.y = |src1| */
3988 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3989 alu.op = ALU_OP3_CNDGE_INT;
3990 alu.is_op3 = 1;
3991
3992 alu.dst.sel = tmp2;
3993 alu.dst.chan = 1;
3994 alu.dst.write = 1;
3995
3996 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3997 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3998 alu.src[2].sel = tmp2;
3999 alu.src[2].chan = 1;
4000
4001 alu.last = 1;
4002 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4003 return r;
4004
4005 }
4006
4007 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
4008 if (ctx->bc->chip_class == CAYMAN) {
4009 /* tmp3.x = u2f(src2) */
4010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4011 alu.op = ALU_OP1_UINT_TO_FLT;
4012
4013 alu.dst.sel = tmp3;
4014 alu.dst.chan = 0;
4015 alu.dst.write = 1;
4016
4017 if (signed_op) {
4018 alu.src[0].sel = tmp2;
4019 alu.src[0].chan = 1;
4020 } else {
4021 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4022 }
4023
4024 alu.last = 1;
4025 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4026 return r;
4027
4028 /* tmp0.x = recip(tmp3.x) */
4029 for (j = 0 ; j < 3; j++) {
4030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4031 alu.op = ALU_OP1_RECIP_IEEE;
4032
4033 alu.dst.sel = tmp0;
4034 alu.dst.chan = j;
4035 alu.dst.write = (j == 0);
4036
4037 alu.src[0].sel = tmp3;
4038 alu.src[0].chan = 0;
4039
4040 if (j == 2)
4041 alu.last = 1;
4042 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4043 return r;
4044 }
4045
4046 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4047 alu.op = ALU_OP2_MUL;
4048
4049 alu.src[0].sel = tmp0;
4050 alu.src[0].chan = 0;
4051
4052 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4053 alu.src[1].value = 0x4f800000;
4054
4055 alu.dst.sel = tmp3;
4056 alu.dst.write = 1;
4057 alu.last = 1;
4058 r = r600_bytecode_add_alu(ctx->bc, &alu);
4059 if (r)
4060 return r;
4061
4062 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4063 alu.op = ALU_OP1_FLT_TO_UINT;
4064
4065 alu.dst.sel = tmp0;
4066 alu.dst.chan = 0;
4067 alu.dst.write = 1;
4068
4069 alu.src[0].sel = tmp3;
4070 alu.src[0].chan = 0;
4071
4072 alu.last = 1;
4073 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4074 return r;
4075
4076 } else {
4077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4078 alu.op = ALU_OP1_RECIP_UINT;
4079
4080 alu.dst.sel = tmp0;
4081 alu.dst.chan = 0;
4082 alu.dst.write = 1;
4083
4084 if (signed_op) {
4085 alu.src[0].sel = tmp2;
4086 alu.src[0].chan = 1;
4087 } else {
4088 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4089 }
4090
4091 alu.last = 1;
4092 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4093 return r;
4094 }
4095
4096 /* 2. tmp0.z = lo (tmp0.x * src2) */
4097 if (ctx->bc->chip_class == CAYMAN) {
4098 for (j = 0 ; j < 4; j++) {
4099 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4100 alu.op = ALU_OP2_MULLO_UINT;
4101
4102 alu.dst.sel = tmp0;
4103 alu.dst.chan = j;
4104 alu.dst.write = (j == 2);
4105
4106 alu.src[0].sel = tmp0;
4107 alu.src[0].chan = 0;
4108 if (signed_op) {
4109 alu.src[1].sel = tmp2;
4110 alu.src[1].chan = 1;
4111 } else {
4112 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4113 }
4114
4115 alu.last = (j == 3);
4116 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4117 return r;
4118 }
4119 } else {
4120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4121 alu.op = ALU_OP2_MULLO_UINT;
4122
4123 alu.dst.sel = tmp0;
4124 alu.dst.chan = 2;
4125 alu.dst.write = 1;
4126
4127 alu.src[0].sel = tmp0;
4128 alu.src[0].chan = 0;
4129 if (signed_op) {
4130 alu.src[1].sel = tmp2;
4131 alu.src[1].chan = 1;
4132 } else {
4133 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4134 }
4135
4136 alu.last = 1;
4137 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4138 return r;
4139 }
4140
4141 /* 3. tmp0.w = -tmp0.z */
4142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4143 alu.op = ALU_OP2_SUB_INT;
4144
4145 alu.dst.sel = tmp0;
4146 alu.dst.chan = 3;
4147 alu.dst.write = 1;
4148
4149 alu.src[0].sel = V_SQ_ALU_SRC_0;
4150 alu.src[1].sel = tmp0;
4151 alu.src[1].chan = 2;
4152
4153 alu.last = 1;
4154 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4155 return r;
4156
4157 /* 4. tmp0.y = hi (tmp0.x * src2) */
4158 if (ctx->bc->chip_class == CAYMAN) {
4159 for (j = 0 ; j < 4; j++) {
4160 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4161 alu.op = ALU_OP2_MULHI_UINT;
4162
4163 alu.dst.sel = tmp0;
4164 alu.dst.chan = j;
4165 alu.dst.write = (j == 1);
4166
4167 alu.src[0].sel = tmp0;
4168 alu.src[0].chan = 0;
4169
4170 if (signed_op) {
4171 alu.src[1].sel = tmp2;
4172 alu.src[1].chan = 1;
4173 } else {
4174 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4175 }
4176 alu.last = (j == 3);
4177 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4178 return r;
4179 }
4180 } else {
4181 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4182 alu.op = ALU_OP2_MULHI_UINT;
4183
4184 alu.dst.sel = tmp0;
4185 alu.dst.chan = 1;
4186 alu.dst.write = 1;
4187
4188 alu.src[0].sel = tmp0;
4189 alu.src[0].chan = 0;
4190
4191 if (signed_op) {
4192 alu.src[1].sel = tmp2;
4193 alu.src[1].chan = 1;
4194 } else {
4195 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4196 }
4197
4198 alu.last = 1;
4199 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4200 return r;
4201 }
4202
4203 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
4204 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4205 alu.op = ALU_OP3_CNDE_INT;
4206 alu.is_op3 = 1;
4207
4208 alu.dst.sel = tmp0;
4209 alu.dst.chan = 2;
4210 alu.dst.write = 1;
4211
4212 alu.src[0].sel = tmp0;
4213 alu.src[0].chan = 1;
4214 alu.src[1].sel = tmp0;
4215 alu.src[1].chan = 3;
4216 alu.src[2].sel = tmp0;
4217 alu.src[2].chan = 2;
4218
4219 alu.last = 1;
4220 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4221 return r;
4222
4223 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
4224 if (ctx->bc->chip_class == CAYMAN) {
4225 for (j = 0 ; j < 4; j++) {
4226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4227 alu.op = ALU_OP2_MULHI_UINT;
4228
4229 alu.dst.sel = tmp0;
4230 alu.dst.chan = j;
4231 alu.dst.write = (j == 3);
4232
4233 alu.src[0].sel = tmp0;
4234 alu.src[0].chan = 2;
4235
4236 alu.src[1].sel = tmp0;
4237 alu.src[1].chan = 0;
4238
4239 alu.last = (j == 3);
4240 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4241 return r;
4242 }
4243 } else {
4244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4245 alu.op = ALU_OP2_MULHI_UINT;
4246
4247 alu.dst.sel = tmp0;
4248 alu.dst.chan = 3;
4249 alu.dst.write = 1;
4250
4251 alu.src[0].sel = tmp0;
4252 alu.src[0].chan = 2;
4253
4254 alu.src[1].sel = tmp0;
4255 alu.src[1].chan = 0;
4256
4257 alu.last = 1;
4258 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4259 return r;
4260 }
4261
4262 /* 7. tmp1.x = tmp0.x - tmp0.w */
4263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4264 alu.op = ALU_OP2_SUB_INT;
4265
4266 alu.dst.sel = tmp1;
4267 alu.dst.chan = 0;
4268 alu.dst.write = 1;
4269
4270 alu.src[0].sel = tmp0;
4271 alu.src[0].chan = 0;
4272 alu.src[1].sel = tmp0;
4273 alu.src[1].chan = 3;
4274
4275 alu.last = 1;
4276 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4277 return r;
4278
4279 /* 8. tmp1.y = tmp0.x + tmp0.w */
4280 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4281 alu.op = ALU_OP2_ADD_INT;
4282
4283 alu.dst.sel = tmp1;
4284 alu.dst.chan = 1;
4285 alu.dst.write = 1;
4286
4287 alu.src[0].sel = tmp0;
4288 alu.src[0].chan = 0;
4289 alu.src[1].sel = tmp0;
4290 alu.src[1].chan = 3;
4291
4292 alu.last = 1;
4293 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4294 return r;
4295
4296 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
4297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4298 alu.op = ALU_OP3_CNDE_INT;
4299 alu.is_op3 = 1;
4300
4301 alu.dst.sel = tmp0;
4302 alu.dst.chan = 0;
4303 alu.dst.write = 1;
4304
4305 alu.src[0].sel = tmp0;
4306 alu.src[0].chan = 1;
4307 alu.src[1].sel = tmp1;
4308 alu.src[1].chan = 1;
4309 alu.src[2].sel = tmp1;
4310 alu.src[2].chan = 0;
4311
4312 alu.last = 1;
4313 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4314 return r;
4315
4316 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
4317 if (ctx->bc->chip_class == CAYMAN) {
4318 for (j = 0 ; j < 4; j++) {
4319 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4320 alu.op = ALU_OP2_MULHI_UINT;
4321
4322 alu.dst.sel = tmp0;
4323 alu.dst.chan = j;
4324 alu.dst.write = (j == 2);
4325
4326 alu.src[0].sel = tmp0;
4327 alu.src[0].chan = 0;
4328
4329 if (signed_op) {
4330 alu.src[1].sel = tmp2;
4331 alu.src[1].chan = 0;
4332 } else {
4333 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4334 }
4335
4336 alu.last = (j == 3);
4337 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4338 return r;
4339 }
4340 } else {
4341 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4342 alu.op = ALU_OP2_MULHI_UINT;
4343
4344 alu.dst.sel = tmp0;
4345 alu.dst.chan = 2;
4346 alu.dst.write = 1;
4347
4348 alu.src[0].sel = tmp0;
4349 alu.src[0].chan = 0;
4350
4351 if (signed_op) {
4352 alu.src[1].sel = tmp2;
4353 alu.src[1].chan = 0;
4354 } else {
4355 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4356 }
4357
4358 alu.last = 1;
4359 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4360 return r;
4361 }
4362
4363 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
4364 if (ctx->bc->chip_class == CAYMAN) {
4365 for (j = 0 ; j < 4; j++) {
4366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4367 alu.op = ALU_OP2_MULLO_UINT;
4368
4369 alu.dst.sel = tmp0;
4370 alu.dst.chan = j;
4371 alu.dst.write = (j == 1);
4372
4373 if (signed_op) {
4374 alu.src[0].sel = tmp2;
4375 alu.src[0].chan = 1;
4376 } else {
4377 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4378 }
4379
4380 alu.src[1].sel = tmp0;
4381 alu.src[1].chan = 2;
4382
4383 alu.last = (j == 3);
4384 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4385 return r;
4386 }
4387 } else {
4388 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4389 alu.op = ALU_OP2_MULLO_UINT;
4390
4391 alu.dst.sel = tmp0;
4392 alu.dst.chan = 1;
4393 alu.dst.write = 1;
4394
4395 if (signed_op) {
4396 alu.src[0].sel = tmp2;
4397 alu.src[0].chan = 1;
4398 } else {
4399 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4400 }
4401
4402 alu.src[1].sel = tmp0;
4403 alu.src[1].chan = 2;
4404
4405 alu.last = 1;
4406 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4407 return r;
4408 }
4409
4410 /* 12. tmp0.w = src1 - tmp0.y = r */
4411 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4412 alu.op = ALU_OP2_SUB_INT;
4413
4414 alu.dst.sel = tmp0;
4415 alu.dst.chan = 3;
4416 alu.dst.write = 1;
4417
4418 if (signed_op) {
4419 alu.src[0].sel = tmp2;
4420 alu.src[0].chan = 0;
4421 } else {
4422 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4423 }
4424
4425 alu.src[1].sel = tmp0;
4426 alu.src[1].chan = 1;
4427
4428 alu.last = 1;
4429 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4430 return r;
4431
4432 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
4433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4434 alu.op = ALU_OP2_SETGE_UINT;
4435
4436 alu.dst.sel = tmp1;
4437 alu.dst.chan = 0;
4438 alu.dst.write = 1;
4439
4440 alu.src[0].sel = tmp0;
4441 alu.src[0].chan = 3;
4442 if (signed_op) {
4443 alu.src[1].sel = tmp2;
4444 alu.src[1].chan = 1;
4445 } else {
4446 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4447 }
4448
4449 alu.last = 1;
4450 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4451 return r;
4452
4453 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
4454 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4455 alu.op = ALU_OP2_SETGE_UINT;
4456
4457 alu.dst.sel = tmp1;
4458 alu.dst.chan = 1;
4459 alu.dst.write = 1;
4460
4461 if (signed_op) {
4462 alu.src[0].sel = tmp2;
4463 alu.src[0].chan = 0;
4464 } else {
4465 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4466 }
4467
4468 alu.src[1].sel = tmp0;
4469 alu.src[1].chan = 1;
4470
4471 alu.last = 1;
4472 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4473 return r;
4474
4475 if (mod) { /* UMOD */
4476
4477 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
4478 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4479 alu.op = ALU_OP2_SUB_INT;
4480
4481 alu.dst.sel = tmp1;
4482 alu.dst.chan = 2;
4483 alu.dst.write = 1;
4484
4485 alu.src[0].sel = tmp0;
4486 alu.src[0].chan = 3;
4487
4488 if (signed_op) {
4489 alu.src[1].sel = tmp2;
4490 alu.src[1].chan = 1;
4491 } else {
4492 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4493 }
4494
4495 alu.last = 1;
4496 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4497 return r;
4498
4499 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
4500 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4501 alu.op = ALU_OP2_ADD_INT;
4502
4503 alu.dst.sel = tmp1;
4504 alu.dst.chan = 3;
4505 alu.dst.write = 1;
4506
4507 alu.src[0].sel = tmp0;
4508 alu.src[0].chan = 3;
4509 if (signed_op) {
4510 alu.src[1].sel = tmp2;
4511 alu.src[1].chan = 1;
4512 } else {
4513 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4514 }
4515
4516 alu.last = 1;
4517 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4518 return r;
4519
4520 } else { /* UDIV */
4521
4522 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
4523 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4524 alu.op = ALU_OP2_ADD_INT;
4525
4526 alu.dst.sel = tmp1;
4527 alu.dst.chan = 2;
4528 alu.dst.write = 1;
4529
4530 alu.src[0].sel = tmp0;
4531 alu.src[0].chan = 2;
4532 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4533
4534 alu.last = 1;
4535 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4536 return r;
4537
4538 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
4539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4540 alu.op = ALU_OP2_ADD_INT;
4541
4542 alu.dst.sel = tmp1;
4543 alu.dst.chan = 3;
4544 alu.dst.write = 1;
4545
4546 alu.src[0].sel = tmp0;
4547 alu.src[0].chan = 2;
4548 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
4549
4550 alu.last = 1;
4551 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4552 return r;
4553
4554 }
4555
4556 /* 17. tmp1.x = tmp1.x & tmp1.y */
4557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4558 alu.op = ALU_OP2_AND_INT;
4559
4560 alu.dst.sel = tmp1;
4561 alu.dst.chan = 0;
4562 alu.dst.write = 1;
4563
4564 alu.src[0].sel = tmp1;
4565 alu.src[0].chan = 0;
4566 alu.src[1].sel = tmp1;
4567 alu.src[1].chan = 1;
4568
4569 alu.last = 1;
4570 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4571 return r;
4572
4573 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
4574 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
4575 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4576 alu.op = ALU_OP3_CNDE_INT;
4577 alu.is_op3 = 1;
4578
4579 alu.dst.sel = tmp0;
4580 alu.dst.chan = 2;
4581 alu.dst.write = 1;
4582
4583 alu.src[0].sel = tmp1;
4584 alu.src[0].chan = 0;
4585 alu.src[1].sel = tmp0;
4586 alu.src[1].chan = mod ? 3 : 2;
4587 alu.src[2].sel = tmp1;
4588 alu.src[2].chan = 2;
4589
4590 alu.last = 1;
4591 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4592 return r;
4593
4594 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
4595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4596 alu.op = ALU_OP3_CNDE_INT;
4597 alu.is_op3 = 1;
4598
4599 if (signed_op) {
4600 alu.dst.sel = tmp0;
4601 alu.dst.chan = 2;
4602 alu.dst.write = 1;
4603 } else {
4604 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4605 }
4606
4607 alu.src[0].sel = tmp1;
4608 alu.src[0].chan = 1;
4609 alu.src[1].sel = tmp1;
4610 alu.src[1].chan = 3;
4611 alu.src[2].sel = tmp0;
4612 alu.src[2].chan = 2;
4613
4614 alu.last = 1;
4615 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4616 return r;
4617
4618 if (signed_op) {
4619
4620 /* fix the sign of the result */
4621
4622 if (mod) {
4623
4624 /* tmp0.x = -tmp0.z */
4625 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4626 alu.op = ALU_OP2_SUB_INT;
4627
4628 alu.dst.sel = tmp0;
4629 alu.dst.chan = 0;
4630 alu.dst.write = 1;
4631
4632 alu.src[0].sel = V_SQ_ALU_SRC_0;
4633 alu.src[1].sel = tmp0;
4634 alu.src[1].chan = 2;
4635
4636 alu.last = 1;
4637 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4638 return r;
4639
4640 /* sign of the remainder is the same as the sign of src0 */
4641 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
4642 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4643 alu.op = ALU_OP3_CNDGE_INT;
4644 alu.is_op3 = 1;
4645
4646 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4647
4648 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4649 alu.src[1].sel = tmp0;
4650 alu.src[1].chan = 2;
4651 alu.src[2].sel = tmp0;
4652 alu.src[2].chan = 0;
4653
4654 alu.last = 1;
4655 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4656 return r;
4657
4658 } else {
4659
4660 /* tmp0.x = -tmp0.z */
4661 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4662 alu.op = ALU_OP2_SUB_INT;
4663
4664 alu.dst.sel = tmp0;
4665 alu.dst.chan = 0;
4666 alu.dst.write = 1;
4667
4668 alu.src[0].sel = V_SQ_ALU_SRC_0;
4669 alu.src[1].sel = tmp0;
4670 alu.src[1].chan = 2;
4671
4672 alu.last = 1;
4673 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4674 return r;
4675
4676 /* fix the quotient sign (same as the sign of src0*src1) */
4677 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
4678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4679 alu.op = ALU_OP3_CNDGE_INT;
4680 alu.is_op3 = 1;
4681
4682 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4683
4684 alu.src[0].sel = tmp2;
4685 alu.src[0].chan = 2;
4686 alu.src[1].sel = tmp0;
4687 alu.src[1].chan = 2;
4688 alu.src[2].sel = tmp0;
4689 alu.src[2].chan = 0;
4690
4691 alu.last = 1;
4692 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4693 return r;
4694 }
4695 }
4696 }
4697 return 0;
4698 }
4699
4700 static int tgsi_udiv(struct r600_shader_ctx *ctx)
4701 {
4702 return tgsi_divmod(ctx, 0, 0);
4703 }
4704
4705 static int tgsi_umod(struct r600_shader_ctx *ctx)
4706 {
4707 return tgsi_divmod(ctx, 1, 0);
4708 }
4709
4710 static int tgsi_idiv(struct r600_shader_ctx *ctx)
4711 {
4712 return tgsi_divmod(ctx, 0, 1);
4713 }
4714
4715 static int tgsi_imod(struct r600_shader_ctx *ctx)
4716 {
4717 return tgsi_divmod(ctx, 1, 1);
4718 }
4719
4720
4721 static int tgsi_f2i(struct r600_shader_ctx *ctx)
4722 {
4723 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4724 struct r600_bytecode_alu alu;
4725 int i, r;
4726 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4727 int last_inst = tgsi_last_instruction(write_mask);
4728
4729 for (i = 0; i < 4; i++) {
4730 if (!(write_mask & (1<<i)))
4731 continue;
4732
4733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4734 alu.op = ALU_OP1_TRUNC;
4735
4736 alu.dst.sel = ctx->temp_reg;
4737 alu.dst.chan = i;
4738 alu.dst.write = 1;
4739
4740 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4741 if (i == last_inst)
4742 alu.last = 1;
4743 r = r600_bytecode_add_alu(ctx->bc, &alu);
4744 if (r)
4745 return r;
4746 }
4747
4748 for (i = 0; i < 4; i++) {
4749 if (!(write_mask & (1<<i)))
4750 continue;
4751
4752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4753 alu.op = ctx->inst_info->op;
4754
4755 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4756
4757 alu.src[0].sel = ctx->temp_reg;
4758 alu.src[0].chan = i;
4759
4760 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
4761 alu.last = 1;
4762 r = r600_bytecode_add_alu(ctx->bc, &alu);
4763 if (r)
4764 return r;
4765 }
4766
4767 return 0;
4768 }
4769
4770 static int tgsi_iabs(struct r600_shader_ctx *ctx)
4771 {
4772 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4773 struct r600_bytecode_alu alu;
4774 int i, r;
4775 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4776 int last_inst = tgsi_last_instruction(write_mask);
4777
4778 /* tmp = -src */
4779 for (i = 0; i < 4; i++) {
4780 if (!(write_mask & (1<<i)))
4781 continue;
4782
4783 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4784 alu.op = ALU_OP2_SUB_INT;
4785
4786 alu.dst.sel = ctx->temp_reg;
4787 alu.dst.chan = i;
4788 alu.dst.write = 1;
4789
4790 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4791 alu.src[0].sel = V_SQ_ALU_SRC_0;
4792
4793 if (i == last_inst)
4794 alu.last = 1;
4795 r = r600_bytecode_add_alu(ctx->bc, &alu);
4796 if (r)
4797 return r;
4798 }
4799
4800 /* dst = (src >= 0 ? src : tmp) */
4801 for (i = 0; i < 4; i++) {
4802 if (!(write_mask & (1<<i)))
4803 continue;
4804
4805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4806 alu.op = ALU_OP3_CNDGE_INT;
4807 alu.is_op3 = 1;
4808 alu.dst.write = 1;
4809
4810 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4811
4812 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4813 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4814 alu.src[2].sel = ctx->temp_reg;
4815 alu.src[2].chan = i;
4816
4817 if (i == last_inst)
4818 alu.last = 1;
4819 r = r600_bytecode_add_alu(ctx->bc, &alu);
4820 if (r)
4821 return r;
4822 }
4823 return 0;
4824 }
4825
4826 static int tgsi_issg(struct r600_shader_ctx *ctx)
4827 {
4828 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4829 struct r600_bytecode_alu alu;
4830 int i, r;
4831 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4832 int last_inst = tgsi_last_instruction(write_mask);
4833
4834 /* tmp = (src >= 0 ? src : -1) */
4835 for (i = 0; i < 4; i++) {
4836 if (!(write_mask & (1<<i)))
4837 continue;
4838
4839 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4840 alu.op = ALU_OP3_CNDGE_INT;
4841 alu.is_op3 = 1;
4842
4843 alu.dst.sel = ctx->temp_reg;
4844 alu.dst.chan = i;
4845 alu.dst.write = 1;
4846
4847 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4848 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4849 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
4850
4851 if (i == last_inst)
4852 alu.last = 1;
4853 r = r600_bytecode_add_alu(ctx->bc, &alu);
4854 if (r)
4855 return r;
4856 }
4857
4858 /* dst = (tmp > 0 ? 1 : tmp) */
4859 for (i = 0; i < 4; i++) {
4860 if (!(write_mask & (1<<i)))
4861 continue;
4862
4863 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4864 alu.op = ALU_OP3_CNDGT_INT;
4865 alu.is_op3 = 1;
4866 alu.dst.write = 1;
4867
4868 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4869
4870 alu.src[0].sel = ctx->temp_reg;
4871 alu.src[0].chan = i;
4872
4873 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4874
4875 alu.src[2].sel = ctx->temp_reg;
4876 alu.src[2].chan = i;
4877
4878 if (i == last_inst)
4879 alu.last = 1;
4880 r = r600_bytecode_add_alu(ctx->bc, &alu);
4881 if (r)
4882 return r;
4883 }
4884 return 0;
4885 }
4886
4887
4888
4889 static int tgsi_ssg(struct r600_shader_ctx *ctx)
4890 {
4891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4892 struct r600_bytecode_alu alu;
4893 int i, r;
4894
4895 /* tmp = (src > 0 ? 1 : src) */
4896 for (i = 0; i < 4; i++) {
4897 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4898 alu.op = ALU_OP3_CNDGT;
4899 alu.is_op3 = 1;
4900
4901 alu.dst.sel = ctx->temp_reg;
4902 alu.dst.chan = i;
4903
4904 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4905 alu.src[1].sel = V_SQ_ALU_SRC_1;
4906 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
4907
4908 if (i == 3)
4909 alu.last = 1;
4910 r = r600_bytecode_add_alu(ctx->bc, &alu);
4911 if (r)
4912 return r;
4913 }
4914
4915 /* dst = (-tmp > 0 ? -1 : tmp) */
4916 for (i = 0; i < 4; i++) {
4917 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4918 alu.op = ALU_OP3_CNDGT;
4919 alu.is_op3 = 1;
4920 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4921
4922 alu.src[0].sel = ctx->temp_reg;
4923 alu.src[0].chan = i;
4924 alu.src[0].neg = 1;
4925
4926 alu.src[1].sel = V_SQ_ALU_SRC_1;
4927 alu.src[1].neg = 1;
4928
4929 alu.src[2].sel = ctx->temp_reg;
4930 alu.src[2].chan = i;
4931
4932 if (i == 3)
4933 alu.last = 1;
4934 r = r600_bytecode_add_alu(ctx->bc, &alu);
4935 if (r)
4936 return r;
4937 }
4938 return 0;
4939 }
4940
4941 static int tgsi_bfi(struct r600_shader_ctx *ctx)
4942 {
4943 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4944 struct r600_bytecode_alu alu;
4945 int i, r, t1, t2;
4946
4947 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4948 int last_inst = tgsi_last_instruction(write_mask);
4949
4950 t1 = ctx->temp_reg;
4951
4952 for (i = 0; i < 4; i++) {
4953 if (!(write_mask & (1<<i)))
4954 continue;
4955
4956 /* create mask tmp */
4957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4958 alu.op = ALU_OP2_BFM_INT;
4959 alu.dst.sel = t1;
4960 alu.dst.chan = i;
4961 alu.dst.write = 1;
4962 alu.last = i == last_inst;
4963
4964 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
4965 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4966
4967 r = r600_bytecode_add_alu(ctx->bc, &alu);
4968 if (r)
4969 return r;
4970 }
4971
4972 t2 = r600_get_temp(ctx);
4973
4974 for (i = 0; i < 4; i++) {
4975 if (!(write_mask & (1<<i)))
4976 continue;
4977
4978 /* shift insert left */
4979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4980 alu.op = ALU_OP2_LSHL_INT;
4981 alu.dst.sel = t2;
4982 alu.dst.chan = i;
4983 alu.dst.write = 1;
4984 alu.last = i == last_inst;
4985
4986 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4987 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4988
4989 r = r600_bytecode_add_alu(ctx->bc, &alu);
4990 if (r)
4991 return r;
4992 }
4993
4994 for (i = 0; i < 4; i++) {
4995 if (!(write_mask & (1<<i)))
4996 continue;
4997
4998 /* actual bitfield insert */
4999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5000 alu.op = ALU_OP3_BFI_INT;
5001 alu.is_op3 = 1;
5002 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5003 alu.dst.chan = i;
5004 alu.dst.write = 1;
5005 alu.last = i == last_inst;
5006
5007 alu.src[0].sel = t1;
5008 alu.src[0].chan = i;
5009 alu.src[1].sel = t2;
5010 alu.src[1].chan = i;
5011 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
5012
5013 r = r600_bytecode_add_alu(ctx->bc, &alu);
5014 if (r)
5015 return r;
5016 }
5017
5018 return 0;
5019 }
5020
5021 static int tgsi_msb(struct r600_shader_ctx *ctx)
5022 {
5023 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5024 struct r600_bytecode_alu alu;
5025 int i, r, t1, t2;
5026
5027 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5028 int last_inst = tgsi_last_instruction(write_mask);
5029
5030 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
5031 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
5032
5033 t1 = ctx->temp_reg;
5034
5035 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
5036 for (i = 0; i < 4; i++) {
5037 if (!(write_mask & (1<<i)))
5038 continue;
5039
5040 /* t1 = FFBH_INT / FFBH_UINT */
5041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5042 alu.op = ctx->inst_info->op;
5043 alu.dst.sel = t1;
5044 alu.dst.chan = i;
5045 alu.dst.write = 1;
5046 alu.last = i == last_inst;
5047
5048 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5049
5050 r = r600_bytecode_add_alu(ctx->bc, &alu);
5051 if (r)
5052 return r;
5053 }
5054
5055 t2 = r600_get_temp(ctx);
5056
5057 for (i = 0; i < 4; i++) {
5058 if (!(write_mask & (1<<i)))
5059 continue;
5060
5061 /* t2 = 31 - t1 */
5062 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5063 alu.op = ALU_OP2_SUB_INT;
5064 alu.dst.sel = t2;
5065 alu.dst.chan = i;
5066 alu.dst.write = 1;
5067 alu.last = i == last_inst;
5068
5069 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
5070 alu.src[0].value = 31;
5071 alu.src[1].sel = t1;
5072 alu.src[1].chan = i;
5073
5074 r = r600_bytecode_add_alu(ctx->bc, &alu);
5075 if (r)
5076 return r;
5077 }
5078
5079 for (i = 0; i < 4; i++) {
5080 if (!(write_mask & (1<<i)))
5081 continue;
5082
5083 /* result = t1 >= 0 ? t2 : t1 */
5084 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5085 alu.op = ALU_OP3_CNDGE_INT;
5086 alu.is_op3 = 1;
5087 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5088 alu.dst.chan = i;
5089 alu.dst.write = 1;
5090 alu.last = i == last_inst;
5091
5092 alu.src[0].sel = t1;
5093 alu.src[0].chan = i;
5094 alu.src[1].sel = t2;
5095 alu.src[1].chan = i;
5096 alu.src[2].sel = t1;
5097 alu.src[2].chan = i;
5098
5099 r = r600_bytecode_add_alu(ctx->bc, &alu);
5100 if (r)
5101 return r;
5102 }
5103
5104 return 0;
5105 }
5106
5107 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
5108 {
5109 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5110 struct r600_bytecode_alu alu;
5111 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
5112 unsigned location;
5113 int input;
5114
5115 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5116
5117 input = inst->Src[0].Register.Index;
5118
5119 /* Interpolators have been marked for use already by allocate_system_value_inputs */
5120 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5121 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5122 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
5123 }
5124 else {
5125 location = TGSI_INTERPOLATE_LOC_CENTROID;
5126 }
5127
5128 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
5129 if (k < 0)
5130 k = 0;
5131 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
5132 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
5133
5134 /* NOTE: currently offset is not perspective correct */
5135 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5136 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5137 int sample_gpr = -1;
5138 int gradientsH, gradientsV;
5139 struct r600_bytecode_tex tex;
5140
5141 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5142 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
5143 }
5144
5145 gradientsH = r600_get_temp(ctx);
5146 gradientsV = r600_get_temp(ctx);
5147 for (i = 0; i < 2; i++) {
5148 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5149 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
5150 tex.src_gpr = interp_gpr;
5151 tex.src_sel_x = interp_base_chan + 0;
5152 tex.src_sel_y = interp_base_chan + 1;
5153 tex.src_sel_z = 0;
5154 tex.src_sel_w = 0;
5155 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
5156 tex.dst_sel_x = 0;
5157 tex.dst_sel_y = 1;
5158 tex.dst_sel_z = 7;
5159 tex.dst_sel_w = 7;
5160 tex.inst_mod = 1; // Use per pixel gradient calculation
5161 tex.sampler_id = 0;
5162 tex.resource_id = tex.sampler_id;
5163 r = r600_bytecode_add_tex(ctx->bc, &tex);
5164 if (r)
5165 return r;
5166 }
5167
5168 for (i = 0; i < 2; i++) {
5169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5170 alu.op = ALU_OP3_MULADD;
5171 alu.is_op3 = 1;
5172 alu.src[0].sel = gradientsH;
5173 alu.src[0].chan = i;
5174 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5175 alu.src[1].sel = sample_gpr;
5176 alu.src[1].chan = 2;
5177 }
5178 else {
5179 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
5180 }
5181 alu.src[2].sel = interp_gpr;
5182 alu.src[2].chan = interp_base_chan + i;
5183 alu.dst.sel = ctx->temp_reg;
5184 alu.dst.chan = i;
5185 alu.last = i == 1;
5186
5187 r = r600_bytecode_add_alu(ctx->bc, &alu);
5188 if (r)
5189 return r;
5190 }
5191
5192 for (i = 0; i < 2; i++) {
5193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5194 alu.op = ALU_OP3_MULADD;
5195 alu.is_op3 = 1;
5196 alu.src[0].sel = gradientsV;
5197 alu.src[0].chan = i;
5198 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5199 alu.src[1].sel = sample_gpr;
5200 alu.src[1].chan = 3;
5201 }
5202 else {
5203 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
5204 }
5205 alu.src[2].sel = ctx->temp_reg;
5206 alu.src[2].chan = i;
5207 alu.dst.sel = ctx->temp_reg;
5208 alu.dst.chan = i;
5209 alu.last = i == 1;
5210
5211 r = r600_bytecode_add_alu(ctx->bc, &alu);
5212 if (r)
5213 return r;
5214 }
5215 }
5216
5217 tmp = r600_get_temp(ctx);
5218 for (i = 0; i < 8; i++) {
5219 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5220 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
5221
5222 alu.dst.sel = tmp;
5223 if ((i > 1 && i < 6)) {
5224 alu.dst.write = 1;
5225 }
5226 else {
5227 alu.dst.write = 0;
5228 }
5229 alu.dst.chan = i % 4;
5230
5231 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5232 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5233 alu.src[0].sel = ctx->temp_reg;
5234 alu.src[0].chan = 1 - (i % 2);
5235 } else {
5236 alu.src[0].sel = interp_gpr;
5237 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
5238 }
5239 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
5240 alu.src[1].chan = 0;
5241
5242 alu.last = i % 4 == 3;
5243 alu.bank_swizzle_force = SQ_ALU_VEC_210;
5244
5245 r = r600_bytecode_add_alu(ctx->bc, &alu);
5246 if (r)
5247 return r;
5248 }
5249
5250 // INTERP can't swizzle dst
5251 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5252 for (i = 0; i <= lasti; i++) {
5253 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5254 continue;
5255
5256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5257 alu.op = ALU_OP1_MOV;
5258 alu.src[0].sel = tmp;
5259 alu.src[0].chan = ctx->src[0].swizzle[i];
5260 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5261 alu.dst.write = 1;
5262 alu.last = i == lasti;
5263 r = r600_bytecode_add_alu(ctx->bc, &alu);
5264 if (r)
5265 return r;
5266 }
5267
5268 return 0;
5269 }
5270
5271
5272 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
5273 {
5274 struct r600_bytecode_alu alu;
5275 int i, r;
5276
5277 for (i = 0; i < 4; i++) {
5278 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5279 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
5280 alu.op = ALU_OP0_NOP;
5281 alu.dst.chan = i;
5282 } else {
5283 alu.op = ALU_OP1_MOV;
5284 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5285 alu.src[0].sel = ctx->temp_reg;
5286 alu.src[0].chan = i;
5287 }
5288 if (i == 3) {
5289 alu.last = 1;
5290 }
5291 r = r600_bytecode_add_alu(ctx->bc, &alu);
5292 if (r)
5293 return r;
5294 }
5295 return 0;
5296 }
5297
5298 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
5299 unsigned temp, int chan,
5300 struct r600_bytecode_alu_src *bc_src,
5301 const struct r600_shader_src *shader_src)
5302 {
5303 struct r600_bytecode_alu alu;
5304 int r;
5305
5306 r600_bytecode_src(bc_src, shader_src, chan);
5307
5308 /* op3 operands don't support abs modifier */
5309 if (bc_src->abs) {
5310 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
5311 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5312 alu.op = ALU_OP1_MOV;
5313 alu.dst.sel = temp;
5314 alu.dst.chan = chan;
5315 alu.dst.write = 1;
5316
5317 alu.src[0] = *bc_src;
5318 alu.last = true; // sufficient?
5319 r = r600_bytecode_add_alu(ctx->bc, &alu);
5320 if (r)
5321 return r;
5322
5323 memset(bc_src, 0, sizeof(*bc_src));
5324 bc_src->sel = temp;
5325 bc_src->chan = chan;
5326 }
5327 return 0;
5328 }
5329
5330 static int tgsi_op3(struct r600_shader_ctx *ctx)
5331 {
5332 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5333 struct r600_bytecode_alu alu;
5334 int i, j, r;
5335 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5336 int temp_regs[4];
5337
5338 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5339 temp_regs[j] = 0;
5340 if (ctx->src[j].abs)
5341 temp_regs[j] = r600_get_temp(ctx);
5342 }
5343 for (i = 0; i < lasti + 1; i++) {
5344 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5345 continue;
5346
5347 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5348 alu.op = ctx->inst_info->op;
5349 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5350 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
5351 if (r)
5352 return r;
5353 }
5354
5355 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5356 alu.dst.chan = i;
5357 alu.dst.write = 1;
5358 alu.is_op3 = 1;
5359 if (i == lasti) {
5360 alu.last = 1;
5361 }
5362 r = r600_bytecode_add_alu(ctx->bc, &alu);
5363 if (r)
5364 return r;
5365 }
5366 return 0;
5367 }
5368
5369 static int tgsi_dp(struct r600_shader_ctx *ctx)
5370 {
5371 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5372 struct r600_bytecode_alu alu;
5373 int i, j, r;
5374
5375 for (i = 0; i < 4; i++) {
5376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5377 alu.op = ctx->inst_info->op;
5378 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5379 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5380 }
5381
5382 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5383 alu.dst.chan = i;
5384 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5385 /* handle some special cases */
5386 switch (inst->Instruction.Opcode) {
5387 case TGSI_OPCODE_DP2:
5388 if (i > 1) {
5389 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5390 alu.src[0].chan = alu.src[1].chan = 0;
5391 }
5392 break;
5393 case TGSI_OPCODE_DP3:
5394 if (i > 2) {
5395 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5396 alu.src[0].chan = alu.src[1].chan = 0;
5397 }
5398 break;
5399 case TGSI_OPCODE_DPH:
5400 if (i == 3) {
5401 alu.src[0].sel = V_SQ_ALU_SRC_1;
5402 alu.src[0].chan = 0;
5403 alu.src[0].neg = 0;
5404 }
5405 break;
5406 default:
5407 break;
5408 }
5409 if (i == 3) {
5410 alu.last = 1;
5411 }
5412 r = r600_bytecode_add_alu(ctx->bc, &alu);
5413 if (r)
5414 return r;
5415 }
5416 return 0;
5417 }
5418
5419 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
5420 unsigned index)
5421 {
5422 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5423 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
5424 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
5425 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
5426 ctx->src[index].neg || ctx->src[index].abs ||
5427 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
5428 }
5429
5430 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
5431 unsigned index)
5432 {
5433 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5434 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
5435 }
5436
5437 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
5438 {
5439 struct r600_bytecode_vtx vtx;
5440 struct r600_bytecode_alu alu;
5441 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5442 int src_gpr, r, i;
5443 int id = tgsi_tex_get_src_gpr(ctx, 1);
5444
5445 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5446 if (src_requires_loading) {
5447 for (i = 0; i < 4; i++) {
5448 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5449 alu.op = ALU_OP1_MOV;
5450 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5451 alu.dst.sel = ctx->temp_reg;
5452 alu.dst.chan = i;
5453 if (i == 3)
5454 alu.last = 1;
5455 alu.dst.write = 1;
5456 r = r600_bytecode_add_alu(ctx->bc, &alu);
5457 if (r)
5458 return r;
5459 }
5460 src_gpr = ctx->temp_reg;
5461 }
5462
5463 memset(&vtx, 0, sizeof(vtx));
5464 vtx.op = FETCH_OP_VFETCH;
5465 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
5466 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
5467 vtx.src_gpr = src_gpr;
5468 vtx.mega_fetch_count = 16;
5469 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5470 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
5471 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
5472 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
5473 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
5474 vtx.use_const_fields = 1;
5475
5476 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
5477 return r;
5478
5479 if (ctx->bc->chip_class >= EVERGREEN)
5480 return 0;
5481
5482 for (i = 0; i < 4; i++) {
5483 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5484 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5485 continue;
5486
5487 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5488 alu.op = ALU_OP2_AND_INT;
5489
5490 alu.dst.chan = i;
5491 alu.dst.sel = vtx.dst_gpr;
5492 alu.dst.write = 1;
5493
5494 alu.src[0].sel = vtx.dst_gpr;
5495 alu.src[0].chan = i;
5496
5497 alu.src[1].sel = 512 + (id * 2);
5498 alu.src[1].chan = i % 4;
5499 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5500
5501 if (i == lasti)
5502 alu.last = 1;
5503 r = r600_bytecode_add_alu(ctx->bc, &alu);
5504 if (r)
5505 return r;
5506 }
5507
5508 if (inst->Dst[0].Register.WriteMask & 3) {
5509 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5510 alu.op = ALU_OP2_OR_INT;
5511
5512 alu.dst.chan = 3;
5513 alu.dst.sel = vtx.dst_gpr;
5514 alu.dst.write = 1;
5515
5516 alu.src[0].sel = vtx.dst_gpr;
5517 alu.src[0].chan = 3;
5518
5519 alu.src[1].sel = 512 + (id * 2) + 1;
5520 alu.src[1].chan = 0;
5521 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5522
5523 alu.last = 1;
5524 r = r600_bytecode_add_alu(ctx->bc, &alu);
5525 if (r)
5526 return r;
5527 }
5528 return 0;
5529 }
5530
5531 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
5532 {
5533 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5534 struct r600_bytecode_alu alu;
5535 int r;
5536 int id = tgsi_tex_get_src_gpr(ctx, 1);
5537
5538 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5539 alu.op = ALU_OP1_MOV;
5540
5541 if (ctx->bc->chip_class >= EVERGREEN) {
5542 /* channel 0 or 2 of each word */
5543 alu.src[0].sel = 512 + (id / 2);
5544 alu.src[0].chan = (id % 2) * 2;
5545 } else {
5546 /* r600 we have them at channel 2 of the second dword */
5547 alu.src[0].sel = 512 + (id * 2) + 1;
5548 alu.src[0].chan = 1;
5549 }
5550 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5551 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5552 alu.last = 1;
5553 r = r600_bytecode_add_alu(ctx->bc, &alu);
5554 if (r)
5555 return r;
5556 return 0;
5557 }
5558
5559 static int tgsi_tex(struct r600_shader_ctx *ctx)
5560 {
5561 static float one_point_five = 1.5f;
5562 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5563 struct r600_bytecode_tex tex;
5564 struct r600_bytecode_alu alu;
5565 unsigned src_gpr;
5566 int r, i, j;
5567 int opcode;
5568 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
5569 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5570 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
5571 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
5572
5573 bool txf_add_offsets = inst->Texture.NumOffsets &&
5574 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5575 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
5576
5577 /* Texture fetch instructions can only use gprs as source.
5578 * Also they cannot negate the source or take the absolute value */
5579 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
5580 tgsi_tex_src_requires_loading(ctx, 0)) ||
5581 read_compressed_msaa || txf_add_offsets;
5582
5583 boolean src_loaded = FALSE;
5584 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
5585 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
5586 boolean has_txq_cube_array_z = false;
5587 unsigned sampler_index_mode;
5588
5589 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
5590 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5591 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
5592 if (inst->Dst[0].Register.WriteMask & 4) {
5593 ctx->shader->has_txq_cube_array_z_comp = true;
5594 has_txq_cube_array_z = true;
5595 }
5596
5597 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
5598 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5599 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
5600 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
5601 sampler_src_reg = 2;
5602
5603 /* TGSI moves the sampler to src reg 3 for TXD */
5604 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
5605 sampler_src_reg = 3;
5606
5607 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
5608 if (sampler_index_mode)
5609 ctx->shader->uses_index_registers = true;
5610
5611 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5612
5613 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
5614 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
5615 ctx->shader->uses_tex_buffers = true;
5616 return r600_do_buffer_txq(ctx);
5617 }
5618 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
5619 if (ctx->bc->chip_class < EVERGREEN)
5620 ctx->shader->uses_tex_buffers = true;
5621 return do_vtx_fetch_inst(ctx, src_requires_loading);
5622 }
5623 }
5624
5625 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
5626 int out_chan;
5627 /* Add perspective divide */
5628 if (ctx->bc->chip_class == CAYMAN) {
5629 out_chan = 2;
5630 for (i = 0; i < 3; i++) {
5631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5632 alu.op = ALU_OP1_RECIP_IEEE;
5633 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5634
5635 alu.dst.sel = ctx->temp_reg;
5636 alu.dst.chan = i;
5637 if (i == 2)
5638 alu.last = 1;
5639 if (out_chan == i)
5640 alu.dst.write = 1;
5641 r = r600_bytecode_add_alu(ctx->bc, &alu);
5642 if (r)
5643 return r;
5644 }
5645
5646 } else {
5647 out_chan = 3;
5648 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5649 alu.op = ALU_OP1_RECIP_IEEE;
5650 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5651
5652 alu.dst.sel = ctx->temp_reg;
5653 alu.dst.chan = out_chan;
5654 alu.last = 1;
5655 alu.dst.write = 1;
5656 r = r600_bytecode_add_alu(ctx->bc, &alu);
5657 if (r)
5658 return r;
5659 }
5660
5661 for (i = 0; i < 3; i++) {
5662 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5663 alu.op = ALU_OP2_MUL;
5664 alu.src[0].sel = ctx->temp_reg;
5665 alu.src[0].chan = out_chan;
5666 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5667 alu.dst.sel = ctx->temp_reg;
5668 alu.dst.chan = i;
5669 alu.dst.write = 1;
5670 r = r600_bytecode_add_alu(ctx->bc, &alu);
5671 if (r)
5672 return r;
5673 }
5674 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5675 alu.op = ALU_OP1_MOV;
5676 alu.src[0].sel = V_SQ_ALU_SRC_1;
5677 alu.src[0].chan = 0;
5678 alu.dst.sel = ctx->temp_reg;
5679 alu.dst.chan = 3;
5680 alu.last = 1;
5681 alu.dst.write = 1;
5682 r = r600_bytecode_add_alu(ctx->bc, &alu);
5683 if (r)
5684 return r;
5685 src_loaded = TRUE;
5686 src_gpr = ctx->temp_reg;
5687 }
5688
5689
5690 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
5691 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5692 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5693 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
5694 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
5695 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
5696
5697 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
5698 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
5699
5700 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
5701 for (i = 0; i < 4; i++) {
5702 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5703 alu.op = ALU_OP2_CUBE;
5704 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5705 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
5706 alu.dst.sel = ctx->temp_reg;
5707 alu.dst.chan = i;
5708 if (i == 3)
5709 alu.last = 1;
5710 alu.dst.write = 1;
5711 r = r600_bytecode_add_alu(ctx->bc, &alu);
5712 if (r)
5713 return r;
5714 }
5715
5716 /* tmp1.z = RCP_e(|tmp1.z|) */
5717 if (ctx->bc->chip_class == CAYMAN) {
5718 for (i = 0; i < 3; i++) {
5719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5720 alu.op = ALU_OP1_RECIP_IEEE;
5721 alu.src[0].sel = ctx->temp_reg;
5722 alu.src[0].chan = 2;
5723 alu.src[0].abs = 1;
5724 alu.dst.sel = ctx->temp_reg;
5725 alu.dst.chan = i;
5726 if (i == 2)
5727 alu.dst.write = 1;
5728 if (i == 2)
5729 alu.last = 1;
5730 r = r600_bytecode_add_alu(ctx->bc, &alu);
5731 if (r)
5732 return r;
5733 }
5734 } else {
5735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5736 alu.op = ALU_OP1_RECIP_IEEE;
5737 alu.src[0].sel = ctx->temp_reg;
5738 alu.src[0].chan = 2;
5739 alu.src[0].abs = 1;
5740 alu.dst.sel = ctx->temp_reg;
5741 alu.dst.chan = 2;
5742 alu.dst.write = 1;
5743 alu.last = 1;
5744 r = r600_bytecode_add_alu(ctx->bc, &alu);
5745 if (r)
5746 return r;
5747 }
5748
5749 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
5750 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
5751 * muladd has no writemask, have to use another temp
5752 */
5753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5754 alu.op = ALU_OP3_MULADD;
5755 alu.is_op3 = 1;
5756
5757 alu.src[0].sel = ctx->temp_reg;
5758 alu.src[0].chan = 0;
5759 alu.src[1].sel = ctx->temp_reg;
5760 alu.src[1].chan = 2;
5761
5762 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5763 alu.src[2].chan = 0;
5764 alu.src[2].value = *(uint32_t *)&one_point_five;
5765
5766 alu.dst.sel = ctx->temp_reg;
5767 alu.dst.chan = 0;
5768 alu.dst.write = 1;
5769
5770 r = r600_bytecode_add_alu(ctx->bc, &alu);
5771 if (r)
5772 return r;
5773
5774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5775 alu.op = ALU_OP3_MULADD;
5776 alu.is_op3 = 1;
5777
5778 alu.src[0].sel = ctx->temp_reg;
5779 alu.src[0].chan = 1;
5780 alu.src[1].sel = ctx->temp_reg;
5781 alu.src[1].chan = 2;
5782
5783 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5784 alu.src[2].chan = 0;
5785 alu.src[2].value = *(uint32_t *)&one_point_five;
5786
5787 alu.dst.sel = ctx->temp_reg;
5788 alu.dst.chan = 1;
5789 alu.dst.write = 1;
5790
5791 alu.last = 1;
5792 r = r600_bytecode_add_alu(ctx->bc, &alu);
5793 if (r)
5794 return r;
5795 /* write initial compare value into Z component
5796 - W src 0 for shadow cube
5797 - X src 1 for shadow cube array */
5798 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5799 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5800 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5801 alu.op = ALU_OP1_MOV;
5802 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
5803 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5804 else
5805 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5806 alu.dst.sel = ctx->temp_reg;
5807 alu.dst.chan = 2;
5808 alu.dst.write = 1;
5809 alu.last = 1;
5810 r = r600_bytecode_add_alu(ctx->bc, &alu);
5811 if (r)
5812 return r;
5813 }
5814
5815 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5816 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5817 if (ctx->bc->chip_class >= EVERGREEN) {
5818 int mytmp = r600_get_temp(ctx);
5819 static const float eight = 8.0f;
5820 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5821 alu.op = ALU_OP1_MOV;
5822 alu.src[0].sel = ctx->temp_reg;
5823 alu.src[0].chan = 3;
5824 alu.dst.sel = mytmp;
5825 alu.dst.chan = 0;
5826 alu.dst.write = 1;
5827 alu.last = 1;
5828 r = r600_bytecode_add_alu(ctx->bc, &alu);
5829 if (r)
5830 return r;
5831
5832 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
5833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5834 alu.op = ALU_OP3_MULADD;
5835 alu.is_op3 = 1;
5836 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5837 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5838 alu.src[1].chan = 0;
5839 alu.src[1].value = *(uint32_t *)&eight;
5840 alu.src[2].sel = mytmp;
5841 alu.src[2].chan = 0;
5842 alu.dst.sel = ctx->temp_reg;
5843 alu.dst.chan = 3;
5844 alu.dst.write = 1;
5845 alu.last = 1;
5846 r = r600_bytecode_add_alu(ctx->bc, &alu);
5847 if (r)
5848 return r;
5849 } else if (ctx->bc->chip_class < EVERGREEN) {
5850 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5851 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
5852 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5853 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5854 tex.src_gpr = r600_get_temp(ctx);
5855 tex.src_sel_x = 0;
5856 tex.src_sel_y = 0;
5857 tex.src_sel_z = 0;
5858 tex.src_sel_w = 0;
5859 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
5860 tex.coord_type_x = 1;
5861 tex.coord_type_y = 1;
5862 tex.coord_type_z = 1;
5863 tex.coord_type_w = 1;
5864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5865 alu.op = ALU_OP1_MOV;
5866 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5867 alu.dst.sel = tex.src_gpr;
5868 alu.dst.chan = 0;
5869 alu.last = 1;
5870 alu.dst.write = 1;
5871 r = r600_bytecode_add_alu(ctx->bc, &alu);
5872 if (r)
5873 return r;
5874
5875 r = r600_bytecode_add_tex(ctx->bc, &tex);
5876 if (r)
5877 return r;
5878 }
5879
5880 }
5881
5882 /* for cube forms of lod and bias we need to route things */
5883 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
5884 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
5885 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5886 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
5887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5888 alu.op = ALU_OP1_MOV;
5889 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5890 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
5891 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5892 else
5893 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5894 alu.dst.sel = ctx->temp_reg;
5895 alu.dst.chan = 2;
5896 alu.last = 1;
5897 alu.dst.write = 1;
5898 r = r600_bytecode_add_alu(ctx->bc, &alu);
5899 if (r)
5900 return r;
5901 }
5902
5903 src_loaded = TRUE;
5904 src_gpr = ctx->temp_reg;
5905 }
5906
5907 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
5908 int temp_h = 0, temp_v = 0;
5909 int start_val = 0;
5910
5911 /* if we've already loaded the src (i.e. CUBE don't reload it). */
5912 if (src_loaded == TRUE)
5913 start_val = 1;
5914 else
5915 src_loaded = TRUE;
5916 for (i = start_val; i < 3; i++) {
5917 int treg = r600_get_temp(ctx);
5918
5919 if (i == 0)
5920 src_gpr = treg;
5921 else if (i == 1)
5922 temp_h = treg;
5923 else
5924 temp_v = treg;
5925
5926 for (j = 0; j < 4; j++) {
5927 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5928 alu.op = ALU_OP1_MOV;
5929 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
5930 alu.dst.sel = treg;
5931 alu.dst.chan = j;
5932 if (j == 3)
5933 alu.last = 1;
5934 alu.dst.write = 1;
5935 r = r600_bytecode_add_alu(ctx->bc, &alu);
5936 if (r)
5937 return r;
5938 }
5939 }
5940 for (i = 1; i < 3; i++) {
5941 /* set gradients h/v */
5942 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5943 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
5944 FETCH_OP_SET_GRADIENTS_V;
5945 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5946 tex.sampler_index_mode = sampler_index_mode;
5947 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5948 tex.resource_index_mode = sampler_index_mode;
5949
5950 tex.src_gpr = (i == 1) ? temp_h : temp_v;
5951 tex.src_sel_x = 0;
5952 tex.src_sel_y = 1;
5953 tex.src_sel_z = 2;
5954 tex.src_sel_w = 3;
5955
5956 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
5957 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
5958 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
5959 tex.coord_type_x = 1;
5960 tex.coord_type_y = 1;
5961 tex.coord_type_z = 1;
5962 tex.coord_type_w = 1;
5963 }
5964 r = r600_bytecode_add_tex(ctx->bc, &tex);
5965 if (r)
5966 return r;
5967 }
5968 }
5969
5970 if (src_requires_loading && !src_loaded) {
5971 for (i = 0; i < 4; i++) {
5972 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5973 alu.op = ALU_OP1_MOV;
5974 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5975 alu.dst.sel = ctx->temp_reg;
5976 alu.dst.chan = i;
5977 if (i == 3)
5978 alu.last = 1;
5979 alu.dst.write = 1;
5980 r = r600_bytecode_add_alu(ctx->bc, &alu);
5981 if (r)
5982 return r;
5983 }
5984 src_loaded = TRUE;
5985 src_gpr = ctx->temp_reg;
5986 }
5987
5988 /* get offset values */
5989 if (inst->Texture.NumOffsets) {
5990 assert(inst->Texture.NumOffsets == 1);
5991
5992 /* The texture offset feature doesn't work with the TXF instruction
5993 * and must be emulated by adding the offset to the texture coordinates. */
5994 if (txf_add_offsets) {
5995 const struct tgsi_texture_offset *off = inst->TexOffsets;
5996
5997 switch (inst->Texture.Texture) {
5998 case TGSI_TEXTURE_3D:
5999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6000 alu.op = ALU_OP2_ADD_INT;
6001 alu.src[0].sel = src_gpr;
6002 alu.src[0].chan = 2;
6003 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6004 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
6005 alu.dst.sel = src_gpr;
6006 alu.dst.chan = 2;
6007 alu.dst.write = 1;
6008 alu.last = 1;
6009 r = r600_bytecode_add_alu(ctx->bc, &alu);
6010 if (r)
6011 return r;
6012 /* fall through */
6013
6014 case TGSI_TEXTURE_2D:
6015 case TGSI_TEXTURE_SHADOW2D:
6016 case TGSI_TEXTURE_RECT:
6017 case TGSI_TEXTURE_SHADOWRECT:
6018 case TGSI_TEXTURE_2D_ARRAY:
6019 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6021 alu.op = ALU_OP2_ADD_INT;
6022 alu.src[0].sel = src_gpr;
6023 alu.src[0].chan = 1;
6024 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6025 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
6026 alu.dst.sel = src_gpr;
6027 alu.dst.chan = 1;
6028 alu.dst.write = 1;
6029 alu.last = 1;
6030 r = r600_bytecode_add_alu(ctx->bc, &alu);
6031 if (r)
6032 return r;
6033 /* fall through */
6034
6035 case TGSI_TEXTURE_1D:
6036 case TGSI_TEXTURE_SHADOW1D:
6037 case TGSI_TEXTURE_1D_ARRAY:
6038 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6040 alu.op = ALU_OP2_ADD_INT;
6041 alu.src[0].sel = src_gpr;
6042 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6043 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
6044 alu.dst.sel = src_gpr;
6045 alu.dst.write = 1;
6046 alu.last = 1;
6047 r = r600_bytecode_add_alu(ctx->bc, &alu);
6048 if (r)
6049 return r;
6050 break;
6051 /* texture offsets do not apply to other texture targets */
6052 }
6053 } else {
6054 switch (inst->Texture.Texture) {
6055 case TGSI_TEXTURE_3D:
6056 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
6057 /* fallthrough */
6058 case TGSI_TEXTURE_2D:
6059 case TGSI_TEXTURE_SHADOW2D:
6060 case TGSI_TEXTURE_RECT:
6061 case TGSI_TEXTURE_SHADOWRECT:
6062 case TGSI_TEXTURE_2D_ARRAY:
6063 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6064 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
6065 /* fallthrough */
6066 case TGSI_TEXTURE_1D:
6067 case TGSI_TEXTURE_SHADOW1D:
6068 case TGSI_TEXTURE_1D_ARRAY:
6069 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6070 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
6071 }
6072 }
6073 }
6074
6075 /* Obtain the sample index for reading a compressed MSAA color texture.
6076 * To read the FMASK, we use the ldfptr instruction, which tells us
6077 * where the samples are stored.
6078 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
6079 * which is the identity mapping. Each nibble says which physical sample
6080 * should be fetched to get that sample.
6081 *
6082 * Assume src.z contains the sample index. It should be modified like this:
6083 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
6084 * Then fetch the texel with src.
6085 */
6086 if (read_compressed_msaa) {
6087 unsigned sample_chan = 3;
6088 unsigned temp = r600_get_temp(ctx);
6089 assert(src_loaded);
6090
6091 /* temp.w = ldfptr() */
6092 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6093 tex.op = FETCH_OP_LD;
6094 tex.inst_mod = 1; /* to indicate this is ldfptr */
6095 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6096 tex.sampler_index_mode = sampler_index_mode;
6097 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6098 tex.resource_index_mode = sampler_index_mode;
6099 tex.src_gpr = src_gpr;
6100 tex.dst_gpr = temp;
6101 tex.dst_sel_x = 7; /* mask out these components */
6102 tex.dst_sel_y = 7;
6103 tex.dst_sel_z = 7;
6104 tex.dst_sel_w = 0; /* store X */
6105 tex.src_sel_x = 0;
6106 tex.src_sel_y = 1;
6107 tex.src_sel_z = 2;
6108 tex.src_sel_w = 3;
6109 tex.offset_x = offset_x;
6110 tex.offset_y = offset_y;
6111 tex.offset_z = offset_z;
6112 r = r600_bytecode_add_tex(ctx->bc, &tex);
6113 if (r)
6114 return r;
6115
6116 /* temp.x = sample_index*4 */
6117 if (ctx->bc->chip_class == CAYMAN) {
6118 for (i = 0 ; i < 4; i++) {
6119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6120 alu.op = ALU_OP2_MULLO_INT;
6121 alu.src[0].sel = src_gpr;
6122 alu.src[0].chan = sample_chan;
6123 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6124 alu.src[1].value = 4;
6125 alu.dst.sel = temp;
6126 alu.dst.chan = i;
6127 alu.dst.write = i == 0;
6128 if (i == 3)
6129 alu.last = 1;
6130 r = r600_bytecode_add_alu(ctx->bc, &alu);
6131 if (r)
6132 return r;
6133 }
6134 } else {
6135 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6136 alu.op = ALU_OP2_MULLO_INT;
6137 alu.src[0].sel = src_gpr;
6138 alu.src[0].chan = sample_chan;
6139 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6140 alu.src[1].value = 4;
6141 alu.dst.sel = temp;
6142 alu.dst.chan = 0;
6143 alu.dst.write = 1;
6144 alu.last = 1;
6145 r = r600_bytecode_add_alu(ctx->bc, &alu);
6146 if (r)
6147 return r;
6148 }
6149
6150 /* sample_index = temp.w >> temp.x */
6151 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6152 alu.op = ALU_OP2_LSHR_INT;
6153 alu.src[0].sel = temp;
6154 alu.src[0].chan = 3;
6155 alu.src[1].sel = temp;
6156 alu.src[1].chan = 0;
6157 alu.dst.sel = src_gpr;
6158 alu.dst.chan = sample_chan;
6159 alu.dst.write = 1;
6160 alu.last = 1;
6161 r = r600_bytecode_add_alu(ctx->bc, &alu);
6162 if (r)
6163 return r;
6164
6165 /* sample_index & 0xF */
6166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6167 alu.op = ALU_OP2_AND_INT;
6168 alu.src[0].sel = src_gpr;
6169 alu.src[0].chan = sample_chan;
6170 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6171 alu.src[1].value = 0xF;
6172 alu.dst.sel = src_gpr;
6173 alu.dst.chan = sample_chan;
6174 alu.dst.write = 1;
6175 alu.last = 1;
6176 r = r600_bytecode_add_alu(ctx->bc, &alu);
6177 if (r)
6178 return r;
6179 #if 0
6180 /* visualize the FMASK */
6181 for (i = 0; i < 4; i++) {
6182 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6183 alu.op = ALU_OP1_INT_TO_FLT;
6184 alu.src[0].sel = src_gpr;
6185 alu.src[0].chan = sample_chan;
6186 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6187 alu.dst.chan = i;
6188 alu.dst.write = 1;
6189 alu.last = 1;
6190 r = r600_bytecode_add_alu(ctx->bc, &alu);
6191 if (r)
6192 return r;
6193 }
6194 return 0;
6195 #endif
6196 }
6197
6198 /* does this shader want a num layers from TXQ for a cube array? */
6199 if (has_txq_cube_array_z) {
6200 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6201
6202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6203 alu.op = ALU_OP1_MOV;
6204
6205 if (ctx->bc->chip_class >= EVERGREEN) {
6206 /* channel 1 or 3 of each word */
6207 alu.src[0].sel = 512 + (id / 2);
6208 alu.src[0].chan = ((id % 2) * 2) + 1;
6209 } else {
6210 /* r600 we have them at channel 2 of the second dword */
6211 alu.src[0].sel = 512 + (id * 2) + 1;
6212 alu.src[0].chan = 2;
6213 }
6214 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6215 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
6216 alu.last = 1;
6217 r = r600_bytecode_add_alu(ctx->bc, &alu);
6218 if (r)
6219 return r;
6220 /* disable writemask from texture instruction */
6221 inst->Dst[0].Register.WriteMask &= ~4;
6222 }
6223
6224 opcode = ctx->inst_info->op;
6225 if (opcode == FETCH_OP_GATHER4 &&
6226 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
6227 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
6228 opcode = FETCH_OP_GATHER4_O;
6229
6230 /* GATHER4_O/GATHER4_C_O use offset values loaded by
6231 SET_TEXTURE_OFFSETS instruction. The immediate offset values
6232 encoded in the instruction are ignored. */
6233 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6234 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
6235 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6236 tex.sampler_index_mode = sampler_index_mode;
6237 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6238 tex.resource_index_mode = sampler_index_mode;
6239
6240 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
6241 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
6242 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
6243 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
6244 tex.src_sel_w = 4;
6245
6246 tex.dst_sel_x = 7;
6247 tex.dst_sel_y = 7;
6248 tex.dst_sel_z = 7;
6249 tex.dst_sel_w = 7;
6250
6251 r = r600_bytecode_add_tex(ctx->bc, &tex);
6252 if (r)
6253 return r;
6254 }
6255
6256 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6257 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6258 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6259 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6260 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
6261 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6262 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6263 switch (opcode) {
6264 case FETCH_OP_SAMPLE:
6265 opcode = FETCH_OP_SAMPLE_C;
6266 break;
6267 case FETCH_OP_SAMPLE_L:
6268 opcode = FETCH_OP_SAMPLE_C_L;
6269 break;
6270 case FETCH_OP_SAMPLE_LB:
6271 opcode = FETCH_OP_SAMPLE_C_LB;
6272 break;
6273 case FETCH_OP_SAMPLE_G:
6274 opcode = FETCH_OP_SAMPLE_C_G;
6275 break;
6276 /* Texture gather variants */
6277 case FETCH_OP_GATHER4:
6278 opcode = FETCH_OP_GATHER4_C;
6279 break;
6280 case FETCH_OP_GATHER4_O:
6281 opcode = FETCH_OP_GATHER4_C_O;
6282 break;
6283 }
6284 }
6285
6286 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6287 tex.op = opcode;
6288
6289 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6290 tex.sampler_index_mode = sampler_index_mode;
6291 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6292 tex.resource_index_mode = sampler_index_mode;
6293 tex.src_gpr = src_gpr;
6294 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6295
6296 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
6297 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
6298 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
6299 }
6300
6301 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
6302 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
6303 tex.inst_mod = texture_component_select;
6304
6305 if (ctx->bc->chip_class == CAYMAN) {
6306 /* GATHER4 result order is different from TGSI TG4 */
6307 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
6308 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
6309 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
6310 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6311 } else {
6312 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6313 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6314 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6315 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6316 }
6317 }
6318 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
6319 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6320 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6321 tex.dst_sel_z = 7;
6322 tex.dst_sel_w = 7;
6323 }
6324 else {
6325 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6326 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6327 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6328 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6329 }
6330
6331
6332 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
6333 tex.src_sel_x = 4;
6334 tex.src_sel_y = 4;
6335 tex.src_sel_z = 4;
6336 tex.src_sel_w = 4;
6337 } else if (src_loaded) {
6338 tex.src_sel_x = 0;
6339 tex.src_sel_y = 1;
6340 tex.src_sel_z = 2;
6341 tex.src_sel_w = 3;
6342 } else {
6343 tex.src_sel_x = ctx->src[0].swizzle[0];
6344 tex.src_sel_y = ctx->src[0].swizzle[1];
6345 tex.src_sel_z = ctx->src[0].swizzle[2];
6346 tex.src_sel_w = ctx->src[0].swizzle[3];
6347 tex.src_rel = ctx->src[0].rel;
6348 }
6349
6350 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6351 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6352 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6353 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6354 tex.src_sel_x = 1;
6355 tex.src_sel_y = 0;
6356 tex.src_sel_z = 3;
6357 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
6358 }
6359
6360 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
6361 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
6362 tex.coord_type_x = 1;
6363 tex.coord_type_y = 1;
6364 }
6365 tex.coord_type_z = 1;
6366 tex.coord_type_w = 1;
6367
6368 tex.offset_x = offset_x;
6369 tex.offset_y = offset_y;
6370 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
6371 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6372 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
6373 tex.offset_z = 0;
6374 }
6375 else {
6376 tex.offset_z = offset_z;
6377 }
6378
6379 /* Put the depth for comparison in W.
6380 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
6381 * Some instructions expect the depth in Z. */
6382 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6383 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6384 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6385 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
6386 opcode != FETCH_OP_SAMPLE_C_L &&
6387 opcode != FETCH_OP_SAMPLE_C_LB) {
6388 tex.src_sel_w = tex.src_sel_z;
6389 }
6390
6391 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
6392 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
6393 if (opcode == FETCH_OP_SAMPLE_C_L ||
6394 opcode == FETCH_OP_SAMPLE_C_LB) {
6395 /* the array index is read from Y */
6396 tex.coord_type_y = 0;
6397 } else {
6398 /* the array index is read from Z */
6399 tex.coord_type_z = 0;
6400 tex.src_sel_z = tex.src_sel_y;
6401 }
6402 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6403 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6404 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6405 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6406 (ctx->bc->chip_class >= EVERGREEN)))
6407 /* the array index is read from Z */
6408 tex.coord_type_z = 0;
6409
6410 /* mask unused source components */
6411 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
6412 switch (inst->Texture.Texture) {
6413 case TGSI_TEXTURE_2D:
6414 case TGSI_TEXTURE_RECT:
6415 tex.src_sel_z = 7;
6416 tex.src_sel_w = 7;
6417 break;
6418 case TGSI_TEXTURE_1D_ARRAY:
6419 tex.src_sel_y = 7;
6420 tex.src_sel_w = 7;
6421 break;
6422 case TGSI_TEXTURE_1D:
6423 tex.src_sel_y = 7;
6424 tex.src_sel_z = 7;
6425 tex.src_sel_w = 7;
6426 break;
6427 }
6428 }
6429
6430 r = r600_bytecode_add_tex(ctx->bc, &tex);
6431 if (r)
6432 return r;
6433
6434 /* add shadow ambient support - gallium doesn't do it yet */
6435 return 0;
6436 }
6437
6438 static int tgsi_lrp(struct r600_shader_ctx *ctx)
6439 {
6440 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6441 struct r600_bytecode_alu alu;
6442 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6443 unsigned i, temp_regs[2];
6444 int r;
6445
6446 /* optimize if it's just an equal balance */
6447 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
6448 for (i = 0; i < lasti + 1; i++) {
6449 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6450 continue;
6451
6452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6453 alu.op = ALU_OP2_ADD;
6454 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6455 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6456 alu.omod = 3;
6457 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6458 alu.dst.chan = i;
6459 if (i == lasti) {
6460 alu.last = 1;
6461 }
6462 r = r600_bytecode_add_alu(ctx->bc, &alu);
6463 if (r)
6464 return r;
6465 }
6466 return 0;
6467 }
6468
6469 /* 1 - src0 */
6470 for (i = 0; i < lasti + 1; i++) {
6471 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6472 continue;
6473
6474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6475 alu.op = ALU_OP2_ADD;
6476 alu.src[0].sel = V_SQ_ALU_SRC_1;
6477 alu.src[0].chan = 0;
6478 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6479 r600_bytecode_src_toggle_neg(&alu.src[1]);
6480 alu.dst.sel = ctx->temp_reg;
6481 alu.dst.chan = i;
6482 if (i == lasti) {
6483 alu.last = 1;
6484 }
6485 alu.dst.write = 1;
6486 r = r600_bytecode_add_alu(ctx->bc, &alu);
6487 if (r)
6488 return r;
6489 }
6490
6491 /* (1 - src0) * src2 */
6492 for (i = 0; i < lasti + 1; i++) {
6493 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6494 continue;
6495
6496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6497 alu.op = ALU_OP2_MUL;
6498 alu.src[0].sel = ctx->temp_reg;
6499 alu.src[0].chan = i;
6500 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6501 alu.dst.sel = ctx->temp_reg;
6502 alu.dst.chan = i;
6503 if (i == lasti) {
6504 alu.last = 1;
6505 }
6506 alu.dst.write = 1;
6507 r = r600_bytecode_add_alu(ctx->bc, &alu);
6508 if (r)
6509 return r;
6510 }
6511
6512 /* src0 * src1 + (1 - src0) * src2 */
6513 if (ctx->src[0].abs)
6514 temp_regs[0] = r600_get_temp(ctx);
6515 else
6516 temp_regs[0] = 0;
6517 if (ctx->src[1].abs)
6518 temp_regs[1] = r600_get_temp(ctx);
6519 else
6520 temp_regs[1] = 0;
6521
6522 for (i = 0; i < lasti + 1; i++) {
6523 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6524 continue;
6525
6526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6527 alu.op = ALU_OP3_MULADD;
6528 alu.is_op3 = 1;
6529 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6530 if (r)
6531 return r;
6532 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
6533 if (r)
6534 return r;
6535 alu.src[2].sel = ctx->temp_reg;
6536 alu.src[2].chan = i;
6537
6538 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6539 alu.dst.chan = i;
6540 if (i == lasti) {
6541 alu.last = 1;
6542 }
6543 r = r600_bytecode_add_alu(ctx->bc, &alu);
6544 if (r)
6545 return r;
6546 }
6547 return 0;
6548 }
6549
6550 static int tgsi_cmp(struct r600_shader_ctx *ctx)
6551 {
6552 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6553 struct r600_bytecode_alu alu;
6554 int i, r, j;
6555 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6556 int temp_regs[3];
6557
6558 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6559 temp_regs[j] = 0;
6560 if (ctx->src[j].abs)
6561 temp_regs[j] = r600_get_temp(ctx);
6562 }
6563
6564 for (i = 0; i < lasti + 1; i++) {
6565 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6566 continue;
6567
6568 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6569 alu.op = ALU_OP3_CNDGE;
6570 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6571 if (r)
6572 return r;
6573 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
6574 if (r)
6575 return r;
6576 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
6577 if (r)
6578 return r;
6579 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6580 alu.dst.chan = i;
6581 alu.dst.write = 1;
6582 alu.is_op3 = 1;
6583 if (i == lasti)
6584 alu.last = 1;
6585 r = r600_bytecode_add_alu(ctx->bc, &alu);
6586 if (r)
6587 return r;
6588 }
6589 return 0;
6590 }
6591
6592 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
6593 {
6594 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6595 struct r600_bytecode_alu alu;
6596 int i, r;
6597 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6598
6599 for (i = 0; i < lasti + 1; i++) {
6600 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6601 continue;
6602
6603 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6604 alu.op = ALU_OP3_CNDE_INT;
6605 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6606 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6607 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6608 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6609 alu.dst.chan = i;
6610 alu.dst.write = 1;
6611 alu.is_op3 = 1;
6612 if (i == lasti)
6613 alu.last = 1;
6614 r = r600_bytecode_add_alu(ctx->bc, &alu);
6615 if (r)
6616 return r;
6617 }
6618 return 0;
6619 }
6620
6621 static int tgsi_xpd(struct r600_shader_ctx *ctx)
6622 {
6623 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6624 static const unsigned int src0_swizzle[] = {2, 0, 1};
6625 static const unsigned int src1_swizzle[] = {1, 2, 0};
6626 struct r600_bytecode_alu alu;
6627 uint32_t use_temp = 0;
6628 int i, r;
6629
6630 if (inst->Dst[0].Register.WriteMask != 0xf)
6631 use_temp = 1;
6632
6633 for (i = 0; i < 4; i++) {
6634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6635 alu.op = ALU_OP2_MUL;
6636 if (i < 3) {
6637 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6638 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
6639 } else {
6640 alu.src[0].sel = V_SQ_ALU_SRC_0;
6641 alu.src[0].chan = i;
6642 alu.src[1].sel = V_SQ_ALU_SRC_0;
6643 alu.src[1].chan = i;
6644 }
6645
6646 alu.dst.sel = ctx->temp_reg;
6647 alu.dst.chan = i;
6648 alu.dst.write = 1;
6649
6650 if (i == 3)
6651 alu.last = 1;
6652 r = r600_bytecode_add_alu(ctx->bc, &alu);
6653 if (r)
6654 return r;
6655 }
6656
6657 for (i = 0; i < 4; i++) {
6658 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6659 alu.op = ALU_OP3_MULADD;
6660
6661 if (i < 3) {
6662 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
6663 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
6664 } else {
6665 alu.src[0].sel = V_SQ_ALU_SRC_0;
6666 alu.src[0].chan = i;
6667 alu.src[1].sel = V_SQ_ALU_SRC_0;
6668 alu.src[1].chan = i;
6669 }
6670
6671 alu.src[2].sel = ctx->temp_reg;
6672 alu.src[2].neg = 1;
6673 alu.src[2].chan = i;
6674
6675 if (use_temp)
6676 alu.dst.sel = ctx->temp_reg;
6677 else
6678 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6679 alu.dst.chan = i;
6680 alu.dst.write = 1;
6681 alu.is_op3 = 1;
6682 if (i == 3)
6683 alu.last = 1;
6684 r = r600_bytecode_add_alu(ctx->bc, &alu);
6685 if (r)
6686 return r;
6687 }
6688 if (use_temp)
6689 return tgsi_helper_copy(ctx, inst);
6690 return 0;
6691 }
6692
6693 static int tgsi_exp(struct r600_shader_ctx *ctx)
6694 {
6695 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6696 struct r600_bytecode_alu alu;
6697 int r;
6698 int i;
6699
6700 /* result.x = 2^floor(src); */
6701 if (inst->Dst[0].Register.WriteMask & 1) {
6702 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6703
6704 alu.op = ALU_OP1_FLOOR;
6705 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6706
6707 alu.dst.sel = ctx->temp_reg;
6708 alu.dst.chan = 0;
6709 alu.dst.write = 1;
6710 alu.last = 1;
6711 r = r600_bytecode_add_alu(ctx->bc, &alu);
6712 if (r)
6713 return r;
6714
6715 if (ctx->bc->chip_class == CAYMAN) {
6716 for (i = 0; i < 3; i++) {
6717 alu.op = ALU_OP1_EXP_IEEE;
6718 alu.src[0].sel = ctx->temp_reg;
6719 alu.src[0].chan = 0;
6720
6721 alu.dst.sel = ctx->temp_reg;
6722 alu.dst.chan = i;
6723 alu.dst.write = i == 0;
6724 alu.last = i == 2;
6725 r = r600_bytecode_add_alu(ctx->bc, &alu);
6726 if (r)
6727 return r;
6728 }
6729 } else {
6730 alu.op = ALU_OP1_EXP_IEEE;
6731 alu.src[0].sel = ctx->temp_reg;
6732 alu.src[0].chan = 0;
6733
6734 alu.dst.sel = ctx->temp_reg;
6735 alu.dst.chan = 0;
6736 alu.dst.write = 1;
6737 alu.last = 1;
6738 r = r600_bytecode_add_alu(ctx->bc, &alu);
6739 if (r)
6740 return r;
6741 }
6742 }
6743
6744 /* result.y = tmp - floor(tmp); */
6745 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
6746 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6747
6748 alu.op = ALU_OP1_FRACT;
6749 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6750
6751 alu.dst.sel = ctx->temp_reg;
6752 #if 0
6753 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6754 if (r)
6755 return r;
6756 #endif
6757 alu.dst.write = 1;
6758 alu.dst.chan = 1;
6759
6760 alu.last = 1;
6761
6762 r = r600_bytecode_add_alu(ctx->bc, &alu);
6763 if (r)
6764 return r;
6765 }
6766
6767 /* result.z = RoughApprox2ToX(tmp);*/
6768 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
6769 if (ctx->bc->chip_class == CAYMAN) {
6770 for (i = 0; i < 3; i++) {
6771 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6772 alu.op = ALU_OP1_EXP_IEEE;
6773 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6774
6775 alu.dst.sel = ctx->temp_reg;
6776 alu.dst.chan = i;
6777 if (i == 2) {
6778 alu.dst.write = 1;
6779 alu.last = 1;
6780 }
6781
6782 r = r600_bytecode_add_alu(ctx->bc, &alu);
6783 if (r)
6784 return r;
6785 }
6786 } else {
6787 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6788 alu.op = ALU_OP1_EXP_IEEE;
6789 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6790
6791 alu.dst.sel = ctx->temp_reg;
6792 alu.dst.write = 1;
6793 alu.dst.chan = 2;
6794
6795 alu.last = 1;
6796
6797 r = r600_bytecode_add_alu(ctx->bc, &alu);
6798 if (r)
6799 return r;
6800 }
6801 }
6802
6803 /* result.w = 1.0;*/
6804 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
6805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6806
6807 alu.op = ALU_OP1_MOV;
6808 alu.src[0].sel = V_SQ_ALU_SRC_1;
6809 alu.src[0].chan = 0;
6810
6811 alu.dst.sel = ctx->temp_reg;
6812 alu.dst.chan = 3;
6813 alu.dst.write = 1;
6814 alu.last = 1;
6815 r = r600_bytecode_add_alu(ctx->bc, &alu);
6816 if (r)
6817 return r;
6818 }
6819 return tgsi_helper_copy(ctx, inst);
6820 }
6821
6822 static int tgsi_log(struct r600_shader_ctx *ctx)
6823 {
6824 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6825 struct r600_bytecode_alu alu;
6826 int r;
6827 int i;
6828
6829 /* result.x = floor(log2(|src|)); */
6830 if (inst->Dst[0].Register.WriteMask & 1) {
6831 if (ctx->bc->chip_class == CAYMAN) {
6832 for (i = 0; i < 3; i++) {
6833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6834
6835 alu.op = ALU_OP1_LOG_IEEE;
6836 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6837 r600_bytecode_src_set_abs(&alu.src[0]);
6838
6839 alu.dst.sel = ctx->temp_reg;
6840 alu.dst.chan = i;
6841 if (i == 0)
6842 alu.dst.write = 1;
6843 if (i == 2)
6844 alu.last = 1;
6845 r = r600_bytecode_add_alu(ctx->bc, &alu);
6846 if (r)
6847 return r;
6848 }
6849
6850 } else {
6851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6852
6853 alu.op = ALU_OP1_LOG_IEEE;
6854 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6855 r600_bytecode_src_set_abs(&alu.src[0]);
6856
6857 alu.dst.sel = ctx->temp_reg;
6858 alu.dst.chan = 0;
6859 alu.dst.write = 1;
6860 alu.last = 1;
6861 r = r600_bytecode_add_alu(ctx->bc, &alu);
6862 if (r)
6863 return r;
6864 }
6865
6866 alu.op = ALU_OP1_FLOOR;
6867 alu.src[0].sel = ctx->temp_reg;
6868 alu.src[0].chan = 0;
6869
6870 alu.dst.sel = ctx->temp_reg;
6871 alu.dst.chan = 0;
6872 alu.dst.write = 1;
6873 alu.last = 1;
6874
6875 r = r600_bytecode_add_alu(ctx->bc, &alu);
6876 if (r)
6877 return r;
6878 }
6879
6880 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
6881 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
6882
6883 if (ctx->bc->chip_class == CAYMAN) {
6884 for (i = 0; i < 3; i++) {
6885 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6886
6887 alu.op = ALU_OP1_LOG_IEEE;
6888 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6889 r600_bytecode_src_set_abs(&alu.src[0]);
6890
6891 alu.dst.sel = ctx->temp_reg;
6892 alu.dst.chan = i;
6893 if (i == 1)
6894 alu.dst.write = 1;
6895 if (i == 2)
6896 alu.last = 1;
6897
6898 r = r600_bytecode_add_alu(ctx->bc, &alu);
6899 if (r)
6900 return r;
6901 }
6902 } else {
6903 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6904
6905 alu.op = ALU_OP1_LOG_IEEE;
6906 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6907 r600_bytecode_src_set_abs(&alu.src[0]);
6908
6909 alu.dst.sel = ctx->temp_reg;
6910 alu.dst.chan = 1;
6911 alu.dst.write = 1;
6912 alu.last = 1;
6913
6914 r = r600_bytecode_add_alu(ctx->bc, &alu);
6915 if (r)
6916 return r;
6917 }
6918
6919 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6920
6921 alu.op = ALU_OP1_FLOOR;
6922 alu.src[0].sel = ctx->temp_reg;
6923 alu.src[0].chan = 1;
6924
6925 alu.dst.sel = ctx->temp_reg;
6926 alu.dst.chan = 1;
6927 alu.dst.write = 1;
6928 alu.last = 1;
6929
6930 r = r600_bytecode_add_alu(ctx->bc, &alu);
6931 if (r)
6932 return r;
6933
6934 if (ctx->bc->chip_class == CAYMAN) {
6935 for (i = 0; i < 3; i++) {
6936 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6937 alu.op = ALU_OP1_EXP_IEEE;
6938 alu.src[0].sel = ctx->temp_reg;
6939 alu.src[0].chan = 1;
6940
6941 alu.dst.sel = ctx->temp_reg;
6942 alu.dst.chan = i;
6943 if (i == 1)
6944 alu.dst.write = 1;
6945 if (i == 2)
6946 alu.last = 1;
6947
6948 r = r600_bytecode_add_alu(ctx->bc, &alu);
6949 if (r)
6950 return r;
6951 }
6952 } else {
6953 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6954 alu.op = ALU_OP1_EXP_IEEE;
6955 alu.src[0].sel = ctx->temp_reg;
6956 alu.src[0].chan = 1;
6957
6958 alu.dst.sel = ctx->temp_reg;
6959 alu.dst.chan = 1;
6960 alu.dst.write = 1;
6961 alu.last = 1;
6962
6963 r = r600_bytecode_add_alu(ctx->bc, &alu);
6964 if (r)
6965 return r;
6966 }
6967
6968 if (ctx->bc->chip_class == CAYMAN) {
6969 for (i = 0; i < 3; i++) {
6970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6971 alu.op = ALU_OP1_RECIP_IEEE;
6972 alu.src[0].sel = ctx->temp_reg;
6973 alu.src[0].chan = 1;
6974
6975 alu.dst.sel = ctx->temp_reg;
6976 alu.dst.chan = i;
6977 if (i == 1)
6978 alu.dst.write = 1;
6979 if (i == 2)
6980 alu.last = 1;
6981
6982 r = r600_bytecode_add_alu(ctx->bc, &alu);
6983 if (r)
6984 return r;
6985 }
6986 } else {
6987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6988 alu.op = ALU_OP1_RECIP_IEEE;
6989 alu.src[0].sel = ctx->temp_reg;
6990 alu.src[0].chan = 1;
6991
6992 alu.dst.sel = ctx->temp_reg;
6993 alu.dst.chan = 1;
6994 alu.dst.write = 1;
6995 alu.last = 1;
6996
6997 r = r600_bytecode_add_alu(ctx->bc, &alu);
6998 if (r)
6999 return r;
7000 }
7001
7002 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7003
7004 alu.op = ALU_OP2_MUL;
7005
7006 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7007 r600_bytecode_src_set_abs(&alu.src[0]);
7008
7009 alu.src[1].sel = ctx->temp_reg;
7010 alu.src[1].chan = 1;
7011
7012 alu.dst.sel = ctx->temp_reg;
7013 alu.dst.chan = 1;
7014 alu.dst.write = 1;
7015 alu.last = 1;
7016
7017 r = r600_bytecode_add_alu(ctx->bc, &alu);
7018 if (r)
7019 return r;
7020 }
7021
7022 /* result.z = log2(|src|);*/
7023 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
7024 if (ctx->bc->chip_class == CAYMAN) {
7025 for (i = 0; i < 3; i++) {
7026 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7027
7028 alu.op = ALU_OP1_LOG_IEEE;
7029 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7030 r600_bytecode_src_set_abs(&alu.src[0]);
7031
7032 alu.dst.sel = ctx->temp_reg;
7033 if (i == 2)
7034 alu.dst.write = 1;
7035 alu.dst.chan = i;
7036 if (i == 2)
7037 alu.last = 1;
7038
7039 r = r600_bytecode_add_alu(ctx->bc, &alu);
7040 if (r)
7041 return r;
7042 }
7043 } else {
7044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7045
7046 alu.op = ALU_OP1_LOG_IEEE;
7047 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7048 r600_bytecode_src_set_abs(&alu.src[0]);
7049
7050 alu.dst.sel = ctx->temp_reg;
7051 alu.dst.write = 1;
7052 alu.dst.chan = 2;
7053 alu.last = 1;
7054
7055 r = r600_bytecode_add_alu(ctx->bc, &alu);
7056 if (r)
7057 return r;
7058 }
7059 }
7060
7061 /* result.w = 1.0; */
7062 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
7063 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7064
7065 alu.op = ALU_OP1_MOV;
7066 alu.src[0].sel = V_SQ_ALU_SRC_1;
7067 alu.src[0].chan = 0;
7068
7069 alu.dst.sel = ctx->temp_reg;
7070 alu.dst.chan = 3;
7071 alu.dst.write = 1;
7072 alu.last = 1;
7073
7074 r = r600_bytecode_add_alu(ctx->bc, &alu);
7075 if (r)
7076 return r;
7077 }
7078
7079 return tgsi_helper_copy(ctx, inst);
7080 }
7081
7082 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
7083 {
7084 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7085 struct r600_bytecode_alu alu;
7086 int r;
7087 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7088 unsigned reg = inst->Dst[0].Register.Index > 0 ? ctx->bc->index_reg[inst->Dst[0].Register.Index - 1] : ctx->bc->ar_reg;
7089
7090 assert(inst->Dst[0].Register.Index < 3);
7091 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7092
7093 switch (inst->Instruction.Opcode) {
7094 case TGSI_OPCODE_ARL:
7095 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
7096 break;
7097 case TGSI_OPCODE_ARR:
7098 alu.op = ALU_OP1_FLT_TO_INT;
7099 break;
7100 case TGSI_OPCODE_UARL:
7101 alu.op = ALU_OP1_MOV;
7102 break;
7103 default:
7104 assert(0);
7105 return -1;
7106 }
7107
7108 for (i = 0; i <= lasti; ++i) {
7109 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7110 continue;
7111 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7112 alu.last = i == lasti;
7113 alu.dst.sel = reg;
7114 alu.dst.chan = i;
7115 alu.dst.write = 1;
7116 r = r600_bytecode_add_alu(ctx->bc, &alu);
7117 if (r)
7118 return r;
7119 }
7120
7121 if (inst->Dst[0].Register.Index > 0)
7122 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
7123 else
7124 ctx->bc->ar_loaded = 0;
7125
7126 return 0;
7127 }
7128 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
7129 {
7130 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7131 struct r600_bytecode_alu alu;
7132 int r;
7133 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7134
7135 switch (inst->Instruction.Opcode) {
7136 case TGSI_OPCODE_ARL:
7137 memset(&alu, 0, sizeof(alu));
7138 alu.op = ALU_OP1_FLOOR;
7139 alu.dst.sel = ctx->bc->ar_reg;
7140 alu.dst.write = 1;
7141 for (i = 0; i <= lasti; ++i) {
7142 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7143 alu.dst.chan = i;
7144 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7145 alu.last = i == lasti;
7146 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7147 return r;
7148 }
7149 }
7150
7151 memset(&alu, 0, sizeof(alu));
7152 alu.op = ALU_OP1_FLT_TO_INT;
7153 alu.src[0].sel = ctx->bc->ar_reg;
7154 alu.dst.sel = ctx->bc->ar_reg;
7155 alu.dst.write = 1;
7156 /* FLT_TO_INT is trans-only on r600/r700 */
7157 alu.last = TRUE;
7158 for (i = 0; i <= lasti; ++i) {
7159 alu.dst.chan = i;
7160 alu.src[0].chan = i;
7161 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7162 return r;
7163 }
7164 break;
7165 case TGSI_OPCODE_ARR:
7166 memset(&alu, 0, sizeof(alu));
7167 alu.op = ALU_OP1_FLT_TO_INT;
7168 alu.dst.sel = ctx->bc->ar_reg;
7169 alu.dst.write = 1;
7170 /* FLT_TO_INT is trans-only on r600/r700 */
7171 alu.last = TRUE;
7172 for (i = 0; i <= lasti; ++i) {
7173 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7174 alu.dst.chan = i;
7175 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7176 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7177 return r;
7178 }
7179 }
7180 break;
7181 case TGSI_OPCODE_UARL:
7182 memset(&alu, 0, sizeof(alu));
7183 alu.op = ALU_OP1_MOV;
7184 alu.dst.sel = ctx->bc->ar_reg;
7185 alu.dst.write = 1;
7186 for (i = 0; i <= lasti; ++i) {
7187 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7188 alu.dst.chan = i;
7189 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7190 alu.last = i == lasti;
7191 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7192 return r;
7193 }
7194 }
7195 break;
7196 default:
7197 assert(0);
7198 return -1;
7199 }
7200
7201 ctx->bc->ar_loaded = 0;
7202 return 0;
7203 }
7204
7205 static int tgsi_opdst(struct r600_shader_ctx *ctx)
7206 {
7207 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7208 struct r600_bytecode_alu alu;
7209 int i, r = 0;
7210
7211 for (i = 0; i < 4; i++) {
7212 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7213
7214 alu.op = ALU_OP2_MUL;
7215 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7216
7217 if (i == 0 || i == 3) {
7218 alu.src[0].sel = V_SQ_ALU_SRC_1;
7219 } else {
7220 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7221 }
7222
7223 if (i == 0 || i == 2) {
7224 alu.src[1].sel = V_SQ_ALU_SRC_1;
7225 } else {
7226 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
7227 }
7228 if (i == 3)
7229 alu.last = 1;
7230 r = r600_bytecode_add_alu(ctx->bc, &alu);
7231 if (r)
7232 return r;
7233 }
7234 return 0;
7235 }
7236
7237 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
7238 {
7239 struct r600_bytecode_alu alu;
7240 int r;
7241
7242 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7243 alu.op = opcode;
7244 alu.execute_mask = 1;
7245 alu.update_pred = 1;
7246
7247 alu.dst.sel = ctx->temp_reg;
7248 alu.dst.write = 1;
7249 alu.dst.chan = 0;
7250
7251 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7252 alu.src[1].sel = V_SQ_ALU_SRC_0;
7253 alu.src[1].chan = 0;
7254
7255 alu.last = 1;
7256
7257 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
7258 if (r)
7259 return r;
7260 return 0;
7261 }
7262
7263 static int pops(struct r600_shader_ctx *ctx, int pops)
7264 {
7265 unsigned force_pop = ctx->bc->force_add_cf;
7266
7267 if (!force_pop) {
7268 int alu_pop = 3;
7269 if (ctx->bc->cf_last) {
7270 if (ctx->bc->cf_last->op == CF_OP_ALU)
7271 alu_pop = 0;
7272 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
7273 alu_pop = 1;
7274 }
7275 alu_pop += pops;
7276 if (alu_pop == 1) {
7277 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
7278 ctx->bc->force_add_cf = 1;
7279 } else if (alu_pop == 2) {
7280 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
7281 ctx->bc->force_add_cf = 1;
7282 } else {
7283 force_pop = 1;
7284 }
7285 }
7286
7287 if (force_pop) {
7288 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
7289 ctx->bc->cf_last->pop_count = pops;
7290 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7291 }
7292
7293 return 0;
7294 }
7295
7296 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
7297 unsigned reason)
7298 {
7299 struct r600_stack_info *stack = &ctx->bc->stack;
7300 unsigned elements, entries;
7301
7302 unsigned entry_size = stack->entry_size;
7303
7304 elements = (stack->loop + stack->push_wqm ) * entry_size;
7305 elements += stack->push;
7306
7307 switch (ctx->bc->chip_class) {
7308 case R600:
7309 case R700:
7310 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
7311 * the stack must be reserved to hold the current active/continue
7312 * masks */
7313 if (reason == FC_PUSH_VPM) {
7314 elements += 2;
7315 }
7316 break;
7317
7318 case CAYMAN:
7319 /* r9xx: any stack operation on empty stack consumes 2 additional
7320 * elements */
7321 elements += 2;
7322
7323 /* fallthrough */
7324 /* FIXME: do the two elements added above cover the cases for the
7325 * r8xx+ below? */
7326
7327 case EVERGREEN:
7328 /* r8xx+: 2 extra elements are not always required, but one extra
7329 * element must be added for each of the following cases:
7330 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
7331 * stack usage.
7332 * (Currently we don't use ALU_ELSE_AFTER.)
7333 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
7334 * PUSH instruction executed.
7335 *
7336 * NOTE: it seems we also need to reserve additional element in some
7337 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
7338 * then STACK_SIZE should be 2 instead of 1 */
7339 if (reason == FC_PUSH_VPM) {
7340 elements += 1;
7341 }
7342 break;
7343
7344 default:
7345 assert(0);
7346 break;
7347 }
7348
7349 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
7350 * for all chips, so we use 4 in the final formula, not the real entry_size
7351 * for the chip */
7352 entry_size = 4;
7353
7354 entries = (elements + (entry_size - 1)) / entry_size;
7355
7356 if (entries > stack->max_entries)
7357 stack->max_entries = entries;
7358 }
7359
7360 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
7361 {
7362 switch(reason) {
7363 case FC_PUSH_VPM:
7364 --ctx->bc->stack.push;
7365 assert(ctx->bc->stack.push >= 0);
7366 break;
7367 case FC_PUSH_WQM:
7368 --ctx->bc->stack.push_wqm;
7369 assert(ctx->bc->stack.push_wqm >= 0);
7370 break;
7371 case FC_LOOP:
7372 --ctx->bc->stack.loop;
7373 assert(ctx->bc->stack.loop >= 0);
7374 break;
7375 default:
7376 assert(0);
7377 break;
7378 }
7379 }
7380
7381 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
7382 {
7383 switch (reason) {
7384 case FC_PUSH_VPM:
7385 ++ctx->bc->stack.push;
7386 break;
7387 case FC_PUSH_WQM:
7388 ++ctx->bc->stack.push_wqm;
7389 case FC_LOOP:
7390 ++ctx->bc->stack.loop;
7391 break;
7392 default:
7393 assert(0);
7394 }
7395
7396 callstack_update_max_depth(ctx, reason);
7397 }
7398
7399 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
7400 {
7401 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
7402
7403 sp->mid = realloc((void *)sp->mid,
7404 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
7405 sp->mid[sp->num_mid] = ctx->bc->cf_last;
7406 sp->num_mid++;
7407 }
7408
7409 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
7410 {
7411 ctx->bc->fc_sp++;
7412 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
7413 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
7414 }
7415
7416 static void fc_poplevel(struct r600_shader_ctx *ctx)
7417 {
7418 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
7419 free(sp->mid);
7420 sp->mid = NULL;
7421 sp->num_mid = 0;
7422 sp->start = NULL;
7423 sp->type = 0;
7424 ctx->bc->fc_sp--;
7425 }
7426
7427 #if 0
7428 static int emit_return(struct r600_shader_ctx *ctx)
7429 {
7430 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
7431 return 0;
7432 }
7433
7434 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
7435 {
7436
7437 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
7438 ctx->bc->cf_last->pop_count = pops;
7439 /* XXX work out offset */
7440 return 0;
7441 }
7442
7443 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
7444 {
7445 return 0;
7446 }
7447
7448 static void emit_testflag(struct r600_shader_ctx *ctx)
7449 {
7450
7451 }
7452
7453 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
7454 {
7455 emit_testflag(ctx);
7456 emit_jump_to_offset(ctx, 1, 4);
7457 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
7458 pops(ctx, ifidx + 1);
7459 emit_return(ctx);
7460 }
7461
7462 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
7463 {
7464 emit_testflag(ctx);
7465
7466 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7467 ctx->bc->cf_last->pop_count = 1;
7468
7469 fc_set_mid(ctx, fc_sp);
7470
7471 pops(ctx, 1);
7472 }
7473 #endif
7474
7475 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
7476 {
7477 int alu_type = CF_OP_ALU_PUSH_BEFORE;
7478
7479 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
7480 * LOOP_STARTxxx for nested loops may put the branch stack into a state
7481 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
7482 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
7483 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
7484 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
7485 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7486 alu_type = CF_OP_ALU;
7487 }
7488
7489 emit_logic_pred(ctx, opcode, alu_type);
7490
7491 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
7492
7493 fc_pushlevel(ctx, FC_IF);
7494
7495 callstack_push(ctx, FC_PUSH_VPM);
7496 return 0;
7497 }
7498
7499 static int tgsi_if(struct r600_shader_ctx *ctx)
7500 {
7501 return emit_if(ctx, ALU_OP2_PRED_SETNE);
7502 }
7503
7504 static int tgsi_uif(struct r600_shader_ctx *ctx)
7505 {
7506 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
7507 }
7508
7509 static int tgsi_else(struct r600_shader_ctx *ctx)
7510 {
7511 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
7512 ctx->bc->cf_last->pop_count = 1;
7513
7514 fc_set_mid(ctx, ctx->bc->fc_sp);
7515 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
7516 return 0;
7517 }
7518
7519 static int tgsi_endif(struct r600_shader_ctx *ctx)
7520 {
7521 pops(ctx, 1);
7522 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
7523 R600_ERR("if/endif unbalanced in shader\n");
7524 return -1;
7525 }
7526
7527 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
7528 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7529 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
7530 } else {
7531 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
7532 }
7533 fc_poplevel(ctx);
7534
7535 callstack_pop(ctx, FC_PUSH_VPM);
7536 return 0;
7537 }
7538
7539 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
7540 {
7541 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
7542 * limited to 4096 iterations, like the other LOOP_* instructions. */
7543 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
7544
7545 fc_pushlevel(ctx, FC_LOOP);
7546
7547 /* check stack depth */
7548 callstack_push(ctx, FC_LOOP);
7549 return 0;
7550 }
7551
7552 static int tgsi_endloop(struct r600_shader_ctx *ctx)
7553 {
7554 int i;
7555
7556 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
7557
7558 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
7559 R600_ERR("loop/endloop in shader code are not paired.\n");
7560 return -EINVAL;
7561 }
7562
7563 /* fixup loop pointers - from r600isa
7564 LOOP END points to CF after LOOP START,
7565 LOOP START point to CF after LOOP END
7566 BRK/CONT point to LOOP END CF
7567 */
7568 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
7569
7570 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7571
7572 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
7573 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
7574 }
7575 /* XXX add LOOPRET support */
7576 fc_poplevel(ctx);
7577 callstack_pop(ctx, FC_LOOP);
7578 return 0;
7579 }
7580
7581 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
7582 {
7583 int r;
7584 unsigned int fscp;
7585
7586 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7587 {
7588 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7589 break;
7590 }
7591 if (fscp == 0) {
7592 R600_ERR("BREAKC not inside loop/endloop pair\n");
7593 return -EINVAL;
7594 }
7595
7596 if (ctx->bc->chip_class == EVERGREEN &&
7597 ctx->bc->family != CHIP_CYPRESS &&
7598 ctx->bc->family != CHIP_JUNIPER) {
7599 /* HW bug: ALU_BREAK does not save the active mask correctly */
7600 r = tgsi_uif(ctx);
7601 if (r)
7602 return r;
7603
7604 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
7605 if (r)
7606 return r;
7607 fc_set_mid(ctx, fscp);
7608
7609 return tgsi_endif(ctx);
7610 } else {
7611 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
7612 if (r)
7613 return r;
7614 fc_set_mid(ctx, fscp);
7615 }
7616
7617 return 0;
7618 }
7619
7620 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
7621 {
7622 unsigned int fscp;
7623
7624 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7625 {
7626 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7627 break;
7628 }
7629
7630 if (fscp == 0) {
7631 R600_ERR("Break not inside loop/endloop pair\n");
7632 return -EINVAL;
7633 }
7634
7635 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7636
7637 fc_set_mid(ctx, fscp);
7638
7639 return 0;
7640 }
7641
7642 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
7643 {
7644 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7645 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
7646 int r;
7647
7648 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
7649 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
7650
7651 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7652 if (!r)
7653 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
7654 return r;
7655 }
7656
7657 static int tgsi_umad(struct r600_shader_ctx *ctx)
7658 {
7659 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7660 struct r600_bytecode_alu alu;
7661 int i, j, k, r;
7662 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7663
7664 /* src0 * src1 */
7665 for (i = 0; i < lasti + 1; i++) {
7666 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7667 continue;
7668
7669 if (ctx->bc->chip_class == CAYMAN) {
7670 for (j = 0 ; j < 4; j++) {
7671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7672
7673 alu.op = ALU_OP2_MULLO_UINT;
7674 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
7675 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
7676 }
7677 alu.dst.chan = j;
7678 alu.dst.sel = ctx->temp_reg;
7679 alu.dst.write = (j == i);
7680 if (j == 3)
7681 alu.last = 1;
7682 r = r600_bytecode_add_alu(ctx->bc, &alu);
7683 if (r)
7684 return r;
7685 }
7686 } else {
7687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7688
7689 alu.dst.chan = i;
7690 alu.dst.sel = ctx->temp_reg;
7691 alu.dst.write = 1;
7692
7693 alu.op = ALU_OP2_MULLO_UINT;
7694 for (j = 0; j < 2; j++) {
7695 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
7696 }
7697
7698 alu.last = 1;
7699 r = r600_bytecode_add_alu(ctx->bc, &alu);
7700 if (r)
7701 return r;
7702 }
7703 }
7704
7705
7706 for (i = 0; i < lasti + 1; i++) {
7707 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7708 continue;
7709
7710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7711 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7712
7713 alu.op = ALU_OP2_ADD_INT;
7714
7715 alu.src[0].sel = ctx->temp_reg;
7716 alu.src[0].chan = i;
7717
7718 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7719 if (i == lasti) {
7720 alu.last = 1;
7721 }
7722 r = r600_bytecode_add_alu(ctx->bc, &alu);
7723 if (r)
7724 return r;
7725 }
7726 return 0;
7727 }
7728
7729 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
7730 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
7731 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
7732 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
7733
7734 /* XXX:
7735 * For state trackers other than OpenGL, we'll want to use
7736 * _RECIP_IEEE instead.
7737 */
7738 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
7739
7740 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
7741 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
7742 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
7743 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
7744 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
7745 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
7746 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
7747 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
7748 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
7749 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
7750 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
7751 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
7752 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
7753 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
7754 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
7755 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
7756 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
7757 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
7758 [22] = { ALU_OP0_NOP, tgsi_unsupported},
7759 [23] = { ALU_OP0_NOP, tgsi_unsupported},
7760 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
7761 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
7762 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
7763 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
7764 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
7765 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
7766 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
7767 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
7768 [32] = { ALU_OP0_NOP, tgsi_unsupported},
7769 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
7770 [34] = { ALU_OP0_NOP, tgsi_unsupported},
7771 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
7772 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
7773 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7774 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7775 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
7776 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
7777 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
7778 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
7779 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7780 [44] = { ALU_OP0_NOP, tgsi_unsupported},
7781 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
7782 [46] = { ALU_OP0_NOP, tgsi_unsupported},
7783 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
7784 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
7785 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
7786 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
7787 [51] = { ALU_OP0_NOP, tgsi_unsupported},
7788 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
7789 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
7790 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
7791 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
7792 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
7793 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
7794 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7795 [59] = { ALU_OP0_NOP, tgsi_unsupported},
7796 [60] = { ALU_OP0_NOP, tgsi_unsupported},
7797 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
7798 [62] = { ALU_OP0_NOP, tgsi_unsupported},
7799 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
7800 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
7801 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
7802 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
7803 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
7804 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7805 [69] = { ALU_OP0_NOP, tgsi_unsupported},
7806 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
7807 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
7808 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7809 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
7810 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
7811 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
7812 [76] = { ALU_OP0_NOP, tgsi_unsupported},
7813 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
7814 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
7815 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
7816 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
7817 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
7818 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
7819 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
7820 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
7821 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
7822 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
7823 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
7824 [88] = { ALU_OP0_NOP, tgsi_unsupported},
7825 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
7826 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
7827 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
7828 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
7829 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
7830 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
7831 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7832 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
7833 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
7834 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
7835 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
7836 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7837 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
7838 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
7839 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7840 [104] = { ALU_OP0_NOP, tgsi_unsupported},
7841 [105] = { ALU_OP0_NOP, tgsi_unsupported},
7842 [106] = { ALU_OP0_NOP, tgsi_unsupported},
7843 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
7844 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
7845 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
7846 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
7847 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
7848 [112] = { ALU_OP0_NOP, tgsi_unsupported},
7849 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
7850 [114] = { ALU_OP0_NOP, tgsi_unsupported},
7851 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
7852 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
7853 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
7854 [118] = { ALU_OP0_NOP, tgsi_unsupported},
7855 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
7856 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
7857 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
7858 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
7859 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
7860 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
7861 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
7862 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
7863 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
7864 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
7865 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
7866 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
7867 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
7868 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
7869 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
7870 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
7871 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
7872 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
7873 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
7874 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
7875 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
7876 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
7877 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7878 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
7879 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
7880 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
7881 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
7882 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
7883 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
7884 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
7885 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
7886 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
7887 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
7888 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
7889 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
7890 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
7891 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
7892 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
7893 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
7894 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
7895 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
7896 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
7897 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
7898 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
7899 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7900 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7901 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
7902 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
7903 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
7904 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
7905 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
7906 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
7907 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
7908 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
7909 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
7910 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
7911 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
7912 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
7913 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
7914 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
7915 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
7916 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
7917 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
7918 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
7919 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
7920 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
7921 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
7922 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
7923 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
7924 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
7925 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
7926 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
7927 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
7928 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
7929 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
7930 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
7931 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
7932 };
7933
7934 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
7935 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
7936 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
7937 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
7938 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
7939 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
7940 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
7941 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
7942 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
7943 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
7944 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
7945 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
7946 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
7947 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
7948 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
7949 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
7950 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
7951 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
7952 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
7953 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
7954 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
7955 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
7956 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
7957 [22] = { ALU_OP0_NOP, tgsi_unsupported},
7958 [23] = { ALU_OP0_NOP, tgsi_unsupported},
7959 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
7960 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
7961 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
7962 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
7963 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
7964 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
7965 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
7966 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
7967 [32] = { ALU_OP0_NOP, tgsi_unsupported},
7968 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
7969 [34] = { ALU_OP0_NOP, tgsi_unsupported},
7970 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
7971 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
7972 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7973 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7974 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
7975 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
7976 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
7977 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
7978 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7979 [44] = { ALU_OP0_NOP, tgsi_unsupported},
7980 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
7981 [46] = { ALU_OP0_NOP, tgsi_unsupported},
7982 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
7983 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
7984 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
7985 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
7986 [51] = { ALU_OP0_NOP, tgsi_unsupported},
7987 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
7988 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
7989 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
7990 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
7991 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
7992 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
7993 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7994 [59] = { ALU_OP0_NOP, tgsi_unsupported},
7995 [60] = { ALU_OP0_NOP, tgsi_unsupported},
7996 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
7997 [62] = { ALU_OP0_NOP, tgsi_unsupported},
7998 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
7999 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8000 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8001 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8002 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8003 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8004 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8005 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8006 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8007 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8008 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8009 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8010 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8011 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8012 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8013 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8014 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8015 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8016 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8017 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8018 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8019 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
8020 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8021 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8022 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8023 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8024 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8025 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8026 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8027 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8028 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8029 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8030 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8031 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8032 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8033 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8034 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8035 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8036 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8037 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8038 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8039 [104] = { ALU_OP0_NOP, tgsi_unsupported},
8040 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8041 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8042 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8043 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8044 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8045 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8046 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8047 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8048 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8049 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8050 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8051 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8052 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8053 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8054 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
8055 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8056 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8057 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8058 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8059 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8060 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8061 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8062 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
8063 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
8064 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8065 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8066 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8067 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8068 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8069 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8070 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
8071 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8072 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8073 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8074 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8075 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8076 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8077 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8078 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8079 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8080 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8081 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8082 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8083 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8084 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8085 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8086 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8087 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8088 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8089 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8090 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8091 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8092 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8093 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8094 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8095 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8096 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8097 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8098 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8099 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8100 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8101 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8102 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8103 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8104 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8105 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8106 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8107 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8108 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8109 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8110 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8111 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8112 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8113 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8114 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8115 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
8116 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
8117 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8118 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8119 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8120 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8121 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8122 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8123 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8124 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8125 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8126 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8127 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8128 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8129 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8130 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8131 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8132 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8133 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8134 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8135 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8136 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8137 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8138 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8139 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8140 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8141 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8142 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8143 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8144 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8145 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8146 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8147 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8148 [TGSI_OPCODE_D2I] = { ALU_OP0_NOP, tgsi_unsupported},
8149 [TGSI_OPCODE_I2D] = { ALU_OP0_NOP, tgsi_unsupported},
8150 [TGSI_OPCODE_D2U] = { ALU_OP0_NOP, tgsi_unsupported},
8151 [TGSI_OPCODE_U2D] = { ALU_OP0_NOP, tgsi_unsupported},
8152 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8153 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8154 };
8155
8156 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
8157 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
8158 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8159 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8160 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
8161 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
8162 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8163 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8164 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8165 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8166 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8167 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8168 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8169 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8170 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8171 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8172 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8173 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8174 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8175 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8176 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8177 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
8178 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8179 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8180 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8181 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8182 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8183 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8184 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8185 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
8186 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
8187 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
8188 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8189 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8190 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8191 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8192 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8193 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
8194 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8195 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8196 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8197 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8198 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8199 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8200 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8201 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8202 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8203 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8204 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8205 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
8206 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8207 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8208 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8209 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8210 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8211 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8212 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8213 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8214 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8215 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8216 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8217 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8218 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
8219 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8220 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8221 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8222 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8223 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8224 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8225 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8226 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8227 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8228 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8229 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8230 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8231 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8232 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8233 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8234 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8235 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8236 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8237 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8238 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8239 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8240 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8241 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
8242 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8243 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8244 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8245 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8246 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8247 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8248 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8249 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8250 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8251 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8252 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8253 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8254 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8255 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8256 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8257 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8258 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8259 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8260 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8261 [104] = { ALU_OP0_NOP, tgsi_unsupported},
8262 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8263 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8264 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8265 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8266 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8267 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8268 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8269 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8270 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8271 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8272 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8273 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8274 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8275 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8276 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
8277 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8278 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8279 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8280 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8281 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8282 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8283 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8284 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
8285 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
8286 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8287 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8288 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8289 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8290 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8291 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8292 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
8293 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8294 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8295 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8296 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8297 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8298 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8299 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8300 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8301 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8302 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8303 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8304 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8305 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8306 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8307 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8308 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8309 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8310 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8311 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8312 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8313 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8314 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8315 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8316 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8317 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8318 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8319 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8320 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8321 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8322 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8323 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8324 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8325 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8326 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8327 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8328 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8329 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8330 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8331 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8332 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8333 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8334 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8335 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8336 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8337 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
8338 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
8339 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8340 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8341 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8342 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8343 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8344 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8345 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8346 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8347 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8348 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8349 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8350 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8351 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8352 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8353 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8354 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8355 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8356 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8357 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8358 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8359 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8360 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8361 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8362 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8363 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8364 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8365 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8366 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8367 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8368 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8369 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8370 [TGSI_OPCODE_D2I] = { ALU_OP0_NOP, tgsi_unsupported},
8371 [TGSI_OPCODE_I2D] = { ALU_OP0_NOP, tgsi_unsupported},
8372 [TGSI_OPCODE_D2U] = { ALU_OP0_NOP, tgsi_unsupported},
8373 [TGSI_OPCODE_U2D] = { ALU_OP0_NOP, tgsi_unsupported},
8374 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8375 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8376 };