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Merge branch 'draw-instanced'
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
49 */
50 for (i = 0; i < 10; i++) {
51 spi_vs_out_id[i] = 0;
52 }
53 for (i = 0; i < 32; i++) {
54 tmp = i << ((i & 3) * 8);
55 spi_vs_out_id[i / 4] |= tmp;
56 }
57 for (i = 0; i < 10; i++) {
58 r600_pipe_state_add_reg(rstate,
59 R_028614_SPI_VS_OUT_ID_0 + i * 4,
60 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
61 }
62
63 r600_pipe_state_add_reg(rstate,
64 R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
66 0xFFFFFFFF, NULL);
67 r600_pipe_state_add_reg(rstate,
68 R_028868_SQ_PGM_RESOURCES_VS,
69 S_028868_NUM_GPRS(rshader->bc.ngpr) |
70 S_028868_STACK_SIZE(rshader->bc.nstack),
71 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_028858_SQ_PGM_START_VS,
77 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
78
79 r600_pipe_state_add_reg(rstate,
80 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
81 0xFFFFFFFF, NULL);
82
83 }
84
85 int r600_find_vs_semantic_index(struct r600_shader *vs,
86 struct r600_shader *ps, int id)
87 {
88 struct r600_shader_io *input = &ps->input[id];
89
90 for (int i = 0; i < vs->noutput; i++) {
91 if (input->name == vs->output[i].name &&
92 input->sid == vs->output[i].sid) {
93 return i - 1;
94 }
95 }
96 return 0;
97 }
98
99 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
100 {
101 struct r600_pipe_state *rstate = &shader->rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
104 int pos_index = -1, face_index = -1;
105
106 rstate->nregs = 0;
107
108 for (i = 0; i < rshader->ninput; i++) {
109 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
110 pos_index = i;
111 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
112 face_index = i;
113 }
114
115 for (i = 0; i < rshader->noutput; i++) {
116 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
117 r600_pipe_state_add_reg(rstate,
118 R_02880C_DB_SHADER_CONTROL,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL);
121 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
122 r600_pipe_state_add_reg(rstate,
123 R_02880C_DB_SHADER_CONTROL,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
126 }
127
128 exports_ps = 0;
129 num_cout = 0;
130 for (i = 0; i < rshader->noutput; i++) {
131 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
132 exports_ps |= 1;
133 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
134 num_cout++;
135 }
136 }
137 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
138 if (!exports_ps) {
139 /* always at least export 1 component per pixel */
140 exports_ps = 2;
141 }
142
143 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
145 spi_input_z = 0;
146 if (pos_index != -1) {
147 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
149 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
151 spi_input_z |= 1;
152 }
153
154 spi_ps_in_control_1 = 0;
155 if (face_index != -1) {
156 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
158 }
159
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->uses_kill) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate,
181 R_02880C_DB_SHADER_CONTROL,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL);
184 }
185 r600_pipe_state_add_reg(rstate,
186 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
187 0xFFFFFFFF, NULL);
188 }
189
190 int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
191 {
192 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
193 struct r600_shader *rshader = &shader->shader;
194 void *ptr;
195
196 /* copy new shader */
197 if (shader->bo == NULL) {
198 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
199 if (shader->bo == NULL) {
200 return -ENOMEM;
201 }
202 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
203 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
204 r600_bo_unmap(rctx->radeon, shader->bo);
205 }
206 /* build state */
207 switch (rshader->processor_type) {
208 case TGSI_PROCESSOR_VERTEX:
209 if (rshader->family >= CHIP_CEDAR) {
210 evergreen_pipe_shader_vs(ctx, shader);
211 } else {
212 r600_pipe_shader_vs(ctx, shader);
213 }
214 break;
215 case TGSI_PROCESSOR_FRAGMENT:
216 if (rshader->family >= CHIP_CEDAR) {
217 evergreen_pipe_shader_ps(ctx, shader);
218 } else {
219 r600_pipe_shader_ps(ctx, shader);
220 }
221 break;
222 default:
223 return -EINVAL;
224 }
225 return 0;
226 }
227
228 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader, u32 **literals);
229 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
230 {
231 static int dump_shaders = -1;
232 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
233 u32 *literals;
234 int r;
235
236 /* Would like some magic "get_bool_option_once" routine.
237 */
238 if (dump_shaders == -1)
239 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
240
241 if (dump_shaders) {
242 fprintf(stderr, "--------------------------------------------------------------\n");
243 tgsi_dump(tokens, 0);
244 }
245 shader->shader.family = r600_get_family(rctx->radeon);
246 r = r600_shader_from_tgsi(tokens, &shader->shader, &literals);
247 if (r) {
248 R600_ERR("translation from TGSI failed !\n");
249 return r;
250 }
251 r = r600_bc_build(&shader->shader.bc);
252 free(literals);
253 if (r) {
254 R600_ERR("building bytecode failed !\n");
255 return r;
256 }
257 if (dump_shaders) {
258 r600_bc_dump(&shader->shader.bc);
259 fprintf(stderr, "______________________________________________________________\n");
260 }
261 return r600_pipe_shader(ctx, shader);
262 }
263
264 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
265 {
266 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
267
268 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
269 r600_bc_clear(&shader->shader.bc);
270 }
271
272 /*
273 * tgsi -> r600 shader
274 */
275 struct r600_shader_tgsi_instruction;
276
277 struct r600_shader_ctx {
278 struct tgsi_shader_info info;
279 struct tgsi_parse_context parse;
280 const struct tgsi_token *tokens;
281 unsigned type;
282 unsigned file_offset[TGSI_FILE_COUNT];
283 unsigned temp_reg;
284 struct r600_shader_tgsi_instruction *inst_info;
285 struct r600_bc *bc;
286 struct r600_shader *shader;
287 u32 *literals;
288 u32 nliterals;
289 u32 max_driver_temp_used;
290 /* needed for evergreen interpolation */
291 boolean input_centroid;
292 boolean input_linear;
293 boolean input_perspective;
294 int num_interp_gpr;
295 };
296
297 struct r600_shader_tgsi_instruction {
298 unsigned tgsi_opcode;
299 unsigned is_op3;
300 unsigned r600_opcode;
301 int (*process)(struct r600_shader_ctx *ctx);
302 };
303
304 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
305 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
306
307 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
308 {
309 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
310 int j;
311
312 if (i->Instruction.NumDstRegs > 1) {
313 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
314 return -EINVAL;
315 }
316 if (i->Instruction.Predicate) {
317 R600_ERR("predicate unsupported\n");
318 return -EINVAL;
319 }
320 #if 0
321 if (i->Instruction.Label) {
322 R600_ERR("label unsupported\n");
323 return -EINVAL;
324 }
325 #endif
326 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
327 if (i->Src[j].Register.Dimension) {
328 R600_ERR("unsupported src %d (dimension %d)\n", j,
329 i->Src[j].Register.Dimension);
330 return -EINVAL;
331 }
332 }
333 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
334 if (i->Dst[j].Register.Dimension) {
335 R600_ERR("unsupported dst (dimension)\n");
336 return -EINVAL;
337 }
338 }
339 return 0;
340 }
341
342 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
343 {
344 int i, r;
345 struct r600_bc_alu alu;
346 int gpr = 0, base_chan = 0;
347 int ij_index = 0;
348
349 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
350 ij_index = 0;
351 if (ctx->shader->input[input].centroid)
352 ij_index++;
353 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
354 ij_index = 0;
355 /* if we have perspective add one */
356 if (ctx->input_perspective) {
357 ij_index++;
358 /* if we have perspective centroid */
359 if (ctx->input_centroid)
360 ij_index++;
361 }
362 if (ctx->shader->input[input].centroid)
363 ij_index++;
364 }
365
366 /* work out gpr and base_chan from index */
367 gpr = ij_index / 2;
368 base_chan = (2 * (ij_index % 2)) + 1;
369
370 for (i = 0; i < 8; i++) {
371 memset(&alu, 0, sizeof(struct r600_bc_alu));
372
373 if (i < 4)
374 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
375 else
376 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
377
378 if ((i > 1) && (i < 6)) {
379 alu.dst.sel = ctx->shader->input[input].gpr;
380 alu.dst.write = 1;
381 }
382
383 alu.dst.chan = i % 4;
384
385 alu.src[0].sel = gpr;
386 alu.src[0].chan = (base_chan - (i % 2));
387
388 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
389
390 alu.bank_swizzle_force = SQ_ALU_VEC_210;
391 if ((i % 4) == 3)
392 alu.last = 1;
393 r = r600_bc_add_alu(ctx->bc, &alu);
394 if (r)
395 return r;
396 }
397 return 0;
398 }
399
400
401 static int tgsi_declaration(struct r600_shader_ctx *ctx)
402 {
403 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
404 unsigned i;
405
406 switch (d->Declaration.File) {
407 case TGSI_FILE_INPUT:
408 i = ctx->shader->ninput++;
409 ctx->shader->input[i].name = d->Semantic.Name;
410 ctx->shader->input[i].sid = d->Semantic.Index;
411 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
412 ctx->shader->input[i].centroid = d->Declaration.Centroid;
413 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
414 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
415 /* turn input into interpolate on EG */
416 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
417 if (ctx->shader->input[i].interpolate > 0) {
418 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
419 evergreen_interp_alu(ctx, i);
420 }
421 }
422 }
423 break;
424 case TGSI_FILE_OUTPUT:
425 i = ctx->shader->noutput++;
426 ctx->shader->output[i].name = d->Semantic.Name;
427 ctx->shader->output[i].sid = d->Semantic.Index;
428 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
429 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
430 break;
431 case TGSI_FILE_CONSTANT:
432 case TGSI_FILE_TEMPORARY:
433 case TGSI_FILE_SAMPLER:
434 case TGSI_FILE_ADDRESS:
435 break;
436 default:
437 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
438 return -EINVAL;
439 }
440 return 0;
441 }
442
443 static int r600_get_temp(struct r600_shader_ctx *ctx)
444 {
445 return ctx->temp_reg + ctx->max_driver_temp_used++;
446 }
447
448 /*
449 * for evergreen we need to scan the shader to find the number of GPRs we need to
450 * reserve for interpolation.
451 *
452 * we need to know if we are going to emit
453 * any centroid inputs
454 * if perspective and linear are required
455 */
456 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
457 {
458 int i;
459 int num_baryc;
460
461 ctx->input_linear = FALSE;
462 ctx->input_perspective = FALSE;
463 ctx->input_centroid = FALSE;
464 ctx->num_interp_gpr = 1;
465
466 /* any centroid inputs */
467 for (i = 0; i < ctx->info.num_inputs; i++) {
468 /* skip position/face */
469 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
470 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
471 continue;
472 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
473 ctx->input_linear = TRUE;
474 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
475 ctx->input_perspective = TRUE;
476 if (ctx->info.input_centroid[i])
477 ctx->input_centroid = TRUE;
478 }
479
480 num_baryc = 0;
481 /* ignoring sample for now */
482 if (ctx->input_perspective)
483 num_baryc++;
484 if (ctx->input_linear)
485 num_baryc++;
486 if (ctx->input_centroid)
487 num_baryc *= 2;
488
489 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
490
491 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
492 return ctx->num_interp_gpr;
493 }
494
495 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader, u32 **literals)
496 {
497 struct tgsi_full_immediate *immediate;
498 struct r600_shader_ctx ctx;
499 struct r600_bc_output output[32];
500 unsigned output_done, noutput;
501 unsigned opcode;
502 int i, r = 0, pos0;
503
504 ctx.bc = &shader->bc;
505 ctx.shader = shader;
506 r = r600_bc_init(ctx.bc, shader->family);
507 if (r)
508 return r;
509 ctx.tokens = tokens;
510 tgsi_scan_shader(tokens, &ctx.info);
511 tgsi_parse_init(&ctx.parse, tokens);
512 ctx.type = ctx.parse.FullHeader.Processor.Processor;
513 shader->processor_type = ctx.type;
514 ctx.bc->type = shader->processor_type;
515
516 /* register allocations */
517 /* Values [0,127] correspond to GPR[0..127].
518 * Values [128,159] correspond to constant buffer bank 0
519 * Values [160,191] correspond to constant buffer bank 1
520 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
521 * Values [256,287] correspond to constant buffer bank 2 (EG)
522 * Values [288,319] correspond to constant buffer bank 3 (EG)
523 * Other special values are shown in the list below.
524 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
525 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
526 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
527 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
528 * 248 SQ_ALU_SRC_0: special constant 0.0.
529 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
530 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
531 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
532 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
533 * 253 SQ_ALU_SRC_LITERAL: literal constant.
534 * 254 SQ_ALU_SRC_PV: previous vector result.
535 * 255 SQ_ALU_SRC_PS: previous scalar result.
536 */
537 for (i = 0; i < TGSI_FILE_COUNT; i++) {
538 ctx.file_offset[i] = 0;
539 }
540 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
541 ctx.file_offset[TGSI_FILE_INPUT] = 1;
542 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
543 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
544 } else {
545 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
546 }
547 }
548 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
549 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
550 }
551 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
552 ctx.info.file_count[TGSI_FILE_INPUT];
553 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
554 ctx.info.file_count[TGSI_FILE_OUTPUT];
555
556 /* Outside the GPR range. This will be translated to one of the
557 * kcache banks later. */
558 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
559
560 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
561 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
562 ctx.info.file_count[TGSI_FILE_TEMPORARY];
563
564 ctx.nliterals = 0;
565 ctx.literals = NULL;
566
567 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
568 tgsi_parse_token(&ctx.parse);
569 switch (ctx.parse.FullToken.Token.Type) {
570 case TGSI_TOKEN_TYPE_IMMEDIATE:
571 immediate = &ctx.parse.FullToken.FullImmediate;
572 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
573 if(ctx.literals == NULL) {
574 r = -ENOMEM;
575 goto out_err;
576 }
577 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
578 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
579 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
580 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
581 ctx.nliterals++;
582 break;
583 case TGSI_TOKEN_TYPE_DECLARATION:
584 r = tgsi_declaration(&ctx);
585 if (r)
586 goto out_err;
587 break;
588 case TGSI_TOKEN_TYPE_INSTRUCTION:
589 r = tgsi_is_supported(&ctx);
590 if (r)
591 goto out_err;
592 ctx.max_driver_temp_used = 0;
593 /* reserve first tmp for everyone */
594 r600_get_temp(&ctx);
595 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
596 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
597 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
598 else
599 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
600 r = ctx.inst_info->process(&ctx);
601 if (r)
602 goto out_err;
603 break;
604 case TGSI_TOKEN_TYPE_PROPERTY:
605 break;
606 default:
607 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
608 r = -EINVAL;
609 goto out_err;
610 }
611 }
612 /* export output */
613 noutput = shader->noutput;
614 for (i = 0, pos0 = 0; i < noutput; i++) {
615 memset(&output[i], 0, sizeof(struct r600_bc_output));
616 output[i].gpr = shader->output[i].gpr;
617 output[i].elem_size = 3;
618 output[i].swizzle_x = 0;
619 output[i].swizzle_y = 1;
620 output[i].swizzle_z = 2;
621 output[i].swizzle_w = 3;
622 output[i].barrier = 1;
623 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
624 output[i].array_base = i - pos0;
625 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
626 switch (ctx.type) {
627 case TGSI_PROCESSOR_VERTEX:
628 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
629 output[i].array_base = 60;
630 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
631 /* position doesn't count in array_base */
632 pos0++;
633 }
634 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
635 output[i].array_base = 61;
636 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
637 /* position doesn't count in array_base */
638 pos0++;
639 }
640 break;
641 case TGSI_PROCESSOR_FRAGMENT:
642 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
643 output[i].array_base = shader->output[i].sid;
644 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
645 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
646 output[i].array_base = 61;
647 output[i].swizzle_x = 2;
648 output[i].swizzle_y = 7;
649 output[i].swizzle_z = output[i].swizzle_w = 7;
650 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
651 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
652 output[i].array_base = 61;
653 output[i].swizzle_x = 7;
654 output[i].swizzle_y = 1;
655 output[i].swizzle_z = output[i].swizzle_w = 7;
656 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
657 } else {
658 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
659 r = -EINVAL;
660 goto out_err;
661 }
662 break;
663 default:
664 R600_ERR("unsupported processor type %d\n", ctx.type);
665 r = -EINVAL;
666 goto out_err;
667 }
668 }
669 /* add fake param output for vertex shader if no param is exported */
670 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
671 for (i = 0, pos0 = 0; i < noutput; i++) {
672 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
673 pos0 = 1;
674 break;
675 }
676 }
677 if (!pos0) {
678 memset(&output[i], 0, sizeof(struct r600_bc_output));
679 output[i].gpr = 0;
680 output[i].elem_size = 3;
681 output[i].swizzle_x = 0;
682 output[i].swizzle_y = 1;
683 output[i].swizzle_z = 2;
684 output[i].swizzle_w = 3;
685 output[i].barrier = 1;
686 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
687 output[i].array_base = 0;
688 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
689 noutput++;
690 }
691 }
692 /* add fake pixel export */
693 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
694 memset(&output[0], 0, sizeof(struct r600_bc_output));
695 output[0].gpr = 0;
696 output[0].elem_size = 3;
697 output[0].swizzle_x = 7;
698 output[0].swizzle_y = 7;
699 output[0].swizzle_z = 7;
700 output[0].swizzle_w = 7;
701 output[0].barrier = 1;
702 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
703 output[0].array_base = 0;
704 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
705 noutput++;
706 }
707 /* set export done on last export of each type */
708 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
709 if (i == (noutput - 1)) {
710 output[i].end_of_program = 1;
711 }
712 if (!(output_done & (1 << output[i].type))) {
713 output_done |= (1 << output[i].type);
714 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
715 }
716 }
717 /* add output to bytecode */
718 for (i = 0; i < noutput; i++) {
719 r = r600_bc_add_output(ctx.bc, &output[i]);
720 if (r)
721 goto out_err;
722 }
723 *literals = ctx.literals;
724 tgsi_parse_free(&ctx.parse);
725 return 0;
726 out_err:
727 free(ctx.literals);
728 tgsi_parse_free(&ctx.parse);
729 return r;
730 }
731
732 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
733 {
734 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
735 return -EINVAL;
736 }
737
738 static int tgsi_end(struct r600_shader_ctx *ctx)
739 {
740 return 0;
741 }
742
743 static int tgsi_src(struct r600_shader_ctx *ctx,
744 const struct tgsi_full_src_register *tgsi_src,
745 struct r600_bc_alu_src *r600_src)
746 {
747 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
748 r600_src->neg = tgsi_src->Register.Negate;
749 r600_src->abs = tgsi_src->Register.Absolute;
750 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
751 int index;
752 if((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
753 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
754 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
755
756 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
757 r600_bc_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
758 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
759 return 0;
760 }
761 index = tgsi_src->Register.Index;
762 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
763 r600_src->value = ctx->literals + index * 4;
764 } else {
765 if (tgsi_src->Register.Indirect)
766 r600_src->rel = V_SQ_REL_RELATIVE;
767 r600_src->sel = tgsi_src->Register.Index;
768 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
769 }
770 return 0;
771 }
772
773 static int tgsi_dst(struct r600_shader_ctx *ctx,
774 const struct tgsi_full_dst_register *tgsi_dst,
775 unsigned swizzle,
776 struct r600_bc_alu_dst *r600_dst)
777 {
778 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
779
780 r600_dst->sel = tgsi_dst->Register.Index;
781 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
782 r600_dst->chan = swizzle;
783 r600_dst->write = 1;
784 if (tgsi_dst->Register.Indirect)
785 r600_dst->rel = V_SQ_REL_RELATIVE;
786 if (inst->Instruction.Saturate) {
787 r600_dst->clamp = 1;
788 }
789 return 0;
790 }
791
792 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
793 {
794 switch (swizzle) {
795 case 0:
796 return tgsi_src->Register.SwizzleX;
797 case 1:
798 return tgsi_src->Register.SwizzleY;
799 case 2:
800 return tgsi_src->Register.SwizzleZ;
801 case 3:
802 return tgsi_src->Register.SwizzleW;
803 default:
804 return 0;
805 }
806 }
807
808 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
809 {
810 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
811 struct r600_bc_alu alu;
812 int i, j, k, nconst, r;
813
814 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
815 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
816 nconst++;
817 }
818 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
819 if (r) {
820 return r;
821 }
822 }
823 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
824 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
825 int treg = r600_get_temp(ctx);
826 for (k = 0; k < 4; k++) {
827 memset(&alu, 0, sizeof(struct r600_bc_alu));
828 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
829 alu.src[0].sel = r600_src[i].sel;
830 alu.src[0].chan = k;
831 alu.src[0].rel = r600_src[i].rel;
832 alu.dst.sel = treg;
833 alu.dst.chan = k;
834 alu.dst.write = 1;
835 if (k == 3)
836 alu.last = 1;
837 r = r600_bc_add_alu(ctx->bc, &alu);
838 if (r)
839 return r;
840 }
841 r600_src[i].sel = treg;
842 r600_src[i].rel =0;
843 j--;
844 }
845 }
846 return 0;
847 }
848
849 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
850 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
851 {
852 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
853 struct r600_bc_alu alu;
854 int i, j, k, nliteral, r;
855
856 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
857 if (r600_src[i].sel == V_SQ_ALU_SRC_LITERAL) {
858 nliteral++;
859 }
860 }
861 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
862 if (j > 0 && r600_src[i].sel == V_SQ_ALU_SRC_LITERAL) {
863 int treg = r600_get_temp(ctx);
864 for (k = 0; k < 4; k++) {
865 memset(&alu, 0, sizeof(struct r600_bc_alu));
866 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
867 alu.src[0].sel = r600_src[i].sel;
868 alu.src[0].chan = k;
869 alu.src[0].value = r600_src[i].value;
870 alu.dst.sel = treg;
871 alu.dst.chan = k;
872 alu.dst.write = 1;
873 if (k == 3)
874 alu.last = 1;
875 r = r600_bc_add_alu(ctx->bc, &alu);
876 if (r)
877 return r;
878 }
879 r600_src[i].sel = treg;
880 j--;
881 }
882 }
883 return 0;
884 }
885
886 static int tgsi_last_instruction(unsigned writemask)
887 {
888 int i, lasti = 0;
889
890 for (i = 0; i < 4; i++) {
891 if (writemask & (1 << i)) {
892 lasti = i;
893 }
894 }
895 return lasti;
896 }
897
898 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
899 {
900 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
901 struct r600_bc_alu_src r600_src[3];
902 struct r600_bc_alu alu;
903 int i, j, r;
904 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
905
906 r = tgsi_split_constant(ctx, r600_src);
907 if (r)
908 return r;
909 r = tgsi_split_literal_constant(ctx, r600_src);
910 if (r)
911 return r;
912 for (i = 0; i < lasti + 1; i++) {
913 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
914 continue;
915
916 memset(&alu, 0, sizeof(struct r600_bc_alu));
917 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
918 if (r)
919 return r;
920
921 alu.inst = ctx->inst_info->r600_opcode;
922 if (!swap) {
923 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
924 alu.src[j] = r600_src[j];
925 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
926 }
927 } else {
928 alu.src[0] = r600_src[1];
929 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
930
931 alu.src[1] = r600_src[0];
932 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
933 }
934 /* handle some special cases */
935 switch (ctx->inst_info->tgsi_opcode) {
936 case TGSI_OPCODE_SUB:
937 alu.src[1].neg = 1;
938 break;
939 case TGSI_OPCODE_ABS:
940 alu.src[0].abs = 1;
941 break;
942 default:
943 break;
944 }
945 if (i == lasti) {
946 alu.last = 1;
947 }
948 r = r600_bc_add_alu(ctx->bc, &alu);
949 if (r)
950 return r;
951 }
952 return 0;
953 }
954
955 static int tgsi_op2(struct r600_shader_ctx *ctx)
956 {
957 return tgsi_op2_s(ctx, 0);
958 }
959
960 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
961 {
962 return tgsi_op2_s(ctx, 1);
963 }
964
965 /*
966 * r600 - trunc to -PI..PI range
967 * r700 - normalize by dividing by 2PI
968 * see fdo bug 27901
969 */
970 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
971 struct r600_bc_alu_src r600_src[3])
972 {
973 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
974 static float double_pi = 3.1415926535 * 2;
975 static float neg_pi = -3.1415926535;
976
977 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
978 int r;
979 struct r600_bc_alu alu;
980
981 r = tgsi_split_constant(ctx, r600_src);
982 if (r)
983 return r;
984 r = tgsi_split_literal_constant(ctx, r600_src);
985 if (r)
986 return r;
987
988 memset(&alu, 0, sizeof(struct r600_bc_alu));
989 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
990 alu.is_op3 = 1;
991
992 alu.dst.chan = 0;
993 alu.dst.sel = ctx->temp_reg;
994 alu.dst.write = 1;
995
996 alu.src[0] = r600_src[0];
997 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
998
999 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1000 alu.src[1].chan = 0;
1001 alu.src[1].value = (uint32_t *)&half_inv_pi;
1002 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1003 alu.src[2].chan = 1;
1004 alu.last = 1;
1005 r = r600_bc_add_alu(ctx->bc, &alu);
1006 if (r)
1007 return r;
1008
1009 memset(&alu, 0, sizeof(struct r600_bc_alu));
1010 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1011
1012 alu.dst.chan = 0;
1013 alu.dst.sel = ctx->temp_reg;
1014 alu.dst.write = 1;
1015
1016 alu.src[0].sel = ctx->temp_reg;
1017 alu.src[0].chan = 0;
1018 alu.last = 1;
1019 r = r600_bc_add_alu(ctx->bc, &alu);
1020 if (r)
1021 return r;
1022
1023 memset(&alu, 0, sizeof(struct r600_bc_alu));
1024 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1025 alu.is_op3 = 1;
1026
1027 alu.dst.chan = 0;
1028 alu.dst.sel = ctx->temp_reg;
1029 alu.dst.write = 1;
1030
1031 alu.src[0].sel = ctx->temp_reg;
1032 alu.src[0].chan = 0;
1033
1034 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1035 alu.src[1].chan = 0;
1036 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1037 alu.src[2].chan = 1;
1038
1039 if (ctx->bc->chiprev == CHIPREV_R600) {
1040 alu.src[1].value = (uint32_t *)&double_pi;
1041 alu.src[2].value = (uint32_t *)&neg_pi;
1042 } else {
1043 alu.src[1].sel = V_SQ_ALU_SRC_1;
1044 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1045 alu.src[2].neg = 1;
1046 }
1047
1048 alu.last = 1;
1049 r = r600_bc_add_alu(ctx->bc, &alu);
1050 if (r)
1051 return r;
1052 return 0;
1053 }
1054
1055 static int tgsi_trig(struct r600_shader_ctx *ctx)
1056 {
1057 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1058 struct r600_bc_alu_src r600_src[3];
1059 struct r600_bc_alu alu;
1060 int i, r;
1061 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1062
1063 r = tgsi_setup_trig(ctx, r600_src);
1064 if (r)
1065 return r;
1066
1067 memset(&alu, 0, sizeof(struct r600_bc_alu));
1068 alu.inst = ctx->inst_info->r600_opcode;
1069 alu.dst.chan = 0;
1070 alu.dst.sel = ctx->temp_reg;
1071 alu.dst.write = 1;
1072
1073 alu.src[0].sel = ctx->temp_reg;
1074 alu.src[0].chan = 0;
1075 alu.last = 1;
1076 r = r600_bc_add_alu(ctx->bc, &alu);
1077 if (r)
1078 return r;
1079
1080 /* replicate result */
1081 for (i = 0; i < lasti + 1; i++) {
1082 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1083 continue;
1084
1085 memset(&alu, 0, sizeof(struct r600_bc_alu));
1086 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1087
1088 alu.src[0].sel = ctx->temp_reg;
1089 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1090 if (r)
1091 return r;
1092 if (i == lasti)
1093 alu.last = 1;
1094 r = r600_bc_add_alu(ctx->bc, &alu);
1095 if (r)
1096 return r;
1097 }
1098 return 0;
1099 }
1100
1101 static int tgsi_scs(struct r600_shader_ctx *ctx)
1102 {
1103 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1104 struct r600_bc_alu_src r600_src[3];
1105 struct r600_bc_alu alu;
1106 int r;
1107
1108 /* We'll only need the trig stuff if we are going to write to the
1109 * X or Y components of the destination vector.
1110 */
1111 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1112 r = tgsi_setup_trig(ctx, r600_src);
1113 if (r)
1114 return r;
1115 }
1116
1117 /* dst.x = COS */
1118 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1119 memset(&alu, 0, sizeof(struct r600_bc_alu));
1120 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1121 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1122 if (r)
1123 return r;
1124
1125 alu.src[0].sel = ctx->temp_reg;
1126 alu.src[0].chan = 0;
1127 alu.last = 1;
1128 r = r600_bc_add_alu(ctx->bc, &alu);
1129 if (r)
1130 return r;
1131 }
1132
1133 /* dst.y = SIN */
1134 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1135 memset(&alu, 0, sizeof(struct r600_bc_alu));
1136 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1137 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1138 if (r)
1139 return r;
1140
1141 alu.src[0].sel = ctx->temp_reg;
1142 alu.src[0].chan = 0;
1143 alu.last = 1;
1144 r = r600_bc_add_alu(ctx->bc, &alu);
1145 if (r)
1146 return r;
1147 }
1148
1149 /* dst.z = 0.0; */
1150 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1151 memset(&alu, 0, sizeof(struct r600_bc_alu));
1152
1153 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1154
1155 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1156 if (r)
1157 return r;
1158
1159 alu.src[0].sel = V_SQ_ALU_SRC_0;
1160 alu.src[0].chan = 0;
1161
1162 alu.last = 1;
1163
1164 r = r600_bc_add_alu(ctx->bc, &alu);
1165 if (r)
1166 return r;
1167 }
1168
1169 /* dst.w = 1.0; */
1170 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1171 memset(&alu, 0, sizeof(struct r600_bc_alu));
1172
1173 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1174
1175 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1176 if (r)
1177 return r;
1178
1179 alu.src[0].sel = V_SQ_ALU_SRC_1;
1180 alu.src[0].chan = 0;
1181
1182 alu.last = 1;
1183
1184 r = r600_bc_add_alu(ctx->bc, &alu);
1185 if (r)
1186 return r;
1187 }
1188
1189 return 0;
1190 }
1191
1192 static int tgsi_kill(struct r600_shader_ctx *ctx)
1193 {
1194 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1195 struct r600_bc_alu alu;
1196 int i, r;
1197
1198 for (i = 0; i < 4; i++) {
1199 memset(&alu, 0, sizeof(struct r600_bc_alu));
1200 alu.inst = ctx->inst_info->r600_opcode;
1201
1202 alu.dst.chan = i;
1203
1204 alu.src[0].sel = V_SQ_ALU_SRC_0;
1205
1206 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1207 alu.src[1].sel = V_SQ_ALU_SRC_1;
1208 alu.src[1].neg = 1;
1209 } else {
1210 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1211 if (r)
1212 return r;
1213 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1214 }
1215 if (i == 3) {
1216 alu.last = 1;
1217 }
1218 r = r600_bc_add_alu(ctx->bc, &alu);
1219 if (r)
1220 return r;
1221 }
1222
1223 /* kill must be last in ALU */
1224 ctx->bc->force_add_cf = 1;
1225 ctx->shader->uses_kill = TRUE;
1226 return 0;
1227 }
1228
1229 static int tgsi_lit(struct r600_shader_ctx *ctx)
1230 {
1231 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1232 struct r600_bc_alu alu;
1233 struct r600_bc_alu_src r600_src[3];
1234 int r;
1235
1236 r = tgsi_split_constant(ctx, r600_src);
1237 if (r)
1238 return r;
1239 r = tgsi_split_literal_constant(ctx, r600_src);
1240 if (r)
1241 return r;
1242
1243 /* dst.x, <- 1.0 */
1244 memset(&alu, 0, sizeof(struct r600_bc_alu));
1245 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1246 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1247 alu.src[0].chan = 0;
1248 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1249 if (r)
1250 return r;
1251 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1252 r = r600_bc_add_alu(ctx->bc, &alu);
1253 if (r)
1254 return r;
1255
1256 /* dst.y = max(src.x, 0.0) */
1257 memset(&alu, 0, sizeof(struct r600_bc_alu));
1258 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1259 alu.src[0] = r600_src[0];
1260 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1261 alu.src[1].chan = 0;
1262 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1263 if (r)
1264 return r;
1265 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1266 r = r600_bc_add_alu(ctx->bc, &alu);
1267 if (r)
1268 return r;
1269
1270 /* dst.w, <- 1.0 */
1271 memset(&alu, 0, sizeof(struct r600_bc_alu));
1272 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1273 alu.src[0].sel = V_SQ_ALU_SRC_1;
1274 alu.src[0].chan = 0;
1275 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1276 if (r)
1277 return r;
1278 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1279 alu.last = 1;
1280 r = r600_bc_add_alu(ctx->bc, &alu);
1281 if (r)
1282 return r;
1283
1284 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1285 {
1286 int chan;
1287 int sel;
1288
1289 /* dst.z = log(src.y) */
1290 memset(&alu, 0, sizeof(struct r600_bc_alu));
1291 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1292 alu.src[0] = r600_src[0];
1293 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1294 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1295 if (r)
1296 return r;
1297 alu.last = 1;
1298 r = r600_bc_add_alu(ctx->bc, &alu);
1299 if (r)
1300 return r;
1301
1302 chan = alu.dst.chan;
1303 sel = alu.dst.sel;
1304
1305 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1306 memset(&alu, 0, sizeof(struct r600_bc_alu));
1307 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1308 alu.src[0] = r600_src[0];
1309 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1310 alu.src[1].sel = sel;
1311 alu.src[1].chan = chan;
1312
1313 alu.src[2] = r600_src[0];
1314 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1315 alu.dst.sel = ctx->temp_reg;
1316 alu.dst.chan = 0;
1317 alu.dst.write = 1;
1318 alu.is_op3 = 1;
1319 alu.last = 1;
1320 r = r600_bc_add_alu(ctx->bc, &alu);
1321 if (r)
1322 return r;
1323
1324 /* dst.z = exp(tmp.x) */
1325 memset(&alu, 0, sizeof(struct r600_bc_alu));
1326 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1327 alu.src[0].sel = ctx->temp_reg;
1328 alu.src[0].chan = 0;
1329 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1330 if (r)
1331 return r;
1332 alu.last = 1;
1333 r = r600_bc_add_alu(ctx->bc, &alu);
1334 if (r)
1335 return r;
1336 }
1337 return 0;
1338 }
1339
1340 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1341 {
1342 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1343 struct r600_bc_alu alu;
1344 int i, r;
1345
1346 memset(&alu, 0, sizeof(struct r600_bc_alu));
1347
1348 /* FIXME:
1349 * For state trackers other than OpenGL, we'll want to use
1350 * _RECIPSQRT_IEEE instead.
1351 */
1352 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1353
1354 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1355 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1356 if (r)
1357 return r;
1358 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1359 alu.src[i].abs = 1;
1360 }
1361 alu.dst.sel = ctx->temp_reg;
1362 alu.dst.write = 1;
1363 alu.last = 1;
1364 r = r600_bc_add_alu(ctx->bc, &alu);
1365 if (r)
1366 return r;
1367 /* replicate result */
1368 return tgsi_helper_tempx_replicate(ctx);
1369 }
1370
1371 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1372 {
1373 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1374 struct r600_bc_alu alu;
1375 int i, r;
1376
1377 for (i = 0; i < 4; i++) {
1378 memset(&alu, 0, sizeof(struct r600_bc_alu));
1379 alu.src[0].sel = ctx->temp_reg;
1380 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1381 alu.dst.chan = i;
1382 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1383 if (r)
1384 return r;
1385 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1386 if (i == 3)
1387 alu.last = 1;
1388 r = r600_bc_add_alu(ctx->bc, &alu);
1389 if (r)
1390 return r;
1391 }
1392 return 0;
1393 }
1394
1395 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1396 {
1397 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1398 struct r600_bc_alu alu;
1399 int i, r;
1400
1401 memset(&alu, 0, sizeof(struct r600_bc_alu));
1402 alu.inst = ctx->inst_info->r600_opcode;
1403 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1404 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1405 if (r)
1406 return r;
1407 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1408 }
1409 alu.dst.sel = ctx->temp_reg;
1410 alu.dst.write = 1;
1411 alu.last = 1;
1412 r = r600_bc_add_alu(ctx->bc, &alu);
1413 if (r)
1414 return r;
1415 /* replicate result */
1416 return tgsi_helper_tempx_replicate(ctx);
1417 }
1418
1419 static int tgsi_pow(struct r600_shader_ctx *ctx)
1420 {
1421 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1422 struct r600_bc_alu alu;
1423 int r;
1424
1425 /* LOG2(a) */
1426 memset(&alu, 0, sizeof(struct r600_bc_alu));
1427 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1428 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1429 if (r)
1430 return r;
1431 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1432 alu.dst.sel = ctx->temp_reg;
1433 alu.dst.write = 1;
1434 alu.last = 1;
1435 r = r600_bc_add_alu(ctx->bc, &alu);
1436 if (r)
1437 return r;
1438 /* b * LOG2(a) */
1439 memset(&alu, 0, sizeof(struct r600_bc_alu));
1440 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1441 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1442 if (r)
1443 return r;
1444 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1445 alu.src[1].sel = ctx->temp_reg;
1446 alu.dst.sel = ctx->temp_reg;
1447 alu.dst.write = 1;
1448 alu.last = 1;
1449 r = r600_bc_add_alu(ctx->bc, &alu);
1450 if (r)
1451 return r;
1452 /* POW(a,b) = EXP2(b * LOG2(a))*/
1453 memset(&alu, 0, sizeof(struct r600_bc_alu));
1454 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1455 alu.src[0].sel = ctx->temp_reg;
1456 alu.dst.sel = ctx->temp_reg;
1457 alu.dst.write = 1;
1458 alu.last = 1;
1459 r = r600_bc_add_alu(ctx->bc, &alu);
1460 if (r)
1461 return r;
1462 return tgsi_helper_tempx_replicate(ctx);
1463 }
1464
1465 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1466 {
1467 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1468 struct r600_bc_alu alu;
1469 struct r600_bc_alu_src r600_src[3];
1470 int i, r;
1471
1472 r = tgsi_split_constant(ctx, r600_src);
1473 if (r)
1474 return r;
1475 r = tgsi_split_literal_constant(ctx, r600_src);
1476 if (r)
1477 return r;
1478
1479 /* tmp = (src > 0 ? 1 : src) */
1480 for (i = 0; i < 4; i++) {
1481 memset(&alu, 0, sizeof(struct r600_bc_alu));
1482 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1483 alu.is_op3 = 1;
1484
1485 alu.dst.sel = ctx->temp_reg;
1486 alu.dst.chan = i;
1487
1488 alu.src[0] = r600_src[0];
1489 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1490
1491 alu.src[1].sel = V_SQ_ALU_SRC_1;
1492
1493 alu.src[2] = r600_src[0];
1494 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1495 if (i == 3)
1496 alu.last = 1;
1497 r = r600_bc_add_alu(ctx->bc, &alu);
1498 if (r)
1499 return r;
1500 }
1501
1502 /* dst = (-tmp > 0 ? -1 : tmp) */
1503 for (i = 0; i < 4; i++) {
1504 memset(&alu, 0, sizeof(struct r600_bc_alu));
1505 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1506 alu.is_op3 = 1;
1507 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1508 if (r)
1509 return r;
1510
1511 alu.src[0].sel = ctx->temp_reg;
1512 alu.src[0].chan = i;
1513 alu.src[0].neg = 1;
1514
1515 alu.src[1].sel = V_SQ_ALU_SRC_1;
1516 alu.src[1].neg = 1;
1517
1518 alu.src[2].sel = ctx->temp_reg;
1519 alu.src[2].chan = i;
1520
1521 if (i == 3)
1522 alu.last = 1;
1523 r = r600_bc_add_alu(ctx->bc, &alu);
1524 if (r)
1525 return r;
1526 }
1527 return 0;
1528 }
1529
1530 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1531 {
1532 struct r600_bc_alu alu;
1533 int i, r;
1534
1535 for (i = 0; i < 4; i++) {
1536 memset(&alu, 0, sizeof(struct r600_bc_alu));
1537 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1538 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1539 alu.dst.chan = i;
1540 } else {
1541 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1542 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1543 if (r)
1544 return r;
1545 alu.src[0].sel = ctx->temp_reg;
1546 alu.src[0].chan = i;
1547 }
1548 if (i == 3) {
1549 alu.last = 1;
1550 }
1551 r = r600_bc_add_alu(ctx->bc, &alu);
1552 if (r)
1553 return r;
1554 }
1555 return 0;
1556 }
1557
1558 static int tgsi_op3(struct r600_shader_ctx *ctx)
1559 {
1560 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1561 struct r600_bc_alu_src r600_src[3];
1562 struct r600_bc_alu alu;
1563 int i, j, r;
1564 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1565
1566 r = tgsi_split_constant(ctx, r600_src);
1567 if (r)
1568 return r;
1569 r = tgsi_split_literal_constant(ctx, r600_src);
1570 if (r)
1571 return r;
1572 for (i = 0; i < lasti + 1; i++) {
1573 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1574 continue;
1575
1576 memset(&alu, 0, sizeof(struct r600_bc_alu));
1577 alu.inst = ctx->inst_info->r600_opcode;
1578 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1579 alu.src[j] = r600_src[j];
1580 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1581 }
1582
1583 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1584 if (r)
1585 return r;
1586
1587 alu.dst.chan = i;
1588 alu.dst.write = 1;
1589 alu.is_op3 = 1;
1590 if (i == lasti) {
1591 alu.last = 1;
1592 }
1593 r = r600_bc_add_alu(ctx->bc, &alu);
1594 if (r)
1595 return r;
1596 }
1597 return 0;
1598 }
1599
1600 static int tgsi_dp(struct r600_shader_ctx *ctx)
1601 {
1602 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1603 struct r600_bc_alu_src r600_src[3];
1604 struct r600_bc_alu alu;
1605 int i, j, r;
1606
1607 r = tgsi_split_constant(ctx, r600_src);
1608 if (r)
1609 return r;
1610 r = tgsi_split_literal_constant(ctx, r600_src);
1611 if (r)
1612 return r;
1613 for (i = 0; i < 4; i++) {
1614 memset(&alu, 0, sizeof(struct r600_bc_alu));
1615 alu.inst = ctx->inst_info->r600_opcode;
1616 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1617 alu.src[j] = r600_src[j];
1618 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1619 }
1620
1621 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1622 if (r)
1623 return r;
1624
1625 alu.dst.chan = i;
1626 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1627 /* handle some special cases */
1628 switch (ctx->inst_info->tgsi_opcode) {
1629 case TGSI_OPCODE_DP2:
1630 if (i > 1) {
1631 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1632 alu.src[0].chan = alu.src[1].chan = 0;
1633 }
1634 break;
1635 case TGSI_OPCODE_DP3:
1636 if (i > 2) {
1637 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1638 alu.src[0].chan = alu.src[1].chan = 0;
1639 }
1640 break;
1641 case TGSI_OPCODE_DPH:
1642 if (i == 3) {
1643 alu.src[0].sel = V_SQ_ALU_SRC_1;
1644 alu.src[0].chan = 0;
1645 alu.src[0].neg = 0;
1646 }
1647 break;
1648 default:
1649 break;
1650 }
1651 if (i == 3) {
1652 alu.last = 1;
1653 }
1654 r = r600_bc_add_alu(ctx->bc, &alu);
1655 if (r)
1656 return r;
1657 }
1658 return 0;
1659 }
1660
1661 static int tgsi_tex(struct r600_shader_ctx *ctx)
1662 {
1663 static float one_point_five = 1.5f;
1664 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1665 struct r600_bc_tex tex;
1666 struct r600_bc_alu alu;
1667 unsigned src_gpr;
1668 int r, i;
1669 int opcode;
1670 boolean src_not_temp =
1671 inst->Src[0].Register.File != TGSI_FILE_TEMPORARY &&
1672 inst->Src[0].Register.File != TGSI_FILE_INPUT;
1673
1674 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1675
1676 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1677 /* Add perspective divide */
1678 memset(&alu, 0, sizeof(struct r600_bc_alu));
1679 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1680 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1681 if (r)
1682 return r;
1683
1684 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1685 alu.dst.sel = ctx->temp_reg;
1686 alu.dst.chan = 3;
1687 alu.last = 1;
1688 alu.dst.write = 1;
1689 r = r600_bc_add_alu(ctx->bc, &alu);
1690 if (r)
1691 return r;
1692
1693 for (i = 0; i < 3; i++) {
1694 memset(&alu, 0, sizeof(struct r600_bc_alu));
1695 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1696 alu.src[0].sel = ctx->temp_reg;
1697 alu.src[0].chan = 3;
1698 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1699 if (r)
1700 return r;
1701 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1702 alu.dst.sel = ctx->temp_reg;
1703 alu.dst.chan = i;
1704 alu.dst.write = 1;
1705 r = r600_bc_add_alu(ctx->bc, &alu);
1706 if (r)
1707 return r;
1708 }
1709 memset(&alu, 0, sizeof(struct r600_bc_alu));
1710 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1711 alu.src[0].sel = V_SQ_ALU_SRC_1;
1712 alu.src[0].chan = 0;
1713 alu.dst.sel = ctx->temp_reg;
1714 alu.dst.chan = 3;
1715 alu.last = 1;
1716 alu.dst.write = 1;
1717 r = r600_bc_add_alu(ctx->bc, &alu);
1718 if (r)
1719 return r;
1720 src_not_temp = FALSE;
1721 src_gpr = ctx->temp_reg;
1722 }
1723
1724 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1725 int src_chan, src2_chan;
1726
1727 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1728 for (i = 0; i < 4; i++) {
1729 memset(&alu, 0, sizeof(struct r600_bc_alu));
1730 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1731 switch (i) {
1732 case 0:
1733 src_chan = 2;
1734 src2_chan = 1;
1735 break;
1736 case 1:
1737 src_chan = 2;
1738 src2_chan = 0;
1739 break;
1740 case 2:
1741 src_chan = 0;
1742 src2_chan = 2;
1743 break;
1744 case 3:
1745 src_chan = 1;
1746 src2_chan = 2;
1747 break;
1748 default:
1749 assert(0);
1750 src_chan = 0;
1751 src2_chan = 0;
1752 break;
1753 }
1754 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1755 if (r)
1756 return r;
1757 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1758 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1759 if (r)
1760 return r;
1761 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1762 alu.dst.sel = ctx->temp_reg;
1763 alu.dst.chan = i;
1764 if (i == 3)
1765 alu.last = 1;
1766 alu.dst.write = 1;
1767 r = r600_bc_add_alu(ctx->bc, &alu);
1768 if (r)
1769 return r;
1770 }
1771
1772 /* tmp1.z = RCP_e(|tmp1.z|) */
1773 memset(&alu, 0, sizeof(struct r600_bc_alu));
1774 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1775 alu.src[0].sel = ctx->temp_reg;
1776 alu.src[0].chan = 2;
1777 alu.src[0].abs = 1;
1778 alu.dst.sel = ctx->temp_reg;
1779 alu.dst.chan = 2;
1780 alu.dst.write = 1;
1781 alu.last = 1;
1782 r = r600_bc_add_alu(ctx->bc, &alu);
1783 if (r)
1784 return r;
1785
1786 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1787 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1788 * muladd has no writemask, have to use another temp
1789 */
1790 memset(&alu, 0, sizeof(struct r600_bc_alu));
1791 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1792 alu.is_op3 = 1;
1793
1794 alu.src[0].sel = ctx->temp_reg;
1795 alu.src[0].chan = 0;
1796 alu.src[1].sel = ctx->temp_reg;
1797 alu.src[1].chan = 2;
1798
1799 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1800 alu.src[2].chan = 0;
1801 alu.src[2].value = (u32*)&one_point_five;
1802
1803 alu.dst.sel = ctx->temp_reg;
1804 alu.dst.chan = 0;
1805 alu.dst.write = 1;
1806
1807 r = r600_bc_add_alu(ctx->bc, &alu);
1808 if (r)
1809 return r;
1810
1811 memset(&alu, 0, sizeof(struct r600_bc_alu));
1812 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1813 alu.is_op3 = 1;
1814
1815 alu.src[0].sel = ctx->temp_reg;
1816 alu.src[0].chan = 1;
1817 alu.src[1].sel = ctx->temp_reg;
1818 alu.src[1].chan = 2;
1819
1820 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1821 alu.src[2].chan = 0;
1822 alu.src[2].value = (u32*)&one_point_five;
1823
1824 alu.dst.sel = ctx->temp_reg;
1825 alu.dst.chan = 1;
1826 alu.dst.write = 1;
1827
1828 alu.last = 1;
1829 r = r600_bc_add_alu(ctx->bc, &alu);
1830 if (r)
1831 return r;
1832
1833 src_not_temp = FALSE;
1834 src_gpr = ctx->temp_reg;
1835 }
1836
1837 if (src_not_temp) {
1838 for (i = 0; i < 4; i++) {
1839 memset(&alu, 0, sizeof(struct r600_bc_alu));
1840 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1841 alu.src[0].sel = src_gpr;
1842 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1843 alu.dst.sel = ctx->temp_reg;
1844 alu.dst.chan = i;
1845 if (i == 3)
1846 alu.last = 1;
1847 alu.dst.write = 1;
1848 r = r600_bc_add_alu(ctx->bc, &alu);
1849 if (r)
1850 return r;
1851 }
1852 src_gpr = ctx->temp_reg;
1853 }
1854
1855 opcode = ctx->inst_info->r600_opcode;
1856 if (opcode == SQ_TEX_INST_SAMPLE &&
1857 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1858 opcode = SQ_TEX_INST_SAMPLE_C;
1859
1860 memset(&tex, 0, sizeof(struct r600_bc_tex));
1861 tex.inst = opcode;
1862 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1863 tex.resource_id = tex.sampler_id;
1864 tex.src_gpr = src_gpr;
1865 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1866 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1867 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1868 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1869 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1870 tex.src_sel_x = 0;
1871 tex.src_sel_y = 1;
1872 tex.src_sel_z = 2;
1873 tex.src_sel_w = 3;
1874
1875 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1876 tex.src_sel_x = 1;
1877 tex.src_sel_y = 0;
1878 tex.src_sel_z = 3;
1879 tex.src_sel_w = 1;
1880 }
1881
1882 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1883 tex.coord_type_x = 1;
1884 tex.coord_type_y = 1;
1885 tex.coord_type_z = 1;
1886 tex.coord_type_w = 1;
1887 }
1888
1889 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1890 tex.src_sel_w = 2;
1891
1892 r = r600_bc_add_tex(ctx->bc, &tex);
1893 if (r)
1894 return r;
1895
1896 /* add shadow ambient support - gallium doesn't do it yet */
1897 return 0;
1898 }
1899
1900 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1901 {
1902 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1903 struct r600_bc_alu_src r600_src[3];
1904 struct r600_bc_alu alu;
1905 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1906 unsigned i;
1907 int r;
1908
1909 r = tgsi_split_constant(ctx, r600_src);
1910 if (r)
1911 return r;
1912 r = tgsi_split_literal_constant(ctx, r600_src);
1913 if (r)
1914 return r;
1915
1916 /* optimize if it's just an equal balance */
1917 if(r600_src[0].sel == V_SQ_ALU_SRC_0_5) {
1918 for (i = 0; i < lasti + 1; i++) {
1919 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1920 continue;
1921
1922 memset(&alu, 0, sizeof(struct r600_bc_alu));
1923 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1924 alu.src[0] = r600_src[1];
1925 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
1926 alu.src[1] = r600_src[2];
1927 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1928 alu.omod = 3;
1929 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1930 if (r)
1931 return r;
1932
1933 alu.dst.chan = i;
1934 if (i == lasti) {
1935 alu.last = 1;
1936 }
1937 r = r600_bc_add_alu(ctx->bc, &alu);
1938 if (r)
1939 return r;
1940 }
1941 return 0;
1942 }
1943
1944 /* 1 - src0 */
1945 for (i = 0; i < lasti + 1; i++) {
1946 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1947 continue;
1948
1949 memset(&alu, 0, sizeof(struct r600_bc_alu));
1950 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1951 alu.src[0].sel = V_SQ_ALU_SRC_1;
1952 alu.src[0].chan = 0;
1953 alu.src[1] = r600_src[0];
1954 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1955 alu.src[1].neg = 1;
1956 alu.dst.sel = ctx->temp_reg;
1957 alu.dst.chan = i;
1958 if (i == lasti) {
1959 alu.last = 1;
1960 }
1961 alu.dst.write = 1;
1962 r = r600_bc_add_alu(ctx->bc, &alu);
1963 if (r)
1964 return r;
1965 }
1966
1967 /* (1 - src0) * src2 */
1968 for (i = 0; i < lasti + 1; i++) {
1969 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1970 continue;
1971
1972 memset(&alu, 0, sizeof(struct r600_bc_alu));
1973 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1974 alu.src[0].sel = ctx->temp_reg;
1975 alu.src[0].chan = i;
1976 alu.src[1] = r600_src[2];
1977 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1978 alu.dst.sel = ctx->temp_reg;
1979 alu.dst.chan = i;
1980 if (i == lasti) {
1981 alu.last = 1;
1982 }
1983 alu.dst.write = 1;
1984 r = r600_bc_add_alu(ctx->bc, &alu);
1985 if (r)
1986 return r;
1987 }
1988
1989 /* src0 * src1 + (1 - src0) * src2 */
1990 for (i = 0; i < lasti + 1; i++) {
1991 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1992 continue;
1993
1994 memset(&alu, 0, sizeof(struct r600_bc_alu));
1995 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1996 alu.is_op3 = 1;
1997 alu.src[0] = r600_src[0];
1998 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1999 alu.src[1] = r600_src[1];
2000 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2001 alu.src[2].sel = ctx->temp_reg;
2002 alu.src[2].chan = i;
2003
2004 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2005 if (r)
2006 return r;
2007
2008 alu.dst.chan = i;
2009 if (i == lasti) {
2010 alu.last = 1;
2011 }
2012 r = r600_bc_add_alu(ctx->bc, &alu);
2013 if (r)
2014 return r;
2015 }
2016 return 0;
2017 }
2018
2019 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2020 {
2021 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2022 struct r600_bc_alu_src r600_src[3];
2023 struct r600_bc_alu alu;
2024 int i, r;
2025 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2026
2027 r = tgsi_split_constant(ctx, r600_src);
2028 if (r)
2029 return r;
2030 r = tgsi_split_literal_constant(ctx, r600_src);
2031 if (r)
2032 return r;
2033
2034 for (i = 0; i < lasti + 1; i++) {
2035 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2036 continue;
2037
2038 memset(&alu, 0, sizeof(struct r600_bc_alu));
2039 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2040 alu.src[0] = r600_src[0];
2041 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2042
2043 alu.src[1] = r600_src[2];
2044 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2045
2046 alu.src[2] = r600_src[1];
2047 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2048
2049 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2050 if (r)
2051 return r;
2052
2053 alu.dst.chan = i;
2054 alu.dst.write = 1;
2055 alu.is_op3 = 1;
2056 if (i == lasti)
2057 alu.last = 1;
2058 r = r600_bc_add_alu(ctx->bc, &alu);
2059 if (r)
2060 return r;
2061 }
2062 return 0;
2063 }
2064
2065 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2066 {
2067 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2068 struct r600_bc_alu_src r600_src[3];
2069 struct r600_bc_alu alu;
2070 uint32_t use_temp = 0;
2071 int i, r;
2072
2073 if (inst->Dst[0].Register.WriteMask != 0xf)
2074 use_temp = 1;
2075
2076 r = tgsi_split_constant(ctx, r600_src);
2077 if (r)
2078 return r;
2079 r = tgsi_split_literal_constant(ctx, r600_src);
2080 if (r)
2081 return r;
2082
2083 for (i = 0; i < 4; i++) {
2084 memset(&alu, 0, sizeof(struct r600_bc_alu));
2085 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2086
2087 alu.src[0] = r600_src[0];
2088 switch (i) {
2089 case 0:
2090 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2091 break;
2092 case 1:
2093 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2094 break;
2095 case 2:
2096 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2097 break;
2098 case 3:
2099 alu.src[0].sel = V_SQ_ALU_SRC_0;
2100 alu.src[0].chan = i;
2101 }
2102
2103 alu.src[1] = r600_src[1];
2104 switch (i) {
2105 case 0:
2106 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2107 break;
2108 case 1:
2109 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2110 break;
2111 case 2:
2112 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2113 break;
2114 case 3:
2115 alu.src[1].sel = V_SQ_ALU_SRC_0;
2116 alu.src[1].chan = i;
2117 }
2118
2119 alu.dst.sel = ctx->temp_reg;
2120 alu.dst.chan = i;
2121 alu.dst.write = 1;
2122
2123 if (i == 3)
2124 alu.last = 1;
2125 r = r600_bc_add_alu(ctx->bc, &alu);
2126 if (r)
2127 return r;
2128 }
2129
2130 for (i = 0; i < 4; i++) {
2131 memset(&alu, 0, sizeof(struct r600_bc_alu));
2132 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2133
2134 alu.src[0] = r600_src[0];
2135 switch (i) {
2136 case 0:
2137 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2138 break;
2139 case 1:
2140 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2141 break;
2142 case 2:
2143 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2144 break;
2145 case 3:
2146 alu.src[0].sel = V_SQ_ALU_SRC_0;
2147 alu.src[0].chan = i;
2148 }
2149
2150 alu.src[1] = r600_src[1];
2151 switch (i) {
2152 case 0:
2153 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2154 break;
2155 case 1:
2156 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2157 break;
2158 case 2:
2159 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2160 break;
2161 case 3:
2162 alu.src[1].sel = V_SQ_ALU_SRC_0;
2163 alu.src[1].chan = i;
2164 }
2165
2166 alu.src[2].sel = ctx->temp_reg;
2167 alu.src[2].neg = 1;
2168 alu.src[2].chan = i;
2169
2170 if (use_temp)
2171 alu.dst.sel = ctx->temp_reg;
2172 else {
2173 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2174 if (r)
2175 return r;
2176 }
2177 alu.dst.chan = i;
2178 alu.dst.write = 1;
2179 alu.is_op3 = 1;
2180 if (i == 3)
2181 alu.last = 1;
2182 r = r600_bc_add_alu(ctx->bc, &alu);
2183 if (r)
2184 return r;
2185 }
2186 if (use_temp)
2187 return tgsi_helper_copy(ctx, inst);
2188 return 0;
2189 }
2190
2191 static int tgsi_exp(struct r600_shader_ctx *ctx)
2192 {
2193 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2194 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2195 struct r600_bc_alu alu;
2196 int r;
2197
2198 /* result.x = 2^floor(src); */
2199 if (inst->Dst[0].Register.WriteMask & 1) {
2200 memset(&alu, 0, sizeof(struct r600_bc_alu));
2201
2202 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2203 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2204 if (r)
2205 return r;
2206
2207 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2208
2209 alu.dst.sel = ctx->temp_reg;
2210 alu.dst.chan = 0;
2211 alu.dst.write = 1;
2212 alu.last = 1;
2213 r = r600_bc_add_alu(ctx->bc, &alu);
2214 if (r)
2215 return r;
2216
2217 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2218 alu.src[0].sel = ctx->temp_reg;
2219 alu.src[0].chan = 0;
2220
2221 alu.dst.sel = ctx->temp_reg;
2222 alu.dst.chan = 0;
2223 alu.dst.write = 1;
2224 alu.last = 1;
2225 r = r600_bc_add_alu(ctx->bc, &alu);
2226 if (r)
2227 return r;
2228 }
2229
2230 /* result.y = tmp - floor(tmp); */
2231 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2232 memset(&alu, 0, sizeof(struct r600_bc_alu));
2233
2234 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2235 alu.src[0] = r600_src[0];
2236 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2237 if (r)
2238 return r;
2239 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2240
2241 alu.dst.sel = ctx->temp_reg;
2242 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2243 // if (r)
2244 // return r;
2245 alu.dst.write = 1;
2246 alu.dst.chan = 1;
2247
2248 alu.last = 1;
2249
2250 r = r600_bc_add_alu(ctx->bc, &alu);
2251 if (r)
2252 return r;
2253 }
2254
2255 /* result.z = RoughApprox2ToX(tmp);*/
2256 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2257 memset(&alu, 0, sizeof(struct r600_bc_alu));
2258 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2259 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2260 if (r)
2261 return r;
2262 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2263
2264 alu.dst.sel = ctx->temp_reg;
2265 alu.dst.write = 1;
2266 alu.dst.chan = 2;
2267
2268 alu.last = 1;
2269
2270 r = r600_bc_add_alu(ctx->bc, &alu);
2271 if (r)
2272 return r;
2273 }
2274
2275 /* result.w = 1.0;*/
2276 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2277 memset(&alu, 0, sizeof(struct r600_bc_alu));
2278
2279 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2280 alu.src[0].sel = V_SQ_ALU_SRC_1;
2281 alu.src[0].chan = 0;
2282
2283 alu.dst.sel = ctx->temp_reg;
2284 alu.dst.chan = 3;
2285 alu.dst.write = 1;
2286 alu.last = 1;
2287 r = r600_bc_add_alu(ctx->bc, &alu);
2288 if (r)
2289 return r;
2290 }
2291 return tgsi_helper_copy(ctx, inst);
2292 }
2293
2294 static int tgsi_log(struct r600_shader_ctx *ctx)
2295 {
2296 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2297 struct r600_bc_alu alu;
2298 int r;
2299
2300 /* result.x = floor(log2(src)); */
2301 if (inst->Dst[0].Register.WriteMask & 1) {
2302 memset(&alu, 0, sizeof(struct r600_bc_alu));
2303
2304 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2305 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2306 if (r)
2307 return r;
2308
2309 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2310
2311 alu.dst.sel = ctx->temp_reg;
2312 alu.dst.chan = 0;
2313 alu.dst.write = 1;
2314 alu.last = 1;
2315 r = r600_bc_add_alu(ctx->bc, &alu);
2316 if (r)
2317 return r;
2318
2319 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2320 alu.src[0].sel = ctx->temp_reg;
2321 alu.src[0].chan = 0;
2322
2323 alu.dst.sel = ctx->temp_reg;
2324 alu.dst.chan = 0;
2325 alu.dst.write = 1;
2326 alu.last = 1;
2327
2328 r = r600_bc_add_alu(ctx->bc, &alu);
2329 if (r)
2330 return r;
2331 }
2332
2333 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2334 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2335 memset(&alu, 0, sizeof(struct r600_bc_alu));
2336
2337 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2338 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2339 if (r)
2340 return r;
2341
2342 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2343
2344 alu.dst.sel = ctx->temp_reg;
2345 alu.dst.chan = 1;
2346 alu.dst.write = 1;
2347 alu.last = 1;
2348
2349 r = r600_bc_add_alu(ctx->bc, &alu);
2350 if (r)
2351 return r;
2352
2353 memset(&alu, 0, sizeof(struct r600_bc_alu));
2354
2355 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2356 alu.src[0].sel = ctx->temp_reg;
2357 alu.src[0].chan = 1;
2358
2359 alu.dst.sel = ctx->temp_reg;
2360 alu.dst.chan = 1;
2361 alu.dst.write = 1;
2362 alu.last = 1;
2363
2364 r = r600_bc_add_alu(ctx->bc, &alu);
2365 if (r)
2366 return r;
2367
2368 memset(&alu, 0, sizeof(struct r600_bc_alu));
2369
2370 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2371 alu.src[0].sel = ctx->temp_reg;
2372 alu.src[0].chan = 1;
2373
2374 alu.dst.sel = ctx->temp_reg;
2375 alu.dst.chan = 1;
2376 alu.dst.write = 1;
2377 alu.last = 1;
2378
2379 r = r600_bc_add_alu(ctx->bc, &alu);
2380 if (r)
2381 return r;
2382
2383 memset(&alu, 0, sizeof(struct r600_bc_alu));
2384
2385 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2386 alu.src[0].sel = ctx->temp_reg;
2387 alu.src[0].chan = 1;
2388
2389 alu.dst.sel = ctx->temp_reg;
2390 alu.dst.chan = 1;
2391 alu.dst.write = 1;
2392 alu.last = 1;
2393
2394 r = r600_bc_add_alu(ctx->bc, &alu);
2395 if (r)
2396 return r;
2397
2398 memset(&alu, 0, sizeof(struct r600_bc_alu));
2399
2400 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2401
2402 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2403 if (r)
2404 return r;
2405
2406 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2407
2408 alu.src[1].sel = ctx->temp_reg;
2409 alu.src[1].chan = 1;
2410
2411 alu.dst.sel = ctx->temp_reg;
2412 alu.dst.chan = 1;
2413 alu.dst.write = 1;
2414 alu.last = 1;
2415
2416 r = r600_bc_add_alu(ctx->bc, &alu);
2417 if (r)
2418 return r;
2419 }
2420
2421 /* result.z = log2(src);*/
2422 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2423 memset(&alu, 0, sizeof(struct r600_bc_alu));
2424
2425 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2426 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2427 if (r)
2428 return r;
2429
2430 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2431
2432 alu.dst.sel = ctx->temp_reg;
2433 alu.dst.write = 1;
2434 alu.dst.chan = 2;
2435 alu.last = 1;
2436
2437 r = r600_bc_add_alu(ctx->bc, &alu);
2438 if (r)
2439 return r;
2440 }
2441
2442 /* result.w = 1.0; */
2443 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2444 memset(&alu, 0, sizeof(struct r600_bc_alu));
2445
2446 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2447 alu.src[0].sel = V_SQ_ALU_SRC_1;
2448 alu.src[0].chan = 0;
2449
2450 alu.dst.sel = ctx->temp_reg;
2451 alu.dst.chan = 3;
2452 alu.dst.write = 1;
2453 alu.last = 1;
2454
2455 r = r600_bc_add_alu(ctx->bc, &alu);
2456 if (r)
2457 return r;
2458 }
2459
2460 return tgsi_helper_copy(ctx, inst);
2461 }
2462
2463 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2464 {
2465 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2466 struct r600_bc_alu alu;
2467 int r;
2468 memset(&alu, 0, sizeof(struct r600_bc_alu));
2469
2470 switch (inst->Instruction.Opcode) {
2471 case TGSI_OPCODE_ARL:
2472 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2473 break;
2474 case TGSI_OPCODE_ARR:
2475 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2476 break;
2477 default:
2478 assert(0);
2479 return -1;
2480 }
2481
2482 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2483 if (r)
2484 return r;
2485 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2486 alu.last = 1;
2487 alu.dst.chan = 0;
2488 alu.dst.sel = ctx->temp_reg;
2489 alu.dst.write = 1;
2490 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2491 if (r)
2492 return r;
2493 memset(&alu, 0, sizeof(struct r600_bc_alu));
2494 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2495 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2496 if (r)
2497 return r;
2498 alu.src[0].sel = ctx->temp_reg;
2499 alu.src[0].chan = 0;
2500 alu.last = 1;
2501 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2502 if (r)
2503 return r;
2504 return 0;
2505 }
2506 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2507 {
2508 /* TODO from r600c, ar values don't persist between clauses */
2509 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2510 struct r600_bc_alu alu;
2511 int r;
2512 memset(&alu, 0, sizeof(struct r600_bc_alu));
2513
2514 switch (inst->Instruction.Opcode) {
2515 case TGSI_OPCODE_ARL:
2516 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2517 break;
2518 case TGSI_OPCODE_ARR:
2519 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2520 break;
2521 default:
2522 assert(0);
2523 return -1;
2524 }
2525
2526
2527 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2528 if (r)
2529 return r;
2530 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2531
2532 alu.last = 1;
2533
2534 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2535 if (r)
2536 return r;
2537 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2538 return 0;
2539 }
2540
2541 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2542 {
2543 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2544 struct r600_bc_alu alu;
2545 int i, r = 0;
2546
2547 for (i = 0; i < 4; i++) {
2548 memset(&alu, 0, sizeof(struct r600_bc_alu));
2549
2550 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2551 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2552 if (r)
2553 return r;
2554
2555 if (i == 0 || i == 3) {
2556 alu.src[0].sel = V_SQ_ALU_SRC_1;
2557 } else {
2558 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2559 if (r)
2560 return r;
2561 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2562 }
2563
2564 if (i == 0 || i == 2) {
2565 alu.src[1].sel = V_SQ_ALU_SRC_1;
2566 } else {
2567 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2568 if (r)
2569 return r;
2570 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2571 }
2572 if (i == 3)
2573 alu.last = 1;
2574 r = r600_bc_add_alu(ctx->bc, &alu);
2575 if (r)
2576 return r;
2577 }
2578 return 0;
2579 }
2580
2581 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2582 {
2583 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2584 struct r600_bc_alu alu;
2585 int r;
2586
2587 memset(&alu, 0, sizeof(struct r600_bc_alu));
2588 alu.inst = opcode;
2589 alu.predicate = 1;
2590
2591 alu.dst.sel = ctx->temp_reg;
2592 alu.dst.write = 1;
2593 alu.dst.chan = 0;
2594
2595 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2596 if (r)
2597 return r;
2598 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2599 alu.src[1].sel = V_SQ_ALU_SRC_0;
2600 alu.src[1].chan = 0;
2601
2602 alu.last = 1;
2603
2604 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2605 if (r)
2606 return r;
2607 return 0;
2608 }
2609
2610 static int pops(struct r600_shader_ctx *ctx, int pops)
2611 {
2612 int alu_pop = 3;
2613 if (ctx->bc->cf_last) {
2614 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) << 3)
2615 alu_pop = 0;
2616 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3)
2617 alu_pop = 1;
2618 }
2619 alu_pop += pops;
2620 if (alu_pop == 1) {
2621 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3;
2622 ctx->bc->force_add_cf = 1;
2623 } else if (alu_pop == 2) {
2624 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER) << 3;
2625 ctx->bc->force_add_cf = 1;
2626 } else {
2627 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2628 ctx->bc->cf_last->pop_count = pops;
2629 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2630 }
2631 return 0;
2632 }
2633
2634 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2635 {
2636 switch(reason) {
2637 case FC_PUSH_VPM:
2638 ctx->bc->callstack[ctx->bc->call_sp].current--;
2639 break;
2640 case FC_PUSH_WQM:
2641 case FC_LOOP:
2642 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2643 break;
2644 case FC_REP:
2645 /* TOODO : for 16 vp asic should -= 2; */
2646 ctx->bc->callstack[ctx->bc->call_sp].current --;
2647 break;
2648 }
2649 }
2650
2651 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2652 {
2653 if (check_max_only) {
2654 int diff;
2655 switch (reason) {
2656 case FC_PUSH_VPM:
2657 diff = 1;
2658 break;
2659 case FC_PUSH_WQM:
2660 diff = 4;
2661 break;
2662 default:
2663 assert(0);
2664 diff = 0;
2665 }
2666 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2667 ctx->bc->callstack[ctx->bc->call_sp].max) {
2668 ctx->bc->callstack[ctx->bc->call_sp].max =
2669 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2670 }
2671 return;
2672 }
2673 switch (reason) {
2674 case FC_PUSH_VPM:
2675 ctx->bc->callstack[ctx->bc->call_sp].current++;
2676 break;
2677 case FC_PUSH_WQM:
2678 case FC_LOOP:
2679 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2680 break;
2681 case FC_REP:
2682 ctx->bc->callstack[ctx->bc->call_sp].current++;
2683 break;
2684 }
2685
2686 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2687 ctx->bc->callstack[ctx->bc->call_sp].max) {
2688 ctx->bc->callstack[ctx->bc->call_sp].max =
2689 ctx->bc->callstack[ctx->bc->call_sp].current;
2690 }
2691 }
2692
2693 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2694 {
2695 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2696
2697 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2698 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2699 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2700 sp->num_mid++;
2701 }
2702
2703 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2704 {
2705 ctx->bc->fc_sp++;
2706 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2707 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2708 }
2709
2710 static void fc_poplevel(struct r600_shader_ctx *ctx)
2711 {
2712 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2713 if (sp->mid) {
2714 free(sp->mid);
2715 sp->mid = NULL;
2716 }
2717 sp->num_mid = 0;
2718 sp->start = NULL;
2719 sp->type = 0;
2720 ctx->bc->fc_sp--;
2721 }
2722
2723 #if 0
2724 static int emit_return(struct r600_shader_ctx *ctx)
2725 {
2726 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2727 return 0;
2728 }
2729
2730 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2731 {
2732
2733 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2734 ctx->bc->cf_last->pop_count = pops;
2735 /* TODO work out offset */
2736 return 0;
2737 }
2738
2739 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2740 {
2741 return 0;
2742 }
2743
2744 static void emit_testflag(struct r600_shader_ctx *ctx)
2745 {
2746
2747 }
2748
2749 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2750 {
2751 emit_testflag(ctx);
2752 emit_jump_to_offset(ctx, 1, 4);
2753 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2754 pops(ctx, ifidx + 1);
2755 emit_return(ctx);
2756 }
2757
2758 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2759 {
2760 emit_testflag(ctx);
2761
2762 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2763 ctx->bc->cf_last->pop_count = 1;
2764
2765 fc_set_mid(ctx, fc_sp);
2766
2767 pops(ctx, 1);
2768 }
2769 #endif
2770
2771 static int tgsi_if(struct r600_shader_ctx *ctx)
2772 {
2773 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2774
2775 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2776
2777 fc_pushlevel(ctx, FC_IF);
2778
2779 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2780 return 0;
2781 }
2782
2783 static int tgsi_else(struct r600_shader_ctx *ctx)
2784 {
2785 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2786 ctx->bc->cf_last->pop_count = 1;
2787
2788 fc_set_mid(ctx, ctx->bc->fc_sp);
2789 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2790 return 0;
2791 }
2792
2793 static int tgsi_endif(struct r600_shader_ctx *ctx)
2794 {
2795 pops(ctx, 1);
2796 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2797 R600_ERR("if/endif unbalanced in shader\n");
2798 return -1;
2799 }
2800
2801 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2802 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2803 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2804 } else {
2805 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2806 }
2807 fc_poplevel(ctx);
2808
2809 callstack_decrease_current(ctx, FC_PUSH_VPM);
2810 return 0;
2811 }
2812
2813 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2814 {
2815 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2816
2817 fc_pushlevel(ctx, FC_LOOP);
2818
2819 /* check stack depth */
2820 callstack_check_depth(ctx, FC_LOOP, 0);
2821 return 0;
2822 }
2823
2824 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2825 {
2826 int i;
2827
2828 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2829
2830 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2831 R600_ERR("loop/endloop in shader code are not paired.\n");
2832 return -EINVAL;
2833 }
2834
2835 /* fixup loop pointers - from r600isa
2836 LOOP END points to CF after LOOP START,
2837 LOOP START point to CF after LOOP END
2838 BRK/CONT point to LOOP END CF
2839 */
2840 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2841
2842 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2843
2844 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2845 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2846 }
2847 /* TODO add LOOPRET support */
2848 fc_poplevel(ctx);
2849 callstack_decrease_current(ctx, FC_LOOP);
2850 return 0;
2851 }
2852
2853 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2854 {
2855 unsigned int fscp;
2856
2857 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2858 {
2859 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2860 break;
2861 }
2862
2863 if (fscp == 0) {
2864 R600_ERR("Break not inside loop/endloop pair\n");
2865 return -EINVAL;
2866 }
2867
2868 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2869 ctx->bc->cf_last->pop_count = 1;
2870
2871 fc_set_mid(ctx, fscp);
2872
2873 pops(ctx, 1);
2874 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2875 return 0;
2876 }
2877
2878 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2879 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2880 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2881 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2882
2883 /* FIXME:
2884 * For state trackers other than OpenGL, we'll want to use
2885 * _RECIP_IEEE instead.
2886 */
2887 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2888
2889 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2890 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2891 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2892 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2893 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2894 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2895 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2896 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2897 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2898 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2899 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2900 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2901 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2902 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2903 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2904 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 /* gap */
2906 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2908 /* gap */
2909 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2910 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2911 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2912 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2914 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2916 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2917 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2918 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2919 /* gap */
2920 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2921 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2922 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2924 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2925 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2926 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2927 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2928 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2932 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2934 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2936 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2937 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2938 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2939 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2941 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2943 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2950 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2954 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2955 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2956 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2957 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2958 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2960 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2961 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2962 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2963 /* gap */
2964 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2967 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2968 /* gap */
2969 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2977 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 /* gap */
2979 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2988 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2991 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2993 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 /* gap */
2995 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 /* gap */
3001 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3010 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3011 /* gap */
3012 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3015 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3026 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3027 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3028 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3029 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3037 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3039 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3040 };
3041
3042 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3043 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3044 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3045 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3046 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3047 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3048 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3049 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3051 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3052 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3053 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3054 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3055 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3056 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3057 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3058 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3059 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3060 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3061 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3062 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 /* gap */
3064 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 /* gap */
3067 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3069 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3070 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3072 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3074 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3075 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3076 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3077 /* gap */
3078 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3079 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3080 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3082 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3083 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3084 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3085 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3086 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3092 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3094 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3095 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3096 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3097 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3099 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3101 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3106 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3107 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3108 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3112 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3113 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3114 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3115 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3116 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3118 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3119 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3120 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3121 /* gap */
3122 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3125 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3126 /* gap */
3127 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3132 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3135 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 /* gap */
3137 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3143 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3146 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3147 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3149 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3151 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 /* gap */
3153 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3154 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3156 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3157 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3158 /* gap */
3159 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3160 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3161 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3162 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3163 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3164 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3166 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3167 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3168 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3169 /* gap */
3170 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3171 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3172 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3173 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3174 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3176 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3177 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3178 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3179 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3180 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3181 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3182 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3183 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3184 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3185 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3186 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3187 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3188 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3189 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3190 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3191 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3192 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3193 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3194 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3195 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3196 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3197 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3198 };