2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
38 struct r600_shader_tgsi_instruction
;
40 struct r600_shader_ctx
{
41 struct tgsi_shader_info info
;
42 struct tgsi_parse_context parse
;
43 const struct tgsi_token
*tokens
;
45 unsigned file_offset
[TGSI_FILE_COUNT
];
47 struct r600_shader_tgsi_instruction
*inst_info
;
49 struct r600_shader
*shader
;
53 u32 max_driver_temp_used
;
56 struct r600_shader_tgsi_instruction
{
60 int (*process
)(struct r600_shader_ctx
*ctx
);
63 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[];
64 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
66 static int r600_shader_update(struct pipe_context
*ctx
, struct r600_shader
*shader
)
68 struct r600_context
*rctx
= r600_context(ctx
);
69 const struct util_format_description
*desc
;
70 enum pipe_format resource_format
[160];
71 unsigned i
, nresources
= 0;
72 struct r600_bc
*bc
= &shader
->bc
;
73 struct r600_bc_cf
*cf
;
74 struct r600_bc_vtx
*vtx
;
76 if (shader
->processor_type
!= TGSI_PROCESSOR_VERTEX
)
78 for (i
= 0; i
< rctx
->vertex_elements
->count
; i
++) {
79 resource_format
[nresources
++] = rctx
->vertex_elements
->elements
[i
].src_format
;
81 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
83 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
84 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
85 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
86 desc
= util_format_description(resource_format
[vtx
->buffer_id
]);
88 R600_ERR("unknown format %d\n", resource_format
[vtx
->buffer_id
]);
91 vtx
->dst_sel_x
= desc
->swizzle
[0];
92 vtx
->dst_sel_y
= desc
->swizzle
[1];
93 vtx
->dst_sel_z
= desc
->swizzle
[2];
94 vtx
->dst_sel_w
= desc
->swizzle
[3];
101 return r600_bc_build(&shader
->bc
);
104 int r600_pipe_shader_create(struct pipe_context
*ctx
,
105 struct r600_context_state
*rpshader
,
106 const struct tgsi_token
*tokens
)
108 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
111 //fprintf(stderr, "--------------------------------------------------------------\n");
112 //tgsi_dump(tokens, 0);
113 if (rpshader
== NULL
)
115 rpshader
->shader
.family
= radeon_get_family(rscreen
->rw
);
116 r
= r600_shader_from_tgsi(tokens
, &rpshader
->shader
);
118 R600_ERR("translation from TGSI failed !\n");
121 r
= r600_bc_build(&rpshader
->shader
.bc
);
123 R600_ERR("building bytecode failed !\n");
126 //fprintf(stderr, "______________________________________________________________\n");
130 static int r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
132 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
133 struct r600_shader
*rshader
= &rpshader
->shader
;
134 struct radeon_state
*state
;
137 state
= &rpshader
->rstate
;
138 radeon_state_fini(&rpshader
->rstate
);
139 radeon_state_init(state
, rscreen
->rw
, R600_STATE_SHADER
, 0, R600_SHADER_VS
);
140 for (i
= 0; i
< 10; i
++) {
141 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
] = 0;
143 /* so far never got proper semantic id from tgsi */
144 for (i
= 0; i
< 32; i
++) {
145 tmp
= i
<< ((i
& 3) * 8);
146 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
/ 4] |= tmp
;
148 state
->states
[R600_VS_SHADER__SPI_VS_OUT_CONFIG
] = S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2);
149 state
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
150 S_028868_STACK_SIZE(rshader
->bc
.nstack
);
151 state
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
152 state
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
154 state
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
155 state
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
156 return radeon_state_pm4(state
);
159 static int r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
161 const struct pipe_rasterizer_state
*rasterizer
;
162 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
163 struct r600_shader
*rshader
= &rpshader
->shader
;
164 struct r600_context
*rctx
= r600_context(ctx
);
165 struct radeon_state
*state
;
166 unsigned i
, tmp
, exports_ps
, num_cout
;
167 boolean have_pos
= FALSE
;
169 state
= &rpshader
->rstate
;
170 rasterizer
= &rctx
->rasterizer
->state
.rasterizer
;
171 radeon_state_fini(state
);
172 radeon_state_init(state
, rscreen
->rw
, R600_STATE_SHADER
, 0, R600_SHADER_PS
);
173 for (i
= 0; i
< rshader
->ninput
; i
++) {
174 tmp
= S_028644_SEMANTIC(i
);
175 tmp
|= S_028644_SEL_CENTROID(1);
176 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
178 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
179 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
||
180 rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
) {
181 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
183 if (rasterizer
->sprite_coord_enable
& (1 << i
)) {
184 tmp
|= S_028644_PT_SPRITE_TEX(1);
186 state
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
+ i
] = tmp
;
191 for (i
= 0; i
< rshader
->noutput
; i
++) {
192 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
194 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
195 exports_ps
|= (1 << (num_cout
+1));
200 /* always at least export 1 component per pixel */
203 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] = S_0286CC_NUM_INTERP(rshader
->ninput
) |
204 S_0286CC_PERSP_GRADIENT_ENA(1);
206 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] |= S_0286CC_POSITION_ENA(1) |
207 S_0286CC_BARYC_SAMPLE_CNTL(1);
208 state
->states
[R600_PS_SHADER__SPI_INPUT_Z
] |= 1;
210 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_1
] = 0x00000000;
211 state
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
212 S_028868_STACK_SIZE(rshader
->bc
.nstack
);
213 state
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = exports_ps
;
214 state
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
216 state
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
217 return radeon_state_pm4(state
);
220 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
222 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
223 struct r600_context
*rctx
= r600_context(ctx
);
224 struct r600_shader
*rshader
= &rpshader
->shader
;
227 /* copy new shader */
228 radeon_bo_decref(rscreen
->rw
, rpshader
->bo
);
230 rpshader
->bo
= radeon_bo(rscreen
->rw
, 0, rshader
->bc
.ndw
* 4,
232 if (rpshader
->bo
== NULL
) {
235 radeon_bo_map(rscreen
->rw
, rpshader
->bo
);
236 memcpy(rpshader
->bo
->data
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
237 radeon_bo_unmap(rscreen
->rw
, rpshader
->bo
);
239 rshader
->flat_shade
= rctx
->flat_shade
;
240 switch (rshader
->processor_type
) {
241 case TGSI_PROCESSOR_VERTEX
:
242 r
= r600_pipe_shader_vs(ctx
, rpshader
);
244 case TGSI_PROCESSOR_FRAGMENT
:
245 r
= r600_pipe_shader_ps(ctx
, rpshader
);
254 int r600_pipe_shader_update(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
256 struct r600_context
*rctx
= r600_context(ctx
);
259 if (rpshader
== NULL
)
261 /* there should be enough input */
262 if (rctx
->vertex_elements
->count
< rpshader
->shader
.bc
.nresource
) {
263 R600_ERR("%d resources provided, expecting %d\n",
264 rctx
->vertex_elements
->count
, rpshader
->shader
.bc
.nresource
);
267 r
= r600_shader_update(ctx
, &rpshader
->shader
);
270 return r600_pipe_shader(ctx
, rpshader
);
273 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
275 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
278 if (i
->Instruction
.NumDstRegs
> 1) {
279 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
282 if (i
->Instruction
.Predicate
) {
283 R600_ERR("predicate unsupported\n");
287 if (i
->Instruction
.Label
) {
288 R600_ERR("label unsupported\n");
292 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
293 if (i
->Src
[j
].Register
.Dimension
||
294 i
->Src
[j
].Register
.Absolute
) {
295 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j
,
296 i
->Src
[j
].Register
.Dimension
,
297 i
->Src
[j
].Register
.Absolute
);
301 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
302 if (i
->Dst
[j
].Register
.Dimension
) {
303 R600_ERR("unsupported dst (dimension)\n");
310 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
312 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
313 struct r600_bc_vtx vtx
;
317 switch (d
->Declaration
.File
) {
318 case TGSI_FILE_INPUT
:
319 i
= ctx
->shader
->ninput
++;
320 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
321 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
322 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
323 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
324 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
325 /* turn input into fetch */
326 memset(&vtx
, 0, sizeof(struct r600_bc_vtx
));
330 /* register containing the index into the buffer */
333 vtx
.mega_fetch_count
= 0x1F;
334 vtx
.dst_gpr
= ctx
->shader
->input
[i
].gpr
;
339 r
= r600_bc_add_vtx(ctx
->bc
, &vtx
);
344 case TGSI_FILE_OUTPUT
:
345 i
= ctx
->shader
->noutput
++;
346 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
347 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
348 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
349 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
351 case TGSI_FILE_CONSTANT
:
352 case TGSI_FILE_TEMPORARY
:
353 case TGSI_FILE_SAMPLER
:
354 case TGSI_FILE_ADDRESS
:
357 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
363 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
365 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
368 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
370 struct tgsi_full_immediate
*immediate
;
371 struct r600_shader_ctx ctx
;
372 struct r600_bc_output output
[32];
373 unsigned output_done
, noutput
;
377 ctx
.bc
= &shader
->bc
;
379 r
= r600_bc_init(ctx
.bc
, shader
->family
);
383 tgsi_scan_shader(tokens
, &ctx
.info
);
384 tgsi_parse_init(&ctx
.parse
, tokens
);
385 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
386 shader
->processor_type
= ctx
.type
;
388 /* register allocations */
389 /* Values [0,127] correspond to GPR[0..127].
390 * Values [128,159] correspond to constant buffer bank 0
391 * Values [160,191] correspond to constant buffer bank 1
392 * Values [256,511] correspond to cfile constants c[0..255].
393 * Other special values are shown in the list below.
394 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
395 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
396 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
397 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
398 * 248 SQ_ALU_SRC_0: special constant 0.0.
399 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
400 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
401 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
402 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
403 * 253 SQ_ALU_SRC_LITERAL: literal constant.
404 * 254 SQ_ALU_SRC_PV: previous vector result.
405 * 255 SQ_ALU_SRC_PS: previous scalar result.
407 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
408 ctx
.file_offset
[i
] = 0;
410 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
411 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
413 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
414 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
415 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
416 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
417 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 256;
418 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = 253;
419 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
420 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
425 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
426 tgsi_parse_token(&ctx
.parse
);
427 switch (ctx
.parse
.FullToken
.Token
.Type
) {
428 case TGSI_TOKEN_TYPE_IMMEDIATE
:
429 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
430 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
431 if(ctx
.literals
== NULL
) {
435 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
436 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
437 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
438 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
441 case TGSI_TOKEN_TYPE_DECLARATION
:
442 r
= tgsi_declaration(&ctx
);
446 case TGSI_TOKEN_TYPE_INSTRUCTION
:
447 r
= tgsi_is_supported(&ctx
);
450 ctx
.max_driver_temp_used
= 0;
451 /* reserve first tmp for everyone */
453 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
454 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
455 r
= ctx
.inst_info
->process(&ctx
);
458 r
= r600_bc_add_literal(ctx
.bc
, ctx
.value
);
463 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
469 noutput
= shader
->noutput
;
470 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
471 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
472 output
[i
].gpr
= shader
->output
[i
].gpr
;
473 output
[i
].elem_size
= 3;
474 output
[i
].swizzle_x
= 0;
475 output
[i
].swizzle_y
= 1;
476 output
[i
].swizzle_z
= 2;
477 output
[i
].swizzle_w
= 3;
478 output
[i
].barrier
= 1;
479 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
480 output
[i
].array_base
= i
- pos0
;
481 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
483 case TGSI_PROCESSOR_VERTEX
:
484 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
485 output
[i
].array_base
= 60;
486 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
487 /* position doesn't count in array_base */
490 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
491 output
[i
].array_base
= 61;
492 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
493 /* position doesn't count in array_base */
497 case TGSI_PROCESSOR_FRAGMENT
:
498 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
499 output
[i
].array_base
= shader
->output
[i
].sid
;
500 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
501 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
502 output
[i
].array_base
= 61;
503 output
[i
].swizzle_x
= 2;
504 output
[i
].swizzle_y
= output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
505 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
507 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
513 R600_ERR("unsupported processor type %d\n", ctx
.type
);
518 /* add fake param output for vertex shader if no param is exported */
519 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
520 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
521 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
527 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
529 output
[i
].elem_size
= 3;
530 output
[i
].swizzle_x
= 0;
531 output
[i
].swizzle_y
= 1;
532 output
[i
].swizzle_z
= 2;
533 output
[i
].swizzle_w
= 3;
534 output
[i
].barrier
= 1;
535 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
536 output
[i
].array_base
= 0;
537 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
541 /* add fake pixel export */
542 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
543 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
545 output
[0].elem_size
= 3;
546 output
[0].swizzle_x
= 7;
547 output
[0].swizzle_y
= 7;
548 output
[0].swizzle_z
= 7;
549 output
[0].swizzle_w
= 7;
550 output
[0].barrier
= 1;
551 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
552 output
[0].array_base
= 0;
553 output
[0].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
556 /* set export done on last export of each type */
557 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
558 if (i
== (noutput
- 1)) {
559 output
[i
].end_of_program
= 1;
561 if (!(output_done
& (1 << output
[i
].type
))) {
562 output_done
|= (1 << output
[i
].type
);
563 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
;
566 /* add output to bytecode */
567 for (i
= 0; i
< noutput
; i
++) {
568 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
573 tgsi_parse_free(&ctx
.parse
);
577 tgsi_parse_free(&ctx
.parse
);
581 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
583 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
587 static int tgsi_end(struct r600_shader_ctx
*ctx
)
592 static int tgsi_src(struct r600_shader_ctx
*ctx
,
593 const struct tgsi_full_src_register
*tgsi_src
,
594 struct r600_bc_alu_src
*r600_src
)
597 memset(r600_src
, 0, sizeof(struct r600_bc_alu_src
));
598 r600_src
->sel
= tgsi_src
->Register
.Index
;
599 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
601 index
= tgsi_src
->Register
.Index
;
602 ctx
->value
[0] = ctx
->literals
[index
* 4 + 0];
603 ctx
->value
[1] = ctx
->literals
[index
* 4 + 1];
604 ctx
->value
[2] = ctx
->literals
[index
* 4 + 2];
605 ctx
->value
[3] = ctx
->literals
[index
* 4 + 3];
607 if (tgsi_src
->Register
.Indirect
)
608 r600_src
->rel
= V_SQ_REL_RELATIVE
;
609 r600_src
->neg
= tgsi_src
->Register
.Negate
;
610 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
614 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
615 const struct tgsi_full_dst_register
*tgsi_dst
,
617 struct r600_bc_alu_dst
*r600_dst
)
619 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
621 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
622 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
623 r600_dst
->chan
= swizzle
;
625 if (tgsi_dst
->Register
.Indirect
)
626 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
627 if (inst
->Instruction
.Saturate
) {
633 static unsigned tgsi_chan(const struct tgsi_full_src_register
*tgsi_src
, unsigned swizzle
)
637 return tgsi_src
->Register
.SwizzleX
;
639 return tgsi_src
->Register
.SwizzleY
;
641 return tgsi_src
->Register
.SwizzleZ
;
643 return tgsi_src
->Register
.SwizzleW
;
649 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
651 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
652 struct r600_bc_alu alu
;
653 int i
, j
, k
, nconst
, r
;
655 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
656 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
659 r
= tgsi_src(ctx
, &inst
->Src
[i
], &r600_src
[i
]);
664 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
665 if (inst
->Src
[j
].Register
.File
== TGSI_FILE_CONSTANT
&& j
> 0) {
666 int treg
= r600_get_temp(ctx
);
667 for (k
= 0; k
< 4; k
++) {
668 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
669 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
670 alu
.src
[0].sel
= r600_src
[j
].sel
;
677 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
681 r600_src
[j
].sel
= treg
;
688 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
689 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
691 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
692 struct r600_bc_alu alu
;
693 int i
, j
, k
, nliteral
, r
;
695 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
696 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_IMMEDIATE
) {
700 for (i
= 0, j
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
701 if (inst
->Src
[j
].Register
.File
== TGSI_FILE_IMMEDIATE
) {
702 int treg
= r600_get_temp(ctx
);
703 for (k
= 0; k
< 4; k
++) {
704 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
705 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
706 alu
.src
[0].sel
= r600_src
[j
].sel
;
713 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
717 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
720 r600_src
[j
].sel
= treg
;
727 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
)
729 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
730 struct r600_bc_alu_src r600_src
[3];
731 struct r600_bc_alu alu
;
735 for (i
= 0; i
< 4; i
++) {
736 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
741 r
= tgsi_split_constant(ctx
, r600_src
);
744 for (i
= 0; i
< lasti
+ 1; i
++) {
745 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
748 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
749 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
753 alu
.inst
= ctx
->inst_info
->r600_opcode
;
755 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
756 alu
.src
[j
] = r600_src
[j
];
757 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
760 alu
.src
[0] = r600_src
[1];
761 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
763 alu
.src
[1] = r600_src
[0];
764 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
766 /* handle some special cases */
767 switch (ctx
->inst_info
->tgsi_opcode
) {
768 case TGSI_OPCODE_SUB
:
771 case TGSI_OPCODE_ABS
:
780 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
787 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
789 return tgsi_op2_s(ctx
, 0);
792 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
794 return tgsi_op2_s(ctx
, 1);
798 * r600 - trunc to -PI..PI range
799 * r700 - normalize by dividing by 2PI
802 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
,
803 struct r600_bc_alu_src r600_src
[3])
805 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
807 uint32_t lit_vals
[4];
808 struct r600_bc_alu alu
;
810 memset(lit_vals
, 0, 4*4);
811 r
= tgsi_split_constant(ctx
, r600_src
);
815 r
= tgsi_split_literal_constant(ctx
, r600_src
);
819 lit_vals
[0] = fui(1.0 /(3.1415926535 * 2));
820 lit_vals
[1] = fui(0.5f
);
822 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
823 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
827 alu
.dst
.sel
= ctx
->temp_reg
;
830 alu
.src
[0] = r600_src
[0];
831 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
833 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
835 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
838 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
841 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
845 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
846 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
;
849 alu
.dst
.sel
= ctx
->temp_reg
;
852 alu
.src
[0].sel
= ctx
->temp_reg
;
855 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
859 if (ctx
->bc
->chiprev
== 0) {
860 lit_vals
[0] = fui(3.1415926535897f
* 2.0f
);
861 lit_vals
[1] = fui(-3.1415926535897f
);
863 lit_vals
[0] = fui(1.0f
);
864 lit_vals
[1] = fui(-0.5f
);
867 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
868 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
872 alu
.dst
.sel
= ctx
->temp_reg
;
875 alu
.src
[0].sel
= ctx
->temp_reg
;
878 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
880 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
883 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
886 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
892 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
894 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
895 struct r600_bc_alu_src r600_src
[3];
896 struct r600_bc_alu alu
;
900 r
= tgsi_setup_trig(ctx
, r600_src
);
904 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
905 alu
.inst
= ctx
->inst_info
->r600_opcode
;
907 alu
.dst
.sel
= ctx
->temp_reg
;
910 alu
.src
[0].sel
= ctx
->temp_reg
;
913 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
917 /* replicate result */
918 for (i
= 0; i
< 4; i
++) {
919 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
))
922 for (i
= 0; i
< lasti
+ 1; i
++) {
923 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
926 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
927 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
929 alu
.src
[0].sel
= ctx
->temp_reg
;
930 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
935 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
942 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
944 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
945 struct r600_bc_alu_src r600_src
[3];
946 struct r600_bc_alu alu
;
949 r
= tgsi_setup_trig(ctx
, r600_src
);
955 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
956 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
;
957 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
961 alu
.src
[0].sel
= ctx
->temp_reg
;
964 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
969 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
970 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
;
971 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
975 alu
.src
[0].sel
= ctx
->temp_reg
;
978 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
984 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
986 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
987 struct r600_bc_alu alu
;
990 for (i
= 0; i
< 4; i
++) {
991 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
992 alu
.inst
= ctx
->inst_info
->r600_opcode
;
996 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
998 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILP
) {
999 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1002 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1005 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1010 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1014 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1018 /* kill must be last in ALU */
1019 ctx
->bc
->force_add_cf
= 1;
1020 ctx
->shader
->uses_kill
= TRUE
;
1024 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
1026 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1027 struct r600_bc_alu alu
;
1028 struct r600_bc_alu_src r600_src
[3];
1031 r
= tgsi_split_constant(ctx
, r600_src
);
1034 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1039 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1040 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1041 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
1042 alu
.src
[0].chan
= 0;
1043 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1046 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
1047 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1051 /* dst.y = max(src.x, 0.0) */
1052 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1053 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
;
1054 alu
.src
[0] = r600_src
[0];
1055 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
1056 alu
.src
[1].chan
= 0;
1057 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1060 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
1061 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1066 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1067 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1068 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1069 alu
.src
[0].chan
= 0;
1070 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1073 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
1075 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1079 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1083 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
1088 /* dst.z = log(src.y) */
1089 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1090 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
;
1091 alu
.src
[0] = r600_src
[0];
1092 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
1093 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1097 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1101 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1105 chan
= alu
.dst
.chan
;
1108 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1109 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1110 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
1111 alu
.src
[0] = r600_src
[0];
1112 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1113 alu
.src
[1].sel
= sel
;
1114 alu
.src
[1].chan
= chan
;
1116 alu
.src
[2] = r600_src
[0];
1117 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], 0);
1118 alu
.dst
.sel
= ctx
->temp_reg
;
1123 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1127 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1130 /* dst.z = exp(tmp.x) */
1131 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1132 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
1133 alu
.src
[0].sel
= ctx
->temp_reg
;
1134 alu
.src
[0].chan
= 0;
1135 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1139 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1146 static int tgsi_trans(struct r600_shader_ctx
*ctx
)
1148 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1149 struct r600_bc_alu alu
;
1152 for (i
= 0; i
< 4; i
++) {
1153 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1154 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
1155 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1156 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1157 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
1160 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1162 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1166 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1174 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
1176 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1177 struct r600_bc_alu alu
;
1180 for (i
= 0; i
< 4; i
++) {
1181 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1182 alu
.src
[0].sel
= ctx
->temp_reg
;
1183 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1185 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1188 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1191 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1198 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
1200 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1201 struct r600_bc_alu alu
;
1204 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1205 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1206 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1207 r
= tgsi_src(ctx
, &inst
->Src
[i
], &alu
.src
[i
]);
1210 alu
.src
[i
].chan
= tgsi_chan(&inst
->Src
[i
], 0);
1212 alu
.dst
.sel
= ctx
->temp_reg
;
1215 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1218 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1221 /* replicate result */
1222 return tgsi_helper_tempx_replicate(ctx
);
1225 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
1227 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1228 struct r600_bc_alu alu
;
1232 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1233 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
;
1234 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1237 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1238 alu
.dst
.sel
= ctx
->temp_reg
;
1241 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1244 r
= r600_bc_add_literal(ctx
->bc
,ctx
->value
);
1248 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1249 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE
;
1250 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[0]);
1253 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], 0);
1254 alu
.src
[1].sel
= ctx
->temp_reg
;
1255 alu
.dst
.sel
= ctx
->temp_reg
;
1258 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1261 r
= r600_bc_add_literal(ctx
->bc
,ctx
->value
);
1264 /* POW(a,b) = EXP2(b * LOG2(a))*/
1265 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1266 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
1267 alu
.src
[0].sel
= ctx
->temp_reg
;
1268 alu
.dst
.sel
= ctx
->temp_reg
;
1271 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1274 r
= r600_bc_add_literal(ctx
->bc
,ctx
->value
);
1277 return tgsi_helper_tempx_replicate(ctx
);
1280 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
1282 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1283 struct r600_bc_alu alu
;
1284 struct r600_bc_alu_src r600_src
[3];
1287 r
= tgsi_split_constant(ctx
, r600_src
);
1291 /* tmp = (src > 0 ? 1 : src) */
1292 for (i
= 0; i
< 4; i
++) {
1293 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1294 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
;
1297 alu
.dst
.sel
= ctx
->temp_reg
;
1300 alu
.src
[0] = r600_src
[0];
1301 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1303 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1305 alu
.src
[2] = r600_src
[0];
1306 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], i
);
1309 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1313 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1317 /* dst = (-tmp > 0 ? -1 : tmp) */
1318 for (i
= 0; i
< 4; i
++) {
1319 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1320 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
;
1322 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1326 alu
.src
[0].sel
= ctx
->temp_reg
;
1327 alu
.src
[0].chan
= i
;
1330 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1333 alu
.src
[2].sel
= ctx
->temp_reg
;
1334 alu
.src
[2].chan
= i
;
1338 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1345 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
1347 struct r600_bc_alu alu
;
1350 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1353 for (i
= 0; i
< 4; i
++) {
1354 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1355 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
1356 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
1359 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1360 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1363 alu
.src
[0].sel
= ctx
->temp_reg
;
1364 alu
.src
[0].chan
= i
;
1369 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1376 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
1378 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1379 struct r600_bc_alu_src r600_src
[3];
1380 struct r600_bc_alu alu
;
1383 r
= tgsi_split_constant(ctx
, r600_src
);
1386 /* do it in 2 step as op3 doesn't support writemask */
1387 for (i
= 0; i
< 4; i
++) {
1388 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1389 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1390 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1391 alu
.src
[j
] = r600_src
[j
];
1392 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1394 alu
.dst
.sel
= ctx
->temp_reg
;
1401 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1405 return tgsi_helper_copy(ctx
, inst
);
1408 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
1410 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1411 struct r600_bc_alu_src r600_src
[3];
1412 struct r600_bc_alu alu
;
1415 r
= tgsi_split_constant(ctx
, r600_src
);
1418 for (i
= 0; i
< 4; i
++) {
1419 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1420 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1421 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1422 alu
.src
[j
] = r600_src
[j
];
1423 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1425 alu
.dst
.sel
= ctx
->temp_reg
;
1428 /* handle some special cases */
1429 switch (ctx
->inst_info
->tgsi_opcode
) {
1430 case TGSI_OPCODE_DP2
:
1432 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1433 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1436 case TGSI_OPCODE_DP3
:
1438 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1439 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1442 case TGSI_OPCODE_DPH
:
1444 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1445 alu
.src
[0].chan
= 0;
1455 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1459 return tgsi_helper_copy(ctx
, inst
);
1462 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1464 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1465 struct r600_bc_tex tex
;
1466 struct r600_bc_alu alu
;
1470 boolean src_not_temp
= inst
->Src
[0].Register
.File
!= TGSI_FILE_TEMPORARY
;
1471 uint32_t lit_vals
[4];
1473 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1475 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1476 /* Add perspective divide */
1477 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1478 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
1479 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1483 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1484 alu
.dst
.sel
= ctx
->temp_reg
;
1488 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1492 for (i
= 0; i
< 3; i
++) {
1493 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1494 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1495 alu
.src
[0].sel
= ctx
->temp_reg
;
1496 alu
.src
[0].chan
= 3;
1497 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1500 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1501 alu
.dst
.sel
= ctx
->temp_reg
;
1504 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1508 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1509 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1510 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1511 alu
.src
[0].chan
= 0;
1512 alu
.dst
.sel
= ctx
->temp_reg
;
1516 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1519 src_not_temp
= false;
1520 src_gpr
= ctx
->temp_reg
;
1523 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1524 int src_chan
, src2_chan
;
1526 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1527 for (i
= 0; i
< 4; i
++) {
1528 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1529 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
;
1548 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1551 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], src_chan
);
1552 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1555 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], src2_chan
);
1556 alu
.dst
.sel
= ctx
->temp_reg
;
1561 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1566 /* tmp1.z = RCP_e(|tmp1.z|) */
1567 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1568 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
1569 alu
.src
[0].sel
= ctx
->temp_reg
;
1570 alu
.src
[0].chan
= 2;
1572 alu
.dst
.sel
= ctx
->temp_reg
;
1576 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1580 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1581 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1582 * muladd has no writemask, have to use another temp
1584 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1585 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1588 alu
.src
[0].sel
= ctx
->temp_reg
;
1589 alu
.src
[0].chan
= 0;
1590 alu
.src
[1].sel
= ctx
->temp_reg
;
1591 alu
.src
[1].chan
= 2;
1593 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1594 alu
.src
[2].chan
= 0;
1596 alu
.dst
.sel
= ctx
->temp_reg
;
1600 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1604 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1605 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1608 alu
.src
[0].sel
= ctx
->temp_reg
;
1609 alu
.src
[0].chan
= 1;
1610 alu
.src
[1].sel
= ctx
->temp_reg
;
1611 alu
.src
[1].chan
= 2;
1613 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1614 alu
.src
[2].chan
= 0;
1616 alu
.dst
.sel
= ctx
->temp_reg
;
1621 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1625 lit_vals
[0] = fui(1.5f
);
1627 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
1630 src_not_temp
= false;
1631 src_gpr
= ctx
->temp_reg
;
1635 for (i
= 0; i
< 4; i
++) {
1636 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1637 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1638 alu
.src
[0].sel
= src_gpr
;
1639 alu
.src
[0].chan
= i
;
1640 alu
.dst
.sel
= ctx
->temp_reg
;
1645 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1649 src_gpr
= ctx
->temp_reg
;
1652 opcode
= ctx
->inst_info
->r600_opcode
;
1653 if (opcode
== SQ_TEX_INST_SAMPLE
&&
1654 (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
))
1655 opcode
= SQ_TEX_INST_SAMPLE_C
;
1657 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1659 tex
.resource_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1660 tex
.sampler_id
= tex
.resource_id
;
1661 tex
.src_gpr
= src_gpr
;
1662 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1672 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1679 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1680 tex
.coord_type_x
= 1;
1681 tex
.coord_type_y
= 1;
1682 tex
.coord_type_z
= 1;
1683 tex
.coord_type_w
= 1;
1686 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
)
1687 tex
.coord_type_w
= 2;
1689 r
= r600_bc_add_tex(ctx
->bc
, &tex
);
1693 /* add shadow ambient support - gallium doesn't do it yet */
1698 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1700 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1701 struct r600_bc_alu_src r600_src
[3];
1702 struct r600_bc_alu alu
;
1706 r
= tgsi_split_constant(ctx
, r600_src
);
1710 for (i
= 0; i
< 4; i
++) {
1711 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1712 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
;
1713 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1714 alu
.src
[0].chan
= 0;
1715 alu
.src
[1] = r600_src
[0];
1716 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1718 alu
.dst
.sel
= ctx
->temp_reg
;
1724 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1728 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1732 /* (1 - src0) * src2 */
1733 for (i
= 0; i
< 4; i
++) {
1734 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1735 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1736 alu
.src
[0].sel
= ctx
->temp_reg
;
1737 alu
.src
[0].chan
= i
;
1738 alu
.src
[1] = r600_src
[2];
1739 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1740 alu
.dst
.sel
= ctx
->temp_reg
;
1746 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1750 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1754 /* src0 * src1 + (1 - src0) * src2 */
1755 for (i
= 0; i
< 4; i
++) {
1756 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1757 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1759 alu
.src
[0] = r600_src
[0];
1760 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1761 alu
.src
[1] = r600_src
[1];
1762 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
1763 alu
.src
[2].sel
= ctx
->temp_reg
;
1764 alu
.src
[2].chan
= i
;
1765 alu
.dst
.sel
= ctx
->temp_reg
;
1770 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1774 return tgsi_helper_copy(ctx
, inst
);
1777 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
1779 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1780 struct r600_bc_alu_src r600_src
[3];
1781 struct r600_bc_alu alu
;
1785 r
= tgsi_split_constant(ctx
, r600_src
);
1789 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
1792 for (i
= 0; i
< 4; i
++) {
1793 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1794 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
;
1795 alu
.src
[0] = r600_src
[0];
1796 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1798 alu
.src
[1] = r600_src
[2];
1799 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1801 alu
.src
[2] = r600_src
[1];
1802 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[1], i
);
1805 alu
.dst
.sel
= ctx
->temp_reg
;
1807 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1816 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1821 return tgsi_helper_copy(ctx
, inst
);
1825 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
1827 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1828 struct r600_bc_alu_src r600_src
[3];
1829 struct r600_bc_alu alu
;
1830 uint32_t use_temp
= 0;
1833 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
1836 r
= tgsi_split_constant(ctx
, r600_src
);
1840 for (i
= 0; i
< 4; i
++) {
1841 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1842 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1844 alu
.src
[0] = r600_src
[0];
1847 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
1850 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1853 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
1856 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1857 alu
.src
[0].chan
= i
;
1860 alu
.src
[1] = r600_src
[1];
1863 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
1866 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
1869 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
1872 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1873 alu
.src
[1].chan
= i
;
1876 alu
.dst
.sel
= ctx
->temp_reg
;
1882 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1887 for (i
= 0; i
< 4; i
++) {
1888 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1889 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1891 alu
.src
[0] = r600_src
[0];
1894 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
1897 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
1900 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1903 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1904 alu
.src
[0].chan
= i
;
1907 alu
.src
[1] = r600_src
[1];
1910 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
1913 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
1916 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
1919 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1920 alu
.src
[1].chan
= i
;
1923 alu
.src
[2].sel
= ctx
->temp_reg
;
1925 alu
.src
[2].chan
= i
;
1928 alu
.dst
.sel
= ctx
->temp_reg
;
1930 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1939 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1944 return tgsi_helper_copy(ctx
, inst
);
1948 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
1950 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1951 struct r600_bc_alu_src r600_src
[3];
1952 struct r600_bc_alu alu
;
1955 /* result.x = 2^floor(src); */
1956 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
1957 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1959 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
;
1960 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1964 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1966 alu
.dst
.sel
= ctx
->temp_reg
;
1970 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1974 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1978 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
1979 alu
.src
[0].sel
= ctx
->temp_reg
;
1980 alu
.src
[0].chan
= 0;
1982 alu
.dst
.sel
= ctx
->temp_reg
;
1986 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1990 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1995 /* result.y = tmp - floor(tmp); */
1996 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
1997 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1999 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
;
2000 alu
.src
[0] = r600_src
[0];
2001 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2004 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2006 alu
.dst
.sel
= ctx
->temp_reg
;
2007 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2015 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2018 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2023 /* result.z = RoughApprox2ToX(tmp);*/
2024 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
2025 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2026 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
2027 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2030 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2032 alu
.dst
.sel
= ctx
->temp_reg
;
2038 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2041 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2046 /* result.w = 1.0;*/
2047 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
2048 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2050 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
2051 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2052 alu
.src
[0].chan
= 0;
2054 alu
.dst
.sel
= ctx
->temp_reg
;
2058 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2061 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
2065 return tgsi_helper_copy(ctx
, inst
);
2068 static int tgsi_arl(struct r600_shader_ctx
*ctx
)
2070 /* TODO from r600c, ar values don't persist between clauses */
2071 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2072 struct r600_bc_alu alu
;
2074 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2076 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
;
2078 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2081 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2085 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
);
2091 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
2093 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2094 struct r600_bc_alu alu
;
2097 for (i
= 0; i
< 4; i
++) {
2098 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2100 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
2101 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2105 if (i
== 0 || i
== 3) {
2106 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2108 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2111 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
2114 if (i
== 0 || i
== 2) {
2115 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
2117 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[1]);
2120 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
2124 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2131 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
2133 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2134 struct r600_bc_alu alu
;
2137 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2141 alu
.dst
.sel
= ctx
->temp_reg
;
2145 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2148 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2149 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2150 alu
.src
[1].chan
= 0;
2154 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
);
2160 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
2162 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_POP
);
2163 ctx
->bc
->cf_last
->pop_count
= pops
;
2167 static inline void callstack_decrease_current(struct r600_shader_ctx
*ctx
, unsigned reason
)
2171 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2175 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
-= 4;
2178 /* TOODO : for 16 vp asic should -= 2; */
2179 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2184 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
)
2186 if (check_max_only
) {
2196 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
) >
2197 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2198 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2199 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
;
2205 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2209 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+= 4;
2212 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2216 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
) >
2217 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2218 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2219 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
;
2223 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
2225 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
2227 sp
->mid
= (struct r600_bc_cf
**)realloc((void *)sp
->mid
,
2228 sizeof(struct r600_bc_cf
*) * (sp
->num_mid
+ 1));
2229 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
2233 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
2236 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
2237 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
2240 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
2242 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
2254 static int emit_return(struct r600_shader_ctx
*ctx
)
2256 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_RETURN
);
2260 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
2263 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_JUMP
);
2264 ctx
->bc
->cf_last
->pop_count
= pops
;
2265 /* TODO work out offset */
2269 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
2274 static void emit_testflag(struct r600_shader_ctx
*ctx
)
2279 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
2282 emit_jump_to_offset(ctx
, 1, 4);
2283 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
2284 pops(ctx
, ifidx
+ 1);
2288 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
2292 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2293 ctx
->bc
->cf_last
->pop_count
= 1;
2295 fc_set_mid(ctx
, fc_sp
);
2301 static int tgsi_if(struct r600_shader_ctx
*ctx
)
2303 emit_logic_pred(ctx
, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
);
2305 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_JUMP
);
2307 fc_pushlevel(ctx
, FC_IF
);
2309 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
2313 static int tgsi_else(struct r600_shader_ctx
*ctx
)
2315 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_ELSE
);
2316 ctx
->bc
->cf_last
->pop_count
= 1;
2318 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
2319 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
2323 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
2326 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
2327 R600_ERR("if/endif unbalanced in shader\n");
2331 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
2332 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2333 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
2335 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2339 callstack_decrease_current(ctx
, FC_PUSH_VPM
);
2343 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
2345 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
);
2347 fc_pushlevel(ctx
, FC_LOOP
);
2349 /* check stack depth */
2350 callstack_check_depth(ctx
, FC_LOOP
, 0);
2354 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
2358 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
);
2360 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
2361 R600_ERR("loop/endloop in shader code are not paired.\n");
2365 /* fixup loop pointers - from r600isa
2366 LOOP END points to CF after LOOP START,
2367 LOOP START point to CF after LOOP END
2368 BRK/CONT point to LOOP END CF
2370 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
2372 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2374 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
2375 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
2377 /* TODO add LOOPRET support */
2379 callstack_decrease_current(ctx
, FC_LOOP
);
2383 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
2387 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
2389 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
2394 R600_ERR("Break not inside loop/endloop pair\n");
2398 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2399 ctx
->bc
->cf_last
->pop_count
= 1;
2401 fc_set_mid(ctx
, fscp
);
2404 callstack_check_depth(ctx
, FC_PUSH_VPM
, 1);
2408 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
2409 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_arl
},
2410 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2411 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
2412 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
2413 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
2414 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
2415 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2416 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
2417 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2418 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2419 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2420 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
2421 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
2422 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
2423 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
2424 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
2425 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
2426 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2427 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
2428 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2430 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2431 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2433 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2434 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2435 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
2436 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2437 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
2438 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2439 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
2440 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
2441 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
2442 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
2444 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2445 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2446 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2447 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2448 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
2449 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
2450 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
2451 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
2452 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2453 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2454 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2455 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2456 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2457 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
2458 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2459 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
2460 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
2461 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
2462 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
2463 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2464 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2465 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2466 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2467 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2468 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2469 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2470 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2471 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2472 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2473 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2474 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2475 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2476 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2477 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
2478 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
2479 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
2480 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2481 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2482 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2483 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2484 {TGSI_OPCODE_TXL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2485 {TGSI_OPCODE_BRK
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
2486 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
2488 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2489 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2490 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
2491 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
2493 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2494 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2495 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2496 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2497 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2498 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2499 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2500 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
2501 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2503 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2504 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2505 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2506 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2507 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2508 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2509 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2510 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2511 {TGSI_OPCODE_CONT
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
2512 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2513 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2514 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
2515 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2516 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
2517 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2519 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2520 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2521 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2522 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2523 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2525 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2526 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2527 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2528 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2529 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2530 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2531 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2532 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2533 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
2534 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
2536 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2537 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2538 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2539 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2540 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2541 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2542 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2543 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2544 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2545 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2546 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2547 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2548 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2549 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2550 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2551 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2552 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2553 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2554 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2555 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2556 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2557 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2558 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2559 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2560 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2561 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2562 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2563 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},