projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: more cleanup
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 for (i = 0; i < 10; i++) {
48 spi_vs_out_id[i] = 0;
49 }
50 for (i = 0; i < 32; i++) {
51 tmp = i << ((i & 3) * 8);
52 spi_vs_out_id[i / 4] |= tmp;
53 }
54 for (i = 0; i < 10; i++) {
55 r600_pipe_state_add_reg(rstate,
56 R_028614_SPI_VS_OUT_ID_0 + i * 4,
57 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
58 }
59
60 r600_pipe_state_add_reg(rstate,
61 R_0286C4_SPI_VS_OUT_CONFIG,
62 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
63 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate,
65 R_028868_SQ_PGM_RESOURCES_VS,
66 S_028868_NUM_GPRS(rshader->bc.ngpr) |
67 S_028868_STACK_SIZE(rshader->bc.nstack),
68 0xFFFFFFFF, NULL);
69 r600_pipe_state_add_reg(rstate,
70 R_0288A4_SQ_PGM_RESOURCES_FS,
71 0x00000000, 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS,
77 0x00000000, 0xFFFFFFFF, NULL);
78 r600_pipe_state_add_reg(rstate,
79 R_028858_SQ_PGM_START_VS,
80 0x00000000, 0xFFFFFFFF, shader->bo);
81 r600_pipe_state_add_reg(rstate,
82 R_028894_SQ_PGM_START_FS,
83 0x00000000, 0xFFFFFFFF, shader->bo);
84 }
85
86 int r600_find_vs_semantic_index2(struct r600_shader *vs,
87 struct r600_shader *ps, int id)
88 {
89 struct r600_shader_io *input = &ps->input[id];
90
91 for (int i = 0; i < vs->noutput; i++) {
92 if (input->name == vs->output[i].name &&
93 input->sid == vs->output[i].sid) {
94 return i - 1;
95 }
96 }
97 return 0;
98 }
99
100 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
101 {
102 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
103 struct r600_pipe_state *rstate = &shader->rstate;
104 struct r600_shader *rshader = &shader->shader;
105 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
106 boolean have_pos = FALSE, have_face = FALSE;
107
108 /* clear previous register */
109 rstate->nregs = 0;
110
111 for (i = 0; i < rshader->ninput; i++) {
112 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index2(&rctx->vs_shader->shader, rshader, i));
113 tmp |= S_028644_SEL_CENTROID(1);
114 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
115 have_pos = TRUE;
116 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
117 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
118 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
119 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
120 }
121 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
122 have_face = TRUE;
123 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
124 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
125 tmp |= S_028644_PT_SPRITE_TEX(1);
126 }
127 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
128 }
129 for (i = 0; i < rshader->noutput; i++) {
130 r600_pipe_state_add_reg(rstate,
131 R_02880C_DB_SHADER_CONTROL,
132 S_02880C_Z_EXPORT_ENABLE(1),
133 S_02880C_Z_EXPORT_ENABLE(1), NULL);
134 }
135
136 exports_ps = 0;
137 num_cout = 0;
138 for (i = 0; i < rshader->noutput; i++) {
139 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
140 exports_ps |= 1;
141 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
142 num_cout++;
143 }
144 }
145 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
146 if (!exports_ps) {
147 /* always at least export 1 component per pixel */
148 exports_ps = 2;
149 }
150
151 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
152 S_0286CC_PERSP_GRADIENT_ENA(1);
153 spi_input_z = 0;
154 if (have_pos) {
155 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
156 S_0286CC_BARYC_SAMPLE_CNTL(1);
157 spi_input_z |= 1;
158 }
159 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
160 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate,
163 R_028840_SQ_PGM_START_PS,
164 0x00000000, 0xFFFFFFFF, shader->bo);
165 r600_pipe_state_add_reg(rstate,
166 R_028850_SQ_PGM_RESOURCES_PS,
167 S_028868_NUM_GPRS(rshader->bc.ngpr) |
168 S_028868_STACK_SIZE(rshader->bc.nstack),
169 0xFFFFFFFF, NULL);
170 r600_pipe_state_add_reg(rstate,
171 R_028854_SQ_PGM_EXPORTS_PS,
172 exports_ps, 0xFFFFFFFF, NULL);
173 r600_pipe_state_add_reg(rstate,
174 R_0288CC_SQ_PGM_CF_OFFSET_PS,
175 0x00000000, 0xFFFFFFFF, NULL);
176
177 if (rshader->uses_kill) {
178 /* only set some bits here, the other bits are set in the dsa state */
179 r600_pipe_state_add_reg(rstate,
180 R_02880C_DB_SHADER_CONTROL,
181 S_02880C_KILL_ENABLE(1),
182 S_02880C_KILL_ENABLE(1), NULL);
183 }
184 }
185
186 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
187 {
188 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
189 struct r600_shader *rshader = &shader->shader;
190 void *ptr;
191
192 /* copy new shader */
193 if (shader->bo == NULL) {
194 shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
195 if (shader->bo == NULL) {
196 return -ENOMEM;
197 }
198 ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
199 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
200 radeon_ws_bo_unmap(rctx->radeon, shader->bo);
201 }
202 /* build state */
203 rshader->flat_shade = rctx->flatshade;
204 switch (rshader->processor_type) {
205 case TGSI_PROCESSOR_VERTEX:
206 if (rshader->family >= CHIP_CEDAR) {
207 evergreen_pipe_shader_vs(ctx, shader);
208 } else {
209 r600_pipe_shader_vs(ctx, shader);
210 }
211 break;
212 case TGSI_PROCESSOR_FRAGMENT:
213 if (rshader->family >= CHIP_CEDAR) {
214 evergreen_pipe_shader_ps(ctx, shader);
215 } else {
216 r600_pipe_shader_ps(ctx, shader);
217 }
218 break;
219 default:
220 return -EINVAL;
221 }
222 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
223 return 0;
224 }
225
226 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
227 {
228 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
229 struct r600_shader *shader = &rshader->shader;
230 const struct util_format_description *desc;
231 enum pipe_format resource_format[160];
232 unsigned i, nresources = 0;
233 struct r600_bc *bc = &shader->bc;
234 struct r600_bc_cf *cf;
235 struct r600_bc_vtx *vtx;
236
237 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
238 return 0;
239 if (!memcmp(&rshader->vertex_elements, rctx->vertex_elements, sizeof(struct r600_vertex_element))) {
240 return 0;
241 }
242 rshader->vertex_elements = *rctx->vertex_elements;
243 for (i = 0; i < rctx->vertex_elements->count; i++) {
244 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
245 }
246 radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
247 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
248 switch (cf->inst) {
249 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
250 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
251 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
252 desc = util_format_description(resource_format[vtx->buffer_id]);
253 if (desc == NULL) {
254 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
255 return -EINVAL;
256 }
257 vtx->dst_sel_x = desc->swizzle[0];
258 vtx->dst_sel_y = desc->swizzle[1];
259 vtx->dst_sel_z = desc->swizzle[2];
260 vtx->dst_sel_w = desc->swizzle[3];
261 }
262 break;
263 default:
264 break;
265 }
266 }
267 return r600_bc_build(&shader->bc);
268 }
269
270 int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
271 {
272 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
273 int r;
274
275 if (shader == NULL)
276 return -EINVAL;
277 /* there should be enough input */
278 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
279 R600_ERR("%d resources provided, expecting %d\n",
280 rctx->vertex_elements->count, shader->shader.bc.nresource);
281 return -EINVAL;
282 }
283 r = r600_shader_update(ctx, shader);
284 if (r)
285 return r;
286 return r600_pipe_shader(ctx, shader);
287 }
288
289 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
290 int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
291 {
292 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
293 int r;
294
295 //fprintf(stderr, "--------------------------------------------------------------\n");
296 //tgsi_dump(tokens, 0);
297 shader->shader.family = r600_get_family(rctx->radeon);
298 r = r600_shader_from_tgsi(tokens, &shader->shader);
299 if (r) {
300 R600_ERR("translation from TGSI failed !\n");
301 return r;
302 }
303 r = r600_bc_build(&shader->shader.bc);
304 if (r) {
305 R600_ERR("building bytecode failed !\n");
306 return r;
307 }
308 //fprintf(stderr, "______________________________________________________________\n");
309 return 0;
310 }
311
312 /*
313 * tgsi -> r600 shader
314 */
315 struct r600_shader_tgsi_instruction;
316
317 struct r600_shader_ctx {
318 struct tgsi_shader_info info;
319 struct tgsi_parse_context parse;
320 const struct tgsi_token *tokens;
321 unsigned type;
322 unsigned file_offset[TGSI_FILE_COUNT];
323 unsigned temp_reg;
324 struct r600_shader_tgsi_instruction *inst_info;
325 struct r600_bc *bc;
326 struct r600_shader *shader;
327 u32 value[4];
328 u32 *literals;
329 u32 nliterals;
330 u32 max_driver_temp_used;
331 };
332
333 struct r600_shader_tgsi_instruction {
334 unsigned tgsi_opcode;
335 unsigned is_op3;
336 unsigned r600_opcode;
337 int (*process)(struct r600_shader_ctx *ctx);
338 };
339
340 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
341 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
342
343 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
344 {
345 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
346 int j;
347
348 if (i->Instruction.NumDstRegs > 1) {
349 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
350 return -EINVAL;
351 }
352 if (i->Instruction.Predicate) {
353 R600_ERR("predicate unsupported\n");
354 return -EINVAL;
355 }
356 #if 0
357 if (i->Instruction.Label) {
358 R600_ERR("label unsupported\n");
359 return -EINVAL;
360 }
361 #endif
362 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
363 if (i->Src[j].Register.Dimension ||
364 i->Src[j].Register.Absolute) {
365 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
366 i->Src[j].Register.Dimension,
367 i->Src[j].Register.Absolute);
368 return -EINVAL;
369 }
370 }
371 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
372 if (i->Dst[j].Register.Dimension) {
373 R600_ERR("unsupported dst (dimension)\n");
374 return -EINVAL;
375 }
376 }
377 return 0;
378 }
379
380 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
381 {
382 int i, r;
383 struct r600_bc_alu alu;
384
385 for (i = 0; i < 8; i++) {
386 memset(&alu, 0, sizeof(struct r600_bc_alu));
387
388 if (i < 4)
389 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
390 else
391 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
392
393 if ((i > 1) && (i < 6)) {
394 alu.dst.sel = ctx->shader->input[gpr].gpr;
395 alu.dst.write = 1;
396 }
397
398 alu.dst.chan = i % 4;
399 alu.src[0].chan = (1 - (i % 2));
400 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
401
402 alu.bank_swizzle_force = SQ_ALU_VEC_210;
403 if ((i % 4) == 3)
404 alu.last = 1;
405 r = r600_bc_add_alu(ctx->bc, &alu);
406 if (r)
407 return r;
408 }
409 return 0;
410 }
411
412
413 static int tgsi_declaration(struct r600_shader_ctx *ctx)
414 {
415 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
416 struct r600_bc_vtx vtx;
417 unsigned i;
418 int r;
419
420 switch (d->Declaration.File) {
421 case TGSI_FILE_INPUT:
422 i = ctx->shader->ninput++;
423 ctx->shader->input[i].name = d->Semantic.Name;
424 ctx->shader->input[i].sid = d->Semantic.Index;
425 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
426 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
427 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
428 /* turn input into fetch */
429 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
430 vtx.inst = 0;
431 vtx.fetch_type = 0;
432 vtx.buffer_id = i;
433 /* register containing the index into the buffer */
434 vtx.src_gpr = 0;
435 vtx.src_sel_x = 0;
436 vtx.mega_fetch_count = 0x1F;
437 vtx.dst_gpr = ctx->shader->input[i].gpr;
438 vtx.dst_sel_x = 0;
439 vtx.dst_sel_y = 1;
440 vtx.dst_sel_z = 2;
441 vtx.dst_sel_w = 3;
442 r = r600_bc_add_vtx(ctx->bc, &vtx);
443 if (r)
444 return r;
445 }
446 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
447 /* turn input into interpolate on EG */
448 evergreen_interp_alu(ctx, i);
449 }
450 break;
451 case TGSI_FILE_OUTPUT:
452 i = ctx->shader->noutput++;
453 ctx->shader->output[i].name = d->Semantic.Name;
454 ctx->shader->output[i].sid = d->Semantic.Index;
455 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
456 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
457 break;
458 case TGSI_FILE_CONSTANT:
459 case TGSI_FILE_TEMPORARY:
460 case TGSI_FILE_SAMPLER:
461 case TGSI_FILE_ADDRESS:
462 break;
463 default:
464 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
465 return -EINVAL;
466 }
467 return 0;
468 }
469
470 static int r600_get_temp(struct r600_shader_ctx *ctx)
471 {
472 return ctx->temp_reg + ctx->max_driver_temp_used++;
473 }
474
475 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
476 {
477 struct tgsi_full_immediate *immediate;
478 struct r600_shader_ctx ctx;
479 struct r600_bc_output output[32];
480 unsigned output_done, noutput;
481 unsigned opcode;
482 int i, r = 0, pos0;
483
484 ctx.bc = &shader->bc;
485 ctx.shader = shader;
486 r = r600_bc_init(ctx.bc, shader->family);
487 if (r)
488 return r;
489 ctx.bc->use_mem_constant = shader->use_mem_constant;
490 ctx.tokens = tokens;
491 tgsi_scan_shader(tokens, &ctx.info);
492 tgsi_parse_init(&ctx.parse, tokens);
493 ctx.type = ctx.parse.FullHeader.Processor.Processor;
494 shader->processor_type = ctx.type;
495
496 /* register allocations */
497 /* Values [0,127] correspond to GPR[0..127].
498 * Values [128,159] correspond to constant buffer bank 0
499 * Values [160,191] correspond to constant buffer bank 1
500 * Values [256,511] correspond to cfile constants c[0..255].
501 * Other special values are shown in the list below.
502 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
503 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
504 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
505 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
506 * 248 SQ_ALU_SRC_0: special constant 0.0.
507 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
508 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
509 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
510 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
511 * 253 SQ_ALU_SRC_LITERAL: literal constant.
512 * 254 SQ_ALU_SRC_PV: previous vector result.
513 * 255 SQ_ALU_SRC_PS: previous scalar result.
514 */
515 for (i = 0; i < TGSI_FILE_COUNT; i++) {
516 ctx.file_offset[i] = 0;
517 }
518 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
519 ctx.file_offset[TGSI_FILE_INPUT] = 1;
520 }
521 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
522 ctx.info.file_count[TGSI_FILE_INPUT];
523 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
524 ctx.info.file_count[TGSI_FILE_OUTPUT];
525 if (ctx.shader->use_mem_constant)
526 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
527 else
528 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
529
530 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
531 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
532 ctx.info.file_count[TGSI_FILE_TEMPORARY];
533
534 ctx.nliterals = 0;
535 ctx.literals = NULL;
536
537 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
538 tgsi_parse_token(&ctx.parse);
539 switch (ctx.parse.FullToken.Token.Type) {
540 case TGSI_TOKEN_TYPE_IMMEDIATE:
541 immediate = &ctx.parse.FullToken.FullImmediate;
542 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
543 if(ctx.literals == NULL) {
544 r = -ENOMEM;
545 goto out_err;
546 }
547 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
548 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
549 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
550 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
551 ctx.nliterals++;
552 break;
553 case TGSI_TOKEN_TYPE_DECLARATION:
554 r = tgsi_declaration(&ctx);
555 if (r)
556 goto out_err;
557 break;
558 case TGSI_TOKEN_TYPE_INSTRUCTION:
559 r = tgsi_is_supported(&ctx);
560 if (r)
561 goto out_err;
562 ctx.max_driver_temp_used = 0;
563 /* reserve first tmp for everyone */
564 r600_get_temp(&ctx);
565 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
566 if (ctx.bc->chiprev == 2)
567 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
568 else
569 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
570 r = ctx.inst_info->process(&ctx);
571 if (r)
572 goto out_err;
573 r = r600_bc_add_literal(ctx.bc, ctx.value);
574 if (r)
575 goto out_err;
576 break;
577 default:
578 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
579 r = -EINVAL;
580 goto out_err;
581 }
582 }
583 /* export output */
584 noutput = shader->noutput;
585 for (i = 0, pos0 = 0; i < noutput; i++) {
586 memset(&output[i], 0, sizeof(struct r600_bc_output));
587 output[i].gpr = shader->output[i].gpr;
588 output[i].elem_size = 3;
589 output[i].swizzle_x = 0;
590 output[i].swizzle_y = 1;
591 output[i].swizzle_z = 2;
592 output[i].swizzle_w = 3;
593 output[i].barrier = 1;
594 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
595 output[i].array_base = i - pos0;
596 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
597 switch (ctx.type) {
598 case TGSI_PROCESSOR_VERTEX:
599 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
600 output[i].array_base = 60;
601 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
602 /* position doesn't count in array_base */
603 pos0++;
604 }
605 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
606 output[i].array_base = 61;
607 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
608 /* position doesn't count in array_base */
609 pos0++;
610 }
611 break;
612 case TGSI_PROCESSOR_FRAGMENT:
613 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
614 output[i].array_base = shader->output[i].sid;
615 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
616 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
617 output[i].array_base = 61;
618 output[i].swizzle_x = 2;
619 output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
620 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
621 } else {
622 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
623 r = -EINVAL;
624 goto out_err;
625 }
626 break;
627 default:
628 R600_ERR("unsupported processor type %d\n", ctx.type);
629 r = -EINVAL;
630 goto out_err;
631 }
632 }
633 /* add fake param output for vertex shader if no param is exported */
634 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
635 for (i = 0, pos0 = 0; i < noutput; i++) {
636 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
637 pos0 = 1;
638 break;
639 }
640 }
641 if (!pos0) {
642 memset(&output[i], 0, sizeof(struct r600_bc_output));
643 output[i].gpr = 0;
644 output[i].elem_size = 3;
645 output[i].swizzle_x = 0;
646 output[i].swizzle_y = 1;
647 output[i].swizzle_z = 2;
648 output[i].swizzle_w = 3;
649 output[i].barrier = 1;
650 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
651 output[i].array_base = 0;
652 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
653 noutput++;
654 }
655 }
656 /* add fake pixel export */
657 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
658 memset(&output[0], 0, sizeof(struct r600_bc_output));
659 output[0].gpr = 0;
660 output[0].elem_size = 3;
661 output[0].swizzle_x = 7;
662 output[0].swizzle_y = 7;
663 output[0].swizzle_z = 7;
664 output[0].swizzle_w = 7;
665 output[0].barrier = 1;
666 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
667 output[0].array_base = 0;
668 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
669 noutput++;
670 }
671 /* set export done on last export of each type */
672 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
673 if (i == (noutput - 1)) {
674 output[i].end_of_program = 1;
675 }
676 if (!(output_done & (1 << output[i].type))) {
677 output_done |= (1 << output[i].type);
678 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
679 }
680 }
681 /* add output to bytecode */
682 for (i = 0; i < noutput; i++) {
683 r = r600_bc_add_output(ctx.bc, &output[i]);
684 if (r)
685 goto out_err;
686 }
687 free(ctx.literals);
688 tgsi_parse_free(&ctx.parse);
689 return 0;
690 out_err:
691 free(ctx.literals);
692 tgsi_parse_free(&ctx.parse);
693 return r;
694 }
695
696 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
697 {
698 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
699 return -EINVAL;
700 }
701
702 static int tgsi_end(struct r600_shader_ctx *ctx)
703 {
704 return 0;
705 }
706
707 static int tgsi_src(struct r600_shader_ctx *ctx,
708 const struct tgsi_full_src_register *tgsi_src,
709 struct r600_bc_alu_src *r600_src)
710 {
711 int index;
712 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
713 r600_src->sel = tgsi_src->Register.Index;
714 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
715 r600_src->sel = 0;
716 index = tgsi_src->Register.Index;
717 ctx->value[0] = ctx->literals[index * 4 + 0];
718 ctx->value[1] = ctx->literals[index * 4 + 1];
719 ctx->value[2] = ctx->literals[index * 4 + 2];
720 ctx->value[3] = ctx->literals[index * 4 + 3];
721 }
722 if (tgsi_src->Register.Indirect)
723 r600_src->rel = V_SQ_REL_RELATIVE;
724 r600_src->neg = tgsi_src->Register.Negate;
725 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
726 return 0;
727 }
728
729 static int tgsi_dst(struct r600_shader_ctx *ctx,
730 const struct tgsi_full_dst_register *tgsi_dst,
731 unsigned swizzle,
732 struct r600_bc_alu_dst *r600_dst)
733 {
734 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
735
736 r600_dst->sel = tgsi_dst->Register.Index;
737 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
738 r600_dst->chan = swizzle;
739 r600_dst->write = 1;
740 if (tgsi_dst->Register.Indirect)
741 r600_dst->rel = V_SQ_REL_RELATIVE;
742 if (inst->Instruction.Saturate) {
743 r600_dst->clamp = 1;
744 }
745 return 0;
746 }
747
748 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
749 {
750 switch (swizzle) {
751 case 0:
752 return tgsi_src->Register.SwizzleX;
753 case 1:
754 return tgsi_src->Register.SwizzleY;
755 case 2:
756 return tgsi_src->Register.SwizzleZ;
757 case 3:
758 return tgsi_src->Register.SwizzleW;
759 default:
760 return 0;
761 }
762 }
763
764 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
765 {
766 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
767 struct r600_bc_alu alu;
768 int i, j, k, nconst, r;
769
770 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
771 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
772 nconst++;
773 }
774 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
775 if (r) {
776 return r;
777 }
778 }
779 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
780 if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
781 int treg = r600_get_temp(ctx);
782 for (k = 0; k < 4; k++) {
783 memset(&alu, 0, sizeof(struct r600_bc_alu));
784 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
785 alu.src[0].sel = r600_src[j].sel;
786 alu.src[0].chan = k;
787 alu.dst.sel = treg;
788 alu.dst.chan = k;
789 alu.dst.write = 1;
790 if (k == 3)
791 alu.last = 1;
792 r = r600_bc_add_alu(ctx->bc, &alu);
793 if (r)
794 return r;
795 }
796 r600_src[j].sel = treg;
797 j--;
798 }
799 }
800 return 0;
801 }
802
803 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
804 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
805 {
806 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
807 struct r600_bc_alu alu;
808 int i, j, k, nliteral, r;
809
810 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
811 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
812 nliteral++;
813 }
814 }
815 for (i = 0, j = 0; i < inst->Instruction.NumSrcRegs; i++) {
816 if (inst->Src[j].Register.File == TGSI_FILE_IMMEDIATE) {
817 int treg = r600_get_temp(ctx);
818 for (k = 0; k < 4; k++) {
819 memset(&alu, 0, sizeof(struct r600_bc_alu));
820 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
821 alu.src[0].sel = r600_src[j].sel;
822 alu.src[0].chan = k;
823 alu.dst.sel = treg;
824 alu.dst.chan = k;
825 alu.dst.write = 1;
826 if (k == 3)
827 alu.last = 1;
828 r = r600_bc_add_alu(ctx->bc, &alu);
829 if (r)
830 return r;
831 }
832 r = r600_bc_add_literal(ctx->bc, ctx->value);
833 if (r)
834 return r;
835 r600_src[j].sel = treg;
836 j++;
837 }
838 }
839 return 0;
840 }
841
842 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
843 {
844 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
845 struct r600_bc_alu_src r600_src[3];
846 struct r600_bc_alu alu;
847 int i, j, r;
848 int lasti = 0;
849
850 for (i = 0; i < 4; i++) {
851 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
852 lasti = i;
853 }
854 }
855
856 r = tgsi_split_constant(ctx, r600_src);
857 if (r)
858 return r;
859 for (i = 0; i < lasti + 1; i++) {
860 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
861 continue;
862
863 memset(&alu, 0, sizeof(struct r600_bc_alu));
864 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
865 if (r)
866 return r;
867
868 alu.inst = ctx->inst_info->r600_opcode;
869 if (!swap) {
870 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
871 alu.src[j] = r600_src[j];
872 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
873 }
874 } else {
875 alu.src[0] = r600_src[1];
876 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
877
878 alu.src[1] = r600_src[0];
879 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
880 }
881 /* handle some special cases */
882 switch (ctx->inst_info->tgsi_opcode) {
883 case TGSI_OPCODE_SUB:
884 alu.src[1].neg = 1;
885 break;
886 case TGSI_OPCODE_ABS:
887 alu.src[0].abs = 1;
888 break;
889 default:
890 break;
891 }
892 if (i == lasti) {
893 alu.last = 1;
894 }
895 r = r600_bc_add_alu(ctx->bc, &alu);
896 if (r)
897 return r;
898 }
899 return 0;
900 }
901
902 static int tgsi_op2(struct r600_shader_ctx *ctx)
903 {
904 return tgsi_op2_s(ctx, 0);
905 }
906
907 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
908 {
909 return tgsi_op2_s(ctx, 1);
910 }
911
912 /*
913 * r600 - trunc to -PI..PI range
914 * r700 - normalize by dividing by 2PI
915 * see fdo bug 27901
916 */
917 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
918 struct r600_bc_alu_src r600_src[3])
919 {
920 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
921 int r;
922 uint32_t lit_vals[4];
923 struct r600_bc_alu alu;
924
925 memset(lit_vals, 0, 4*4);
926 r = tgsi_split_constant(ctx, r600_src);
927 if (r)
928 return r;
929
930 r = tgsi_split_literal_constant(ctx, r600_src);
931 if (r)
932 return r;
933
934 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
935 lit_vals[1] = fui(0.5f);
936
937 memset(&alu, 0, sizeof(struct r600_bc_alu));
938 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
939 alu.is_op3 = 1;
940
941 alu.dst.chan = 0;
942 alu.dst.sel = ctx->temp_reg;
943 alu.dst.write = 1;
944
945 alu.src[0] = r600_src[0];
946 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
947
948 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
949 alu.src[1].chan = 0;
950 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
951 alu.src[2].chan = 1;
952 alu.last = 1;
953 r = r600_bc_add_alu(ctx->bc, &alu);
954 if (r)
955 return r;
956 r = r600_bc_add_literal(ctx->bc, lit_vals);
957 if (r)
958 return r;
959
960 memset(&alu, 0, sizeof(struct r600_bc_alu));
961 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
962
963 alu.dst.chan = 0;
964 alu.dst.sel = ctx->temp_reg;
965 alu.dst.write = 1;
966
967 alu.src[0].sel = ctx->temp_reg;
968 alu.src[0].chan = 0;
969 alu.last = 1;
970 r = r600_bc_add_alu(ctx->bc, &alu);
971 if (r)
972 return r;
973
974 if (ctx->bc->chiprev == 0) {
975 lit_vals[0] = fui(3.1415926535897f * 2.0f);
976 lit_vals[1] = fui(-3.1415926535897f);
977 } else {
978 lit_vals[0] = fui(1.0f);
979 lit_vals[1] = fui(-0.5f);
980 }
981
982 memset(&alu, 0, sizeof(struct r600_bc_alu));
983 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
984 alu.is_op3 = 1;
985
986 alu.dst.chan = 0;
987 alu.dst.sel = ctx->temp_reg;
988 alu.dst.write = 1;
989
990 alu.src[0].sel = ctx->temp_reg;
991 alu.src[0].chan = 0;
992
993 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
994 alu.src[1].chan = 0;
995 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
996 alu.src[2].chan = 1;
997 alu.last = 1;
998 r = r600_bc_add_alu(ctx->bc, &alu);
999 if (r)
1000 return r;
1001 r = r600_bc_add_literal(ctx->bc, lit_vals);
1002 if (r)
1003 return r;
1004 return 0;
1005 }
1006
1007 static int tgsi_trig(struct r600_shader_ctx *ctx)
1008 {
1009 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1010 struct r600_bc_alu_src r600_src[3];
1011 struct r600_bc_alu alu;
1012 int i, r;
1013 int lasti = 0;
1014
1015 r = tgsi_setup_trig(ctx, r600_src);
1016 if (r)
1017 return r;
1018
1019 memset(&alu, 0, sizeof(struct r600_bc_alu));
1020 alu.inst = ctx->inst_info->r600_opcode;
1021 alu.dst.chan = 0;
1022 alu.dst.sel = ctx->temp_reg;
1023 alu.dst.write = 1;
1024
1025 alu.src[0].sel = ctx->temp_reg;
1026 alu.src[0].chan = 0;
1027 alu.last = 1;
1028 r = r600_bc_add_alu(ctx->bc, &alu);
1029 if (r)
1030 return r;
1031
1032 /* replicate result */
1033 for (i = 0; i < 4; i++) {
1034 if (inst->Dst[0].Register.WriteMask & (1 << i))
1035 lasti = i;
1036 }
1037 for (i = 0; i < lasti + 1; i++) {
1038 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1039 continue;
1040
1041 memset(&alu, 0, sizeof(struct r600_bc_alu));
1042 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1043
1044 alu.src[0].sel = ctx->temp_reg;
1045 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1046 if (r)
1047 return r;
1048 if (i == lasti)
1049 alu.last = 1;
1050 r = r600_bc_add_alu(ctx->bc, &alu);
1051 if (r)
1052 return r;
1053 }
1054 return 0;
1055 }
1056
1057 static int tgsi_scs(struct r600_shader_ctx *ctx)
1058 {
1059 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1060 struct r600_bc_alu_src r600_src[3];
1061 struct r600_bc_alu alu;
1062 int r;
1063
1064 /* We'll only need the trig stuff if we are going to write to the
1065 * X or Y components of the destination vector.
1066 */
1067 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1068 r = tgsi_setup_trig(ctx, r600_src);
1069 if (r)
1070 return r;
1071 }
1072
1073 /* dst.x = COS */
1074 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1075 memset(&alu, 0, sizeof(struct r600_bc_alu));
1076 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1077 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1078 if (r)
1079 return r;
1080
1081 alu.src[0].sel = ctx->temp_reg;
1082 alu.src[0].chan = 0;
1083 alu.last = 1;
1084 r = r600_bc_add_alu(ctx->bc, &alu);
1085 if (r)
1086 return r;
1087 }
1088
1089 /* dst.y = SIN */
1090 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1091 memset(&alu, 0, sizeof(struct r600_bc_alu));
1092 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1093 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1094 if (r)
1095 return r;
1096
1097 alu.src[0].sel = ctx->temp_reg;
1098 alu.src[0].chan = 0;
1099 alu.last = 1;
1100 r = r600_bc_add_alu(ctx->bc, &alu);
1101 if (r)
1102 return r;
1103 }
1104
1105 /* dst.z = 0.0; */
1106 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1107 memset(&alu, 0, sizeof(struct r600_bc_alu));
1108
1109 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1110
1111 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1112 if (r)
1113 return r;
1114
1115 alu.src[0].sel = V_SQ_ALU_SRC_0;
1116 alu.src[0].chan = 0;
1117
1118 alu.last = 1;
1119
1120 r = r600_bc_add_alu(ctx->bc, &alu);
1121 if (r)
1122 return r;
1123
1124 r = r600_bc_add_literal(ctx->bc, ctx->value);
1125 if (r)
1126 return r;
1127 }
1128
1129 /* dst.w = 1.0; */
1130 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1131 memset(&alu, 0, sizeof(struct r600_bc_alu));
1132
1133 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1134
1135 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1136 if (r)
1137 return r;
1138
1139 alu.src[0].sel = V_SQ_ALU_SRC_1;
1140 alu.src[0].chan = 0;
1141
1142 alu.last = 1;
1143
1144 r = r600_bc_add_alu(ctx->bc, &alu);
1145 if (r)
1146 return r;
1147
1148 r = r600_bc_add_literal(ctx->bc, ctx->value);
1149 if (r)
1150 return r;
1151 }
1152
1153 return 0;
1154 }
1155
1156 static int tgsi_kill(struct r600_shader_ctx *ctx)
1157 {
1158 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1159 struct r600_bc_alu alu;
1160 int i, r;
1161
1162 for (i = 0; i < 4; i++) {
1163 memset(&alu, 0, sizeof(struct r600_bc_alu));
1164 alu.inst = ctx->inst_info->r600_opcode;
1165
1166 alu.dst.chan = i;
1167
1168 alu.src[0].sel = V_SQ_ALU_SRC_0;
1169
1170 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1171 alu.src[1].sel = V_SQ_ALU_SRC_1;
1172 alu.src[1].neg = 1;
1173 } else {
1174 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1175 if (r)
1176 return r;
1177 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1178 }
1179 if (i == 3) {
1180 alu.last = 1;
1181 }
1182 r = r600_bc_add_alu(ctx->bc, &alu);
1183 if (r)
1184 return r;
1185 }
1186 r = r600_bc_add_literal(ctx->bc, ctx->value);
1187 if (r)
1188 return r;
1189
1190 /* kill must be last in ALU */
1191 ctx->bc->force_add_cf = 1;
1192 ctx->shader->uses_kill = TRUE;
1193 return 0;
1194 }
1195
1196 static int tgsi_lit(struct r600_shader_ctx *ctx)
1197 {
1198 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1199 struct r600_bc_alu alu;
1200 struct r600_bc_alu_src r600_src[3];
1201 int r;
1202
1203 r = tgsi_split_constant(ctx, r600_src);
1204 if (r)
1205 return r;
1206 r = tgsi_split_literal_constant(ctx, r600_src);
1207 if (r)
1208 return r;
1209
1210 /* dst.x, <- 1.0 */
1211 memset(&alu, 0, sizeof(struct r600_bc_alu));
1212 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1213 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1214 alu.src[0].chan = 0;
1215 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1216 if (r)
1217 return r;
1218 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1219 r = r600_bc_add_alu(ctx->bc, &alu);
1220 if (r)
1221 return r;
1222
1223 /* dst.y = max(src.x, 0.0) */
1224 memset(&alu, 0, sizeof(struct r600_bc_alu));
1225 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1226 alu.src[0] = r600_src[0];
1227 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1228 alu.src[1].chan = 0;
1229 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1230 if (r)
1231 return r;
1232 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1233 r = r600_bc_add_alu(ctx->bc, &alu);
1234 if (r)
1235 return r;
1236
1237 /* dst.w, <- 1.0 */
1238 memset(&alu, 0, sizeof(struct r600_bc_alu));
1239 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1240 alu.src[0].sel = V_SQ_ALU_SRC_1;
1241 alu.src[0].chan = 0;
1242 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1243 if (r)
1244 return r;
1245 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1246 alu.last = 1;
1247 r = r600_bc_add_alu(ctx->bc, &alu);
1248 if (r)
1249 return r;
1250
1251 r = r600_bc_add_literal(ctx->bc, ctx->value);
1252 if (r)
1253 return r;
1254
1255 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1256 {
1257 int chan;
1258 int sel;
1259
1260 /* dst.z = log(src.y) */
1261 memset(&alu, 0, sizeof(struct r600_bc_alu));
1262 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1263 alu.src[0] = r600_src[0];
1264 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1265 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1266 if (r)
1267 return r;
1268 alu.last = 1;
1269 r = r600_bc_add_alu(ctx->bc, &alu);
1270 if (r)
1271 return r;
1272
1273 r = r600_bc_add_literal(ctx->bc, ctx->value);
1274 if (r)
1275 return r;
1276
1277 chan = alu.dst.chan;
1278 sel = alu.dst.sel;
1279
1280 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1281 memset(&alu, 0, sizeof(struct r600_bc_alu));
1282 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1283 alu.src[0] = r600_src[0];
1284 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1285 alu.src[1].sel = sel;
1286 alu.src[1].chan = chan;
1287
1288 alu.src[2] = r600_src[0];
1289 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1290 alu.dst.sel = ctx->temp_reg;
1291 alu.dst.chan = 0;
1292 alu.dst.write = 1;
1293 alu.is_op3 = 1;
1294 alu.last = 1;
1295 r = r600_bc_add_alu(ctx->bc, &alu);
1296 if (r)
1297 return r;
1298
1299 r = r600_bc_add_literal(ctx->bc, ctx->value);
1300 if (r)
1301 return r;
1302 /* dst.z = exp(tmp.x) */
1303 memset(&alu, 0, sizeof(struct r600_bc_alu));
1304 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1305 alu.src[0].sel = ctx->temp_reg;
1306 alu.src[0].chan = 0;
1307 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1308 if (r)
1309 return r;
1310 alu.last = 1;
1311 r = r600_bc_add_alu(ctx->bc, &alu);
1312 if (r)
1313 return r;
1314 }
1315 return 0;
1316 }
1317
1318 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1319 {
1320 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1321 struct r600_bc_alu alu;
1322 int i, r;
1323
1324 memset(&alu, 0, sizeof(struct r600_bc_alu));
1325
1326 /* FIXME:
1327 * For state trackers other than OpenGL, we'll want to use
1328 * _RECIPSQRT_IEEE instead.
1329 */
1330 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1331
1332 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1333 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1334 if (r)
1335 return r;
1336 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1337 alu.src[i].abs = 1;
1338 }
1339 alu.dst.sel = ctx->temp_reg;
1340 alu.dst.write = 1;
1341 alu.last = 1;
1342 r = r600_bc_add_alu(ctx->bc, &alu);
1343 if (r)
1344 return r;
1345 r = r600_bc_add_literal(ctx->bc, ctx->value);
1346 if (r)
1347 return r;
1348 /* replicate result */
1349 return tgsi_helper_tempx_replicate(ctx);
1350 }
1351
1352 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1353 {
1354 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1355 struct r600_bc_alu alu;
1356 int i, r;
1357
1358 for (i = 0; i < 4; i++) {
1359 memset(&alu, 0, sizeof(struct r600_bc_alu));
1360 alu.src[0].sel = ctx->temp_reg;
1361 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1362 alu.dst.chan = i;
1363 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1364 if (r)
1365 return r;
1366 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1367 if (i == 3)
1368 alu.last = 1;
1369 r = r600_bc_add_alu(ctx->bc, &alu);
1370 if (r)
1371 return r;
1372 }
1373 return 0;
1374 }
1375
1376 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1377 {
1378 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1379 struct r600_bc_alu alu;
1380 int i, r;
1381
1382 memset(&alu, 0, sizeof(struct r600_bc_alu));
1383 alu.inst = ctx->inst_info->r600_opcode;
1384 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1385 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1386 if (r)
1387 return r;
1388 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1389 }
1390 alu.dst.sel = ctx->temp_reg;
1391 alu.dst.write = 1;
1392 alu.last = 1;
1393 r = r600_bc_add_alu(ctx->bc, &alu);
1394 if (r)
1395 return r;
1396 r = r600_bc_add_literal(ctx->bc, ctx->value);
1397 if (r)
1398 return r;
1399 /* replicate result */
1400 return tgsi_helper_tempx_replicate(ctx);
1401 }
1402
1403 static int tgsi_pow(struct r600_shader_ctx *ctx)
1404 {
1405 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1406 struct r600_bc_alu alu;
1407 int r;
1408
1409 /* LOG2(a) */
1410 memset(&alu, 0, sizeof(struct r600_bc_alu));
1411 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1412 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1413 if (r)
1414 return r;
1415 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1416 alu.dst.sel = ctx->temp_reg;
1417 alu.dst.write = 1;
1418 alu.last = 1;
1419 r = r600_bc_add_alu(ctx->bc, &alu);
1420 if (r)
1421 return r;
1422 r = r600_bc_add_literal(ctx->bc,ctx->value);
1423 if (r)
1424 return r;
1425 /* b * LOG2(a) */
1426 memset(&alu, 0, sizeof(struct r600_bc_alu));
1427 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1428 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1429 if (r)
1430 return r;
1431 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1432 alu.src[1].sel = ctx->temp_reg;
1433 alu.dst.sel = ctx->temp_reg;
1434 alu.dst.write = 1;
1435 alu.last = 1;
1436 r = r600_bc_add_alu(ctx->bc, &alu);
1437 if (r)
1438 return r;
1439 r = r600_bc_add_literal(ctx->bc,ctx->value);
1440 if (r)
1441 return r;
1442 /* POW(a,b) = EXP2(b * LOG2(a))*/
1443 memset(&alu, 0, sizeof(struct r600_bc_alu));
1444 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1445 alu.src[0].sel = ctx->temp_reg;
1446 alu.dst.sel = ctx->temp_reg;
1447 alu.dst.write = 1;
1448 alu.last = 1;
1449 r = r600_bc_add_alu(ctx->bc, &alu);
1450 if (r)
1451 return r;
1452 r = r600_bc_add_literal(ctx->bc,ctx->value);
1453 if (r)
1454 return r;
1455 return tgsi_helper_tempx_replicate(ctx);
1456 }
1457
1458 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1459 {
1460 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1461 struct r600_bc_alu alu;
1462 struct r600_bc_alu_src r600_src[3];
1463 int i, r;
1464
1465 r = tgsi_split_constant(ctx, r600_src);
1466 if (r)
1467 return r;
1468
1469 /* tmp = (src > 0 ? 1 : src) */
1470 for (i = 0; i < 4; i++) {
1471 memset(&alu, 0, sizeof(struct r600_bc_alu));
1472 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1473 alu.is_op3 = 1;
1474
1475 alu.dst.sel = ctx->temp_reg;
1476 alu.dst.chan = i;
1477
1478 alu.src[0] = r600_src[0];
1479 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1480
1481 alu.src[1].sel = V_SQ_ALU_SRC_1;
1482
1483 alu.src[2] = r600_src[0];
1484 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1485 if (i == 3)
1486 alu.last = 1;
1487 r = r600_bc_add_alu(ctx->bc, &alu);
1488 if (r)
1489 return r;
1490 }
1491 r = r600_bc_add_literal(ctx->bc, ctx->value);
1492 if (r)
1493 return r;
1494
1495 /* dst = (-tmp > 0 ? -1 : tmp) */
1496 for (i = 0; i < 4; i++) {
1497 memset(&alu, 0, sizeof(struct r600_bc_alu));
1498 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1499 alu.is_op3 = 1;
1500 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1501 if (r)
1502 return r;
1503
1504 alu.src[0].sel = ctx->temp_reg;
1505 alu.src[0].chan = i;
1506 alu.src[0].neg = 1;
1507
1508 alu.src[1].sel = V_SQ_ALU_SRC_1;
1509 alu.src[1].neg = 1;
1510
1511 alu.src[2].sel = ctx->temp_reg;
1512 alu.src[2].chan = i;
1513
1514 if (i == 3)
1515 alu.last = 1;
1516 r = r600_bc_add_alu(ctx->bc, &alu);
1517 if (r)
1518 return r;
1519 }
1520 return 0;
1521 }
1522
1523 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1524 {
1525 struct r600_bc_alu alu;
1526 int i, r;
1527
1528 r = r600_bc_add_literal(ctx->bc, ctx->value);
1529 if (r)
1530 return r;
1531 for (i = 0; i < 4; i++) {
1532 memset(&alu, 0, sizeof(struct r600_bc_alu));
1533 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1534 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1535 alu.dst.chan = i;
1536 } else {
1537 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1538 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1539 if (r)
1540 return r;
1541 alu.src[0].sel = ctx->temp_reg;
1542 alu.src[0].chan = i;
1543 }
1544 if (i == 3) {
1545 alu.last = 1;
1546 }
1547 r = r600_bc_add_alu(ctx->bc, &alu);
1548 if (r)
1549 return r;
1550 }
1551 return 0;
1552 }
1553
1554 static int tgsi_op3(struct r600_shader_ctx *ctx)
1555 {
1556 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1557 struct r600_bc_alu_src r600_src[3];
1558 struct r600_bc_alu alu;
1559 int i, j, r;
1560
1561 r = tgsi_split_constant(ctx, r600_src);
1562 if (r)
1563 return r;
1564 /* do it in 2 step as op3 doesn't support writemask */
1565 for (i = 0; i < 4; i++) {
1566 memset(&alu, 0, sizeof(struct r600_bc_alu));
1567 alu.inst = ctx->inst_info->r600_opcode;
1568 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1569 alu.src[j] = r600_src[j];
1570 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1571 }
1572 alu.dst.sel = ctx->temp_reg;
1573 alu.dst.chan = i;
1574 alu.dst.write = 1;
1575 alu.is_op3 = 1;
1576 if (i == 3) {
1577 alu.last = 1;
1578 }
1579 r = r600_bc_add_alu(ctx->bc, &alu);
1580 if (r)
1581 return r;
1582 }
1583 return tgsi_helper_copy(ctx, inst);
1584 }
1585
1586 static int tgsi_dp(struct r600_shader_ctx *ctx)
1587 {
1588 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1589 struct r600_bc_alu_src r600_src[3];
1590 struct r600_bc_alu alu;
1591 int i, j, r;
1592
1593 r = tgsi_split_constant(ctx, r600_src);
1594 if (r)
1595 return r;
1596 for (i = 0; i < 4; i++) {
1597 memset(&alu, 0, sizeof(struct r600_bc_alu));
1598 alu.inst = ctx->inst_info->r600_opcode;
1599 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1600 alu.src[j] = r600_src[j];
1601 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1602 }
1603 alu.dst.sel = ctx->temp_reg;
1604 alu.dst.chan = i;
1605 alu.dst.write = 1;
1606 /* handle some special cases */
1607 switch (ctx->inst_info->tgsi_opcode) {
1608 case TGSI_OPCODE_DP2:
1609 if (i > 1) {
1610 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1611 alu.src[0].chan = alu.src[1].chan = 0;
1612 }
1613 break;
1614 case TGSI_OPCODE_DP3:
1615 if (i > 2) {
1616 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1617 alu.src[0].chan = alu.src[1].chan = 0;
1618 }
1619 break;
1620 case TGSI_OPCODE_DPH:
1621 if (i == 3) {
1622 alu.src[0].sel = V_SQ_ALU_SRC_1;
1623 alu.src[0].chan = 0;
1624 alu.src[0].neg = 0;
1625 }
1626 break;
1627 default:
1628 break;
1629 }
1630 if (i == 3) {
1631 alu.last = 1;
1632 }
1633 r = r600_bc_add_alu(ctx->bc, &alu);
1634 if (r)
1635 return r;
1636 }
1637 return tgsi_helper_copy(ctx, inst);
1638 }
1639
1640 static int tgsi_tex(struct r600_shader_ctx *ctx)
1641 {
1642 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1643 struct r600_bc_tex tex;
1644 struct r600_bc_alu alu;
1645 unsigned src_gpr;
1646 int r, i;
1647 int opcode;
1648 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1649 uint32_t lit_vals[4];
1650
1651 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1652
1653 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1654 /* Add perspective divide */
1655 memset(&alu, 0, sizeof(struct r600_bc_alu));
1656 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1657 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1658 if (r)
1659 return r;
1660
1661 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1662 alu.dst.sel = ctx->temp_reg;
1663 alu.dst.chan = 3;
1664 alu.last = 1;
1665 alu.dst.write = 1;
1666 r = r600_bc_add_alu(ctx->bc, &alu);
1667 if (r)
1668 return r;
1669
1670 for (i = 0; i < 3; i++) {
1671 memset(&alu, 0, sizeof(struct r600_bc_alu));
1672 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1673 alu.src[0].sel = ctx->temp_reg;
1674 alu.src[0].chan = 3;
1675 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1676 if (r)
1677 return r;
1678 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1679 alu.dst.sel = ctx->temp_reg;
1680 alu.dst.chan = i;
1681 alu.dst.write = 1;
1682 r = r600_bc_add_alu(ctx->bc, &alu);
1683 if (r)
1684 return r;
1685 }
1686 memset(&alu, 0, sizeof(struct r600_bc_alu));
1687 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1688 alu.src[0].sel = V_SQ_ALU_SRC_1;
1689 alu.src[0].chan = 0;
1690 alu.dst.sel = ctx->temp_reg;
1691 alu.dst.chan = 3;
1692 alu.last = 1;
1693 alu.dst.write = 1;
1694 r = r600_bc_add_alu(ctx->bc, &alu);
1695 if (r)
1696 return r;
1697 src_not_temp = FALSE;
1698 src_gpr = ctx->temp_reg;
1699 }
1700
1701 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1702 int src_chan, src2_chan;
1703
1704 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1705 for (i = 0; i < 4; i++) {
1706 memset(&alu, 0, sizeof(struct r600_bc_alu));
1707 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1708 switch (i) {
1709 case 0:
1710 src_chan = 2;
1711 src2_chan = 1;
1712 break;
1713 case 1:
1714 src_chan = 2;
1715 src2_chan = 0;
1716 break;
1717 case 2:
1718 src_chan = 0;
1719 src2_chan = 2;
1720 break;
1721 case 3:
1722 src_chan = 1;
1723 src2_chan = 2;
1724 break;
1725 default:
1726 assert(0);
1727 src_chan = 0;
1728 src2_chan = 0;
1729 break;
1730 }
1731 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1732 if (r)
1733 return r;
1734 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1735 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1736 if (r)
1737 return r;
1738 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1739 alu.dst.sel = ctx->temp_reg;
1740 alu.dst.chan = i;
1741 if (i == 3)
1742 alu.last = 1;
1743 alu.dst.write = 1;
1744 r = r600_bc_add_alu(ctx->bc, &alu);
1745 if (r)
1746 return r;
1747 }
1748
1749 /* tmp1.z = RCP_e(|tmp1.z|) */
1750 memset(&alu, 0, sizeof(struct r600_bc_alu));
1751 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1752 alu.src[0].sel = ctx->temp_reg;
1753 alu.src[0].chan = 2;
1754 alu.src[0].abs = 1;
1755 alu.dst.sel = ctx->temp_reg;
1756 alu.dst.chan = 2;
1757 alu.dst.write = 1;
1758 alu.last = 1;
1759 r = r600_bc_add_alu(ctx->bc, &alu);
1760 if (r)
1761 return r;
1762
1763 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1764 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1765 * muladd has no writemask, have to use another temp
1766 */
1767 memset(&alu, 0, sizeof(struct r600_bc_alu));
1768 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1769 alu.is_op3 = 1;
1770
1771 alu.src[0].sel = ctx->temp_reg;
1772 alu.src[0].chan = 0;
1773 alu.src[1].sel = ctx->temp_reg;
1774 alu.src[1].chan = 2;
1775
1776 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1777 alu.src[2].chan = 0;
1778
1779 alu.dst.sel = ctx->temp_reg;
1780 alu.dst.chan = 0;
1781 alu.dst.write = 1;
1782
1783 r = r600_bc_add_alu(ctx->bc, &alu);
1784 if (r)
1785 return r;
1786
1787 memset(&alu, 0, sizeof(struct r600_bc_alu));
1788 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1789 alu.is_op3 = 1;
1790
1791 alu.src[0].sel = ctx->temp_reg;
1792 alu.src[0].chan = 1;
1793 alu.src[1].sel = ctx->temp_reg;
1794 alu.src[1].chan = 2;
1795
1796 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1797 alu.src[2].chan = 0;
1798
1799 alu.dst.sel = ctx->temp_reg;
1800 alu.dst.chan = 1;
1801 alu.dst.write = 1;
1802
1803 alu.last = 1;
1804 r = r600_bc_add_alu(ctx->bc, &alu);
1805 if (r)
1806 return r;
1807
1808 lit_vals[0] = fui(1.5f);
1809
1810 r = r600_bc_add_literal(ctx->bc, lit_vals);
1811 if (r)
1812 return r;
1813 src_not_temp = FALSE;
1814 src_gpr = ctx->temp_reg;
1815 }
1816
1817 if (src_not_temp) {
1818 for (i = 0; i < 4; i++) {
1819 memset(&alu, 0, sizeof(struct r600_bc_alu));
1820 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1821 alu.src[0].sel = src_gpr;
1822 alu.src[0].chan = i;
1823 alu.dst.sel = ctx->temp_reg;
1824 alu.dst.chan = i;
1825 if (i == 3)
1826 alu.last = 1;
1827 alu.dst.write = 1;
1828 r = r600_bc_add_alu(ctx->bc, &alu);
1829 if (r)
1830 return r;
1831 }
1832 src_gpr = ctx->temp_reg;
1833 }
1834
1835 opcode = ctx->inst_info->r600_opcode;
1836 if (opcode == SQ_TEX_INST_SAMPLE &&
1837 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1838 opcode = SQ_TEX_INST_SAMPLE_C;
1839
1840 memset(&tex, 0, sizeof(struct r600_bc_tex));
1841 tex.inst = opcode;
1842 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1843 tex.sampler_id = tex.resource_id;
1844 tex.src_gpr = src_gpr;
1845 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1846 tex.dst_sel_x = 0;
1847 tex.dst_sel_y = 1;
1848 tex.dst_sel_z = 2;
1849 tex.dst_sel_w = 3;
1850 tex.src_sel_x = 0;
1851 tex.src_sel_y = 1;
1852 tex.src_sel_z = 2;
1853 tex.src_sel_w = 3;
1854
1855 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1856 tex.src_sel_x = 1;
1857 tex.src_sel_y = 0;
1858 tex.src_sel_z = 3;
1859 tex.src_sel_w = 1;
1860 }
1861
1862 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1863 tex.coord_type_x = 1;
1864 tex.coord_type_y = 1;
1865 tex.coord_type_z = 1;
1866 tex.coord_type_w = 1;
1867 }
1868
1869 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1870 tex.src_sel_w = 2;
1871
1872 r = r600_bc_add_tex(ctx->bc, &tex);
1873 if (r)
1874 return r;
1875
1876 /* add shadow ambient support - gallium doesn't do it yet */
1877 return 0;
1878
1879 }
1880
1881 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1882 {
1883 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1884 struct r600_bc_alu_src r600_src[3];
1885 struct r600_bc_alu alu;
1886 unsigned i;
1887 int r;
1888
1889 r = tgsi_split_constant(ctx, r600_src);
1890 if (r)
1891 return r;
1892 /* 1 - src0 */
1893 for (i = 0; i < 4; i++) {
1894 memset(&alu, 0, sizeof(struct r600_bc_alu));
1895 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1896 alu.src[0].sel = V_SQ_ALU_SRC_1;
1897 alu.src[0].chan = 0;
1898 alu.src[1] = r600_src[0];
1899 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1900 alu.src[1].neg = 1;
1901 alu.dst.sel = ctx->temp_reg;
1902 alu.dst.chan = i;
1903 if (i == 3) {
1904 alu.last = 1;
1905 }
1906 alu.dst.write = 1;
1907 r = r600_bc_add_alu(ctx->bc, &alu);
1908 if (r)
1909 return r;
1910 }
1911 r = r600_bc_add_literal(ctx->bc, ctx->value);
1912 if (r)
1913 return r;
1914
1915 /* (1 - src0) * src2 */
1916 for (i = 0; i < 4; i++) {
1917 memset(&alu, 0, sizeof(struct r600_bc_alu));
1918 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1919 alu.src[0].sel = ctx->temp_reg;
1920 alu.src[0].chan = i;
1921 alu.src[1] = r600_src[2];
1922 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1923 alu.dst.sel = ctx->temp_reg;
1924 alu.dst.chan = i;
1925 if (i == 3) {
1926 alu.last = 1;
1927 }
1928 alu.dst.write = 1;
1929 r = r600_bc_add_alu(ctx->bc, &alu);
1930 if (r)
1931 return r;
1932 }
1933 r = r600_bc_add_literal(ctx->bc, ctx->value);
1934 if (r)
1935 return r;
1936
1937 /* src0 * src1 + (1 - src0) * src2 */
1938 for (i = 0; i < 4; i++) {
1939 memset(&alu, 0, sizeof(struct r600_bc_alu));
1940 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1941 alu.is_op3 = 1;
1942 alu.src[0] = r600_src[0];
1943 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1944 alu.src[1] = r600_src[1];
1945 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1946 alu.src[2].sel = ctx->temp_reg;
1947 alu.src[2].chan = i;
1948 alu.dst.sel = ctx->temp_reg;
1949 alu.dst.chan = i;
1950 if (i == 3) {
1951 alu.last = 1;
1952 }
1953 r = r600_bc_add_alu(ctx->bc, &alu);
1954 if (r)
1955 return r;
1956 }
1957 return tgsi_helper_copy(ctx, inst);
1958 }
1959
1960 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1961 {
1962 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1963 struct r600_bc_alu_src r600_src[3];
1964 struct r600_bc_alu alu;
1965 int use_temp = 0;
1966 int i, r;
1967
1968 r = tgsi_split_constant(ctx, r600_src);
1969 if (r)
1970 return r;
1971
1972 if (inst->Dst[0].Register.WriteMask != 0xf)
1973 use_temp = 1;
1974
1975 for (i = 0; i < 4; i++) {
1976 memset(&alu, 0, sizeof(struct r600_bc_alu));
1977 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1978 alu.src[0] = r600_src[0];
1979 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1980
1981 alu.src[1] = r600_src[2];
1982 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1983
1984 alu.src[2] = r600_src[1];
1985 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
1986
1987 if (use_temp)
1988 alu.dst.sel = ctx->temp_reg;
1989 else {
1990 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1991 if (r)
1992 return r;
1993 }
1994 alu.dst.chan = i;
1995 alu.dst.write = 1;
1996 alu.is_op3 = 1;
1997 if (i == 3)
1998 alu.last = 1;
1999 r = r600_bc_add_alu(ctx->bc, &alu);
2000 if (r)
2001 return r;
2002 }
2003 if (use_temp)
2004 return tgsi_helper_copy(ctx, inst);
2005 return 0;
2006 }
2007
2008 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2009 {
2010 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2011 struct r600_bc_alu_src r600_src[3];
2012 struct r600_bc_alu alu;
2013 uint32_t use_temp = 0;
2014 int i, r;
2015
2016 if (inst->Dst[0].Register.WriteMask != 0xf)
2017 use_temp = 1;
2018
2019 r = tgsi_split_constant(ctx, r600_src);
2020 if (r)
2021 return r;
2022
2023 for (i = 0; i < 4; i++) {
2024 memset(&alu, 0, sizeof(struct r600_bc_alu));
2025 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2026
2027 alu.src[0] = r600_src[0];
2028 switch (i) {
2029 case 0:
2030 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2031 break;
2032 case 1:
2033 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2034 break;
2035 case 2:
2036 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2037 break;
2038 case 3:
2039 alu.src[0].sel = V_SQ_ALU_SRC_0;
2040 alu.src[0].chan = i;
2041 }
2042
2043 alu.src[1] = r600_src[1];
2044 switch (i) {
2045 case 0:
2046 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2047 break;
2048 case 1:
2049 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2050 break;
2051 case 2:
2052 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2053 break;
2054 case 3:
2055 alu.src[1].sel = V_SQ_ALU_SRC_0;
2056 alu.src[1].chan = i;
2057 }
2058
2059 alu.dst.sel = ctx->temp_reg;
2060 alu.dst.chan = i;
2061 alu.dst.write = 1;
2062
2063 if (i == 3)
2064 alu.last = 1;
2065 r = r600_bc_add_alu(ctx->bc, &alu);
2066 if (r)
2067 return r;
2068
2069 r = r600_bc_add_literal(ctx->bc, ctx->value);
2070 if (r)
2071 return r;
2072 }
2073
2074 for (i = 0; i < 4; i++) {
2075 memset(&alu, 0, sizeof(struct r600_bc_alu));
2076 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2077
2078 alu.src[0] = r600_src[0];
2079 switch (i) {
2080 case 0:
2081 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2082 break;
2083 case 1:
2084 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2085 break;
2086 case 2:
2087 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2088 break;
2089 case 3:
2090 alu.src[0].sel = V_SQ_ALU_SRC_0;
2091 alu.src[0].chan = i;
2092 }
2093
2094 alu.src[1] = r600_src[1];
2095 switch (i) {
2096 case 0:
2097 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2098 break;
2099 case 1:
2100 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2101 break;
2102 case 2:
2103 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2104 break;
2105 case 3:
2106 alu.src[1].sel = V_SQ_ALU_SRC_0;
2107 alu.src[1].chan = i;
2108 }
2109
2110 alu.src[2].sel = ctx->temp_reg;
2111 alu.src[2].neg = 1;
2112 alu.src[2].chan = i;
2113
2114 if (use_temp)
2115 alu.dst.sel = ctx->temp_reg;
2116 else {
2117 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2118 if (r)
2119 return r;
2120 }
2121 alu.dst.chan = i;
2122 alu.dst.write = 1;
2123 alu.is_op3 = 1;
2124 if (i == 3)
2125 alu.last = 1;
2126 r = r600_bc_add_alu(ctx->bc, &alu);
2127 if (r)
2128 return r;
2129
2130 r = r600_bc_add_literal(ctx->bc, ctx->value);
2131 if (r)
2132 return r;
2133 }
2134 if (use_temp)
2135 return tgsi_helper_copy(ctx, inst);
2136 return 0;
2137 }
2138
2139 static int tgsi_exp(struct r600_shader_ctx *ctx)
2140 {
2141 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2142 struct r600_bc_alu_src r600_src[3];
2143 struct r600_bc_alu alu;
2144 int r;
2145
2146 /* result.x = 2^floor(src); */
2147 if (inst->Dst[0].Register.WriteMask & 1) {
2148 memset(&alu, 0, sizeof(struct r600_bc_alu));
2149
2150 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2151 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2152 if (r)
2153 return r;
2154
2155 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2156
2157 alu.dst.sel = ctx->temp_reg;
2158 alu.dst.chan = 0;
2159 alu.dst.write = 1;
2160 alu.last = 1;
2161 r = r600_bc_add_alu(ctx->bc, &alu);
2162 if (r)
2163 return r;
2164
2165 r = r600_bc_add_literal(ctx->bc, ctx->value);
2166 if (r)
2167 return r;
2168
2169 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2170 alu.src[0].sel = ctx->temp_reg;
2171 alu.src[0].chan = 0;
2172
2173 alu.dst.sel = ctx->temp_reg;
2174 alu.dst.chan = 0;
2175 alu.dst.write = 1;
2176 alu.last = 1;
2177 r = r600_bc_add_alu(ctx->bc, &alu);
2178 if (r)
2179 return r;
2180
2181 r = r600_bc_add_literal(ctx->bc, ctx->value);
2182 if (r)
2183 return r;
2184 }
2185
2186 /* result.y = tmp - floor(tmp); */
2187 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2188 memset(&alu, 0, sizeof(struct r600_bc_alu));
2189
2190 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2191 alu.src[0] = r600_src[0];
2192 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2193 if (r)
2194 return r;
2195 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2196
2197 alu.dst.sel = ctx->temp_reg;
2198 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2199 // if (r)
2200 // return r;
2201 alu.dst.write = 1;
2202 alu.dst.chan = 1;
2203
2204 alu.last = 1;
2205
2206 r = r600_bc_add_alu(ctx->bc, &alu);
2207 if (r)
2208 return r;
2209 r = r600_bc_add_literal(ctx->bc, ctx->value);
2210 if (r)
2211 return r;
2212 }
2213
2214 /* result.z = RoughApprox2ToX(tmp);*/
2215 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2216 memset(&alu, 0, sizeof(struct r600_bc_alu));
2217 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2218 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2219 if (r)
2220 return r;
2221 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2222
2223 alu.dst.sel = ctx->temp_reg;
2224 alu.dst.write = 1;
2225 alu.dst.chan = 2;
2226
2227 alu.last = 1;
2228
2229 r = r600_bc_add_alu(ctx->bc, &alu);
2230 if (r)
2231 return r;
2232 r = r600_bc_add_literal(ctx->bc, ctx->value);
2233 if (r)
2234 return r;
2235 }
2236
2237 /* result.w = 1.0;*/
2238 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2239 memset(&alu, 0, sizeof(struct r600_bc_alu));
2240
2241 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2242 alu.src[0].sel = V_SQ_ALU_SRC_1;
2243 alu.src[0].chan = 0;
2244
2245 alu.dst.sel = ctx->temp_reg;
2246 alu.dst.chan = 3;
2247 alu.dst.write = 1;
2248 alu.last = 1;
2249 r = r600_bc_add_alu(ctx->bc, &alu);
2250 if (r)
2251 return r;
2252 r = r600_bc_add_literal(ctx->bc, ctx->value);
2253 if (r)
2254 return r;
2255 }
2256 return tgsi_helper_copy(ctx, inst);
2257 }
2258
2259 static int tgsi_log(struct r600_shader_ctx *ctx)
2260 {
2261 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2262 struct r600_bc_alu alu;
2263 int r;
2264
2265 /* result.x = floor(log2(src)); */
2266 if (inst->Dst[0].Register.WriteMask & 1) {
2267 memset(&alu, 0, sizeof(struct r600_bc_alu));
2268
2269 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2270 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2271 if (r)
2272 return r;
2273
2274 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2275
2276 alu.dst.sel = ctx->temp_reg;
2277 alu.dst.chan = 0;
2278 alu.dst.write = 1;
2279 alu.last = 1;
2280 r = r600_bc_add_alu(ctx->bc, &alu);
2281 if (r)
2282 return r;
2283
2284 r = r600_bc_add_literal(ctx->bc, ctx->value);
2285 if (r)
2286 return r;
2287
2288 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2289 alu.src[0].sel = ctx->temp_reg;
2290 alu.src[0].chan = 0;
2291
2292 alu.dst.sel = ctx->temp_reg;
2293 alu.dst.chan = 0;
2294 alu.dst.write = 1;
2295 alu.last = 1;
2296
2297 r = r600_bc_add_alu(ctx->bc, &alu);
2298 if (r)
2299 return r;
2300
2301 r = r600_bc_add_literal(ctx->bc, ctx->value);
2302 if (r)
2303 return r;
2304 }
2305
2306 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2307 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2308 memset(&alu, 0, sizeof(struct r600_bc_alu));
2309
2310 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2311 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2312 if (r)
2313 return r;
2314
2315 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2316
2317 alu.dst.sel = ctx->temp_reg;
2318 alu.dst.chan = 1;
2319 alu.dst.write = 1;
2320 alu.last = 1;
2321
2322 r = r600_bc_add_alu(ctx->bc, &alu);
2323 if (r)
2324 return r;
2325
2326 r = r600_bc_add_literal(ctx->bc, ctx->value);
2327 if (r)
2328 return r;
2329
2330 memset(&alu, 0, sizeof(struct r600_bc_alu));
2331
2332 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2333 alu.src[0].sel = ctx->temp_reg;
2334 alu.src[0].chan = 1;
2335
2336 alu.dst.sel = ctx->temp_reg;
2337 alu.dst.chan = 1;
2338 alu.dst.write = 1;
2339 alu.last = 1;
2340
2341 r = r600_bc_add_alu(ctx->bc, &alu);
2342 if (r)
2343 return r;
2344
2345 r = r600_bc_add_literal(ctx->bc, ctx->value);
2346 if (r)
2347 return r;
2348
2349 memset(&alu, 0, sizeof(struct r600_bc_alu));
2350
2351 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2352 alu.src[0].sel = ctx->temp_reg;
2353 alu.src[0].chan = 1;
2354
2355 alu.dst.sel = ctx->temp_reg;
2356 alu.dst.chan = 1;
2357 alu.dst.write = 1;
2358 alu.last = 1;
2359
2360 r = r600_bc_add_alu(ctx->bc, &alu);
2361 if (r)
2362 return r;
2363
2364 r = r600_bc_add_literal(ctx->bc, ctx->value);
2365 if (r)
2366 return r;
2367
2368 memset(&alu, 0, sizeof(struct r600_bc_alu));
2369
2370 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2371 alu.src[0].sel = ctx->temp_reg;
2372 alu.src[0].chan = 1;
2373
2374 alu.dst.sel = ctx->temp_reg;
2375 alu.dst.chan = 1;
2376 alu.dst.write = 1;
2377 alu.last = 1;
2378
2379 r = r600_bc_add_alu(ctx->bc, &alu);
2380 if (r)
2381 return r;
2382
2383 r = r600_bc_add_literal(ctx->bc, ctx->value);
2384 if (r)
2385 return r;
2386
2387 memset(&alu, 0, sizeof(struct r600_bc_alu));
2388
2389 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2390
2391 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2392 if (r)
2393 return r;
2394
2395 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2396
2397 alu.src[1].sel = ctx->temp_reg;
2398 alu.src[1].chan = 1;
2399
2400 alu.dst.sel = ctx->temp_reg;
2401 alu.dst.chan = 1;
2402 alu.dst.write = 1;
2403 alu.last = 1;
2404
2405 r = r600_bc_add_alu(ctx->bc, &alu);
2406 if (r)
2407 return r;
2408
2409 r = r600_bc_add_literal(ctx->bc, ctx->value);
2410 if (r)
2411 return r;
2412 }
2413
2414 /* result.z = log2(src);*/
2415 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2416 memset(&alu, 0, sizeof(struct r600_bc_alu));
2417
2418 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2419 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2420 if (r)
2421 return r;
2422
2423 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2424
2425 alu.dst.sel = ctx->temp_reg;
2426 alu.dst.write = 1;
2427 alu.dst.chan = 2;
2428 alu.last = 1;
2429
2430 r = r600_bc_add_alu(ctx->bc, &alu);
2431 if (r)
2432 return r;
2433
2434 r = r600_bc_add_literal(ctx->bc, ctx->value);
2435 if (r)
2436 return r;
2437 }
2438
2439 /* result.w = 1.0; */
2440 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2441 memset(&alu, 0, sizeof(struct r600_bc_alu));
2442
2443 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2444 alu.src[0].sel = V_SQ_ALU_SRC_1;
2445 alu.src[0].chan = 0;
2446
2447 alu.dst.sel = ctx->temp_reg;
2448 alu.dst.chan = 3;
2449 alu.dst.write = 1;
2450 alu.last = 1;
2451
2452 r = r600_bc_add_alu(ctx->bc, &alu);
2453 if (r)
2454 return r;
2455
2456 r = r600_bc_add_literal(ctx->bc, ctx->value);
2457 if (r)
2458 return r;
2459 }
2460
2461 return tgsi_helper_copy(ctx, inst);
2462 }
2463
2464 /* r6/7 only for now */
2465 static int tgsi_arl(struct r600_shader_ctx *ctx)
2466 {
2467 /* TODO from r600c, ar values don't persist between clauses */
2468 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2469 struct r600_bc_alu alu;
2470 int r;
2471 memset(&alu, 0, sizeof(struct r600_bc_alu));
2472
2473 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2474
2475 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2476 if (r)
2477 return r;
2478 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2479
2480 alu.last = 1;
2481
2482 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2483 if (r)
2484 return r;
2485 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2486 return 0;
2487 }
2488
2489 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2490 {
2491 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2492 struct r600_bc_alu alu;
2493 int i, r = 0;
2494
2495 for (i = 0; i < 4; i++) {
2496 memset(&alu, 0, sizeof(struct r600_bc_alu));
2497
2498 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2499 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2500 if (r)
2501 return r;
2502
2503 if (i == 0 || i == 3) {
2504 alu.src[0].sel = V_SQ_ALU_SRC_1;
2505 } else {
2506 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2507 if (r)
2508 return r;
2509 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2510 }
2511
2512 if (i == 0 || i == 2) {
2513 alu.src[1].sel = V_SQ_ALU_SRC_1;
2514 } else {
2515 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2516 if (r)
2517 return r;
2518 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2519 }
2520 if (i == 3)
2521 alu.last = 1;
2522 r = r600_bc_add_alu(ctx->bc, &alu);
2523 if (r)
2524 return r;
2525 }
2526 return 0;
2527 }
2528
2529 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2530 {
2531 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2532 struct r600_bc_alu alu;
2533 int r;
2534
2535 memset(&alu, 0, sizeof(struct r600_bc_alu));
2536 alu.inst = opcode;
2537 alu.predicate = 1;
2538
2539 alu.dst.sel = ctx->temp_reg;
2540 alu.dst.write = 1;
2541 alu.dst.chan = 0;
2542
2543 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2544 if (r)
2545 return r;
2546 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2547 alu.src[1].sel = V_SQ_ALU_SRC_0;
2548 alu.src[1].chan = 0;
2549
2550 alu.last = 1;
2551
2552 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2553 if (r)
2554 return r;
2555 return 0;
2556 }
2557
2558 static int pops(struct r600_shader_ctx *ctx, int pops)
2559 {
2560 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2561 ctx->bc->cf_last->pop_count = pops;
2562 return 0;
2563 }
2564
2565 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2566 {
2567 switch(reason) {
2568 case FC_PUSH_VPM:
2569 ctx->bc->callstack[ctx->bc->call_sp].current--;
2570 break;
2571 case FC_PUSH_WQM:
2572 case FC_LOOP:
2573 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2574 break;
2575 case FC_REP:
2576 /* TOODO : for 16 vp asic should -= 2; */
2577 ctx->bc->callstack[ctx->bc->call_sp].current --;
2578 break;
2579 }
2580 }
2581
2582 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2583 {
2584 if (check_max_only) {
2585 int diff;
2586 switch (reason) {
2587 case FC_PUSH_VPM:
2588 diff = 1;
2589 break;
2590 case FC_PUSH_WQM:
2591 diff = 4;
2592 break;
2593 default:
2594 assert(0);
2595 diff = 0;
2596 }
2597 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2598 ctx->bc->callstack[ctx->bc->call_sp].max) {
2599 ctx->bc->callstack[ctx->bc->call_sp].max =
2600 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2601 }
2602 return;
2603 }
2604 switch (reason) {
2605 case FC_PUSH_VPM:
2606 ctx->bc->callstack[ctx->bc->call_sp].current++;
2607 break;
2608 case FC_PUSH_WQM:
2609 case FC_LOOP:
2610 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2611 break;
2612 case FC_REP:
2613 ctx->bc->callstack[ctx->bc->call_sp].current++;
2614 break;
2615 }
2616
2617 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2618 ctx->bc->callstack[ctx->bc->call_sp].max) {
2619 ctx->bc->callstack[ctx->bc->call_sp].max =
2620 ctx->bc->callstack[ctx->bc->call_sp].current;
2621 }
2622 }
2623
2624 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2625 {
2626 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2627
2628 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2629 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2630 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2631 sp->num_mid++;
2632 }
2633
2634 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2635 {
2636 ctx->bc->fc_sp++;
2637 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2638 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2639 }
2640
2641 static void fc_poplevel(struct r600_shader_ctx *ctx)
2642 {
2643 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2644 if (sp->mid) {
2645 free(sp->mid);
2646 sp->mid = NULL;
2647 }
2648 sp->num_mid = 0;
2649 sp->start = NULL;
2650 sp->type = 0;
2651 ctx->bc->fc_sp--;
2652 }
2653
2654 #if 0
2655 static int emit_return(struct r600_shader_ctx *ctx)
2656 {
2657 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2658 return 0;
2659 }
2660
2661 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2662 {
2663
2664 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2665 ctx->bc->cf_last->pop_count = pops;
2666 /* TODO work out offset */
2667 return 0;
2668 }
2669
2670 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2671 {
2672 return 0;
2673 }
2674
2675 static void emit_testflag(struct r600_shader_ctx *ctx)
2676 {
2677
2678 }
2679
2680 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2681 {
2682 emit_testflag(ctx);
2683 emit_jump_to_offset(ctx, 1, 4);
2684 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2685 pops(ctx, ifidx + 1);
2686 emit_return(ctx);
2687 }
2688
2689 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2690 {
2691 emit_testflag(ctx);
2692
2693 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2694 ctx->bc->cf_last->pop_count = 1;
2695
2696 fc_set_mid(ctx, fc_sp);
2697
2698 pops(ctx, 1);
2699 }
2700 #endif
2701
2702 static int tgsi_if(struct r600_shader_ctx *ctx)
2703 {
2704 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2705
2706 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2707
2708 fc_pushlevel(ctx, FC_IF);
2709
2710 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2711 return 0;
2712 }
2713
2714 static int tgsi_else(struct r600_shader_ctx *ctx)
2715 {
2716 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2717 ctx->bc->cf_last->pop_count = 1;
2718
2719 fc_set_mid(ctx, ctx->bc->fc_sp);
2720 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2721 return 0;
2722 }
2723
2724 static int tgsi_endif(struct r600_shader_ctx *ctx)
2725 {
2726 pops(ctx, 1);
2727 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2728 R600_ERR("if/endif unbalanced in shader\n");
2729 return -1;
2730 }
2731
2732 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2733 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2734 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2735 } else {
2736 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2737 }
2738 fc_poplevel(ctx);
2739
2740 callstack_decrease_current(ctx, FC_PUSH_VPM);
2741 return 0;
2742 }
2743
2744 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2745 {
2746 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2747
2748 fc_pushlevel(ctx, FC_LOOP);
2749
2750 /* check stack depth */
2751 callstack_check_depth(ctx, FC_LOOP, 0);
2752 return 0;
2753 }
2754
2755 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2756 {
2757 int i;
2758
2759 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2760
2761 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2762 R600_ERR("loop/endloop in shader code are not paired.\n");
2763 return -EINVAL;
2764 }
2765
2766 /* fixup loop pointers - from r600isa
2767 LOOP END points to CF after LOOP START,
2768 LOOP START point to CF after LOOP END
2769 BRK/CONT point to LOOP END CF
2770 */
2771 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2772
2773 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2774
2775 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2776 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2777 }
2778 /* TODO add LOOPRET support */
2779 fc_poplevel(ctx);
2780 callstack_decrease_current(ctx, FC_LOOP);
2781 return 0;
2782 }
2783
2784 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2785 {
2786 unsigned int fscp;
2787
2788 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2789 {
2790 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2791 break;
2792 }
2793
2794 if (fscp == 0) {
2795 R600_ERR("Break not inside loop/endloop pair\n");
2796 return -EINVAL;
2797 }
2798
2799 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2800 ctx->bc->cf_last->pop_count = 1;
2801
2802 fc_set_mid(ctx, fscp);
2803
2804 pops(ctx, 1);
2805 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2806 return 0;
2807 }
2808
2809 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2810 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2811 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2812 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2813
2814 /* FIXME:
2815 * For state trackers other than OpenGL, we'll want to use
2816 * _RECIP_IEEE instead.
2817 */
2818 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2819
2820 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2821 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2822 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2823 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2824 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2825 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2826 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2827 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2828 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2829 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2830 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2831 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2832 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2833 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2834 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2835 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2836 /* gap */
2837 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2838 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2839 /* gap */
2840 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2841 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2842 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2843 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2844 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2845 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2846 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2847 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2848 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2849 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2850 /* gap */
2851 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2852 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2853 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2854 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2855 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2856 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2857 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2858 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2859 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2860 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2861 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2862 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2863 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2864 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2865 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2866 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2867 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2868 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2869 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2870 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2871 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2872 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2873 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2874 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2875 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2876 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2877 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2878 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2879 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2880 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2881 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2882 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2883 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2884 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2885 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2886 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2887 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2888 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2889 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2891 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2892 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2893 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2894 /* gap */
2895 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2896 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2897 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2898 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2899 /* gap */
2900 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2901 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2902 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2903 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2904 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2908 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 /* gap */
2910 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2911 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2912 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2914 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2917 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2918 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2919 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2920 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2921 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2922 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2924 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 /* gap */
2926 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2927 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 /* gap */
2932 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2934 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2937 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2941 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2942 /* gap */
2943 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2950 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2955 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2957 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2958 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2960 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2961 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2968 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2969 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 };
2972
2973 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
2974 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2976 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2977 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2978 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
2979 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2980 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2982 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2983 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2984 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2985 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2986 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2987 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2988 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2989 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2990 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2991 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2992 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2993 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 /* gap */
2995 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 /* gap */
2998 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3001 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3003 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3005 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3006 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3007 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3008 /* gap */
3009 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3010 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3011 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3013 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3014 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3015 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3016 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3017 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3023 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3025 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3026 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3027 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3028 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3029 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3030 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3032 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3037 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3039 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3040 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3041 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3042 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3043 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3044 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3045 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3046 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3049 {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3051 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3052 /* gap */
3053 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3054 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3056 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3057 /* gap */
3058 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3066 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 /* gap */
3068 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3069 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3070 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3075 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3076 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3077 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3078 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3079 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3080 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3082 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 /* gap */
3084 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 /* gap */
3090 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3092 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3099 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3100 /* gap */
3101 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3106 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3107 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3108 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3113 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3115 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3116 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3118 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3127 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 };