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r600g: Split constants in r600_shader_from_tgsi().
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
49 */
50 for (i = 0; i < 10; i++) {
51 spi_vs_out_id[i] = 0;
52 }
53 for (i = 0; i < 32; i++) {
54 tmp = i << ((i & 3) * 8);
55 spi_vs_out_id[i / 4] |= tmp;
56 }
57 for (i = 0; i < 10; i++) {
58 r600_pipe_state_add_reg(rstate,
59 R_028614_SPI_VS_OUT_ID_0 + i * 4,
60 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
61 }
62
63 r600_pipe_state_add_reg(rstate,
64 R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
66 0xFFFFFFFF, NULL);
67 r600_pipe_state_add_reg(rstate,
68 R_028868_SQ_PGM_RESOURCES_VS,
69 S_028868_NUM_GPRS(rshader->bc.ngpr) |
70 S_028868_STACK_SIZE(rshader->bc.nstack),
71 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_028858_SQ_PGM_START_VS,
77 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
78
79 r600_pipe_state_add_reg(rstate,
80 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
81 0xFFFFFFFF, NULL);
82
83 }
84
85 int r600_find_vs_semantic_index(struct r600_shader *vs,
86 struct r600_shader *ps, int id)
87 {
88 struct r600_shader_io *input = &ps->input[id];
89
90 for (int i = 0; i < vs->noutput; i++) {
91 if (input->name == vs->output[i].name &&
92 input->sid == vs->output[i].sid) {
93 return i - 1;
94 }
95 }
96 return 0;
97 }
98
99 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
100 {
101 struct r600_pipe_state *rstate = &shader->rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
104 int pos_index = -1, face_index = -1;
105
106 rstate->nregs = 0;
107
108 for (i = 0; i < rshader->ninput; i++) {
109 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
110 pos_index = i;
111 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
112 face_index = i;
113 }
114
115 for (i = 0; i < rshader->noutput; i++) {
116 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
117 r600_pipe_state_add_reg(rstate,
118 R_02880C_DB_SHADER_CONTROL,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL);
121 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
122 r600_pipe_state_add_reg(rstate,
123 R_02880C_DB_SHADER_CONTROL,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
126 }
127
128 exports_ps = 0;
129 num_cout = 0;
130 for (i = 0; i < rshader->noutput; i++) {
131 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
132 exports_ps |= 1;
133 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
134 num_cout++;
135 }
136 }
137 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
138 if (!exports_ps) {
139 /* always at least export 1 component per pixel */
140 exports_ps = 2;
141 }
142
143 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
145 spi_input_z = 0;
146 if (pos_index != -1) {
147 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
149 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
151 spi_input_z |= 1;
152 }
153
154 spi_ps_in_control_1 = 0;
155 if (face_index != -1) {
156 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
158 }
159
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->fs_write_all) {
179 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
180 S_028808_MULTIWRITE_ENABLE(1),
181 S_028808_MULTIWRITE_ENABLE(1),
182 NULL);
183 }
184
185 if (rshader->uses_kill) {
186 /* only set some bits here, the other bits are set in the dsa state */
187 r600_pipe_state_add_reg(rstate,
188 R_02880C_DB_SHADER_CONTROL,
189 S_02880C_KILL_ENABLE(1),
190 S_02880C_KILL_ENABLE(1), NULL);
191 }
192 r600_pipe_state_add_reg(rstate,
193 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
194 0xFFFFFFFF, NULL);
195 }
196
197 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
198 {
199 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
200 struct r600_shader *rshader = &shader->shader;
201 void *ptr;
202
203 /* copy new shader */
204 if (shader->bo == NULL) {
205 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
206 if (shader->bo == NULL) {
207 return -ENOMEM;
208 }
209 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
210 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
211 r600_bo_unmap(rctx->radeon, shader->bo);
212 }
213 /* build state */
214 switch (rshader->processor_type) {
215 case TGSI_PROCESSOR_VERTEX:
216 if (rshader->family >= CHIP_CEDAR) {
217 evergreen_pipe_shader_vs(ctx, shader);
218 } else {
219 r600_pipe_shader_vs(ctx, shader);
220 }
221 break;
222 case TGSI_PROCESSOR_FRAGMENT:
223 if (rshader->family >= CHIP_CEDAR) {
224 evergreen_pipe_shader_ps(ctx, shader);
225 } else {
226 r600_pipe_shader_ps(ctx, shader);
227 }
228 break;
229 default:
230 return -EINVAL;
231 }
232 return 0;
233 }
234
235 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
236
237 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
238 {
239 static int dump_shaders = -1;
240 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
241 int r;
242
243 /* Would like some magic "get_bool_option_once" routine.
244 */
245 if (dump_shaders == -1)
246 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
247
248 if (dump_shaders) {
249 fprintf(stderr, "--------------------------------------------------------------\n");
250 tgsi_dump(tokens, 0);
251 }
252 shader->shader.family = r600_get_family(rctx->radeon);
253 r = r600_shader_from_tgsi(tokens, &shader->shader);
254 if (r) {
255 R600_ERR("translation from TGSI failed !\n");
256 return r;
257 }
258 r = r600_bc_build(&shader->shader.bc);
259 if (r) {
260 R600_ERR("building bytecode failed !\n");
261 return r;
262 }
263 if (dump_shaders) {
264 r600_bc_dump(&shader->shader.bc);
265 fprintf(stderr, "______________________________________________________________\n");
266 }
267 return r600_pipe_shader(ctx, shader);
268 }
269
270 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
271 {
272 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
273
274 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
275 r600_bc_clear(&shader->shader.bc);
276 }
277
278 /*
279 * tgsi -> r600 shader
280 */
281 struct r600_shader_tgsi_instruction;
282
283 struct r600_shader_src {
284 unsigned sel;
285 unsigned swizzle[4];
286 unsigned neg;
287 unsigned abs;
288 unsigned rel;
289 uint32_t value[4];
290 };
291
292 struct r600_shader_ctx {
293 struct tgsi_shader_info info;
294 struct tgsi_parse_context parse;
295 const struct tgsi_token *tokens;
296 unsigned type;
297 unsigned file_offset[TGSI_FILE_COUNT];
298 unsigned temp_reg;
299 struct r600_shader_tgsi_instruction *inst_info;
300 struct r600_bc *bc;
301 struct r600_shader *shader;
302 struct r600_shader_src src[3];
303 u32 *literals;
304 u32 nliterals;
305 u32 max_driver_temp_used;
306 /* needed for evergreen interpolation */
307 boolean input_centroid;
308 boolean input_linear;
309 boolean input_perspective;
310 int num_interp_gpr;
311 };
312
313 struct r600_shader_tgsi_instruction {
314 unsigned tgsi_opcode;
315 unsigned is_op3;
316 unsigned r600_opcode;
317 int (*process)(struct r600_shader_ctx *ctx);
318 };
319
320 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
321 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
322
323 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
324 {
325 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
326 int j;
327
328 if (i->Instruction.NumDstRegs > 1) {
329 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
330 return -EINVAL;
331 }
332 if (i->Instruction.Predicate) {
333 R600_ERR("predicate unsupported\n");
334 return -EINVAL;
335 }
336 #if 0
337 if (i->Instruction.Label) {
338 R600_ERR("label unsupported\n");
339 return -EINVAL;
340 }
341 #endif
342 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
343 if (i->Src[j].Register.Dimension) {
344 R600_ERR("unsupported src %d (dimension %d)\n", j,
345 i->Src[j].Register.Dimension);
346 return -EINVAL;
347 }
348 }
349 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
350 if (i->Dst[j].Register.Dimension) {
351 R600_ERR("unsupported dst (dimension)\n");
352 return -EINVAL;
353 }
354 }
355 return 0;
356 }
357
358 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
359 {
360 int i, r;
361 struct r600_bc_alu alu;
362 int gpr = 0, base_chan = 0;
363 int ij_index = 0;
364
365 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
366 ij_index = 0;
367 if (ctx->shader->input[input].centroid)
368 ij_index++;
369 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
370 ij_index = 0;
371 /* if we have perspective add one */
372 if (ctx->input_perspective) {
373 ij_index++;
374 /* if we have perspective centroid */
375 if (ctx->input_centroid)
376 ij_index++;
377 }
378 if (ctx->shader->input[input].centroid)
379 ij_index++;
380 }
381
382 /* work out gpr and base_chan from index */
383 gpr = ij_index / 2;
384 base_chan = (2 * (ij_index % 2)) + 1;
385
386 for (i = 0; i < 8; i++) {
387 memset(&alu, 0, sizeof(struct r600_bc_alu));
388
389 if (i < 4)
390 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
391 else
392 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
393
394 if ((i > 1) && (i < 6)) {
395 alu.dst.sel = ctx->shader->input[input].gpr;
396 alu.dst.write = 1;
397 }
398
399 alu.dst.chan = i % 4;
400
401 alu.src[0].sel = gpr;
402 alu.src[0].chan = (base_chan - (i % 2));
403
404 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
405
406 alu.bank_swizzle_force = SQ_ALU_VEC_210;
407 if ((i % 4) == 3)
408 alu.last = 1;
409 r = r600_bc_add_alu(ctx->bc, &alu);
410 if (r)
411 return r;
412 }
413 return 0;
414 }
415
416
417 static int tgsi_declaration(struct r600_shader_ctx *ctx)
418 {
419 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
420 unsigned i;
421
422 switch (d->Declaration.File) {
423 case TGSI_FILE_INPUT:
424 i = ctx->shader->ninput++;
425 ctx->shader->input[i].name = d->Semantic.Name;
426 ctx->shader->input[i].sid = d->Semantic.Index;
427 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
428 ctx->shader->input[i].centroid = d->Declaration.Centroid;
429 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
430 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
431 /* turn input into interpolate on EG */
432 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
433 if (ctx->shader->input[i].interpolate > 0) {
434 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
435 evergreen_interp_alu(ctx, i);
436 }
437 }
438 }
439 break;
440 case TGSI_FILE_OUTPUT:
441 i = ctx->shader->noutput++;
442 ctx->shader->output[i].name = d->Semantic.Name;
443 ctx->shader->output[i].sid = d->Semantic.Index;
444 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
445 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
446 break;
447 case TGSI_FILE_CONSTANT:
448 case TGSI_FILE_TEMPORARY:
449 case TGSI_FILE_SAMPLER:
450 case TGSI_FILE_ADDRESS:
451 break;
452 default:
453 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
454 return -EINVAL;
455 }
456 return 0;
457 }
458
459 static int r600_get_temp(struct r600_shader_ctx *ctx)
460 {
461 return ctx->temp_reg + ctx->max_driver_temp_used++;
462 }
463
464 /*
465 * for evergreen we need to scan the shader to find the number of GPRs we need to
466 * reserve for interpolation.
467 *
468 * we need to know if we are going to emit
469 * any centroid inputs
470 * if perspective and linear are required
471 */
472 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
473 {
474 int i;
475 int num_baryc;
476
477 ctx->input_linear = FALSE;
478 ctx->input_perspective = FALSE;
479 ctx->input_centroid = FALSE;
480 ctx->num_interp_gpr = 1;
481
482 /* any centroid inputs */
483 for (i = 0; i < ctx->info.num_inputs; i++) {
484 /* skip position/face */
485 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
486 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
487 continue;
488 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
489 ctx->input_linear = TRUE;
490 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
491 ctx->input_perspective = TRUE;
492 if (ctx->info.input_centroid[i])
493 ctx->input_centroid = TRUE;
494 }
495
496 num_baryc = 0;
497 /* ignoring sample for now */
498 if (ctx->input_perspective)
499 num_baryc++;
500 if (ctx->input_linear)
501 num_baryc++;
502 if (ctx->input_centroid)
503 num_baryc *= 2;
504
505 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
506
507 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
508 return ctx->num_interp_gpr;
509 }
510
511 static void tgsi_src(struct r600_shader_ctx *ctx,
512 const struct tgsi_full_src_register *tgsi_src,
513 struct r600_shader_src *r600_src)
514 {
515 memset(r600_src, 0, sizeof(*r600_src));
516 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
517 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
518 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
519 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
520 r600_src->neg = tgsi_src->Register.Negate;
521 r600_src->abs = tgsi_src->Register.Absolute;
522 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
523 int index;
524 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
525 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
526 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
527
528 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
529 r600_bc_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
530 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
531 return;
532 }
533 index = tgsi_src->Register.Index;
534 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
535 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
536 } else {
537 if (tgsi_src->Register.Indirect)
538 r600_src->rel = V_SQ_REL_RELATIVE;
539 r600_src->sel = tgsi_src->Register.Index;
540 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
541 }
542 }
543
544 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
545 {
546 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
547 struct r600_bc_alu alu;
548 int i, j, k, nconst, r;
549
550 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
551 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
552 nconst++;
553 }
554 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
555 }
556 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
557 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
558 int treg = r600_get_temp(ctx);
559 for (k = 0; k < 4; k++) {
560 memset(&alu, 0, sizeof(struct r600_bc_alu));
561 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
562 alu.src[0].sel = ctx->src[i].sel;
563 alu.src[0].chan = k;
564 alu.src[0].rel = ctx->src[i].rel;
565 alu.dst.sel = treg;
566 alu.dst.chan = k;
567 alu.dst.write = 1;
568 if (k == 3)
569 alu.last = 1;
570 r = r600_bc_add_alu(ctx->bc, &alu);
571 if (r)
572 return r;
573 }
574 ctx->src[i].sel = treg;
575 ctx->src[i].rel =0;
576 j--;
577 }
578 }
579 return 0;
580 }
581
582 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
583 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
584 {
585 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
586 struct r600_bc_alu alu;
587 int i, j, k, nliteral, r;
588
589 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
590 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
591 nliteral++;
592 }
593 }
594 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
595 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
596 int treg = r600_get_temp(ctx);
597 for (k = 0; k < 4; k++) {
598 memset(&alu, 0, sizeof(struct r600_bc_alu));
599 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
600 alu.src[0].sel = ctx->src[i].sel;
601 alu.src[0].chan = k;
602 alu.src[0].value = ctx->src[i].value[k];
603 alu.dst.sel = treg;
604 alu.dst.chan = k;
605 alu.dst.write = 1;
606 if (k == 3)
607 alu.last = 1;
608 r = r600_bc_add_alu(ctx->bc, &alu);
609 if (r)
610 return r;
611 }
612 ctx->src[i].sel = treg;
613 j--;
614 }
615 }
616 return 0;
617 }
618
619 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
620 {
621 struct tgsi_full_immediate *immediate;
622 struct tgsi_full_property *property;
623 struct r600_shader_ctx ctx;
624 struct r600_bc_output output[32];
625 unsigned output_done, noutput;
626 unsigned opcode;
627 int i, r = 0, pos0;
628
629 ctx.bc = &shader->bc;
630 ctx.shader = shader;
631 r = r600_bc_init(ctx.bc, shader->family);
632 if (r)
633 return r;
634 ctx.tokens = tokens;
635 tgsi_scan_shader(tokens, &ctx.info);
636 tgsi_parse_init(&ctx.parse, tokens);
637 ctx.type = ctx.parse.FullHeader.Processor.Processor;
638 shader->processor_type = ctx.type;
639 ctx.bc->type = shader->processor_type;
640
641 /* register allocations */
642 /* Values [0,127] correspond to GPR[0..127].
643 * Values [128,159] correspond to constant buffer bank 0
644 * Values [160,191] correspond to constant buffer bank 1
645 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
646 * Values [256,287] correspond to constant buffer bank 2 (EG)
647 * Values [288,319] correspond to constant buffer bank 3 (EG)
648 * Other special values are shown in the list below.
649 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
650 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
651 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
652 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
653 * 248 SQ_ALU_SRC_0: special constant 0.0.
654 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
655 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
656 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
657 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
658 * 253 SQ_ALU_SRC_LITERAL: literal constant.
659 * 254 SQ_ALU_SRC_PV: previous vector result.
660 * 255 SQ_ALU_SRC_PS: previous scalar result.
661 */
662 for (i = 0; i < TGSI_FILE_COUNT; i++) {
663 ctx.file_offset[i] = 0;
664 }
665 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
666 ctx.file_offset[TGSI_FILE_INPUT] = 1;
667 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
668 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
669 } else {
670 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
671 }
672 }
673 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
674 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
675 }
676 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
677 ctx.info.file_count[TGSI_FILE_INPUT];
678 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
679 ctx.info.file_count[TGSI_FILE_OUTPUT];
680
681 /* Outside the GPR range. This will be translated to one of the
682 * kcache banks later. */
683 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
684
685 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
686 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
687 ctx.info.file_count[TGSI_FILE_TEMPORARY];
688
689 ctx.nliterals = 0;
690 ctx.literals = NULL;
691 shader->fs_write_all = FALSE;
692 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
693 tgsi_parse_token(&ctx.parse);
694 switch (ctx.parse.FullToken.Token.Type) {
695 case TGSI_TOKEN_TYPE_IMMEDIATE:
696 immediate = &ctx.parse.FullToken.FullImmediate;
697 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
698 if(ctx.literals == NULL) {
699 r = -ENOMEM;
700 goto out_err;
701 }
702 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
703 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
704 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
705 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
706 ctx.nliterals++;
707 break;
708 case TGSI_TOKEN_TYPE_DECLARATION:
709 r = tgsi_declaration(&ctx);
710 if (r)
711 goto out_err;
712 break;
713 case TGSI_TOKEN_TYPE_INSTRUCTION:
714 r = tgsi_is_supported(&ctx);
715 if (r)
716 goto out_err;
717 ctx.max_driver_temp_used = 0;
718 /* reserve first tmp for everyone */
719 r600_get_temp(&ctx);
720
721 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
722 if ((r = tgsi_split_constant(&ctx)))
723 goto out_err;
724 if ((r = tgsi_split_literal_constant(&ctx)))
725 goto out_err;
726 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
727 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
728 else
729 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
730 r = ctx.inst_info->process(&ctx);
731 if (r)
732 goto out_err;
733 break;
734 case TGSI_TOKEN_TYPE_PROPERTY:
735 property = &ctx.parse.FullToken.FullProperty;
736 if (property->Property.PropertyName == TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS) {
737 if (property->u[0].Data == 1)
738 shader->fs_write_all = TRUE;
739 }
740 break;
741 default:
742 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
743 r = -EINVAL;
744 goto out_err;
745 }
746 }
747 /* export output */
748 noutput = shader->noutput;
749 for (i = 0, pos0 = 0; i < noutput; i++) {
750 memset(&output[i], 0, sizeof(struct r600_bc_output));
751 output[i].gpr = shader->output[i].gpr;
752 output[i].elem_size = 3;
753 output[i].swizzle_x = 0;
754 output[i].swizzle_y = 1;
755 output[i].swizzle_z = 2;
756 output[i].swizzle_w = 3;
757 output[i].burst_count = 1;
758 output[i].barrier = 1;
759 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
760 output[i].array_base = i - pos0;
761 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
762 switch (ctx.type) {
763 case TGSI_PROCESSOR_VERTEX:
764 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
765 output[i].array_base = 60;
766 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
767 /* position doesn't count in array_base */
768 pos0++;
769 }
770 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
771 output[i].array_base = 61;
772 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
773 /* position doesn't count in array_base */
774 pos0++;
775 }
776 break;
777 case TGSI_PROCESSOR_FRAGMENT:
778 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
779 output[i].array_base = shader->output[i].sid;
780 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
781 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
782 output[i].array_base = 61;
783 output[i].swizzle_x = 2;
784 output[i].swizzle_y = 7;
785 output[i].swizzle_z = output[i].swizzle_w = 7;
786 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
787 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
788 output[i].array_base = 61;
789 output[i].swizzle_x = 7;
790 output[i].swizzle_y = 1;
791 output[i].swizzle_z = output[i].swizzle_w = 7;
792 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
793 } else {
794 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
795 r = -EINVAL;
796 goto out_err;
797 }
798 break;
799 default:
800 R600_ERR("unsupported processor type %d\n", ctx.type);
801 r = -EINVAL;
802 goto out_err;
803 }
804 }
805 /* add fake param output for vertex shader if no param is exported */
806 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
807 for (i = 0, pos0 = 0; i < noutput; i++) {
808 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
809 pos0 = 1;
810 break;
811 }
812 }
813 if (!pos0) {
814 memset(&output[i], 0, sizeof(struct r600_bc_output));
815 output[i].gpr = 0;
816 output[i].elem_size = 3;
817 output[i].swizzle_x = 0;
818 output[i].swizzle_y = 1;
819 output[i].swizzle_z = 2;
820 output[i].swizzle_w = 3;
821 output[i].burst_count = 1;
822 output[i].barrier = 1;
823 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
824 output[i].array_base = 0;
825 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
826 noutput++;
827 }
828 }
829 /* add fake pixel export */
830 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
831 memset(&output[0], 0, sizeof(struct r600_bc_output));
832 output[0].gpr = 0;
833 output[0].elem_size = 3;
834 output[0].swizzle_x = 7;
835 output[0].swizzle_y = 7;
836 output[0].swizzle_z = 7;
837 output[0].swizzle_w = 7;
838 output[0].burst_count = 1;
839 output[0].barrier = 1;
840 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
841 output[0].array_base = 0;
842 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
843 noutput++;
844 }
845 /* set export done on last export of each type */
846 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
847 if (i == (noutput - 1)) {
848 output[i].end_of_program = 1;
849 }
850 if (!(output_done & (1 << output[i].type))) {
851 output_done |= (1 << output[i].type);
852 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
853 }
854 }
855 /* add output to bytecode */
856 for (i = 0; i < noutput; i++) {
857 r = r600_bc_add_output(ctx.bc, &output[i]);
858 if (r)
859 goto out_err;
860 }
861 free(ctx.literals);
862 tgsi_parse_free(&ctx.parse);
863 return 0;
864 out_err:
865 free(ctx.literals);
866 tgsi_parse_free(&ctx.parse);
867 return r;
868 }
869
870 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
871 {
872 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
873 return -EINVAL;
874 }
875
876 static int tgsi_end(struct r600_shader_ctx *ctx)
877 {
878 return 0;
879 }
880
881 static void r600_bc_src(struct r600_bc_alu_src *bc_src,
882 const struct r600_shader_src *shader_src,
883 unsigned chan)
884 {
885 bc_src->sel = shader_src->sel;
886 bc_src->chan = shader_src->swizzle[chan];
887 bc_src->neg = shader_src->neg;
888 bc_src->abs = shader_src->abs;
889 bc_src->rel = shader_src->rel;
890 bc_src->value = shader_src->value[bc_src->chan];
891 }
892
893 static void tgsi_dst(struct r600_shader_ctx *ctx,
894 const struct tgsi_full_dst_register *tgsi_dst,
895 unsigned swizzle,
896 struct r600_bc_alu_dst *r600_dst)
897 {
898 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
899
900 r600_dst->sel = tgsi_dst->Register.Index;
901 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
902 r600_dst->chan = swizzle;
903 r600_dst->write = 1;
904 if (tgsi_dst->Register.Indirect)
905 r600_dst->rel = V_SQ_REL_RELATIVE;
906 if (inst->Instruction.Saturate) {
907 r600_dst->clamp = 1;
908 }
909 }
910
911 static int tgsi_last_instruction(unsigned writemask)
912 {
913 int i, lasti = 0;
914
915 for (i = 0; i < 4; i++) {
916 if (writemask & (1 << i)) {
917 lasti = i;
918 }
919 }
920 return lasti;
921 }
922
923 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
924 {
925 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
926 struct r600_bc_alu alu;
927 int i, j, r;
928 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
929
930 for (i = 0; i < lasti + 1; i++) {
931 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
932 continue;
933
934 memset(&alu, 0, sizeof(struct r600_bc_alu));
935 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
936
937 alu.inst = ctx->inst_info->r600_opcode;
938 if (!swap) {
939 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
940 r600_bc_src(&alu.src[j], &ctx->src[j], i);
941 }
942 } else {
943 r600_bc_src(&alu.src[0], &ctx->src[1], i);
944 r600_bc_src(&alu.src[1], &ctx->src[0], i);
945 }
946 /* handle some special cases */
947 switch (ctx->inst_info->tgsi_opcode) {
948 case TGSI_OPCODE_SUB:
949 alu.src[1].neg = 1;
950 break;
951 case TGSI_OPCODE_ABS:
952 alu.src[0].abs = 1;
953 break;
954 default:
955 break;
956 }
957 if (i == lasti) {
958 alu.last = 1;
959 }
960 r = r600_bc_add_alu(ctx->bc, &alu);
961 if (r)
962 return r;
963 }
964 return 0;
965 }
966
967 static int tgsi_op2(struct r600_shader_ctx *ctx)
968 {
969 return tgsi_op2_s(ctx, 0);
970 }
971
972 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
973 {
974 return tgsi_op2_s(ctx, 1);
975 }
976
977 /*
978 * r600 - trunc to -PI..PI range
979 * r700 - normalize by dividing by 2PI
980 * see fdo bug 27901
981 */
982 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
983 {
984 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
985 static float double_pi = 3.1415926535 * 2;
986 static float neg_pi = -3.1415926535;
987
988 int r;
989 struct r600_bc_alu alu;
990
991 memset(&alu, 0, sizeof(struct r600_bc_alu));
992 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
993 alu.is_op3 = 1;
994
995 alu.dst.chan = 0;
996 alu.dst.sel = ctx->temp_reg;
997 alu.dst.write = 1;
998
999 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
1000
1001 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1002 alu.src[1].chan = 0;
1003 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1004 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1005 alu.src[2].chan = 0;
1006 alu.last = 1;
1007 r = r600_bc_add_alu(ctx->bc, &alu);
1008 if (r)
1009 return r;
1010
1011 memset(&alu, 0, sizeof(struct r600_bc_alu));
1012 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1013
1014 alu.dst.chan = 0;
1015 alu.dst.sel = ctx->temp_reg;
1016 alu.dst.write = 1;
1017
1018 alu.src[0].sel = ctx->temp_reg;
1019 alu.src[0].chan = 0;
1020 alu.last = 1;
1021 r = r600_bc_add_alu(ctx->bc, &alu);
1022 if (r)
1023 return r;
1024
1025 memset(&alu, 0, sizeof(struct r600_bc_alu));
1026 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1027 alu.is_op3 = 1;
1028
1029 alu.dst.chan = 0;
1030 alu.dst.sel = ctx->temp_reg;
1031 alu.dst.write = 1;
1032
1033 alu.src[0].sel = ctx->temp_reg;
1034 alu.src[0].chan = 0;
1035
1036 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1037 alu.src[1].chan = 0;
1038 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1039 alu.src[2].chan = 0;
1040
1041 if (ctx->bc->chiprev == CHIPREV_R600) {
1042 alu.src[1].value = *(uint32_t *)&double_pi;
1043 alu.src[2].value = *(uint32_t *)&neg_pi;
1044 } else {
1045 alu.src[1].sel = V_SQ_ALU_SRC_1;
1046 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1047 alu.src[2].neg = 1;
1048 }
1049
1050 alu.last = 1;
1051 r = r600_bc_add_alu(ctx->bc, &alu);
1052 if (r)
1053 return r;
1054 return 0;
1055 }
1056
1057 static int tgsi_trig(struct r600_shader_ctx *ctx)
1058 {
1059 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1060 struct r600_bc_alu alu;
1061 int i, r;
1062 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1063
1064 r = tgsi_setup_trig(ctx);
1065 if (r)
1066 return r;
1067
1068 memset(&alu, 0, sizeof(struct r600_bc_alu));
1069 alu.inst = ctx->inst_info->r600_opcode;
1070 alu.dst.chan = 0;
1071 alu.dst.sel = ctx->temp_reg;
1072 alu.dst.write = 1;
1073
1074 alu.src[0].sel = ctx->temp_reg;
1075 alu.src[0].chan = 0;
1076 alu.last = 1;
1077 r = r600_bc_add_alu(ctx->bc, &alu);
1078 if (r)
1079 return r;
1080
1081 /* replicate result */
1082 for (i = 0; i < lasti + 1; i++) {
1083 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1084 continue;
1085
1086 memset(&alu, 0, sizeof(struct r600_bc_alu));
1087 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1088
1089 alu.src[0].sel = ctx->temp_reg;
1090 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1091 if (i == lasti)
1092 alu.last = 1;
1093 r = r600_bc_add_alu(ctx->bc, &alu);
1094 if (r)
1095 return r;
1096 }
1097 return 0;
1098 }
1099
1100 static int tgsi_scs(struct r600_shader_ctx *ctx)
1101 {
1102 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1103 struct r600_bc_alu alu;
1104 int r;
1105
1106 /* We'll only need the trig stuff if we are going to write to the
1107 * X or Y components of the destination vector.
1108 */
1109 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1110 r = tgsi_setup_trig(ctx);
1111 if (r)
1112 return r;
1113 }
1114
1115 /* dst.x = COS */
1116 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1117 memset(&alu, 0, sizeof(struct r600_bc_alu));
1118 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1119 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1120
1121 alu.src[0].sel = ctx->temp_reg;
1122 alu.src[0].chan = 0;
1123 alu.last = 1;
1124 r = r600_bc_add_alu(ctx->bc, &alu);
1125 if (r)
1126 return r;
1127 }
1128
1129 /* dst.y = SIN */
1130 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1131 memset(&alu, 0, sizeof(struct r600_bc_alu));
1132 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1133 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1134
1135 alu.src[0].sel = ctx->temp_reg;
1136 alu.src[0].chan = 0;
1137 alu.last = 1;
1138 r = r600_bc_add_alu(ctx->bc, &alu);
1139 if (r)
1140 return r;
1141 }
1142
1143 /* dst.z = 0.0; */
1144 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1145 memset(&alu, 0, sizeof(struct r600_bc_alu));
1146
1147 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1148
1149 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1150
1151 alu.src[0].sel = V_SQ_ALU_SRC_0;
1152 alu.src[0].chan = 0;
1153
1154 alu.last = 1;
1155
1156 r = r600_bc_add_alu(ctx->bc, &alu);
1157 if (r)
1158 return r;
1159 }
1160
1161 /* dst.w = 1.0; */
1162 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1163 memset(&alu, 0, sizeof(struct r600_bc_alu));
1164
1165 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1166
1167 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1168
1169 alu.src[0].sel = V_SQ_ALU_SRC_1;
1170 alu.src[0].chan = 0;
1171
1172 alu.last = 1;
1173
1174 r = r600_bc_add_alu(ctx->bc, &alu);
1175 if (r)
1176 return r;
1177 }
1178
1179 return 0;
1180 }
1181
1182 static int tgsi_kill(struct r600_shader_ctx *ctx)
1183 {
1184 struct r600_bc_alu alu;
1185 int i, r;
1186
1187 for (i = 0; i < 4; i++) {
1188 memset(&alu, 0, sizeof(struct r600_bc_alu));
1189 alu.inst = ctx->inst_info->r600_opcode;
1190
1191 alu.dst.chan = i;
1192
1193 alu.src[0].sel = V_SQ_ALU_SRC_0;
1194
1195 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1196 alu.src[1].sel = V_SQ_ALU_SRC_1;
1197 alu.src[1].neg = 1;
1198 } else {
1199 r600_bc_src(&alu.src[1], &ctx->src[0], i);
1200 }
1201 if (i == 3) {
1202 alu.last = 1;
1203 }
1204 r = r600_bc_add_alu(ctx->bc, &alu);
1205 if (r)
1206 return r;
1207 }
1208
1209 /* kill must be last in ALU */
1210 ctx->bc->force_add_cf = 1;
1211 ctx->shader->uses_kill = TRUE;
1212 return 0;
1213 }
1214
1215 static int tgsi_lit(struct r600_shader_ctx *ctx)
1216 {
1217 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1218 struct r600_bc_alu alu;
1219 int r;
1220
1221 /* dst.x, <- 1.0 */
1222 memset(&alu, 0, sizeof(struct r600_bc_alu));
1223 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1224 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1225 alu.src[0].chan = 0;
1226 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1227 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1228 r = r600_bc_add_alu(ctx->bc, &alu);
1229 if (r)
1230 return r;
1231
1232 /* dst.y = max(src.x, 0.0) */
1233 memset(&alu, 0, sizeof(struct r600_bc_alu));
1234 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1235 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
1236 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1237 alu.src[1].chan = 0;
1238 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1239 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1240 r = r600_bc_add_alu(ctx->bc, &alu);
1241 if (r)
1242 return r;
1243
1244 /* dst.w, <- 1.0 */
1245 memset(&alu, 0, sizeof(struct r600_bc_alu));
1246 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1247 alu.src[0].sel = V_SQ_ALU_SRC_1;
1248 alu.src[0].chan = 0;
1249 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1250 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1251 alu.last = 1;
1252 r = r600_bc_add_alu(ctx->bc, &alu);
1253 if (r)
1254 return r;
1255
1256 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1257 {
1258 int chan;
1259 int sel;
1260
1261 /* dst.z = log(src.y) */
1262 memset(&alu, 0, sizeof(struct r600_bc_alu));
1263 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1264 r600_bc_src(&alu.src[0], &ctx->src[0], 1);
1265 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1266 alu.last = 1;
1267 r = r600_bc_add_alu(ctx->bc, &alu);
1268 if (r)
1269 return r;
1270
1271 chan = alu.dst.chan;
1272 sel = alu.dst.sel;
1273
1274 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1275 memset(&alu, 0, sizeof(struct r600_bc_alu));
1276 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1277 r600_bc_src(&alu.src[0], &ctx->src[0], 3);
1278 alu.src[1].sel = sel;
1279 alu.src[1].chan = chan;
1280
1281 r600_bc_src(&alu.src[2], &ctx->src[0], 0);
1282 alu.dst.sel = ctx->temp_reg;
1283 alu.dst.chan = 0;
1284 alu.dst.write = 1;
1285 alu.is_op3 = 1;
1286 alu.last = 1;
1287 r = r600_bc_add_alu(ctx->bc, &alu);
1288 if (r)
1289 return r;
1290
1291 /* dst.z = exp(tmp.x) */
1292 memset(&alu, 0, sizeof(struct r600_bc_alu));
1293 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1294 alu.src[0].sel = ctx->temp_reg;
1295 alu.src[0].chan = 0;
1296 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1297 alu.last = 1;
1298 r = r600_bc_add_alu(ctx->bc, &alu);
1299 if (r)
1300 return r;
1301 }
1302 return 0;
1303 }
1304
1305 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1306 {
1307 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1308 struct r600_bc_alu alu;
1309 int i, r;
1310
1311 memset(&alu, 0, sizeof(struct r600_bc_alu));
1312
1313 /* FIXME:
1314 * For state trackers other than OpenGL, we'll want to use
1315 * _RECIPSQRT_IEEE instead.
1316 */
1317 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1318
1319 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1320 r600_bc_src(&alu.src[i], &ctx->src[i], 0);
1321 alu.src[i].abs = 1;
1322 }
1323 alu.dst.sel = ctx->temp_reg;
1324 alu.dst.write = 1;
1325 alu.last = 1;
1326 r = r600_bc_add_alu(ctx->bc, &alu);
1327 if (r)
1328 return r;
1329 /* replicate result */
1330 return tgsi_helper_tempx_replicate(ctx);
1331 }
1332
1333 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1334 {
1335 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1336 struct r600_bc_alu alu;
1337 int i, r;
1338
1339 for (i = 0; i < 4; i++) {
1340 memset(&alu, 0, sizeof(struct r600_bc_alu));
1341 alu.src[0].sel = ctx->temp_reg;
1342 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1343 alu.dst.chan = i;
1344 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1345 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1346 if (i == 3)
1347 alu.last = 1;
1348 r = r600_bc_add_alu(ctx->bc, &alu);
1349 if (r)
1350 return r;
1351 }
1352 return 0;
1353 }
1354
1355 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1356 {
1357 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1358 struct r600_bc_alu alu;
1359 int i, r;
1360
1361 memset(&alu, 0, sizeof(struct r600_bc_alu));
1362 alu.inst = ctx->inst_info->r600_opcode;
1363 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1364 r600_bc_src(&alu.src[i], &ctx->src[i], 0);
1365 }
1366 alu.dst.sel = ctx->temp_reg;
1367 alu.dst.write = 1;
1368 alu.last = 1;
1369 r = r600_bc_add_alu(ctx->bc, &alu);
1370 if (r)
1371 return r;
1372 /* replicate result */
1373 return tgsi_helper_tempx_replicate(ctx);
1374 }
1375
1376 static int tgsi_pow(struct r600_shader_ctx *ctx)
1377 {
1378 struct r600_bc_alu alu;
1379 int r;
1380
1381 /* LOG2(a) */
1382 memset(&alu, 0, sizeof(struct r600_bc_alu));
1383 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1384 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
1385 alu.dst.sel = ctx->temp_reg;
1386 alu.dst.write = 1;
1387 alu.last = 1;
1388 r = r600_bc_add_alu(ctx->bc, &alu);
1389 if (r)
1390 return r;
1391 /* b * LOG2(a) */
1392 memset(&alu, 0, sizeof(struct r600_bc_alu));
1393 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1394 r600_bc_src(&alu.src[0], &ctx->src[1], 0);
1395 alu.src[1].sel = ctx->temp_reg;
1396 alu.dst.sel = ctx->temp_reg;
1397 alu.dst.write = 1;
1398 alu.last = 1;
1399 r = r600_bc_add_alu(ctx->bc, &alu);
1400 if (r)
1401 return r;
1402 /* POW(a,b) = EXP2(b * LOG2(a))*/
1403 memset(&alu, 0, sizeof(struct r600_bc_alu));
1404 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1405 alu.src[0].sel = ctx->temp_reg;
1406 alu.dst.sel = ctx->temp_reg;
1407 alu.dst.write = 1;
1408 alu.last = 1;
1409 r = r600_bc_add_alu(ctx->bc, &alu);
1410 if (r)
1411 return r;
1412 return tgsi_helper_tempx_replicate(ctx);
1413 }
1414
1415 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1416 {
1417 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1418 struct r600_bc_alu alu;
1419 int i, r;
1420
1421 /* tmp = (src > 0 ? 1 : src) */
1422 for (i = 0; i < 4; i++) {
1423 memset(&alu, 0, sizeof(struct r600_bc_alu));
1424 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1425 alu.is_op3 = 1;
1426
1427 alu.dst.sel = ctx->temp_reg;
1428 alu.dst.chan = i;
1429
1430 r600_bc_src(&alu.src[0], &ctx->src[0], i);
1431 alu.src[1].sel = V_SQ_ALU_SRC_1;
1432 r600_bc_src(&alu.src[2], &ctx->src[0], i);
1433
1434 if (i == 3)
1435 alu.last = 1;
1436 r = r600_bc_add_alu(ctx->bc, &alu);
1437 if (r)
1438 return r;
1439 }
1440
1441 /* dst = (-tmp > 0 ? -1 : tmp) */
1442 for (i = 0; i < 4; i++) {
1443 memset(&alu, 0, sizeof(struct r600_bc_alu));
1444 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1445 alu.is_op3 = 1;
1446 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1447
1448 alu.src[0].sel = ctx->temp_reg;
1449 alu.src[0].chan = i;
1450 alu.src[0].neg = 1;
1451
1452 alu.src[1].sel = V_SQ_ALU_SRC_1;
1453 alu.src[1].neg = 1;
1454
1455 alu.src[2].sel = ctx->temp_reg;
1456 alu.src[2].chan = i;
1457
1458 if (i == 3)
1459 alu.last = 1;
1460 r = r600_bc_add_alu(ctx->bc, &alu);
1461 if (r)
1462 return r;
1463 }
1464 return 0;
1465 }
1466
1467 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1468 {
1469 struct r600_bc_alu alu;
1470 int i, r;
1471
1472 for (i = 0; i < 4; i++) {
1473 memset(&alu, 0, sizeof(struct r600_bc_alu));
1474 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1475 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1476 alu.dst.chan = i;
1477 } else {
1478 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1479 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1480 alu.src[0].sel = ctx->temp_reg;
1481 alu.src[0].chan = i;
1482 }
1483 if (i == 3) {
1484 alu.last = 1;
1485 }
1486 r = r600_bc_add_alu(ctx->bc, &alu);
1487 if (r)
1488 return r;
1489 }
1490 return 0;
1491 }
1492
1493 static int tgsi_op3(struct r600_shader_ctx *ctx)
1494 {
1495 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1496 struct r600_bc_alu alu;
1497 int i, j, r;
1498 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1499
1500 for (i = 0; i < lasti + 1; i++) {
1501 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1502 continue;
1503
1504 memset(&alu, 0, sizeof(struct r600_bc_alu));
1505 alu.inst = ctx->inst_info->r600_opcode;
1506 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1507 r600_bc_src(&alu.src[j], &ctx->src[j], i);
1508 }
1509
1510 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1511 alu.dst.chan = i;
1512 alu.dst.write = 1;
1513 alu.is_op3 = 1;
1514 if (i == lasti) {
1515 alu.last = 1;
1516 }
1517 r = r600_bc_add_alu(ctx->bc, &alu);
1518 if (r)
1519 return r;
1520 }
1521 return 0;
1522 }
1523
1524 static int tgsi_dp(struct r600_shader_ctx *ctx)
1525 {
1526 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1527 struct r600_bc_alu alu;
1528 int i, j, r;
1529
1530 for (i = 0; i < 4; i++) {
1531 memset(&alu, 0, sizeof(struct r600_bc_alu));
1532 alu.inst = ctx->inst_info->r600_opcode;
1533 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1534 r600_bc_src(&alu.src[j], &ctx->src[j], i);
1535 }
1536
1537 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1538 alu.dst.chan = i;
1539 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1540 /* handle some special cases */
1541 switch (ctx->inst_info->tgsi_opcode) {
1542 case TGSI_OPCODE_DP2:
1543 if (i > 1) {
1544 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1545 alu.src[0].chan = alu.src[1].chan = 0;
1546 }
1547 break;
1548 case TGSI_OPCODE_DP3:
1549 if (i > 2) {
1550 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1551 alu.src[0].chan = alu.src[1].chan = 0;
1552 }
1553 break;
1554 case TGSI_OPCODE_DPH:
1555 if (i == 3) {
1556 alu.src[0].sel = V_SQ_ALU_SRC_1;
1557 alu.src[0].chan = 0;
1558 alu.src[0].neg = 0;
1559 }
1560 break;
1561 default:
1562 break;
1563 }
1564 if (i == 3) {
1565 alu.last = 1;
1566 }
1567 r = r600_bc_add_alu(ctx->bc, &alu);
1568 if (r)
1569 return r;
1570 }
1571 return 0;
1572 }
1573
1574 static int tgsi_tex(struct r600_shader_ctx *ctx)
1575 {
1576 static float one_point_five = 1.5f;
1577 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1578 struct r600_bc_tex tex;
1579 struct r600_bc_alu alu;
1580 unsigned src_gpr;
1581 int r, i;
1582 int opcode;
1583 boolean src_not_temp =
1584 inst->Src[0].Register.File != TGSI_FILE_TEMPORARY &&
1585 inst->Src[0].Register.File != TGSI_FILE_INPUT;
1586
1587 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1588
1589 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1590 /* Add perspective divide */
1591 memset(&alu, 0, sizeof(struct r600_bc_alu));
1592 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1593 r600_bc_src(&alu.src[0], &ctx->src[0], 3);
1594
1595 alu.dst.sel = ctx->temp_reg;
1596 alu.dst.chan = 3;
1597 alu.last = 1;
1598 alu.dst.write = 1;
1599 r = r600_bc_add_alu(ctx->bc, &alu);
1600 if (r)
1601 return r;
1602
1603 for (i = 0; i < 3; i++) {
1604 memset(&alu, 0, sizeof(struct r600_bc_alu));
1605 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1606 alu.src[0].sel = ctx->temp_reg;
1607 alu.src[0].chan = 3;
1608 r600_bc_src(&alu.src[1], &ctx->src[0], i);
1609 alu.dst.sel = ctx->temp_reg;
1610 alu.dst.chan = i;
1611 alu.dst.write = 1;
1612 r = r600_bc_add_alu(ctx->bc, &alu);
1613 if (r)
1614 return r;
1615 }
1616 memset(&alu, 0, sizeof(struct r600_bc_alu));
1617 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1618 alu.src[0].sel = V_SQ_ALU_SRC_1;
1619 alu.src[0].chan = 0;
1620 alu.dst.sel = ctx->temp_reg;
1621 alu.dst.chan = 3;
1622 alu.last = 1;
1623 alu.dst.write = 1;
1624 r = r600_bc_add_alu(ctx->bc, &alu);
1625 if (r)
1626 return r;
1627 src_not_temp = FALSE;
1628 src_gpr = ctx->temp_reg;
1629 }
1630
1631 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1632 int src_chan, src2_chan;
1633
1634 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1635 for (i = 0; i < 4; i++) {
1636 memset(&alu, 0, sizeof(struct r600_bc_alu));
1637 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1638 switch (i) {
1639 case 0:
1640 src_chan = 2;
1641 src2_chan = 1;
1642 break;
1643 case 1:
1644 src_chan = 2;
1645 src2_chan = 0;
1646 break;
1647 case 2:
1648 src_chan = 0;
1649 src2_chan = 2;
1650 break;
1651 case 3:
1652 src_chan = 1;
1653 src2_chan = 2;
1654 break;
1655 default:
1656 assert(0);
1657 src_chan = 0;
1658 src2_chan = 0;
1659 break;
1660 }
1661 r600_bc_src(&alu.src[0], &ctx->src[0], src_chan);
1662 r600_bc_src(&alu.src[1], &ctx->src[0], src2_chan);
1663 alu.dst.sel = ctx->temp_reg;
1664 alu.dst.chan = i;
1665 if (i == 3)
1666 alu.last = 1;
1667 alu.dst.write = 1;
1668 r = r600_bc_add_alu(ctx->bc, &alu);
1669 if (r)
1670 return r;
1671 }
1672
1673 /* tmp1.z = RCP_e(|tmp1.z|) */
1674 memset(&alu, 0, sizeof(struct r600_bc_alu));
1675 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1676 alu.src[0].sel = ctx->temp_reg;
1677 alu.src[0].chan = 2;
1678 alu.src[0].abs = 1;
1679 alu.dst.sel = ctx->temp_reg;
1680 alu.dst.chan = 2;
1681 alu.dst.write = 1;
1682 alu.last = 1;
1683 r = r600_bc_add_alu(ctx->bc, &alu);
1684 if (r)
1685 return r;
1686
1687 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1688 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1689 * muladd has no writemask, have to use another temp
1690 */
1691 memset(&alu, 0, sizeof(struct r600_bc_alu));
1692 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1693 alu.is_op3 = 1;
1694
1695 alu.src[0].sel = ctx->temp_reg;
1696 alu.src[0].chan = 0;
1697 alu.src[1].sel = ctx->temp_reg;
1698 alu.src[1].chan = 2;
1699
1700 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1701 alu.src[2].chan = 0;
1702 alu.src[2].value = *(uint32_t *)&one_point_five;
1703
1704 alu.dst.sel = ctx->temp_reg;
1705 alu.dst.chan = 0;
1706 alu.dst.write = 1;
1707
1708 r = r600_bc_add_alu(ctx->bc, &alu);
1709 if (r)
1710 return r;
1711
1712 memset(&alu, 0, sizeof(struct r600_bc_alu));
1713 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1714 alu.is_op3 = 1;
1715
1716 alu.src[0].sel = ctx->temp_reg;
1717 alu.src[0].chan = 1;
1718 alu.src[1].sel = ctx->temp_reg;
1719 alu.src[1].chan = 2;
1720
1721 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1722 alu.src[2].chan = 0;
1723 alu.src[2].value = *(uint32_t *)&one_point_five;
1724
1725 alu.dst.sel = ctx->temp_reg;
1726 alu.dst.chan = 1;
1727 alu.dst.write = 1;
1728
1729 alu.last = 1;
1730 r = r600_bc_add_alu(ctx->bc, &alu);
1731 if (r)
1732 return r;
1733
1734 src_not_temp = FALSE;
1735 src_gpr = ctx->temp_reg;
1736 }
1737
1738 if (src_not_temp) {
1739 for (i = 0; i < 4; i++) {
1740 memset(&alu, 0, sizeof(struct r600_bc_alu));
1741 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1742 r600_bc_src(&alu.src[0], &ctx->src[0], i);
1743 alu.dst.sel = ctx->temp_reg;
1744 alu.dst.chan = i;
1745 if (i == 3)
1746 alu.last = 1;
1747 alu.dst.write = 1;
1748 r = r600_bc_add_alu(ctx->bc, &alu);
1749 if (r)
1750 return r;
1751 }
1752 src_gpr = ctx->temp_reg;
1753 }
1754
1755 opcode = ctx->inst_info->r600_opcode;
1756 if (opcode == SQ_TEX_INST_SAMPLE &&
1757 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1758 opcode = SQ_TEX_INST_SAMPLE_C;
1759
1760 memset(&tex, 0, sizeof(struct r600_bc_tex));
1761 tex.inst = opcode;
1762 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1763 tex.resource_id = tex.sampler_id;
1764 tex.src_gpr = src_gpr;
1765 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1766 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1767 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1768 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1769 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1770 tex.src_sel_x = 0;
1771 tex.src_sel_y = 1;
1772 tex.src_sel_z = 2;
1773 tex.src_sel_w = 3;
1774
1775 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1776 tex.src_sel_x = 1;
1777 tex.src_sel_y = 0;
1778 tex.src_sel_z = 3;
1779 tex.src_sel_w = 1;
1780 }
1781
1782 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1783 tex.coord_type_x = 1;
1784 tex.coord_type_y = 1;
1785 tex.coord_type_z = 1;
1786 tex.coord_type_w = 1;
1787 }
1788
1789 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1790 tex.src_sel_w = 2;
1791
1792 r = r600_bc_add_tex(ctx->bc, &tex);
1793 if (r)
1794 return r;
1795
1796 /* add shadow ambient support - gallium doesn't do it yet */
1797 return 0;
1798 }
1799
1800 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1801 {
1802 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1803 struct r600_bc_alu alu;
1804 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1805 unsigned i;
1806 int r;
1807
1808 /* optimize if it's just an equal balance */
1809 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
1810 for (i = 0; i < lasti + 1; i++) {
1811 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1812 continue;
1813
1814 memset(&alu, 0, sizeof(struct r600_bc_alu));
1815 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1816 r600_bc_src(&alu.src[0], &ctx->src[1], i);
1817 r600_bc_src(&alu.src[1], &ctx->src[2], i);
1818 alu.omod = 3;
1819 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1820 alu.dst.chan = i;
1821 if (i == lasti) {
1822 alu.last = 1;
1823 }
1824 r = r600_bc_add_alu(ctx->bc, &alu);
1825 if (r)
1826 return r;
1827 }
1828 return 0;
1829 }
1830
1831 /* 1 - src0 */
1832 for (i = 0; i < lasti + 1; i++) {
1833 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1834 continue;
1835
1836 memset(&alu, 0, sizeof(struct r600_bc_alu));
1837 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1838 alu.src[0].sel = V_SQ_ALU_SRC_1;
1839 alu.src[0].chan = 0;
1840 r600_bc_src(&alu.src[1], &ctx->src[0], i);
1841 alu.src[1].neg = 1;
1842 alu.dst.sel = ctx->temp_reg;
1843 alu.dst.chan = i;
1844 if (i == lasti) {
1845 alu.last = 1;
1846 }
1847 alu.dst.write = 1;
1848 r = r600_bc_add_alu(ctx->bc, &alu);
1849 if (r)
1850 return r;
1851 }
1852
1853 /* (1 - src0) * src2 */
1854 for (i = 0; i < lasti + 1; i++) {
1855 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1856 continue;
1857
1858 memset(&alu, 0, sizeof(struct r600_bc_alu));
1859 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1860 alu.src[0].sel = ctx->temp_reg;
1861 alu.src[0].chan = i;
1862 r600_bc_src(&alu.src[1], &ctx->src[2], i);
1863 alu.dst.sel = ctx->temp_reg;
1864 alu.dst.chan = i;
1865 if (i == lasti) {
1866 alu.last = 1;
1867 }
1868 alu.dst.write = 1;
1869 r = r600_bc_add_alu(ctx->bc, &alu);
1870 if (r)
1871 return r;
1872 }
1873
1874 /* src0 * src1 + (1 - src0) * src2 */
1875 for (i = 0; i < lasti + 1; i++) {
1876 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1877 continue;
1878
1879 memset(&alu, 0, sizeof(struct r600_bc_alu));
1880 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1881 alu.is_op3 = 1;
1882 r600_bc_src(&alu.src[0], &ctx->src[0], i);
1883 r600_bc_src(&alu.src[1], &ctx->src[1], i);
1884 alu.src[2].sel = ctx->temp_reg;
1885 alu.src[2].chan = i;
1886
1887 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1888 alu.dst.chan = i;
1889 if (i == lasti) {
1890 alu.last = 1;
1891 }
1892 r = r600_bc_add_alu(ctx->bc, &alu);
1893 if (r)
1894 return r;
1895 }
1896 return 0;
1897 }
1898
1899 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1900 {
1901 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1902 struct r600_bc_alu alu;
1903 int i, r;
1904 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1905
1906 for (i = 0; i < lasti + 1; i++) {
1907 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1908 continue;
1909
1910 memset(&alu, 0, sizeof(struct r600_bc_alu));
1911 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1912 r600_bc_src(&alu.src[0], &ctx->src[0], i);
1913 r600_bc_src(&alu.src[1], &ctx->src[2], i);
1914 r600_bc_src(&alu.src[2], &ctx->src[1], i);
1915 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1916 alu.dst.chan = i;
1917 alu.dst.write = 1;
1918 alu.is_op3 = 1;
1919 if (i == lasti)
1920 alu.last = 1;
1921 r = r600_bc_add_alu(ctx->bc, &alu);
1922 if (r)
1923 return r;
1924 }
1925 return 0;
1926 }
1927
1928 static int tgsi_xpd(struct r600_shader_ctx *ctx)
1929 {
1930 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1931 struct r600_bc_alu alu;
1932 uint32_t use_temp = 0;
1933 int i, r;
1934
1935 if (inst->Dst[0].Register.WriteMask != 0xf)
1936 use_temp = 1;
1937
1938 for (i = 0; i < 4; i++) {
1939 memset(&alu, 0, sizeof(struct r600_bc_alu));
1940 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1941
1942 switch (i) {
1943 case 0:
1944 r600_bc_src(&alu.src[0], &ctx->src[0], 2);
1945 break;
1946 case 1:
1947 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
1948 break;
1949 case 2:
1950 r600_bc_src(&alu.src[0], &ctx->src[0], 1);
1951 break;
1952 case 3:
1953 alu.src[0].sel = V_SQ_ALU_SRC_0;
1954 alu.src[0].chan = i;
1955 }
1956
1957 switch (i) {
1958 case 0:
1959 r600_bc_src(&alu.src[1], &ctx->src[1], 1);
1960 break;
1961 case 1:
1962 r600_bc_src(&alu.src[1], &ctx->src[1], 2);
1963 break;
1964 case 2:
1965 r600_bc_src(&alu.src[1], &ctx->src[1], 0);
1966 break;
1967 case 3:
1968 alu.src[1].sel = V_SQ_ALU_SRC_0;
1969 alu.src[1].chan = i;
1970 }
1971
1972 alu.dst.sel = ctx->temp_reg;
1973 alu.dst.chan = i;
1974 alu.dst.write = 1;
1975
1976 if (i == 3)
1977 alu.last = 1;
1978 r = r600_bc_add_alu(ctx->bc, &alu);
1979 if (r)
1980 return r;
1981 }
1982
1983 for (i = 0; i < 4; i++) {
1984 memset(&alu, 0, sizeof(struct r600_bc_alu));
1985 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1986
1987 switch (i) {
1988 case 0:
1989 r600_bc_src(&alu.src[0], &ctx->src[0], 1);
1990 break;
1991 case 1:
1992 r600_bc_src(&alu.src[0], &ctx->src[0], 2);
1993 break;
1994 case 2:
1995 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
1996 break;
1997 case 3:
1998 alu.src[0].sel = V_SQ_ALU_SRC_0;
1999 alu.src[0].chan = i;
2000 }
2001
2002 switch (i) {
2003 case 0:
2004 r600_bc_src(&alu.src[1], &ctx->src[1], 2);
2005 break;
2006 case 1:
2007 r600_bc_src(&alu.src[1], &ctx->src[1], 0);
2008 break;
2009 case 2:
2010 r600_bc_src(&alu.src[1], &ctx->src[1], 1);
2011 break;
2012 case 3:
2013 alu.src[1].sel = V_SQ_ALU_SRC_0;
2014 alu.src[1].chan = i;
2015 }
2016
2017 alu.src[2].sel = ctx->temp_reg;
2018 alu.src[2].neg = 1;
2019 alu.src[2].chan = i;
2020
2021 if (use_temp)
2022 alu.dst.sel = ctx->temp_reg;
2023 else
2024 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2025 alu.dst.chan = i;
2026 alu.dst.write = 1;
2027 alu.is_op3 = 1;
2028 if (i == 3)
2029 alu.last = 1;
2030 r = r600_bc_add_alu(ctx->bc, &alu);
2031 if (r)
2032 return r;
2033 }
2034 if (use_temp)
2035 return tgsi_helper_copy(ctx, inst);
2036 return 0;
2037 }
2038
2039 static int tgsi_exp(struct r600_shader_ctx *ctx)
2040 {
2041 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2042 struct r600_bc_alu alu;
2043 int r;
2044
2045 /* result.x = 2^floor(src); */
2046 if (inst->Dst[0].Register.WriteMask & 1) {
2047 memset(&alu, 0, sizeof(struct r600_bc_alu));
2048
2049 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2050 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2051
2052 alu.dst.sel = ctx->temp_reg;
2053 alu.dst.chan = 0;
2054 alu.dst.write = 1;
2055 alu.last = 1;
2056 r = r600_bc_add_alu(ctx->bc, &alu);
2057 if (r)
2058 return r;
2059
2060 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2061 alu.src[0].sel = ctx->temp_reg;
2062 alu.src[0].chan = 0;
2063
2064 alu.dst.sel = ctx->temp_reg;
2065 alu.dst.chan = 0;
2066 alu.dst.write = 1;
2067 alu.last = 1;
2068 r = r600_bc_add_alu(ctx->bc, &alu);
2069 if (r)
2070 return r;
2071 }
2072
2073 /* result.y = tmp - floor(tmp); */
2074 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2075 memset(&alu, 0, sizeof(struct r600_bc_alu));
2076
2077 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2078 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2079
2080 alu.dst.sel = ctx->temp_reg;
2081 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2082 // if (r)
2083 // return r;
2084 alu.dst.write = 1;
2085 alu.dst.chan = 1;
2086
2087 alu.last = 1;
2088
2089 r = r600_bc_add_alu(ctx->bc, &alu);
2090 if (r)
2091 return r;
2092 }
2093
2094 /* result.z = RoughApprox2ToX(tmp);*/
2095 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2096 memset(&alu, 0, sizeof(struct r600_bc_alu));
2097 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2098 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2099
2100 alu.dst.sel = ctx->temp_reg;
2101 alu.dst.write = 1;
2102 alu.dst.chan = 2;
2103
2104 alu.last = 1;
2105
2106 r = r600_bc_add_alu(ctx->bc, &alu);
2107 if (r)
2108 return r;
2109 }
2110
2111 /* result.w = 1.0;*/
2112 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2113 memset(&alu, 0, sizeof(struct r600_bc_alu));
2114
2115 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2116 alu.src[0].sel = V_SQ_ALU_SRC_1;
2117 alu.src[0].chan = 0;
2118
2119 alu.dst.sel = ctx->temp_reg;
2120 alu.dst.chan = 3;
2121 alu.dst.write = 1;
2122 alu.last = 1;
2123 r = r600_bc_add_alu(ctx->bc, &alu);
2124 if (r)
2125 return r;
2126 }
2127 return tgsi_helper_copy(ctx, inst);
2128 }
2129
2130 static int tgsi_log(struct r600_shader_ctx *ctx)
2131 {
2132 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2133 struct r600_bc_alu alu;
2134 int r;
2135
2136 /* result.x = floor(log2(src)); */
2137 if (inst->Dst[0].Register.WriteMask & 1) {
2138 memset(&alu, 0, sizeof(struct r600_bc_alu));
2139
2140 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2141 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2142
2143 alu.dst.sel = ctx->temp_reg;
2144 alu.dst.chan = 0;
2145 alu.dst.write = 1;
2146 alu.last = 1;
2147 r = r600_bc_add_alu(ctx->bc, &alu);
2148 if (r)
2149 return r;
2150
2151 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2152 alu.src[0].sel = ctx->temp_reg;
2153 alu.src[0].chan = 0;
2154
2155 alu.dst.sel = ctx->temp_reg;
2156 alu.dst.chan = 0;
2157 alu.dst.write = 1;
2158 alu.last = 1;
2159
2160 r = r600_bc_add_alu(ctx->bc, &alu);
2161 if (r)
2162 return r;
2163 }
2164
2165 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2166 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2167 memset(&alu, 0, sizeof(struct r600_bc_alu));
2168
2169 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2170 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2171
2172 alu.dst.sel = ctx->temp_reg;
2173 alu.dst.chan = 1;
2174 alu.dst.write = 1;
2175 alu.last = 1;
2176
2177 r = r600_bc_add_alu(ctx->bc, &alu);
2178 if (r)
2179 return r;
2180
2181 memset(&alu, 0, sizeof(struct r600_bc_alu));
2182
2183 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2184 alu.src[0].sel = ctx->temp_reg;
2185 alu.src[0].chan = 1;
2186
2187 alu.dst.sel = ctx->temp_reg;
2188 alu.dst.chan = 1;
2189 alu.dst.write = 1;
2190 alu.last = 1;
2191
2192 r = r600_bc_add_alu(ctx->bc, &alu);
2193 if (r)
2194 return r;
2195
2196 memset(&alu, 0, sizeof(struct r600_bc_alu));
2197
2198 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2199 alu.src[0].sel = ctx->temp_reg;
2200 alu.src[0].chan = 1;
2201
2202 alu.dst.sel = ctx->temp_reg;
2203 alu.dst.chan = 1;
2204 alu.dst.write = 1;
2205 alu.last = 1;
2206
2207 r = r600_bc_add_alu(ctx->bc, &alu);
2208 if (r)
2209 return r;
2210
2211 memset(&alu, 0, sizeof(struct r600_bc_alu));
2212
2213 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2214 alu.src[0].sel = ctx->temp_reg;
2215 alu.src[0].chan = 1;
2216
2217 alu.dst.sel = ctx->temp_reg;
2218 alu.dst.chan = 1;
2219 alu.dst.write = 1;
2220 alu.last = 1;
2221
2222 r = r600_bc_add_alu(ctx->bc, &alu);
2223 if (r)
2224 return r;
2225
2226 memset(&alu, 0, sizeof(struct r600_bc_alu));
2227
2228 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2229
2230 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2231
2232 alu.src[1].sel = ctx->temp_reg;
2233 alu.src[1].chan = 1;
2234
2235 alu.dst.sel = ctx->temp_reg;
2236 alu.dst.chan = 1;
2237 alu.dst.write = 1;
2238 alu.last = 1;
2239
2240 r = r600_bc_add_alu(ctx->bc, &alu);
2241 if (r)
2242 return r;
2243 }
2244
2245 /* result.z = log2(src);*/
2246 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2247 memset(&alu, 0, sizeof(struct r600_bc_alu));
2248
2249 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2250 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2251
2252 alu.dst.sel = ctx->temp_reg;
2253 alu.dst.write = 1;
2254 alu.dst.chan = 2;
2255 alu.last = 1;
2256
2257 r = r600_bc_add_alu(ctx->bc, &alu);
2258 if (r)
2259 return r;
2260 }
2261
2262 /* result.w = 1.0; */
2263 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2264 memset(&alu, 0, sizeof(struct r600_bc_alu));
2265
2266 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2267 alu.src[0].sel = V_SQ_ALU_SRC_1;
2268 alu.src[0].chan = 0;
2269
2270 alu.dst.sel = ctx->temp_reg;
2271 alu.dst.chan = 3;
2272 alu.dst.write = 1;
2273 alu.last = 1;
2274
2275 r = r600_bc_add_alu(ctx->bc, &alu);
2276 if (r)
2277 return r;
2278 }
2279
2280 return tgsi_helper_copy(ctx, inst);
2281 }
2282
2283 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2284 {
2285 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2286 struct r600_bc_alu alu;
2287 int r;
2288
2289 memset(&alu, 0, sizeof(struct r600_bc_alu));
2290
2291 switch (inst->Instruction.Opcode) {
2292 case TGSI_OPCODE_ARL:
2293 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2294 break;
2295 case TGSI_OPCODE_ARR:
2296 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2297 break;
2298 default:
2299 assert(0);
2300 return -1;
2301 }
2302
2303 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2304 alu.last = 1;
2305 alu.dst.chan = 0;
2306 alu.dst.sel = ctx->temp_reg;
2307 alu.dst.write = 1;
2308 r = r600_bc_add_alu(ctx->bc, &alu);
2309 if (r)
2310 return r;
2311 memset(&alu, 0, sizeof(struct r600_bc_alu));
2312 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2313 alu.src[0].sel = ctx->temp_reg;
2314 alu.src[0].chan = 0;
2315 alu.last = 1;
2316 r = r600_bc_add_alu(ctx->bc, &alu);
2317 if (r)
2318 return r;
2319 return 0;
2320 }
2321 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2322 {
2323 /* TODO from r600c, ar values don't persist between clauses */
2324 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2325 struct r600_bc_alu alu;
2326 int r;
2327
2328 memset(&alu, 0, sizeof(struct r600_bc_alu));
2329
2330 switch (inst->Instruction.Opcode) {
2331 case TGSI_OPCODE_ARL:
2332 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2333 break;
2334 case TGSI_OPCODE_ARR:
2335 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2336 break;
2337 default:
2338 assert(0);
2339 return -1;
2340 }
2341
2342 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2343
2344 alu.last = 1;
2345
2346 r = r600_bc_add_alu(ctx->bc, &alu);
2347 if (r)
2348 return r;
2349 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2350 return 0;
2351 }
2352
2353 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2354 {
2355 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2356 struct r600_bc_alu alu;
2357 int i, r = 0;
2358
2359 for (i = 0; i < 4; i++) {
2360 memset(&alu, 0, sizeof(struct r600_bc_alu));
2361
2362 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2363 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2364
2365 if (i == 0 || i == 3) {
2366 alu.src[0].sel = V_SQ_ALU_SRC_1;
2367 } else {
2368 r600_bc_src(&alu.src[0], &ctx->src[0], i);
2369 }
2370
2371 if (i == 0 || i == 2) {
2372 alu.src[1].sel = V_SQ_ALU_SRC_1;
2373 } else {
2374 r600_bc_src(&alu.src[1], &ctx->src[1], i);
2375 }
2376 if (i == 3)
2377 alu.last = 1;
2378 r = r600_bc_add_alu(ctx->bc, &alu);
2379 if (r)
2380 return r;
2381 }
2382 return 0;
2383 }
2384
2385 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2386 {
2387 struct r600_bc_alu alu;
2388 int r;
2389
2390 memset(&alu, 0, sizeof(struct r600_bc_alu));
2391 alu.inst = opcode;
2392 alu.predicate = 1;
2393
2394 alu.dst.sel = ctx->temp_reg;
2395 alu.dst.write = 1;
2396 alu.dst.chan = 0;
2397
2398 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2399 alu.src[1].sel = V_SQ_ALU_SRC_0;
2400 alu.src[1].chan = 0;
2401
2402 alu.last = 1;
2403
2404 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2405 if (r)
2406 return r;
2407 return 0;
2408 }
2409
2410 static int pops(struct r600_shader_ctx *ctx, int pops)
2411 {
2412 int alu_pop = 3;
2413 if (ctx->bc->cf_last) {
2414 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) << 3)
2415 alu_pop = 0;
2416 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3)
2417 alu_pop = 1;
2418 }
2419 alu_pop += pops;
2420 if (alu_pop == 1) {
2421 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3;
2422 ctx->bc->force_add_cf = 1;
2423 } else if (alu_pop == 2) {
2424 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER) << 3;
2425 ctx->bc->force_add_cf = 1;
2426 } else {
2427 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2428 ctx->bc->cf_last->pop_count = pops;
2429 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2430 }
2431 return 0;
2432 }
2433
2434 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2435 {
2436 switch(reason) {
2437 case FC_PUSH_VPM:
2438 ctx->bc->callstack[ctx->bc->call_sp].current--;
2439 break;
2440 case FC_PUSH_WQM:
2441 case FC_LOOP:
2442 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2443 break;
2444 case FC_REP:
2445 /* TOODO : for 16 vp asic should -= 2; */
2446 ctx->bc->callstack[ctx->bc->call_sp].current --;
2447 break;
2448 }
2449 }
2450
2451 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2452 {
2453 if (check_max_only) {
2454 int diff;
2455 switch (reason) {
2456 case FC_PUSH_VPM:
2457 diff = 1;
2458 break;
2459 case FC_PUSH_WQM:
2460 diff = 4;
2461 break;
2462 default:
2463 assert(0);
2464 diff = 0;
2465 }
2466 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2467 ctx->bc->callstack[ctx->bc->call_sp].max) {
2468 ctx->bc->callstack[ctx->bc->call_sp].max =
2469 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2470 }
2471 return;
2472 }
2473 switch (reason) {
2474 case FC_PUSH_VPM:
2475 ctx->bc->callstack[ctx->bc->call_sp].current++;
2476 break;
2477 case FC_PUSH_WQM:
2478 case FC_LOOP:
2479 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2480 break;
2481 case FC_REP:
2482 ctx->bc->callstack[ctx->bc->call_sp].current++;
2483 break;
2484 }
2485
2486 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2487 ctx->bc->callstack[ctx->bc->call_sp].max) {
2488 ctx->bc->callstack[ctx->bc->call_sp].max =
2489 ctx->bc->callstack[ctx->bc->call_sp].current;
2490 }
2491 }
2492
2493 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2494 {
2495 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2496
2497 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2498 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2499 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2500 sp->num_mid++;
2501 }
2502
2503 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2504 {
2505 ctx->bc->fc_sp++;
2506 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2507 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2508 }
2509
2510 static void fc_poplevel(struct r600_shader_ctx *ctx)
2511 {
2512 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2513 if (sp->mid) {
2514 free(sp->mid);
2515 sp->mid = NULL;
2516 }
2517 sp->num_mid = 0;
2518 sp->start = NULL;
2519 sp->type = 0;
2520 ctx->bc->fc_sp--;
2521 }
2522
2523 #if 0
2524 static int emit_return(struct r600_shader_ctx *ctx)
2525 {
2526 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2527 return 0;
2528 }
2529
2530 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2531 {
2532
2533 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2534 ctx->bc->cf_last->pop_count = pops;
2535 /* TODO work out offset */
2536 return 0;
2537 }
2538
2539 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2540 {
2541 return 0;
2542 }
2543
2544 static void emit_testflag(struct r600_shader_ctx *ctx)
2545 {
2546
2547 }
2548
2549 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2550 {
2551 emit_testflag(ctx);
2552 emit_jump_to_offset(ctx, 1, 4);
2553 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2554 pops(ctx, ifidx + 1);
2555 emit_return(ctx);
2556 }
2557
2558 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2559 {
2560 emit_testflag(ctx);
2561
2562 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2563 ctx->bc->cf_last->pop_count = 1;
2564
2565 fc_set_mid(ctx, fc_sp);
2566
2567 pops(ctx, 1);
2568 }
2569 #endif
2570
2571 static int tgsi_if(struct r600_shader_ctx *ctx)
2572 {
2573 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2574
2575 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2576
2577 fc_pushlevel(ctx, FC_IF);
2578
2579 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2580 return 0;
2581 }
2582
2583 static int tgsi_else(struct r600_shader_ctx *ctx)
2584 {
2585 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2586 ctx->bc->cf_last->pop_count = 1;
2587
2588 fc_set_mid(ctx, ctx->bc->fc_sp);
2589 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2590 return 0;
2591 }
2592
2593 static int tgsi_endif(struct r600_shader_ctx *ctx)
2594 {
2595 pops(ctx, 1);
2596 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2597 R600_ERR("if/endif unbalanced in shader\n");
2598 return -1;
2599 }
2600
2601 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2602 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2603 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2604 } else {
2605 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2606 }
2607 fc_poplevel(ctx);
2608
2609 callstack_decrease_current(ctx, FC_PUSH_VPM);
2610 return 0;
2611 }
2612
2613 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2614 {
2615 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2616
2617 fc_pushlevel(ctx, FC_LOOP);
2618
2619 /* check stack depth */
2620 callstack_check_depth(ctx, FC_LOOP, 0);
2621 return 0;
2622 }
2623
2624 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2625 {
2626 int i;
2627
2628 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2629
2630 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2631 R600_ERR("loop/endloop in shader code are not paired.\n");
2632 return -EINVAL;
2633 }
2634
2635 /* fixup loop pointers - from r600isa
2636 LOOP END points to CF after LOOP START,
2637 LOOP START point to CF after LOOP END
2638 BRK/CONT point to LOOP END CF
2639 */
2640 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2641
2642 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2643
2644 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2645 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2646 }
2647 /* TODO add LOOPRET support */
2648 fc_poplevel(ctx);
2649 callstack_decrease_current(ctx, FC_LOOP);
2650 return 0;
2651 }
2652
2653 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2654 {
2655 unsigned int fscp;
2656
2657 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2658 {
2659 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2660 break;
2661 }
2662
2663 if (fscp == 0) {
2664 R600_ERR("Break not inside loop/endloop pair\n");
2665 return -EINVAL;
2666 }
2667
2668 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2669 ctx->bc->cf_last->pop_count = 1;
2670
2671 fc_set_mid(ctx, fscp);
2672
2673 pops(ctx, 1);
2674 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2675 return 0;
2676 }
2677
2678 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2679 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2680 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2681 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2682
2683 /* FIXME:
2684 * For state trackers other than OpenGL, we'll want to use
2685 * _RECIP_IEEE instead.
2686 */
2687 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2688
2689 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2690 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2691 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2692 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2693 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2694 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2695 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2696 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2697 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2698 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2699 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2700 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2701 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2702 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2703 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2704 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2705 /* gap */
2706 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2707 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2708 /* gap */
2709 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2710 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2711 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2712 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2713 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2714 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2715 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2716 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2717 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2718 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2719 /* gap */
2720 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2721 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2722 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2723 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2724 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2725 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2726 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2727 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2728 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2729 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2730 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2731 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2732 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2733 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2734 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2735 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2736 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2737 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2738 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2739 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2740 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2741 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2742 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2743 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2744 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2745 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2746 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2747 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2748 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2749 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2750 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2751 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2752 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2753 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2754 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2755 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2756 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2757 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2758 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2759 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2760 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2761 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2762 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2763 /* gap */
2764 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2765 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2766 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2767 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2768 /* gap */
2769 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2770 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2771 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2772 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2773 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2774 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2775 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2776 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2777 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2778 /* gap */
2779 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2780 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2781 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2782 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2783 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2784 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2785 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2786 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2787 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2788 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2789 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2790 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2791 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2792 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2793 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2794 /* gap */
2795 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2796 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2797 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2798 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2799 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2800 /* gap */
2801 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2802 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2803 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2804 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2805 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2806 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2807 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2808 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2809 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2810 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2811 /* gap */
2812 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2813 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2814 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2815 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2816 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2817 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2818 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2819 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2820 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2821 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2822 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2823 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2824 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2825 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2826 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2827 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2828 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2829 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2830 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2831 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2832 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2833 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2834 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2835 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2836 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2837 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2838 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2839 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2840 };
2841
2842 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
2843 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
2844 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2845 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2846 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2847 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
2848 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2849 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2850 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2851 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2852 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2853 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2854 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2855 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2856 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2857 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2858 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2859 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2860 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2861 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2862 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2863 /* gap */
2864 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2865 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2866 /* gap */
2867 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2868 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2869 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2870 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2871 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2872 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2873 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2874 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2875 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2876 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2877 /* gap */
2878 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2879 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2880 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2881 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2882 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2883 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2884 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2885 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2886 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2887 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2888 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2889 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2891 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2892 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2893 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2894 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2895 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2896 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2897 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2898 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2899 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2900 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2901 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2902 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2903 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2904 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
2908 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2910 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2911 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2912 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2913 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2914 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2915 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2917 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2918 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2919 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2920 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2921 /* gap */
2922 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2924 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2925 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2926 /* gap */
2927 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2932 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2934 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2935 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 /* gap */
2937 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2946 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2949 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2950 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2951 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 /* gap */
2953 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2955 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2957 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2958 /* gap */
2959 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2960 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2961 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2968 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2969 /* gap */
2970 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2993 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 };