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r600g: only set the Z export if shader exports it.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 for (i = 0; i < 10; i++) {
48 spi_vs_out_id[i] = 0;
49 }
50 for (i = 0; i < 32; i++) {
51 tmp = i << ((i & 3) * 8);
52 spi_vs_out_id[i / 4] |= tmp;
53 }
54 for (i = 0; i < 10; i++) {
55 r600_pipe_state_add_reg(rstate,
56 R_028614_SPI_VS_OUT_ID_0 + i * 4,
57 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
58 }
59
60 r600_pipe_state_add_reg(rstate,
61 R_0286C4_SPI_VS_OUT_CONFIG,
62 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
63 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate,
65 R_028868_SQ_PGM_RESOURCES_VS,
66 S_028868_NUM_GPRS(rshader->bc.ngpr) |
67 S_028868_STACK_SIZE(rshader->bc.nstack),
68 0xFFFFFFFF, NULL);
69 r600_pipe_state_add_reg(rstate,
70 R_0288A4_SQ_PGM_RESOURCES_FS,
71 0x00000000, 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS,
77 0x00000000, 0xFFFFFFFF, NULL);
78 r600_pipe_state_add_reg(rstate,
79 R_028858_SQ_PGM_START_VS,
80 0x00000000, 0xFFFFFFFF, shader->bo);
81 r600_pipe_state_add_reg(rstate,
82 R_028894_SQ_PGM_START_FS,
83 0x00000000, 0xFFFFFFFF, shader->bo);
84 }
85
86 int r600_find_vs_semantic_index(struct r600_shader *vs,
87 struct r600_shader *ps, int id)
88 {
89 struct r600_shader_io *input = &ps->input[id];
90
91 for (int i = 0; i < vs->noutput; i++) {
92 if (input->name == vs->output[i].name &&
93 input->sid == vs->output[i].sid) {
94 return i - 1;
95 }
96 }
97 return 0;
98 }
99
100 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
101 {
102 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
103 struct r600_pipe_state *rstate = &shader->rstate;
104 struct r600_shader *rshader = &shader->shader;
105 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
106 boolean have_pos = FALSE, have_face = FALSE;
107
108 /* clear previous register */
109 rstate->nregs = 0;
110
111 for (i = 0; i < rshader->ninput; i++) {
112 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
113 tmp |= S_028644_SEL_CENTROID(1);
114 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
115 have_pos = TRUE;
116 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
117 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
118 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
119 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
120 }
121 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
122 have_face = TRUE;
123 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
124 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
125 tmp |= S_028644_PT_SPRITE_TEX(1);
126 }
127 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
128 }
129 for (i = 0; i < rshader->noutput; i++) {
130 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
131 r600_pipe_state_add_reg(rstate,
132 R_02880C_DB_SHADER_CONTROL,
133 S_02880C_Z_EXPORT_ENABLE(1),
134 S_02880C_Z_EXPORT_ENABLE(1), NULL);
135 }
136
137 exports_ps = 0;
138 num_cout = 0;
139 for (i = 0; i < rshader->noutput; i++) {
140 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
141 exports_ps |= 1;
142 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
143 num_cout++;
144 }
145 }
146 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
147 if (!exports_ps) {
148 /* always at least export 1 component per pixel */
149 exports_ps = 2;
150 }
151
152 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
153 S_0286CC_PERSP_GRADIENT_ENA(1);
154 spi_input_z = 0;
155 if (have_pos) {
156 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
157 S_0286CC_BARYC_SAMPLE_CNTL(1);
158 spi_input_z |= 1;
159 }
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 0x00000000, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->uses_kill) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate,
181 R_02880C_DB_SHADER_CONTROL,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL);
184 }
185 }
186
187 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
188 {
189 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
190 struct r600_shader *rshader = &shader->shader;
191 void *ptr;
192
193 /* copy new shader */
194 if (shader->bo == NULL) {
195 shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
196 if (shader->bo == NULL) {
197 return -ENOMEM;
198 }
199 ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
200 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
201 radeon_ws_bo_unmap(rctx->radeon, shader->bo);
202 }
203 /* build state */
204 rshader->flat_shade = rctx->flatshade;
205 switch (rshader->processor_type) {
206 case TGSI_PROCESSOR_VERTEX:
207 if (rshader->family >= CHIP_CEDAR) {
208 evergreen_pipe_shader_vs(ctx, shader);
209 } else {
210 r600_pipe_shader_vs(ctx, shader);
211 }
212 break;
213 case TGSI_PROCESSOR_FRAGMENT:
214 if (rshader->family >= CHIP_CEDAR) {
215 evergreen_pipe_shader_ps(ctx, shader);
216 } else {
217 r600_pipe_shader_ps(ctx, shader);
218 }
219 break;
220 default:
221 return -EINVAL;
222 }
223 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
224 return 0;
225 }
226
227 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
228 {
229 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
230 struct r600_shader *shader = &rshader->shader;
231 const struct util_format_description *desc;
232 enum pipe_format resource_format[160];
233 unsigned i, nresources = 0;
234 struct r600_bc *bc = &shader->bc;
235 struct r600_bc_cf *cf;
236 struct r600_bc_vtx *vtx;
237
238 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
239 return 0;
240 if (!memcmp(&rshader->vertex_elements, rctx->vertex_elements, sizeof(struct r600_vertex_element))) {
241 return 0;
242 }
243 rshader->vertex_elements = *rctx->vertex_elements;
244 for (i = 0; i < rctx->vertex_elements->count; i++) {
245 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
246 }
247 radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
248 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
249 switch (cf->inst) {
250 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
251 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
252 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
253 desc = util_format_description(resource_format[vtx->buffer_id]);
254 if (desc == NULL) {
255 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
256 return -EINVAL;
257 }
258 vtx->dst_sel_x = desc->swizzle[0];
259 vtx->dst_sel_y = desc->swizzle[1];
260 vtx->dst_sel_z = desc->swizzle[2];
261 vtx->dst_sel_w = desc->swizzle[3];
262 }
263 break;
264 default:
265 break;
266 }
267 }
268 return r600_bc_build(&shader->bc);
269 }
270
271 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
272 {
273 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
274 int r;
275
276 if (shader == NULL)
277 return -EINVAL;
278 /* there should be enough input */
279 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
280 R600_ERR("%d resources provided, expecting %d\n",
281 rctx->vertex_elements->count, shader->shader.bc.nresource);
282 return -EINVAL;
283 }
284 r = r600_shader_update(ctx, shader);
285 if (r)
286 return r;
287 return r600_pipe_shader(ctx, shader);
288 }
289
290 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
291 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
292 {
293 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
294 int r;
295
296 //fprintf(stderr, "--------------------------------------------------------------\n");
297 //tgsi_dump(tokens, 0);
298 shader->shader.family = r600_get_family(rctx->radeon);
299 r = r600_shader_from_tgsi(tokens, &shader->shader);
300 if (r) {
301 R600_ERR("translation from TGSI failed !\n");
302 return r;
303 }
304 r = r600_bc_build(&shader->shader.bc);
305 if (r) {
306 R600_ERR("building bytecode failed !\n");
307 return r;
308 }
309 //fprintf(stderr, "______________________________________________________________\n");
310 return 0;
311 }
312
313 /*
314 * tgsi -> r600 shader
315 */
316 struct r600_shader_tgsi_instruction;
317
318 struct r600_shader_ctx {
319 struct tgsi_shader_info info;
320 struct tgsi_parse_context parse;
321 const struct tgsi_token *tokens;
322 unsigned type;
323 unsigned file_offset[TGSI_FILE_COUNT];
324 unsigned temp_reg;
325 struct r600_shader_tgsi_instruction *inst_info;
326 struct r600_bc *bc;
327 struct r600_shader *shader;
328 u32 value[4];
329 u32 *literals;
330 u32 nliterals;
331 u32 max_driver_temp_used;
332 };
333
334 struct r600_shader_tgsi_instruction {
335 unsigned tgsi_opcode;
336 unsigned is_op3;
337 unsigned r600_opcode;
338 int (*process)(struct r600_shader_ctx *ctx);
339 };
340
341 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
342 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
343
344 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
345 {
346 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
347 int j;
348
349 if (i->Instruction.NumDstRegs > 1) {
350 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
351 return -EINVAL;
352 }
353 if (i->Instruction.Predicate) {
354 R600_ERR("predicate unsupported\n");
355 return -EINVAL;
356 }
357 #if 0
358 if (i->Instruction.Label) {
359 R600_ERR("label unsupported\n");
360 return -EINVAL;
361 }
362 #endif
363 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
364 if (i->Src[j].Register.Dimension ||
365 i->Src[j].Register.Absolute) {
366 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
367 i->Src[j].Register.Dimension,
368 i->Src[j].Register.Absolute);
369 return -EINVAL;
370 }
371 }
372 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
373 if (i->Dst[j].Register.Dimension) {
374 R600_ERR("unsupported dst (dimension)\n");
375 return -EINVAL;
376 }
377 }
378 return 0;
379 }
380
381 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
382 {
383 int i, r;
384 struct r600_bc_alu alu;
385
386 for (i = 0; i < 8; i++) {
387 memset(&alu, 0, sizeof(struct r600_bc_alu));
388
389 if (i < 4)
390 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
391 else
392 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
393
394 if ((i > 1) && (i < 6)) {
395 alu.dst.sel = ctx->shader->input[gpr].gpr;
396 alu.dst.write = 1;
397 }
398
399 alu.dst.chan = i % 4;
400 alu.src[0].chan = (1 - (i % 2));
401 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
402
403 alu.bank_swizzle_force = SQ_ALU_VEC_210;
404 if ((i % 4) == 3)
405 alu.last = 1;
406 r = r600_bc_add_alu(ctx->bc, &alu);
407 if (r)
408 return r;
409 }
410 return 0;
411 }
412
413
414 static int tgsi_declaration(struct r600_shader_ctx *ctx)
415 {
416 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
417 struct r600_bc_vtx vtx;
418 unsigned i;
419 int r;
420
421 switch (d->Declaration.File) {
422 case TGSI_FILE_INPUT:
423 i = ctx->shader->ninput++;
424 ctx->shader->input[i].name = d->Semantic.Name;
425 ctx->shader->input[i].sid = d->Semantic.Index;
426 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
427 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
428 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
429 /* turn input into fetch */
430 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
431 vtx.inst = 0;
432 vtx.fetch_type = 0;
433 vtx.buffer_id = i;
434 /* register containing the index into the buffer */
435 vtx.src_gpr = 0;
436 vtx.src_sel_x = 0;
437 vtx.mega_fetch_count = 0x1F;
438 vtx.dst_gpr = ctx->shader->input[i].gpr;
439 vtx.dst_sel_x = 0;
440 vtx.dst_sel_y = 1;
441 vtx.dst_sel_z = 2;
442 vtx.dst_sel_w = 3;
443 vtx.use_const_fields = 1;
444 r = r600_bc_add_vtx(ctx->bc, &vtx);
445 if (r)
446 return r;
447 }
448 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
449 /* turn input into interpolate on EG */
450 evergreen_interp_alu(ctx, i);
451 }
452 break;
453 case TGSI_FILE_OUTPUT:
454 i = ctx->shader->noutput++;
455 ctx->shader->output[i].name = d->Semantic.Name;
456 ctx->shader->output[i].sid = d->Semantic.Index;
457 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
458 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
459 break;
460 case TGSI_FILE_CONSTANT:
461 case TGSI_FILE_TEMPORARY:
462 case TGSI_FILE_SAMPLER:
463 case TGSI_FILE_ADDRESS:
464 break;
465 default:
466 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
467 return -EINVAL;
468 }
469 return 0;
470 }
471
472 static int r600_get_temp(struct r600_shader_ctx *ctx)
473 {
474 return ctx->temp_reg + ctx->max_driver_temp_used++;
475 }
476
477 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
478 {
479 struct tgsi_full_immediate *immediate;
480 struct r600_shader_ctx ctx;
481 struct r600_bc_output output[32];
482 unsigned output_done, noutput;
483 unsigned opcode;
484 int i, r = 0, pos0;
485
486 ctx.bc = &shader->bc;
487 ctx.shader = shader;
488 r = r600_bc_init(ctx.bc, shader->family);
489 if (r)
490 return r;
491 ctx.bc->use_mem_constant = shader->use_mem_constant;
492 ctx.tokens = tokens;
493 tgsi_scan_shader(tokens, &ctx.info);
494 tgsi_parse_init(&ctx.parse, tokens);
495 ctx.type = ctx.parse.FullHeader.Processor.Processor;
496 shader->processor_type = ctx.type;
497
498 /* register allocations */
499 /* Values [0,127] correspond to GPR[0..127].
500 * Values [128,159] correspond to constant buffer bank 0
501 * Values [160,191] correspond to constant buffer bank 1
502 * Values [256,511] correspond to cfile constants c[0..255].
503 * Other special values are shown in the list below.
504 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
505 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
506 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
507 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
508 * 248 SQ_ALU_SRC_0: special constant 0.0.
509 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
510 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
511 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
512 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
513 * 253 SQ_ALU_SRC_LITERAL: literal constant.
514 * 254 SQ_ALU_SRC_PV: previous vector result.
515 * 255 SQ_ALU_SRC_PS: previous scalar result.
516 */
517 for (i = 0; i < TGSI_FILE_COUNT; i++) {
518 ctx.file_offset[i] = 0;
519 }
520 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
521 ctx.file_offset[TGSI_FILE_INPUT] = 1;
522 }
523 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
524 ctx.info.file_count[TGSI_FILE_INPUT];
525 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
526 ctx.info.file_count[TGSI_FILE_OUTPUT];
527 if (ctx.shader->use_mem_constant)
528 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
529 else
530 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
531
532 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
533 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
534 ctx.info.file_count[TGSI_FILE_TEMPORARY];
535
536 ctx.nliterals = 0;
537 ctx.literals = NULL;
538
539 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
540 tgsi_parse_token(&ctx.parse);
541 switch (ctx.parse.FullToken.Token.Type) {
542 case TGSI_TOKEN_TYPE_IMMEDIATE:
543 immediate = &ctx.parse.FullToken.FullImmediate;
544 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
545 if(ctx.literals == NULL) {
546 r = -ENOMEM;
547 goto out_err;
548 }
549 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
550 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
551 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
552 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
553 ctx.nliterals++;
554 break;
555 case TGSI_TOKEN_TYPE_DECLARATION:
556 r = tgsi_declaration(&ctx);
557 if (r)
558 goto out_err;
559 break;
560 case TGSI_TOKEN_TYPE_INSTRUCTION:
561 r = tgsi_is_supported(&ctx);
562 if (r)
563 goto out_err;
564 ctx.max_driver_temp_used = 0;
565 /* reserve first tmp for everyone */
566 r600_get_temp(&ctx);
567 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
568 if (ctx.bc->chiprev == 2)
569 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
570 else
571 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
572 r = ctx.inst_info->process(&ctx);
573 if (r)
574 goto out_err;
575 r = r600_bc_add_literal(ctx.bc, ctx.value);
576 if (r)
577 goto out_err;
578 break;
579 default:
580 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
581 r = -EINVAL;
582 goto out_err;
583 }
584 }
585 /* export output */
586 noutput = shader->noutput;
587 for (i = 0, pos0 = 0; i < noutput; i++) {
588 memset(&output[i], 0, sizeof(struct r600_bc_output));
589 output[i].gpr = shader->output[i].gpr;
590 output[i].elem_size = 3;
591 output[i].swizzle_x = 0;
592 output[i].swizzle_y = 1;
593 output[i].swizzle_z = 2;
594 output[i].swizzle_w = 3;
595 output[i].barrier = 1;
596 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
597 output[i].array_base = i - pos0;
598 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
599 switch (ctx.type) {
600 case TGSI_PROCESSOR_VERTEX:
601 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
602 output[i].array_base = 60;
603 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
604 /* position doesn't count in array_base */
605 pos0++;
606 }
607 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
608 output[i].array_base = 61;
609 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
610 /* position doesn't count in array_base */
611 pos0++;
612 }
613 break;
614 case TGSI_PROCESSOR_FRAGMENT:
615 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
616 output[i].array_base = shader->output[i].sid;
617 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
618 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
619 output[i].array_base = 61;
620 output[i].swizzle_x = 2;
621 output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
622 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
623 } else {
624 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
625 r = -EINVAL;
626 goto out_err;
627 }
628 break;
629 default:
630 R600_ERR("unsupported processor type %d\n", ctx.type);
631 r = -EINVAL;
632 goto out_err;
633 }
634 }
635 /* add fake param output for vertex shader if no param is exported */
636 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
637 for (i = 0, pos0 = 0; i < noutput; i++) {
638 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
639 pos0 = 1;
640 break;
641 }
642 }
643 if (!pos0) {
644 memset(&output[i], 0, sizeof(struct r600_bc_output));
645 output[i].gpr = 0;
646 output[i].elem_size = 3;
647 output[i].swizzle_x = 0;
648 output[i].swizzle_y = 1;
649 output[i].swizzle_z = 2;
650 output[i].swizzle_w = 3;
651 output[i].barrier = 1;
652 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
653 output[i].array_base = 0;
654 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
655 noutput++;
656 }
657 }
658 /* add fake pixel export */
659 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
660 memset(&output[0], 0, sizeof(struct r600_bc_output));
661 output[0].gpr = 0;
662 output[0].elem_size = 3;
663 output[0].swizzle_x = 7;
664 output[0].swizzle_y = 7;
665 output[0].swizzle_z = 7;
666 output[0].swizzle_w = 7;
667 output[0].barrier = 1;
668 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
669 output[0].array_base = 0;
670 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
671 noutput++;
672 }
673 /* set export done on last export of each type */
674 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
675 if (i == (noutput - 1)) {
676 output[i].end_of_program = 1;
677 }
678 if (!(output_done & (1 << output[i].type))) {
679 output_done |= (1 << output[i].type);
680 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
681 }
682 }
683 /* add output to bytecode */
684 for (i = 0; i < noutput; i++) {
685 r = r600_bc_add_output(ctx.bc, &output[i]);
686 if (r)
687 goto out_err;
688 }
689 free(ctx.literals);
690 tgsi_parse_free(&ctx.parse);
691 return 0;
692 out_err:
693 free(ctx.literals);
694 tgsi_parse_free(&ctx.parse);
695 return r;
696 }
697
698 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
699 {
700 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
701 return -EINVAL;
702 }
703
704 static int tgsi_end(struct r600_shader_ctx *ctx)
705 {
706 return 0;
707 }
708
709 static int tgsi_src(struct r600_shader_ctx *ctx,
710 const struct tgsi_full_src_register *tgsi_src,
711 struct r600_bc_alu_src *r600_src)
712 {
713 int index;
714 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
715 r600_src->sel = tgsi_src->Register.Index;
716 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
717 r600_src->sel = 0;
718 index = tgsi_src->Register.Index;
719 ctx->value[0] = ctx->literals[index * 4 + 0];
720 ctx->value[1] = ctx->literals[index * 4 + 1];
721 ctx->value[2] = ctx->literals[index * 4 + 2];
722 ctx->value[3] = ctx->literals[index * 4 + 3];
723 }
724 if (tgsi_src->Register.Indirect)
725 r600_src->rel = V_SQ_REL_RELATIVE;
726 r600_src->neg = tgsi_src->Register.Negate;
727 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
728 return 0;
729 }
730
731 static int tgsi_dst(struct r600_shader_ctx *ctx,
732 const struct tgsi_full_dst_register *tgsi_dst,
733 unsigned swizzle,
734 struct r600_bc_alu_dst *r600_dst)
735 {
736 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
737
738 r600_dst->sel = tgsi_dst->Register.Index;
739 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
740 r600_dst->chan = swizzle;
741 r600_dst->write = 1;
742 if (tgsi_dst->Register.Indirect)
743 r600_dst->rel = V_SQ_REL_RELATIVE;
744 if (inst->Instruction.Saturate) {
745 r600_dst->clamp = 1;
746 }
747 return 0;
748 }
749
750 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
751 {
752 switch (swizzle) {
753 case 0:
754 return tgsi_src->Register.SwizzleX;
755 case 1:
756 return tgsi_src->Register.SwizzleY;
757 case 2:
758 return tgsi_src->Register.SwizzleZ;
759 case 3:
760 return tgsi_src->Register.SwizzleW;
761 default:
762 return 0;
763 }
764 }
765
766 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
767 {
768 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
769 struct r600_bc_alu alu;
770 int i, j, k, nconst, r;
771
772 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
773 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
774 nconst++;
775 }
776 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
777 if (r) {
778 return r;
779 }
780 }
781 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
782 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
783 int treg = r600_get_temp(ctx);
784 for (k = 0; k < 4; k++) {
785 memset(&alu, 0, sizeof(struct r600_bc_alu));
786 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
787 alu.src[0].sel = r600_src[i].sel;
788 alu.src[0].chan = k;
789 alu.dst.sel = treg;
790 alu.dst.chan = k;
791 alu.dst.write = 1;
792 if (k == 3)
793 alu.last = 1;
794 r = r600_bc_add_alu(ctx->bc, &alu);
795 if (r)
796 return r;
797 }
798 r600_src[i].sel = treg;
799 j--;
800 }
801 }
802 return 0;
803 }
804
805 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
806 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
807 {
808 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
809 struct r600_bc_alu alu;
810 int i, j, k, nliteral, r, index;
811
812 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
813 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
814 nliteral++;
815 }
816 }
817 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
818 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
819 int treg = r600_get_temp(ctx);
820 for (k = 0; k < 4; k++) {
821 memset(&alu, 0, sizeof(struct r600_bc_alu));
822 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
823 alu.src[0].sel = r600_src[i].sel;
824 alu.src[0].chan = k;
825 alu.dst.sel = treg;
826 alu.dst.chan = k;
827 alu.dst.write = 1;
828 if (k == 3)
829 alu.last = 1;
830 r = r600_bc_add_alu(ctx->bc, &alu);
831 if (r)
832 return r;
833 }
834 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
835 if (r)
836 return r;
837 r600_src[i].sel = treg;
838 j--;
839 }
840 }
841 return 0;
842 }
843
844 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
845 {
846 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
847 struct r600_bc_alu_src r600_src[3];
848 struct r600_bc_alu alu;
849 int i, j, r;
850 int lasti = 0;
851
852 for (i = 0; i < 4; i++) {
853 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
854 lasti = i;
855 }
856 }
857
858 r = tgsi_split_constant(ctx, r600_src);
859 if (r)
860 return r;
861 r = tgsi_split_literal_constant(ctx, r600_src);
862 if (r)
863 return r;
864 for (i = 0; i < lasti + 1; i++) {
865 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
866 continue;
867
868 memset(&alu, 0, sizeof(struct r600_bc_alu));
869 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
870 if (r)
871 return r;
872
873 alu.inst = ctx->inst_info->r600_opcode;
874 if (!swap) {
875 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
876 alu.src[j] = r600_src[j];
877 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
878 }
879 } else {
880 alu.src[0] = r600_src[1];
881 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
882
883 alu.src[1] = r600_src[0];
884 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
885 }
886 /* handle some special cases */
887 switch (ctx->inst_info->tgsi_opcode) {
888 case TGSI_OPCODE_SUB:
889 alu.src[1].neg = 1;
890 break;
891 case TGSI_OPCODE_ABS:
892 alu.src[0].abs = 1;
893 break;
894 default:
895 break;
896 }
897 if (i == lasti) {
898 alu.last = 1;
899 }
900 r = r600_bc_add_alu(ctx->bc, &alu);
901 if (r)
902 return r;
903 }
904 return 0;
905 }
906
907 static int tgsi_op2(struct r600_shader_ctx *ctx)
908 {
909 return tgsi_op2_s(ctx, 0);
910 }
911
912 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
913 {
914 return tgsi_op2_s(ctx, 1);
915 }
916
917 /*
918 * r600 - trunc to -PI..PI range
919 * r700 - normalize by dividing by 2PI
920 * see fdo bug 27901
921 */
922 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
923 struct r600_bc_alu_src r600_src[3])
924 {
925 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
926 int r;
927 uint32_t lit_vals[4];
928 struct r600_bc_alu alu;
929
930 memset(lit_vals, 0, 4*4);
931 r = tgsi_split_constant(ctx, r600_src);
932 if (r)
933 return r;
934 r = tgsi_split_literal_constant(ctx, r600_src);
935 if (r)
936 return r;
937
938 r = tgsi_split_literal_constant(ctx, r600_src);
939 if (r)
940 return r;
941
942 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
943 lit_vals[1] = fui(0.5f);
944
945 memset(&alu, 0, sizeof(struct r600_bc_alu));
946 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
947 alu.is_op3 = 1;
948
949 alu.dst.chan = 0;
950 alu.dst.sel = ctx->temp_reg;
951 alu.dst.write = 1;
952
953 alu.src[0] = r600_src[0];
954 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
955
956 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
957 alu.src[1].chan = 0;
958 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
959 alu.src[2].chan = 1;
960 alu.last = 1;
961 r = r600_bc_add_alu(ctx->bc, &alu);
962 if (r)
963 return r;
964 r = r600_bc_add_literal(ctx->bc, lit_vals);
965 if (r)
966 return r;
967
968 memset(&alu, 0, sizeof(struct r600_bc_alu));
969 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
970
971 alu.dst.chan = 0;
972 alu.dst.sel = ctx->temp_reg;
973 alu.dst.write = 1;
974
975 alu.src[0].sel = ctx->temp_reg;
976 alu.src[0].chan = 0;
977 alu.last = 1;
978 r = r600_bc_add_alu(ctx->bc, &alu);
979 if (r)
980 return r;
981
982 if (ctx->bc->chiprev == 0) {
983 lit_vals[0] = fui(3.1415926535897f * 2.0f);
984 lit_vals[1] = fui(-3.1415926535897f);
985 } else {
986 lit_vals[0] = fui(1.0f);
987 lit_vals[1] = fui(-0.5f);
988 }
989
990 memset(&alu, 0, sizeof(struct r600_bc_alu));
991 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
992 alu.is_op3 = 1;
993
994 alu.dst.chan = 0;
995 alu.dst.sel = ctx->temp_reg;
996 alu.dst.write = 1;
997
998 alu.src[0].sel = ctx->temp_reg;
999 alu.src[0].chan = 0;
1000
1001 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1002 alu.src[1].chan = 0;
1003 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1004 alu.src[2].chan = 1;
1005 alu.last = 1;
1006 r = r600_bc_add_alu(ctx->bc, &alu);
1007 if (r)
1008 return r;
1009 r = r600_bc_add_literal(ctx->bc, lit_vals);
1010 if (r)
1011 return r;
1012 return 0;
1013 }
1014
1015 static int tgsi_trig(struct r600_shader_ctx *ctx)
1016 {
1017 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1018 struct r600_bc_alu_src r600_src[3];
1019 struct r600_bc_alu alu;
1020 int i, r;
1021 int lasti = 0;
1022
1023 r = tgsi_setup_trig(ctx, r600_src);
1024 if (r)
1025 return r;
1026
1027 memset(&alu, 0, sizeof(struct r600_bc_alu));
1028 alu.inst = ctx->inst_info->r600_opcode;
1029 alu.dst.chan = 0;
1030 alu.dst.sel = ctx->temp_reg;
1031 alu.dst.write = 1;
1032
1033 alu.src[0].sel = ctx->temp_reg;
1034 alu.src[0].chan = 0;
1035 alu.last = 1;
1036 r = r600_bc_add_alu(ctx->bc, &alu);
1037 if (r)
1038 return r;
1039
1040 /* replicate result */
1041 for (i = 0; i < 4; i++) {
1042 if (inst->Dst[0].Register.WriteMask & (1 << i))
1043 lasti = i;
1044 }
1045 for (i = 0; i < lasti + 1; i++) {
1046 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1047 continue;
1048
1049 memset(&alu, 0, sizeof(struct r600_bc_alu));
1050 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1051
1052 alu.src[0].sel = ctx->temp_reg;
1053 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1054 if (r)
1055 return r;
1056 if (i == lasti)
1057 alu.last = 1;
1058 r = r600_bc_add_alu(ctx->bc, &alu);
1059 if (r)
1060 return r;
1061 }
1062 return 0;
1063 }
1064
1065 static int tgsi_scs(struct r600_shader_ctx *ctx)
1066 {
1067 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1068 struct r600_bc_alu_src r600_src[3];
1069 struct r600_bc_alu alu;
1070 int r;
1071
1072 /* We'll only need the trig stuff if we are going to write to the
1073 * X or Y components of the destination vector.
1074 */
1075 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1076 r = tgsi_setup_trig(ctx, r600_src);
1077 if (r)
1078 return r;
1079 }
1080
1081 /* dst.x = COS */
1082 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1083 memset(&alu, 0, sizeof(struct r600_bc_alu));
1084 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1085 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1086 if (r)
1087 return r;
1088
1089 alu.src[0].sel = ctx->temp_reg;
1090 alu.src[0].chan = 0;
1091 alu.last = 1;
1092 r = r600_bc_add_alu(ctx->bc, &alu);
1093 if (r)
1094 return r;
1095 }
1096
1097 /* dst.y = SIN */
1098 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1099 memset(&alu, 0, sizeof(struct r600_bc_alu));
1100 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1101 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1102 if (r)
1103 return r;
1104
1105 alu.src[0].sel = ctx->temp_reg;
1106 alu.src[0].chan = 0;
1107 alu.last = 1;
1108 r = r600_bc_add_alu(ctx->bc, &alu);
1109 if (r)
1110 return r;
1111 }
1112
1113 /* dst.z = 0.0; */
1114 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1115 memset(&alu, 0, sizeof(struct r600_bc_alu));
1116
1117 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1118
1119 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1120 if (r)
1121 return r;
1122
1123 alu.src[0].sel = V_SQ_ALU_SRC_0;
1124 alu.src[0].chan = 0;
1125
1126 alu.last = 1;
1127
1128 r = r600_bc_add_alu(ctx->bc, &alu);
1129 if (r)
1130 return r;
1131
1132 r = r600_bc_add_literal(ctx->bc, ctx->value);
1133 if (r)
1134 return r;
1135 }
1136
1137 /* dst.w = 1.0; */
1138 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1139 memset(&alu, 0, sizeof(struct r600_bc_alu));
1140
1141 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1142
1143 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1144 if (r)
1145 return r;
1146
1147 alu.src[0].sel = V_SQ_ALU_SRC_1;
1148 alu.src[0].chan = 0;
1149
1150 alu.last = 1;
1151
1152 r = r600_bc_add_alu(ctx->bc, &alu);
1153 if (r)
1154 return r;
1155
1156 r = r600_bc_add_literal(ctx->bc, ctx->value);
1157 if (r)
1158 return r;
1159 }
1160
1161 return 0;
1162 }
1163
1164 static int tgsi_kill(struct r600_shader_ctx *ctx)
1165 {
1166 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1167 struct r600_bc_alu alu;
1168 int i, r;
1169
1170 for (i = 0; i < 4; i++) {
1171 memset(&alu, 0, sizeof(struct r600_bc_alu));
1172 alu.inst = ctx->inst_info->r600_opcode;
1173
1174 alu.dst.chan = i;
1175
1176 alu.src[0].sel = V_SQ_ALU_SRC_0;
1177
1178 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1179 alu.src[1].sel = V_SQ_ALU_SRC_1;
1180 alu.src[1].neg = 1;
1181 } else {
1182 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1183 if (r)
1184 return r;
1185 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1186 }
1187 if (i == 3) {
1188 alu.last = 1;
1189 }
1190 r = r600_bc_add_alu(ctx->bc, &alu);
1191 if (r)
1192 return r;
1193 }
1194 r = r600_bc_add_literal(ctx->bc, ctx->value);
1195 if (r)
1196 return r;
1197
1198 /* kill must be last in ALU */
1199 ctx->bc->force_add_cf = 1;
1200 ctx->shader->uses_kill = TRUE;
1201 return 0;
1202 }
1203
1204 static int tgsi_lit(struct r600_shader_ctx *ctx)
1205 {
1206 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1207 struct r600_bc_alu alu;
1208 struct r600_bc_alu_src r600_src[3];
1209 int r;
1210
1211 r = tgsi_split_constant(ctx, r600_src);
1212 if (r)
1213 return r;
1214 r = tgsi_split_literal_constant(ctx, r600_src);
1215 if (r)
1216 return r;
1217
1218 /* dst.x, <- 1.0 */
1219 memset(&alu, 0, sizeof(struct r600_bc_alu));
1220 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1221 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1222 alu.src[0].chan = 0;
1223 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1224 if (r)
1225 return r;
1226 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1227 r = r600_bc_add_alu(ctx->bc, &alu);
1228 if (r)
1229 return r;
1230
1231 /* dst.y = max(src.x, 0.0) */
1232 memset(&alu, 0, sizeof(struct r600_bc_alu));
1233 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1234 alu.src[0] = r600_src[0];
1235 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1236 alu.src[1].chan = 0;
1237 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1238 if (r)
1239 return r;
1240 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1241 r = r600_bc_add_alu(ctx->bc, &alu);
1242 if (r)
1243 return r;
1244
1245 /* dst.w, <- 1.0 */
1246 memset(&alu, 0, sizeof(struct r600_bc_alu));
1247 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1248 alu.src[0].sel = V_SQ_ALU_SRC_1;
1249 alu.src[0].chan = 0;
1250 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1251 if (r)
1252 return r;
1253 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1254 alu.last = 1;
1255 r = r600_bc_add_alu(ctx->bc, &alu);
1256 if (r)
1257 return r;
1258
1259 r = r600_bc_add_literal(ctx->bc, ctx->value);
1260 if (r)
1261 return r;
1262
1263 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1264 {
1265 int chan;
1266 int sel;
1267
1268 /* dst.z = log(src.y) */
1269 memset(&alu, 0, sizeof(struct r600_bc_alu));
1270 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1271 alu.src[0] = r600_src[0];
1272 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1273 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1274 if (r)
1275 return r;
1276 alu.last = 1;
1277 r = r600_bc_add_alu(ctx->bc, &alu);
1278 if (r)
1279 return r;
1280
1281 r = r600_bc_add_literal(ctx->bc, ctx->value);
1282 if (r)
1283 return r;
1284
1285 chan = alu.dst.chan;
1286 sel = alu.dst.sel;
1287
1288 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1289 memset(&alu, 0, sizeof(struct r600_bc_alu));
1290 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1291 alu.src[0] = r600_src[0];
1292 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1293 alu.src[1].sel = sel;
1294 alu.src[1].chan = chan;
1295
1296 alu.src[2] = r600_src[0];
1297 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1298 alu.dst.sel = ctx->temp_reg;
1299 alu.dst.chan = 0;
1300 alu.dst.write = 1;
1301 alu.is_op3 = 1;
1302 alu.last = 1;
1303 r = r600_bc_add_alu(ctx->bc, &alu);
1304 if (r)
1305 return r;
1306
1307 r = r600_bc_add_literal(ctx->bc, ctx->value);
1308 if (r)
1309 return r;
1310 /* dst.z = exp(tmp.x) */
1311 memset(&alu, 0, sizeof(struct r600_bc_alu));
1312 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1313 alu.src[0].sel = ctx->temp_reg;
1314 alu.src[0].chan = 0;
1315 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1316 if (r)
1317 return r;
1318 alu.last = 1;
1319 r = r600_bc_add_alu(ctx->bc, &alu);
1320 if (r)
1321 return r;
1322 }
1323 return 0;
1324 }
1325
1326 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1327 {
1328 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1329 struct r600_bc_alu alu;
1330 int i, r;
1331
1332 memset(&alu, 0, sizeof(struct r600_bc_alu));
1333
1334 /* FIXME:
1335 * For state trackers other than OpenGL, we'll want to use
1336 * _RECIPSQRT_IEEE instead.
1337 */
1338 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1339
1340 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1341 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1342 if (r)
1343 return r;
1344 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1345 alu.src[i].abs = 1;
1346 }
1347 alu.dst.sel = ctx->temp_reg;
1348 alu.dst.write = 1;
1349 alu.last = 1;
1350 r = r600_bc_add_alu(ctx->bc, &alu);
1351 if (r)
1352 return r;
1353 r = r600_bc_add_literal(ctx->bc, ctx->value);
1354 if (r)
1355 return r;
1356 /* replicate result */
1357 return tgsi_helper_tempx_replicate(ctx);
1358 }
1359
1360 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1361 {
1362 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1363 struct r600_bc_alu alu;
1364 int i, r;
1365
1366 for (i = 0; i < 4; i++) {
1367 memset(&alu, 0, sizeof(struct r600_bc_alu));
1368 alu.src[0].sel = ctx->temp_reg;
1369 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1370 alu.dst.chan = i;
1371 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1372 if (r)
1373 return r;
1374 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1375 if (i == 3)
1376 alu.last = 1;
1377 r = r600_bc_add_alu(ctx->bc, &alu);
1378 if (r)
1379 return r;
1380 }
1381 return 0;
1382 }
1383
1384 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1385 {
1386 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1387 struct r600_bc_alu alu;
1388 int i, r;
1389
1390 memset(&alu, 0, sizeof(struct r600_bc_alu));
1391 alu.inst = ctx->inst_info->r600_opcode;
1392 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1393 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1394 if (r)
1395 return r;
1396 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1397 }
1398 alu.dst.sel = ctx->temp_reg;
1399 alu.dst.write = 1;
1400 alu.last = 1;
1401 r = r600_bc_add_alu(ctx->bc, &alu);
1402 if (r)
1403 return r;
1404 r = r600_bc_add_literal(ctx->bc, ctx->value);
1405 if (r)
1406 return r;
1407 /* replicate result */
1408 return tgsi_helper_tempx_replicate(ctx);
1409 }
1410
1411 static int tgsi_pow(struct r600_shader_ctx *ctx)
1412 {
1413 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1414 struct r600_bc_alu alu;
1415 int r;
1416
1417 /* LOG2(a) */
1418 memset(&alu, 0, sizeof(struct r600_bc_alu));
1419 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1420 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1421 if (r)
1422 return r;
1423 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1424 alu.dst.sel = ctx->temp_reg;
1425 alu.dst.write = 1;
1426 alu.last = 1;
1427 r = r600_bc_add_alu(ctx->bc, &alu);
1428 if (r)
1429 return r;
1430 r = r600_bc_add_literal(ctx->bc,ctx->value);
1431 if (r)
1432 return r;
1433 /* b * LOG2(a) */
1434 memset(&alu, 0, sizeof(struct r600_bc_alu));
1435 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1436 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1437 if (r)
1438 return r;
1439 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1440 alu.src[1].sel = ctx->temp_reg;
1441 alu.dst.sel = ctx->temp_reg;
1442 alu.dst.write = 1;
1443 alu.last = 1;
1444 r = r600_bc_add_alu(ctx->bc, &alu);
1445 if (r)
1446 return r;
1447 r = r600_bc_add_literal(ctx->bc,ctx->value);
1448 if (r)
1449 return r;
1450 /* POW(a,b) = EXP2(b * LOG2(a))*/
1451 memset(&alu, 0, sizeof(struct r600_bc_alu));
1452 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1453 alu.src[0].sel = ctx->temp_reg;
1454 alu.dst.sel = ctx->temp_reg;
1455 alu.dst.write = 1;
1456 alu.last = 1;
1457 r = r600_bc_add_alu(ctx->bc, &alu);
1458 if (r)
1459 return r;
1460 r = r600_bc_add_literal(ctx->bc,ctx->value);
1461 if (r)
1462 return r;
1463 return tgsi_helper_tempx_replicate(ctx);
1464 }
1465
1466 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1467 {
1468 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1469 struct r600_bc_alu alu;
1470 struct r600_bc_alu_src r600_src[3];
1471 int i, r;
1472
1473 r = tgsi_split_constant(ctx, r600_src);
1474 if (r)
1475 return r;
1476 r = tgsi_split_literal_constant(ctx, r600_src);
1477 if (r)
1478 return r;
1479
1480 /* tmp = (src > 0 ? 1 : src) */
1481 for (i = 0; i < 4; i++) {
1482 memset(&alu, 0, sizeof(struct r600_bc_alu));
1483 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1484 alu.is_op3 = 1;
1485
1486 alu.dst.sel = ctx->temp_reg;
1487 alu.dst.chan = i;
1488
1489 alu.src[0] = r600_src[0];
1490 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1491
1492 alu.src[1].sel = V_SQ_ALU_SRC_1;
1493
1494 alu.src[2] = r600_src[0];
1495 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1496 if (i == 3)
1497 alu.last = 1;
1498 r = r600_bc_add_alu(ctx->bc, &alu);
1499 if (r)
1500 return r;
1501 }
1502 r = r600_bc_add_literal(ctx->bc, ctx->value);
1503 if (r)
1504 return r;
1505
1506 /* dst = (-tmp > 0 ? -1 : tmp) */
1507 for (i = 0; i < 4; i++) {
1508 memset(&alu, 0, sizeof(struct r600_bc_alu));
1509 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1510 alu.is_op3 = 1;
1511 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1512 if (r)
1513 return r;
1514
1515 alu.src[0].sel = ctx->temp_reg;
1516 alu.src[0].chan = i;
1517 alu.src[0].neg = 1;
1518
1519 alu.src[1].sel = V_SQ_ALU_SRC_1;
1520 alu.src[1].neg = 1;
1521
1522 alu.src[2].sel = ctx->temp_reg;
1523 alu.src[2].chan = i;
1524
1525 if (i == 3)
1526 alu.last = 1;
1527 r = r600_bc_add_alu(ctx->bc, &alu);
1528 if (r)
1529 return r;
1530 }
1531 return 0;
1532 }
1533
1534 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1535 {
1536 struct r600_bc_alu alu;
1537 int i, r;
1538
1539 r = r600_bc_add_literal(ctx->bc, ctx->value);
1540 if (r)
1541 return r;
1542 for (i = 0; i < 4; i++) {
1543 memset(&alu, 0, sizeof(struct r600_bc_alu));
1544 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1545 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1546 alu.dst.chan = i;
1547 } else {
1548 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1549 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1550 if (r)
1551 return r;
1552 alu.src[0].sel = ctx->temp_reg;
1553 alu.src[0].chan = i;
1554 }
1555 if (i == 3) {
1556 alu.last = 1;
1557 }
1558 r = r600_bc_add_alu(ctx->bc, &alu);
1559 if (r)
1560 return r;
1561 }
1562 return 0;
1563 }
1564
1565 static int tgsi_op3(struct r600_shader_ctx *ctx)
1566 {
1567 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1568 struct r600_bc_alu_src r600_src[3];
1569 struct r600_bc_alu alu;
1570 int i, j, r;
1571
1572 r = tgsi_split_constant(ctx, r600_src);
1573 if (r)
1574 return r;
1575 r = tgsi_split_literal_constant(ctx, r600_src);
1576 if (r)
1577 return r;
1578 /* do it in 2 step as op3 doesn't support writemask */
1579 for (i = 0; i < 4; i++) {
1580 memset(&alu, 0, sizeof(struct r600_bc_alu));
1581 alu.inst = ctx->inst_info->r600_opcode;
1582 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1583 alu.src[j] = r600_src[j];
1584 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1585 }
1586 alu.dst.sel = ctx->temp_reg;
1587 alu.dst.chan = i;
1588 alu.dst.write = 1;
1589 alu.is_op3 = 1;
1590 if (i == 3) {
1591 alu.last = 1;
1592 }
1593 r = r600_bc_add_alu(ctx->bc, &alu);
1594 if (r)
1595 return r;
1596 }
1597 return tgsi_helper_copy(ctx, inst);
1598 }
1599
1600 static int tgsi_dp(struct r600_shader_ctx *ctx)
1601 {
1602 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1603 struct r600_bc_alu_src r600_src[3];
1604 struct r600_bc_alu alu;
1605 int i, j, r;
1606
1607 r = tgsi_split_constant(ctx, r600_src);
1608 if (r)
1609 return r;
1610 r = tgsi_split_literal_constant(ctx, r600_src);
1611 if (r)
1612 return r;
1613 for (i = 0; i < 4; i++) {
1614 memset(&alu, 0, sizeof(struct r600_bc_alu));
1615 alu.inst = ctx->inst_info->r600_opcode;
1616 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1617 alu.src[j] = r600_src[j];
1618 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1619 }
1620 alu.dst.sel = ctx->temp_reg;
1621 alu.dst.chan = i;
1622 alu.dst.write = 1;
1623 /* handle some special cases */
1624 switch (ctx->inst_info->tgsi_opcode) {
1625 case TGSI_OPCODE_DP2:
1626 if (i > 1) {
1627 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1628 alu.src[0].chan = alu.src[1].chan = 0;
1629 }
1630 break;
1631 case TGSI_OPCODE_DP3:
1632 if (i > 2) {
1633 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1634 alu.src[0].chan = alu.src[1].chan = 0;
1635 }
1636 break;
1637 case TGSI_OPCODE_DPH:
1638 if (i == 3) {
1639 alu.src[0].sel = V_SQ_ALU_SRC_1;
1640 alu.src[0].chan = 0;
1641 alu.src[0].neg = 0;
1642 }
1643 break;
1644 default:
1645 break;
1646 }
1647 if (i == 3) {
1648 alu.last = 1;
1649 }
1650 r = r600_bc_add_alu(ctx->bc, &alu);
1651 if (r)
1652 return r;
1653 }
1654 return tgsi_helper_copy(ctx, inst);
1655 }
1656
1657 static int tgsi_tex(struct r600_shader_ctx *ctx)
1658 {
1659 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1660 struct r600_bc_tex tex;
1661 struct r600_bc_alu alu;
1662 unsigned src_gpr;
1663 int r, i;
1664 int opcode;
1665 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1666 uint32_t lit_vals[4];
1667
1668 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1669
1670 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1671 /* Add perspective divide */
1672 memset(&alu, 0, sizeof(struct r600_bc_alu));
1673 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1674 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1675 if (r)
1676 return r;
1677
1678 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1679 alu.dst.sel = ctx->temp_reg;
1680 alu.dst.chan = 3;
1681 alu.last = 1;
1682 alu.dst.write = 1;
1683 r = r600_bc_add_alu(ctx->bc, &alu);
1684 if (r)
1685 return r;
1686
1687 for (i = 0; i < 3; i++) {
1688 memset(&alu, 0, sizeof(struct r600_bc_alu));
1689 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1690 alu.src[0].sel = ctx->temp_reg;
1691 alu.src[0].chan = 3;
1692 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1693 if (r)
1694 return r;
1695 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1696 alu.dst.sel = ctx->temp_reg;
1697 alu.dst.chan = i;
1698 alu.dst.write = 1;
1699 r = r600_bc_add_alu(ctx->bc, &alu);
1700 if (r)
1701 return r;
1702 }
1703 memset(&alu, 0, sizeof(struct r600_bc_alu));
1704 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1705 alu.src[0].sel = V_SQ_ALU_SRC_1;
1706 alu.src[0].chan = 0;
1707 alu.dst.sel = ctx->temp_reg;
1708 alu.dst.chan = 3;
1709 alu.last = 1;
1710 alu.dst.write = 1;
1711 r = r600_bc_add_alu(ctx->bc, &alu);
1712 if (r)
1713 return r;
1714 src_not_temp = FALSE;
1715 src_gpr = ctx->temp_reg;
1716 }
1717
1718 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1719 int src_chan, src2_chan;
1720
1721 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1722 for (i = 0; i < 4; i++) {
1723 memset(&alu, 0, sizeof(struct r600_bc_alu));
1724 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1725 switch (i) {
1726 case 0:
1727 src_chan = 2;
1728 src2_chan = 1;
1729 break;
1730 case 1:
1731 src_chan = 2;
1732 src2_chan = 0;
1733 break;
1734 case 2:
1735 src_chan = 0;
1736 src2_chan = 2;
1737 break;
1738 case 3:
1739 src_chan = 1;
1740 src2_chan = 2;
1741 break;
1742 default:
1743 assert(0);
1744 src_chan = 0;
1745 src2_chan = 0;
1746 break;
1747 }
1748 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1749 if (r)
1750 return r;
1751 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1752 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1753 if (r)
1754 return r;
1755 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1756 alu.dst.sel = ctx->temp_reg;
1757 alu.dst.chan = i;
1758 if (i == 3)
1759 alu.last = 1;
1760 alu.dst.write = 1;
1761 r = r600_bc_add_alu(ctx->bc, &alu);
1762 if (r)
1763 return r;
1764 }
1765
1766 /* tmp1.z = RCP_e(|tmp1.z|) */
1767 memset(&alu, 0, sizeof(struct r600_bc_alu));
1768 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1769 alu.src[0].sel = ctx->temp_reg;
1770 alu.src[0].chan = 2;
1771 alu.src[0].abs = 1;
1772 alu.dst.sel = ctx->temp_reg;
1773 alu.dst.chan = 2;
1774 alu.dst.write = 1;
1775 alu.last = 1;
1776 r = r600_bc_add_alu(ctx->bc, &alu);
1777 if (r)
1778 return r;
1779
1780 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1781 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1782 * muladd has no writemask, have to use another temp
1783 */
1784 memset(&alu, 0, sizeof(struct r600_bc_alu));
1785 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1786 alu.is_op3 = 1;
1787
1788 alu.src[0].sel = ctx->temp_reg;
1789 alu.src[0].chan = 0;
1790 alu.src[1].sel = ctx->temp_reg;
1791 alu.src[1].chan = 2;
1792
1793 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1794 alu.src[2].chan = 0;
1795
1796 alu.dst.sel = ctx->temp_reg;
1797 alu.dst.chan = 0;
1798 alu.dst.write = 1;
1799
1800 r = r600_bc_add_alu(ctx->bc, &alu);
1801 if (r)
1802 return r;
1803
1804 memset(&alu, 0, sizeof(struct r600_bc_alu));
1805 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1806 alu.is_op3 = 1;
1807
1808 alu.src[0].sel = ctx->temp_reg;
1809 alu.src[0].chan = 1;
1810 alu.src[1].sel = ctx->temp_reg;
1811 alu.src[1].chan = 2;
1812
1813 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1814 alu.src[2].chan = 0;
1815
1816 alu.dst.sel = ctx->temp_reg;
1817 alu.dst.chan = 1;
1818 alu.dst.write = 1;
1819
1820 alu.last = 1;
1821 r = r600_bc_add_alu(ctx->bc, &alu);
1822 if (r)
1823 return r;
1824
1825 lit_vals[0] = fui(1.5f);
1826
1827 r = r600_bc_add_literal(ctx->bc, lit_vals);
1828 if (r)
1829 return r;
1830 src_not_temp = FALSE;
1831 src_gpr = ctx->temp_reg;
1832 }
1833
1834 if (src_not_temp) {
1835 for (i = 0; i < 4; i++) {
1836 memset(&alu, 0, sizeof(struct r600_bc_alu));
1837 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1838 alu.src[0].sel = src_gpr;
1839 alu.src[0].chan = i;
1840 alu.dst.sel = ctx->temp_reg;
1841 alu.dst.chan = i;
1842 if (i == 3)
1843 alu.last = 1;
1844 alu.dst.write = 1;
1845 r = r600_bc_add_alu(ctx->bc, &alu);
1846 if (r)
1847 return r;
1848 }
1849 src_gpr = ctx->temp_reg;
1850 }
1851
1852 opcode = ctx->inst_info->r600_opcode;
1853 if (opcode == SQ_TEX_INST_SAMPLE &&
1854 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1855 opcode = SQ_TEX_INST_SAMPLE_C;
1856
1857 memset(&tex, 0, sizeof(struct r600_bc_tex));
1858 tex.inst = opcode;
1859 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1860 tex.sampler_id = tex.resource_id;
1861 tex.src_gpr = src_gpr;
1862 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1863 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1864 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1865 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1866 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1867 tex.src_sel_x = 0;
1868 tex.src_sel_y = 1;
1869 tex.src_sel_z = 2;
1870 tex.src_sel_w = 3;
1871
1872 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1873 tex.src_sel_x = 1;
1874 tex.src_sel_y = 0;
1875 tex.src_sel_z = 3;
1876 tex.src_sel_w = 1;
1877 }
1878
1879 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1880 tex.coord_type_x = 1;
1881 tex.coord_type_y = 1;
1882 tex.coord_type_z = 1;
1883 tex.coord_type_w = 1;
1884 }
1885
1886 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1887 tex.src_sel_w = 2;
1888
1889 r = r600_bc_add_tex(ctx->bc, &tex);
1890 if (r)
1891 return r;
1892
1893 /* add shadow ambient support - gallium doesn't do it yet */
1894 return 0;
1895
1896 }
1897
1898 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1899 {
1900 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1901 struct r600_bc_alu_src r600_src[3];
1902 struct r600_bc_alu alu;
1903 unsigned i;
1904 int r;
1905
1906 r = tgsi_split_constant(ctx, r600_src);
1907 if (r)
1908 return r;
1909 r = tgsi_split_literal_constant(ctx, r600_src);
1910 if (r)
1911 return r;
1912 /* 1 - src0 */
1913 for (i = 0; i < 4; i++) {
1914 memset(&alu, 0, sizeof(struct r600_bc_alu));
1915 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1916 alu.src[0].sel = V_SQ_ALU_SRC_1;
1917 alu.src[0].chan = 0;
1918 alu.src[1] = r600_src[0];
1919 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1920 alu.src[1].neg = 1;
1921 alu.dst.sel = ctx->temp_reg;
1922 alu.dst.chan = i;
1923 if (i == 3) {
1924 alu.last = 1;
1925 }
1926 alu.dst.write = 1;
1927 r = r600_bc_add_alu(ctx->bc, &alu);
1928 if (r)
1929 return r;
1930 }
1931 r = r600_bc_add_literal(ctx->bc, ctx->value);
1932 if (r)
1933 return r;
1934
1935 /* (1 - src0) * src2 */
1936 for (i = 0; i < 4; i++) {
1937 memset(&alu, 0, sizeof(struct r600_bc_alu));
1938 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1939 alu.src[0].sel = ctx->temp_reg;
1940 alu.src[0].chan = i;
1941 alu.src[1] = r600_src[2];
1942 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1943 alu.dst.sel = ctx->temp_reg;
1944 alu.dst.chan = i;
1945 if (i == 3) {
1946 alu.last = 1;
1947 }
1948 alu.dst.write = 1;
1949 r = r600_bc_add_alu(ctx->bc, &alu);
1950 if (r)
1951 return r;
1952 }
1953 r = r600_bc_add_literal(ctx->bc, ctx->value);
1954 if (r)
1955 return r;
1956
1957 /* src0 * src1 + (1 - src0) * src2 */
1958 for (i = 0; i < 4; i++) {
1959 memset(&alu, 0, sizeof(struct r600_bc_alu));
1960 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1961 alu.is_op3 = 1;
1962 alu.src[0] = r600_src[0];
1963 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1964 alu.src[1] = r600_src[1];
1965 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1966 alu.src[2].sel = ctx->temp_reg;
1967 alu.src[2].chan = i;
1968 alu.dst.sel = ctx->temp_reg;
1969 alu.dst.chan = i;
1970 if (i == 3) {
1971 alu.last = 1;
1972 }
1973 r = r600_bc_add_alu(ctx->bc, &alu);
1974 if (r)
1975 return r;
1976 }
1977 return tgsi_helper_copy(ctx, inst);
1978 }
1979
1980 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1981 {
1982 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1983 struct r600_bc_alu_src r600_src[3];
1984 struct r600_bc_alu alu;
1985 int use_temp = 0;
1986 int i, r;
1987
1988 r = tgsi_split_constant(ctx, r600_src);
1989 if (r)
1990 return r;
1991 r = tgsi_split_literal_constant(ctx, r600_src);
1992 if (r)
1993 return r;
1994
1995 if (inst->Dst[0].Register.WriteMask != 0xf)
1996 use_temp = 1;
1997
1998 for (i = 0; i < 4; i++) {
1999 memset(&alu, 0, sizeof(struct r600_bc_alu));
2000 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2001 alu.src[0] = r600_src[0];
2002 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2003
2004 alu.src[1] = r600_src[2];
2005 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2006
2007 alu.src[2] = r600_src[1];
2008 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2009
2010 if (use_temp)
2011 alu.dst.sel = ctx->temp_reg;
2012 else {
2013 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2014 if (r)
2015 return r;
2016 }
2017 alu.dst.chan = i;
2018 alu.dst.write = 1;
2019 alu.is_op3 = 1;
2020 if (i == 3)
2021 alu.last = 1;
2022 r = r600_bc_add_alu(ctx->bc, &alu);
2023 if (r)
2024 return r;
2025 }
2026 if (use_temp)
2027 return tgsi_helper_copy(ctx, inst);
2028 return 0;
2029 }
2030
2031 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2032 {
2033 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2034 struct r600_bc_alu_src r600_src[3];
2035 struct r600_bc_alu alu;
2036 uint32_t use_temp = 0;
2037 int i, r;
2038
2039 if (inst->Dst[0].Register.WriteMask != 0xf)
2040 use_temp = 1;
2041
2042 r = tgsi_split_constant(ctx, r600_src);
2043 if (r)
2044 return r;
2045 r = tgsi_split_literal_constant(ctx, r600_src);
2046 if (r)
2047 return r;
2048
2049 for (i = 0; i < 4; i++) {
2050 memset(&alu, 0, sizeof(struct r600_bc_alu));
2051 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2052
2053 alu.src[0] = r600_src[0];
2054 switch (i) {
2055 case 0:
2056 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2057 break;
2058 case 1:
2059 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2060 break;
2061 case 2:
2062 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2063 break;
2064 case 3:
2065 alu.src[0].sel = V_SQ_ALU_SRC_0;
2066 alu.src[0].chan = i;
2067 }
2068
2069 alu.src[1] = r600_src[1];
2070 switch (i) {
2071 case 0:
2072 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2073 break;
2074 case 1:
2075 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2076 break;
2077 case 2:
2078 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2079 break;
2080 case 3:
2081 alu.src[1].sel = V_SQ_ALU_SRC_0;
2082 alu.src[1].chan = i;
2083 }
2084
2085 alu.dst.sel = ctx->temp_reg;
2086 alu.dst.chan = i;
2087 alu.dst.write = 1;
2088
2089 if (i == 3)
2090 alu.last = 1;
2091 r = r600_bc_add_alu(ctx->bc, &alu);
2092 if (r)
2093 return r;
2094
2095 r = r600_bc_add_literal(ctx->bc, ctx->value);
2096 if (r)
2097 return r;
2098 }
2099
2100 for (i = 0; i < 4; i++) {
2101 memset(&alu, 0, sizeof(struct r600_bc_alu));
2102 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2103
2104 alu.src[0] = r600_src[0];
2105 switch (i) {
2106 case 0:
2107 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2108 break;
2109 case 1:
2110 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2111 break;
2112 case 2:
2113 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2114 break;
2115 case 3:
2116 alu.src[0].sel = V_SQ_ALU_SRC_0;
2117 alu.src[0].chan = i;
2118 }
2119
2120 alu.src[1] = r600_src[1];
2121 switch (i) {
2122 case 0:
2123 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2124 break;
2125 case 1:
2126 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2127 break;
2128 case 2:
2129 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2130 break;
2131 case 3:
2132 alu.src[1].sel = V_SQ_ALU_SRC_0;
2133 alu.src[1].chan = i;
2134 }
2135
2136 alu.src[2].sel = ctx->temp_reg;
2137 alu.src[2].neg = 1;
2138 alu.src[2].chan = i;
2139
2140 if (use_temp)
2141 alu.dst.sel = ctx->temp_reg;
2142 else {
2143 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2144 if (r)
2145 return r;
2146 }
2147 alu.dst.chan = i;
2148 alu.dst.write = 1;
2149 alu.is_op3 = 1;
2150 if (i == 3)
2151 alu.last = 1;
2152 r = r600_bc_add_alu(ctx->bc, &alu);
2153 if (r)
2154 return r;
2155
2156 r = r600_bc_add_literal(ctx->bc, ctx->value);
2157 if (r)
2158 return r;
2159 }
2160 if (use_temp)
2161 return tgsi_helper_copy(ctx, inst);
2162 return 0;
2163 }
2164
2165 static int tgsi_exp(struct r600_shader_ctx *ctx)
2166 {
2167 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2168 struct r600_bc_alu_src r600_src[3];
2169 struct r600_bc_alu alu;
2170 int r;
2171
2172 /* result.x = 2^floor(src); */
2173 if (inst->Dst[0].Register.WriteMask & 1) {
2174 memset(&alu, 0, sizeof(struct r600_bc_alu));
2175
2176 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2177 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2178 if (r)
2179 return r;
2180
2181 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2182
2183 alu.dst.sel = ctx->temp_reg;
2184 alu.dst.chan = 0;
2185 alu.dst.write = 1;
2186 alu.last = 1;
2187 r = r600_bc_add_alu(ctx->bc, &alu);
2188 if (r)
2189 return r;
2190
2191 r = r600_bc_add_literal(ctx->bc, ctx->value);
2192 if (r)
2193 return r;
2194
2195 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2196 alu.src[0].sel = ctx->temp_reg;
2197 alu.src[0].chan = 0;
2198
2199 alu.dst.sel = ctx->temp_reg;
2200 alu.dst.chan = 0;
2201 alu.dst.write = 1;
2202 alu.last = 1;
2203 r = r600_bc_add_alu(ctx->bc, &alu);
2204 if (r)
2205 return r;
2206
2207 r = r600_bc_add_literal(ctx->bc, ctx->value);
2208 if (r)
2209 return r;
2210 }
2211
2212 /* result.y = tmp - floor(tmp); */
2213 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2214 memset(&alu, 0, sizeof(struct r600_bc_alu));
2215
2216 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2217 alu.src[0] = r600_src[0];
2218 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2219 if (r)
2220 return r;
2221 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2222
2223 alu.dst.sel = ctx->temp_reg;
2224 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2225 // if (r)
2226 // return r;
2227 alu.dst.write = 1;
2228 alu.dst.chan = 1;
2229
2230 alu.last = 1;
2231
2232 r = r600_bc_add_alu(ctx->bc, &alu);
2233 if (r)
2234 return r;
2235 r = r600_bc_add_literal(ctx->bc, ctx->value);
2236 if (r)
2237 return r;
2238 }
2239
2240 /* result.z = RoughApprox2ToX(tmp);*/
2241 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2242 memset(&alu, 0, sizeof(struct r600_bc_alu));
2243 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2244 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2245 if (r)
2246 return r;
2247 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2248
2249 alu.dst.sel = ctx->temp_reg;
2250 alu.dst.write = 1;
2251 alu.dst.chan = 2;
2252
2253 alu.last = 1;
2254
2255 r = r600_bc_add_alu(ctx->bc, &alu);
2256 if (r)
2257 return r;
2258 r = r600_bc_add_literal(ctx->bc, ctx->value);
2259 if (r)
2260 return r;
2261 }
2262
2263 /* result.w = 1.0;*/
2264 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2265 memset(&alu, 0, sizeof(struct r600_bc_alu));
2266
2267 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2268 alu.src[0].sel = V_SQ_ALU_SRC_1;
2269 alu.src[0].chan = 0;
2270
2271 alu.dst.sel = ctx->temp_reg;
2272 alu.dst.chan = 3;
2273 alu.dst.write = 1;
2274 alu.last = 1;
2275 r = r600_bc_add_alu(ctx->bc, &alu);
2276 if (r)
2277 return r;
2278 r = r600_bc_add_literal(ctx->bc, ctx->value);
2279 if (r)
2280 return r;
2281 }
2282 return tgsi_helper_copy(ctx, inst);
2283 }
2284
2285 static int tgsi_log(struct r600_shader_ctx *ctx)
2286 {
2287 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2288 struct r600_bc_alu alu;
2289 int r;
2290
2291 /* result.x = floor(log2(src)); */
2292 if (inst->Dst[0].Register.WriteMask & 1) {
2293 memset(&alu, 0, sizeof(struct r600_bc_alu));
2294
2295 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2296 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2297 if (r)
2298 return r;
2299
2300 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2301
2302 alu.dst.sel = ctx->temp_reg;
2303 alu.dst.chan = 0;
2304 alu.dst.write = 1;
2305 alu.last = 1;
2306 r = r600_bc_add_alu(ctx->bc, &alu);
2307 if (r)
2308 return r;
2309
2310 r = r600_bc_add_literal(ctx->bc, ctx->value);
2311 if (r)
2312 return r;
2313
2314 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2315 alu.src[0].sel = ctx->temp_reg;
2316 alu.src[0].chan = 0;
2317
2318 alu.dst.sel = ctx->temp_reg;
2319 alu.dst.chan = 0;
2320 alu.dst.write = 1;
2321 alu.last = 1;
2322
2323 r = r600_bc_add_alu(ctx->bc, &alu);
2324 if (r)
2325 return r;
2326
2327 r = r600_bc_add_literal(ctx->bc, ctx->value);
2328 if (r)
2329 return r;
2330 }
2331
2332 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2333 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2334 memset(&alu, 0, sizeof(struct r600_bc_alu));
2335
2336 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2337 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2338 if (r)
2339 return r;
2340
2341 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2342
2343 alu.dst.sel = ctx->temp_reg;
2344 alu.dst.chan = 1;
2345 alu.dst.write = 1;
2346 alu.last = 1;
2347
2348 r = r600_bc_add_alu(ctx->bc, &alu);
2349 if (r)
2350 return r;
2351
2352 r = r600_bc_add_literal(ctx->bc, ctx->value);
2353 if (r)
2354 return r;
2355
2356 memset(&alu, 0, sizeof(struct r600_bc_alu));
2357
2358 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2359 alu.src[0].sel = ctx->temp_reg;
2360 alu.src[0].chan = 1;
2361
2362 alu.dst.sel = ctx->temp_reg;
2363 alu.dst.chan = 1;
2364 alu.dst.write = 1;
2365 alu.last = 1;
2366
2367 r = r600_bc_add_alu(ctx->bc, &alu);
2368 if (r)
2369 return r;
2370
2371 r = r600_bc_add_literal(ctx->bc, ctx->value);
2372 if (r)
2373 return r;
2374
2375 memset(&alu, 0, sizeof(struct r600_bc_alu));
2376
2377 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2378 alu.src[0].sel = ctx->temp_reg;
2379 alu.src[0].chan = 1;
2380
2381 alu.dst.sel = ctx->temp_reg;
2382 alu.dst.chan = 1;
2383 alu.dst.write = 1;
2384 alu.last = 1;
2385
2386 r = r600_bc_add_alu(ctx->bc, &alu);
2387 if (r)
2388 return r;
2389
2390 r = r600_bc_add_literal(ctx->bc, ctx->value);
2391 if (r)
2392 return r;
2393
2394 memset(&alu, 0, sizeof(struct r600_bc_alu));
2395
2396 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2397 alu.src[0].sel = ctx->temp_reg;
2398 alu.src[0].chan = 1;
2399
2400 alu.dst.sel = ctx->temp_reg;
2401 alu.dst.chan = 1;
2402 alu.dst.write = 1;
2403 alu.last = 1;
2404
2405 r = r600_bc_add_alu(ctx->bc, &alu);
2406 if (r)
2407 return r;
2408
2409 r = r600_bc_add_literal(ctx->bc, ctx->value);
2410 if (r)
2411 return r;
2412
2413 memset(&alu, 0, sizeof(struct r600_bc_alu));
2414
2415 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2416
2417 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2418 if (r)
2419 return r;
2420
2421 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2422
2423 alu.src[1].sel = ctx->temp_reg;
2424 alu.src[1].chan = 1;
2425
2426 alu.dst.sel = ctx->temp_reg;
2427 alu.dst.chan = 1;
2428 alu.dst.write = 1;
2429 alu.last = 1;
2430
2431 r = r600_bc_add_alu(ctx->bc, &alu);
2432 if (r)
2433 return r;
2434
2435 r = r600_bc_add_literal(ctx->bc, ctx->value);
2436 if (r)
2437 return r;
2438 }
2439
2440 /* result.z = log2(src);*/
2441 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2442 memset(&alu, 0, sizeof(struct r600_bc_alu));
2443
2444 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2445 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2446 if (r)
2447 return r;
2448
2449 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2450
2451 alu.dst.sel = ctx->temp_reg;
2452 alu.dst.write = 1;
2453 alu.dst.chan = 2;
2454 alu.last = 1;
2455
2456 r = r600_bc_add_alu(ctx->bc, &alu);
2457 if (r)
2458 return r;
2459
2460 r = r600_bc_add_literal(ctx->bc, ctx->value);
2461 if (r)
2462 return r;
2463 }
2464
2465 /* result.w = 1.0; */
2466 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2467 memset(&alu, 0, sizeof(struct r600_bc_alu));
2468
2469 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2470 alu.src[0].sel = V_SQ_ALU_SRC_1;
2471 alu.src[0].chan = 0;
2472
2473 alu.dst.sel = ctx->temp_reg;
2474 alu.dst.chan = 3;
2475 alu.dst.write = 1;
2476 alu.last = 1;
2477
2478 r = r600_bc_add_alu(ctx->bc, &alu);
2479 if (r)
2480 return r;
2481
2482 r = r600_bc_add_literal(ctx->bc, ctx->value);
2483 if (r)
2484 return r;
2485 }
2486
2487 return tgsi_helper_copy(ctx, inst);
2488 }
2489
2490 /* r6/7 only for now */
2491 static int tgsi_arl(struct r600_shader_ctx *ctx)
2492 {
2493 /* TODO from r600c, ar values don't persist between clauses */
2494 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2495 struct r600_bc_alu alu;
2496 int r;
2497 memset(&alu, 0, sizeof(struct r600_bc_alu));
2498
2499 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2500
2501 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2502 if (r)
2503 return r;
2504 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2505
2506 alu.last = 1;
2507
2508 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2509 if (r)
2510 return r;
2511 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2512 return 0;
2513 }
2514
2515 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2516 {
2517 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2518 struct r600_bc_alu alu;
2519 int i, r = 0;
2520
2521 for (i = 0; i < 4; i++) {
2522 memset(&alu, 0, sizeof(struct r600_bc_alu));
2523
2524 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2525 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2526 if (r)
2527 return r;
2528
2529 if (i == 0 || i == 3) {
2530 alu.src[0].sel = V_SQ_ALU_SRC_1;
2531 } else {
2532 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2533 if (r)
2534 return r;
2535 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2536 }
2537
2538 if (i == 0 || i == 2) {
2539 alu.src[1].sel = V_SQ_ALU_SRC_1;
2540 } else {
2541 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2542 if (r)
2543 return r;
2544 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2545 }
2546 if (i == 3)
2547 alu.last = 1;
2548 r = r600_bc_add_alu(ctx->bc, &alu);
2549 if (r)
2550 return r;
2551 }
2552 return 0;
2553 }
2554
2555 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2556 {
2557 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2558 struct r600_bc_alu alu;
2559 int r;
2560
2561 memset(&alu, 0, sizeof(struct r600_bc_alu));
2562 alu.inst = opcode;
2563 alu.predicate = 1;
2564
2565 alu.dst.sel = ctx->temp_reg;
2566 alu.dst.write = 1;
2567 alu.dst.chan = 0;
2568
2569 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2570 if (r)
2571 return r;
2572 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2573 alu.src[1].sel = V_SQ_ALU_SRC_0;
2574 alu.src[1].chan = 0;
2575
2576 alu.last = 1;
2577
2578 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2579 if (r)
2580 return r;
2581 return 0;
2582 }
2583
2584 static int pops(struct r600_shader_ctx *ctx, int pops)
2585 {
2586 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2587 ctx->bc->cf_last->pop_count = pops;
2588 return 0;
2589 }
2590
2591 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2592 {
2593 switch(reason) {
2594 case FC_PUSH_VPM:
2595 ctx->bc->callstack[ctx->bc->call_sp].current--;
2596 break;
2597 case FC_PUSH_WQM:
2598 case FC_LOOP:
2599 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2600 break;
2601 case FC_REP:
2602 /* TOODO : for 16 vp asic should -= 2; */
2603 ctx->bc->callstack[ctx->bc->call_sp].current --;
2604 break;
2605 }
2606 }
2607
2608 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2609 {
2610 if (check_max_only) {
2611 int diff;
2612 switch (reason) {
2613 case FC_PUSH_VPM:
2614 diff = 1;
2615 break;
2616 case FC_PUSH_WQM:
2617 diff = 4;
2618 break;
2619 default:
2620 assert(0);
2621 diff = 0;
2622 }
2623 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2624 ctx->bc->callstack[ctx->bc->call_sp].max) {
2625 ctx->bc->callstack[ctx->bc->call_sp].max =
2626 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2627 }
2628 return;
2629 }
2630 switch (reason) {
2631 case FC_PUSH_VPM:
2632 ctx->bc->callstack[ctx->bc->call_sp].current++;
2633 break;
2634 case FC_PUSH_WQM:
2635 case FC_LOOP:
2636 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2637 break;
2638 case FC_REP:
2639 ctx->bc->callstack[ctx->bc->call_sp].current++;
2640 break;
2641 }
2642
2643 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2644 ctx->bc->callstack[ctx->bc->call_sp].max) {
2645 ctx->bc->callstack[ctx->bc->call_sp].max =
2646 ctx->bc->callstack[ctx->bc->call_sp].current;
2647 }
2648 }
2649
2650 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2651 {
2652 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2653
2654 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2655 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2656 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2657 sp->num_mid++;
2658 }
2659
2660 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2661 {
2662 ctx->bc->fc_sp++;
2663 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2664 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2665 }
2666
2667 static void fc_poplevel(struct r600_shader_ctx *ctx)
2668 {
2669 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2670 if (sp->mid) {
2671 free(sp->mid);
2672 sp->mid = NULL;
2673 }
2674 sp->num_mid = 0;
2675 sp->start = NULL;
2676 sp->type = 0;
2677 ctx->bc->fc_sp--;
2678 }
2679
2680 #if 0
2681 static int emit_return(struct r600_shader_ctx *ctx)
2682 {
2683 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2684 return 0;
2685 }
2686
2687 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2688 {
2689
2690 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2691 ctx->bc->cf_last->pop_count = pops;
2692 /* TODO work out offset */
2693 return 0;
2694 }
2695
2696 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2697 {
2698 return 0;
2699 }
2700
2701 static void emit_testflag(struct r600_shader_ctx *ctx)
2702 {
2703
2704 }
2705
2706 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2707 {
2708 emit_testflag(ctx);
2709 emit_jump_to_offset(ctx, 1, 4);
2710 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2711 pops(ctx, ifidx + 1);
2712 emit_return(ctx);
2713 }
2714
2715 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2716 {
2717 emit_testflag(ctx);
2718
2719 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2720 ctx->bc->cf_last->pop_count = 1;
2721
2722 fc_set_mid(ctx, fc_sp);
2723
2724 pops(ctx, 1);
2725 }
2726 #endif
2727
2728 static int tgsi_if(struct r600_shader_ctx *ctx)
2729 {
2730 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2731
2732 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2733
2734 fc_pushlevel(ctx, FC_IF);
2735
2736 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2737 return 0;
2738 }
2739
2740 static int tgsi_else(struct r600_shader_ctx *ctx)
2741 {
2742 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2743 ctx->bc->cf_last->pop_count = 1;
2744
2745 fc_set_mid(ctx, ctx->bc->fc_sp);
2746 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2747 return 0;
2748 }
2749
2750 static int tgsi_endif(struct r600_shader_ctx *ctx)
2751 {
2752 pops(ctx, 1);
2753 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2754 R600_ERR("if/endif unbalanced in shader\n");
2755 return -1;
2756 }
2757
2758 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2759 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2760 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2761 } else {
2762 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2763 }
2764 fc_poplevel(ctx);
2765
2766 callstack_decrease_current(ctx, FC_PUSH_VPM);
2767 return 0;
2768 }
2769
2770 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2771 {
2772 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2773
2774 fc_pushlevel(ctx, FC_LOOP);
2775
2776 /* check stack depth */
2777 callstack_check_depth(ctx, FC_LOOP, 0);
2778 return 0;
2779 }
2780
2781 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2782 {
2783 int i;
2784
2785 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2786
2787 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2788 R600_ERR("loop/endloop in shader code are not paired.\n");
2789 return -EINVAL;
2790 }
2791
2792 /* fixup loop pointers - from r600isa
2793 LOOP END points to CF after LOOP START,
2794 LOOP START point to CF after LOOP END
2795 BRK/CONT point to LOOP END CF
2796 */
2797 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2798
2799 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2800
2801 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2802 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2803 }
2804 /* TODO add LOOPRET support */
2805 fc_poplevel(ctx);
2806 callstack_decrease_current(ctx, FC_LOOP);
2807 return 0;
2808 }
2809
2810 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2811 {
2812 unsigned int fscp;
2813
2814 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2815 {
2816 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2817 break;
2818 }
2819
2820 if (fscp == 0) {
2821 R600_ERR("Break not inside loop/endloop pair\n");
2822 return -EINVAL;
2823 }
2824
2825 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2826 ctx->bc->cf_last->pop_count = 1;
2827
2828 fc_set_mid(ctx, fscp);
2829
2830 pops(ctx, 1);
2831 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2832 return 0;
2833 }
2834
2835 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2836 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2837 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2838 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2839
2840 /* FIXME:
2841 * For state trackers other than OpenGL, we'll want to use
2842 * _RECIP_IEEE instead.
2843 */
2844 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2845
2846 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2847 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2848 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2849 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2850 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2851 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2852 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2853 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2854 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2855 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2856 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2857 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2858 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2859 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2860 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2861 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2862 /* gap */
2863 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2864 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2865 /* gap */
2866 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2867 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2868 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2869 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2870 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2871 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2872 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2873 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2874 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2875 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2876 /* gap */
2877 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2878 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2879 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2880 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2881 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2882 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2883 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2884 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2885 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2886 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2887 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2888 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2889 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2891 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2892 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2893 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2894 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2895 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2896 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2897 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2898 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2899 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2900 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2901 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2902 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2903 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2904 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2908 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2910 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2911 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2912 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2913 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2914 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2917 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2918 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2919 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2920 /* gap */
2921 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2922 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2924 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2925 /* gap */
2926 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2927 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2932 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2934 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 /* gap */
2936 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2937 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2945 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2948 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2950 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 /* gap */
2952 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2955 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2957 /* gap */
2958 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2960 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2961 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2967 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2968 /* gap */
2969 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2993 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 };
2998
2999 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3000 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3002 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3003 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3004 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3005 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3006 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3008 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3009 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3010 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3011 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3012 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3013 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3014 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3015 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3016 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3017 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3018 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3019 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 /* gap */
3021 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 /* gap */
3024 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3026 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3027 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3028 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3029 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3031 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3032 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3033 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3034 /* gap */
3035 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3037 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3039 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3040 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3041 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3042 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3043 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3044 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3045 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3049 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3051 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3052 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3053 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3054 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3056 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3058 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3069 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3070 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3071 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3072 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3075 {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3076 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3077 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3078 /* gap */
3079 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3080 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3082 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3083 /* gap */
3084 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3092 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 /* gap */
3094 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3103 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3104 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3106 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3107 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3108 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 /* gap */
3110 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3113 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3115 /* gap */
3116 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3118 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3125 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3126 /* gap */
3127 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3132 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3143 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3147 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3149 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3153 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3154 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 };