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r600g: fixup for MSAA texture support checking
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include <stdio.h>
39 #include <errno.h>
40 #include <byteswap.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
88 {
89 struct tgsi_parse_context parse;
90
91 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
92 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
93 return ~0;
94 }
95 return parse.FullHeader.Processor.Processor;
96 }
97
98 static bool r600_can_dump_shader(struct r600_screen *rscreen, unsigned processor_type)
99 {
100 switch (processor_type) {
101 case TGSI_PROCESSOR_VERTEX:
102 return (rscreen->debug_flags & DBG_VS) != 0;
103 case TGSI_PROCESSOR_GEOMETRY:
104 return (rscreen->debug_flags & DBG_GS) != 0;
105 case TGSI_PROCESSOR_FRAGMENT:
106 return (rscreen->debug_flags & DBG_PS) != 0;
107 case TGSI_PROCESSOR_COMPUTE:
108 return (rscreen->debug_flags & DBG_CS) != 0;
109 default:
110 return false;
111 }
112 }
113
114 static void r600_dump_streamout(struct pipe_stream_output_info *so)
115 {
116 unsigned i;
117
118 fprintf(stderr, "STREAMOUT\n");
119 for (i = 0; i < so->num_outputs; i++) {
120 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
121 so->output[i].start_component;
122 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
123 i, so->output[i].output_buffer,
124 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
125 so->output[i].register_index,
126 mask & 1 ? "x" : "",
127 mask & 2 ? "y" : "",
128 mask & 4 ? "z" : "",
129 mask & 8 ? "w" : "",
130 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
131 }
132 }
133
134 int r600_pipe_shader_create(struct pipe_context *ctx,
135 struct r600_pipe_shader *shader,
136 struct r600_shader_key key)
137 {
138 struct r600_context *rctx = (struct r600_context *)ctx;
139 struct r600_pipe_shader_selector *sel = shader->selector;
140 int r, i;
141 uint32_t *ptr;
142 bool dump = r600_can_dump_shader(rctx->screen, tgsi_get_processor_type(sel->tokens));
143 unsigned use_sb = rctx->screen->debug_flags & DBG_SB;
144 unsigned sb_disasm = use_sb || (rctx->screen->debug_flags & DBG_SB_DISASM);
145
146 shader->shader.bc.isa = rctx->isa;
147
148 if (dump) {
149 fprintf(stderr, "--------------------------------------------------------------\n");
150 tgsi_dump(sel->tokens, 0);
151
152 if (sel->so.num_outputs) {
153 r600_dump_streamout(&sel->so);
154 }
155 }
156 r = r600_shader_from_tgsi(rctx->screen, shader, key);
157 if (r) {
158 R600_ERR("translation from TGSI failed !\n");
159 return r;
160 }
161
162 /* Check if the bytecode has already been built. When using the llvm
163 * backend, r600_shader_from_tgsi() will take care of building the
164 * bytecode.
165 */
166 if (!shader->shader.bc.bytecode) {
167 r = r600_bytecode_build(&shader->shader.bc);
168 if (r) {
169 R600_ERR("building bytecode failed !\n");
170 return r;
171 }
172 }
173
174 if (dump && !sb_disasm) {
175 fprintf(stderr, "--------------------------------------------------------------\n");
176 r600_bytecode_disasm(&shader->shader.bc);
177 fprintf(stderr, "______________________________________________________________\n");
178 } else if ((dump && sb_disasm) || use_sb) {
179 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
180 dump, use_sb);
181 if (r) {
182 R600_ERR("r600_sb_bytecode_process failed !\n");
183 return r;
184 }
185 }
186
187 /* Store the shader in a buffer. */
188 if (shader->bo == NULL) {
189 shader->bo = (struct r600_resource*)
190 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
191 if (shader->bo == NULL) {
192 return -ENOMEM;
193 }
194 ptr = r600_buffer_mmap_sync_with_rings(rctx, shader->bo, PIPE_TRANSFER_WRITE);
195 if (R600_BIG_ENDIAN) {
196 for (i = 0; i < shader->shader.bc.ndw; ++i) {
197 ptr[i] = bswap_32(shader->shader.bc.bytecode[i]);
198 }
199 } else {
200 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
201 }
202 rctx->ws->buffer_unmap(shader->bo->cs_buf);
203 }
204
205 /* Build state. */
206 switch (shader->shader.processor_type) {
207 case TGSI_PROCESSOR_VERTEX:
208 if (rctx->chip_class >= EVERGREEN) {
209 evergreen_update_vs_state(ctx, shader);
210 } else {
211 r600_update_vs_state(ctx, shader);
212 }
213 break;
214 case TGSI_PROCESSOR_FRAGMENT:
215 if (rctx->chip_class >= EVERGREEN) {
216 evergreen_update_ps_state(ctx, shader);
217 } else {
218 r600_update_ps_state(ctx, shader);
219 }
220 break;
221 default:
222 return -EINVAL;
223 }
224 return 0;
225 }
226
227 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
228 {
229 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
230 r600_bytecode_clear(&shader->shader.bc);
231 r600_release_command_buffer(&shader->command_buffer);
232 }
233
234 /*
235 * tgsi -> r600 shader
236 */
237 struct r600_shader_tgsi_instruction;
238
239 struct r600_shader_src {
240 unsigned sel;
241 unsigned swizzle[4];
242 unsigned neg;
243 unsigned abs;
244 unsigned rel;
245 unsigned kc_bank;
246 uint32_t value[4];
247 };
248
249 struct r600_shader_ctx {
250 struct tgsi_shader_info info;
251 struct tgsi_parse_context parse;
252 const struct tgsi_token *tokens;
253 unsigned type;
254 unsigned file_offset[TGSI_FILE_COUNT];
255 unsigned temp_reg;
256 struct r600_shader_tgsi_instruction *inst_info;
257 struct r600_bytecode *bc;
258 struct r600_shader *shader;
259 struct r600_shader_src src[4];
260 uint32_t *literals;
261 uint32_t nliterals;
262 uint32_t max_driver_temp_used;
263 boolean use_llvm;
264 /* needed for evergreen interpolation */
265 boolean input_centroid;
266 boolean input_linear;
267 boolean input_perspective;
268 int num_interp_gpr;
269 int face_gpr;
270 int colors_used;
271 boolean clip_vertex_write;
272 unsigned cv_output;
273 int fragcoord_input;
274 int native_integers;
275 };
276
277 struct r600_shader_tgsi_instruction {
278 unsigned tgsi_opcode;
279 unsigned is_op3;
280 unsigned op;
281 int (*process)(struct r600_shader_ctx *ctx);
282 };
283
284 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
285 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
286 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
287 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
288 static int tgsi_else(struct r600_shader_ctx *ctx);
289 static int tgsi_endif(struct r600_shader_ctx *ctx);
290 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
291 static int tgsi_endloop(struct r600_shader_ctx *ctx);
292 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
293
294 #ifdef HAVE_OPENCL
295 int r600_compute_shader_create(struct pipe_context * ctx,
296 LLVMModuleRef mod, struct r600_bytecode * bytecode)
297 {
298 struct r600_context *r600_ctx = (struct r600_context *)ctx;
299 struct r600_shader_ctx shader_ctx;
300 boolean use_kill = false;
301 bool dump = (r600_ctx->screen->debug_flags & DBG_CS) != 0;
302 unsigned use_sb = r600_ctx->screen->debug_flags & DBG_SB_CS;
303 unsigned sb_disasm = use_sb ||
304 (r600_ctx->screen->debug_flags & DBG_SB_DISASM);
305
306 shader_ctx.bc = bytecode;
307 r600_bytecode_init(shader_ctx.bc, r600_ctx->chip_class, r600_ctx->family,
308 r600_ctx->screen->has_compressed_msaa_texturing);
309 shader_ctx.bc->type = TGSI_PROCESSOR_COMPUTE;
310 shader_ctx.bc->isa = r600_ctx->isa;
311 r600_llvm_compile(mod, r600_ctx->family,
312 shader_ctx.bc, &use_kill, dump);
313
314 if (dump && !sb_disasm) {
315 r600_bytecode_disasm(shader_ctx.bc);
316 } else if ((dump && sb_disasm) || use_sb) {
317 if (r600_sb_bytecode_process(r600_ctx, shader_ctx.bc, NULL, dump, use_sb))
318 R600_ERR("r600_sb_bytecode_process failed!\n");
319 }
320
321 return 1;
322 }
323
324 #endif /* HAVE_OPENCL */
325
326 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
327 {
328 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
329 int j;
330
331 if (i->Instruction.NumDstRegs > 1) {
332 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
333 return -EINVAL;
334 }
335 if (i->Instruction.Predicate) {
336 R600_ERR("predicate unsupported\n");
337 return -EINVAL;
338 }
339 #if 0
340 if (i->Instruction.Label) {
341 R600_ERR("label unsupported\n");
342 return -EINVAL;
343 }
344 #endif
345 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
346 if (i->Src[j].Register.Dimension) {
347 if (i->Src[j].Register.File != TGSI_FILE_CONSTANT) {
348 R600_ERR("unsupported src %d (dimension %d)\n", j,
349 i->Src[j].Register.Dimension);
350 return -EINVAL;
351 }
352 }
353 }
354 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
355 if (i->Dst[j].Register.Dimension) {
356 R600_ERR("unsupported dst (dimension)\n");
357 return -EINVAL;
358 }
359 }
360 return 0;
361 }
362
363 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
364 int input)
365 {
366 int ij_index = 0;
367
368 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
369 if (ctx->shader->input[input].centroid)
370 ij_index++;
371 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
372 /* if we have perspective add one */
373 if (ctx->input_perspective) {
374 ij_index++;
375 /* if we have perspective centroid */
376 if (ctx->input_centroid)
377 ij_index++;
378 }
379 if (ctx->shader->input[input].centroid)
380 ij_index++;
381 }
382
383 ctx->shader->input[input].ij_index = ij_index;
384 }
385
386 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
387 {
388 int i, r;
389 struct r600_bytecode_alu alu;
390 int gpr = 0, base_chan = 0;
391 int ij_index = ctx->shader->input[input].ij_index;
392
393 /* work out gpr and base_chan from index */
394 gpr = ij_index / 2;
395 base_chan = (2 * (ij_index % 2)) + 1;
396
397 for (i = 0; i < 8; i++) {
398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
399
400 if (i < 4)
401 alu.op = ALU_OP2_INTERP_ZW;
402 else
403 alu.op = ALU_OP2_INTERP_XY;
404
405 if ((i > 1) && (i < 6)) {
406 alu.dst.sel = ctx->shader->input[input].gpr;
407 alu.dst.write = 1;
408 }
409
410 alu.dst.chan = i % 4;
411
412 alu.src[0].sel = gpr;
413 alu.src[0].chan = (base_chan - (i % 2));
414
415 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
416
417 alu.bank_swizzle_force = SQ_ALU_VEC_210;
418 if ((i % 4) == 3)
419 alu.last = 1;
420 r = r600_bytecode_add_alu(ctx->bc, &alu);
421 if (r)
422 return r;
423 }
424 return 0;
425 }
426
427 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
428 {
429 int i, r;
430 struct r600_bytecode_alu alu;
431
432 for (i = 0; i < 4; i++) {
433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
434
435 alu.op = ALU_OP1_INTERP_LOAD_P0;
436
437 alu.dst.sel = ctx->shader->input[input].gpr;
438 alu.dst.write = 1;
439
440 alu.dst.chan = i;
441
442 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
443 alu.src[0].chan = i;
444
445 if (i == 3)
446 alu.last = 1;
447 r = r600_bytecode_add_alu(ctx->bc, &alu);
448 if (r)
449 return r;
450 }
451 return 0;
452 }
453
454 /*
455 * Special export handling in shaders
456 *
457 * shader export ARRAY_BASE for EXPORT_POS:
458 * 60 is position
459 * 61 is misc vector
460 * 62, 63 are clip distance vectors
461 *
462 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
463 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
464 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
465 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
466 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
467 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
468 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
469 * exclusive from render target index)
470 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
471 *
472 *
473 * shader export ARRAY_BASE for EXPORT_PIXEL:
474 * 0-7 CB targets
475 * 61 computed Z vector
476 *
477 * The use of the values exported in the computed Z vector are controlled
478 * by DB_SHADER_CONTROL:
479 * Z_EXPORT_ENABLE - Z as a float in RED
480 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
481 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
482 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
483 * DB_SOURCE_FORMAT - export control restrictions
484 *
485 */
486
487
488 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
489 static int r600_spi_sid(struct r600_shader_io * io)
490 {
491 int index, name = io->name;
492
493 /* These params are handled differently, they don't need
494 * semantic indices, so we'll use 0 for them.
495 */
496 if (name == TGSI_SEMANTIC_POSITION ||
497 name == TGSI_SEMANTIC_PSIZE ||
498 name == TGSI_SEMANTIC_FACE)
499 index = 0;
500 else {
501 if (name == TGSI_SEMANTIC_GENERIC) {
502 /* For generic params simply use sid from tgsi */
503 index = io->sid;
504 } else {
505 /* For non-generic params - pack name and sid into 8 bits */
506 index = 0x80 | (name<<3) | (io->sid);
507 }
508
509 /* Make sure that all really used indices have nonzero value, so
510 * we can just compare it to 0 later instead of comparing the name
511 * with different values to detect special cases. */
512 index++;
513 }
514
515 return index;
516 };
517
518 /* turn input into interpolate on EG */
519 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
520 {
521 int r = 0;
522
523 if (ctx->shader->input[index].spi_sid) {
524 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
525 if (ctx->shader->input[index].interpolate > 0) {
526 evergreen_interp_assign_ij_index(ctx, index);
527 if (!ctx->use_llvm)
528 r = evergreen_interp_alu(ctx, index);
529 } else {
530 if (!ctx->use_llvm)
531 r = evergreen_interp_flat(ctx, index);
532 }
533 }
534 return r;
535 }
536
537 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
538 {
539 struct r600_bytecode_alu alu;
540 int i, r;
541 int gpr_front = ctx->shader->input[front].gpr;
542 int gpr_back = ctx->shader->input[back].gpr;
543
544 for (i = 0; i < 4; i++) {
545 memset(&alu, 0, sizeof(alu));
546 alu.op = ALU_OP3_CNDGT;
547 alu.is_op3 = 1;
548 alu.dst.write = 1;
549 alu.dst.sel = gpr_front;
550 alu.src[0].sel = ctx->face_gpr;
551 alu.src[1].sel = gpr_front;
552 alu.src[2].sel = gpr_back;
553
554 alu.dst.chan = i;
555 alu.src[1].chan = i;
556 alu.src[2].chan = i;
557 alu.last = (i==3);
558
559 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
560 return r;
561 }
562
563 return 0;
564 }
565
566 static int tgsi_declaration(struct r600_shader_ctx *ctx)
567 {
568 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
569 int r, i, j, count = d->Range.Last - d->Range.First + 1;
570
571 switch (d->Declaration.File) {
572 case TGSI_FILE_INPUT:
573 i = ctx->shader->ninput;
574 assert(i < Elements(ctx->shader->input));
575 ctx->shader->ninput += count;
576 ctx->shader->input[i].name = d->Semantic.Name;
577 ctx->shader->input[i].sid = d->Semantic.Index;
578 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
579 ctx->shader->input[i].centroid = d->Interp.Centroid;
580 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
581 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
582 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
583 switch (ctx->shader->input[i].name) {
584 case TGSI_SEMANTIC_FACE:
585 ctx->face_gpr = ctx->shader->input[i].gpr;
586 break;
587 case TGSI_SEMANTIC_COLOR:
588 ctx->colors_used++;
589 break;
590 case TGSI_SEMANTIC_POSITION:
591 ctx->fragcoord_input = i;
592 break;
593 }
594 if (ctx->bc->chip_class >= EVERGREEN) {
595 if ((r = evergreen_interp_input(ctx, i)))
596 return r;
597 }
598 }
599 for (j = 1; j < count; ++j) {
600 ctx->shader->input[i + j] = ctx->shader->input[i];
601 ctx->shader->input[i + j].gpr += j;
602 }
603 break;
604 case TGSI_FILE_OUTPUT:
605 i = ctx->shader->noutput++;
606 assert(i < Elements(ctx->shader->output));
607 ctx->shader->output[i].name = d->Semantic.Name;
608 ctx->shader->output[i].sid = d->Semantic.Index;
609 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
610 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
611 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
612 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
613 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
614 switch (d->Semantic.Name) {
615 case TGSI_SEMANTIC_CLIPDIST:
616 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
617 break;
618 case TGSI_SEMANTIC_PSIZE:
619 ctx->shader->vs_out_misc_write = 1;
620 ctx->shader->vs_out_point_size = 1;
621 break;
622 case TGSI_SEMANTIC_CLIPVERTEX:
623 ctx->clip_vertex_write = TRUE;
624 ctx->cv_output = i;
625 break;
626 }
627 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
628 switch (d->Semantic.Name) {
629 case TGSI_SEMANTIC_COLOR:
630 ctx->shader->nr_ps_max_color_exports++;
631 break;
632 }
633 }
634 break;
635 case TGSI_FILE_TEMPORARY:
636 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
637 if (d->Array.ArrayID) {
638 r600_add_gpr_array(ctx->shader,
639 ctx->file_offset[TGSI_FILE_TEMPORARY] +
640 d->Range.First,
641 d->Range.Last - d->Range.First + 1, 0x0F);
642 }
643 }
644 break;
645
646 case TGSI_FILE_CONSTANT:
647 case TGSI_FILE_SAMPLER:
648 case TGSI_FILE_ADDRESS:
649 break;
650
651 case TGSI_FILE_SYSTEM_VALUE:
652 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
653 if (!ctx->native_integers) {
654 struct r600_bytecode_alu alu;
655 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
656
657 alu.op = ALU_OP1_INT_TO_FLT;
658 alu.src[0].sel = 0;
659 alu.src[0].chan = 3;
660
661 alu.dst.sel = 0;
662 alu.dst.chan = 3;
663 alu.dst.write = 1;
664 alu.last = 1;
665
666 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
667 return r;
668 }
669 break;
670 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
671 break;
672 default:
673 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
674 return -EINVAL;
675 }
676 return 0;
677 }
678
679 static int r600_get_temp(struct r600_shader_ctx *ctx)
680 {
681 return ctx->temp_reg + ctx->max_driver_temp_used++;
682 }
683
684 /*
685 * for evergreen we need to scan the shader to find the number of GPRs we need to
686 * reserve for interpolation.
687 *
688 * we need to know if we are going to emit
689 * any centroid inputs
690 * if perspective and linear are required
691 */
692 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
693 {
694 int i;
695 int num_baryc;
696
697 ctx->input_linear = FALSE;
698 ctx->input_perspective = FALSE;
699 ctx->input_centroid = FALSE;
700 ctx->num_interp_gpr = 1;
701
702 /* any centroid inputs */
703 for (i = 0; i < ctx->info.num_inputs; i++) {
704 /* skip position/face */
705 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
706 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
707 continue;
708 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
709 ctx->input_linear = TRUE;
710 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
711 ctx->input_perspective = TRUE;
712 if (ctx->info.input_centroid[i])
713 ctx->input_centroid = TRUE;
714 }
715
716 num_baryc = 0;
717 /* ignoring sample for now */
718 if (ctx->input_perspective)
719 num_baryc++;
720 if (ctx->input_linear)
721 num_baryc++;
722 if (ctx->input_centroid)
723 num_baryc *= 2;
724
725 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
726
727 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
728 return ctx->num_interp_gpr;
729 }
730
731 static void tgsi_src(struct r600_shader_ctx *ctx,
732 const struct tgsi_full_src_register *tgsi_src,
733 struct r600_shader_src *r600_src)
734 {
735 memset(r600_src, 0, sizeof(*r600_src));
736 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
737 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
738 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
739 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
740 r600_src->neg = tgsi_src->Register.Negate;
741 r600_src->abs = tgsi_src->Register.Absolute;
742
743 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
744 int index;
745 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
746 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
747 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
748
749 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
750 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
751 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
752 return;
753 }
754 index = tgsi_src->Register.Index;
755 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
756 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
757 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
758 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
759 r600_src->swizzle[0] = 3;
760 r600_src->swizzle[1] = 3;
761 r600_src->swizzle[2] = 3;
762 r600_src->swizzle[3] = 3;
763 r600_src->sel = 0;
764 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
765 r600_src->swizzle[0] = 0;
766 r600_src->swizzle[1] = 0;
767 r600_src->swizzle[2] = 0;
768 r600_src->swizzle[3] = 0;
769 r600_src->sel = 0;
770 }
771 } else {
772 if (tgsi_src->Register.Indirect)
773 r600_src->rel = V_SQ_REL_RELATIVE;
774 r600_src->sel = tgsi_src->Register.Index;
775 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
776 }
777 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
778 if (tgsi_src->Register.Dimension) {
779 r600_src->kc_bank = tgsi_src->Dimension.Index;
780 }
781 }
782 }
783
784 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
785 {
786 struct r600_bytecode_vtx vtx;
787 unsigned int ar_reg;
788 int r;
789
790 if (offset) {
791 struct r600_bytecode_alu alu;
792
793 memset(&alu, 0, sizeof(alu));
794
795 alu.op = ALU_OP2_ADD_INT;
796 alu.src[0].sel = ctx->bc->ar_reg;
797
798 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
799 alu.src[1].value = offset;
800
801 alu.dst.sel = dst_reg;
802 alu.dst.write = 1;
803 alu.last = 1;
804
805 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
806 return r;
807
808 ar_reg = dst_reg;
809 } else {
810 ar_reg = ctx->bc->ar_reg;
811 }
812
813 memset(&vtx, 0, sizeof(vtx));
814 vtx.buffer_id = cb_idx;
815 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
816 vtx.src_gpr = ar_reg;
817 vtx.mega_fetch_count = 16;
818 vtx.dst_gpr = dst_reg;
819 vtx.dst_sel_x = 0; /* SEL_X */
820 vtx.dst_sel_y = 1; /* SEL_Y */
821 vtx.dst_sel_z = 2; /* SEL_Z */
822 vtx.dst_sel_w = 3; /* SEL_W */
823 vtx.data_format = FMT_32_32_32_32_FLOAT;
824 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
825 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
826 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
827 vtx.endian = r600_endian_swap(32);
828
829 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
830 return r;
831
832 return 0;
833 }
834
835 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
836 {
837 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
838 struct r600_bytecode_alu alu;
839 int i, j, k, nconst, r;
840
841 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
842 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
843 nconst++;
844 }
845 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
846 }
847 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
848 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
849 continue;
850 }
851
852 if (ctx->src[i].rel) {
853 int treg = r600_get_temp(ctx);
854 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
855 return r;
856
857 ctx->src[i].kc_bank = 0;
858 ctx->src[i].sel = treg;
859 ctx->src[i].rel = 0;
860 j--;
861 } else if (j > 0) {
862 int treg = r600_get_temp(ctx);
863 for (k = 0; k < 4; k++) {
864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
865 alu.op = ALU_OP1_MOV;
866 alu.src[0].sel = ctx->src[i].sel;
867 alu.src[0].chan = k;
868 alu.src[0].rel = ctx->src[i].rel;
869 alu.dst.sel = treg;
870 alu.dst.chan = k;
871 alu.dst.write = 1;
872 if (k == 3)
873 alu.last = 1;
874 r = r600_bytecode_add_alu(ctx->bc, &alu);
875 if (r)
876 return r;
877 }
878 ctx->src[i].sel = treg;
879 ctx->src[i].rel =0;
880 j--;
881 }
882 }
883 return 0;
884 }
885
886 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
887 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
888 {
889 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
890 struct r600_bytecode_alu alu;
891 int i, j, k, nliteral, r;
892
893 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
894 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
895 nliteral++;
896 }
897 }
898 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
899 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
900 int treg = r600_get_temp(ctx);
901 for (k = 0; k < 4; k++) {
902 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
903 alu.op = ALU_OP1_MOV;
904 alu.src[0].sel = ctx->src[i].sel;
905 alu.src[0].chan = k;
906 alu.src[0].value = ctx->src[i].value[k];
907 alu.dst.sel = treg;
908 alu.dst.chan = k;
909 alu.dst.write = 1;
910 if (k == 3)
911 alu.last = 1;
912 r = r600_bytecode_add_alu(ctx->bc, &alu);
913 if (r)
914 return r;
915 }
916 ctx->src[i].sel = treg;
917 j--;
918 }
919 }
920 return 0;
921 }
922
923 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
924 {
925 int i, r, count = ctx->shader->ninput;
926
927 for (i = 0; i < count; i++) {
928 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
929 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
930 if (r)
931 return r;
932 }
933 }
934 return 0;
935 }
936
937
938 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
939 struct r600_pipe_shader *pipeshader,
940 struct r600_shader_key key)
941 {
942 struct r600_shader *shader = &pipeshader->shader;
943 struct tgsi_token *tokens = pipeshader->selector->tokens;
944 struct pipe_stream_output_info so = pipeshader->selector->so;
945 struct tgsi_full_immediate *immediate;
946 struct tgsi_full_property *property;
947 struct r600_shader_ctx ctx;
948 struct r600_bytecode_output output[32];
949 unsigned output_done, noutput;
950 unsigned opcode;
951 int i, j, k, r = 0;
952 int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
953 /* Declarations used by llvm code */
954 bool use_llvm = false;
955 bool indirect_gprs;
956
957 #ifdef R600_USE_LLVM
958 use_llvm = !(rscreen->debug_flags & DBG_NO_LLVM);
959 #endif
960 ctx.bc = &shader->bc;
961 ctx.shader = shader;
962 ctx.native_integers = true;
963
964 r600_bytecode_init(ctx.bc, rscreen->chip_class, rscreen->family,
965 rscreen->has_compressed_msaa_texturing);
966 ctx.tokens = tokens;
967 tgsi_scan_shader(tokens, &ctx.info);
968 shader->indirect_files = ctx.info.indirect_files;
969 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
970 tgsi_parse_init(&ctx.parse, tokens);
971 ctx.type = ctx.parse.FullHeader.Processor.Processor;
972 shader->processor_type = ctx.type;
973 ctx.bc->type = shader->processor_type;
974
975 ctx.face_gpr = -1;
976 ctx.fragcoord_input = -1;
977 ctx.colors_used = 0;
978 ctx.clip_vertex_write = 0;
979
980 shader->nr_ps_color_exports = 0;
981 shader->nr_ps_max_color_exports = 0;
982
983 shader->two_side = key.color_two_side;
984
985 /* register allocations */
986 /* Values [0,127] correspond to GPR[0..127].
987 * Values [128,159] correspond to constant buffer bank 0
988 * Values [160,191] correspond to constant buffer bank 1
989 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
990 * Values [256,287] correspond to constant buffer bank 2 (EG)
991 * Values [288,319] correspond to constant buffer bank 3 (EG)
992 * Other special values are shown in the list below.
993 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
994 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
995 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
996 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
997 * 248 SQ_ALU_SRC_0: special constant 0.0.
998 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
999 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1000 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1001 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1002 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1003 * 254 SQ_ALU_SRC_PV: previous vector result.
1004 * 255 SQ_ALU_SRC_PS: previous scalar result.
1005 */
1006 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1007 ctx.file_offset[i] = 0;
1008 }
1009
1010 #ifdef R600_USE_LLVM
1011 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1012 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1013 "indirect adressing. Falling back to TGSI "
1014 "backend.\n");
1015 use_llvm = 0;
1016 }
1017 #endif
1018 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1019 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1020 if (!use_llvm) {
1021 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1022 }
1023 }
1024 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1025 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1026 }
1027 ctx.use_llvm = use_llvm;
1028
1029 if (use_llvm) {
1030 ctx.file_offset[TGSI_FILE_OUTPUT] =
1031 ctx.file_offset[TGSI_FILE_INPUT];
1032 } else {
1033 ctx.file_offset[TGSI_FILE_OUTPUT] =
1034 ctx.file_offset[TGSI_FILE_INPUT] +
1035 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1036 }
1037 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1038 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1039
1040 /* Outside the GPR range. This will be translated to one of the
1041 * kcache banks later. */
1042 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1043
1044 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1045 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1046 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1047 ctx.temp_reg = ctx.bc->ar_reg + 1;
1048
1049 if (indirect_gprs) {
1050 shader->max_arrays = 0;
1051 shader->num_arrays = 0;
1052
1053 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1054 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1055 ctx.file_offset[TGSI_FILE_OUTPUT] -
1056 ctx.file_offset[TGSI_FILE_INPUT],
1057 0x0F);
1058 }
1059 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1060 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1061 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1062 ctx.file_offset[TGSI_FILE_OUTPUT],
1063 0x0F);
1064 }
1065 }
1066
1067 ctx.nliterals = 0;
1068 ctx.literals = NULL;
1069 shader->fs_write_all = FALSE;
1070 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1071 tgsi_parse_token(&ctx.parse);
1072 switch (ctx.parse.FullToken.Token.Type) {
1073 case TGSI_TOKEN_TYPE_IMMEDIATE:
1074 immediate = &ctx.parse.FullToken.FullImmediate;
1075 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1076 if(ctx.literals == NULL) {
1077 r = -ENOMEM;
1078 goto out_err;
1079 }
1080 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1081 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1082 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1083 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1084 ctx.nliterals++;
1085 break;
1086 case TGSI_TOKEN_TYPE_DECLARATION:
1087 r = tgsi_declaration(&ctx);
1088 if (r)
1089 goto out_err;
1090 break;
1091 case TGSI_TOKEN_TYPE_INSTRUCTION:
1092 break;
1093 case TGSI_TOKEN_TYPE_PROPERTY:
1094 property = &ctx.parse.FullToken.FullProperty;
1095 switch (property->Property.PropertyName) {
1096 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1097 if (property->u[0].Data == 1)
1098 shader->fs_write_all = TRUE;
1099 break;
1100 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1101 /* we don't need this one */
1102 break;
1103 }
1104 break;
1105 default:
1106 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1107 r = -EINVAL;
1108 goto out_err;
1109 }
1110 }
1111
1112 /* Process two side if needed */
1113 if (shader->two_side && ctx.colors_used) {
1114 int i, count = ctx.shader->ninput;
1115 unsigned next_lds_loc = ctx.shader->nlds;
1116
1117 /* additional inputs will be allocated right after the existing inputs,
1118 * we won't need them after the color selection, so we don't need to
1119 * reserve these gprs for the rest of the shader code and to adjust
1120 * output offsets etc. */
1121 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1122 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1123
1124 if (ctx.face_gpr == -1) {
1125 i = ctx.shader->ninput++;
1126 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1127 ctx.shader->input[i].spi_sid = 0;
1128 ctx.shader->input[i].gpr = gpr++;
1129 ctx.face_gpr = ctx.shader->input[i].gpr;
1130 }
1131
1132 for (i = 0; i < count; i++) {
1133 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1134 int ni = ctx.shader->ninput++;
1135 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1136 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1137 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1138 ctx.shader->input[ni].gpr = gpr++;
1139 // TGSI to LLVM needs to know the lds position of inputs.
1140 // Non LLVM path computes it later (in process_twoside_color)
1141 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1142 ctx.shader->input[i].back_color_input = ni;
1143 if (ctx.bc->chip_class >= EVERGREEN) {
1144 if ((r = evergreen_interp_input(&ctx, ni)))
1145 return r;
1146 }
1147 }
1148 }
1149 }
1150
1151 /* LLVM backend setup */
1152 #ifdef R600_USE_LLVM
1153 if (use_llvm) {
1154 struct radeon_llvm_context radeon_llvm_ctx;
1155 LLVMModuleRef mod;
1156 bool dump = r600_can_dump_shader(rscreen, ctx.type);
1157 boolean use_kill = false;
1158
1159 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1160 radeon_llvm_ctx.type = ctx.type;
1161 radeon_llvm_ctx.two_side = shader->two_side;
1162 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1163 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1164 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1165 radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
1166 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1167 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
1168 radeon_llvm_ctx.stream_outputs = &so;
1169 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1170 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1171 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1172
1173 if (r600_llvm_compile(mod, rscreen->family, ctx.bc, &use_kill, dump)) {
1174 radeon_llvm_dispose(&radeon_llvm_ctx);
1175 use_llvm = 0;
1176 fprintf(stderr, "R600 LLVM backend failed to compile "
1177 "shader. Falling back to TGSI\n");
1178 } else {
1179 ctx.file_offset[TGSI_FILE_OUTPUT] =
1180 ctx.file_offset[TGSI_FILE_INPUT];
1181 }
1182 if (use_kill)
1183 ctx.shader->uses_kill = use_kill;
1184 radeon_llvm_dispose(&radeon_llvm_ctx);
1185 }
1186 #endif
1187 /* End of LLVM backend setup */
1188
1189 if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
1190 shader->nr_ps_max_color_exports = 8;
1191
1192 if (!use_llvm) {
1193 if (ctx.fragcoord_input >= 0) {
1194 if (ctx.bc->chip_class == CAYMAN) {
1195 for (j = 0 ; j < 4; j++) {
1196 struct r600_bytecode_alu alu;
1197 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1198 alu.op = ALU_OP1_RECIP_IEEE;
1199 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1200 alu.src[0].chan = 3;
1201
1202 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1203 alu.dst.chan = j;
1204 alu.dst.write = (j == 3);
1205 alu.last = 1;
1206 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1207 return r;
1208 }
1209 } else {
1210 struct r600_bytecode_alu alu;
1211 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1212 alu.op = ALU_OP1_RECIP_IEEE;
1213 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1214 alu.src[0].chan = 3;
1215
1216 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1217 alu.dst.chan = 3;
1218 alu.dst.write = 1;
1219 alu.last = 1;
1220 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1221 return r;
1222 }
1223 }
1224
1225 if (shader->two_side && ctx.colors_used) {
1226 if ((r = process_twoside_color_inputs(&ctx)))
1227 return r;
1228 }
1229
1230 tgsi_parse_init(&ctx.parse, tokens);
1231 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1232 tgsi_parse_token(&ctx.parse);
1233 switch (ctx.parse.FullToken.Token.Type) {
1234 case TGSI_TOKEN_TYPE_INSTRUCTION:
1235 r = tgsi_is_supported(&ctx);
1236 if (r)
1237 goto out_err;
1238 ctx.max_driver_temp_used = 0;
1239 /* reserve first tmp for everyone */
1240 r600_get_temp(&ctx);
1241
1242 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1243 if ((r = tgsi_split_constant(&ctx)))
1244 goto out_err;
1245 if ((r = tgsi_split_literal_constant(&ctx)))
1246 goto out_err;
1247 if (ctx.bc->chip_class == CAYMAN)
1248 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1249 else if (ctx.bc->chip_class >= EVERGREEN)
1250 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1251 else
1252 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1253 r = ctx.inst_info->process(&ctx);
1254 if (r)
1255 goto out_err;
1256 break;
1257 default:
1258 break;
1259 }
1260 }
1261 }
1262
1263 /* Reset the temporary register counter. */
1264 ctx.max_driver_temp_used = 0;
1265
1266 noutput = shader->noutput;
1267
1268 if (ctx.clip_vertex_write) {
1269 unsigned clipdist_temp[2];
1270
1271 clipdist_temp[0] = r600_get_temp(&ctx);
1272 clipdist_temp[1] = r600_get_temp(&ctx);
1273
1274 /* need to convert a clipvertex write into clipdistance writes and not export
1275 the clip vertex anymore */
1276
1277 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1278 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1279 shader->output[noutput].gpr = clipdist_temp[0];
1280 noutput++;
1281 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1282 shader->output[noutput].gpr = clipdist_temp[1];
1283 noutput++;
1284
1285 /* reset spi_sid for clipvertex output to avoid confusing spi */
1286 shader->output[ctx.cv_output].spi_sid = 0;
1287
1288 shader->clip_dist_write = 0xFF;
1289
1290 for (i = 0; i < 8; i++) {
1291 int oreg = i >> 2;
1292 int ochan = i & 3;
1293
1294 for (j = 0; j < 4; j++) {
1295 struct r600_bytecode_alu alu;
1296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1297 alu.op = ALU_OP2_DOT4;
1298 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1299 alu.src[0].chan = j;
1300
1301 alu.src[1].sel = 512 + i;
1302 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1303 alu.src[1].chan = j;
1304
1305 alu.dst.sel = clipdist_temp[oreg];
1306 alu.dst.chan = j;
1307 alu.dst.write = (j == ochan);
1308 if (j == 3)
1309 alu.last = 1;
1310 if (!use_llvm)
1311 r = r600_bytecode_add_alu(ctx.bc, &alu);
1312 if (r)
1313 return r;
1314 }
1315 }
1316 }
1317
1318 /* Add stream outputs. */
1319 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
1320 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1321
1322 /* Sanity checking. */
1323 if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1324 R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
1325 r = -EINVAL;
1326 goto out_err;
1327 }
1328 for (i = 0; i < so.num_outputs; i++) {
1329 if (so.output[i].output_buffer >= 4) {
1330 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1331 so.output[i].output_buffer);
1332 r = -EINVAL;
1333 goto out_err;
1334 }
1335 }
1336
1337 /* Initialize locations where the outputs are stored. */
1338 for (i = 0; i < so.num_outputs; i++) {
1339 so_gpr[i] = shader->output[so.output[i].register_index].gpr;
1340
1341 /* Lower outputs with dst_offset < start_component.
1342 *
1343 * We can only output 4D vectors with a write mask, e.g. we can
1344 * only output the W component at offset 3, etc. If we want
1345 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1346 * to move it to X and output X. */
1347 if (so.output[i].dst_offset < so.output[i].start_component) {
1348 unsigned tmp = r600_get_temp(&ctx);
1349
1350 for (j = 0; j < so.output[i].num_components; j++) {
1351 struct r600_bytecode_alu alu;
1352 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1353 alu.op = ALU_OP1_MOV;
1354 alu.src[0].sel = so_gpr[i];
1355 alu.src[0].chan = so.output[i].start_component + j;
1356
1357 alu.dst.sel = tmp;
1358 alu.dst.chan = j;
1359 alu.dst.write = 1;
1360 if (j == so.output[i].num_components - 1)
1361 alu.last = 1;
1362 r = r600_bytecode_add_alu(ctx.bc, &alu);
1363 if (r)
1364 return r;
1365 }
1366 so.output[i].start_component = 0;
1367 so_gpr[i] = tmp;
1368 }
1369 }
1370
1371 /* Write outputs to buffers. */
1372 for (i = 0; i < so.num_outputs; i++) {
1373 struct r600_bytecode_output output;
1374
1375 memset(&output, 0, sizeof(struct r600_bytecode_output));
1376 output.gpr = so_gpr[i];
1377 output.elem_size = so.output[i].num_components;
1378 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1379 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1380 output.burst_count = 1;
1381 output.barrier = 1;
1382 /* array_size is an upper limit for the burst_count
1383 * with MEM_STREAM instructions */
1384 output.array_size = 0xFFF;
1385 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1386 if (ctx.bc->chip_class >= EVERGREEN) {
1387 switch (so.output[i].output_buffer) {
1388 case 0:
1389 output.op = CF_OP_MEM_STREAM0_BUF0;
1390 break;
1391 case 1:
1392 output.op = CF_OP_MEM_STREAM0_BUF1;
1393 break;
1394 case 2:
1395 output.op = CF_OP_MEM_STREAM0_BUF2;
1396 break;
1397 case 3:
1398 output.op = CF_OP_MEM_STREAM0_BUF3;
1399 break;
1400 }
1401 } else {
1402 switch (so.output[i].output_buffer) {
1403 case 0:
1404 output.op = CF_OP_MEM_STREAM0;
1405 break;
1406 case 1:
1407 output.op = CF_OP_MEM_STREAM1;
1408 break;
1409 case 2:
1410 output.op = CF_OP_MEM_STREAM2;
1411 break;
1412 case 3:
1413 output.op = CF_OP_MEM_STREAM3;
1414 break;
1415 }
1416 }
1417 r = r600_bytecode_add_output(ctx.bc, &output);
1418 if (r)
1419 goto out_err;
1420 }
1421 }
1422
1423 /* export output */
1424 for (i = 0, j = 0; i < noutput; i++, j++) {
1425 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1426 output[j].gpr = shader->output[i].gpr;
1427 output[j].elem_size = 3;
1428 output[j].swizzle_x = 0;
1429 output[j].swizzle_y = 1;
1430 output[j].swizzle_z = 2;
1431 output[j].swizzle_w = 3;
1432 output[j].burst_count = 1;
1433 output[j].barrier = 1;
1434 output[j].type = -1;
1435 output[j].op = CF_OP_EXPORT;
1436 switch (ctx.type) {
1437 case TGSI_PROCESSOR_VERTEX:
1438 switch (shader->output[i].name) {
1439 case TGSI_SEMANTIC_POSITION:
1440 output[j].array_base = next_pos_base++;
1441 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1442 break;
1443
1444 case TGSI_SEMANTIC_PSIZE:
1445 output[j].array_base = next_pos_base++;
1446 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1447 break;
1448 case TGSI_SEMANTIC_CLIPVERTEX:
1449 j--;
1450 break;
1451 case TGSI_SEMANTIC_CLIPDIST:
1452 output[j].array_base = next_pos_base++;
1453 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1454 /* spi_sid is 0 for clipdistance outputs that were generated
1455 * for clipvertex - we don't need to pass them to PS */
1456 if (shader->output[i].spi_sid) {
1457 j++;
1458 /* duplicate it as PARAM to pass to the pixel shader */
1459 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1460 output[j].array_base = next_param_base++;
1461 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1462 }
1463 break;
1464 case TGSI_SEMANTIC_FOG:
1465 output[j].swizzle_y = 4; /* 0 */
1466 output[j].swizzle_z = 4; /* 0 */
1467 output[j].swizzle_w = 5; /* 1 */
1468 break;
1469 }
1470 break;
1471 case TGSI_PROCESSOR_FRAGMENT:
1472 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1473 /* never export more colors than the number of CBs */
1474 if (next_pixel_base && next_pixel_base >= key.nr_cbufs) {
1475 /* skip export */
1476 j--;
1477 continue;
1478 }
1479 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1480 output[j].array_base = next_pixel_base++;
1481 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1482 shader->nr_ps_color_exports++;
1483 if (shader->fs_write_all && (rscreen->chip_class >= EVERGREEN)) {
1484 for (k = 1; k < key.nr_cbufs; k++) {
1485 j++;
1486 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1487 output[j].gpr = shader->output[i].gpr;
1488 output[j].elem_size = 3;
1489 output[j].swizzle_x = 0;
1490 output[j].swizzle_y = 1;
1491 output[j].swizzle_z = 2;
1492 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1493 output[j].burst_count = 1;
1494 output[j].barrier = 1;
1495 output[j].array_base = next_pixel_base++;
1496 output[j].op = CF_OP_EXPORT;
1497 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1498 shader->nr_ps_color_exports++;
1499 }
1500 }
1501 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1502 output[j].array_base = 61;
1503 output[j].swizzle_x = 2;
1504 output[j].swizzle_y = 7;
1505 output[j].swizzle_z = output[j].swizzle_w = 7;
1506 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1507 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1508 output[j].array_base = 61;
1509 output[j].swizzle_x = 7;
1510 output[j].swizzle_y = 1;
1511 output[j].swizzle_z = output[j].swizzle_w = 7;
1512 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1513 } else {
1514 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1515 r = -EINVAL;
1516 goto out_err;
1517 }
1518 break;
1519 default:
1520 R600_ERR("unsupported processor type %d\n", ctx.type);
1521 r = -EINVAL;
1522 goto out_err;
1523 }
1524
1525 if (output[j].type==-1) {
1526 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1527 output[j].array_base = next_param_base++;
1528 }
1529 }
1530
1531 /* add fake position export */
1532 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1533 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1534 output[j].gpr = 0;
1535 output[j].elem_size = 3;
1536 output[j].swizzle_x = 7;
1537 output[j].swizzle_y = 7;
1538 output[j].swizzle_z = 7;
1539 output[j].swizzle_w = 7;
1540 output[j].burst_count = 1;
1541 output[j].barrier = 1;
1542 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1543 output[j].array_base = next_pos_base;
1544 output[j].op = CF_OP_EXPORT;
1545 j++;
1546 }
1547
1548 /* add fake param output for vertex shader if no param is exported */
1549 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1550 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1551 output[j].gpr = 0;
1552 output[j].elem_size = 3;
1553 output[j].swizzle_x = 7;
1554 output[j].swizzle_y = 7;
1555 output[j].swizzle_z = 7;
1556 output[j].swizzle_w = 7;
1557 output[j].burst_count = 1;
1558 output[j].barrier = 1;
1559 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1560 output[j].array_base = 0;
1561 output[j].op = CF_OP_EXPORT;
1562 j++;
1563 }
1564
1565 /* add fake pixel export */
1566 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && next_pixel_base == 0) {
1567 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1568 output[j].gpr = 0;
1569 output[j].elem_size = 3;
1570 output[j].swizzle_x = 7;
1571 output[j].swizzle_y = 7;
1572 output[j].swizzle_z = 7;
1573 output[j].swizzle_w = 7;
1574 output[j].burst_count = 1;
1575 output[j].barrier = 1;
1576 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1577 output[j].array_base = 0;
1578 output[j].op = CF_OP_EXPORT;
1579 j++;
1580 }
1581
1582 noutput = j;
1583
1584 /* set export done on last export of each type */
1585 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1586 if (ctx.bc->chip_class < CAYMAN) {
1587 if (i == (noutput - 1)) {
1588 output[i].end_of_program = 1;
1589 }
1590 }
1591 if (!(output_done & (1 << output[i].type))) {
1592 output_done |= (1 << output[i].type);
1593 output[i].op = CF_OP_EXPORT_DONE;
1594 }
1595 }
1596 /* add output to bytecode */
1597 if (!use_llvm) {
1598 for (i = 0; i < noutput; i++) {
1599 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1600 if (r)
1601 goto out_err;
1602 }
1603 }
1604 /* add program end */
1605 if (!use_llvm && ctx.bc->chip_class == CAYMAN)
1606 cm_bytecode_add_cf_end(ctx.bc);
1607
1608 /* check GPR limit - we have 124 = 128 - 4
1609 * (4 are reserved as alu clause temporary registers) */
1610 if (ctx.bc->ngpr > 124) {
1611 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1612 r = -ENOMEM;
1613 goto out_err;
1614 }
1615
1616 free(ctx.literals);
1617 tgsi_parse_free(&ctx.parse);
1618 return 0;
1619 out_err:
1620 free(ctx.literals);
1621 tgsi_parse_free(&ctx.parse);
1622 return r;
1623 }
1624
1625 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1626 {
1627 R600_ERR("%s tgsi opcode unsupported\n",
1628 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1629 return -EINVAL;
1630 }
1631
1632 static int tgsi_end(struct r600_shader_ctx *ctx)
1633 {
1634 return 0;
1635 }
1636
1637 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1638 const struct r600_shader_src *shader_src,
1639 unsigned chan)
1640 {
1641 bc_src->sel = shader_src->sel;
1642 bc_src->chan = shader_src->swizzle[chan];
1643 bc_src->neg = shader_src->neg;
1644 bc_src->abs = shader_src->abs;
1645 bc_src->rel = shader_src->rel;
1646 bc_src->value = shader_src->value[bc_src->chan];
1647 bc_src->kc_bank = shader_src->kc_bank;
1648 }
1649
1650 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1651 {
1652 bc_src->abs = 1;
1653 bc_src->neg = 0;
1654 }
1655
1656 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1657 {
1658 bc_src->neg = !bc_src->neg;
1659 }
1660
1661 static void tgsi_dst(struct r600_shader_ctx *ctx,
1662 const struct tgsi_full_dst_register *tgsi_dst,
1663 unsigned swizzle,
1664 struct r600_bytecode_alu_dst *r600_dst)
1665 {
1666 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1667
1668 r600_dst->sel = tgsi_dst->Register.Index;
1669 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1670 r600_dst->chan = swizzle;
1671 r600_dst->write = 1;
1672 if (tgsi_dst->Register.Indirect)
1673 r600_dst->rel = V_SQ_REL_RELATIVE;
1674 if (inst->Instruction.Saturate) {
1675 r600_dst->clamp = 1;
1676 }
1677 }
1678
1679 static int tgsi_last_instruction(unsigned writemask)
1680 {
1681 int i, lasti = 0;
1682
1683 for (i = 0; i < 4; i++) {
1684 if (writemask & (1 << i)) {
1685 lasti = i;
1686 }
1687 }
1688 return lasti;
1689 }
1690
1691 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1692 {
1693 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1694 struct r600_bytecode_alu alu;
1695 int i, j, r;
1696 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1697
1698 for (i = 0; i < lasti + 1; i++) {
1699 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1700 continue;
1701
1702 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1703 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1704
1705 alu.op = ctx->inst_info->op;
1706 if (!swap) {
1707 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1708 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1709 }
1710 } else {
1711 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1712 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1713 }
1714 /* handle some special cases */
1715 switch (ctx->inst_info->tgsi_opcode) {
1716 case TGSI_OPCODE_SUB:
1717 r600_bytecode_src_toggle_neg(&alu.src[1]);
1718 break;
1719 case TGSI_OPCODE_ABS:
1720 r600_bytecode_src_set_abs(&alu.src[0]);
1721 break;
1722 default:
1723 break;
1724 }
1725 if (i == lasti || trans_only) {
1726 alu.last = 1;
1727 }
1728 r = r600_bytecode_add_alu(ctx->bc, &alu);
1729 if (r)
1730 return r;
1731 }
1732 return 0;
1733 }
1734
1735 static int tgsi_op2(struct r600_shader_ctx *ctx)
1736 {
1737 return tgsi_op2_s(ctx, 0, 0);
1738 }
1739
1740 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1741 {
1742 return tgsi_op2_s(ctx, 1, 0);
1743 }
1744
1745 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1746 {
1747 return tgsi_op2_s(ctx, 0, 1);
1748 }
1749
1750 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1751 {
1752 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1753 struct r600_bytecode_alu alu;
1754 int i, r;
1755 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1756
1757 for (i = 0; i < lasti + 1; i++) {
1758
1759 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1760 continue;
1761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1762 alu.op = ctx->inst_info->op;
1763
1764 alu.src[0].sel = V_SQ_ALU_SRC_0;
1765
1766 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1767
1768 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1769
1770 if (i == lasti) {
1771 alu.last = 1;
1772 }
1773 r = r600_bytecode_add_alu(ctx->bc, &alu);
1774 if (r)
1775 return r;
1776 }
1777 return 0;
1778
1779 }
1780
1781 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1782 {
1783 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1784 int i, j, r;
1785 struct r600_bytecode_alu alu;
1786 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1787
1788 for (i = 0 ; i < last_slot; i++) {
1789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1790 alu.op = ctx->inst_info->op;
1791 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1792 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1793
1794 /* RSQ should take the absolute value of src */
1795 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
1796 r600_bytecode_src_set_abs(&alu.src[j]);
1797 }
1798 }
1799 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1800 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1801
1802 if (i == last_slot - 1)
1803 alu.last = 1;
1804 r = r600_bytecode_add_alu(ctx->bc, &alu);
1805 if (r)
1806 return r;
1807 }
1808 return 0;
1809 }
1810
1811 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
1812 {
1813 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1814 int i, j, k, r;
1815 struct r600_bytecode_alu alu;
1816 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1817 for (k = 0; k < last_slot; k++) {
1818 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
1819 continue;
1820
1821 for (i = 0 ; i < 4; i++) {
1822 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1823 alu.op = ctx->inst_info->op;
1824 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1825 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
1826 }
1827 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1828 alu.dst.write = (i == k);
1829 if (i == 3)
1830 alu.last = 1;
1831 r = r600_bytecode_add_alu(ctx->bc, &alu);
1832 if (r)
1833 return r;
1834 }
1835 }
1836 return 0;
1837 }
1838
1839 /*
1840 * r600 - trunc to -PI..PI range
1841 * r700 - normalize by dividing by 2PI
1842 * see fdo bug 27901
1843 */
1844 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1845 {
1846 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1847 static float double_pi = 3.1415926535 * 2;
1848 static float neg_pi = -3.1415926535;
1849
1850 int r;
1851 struct r600_bytecode_alu alu;
1852
1853 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1854 alu.op = ALU_OP3_MULADD;
1855 alu.is_op3 = 1;
1856
1857 alu.dst.chan = 0;
1858 alu.dst.sel = ctx->temp_reg;
1859 alu.dst.write = 1;
1860
1861 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1862
1863 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1864 alu.src[1].chan = 0;
1865 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1866 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1867 alu.src[2].chan = 0;
1868 alu.last = 1;
1869 r = r600_bytecode_add_alu(ctx->bc, &alu);
1870 if (r)
1871 return r;
1872
1873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1874 alu.op = ALU_OP1_FRACT;
1875
1876 alu.dst.chan = 0;
1877 alu.dst.sel = ctx->temp_reg;
1878 alu.dst.write = 1;
1879
1880 alu.src[0].sel = ctx->temp_reg;
1881 alu.src[0].chan = 0;
1882 alu.last = 1;
1883 r = r600_bytecode_add_alu(ctx->bc, &alu);
1884 if (r)
1885 return r;
1886
1887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1888 alu.op = ALU_OP3_MULADD;
1889 alu.is_op3 = 1;
1890
1891 alu.dst.chan = 0;
1892 alu.dst.sel = ctx->temp_reg;
1893 alu.dst.write = 1;
1894
1895 alu.src[0].sel = ctx->temp_reg;
1896 alu.src[0].chan = 0;
1897
1898 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1899 alu.src[1].chan = 0;
1900 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1901 alu.src[2].chan = 0;
1902
1903 if (ctx->bc->chip_class == R600) {
1904 alu.src[1].value = *(uint32_t *)&double_pi;
1905 alu.src[2].value = *(uint32_t *)&neg_pi;
1906 } else {
1907 alu.src[1].sel = V_SQ_ALU_SRC_1;
1908 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1909 alu.src[2].neg = 1;
1910 }
1911
1912 alu.last = 1;
1913 r = r600_bytecode_add_alu(ctx->bc, &alu);
1914 if (r)
1915 return r;
1916 return 0;
1917 }
1918
1919 static int cayman_trig(struct r600_shader_ctx *ctx)
1920 {
1921 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1922 struct r600_bytecode_alu alu;
1923 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1924 int i, r;
1925
1926 r = tgsi_setup_trig(ctx);
1927 if (r)
1928 return r;
1929
1930
1931 for (i = 0; i < last_slot; i++) {
1932 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1933 alu.op = ctx->inst_info->op;
1934 alu.dst.chan = i;
1935
1936 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1937 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1938
1939 alu.src[0].sel = ctx->temp_reg;
1940 alu.src[0].chan = 0;
1941 if (i == last_slot - 1)
1942 alu.last = 1;
1943 r = r600_bytecode_add_alu(ctx->bc, &alu);
1944 if (r)
1945 return r;
1946 }
1947 return 0;
1948 }
1949
1950 static int tgsi_trig(struct r600_shader_ctx *ctx)
1951 {
1952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1953 struct r600_bytecode_alu alu;
1954 int i, r;
1955 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1956
1957 r = tgsi_setup_trig(ctx);
1958 if (r)
1959 return r;
1960
1961 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1962 alu.op = ctx->inst_info->op;
1963 alu.dst.chan = 0;
1964 alu.dst.sel = ctx->temp_reg;
1965 alu.dst.write = 1;
1966
1967 alu.src[0].sel = ctx->temp_reg;
1968 alu.src[0].chan = 0;
1969 alu.last = 1;
1970 r = r600_bytecode_add_alu(ctx->bc, &alu);
1971 if (r)
1972 return r;
1973
1974 /* replicate result */
1975 for (i = 0; i < lasti + 1; i++) {
1976 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1977 continue;
1978
1979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1980 alu.op = ALU_OP1_MOV;
1981
1982 alu.src[0].sel = ctx->temp_reg;
1983 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1984 if (i == lasti)
1985 alu.last = 1;
1986 r = r600_bytecode_add_alu(ctx->bc, &alu);
1987 if (r)
1988 return r;
1989 }
1990 return 0;
1991 }
1992
1993 static int tgsi_scs(struct r600_shader_ctx *ctx)
1994 {
1995 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1996 struct r600_bytecode_alu alu;
1997 int i, r;
1998
1999 /* We'll only need the trig stuff if we are going to write to the
2000 * X or Y components of the destination vector.
2001 */
2002 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2003 r = tgsi_setup_trig(ctx);
2004 if (r)
2005 return r;
2006 }
2007
2008 /* dst.x = COS */
2009 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2010 if (ctx->bc->chip_class == CAYMAN) {
2011 for (i = 0 ; i < 3; i++) {
2012 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2013 alu.op = ALU_OP1_COS;
2014 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2015
2016 if (i == 0)
2017 alu.dst.write = 1;
2018 else
2019 alu.dst.write = 0;
2020 alu.src[0].sel = ctx->temp_reg;
2021 alu.src[0].chan = 0;
2022 if (i == 2)
2023 alu.last = 1;
2024 r = r600_bytecode_add_alu(ctx->bc, &alu);
2025 if (r)
2026 return r;
2027 }
2028 } else {
2029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2030 alu.op = ALU_OP1_COS;
2031 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2032
2033 alu.src[0].sel = ctx->temp_reg;
2034 alu.src[0].chan = 0;
2035 alu.last = 1;
2036 r = r600_bytecode_add_alu(ctx->bc, &alu);
2037 if (r)
2038 return r;
2039 }
2040 }
2041
2042 /* dst.y = SIN */
2043 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2044 if (ctx->bc->chip_class == CAYMAN) {
2045 for (i = 0 ; i < 3; i++) {
2046 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2047 alu.op = ALU_OP1_SIN;
2048 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2049 if (i == 1)
2050 alu.dst.write = 1;
2051 else
2052 alu.dst.write = 0;
2053 alu.src[0].sel = ctx->temp_reg;
2054 alu.src[0].chan = 0;
2055 if (i == 2)
2056 alu.last = 1;
2057 r = r600_bytecode_add_alu(ctx->bc, &alu);
2058 if (r)
2059 return r;
2060 }
2061 } else {
2062 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2063 alu.op = ALU_OP1_SIN;
2064 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2065
2066 alu.src[0].sel = ctx->temp_reg;
2067 alu.src[0].chan = 0;
2068 alu.last = 1;
2069 r = r600_bytecode_add_alu(ctx->bc, &alu);
2070 if (r)
2071 return r;
2072 }
2073 }
2074
2075 /* dst.z = 0.0; */
2076 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2077 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2078
2079 alu.op = ALU_OP1_MOV;
2080
2081 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2082
2083 alu.src[0].sel = V_SQ_ALU_SRC_0;
2084 alu.src[0].chan = 0;
2085
2086 alu.last = 1;
2087
2088 r = r600_bytecode_add_alu(ctx->bc, &alu);
2089 if (r)
2090 return r;
2091 }
2092
2093 /* dst.w = 1.0; */
2094 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2095 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2096
2097 alu.op = ALU_OP1_MOV;
2098
2099 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2100
2101 alu.src[0].sel = V_SQ_ALU_SRC_1;
2102 alu.src[0].chan = 0;
2103
2104 alu.last = 1;
2105
2106 r = r600_bytecode_add_alu(ctx->bc, &alu);
2107 if (r)
2108 return r;
2109 }
2110
2111 return 0;
2112 }
2113
2114 static int tgsi_kill(struct r600_shader_ctx *ctx)
2115 {
2116 struct r600_bytecode_alu alu;
2117 int i, r;
2118
2119 for (i = 0; i < 4; i++) {
2120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2121 alu.op = ctx->inst_info->op;
2122
2123 alu.dst.chan = i;
2124
2125 alu.src[0].sel = V_SQ_ALU_SRC_0;
2126
2127 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
2128 alu.src[1].sel = V_SQ_ALU_SRC_1;
2129 alu.src[1].neg = 1;
2130 } else {
2131 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2132 }
2133 if (i == 3) {
2134 alu.last = 1;
2135 }
2136 r = r600_bytecode_add_alu(ctx->bc, &alu);
2137 if (r)
2138 return r;
2139 }
2140
2141 /* kill must be last in ALU */
2142 ctx->bc->force_add_cf = 1;
2143 ctx->shader->uses_kill = TRUE;
2144 return 0;
2145 }
2146
2147 static int tgsi_lit(struct r600_shader_ctx *ctx)
2148 {
2149 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2150 struct r600_bytecode_alu alu;
2151 int r;
2152
2153 /* tmp.x = max(src.y, 0.0) */
2154 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2155 alu.op = ALU_OP2_MAX;
2156 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2157 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2158 alu.src[1].chan = 1;
2159
2160 alu.dst.sel = ctx->temp_reg;
2161 alu.dst.chan = 0;
2162 alu.dst.write = 1;
2163
2164 alu.last = 1;
2165 r = r600_bytecode_add_alu(ctx->bc, &alu);
2166 if (r)
2167 return r;
2168
2169 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2170 {
2171 int chan;
2172 int sel;
2173 int i;
2174
2175 if (ctx->bc->chip_class == CAYMAN) {
2176 for (i = 0; i < 3; i++) {
2177 /* tmp.z = log(tmp.x) */
2178 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2179 alu.op = ALU_OP1_LOG_CLAMPED;
2180 alu.src[0].sel = ctx->temp_reg;
2181 alu.src[0].chan = 0;
2182 alu.dst.sel = ctx->temp_reg;
2183 alu.dst.chan = i;
2184 if (i == 2) {
2185 alu.dst.write = 1;
2186 alu.last = 1;
2187 } else
2188 alu.dst.write = 0;
2189
2190 r = r600_bytecode_add_alu(ctx->bc, &alu);
2191 if (r)
2192 return r;
2193 }
2194 } else {
2195 /* tmp.z = log(tmp.x) */
2196 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2197 alu.op = ALU_OP1_LOG_CLAMPED;
2198 alu.src[0].sel = ctx->temp_reg;
2199 alu.src[0].chan = 0;
2200 alu.dst.sel = ctx->temp_reg;
2201 alu.dst.chan = 2;
2202 alu.dst.write = 1;
2203 alu.last = 1;
2204 r = r600_bytecode_add_alu(ctx->bc, &alu);
2205 if (r)
2206 return r;
2207 }
2208
2209 chan = alu.dst.chan;
2210 sel = alu.dst.sel;
2211
2212 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2214 alu.op = ALU_OP3_MUL_LIT;
2215 alu.src[0].sel = sel;
2216 alu.src[0].chan = chan;
2217 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2218 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2219 alu.dst.sel = ctx->temp_reg;
2220 alu.dst.chan = 0;
2221 alu.dst.write = 1;
2222 alu.is_op3 = 1;
2223 alu.last = 1;
2224 r = r600_bytecode_add_alu(ctx->bc, &alu);
2225 if (r)
2226 return r;
2227
2228 if (ctx->bc->chip_class == CAYMAN) {
2229 for (i = 0; i < 3; i++) {
2230 /* dst.z = exp(tmp.x) */
2231 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2232 alu.op = ALU_OP1_EXP_IEEE;
2233 alu.src[0].sel = ctx->temp_reg;
2234 alu.src[0].chan = 0;
2235 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2236 if (i == 2) {
2237 alu.dst.write = 1;
2238 alu.last = 1;
2239 } else
2240 alu.dst.write = 0;
2241 r = r600_bytecode_add_alu(ctx->bc, &alu);
2242 if (r)
2243 return r;
2244 }
2245 } else {
2246 /* dst.z = exp(tmp.x) */
2247 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2248 alu.op = ALU_OP1_EXP_IEEE;
2249 alu.src[0].sel = ctx->temp_reg;
2250 alu.src[0].chan = 0;
2251 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2252 alu.last = 1;
2253 r = r600_bytecode_add_alu(ctx->bc, &alu);
2254 if (r)
2255 return r;
2256 }
2257 }
2258
2259 /* dst.x, <- 1.0 */
2260 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2261 alu.op = ALU_OP1_MOV;
2262 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2263 alu.src[0].chan = 0;
2264 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2265 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2266 r = r600_bytecode_add_alu(ctx->bc, &alu);
2267 if (r)
2268 return r;
2269
2270 /* dst.y = max(src.x, 0.0) */
2271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2272 alu.op = ALU_OP2_MAX;
2273 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2274 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2275 alu.src[1].chan = 0;
2276 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2277 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2278 r = r600_bytecode_add_alu(ctx->bc, &alu);
2279 if (r)
2280 return r;
2281
2282 /* dst.w, <- 1.0 */
2283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2284 alu.op = ALU_OP1_MOV;
2285 alu.src[0].sel = V_SQ_ALU_SRC_1;
2286 alu.src[0].chan = 0;
2287 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2288 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2289 alu.last = 1;
2290 r = r600_bytecode_add_alu(ctx->bc, &alu);
2291 if (r)
2292 return r;
2293
2294 return 0;
2295 }
2296
2297 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2298 {
2299 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2300 struct r600_bytecode_alu alu;
2301 int i, r;
2302
2303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2304
2305 /* XXX:
2306 * For state trackers other than OpenGL, we'll want to use
2307 * _RECIPSQRT_IEEE instead.
2308 */
2309 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2310
2311 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2312 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2313 r600_bytecode_src_set_abs(&alu.src[i]);
2314 }
2315 alu.dst.sel = ctx->temp_reg;
2316 alu.dst.write = 1;
2317 alu.last = 1;
2318 r = r600_bytecode_add_alu(ctx->bc, &alu);
2319 if (r)
2320 return r;
2321 /* replicate result */
2322 return tgsi_helper_tempx_replicate(ctx);
2323 }
2324
2325 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2326 {
2327 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2328 struct r600_bytecode_alu alu;
2329 int i, r;
2330
2331 for (i = 0; i < 4; i++) {
2332 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2333 alu.src[0].sel = ctx->temp_reg;
2334 alu.op = ALU_OP1_MOV;
2335 alu.dst.chan = i;
2336 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2337 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2338 if (i == 3)
2339 alu.last = 1;
2340 r = r600_bytecode_add_alu(ctx->bc, &alu);
2341 if (r)
2342 return r;
2343 }
2344 return 0;
2345 }
2346
2347 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2348 {
2349 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2350 struct r600_bytecode_alu alu;
2351 int i, r;
2352
2353 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2354 alu.op = ctx->inst_info->op;
2355 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2356 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2357 }
2358 alu.dst.sel = ctx->temp_reg;
2359 alu.dst.write = 1;
2360 alu.last = 1;
2361 r = r600_bytecode_add_alu(ctx->bc, &alu);
2362 if (r)
2363 return r;
2364 /* replicate result */
2365 return tgsi_helper_tempx_replicate(ctx);
2366 }
2367
2368 static int cayman_pow(struct r600_shader_ctx *ctx)
2369 {
2370 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2371 int i, r;
2372 struct r600_bytecode_alu alu;
2373 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2374
2375 for (i = 0; i < 3; i++) {
2376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2377 alu.op = ALU_OP1_LOG_IEEE;
2378 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2379 alu.dst.sel = ctx->temp_reg;
2380 alu.dst.chan = i;
2381 alu.dst.write = 1;
2382 if (i == 2)
2383 alu.last = 1;
2384 r = r600_bytecode_add_alu(ctx->bc, &alu);
2385 if (r)
2386 return r;
2387 }
2388
2389 /* b * LOG2(a) */
2390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2391 alu.op = ALU_OP2_MUL;
2392 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2393 alu.src[1].sel = ctx->temp_reg;
2394 alu.dst.sel = ctx->temp_reg;
2395 alu.dst.write = 1;
2396 alu.last = 1;
2397 r = r600_bytecode_add_alu(ctx->bc, &alu);
2398 if (r)
2399 return r;
2400
2401 for (i = 0; i < last_slot; i++) {
2402 /* POW(a,b) = EXP2(b * LOG2(a))*/
2403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2404 alu.op = ALU_OP1_EXP_IEEE;
2405 alu.src[0].sel = ctx->temp_reg;
2406
2407 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2408 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2409 if (i == last_slot - 1)
2410 alu.last = 1;
2411 r = r600_bytecode_add_alu(ctx->bc, &alu);
2412 if (r)
2413 return r;
2414 }
2415 return 0;
2416 }
2417
2418 static int tgsi_pow(struct r600_shader_ctx *ctx)
2419 {
2420 struct r600_bytecode_alu alu;
2421 int r;
2422
2423 /* LOG2(a) */
2424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2425 alu.op = ALU_OP1_LOG_IEEE;
2426 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2427 alu.dst.sel = ctx->temp_reg;
2428 alu.dst.write = 1;
2429 alu.last = 1;
2430 r = r600_bytecode_add_alu(ctx->bc, &alu);
2431 if (r)
2432 return r;
2433 /* b * LOG2(a) */
2434 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2435 alu.op = ALU_OP2_MUL;
2436 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2437 alu.src[1].sel = ctx->temp_reg;
2438 alu.dst.sel = ctx->temp_reg;
2439 alu.dst.write = 1;
2440 alu.last = 1;
2441 r = r600_bytecode_add_alu(ctx->bc, &alu);
2442 if (r)
2443 return r;
2444 /* POW(a,b) = EXP2(b * LOG2(a))*/
2445 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2446 alu.op = ALU_OP1_EXP_IEEE;
2447 alu.src[0].sel = ctx->temp_reg;
2448 alu.dst.sel = ctx->temp_reg;
2449 alu.dst.write = 1;
2450 alu.last = 1;
2451 r = r600_bytecode_add_alu(ctx->bc, &alu);
2452 if (r)
2453 return r;
2454 return tgsi_helper_tempx_replicate(ctx);
2455 }
2456
2457 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2458 {
2459 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2460 struct r600_bytecode_alu alu;
2461 int i, r, j;
2462 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2463 int tmp0 = ctx->temp_reg;
2464 int tmp1 = r600_get_temp(ctx);
2465 int tmp2 = r600_get_temp(ctx);
2466 int tmp3 = r600_get_temp(ctx);
2467 /* Unsigned path:
2468 *
2469 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2470 *
2471 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2472 * 2. tmp0.z = lo (tmp0.x * src2)
2473 * 3. tmp0.w = -tmp0.z
2474 * 4. tmp0.y = hi (tmp0.x * src2)
2475 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2476 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2477 * 7. tmp1.x = tmp0.x - tmp0.w
2478 * 8. tmp1.y = tmp0.x + tmp0.w
2479 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2480 * 10. tmp0.z = hi(tmp0.x * src1) = q
2481 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2482 *
2483 * 12. tmp0.w = src1 - tmp0.y = r
2484 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2485 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2486 *
2487 * if DIV
2488 *
2489 * 15. tmp1.z = tmp0.z + 1 = q + 1
2490 * 16. tmp1.w = tmp0.z - 1 = q - 1
2491 *
2492 * else MOD
2493 *
2494 * 15. tmp1.z = tmp0.w - src2 = r - src2
2495 * 16. tmp1.w = tmp0.w + src2 = r + src2
2496 *
2497 * endif
2498 *
2499 * 17. tmp1.x = tmp1.x & tmp1.y
2500 *
2501 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2502 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2503 *
2504 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2505 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2506 *
2507 * Signed path:
2508 *
2509 * Same as unsigned, using abs values of the operands,
2510 * and fixing the sign of the result in the end.
2511 */
2512
2513 for (i = 0; i < 4; i++) {
2514 if (!(write_mask & (1<<i)))
2515 continue;
2516
2517 if (signed_op) {
2518
2519 /* tmp2.x = -src0 */
2520 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2521 alu.op = ALU_OP2_SUB_INT;
2522
2523 alu.dst.sel = tmp2;
2524 alu.dst.chan = 0;
2525 alu.dst.write = 1;
2526
2527 alu.src[0].sel = V_SQ_ALU_SRC_0;
2528
2529 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2530
2531 alu.last = 1;
2532 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2533 return r;
2534
2535 /* tmp2.y = -src1 */
2536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2537 alu.op = ALU_OP2_SUB_INT;
2538
2539 alu.dst.sel = tmp2;
2540 alu.dst.chan = 1;
2541 alu.dst.write = 1;
2542
2543 alu.src[0].sel = V_SQ_ALU_SRC_0;
2544
2545 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2546
2547 alu.last = 1;
2548 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2549 return r;
2550
2551 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2552 /* it will be a sign of the quotient */
2553 if (!mod) {
2554
2555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2556 alu.op = ALU_OP2_XOR_INT;
2557
2558 alu.dst.sel = tmp2;
2559 alu.dst.chan = 2;
2560 alu.dst.write = 1;
2561
2562 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2563 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2564
2565 alu.last = 1;
2566 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2567 return r;
2568 }
2569
2570 /* tmp2.x = |src0| */
2571 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2572 alu.op = ALU_OP3_CNDGE_INT;
2573 alu.is_op3 = 1;
2574
2575 alu.dst.sel = tmp2;
2576 alu.dst.chan = 0;
2577 alu.dst.write = 1;
2578
2579 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2580 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2581 alu.src[2].sel = tmp2;
2582 alu.src[2].chan = 0;
2583
2584 alu.last = 1;
2585 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2586 return r;
2587
2588 /* tmp2.y = |src1| */
2589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2590 alu.op = ALU_OP3_CNDGE_INT;
2591 alu.is_op3 = 1;
2592
2593 alu.dst.sel = tmp2;
2594 alu.dst.chan = 1;
2595 alu.dst.write = 1;
2596
2597 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2598 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2599 alu.src[2].sel = tmp2;
2600 alu.src[2].chan = 1;
2601
2602 alu.last = 1;
2603 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2604 return r;
2605
2606 }
2607
2608 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2609 if (ctx->bc->chip_class == CAYMAN) {
2610 /* tmp3.x = u2f(src2) */
2611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2612 alu.op = ALU_OP1_UINT_TO_FLT;
2613
2614 alu.dst.sel = tmp3;
2615 alu.dst.chan = 0;
2616 alu.dst.write = 1;
2617
2618 if (signed_op) {
2619 alu.src[0].sel = tmp2;
2620 alu.src[0].chan = 1;
2621 } else {
2622 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2623 }
2624
2625 alu.last = 1;
2626 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2627 return r;
2628
2629 /* tmp0.x = recip(tmp3.x) */
2630 for (j = 0 ; j < 3; j++) {
2631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2632 alu.op = ALU_OP1_RECIP_IEEE;
2633
2634 alu.dst.sel = tmp0;
2635 alu.dst.chan = j;
2636 alu.dst.write = (j == 0);
2637
2638 alu.src[0].sel = tmp3;
2639 alu.src[0].chan = 0;
2640
2641 if (j == 2)
2642 alu.last = 1;
2643 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2644 return r;
2645 }
2646
2647 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2648 alu.op = ALU_OP2_MUL;
2649
2650 alu.src[0].sel = tmp0;
2651 alu.src[0].chan = 0;
2652
2653 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2654 alu.src[1].value = 0x4f800000;
2655
2656 alu.dst.sel = tmp3;
2657 alu.dst.write = 1;
2658 alu.last = 1;
2659 r = r600_bytecode_add_alu(ctx->bc, &alu);
2660 if (r)
2661 return r;
2662
2663 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2664 alu.op = ALU_OP1_FLT_TO_UINT;
2665
2666 alu.dst.sel = tmp0;
2667 alu.dst.chan = 0;
2668 alu.dst.write = 1;
2669
2670 alu.src[0].sel = tmp3;
2671 alu.src[0].chan = 0;
2672
2673 alu.last = 1;
2674 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2675 return r;
2676
2677 } else {
2678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2679 alu.op = ALU_OP1_RECIP_UINT;
2680
2681 alu.dst.sel = tmp0;
2682 alu.dst.chan = 0;
2683 alu.dst.write = 1;
2684
2685 if (signed_op) {
2686 alu.src[0].sel = tmp2;
2687 alu.src[0].chan = 1;
2688 } else {
2689 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2690 }
2691
2692 alu.last = 1;
2693 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2694 return r;
2695 }
2696
2697 /* 2. tmp0.z = lo (tmp0.x * src2) */
2698 if (ctx->bc->chip_class == CAYMAN) {
2699 for (j = 0 ; j < 4; j++) {
2700 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2701 alu.op = ALU_OP2_MULLO_UINT;
2702
2703 alu.dst.sel = tmp0;
2704 alu.dst.chan = j;
2705 alu.dst.write = (j == 2);
2706
2707 alu.src[0].sel = tmp0;
2708 alu.src[0].chan = 0;
2709 if (signed_op) {
2710 alu.src[1].sel = tmp2;
2711 alu.src[1].chan = 1;
2712 } else {
2713 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2714 }
2715
2716 alu.last = (j == 3);
2717 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2718 return r;
2719 }
2720 } else {
2721 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2722 alu.op = ALU_OP2_MULLO_UINT;
2723
2724 alu.dst.sel = tmp0;
2725 alu.dst.chan = 2;
2726 alu.dst.write = 1;
2727
2728 alu.src[0].sel = tmp0;
2729 alu.src[0].chan = 0;
2730 if (signed_op) {
2731 alu.src[1].sel = tmp2;
2732 alu.src[1].chan = 1;
2733 } else {
2734 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2735 }
2736
2737 alu.last = 1;
2738 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2739 return r;
2740 }
2741
2742 /* 3. tmp0.w = -tmp0.z */
2743 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2744 alu.op = ALU_OP2_SUB_INT;
2745
2746 alu.dst.sel = tmp0;
2747 alu.dst.chan = 3;
2748 alu.dst.write = 1;
2749
2750 alu.src[0].sel = V_SQ_ALU_SRC_0;
2751 alu.src[1].sel = tmp0;
2752 alu.src[1].chan = 2;
2753
2754 alu.last = 1;
2755 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2756 return r;
2757
2758 /* 4. tmp0.y = hi (tmp0.x * src2) */
2759 if (ctx->bc->chip_class == CAYMAN) {
2760 for (j = 0 ; j < 4; j++) {
2761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2762 alu.op = ALU_OP2_MULHI_UINT;
2763
2764 alu.dst.sel = tmp0;
2765 alu.dst.chan = j;
2766 alu.dst.write = (j == 1);
2767
2768 alu.src[0].sel = tmp0;
2769 alu.src[0].chan = 0;
2770
2771 if (signed_op) {
2772 alu.src[1].sel = tmp2;
2773 alu.src[1].chan = 1;
2774 } else {
2775 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2776 }
2777 alu.last = (j == 3);
2778 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2779 return r;
2780 }
2781 } else {
2782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2783 alu.op = ALU_OP2_MULHI_UINT;
2784
2785 alu.dst.sel = tmp0;
2786 alu.dst.chan = 1;
2787 alu.dst.write = 1;
2788
2789 alu.src[0].sel = tmp0;
2790 alu.src[0].chan = 0;
2791
2792 if (signed_op) {
2793 alu.src[1].sel = tmp2;
2794 alu.src[1].chan = 1;
2795 } else {
2796 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2797 }
2798
2799 alu.last = 1;
2800 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2801 return r;
2802 }
2803
2804 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2806 alu.op = ALU_OP3_CNDE_INT;
2807 alu.is_op3 = 1;
2808
2809 alu.dst.sel = tmp0;
2810 alu.dst.chan = 2;
2811 alu.dst.write = 1;
2812
2813 alu.src[0].sel = tmp0;
2814 alu.src[0].chan = 1;
2815 alu.src[1].sel = tmp0;
2816 alu.src[1].chan = 3;
2817 alu.src[2].sel = tmp0;
2818 alu.src[2].chan = 2;
2819
2820 alu.last = 1;
2821 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2822 return r;
2823
2824 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2825 if (ctx->bc->chip_class == CAYMAN) {
2826 for (j = 0 ; j < 4; j++) {
2827 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2828 alu.op = ALU_OP2_MULHI_UINT;
2829
2830 alu.dst.sel = tmp0;
2831 alu.dst.chan = j;
2832 alu.dst.write = (j == 3);
2833
2834 alu.src[0].sel = tmp0;
2835 alu.src[0].chan = 2;
2836
2837 alu.src[1].sel = tmp0;
2838 alu.src[1].chan = 0;
2839
2840 alu.last = (j == 3);
2841 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2842 return r;
2843 }
2844 } else {
2845 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2846 alu.op = ALU_OP2_MULHI_UINT;
2847
2848 alu.dst.sel = tmp0;
2849 alu.dst.chan = 3;
2850 alu.dst.write = 1;
2851
2852 alu.src[0].sel = tmp0;
2853 alu.src[0].chan = 2;
2854
2855 alu.src[1].sel = tmp0;
2856 alu.src[1].chan = 0;
2857
2858 alu.last = 1;
2859 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2860 return r;
2861 }
2862
2863 /* 7. tmp1.x = tmp0.x - tmp0.w */
2864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2865 alu.op = ALU_OP2_SUB_INT;
2866
2867 alu.dst.sel = tmp1;
2868 alu.dst.chan = 0;
2869 alu.dst.write = 1;
2870
2871 alu.src[0].sel = tmp0;
2872 alu.src[0].chan = 0;
2873 alu.src[1].sel = tmp0;
2874 alu.src[1].chan = 3;
2875
2876 alu.last = 1;
2877 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2878 return r;
2879
2880 /* 8. tmp1.y = tmp0.x + tmp0.w */
2881 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2882 alu.op = ALU_OP2_ADD_INT;
2883
2884 alu.dst.sel = tmp1;
2885 alu.dst.chan = 1;
2886 alu.dst.write = 1;
2887
2888 alu.src[0].sel = tmp0;
2889 alu.src[0].chan = 0;
2890 alu.src[1].sel = tmp0;
2891 alu.src[1].chan = 3;
2892
2893 alu.last = 1;
2894 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2895 return r;
2896
2897 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2898 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2899 alu.op = ALU_OP3_CNDE_INT;
2900 alu.is_op3 = 1;
2901
2902 alu.dst.sel = tmp0;
2903 alu.dst.chan = 0;
2904 alu.dst.write = 1;
2905
2906 alu.src[0].sel = tmp0;
2907 alu.src[0].chan = 1;
2908 alu.src[1].sel = tmp1;
2909 alu.src[1].chan = 1;
2910 alu.src[2].sel = tmp1;
2911 alu.src[2].chan = 0;
2912
2913 alu.last = 1;
2914 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2915 return r;
2916
2917 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2918 if (ctx->bc->chip_class == CAYMAN) {
2919 for (j = 0 ; j < 4; j++) {
2920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2921 alu.op = ALU_OP2_MULHI_UINT;
2922
2923 alu.dst.sel = tmp0;
2924 alu.dst.chan = j;
2925 alu.dst.write = (j == 2);
2926
2927 alu.src[0].sel = tmp0;
2928 alu.src[0].chan = 0;
2929
2930 if (signed_op) {
2931 alu.src[1].sel = tmp2;
2932 alu.src[1].chan = 0;
2933 } else {
2934 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2935 }
2936
2937 alu.last = (j == 3);
2938 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2939 return r;
2940 }
2941 } else {
2942 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2943 alu.op = ALU_OP2_MULHI_UINT;
2944
2945 alu.dst.sel = tmp0;
2946 alu.dst.chan = 2;
2947 alu.dst.write = 1;
2948
2949 alu.src[0].sel = tmp0;
2950 alu.src[0].chan = 0;
2951
2952 if (signed_op) {
2953 alu.src[1].sel = tmp2;
2954 alu.src[1].chan = 0;
2955 } else {
2956 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2957 }
2958
2959 alu.last = 1;
2960 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2961 return r;
2962 }
2963
2964 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
2965 if (ctx->bc->chip_class == CAYMAN) {
2966 for (j = 0 ; j < 4; j++) {
2967 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2968 alu.op = ALU_OP2_MULLO_UINT;
2969
2970 alu.dst.sel = tmp0;
2971 alu.dst.chan = j;
2972 alu.dst.write = (j == 1);
2973
2974 if (signed_op) {
2975 alu.src[0].sel = tmp2;
2976 alu.src[0].chan = 1;
2977 } else {
2978 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2979 }
2980
2981 alu.src[1].sel = tmp0;
2982 alu.src[1].chan = 2;
2983
2984 alu.last = (j == 3);
2985 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2986 return r;
2987 }
2988 } else {
2989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2990 alu.op = ALU_OP2_MULLO_UINT;
2991
2992 alu.dst.sel = tmp0;
2993 alu.dst.chan = 1;
2994 alu.dst.write = 1;
2995
2996 if (signed_op) {
2997 alu.src[0].sel = tmp2;
2998 alu.src[0].chan = 1;
2999 } else {
3000 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3001 }
3002
3003 alu.src[1].sel = tmp0;
3004 alu.src[1].chan = 2;
3005
3006 alu.last = 1;
3007 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3008 return r;
3009 }
3010
3011 /* 12. tmp0.w = src1 - tmp0.y = r */
3012 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3013 alu.op = ALU_OP2_SUB_INT;
3014
3015 alu.dst.sel = tmp0;
3016 alu.dst.chan = 3;
3017 alu.dst.write = 1;
3018
3019 if (signed_op) {
3020 alu.src[0].sel = tmp2;
3021 alu.src[0].chan = 0;
3022 } else {
3023 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3024 }
3025
3026 alu.src[1].sel = tmp0;
3027 alu.src[1].chan = 1;
3028
3029 alu.last = 1;
3030 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3031 return r;
3032
3033 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3034 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3035 alu.op = ALU_OP2_SETGE_UINT;
3036
3037 alu.dst.sel = tmp1;
3038 alu.dst.chan = 0;
3039 alu.dst.write = 1;
3040
3041 alu.src[0].sel = tmp0;
3042 alu.src[0].chan = 3;
3043 if (signed_op) {
3044 alu.src[1].sel = tmp2;
3045 alu.src[1].chan = 1;
3046 } else {
3047 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3048 }
3049
3050 alu.last = 1;
3051 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3052 return r;
3053
3054 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3055 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3056 alu.op = ALU_OP2_SETGE_UINT;
3057
3058 alu.dst.sel = tmp1;
3059 alu.dst.chan = 1;
3060 alu.dst.write = 1;
3061
3062 if (signed_op) {
3063 alu.src[0].sel = tmp2;
3064 alu.src[0].chan = 0;
3065 } else {
3066 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3067 }
3068
3069 alu.src[1].sel = tmp0;
3070 alu.src[1].chan = 1;
3071
3072 alu.last = 1;
3073 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3074 return r;
3075
3076 if (mod) { /* UMOD */
3077
3078 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3079 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3080 alu.op = ALU_OP2_SUB_INT;
3081
3082 alu.dst.sel = tmp1;
3083 alu.dst.chan = 2;
3084 alu.dst.write = 1;
3085
3086 alu.src[0].sel = tmp0;
3087 alu.src[0].chan = 3;
3088
3089 if (signed_op) {
3090 alu.src[1].sel = tmp2;
3091 alu.src[1].chan = 1;
3092 } else {
3093 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3094 }
3095
3096 alu.last = 1;
3097 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3098 return r;
3099
3100 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3101 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3102 alu.op = ALU_OP2_ADD_INT;
3103
3104 alu.dst.sel = tmp1;
3105 alu.dst.chan = 3;
3106 alu.dst.write = 1;
3107
3108 alu.src[0].sel = tmp0;
3109 alu.src[0].chan = 3;
3110 if (signed_op) {
3111 alu.src[1].sel = tmp2;
3112 alu.src[1].chan = 1;
3113 } else {
3114 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3115 }
3116
3117 alu.last = 1;
3118 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3119 return r;
3120
3121 } else { /* UDIV */
3122
3123 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3124 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3125 alu.op = ALU_OP2_ADD_INT;
3126
3127 alu.dst.sel = tmp1;
3128 alu.dst.chan = 2;
3129 alu.dst.write = 1;
3130
3131 alu.src[0].sel = tmp0;
3132 alu.src[0].chan = 2;
3133 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3134
3135 alu.last = 1;
3136 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3137 return r;
3138
3139 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3140 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3141 alu.op = ALU_OP2_ADD_INT;
3142
3143 alu.dst.sel = tmp1;
3144 alu.dst.chan = 3;
3145 alu.dst.write = 1;
3146
3147 alu.src[0].sel = tmp0;
3148 alu.src[0].chan = 2;
3149 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3150
3151 alu.last = 1;
3152 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3153 return r;
3154
3155 }
3156
3157 /* 17. tmp1.x = tmp1.x & tmp1.y */
3158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3159 alu.op = ALU_OP2_AND_INT;
3160
3161 alu.dst.sel = tmp1;
3162 alu.dst.chan = 0;
3163 alu.dst.write = 1;
3164
3165 alu.src[0].sel = tmp1;
3166 alu.src[0].chan = 0;
3167 alu.src[1].sel = tmp1;
3168 alu.src[1].chan = 1;
3169
3170 alu.last = 1;
3171 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3172 return r;
3173
3174 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3175 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3176 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3177 alu.op = ALU_OP3_CNDE_INT;
3178 alu.is_op3 = 1;
3179
3180 alu.dst.sel = tmp0;
3181 alu.dst.chan = 2;
3182 alu.dst.write = 1;
3183
3184 alu.src[0].sel = tmp1;
3185 alu.src[0].chan = 0;
3186 alu.src[1].sel = tmp0;
3187 alu.src[1].chan = mod ? 3 : 2;
3188 alu.src[2].sel = tmp1;
3189 alu.src[2].chan = 2;
3190
3191 alu.last = 1;
3192 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3193 return r;
3194
3195 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3196 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3197 alu.op = ALU_OP3_CNDE_INT;
3198 alu.is_op3 = 1;
3199
3200 if (signed_op) {
3201 alu.dst.sel = tmp0;
3202 alu.dst.chan = 2;
3203 alu.dst.write = 1;
3204 } else {
3205 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3206 }
3207
3208 alu.src[0].sel = tmp1;
3209 alu.src[0].chan = 1;
3210 alu.src[1].sel = tmp1;
3211 alu.src[1].chan = 3;
3212 alu.src[2].sel = tmp0;
3213 alu.src[2].chan = 2;
3214
3215 alu.last = 1;
3216 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3217 return r;
3218
3219 if (signed_op) {
3220
3221 /* fix the sign of the result */
3222
3223 if (mod) {
3224
3225 /* tmp0.x = -tmp0.z */
3226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3227 alu.op = ALU_OP2_SUB_INT;
3228
3229 alu.dst.sel = tmp0;
3230 alu.dst.chan = 0;
3231 alu.dst.write = 1;
3232
3233 alu.src[0].sel = V_SQ_ALU_SRC_0;
3234 alu.src[1].sel = tmp0;
3235 alu.src[1].chan = 2;
3236
3237 alu.last = 1;
3238 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3239 return r;
3240
3241 /* sign of the remainder is the same as the sign of src0 */
3242 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3243 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3244 alu.op = ALU_OP3_CNDGE_INT;
3245 alu.is_op3 = 1;
3246
3247 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3248
3249 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3250 alu.src[1].sel = tmp0;
3251 alu.src[1].chan = 2;
3252 alu.src[2].sel = tmp0;
3253 alu.src[2].chan = 0;
3254
3255 alu.last = 1;
3256 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3257 return r;
3258
3259 } else {
3260
3261 /* tmp0.x = -tmp0.z */
3262 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3263 alu.op = ALU_OP2_SUB_INT;
3264
3265 alu.dst.sel = tmp0;
3266 alu.dst.chan = 0;
3267 alu.dst.write = 1;
3268
3269 alu.src[0].sel = V_SQ_ALU_SRC_0;
3270 alu.src[1].sel = tmp0;
3271 alu.src[1].chan = 2;
3272
3273 alu.last = 1;
3274 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3275 return r;
3276
3277 /* fix the quotient sign (same as the sign of src0*src1) */
3278 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3279 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3280 alu.op = ALU_OP3_CNDGE_INT;
3281 alu.is_op3 = 1;
3282
3283 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3284
3285 alu.src[0].sel = tmp2;
3286 alu.src[0].chan = 2;
3287 alu.src[1].sel = tmp0;
3288 alu.src[1].chan = 2;
3289 alu.src[2].sel = tmp0;
3290 alu.src[2].chan = 0;
3291
3292 alu.last = 1;
3293 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3294 return r;
3295 }
3296 }
3297 }
3298 return 0;
3299 }
3300
3301 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3302 {
3303 return tgsi_divmod(ctx, 0, 0);
3304 }
3305
3306 static int tgsi_umod(struct r600_shader_ctx *ctx)
3307 {
3308 return tgsi_divmod(ctx, 1, 0);
3309 }
3310
3311 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3312 {
3313 return tgsi_divmod(ctx, 0, 1);
3314 }
3315
3316 static int tgsi_imod(struct r600_shader_ctx *ctx)
3317 {
3318 return tgsi_divmod(ctx, 1, 1);
3319 }
3320
3321
3322 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3323 {
3324 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3325 struct r600_bytecode_alu alu;
3326 int i, r;
3327 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3328 int last_inst = tgsi_last_instruction(write_mask);
3329
3330 for (i = 0; i < 4; i++) {
3331 if (!(write_mask & (1<<i)))
3332 continue;
3333
3334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3335 alu.op = ALU_OP1_TRUNC;
3336
3337 alu.dst.sel = ctx->temp_reg;
3338 alu.dst.chan = i;
3339 alu.dst.write = 1;
3340
3341 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3342 if (i == last_inst)
3343 alu.last = 1;
3344 r = r600_bytecode_add_alu(ctx->bc, &alu);
3345 if (r)
3346 return r;
3347 }
3348
3349 for (i = 0; i < 4; i++) {
3350 if (!(write_mask & (1<<i)))
3351 continue;
3352
3353 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3354 alu.op = ctx->inst_info->op;
3355
3356 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3357
3358 alu.src[0].sel = ctx->temp_reg;
3359 alu.src[0].chan = i;
3360
3361 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3362 alu.last = 1;
3363 r = r600_bytecode_add_alu(ctx->bc, &alu);
3364 if (r)
3365 return r;
3366 }
3367
3368 return 0;
3369 }
3370
3371 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3372 {
3373 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3374 struct r600_bytecode_alu alu;
3375 int i, r;
3376 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3377 int last_inst = tgsi_last_instruction(write_mask);
3378
3379 /* tmp = -src */
3380 for (i = 0; i < 4; i++) {
3381 if (!(write_mask & (1<<i)))
3382 continue;
3383
3384 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3385 alu.op = ALU_OP2_SUB_INT;
3386
3387 alu.dst.sel = ctx->temp_reg;
3388 alu.dst.chan = i;
3389 alu.dst.write = 1;
3390
3391 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3392 alu.src[0].sel = V_SQ_ALU_SRC_0;
3393
3394 if (i == last_inst)
3395 alu.last = 1;
3396 r = r600_bytecode_add_alu(ctx->bc, &alu);
3397 if (r)
3398 return r;
3399 }
3400
3401 /* dst = (src >= 0 ? src : tmp) */
3402 for (i = 0; i < 4; i++) {
3403 if (!(write_mask & (1<<i)))
3404 continue;
3405
3406 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3407 alu.op = ALU_OP3_CNDGE_INT;
3408 alu.is_op3 = 1;
3409 alu.dst.write = 1;
3410
3411 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3412
3413 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3414 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3415 alu.src[2].sel = ctx->temp_reg;
3416 alu.src[2].chan = i;
3417
3418 if (i == last_inst)
3419 alu.last = 1;
3420 r = r600_bytecode_add_alu(ctx->bc, &alu);
3421 if (r)
3422 return r;
3423 }
3424 return 0;
3425 }
3426
3427 static int tgsi_issg(struct r600_shader_ctx *ctx)
3428 {
3429 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3430 struct r600_bytecode_alu alu;
3431 int i, r;
3432 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3433 int last_inst = tgsi_last_instruction(write_mask);
3434
3435 /* tmp = (src >= 0 ? src : -1) */
3436 for (i = 0; i < 4; i++) {
3437 if (!(write_mask & (1<<i)))
3438 continue;
3439
3440 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3441 alu.op = ALU_OP3_CNDGE_INT;
3442 alu.is_op3 = 1;
3443
3444 alu.dst.sel = ctx->temp_reg;
3445 alu.dst.chan = i;
3446 alu.dst.write = 1;
3447
3448 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3449 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3450 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3451
3452 if (i == last_inst)
3453 alu.last = 1;
3454 r = r600_bytecode_add_alu(ctx->bc, &alu);
3455 if (r)
3456 return r;
3457 }
3458
3459 /* dst = (tmp > 0 ? 1 : tmp) */
3460 for (i = 0; i < 4; i++) {
3461 if (!(write_mask & (1<<i)))
3462 continue;
3463
3464 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3465 alu.op = ALU_OP3_CNDGT_INT;
3466 alu.is_op3 = 1;
3467 alu.dst.write = 1;
3468
3469 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3470
3471 alu.src[0].sel = ctx->temp_reg;
3472 alu.src[0].chan = i;
3473
3474 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3475
3476 alu.src[2].sel = ctx->temp_reg;
3477 alu.src[2].chan = i;
3478
3479 if (i == last_inst)
3480 alu.last = 1;
3481 r = r600_bytecode_add_alu(ctx->bc, &alu);
3482 if (r)
3483 return r;
3484 }
3485 return 0;
3486 }
3487
3488
3489
3490 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3491 {
3492 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3493 struct r600_bytecode_alu alu;
3494 int i, r;
3495
3496 /* tmp = (src > 0 ? 1 : src) */
3497 for (i = 0; i < 4; i++) {
3498 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3499 alu.op = ALU_OP3_CNDGT;
3500 alu.is_op3 = 1;
3501
3502 alu.dst.sel = ctx->temp_reg;
3503 alu.dst.chan = i;
3504
3505 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3506 alu.src[1].sel = V_SQ_ALU_SRC_1;
3507 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3508
3509 if (i == 3)
3510 alu.last = 1;
3511 r = r600_bytecode_add_alu(ctx->bc, &alu);
3512 if (r)
3513 return r;
3514 }
3515
3516 /* dst = (-tmp > 0 ? -1 : tmp) */
3517 for (i = 0; i < 4; i++) {
3518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3519 alu.op = ALU_OP3_CNDGT;
3520 alu.is_op3 = 1;
3521 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3522
3523 alu.src[0].sel = ctx->temp_reg;
3524 alu.src[0].chan = i;
3525 alu.src[0].neg = 1;
3526
3527 alu.src[1].sel = V_SQ_ALU_SRC_1;
3528 alu.src[1].neg = 1;
3529
3530 alu.src[2].sel = ctx->temp_reg;
3531 alu.src[2].chan = i;
3532
3533 if (i == 3)
3534 alu.last = 1;
3535 r = r600_bytecode_add_alu(ctx->bc, &alu);
3536 if (r)
3537 return r;
3538 }
3539 return 0;
3540 }
3541
3542 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3543 {
3544 struct r600_bytecode_alu alu;
3545 int i, r;
3546
3547 for (i = 0; i < 4; i++) {
3548 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3549 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3550 alu.op = ALU_OP0_NOP;
3551 alu.dst.chan = i;
3552 } else {
3553 alu.op = ALU_OP1_MOV;
3554 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3555 alu.src[0].sel = ctx->temp_reg;
3556 alu.src[0].chan = i;
3557 }
3558 if (i == 3) {
3559 alu.last = 1;
3560 }
3561 r = r600_bytecode_add_alu(ctx->bc, &alu);
3562 if (r)
3563 return r;
3564 }
3565 return 0;
3566 }
3567
3568 static int tgsi_op3(struct r600_shader_ctx *ctx)
3569 {
3570 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3571 struct r600_bytecode_alu alu;
3572 int i, j, r;
3573 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3574
3575 for (i = 0; i < lasti + 1; i++) {
3576 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3577 continue;
3578
3579 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3580 alu.op = ctx->inst_info->op;
3581 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3582 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3583 }
3584
3585 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3586 alu.dst.chan = i;
3587 alu.dst.write = 1;
3588 alu.is_op3 = 1;
3589 if (i == lasti) {
3590 alu.last = 1;
3591 }
3592 r = r600_bytecode_add_alu(ctx->bc, &alu);
3593 if (r)
3594 return r;
3595 }
3596 return 0;
3597 }
3598
3599 static int tgsi_dp(struct r600_shader_ctx *ctx)
3600 {
3601 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3602 struct r600_bytecode_alu alu;
3603 int i, j, r;
3604
3605 for (i = 0; i < 4; i++) {
3606 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3607 alu.op = ctx->inst_info->op;
3608 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3609 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3610 }
3611
3612 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3613 alu.dst.chan = i;
3614 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3615 /* handle some special cases */
3616 switch (ctx->inst_info->tgsi_opcode) {
3617 case TGSI_OPCODE_DP2:
3618 if (i > 1) {
3619 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3620 alu.src[0].chan = alu.src[1].chan = 0;
3621 }
3622 break;
3623 case TGSI_OPCODE_DP3:
3624 if (i > 2) {
3625 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3626 alu.src[0].chan = alu.src[1].chan = 0;
3627 }
3628 break;
3629 case TGSI_OPCODE_DPH:
3630 if (i == 3) {
3631 alu.src[0].sel = V_SQ_ALU_SRC_1;
3632 alu.src[0].chan = 0;
3633 alu.src[0].neg = 0;
3634 }
3635 break;
3636 default:
3637 break;
3638 }
3639 if (i == 3) {
3640 alu.last = 1;
3641 }
3642 r = r600_bytecode_add_alu(ctx->bc, &alu);
3643 if (r)
3644 return r;
3645 }
3646 return 0;
3647 }
3648
3649 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3650 unsigned index)
3651 {
3652 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3653 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3654 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3655 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3656 ctx->src[index].neg || ctx->src[index].abs;
3657 }
3658
3659 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3660 unsigned index)
3661 {
3662 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3663 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3664 }
3665
3666 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
3667 {
3668 struct r600_bytecode_vtx vtx;
3669 struct r600_bytecode_alu alu;
3670 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3671 int src_gpr, r, i;
3672 int id = tgsi_tex_get_src_gpr(ctx, 1);
3673
3674 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3675 if (src_requires_loading) {
3676 for (i = 0; i < 4; i++) {
3677 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3678 alu.op = ALU_OP1_MOV;
3679 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3680 alu.dst.sel = ctx->temp_reg;
3681 alu.dst.chan = i;
3682 if (i == 3)
3683 alu.last = 1;
3684 alu.dst.write = 1;
3685 r = r600_bytecode_add_alu(ctx->bc, &alu);
3686 if (r)
3687 return r;
3688 }
3689 src_gpr = ctx->temp_reg;
3690 }
3691
3692 memset(&vtx, 0, sizeof(vtx));
3693 vtx.op = FETCH_OP_VFETCH;
3694 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
3695 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
3696 vtx.src_gpr = src_gpr;
3697 vtx.mega_fetch_count = 16;
3698 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3699 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
3700 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
3701 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
3702 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
3703 vtx.use_const_fields = 1;
3704 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
3705
3706 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
3707 return r;
3708
3709 if (ctx->bc->chip_class >= EVERGREEN)
3710 return 0;
3711
3712 for (i = 0; i < 4; i++) {
3713 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3714 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3715 continue;
3716
3717 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3718 alu.op = ALU_OP2_AND_INT;
3719
3720 alu.dst.chan = i;
3721 alu.dst.sel = vtx.dst_gpr;
3722 alu.dst.write = 1;
3723
3724 alu.src[0].sel = vtx.dst_gpr;
3725 alu.src[0].chan = i;
3726
3727 alu.src[1].sel = 512 + (id * 2);
3728 alu.src[1].chan = i % 4;
3729 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3730
3731 if (i == lasti)
3732 alu.last = 1;
3733 r = r600_bytecode_add_alu(ctx->bc, &alu);
3734 if (r)
3735 return r;
3736 }
3737
3738 if (inst->Dst[0].Register.WriteMask & 3) {
3739 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3740 alu.op = ALU_OP2_OR_INT;
3741
3742 alu.dst.chan = 3;
3743 alu.dst.sel = vtx.dst_gpr;
3744 alu.dst.write = 1;
3745
3746 alu.src[0].sel = vtx.dst_gpr;
3747 alu.src[0].chan = 3;
3748
3749 alu.src[1].sel = 512 + (id * 2) + 1;
3750 alu.src[1].chan = 0;
3751 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3752
3753 alu.last = 1;
3754 r = r600_bytecode_add_alu(ctx->bc, &alu);
3755 if (r)
3756 return r;
3757 }
3758 return 0;
3759 }
3760
3761 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
3762 {
3763 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3764 struct r600_bytecode_alu alu;
3765 int r;
3766 int id = tgsi_tex_get_src_gpr(ctx, 1);
3767
3768 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3769 alu.op = ALU_OP1_MOV;
3770
3771 if (ctx->bc->chip_class >= EVERGREEN) {
3772 alu.src[0].sel = 512 + (id / 4);
3773 alu.src[0].chan = id % 4;
3774 } else {
3775 /* r600 we have them at channel 2 of the second dword */
3776 alu.src[0].sel = 512 + (id * 2) + 1;
3777 alu.src[0].chan = 1;
3778 }
3779 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3780 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3781 alu.last = 1;
3782 r = r600_bytecode_add_alu(ctx->bc, &alu);
3783 if (r)
3784 return r;
3785 return 0;
3786 }
3787
3788 static int tgsi_tex(struct r600_shader_ctx *ctx)
3789 {
3790 static float one_point_five = 1.5f;
3791 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3792 struct r600_bytecode_tex tex;
3793 struct r600_bytecode_alu alu;
3794 unsigned src_gpr;
3795 int r, i, j;
3796 int opcode;
3797 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
3798 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
3799 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
3800 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
3801
3802 /* Texture fetch instructions can only use gprs as source.
3803 * Also they cannot negate the source or take the absolute value */
3804 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
3805 tgsi_tex_src_requires_loading(ctx, 0)) ||
3806 read_compressed_msaa;
3807 boolean src_loaded = FALSE;
3808 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
3809 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
3810 boolean has_txq_cube_array_z = false;
3811
3812 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
3813 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3814 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
3815 if (inst->Dst[0].Register.WriteMask & 4) {
3816 ctx->shader->has_txq_cube_array_z_comp = true;
3817 has_txq_cube_array_z = true;
3818 }
3819
3820 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
3821 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
3822 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
3823 sampler_src_reg = 2;
3824
3825 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3826
3827 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
3828 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
3829 ctx->shader->uses_tex_buffers = true;
3830 return r600_do_buffer_txq(ctx);
3831 }
3832 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3833 if (ctx->bc->chip_class < EVERGREEN)
3834 ctx->shader->uses_tex_buffers = true;
3835 return do_vtx_fetch_inst(ctx, src_requires_loading);
3836 }
3837 }
3838
3839 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3840 /* get offset values */
3841 if (inst->Texture.NumOffsets) {
3842 assert(inst->Texture.NumOffsets == 1);
3843
3844 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
3845 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
3846 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
3847 }
3848 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3849 /* TGSI moves the sampler to src reg 3 for TXD */
3850 sampler_src_reg = 3;
3851
3852 for (i = 1; i < 3; i++) {
3853 /* set gradients h/v */
3854 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3855 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
3856 FETCH_OP_SET_GRADIENTS_V;
3857 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3858 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3859
3860 if (tgsi_tex_src_requires_loading(ctx, i)) {
3861 tex.src_gpr = r600_get_temp(ctx);
3862 tex.src_sel_x = 0;
3863 tex.src_sel_y = 1;
3864 tex.src_sel_z = 2;
3865 tex.src_sel_w = 3;
3866
3867 for (j = 0; j < 4; j++) {
3868 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3869 alu.op = ALU_OP1_MOV;
3870 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
3871 alu.dst.sel = tex.src_gpr;
3872 alu.dst.chan = j;
3873 if (j == 3)
3874 alu.last = 1;
3875 alu.dst.write = 1;
3876 r = r600_bytecode_add_alu(ctx->bc, &alu);
3877 if (r)
3878 return r;
3879 }
3880
3881 } else {
3882 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
3883 tex.src_sel_x = ctx->src[i].swizzle[0];
3884 tex.src_sel_y = ctx->src[i].swizzle[1];
3885 tex.src_sel_z = ctx->src[i].swizzle[2];
3886 tex.src_sel_w = ctx->src[i].swizzle[3];
3887 tex.src_rel = ctx->src[i].rel;
3888 }
3889 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
3890 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
3891 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
3892 tex.coord_type_x = 1;
3893 tex.coord_type_y = 1;
3894 tex.coord_type_z = 1;
3895 tex.coord_type_w = 1;
3896 }
3897 r = r600_bytecode_add_tex(ctx->bc, &tex);
3898 if (r)
3899 return r;
3900 }
3901 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3902 int out_chan;
3903 /* Add perspective divide */
3904 if (ctx->bc->chip_class == CAYMAN) {
3905 out_chan = 2;
3906 for (i = 0; i < 3; i++) {
3907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3908 alu.op = ALU_OP1_RECIP_IEEE;
3909 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3910
3911 alu.dst.sel = ctx->temp_reg;
3912 alu.dst.chan = i;
3913 if (i == 2)
3914 alu.last = 1;
3915 if (out_chan == i)
3916 alu.dst.write = 1;
3917 r = r600_bytecode_add_alu(ctx->bc, &alu);
3918 if (r)
3919 return r;
3920 }
3921
3922 } else {
3923 out_chan = 3;
3924 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3925 alu.op = ALU_OP1_RECIP_IEEE;
3926 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3927
3928 alu.dst.sel = ctx->temp_reg;
3929 alu.dst.chan = out_chan;
3930 alu.last = 1;
3931 alu.dst.write = 1;
3932 r = r600_bytecode_add_alu(ctx->bc, &alu);
3933 if (r)
3934 return r;
3935 }
3936
3937 for (i = 0; i < 3; i++) {
3938 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3939 alu.op = ALU_OP2_MUL;
3940 alu.src[0].sel = ctx->temp_reg;
3941 alu.src[0].chan = out_chan;
3942 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3943 alu.dst.sel = ctx->temp_reg;
3944 alu.dst.chan = i;
3945 alu.dst.write = 1;
3946 r = r600_bytecode_add_alu(ctx->bc, &alu);
3947 if (r)
3948 return r;
3949 }
3950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3951 alu.op = ALU_OP1_MOV;
3952 alu.src[0].sel = V_SQ_ALU_SRC_1;
3953 alu.src[0].chan = 0;
3954 alu.dst.sel = ctx->temp_reg;
3955 alu.dst.chan = 3;
3956 alu.last = 1;
3957 alu.dst.write = 1;
3958 r = r600_bytecode_add_alu(ctx->bc, &alu);
3959 if (r)
3960 return r;
3961 src_loaded = TRUE;
3962 src_gpr = ctx->temp_reg;
3963 }
3964
3965 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
3966 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3967 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
3968 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
3969 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
3970 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
3971
3972 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
3973 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
3974
3975 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3976 for (i = 0; i < 4; i++) {
3977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3978 alu.op = ALU_OP2_CUBE;
3979 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3980 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
3981 alu.dst.sel = ctx->temp_reg;
3982 alu.dst.chan = i;
3983 if (i == 3)
3984 alu.last = 1;
3985 alu.dst.write = 1;
3986 r = r600_bytecode_add_alu(ctx->bc, &alu);
3987 if (r)
3988 return r;
3989 }
3990
3991 /* tmp1.z = RCP_e(|tmp1.z|) */
3992 if (ctx->bc->chip_class == CAYMAN) {
3993 for (i = 0; i < 3; i++) {
3994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3995 alu.op = ALU_OP1_RECIP_IEEE;
3996 alu.src[0].sel = ctx->temp_reg;
3997 alu.src[0].chan = 2;
3998 alu.src[0].abs = 1;
3999 alu.dst.sel = ctx->temp_reg;
4000 alu.dst.chan = i;
4001 if (i == 2)
4002 alu.dst.write = 1;
4003 if (i == 2)
4004 alu.last = 1;
4005 r = r600_bytecode_add_alu(ctx->bc, &alu);
4006 if (r)
4007 return r;
4008 }
4009 } else {
4010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4011 alu.op = ALU_OP1_RECIP_IEEE;
4012 alu.src[0].sel = ctx->temp_reg;
4013 alu.src[0].chan = 2;
4014 alu.src[0].abs = 1;
4015 alu.dst.sel = ctx->temp_reg;
4016 alu.dst.chan = 2;
4017 alu.dst.write = 1;
4018 alu.last = 1;
4019 r = r600_bytecode_add_alu(ctx->bc, &alu);
4020 if (r)
4021 return r;
4022 }
4023
4024 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4025 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4026 * muladd has no writemask, have to use another temp
4027 */
4028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4029 alu.op = ALU_OP3_MULADD;
4030 alu.is_op3 = 1;
4031
4032 alu.src[0].sel = ctx->temp_reg;
4033 alu.src[0].chan = 0;
4034 alu.src[1].sel = ctx->temp_reg;
4035 alu.src[1].chan = 2;
4036
4037 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4038 alu.src[2].chan = 0;
4039 alu.src[2].value = *(uint32_t *)&one_point_five;
4040
4041 alu.dst.sel = ctx->temp_reg;
4042 alu.dst.chan = 0;
4043 alu.dst.write = 1;
4044
4045 r = r600_bytecode_add_alu(ctx->bc, &alu);
4046 if (r)
4047 return r;
4048
4049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4050 alu.op = ALU_OP3_MULADD;
4051 alu.is_op3 = 1;
4052
4053 alu.src[0].sel = ctx->temp_reg;
4054 alu.src[0].chan = 1;
4055 alu.src[1].sel = ctx->temp_reg;
4056 alu.src[1].chan = 2;
4057
4058 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4059 alu.src[2].chan = 0;
4060 alu.src[2].value = *(uint32_t *)&one_point_five;
4061
4062 alu.dst.sel = ctx->temp_reg;
4063 alu.dst.chan = 1;
4064 alu.dst.write = 1;
4065
4066 alu.last = 1;
4067 r = r600_bytecode_add_alu(ctx->bc, &alu);
4068 if (r)
4069 return r;
4070 /* write initial compare value into Z component
4071 - W src 0 for shadow cube
4072 - X src 1 for shadow cube array */
4073 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4074 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4075 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4076 alu.op = ALU_OP1_MOV;
4077 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4078 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4079 else
4080 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4081 alu.dst.sel = ctx->temp_reg;
4082 alu.dst.chan = 2;
4083 alu.dst.write = 1;
4084 alu.last = 1;
4085 r = r600_bytecode_add_alu(ctx->bc, &alu);
4086 if (r)
4087 return r;
4088 }
4089
4090 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4091 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4092 if (ctx->bc->chip_class >= EVERGREEN) {
4093 int mytmp = r600_get_temp(ctx);
4094 static const float eight = 8.0f;
4095 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4096 alu.op = ALU_OP1_MOV;
4097 alu.src[0].sel = ctx->temp_reg;
4098 alu.src[0].chan = 3;
4099 alu.dst.sel = mytmp;
4100 alu.dst.chan = 0;
4101 alu.dst.write = 1;
4102 alu.last = 1;
4103 r = r600_bytecode_add_alu(ctx->bc, &alu);
4104 if (r)
4105 return r;
4106
4107 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4108 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4109 alu.op = ALU_OP3_MULADD;
4110 alu.is_op3 = 1;
4111 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4112 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4113 alu.src[1].chan = 0;
4114 alu.src[1].value = *(uint32_t *)&eight;
4115 alu.src[2].sel = mytmp;
4116 alu.src[2].chan = 0;
4117 alu.dst.sel = ctx->temp_reg;
4118 alu.dst.chan = 3;
4119 alu.dst.write = 1;
4120 alu.last = 1;
4121 r = r600_bytecode_add_alu(ctx->bc, &alu);
4122 if (r)
4123 return r;
4124 } else if (ctx->bc->chip_class < EVERGREEN) {
4125 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4126 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4127 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4128 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4129 tex.src_gpr = r600_get_temp(ctx);
4130 tex.src_sel_x = 0;
4131 tex.src_sel_y = 0;
4132 tex.src_sel_z = 0;
4133 tex.src_sel_w = 0;
4134 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4135 tex.coord_type_x = 1;
4136 tex.coord_type_y = 1;
4137 tex.coord_type_z = 1;
4138 tex.coord_type_w = 1;
4139 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4140 alu.op = ALU_OP1_MOV;
4141 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4142 alu.dst.sel = tex.src_gpr;
4143 alu.dst.chan = 0;
4144 alu.last = 1;
4145 alu.dst.write = 1;
4146 r = r600_bytecode_add_alu(ctx->bc, &alu);
4147 if (r)
4148 return r;
4149
4150 r = r600_bytecode_add_tex(ctx->bc, &tex);
4151 if (r)
4152 return r;
4153 }
4154
4155 }
4156
4157 /* for cube forms of lod and bias we need to route things */
4158 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4159 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4160 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4161 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4163 alu.op = ALU_OP1_MOV;
4164 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4165 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4166 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4167 else
4168 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4169 alu.dst.sel = ctx->temp_reg;
4170 alu.dst.chan = 2;
4171 alu.last = 1;
4172 alu.dst.write = 1;
4173 r = r600_bytecode_add_alu(ctx->bc, &alu);
4174 if (r)
4175 return r;
4176 }
4177
4178 src_loaded = TRUE;
4179 src_gpr = ctx->temp_reg;
4180 }
4181
4182 if (src_requires_loading && !src_loaded) {
4183 for (i = 0; i < 4; i++) {
4184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4185 alu.op = ALU_OP1_MOV;
4186 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4187 alu.dst.sel = ctx->temp_reg;
4188 alu.dst.chan = i;
4189 if (i == 3)
4190 alu.last = 1;
4191 alu.dst.write = 1;
4192 r = r600_bytecode_add_alu(ctx->bc, &alu);
4193 if (r)
4194 return r;
4195 }
4196 src_loaded = TRUE;
4197 src_gpr = ctx->temp_reg;
4198 }
4199
4200 /* Obtain the sample index for reading a compressed MSAA color texture.
4201 * To read the FMASK, we use the ldfptr instruction, which tells us
4202 * where the samples are stored.
4203 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4204 * which is the identity mapping. Each nibble says which physical sample
4205 * should be fetched to get that sample.
4206 *
4207 * Assume src.z contains the sample index. It should be modified like this:
4208 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4209 * Then fetch the texel with src.
4210 */
4211 if (read_compressed_msaa) {
4212 unsigned sample_chan = 3;
4213 unsigned temp = r600_get_temp(ctx);
4214 assert(src_loaded);
4215
4216 /* temp.w = ldfptr() */
4217 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4218 tex.op = FETCH_OP_LD;
4219 tex.inst_mod = 1; /* to indicate this is ldfptr */
4220 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4221 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4222 tex.src_gpr = src_gpr;
4223 tex.dst_gpr = temp;
4224 tex.dst_sel_x = 7; /* mask out these components */
4225 tex.dst_sel_y = 7;
4226 tex.dst_sel_z = 7;
4227 tex.dst_sel_w = 0; /* store X */
4228 tex.src_sel_x = 0;
4229 tex.src_sel_y = 1;
4230 tex.src_sel_z = 2;
4231 tex.src_sel_w = 3;
4232 tex.offset_x = offset_x;
4233 tex.offset_y = offset_y;
4234 tex.offset_z = offset_z;
4235 r = r600_bytecode_add_tex(ctx->bc, &tex);
4236 if (r)
4237 return r;
4238
4239 /* temp.x = sample_index*4 */
4240 if (ctx->bc->chip_class == CAYMAN) {
4241 for (i = 0 ; i < 4; i++) {
4242 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4243 alu.op = ALU_OP2_MULLO_INT;
4244 alu.src[0].sel = src_gpr;
4245 alu.src[0].chan = sample_chan;
4246 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4247 alu.src[1].value = 4;
4248 alu.dst.sel = temp;
4249 alu.dst.chan = i;
4250 alu.dst.write = i == 0;
4251 if (i == 3)
4252 alu.last = 1;
4253 r = r600_bytecode_add_alu(ctx->bc, &alu);
4254 if (r)
4255 return r;
4256 }
4257 } else {
4258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4259 alu.op = ALU_OP2_MULLO_INT;
4260 alu.src[0].sel = src_gpr;
4261 alu.src[0].chan = sample_chan;
4262 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4263 alu.src[1].value = 4;
4264 alu.dst.sel = temp;
4265 alu.dst.chan = 0;
4266 alu.dst.write = 1;
4267 alu.last = 1;
4268 r = r600_bytecode_add_alu(ctx->bc, &alu);
4269 if (r)
4270 return r;
4271 }
4272
4273 /* sample_index = temp.w >> temp.x */
4274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4275 alu.op = ALU_OP2_LSHR_INT;
4276 alu.src[0].sel = temp;
4277 alu.src[0].chan = 3;
4278 alu.src[1].sel = temp;
4279 alu.src[1].chan = 0;
4280 alu.dst.sel = src_gpr;
4281 alu.dst.chan = sample_chan;
4282 alu.dst.write = 1;
4283 alu.last = 1;
4284 r = r600_bytecode_add_alu(ctx->bc, &alu);
4285 if (r)
4286 return r;
4287
4288 /* sample_index & 0xF */
4289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4290 alu.op = ALU_OP2_AND_INT;
4291 alu.src[0].sel = src_gpr;
4292 alu.src[0].chan = sample_chan;
4293 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4294 alu.src[1].value = 0xF;
4295 alu.dst.sel = src_gpr;
4296 alu.dst.chan = sample_chan;
4297 alu.dst.write = 1;
4298 alu.last = 1;
4299 r = r600_bytecode_add_alu(ctx->bc, &alu);
4300 if (r)
4301 return r;
4302 #if 0
4303 /* visualize the FMASK */
4304 for (i = 0; i < 4; i++) {
4305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4306 alu.op = ALU_OP1_INT_TO_FLT;
4307 alu.src[0].sel = src_gpr;
4308 alu.src[0].chan = sample_chan;
4309 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4310 alu.dst.chan = i;
4311 alu.dst.write = 1;
4312 alu.last = 1;
4313 r = r600_bytecode_add_alu(ctx->bc, &alu);
4314 if (r)
4315 return r;
4316 }
4317 return 0;
4318 #endif
4319 }
4320
4321 /* does this shader want a num layers from TXQ for a cube array? */
4322 if (has_txq_cube_array_z) {
4323 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4324
4325 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4326 alu.op = ALU_OP1_MOV;
4327
4328 alu.src[0].sel = 512 + (id / 4);
4329 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4330 alu.src[0].chan = id % 4;
4331 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4332 alu.last = 1;
4333 r = r600_bytecode_add_alu(ctx->bc, &alu);
4334 if (r)
4335 return r;
4336 /* disable writemask from texture instruction */
4337 inst->Dst[0].Register.WriteMask &= ~4;
4338 }
4339
4340 opcode = ctx->inst_info->op;
4341 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4342 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4343 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4344 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4345 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4346 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4347 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4348 switch (opcode) {
4349 case FETCH_OP_SAMPLE:
4350 opcode = FETCH_OP_SAMPLE_C;
4351 break;
4352 case FETCH_OP_SAMPLE_L:
4353 opcode = FETCH_OP_SAMPLE_C_L;
4354 break;
4355 case FETCH_OP_SAMPLE_LB:
4356 opcode = FETCH_OP_SAMPLE_C_LB;
4357 break;
4358 case FETCH_OP_SAMPLE_G:
4359 opcode = FETCH_OP_SAMPLE_C_G;
4360 break;
4361 }
4362 }
4363
4364 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4365 tex.op = opcode;
4366
4367 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4368 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4369 tex.src_gpr = src_gpr;
4370 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4371 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4372 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4373 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4374 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4375
4376 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4377 tex.src_sel_x = 4;
4378 tex.src_sel_y = 4;
4379 tex.src_sel_z = 4;
4380 tex.src_sel_w = 4;
4381 } else if (src_loaded) {
4382 tex.src_sel_x = 0;
4383 tex.src_sel_y = 1;
4384 tex.src_sel_z = 2;
4385 tex.src_sel_w = 3;
4386 } else {
4387 tex.src_sel_x = ctx->src[0].swizzle[0];
4388 tex.src_sel_y = ctx->src[0].swizzle[1];
4389 tex.src_sel_z = ctx->src[0].swizzle[2];
4390 tex.src_sel_w = ctx->src[0].swizzle[3];
4391 tex.src_rel = ctx->src[0].rel;
4392 }
4393
4394 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4395 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4396 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4397 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4398 tex.src_sel_x = 1;
4399 tex.src_sel_y = 0;
4400 tex.src_sel_z = 3;
4401 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4402 }
4403
4404 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4405 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4406 tex.coord_type_x = 1;
4407 tex.coord_type_y = 1;
4408 }
4409 tex.coord_type_z = 1;
4410 tex.coord_type_w = 1;
4411
4412 tex.offset_x = offset_x;
4413 tex.offset_y = offset_y;
4414 tex.offset_z = offset_z;
4415
4416 /* Put the depth for comparison in W.
4417 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4418 * Some instructions expect the depth in Z. */
4419 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4420 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4421 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4422 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4423 opcode != FETCH_OP_SAMPLE_C_L &&
4424 opcode != FETCH_OP_SAMPLE_C_LB) {
4425 tex.src_sel_w = tex.src_sel_z;
4426 }
4427
4428 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4429 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4430 if (opcode == FETCH_OP_SAMPLE_C_L ||
4431 opcode == FETCH_OP_SAMPLE_C_LB) {
4432 /* the array index is read from Y */
4433 tex.coord_type_y = 0;
4434 } else {
4435 /* the array index is read from Z */
4436 tex.coord_type_z = 0;
4437 tex.src_sel_z = tex.src_sel_y;
4438 }
4439 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4440 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4441 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4442 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4443 (ctx->bc->chip_class >= EVERGREEN)))
4444 /* the array index is read from Z */
4445 tex.coord_type_z = 0;
4446
4447 /* mask unused source components */
4448 if (opcode == FETCH_OP_SAMPLE) {
4449 switch (inst->Texture.Texture) {
4450 case TGSI_TEXTURE_2D:
4451 case TGSI_TEXTURE_RECT:
4452 tex.src_sel_z = 7;
4453 tex.src_sel_w = 7;
4454 break;
4455 case TGSI_TEXTURE_1D_ARRAY:
4456 tex.src_sel_y = 7;
4457 tex.src_sel_w = 7;
4458 break;
4459 case TGSI_TEXTURE_1D:
4460 tex.src_sel_y = 7;
4461 tex.src_sel_z = 7;
4462 tex.src_sel_w = 7;
4463 break;
4464 }
4465 }
4466
4467 r = r600_bytecode_add_tex(ctx->bc, &tex);
4468 if (r)
4469 return r;
4470
4471 /* add shadow ambient support - gallium doesn't do it yet */
4472 return 0;
4473 }
4474
4475 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4476 {
4477 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4478 struct r600_bytecode_alu alu;
4479 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4480 unsigned i;
4481 int r;
4482
4483 /* optimize if it's just an equal balance */
4484 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4485 for (i = 0; i < lasti + 1; i++) {
4486 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4487 continue;
4488
4489 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4490 alu.op = ALU_OP2_ADD;
4491 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4492 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4493 alu.omod = 3;
4494 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4495 alu.dst.chan = i;
4496 if (i == lasti) {
4497 alu.last = 1;
4498 }
4499 r = r600_bytecode_add_alu(ctx->bc, &alu);
4500 if (r)
4501 return r;
4502 }
4503 return 0;
4504 }
4505
4506 /* 1 - src0 */
4507 for (i = 0; i < lasti + 1; i++) {
4508 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4509 continue;
4510
4511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4512 alu.op = ALU_OP2_ADD;
4513 alu.src[0].sel = V_SQ_ALU_SRC_1;
4514 alu.src[0].chan = 0;
4515 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4516 r600_bytecode_src_toggle_neg(&alu.src[1]);
4517 alu.dst.sel = ctx->temp_reg;
4518 alu.dst.chan = i;
4519 if (i == lasti) {
4520 alu.last = 1;
4521 }
4522 alu.dst.write = 1;
4523 r = r600_bytecode_add_alu(ctx->bc, &alu);
4524 if (r)
4525 return r;
4526 }
4527
4528 /* (1 - src0) * src2 */
4529 for (i = 0; i < lasti + 1; i++) {
4530 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4531 continue;
4532
4533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4534 alu.op = ALU_OP2_MUL;
4535 alu.src[0].sel = ctx->temp_reg;
4536 alu.src[0].chan = i;
4537 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4538 alu.dst.sel = ctx->temp_reg;
4539 alu.dst.chan = i;
4540 if (i == lasti) {
4541 alu.last = 1;
4542 }
4543 alu.dst.write = 1;
4544 r = r600_bytecode_add_alu(ctx->bc, &alu);
4545 if (r)
4546 return r;
4547 }
4548
4549 /* src0 * src1 + (1 - src0) * src2 */
4550 for (i = 0; i < lasti + 1; i++) {
4551 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4552 continue;
4553
4554 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4555 alu.op = ALU_OP3_MULADD;
4556 alu.is_op3 = 1;
4557 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4558 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4559 alu.src[2].sel = ctx->temp_reg;
4560 alu.src[2].chan = i;
4561
4562 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4563 alu.dst.chan = i;
4564 if (i == lasti) {
4565 alu.last = 1;
4566 }
4567 r = r600_bytecode_add_alu(ctx->bc, &alu);
4568 if (r)
4569 return r;
4570 }
4571 return 0;
4572 }
4573
4574 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4575 {
4576 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4577 struct r600_bytecode_alu alu;
4578 int i, r;
4579 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4580
4581 for (i = 0; i < lasti + 1; i++) {
4582 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4583 continue;
4584
4585 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4586 alu.op = ALU_OP3_CNDGE;
4587 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4588 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4589 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4590 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4591 alu.dst.chan = i;
4592 alu.dst.write = 1;
4593 alu.is_op3 = 1;
4594 if (i == lasti)
4595 alu.last = 1;
4596 r = r600_bytecode_add_alu(ctx->bc, &alu);
4597 if (r)
4598 return r;
4599 }
4600 return 0;
4601 }
4602
4603 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4604 {
4605 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4606 struct r600_bytecode_alu alu;
4607 int i, r;
4608 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4609
4610 for (i = 0; i < lasti + 1; i++) {
4611 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4612 continue;
4613
4614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4615 alu.op = ALU_OP3_CNDGE_INT;
4616 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4617 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4618 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4619 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4620 alu.dst.chan = i;
4621 alu.dst.write = 1;
4622 alu.is_op3 = 1;
4623 if (i == lasti)
4624 alu.last = 1;
4625 r = r600_bytecode_add_alu(ctx->bc, &alu);
4626 if (r)
4627 return r;
4628 }
4629 return 0;
4630 }
4631
4632 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4633 {
4634 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4635 static const unsigned int src0_swizzle[] = {2, 0, 1};
4636 static const unsigned int src1_swizzle[] = {1, 2, 0};
4637 struct r600_bytecode_alu alu;
4638 uint32_t use_temp = 0;
4639 int i, r;
4640
4641 if (inst->Dst[0].Register.WriteMask != 0xf)
4642 use_temp = 1;
4643
4644 for (i = 0; i < 4; i++) {
4645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4646 alu.op = ALU_OP2_MUL;
4647 if (i < 3) {
4648 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4649 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4650 } else {
4651 alu.src[0].sel = V_SQ_ALU_SRC_0;
4652 alu.src[0].chan = i;
4653 alu.src[1].sel = V_SQ_ALU_SRC_0;
4654 alu.src[1].chan = i;
4655 }
4656
4657 alu.dst.sel = ctx->temp_reg;
4658 alu.dst.chan = i;
4659 alu.dst.write = 1;
4660
4661 if (i == 3)
4662 alu.last = 1;
4663 r = r600_bytecode_add_alu(ctx->bc, &alu);
4664 if (r)
4665 return r;
4666 }
4667
4668 for (i = 0; i < 4; i++) {
4669 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4670 alu.op = ALU_OP3_MULADD;
4671
4672 if (i < 3) {
4673 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4674 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4675 } else {
4676 alu.src[0].sel = V_SQ_ALU_SRC_0;
4677 alu.src[0].chan = i;
4678 alu.src[1].sel = V_SQ_ALU_SRC_0;
4679 alu.src[1].chan = i;
4680 }
4681
4682 alu.src[2].sel = ctx->temp_reg;
4683 alu.src[2].neg = 1;
4684 alu.src[2].chan = i;
4685
4686 if (use_temp)
4687 alu.dst.sel = ctx->temp_reg;
4688 else
4689 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4690 alu.dst.chan = i;
4691 alu.dst.write = 1;
4692 alu.is_op3 = 1;
4693 if (i == 3)
4694 alu.last = 1;
4695 r = r600_bytecode_add_alu(ctx->bc, &alu);
4696 if (r)
4697 return r;
4698 }
4699 if (use_temp)
4700 return tgsi_helper_copy(ctx, inst);
4701 return 0;
4702 }
4703
4704 static int tgsi_exp(struct r600_shader_ctx *ctx)
4705 {
4706 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4707 struct r600_bytecode_alu alu;
4708 int r;
4709 int i;
4710
4711 /* result.x = 2^floor(src); */
4712 if (inst->Dst[0].Register.WriteMask & 1) {
4713 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4714
4715 alu.op = ALU_OP1_FLOOR;
4716 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4717
4718 alu.dst.sel = ctx->temp_reg;
4719 alu.dst.chan = 0;
4720 alu.dst.write = 1;
4721 alu.last = 1;
4722 r = r600_bytecode_add_alu(ctx->bc, &alu);
4723 if (r)
4724 return r;
4725
4726 if (ctx->bc->chip_class == CAYMAN) {
4727 for (i = 0; i < 3; i++) {
4728 alu.op = ALU_OP1_EXP_IEEE;
4729 alu.src[0].sel = ctx->temp_reg;
4730 alu.src[0].chan = 0;
4731
4732 alu.dst.sel = ctx->temp_reg;
4733 alu.dst.chan = i;
4734 alu.dst.write = i == 0;
4735 alu.last = i == 2;
4736 r = r600_bytecode_add_alu(ctx->bc, &alu);
4737 if (r)
4738 return r;
4739 }
4740 } else {
4741 alu.op = ALU_OP1_EXP_IEEE;
4742 alu.src[0].sel = ctx->temp_reg;
4743 alu.src[0].chan = 0;
4744
4745 alu.dst.sel = ctx->temp_reg;
4746 alu.dst.chan = 0;
4747 alu.dst.write = 1;
4748 alu.last = 1;
4749 r = r600_bytecode_add_alu(ctx->bc, &alu);
4750 if (r)
4751 return r;
4752 }
4753 }
4754
4755 /* result.y = tmp - floor(tmp); */
4756 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4758
4759 alu.op = ALU_OP1_FRACT;
4760 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4761
4762 alu.dst.sel = ctx->temp_reg;
4763 #if 0
4764 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4765 if (r)
4766 return r;
4767 #endif
4768 alu.dst.write = 1;
4769 alu.dst.chan = 1;
4770
4771 alu.last = 1;
4772
4773 r = r600_bytecode_add_alu(ctx->bc, &alu);
4774 if (r)
4775 return r;
4776 }
4777
4778 /* result.z = RoughApprox2ToX(tmp);*/
4779 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
4780 if (ctx->bc->chip_class == CAYMAN) {
4781 for (i = 0; i < 3; i++) {
4782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4783 alu.op = ALU_OP1_EXP_IEEE;
4784 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4785
4786 alu.dst.sel = ctx->temp_reg;
4787 alu.dst.chan = i;
4788 if (i == 2) {
4789 alu.dst.write = 1;
4790 alu.last = 1;
4791 }
4792
4793 r = r600_bytecode_add_alu(ctx->bc, &alu);
4794 if (r)
4795 return r;
4796 }
4797 } else {
4798 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4799 alu.op = ALU_OP1_EXP_IEEE;
4800 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4801
4802 alu.dst.sel = ctx->temp_reg;
4803 alu.dst.write = 1;
4804 alu.dst.chan = 2;
4805
4806 alu.last = 1;
4807
4808 r = r600_bytecode_add_alu(ctx->bc, &alu);
4809 if (r)
4810 return r;
4811 }
4812 }
4813
4814 /* result.w = 1.0;*/
4815 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
4816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4817
4818 alu.op = ALU_OP1_MOV;
4819 alu.src[0].sel = V_SQ_ALU_SRC_1;
4820 alu.src[0].chan = 0;
4821
4822 alu.dst.sel = ctx->temp_reg;
4823 alu.dst.chan = 3;
4824 alu.dst.write = 1;
4825 alu.last = 1;
4826 r = r600_bytecode_add_alu(ctx->bc, &alu);
4827 if (r)
4828 return r;
4829 }
4830 return tgsi_helper_copy(ctx, inst);
4831 }
4832
4833 static int tgsi_log(struct r600_shader_ctx *ctx)
4834 {
4835 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4836 struct r600_bytecode_alu alu;
4837 int r;
4838 int i;
4839
4840 /* result.x = floor(log2(|src|)); */
4841 if (inst->Dst[0].Register.WriteMask & 1) {
4842 if (ctx->bc->chip_class == CAYMAN) {
4843 for (i = 0; i < 3; i++) {
4844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4845
4846 alu.op = ALU_OP1_LOG_IEEE;
4847 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4848 r600_bytecode_src_set_abs(&alu.src[0]);
4849
4850 alu.dst.sel = ctx->temp_reg;
4851 alu.dst.chan = i;
4852 if (i == 0)
4853 alu.dst.write = 1;
4854 if (i == 2)
4855 alu.last = 1;
4856 r = r600_bytecode_add_alu(ctx->bc, &alu);
4857 if (r)
4858 return r;
4859 }
4860
4861 } else {
4862 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4863
4864 alu.op = ALU_OP1_LOG_IEEE;
4865 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4866 r600_bytecode_src_set_abs(&alu.src[0]);
4867
4868 alu.dst.sel = ctx->temp_reg;
4869 alu.dst.chan = 0;
4870 alu.dst.write = 1;
4871 alu.last = 1;
4872 r = r600_bytecode_add_alu(ctx->bc, &alu);
4873 if (r)
4874 return r;
4875 }
4876
4877 alu.op = ALU_OP1_FLOOR;
4878 alu.src[0].sel = ctx->temp_reg;
4879 alu.src[0].chan = 0;
4880
4881 alu.dst.sel = ctx->temp_reg;
4882 alu.dst.chan = 0;
4883 alu.dst.write = 1;
4884 alu.last = 1;
4885
4886 r = r600_bytecode_add_alu(ctx->bc, &alu);
4887 if (r)
4888 return r;
4889 }
4890
4891 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4892 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4893
4894 if (ctx->bc->chip_class == CAYMAN) {
4895 for (i = 0; i < 3; i++) {
4896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4897
4898 alu.op = ALU_OP1_LOG_IEEE;
4899 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4900 r600_bytecode_src_set_abs(&alu.src[0]);
4901
4902 alu.dst.sel = ctx->temp_reg;
4903 alu.dst.chan = i;
4904 if (i == 1)
4905 alu.dst.write = 1;
4906 if (i == 2)
4907 alu.last = 1;
4908
4909 r = r600_bytecode_add_alu(ctx->bc, &alu);
4910 if (r)
4911 return r;
4912 }
4913 } else {
4914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4915
4916 alu.op = ALU_OP1_LOG_IEEE;
4917 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4918 r600_bytecode_src_set_abs(&alu.src[0]);
4919
4920 alu.dst.sel = ctx->temp_reg;
4921 alu.dst.chan = 1;
4922 alu.dst.write = 1;
4923 alu.last = 1;
4924
4925 r = r600_bytecode_add_alu(ctx->bc, &alu);
4926 if (r)
4927 return r;
4928 }
4929
4930 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4931
4932 alu.op = ALU_OP1_FLOOR;
4933 alu.src[0].sel = ctx->temp_reg;
4934 alu.src[0].chan = 1;
4935
4936 alu.dst.sel = ctx->temp_reg;
4937 alu.dst.chan = 1;
4938 alu.dst.write = 1;
4939 alu.last = 1;
4940
4941 r = r600_bytecode_add_alu(ctx->bc, &alu);
4942 if (r)
4943 return r;
4944
4945 if (ctx->bc->chip_class == CAYMAN) {
4946 for (i = 0; i < 3; i++) {
4947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4948 alu.op = ALU_OP1_EXP_IEEE;
4949 alu.src[0].sel = ctx->temp_reg;
4950 alu.src[0].chan = 1;
4951
4952 alu.dst.sel = ctx->temp_reg;
4953 alu.dst.chan = i;
4954 if (i == 1)
4955 alu.dst.write = 1;
4956 if (i == 2)
4957 alu.last = 1;
4958
4959 r = r600_bytecode_add_alu(ctx->bc, &alu);
4960 if (r)
4961 return r;
4962 }
4963 } else {
4964 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4965 alu.op = ALU_OP1_EXP_IEEE;
4966 alu.src[0].sel = ctx->temp_reg;
4967 alu.src[0].chan = 1;
4968
4969 alu.dst.sel = ctx->temp_reg;
4970 alu.dst.chan = 1;
4971 alu.dst.write = 1;
4972 alu.last = 1;
4973
4974 r = r600_bytecode_add_alu(ctx->bc, &alu);
4975 if (r)
4976 return r;
4977 }
4978
4979 if (ctx->bc->chip_class == CAYMAN) {
4980 for (i = 0; i < 3; i++) {
4981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4982 alu.op = ALU_OP1_RECIP_IEEE;
4983 alu.src[0].sel = ctx->temp_reg;
4984 alu.src[0].chan = 1;
4985
4986 alu.dst.sel = ctx->temp_reg;
4987 alu.dst.chan = i;
4988 if (i == 1)
4989 alu.dst.write = 1;
4990 if (i == 2)
4991 alu.last = 1;
4992
4993 r = r600_bytecode_add_alu(ctx->bc, &alu);
4994 if (r)
4995 return r;
4996 }
4997 } else {
4998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4999 alu.op = ALU_OP1_RECIP_IEEE;
5000 alu.src[0].sel = ctx->temp_reg;
5001 alu.src[0].chan = 1;
5002
5003 alu.dst.sel = ctx->temp_reg;
5004 alu.dst.chan = 1;
5005 alu.dst.write = 1;
5006 alu.last = 1;
5007
5008 r = r600_bytecode_add_alu(ctx->bc, &alu);
5009 if (r)
5010 return r;
5011 }
5012
5013 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5014
5015 alu.op = ALU_OP2_MUL;
5016
5017 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5018 r600_bytecode_src_set_abs(&alu.src[0]);
5019
5020 alu.src[1].sel = ctx->temp_reg;
5021 alu.src[1].chan = 1;
5022
5023 alu.dst.sel = ctx->temp_reg;
5024 alu.dst.chan = 1;
5025 alu.dst.write = 1;
5026 alu.last = 1;
5027
5028 r = r600_bytecode_add_alu(ctx->bc, &alu);
5029 if (r)
5030 return r;
5031 }
5032
5033 /* result.z = log2(|src|);*/
5034 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5035 if (ctx->bc->chip_class == CAYMAN) {
5036 for (i = 0; i < 3; i++) {
5037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5038
5039 alu.op = ALU_OP1_LOG_IEEE;
5040 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5041 r600_bytecode_src_set_abs(&alu.src[0]);
5042
5043 alu.dst.sel = ctx->temp_reg;
5044 if (i == 2)
5045 alu.dst.write = 1;
5046 alu.dst.chan = i;
5047 if (i == 2)
5048 alu.last = 1;
5049
5050 r = r600_bytecode_add_alu(ctx->bc, &alu);
5051 if (r)
5052 return r;
5053 }
5054 } else {
5055 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5056
5057 alu.op = ALU_OP1_LOG_IEEE;
5058 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5059 r600_bytecode_src_set_abs(&alu.src[0]);
5060
5061 alu.dst.sel = ctx->temp_reg;
5062 alu.dst.write = 1;
5063 alu.dst.chan = 2;
5064 alu.last = 1;
5065
5066 r = r600_bytecode_add_alu(ctx->bc, &alu);
5067 if (r)
5068 return r;
5069 }
5070 }
5071
5072 /* result.w = 1.0; */
5073 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5074 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5075
5076 alu.op = ALU_OP1_MOV;
5077 alu.src[0].sel = V_SQ_ALU_SRC_1;
5078 alu.src[0].chan = 0;
5079
5080 alu.dst.sel = ctx->temp_reg;
5081 alu.dst.chan = 3;
5082 alu.dst.write = 1;
5083 alu.last = 1;
5084
5085 r = r600_bytecode_add_alu(ctx->bc, &alu);
5086 if (r)
5087 return r;
5088 }
5089
5090 return tgsi_helper_copy(ctx, inst);
5091 }
5092
5093 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5094 {
5095 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5096 struct r600_bytecode_alu alu;
5097 int r;
5098
5099 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5100
5101 switch (inst->Instruction.Opcode) {
5102 case TGSI_OPCODE_ARL:
5103 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5104 break;
5105 case TGSI_OPCODE_ARR:
5106 alu.op = ALU_OP1_FLT_TO_INT;
5107 break;
5108 case TGSI_OPCODE_UARL:
5109 alu.op = ALU_OP1_MOV;
5110 break;
5111 default:
5112 assert(0);
5113 return -1;
5114 }
5115
5116 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5117 alu.last = 1;
5118 alu.dst.sel = ctx->bc->ar_reg;
5119 alu.dst.write = 1;
5120 r = r600_bytecode_add_alu(ctx->bc, &alu);
5121 if (r)
5122 return r;
5123
5124 ctx->bc->ar_loaded = 0;
5125 return 0;
5126 }
5127 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5128 {
5129 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5130 struct r600_bytecode_alu alu;
5131 int r;
5132
5133 switch (inst->Instruction.Opcode) {
5134 case TGSI_OPCODE_ARL:
5135 memset(&alu, 0, sizeof(alu));
5136 alu.op = ALU_OP1_FLOOR;
5137 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5138 alu.dst.sel = ctx->bc->ar_reg;
5139 alu.dst.write = 1;
5140 alu.last = 1;
5141
5142 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5143 return r;
5144
5145 memset(&alu, 0, sizeof(alu));
5146 alu.op = ALU_OP1_FLT_TO_INT;
5147 alu.src[0].sel = ctx->bc->ar_reg;
5148 alu.dst.sel = ctx->bc->ar_reg;
5149 alu.dst.write = 1;
5150 alu.last = 1;
5151
5152 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5153 return r;
5154 break;
5155 case TGSI_OPCODE_ARR:
5156 memset(&alu, 0, sizeof(alu));
5157 alu.op = ALU_OP1_FLT_TO_INT;
5158 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5159 alu.dst.sel = ctx->bc->ar_reg;
5160 alu.dst.write = 1;
5161 alu.last = 1;
5162
5163 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5164 return r;
5165 break;
5166 case TGSI_OPCODE_UARL:
5167 memset(&alu, 0, sizeof(alu));
5168 alu.op = ALU_OP1_MOV;
5169 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5170 alu.dst.sel = ctx->bc->ar_reg;
5171 alu.dst.write = 1;
5172 alu.last = 1;
5173
5174 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5175 return r;
5176 break;
5177 default:
5178 assert(0);
5179 return -1;
5180 }
5181
5182 ctx->bc->ar_loaded = 0;
5183 return 0;
5184 }
5185
5186 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5187 {
5188 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5189 struct r600_bytecode_alu alu;
5190 int i, r = 0;
5191
5192 for (i = 0; i < 4; i++) {
5193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5194
5195 alu.op = ALU_OP2_MUL;
5196 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5197
5198 if (i == 0 || i == 3) {
5199 alu.src[0].sel = V_SQ_ALU_SRC_1;
5200 } else {
5201 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5202 }
5203
5204 if (i == 0 || i == 2) {
5205 alu.src[1].sel = V_SQ_ALU_SRC_1;
5206 } else {
5207 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5208 }
5209 if (i == 3)
5210 alu.last = 1;
5211 r = r600_bytecode_add_alu(ctx->bc, &alu);
5212 if (r)
5213 return r;
5214 }
5215 return 0;
5216 }
5217
5218 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5219 {
5220 struct r600_bytecode_alu alu;
5221 int r;
5222
5223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5224 alu.op = opcode;
5225 alu.execute_mask = 1;
5226 alu.update_pred = 1;
5227
5228 alu.dst.sel = ctx->temp_reg;
5229 alu.dst.write = 1;
5230 alu.dst.chan = 0;
5231
5232 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5233 alu.src[1].sel = V_SQ_ALU_SRC_0;
5234 alu.src[1].chan = 0;
5235
5236 alu.last = 1;
5237
5238 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5239 if (r)
5240 return r;
5241 return 0;
5242 }
5243
5244 static int pops(struct r600_shader_ctx *ctx, int pops)
5245 {
5246 unsigned force_pop = ctx->bc->force_add_cf;
5247
5248 if (!force_pop) {
5249 int alu_pop = 3;
5250 if (ctx->bc->cf_last) {
5251 if (ctx->bc->cf_last->op == CF_OP_ALU)
5252 alu_pop = 0;
5253 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5254 alu_pop = 1;
5255 }
5256 alu_pop += pops;
5257 if (alu_pop == 1) {
5258 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5259 ctx->bc->force_add_cf = 1;
5260 } else if (alu_pop == 2) {
5261 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5262 ctx->bc->force_add_cf = 1;
5263 } else {
5264 force_pop = 1;
5265 }
5266 }
5267
5268 if (force_pop) {
5269 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5270 ctx->bc->cf_last->pop_count = pops;
5271 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5272 }
5273
5274 return 0;
5275 }
5276
5277 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5278 unsigned reason)
5279 {
5280 struct r600_stack_info *stack = &ctx->bc->stack;
5281 unsigned elements, entries;
5282
5283 unsigned entry_size = stack->entry_size;
5284
5285 elements = (stack->loop + stack->push_wqm ) * entry_size;
5286 elements += stack->push;
5287
5288 switch (ctx->bc->chip_class) {
5289 case R600:
5290 case R700:
5291 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5292 * the stack must be reserved to hold the current active/continue
5293 * masks */
5294 if (reason == FC_PUSH_VPM) {
5295 elements += 2;
5296 }
5297 break;
5298
5299 case CAYMAN:
5300 /* r9xx: any stack operation on empty stack consumes 2 additional
5301 * elements */
5302 elements += 2;
5303
5304 /* fallthrough */
5305 /* FIXME: do the two elements added above cover the cases for the
5306 * r8xx+ below? */
5307
5308 case EVERGREEN:
5309 /* r8xx+: 2 extra elements are not always required, but one extra
5310 * element must be added for each of the following cases:
5311 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5312 * stack usage.
5313 * (Currently we don't use ALU_ELSE_AFTER.)
5314 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5315 * PUSH instruction executed.
5316 *
5317 * NOTE: it seems we also need to reserve additional element in some
5318 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5319 * then STACK_SIZE should be 2 instead of 1 */
5320 if (reason == FC_PUSH_VPM) {
5321 elements += 1;
5322 }
5323 break;
5324
5325 default:
5326 assert(0);
5327 break;
5328 }
5329
5330 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5331 * for all chips, so we use 4 in the final formula, not the real entry_size
5332 * for the chip */
5333 entry_size = 4;
5334
5335 entries = (elements + (entry_size - 1)) / entry_size;
5336
5337 if (entries > stack->max_entries)
5338 stack->max_entries = entries;
5339 }
5340
5341 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5342 {
5343 switch(reason) {
5344 case FC_PUSH_VPM:
5345 --ctx->bc->stack.push;
5346 assert(ctx->bc->stack.push >= 0);
5347 break;
5348 case FC_PUSH_WQM:
5349 --ctx->bc->stack.push_wqm;
5350 assert(ctx->bc->stack.push_wqm >= 0);
5351 break;
5352 case FC_LOOP:
5353 --ctx->bc->stack.loop;
5354 assert(ctx->bc->stack.loop >= 0);
5355 break;
5356 default:
5357 assert(0);
5358 break;
5359 }
5360 }
5361
5362 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5363 {
5364 switch (reason) {
5365 case FC_PUSH_VPM:
5366 ++ctx->bc->stack.push;
5367 break;
5368 case FC_PUSH_WQM:
5369 ++ctx->bc->stack.push_wqm;
5370 case FC_LOOP:
5371 ++ctx->bc->stack.loop;
5372 break;
5373 default:
5374 assert(0);
5375 }
5376
5377 callstack_update_max_depth(ctx, reason);
5378 }
5379
5380 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5381 {
5382 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5383
5384 sp->mid = realloc((void *)sp->mid,
5385 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5386 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5387 sp->num_mid++;
5388 }
5389
5390 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5391 {
5392 ctx->bc->fc_sp++;
5393 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5394 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5395 }
5396
5397 static void fc_poplevel(struct r600_shader_ctx *ctx)
5398 {
5399 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5400 free(sp->mid);
5401 sp->mid = NULL;
5402 sp->num_mid = 0;
5403 sp->start = NULL;
5404 sp->type = 0;
5405 ctx->bc->fc_sp--;
5406 }
5407
5408 #if 0
5409 static int emit_return(struct r600_shader_ctx *ctx)
5410 {
5411 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5412 return 0;
5413 }
5414
5415 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5416 {
5417
5418 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5419 ctx->bc->cf_last->pop_count = pops;
5420 /* XXX work out offset */
5421 return 0;
5422 }
5423
5424 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5425 {
5426 return 0;
5427 }
5428
5429 static void emit_testflag(struct r600_shader_ctx *ctx)
5430 {
5431
5432 }
5433
5434 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5435 {
5436 emit_testflag(ctx);
5437 emit_jump_to_offset(ctx, 1, 4);
5438 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5439 pops(ctx, ifidx + 1);
5440 emit_return(ctx);
5441 }
5442
5443 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5444 {
5445 emit_testflag(ctx);
5446
5447 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5448 ctx->bc->cf_last->pop_count = 1;
5449
5450 fc_set_mid(ctx, fc_sp);
5451
5452 pops(ctx, 1);
5453 }
5454 #endif
5455
5456 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
5457 {
5458 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5459
5460 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
5461 * LOOP_STARTxxx for nested loops may put the branch stack into a state
5462 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
5463 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
5464 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
5465 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
5466 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5467 alu_type = CF_OP_ALU;
5468 }
5469
5470 emit_logic_pred(ctx, opcode, alu_type);
5471
5472 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5473
5474 fc_pushlevel(ctx, FC_IF);
5475
5476 callstack_push(ctx, FC_PUSH_VPM);
5477 return 0;
5478 }
5479
5480 static int tgsi_if(struct r600_shader_ctx *ctx)
5481 {
5482 return emit_if(ctx, ALU_OP2_PRED_SETNE);
5483 }
5484
5485 static int tgsi_uif(struct r600_shader_ctx *ctx)
5486 {
5487 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
5488 }
5489
5490 static int tgsi_else(struct r600_shader_ctx *ctx)
5491 {
5492 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5493 ctx->bc->cf_last->pop_count = 1;
5494
5495 fc_set_mid(ctx, ctx->bc->fc_sp);
5496 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5497 return 0;
5498 }
5499
5500 static int tgsi_endif(struct r600_shader_ctx *ctx)
5501 {
5502 pops(ctx, 1);
5503 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5504 R600_ERR("if/endif unbalanced in shader\n");
5505 return -1;
5506 }
5507
5508 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5509 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5510 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5511 } else {
5512 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5513 }
5514 fc_poplevel(ctx);
5515
5516 callstack_pop(ctx, FC_PUSH_VPM);
5517 return 0;
5518 }
5519
5520 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5521 {
5522 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5523 * limited to 4096 iterations, like the other LOOP_* instructions. */
5524 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5525
5526 fc_pushlevel(ctx, FC_LOOP);
5527
5528 /* check stack depth */
5529 callstack_push(ctx, FC_LOOP);
5530 return 0;
5531 }
5532
5533 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5534 {
5535 int i;
5536
5537 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5538
5539 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5540 R600_ERR("loop/endloop in shader code are not paired.\n");
5541 return -EINVAL;
5542 }
5543
5544 /* fixup loop pointers - from r600isa
5545 LOOP END points to CF after LOOP START,
5546 LOOP START point to CF after LOOP END
5547 BRK/CONT point to LOOP END CF
5548 */
5549 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5550
5551 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5552
5553 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5554 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5555 }
5556 /* XXX add LOOPRET support */
5557 fc_poplevel(ctx);
5558 callstack_pop(ctx, FC_LOOP);
5559 return 0;
5560 }
5561
5562 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5563 {
5564 unsigned int fscp;
5565
5566 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5567 {
5568 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5569 break;
5570 }
5571
5572 if (fscp == 0) {
5573 R600_ERR("Break not inside loop/endloop pair\n");
5574 return -EINVAL;
5575 }
5576
5577 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5578
5579 fc_set_mid(ctx, fscp);
5580
5581 return 0;
5582 }
5583
5584 static int tgsi_umad(struct r600_shader_ctx *ctx)
5585 {
5586 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5587 struct r600_bytecode_alu alu;
5588 int i, j, k, r;
5589 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5590
5591 /* src0 * src1 */
5592 for (i = 0; i < lasti + 1; i++) {
5593 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5594 continue;
5595
5596 if (ctx->bc->chip_class == CAYMAN) {
5597 for (j = 0 ; j < 4; j++) {
5598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5599
5600 alu.op = ALU_OP2_MULLO_UINT;
5601 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
5602 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
5603 }
5604 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
5605 alu.dst.sel = ctx->temp_reg;
5606 alu.dst.write = (j == i);
5607 if (j == 3)
5608 alu.last = 1;
5609 r = r600_bytecode_add_alu(ctx->bc, &alu);
5610 if (r)
5611 return r;
5612 }
5613 } else {
5614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5615
5616 alu.dst.chan = i;
5617 alu.dst.sel = ctx->temp_reg;
5618 alu.dst.write = 1;
5619
5620 alu.op = ALU_OP2_MULLO_UINT;
5621 for (j = 0; j < 2; j++) {
5622 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5623 }
5624
5625 alu.last = 1;
5626 r = r600_bytecode_add_alu(ctx->bc, &alu);
5627 if (r)
5628 return r;
5629 }
5630 }
5631
5632
5633 for (i = 0; i < lasti + 1; i++) {
5634 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5635 continue;
5636
5637 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5638 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5639
5640 alu.op = ALU_OP2_ADD_INT;
5641
5642 alu.src[0].sel = ctx->temp_reg;
5643 alu.src[0].chan = i;
5644
5645 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5646 if (i == lasti) {
5647 alu.last = 1;
5648 }
5649 r = r600_bytecode_add_alu(ctx->bc, &alu);
5650 if (r)
5651 return r;
5652 }
5653 return 0;
5654 }
5655
5656 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5657 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
5658 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5659 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5660
5661 /* XXX:
5662 * For state trackers other than OpenGL, we'll want to use
5663 * _RECIP_IEEE instead.
5664 */
5665 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5666
5667 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
5668 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5669 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5670 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5671 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5672 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5673 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5674 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5675 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5676 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5677 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5678 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5679 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5680 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5681 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5682 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5683 /* gap */
5684 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5685 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5686 /* gap */
5687 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5688 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5689 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5690 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5691 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5692 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5693 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5694 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5695 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5696 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5697 /* gap */
5698 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5699 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5700 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5701 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5702 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5703 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5704 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5705 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
5706 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5707 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5708 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5709 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5710 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5711 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5712 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5713 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5714 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5715 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5716 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5717 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5718 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5719 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5720 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5721 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5722 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5723 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5724 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5725 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5726 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5727 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
5728 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5729 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5730 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5731 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5732 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5733 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5734 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5735 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5736 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5737 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5738 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5739 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5740 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5741 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5742 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5743 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5744 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5745 /* gap */
5746 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5747 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5748 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5749 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5750 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5751 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5752 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5753 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5754 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
5755 /* gap */
5756 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5757 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5758 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5759 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5760 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5761 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5762 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5763 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5764 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5765 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5766 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5767 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5768 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5769 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5770 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5771 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5772 /* gap */
5773 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5774 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5775 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5776 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5777 /* gap */
5778 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
5779 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
5780 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
5781 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
5782 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5783 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5784 /* gap */
5785 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5786 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5787 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5788 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5789 /* gap */
5790 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5791 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
5792 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5793 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5794 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5795 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5796 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5797 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
5798 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5799 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
5800 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5801 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5802 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5803 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5804 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5805 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5806 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5807 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5808 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5809 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
5810 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
5811 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
5812 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
5813 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5814 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
5815 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
5816 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5817 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5818 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5819 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5820 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5821 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5822 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5823 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5824 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5825 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5826 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5827 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5828 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5829 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
5830 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
5831 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5832 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5833 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5834 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
5835 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5836 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5837 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5838 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
5839 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
5840 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
5841 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
5842 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
5843 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5844 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5845 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5846 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5847 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5848 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5849 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
5850 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5851 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5852 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
5853 };
5854
5855 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
5856 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
5857 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5858 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5859 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
5860 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
5861 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5862 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5863 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5864 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5865 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5866 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5867 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5868 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5869 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5870 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5871 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5872 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5873 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5874 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5875 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5876 /* gap */
5877 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5878 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5879 /* gap */
5880 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5881 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5882 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5883 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5884 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5885 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5886 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5887 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5888 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5889 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5890 /* gap */
5891 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5892 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5893 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5894 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5895 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5896 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5897 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5898 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
5899 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5900 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5901 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5902 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5903 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5904 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5905 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5906 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5907 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5908 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5909 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5910 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5911 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5912 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5913 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5914 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5915 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5916 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5917 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5918 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5919 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5920 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
5921 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5922 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5923 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5924 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5925 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5926 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5927 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5928 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5929 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5930 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5931 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5932 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5933 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5934 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5935 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5936 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5937 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5938 /* gap */
5939 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5940 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5941 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5942 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5943 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5944 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5945 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5946 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5947 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
5948 /* gap */
5949 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5950 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5951 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5952 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5953 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5954 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5955 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5956 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5957 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5958 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5959 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5960 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5961 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5962 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5963 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5964 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5965 /* gap */
5966 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5967 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5968 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5969 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5970 /* gap */
5971 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
5972 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
5973 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
5974 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
5975 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5976 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5977 /* gap */
5978 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5979 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5980 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5981 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5982 /* gap */
5983 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5984 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
5985 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5986 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5987 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5988 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5989 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5990 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
5991 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5992 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
5993 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5994 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5995 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5996 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5997 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5998 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5999 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6000 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6001 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6002 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6003 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6004 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6005 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6006 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6007 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6008 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6009 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6010 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6011 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6012 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6013 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6014 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6015 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6016 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6017 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6018 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6019 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6020 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6021 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6022 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6023 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6024 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6025 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6026 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6027 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6028 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6029 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6030 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6031 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6032 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6033 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6034 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6035 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6036 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6037 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6038 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6039 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6040 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6041 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6042 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6043 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6044 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6045 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6046 };
6047
6048 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6049 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6050 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6051 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6052 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6053 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6054 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6055 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6056 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6057 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6058 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6059 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6060 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6061 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6062 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6063 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6064 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6065 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6066 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6067 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6068 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6069 /* gap */
6070 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6071 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6072 /* gap */
6073 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6074 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6075 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6076 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6077 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6078 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6079 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6080 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6081 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6082 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6083 /* gap */
6084 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6085 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6086 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6087 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6088 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6089 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6090 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6091 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6092 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6093 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6094 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6095 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6096 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6097 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6098 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6099 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6100 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6101 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6102 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6103 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6104 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6105 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6106 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6107 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6108 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6109 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6110 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6111 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6112 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6113 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6114 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6115 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6116 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6117 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6118 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6119 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6120 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6121 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6122 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6123 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6124 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6125 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6126 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6127 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6128 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6129 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6130 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6131 /* gap */
6132 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6133 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6134 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6135 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6136 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6137 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6138 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6139 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6140 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6141 /* gap */
6142 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6143 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6144 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6145 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6146 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6147 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6148 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6149 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6150 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6151 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6152 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6153 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6154 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6155 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6156 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6157 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6158 /* gap */
6159 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6160 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6161 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6162 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6163 /* gap */
6164 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6165 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6166 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6167 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6168 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6169 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6170 /* gap */
6171 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6172 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6173 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6174 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6175 /* gap */
6176 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6177 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6178 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6179 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6180 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6181 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6182 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6183 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6184 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6185 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6186 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6187 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6188 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6189 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6190 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6191 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6192 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6193 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6194 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6195 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6196 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6197 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6198 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6199 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6200 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6201 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6202 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6203 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6204 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6205 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6206 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6207 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6208 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6209 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6210 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6211 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6212 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6213 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6214 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6215 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6216 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6217 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6218 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6219 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6220 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6221 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6222 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6223 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6224 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6225 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6226 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6227 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6228 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6229 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6230 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6231 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6232 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6233 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6234 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6235 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6236 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6237 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6238 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6239 };