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r600g: Silence uninitialized variable warnings.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
31 #include "r600_asm.h"
32 #include "r600_sq.h"
33 #include "r600_opcodes.h"
34 #include "r600d.h"
35 #include <stdio.h>
36 #include <errno.h>
37
38
39 struct r600_shader_tgsi_instruction;
40
41 struct r600_shader_ctx {
42 struct tgsi_shader_info info;
43 struct tgsi_parse_context parse;
44 const struct tgsi_token *tokens;
45 unsigned type;
46 unsigned file_offset[TGSI_FILE_COUNT];
47 unsigned temp_reg;
48 struct r600_shader_tgsi_instruction *inst_info;
49 struct r600_bc *bc;
50 struct r600_shader *shader;
51 u32 value[4];
52 u32 *literals;
53 u32 nliterals;
54 u32 max_driver_temp_used;
55 };
56
57 struct r600_shader_tgsi_instruction {
58 unsigned tgsi_opcode;
59 unsigned is_op3;
60 unsigned r600_opcode;
61 int (*process)(struct r600_shader_ctx *ctx);
62 };
63
64 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
65 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
66
67 /* called from hw states files to find VS->FS mapping */
68 int r600_find_vs_semantic_index(struct r600_context *rctx, struct r600_shader *rshader, int id)
69 {
70 int i;
71 struct r600_shader *vs = &rctx->vs_shader->shader;
72 struct r600_shader_io *input = &rshader->input[id];
73
74 for (i = 0; i < vs->noutput; i++) {
75 if (input->name == vs->output[i].name &&
76 input->sid == vs->output[i].sid) {
77 return i - 1;
78 }
79 }
80 return 0;
81 }
82
83 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
84 {
85 struct r600_context *rctx = r600_context(ctx);
86 const struct util_format_description *desc;
87 enum pipe_format resource_format[160];
88 unsigned i, nresources = 0;
89 struct r600_bc *bc = &shader->bc;
90 struct r600_bc_cf *cf;
91 struct r600_bc_vtx *vtx;
92
93 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
94 return 0;
95 for (i = 0; i < rctx->vertex_elements->count; i++) {
96 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
97 }
98 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
99 switch (cf->inst) {
100 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
101 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
102 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
103 desc = util_format_description(resource_format[vtx->buffer_id]);
104 if (desc == NULL) {
105 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
106 return -EINVAL;
107 }
108 vtx->dst_sel_x = desc->swizzle[0];
109 vtx->dst_sel_y = desc->swizzle[1];
110 vtx->dst_sel_z = desc->swizzle[2];
111 vtx->dst_sel_w = desc->swizzle[3];
112 }
113 break;
114 default:
115 break;
116 }
117 }
118 return r600_bc_build(&shader->bc);
119 }
120
121 int r600_pipe_shader_create(struct pipe_context *ctx,
122 struct r600_context_state *rpshader,
123 const struct tgsi_token *tokens)
124 {
125 struct r600_screen *rscreen = r600_screen(ctx->screen);
126 int r;
127
128 //fprintf(stderr, "--------------------------------------------------------------\n");
129 //tgsi_dump(tokens, 0);
130 if (rpshader == NULL)
131 return -ENOMEM;
132 rpshader->shader.family = radeon_get_family(rscreen->rw);
133 rpshader->shader.use_mem_constant = rscreen->use_mem_constant;
134 r = r600_shader_from_tgsi(tokens, &rpshader->shader);
135 if (r) {
136 R600_ERR("translation from TGSI failed !\n");
137 return r;
138 }
139 r = r600_bc_build(&rpshader->shader.bc);
140 if (r) {
141 R600_ERR("building bytecode failed !\n");
142 return r;
143 }
144 //fprintf(stderr, "______________________________________________________________\n");
145 return 0;
146 }
147
148 static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
149 {
150 struct r600_context *rctx = r600_context(ctx);
151 struct radeon_state *state;
152
153 state = &rpshader->rstate[0];
154 radeon_state_fini(&rpshader->rstate[0]);
155
156 return rctx->vtbl->vs_shader(rctx, rpshader, state);
157 }
158
159 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
160 {
161 struct r600_context *rctx = r600_context(ctx);
162 struct radeon_state *state;
163
164 state = &rpshader->rstate[0];
165 radeon_state_fini(state);
166
167 return rctx->vtbl->ps_shader(rctx, rpshader, state);
168 }
169
170 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
171 {
172 struct r600_screen *rscreen = r600_screen(ctx->screen);
173 struct r600_context *rctx = r600_context(ctx);
174 struct r600_shader *rshader = &rpshader->shader;
175 int r;
176 void *data;
177
178 /* copy new shader */
179 radeon_ws_bo_reference(rscreen->rw, &rpshader->bo, NULL);
180 rpshader->bo = NULL;
181 rpshader->bo = radeon_ws_bo(rscreen->rw, rshader->bc.ndw * 4,
182 4096, 0);
183 if (rpshader->bo == NULL) {
184 return -ENOMEM;
185 }
186 data = radeon_ws_bo_map(rscreen->rw, rpshader->bo, 0, ctx);
187 memcpy(data, rshader->bc.bytecode, rshader->bc.ndw * 4);
188 radeon_ws_bo_unmap(rscreen->rw, rpshader->bo);
189 /* build state */
190 rshader->flat_shade = rctx->flat_shade;
191 switch (rshader->processor_type) {
192 case TGSI_PROCESSOR_VERTEX:
193 r = r600_pipe_shader_vs(ctx, rpshader);
194 break;
195 case TGSI_PROCESSOR_FRAGMENT:
196 r = r600_pipe_shader_ps(ctx, rpshader);
197 break;
198 default:
199 r = -EINVAL;
200 break;
201 }
202 return r;
203 }
204
205 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
206 {
207 struct r600_context *rctx = r600_context(ctx);
208 int r;
209
210 if (rpshader == NULL)
211 return -EINVAL;
212 /* there should be enough input */
213 if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
214 R600_ERR("%d resources provided, expecting %d\n",
215 rctx->vertex_elements->count, rpshader->shader.bc.nresource);
216 return -EINVAL;
217 }
218 r = r600_shader_update(ctx, &rpshader->shader);
219 if (r)
220 return r;
221 return r600_pipe_shader(ctx, rpshader);
222 }
223
224 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
225 {
226 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
227 int j;
228
229 if (i->Instruction.NumDstRegs > 1) {
230 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
231 return -EINVAL;
232 }
233 if (i->Instruction.Predicate) {
234 R600_ERR("predicate unsupported\n");
235 return -EINVAL;
236 }
237 #if 0
238 if (i->Instruction.Label) {
239 R600_ERR("label unsupported\n");
240 return -EINVAL;
241 }
242 #endif
243 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
244 if (i->Src[j].Register.Dimension ||
245 i->Src[j].Register.Absolute) {
246 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
247 i->Src[j].Register.Dimension,
248 i->Src[j].Register.Absolute);
249 return -EINVAL;
250 }
251 }
252 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
253 if (i->Dst[j].Register.Dimension) {
254 R600_ERR("unsupported dst (dimension)\n");
255 return -EINVAL;
256 }
257 }
258 return 0;
259 }
260
261 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
262 {
263 int i, r;
264 struct r600_bc_alu alu;
265
266 for (i = 0; i < 8; i++) {
267 memset(&alu, 0, sizeof(struct r600_bc_alu));
268
269 if (i < 4)
270 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
271 else
272 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
273
274 if ((i > 1) && (i < 6)) {
275 alu.dst.sel = ctx->shader->input[gpr].gpr;
276 alu.dst.write = 1;
277 }
278
279 alu.dst.chan = i % 4;
280 alu.src[0].chan = (1 - (i % 2));
281 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
282
283 alu.bank_swizzle_force = SQ_ALU_VEC_210;
284 if ((i % 4) == 3)
285 alu.last = 1;
286 r = r600_bc_add_alu(ctx->bc, &alu);
287 if (r)
288 return r;
289 }
290 return 0;
291 }
292
293
294 static int tgsi_declaration(struct r600_shader_ctx *ctx)
295 {
296 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
297 struct r600_bc_vtx vtx;
298 unsigned i;
299 int r;
300
301 switch (d->Declaration.File) {
302 case TGSI_FILE_INPUT:
303 i = ctx->shader->ninput++;
304 ctx->shader->input[i].name = d->Semantic.Name;
305 ctx->shader->input[i].sid = d->Semantic.Index;
306 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
307 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
308 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
309 /* turn input into fetch */
310 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
311 vtx.inst = 0;
312 vtx.fetch_type = 0;
313 vtx.buffer_id = i;
314 /* register containing the index into the buffer */
315 vtx.src_gpr = 0;
316 vtx.src_sel_x = 0;
317 vtx.mega_fetch_count = 0x1F;
318 vtx.dst_gpr = ctx->shader->input[i].gpr;
319 vtx.dst_sel_x = 0;
320 vtx.dst_sel_y = 1;
321 vtx.dst_sel_z = 2;
322 vtx.dst_sel_w = 3;
323 r = r600_bc_add_vtx(ctx->bc, &vtx);
324 if (r)
325 return r;
326 }
327 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
328 /* turn input into interpolate on EG */
329 evergreen_interp_alu(ctx, i);
330 }
331 break;
332 case TGSI_FILE_OUTPUT:
333 i = ctx->shader->noutput++;
334 ctx->shader->output[i].name = d->Semantic.Name;
335 ctx->shader->output[i].sid = d->Semantic.Index;
336 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
337 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
338 break;
339 case TGSI_FILE_CONSTANT:
340 case TGSI_FILE_TEMPORARY:
341 case TGSI_FILE_SAMPLER:
342 case TGSI_FILE_ADDRESS:
343 break;
344 default:
345 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
346 return -EINVAL;
347 }
348 return 0;
349 }
350
351 static int r600_get_temp(struct r600_shader_ctx *ctx)
352 {
353 return ctx->temp_reg + ctx->max_driver_temp_used++;
354 }
355
356 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
357 {
358 struct tgsi_full_immediate *immediate;
359 struct r600_shader_ctx ctx;
360 struct r600_bc_output output[32];
361 unsigned output_done, noutput;
362 unsigned opcode;
363 int i, r = 0, pos0;
364
365 ctx.bc = &shader->bc;
366 ctx.shader = shader;
367 r = r600_bc_init(ctx.bc, shader->family);
368 if (r)
369 return r;
370 ctx.bc->use_mem_constant = shader->use_mem_constant;
371 ctx.tokens = tokens;
372 tgsi_scan_shader(tokens, &ctx.info);
373 tgsi_parse_init(&ctx.parse, tokens);
374 ctx.type = ctx.parse.FullHeader.Processor.Processor;
375 shader->processor_type = ctx.type;
376
377 /* register allocations */
378 /* Values [0,127] correspond to GPR[0..127].
379 * Values [128,159] correspond to constant buffer bank 0
380 * Values [160,191] correspond to constant buffer bank 1
381 * Values [256,511] correspond to cfile constants c[0..255].
382 * Other special values are shown in the list below.
383 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
384 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
385 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
386 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
387 * 248 SQ_ALU_SRC_0: special constant 0.0.
388 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
389 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
390 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
391 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
392 * 253 SQ_ALU_SRC_LITERAL: literal constant.
393 * 254 SQ_ALU_SRC_PV: previous vector result.
394 * 255 SQ_ALU_SRC_PS: previous scalar result.
395 */
396 for (i = 0; i < TGSI_FILE_COUNT; i++) {
397 ctx.file_offset[i] = 0;
398 }
399 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
400 ctx.file_offset[TGSI_FILE_INPUT] = 1;
401 }
402 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
403 ctx.info.file_count[TGSI_FILE_INPUT];
404 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
405 ctx.info.file_count[TGSI_FILE_OUTPUT];
406 if (ctx.shader->use_mem_constant)
407 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
408 else
409 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
410
411 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
412 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
413 ctx.info.file_count[TGSI_FILE_TEMPORARY];
414
415 ctx.nliterals = 0;
416 ctx.literals = NULL;
417
418 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
419 tgsi_parse_token(&ctx.parse);
420 switch (ctx.parse.FullToken.Token.Type) {
421 case TGSI_TOKEN_TYPE_IMMEDIATE:
422 immediate = &ctx.parse.FullToken.FullImmediate;
423 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
424 if(ctx.literals == NULL) {
425 r = -ENOMEM;
426 goto out_err;
427 }
428 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
429 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
430 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
431 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
432 ctx.nliterals++;
433 break;
434 case TGSI_TOKEN_TYPE_DECLARATION:
435 r = tgsi_declaration(&ctx);
436 if (r)
437 goto out_err;
438 break;
439 case TGSI_TOKEN_TYPE_INSTRUCTION:
440 r = tgsi_is_supported(&ctx);
441 if (r)
442 goto out_err;
443 ctx.max_driver_temp_used = 0;
444 /* reserve first tmp for everyone */
445 r600_get_temp(&ctx);
446 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
447 if (ctx.bc->chiprev == 2)
448 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
449 else
450 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
451 r = ctx.inst_info->process(&ctx);
452 if (r)
453 goto out_err;
454 r = r600_bc_add_literal(ctx.bc, ctx.value);
455 if (r)
456 goto out_err;
457 break;
458 default:
459 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
460 r = -EINVAL;
461 goto out_err;
462 }
463 }
464 /* export output */
465 noutput = shader->noutput;
466 for (i = 0, pos0 = 0; i < noutput; i++) {
467 memset(&output[i], 0, sizeof(struct r600_bc_output));
468 output[i].gpr = shader->output[i].gpr;
469 output[i].elem_size = 3;
470 output[i].swizzle_x = 0;
471 output[i].swizzle_y = 1;
472 output[i].swizzle_z = 2;
473 output[i].swizzle_w = 3;
474 output[i].barrier = 1;
475 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
476 output[i].array_base = i - pos0;
477 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
478 switch (ctx.type) {
479 case TGSI_PROCESSOR_VERTEX:
480 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
481 output[i].array_base = 60;
482 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
483 /* position doesn't count in array_base */
484 pos0++;
485 }
486 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
487 output[i].array_base = 61;
488 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
489 /* position doesn't count in array_base */
490 pos0++;
491 }
492 break;
493 case TGSI_PROCESSOR_FRAGMENT:
494 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
495 output[i].array_base = shader->output[i].sid;
496 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
497 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
498 output[i].array_base = 61;
499 output[i].swizzle_x = 2;
500 output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
501 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
502 } else {
503 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
504 r = -EINVAL;
505 goto out_err;
506 }
507 break;
508 default:
509 R600_ERR("unsupported processor type %d\n", ctx.type);
510 r = -EINVAL;
511 goto out_err;
512 }
513 }
514 /* add fake param output for vertex shader if no param is exported */
515 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
516 for (i = 0, pos0 = 0; i < noutput; i++) {
517 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
518 pos0 = 1;
519 break;
520 }
521 }
522 if (!pos0) {
523 memset(&output[i], 0, sizeof(struct r600_bc_output));
524 output[i].gpr = 0;
525 output[i].elem_size = 3;
526 output[i].swizzle_x = 0;
527 output[i].swizzle_y = 1;
528 output[i].swizzle_z = 2;
529 output[i].swizzle_w = 3;
530 output[i].barrier = 1;
531 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
532 output[i].array_base = 0;
533 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
534 noutput++;
535 }
536 }
537 /* add fake pixel export */
538 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
539 memset(&output[0], 0, sizeof(struct r600_bc_output));
540 output[0].gpr = 0;
541 output[0].elem_size = 3;
542 output[0].swizzle_x = 7;
543 output[0].swizzle_y = 7;
544 output[0].swizzle_z = 7;
545 output[0].swizzle_w = 7;
546 output[0].barrier = 1;
547 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
548 output[0].array_base = 0;
549 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
550 noutput++;
551 }
552 /* set export done on last export of each type */
553 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
554 if (i == (noutput - 1)) {
555 output[i].end_of_program = 1;
556 }
557 if (!(output_done & (1 << output[i].type))) {
558 output_done |= (1 << output[i].type);
559 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
560 }
561 }
562 /* add output to bytecode */
563 for (i = 0; i < noutput; i++) {
564 r = r600_bc_add_output(ctx.bc, &output[i]);
565 if (r)
566 goto out_err;
567 }
568 free(ctx.literals);
569 tgsi_parse_free(&ctx.parse);
570 return 0;
571 out_err:
572 free(ctx.literals);
573 tgsi_parse_free(&ctx.parse);
574 return r;
575 }
576
577 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
578 {
579 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
580 return -EINVAL;
581 }
582
583 static int tgsi_end(struct r600_shader_ctx *ctx)
584 {
585 return 0;
586 }
587
588 static int tgsi_src(struct r600_shader_ctx *ctx,
589 const struct tgsi_full_src_register *tgsi_src,
590 struct r600_bc_alu_src *r600_src)
591 {
592 int index;
593 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
594 r600_src->sel = tgsi_src->Register.Index;
595 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
596 r600_src->sel = 0;
597 index = tgsi_src->Register.Index;
598 ctx->value[0] = ctx->literals[index * 4 + 0];
599 ctx->value[1] = ctx->literals[index * 4 + 1];
600 ctx->value[2] = ctx->literals[index * 4 + 2];
601 ctx->value[3] = ctx->literals[index * 4 + 3];
602 }
603 if (tgsi_src->Register.Indirect)
604 r600_src->rel = V_SQ_REL_RELATIVE;
605 r600_src->neg = tgsi_src->Register.Negate;
606 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
607 return 0;
608 }
609
610 static int tgsi_dst(struct r600_shader_ctx *ctx,
611 const struct tgsi_full_dst_register *tgsi_dst,
612 unsigned swizzle,
613 struct r600_bc_alu_dst *r600_dst)
614 {
615 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
616
617 r600_dst->sel = tgsi_dst->Register.Index;
618 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
619 r600_dst->chan = swizzle;
620 r600_dst->write = 1;
621 if (tgsi_dst->Register.Indirect)
622 r600_dst->rel = V_SQ_REL_RELATIVE;
623 if (inst->Instruction.Saturate) {
624 r600_dst->clamp = 1;
625 }
626 return 0;
627 }
628
629 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
630 {
631 switch (swizzle) {
632 case 0:
633 return tgsi_src->Register.SwizzleX;
634 case 1:
635 return tgsi_src->Register.SwizzleY;
636 case 2:
637 return tgsi_src->Register.SwizzleZ;
638 case 3:
639 return tgsi_src->Register.SwizzleW;
640 default:
641 return 0;
642 }
643 }
644
645 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
646 {
647 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
648 struct r600_bc_alu alu;
649 int i, j, k, nconst, r;
650
651 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
652 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
653 nconst++;
654 }
655 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
656 if (r) {
657 return r;
658 }
659 }
660 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
661 if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
662 int treg = r600_get_temp(ctx);
663 for (k = 0; k < 4; k++) {
664 memset(&alu, 0, sizeof(struct r600_bc_alu));
665 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
666 alu.src[0].sel = r600_src[j].sel;
667 alu.src[0].chan = k;
668 alu.dst.sel = treg;
669 alu.dst.chan = k;
670 alu.dst.write = 1;
671 if (k == 3)
672 alu.last = 1;
673 r = r600_bc_add_alu(ctx->bc, &alu);
674 if (r)
675 return r;
676 }
677 r600_src[j].sel = treg;
678 j--;
679 }
680 }
681 return 0;
682 }
683
684 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
685 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
686 {
687 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
688 struct r600_bc_alu alu;
689 int i, j, k, nliteral, r;
690
691 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
692 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
693 nliteral++;
694 }
695 }
696 for (i = 0, j = 0; i < inst->Instruction.NumSrcRegs; i++) {
697 if (inst->Src[j].Register.File == TGSI_FILE_IMMEDIATE) {
698 int treg = r600_get_temp(ctx);
699 for (k = 0; k < 4; k++) {
700 memset(&alu, 0, sizeof(struct r600_bc_alu));
701 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
702 alu.src[0].sel = r600_src[j].sel;
703 alu.src[0].chan = k;
704 alu.dst.sel = treg;
705 alu.dst.chan = k;
706 alu.dst.write = 1;
707 if (k == 3)
708 alu.last = 1;
709 r = r600_bc_add_alu(ctx->bc, &alu);
710 if (r)
711 return r;
712 }
713 r = r600_bc_add_literal(ctx->bc, ctx->value);
714 if (r)
715 return r;
716 r600_src[j].sel = treg;
717 j++;
718 }
719 }
720 return 0;
721 }
722
723 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
724 {
725 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
726 struct r600_bc_alu_src r600_src[3];
727 struct r600_bc_alu alu;
728 int i, j, r;
729 int lasti = 0;
730
731 for (i = 0; i < 4; i++) {
732 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
733 lasti = i;
734 }
735 }
736
737 r = tgsi_split_constant(ctx, r600_src);
738 if (r)
739 return r;
740 for (i = 0; i < lasti + 1; i++) {
741 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
742 continue;
743
744 memset(&alu, 0, sizeof(struct r600_bc_alu));
745 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
746 if (r)
747 return r;
748
749 alu.inst = ctx->inst_info->r600_opcode;
750 if (!swap) {
751 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
752 alu.src[j] = r600_src[j];
753 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
754 }
755 } else {
756 alu.src[0] = r600_src[1];
757 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
758
759 alu.src[1] = r600_src[0];
760 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
761 }
762 /* handle some special cases */
763 switch (ctx->inst_info->tgsi_opcode) {
764 case TGSI_OPCODE_SUB:
765 alu.src[1].neg = 1;
766 break;
767 case TGSI_OPCODE_ABS:
768 alu.src[0].abs = 1;
769 break;
770 default:
771 break;
772 }
773 if (i == lasti) {
774 alu.last = 1;
775 }
776 r = r600_bc_add_alu(ctx->bc, &alu);
777 if (r)
778 return r;
779 }
780 return 0;
781 }
782
783 static int tgsi_op2(struct r600_shader_ctx *ctx)
784 {
785 return tgsi_op2_s(ctx, 0);
786 }
787
788 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
789 {
790 return tgsi_op2_s(ctx, 1);
791 }
792
793 /*
794 * r600 - trunc to -PI..PI range
795 * r700 - normalize by dividing by 2PI
796 * see fdo bug 27901
797 */
798 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
799 struct r600_bc_alu_src r600_src[3])
800 {
801 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
802 int r;
803 uint32_t lit_vals[4];
804 struct r600_bc_alu alu;
805
806 memset(lit_vals, 0, 4*4);
807 r = tgsi_split_constant(ctx, r600_src);
808 if (r)
809 return r;
810
811 r = tgsi_split_literal_constant(ctx, r600_src);
812 if (r)
813 return r;
814
815 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
816 lit_vals[1] = fui(0.5f);
817
818 memset(&alu, 0, sizeof(struct r600_bc_alu));
819 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
820 alu.is_op3 = 1;
821
822 alu.dst.chan = 0;
823 alu.dst.sel = ctx->temp_reg;
824 alu.dst.write = 1;
825
826 alu.src[0] = r600_src[0];
827 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
828
829 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
830 alu.src[1].chan = 0;
831 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
832 alu.src[2].chan = 1;
833 alu.last = 1;
834 r = r600_bc_add_alu(ctx->bc, &alu);
835 if (r)
836 return r;
837 r = r600_bc_add_literal(ctx->bc, lit_vals);
838 if (r)
839 return r;
840
841 memset(&alu, 0, sizeof(struct r600_bc_alu));
842 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
843
844 alu.dst.chan = 0;
845 alu.dst.sel = ctx->temp_reg;
846 alu.dst.write = 1;
847
848 alu.src[0].sel = ctx->temp_reg;
849 alu.src[0].chan = 0;
850 alu.last = 1;
851 r = r600_bc_add_alu(ctx->bc, &alu);
852 if (r)
853 return r;
854
855 if (ctx->bc->chiprev == 0) {
856 lit_vals[0] = fui(3.1415926535897f * 2.0f);
857 lit_vals[1] = fui(-3.1415926535897f);
858 } else {
859 lit_vals[0] = fui(1.0f);
860 lit_vals[1] = fui(-0.5f);
861 }
862
863 memset(&alu, 0, sizeof(struct r600_bc_alu));
864 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
865 alu.is_op3 = 1;
866
867 alu.dst.chan = 0;
868 alu.dst.sel = ctx->temp_reg;
869 alu.dst.write = 1;
870
871 alu.src[0].sel = ctx->temp_reg;
872 alu.src[0].chan = 0;
873
874 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
875 alu.src[1].chan = 0;
876 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
877 alu.src[2].chan = 1;
878 alu.last = 1;
879 r = r600_bc_add_alu(ctx->bc, &alu);
880 if (r)
881 return r;
882 r = r600_bc_add_literal(ctx->bc, lit_vals);
883 if (r)
884 return r;
885 return 0;
886 }
887
888 static int tgsi_trig(struct r600_shader_ctx *ctx)
889 {
890 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
891 struct r600_bc_alu_src r600_src[3];
892 struct r600_bc_alu alu;
893 int i, r;
894 int lasti = 0;
895
896 r = tgsi_setup_trig(ctx, r600_src);
897 if (r)
898 return r;
899
900 memset(&alu, 0, sizeof(struct r600_bc_alu));
901 alu.inst = ctx->inst_info->r600_opcode;
902 alu.dst.chan = 0;
903 alu.dst.sel = ctx->temp_reg;
904 alu.dst.write = 1;
905
906 alu.src[0].sel = ctx->temp_reg;
907 alu.src[0].chan = 0;
908 alu.last = 1;
909 r = r600_bc_add_alu(ctx->bc, &alu);
910 if (r)
911 return r;
912
913 /* replicate result */
914 for (i = 0; i < 4; i++) {
915 if (inst->Dst[0].Register.WriteMask & (1 << i))
916 lasti = i;
917 }
918 for (i = 0; i < lasti + 1; i++) {
919 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
920 continue;
921
922 memset(&alu, 0, sizeof(struct r600_bc_alu));
923 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
924
925 alu.src[0].sel = ctx->temp_reg;
926 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
927 if (r)
928 return r;
929 if (i == lasti)
930 alu.last = 1;
931 r = r600_bc_add_alu(ctx->bc, &alu);
932 if (r)
933 return r;
934 }
935 return 0;
936 }
937
938 static int tgsi_scs(struct r600_shader_ctx *ctx)
939 {
940 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
941 struct r600_bc_alu_src r600_src[3];
942 struct r600_bc_alu alu;
943 int r;
944
945 /* We'll only need the trig stuff if we are going to write to the
946 * X or Y components of the destination vector.
947 */
948 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
949 r = tgsi_setup_trig(ctx, r600_src);
950 if (r)
951 return r;
952 }
953
954 /* dst.x = COS */
955 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
956 memset(&alu, 0, sizeof(struct r600_bc_alu));
957 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
958 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
959 if (r)
960 return r;
961
962 alu.src[0].sel = ctx->temp_reg;
963 alu.src[0].chan = 0;
964 alu.last = 1;
965 r = r600_bc_add_alu(ctx->bc, &alu);
966 if (r)
967 return r;
968 }
969
970 /* dst.y = SIN */
971 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
972 memset(&alu, 0, sizeof(struct r600_bc_alu));
973 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
974 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
975 if (r)
976 return r;
977
978 alu.src[0].sel = ctx->temp_reg;
979 alu.src[0].chan = 0;
980 alu.last = 1;
981 r = r600_bc_add_alu(ctx->bc, &alu);
982 if (r)
983 return r;
984 }
985
986 /* dst.z = 0.0; */
987 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
988 memset(&alu, 0, sizeof(struct r600_bc_alu));
989
990 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
991
992 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
993 if (r)
994 return r;
995
996 alu.src[0].sel = V_SQ_ALU_SRC_0;
997 alu.src[0].chan = 0;
998
999 alu.last = 1;
1000
1001 r = r600_bc_add_alu(ctx->bc, &alu);
1002 if (r)
1003 return r;
1004
1005 r = r600_bc_add_literal(ctx->bc, ctx->value);
1006 if (r)
1007 return r;
1008 }
1009
1010 /* dst.w = 1.0; */
1011 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1012 memset(&alu, 0, sizeof(struct r600_bc_alu));
1013
1014 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1015
1016 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1017 if (r)
1018 return r;
1019
1020 alu.src[0].sel = V_SQ_ALU_SRC_1;
1021 alu.src[0].chan = 0;
1022
1023 alu.last = 1;
1024
1025 r = r600_bc_add_alu(ctx->bc, &alu);
1026 if (r)
1027 return r;
1028
1029 r = r600_bc_add_literal(ctx->bc, ctx->value);
1030 if (r)
1031 return r;
1032 }
1033
1034 return 0;
1035 }
1036
1037 static int tgsi_kill(struct r600_shader_ctx *ctx)
1038 {
1039 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1040 struct r600_bc_alu alu;
1041 int i, r;
1042
1043 for (i = 0; i < 4; i++) {
1044 memset(&alu, 0, sizeof(struct r600_bc_alu));
1045 alu.inst = ctx->inst_info->r600_opcode;
1046
1047 alu.dst.chan = i;
1048
1049 alu.src[0].sel = V_SQ_ALU_SRC_0;
1050
1051 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1052 alu.src[1].sel = V_SQ_ALU_SRC_1;
1053 alu.src[1].neg = 1;
1054 } else {
1055 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1056 if (r)
1057 return r;
1058 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1059 }
1060 if (i == 3) {
1061 alu.last = 1;
1062 }
1063 r = r600_bc_add_alu(ctx->bc, &alu);
1064 if (r)
1065 return r;
1066 }
1067 r = r600_bc_add_literal(ctx->bc, ctx->value);
1068 if (r)
1069 return r;
1070
1071 /* kill must be last in ALU */
1072 ctx->bc->force_add_cf = 1;
1073 ctx->shader->uses_kill = TRUE;
1074 return 0;
1075 }
1076
1077 static int tgsi_lit(struct r600_shader_ctx *ctx)
1078 {
1079 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1080 struct r600_bc_alu alu;
1081 struct r600_bc_alu_src r600_src[3];
1082 int r;
1083
1084 r = tgsi_split_constant(ctx, r600_src);
1085 if (r)
1086 return r;
1087 r = tgsi_split_literal_constant(ctx, r600_src);
1088 if (r)
1089 return r;
1090
1091 /* dst.x, <- 1.0 */
1092 memset(&alu, 0, sizeof(struct r600_bc_alu));
1093 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1094 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1095 alu.src[0].chan = 0;
1096 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1097 if (r)
1098 return r;
1099 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1100 r = r600_bc_add_alu(ctx->bc, &alu);
1101 if (r)
1102 return r;
1103
1104 /* dst.y = max(src.x, 0.0) */
1105 memset(&alu, 0, sizeof(struct r600_bc_alu));
1106 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1107 alu.src[0] = r600_src[0];
1108 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1109 alu.src[1].chan = 0;
1110 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1111 if (r)
1112 return r;
1113 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1114 r = r600_bc_add_alu(ctx->bc, &alu);
1115 if (r)
1116 return r;
1117
1118 /* dst.w, <- 1.0 */
1119 memset(&alu, 0, sizeof(struct r600_bc_alu));
1120 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1121 alu.src[0].sel = V_SQ_ALU_SRC_1;
1122 alu.src[0].chan = 0;
1123 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1124 if (r)
1125 return r;
1126 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1127 alu.last = 1;
1128 r = r600_bc_add_alu(ctx->bc, &alu);
1129 if (r)
1130 return r;
1131
1132 r = r600_bc_add_literal(ctx->bc, ctx->value);
1133 if (r)
1134 return r;
1135
1136 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1137 {
1138 int chan;
1139 int sel;
1140
1141 /* dst.z = log(src.y) */
1142 memset(&alu, 0, sizeof(struct r600_bc_alu));
1143 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1144 alu.src[0] = r600_src[0];
1145 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1146 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1147 if (r)
1148 return r;
1149 alu.last = 1;
1150 r = r600_bc_add_alu(ctx->bc, &alu);
1151 if (r)
1152 return r;
1153
1154 r = r600_bc_add_literal(ctx->bc, ctx->value);
1155 if (r)
1156 return r;
1157
1158 chan = alu.dst.chan;
1159 sel = alu.dst.sel;
1160
1161 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1162 memset(&alu, 0, sizeof(struct r600_bc_alu));
1163 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1164 alu.src[0] = r600_src[0];
1165 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1166 alu.src[1].sel = sel;
1167 alu.src[1].chan = chan;
1168
1169 alu.src[2] = r600_src[0];
1170 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1171 alu.dst.sel = ctx->temp_reg;
1172 alu.dst.chan = 0;
1173 alu.dst.write = 1;
1174 alu.is_op3 = 1;
1175 alu.last = 1;
1176 r = r600_bc_add_alu(ctx->bc, &alu);
1177 if (r)
1178 return r;
1179
1180 r = r600_bc_add_literal(ctx->bc, ctx->value);
1181 if (r)
1182 return r;
1183 /* dst.z = exp(tmp.x) */
1184 memset(&alu, 0, sizeof(struct r600_bc_alu));
1185 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1186 alu.src[0].sel = ctx->temp_reg;
1187 alu.src[0].chan = 0;
1188 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1189 if (r)
1190 return r;
1191 alu.last = 1;
1192 r = r600_bc_add_alu(ctx->bc, &alu);
1193 if (r)
1194 return r;
1195 }
1196 return 0;
1197 }
1198
1199 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1200 {
1201 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1202 struct r600_bc_alu alu;
1203 int i, r;
1204
1205 memset(&alu, 0, sizeof(struct r600_bc_alu));
1206
1207 /* FIXME:
1208 * For state trackers other than OpenGL, we'll want to use
1209 * _RECIPSQRT_IEEE instead.
1210 */
1211 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1212
1213 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1214 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1215 if (r)
1216 return r;
1217 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1218 alu.src[i].abs = 1;
1219 }
1220 alu.dst.sel = ctx->temp_reg;
1221 alu.dst.write = 1;
1222 alu.last = 1;
1223 r = r600_bc_add_alu(ctx->bc, &alu);
1224 if (r)
1225 return r;
1226 r = r600_bc_add_literal(ctx->bc, ctx->value);
1227 if (r)
1228 return r;
1229 /* replicate result */
1230 return tgsi_helper_tempx_replicate(ctx);
1231 }
1232
1233 static int tgsi_trans(struct r600_shader_ctx *ctx)
1234 {
1235 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1236 struct r600_bc_alu alu;
1237 int i, j, r;
1238
1239 for (i = 0; i < 4; i++) {
1240 memset(&alu, 0, sizeof(struct r600_bc_alu));
1241 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
1242 alu.inst = ctx->inst_info->r600_opcode;
1243 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1244 r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
1245 if (r)
1246 return r;
1247 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1248 }
1249 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1250 if (r)
1251 return r;
1252 alu.last = 1;
1253 r = r600_bc_add_alu(ctx->bc, &alu);
1254 if (r)
1255 return r;
1256 }
1257 }
1258 return 0;
1259 }
1260
1261 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1262 {
1263 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1264 struct r600_bc_alu alu;
1265 int i, r;
1266
1267 for (i = 0; i < 4; i++) {
1268 memset(&alu, 0, sizeof(struct r600_bc_alu));
1269 alu.src[0].sel = ctx->temp_reg;
1270 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1271 alu.dst.chan = i;
1272 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1273 if (r)
1274 return r;
1275 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1276 if (i == 3)
1277 alu.last = 1;
1278 r = r600_bc_add_alu(ctx->bc, &alu);
1279 if (r)
1280 return r;
1281 }
1282 return 0;
1283 }
1284
1285 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1286 {
1287 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1288 struct r600_bc_alu alu;
1289 int i, r;
1290
1291 memset(&alu, 0, sizeof(struct r600_bc_alu));
1292 alu.inst = ctx->inst_info->r600_opcode;
1293 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1294 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1295 if (r)
1296 return r;
1297 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1298 }
1299 alu.dst.sel = ctx->temp_reg;
1300 alu.dst.write = 1;
1301 alu.last = 1;
1302 r = r600_bc_add_alu(ctx->bc, &alu);
1303 if (r)
1304 return r;
1305 r = r600_bc_add_literal(ctx->bc, ctx->value);
1306 if (r)
1307 return r;
1308 /* replicate result */
1309 return tgsi_helper_tempx_replicate(ctx);
1310 }
1311
1312 static int tgsi_pow(struct r600_shader_ctx *ctx)
1313 {
1314 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1315 struct r600_bc_alu alu;
1316 int r;
1317
1318 /* LOG2(a) */
1319 memset(&alu, 0, sizeof(struct r600_bc_alu));
1320 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1321 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1322 if (r)
1323 return r;
1324 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1325 alu.dst.sel = ctx->temp_reg;
1326 alu.dst.write = 1;
1327 alu.last = 1;
1328 r = r600_bc_add_alu(ctx->bc, &alu);
1329 if (r)
1330 return r;
1331 r = r600_bc_add_literal(ctx->bc,ctx->value);
1332 if (r)
1333 return r;
1334 /* b * LOG2(a) */
1335 memset(&alu, 0, sizeof(struct r600_bc_alu));
1336 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1337 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1338 if (r)
1339 return r;
1340 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1341 alu.src[1].sel = ctx->temp_reg;
1342 alu.dst.sel = ctx->temp_reg;
1343 alu.dst.write = 1;
1344 alu.last = 1;
1345 r = r600_bc_add_alu(ctx->bc, &alu);
1346 if (r)
1347 return r;
1348 r = r600_bc_add_literal(ctx->bc,ctx->value);
1349 if (r)
1350 return r;
1351 /* POW(a,b) = EXP2(b * LOG2(a))*/
1352 memset(&alu, 0, sizeof(struct r600_bc_alu));
1353 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1354 alu.src[0].sel = ctx->temp_reg;
1355 alu.dst.sel = ctx->temp_reg;
1356 alu.dst.write = 1;
1357 alu.last = 1;
1358 r = r600_bc_add_alu(ctx->bc, &alu);
1359 if (r)
1360 return r;
1361 r = r600_bc_add_literal(ctx->bc,ctx->value);
1362 if (r)
1363 return r;
1364 return tgsi_helper_tempx_replicate(ctx);
1365 }
1366
1367 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1368 {
1369 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1370 struct r600_bc_alu alu;
1371 struct r600_bc_alu_src r600_src[3];
1372 int i, r;
1373
1374 r = tgsi_split_constant(ctx, r600_src);
1375 if (r)
1376 return r;
1377
1378 /* tmp = (src > 0 ? 1 : src) */
1379 for (i = 0; i < 4; i++) {
1380 memset(&alu, 0, sizeof(struct r600_bc_alu));
1381 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1382 alu.is_op3 = 1;
1383
1384 alu.dst.sel = ctx->temp_reg;
1385 alu.dst.chan = i;
1386
1387 alu.src[0] = r600_src[0];
1388 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1389
1390 alu.src[1].sel = V_SQ_ALU_SRC_1;
1391
1392 alu.src[2] = r600_src[0];
1393 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1394 if (i == 3)
1395 alu.last = 1;
1396 r = r600_bc_add_alu(ctx->bc, &alu);
1397 if (r)
1398 return r;
1399 }
1400 r = r600_bc_add_literal(ctx->bc, ctx->value);
1401 if (r)
1402 return r;
1403
1404 /* dst = (-tmp > 0 ? -1 : tmp) */
1405 for (i = 0; i < 4; i++) {
1406 memset(&alu, 0, sizeof(struct r600_bc_alu));
1407 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1408 alu.is_op3 = 1;
1409 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1410 if (r)
1411 return r;
1412
1413 alu.src[0].sel = ctx->temp_reg;
1414 alu.src[0].chan = i;
1415 alu.src[0].neg = 1;
1416
1417 alu.src[1].sel = V_SQ_ALU_SRC_1;
1418 alu.src[1].neg = 1;
1419
1420 alu.src[2].sel = ctx->temp_reg;
1421 alu.src[2].chan = i;
1422
1423 if (i == 3)
1424 alu.last = 1;
1425 r = r600_bc_add_alu(ctx->bc, &alu);
1426 if (r)
1427 return r;
1428 }
1429 return 0;
1430 }
1431
1432 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1433 {
1434 struct r600_bc_alu alu;
1435 int i, r;
1436
1437 r = r600_bc_add_literal(ctx->bc, ctx->value);
1438 if (r)
1439 return r;
1440 for (i = 0; i < 4; i++) {
1441 memset(&alu, 0, sizeof(struct r600_bc_alu));
1442 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1443 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1444 alu.dst.chan = i;
1445 } else {
1446 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1447 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1448 if (r)
1449 return r;
1450 alu.src[0].sel = ctx->temp_reg;
1451 alu.src[0].chan = i;
1452 }
1453 if (i == 3) {
1454 alu.last = 1;
1455 }
1456 r = r600_bc_add_alu(ctx->bc, &alu);
1457 if (r)
1458 return r;
1459 }
1460 return 0;
1461 }
1462
1463 static int tgsi_op3(struct r600_shader_ctx *ctx)
1464 {
1465 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1466 struct r600_bc_alu_src r600_src[3];
1467 struct r600_bc_alu alu;
1468 int i, j, r;
1469
1470 r = tgsi_split_constant(ctx, r600_src);
1471 if (r)
1472 return r;
1473 /* do it in 2 step as op3 doesn't support writemask */
1474 for (i = 0; i < 4; i++) {
1475 memset(&alu, 0, sizeof(struct r600_bc_alu));
1476 alu.inst = ctx->inst_info->r600_opcode;
1477 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1478 alu.src[j] = r600_src[j];
1479 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1480 }
1481 alu.dst.sel = ctx->temp_reg;
1482 alu.dst.chan = i;
1483 alu.dst.write = 1;
1484 alu.is_op3 = 1;
1485 if (i == 3) {
1486 alu.last = 1;
1487 }
1488 r = r600_bc_add_alu(ctx->bc, &alu);
1489 if (r)
1490 return r;
1491 }
1492 return tgsi_helper_copy(ctx, inst);
1493 }
1494
1495 static int tgsi_dp(struct r600_shader_ctx *ctx)
1496 {
1497 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1498 struct r600_bc_alu_src r600_src[3];
1499 struct r600_bc_alu alu;
1500 int i, j, r;
1501
1502 r = tgsi_split_constant(ctx, r600_src);
1503 if (r)
1504 return r;
1505 for (i = 0; i < 4; i++) {
1506 memset(&alu, 0, sizeof(struct r600_bc_alu));
1507 alu.inst = ctx->inst_info->r600_opcode;
1508 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1509 alu.src[j] = r600_src[j];
1510 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1511 }
1512 alu.dst.sel = ctx->temp_reg;
1513 alu.dst.chan = i;
1514 alu.dst.write = 1;
1515 /* handle some special cases */
1516 switch (ctx->inst_info->tgsi_opcode) {
1517 case TGSI_OPCODE_DP2:
1518 if (i > 1) {
1519 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1520 alu.src[0].chan = alu.src[1].chan = 0;
1521 }
1522 break;
1523 case TGSI_OPCODE_DP3:
1524 if (i > 2) {
1525 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1526 alu.src[0].chan = alu.src[1].chan = 0;
1527 }
1528 break;
1529 case TGSI_OPCODE_DPH:
1530 if (i == 3) {
1531 alu.src[0].sel = V_SQ_ALU_SRC_1;
1532 alu.src[0].chan = 0;
1533 alu.src[0].neg = 0;
1534 }
1535 break;
1536 default:
1537 break;
1538 }
1539 if (i == 3) {
1540 alu.last = 1;
1541 }
1542 r = r600_bc_add_alu(ctx->bc, &alu);
1543 if (r)
1544 return r;
1545 }
1546 return tgsi_helper_copy(ctx, inst);
1547 }
1548
1549 static int tgsi_tex(struct r600_shader_ctx *ctx)
1550 {
1551 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1552 struct r600_bc_tex tex;
1553 struct r600_bc_alu alu;
1554 unsigned src_gpr;
1555 int r, i;
1556 int opcode;
1557 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1558 uint32_t lit_vals[4];
1559
1560 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1561
1562 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1563 /* Add perspective divide */
1564 memset(&alu, 0, sizeof(struct r600_bc_alu));
1565 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1566 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1567 if (r)
1568 return r;
1569
1570 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1571 alu.dst.sel = ctx->temp_reg;
1572 alu.dst.chan = 3;
1573 alu.last = 1;
1574 alu.dst.write = 1;
1575 r = r600_bc_add_alu(ctx->bc, &alu);
1576 if (r)
1577 return r;
1578
1579 for (i = 0; i < 3; i++) {
1580 memset(&alu, 0, sizeof(struct r600_bc_alu));
1581 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1582 alu.src[0].sel = ctx->temp_reg;
1583 alu.src[0].chan = 3;
1584 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1585 if (r)
1586 return r;
1587 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1588 alu.dst.sel = ctx->temp_reg;
1589 alu.dst.chan = i;
1590 alu.dst.write = 1;
1591 r = r600_bc_add_alu(ctx->bc, &alu);
1592 if (r)
1593 return r;
1594 }
1595 memset(&alu, 0, sizeof(struct r600_bc_alu));
1596 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1597 alu.src[0].sel = V_SQ_ALU_SRC_1;
1598 alu.src[0].chan = 0;
1599 alu.dst.sel = ctx->temp_reg;
1600 alu.dst.chan = 3;
1601 alu.last = 1;
1602 alu.dst.write = 1;
1603 r = r600_bc_add_alu(ctx->bc, &alu);
1604 if (r)
1605 return r;
1606 src_not_temp = FALSE;
1607 src_gpr = ctx->temp_reg;
1608 }
1609
1610 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1611 int src_chan, src2_chan;
1612
1613 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1614 for (i = 0; i < 4; i++) {
1615 memset(&alu, 0, sizeof(struct r600_bc_alu));
1616 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1617 switch (i) {
1618 case 0:
1619 src_chan = 2;
1620 src2_chan = 1;
1621 break;
1622 case 1:
1623 src_chan = 2;
1624 src2_chan = 0;
1625 break;
1626 case 2:
1627 src_chan = 0;
1628 src2_chan = 2;
1629 break;
1630 case 3:
1631 src_chan = 1;
1632 src2_chan = 2;
1633 break;
1634 default:
1635 assert(0);
1636 src_chan = 0;
1637 src2_chan = 0;
1638 break;
1639 }
1640 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1641 if (r)
1642 return r;
1643 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1644 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1645 if (r)
1646 return r;
1647 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1648 alu.dst.sel = ctx->temp_reg;
1649 alu.dst.chan = i;
1650 if (i == 3)
1651 alu.last = 1;
1652 alu.dst.write = 1;
1653 r = r600_bc_add_alu(ctx->bc, &alu);
1654 if (r)
1655 return r;
1656 }
1657
1658 /* tmp1.z = RCP_e(|tmp1.z|) */
1659 memset(&alu, 0, sizeof(struct r600_bc_alu));
1660 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1661 alu.src[0].sel = ctx->temp_reg;
1662 alu.src[0].chan = 2;
1663 alu.src[0].abs = 1;
1664 alu.dst.sel = ctx->temp_reg;
1665 alu.dst.chan = 2;
1666 alu.dst.write = 1;
1667 alu.last = 1;
1668 r = r600_bc_add_alu(ctx->bc, &alu);
1669 if (r)
1670 return r;
1671
1672 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1673 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1674 * muladd has no writemask, have to use another temp
1675 */
1676 memset(&alu, 0, sizeof(struct r600_bc_alu));
1677 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1678 alu.is_op3 = 1;
1679
1680 alu.src[0].sel = ctx->temp_reg;
1681 alu.src[0].chan = 0;
1682 alu.src[1].sel = ctx->temp_reg;
1683 alu.src[1].chan = 2;
1684
1685 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1686 alu.src[2].chan = 0;
1687
1688 alu.dst.sel = ctx->temp_reg;
1689 alu.dst.chan = 0;
1690 alu.dst.write = 1;
1691
1692 r = r600_bc_add_alu(ctx->bc, &alu);
1693 if (r)
1694 return r;
1695
1696 memset(&alu, 0, sizeof(struct r600_bc_alu));
1697 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1698 alu.is_op3 = 1;
1699
1700 alu.src[0].sel = ctx->temp_reg;
1701 alu.src[0].chan = 1;
1702 alu.src[1].sel = ctx->temp_reg;
1703 alu.src[1].chan = 2;
1704
1705 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1706 alu.src[2].chan = 0;
1707
1708 alu.dst.sel = ctx->temp_reg;
1709 alu.dst.chan = 1;
1710 alu.dst.write = 1;
1711
1712 alu.last = 1;
1713 r = r600_bc_add_alu(ctx->bc, &alu);
1714 if (r)
1715 return r;
1716
1717 lit_vals[0] = fui(1.5f);
1718
1719 r = r600_bc_add_literal(ctx->bc, lit_vals);
1720 if (r)
1721 return r;
1722 src_not_temp = FALSE;
1723 src_gpr = ctx->temp_reg;
1724 }
1725
1726 if (src_not_temp) {
1727 for (i = 0; i < 4; i++) {
1728 memset(&alu, 0, sizeof(struct r600_bc_alu));
1729 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1730 alu.src[0].sel = src_gpr;
1731 alu.src[0].chan = i;
1732 alu.dst.sel = ctx->temp_reg;
1733 alu.dst.chan = i;
1734 if (i == 3)
1735 alu.last = 1;
1736 alu.dst.write = 1;
1737 r = r600_bc_add_alu(ctx->bc, &alu);
1738 if (r)
1739 return r;
1740 }
1741 src_gpr = ctx->temp_reg;
1742 }
1743
1744 opcode = ctx->inst_info->r600_opcode;
1745 if (opcode == SQ_TEX_INST_SAMPLE &&
1746 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1747 opcode = SQ_TEX_INST_SAMPLE_C;
1748
1749 memset(&tex, 0, sizeof(struct r600_bc_tex));
1750 tex.inst = opcode;
1751 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1752 tex.sampler_id = tex.resource_id;
1753 tex.src_gpr = src_gpr;
1754 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1755 tex.dst_sel_x = 0;
1756 tex.dst_sel_y = 1;
1757 tex.dst_sel_z = 2;
1758 tex.dst_sel_w = 3;
1759 tex.src_sel_x = 0;
1760 tex.src_sel_y = 1;
1761 tex.src_sel_z = 2;
1762 tex.src_sel_w = 3;
1763
1764 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1765 tex.src_sel_x = 1;
1766 tex.src_sel_y = 0;
1767 tex.src_sel_z = 3;
1768 tex.src_sel_w = 1;
1769 }
1770
1771 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1772 tex.coord_type_x = 1;
1773 tex.coord_type_y = 1;
1774 tex.coord_type_z = 1;
1775 tex.coord_type_w = 1;
1776 }
1777
1778 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1779 tex.src_sel_w = 2;
1780
1781 r = r600_bc_add_tex(ctx->bc, &tex);
1782 if (r)
1783 return r;
1784
1785 /* add shadow ambient support - gallium doesn't do it yet */
1786 return 0;
1787
1788 }
1789
1790 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1791 {
1792 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1793 struct r600_bc_alu_src r600_src[3];
1794 struct r600_bc_alu alu;
1795 unsigned i;
1796 int r;
1797
1798 r = tgsi_split_constant(ctx, r600_src);
1799 if (r)
1800 return r;
1801 /* 1 - src0 */
1802 for (i = 0; i < 4; i++) {
1803 memset(&alu, 0, sizeof(struct r600_bc_alu));
1804 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1805 alu.src[0].sel = V_SQ_ALU_SRC_1;
1806 alu.src[0].chan = 0;
1807 alu.src[1] = r600_src[0];
1808 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1809 alu.src[1].neg = 1;
1810 alu.dst.sel = ctx->temp_reg;
1811 alu.dst.chan = i;
1812 if (i == 3) {
1813 alu.last = 1;
1814 }
1815 alu.dst.write = 1;
1816 r = r600_bc_add_alu(ctx->bc, &alu);
1817 if (r)
1818 return r;
1819 }
1820 r = r600_bc_add_literal(ctx->bc, ctx->value);
1821 if (r)
1822 return r;
1823
1824 /* (1 - src0) * src2 */
1825 for (i = 0; i < 4; i++) {
1826 memset(&alu, 0, sizeof(struct r600_bc_alu));
1827 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1828 alu.src[0].sel = ctx->temp_reg;
1829 alu.src[0].chan = i;
1830 alu.src[1] = r600_src[2];
1831 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1832 alu.dst.sel = ctx->temp_reg;
1833 alu.dst.chan = i;
1834 if (i == 3) {
1835 alu.last = 1;
1836 }
1837 alu.dst.write = 1;
1838 r = r600_bc_add_alu(ctx->bc, &alu);
1839 if (r)
1840 return r;
1841 }
1842 r = r600_bc_add_literal(ctx->bc, ctx->value);
1843 if (r)
1844 return r;
1845
1846 /* src0 * src1 + (1 - src0) * src2 */
1847 for (i = 0; i < 4; i++) {
1848 memset(&alu, 0, sizeof(struct r600_bc_alu));
1849 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1850 alu.is_op3 = 1;
1851 alu.src[0] = r600_src[0];
1852 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1853 alu.src[1] = r600_src[1];
1854 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1855 alu.src[2].sel = ctx->temp_reg;
1856 alu.src[2].chan = i;
1857 alu.dst.sel = ctx->temp_reg;
1858 alu.dst.chan = i;
1859 if (i == 3) {
1860 alu.last = 1;
1861 }
1862 r = r600_bc_add_alu(ctx->bc, &alu);
1863 if (r)
1864 return r;
1865 }
1866 return tgsi_helper_copy(ctx, inst);
1867 }
1868
1869 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1870 {
1871 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1872 struct r600_bc_alu_src r600_src[3];
1873 struct r600_bc_alu alu;
1874 int use_temp = 0;
1875 int i, r;
1876
1877 r = tgsi_split_constant(ctx, r600_src);
1878 if (r)
1879 return r;
1880
1881 if (inst->Dst[0].Register.WriteMask != 0xf)
1882 use_temp = 1;
1883
1884 for (i = 0; i < 4; i++) {
1885 memset(&alu, 0, sizeof(struct r600_bc_alu));
1886 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1887 alu.src[0] = r600_src[0];
1888 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1889
1890 alu.src[1] = r600_src[2];
1891 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1892
1893 alu.src[2] = r600_src[1];
1894 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
1895
1896 if (use_temp)
1897 alu.dst.sel = ctx->temp_reg;
1898 else {
1899 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1900 if (r)
1901 return r;
1902 }
1903 alu.dst.chan = i;
1904 alu.dst.write = 1;
1905 alu.is_op3 = 1;
1906 if (i == 3)
1907 alu.last = 1;
1908 r = r600_bc_add_alu(ctx->bc, &alu);
1909 if (r)
1910 return r;
1911 }
1912 if (use_temp)
1913 return tgsi_helper_copy(ctx, inst);
1914 return 0;
1915 }
1916
1917 static int tgsi_xpd(struct r600_shader_ctx *ctx)
1918 {
1919 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1920 struct r600_bc_alu_src r600_src[3];
1921 struct r600_bc_alu alu;
1922 uint32_t use_temp = 0;
1923 int i, r;
1924
1925 if (inst->Dst[0].Register.WriteMask != 0xf)
1926 use_temp = 1;
1927
1928 r = tgsi_split_constant(ctx, r600_src);
1929 if (r)
1930 return r;
1931
1932 for (i = 0; i < 4; i++) {
1933 memset(&alu, 0, sizeof(struct r600_bc_alu));
1934 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1935
1936 alu.src[0] = r600_src[0];
1937 switch (i) {
1938 case 0:
1939 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1940 break;
1941 case 1:
1942 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1943 break;
1944 case 2:
1945 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1946 break;
1947 case 3:
1948 alu.src[0].sel = V_SQ_ALU_SRC_0;
1949 alu.src[0].chan = i;
1950 }
1951
1952 alu.src[1] = r600_src[1];
1953 switch (i) {
1954 case 0:
1955 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1956 break;
1957 case 1:
1958 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1959 break;
1960 case 2:
1961 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1962 break;
1963 case 3:
1964 alu.src[1].sel = V_SQ_ALU_SRC_0;
1965 alu.src[1].chan = i;
1966 }
1967
1968 alu.dst.sel = ctx->temp_reg;
1969 alu.dst.chan = i;
1970 alu.dst.write = 1;
1971
1972 if (i == 3)
1973 alu.last = 1;
1974 r = r600_bc_add_alu(ctx->bc, &alu);
1975 if (r)
1976 return r;
1977
1978 r = r600_bc_add_literal(ctx->bc, ctx->value);
1979 if (r)
1980 return r;
1981 }
1982
1983 for (i = 0; i < 4; i++) {
1984 memset(&alu, 0, sizeof(struct r600_bc_alu));
1985 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1986
1987 alu.src[0] = r600_src[0];
1988 switch (i) {
1989 case 0:
1990 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1991 break;
1992 case 1:
1993 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1994 break;
1995 case 2:
1996 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1997 break;
1998 case 3:
1999 alu.src[0].sel = V_SQ_ALU_SRC_0;
2000 alu.src[0].chan = i;
2001 }
2002
2003 alu.src[1] = r600_src[1];
2004 switch (i) {
2005 case 0:
2006 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2007 break;
2008 case 1:
2009 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2010 break;
2011 case 2:
2012 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2013 break;
2014 case 3:
2015 alu.src[1].sel = V_SQ_ALU_SRC_0;
2016 alu.src[1].chan = i;
2017 }
2018
2019 alu.src[2].sel = ctx->temp_reg;
2020 alu.src[2].neg = 1;
2021 alu.src[2].chan = i;
2022
2023 if (use_temp)
2024 alu.dst.sel = ctx->temp_reg;
2025 else {
2026 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2027 if (r)
2028 return r;
2029 }
2030 alu.dst.chan = i;
2031 alu.dst.write = 1;
2032 alu.is_op3 = 1;
2033 if (i == 3)
2034 alu.last = 1;
2035 r = r600_bc_add_alu(ctx->bc, &alu);
2036 if (r)
2037 return r;
2038
2039 r = r600_bc_add_literal(ctx->bc, ctx->value);
2040 if (r)
2041 return r;
2042 }
2043 if (use_temp)
2044 return tgsi_helper_copy(ctx, inst);
2045 return 0;
2046 }
2047
2048 static int tgsi_exp(struct r600_shader_ctx *ctx)
2049 {
2050 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2051 struct r600_bc_alu_src r600_src[3];
2052 struct r600_bc_alu alu;
2053 int r;
2054
2055 /* result.x = 2^floor(src); */
2056 if (inst->Dst[0].Register.WriteMask & 1) {
2057 memset(&alu, 0, sizeof(struct r600_bc_alu));
2058
2059 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2060 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2061 if (r)
2062 return r;
2063
2064 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2065
2066 alu.dst.sel = ctx->temp_reg;
2067 alu.dst.chan = 0;
2068 alu.dst.write = 1;
2069 alu.last = 1;
2070 r = r600_bc_add_alu(ctx->bc, &alu);
2071 if (r)
2072 return r;
2073
2074 r = r600_bc_add_literal(ctx->bc, ctx->value);
2075 if (r)
2076 return r;
2077
2078 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2079 alu.src[0].sel = ctx->temp_reg;
2080 alu.src[0].chan = 0;
2081
2082 alu.dst.sel = ctx->temp_reg;
2083 alu.dst.chan = 0;
2084 alu.dst.write = 1;
2085 alu.last = 1;
2086 r = r600_bc_add_alu(ctx->bc, &alu);
2087 if (r)
2088 return r;
2089
2090 r = r600_bc_add_literal(ctx->bc, ctx->value);
2091 if (r)
2092 return r;
2093 }
2094
2095 /* result.y = tmp - floor(tmp); */
2096 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2097 memset(&alu, 0, sizeof(struct r600_bc_alu));
2098
2099 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2100 alu.src[0] = r600_src[0];
2101 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2102 if (r)
2103 return r;
2104 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2105
2106 alu.dst.sel = ctx->temp_reg;
2107 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2108 // if (r)
2109 // return r;
2110 alu.dst.write = 1;
2111 alu.dst.chan = 1;
2112
2113 alu.last = 1;
2114
2115 r = r600_bc_add_alu(ctx->bc, &alu);
2116 if (r)
2117 return r;
2118 r = r600_bc_add_literal(ctx->bc, ctx->value);
2119 if (r)
2120 return r;
2121 }
2122
2123 /* result.z = RoughApprox2ToX(tmp);*/
2124 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2125 memset(&alu, 0, sizeof(struct r600_bc_alu));
2126 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2127 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2128 if (r)
2129 return r;
2130 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2131
2132 alu.dst.sel = ctx->temp_reg;
2133 alu.dst.write = 1;
2134 alu.dst.chan = 2;
2135
2136 alu.last = 1;
2137
2138 r = r600_bc_add_alu(ctx->bc, &alu);
2139 if (r)
2140 return r;
2141 r = r600_bc_add_literal(ctx->bc, ctx->value);
2142 if (r)
2143 return r;
2144 }
2145
2146 /* result.w = 1.0;*/
2147 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2148 memset(&alu, 0, sizeof(struct r600_bc_alu));
2149
2150 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2151 alu.src[0].sel = V_SQ_ALU_SRC_1;
2152 alu.src[0].chan = 0;
2153
2154 alu.dst.sel = ctx->temp_reg;
2155 alu.dst.chan = 3;
2156 alu.dst.write = 1;
2157 alu.last = 1;
2158 r = r600_bc_add_alu(ctx->bc, &alu);
2159 if (r)
2160 return r;
2161 r = r600_bc_add_literal(ctx->bc, ctx->value);
2162 if (r)
2163 return r;
2164 }
2165 return tgsi_helper_copy(ctx, inst);
2166 }
2167
2168 static int tgsi_log(struct r600_shader_ctx *ctx)
2169 {
2170 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2171 struct r600_bc_alu alu;
2172 int r;
2173
2174 /* result.x = floor(log2(src)); */
2175 if (inst->Dst[0].Register.WriteMask & 1) {
2176 memset(&alu, 0, sizeof(struct r600_bc_alu));
2177
2178 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2179 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2180 if (r)
2181 return r;
2182
2183 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2184
2185 alu.dst.sel = ctx->temp_reg;
2186 alu.dst.chan = 0;
2187 alu.dst.write = 1;
2188 alu.last = 1;
2189 r = r600_bc_add_alu(ctx->bc, &alu);
2190 if (r)
2191 return r;
2192
2193 r = r600_bc_add_literal(ctx->bc, ctx->value);
2194 if (r)
2195 return r;
2196
2197 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2198 alu.src[0].sel = ctx->temp_reg;
2199 alu.src[0].chan = 0;
2200
2201 alu.dst.sel = ctx->temp_reg;
2202 alu.dst.chan = 0;
2203 alu.dst.write = 1;
2204 alu.last = 1;
2205
2206 r = r600_bc_add_alu(ctx->bc, &alu);
2207 if (r)
2208 return r;
2209
2210 r = r600_bc_add_literal(ctx->bc, ctx->value);
2211 if (r)
2212 return r;
2213 }
2214
2215 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2216 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2217 memset(&alu, 0, sizeof(struct r600_bc_alu));
2218
2219 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2220 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2221 if (r)
2222 return r;
2223
2224 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2225
2226 alu.dst.sel = ctx->temp_reg;
2227 alu.dst.chan = 1;
2228 alu.dst.write = 1;
2229 alu.last = 1;
2230
2231 r = r600_bc_add_alu(ctx->bc, &alu);
2232 if (r)
2233 return r;
2234
2235 r = r600_bc_add_literal(ctx->bc, ctx->value);
2236 if (r)
2237 return r;
2238
2239 memset(&alu, 0, sizeof(struct r600_bc_alu));
2240
2241 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2242 alu.src[0].sel = ctx->temp_reg;
2243 alu.src[0].chan = 1;
2244
2245 alu.dst.sel = ctx->temp_reg;
2246 alu.dst.chan = 1;
2247 alu.dst.write = 1;
2248 alu.last = 1;
2249
2250 r = r600_bc_add_alu(ctx->bc, &alu);
2251 if (r)
2252 return r;
2253
2254 r = r600_bc_add_literal(ctx->bc, ctx->value);
2255 if (r)
2256 return r;
2257
2258 memset(&alu, 0, sizeof(struct r600_bc_alu));
2259
2260 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2261 alu.src[0].sel = ctx->temp_reg;
2262 alu.src[0].chan = 1;
2263
2264 alu.dst.sel = ctx->temp_reg;
2265 alu.dst.chan = 1;
2266 alu.dst.write = 1;
2267 alu.last = 1;
2268
2269 r = r600_bc_add_alu(ctx->bc, &alu);
2270 if (r)
2271 return r;
2272
2273 r = r600_bc_add_literal(ctx->bc, ctx->value);
2274 if (r)
2275 return r;
2276
2277 memset(&alu, 0, sizeof(struct r600_bc_alu));
2278
2279 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2280 alu.src[0].sel = ctx->temp_reg;
2281 alu.src[0].chan = 1;
2282
2283 alu.dst.sel = ctx->temp_reg;
2284 alu.dst.chan = 1;
2285 alu.dst.write = 1;
2286 alu.last = 1;
2287
2288 r = r600_bc_add_alu(ctx->bc, &alu);
2289 if (r)
2290 return r;
2291
2292 r = r600_bc_add_literal(ctx->bc, ctx->value);
2293 if (r)
2294 return r;
2295
2296 memset(&alu, 0, sizeof(struct r600_bc_alu));
2297
2298 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2299
2300 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2301 if (r)
2302 return r;
2303
2304 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2305
2306 alu.src[1].sel = ctx->temp_reg;
2307 alu.src[1].chan = 1;
2308
2309 alu.dst.sel = ctx->temp_reg;
2310 alu.dst.chan = 1;
2311 alu.dst.write = 1;
2312 alu.last = 1;
2313
2314 r = r600_bc_add_alu(ctx->bc, &alu);
2315 if (r)
2316 return r;
2317
2318 r = r600_bc_add_literal(ctx->bc, ctx->value);
2319 if (r)
2320 return r;
2321 }
2322
2323 /* result.z = log2(src);*/
2324 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2325 memset(&alu, 0, sizeof(struct r600_bc_alu));
2326
2327 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2328 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2329 if (r)
2330 return r;
2331
2332 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2333
2334 alu.dst.sel = ctx->temp_reg;
2335 alu.dst.write = 1;
2336 alu.dst.chan = 2;
2337 alu.last = 1;
2338
2339 r = r600_bc_add_alu(ctx->bc, &alu);
2340 if (r)
2341 return r;
2342
2343 r = r600_bc_add_literal(ctx->bc, ctx->value);
2344 if (r)
2345 return r;
2346 }
2347
2348 /* result.w = 1.0; */
2349 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2350 memset(&alu, 0, sizeof(struct r600_bc_alu));
2351
2352 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2353 alu.src[0].sel = V_SQ_ALU_SRC_1;
2354 alu.src[0].chan = 0;
2355
2356 alu.dst.sel = ctx->temp_reg;
2357 alu.dst.chan = 3;
2358 alu.dst.write = 1;
2359 alu.last = 1;
2360
2361 r = r600_bc_add_alu(ctx->bc, &alu);
2362 if (r)
2363 return r;
2364
2365 r = r600_bc_add_literal(ctx->bc, ctx->value);
2366 if (r)
2367 return r;
2368 }
2369
2370 return tgsi_helper_copy(ctx, inst);
2371 }
2372
2373 /* r6/7 only for now */
2374 static int tgsi_arl(struct r600_shader_ctx *ctx)
2375 {
2376 /* TODO from r600c, ar values don't persist between clauses */
2377 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2378 struct r600_bc_alu alu;
2379 int r;
2380 memset(&alu, 0, sizeof(struct r600_bc_alu));
2381
2382 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2383
2384 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2385 if (r)
2386 return r;
2387 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2388
2389 alu.last = 1;
2390
2391 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2392 if (r)
2393 return r;
2394 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2395 return 0;
2396 }
2397
2398 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2399 {
2400 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2401 struct r600_bc_alu alu;
2402 int i, r = 0;
2403
2404 for (i = 0; i < 4; i++) {
2405 memset(&alu, 0, sizeof(struct r600_bc_alu));
2406
2407 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2408 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2409 if (r)
2410 return r;
2411
2412 if (i == 0 || i == 3) {
2413 alu.src[0].sel = V_SQ_ALU_SRC_1;
2414 } else {
2415 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2416 if (r)
2417 return r;
2418 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2419 }
2420
2421 if (i == 0 || i == 2) {
2422 alu.src[1].sel = V_SQ_ALU_SRC_1;
2423 } else {
2424 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2425 if (r)
2426 return r;
2427 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2428 }
2429 if (i == 3)
2430 alu.last = 1;
2431 r = r600_bc_add_alu(ctx->bc, &alu);
2432 if (r)
2433 return r;
2434 }
2435 return 0;
2436 }
2437
2438 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2439 {
2440 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2441 struct r600_bc_alu alu;
2442 int r;
2443
2444 memset(&alu, 0, sizeof(struct r600_bc_alu));
2445 alu.inst = opcode;
2446 alu.predicate = 1;
2447
2448 alu.dst.sel = ctx->temp_reg;
2449 alu.dst.write = 1;
2450 alu.dst.chan = 0;
2451
2452 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2453 if (r)
2454 return r;
2455 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2456 alu.src[1].sel = V_SQ_ALU_SRC_0;
2457 alu.src[1].chan = 0;
2458
2459 alu.last = 1;
2460
2461 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2462 if (r)
2463 return r;
2464 return 0;
2465 }
2466
2467 static int pops(struct r600_shader_ctx *ctx, int pops)
2468 {
2469 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2470 ctx->bc->cf_last->pop_count = pops;
2471 return 0;
2472 }
2473
2474 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2475 {
2476 switch(reason) {
2477 case FC_PUSH_VPM:
2478 ctx->bc->callstack[ctx->bc->call_sp].current--;
2479 break;
2480 case FC_PUSH_WQM:
2481 case FC_LOOP:
2482 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2483 break;
2484 case FC_REP:
2485 /* TOODO : for 16 vp asic should -= 2; */
2486 ctx->bc->callstack[ctx->bc->call_sp].current --;
2487 break;
2488 }
2489 }
2490
2491 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2492 {
2493 if (check_max_only) {
2494 int diff;
2495 switch (reason) {
2496 case FC_PUSH_VPM:
2497 diff = 1;
2498 break;
2499 case FC_PUSH_WQM:
2500 diff = 4;
2501 break;
2502 default:
2503 assert(0);
2504 diff = 0;
2505 }
2506 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2507 ctx->bc->callstack[ctx->bc->call_sp].max) {
2508 ctx->bc->callstack[ctx->bc->call_sp].max =
2509 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2510 }
2511 return;
2512 }
2513 switch (reason) {
2514 case FC_PUSH_VPM:
2515 ctx->bc->callstack[ctx->bc->call_sp].current++;
2516 break;
2517 case FC_PUSH_WQM:
2518 case FC_LOOP:
2519 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2520 break;
2521 case FC_REP:
2522 ctx->bc->callstack[ctx->bc->call_sp].current++;
2523 break;
2524 }
2525
2526 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2527 ctx->bc->callstack[ctx->bc->call_sp].max) {
2528 ctx->bc->callstack[ctx->bc->call_sp].max =
2529 ctx->bc->callstack[ctx->bc->call_sp].current;
2530 }
2531 }
2532
2533 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2534 {
2535 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2536
2537 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2538 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2539 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2540 sp->num_mid++;
2541 }
2542
2543 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2544 {
2545 ctx->bc->fc_sp++;
2546 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2547 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2548 }
2549
2550 static void fc_poplevel(struct r600_shader_ctx *ctx)
2551 {
2552 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2553 if (sp->mid) {
2554 free(sp->mid);
2555 sp->mid = NULL;
2556 }
2557 sp->num_mid = 0;
2558 sp->start = NULL;
2559 sp->type = 0;
2560 ctx->bc->fc_sp--;
2561 }
2562
2563 #if 0
2564 static int emit_return(struct r600_shader_ctx *ctx)
2565 {
2566 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2567 return 0;
2568 }
2569
2570 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2571 {
2572
2573 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2574 ctx->bc->cf_last->pop_count = pops;
2575 /* TODO work out offset */
2576 return 0;
2577 }
2578
2579 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2580 {
2581 return 0;
2582 }
2583
2584 static void emit_testflag(struct r600_shader_ctx *ctx)
2585 {
2586
2587 }
2588
2589 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2590 {
2591 emit_testflag(ctx);
2592 emit_jump_to_offset(ctx, 1, 4);
2593 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2594 pops(ctx, ifidx + 1);
2595 emit_return(ctx);
2596 }
2597
2598 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2599 {
2600 emit_testflag(ctx);
2601
2602 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2603 ctx->bc->cf_last->pop_count = 1;
2604
2605 fc_set_mid(ctx, fc_sp);
2606
2607 pops(ctx, 1);
2608 }
2609 #endif
2610
2611 static int tgsi_if(struct r600_shader_ctx *ctx)
2612 {
2613 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2614
2615 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2616
2617 fc_pushlevel(ctx, FC_IF);
2618
2619 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2620 return 0;
2621 }
2622
2623 static int tgsi_else(struct r600_shader_ctx *ctx)
2624 {
2625 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2626 ctx->bc->cf_last->pop_count = 1;
2627
2628 fc_set_mid(ctx, ctx->bc->fc_sp);
2629 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2630 return 0;
2631 }
2632
2633 static int tgsi_endif(struct r600_shader_ctx *ctx)
2634 {
2635 pops(ctx, 1);
2636 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2637 R600_ERR("if/endif unbalanced in shader\n");
2638 return -1;
2639 }
2640
2641 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2642 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2643 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2644 } else {
2645 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2646 }
2647 fc_poplevel(ctx);
2648
2649 callstack_decrease_current(ctx, FC_PUSH_VPM);
2650 return 0;
2651 }
2652
2653 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2654 {
2655 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2656
2657 fc_pushlevel(ctx, FC_LOOP);
2658
2659 /* check stack depth */
2660 callstack_check_depth(ctx, FC_LOOP, 0);
2661 return 0;
2662 }
2663
2664 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2665 {
2666 int i;
2667
2668 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2669
2670 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2671 R600_ERR("loop/endloop in shader code are not paired.\n");
2672 return -EINVAL;
2673 }
2674
2675 /* fixup loop pointers - from r600isa
2676 LOOP END points to CF after LOOP START,
2677 LOOP START point to CF after LOOP END
2678 BRK/CONT point to LOOP END CF
2679 */
2680 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2681
2682 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2683
2684 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2685 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2686 }
2687 /* TODO add LOOPRET support */
2688 fc_poplevel(ctx);
2689 callstack_decrease_current(ctx, FC_LOOP);
2690 return 0;
2691 }
2692
2693 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2694 {
2695 unsigned int fscp;
2696
2697 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2698 {
2699 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2700 break;
2701 }
2702
2703 if (fscp == 0) {
2704 R600_ERR("Break not inside loop/endloop pair\n");
2705 return -EINVAL;
2706 }
2707
2708 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2709 ctx->bc->cf_last->pop_count = 1;
2710
2711 fc_set_mid(ctx, fscp);
2712
2713 pops(ctx, 1);
2714 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2715 return 0;
2716 }
2717
2718 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2719 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2720 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2721 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2722
2723 /* FIXME:
2724 * For state trackers other than OpenGL, we'll want to use
2725 * _RECIP_IEEE instead.
2726 */
2727 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2728
2729 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2730 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2731 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2732 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2733 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2734 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2735 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2736 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2737 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2738 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2739 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2740 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2741 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2742 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2743 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2744 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2745 /* gap */
2746 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2747 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2748 /* gap */
2749 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2750 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2751 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2752 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2753 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2754 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2755 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2756 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2757 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2758 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2759 /* gap */
2760 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2761 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2762 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2763 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2764 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2765 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2766 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2767 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2768 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2769 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2770 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2771 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2772 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2773 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2774 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2775 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2776 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2777 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2778 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2779 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2780 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2781 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2782 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2783 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2784 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2785 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2786 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2787 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2788 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2789 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2790 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2791 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2792 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2793 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2794 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2795 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2796 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2797 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2798 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2799 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2800 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2801 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2802 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2803 /* gap */
2804 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2805 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2806 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2807 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2808 /* gap */
2809 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2810 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2811 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2812 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2813 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2814 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2815 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2816 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2817 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2818 /* gap */
2819 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2820 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2821 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2822 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2823 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2824 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2825 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2826 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2827 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2828 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2829 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2830 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2831 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2832 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2833 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2834 /* gap */
2835 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2836 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2837 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2838 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2839 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2840 /* gap */
2841 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2842 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2843 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2844 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2845 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2846 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2847 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2848 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2849 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2850 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2851 /* gap */
2852 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2853 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2854 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2855 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2856 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2857 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2858 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2859 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2860 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2861 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2862 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2863 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2864 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2865 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2866 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2867 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2868 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2869 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2870 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2871 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2872 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2873 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2874 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2875 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2876 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2877 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2878 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2879 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2880 };
2881
2882 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
2883 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2884 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2885 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2886 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2887 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
2888 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2889 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2891 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2892 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2893 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2894 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2895 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2896 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2897 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2898 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2899 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2900 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2901 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2902 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2903 /* gap */
2904 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 /* gap */
2907 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2908 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2910 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2911 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2912 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2914 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2915 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2916 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2917 /* gap */
2918 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2919 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2920 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2921 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2922 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2923 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2924 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2925 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2926 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2927 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2932 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2934 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2935 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2936 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2937 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2939 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2941 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2946 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2948 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2950 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2952 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2953 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2954 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2955 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2957 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2958 {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2960 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2961 /* gap */
2962 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2965 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2966 /* gap */
2967 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2968 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2969 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2975 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 /* gap */
2977 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2986 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2989 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2991 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 /* gap */
2993 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2996 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 /* gap */
2999 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3008 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3009 /* gap */
3010 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3015 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3026 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3027 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3028 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3029 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3037 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3038 };