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r600: fix atomic counter index mode getting emitted on pre-cayman
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193 use_sb &= (shader->shader.processor_type != PIPE_SHADER_COMPUTE);
194
195 /* disable SB for shaders using doubles */
196 use_sb &= !shader->shader.uses_doubles;
197
198 use_sb &= !shader->shader.uses_atomics;
199 use_sb &= !shader->shader.uses_images;
200
201 /* Check if the bytecode has already been built. */
202 if (!shader->shader.bc.bytecode) {
203 r = r600_bytecode_build(&shader->shader.bc);
204 if (r) {
205 R600_ERR("building bytecode failed !\n");
206 goto error;
207 }
208 }
209
210 if (dump && !sb_disasm) {
211 fprintf(stderr, "--------------------------------------------------------------\n");
212 r600_bytecode_disasm(&shader->shader.bc);
213 fprintf(stderr, "______________________________________________________________\n");
214 } else if ((dump && sb_disasm) || use_sb) {
215 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
216 dump, use_sb);
217 if (r) {
218 R600_ERR("r600_sb_bytecode_process failed !\n");
219 goto error;
220 }
221 }
222
223 if (shader->gs_copy_shader) {
224 if (dump) {
225 // dump copy shader
226 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
227 &shader->gs_copy_shader->shader, dump, 0);
228 if (r)
229 goto error;
230 }
231
232 if ((r = store_shader(ctx, shader->gs_copy_shader)))
233 goto error;
234 }
235
236 /* Store the shader in a buffer. */
237 if ((r = store_shader(ctx, shader)))
238 goto error;
239
240 /* Build state. */
241 switch (shader->shader.processor_type) {
242 case PIPE_SHADER_TESS_CTRL:
243 evergreen_update_hs_state(ctx, shader);
244 break;
245 case PIPE_SHADER_TESS_EVAL:
246 if (key.tes.as_es)
247 evergreen_update_es_state(ctx, shader);
248 else
249 evergreen_update_vs_state(ctx, shader);
250 break;
251 case PIPE_SHADER_GEOMETRY:
252 if (rctx->b.chip_class >= EVERGREEN) {
253 evergreen_update_gs_state(ctx, shader);
254 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
255 } else {
256 r600_update_gs_state(ctx, shader);
257 r600_update_vs_state(ctx, shader->gs_copy_shader);
258 }
259 break;
260 case PIPE_SHADER_VERTEX:
261 export_shader = key.vs.as_es;
262 if (rctx->b.chip_class >= EVERGREEN) {
263 if (key.vs.as_ls)
264 evergreen_update_ls_state(ctx, shader);
265 else if (key.vs.as_es)
266 evergreen_update_es_state(ctx, shader);
267 else
268 evergreen_update_vs_state(ctx, shader);
269 } else {
270 if (export_shader)
271 r600_update_es_state(ctx, shader);
272 else
273 r600_update_vs_state(ctx, shader);
274 }
275 break;
276 case PIPE_SHADER_FRAGMENT:
277 if (rctx->b.chip_class >= EVERGREEN) {
278 evergreen_update_ps_state(ctx, shader);
279 } else {
280 r600_update_ps_state(ctx, shader);
281 }
282 break;
283 case PIPE_SHADER_COMPUTE:
284 evergreen_update_ls_state(ctx, shader);
285 break;
286 default:
287 r = -EINVAL;
288 goto error;
289 }
290 return 0;
291
292 error:
293 r600_pipe_shader_destroy(ctx, shader);
294 return r;
295 }
296
297 void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
298 {
299 r600_resource_reference(&shader->bo, NULL);
300 r600_bytecode_clear(&shader->shader.bc);
301 r600_release_command_buffer(&shader->command_buffer);
302 }
303
304 /*
305 * tgsi -> r600 shader
306 */
307 struct r600_shader_tgsi_instruction;
308
309 struct r600_shader_src {
310 unsigned sel;
311 unsigned swizzle[4];
312 unsigned neg;
313 unsigned abs;
314 unsigned rel;
315 unsigned kc_bank;
316 boolean kc_rel; /* true if cache bank is indexed */
317 uint32_t value[4];
318 };
319
320 struct eg_interp {
321 boolean enabled;
322 unsigned ij_index;
323 };
324
325 struct r600_shader_ctx {
326 struct tgsi_shader_info info;
327 struct tgsi_parse_context parse;
328 const struct tgsi_token *tokens;
329 unsigned type;
330 unsigned file_offset[TGSI_FILE_COUNT];
331 unsigned temp_reg;
332 const struct r600_shader_tgsi_instruction *inst_info;
333 struct r600_bytecode *bc;
334 struct r600_shader *shader;
335 struct r600_shader_src src[4];
336 uint32_t *literals;
337 uint32_t nliterals;
338 uint32_t max_driver_temp_used;
339 /* needed for evergreen interpolation */
340 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
341 /* evergreen/cayman also store sample mask in face register */
342 int face_gpr;
343 /* sample id is .w component stored in fixed point position register */
344 int fixed_pt_position_gpr;
345 int colors_used;
346 boolean clip_vertex_write;
347 unsigned cv_output;
348 unsigned edgeflag_output;
349 int cs_block_size_reg;
350 int cs_grid_size_reg;
351 bool cs_block_size_loaded, cs_grid_size_loaded;
352 int fragcoord_input;
353 int native_integers;
354 int next_ring_offset;
355 int gs_out_ring_offset;
356 int gs_next_vertex;
357 struct r600_shader *gs_for_vs;
358 int gs_export_gpr_tregs[4];
359 int gs_rotated_input[2];
360 const struct pipe_stream_output_info *gs_stream_output_info;
361 unsigned enabled_stream_buffers_mask;
362 unsigned tess_input_info; /* temp with tess input offsets */
363 unsigned tess_output_info; /* temp with tess input offsets */
364 unsigned thread_id_gpr; /* temp with thread id calculated for images */
365 bool thread_id_gpr_loaded;
366 };
367
368 struct r600_shader_tgsi_instruction {
369 unsigned op;
370 int (*process)(struct r600_shader_ctx *ctx);
371 };
372
373 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
374 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
375 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
376 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
377 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
378 static int tgsi_else(struct r600_shader_ctx *ctx);
379 static int tgsi_endif(struct r600_shader_ctx *ctx);
380 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
381 static int tgsi_endloop(struct r600_shader_ctx *ctx);
382 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
383 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
384 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
385 unsigned int dst_reg);
386 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
387 const struct r600_shader_src *shader_src,
388 unsigned chan);
389 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
390 unsigned dst_reg, unsigned mask);
391
392 static int tgsi_last_instruction(unsigned writemask)
393 {
394 int i, lasti = 0;
395
396 for (i = 0; i < 4; i++) {
397 if (writemask & (1 << i)) {
398 lasti = i;
399 }
400 }
401 return lasti;
402 }
403
404 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
405 {
406 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
407 unsigned j;
408
409 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
410 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
411 return -EINVAL;
412 }
413 #if 0
414 if (i->Instruction.Label) {
415 R600_ERR("label unsupported\n");
416 return -EINVAL;
417 }
418 #endif
419 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
420 if (i->Src[j].Register.Dimension) {
421 switch (i->Src[j].Register.File) {
422 case TGSI_FILE_CONSTANT:
423 case TGSI_FILE_HW_ATOMIC:
424 break;
425 case TGSI_FILE_INPUT:
426 if (ctx->type == PIPE_SHADER_GEOMETRY ||
427 ctx->type == PIPE_SHADER_TESS_CTRL ||
428 ctx->type == PIPE_SHADER_TESS_EVAL)
429 break;
430 case TGSI_FILE_OUTPUT:
431 if (ctx->type == PIPE_SHADER_TESS_CTRL)
432 break;
433 default:
434 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
435 i->Src[j].Register.File,
436 i->Src[j].Register.Dimension);
437 return -EINVAL;
438 }
439 }
440 }
441 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
442 if (i->Dst[j].Register.Dimension) {
443 if (ctx->type == PIPE_SHADER_TESS_CTRL)
444 continue;
445 R600_ERR("unsupported dst (dimension)\n");
446 return -EINVAL;
447 }
448 }
449 return 0;
450 }
451
452 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
453 {
454 if (interpolate == TGSI_INTERPOLATE_COLOR ||
455 interpolate == TGSI_INTERPOLATE_LINEAR ||
456 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
457 {
458 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
459 int loc;
460
461 switch(location) {
462 case TGSI_INTERPOLATE_LOC_CENTER:
463 loc = 1;
464 break;
465 case TGSI_INTERPOLATE_LOC_CENTROID:
466 loc = 2;
467 break;
468 case TGSI_INTERPOLATE_LOC_SAMPLE:
469 default:
470 loc = 0; break;
471 }
472
473 return is_linear * 3 + loc;
474 }
475
476 return -1;
477 }
478
479 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
480 int input)
481 {
482 int i = eg_get_interpolator_index(
483 ctx->shader->input[input].interpolate,
484 ctx->shader->input[input].interpolate_location);
485 assert(i >= 0);
486 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
487 }
488
489 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
490 {
491 int i, r;
492 struct r600_bytecode_alu alu;
493 int gpr = 0, base_chan = 0;
494 int ij_index = ctx->shader->input[input].ij_index;
495
496 /* work out gpr and base_chan from index */
497 gpr = ij_index / 2;
498 base_chan = (2 * (ij_index % 2)) + 1;
499
500 for (i = 0; i < 8; i++) {
501 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
502
503 if (i < 4)
504 alu.op = ALU_OP2_INTERP_ZW;
505 else
506 alu.op = ALU_OP2_INTERP_XY;
507
508 if ((i > 1) && (i < 6)) {
509 alu.dst.sel = ctx->shader->input[input].gpr;
510 alu.dst.write = 1;
511 }
512
513 alu.dst.chan = i % 4;
514
515 alu.src[0].sel = gpr;
516 alu.src[0].chan = (base_chan - (i % 2));
517
518 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
519
520 alu.bank_swizzle_force = SQ_ALU_VEC_210;
521 if ((i % 4) == 3)
522 alu.last = 1;
523 r = r600_bytecode_add_alu(ctx->bc, &alu);
524 if (r)
525 return r;
526 }
527 return 0;
528 }
529
530 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
531 {
532 int i, r;
533 struct r600_bytecode_alu alu;
534
535 for (i = 0; i < 4; i++) {
536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
537
538 alu.op = ALU_OP1_INTERP_LOAD_P0;
539
540 alu.dst.sel = ctx->shader->input[input].gpr;
541 alu.dst.write = 1;
542
543 alu.dst.chan = i;
544
545 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
546 alu.src[0].chan = i;
547
548 if (i == 3)
549 alu.last = 1;
550 r = r600_bytecode_add_alu(ctx->bc, &alu);
551 if (r)
552 return r;
553 }
554 return 0;
555 }
556
557 /*
558 * Special export handling in shaders
559 *
560 * shader export ARRAY_BASE for EXPORT_POS:
561 * 60 is position
562 * 61 is misc vector
563 * 62, 63 are clip distance vectors
564 *
565 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
566 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
567 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
568 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
569 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
570 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
571 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
572 * exclusive from render target index)
573 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
574 *
575 *
576 * shader export ARRAY_BASE for EXPORT_PIXEL:
577 * 0-7 CB targets
578 * 61 computed Z vector
579 *
580 * The use of the values exported in the computed Z vector are controlled
581 * by DB_SHADER_CONTROL:
582 * Z_EXPORT_ENABLE - Z as a float in RED
583 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
584 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
585 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
586 * DB_SOURCE_FORMAT - export control restrictions
587 *
588 */
589
590
591 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
592 static int r600_spi_sid(struct r600_shader_io * io)
593 {
594 int index, name = io->name;
595
596 /* These params are handled differently, they don't need
597 * semantic indices, so we'll use 0 for them.
598 */
599 if (name == TGSI_SEMANTIC_POSITION ||
600 name == TGSI_SEMANTIC_PSIZE ||
601 name == TGSI_SEMANTIC_EDGEFLAG ||
602 name == TGSI_SEMANTIC_FACE ||
603 name == TGSI_SEMANTIC_SAMPLEMASK)
604 index = 0;
605 else {
606 if (name == TGSI_SEMANTIC_GENERIC) {
607 /* For generic params simply use sid from tgsi */
608 index = io->sid;
609 } else {
610 /* For non-generic params - pack name and sid into 8 bits */
611 index = 0x80 | (name<<3) | (io->sid);
612 }
613
614 /* Make sure that all really used indices have nonzero value, so
615 * we can just compare it to 0 later instead of comparing the name
616 * with different values to detect special cases. */
617 index++;
618 }
619
620 return index;
621 };
622
623 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
624 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
625 {
626 switch (semantic_name) {
627 case TGSI_SEMANTIC_POSITION:
628 return 0;
629 case TGSI_SEMANTIC_PSIZE:
630 return 1;
631 case TGSI_SEMANTIC_CLIPDIST:
632 assert(index <= 1);
633 return 2 + index;
634 case TGSI_SEMANTIC_GENERIC:
635 if (index <= 63-4)
636 return 4 + index - 9;
637 else
638 /* same explanation as in the default statement,
639 * the only user hitting this is st/nine.
640 */
641 return 0;
642
643 /* patch indices are completely separate and thus start from 0 */
644 case TGSI_SEMANTIC_TESSOUTER:
645 return 0;
646 case TGSI_SEMANTIC_TESSINNER:
647 return 1;
648 case TGSI_SEMANTIC_PATCH:
649 return 2 + index;
650
651 default:
652 /* Don't fail here. The result of this function is only used
653 * for LS, TCS, TES, and GS, where legacy GL semantics can't
654 * occur, but this function is called for all vertex shaders
655 * before it's known whether LS will be compiled or not.
656 */
657 return 0;
658 }
659 }
660
661 /* turn input into interpolate on EG */
662 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
663 {
664 int r = 0;
665
666 if (ctx->shader->input[index].spi_sid) {
667 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
668 if (ctx->shader->input[index].interpolate > 0) {
669 evergreen_interp_assign_ij_index(ctx, index);
670 r = evergreen_interp_alu(ctx, index);
671 } else {
672 r = evergreen_interp_flat(ctx, index);
673 }
674 }
675 return r;
676 }
677
678 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
679 {
680 struct r600_bytecode_alu alu;
681 int i, r;
682 int gpr_front = ctx->shader->input[front].gpr;
683 int gpr_back = ctx->shader->input[back].gpr;
684
685 for (i = 0; i < 4; i++) {
686 memset(&alu, 0, sizeof(alu));
687 alu.op = ALU_OP3_CNDGT;
688 alu.is_op3 = 1;
689 alu.dst.write = 1;
690 alu.dst.sel = gpr_front;
691 alu.src[0].sel = ctx->face_gpr;
692 alu.src[1].sel = gpr_front;
693 alu.src[2].sel = gpr_back;
694
695 alu.dst.chan = i;
696 alu.src[1].chan = i;
697 alu.src[2].chan = i;
698 alu.last = (i==3);
699
700 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
701 return r;
702 }
703
704 return 0;
705 }
706
707 /* execute a single slot ALU calculation */
708 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
709 int dst_sel, int dst_chan,
710 int src0_sel, unsigned src0_chan_val,
711 int src1_sel, unsigned src1_chan_val)
712 {
713 struct r600_bytecode_alu alu;
714 int r, i;
715
716 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
717 for (i = 0; i < 4; i++) {
718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
719 alu.op = op;
720 alu.src[0].sel = src0_sel;
721 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
722 alu.src[0].value = src0_chan_val;
723 else
724 alu.src[0].chan = src0_chan_val;
725 alu.src[1].sel = src1_sel;
726 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
727 alu.src[1].value = src1_chan_val;
728 else
729 alu.src[1].chan = src1_chan_val;
730 alu.dst.sel = dst_sel;
731 alu.dst.chan = i;
732 alu.dst.write = i == dst_chan;
733 alu.last = (i == 3);
734 r = r600_bytecode_add_alu(ctx->bc, &alu);
735 if (r)
736 return r;
737 }
738 return 0;
739 }
740
741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
742 alu.op = op;
743 alu.src[0].sel = src0_sel;
744 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
745 alu.src[0].value = src0_chan_val;
746 else
747 alu.src[0].chan = src0_chan_val;
748 alu.src[1].sel = src1_sel;
749 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
750 alu.src[1].value = src1_chan_val;
751 else
752 alu.src[1].chan = src1_chan_val;
753 alu.dst.sel = dst_sel;
754 alu.dst.chan = dst_chan;
755 alu.dst.write = 1;
756 alu.last = 1;
757 r = r600_bytecode_add_alu(ctx->bc, &alu);
758 if (r)
759 return r;
760 return 0;
761 }
762
763 /* execute a single slot ALU calculation */
764 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
765 int dst_sel, int dst_chan,
766 int src0_sel, unsigned src0_chan_val,
767 int src1_sel, unsigned src1_chan_val,
768 int src2_sel, unsigned src2_chan_val)
769 {
770 struct r600_bytecode_alu alu;
771 int r;
772
773 /* validate this for other ops */
774 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
775 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
776 alu.op = op;
777 alu.src[0].sel = src0_sel;
778 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
779 alu.src[0].value = src0_chan_val;
780 else
781 alu.src[0].chan = src0_chan_val;
782 alu.src[1].sel = src1_sel;
783 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
784 alu.src[1].value = src1_chan_val;
785 else
786 alu.src[1].chan = src1_chan_val;
787 alu.src[2].sel = src2_sel;
788 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
789 alu.src[2].value = src2_chan_val;
790 else
791 alu.src[2].chan = src2_chan_val;
792 alu.dst.sel = dst_sel;
793 alu.dst.chan = dst_chan;
794 alu.is_op3 = 1;
795 alu.last = 1;
796 r = r600_bytecode_add_alu(ctx->bc, &alu);
797 if (r)
798 return r;
799 return 0;
800 }
801
802 /* put it in temp_reg.x */
803 static int get_lds_offset0(struct r600_shader_ctx *ctx,
804 int rel_patch_chan,
805 int temp_reg, bool is_patch_var)
806 {
807 int r;
808
809 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
810 /* ADD
811 Dimension - patch0_offset (input_vals.z),
812 Non-dim - patch0_data_offset (input_vals.w)
813 */
814 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
815 temp_reg, 0,
816 ctx->tess_output_info, 0,
817 0, rel_patch_chan,
818 ctx->tess_output_info, is_patch_var ? 3 : 2);
819 if (r)
820 return r;
821 return 0;
822 }
823
824 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
825 {
826 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
827 }
828
829 static int r600_get_temp(struct r600_shader_ctx *ctx)
830 {
831 return ctx->temp_reg + ctx->max_driver_temp_used++;
832 }
833
834 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
835 {
836 int i;
837 i = ctx->shader->noutput++;
838 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
839 ctx->shader->output[i].sid = 0;
840 ctx->shader->output[i].gpr = 0;
841 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
842 ctx->shader->output[i].write_mask = 0x4;
843 ctx->shader->output[i].spi_sid = prim_id_sid;
844
845 return 0;
846 }
847
848 static int tgsi_barrier(struct r600_shader_ctx *ctx)
849 {
850 struct r600_bytecode_alu alu;
851 int r;
852
853 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
854 alu.op = ctx->inst_info->op;
855 alu.last = 1;
856
857 r = r600_bytecode_add_alu(ctx->bc, &alu);
858 if (r)
859 return r;
860 return 0;
861 }
862
863 static int tgsi_declaration(struct r600_shader_ctx *ctx)
864 {
865 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
866 int r, i, j, count = d->Range.Last - d->Range.First + 1;
867
868 switch (d->Declaration.File) {
869 case TGSI_FILE_INPUT:
870 for (j = 0; j < count; j++) {
871 i = ctx->shader->ninput + j;
872 assert(i < ARRAY_SIZE(ctx->shader->input));
873 ctx->shader->input[i].name = d->Semantic.Name;
874 ctx->shader->input[i].sid = d->Semantic.Index + j;
875 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
876 ctx->shader->input[i].interpolate_location = d->Interp.Location;
877 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
878 if (ctx->type == PIPE_SHADER_FRAGMENT) {
879 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
880 switch (ctx->shader->input[i].name) {
881 case TGSI_SEMANTIC_FACE:
882 if (ctx->face_gpr != -1)
883 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
884 else
885 ctx->face_gpr = ctx->shader->input[i].gpr;
886 break;
887 case TGSI_SEMANTIC_COLOR:
888 ctx->colors_used++;
889 break;
890 case TGSI_SEMANTIC_POSITION:
891 ctx->fragcoord_input = i;
892 break;
893 case TGSI_SEMANTIC_PRIMID:
894 /* set this for now */
895 ctx->shader->gs_prim_id_input = true;
896 ctx->shader->ps_prim_id_input = i;
897 break;
898 }
899 if (ctx->bc->chip_class >= EVERGREEN) {
900 if ((r = evergreen_interp_input(ctx, i)))
901 return r;
902 }
903 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
904 /* FIXME probably skip inputs if they aren't passed in the ring */
905 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
906 ctx->next_ring_offset += 16;
907 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
908 ctx->shader->gs_prim_id_input = true;
909 }
910 }
911 ctx->shader->ninput += count;
912 break;
913 case TGSI_FILE_OUTPUT:
914 for (j = 0; j < count; j++) {
915 i = ctx->shader->noutput + j;
916 assert(i < ARRAY_SIZE(ctx->shader->output));
917 ctx->shader->output[i].name = d->Semantic.Name;
918 ctx->shader->output[i].sid = d->Semantic.Index + j;
919 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
920 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
921 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
922 if (ctx->type == PIPE_SHADER_VERTEX ||
923 ctx->type == PIPE_SHADER_GEOMETRY ||
924 ctx->type == PIPE_SHADER_TESS_EVAL) {
925 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
926 switch (d->Semantic.Name) {
927 case TGSI_SEMANTIC_CLIPDIST:
928 break;
929 case TGSI_SEMANTIC_PSIZE:
930 ctx->shader->vs_out_misc_write = 1;
931 ctx->shader->vs_out_point_size = 1;
932 break;
933 case TGSI_SEMANTIC_EDGEFLAG:
934 ctx->shader->vs_out_misc_write = 1;
935 ctx->shader->vs_out_edgeflag = 1;
936 ctx->edgeflag_output = i;
937 break;
938 case TGSI_SEMANTIC_VIEWPORT_INDEX:
939 ctx->shader->vs_out_misc_write = 1;
940 ctx->shader->vs_out_viewport = 1;
941 break;
942 case TGSI_SEMANTIC_LAYER:
943 ctx->shader->vs_out_misc_write = 1;
944 ctx->shader->vs_out_layer = 1;
945 break;
946 case TGSI_SEMANTIC_CLIPVERTEX:
947 ctx->clip_vertex_write = TRUE;
948 ctx->cv_output = i;
949 break;
950 }
951 if (ctx->type == PIPE_SHADER_GEOMETRY) {
952 ctx->gs_out_ring_offset += 16;
953 }
954 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
955 switch (d->Semantic.Name) {
956 case TGSI_SEMANTIC_COLOR:
957 ctx->shader->nr_ps_max_color_exports++;
958 break;
959 }
960 }
961 }
962 ctx->shader->noutput += count;
963 break;
964 case TGSI_FILE_TEMPORARY:
965 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
966 if (d->Array.ArrayID) {
967 r600_add_gpr_array(ctx->shader,
968 ctx->file_offset[TGSI_FILE_TEMPORARY] +
969 d->Range.First,
970 d->Range.Last - d->Range.First + 1, 0x0F);
971 }
972 }
973 break;
974
975 case TGSI_FILE_CONSTANT:
976 case TGSI_FILE_SAMPLER:
977 case TGSI_FILE_SAMPLER_VIEW:
978 case TGSI_FILE_ADDRESS:
979 case TGSI_FILE_BUFFER:
980 case TGSI_FILE_IMAGE:
981 case TGSI_FILE_MEMORY:
982 break;
983
984 case TGSI_FILE_HW_ATOMIC:
985 i = ctx->shader->nhwatomic_ranges;
986 ctx->shader->atomics[i].start = d->Range.First;
987 ctx->shader->atomics[i].end = d->Range.Last;
988 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
989 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
990 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
991 ctx->shader->nhwatomic_ranges++;
992 ctx->shader->nhwatomic += count;
993 break;
994
995 case TGSI_FILE_SYSTEM_VALUE:
996 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
997 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
998 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
999 break; /* Already handled from allocate_system_value_inputs */
1000 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
1001 if (!ctx->native_integers) {
1002 struct r600_bytecode_alu alu;
1003 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1004
1005 alu.op = ALU_OP1_INT_TO_FLT;
1006 alu.src[0].sel = 0;
1007 alu.src[0].chan = 3;
1008
1009 alu.dst.sel = 0;
1010 alu.dst.chan = 3;
1011 alu.dst.write = 1;
1012 alu.last = 1;
1013
1014 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1015 return r;
1016 }
1017 break;
1018 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1019 break;
1020 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1021 break;
1022 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1023 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1024 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1025 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1026 unsigned temp_reg = r600_get_temp(ctx);
1027
1028 r = get_lds_offset0(ctx, 2, temp_reg, true);
1029 if (r)
1030 return r;
1031
1032 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1033 temp_reg, 0,
1034 temp_reg, 0,
1035 V_SQ_ALU_SRC_LITERAL, param * 16);
1036 if (r)
1037 return r;
1038
1039 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
1040 }
1041 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1042 /* MOV r1.x, r0.x;
1043 MOV r1.y, r0.y;
1044 */
1045 for (i = 0; i < 2; i++) {
1046 struct r600_bytecode_alu alu;
1047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1048 alu.op = ALU_OP1_MOV;
1049 alu.src[0].sel = 0;
1050 alu.src[0].chan = 0 + i;
1051 alu.dst.sel = 1;
1052 alu.dst.chan = 0 + i;
1053 alu.dst.write = 1;
1054 alu.last = (i == 1) ? 1 : 0;
1055 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1056 return r;
1057 }
1058 /* ADD r1.z, 1.0f, -r0.x */
1059 struct r600_bytecode_alu alu;
1060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1061 alu.op = ALU_OP2_ADD;
1062 alu.src[0].sel = V_SQ_ALU_SRC_1;
1063 alu.src[1].sel = 1;
1064 alu.src[1].chan = 0;
1065 alu.src[1].neg = 1;
1066 alu.dst.sel = 1;
1067 alu.dst.chan = 2;
1068 alu.dst.write = 1;
1069 alu.last = 1;
1070 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1071 return r;
1072
1073 /* ADD r1.z, r1.z, -r1.y */
1074 alu.op = ALU_OP2_ADD;
1075 alu.src[0].sel = 1;
1076 alu.src[0].chan = 2;
1077 alu.src[1].sel = 1;
1078 alu.src[1].chan = 1;
1079 alu.src[1].neg = 1;
1080 alu.dst.sel = 1;
1081 alu.dst.chan = 2;
1082 alu.dst.write = 1;
1083 alu.last = 1;
1084 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1085 return r;
1086 break;
1087 }
1088 break;
1089 default:
1090 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1091 return -EINVAL;
1092 }
1093 return 0;
1094 }
1095
1096 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1097 {
1098 struct tgsi_parse_context parse;
1099 struct {
1100 boolean enabled;
1101 int *reg;
1102 unsigned name, alternate_name;
1103 } inputs[2] = {
1104 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1105
1106 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1107 };
1108 int num_regs = 0;
1109 unsigned k, i;
1110
1111 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1112 return 0;
1113 }
1114
1115 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1116 while (!tgsi_parse_end_of_tokens(&parse)) {
1117 tgsi_parse_token(&parse);
1118
1119 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1120 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1121 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1122 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1123 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1124 {
1125 int interpolate, location, k;
1126
1127 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1128 location = TGSI_INTERPOLATE_LOC_CENTER;
1129 inputs[1].enabled = true; /* needs SAMPLEID */
1130 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1131 location = TGSI_INTERPOLATE_LOC_CENTER;
1132 /* Needs sample positions, currently those are always available */
1133 } else {
1134 location = TGSI_INTERPOLATE_LOC_CENTROID;
1135 }
1136
1137 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1138 k = eg_get_interpolator_index(interpolate, location);
1139 if (k >= 0)
1140 ctx->eg_interpolators[k].enabled = true;
1141 }
1142 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1143 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1144 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1145 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1146 if (d->Semantic.Name == inputs[k].name ||
1147 d->Semantic.Name == inputs[k].alternate_name) {
1148 inputs[k].enabled = true;
1149 }
1150 }
1151 }
1152 }
1153 }
1154
1155 tgsi_parse_free(&parse);
1156
1157 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1158 boolean enabled = inputs[i].enabled;
1159 int *reg = inputs[i].reg;
1160 unsigned name = inputs[i].name;
1161
1162 if (enabled) {
1163 int gpr = gpr_offset + num_regs++;
1164 ctx->shader->nsys_inputs++;
1165
1166 // add to inputs, allocate a gpr
1167 k = ctx->shader->ninput++;
1168 ctx->shader->input[k].name = name;
1169 ctx->shader->input[k].sid = 0;
1170 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1171 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1172 *reg = ctx->shader->input[k].gpr = gpr;
1173 }
1174 }
1175
1176 return gpr_offset + num_regs;
1177 }
1178
1179 /*
1180 * for evergreen we need to scan the shader to find the number of GPRs we need to
1181 * reserve for interpolation and system values
1182 *
1183 * we need to know if we are going to emit
1184 * any sample or centroid inputs
1185 * if perspective and linear are required
1186 */
1187 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1188 {
1189 unsigned i;
1190 int num_baryc;
1191 struct tgsi_parse_context parse;
1192
1193 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1194
1195 for (i = 0; i < ctx->info.num_inputs; i++) {
1196 int k;
1197 /* skip position/face/mask/sampleid */
1198 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1199 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1200 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1201 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1202 continue;
1203
1204 k = eg_get_interpolator_index(
1205 ctx->info.input_interpolate[i],
1206 ctx->info.input_interpolate_loc[i]);
1207 if (k >= 0)
1208 ctx->eg_interpolators[k].enabled = TRUE;
1209 }
1210
1211 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1212 return 0;
1213 }
1214
1215 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1216 while (!tgsi_parse_end_of_tokens(&parse)) {
1217 tgsi_parse_token(&parse);
1218
1219 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1220 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1221 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1222 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1223 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1224 {
1225 int interpolate, location, k;
1226
1227 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1228 location = TGSI_INTERPOLATE_LOC_CENTER;
1229 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1230 location = TGSI_INTERPOLATE_LOC_CENTER;
1231 } else {
1232 location = TGSI_INTERPOLATE_LOC_CENTROID;
1233 }
1234
1235 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1236 k = eg_get_interpolator_index(interpolate, location);
1237 if (k >= 0)
1238 ctx->eg_interpolators[k].enabled = true;
1239 }
1240 }
1241 }
1242
1243 tgsi_parse_free(&parse);
1244
1245 /* assign gpr to each interpolator according to priority */
1246 num_baryc = 0;
1247 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1248 if (ctx->eg_interpolators[i].enabled) {
1249 ctx->eg_interpolators[i].ij_index = num_baryc;
1250 num_baryc ++;
1251 }
1252 }
1253
1254 /* XXX PULL MODEL and LINE STIPPLE */
1255
1256 num_baryc = (num_baryc + 1) >> 1;
1257 return allocate_system_value_inputs(ctx, num_baryc);
1258 }
1259
1260 /* sample_id_sel == NULL means fetch for current sample */
1261 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1262 {
1263 struct r600_bytecode_vtx vtx;
1264 int r, t1;
1265
1266 assert(ctx->fixed_pt_position_gpr != -1);
1267
1268 t1 = r600_get_temp(ctx);
1269
1270 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1271 vtx.op = FETCH_OP_VFETCH;
1272 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1273 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1274 if (sample_id == NULL) {
1275 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1276 vtx.src_sel_x = 3;
1277 }
1278 else {
1279 struct r600_bytecode_alu alu;
1280
1281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1282 alu.op = ALU_OP1_MOV;
1283 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1284 alu.dst.sel = t1;
1285 alu.dst.write = 1;
1286 alu.last = 1;
1287 r = r600_bytecode_add_alu(ctx->bc, &alu);
1288 if (r)
1289 return r;
1290
1291 vtx.src_gpr = t1;
1292 vtx.src_sel_x = 0;
1293 }
1294 vtx.mega_fetch_count = 16;
1295 vtx.dst_gpr = t1;
1296 vtx.dst_sel_x = 0;
1297 vtx.dst_sel_y = 1;
1298 vtx.dst_sel_z = 2;
1299 vtx.dst_sel_w = 3;
1300 vtx.data_format = FMT_32_32_32_32_FLOAT;
1301 vtx.num_format_all = 2;
1302 vtx.format_comp_all = 1;
1303 vtx.use_const_fields = 0;
1304 vtx.offset = 1; // first element is size of buffer
1305 vtx.endian = r600_endian_swap(32);
1306 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1307
1308 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1309 if (r)
1310 return r;
1311
1312 return t1;
1313 }
1314
1315 static int load_block_grid_size(struct r600_shader_ctx *ctx, bool load_block)
1316 {
1317 struct r600_bytecode_vtx vtx;
1318 int r, t1;
1319
1320 if (ctx->cs_block_size_loaded)
1321 return ctx->cs_block_size_reg;
1322 if (ctx->cs_grid_size_loaded)
1323 return ctx->cs_grid_size_reg;
1324
1325 t1 = load_block ? ctx->cs_block_size_reg : ctx->cs_grid_size_reg;
1326 struct r600_bytecode_alu alu;
1327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1328 alu.op = ALU_OP1_MOV;
1329 alu.src[0].sel = V_SQ_ALU_SRC_0;
1330 alu.dst.sel = t1;
1331 alu.dst.write = 1;
1332 alu.last = 1;
1333 r = r600_bytecode_add_alu(ctx->bc, &alu);
1334 if (r)
1335 return r;
1336
1337 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1338 vtx.op = FETCH_OP_VFETCH;
1339 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1340 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1341 vtx.src_gpr = t1;
1342 vtx.src_sel_x = 0;
1343
1344 vtx.mega_fetch_count = 16;
1345 vtx.dst_gpr = t1;
1346 vtx.dst_sel_x = 0;
1347 vtx.dst_sel_y = 1;
1348 vtx.dst_sel_z = 2;
1349 vtx.dst_sel_w = 7;
1350 vtx.data_format = FMT_32_32_32_32;
1351 vtx.num_format_all = 1;
1352 vtx.format_comp_all = 0;
1353 vtx.use_const_fields = 0;
1354 vtx.offset = load_block ? 0 : 16; // first element is size of buffer
1355 vtx.endian = r600_endian_swap(32);
1356 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1357
1358 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1359 if (r)
1360 return r;
1361
1362 if (load_block)
1363 ctx->cs_block_size_loaded = true;
1364 else
1365 ctx->cs_grid_size_loaded = true;
1366 return t1;
1367 }
1368
1369 static void tgsi_src(struct r600_shader_ctx *ctx,
1370 const struct tgsi_full_src_register *tgsi_src,
1371 struct r600_shader_src *r600_src)
1372 {
1373 memset(r600_src, 0, sizeof(*r600_src));
1374 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1375 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1376 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1377 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1378 r600_src->neg = tgsi_src->Register.Negate;
1379 r600_src->abs = tgsi_src->Register.Absolute;
1380
1381 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1382 int index;
1383 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1384 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1385 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1386
1387 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1388 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1389 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1390 return;
1391 }
1392 index = tgsi_src->Register.Index;
1393 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1394 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1395 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1396 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1397 r600_src->swizzle[0] = 2; // Z value
1398 r600_src->swizzle[1] = 2;
1399 r600_src->swizzle[2] = 2;
1400 r600_src->swizzle[3] = 2;
1401 r600_src->sel = ctx->face_gpr;
1402 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1403 r600_src->swizzle[0] = 3; // W value
1404 r600_src->swizzle[1] = 3;
1405 r600_src->swizzle[2] = 3;
1406 r600_src->swizzle[3] = 3;
1407 r600_src->sel = ctx->fixed_pt_position_gpr;
1408 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1409 r600_src->swizzle[0] = 0;
1410 r600_src->swizzle[1] = 1;
1411 r600_src->swizzle[2] = 4;
1412 r600_src->swizzle[3] = 4;
1413 r600_src->sel = load_sample_position(ctx, NULL, -1);
1414 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1415 r600_src->swizzle[0] = 3;
1416 r600_src->swizzle[1] = 3;
1417 r600_src->swizzle[2] = 3;
1418 r600_src->swizzle[3] = 3;
1419 r600_src->sel = 0;
1420 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1421 r600_src->swizzle[0] = 0;
1422 r600_src->swizzle[1] = 0;
1423 r600_src->swizzle[2] = 0;
1424 r600_src->swizzle[3] = 0;
1425 r600_src->sel = 0;
1426 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_THREAD_ID) {
1427 r600_src->sel = 0;
1428 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_ID) {
1429 r600_src->sel = 1;
1430 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1431 r600_src->swizzle[0] = 3;
1432 r600_src->swizzle[1] = 3;
1433 r600_src->swizzle[2] = 3;
1434 r600_src->swizzle[3] = 3;
1435 r600_src->sel = 1;
1436 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1437 r600_src->swizzle[0] = 2;
1438 r600_src->swizzle[1] = 2;
1439 r600_src->swizzle[2] = 2;
1440 r600_src->swizzle[3] = 2;
1441 r600_src->sel = 0;
1442 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1443 r600_src->sel = 1;
1444 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1445 r600_src->sel = 3;
1446 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1447 r600_src->sel = 2;
1448 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1449 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1450 r600_src->sel = ctx->tess_input_info;
1451 r600_src->swizzle[0] = 2;
1452 r600_src->swizzle[1] = 2;
1453 r600_src->swizzle[2] = 2;
1454 r600_src->swizzle[3] = 2;
1455 } else {
1456 r600_src->sel = ctx->tess_input_info;
1457 r600_src->swizzle[0] = 3;
1458 r600_src->swizzle[1] = 3;
1459 r600_src->swizzle[2] = 3;
1460 r600_src->swizzle[3] = 3;
1461 }
1462 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1463 r600_src->sel = 0;
1464 r600_src->swizzle[0] = 0;
1465 r600_src->swizzle[1] = 0;
1466 r600_src->swizzle[2] = 0;
1467 r600_src->swizzle[3] = 0;
1468 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1469 r600_src->sel = 0;
1470 r600_src->swizzle[0] = 3;
1471 r600_src->swizzle[1] = 3;
1472 r600_src->swizzle[2] = 3;
1473 r600_src->swizzle[3] = 3;
1474 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_GRID_SIZE) {
1475 r600_src->sel = load_block_grid_size(ctx, false);
1476 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_SIZE) {
1477 r600_src->sel = load_block_grid_size(ctx, true);
1478 }
1479 } else {
1480 if (tgsi_src->Register.Indirect)
1481 r600_src->rel = V_SQ_REL_RELATIVE;
1482 r600_src->sel = tgsi_src->Register.Index;
1483 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1484 }
1485 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1486 if (tgsi_src->Register.Dimension) {
1487 r600_src->kc_bank = tgsi_src->Dimension.Index;
1488 if (tgsi_src->Dimension.Indirect) {
1489 r600_src->kc_rel = 1;
1490 }
1491 }
1492 }
1493 }
1494
1495 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1496 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1497 unsigned int dst_reg)
1498 {
1499 struct r600_bytecode_vtx vtx;
1500 unsigned int ar_reg;
1501 int r;
1502
1503 if (offset) {
1504 struct r600_bytecode_alu alu;
1505
1506 memset(&alu, 0, sizeof(alu));
1507
1508 alu.op = ALU_OP2_ADD_INT;
1509 alu.src[0].sel = ctx->bc->ar_reg;
1510 alu.src[0].chan = ar_chan;
1511
1512 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1513 alu.src[1].value = offset;
1514
1515 alu.dst.sel = dst_reg;
1516 alu.dst.chan = ar_chan;
1517 alu.dst.write = 1;
1518 alu.last = 1;
1519
1520 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1521 return r;
1522
1523 ar_reg = dst_reg;
1524 } else {
1525 ar_reg = ctx->bc->ar_reg;
1526 }
1527
1528 memset(&vtx, 0, sizeof(vtx));
1529 vtx.buffer_id = cb_idx;
1530 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1531 vtx.src_gpr = ar_reg;
1532 vtx.src_sel_x = ar_chan;
1533 vtx.mega_fetch_count = 16;
1534 vtx.dst_gpr = dst_reg;
1535 vtx.dst_sel_x = 0; /* SEL_X */
1536 vtx.dst_sel_y = 1; /* SEL_Y */
1537 vtx.dst_sel_z = 2; /* SEL_Z */
1538 vtx.dst_sel_w = 3; /* SEL_W */
1539 vtx.data_format = FMT_32_32_32_32_FLOAT;
1540 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1541 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1542 vtx.endian = r600_endian_swap(32);
1543 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1544
1545 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1546 return r;
1547
1548 return 0;
1549 }
1550
1551 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1552 {
1553 struct r600_bytecode_vtx vtx;
1554 int r;
1555 unsigned index = src->Register.Index;
1556 unsigned vtx_id = src->Dimension.Index;
1557 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1558 int offset_chan = vtx_id % 3;
1559 int t2 = 0;
1560
1561 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1562 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1563
1564 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1565 offset_chan = 3;
1566
1567 if (src->Dimension.Indirect || src->Register.Indirect)
1568 t2 = r600_get_temp(ctx);
1569
1570 if (src->Dimension.Indirect) {
1571 int treg[3];
1572 struct r600_bytecode_alu alu;
1573 int r, i;
1574 unsigned addr_reg;
1575 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1576 if (src->DimIndirect.Index > 0) {
1577 r = single_alu_op2(ctx, ALU_OP1_MOV,
1578 ctx->bc->ar_reg, 0,
1579 addr_reg, 0,
1580 0, 0);
1581 if (r)
1582 return r;
1583 }
1584 /*
1585 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1586 at least this is what fglrx seems to do. */
1587 for (i = 0; i < 3; i++) {
1588 treg[i] = r600_get_temp(ctx);
1589 }
1590 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1591
1592 for (i = 0; i < 3; i++) {
1593 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1594 alu.op = ALU_OP1_MOV;
1595 alu.src[0].sel = ctx->gs_rotated_input[0];
1596 alu.src[0].chan = i == 2 ? 3 : i;
1597 alu.dst.sel = treg[i];
1598 alu.dst.chan = 0;
1599 alu.dst.write = 1;
1600 alu.last = 1;
1601 r = r600_bytecode_add_alu(ctx->bc, &alu);
1602 if (r)
1603 return r;
1604 }
1605 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1606 alu.op = ALU_OP1_MOV;
1607 alu.src[0].sel = treg[0];
1608 alu.src[0].rel = 1;
1609 alu.dst.sel = t2;
1610 alu.dst.write = 1;
1611 alu.last = 1;
1612 r = r600_bytecode_add_alu(ctx->bc, &alu);
1613 if (r)
1614 return r;
1615 offset_reg = t2;
1616 offset_chan = 0;
1617 }
1618
1619 if (src->Register.Indirect) {
1620 int addr_reg;
1621 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1622
1623 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1624
1625 /* pull the value from index_reg */
1626 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1627 t2, 1,
1628 addr_reg, 0,
1629 V_SQ_ALU_SRC_LITERAL, first);
1630 if (r)
1631 return r;
1632 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1633 t2, 0,
1634 t2, 1,
1635 V_SQ_ALU_SRC_LITERAL, 4,
1636 offset_reg, offset_chan);
1637 if (r)
1638 return r;
1639 offset_reg = t2;
1640 offset_chan = 0;
1641 index = src->Register.Index - first;
1642 }
1643
1644 memset(&vtx, 0, sizeof(vtx));
1645 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1646 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1647 vtx.src_gpr = offset_reg;
1648 vtx.src_sel_x = offset_chan;
1649 vtx.offset = index * 16; /*bytes*/
1650 vtx.mega_fetch_count = 16;
1651 vtx.dst_gpr = dst_reg;
1652 vtx.dst_sel_x = 0; /* SEL_X */
1653 vtx.dst_sel_y = 1; /* SEL_Y */
1654 vtx.dst_sel_z = 2; /* SEL_Z */
1655 vtx.dst_sel_w = 3; /* SEL_W */
1656 if (ctx->bc->chip_class >= EVERGREEN) {
1657 vtx.use_const_fields = 1;
1658 } else {
1659 vtx.data_format = FMT_32_32_32_32_FLOAT;
1660 }
1661
1662 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1663 return r;
1664
1665 return 0;
1666 }
1667
1668 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1669 {
1670 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1671 unsigned i;
1672
1673 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1674 struct tgsi_full_src_register *src = &inst->Src[i];
1675
1676 if (src->Register.File == TGSI_FILE_INPUT) {
1677 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1678 /* primitive id is in R0.z */
1679 ctx->src[i].sel = 0;
1680 ctx->src[i].swizzle[0] = 2;
1681 }
1682 }
1683 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1684 int treg = r600_get_temp(ctx);
1685
1686 fetch_gs_input(ctx, src, treg);
1687 ctx->src[i].sel = treg;
1688 ctx->src[i].rel = 0;
1689 }
1690 }
1691 return 0;
1692 }
1693
1694
1695 /* Tessellation shaders pass outputs to the next shader using LDS.
1696 *
1697 * LS outputs = TCS(HS) inputs
1698 * TCS(HS) outputs = TES(DS) inputs
1699 *
1700 * The LDS layout is:
1701 * - TCS inputs for patch 0
1702 * - TCS inputs for patch 1
1703 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1704 * - ...
1705 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1706 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1707 * - TCS outputs for patch 1
1708 * - Per-patch TCS outputs for patch 1
1709 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1710 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1711 * - ...
1712 *
1713 * All three shaders VS(LS), TCS, TES share the same LDS space.
1714 */
1715 /* this will return with the dw address in temp_reg.x */
1716 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1717 const struct tgsi_full_dst_register *dst,
1718 const struct tgsi_full_src_register *src,
1719 int stride_bytes_reg, int stride_bytes_chan)
1720 {
1721 struct tgsi_full_dst_register reg;
1722 ubyte *name, *index, *array_first;
1723 int r;
1724 int param;
1725 struct tgsi_shader_info *info = &ctx->info;
1726 /* Set the register description. The address computation is the same
1727 * for sources and destinations. */
1728 if (src) {
1729 reg.Register.File = src->Register.File;
1730 reg.Register.Index = src->Register.Index;
1731 reg.Register.Indirect = src->Register.Indirect;
1732 reg.Register.Dimension = src->Register.Dimension;
1733 reg.Indirect = src->Indirect;
1734 reg.Dimension = src->Dimension;
1735 reg.DimIndirect = src->DimIndirect;
1736 } else
1737 reg = *dst;
1738
1739 /* If the register is 2-dimensional (e.g. an array of vertices
1740 * in a primitive), calculate the base address of the vertex. */
1741 if (reg.Register.Dimension) {
1742 int sel, chan;
1743 if (reg.Dimension.Indirect) {
1744 unsigned addr_reg;
1745 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1746
1747 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1748 /* pull the value from index_reg */
1749 sel = addr_reg;
1750 chan = 0;
1751 } else {
1752 sel = V_SQ_ALU_SRC_LITERAL;
1753 chan = reg.Dimension.Index;
1754 }
1755
1756 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1757 temp_reg, 0,
1758 stride_bytes_reg, stride_bytes_chan,
1759 sel, chan,
1760 temp_reg, 0);
1761 if (r)
1762 return r;
1763 }
1764
1765 if (reg.Register.File == TGSI_FILE_INPUT) {
1766 name = info->input_semantic_name;
1767 index = info->input_semantic_index;
1768 array_first = info->input_array_first;
1769 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1770 name = info->output_semantic_name;
1771 index = info->output_semantic_index;
1772 array_first = info->output_array_first;
1773 } else {
1774 assert(0);
1775 return -1;
1776 }
1777 if (reg.Register.Indirect) {
1778 int addr_reg;
1779 int first;
1780 /* Add the relative address of the element. */
1781 if (reg.Indirect.ArrayID)
1782 first = array_first[reg.Indirect.ArrayID];
1783 else
1784 first = reg.Register.Index;
1785
1786 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1787
1788 /* pull the value from index_reg */
1789 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1790 temp_reg, 0,
1791 V_SQ_ALU_SRC_LITERAL, 16,
1792 addr_reg, 0,
1793 temp_reg, 0);
1794 if (r)
1795 return r;
1796
1797 param = r600_get_lds_unique_index(name[first],
1798 index[first]);
1799
1800 } else {
1801 param = r600_get_lds_unique_index(name[reg.Register.Index],
1802 index[reg.Register.Index]);
1803 }
1804
1805 /* add to base_addr - passed in temp_reg.x */
1806 if (param) {
1807 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1808 temp_reg, 0,
1809 temp_reg, 0,
1810 V_SQ_ALU_SRC_LITERAL, param * 16);
1811 if (r)
1812 return r;
1813
1814 }
1815 return 0;
1816 }
1817
1818 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1819 unsigned dst_reg, unsigned mask)
1820 {
1821 struct r600_bytecode_alu alu;
1822 int r, i, lasti;
1823
1824 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1825 ctx->bc->force_add_cf = 1;
1826
1827 lasti = tgsi_last_instruction(mask);
1828 for (i = 1; i <= lasti; i++) {
1829 if (!(mask & (1 << i)))
1830 continue;
1831
1832 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1833 temp_reg, i,
1834 temp_reg, 0,
1835 V_SQ_ALU_SRC_LITERAL, 4 * i);
1836 if (r)
1837 return r;
1838 }
1839 for (i = 0; i <= lasti; i++) {
1840 if (!(mask & (1 << i)))
1841 continue;
1842
1843 /* emit an LDS_READ_RET */
1844 memset(&alu, 0, sizeof(alu));
1845 alu.op = LDS_OP1_LDS_READ_RET;
1846 alu.src[0].sel = temp_reg;
1847 alu.src[0].chan = i;
1848 alu.src[1].sel = V_SQ_ALU_SRC_0;
1849 alu.src[2].sel = V_SQ_ALU_SRC_0;
1850 alu.dst.chan = 0;
1851 alu.is_lds_idx_op = true;
1852 alu.last = 1;
1853 r = r600_bytecode_add_alu(ctx->bc, &alu);
1854 if (r)
1855 return r;
1856 }
1857 for (i = 0; i <= lasti; i++) {
1858 if (!(mask & (1 << i)))
1859 continue;
1860
1861 /* then read from LDS_OQ_A_POP */
1862 memset(&alu, 0, sizeof(alu));
1863
1864 alu.op = ALU_OP1_MOV;
1865 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1866 alu.src[0].chan = 0;
1867 alu.dst.sel = dst_reg;
1868 alu.dst.chan = i;
1869 alu.dst.write = 1;
1870 alu.last = 1;
1871 r = r600_bytecode_add_alu(ctx->bc, &alu);
1872 if (r)
1873 return r;
1874 }
1875 return 0;
1876 }
1877
1878 static int fetch_mask(struct tgsi_src_register *reg)
1879 {
1880 int mask = 0;
1881 mask |= 1 << reg->SwizzleX;
1882 mask |= 1 << reg->SwizzleY;
1883 mask |= 1 << reg->SwizzleZ;
1884 mask |= 1 << reg->SwizzleW;
1885 return mask;
1886 }
1887
1888 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1889 {
1890 int r;
1891 unsigned temp_reg = r600_get_temp(ctx);
1892
1893 r = get_lds_offset0(ctx, 2, temp_reg,
1894 src->Register.Dimension ? false : true);
1895 if (r)
1896 return r;
1897
1898 /* the base address is now in temp.x */
1899 r = r600_get_byte_address(ctx, temp_reg,
1900 NULL, src, ctx->tess_output_info, 1);
1901 if (r)
1902 return r;
1903
1904 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1905 if (r)
1906 return r;
1907 return 0;
1908 }
1909
1910 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1911 {
1912 int r;
1913 unsigned temp_reg = r600_get_temp(ctx);
1914
1915 /* t.x = ips * r0.y */
1916 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1917 temp_reg, 0,
1918 ctx->tess_input_info, 0,
1919 0, 1);
1920
1921 if (r)
1922 return r;
1923
1924 /* the base address is now in temp.x */
1925 r = r600_get_byte_address(ctx, temp_reg,
1926 NULL, src, ctx->tess_input_info, 1);
1927 if (r)
1928 return r;
1929
1930 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1931 if (r)
1932 return r;
1933 return 0;
1934 }
1935
1936 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1937 {
1938 int r;
1939 unsigned temp_reg = r600_get_temp(ctx);
1940
1941 r = get_lds_offset0(ctx, 1, temp_reg,
1942 src->Register.Dimension ? false : true);
1943 if (r)
1944 return r;
1945 /* the base address is now in temp.x */
1946 r = r600_get_byte_address(ctx, temp_reg,
1947 NULL, src,
1948 ctx->tess_output_info, 1);
1949 if (r)
1950 return r;
1951
1952 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1953 if (r)
1954 return r;
1955 return 0;
1956 }
1957
1958 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1959 {
1960 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1961 unsigned i;
1962
1963 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1964 struct tgsi_full_src_register *src = &inst->Src[i];
1965
1966 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1967 int treg = r600_get_temp(ctx);
1968 fetch_tes_input(ctx, src, treg);
1969 ctx->src[i].sel = treg;
1970 ctx->src[i].rel = 0;
1971 }
1972 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1973 int treg = r600_get_temp(ctx);
1974 fetch_tcs_input(ctx, src, treg);
1975 ctx->src[i].sel = treg;
1976 ctx->src[i].rel = 0;
1977 }
1978 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1979 int treg = r600_get_temp(ctx);
1980 fetch_tcs_output(ctx, src, treg);
1981 ctx->src[i].sel = treg;
1982 ctx->src[i].rel = 0;
1983 }
1984 }
1985 return 0;
1986 }
1987
1988 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1989 {
1990 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1991 struct r600_bytecode_alu alu;
1992 int i, j, k, nconst, r;
1993
1994 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1995 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1996 nconst++;
1997 }
1998 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1999 }
2000 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
2001 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
2002 continue;
2003 }
2004
2005 if (ctx->src[i].rel) {
2006 int chan = inst->Src[i].Indirect.Swizzle;
2007 int treg = r600_get_temp(ctx);
2008 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
2009 return r;
2010
2011 ctx->src[i].kc_bank = 0;
2012 ctx->src[i].kc_rel = 0;
2013 ctx->src[i].sel = treg;
2014 ctx->src[i].rel = 0;
2015 j--;
2016 } else if (j > 0) {
2017 int treg = r600_get_temp(ctx);
2018 for (k = 0; k < 4; k++) {
2019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2020 alu.op = ALU_OP1_MOV;
2021 alu.src[0].sel = ctx->src[i].sel;
2022 alu.src[0].chan = k;
2023 alu.src[0].rel = ctx->src[i].rel;
2024 alu.src[0].kc_bank = ctx->src[i].kc_bank;
2025 alu.src[0].kc_rel = ctx->src[i].kc_rel;
2026 alu.dst.sel = treg;
2027 alu.dst.chan = k;
2028 alu.dst.write = 1;
2029 if (k == 3)
2030 alu.last = 1;
2031 r = r600_bytecode_add_alu(ctx->bc, &alu);
2032 if (r)
2033 return r;
2034 }
2035 ctx->src[i].sel = treg;
2036 ctx->src[i].rel =0;
2037 j--;
2038 }
2039 }
2040 return 0;
2041 }
2042
2043 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
2044 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
2045 {
2046 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2047 struct r600_bytecode_alu alu;
2048 int i, j, k, nliteral, r;
2049
2050 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
2051 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2052 nliteral++;
2053 }
2054 }
2055 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
2056 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2057 int treg = r600_get_temp(ctx);
2058 for (k = 0; k < 4; k++) {
2059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2060 alu.op = ALU_OP1_MOV;
2061 alu.src[0].sel = ctx->src[i].sel;
2062 alu.src[0].chan = k;
2063 alu.src[0].value = ctx->src[i].value[k];
2064 alu.dst.sel = treg;
2065 alu.dst.chan = k;
2066 alu.dst.write = 1;
2067 if (k == 3)
2068 alu.last = 1;
2069 r = r600_bytecode_add_alu(ctx->bc, &alu);
2070 if (r)
2071 return r;
2072 }
2073 ctx->src[i].sel = treg;
2074 j--;
2075 }
2076 }
2077 return 0;
2078 }
2079
2080 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
2081 {
2082 int i, r, count = ctx->shader->ninput;
2083
2084 for (i = 0; i < count; i++) {
2085 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2086 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
2087 if (r)
2088 return r;
2089 }
2090 }
2091 return 0;
2092 }
2093
2094 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2095 int stream, unsigned *stream_item_size UNUSED)
2096 {
2097 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2098 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2099 int j, r;
2100 unsigned i;
2101
2102 /* Sanity checking. */
2103 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2104 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2105 r = -EINVAL;
2106 goto out_err;
2107 }
2108 for (i = 0; i < so->num_outputs; i++) {
2109 if (so->output[i].output_buffer >= 4) {
2110 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2111 so->output[i].output_buffer);
2112 r = -EINVAL;
2113 goto out_err;
2114 }
2115 }
2116
2117 /* Initialize locations where the outputs are stored. */
2118 for (i = 0; i < so->num_outputs; i++) {
2119
2120 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2121 start_comp[i] = so->output[i].start_component;
2122 /* Lower outputs with dst_offset < start_component.
2123 *
2124 * We can only output 4D vectors with a write mask, e.g. we can
2125 * only output the W component at offset 3, etc. If we want
2126 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2127 * to move it to X and output X. */
2128 if (so->output[i].dst_offset < so->output[i].start_component) {
2129 unsigned tmp = r600_get_temp(ctx);
2130
2131 for (j = 0; j < so->output[i].num_components; j++) {
2132 struct r600_bytecode_alu alu;
2133 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2134 alu.op = ALU_OP1_MOV;
2135 alu.src[0].sel = so_gpr[i];
2136 alu.src[0].chan = so->output[i].start_component + j;
2137
2138 alu.dst.sel = tmp;
2139 alu.dst.chan = j;
2140 alu.dst.write = 1;
2141 if (j == so->output[i].num_components - 1)
2142 alu.last = 1;
2143 r = r600_bytecode_add_alu(ctx->bc, &alu);
2144 if (r)
2145 return r;
2146 }
2147 start_comp[i] = 0;
2148 so_gpr[i] = tmp;
2149 }
2150 }
2151
2152 /* Write outputs to buffers. */
2153 for (i = 0; i < so->num_outputs; i++) {
2154 struct r600_bytecode_output output;
2155
2156 if (stream != -1 && stream != so->output[i].output_buffer)
2157 continue;
2158
2159 memset(&output, 0, sizeof(struct r600_bytecode_output));
2160 output.gpr = so_gpr[i];
2161 output.elem_size = so->output[i].num_components - 1;
2162 if (output.elem_size == 2)
2163 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2164 output.array_base = so->output[i].dst_offset - start_comp[i];
2165 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2166 output.burst_count = 1;
2167 /* array_size is an upper limit for the burst_count
2168 * with MEM_STREAM instructions */
2169 output.array_size = 0xFFF;
2170 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2171
2172 if (ctx->bc->chip_class >= EVERGREEN) {
2173 switch (so->output[i].output_buffer) {
2174 case 0:
2175 output.op = CF_OP_MEM_STREAM0_BUF0;
2176 break;
2177 case 1:
2178 output.op = CF_OP_MEM_STREAM0_BUF1;
2179 break;
2180 case 2:
2181 output.op = CF_OP_MEM_STREAM0_BUF2;
2182 break;
2183 case 3:
2184 output.op = CF_OP_MEM_STREAM0_BUF3;
2185 break;
2186 }
2187 output.op += so->output[i].stream * 4;
2188 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2189 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2190 } else {
2191 switch (so->output[i].output_buffer) {
2192 case 0:
2193 output.op = CF_OP_MEM_STREAM0;
2194 break;
2195 case 1:
2196 output.op = CF_OP_MEM_STREAM1;
2197 break;
2198 case 2:
2199 output.op = CF_OP_MEM_STREAM2;
2200 break;
2201 case 3:
2202 output.op = CF_OP_MEM_STREAM3;
2203 break;
2204 }
2205 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2206 }
2207 r = r600_bytecode_add_output(ctx->bc, &output);
2208 if (r)
2209 goto out_err;
2210 }
2211 return 0;
2212 out_err:
2213 return r;
2214 }
2215
2216 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2217 {
2218 struct r600_bytecode_alu alu;
2219 unsigned reg;
2220
2221 if (!ctx->shader->vs_out_edgeflag)
2222 return;
2223
2224 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2225
2226 /* clamp(x, 0, 1) */
2227 memset(&alu, 0, sizeof(alu));
2228 alu.op = ALU_OP1_MOV;
2229 alu.src[0].sel = reg;
2230 alu.dst.sel = reg;
2231 alu.dst.write = 1;
2232 alu.dst.clamp = 1;
2233 alu.last = 1;
2234 r600_bytecode_add_alu(ctx->bc, &alu);
2235
2236 memset(&alu, 0, sizeof(alu));
2237 alu.op = ALU_OP1_FLT_TO_INT;
2238 alu.src[0].sel = reg;
2239 alu.dst.sel = reg;
2240 alu.dst.write = 1;
2241 alu.last = 1;
2242 r600_bytecode_add_alu(ctx->bc, &alu);
2243 }
2244
2245 static int generate_gs_copy_shader(struct r600_context *rctx,
2246 struct r600_pipe_shader *gs,
2247 struct pipe_stream_output_info *so)
2248 {
2249 struct r600_shader_ctx ctx = {};
2250 struct r600_shader *gs_shader = &gs->shader;
2251 struct r600_pipe_shader *cshader;
2252 unsigned ocnt = gs_shader->noutput;
2253 struct r600_bytecode_alu alu;
2254 struct r600_bytecode_vtx vtx;
2255 struct r600_bytecode_output output;
2256 struct r600_bytecode_cf *cf_jump, *cf_pop,
2257 *last_exp_pos = NULL, *last_exp_param = NULL;
2258 int next_clip_pos = 61, next_param = 0;
2259 unsigned i, j;
2260 int ring;
2261 bool only_ring_0 = true;
2262 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2263 if (!cshader)
2264 return 0;
2265
2266 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2267 sizeof(struct r600_shader_io));
2268
2269 cshader->shader.noutput = ocnt;
2270
2271 ctx.shader = &cshader->shader;
2272 ctx.bc = &ctx.shader->bc;
2273 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2274
2275 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2276 rctx->screen->has_compressed_msaa_texturing);
2277
2278 ctx.bc->isa = rctx->isa;
2279
2280 cf_jump = NULL;
2281 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2282
2283 /* R0.x = R0.x & 0x3fffffff */
2284 memset(&alu, 0, sizeof(alu));
2285 alu.op = ALU_OP2_AND_INT;
2286 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2287 alu.src[1].value = 0x3fffffff;
2288 alu.dst.write = 1;
2289 r600_bytecode_add_alu(ctx.bc, &alu);
2290
2291 /* R0.y = R0.x >> 30 */
2292 memset(&alu, 0, sizeof(alu));
2293 alu.op = ALU_OP2_LSHR_INT;
2294 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2295 alu.src[1].value = 0x1e;
2296 alu.dst.chan = 1;
2297 alu.dst.write = 1;
2298 alu.last = 1;
2299 r600_bytecode_add_alu(ctx.bc, &alu);
2300
2301 /* fetch vertex data from GSVS ring */
2302 for (i = 0; i < ocnt; ++i) {
2303 struct r600_shader_io *out = &ctx.shader->output[i];
2304
2305 out->gpr = i + 1;
2306 out->ring_offset = i * 16;
2307
2308 memset(&vtx, 0, sizeof(vtx));
2309 vtx.op = FETCH_OP_VFETCH;
2310 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2311 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2312 vtx.mega_fetch_count = 16;
2313 vtx.offset = out->ring_offset;
2314 vtx.dst_gpr = out->gpr;
2315 vtx.src_gpr = 0;
2316 vtx.dst_sel_x = 0;
2317 vtx.dst_sel_y = 1;
2318 vtx.dst_sel_z = 2;
2319 vtx.dst_sel_w = 3;
2320 if (rctx->b.chip_class >= EVERGREEN) {
2321 vtx.use_const_fields = 1;
2322 } else {
2323 vtx.data_format = FMT_32_32_32_32_FLOAT;
2324 }
2325
2326 r600_bytecode_add_vtx(ctx.bc, &vtx);
2327 }
2328 ctx.temp_reg = i + 1;
2329 for (ring = 3; ring >= 0; --ring) {
2330 bool enabled = false;
2331 for (i = 0; i < so->num_outputs; i++) {
2332 if (so->output[i].stream == ring) {
2333 enabled = true;
2334 if (ring > 0)
2335 only_ring_0 = false;
2336 break;
2337 }
2338 }
2339 if (ring != 0 && !enabled) {
2340 cshader->shader.ring_item_sizes[ring] = 0;
2341 continue;
2342 }
2343
2344 if (cf_jump) {
2345 // Patch up jump label
2346 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2347 cf_pop = ctx.bc->cf_last;
2348
2349 cf_jump->cf_addr = cf_pop->id + 2;
2350 cf_jump->pop_count = 1;
2351 cf_pop->cf_addr = cf_pop->id + 2;
2352 cf_pop->pop_count = 1;
2353 }
2354
2355 /* PRED_SETE_INT __, R0.y, ring */
2356 memset(&alu, 0, sizeof(alu));
2357 alu.op = ALU_OP2_PRED_SETE_INT;
2358 alu.src[0].chan = 1;
2359 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2360 alu.src[1].value = ring;
2361 alu.execute_mask = 1;
2362 alu.update_pred = 1;
2363 alu.last = 1;
2364 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2365
2366 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2367 cf_jump = ctx.bc->cf_last;
2368
2369 if (enabled)
2370 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2371 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2372 }
2373
2374 /* bc adds nops - copy it */
2375 if (ctx.bc->chip_class == R600) {
2376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2377 alu.op = ALU_OP0_NOP;
2378 alu.last = 1;
2379 r600_bytecode_add_alu(ctx.bc, &alu);
2380
2381 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2382 }
2383
2384 /* export vertex data */
2385 /* XXX factor out common code with r600_shader_from_tgsi ? */
2386 for (i = 0; i < ocnt; ++i) {
2387 struct r600_shader_io *out = &ctx.shader->output[i];
2388 bool instream0 = true;
2389 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2390 continue;
2391
2392 for (j = 0; j < so->num_outputs; j++) {
2393 if (so->output[j].register_index == i) {
2394 if (so->output[j].stream == 0)
2395 break;
2396 if (so->output[j].stream > 0)
2397 instream0 = false;
2398 }
2399 }
2400 if (!instream0)
2401 continue;
2402 memset(&output, 0, sizeof(output));
2403 output.gpr = out->gpr;
2404 output.elem_size = 3;
2405 output.swizzle_x = 0;
2406 output.swizzle_y = 1;
2407 output.swizzle_z = 2;
2408 output.swizzle_w = 3;
2409 output.burst_count = 1;
2410 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2411 output.op = CF_OP_EXPORT;
2412 switch (out->name) {
2413 case TGSI_SEMANTIC_POSITION:
2414 output.array_base = 60;
2415 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2416 break;
2417
2418 case TGSI_SEMANTIC_PSIZE:
2419 output.array_base = 61;
2420 if (next_clip_pos == 61)
2421 next_clip_pos = 62;
2422 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2423 output.swizzle_y = 7;
2424 output.swizzle_z = 7;
2425 output.swizzle_w = 7;
2426 ctx.shader->vs_out_misc_write = 1;
2427 ctx.shader->vs_out_point_size = 1;
2428 break;
2429 case TGSI_SEMANTIC_LAYER:
2430 if (out->spi_sid) {
2431 /* duplicate it as PARAM to pass to the pixel shader */
2432 output.array_base = next_param++;
2433 r600_bytecode_add_output(ctx.bc, &output);
2434 last_exp_param = ctx.bc->cf_last;
2435 }
2436 output.array_base = 61;
2437 if (next_clip_pos == 61)
2438 next_clip_pos = 62;
2439 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2440 output.swizzle_x = 7;
2441 output.swizzle_y = 7;
2442 output.swizzle_z = 0;
2443 output.swizzle_w = 7;
2444 ctx.shader->vs_out_misc_write = 1;
2445 ctx.shader->vs_out_layer = 1;
2446 break;
2447 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2448 if (out->spi_sid) {
2449 /* duplicate it as PARAM to pass to the pixel shader */
2450 output.array_base = next_param++;
2451 r600_bytecode_add_output(ctx.bc, &output);
2452 last_exp_param = ctx.bc->cf_last;
2453 }
2454 output.array_base = 61;
2455 if (next_clip_pos == 61)
2456 next_clip_pos = 62;
2457 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2458 ctx.shader->vs_out_misc_write = 1;
2459 ctx.shader->vs_out_viewport = 1;
2460 output.swizzle_x = 7;
2461 output.swizzle_y = 7;
2462 output.swizzle_z = 7;
2463 output.swizzle_w = 0;
2464 break;
2465 case TGSI_SEMANTIC_CLIPDIST:
2466 /* spi_sid is 0 for clipdistance outputs that were generated
2467 * for clipvertex - we don't need to pass them to PS */
2468 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2469 ctx.shader->cull_dist_write = gs->shader.cull_dist_write;
2470 ctx.shader->cc_dist_mask = gs->shader.cc_dist_mask;
2471 if (out->spi_sid) {
2472 /* duplicate it as PARAM to pass to the pixel shader */
2473 output.array_base = next_param++;
2474 r600_bytecode_add_output(ctx.bc, &output);
2475 last_exp_param = ctx.bc->cf_last;
2476 }
2477 output.array_base = next_clip_pos++;
2478 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2479 break;
2480 case TGSI_SEMANTIC_FOG:
2481 output.swizzle_y = 4; /* 0 */
2482 output.swizzle_z = 4; /* 0 */
2483 output.swizzle_w = 5; /* 1 */
2484 break;
2485 default:
2486 output.array_base = next_param++;
2487 break;
2488 }
2489 r600_bytecode_add_output(ctx.bc, &output);
2490 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2491 last_exp_param = ctx.bc->cf_last;
2492 else
2493 last_exp_pos = ctx.bc->cf_last;
2494 }
2495
2496 if (!last_exp_pos) {
2497 memset(&output, 0, sizeof(output));
2498 output.gpr = 0;
2499 output.elem_size = 3;
2500 output.swizzle_x = 7;
2501 output.swizzle_y = 7;
2502 output.swizzle_z = 7;
2503 output.swizzle_w = 7;
2504 output.burst_count = 1;
2505 output.type = 2;
2506 output.op = CF_OP_EXPORT;
2507 output.array_base = 60;
2508 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2509 r600_bytecode_add_output(ctx.bc, &output);
2510 last_exp_pos = ctx.bc->cf_last;
2511 }
2512
2513 if (!last_exp_param) {
2514 memset(&output, 0, sizeof(output));
2515 output.gpr = 0;
2516 output.elem_size = 3;
2517 output.swizzle_x = 7;
2518 output.swizzle_y = 7;
2519 output.swizzle_z = 7;
2520 output.swizzle_w = 7;
2521 output.burst_count = 1;
2522 output.type = 2;
2523 output.op = CF_OP_EXPORT;
2524 output.array_base = next_param++;
2525 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2526 r600_bytecode_add_output(ctx.bc, &output);
2527 last_exp_param = ctx.bc->cf_last;
2528 }
2529
2530 last_exp_pos->op = CF_OP_EXPORT_DONE;
2531 last_exp_param->op = CF_OP_EXPORT_DONE;
2532
2533 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2534 cf_pop = ctx.bc->cf_last;
2535
2536 cf_jump->cf_addr = cf_pop->id + 2;
2537 cf_jump->pop_count = 1;
2538 cf_pop->cf_addr = cf_pop->id + 2;
2539 cf_pop->pop_count = 1;
2540
2541 if (ctx.bc->chip_class == CAYMAN)
2542 cm_bytecode_add_cf_end(ctx.bc);
2543 else {
2544 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2545 ctx.bc->cf_last->end_of_program = 1;
2546 }
2547
2548 gs->gs_copy_shader = cshader;
2549 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2550
2551 ctx.bc->nstack = 1;
2552
2553 return r600_bytecode_build(ctx.bc);
2554 }
2555
2556 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2557 {
2558 if (ind) {
2559 struct r600_bytecode_alu alu;
2560 int r;
2561
2562 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2563 alu.op = ALU_OP2_ADD_INT;
2564 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2565 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2566 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2567 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2568 alu.dst.write = 1;
2569 alu.last = 1;
2570 r = r600_bytecode_add_alu(ctx->bc, &alu);
2571 if (r)
2572 return r;
2573 }
2574 return 0;
2575 }
2576
2577 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so UNUSED, int stream, bool ind)
2578 {
2579 struct r600_bytecode_output output;
2580 int ring_offset;
2581 unsigned i, k;
2582 int effective_stream = stream == -1 ? 0 : stream;
2583 int idx = 0;
2584
2585 for (i = 0; i < ctx->shader->noutput; i++) {
2586 if (ctx->gs_for_vs) {
2587 /* for ES we need to lookup corresponding ring offset expected by GS
2588 * (map this output to GS input by name and sid) */
2589 /* FIXME precompute offsets */
2590 ring_offset = -1;
2591 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2592 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2593 struct r600_shader_io *out = &ctx->shader->output[i];
2594 if (in->name == out->name && in->sid == out->sid)
2595 ring_offset = in->ring_offset;
2596 }
2597
2598 if (ring_offset == -1)
2599 continue;
2600 } else {
2601 ring_offset = idx * 16;
2602 idx++;
2603 }
2604
2605 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2606 continue;
2607 /* next_ring_offset after parsing input decls contains total size of
2608 * single vertex data, gs_next_vertex - current vertex index */
2609 if (!ind)
2610 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2611
2612 memset(&output, 0, sizeof(struct r600_bytecode_output));
2613 output.gpr = ctx->shader->output[i].gpr;
2614 output.elem_size = 3;
2615 output.comp_mask = 0xF;
2616 output.burst_count = 1;
2617
2618 if (ind)
2619 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2620 else
2621 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2622
2623 switch (stream) {
2624 default:
2625 case 0:
2626 output.op = CF_OP_MEM_RING; break;
2627 case 1:
2628 output.op = CF_OP_MEM_RING1; break;
2629 case 2:
2630 output.op = CF_OP_MEM_RING2; break;
2631 case 3:
2632 output.op = CF_OP_MEM_RING3; break;
2633 }
2634
2635 if (ind) {
2636 output.array_base = ring_offset >> 2; /* in dwords */
2637 output.array_size = 0xfff;
2638 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2639 } else
2640 output.array_base = ring_offset >> 2; /* in dwords */
2641 r600_bytecode_add_output(ctx->bc, &output);
2642 }
2643
2644 ++ctx->gs_next_vertex;
2645 return 0;
2646 }
2647
2648
2649 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2650 {
2651 int r;
2652 struct r600_bytecode_vtx vtx;
2653 int temp_val = ctx->temp_reg;
2654 /* need to store the TCS output somewhere */
2655 r = single_alu_op2(ctx, ALU_OP1_MOV,
2656 temp_val, 0,
2657 V_SQ_ALU_SRC_LITERAL, 0,
2658 0, 0);
2659 if (r)
2660 return r;
2661
2662 /* used by VS/TCS */
2663 if (ctx->tess_input_info) {
2664 /* fetch tcs input values into resv space */
2665 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2666 vtx.op = FETCH_OP_VFETCH;
2667 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2668 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2669 vtx.mega_fetch_count = 16;
2670 vtx.data_format = FMT_32_32_32_32;
2671 vtx.num_format_all = 2;
2672 vtx.format_comp_all = 1;
2673 vtx.use_const_fields = 0;
2674 vtx.endian = r600_endian_swap(32);
2675 vtx.srf_mode_all = 1;
2676 vtx.offset = 0;
2677 vtx.dst_gpr = ctx->tess_input_info;
2678 vtx.dst_sel_x = 0;
2679 vtx.dst_sel_y = 1;
2680 vtx.dst_sel_z = 2;
2681 vtx.dst_sel_w = 3;
2682 vtx.src_gpr = temp_val;
2683 vtx.src_sel_x = 0;
2684
2685 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2686 if (r)
2687 return r;
2688 }
2689
2690 /* used by TCS/TES */
2691 if (ctx->tess_output_info) {
2692 /* fetch tcs output values into resv space */
2693 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2694 vtx.op = FETCH_OP_VFETCH;
2695 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2696 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2697 vtx.mega_fetch_count = 16;
2698 vtx.data_format = FMT_32_32_32_32;
2699 vtx.num_format_all = 2;
2700 vtx.format_comp_all = 1;
2701 vtx.use_const_fields = 0;
2702 vtx.endian = r600_endian_swap(32);
2703 vtx.srf_mode_all = 1;
2704 vtx.offset = 16;
2705 vtx.dst_gpr = ctx->tess_output_info;
2706 vtx.dst_sel_x = 0;
2707 vtx.dst_sel_y = 1;
2708 vtx.dst_sel_z = 2;
2709 vtx.dst_sel_w = 3;
2710 vtx.src_gpr = temp_val;
2711 vtx.src_sel_x = 0;
2712
2713 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2714 if (r)
2715 return r;
2716 }
2717 return 0;
2718 }
2719
2720 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2721 {
2722 int j, r;
2723 int temp_reg;
2724 unsigned i;
2725
2726 /* fetch tcs input values into input_vals */
2727 ctx->tess_input_info = r600_get_temp(ctx);
2728 ctx->tess_output_info = 0;
2729 r = r600_fetch_tess_io_info(ctx);
2730 if (r)
2731 return r;
2732
2733 temp_reg = r600_get_temp(ctx);
2734 /* dst reg contains LDS address stride * idx */
2735 /* MUL vertexID, vertex_dw_stride */
2736 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2737 temp_reg, 0,
2738 ctx->tess_input_info, 1,
2739 0, 1); /* rel id in r0.y? */
2740 if (r)
2741 return r;
2742
2743 for (i = 0; i < ctx->shader->noutput; i++) {
2744 struct r600_bytecode_alu alu;
2745 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2746
2747 if (param) {
2748 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2749 temp_reg, 1,
2750 temp_reg, 0,
2751 V_SQ_ALU_SRC_LITERAL, param * 16);
2752 if (r)
2753 return r;
2754 }
2755
2756 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2757 temp_reg, 2,
2758 temp_reg, param ? 1 : 0,
2759 V_SQ_ALU_SRC_LITERAL, 8);
2760 if (r)
2761 return r;
2762
2763
2764 for (j = 0; j < 2; j++) {
2765 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2766 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2767 alu.op = LDS_OP3_LDS_WRITE_REL;
2768 alu.src[0].sel = temp_reg;
2769 alu.src[0].chan = chan;
2770 alu.src[1].sel = ctx->shader->output[i].gpr;
2771 alu.src[1].chan = j * 2;
2772 alu.src[2].sel = ctx->shader->output[i].gpr;
2773 alu.src[2].chan = (j * 2) + 1;
2774 alu.last = 1;
2775 alu.dst.chan = 0;
2776 alu.lds_idx = 1;
2777 alu.is_lds_idx_op = true;
2778 r = r600_bytecode_add_alu(ctx->bc, &alu);
2779 if (r)
2780 return r;
2781 }
2782 }
2783 return 0;
2784 }
2785
2786 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2787 {
2788 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2789 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2790 int i, r, lasti;
2791 int temp_reg = r600_get_temp(ctx);
2792 struct r600_bytecode_alu alu;
2793 unsigned write_mask = dst->Register.WriteMask;
2794
2795 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2796 return 0;
2797
2798 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2799 if (r)
2800 return r;
2801
2802 /* the base address is now in temp.x */
2803 r = r600_get_byte_address(ctx, temp_reg,
2804 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2805 if (r)
2806 return r;
2807
2808 /* LDS write */
2809 lasti = tgsi_last_instruction(write_mask);
2810 for (i = 1; i <= lasti; i++) {
2811
2812 if (!(write_mask & (1 << i)))
2813 continue;
2814 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2815 temp_reg, i,
2816 temp_reg, 0,
2817 V_SQ_ALU_SRC_LITERAL, 4 * i);
2818 if (r)
2819 return r;
2820 }
2821
2822 for (i = 0; i <= lasti; i++) {
2823 if (!(write_mask & (1 << i)))
2824 continue;
2825
2826 if ((i == 0 && ((write_mask & 3) == 3)) ||
2827 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2829 alu.op = LDS_OP3_LDS_WRITE_REL;
2830 alu.src[0].sel = temp_reg;
2831 alu.src[0].chan = i;
2832
2833 alu.src[1].sel = dst->Register.Index;
2834 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2835 alu.src[1].chan = i;
2836
2837 alu.src[2].sel = dst->Register.Index;
2838 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2839 alu.src[2].chan = i + 1;
2840 alu.lds_idx = 1;
2841 alu.dst.chan = 0;
2842 alu.last = 1;
2843 alu.is_lds_idx_op = true;
2844 r = r600_bytecode_add_alu(ctx->bc, &alu);
2845 if (r)
2846 return r;
2847 i += 1;
2848 continue;
2849 }
2850 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2851 alu.op = LDS_OP2_LDS_WRITE;
2852 alu.src[0].sel = temp_reg;
2853 alu.src[0].chan = i;
2854
2855 alu.src[1].sel = dst->Register.Index;
2856 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2857 alu.src[1].chan = i;
2858
2859 alu.src[2].sel = V_SQ_ALU_SRC_0;
2860 alu.dst.chan = 0;
2861 alu.last = 1;
2862 alu.is_lds_idx_op = true;
2863 r = r600_bytecode_add_alu(ctx->bc, &alu);
2864 if (r)
2865 return r;
2866 }
2867 return 0;
2868 }
2869
2870 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2871 int output_idx)
2872 {
2873 int param;
2874 unsigned temp_reg = r600_get_temp(ctx);
2875 unsigned name = ctx->shader->output[output_idx].name;
2876 int dreg = ctx->shader->output[output_idx].gpr;
2877 int r;
2878
2879 param = r600_get_lds_unique_index(name, 0);
2880 r = get_lds_offset0(ctx, 1, temp_reg, true);
2881 if (r)
2882 return r;
2883
2884 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2885 temp_reg, 0,
2886 temp_reg, 0,
2887 V_SQ_ALU_SRC_LITERAL, param * 16);
2888 if (r)
2889 return r;
2890
2891 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
2892 return 0;
2893 }
2894
2895 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2896 {
2897 int stride, outer_comps, inner_comps;
2898 int tessinner_idx = -1, tessouter_idx = -1;
2899 int i, r;
2900 unsigned j;
2901 int temp_reg = r600_get_temp(ctx);
2902 int treg[3] = {-1, -1, -1};
2903 struct r600_bytecode_alu alu;
2904 struct r600_bytecode_cf *cf_jump, *cf_pop;
2905
2906 /* only execute factor emission for invocation 0 */
2907 /* PRED_SETE_INT __, R0.x, 0 */
2908 memset(&alu, 0, sizeof(alu));
2909 alu.op = ALU_OP2_PRED_SETE_INT;
2910 alu.src[0].chan = 2;
2911 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2912 alu.execute_mask = 1;
2913 alu.update_pred = 1;
2914 alu.last = 1;
2915 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2916
2917 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2918 cf_jump = ctx->bc->cf_last;
2919
2920 treg[0] = r600_get_temp(ctx);
2921 switch (ctx->shader->tcs_prim_mode) {
2922 case PIPE_PRIM_LINES:
2923 stride = 8; /* 2 dwords, 1 vec2 store */
2924 outer_comps = 2;
2925 inner_comps = 0;
2926 break;
2927 case PIPE_PRIM_TRIANGLES:
2928 stride = 16; /* 4 dwords, 1 vec4 store */
2929 outer_comps = 3;
2930 inner_comps = 1;
2931 treg[1] = r600_get_temp(ctx);
2932 break;
2933 case PIPE_PRIM_QUADS:
2934 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2935 outer_comps = 4;
2936 inner_comps = 2;
2937 treg[1] = r600_get_temp(ctx);
2938 treg[2] = r600_get_temp(ctx);
2939 break;
2940 default:
2941 assert(0);
2942 return -1;
2943 }
2944
2945 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2946 /* TF_WRITE takes index in R.x, value in R.y */
2947 for (j = 0; j < ctx->shader->noutput; j++) {
2948 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSINNER)
2949 tessinner_idx = j;
2950 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSOUTER)
2951 tessouter_idx = j;
2952 }
2953
2954 if (tessouter_idx == -1)
2955 return -1;
2956
2957 if (tessinner_idx == -1 && inner_comps)
2958 return -1;
2959
2960 if (tessouter_idx != -1) {
2961 r = r600_tess_factor_read(ctx, tessouter_idx);
2962 if (r)
2963 return r;
2964 }
2965
2966 if (tessinner_idx != -1) {
2967 r = r600_tess_factor_read(ctx, tessinner_idx);
2968 if (r)
2969 return r;
2970 }
2971
2972 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2973 /* r.x = relpatchid(r0.y) * tf_stride */
2974
2975 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2976 /* add incoming r0.w to it: t.x = t.x + r0.w */
2977 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2978 temp_reg, 0,
2979 0, 1,
2980 V_SQ_ALU_SRC_LITERAL, stride,
2981 0, 3);
2982 if (r)
2983 return r;
2984
2985 for (i = 0; i < outer_comps + inner_comps; i++) {
2986 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2987 int out_comp = i >= outer_comps ? i - outer_comps : i;
2988
2989 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2990 if (out_comp == 1)
2991 out_comp = 0;
2992 else if (out_comp == 0)
2993 out_comp = 1;
2994 }
2995
2996 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2997 treg[i / 2], (2 * (i % 2)),
2998 temp_reg, 0,
2999 V_SQ_ALU_SRC_LITERAL, 4 * i);
3000 if (r)
3001 return r;
3002 r = single_alu_op2(ctx, ALU_OP1_MOV,
3003 treg[i / 2], 1 + (2 * (i%2)),
3004 ctx->shader->output[out_idx].gpr, out_comp,
3005 0, 0);
3006 if (r)
3007 return r;
3008 }
3009 for (i = 0; i < outer_comps + inner_comps; i++) {
3010 struct r600_bytecode_gds gds;
3011
3012 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
3013 gds.src_gpr = treg[i / 2];
3014 gds.src_sel_x = 2 * (i % 2);
3015 gds.src_sel_y = 1 + (2 * (i % 2));
3016 gds.src_sel_z = 4;
3017 gds.dst_sel_x = 7;
3018 gds.dst_sel_y = 7;
3019 gds.dst_sel_z = 7;
3020 gds.dst_sel_w = 7;
3021 gds.op = FETCH_OP_TF_WRITE;
3022 r = r600_bytecode_add_gds(ctx->bc, &gds);
3023 if (r)
3024 return r;
3025 }
3026
3027 // Patch up jump label
3028 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
3029 cf_pop = ctx->bc->cf_last;
3030
3031 cf_jump->cf_addr = cf_pop->id + 2;
3032 cf_jump->pop_count = 1;
3033 cf_pop->cf_addr = cf_pop->id + 2;
3034 cf_pop->pop_count = 1;
3035
3036 return 0;
3037 }
3038
3039 /*
3040 * We have to work out the thread ID for load and atomic
3041 * operations, which store the returned value to an index
3042 * in an intermediate buffer.
3043 * The index is calculated by taking the thread id,
3044 * calculated from the MBCNT instructions.
3045 * Then the shader engine ID is multiplied by 256,
3046 * and the wave id is added.
3047 * Then the result is multipled by 64 and thread id is
3048 * added.
3049 */
3050 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
3051 {
3052 struct r600_bytecode_alu alu;
3053 int r;
3054
3055 if (ctx->thread_id_gpr_loaded)
3056 return 0;
3057
3058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3059 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
3060 alu.dst.sel = ctx->temp_reg;
3061 alu.dst.chan = 0;
3062 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3063 alu.src[0].value = 0xffffffff;
3064 alu.dst.write = 1;
3065 r = r600_bytecode_add_alu(ctx->bc, &alu);
3066 if (r)
3067 return r;
3068
3069 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3070 alu.op = ALU_OP1_MBCNT_32HI_INT;
3071 alu.dst.sel = ctx->temp_reg;
3072 alu.dst.chan = 1;
3073 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3074 alu.src[0].value = 0xffffffff;
3075 alu.dst.write = 1;
3076 r = r600_bytecode_add_alu(ctx->bc, &alu);
3077 if (r)
3078 return r;
3079
3080 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3081 alu.op = ALU_OP3_MULADD_UINT24;
3082 alu.dst.sel = ctx->temp_reg;
3083 alu.dst.chan = 2;
3084 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
3085 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3086 alu.src[1].value = 256;
3087 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
3088 alu.dst.write = 1;
3089 alu.is_op3 = 1;
3090 alu.last = 1;
3091 r = r600_bytecode_add_alu(ctx->bc, &alu);
3092 if (r)
3093 return r;
3094
3095 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3096 ctx->thread_id_gpr, 1,
3097 ctx->temp_reg, 2,
3098 V_SQ_ALU_SRC_LITERAL, 0x40,
3099 ctx->temp_reg, 0);
3100 if (r)
3101 return r;
3102 ctx->thread_id_gpr_loaded = true;
3103 return 0;
3104 }
3105
3106 static int r600_shader_from_tgsi(struct r600_context *rctx,
3107 struct r600_pipe_shader *pipeshader,
3108 union r600_shader_key key)
3109 {
3110 struct r600_screen *rscreen = rctx->screen;
3111 struct r600_shader *shader = &pipeshader->shader;
3112 struct tgsi_token *tokens = pipeshader->selector->tokens;
3113 struct pipe_stream_output_info so = pipeshader->selector->so;
3114 struct tgsi_full_immediate *immediate;
3115 struct r600_shader_ctx ctx;
3116 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3117 unsigned output_done, noutput;
3118 unsigned opcode;
3119 int j, k, r = 0;
3120 unsigned i;
3121 int next_param_base = 0, next_clip_base;
3122 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3123 bool indirect_gprs;
3124 bool ring_outputs = false;
3125 bool lds_outputs = false;
3126 bool lds_inputs = false;
3127 bool pos_emitted = false;
3128
3129 ctx.bc = &shader->bc;
3130 ctx.shader = shader;
3131 ctx.native_integers = true;
3132
3133 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3134 rscreen->has_compressed_msaa_texturing);
3135 ctx.tokens = tokens;
3136 tgsi_scan_shader(tokens, &ctx.info);
3137 shader->indirect_files = ctx.info.indirect_files;
3138
3139 shader->uses_doubles = ctx.info.uses_doubles;
3140 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3141 shader->nsys_inputs = 0;
3142
3143 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0 ||
3144 ctx.info.file_count[TGSI_FILE_BUFFER] > 0;
3145 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3146 tgsi_parse_init(&ctx.parse, tokens);
3147 ctx.type = ctx.info.processor;
3148 shader->processor_type = ctx.type;
3149 ctx.bc->type = shader->processor_type;
3150
3151 switch (ctx.type) {
3152 case PIPE_SHADER_VERTEX:
3153 shader->vs_as_gs_a = key.vs.as_gs_a;
3154 shader->vs_as_es = key.vs.as_es;
3155 shader->vs_as_ls = key.vs.as_ls;
3156 shader->atomic_base = key.vs.first_atomic_counter;
3157 if (shader->vs_as_es)
3158 ring_outputs = true;
3159 if (shader->vs_as_ls)
3160 lds_outputs = true;
3161 break;
3162 case PIPE_SHADER_GEOMETRY:
3163 ring_outputs = true;
3164 shader->atomic_base = key.gs.first_atomic_counter;
3165 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3166 break;
3167 case PIPE_SHADER_TESS_CTRL:
3168 shader->tcs_prim_mode = key.tcs.prim_mode;
3169 shader->atomic_base = key.tcs.first_atomic_counter;
3170 lds_outputs = true;
3171 lds_inputs = true;
3172 break;
3173 case PIPE_SHADER_TESS_EVAL:
3174 shader->tes_as_es = key.tes.as_es;
3175 shader->atomic_base = key.tes.first_atomic_counter;
3176 lds_inputs = true;
3177 if (shader->tes_as_es)
3178 ring_outputs = true;
3179 break;
3180 case PIPE_SHADER_FRAGMENT:
3181 shader->two_side = key.ps.color_two_side;
3182 shader->atomic_base = key.ps.first_atomic_counter;
3183 shader->rat_base = key.ps.nr_cbufs;
3184 shader->image_size_const_offset = key.ps.image_size_const_offset;
3185 break;
3186 case PIPE_SHADER_COMPUTE:
3187 shader->rat_base = 0;
3188 shader->image_size_const_offset = 0;
3189 break;
3190 default:
3191 break;
3192 }
3193
3194 if (shader->vs_as_es || shader->tes_as_es) {
3195 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3196 } else {
3197 ctx.gs_for_vs = NULL;
3198 }
3199
3200 ctx.next_ring_offset = 0;
3201 ctx.gs_out_ring_offset = 0;
3202 ctx.gs_next_vertex = 0;
3203 ctx.gs_stream_output_info = &so;
3204
3205 ctx.face_gpr = -1;
3206 ctx.fixed_pt_position_gpr = -1;
3207 ctx.fragcoord_input = -1;
3208 ctx.colors_used = 0;
3209 ctx.clip_vertex_write = 0;
3210 ctx.thread_id_gpr_loaded = false;
3211
3212 ctx.cs_block_size_reg = -1;
3213 ctx.cs_grid_size_reg = -1;
3214 ctx.cs_block_size_loaded = false;
3215 ctx.cs_grid_size_loaded = false;
3216
3217 shader->nr_ps_color_exports = 0;
3218 shader->nr_ps_max_color_exports = 0;
3219
3220
3221 /* register allocations */
3222 /* Values [0,127] correspond to GPR[0..127].
3223 * Values [128,159] correspond to constant buffer bank 0
3224 * Values [160,191] correspond to constant buffer bank 1
3225 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3226 * Values [256,287] correspond to constant buffer bank 2 (EG)
3227 * Values [288,319] correspond to constant buffer bank 3 (EG)
3228 * Other special values are shown in the list below.
3229 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3230 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3231 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3232 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3233 * 248 SQ_ALU_SRC_0: special constant 0.0.
3234 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3235 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3236 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3237 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3238 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3239 * 254 SQ_ALU_SRC_PV: previous vector result.
3240 * 255 SQ_ALU_SRC_PS: previous scalar result.
3241 */
3242 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3243 ctx.file_offset[i] = 0;
3244 }
3245
3246 if (ctx.type == PIPE_SHADER_VERTEX) {
3247
3248 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3249 if (ctx.info.num_inputs)
3250 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3251 }
3252 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3253 if (ctx.bc->chip_class >= EVERGREEN)
3254 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3255 else
3256 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3257 }
3258 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3259 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3260 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3261 }
3262 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3263 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3264 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3265 bool add_tesscoord = false, add_tess_inout = false;
3266 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3267 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3268 /* if we have tesscoord save one reg */
3269 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3270 add_tesscoord = true;
3271 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3272 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3273 add_tess_inout = true;
3274 }
3275 if (add_tesscoord || add_tess_inout)
3276 ctx.file_offset[TGSI_FILE_INPUT]++;
3277 if (add_tess_inout)
3278 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3279 }
3280 if (ctx.type == PIPE_SHADER_COMPUTE) {
3281 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3282 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3283 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_GRID_SIZE)
3284 ctx.cs_grid_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3285 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_BLOCK_SIZE)
3286 ctx.cs_block_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3287 }
3288 }
3289
3290 ctx.file_offset[TGSI_FILE_OUTPUT] =
3291 ctx.file_offset[TGSI_FILE_INPUT] +
3292 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3293 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3294 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3295
3296 /* Outside the GPR range. This will be translated to one of the
3297 * kcache banks later. */
3298 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3299
3300 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3301 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3302 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3303 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3304 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3305
3306 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3307 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3308 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3309 ctx.temp_reg = ctx.bc->ar_reg + 5;
3310 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3311 ctx.tess_input_info = 0;
3312 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3313 ctx.temp_reg = ctx.bc->ar_reg + 4;
3314 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3315 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3316 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3317 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3318 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3319 ctx.temp_reg = ctx.bc->ar_reg + 7;
3320 if (ctx.shader->gs_tri_strip_adj_fix) {
3321 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3322 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3323 ctx.temp_reg += 2;
3324 } else {
3325 ctx.gs_rotated_input[0] = 0;
3326 ctx.gs_rotated_input[1] = 1;
3327 }
3328 } else {
3329 ctx.temp_reg = ctx.bc->ar_reg + 3;
3330 }
3331
3332 if (shader->uses_images) {
3333 ctx.thread_id_gpr = ctx.temp_reg++;
3334 ctx.thread_id_gpr_loaded = false;
3335 }
3336
3337 shader->max_arrays = 0;
3338 shader->num_arrays = 0;
3339 if (indirect_gprs) {
3340
3341 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3342 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3343 ctx.file_offset[TGSI_FILE_OUTPUT] -
3344 ctx.file_offset[TGSI_FILE_INPUT],
3345 0x0F);
3346 }
3347 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3348 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3349 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3350 ctx.file_offset[TGSI_FILE_OUTPUT],
3351 0x0F);
3352 }
3353 }
3354
3355 ctx.nliterals = 0;
3356 ctx.literals = NULL;
3357
3358 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3359 ctx.info.colors_written == 1;
3360 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3361 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3362
3363 if (ctx.type == PIPE_SHADER_VERTEX ||
3364 ctx.type == PIPE_SHADER_GEOMETRY ||
3365 ctx.type == PIPE_SHADER_TESS_EVAL) {
3366 shader->cc_dist_mask = (1 << (ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED] +
3367 ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED])) - 1;
3368 shader->clip_dist_write = (1 << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED]) - 1;
3369 shader->cull_dist_write = ((1 << ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED]) - 1) << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED];
3370 }
3371
3372 if (shader->vs_as_gs_a)
3373 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3374
3375 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3376 r600_fetch_tess_io_info(&ctx);
3377
3378 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3379 tgsi_parse_token(&ctx.parse);
3380 switch (ctx.parse.FullToken.Token.Type) {
3381 case TGSI_TOKEN_TYPE_IMMEDIATE:
3382 immediate = &ctx.parse.FullToken.FullImmediate;
3383 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3384 if(ctx.literals == NULL) {
3385 r = -ENOMEM;
3386 goto out_err;
3387 }
3388 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3389 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3390 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3391 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3392 ctx.nliterals++;
3393 break;
3394 case TGSI_TOKEN_TYPE_DECLARATION:
3395 r = tgsi_declaration(&ctx);
3396 if (r)
3397 goto out_err;
3398 break;
3399 case TGSI_TOKEN_TYPE_INSTRUCTION:
3400 case TGSI_TOKEN_TYPE_PROPERTY:
3401 break;
3402 default:
3403 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3404 r = -EINVAL;
3405 goto out_err;
3406 }
3407 }
3408
3409 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3410 shader->ring_item_sizes[1] = 0;
3411 shader->ring_item_sizes[2] = 0;
3412 shader->ring_item_sizes[3] = 0;
3413
3414 /* Process two side if needed */
3415 if (shader->two_side && ctx.colors_used) {
3416 int i, count = ctx.shader->ninput;
3417 unsigned next_lds_loc = ctx.shader->nlds;
3418
3419 /* additional inputs will be allocated right after the existing inputs,
3420 * we won't need them after the color selection, so we don't need to
3421 * reserve these gprs for the rest of the shader code and to adjust
3422 * output offsets etc. */
3423 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3424 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3425
3426 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3427 if (ctx.face_gpr == -1) {
3428 i = ctx.shader->ninput++;
3429 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3430 ctx.shader->input[i].spi_sid = 0;
3431 ctx.shader->input[i].gpr = gpr++;
3432 ctx.face_gpr = ctx.shader->input[i].gpr;
3433 }
3434
3435 for (i = 0; i < count; i++) {
3436 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3437 int ni = ctx.shader->ninput++;
3438 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3439 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3440 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3441 ctx.shader->input[ni].gpr = gpr++;
3442 // TGSI to LLVM needs to know the lds position of inputs.
3443 // Non LLVM path computes it later (in process_twoside_color)
3444 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3445 ctx.shader->input[i].back_color_input = ni;
3446 if (ctx.bc->chip_class >= EVERGREEN) {
3447 if ((r = evergreen_interp_input(&ctx, ni)))
3448 return r;
3449 }
3450 }
3451 }
3452 }
3453
3454 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3455 shader->nr_ps_max_color_exports = 8;
3456
3457 if (ctx.fragcoord_input >= 0) {
3458 if (ctx.bc->chip_class == CAYMAN) {
3459 for (j = 0 ; j < 4; j++) {
3460 struct r600_bytecode_alu alu;
3461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3462 alu.op = ALU_OP1_RECIP_IEEE;
3463 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3464 alu.src[0].chan = 3;
3465
3466 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3467 alu.dst.chan = j;
3468 alu.dst.write = (j == 3);
3469 alu.last = 1;
3470 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3471 return r;
3472 }
3473 } else {
3474 struct r600_bytecode_alu alu;
3475 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3476 alu.op = ALU_OP1_RECIP_IEEE;
3477 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3478 alu.src[0].chan = 3;
3479
3480 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3481 alu.dst.chan = 3;
3482 alu.dst.write = 1;
3483 alu.last = 1;
3484 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3485 return r;
3486 }
3487 }
3488
3489 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3490 struct r600_bytecode_alu alu;
3491 int r;
3492
3493 /* GS thread with no output workaround - emit a cut at start of GS */
3494 if (ctx.bc->chip_class == R600)
3495 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3496
3497 for (j = 0; j < 4; j++) {
3498 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3499 alu.op = ALU_OP1_MOV;
3500 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3501 alu.src[0].value = 0;
3502 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3503 alu.dst.write = 1;
3504 alu.last = 1;
3505 r = r600_bytecode_add_alu(ctx.bc, &alu);
3506 if (r)
3507 return r;
3508 }
3509
3510 if (ctx.shader->gs_tri_strip_adj_fix) {
3511 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3512 ctx.gs_rotated_input[0], 2,
3513 0, 2,
3514 V_SQ_ALU_SRC_LITERAL, 1);
3515 if (r)
3516 return r;
3517
3518 for (i = 0; i < 6; i++) {
3519 int rotated = (i + 4) % 6;
3520 int offset_reg = i / 3;
3521 int offset_chan = i % 3;
3522 int rotated_offset_reg = rotated / 3;
3523 int rotated_offset_chan = rotated % 3;
3524
3525 if (offset_reg == 0 && offset_chan == 2)
3526 offset_chan = 3;
3527 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3528 rotated_offset_chan = 3;
3529
3530 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3531 ctx.gs_rotated_input[offset_reg], offset_chan,
3532 ctx.gs_rotated_input[0], 2,
3533 offset_reg, offset_chan,
3534 rotated_offset_reg, rotated_offset_chan);
3535 if (r)
3536 return r;
3537 }
3538 }
3539 }
3540
3541 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3542 r600_fetch_tess_io_info(&ctx);
3543
3544 if (shader->two_side && ctx.colors_used) {
3545 if ((r = process_twoside_color_inputs(&ctx)))
3546 return r;
3547 }
3548
3549 tgsi_parse_init(&ctx.parse, tokens);
3550 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3551 tgsi_parse_token(&ctx.parse);
3552 switch (ctx.parse.FullToken.Token.Type) {
3553 case TGSI_TOKEN_TYPE_INSTRUCTION:
3554 r = tgsi_is_supported(&ctx);
3555 if (r)
3556 goto out_err;
3557 ctx.max_driver_temp_used = 0;
3558 /* reserve first tmp for everyone */
3559 r600_get_temp(&ctx);
3560
3561 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3562 if ((r = tgsi_split_constant(&ctx)))
3563 goto out_err;
3564 if ((r = tgsi_split_literal_constant(&ctx)))
3565 goto out_err;
3566 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3567 if ((r = tgsi_split_gs_inputs(&ctx)))
3568 goto out_err;
3569 } else if (lds_inputs) {
3570 if ((r = tgsi_split_lds_inputs(&ctx)))
3571 goto out_err;
3572 }
3573 if (ctx.bc->chip_class == CAYMAN)
3574 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3575 else if (ctx.bc->chip_class >= EVERGREEN)
3576 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3577 else
3578 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3579 r = ctx.inst_info->process(&ctx);
3580 if (r)
3581 goto out_err;
3582
3583 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3584 r = r600_store_tcs_output(&ctx);
3585 if (r)
3586 goto out_err;
3587 }
3588 break;
3589 default:
3590 break;
3591 }
3592 }
3593
3594 /* Reset the temporary register counter. */
3595 ctx.max_driver_temp_used = 0;
3596
3597 noutput = shader->noutput;
3598
3599 if (!ring_outputs && ctx.clip_vertex_write) {
3600 unsigned clipdist_temp[2];
3601
3602 clipdist_temp[0] = r600_get_temp(&ctx);
3603 clipdist_temp[1] = r600_get_temp(&ctx);
3604
3605 /* need to convert a clipvertex write into clipdistance writes and not export
3606 the clip vertex anymore */
3607
3608 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3609 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3610 shader->output[noutput].gpr = clipdist_temp[0];
3611 noutput++;
3612 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3613 shader->output[noutput].gpr = clipdist_temp[1];
3614 noutput++;
3615
3616 /* reset spi_sid for clipvertex output to avoid confusing spi */
3617 shader->output[ctx.cv_output].spi_sid = 0;
3618
3619 shader->clip_dist_write = 0xFF;
3620 shader->cc_dist_mask = 0xFF;
3621
3622 for (i = 0; i < 8; i++) {
3623 int oreg = i >> 2;
3624 int ochan = i & 3;
3625
3626 for (j = 0; j < 4; j++) {
3627 struct r600_bytecode_alu alu;
3628 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3629 alu.op = ALU_OP2_DOT4;
3630 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3631 alu.src[0].chan = j;
3632
3633 alu.src[1].sel = 512 + i;
3634 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3635 alu.src[1].chan = j;
3636
3637 alu.dst.sel = clipdist_temp[oreg];
3638 alu.dst.chan = j;
3639 alu.dst.write = (j == ochan);
3640 if (j == 3)
3641 alu.last = 1;
3642 r = r600_bytecode_add_alu(ctx.bc, &alu);
3643 if (r)
3644 return r;
3645 }
3646 }
3647 }
3648
3649 /* Add stream outputs. */
3650 if (so.num_outputs) {
3651 bool emit = false;
3652 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3653 emit = true;
3654 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3655 emit = true;
3656 if (emit)
3657 emit_streamout(&ctx, &so, -1, NULL);
3658 }
3659 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3660 convert_edgeflag_to_int(&ctx);
3661
3662 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3663 r600_emit_tess_factor(&ctx);
3664
3665 if (lds_outputs) {
3666 if (ctx.type == PIPE_SHADER_VERTEX) {
3667 if (ctx.shader->noutput)
3668 emit_lds_vs_writes(&ctx);
3669 }
3670 } else if (ring_outputs) {
3671 if (shader->vs_as_es || shader->tes_as_es) {
3672 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3673 ctx.gs_export_gpr_tregs[1] = -1;
3674 ctx.gs_export_gpr_tregs[2] = -1;
3675 ctx.gs_export_gpr_tregs[3] = -1;
3676
3677 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3678 }
3679 } else {
3680 /* Export output */
3681 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3682
3683 for (i = 0, j = 0; i < noutput; i++, j++) {
3684 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3685 output[j].gpr = shader->output[i].gpr;
3686 output[j].elem_size = 3;
3687 output[j].swizzle_x = 0;
3688 output[j].swizzle_y = 1;
3689 output[j].swizzle_z = 2;
3690 output[j].swizzle_w = 3;
3691 output[j].burst_count = 1;
3692 output[j].type = 0xffffffff;
3693 output[j].op = CF_OP_EXPORT;
3694 switch (ctx.type) {
3695 case PIPE_SHADER_VERTEX:
3696 case PIPE_SHADER_TESS_EVAL:
3697 switch (shader->output[i].name) {
3698 case TGSI_SEMANTIC_POSITION:
3699 output[j].array_base = 60;
3700 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3701 pos_emitted = true;
3702 break;
3703
3704 case TGSI_SEMANTIC_PSIZE:
3705 output[j].array_base = 61;
3706 output[j].swizzle_y = 7;
3707 output[j].swizzle_z = 7;
3708 output[j].swizzle_w = 7;
3709 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3710 pos_emitted = true;
3711 break;
3712 case TGSI_SEMANTIC_EDGEFLAG:
3713 output[j].array_base = 61;
3714 output[j].swizzle_x = 7;
3715 output[j].swizzle_y = 0;
3716 output[j].swizzle_z = 7;
3717 output[j].swizzle_w = 7;
3718 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3719 pos_emitted = true;
3720 break;
3721 case TGSI_SEMANTIC_LAYER:
3722 /* spi_sid is 0 for outputs that are
3723 * not consumed by PS */
3724 if (shader->output[i].spi_sid) {
3725 output[j].array_base = next_param_base++;
3726 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3727 j++;
3728 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3729 }
3730 output[j].array_base = 61;
3731 output[j].swizzle_x = 7;
3732 output[j].swizzle_y = 7;
3733 output[j].swizzle_z = 0;
3734 output[j].swizzle_w = 7;
3735 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3736 pos_emitted = true;
3737 break;
3738 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3739 /* spi_sid is 0 for outputs that are
3740 * not consumed by PS */
3741 if (shader->output[i].spi_sid) {
3742 output[j].array_base = next_param_base++;
3743 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3744 j++;
3745 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3746 }
3747 output[j].array_base = 61;
3748 output[j].swizzle_x = 7;
3749 output[j].swizzle_y = 7;
3750 output[j].swizzle_z = 7;
3751 output[j].swizzle_w = 0;
3752 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3753 pos_emitted = true;
3754 break;
3755 case TGSI_SEMANTIC_CLIPVERTEX:
3756 j--;
3757 break;
3758 case TGSI_SEMANTIC_CLIPDIST:
3759 output[j].array_base = next_clip_base++;
3760 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3761 pos_emitted = true;
3762 /* spi_sid is 0 for clipdistance outputs that were generated
3763 * for clipvertex - we don't need to pass them to PS */
3764 if (shader->output[i].spi_sid) {
3765 j++;
3766 /* duplicate it as PARAM to pass to the pixel shader */
3767 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3768 output[j].array_base = next_param_base++;
3769 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3770 }
3771 break;
3772 case TGSI_SEMANTIC_FOG:
3773 output[j].swizzle_y = 4; /* 0 */
3774 output[j].swizzle_z = 4; /* 0 */
3775 output[j].swizzle_w = 5; /* 1 */
3776 break;
3777 case TGSI_SEMANTIC_PRIMID:
3778 output[j].swizzle_x = 2;
3779 output[j].swizzle_y = 4; /* 0 */
3780 output[j].swizzle_z = 4; /* 0 */
3781 output[j].swizzle_w = 4; /* 0 */
3782 break;
3783 }
3784
3785 break;
3786 case PIPE_SHADER_FRAGMENT:
3787 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3788 /* never export more colors than the number of CBs */
3789 if (shader->output[i].sid >= max_color_exports) {
3790 /* skip export */
3791 j--;
3792 continue;
3793 }
3794 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3795 output[j].array_base = shader->output[i].sid;
3796 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3797 shader->nr_ps_color_exports++;
3798 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3799 for (k = 1; k < max_color_exports; k++) {
3800 j++;
3801 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3802 output[j].gpr = shader->output[i].gpr;
3803 output[j].elem_size = 3;
3804 output[j].swizzle_x = 0;
3805 output[j].swizzle_y = 1;
3806 output[j].swizzle_z = 2;
3807 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3808 output[j].burst_count = 1;
3809 output[j].array_base = k;
3810 output[j].op = CF_OP_EXPORT;
3811 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3812 shader->nr_ps_color_exports++;
3813 }
3814 }
3815 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3816 output[j].array_base = 61;
3817 output[j].swizzle_x = 2;
3818 output[j].swizzle_y = 7;
3819 output[j].swizzle_z = output[j].swizzle_w = 7;
3820 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3821 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3822 output[j].array_base = 61;
3823 output[j].swizzle_x = 7;
3824 output[j].swizzle_y = 1;
3825 output[j].swizzle_z = output[j].swizzle_w = 7;
3826 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3827 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3828 output[j].array_base = 61;
3829 output[j].swizzle_x = 7;
3830 output[j].swizzle_y = 7;
3831 output[j].swizzle_z = 0;
3832 output[j].swizzle_w = 7;
3833 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3834 } else {
3835 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3836 r = -EINVAL;
3837 goto out_err;
3838 }
3839 break;
3840 case PIPE_SHADER_TESS_CTRL:
3841 break;
3842 default:
3843 R600_ERR("unsupported processor type %d\n", ctx.type);
3844 r = -EINVAL;
3845 goto out_err;
3846 }
3847
3848 if (output[j].type == 0xffffffff) {
3849 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3850 output[j].array_base = next_param_base++;
3851 }
3852 }
3853
3854 /* add fake position export */
3855 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3856 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3857 output[j].gpr = 0;
3858 output[j].elem_size = 3;
3859 output[j].swizzle_x = 7;
3860 output[j].swizzle_y = 7;
3861 output[j].swizzle_z = 7;
3862 output[j].swizzle_w = 7;
3863 output[j].burst_count = 1;
3864 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3865 output[j].array_base = 60;
3866 output[j].op = CF_OP_EXPORT;
3867 j++;
3868 }
3869
3870 /* add fake param output for vertex shader if no param is exported */
3871 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3872 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3873 output[j].gpr = 0;
3874 output[j].elem_size = 3;
3875 output[j].swizzle_x = 7;
3876 output[j].swizzle_y = 7;
3877 output[j].swizzle_z = 7;
3878 output[j].swizzle_w = 7;
3879 output[j].burst_count = 1;
3880 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3881 output[j].array_base = 0;
3882 output[j].op = CF_OP_EXPORT;
3883 j++;
3884 }
3885
3886 /* add fake pixel export */
3887 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3888 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3889 output[j].gpr = 0;
3890 output[j].elem_size = 3;
3891 output[j].swizzle_x = 7;
3892 output[j].swizzle_y = 7;
3893 output[j].swizzle_z = 7;
3894 output[j].swizzle_w = 7;
3895 output[j].burst_count = 1;
3896 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3897 output[j].array_base = 0;
3898 output[j].op = CF_OP_EXPORT;
3899 j++;
3900 shader->nr_ps_color_exports++;
3901 }
3902
3903 noutput = j;
3904
3905 /* set export done on last export of each type */
3906 for (k = noutput - 1, output_done = 0; k >= 0; k--) {
3907 if (!(output_done & (1 << output[k].type))) {
3908 output_done |= (1 << output[k].type);
3909 output[k].op = CF_OP_EXPORT_DONE;
3910 }
3911 }
3912 /* add output to bytecode */
3913 for (i = 0; i < noutput; i++) {
3914 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3915 if (r)
3916 goto out_err;
3917 }
3918 }
3919
3920 /* add program end */
3921 if (ctx.bc->chip_class == CAYMAN)
3922 cm_bytecode_add_cf_end(ctx.bc);
3923 else {
3924 const struct cf_op_info *last = NULL;
3925
3926 if (ctx.bc->cf_last)
3927 last = r600_isa_cf(ctx.bc->cf_last->op);
3928
3929 /* alu clause instructions don't have EOP bit, so add NOP */
3930 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_POP)
3931 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3932
3933 ctx.bc->cf_last->end_of_program = 1;
3934 }
3935
3936 /* check GPR limit - we have 124 = 128 - 4
3937 * (4 are reserved as alu clause temporary registers) */
3938 if (ctx.bc->ngpr > 124) {
3939 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3940 r = -ENOMEM;
3941 goto out_err;
3942 }
3943
3944 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3945 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3946 return r;
3947 }
3948
3949 free(ctx.literals);
3950 tgsi_parse_free(&ctx.parse);
3951 return 0;
3952 out_err:
3953 free(ctx.literals);
3954 tgsi_parse_free(&ctx.parse);
3955 return r;
3956 }
3957
3958 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3959 {
3960 const unsigned tgsi_opcode =
3961 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3962 R600_ERR("%s tgsi opcode unsupported\n",
3963 tgsi_get_opcode_name(tgsi_opcode));
3964 return -EINVAL;
3965 }
3966
3967 static int tgsi_end(struct r600_shader_ctx *ctx UNUSED)
3968 {
3969 return 0;
3970 }
3971
3972 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3973 const struct r600_shader_src *shader_src,
3974 unsigned chan)
3975 {
3976 bc_src->sel = shader_src->sel;
3977 bc_src->chan = shader_src->swizzle[chan];
3978 bc_src->neg = shader_src->neg;
3979 bc_src->abs = shader_src->abs;
3980 bc_src->rel = shader_src->rel;
3981 bc_src->value = shader_src->value[bc_src->chan];
3982 bc_src->kc_bank = shader_src->kc_bank;
3983 bc_src->kc_rel = shader_src->kc_rel;
3984 }
3985
3986 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3987 {
3988 bc_src->abs = 1;
3989 bc_src->neg = 0;
3990 }
3991
3992 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3993 {
3994 bc_src->neg = !bc_src->neg;
3995 }
3996
3997 static void tgsi_dst(struct r600_shader_ctx *ctx,
3998 const struct tgsi_full_dst_register *tgsi_dst,
3999 unsigned swizzle,
4000 struct r600_bytecode_alu_dst *r600_dst)
4001 {
4002 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4003
4004 r600_dst->sel = tgsi_dst->Register.Index;
4005 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
4006 r600_dst->chan = swizzle;
4007 r600_dst->write = 1;
4008 if (inst->Instruction.Saturate) {
4009 r600_dst->clamp = 1;
4010 }
4011 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
4012 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
4013 return;
4014 }
4015 }
4016 if (tgsi_dst->Register.Indirect)
4017 r600_dst->rel = V_SQ_REL_RELATIVE;
4018
4019 }
4020
4021 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap, int dest_temp, int op_override)
4022 {
4023 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4024 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4025 struct r600_bytecode_alu alu;
4026 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4027 int use_tmp = 0;
4028 int swizzle_x = inst->Src[0].Register.SwizzleX;
4029
4030 if (singledest) {
4031 switch (write_mask) {
4032 case 0x1:
4033 if (swizzle_x == 2) {
4034 write_mask = 0xc;
4035 use_tmp = 3;
4036 } else
4037 write_mask = 0x3;
4038 break;
4039 case 0x2:
4040 if (swizzle_x == 2) {
4041 write_mask = 0xc;
4042 use_tmp = 3;
4043 } else {
4044 write_mask = 0x3;
4045 use_tmp = 1;
4046 }
4047 break;
4048 case 0x4:
4049 if (swizzle_x == 0) {
4050 write_mask = 0x3;
4051 use_tmp = 1;
4052 } else
4053 write_mask = 0xc;
4054 break;
4055 case 0x8:
4056 if (swizzle_x == 0) {
4057 write_mask = 0x3;
4058 use_tmp = 1;
4059 } else {
4060 write_mask = 0xc;
4061 use_tmp = 3;
4062 }
4063 break;
4064 }
4065 }
4066
4067 lasti = tgsi_last_instruction(write_mask);
4068 for (i = 0; i <= lasti; i++) {
4069
4070 if (!(write_mask & (1 << i)))
4071 continue;
4072
4073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4074
4075 if (singledest) {
4076 if (use_tmp || dest_temp) {
4077 alu.dst.sel = use_tmp ? ctx->temp_reg : dest_temp;
4078 alu.dst.chan = i;
4079 alu.dst.write = 1;
4080 } else {
4081 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4082 }
4083 if (i == 1 || i == 3)
4084 alu.dst.write = 0;
4085 } else
4086 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4087
4088 alu.op = op_override ? op_override : ctx->inst_info->op;
4089 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
4090 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4091 } else if (!swap) {
4092 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4093 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4094 }
4095 } else {
4096 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
4097 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
4098 }
4099
4100 /* handle some special cases */
4101 if (i == 1 || i == 3) {
4102 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
4103 case TGSI_OPCODE_DABS:
4104 r600_bytecode_src_set_abs(&alu.src[0]);
4105 break;
4106 default:
4107 break;
4108 }
4109 }
4110 if (i == lasti) {
4111 alu.last = 1;
4112 }
4113 r = r600_bytecode_add_alu(ctx->bc, &alu);
4114 if (r)
4115 return r;
4116 }
4117
4118 if (use_tmp) {
4119 write_mask = inst->Dst[0].Register.WriteMask;
4120
4121 lasti = tgsi_last_instruction(write_mask);
4122 /* move result from temp to dst */
4123 for (i = 0; i <= lasti; i++) {
4124 if (!(write_mask & (1 << i)))
4125 continue;
4126
4127 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4128 alu.op = ALU_OP1_MOV;
4129
4130 if (dest_temp) {
4131 alu.dst.sel = dest_temp;
4132 alu.dst.chan = i;
4133 alu.dst.write = 1;
4134 } else
4135 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4136 alu.src[0].sel = ctx->temp_reg;
4137 alu.src[0].chan = use_tmp - 1;
4138 alu.last = (i == lasti);
4139
4140 r = r600_bytecode_add_alu(ctx->bc, &alu);
4141 if (r)
4142 return r;
4143 }
4144 }
4145 return 0;
4146 }
4147
4148 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
4149 {
4150 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4151 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4152 /* confirm writemasking */
4153 if ((write_mask & 0x3) != 0x3 &&
4154 (write_mask & 0xc) != 0xc) {
4155 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4156 return -1;
4157 }
4158 return tgsi_op2_64_params(ctx, false, false, 0, 0);
4159 }
4160
4161 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4162 {
4163 return tgsi_op2_64_params(ctx, true, false, 0, 0);
4164 }
4165
4166 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4167 {
4168 return tgsi_op2_64_params(ctx, true, true, 0, 0);
4169 }
4170
4171 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4172 {
4173 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4174 struct r600_bytecode_alu alu;
4175 int i, j, r;
4176 int lasti = 3;
4177 int tmp = r600_get_temp(ctx);
4178
4179 for (i = 0; i < lasti + 1; i++) {
4180
4181 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4182 alu.op = ctx->inst_info->op;
4183 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4184 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4185 }
4186
4187 if (inst->Dst[0].Register.WriteMask & (1 << i))
4188 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4189 else
4190 alu.dst.sel = tmp;
4191
4192 alu.dst.chan = i;
4193 alu.is_op3 = 1;
4194 if (i == lasti) {
4195 alu.last = 1;
4196 }
4197 r = r600_bytecode_add_alu(ctx->bc, &alu);
4198 if (r)
4199 return r;
4200 }
4201 return 0;
4202 }
4203
4204 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4205 {
4206 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4207 struct r600_bytecode_alu alu;
4208 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4209 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4210 /* use temp register if trans_only and more than one dst component */
4211 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4212 unsigned op = ctx->inst_info->op;
4213
4214 if (op == ALU_OP2_MUL_IEEE &&
4215 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4216 op = ALU_OP2_MUL;
4217
4218 for (i = 0; i <= lasti; i++) {
4219 if (!(write_mask & (1 << i)))
4220 continue;
4221
4222 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4223 if (use_tmp) {
4224 alu.dst.sel = ctx->temp_reg;
4225 alu.dst.chan = i;
4226 alu.dst.write = 1;
4227 } else
4228 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4229
4230 alu.op = op;
4231 if (!swap) {
4232 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4233 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4234 }
4235 } else {
4236 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4237 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4238 }
4239 if (i == lasti || trans_only) {
4240 alu.last = 1;
4241 }
4242 r = r600_bytecode_add_alu(ctx->bc, &alu);
4243 if (r)
4244 return r;
4245 }
4246
4247 if (use_tmp) {
4248 /* move result from temp to dst */
4249 for (i = 0; i <= lasti; i++) {
4250 if (!(write_mask & (1 << i)))
4251 continue;
4252
4253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4254 alu.op = ALU_OP1_MOV;
4255 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4256 alu.src[0].sel = ctx->temp_reg;
4257 alu.src[0].chan = i;
4258 alu.last = (i == lasti);
4259
4260 r = r600_bytecode_add_alu(ctx->bc, &alu);
4261 if (r)
4262 return r;
4263 }
4264 }
4265 return 0;
4266 }
4267
4268 static int tgsi_op2(struct r600_shader_ctx *ctx)
4269 {
4270 return tgsi_op2_s(ctx, 0, 0);
4271 }
4272
4273 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4274 {
4275 return tgsi_op2_s(ctx, 1, 0);
4276 }
4277
4278 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4279 {
4280 return tgsi_op2_s(ctx, 0, 1);
4281 }
4282
4283 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4284 {
4285 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4286 struct r600_bytecode_alu alu;
4287 int i, r;
4288 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4289
4290 for (i = 0; i < lasti + 1; i++) {
4291
4292 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4293 continue;
4294 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4295 alu.op = ctx->inst_info->op;
4296
4297 alu.src[0].sel = V_SQ_ALU_SRC_0;
4298
4299 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4300
4301 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4302
4303 if (i == lasti) {
4304 alu.last = 1;
4305 }
4306 r = r600_bytecode_add_alu(ctx->bc, &alu);
4307 if (r)
4308 return r;
4309 }
4310 return 0;
4311
4312 }
4313
4314 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4315 {
4316 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4317 struct r600_bytecode_alu alu;
4318 int i, r;
4319 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4320
4321 for (i = 0; i < lasti + 1; i++) {
4322
4323 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4324 continue;
4325 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4326 alu.op = ALU_OP1_MOV;
4327
4328 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4329
4330 if (i == 1 || i == 3)
4331 r600_bytecode_src_toggle_neg(&alu.src[0]);
4332 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4333
4334 if (i == lasti) {
4335 alu.last = 1;
4336 }
4337 r = r600_bytecode_add_alu(ctx->bc, &alu);
4338 if (r)
4339 return r;
4340 }
4341 return 0;
4342
4343 }
4344
4345 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4346 {
4347 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4348 struct r600_bytecode_alu alu;
4349 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4350 int i, j, r;
4351
4352 for (i = 0; i <= 3; i++) {
4353 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4354 alu.op = ctx->inst_info->op;
4355
4356 alu.dst.sel = ctx->temp_reg;
4357 alu.dst.chan = i;
4358 alu.dst.write = 1;
4359 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4360 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4361 }
4362
4363 if (i == 3)
4364 alu.last = 1;
4365
4366 r = r600_bytecode_add_alu(ctx->bc, &alu);
4367 if (r)
4368 return r;
4369 }
4370
4371 /* Replicate significand result across channels. */
4372 for (i = 0; i <= 3; i++) {
4373 if (!(write_mask & (1 << i)))
4374 continue;
4375
4376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4377 alu.op = ALU_OP1_MOV;
4378 alu.src[0].chan = (i & 1) + 2;
4379 alu.src[0].sel = ctx->temp_reg;
4380
4381 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4382 alu.dst.write = 1;
4383 alu.last = 1;
4384 r = r600_bytecode_add_alu(ctx->bc, &alu);
4385 if (r)
4386 return r;
4387 }
4388
4389 for (i = 0; i <= 3; i++) {
4390 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4391 /* MOV third channels to writemask dst1 */
4392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4393 alu.op = ALU_OP1_MOV;
4394 alu.src[0].chan = 1;
4395 alu.src[0].sel = ctx->temp_reg;
4396
4397 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4398 alu.last = 1;
4399 r = r600_bytecode_add_alu(ctx->bc, &alu);
4400 if (r)
4401 return r;
4402 break;
4403 }
4404 }
4405 return 0;
4406 }
4407
4408
4409 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4410 {
4411 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4412 struct r600_bytecode_alu alu;
4413 int i, r;
4414 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4415
4416 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4417 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4418
4419 for (i = 0; i <= (lasti+1)/2; i++) {
4420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4421 alu.op = ctx->inst_info->op;
4422
4423 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4424 alu.dst.sel = ctx->temp_reg;
4425 alu.dst.chan = i;
4426 alu.dst.write = 1;
4427 alu.last = 1;
4428
4429 r = r600_bytecode_add_alu(ctx->bc, &alu);
4430 if (r)
4431 return r;
4432 }
4433
4434 for (i = 0; i <= lasti; i++) {
4435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4436 alu.op = ALU_OP1_FLT32_TO_FLT64;
4437
4438 alu.src[0].chan = i/2;
4439 if (i%2 == 0)
4440 alu.src[0].sel = ctx->temp_reg;
4441 else {
4442 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4443 alu.src[0].value = 0x0;
4444 }
4445 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4446 alu.last = i == lasti;
4447
4448 r = r600_bytecode_add_alu(ctx->bc, &alu);
4449 if (r)
4450 return r;
4451 }
4452
4453 return 0;
4454 }
4455
4456 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4457 {
4458 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4459 struct r600_bytecode_alu alu;
4460 int i, r;
4461 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4462 int treg = r600_get_temp(ctx);
4463 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4464 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4465
4466 /* do a 64->32 into a temp register */
4467 r = tgsi_op2_64_params(ctx, true, false, treg, ALU_OP1_FLT64_TO_FLT32);
4468 if (r)
4469 return r;
4470
4471 for (i = 0; i <= lasti; i++) {
4472 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4473 continue;
4474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4475 alu.op = ctx->inst_info->op;
4476
4477 alu.src[0].chan = i;
4478 alu.src[0].sel = treg;
4479 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4480 alu.last = (i == lasti);
4481
4482 r = r600_bytecode_add_alu(ctx->bc, &alu);
4483 if (r)
4484 return r;
4485 }
4486
4487 return 0;
4488 }
4489
4490 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4491 unsigned op,
4492 int dst_reg,
4493 struct r600_shader_src *src,
4494 bool abs)
4495 {
4496 struct r600_bytecode_alu alu;
4497 const int last_slot = 3;
4498 int r;
4499
4500 /* these have to write the result to X/Y by the looks of it */
4501 for (int i = 0 ; i < last_slot; i++) {
4502 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4503 alu.op = op;
4504
4505 r600_bytecode_src(&alu.src[0], src, 1);
4506 r600_bytecode_src(&alu.src[1], src, 0);
4507
4508 if (abs)
4509 r600_bytecode_src_set_abs(&alu.src[1]);
4510
4511 alu.dst.sel = dst_reg;
4512 alu.dst.chan = i;
4513 alu.dst.write = (i == 0 || i == 1);
4514
4515 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4516 alu.last = 1;
4517 r = r600_bytecode_add_alu(bc, &alu);
4518 if (r)
4519 return r;
4520 }
4521
4522 return 0;
4523 }
4524
4525 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4526 {
4527 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4528 int i, r;
4529 struct r600_bytecode_alu alu;
4530 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4531 int t1 = ctx->temp_reg;
4532
4533 /* should only be one src regs */
4534 assert(inst->Instruction.NumSrcRegs == 1);
4535
4536 /* only support one double at a time */
4537 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4538 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4539
4540 r = cayman_emit_unary_double_raw(
4541 ctx->bc, ctx->inst_info->op, t1,
4542 &ctx->src[0],
4543 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4544 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4545 if (r)
4546 return r;
4547
4548 for (i = 0 ; i <= lasti; i++) {
4549 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4550 continue;
4551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4552 alu.op = ALU_OP1_MOV;
4553 alu.src[0].sel = t1;
4554 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4555 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4556 alu.dst.write = 1;
4557 if (i == lasti)
4558 alu.last = 1;
4559 r = r600_bytecode_add_alu(ctx->bc, &alu);
4560 if (r)
4561 return r;
4562 }
4563 return 0;
4564 }
4565
4566 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4567 {
4568 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4569 int i, j, r;
4570 struct r600_bytecode_alu alu;
4571 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4572
4573 for (i = 0 ; i < last_slot; i++) {
4574 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4575 alu.op = ctx->inst_info->op;
4576 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4577 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4578
4579 /* RSQ should take the absolute value of src */
4580 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4581 r600_bytecode_src_set_abs(&alu.src[j]);
4582 }
4583 }
4584 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4585 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4586
4587 if (i == last_slot - 1)
4588 alu.last = 1;
4589 r = r600_bytecode_add_alu(ctx->bc, &alu);
4590 if (r)
4591 return r;
4592 }
4593 return 0;
4594 }
4595
4596 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4597 {
4598 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4599 int i, j, k, r;
4600 struct r600_bytecode_alu alu;
4601 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4602 int t1 = ctx->temp_reg;
4603
4604 for (k = 0; k <= lasti; k++) {
4605 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4606 continue;
4607
4608 for (i = 0 ; i < 4; i++) {
4609 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4610 alu.op = ctx->inst_info->op;
4611 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4612 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4613 }
4614 alu.dst.sel = t1;
4615 alu.dst.chan = i;
4616 alu.dst.write = (i == k);
4617 if (i == 3)
4618 alu.last = 1;
4619 r = r600_bytecode_add_alu(ctx->bc, &alu);
4620 if (r)
4621 return r;
4622 }
4623 }
4624
4625 for (i = 0 ; i <= lasti; i++) {
4626 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4627 continue;
4628 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4629 alu.op = ALU_OP1_MOV;
4630 alu.src[0].sel = t1;
4631 alu.src[0].chan = i;
4632 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4633 alu.dst.write = 1;
4634 if (i == lasti)
4635 alu.last = 1;
4636 r = r600_bytecode_add_alu(ctx->bc, &alu);
4637 if (r)
4638 return r;
4639 }
4640
4641 return 0;
4642 }
4643
4644
4645 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4646 {
4647 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4648 int i, j, k, r;
4649 struct r600_bytecode_alu alu;
4650 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4651 int t1 = ctx->temp_reg;
4652
4653 /* t1 would get overwritten below if we actually tried to
4654 * multiply two pairs of doubles at a time. */
4655 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4656 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4657
4658 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4659
4660 for (i = 0; i < 4; i++) {
4661 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4662 alu.op = ctx->inst_info->op;
4663 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4664 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4665 }
4666 alu.dst.sel = t1;
4667 alu.dst.chan = i;
4668 alu.dst.write = 1;
4669 if (i == 3)
4670 alu.last = 1;
4671 r = r600_bytecode_add_alu(ctx->bc, &alu);
4672 if (r)
4673 return r;
4674 }
4675
4676 for (i = 0; i <= lasti; i++) {
4677 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4678 continue;
4679 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4680 alu.op = ALU_OP1_MOV;
4681 alu.src[0].sel = t1;
4682 alu.src[0].chan = i;
4683 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4684 alu.dst.write = 1;
4685 if (i == lasti)
4686 alu.last = 1;
4687 r = r600_bytecode_add_alu(ctx->bc, &alu);
4688 if (r)
4689 return r;
4690 }
4691
4692 return 0;
4693 }
4694
4695 /*
4696 * Emit RECIP_64 + MUL_64 to implement division.
4697 */
4698 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4699 {
4700 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4701 int r;
4702 struct r600_bytecode_alu alu;
4703 int t1 = ctx->temp_reg;
4704 int k;
4705
4706 /* Only support one double at a time. This is the same constraint as
4707 * in DMUL lowering. */
4708 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4709 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4710
4711 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4712
4713 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4714 if (r)
4715 return r;
4716
4717 for (int i = 0; i < 4; i++) {
4718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4719 alu.op = ALU_OP2_MUL_64;
4720
4721 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4722
4723 alu.src[1].sel = t1;
4724 alu.src[1].chan = (i == 3) ? 0 : 1;
4725
4726 alu.dst.sel = t1;
4727 alu.dst.chan = i;
4728 alu.dst.write = 1;
4729 if (i == 3)
4730 alu.last = 1;
4731 r = r600_bytecode_add_alu(ctx->bc, &alu);
4732 if (r)
4733 return r;
4734 }
4735
4736 for (int i = 0; i < 2; i++) {
4737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4738 alu.op = ALU_OP1_MOV;
4739 alu.src[0].sel = t1;
4740 alu.src[0].chan = i;
4741 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4742 alu.dst.write = 1;
4743 if (i == 1)
4744 alu.last = 1;
4745 r = r600_bytecode_add_alu(ctx->bc, &alu);
4746 if (r)
4747 return r;
4748 }
4749 return 0;
4750 }
4751
4752 /*
4753 * r600 - trunc to -PI..PI range
4754 * r700 - normalize by dividing by 2PI
4755 * see fdo bug 27901
4756 */
4757 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4758 {
4759 int r;
4760 struct r600_bytecode_alu alu;
4761
4762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4763 alu.op = ALU_OP3_MULADD;
4764 alu.is_op3 = 1;
4765
4766 alu.dst.chan = 0;
4767 alu.dst.sel = ctx->temp_reg;
4768 alu.dst.write = 1;
4769
4770 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4771
4772 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4773 alu.src[1].chan = 0;
4774 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4775 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4776 alu.src[2].chan = 0;
4777 alu.last = 1;
4778 r = r600_bytecode_add_alu(ctx->bc, &alu);
4779 if (r)
4780 return r;
4781
4782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4783 alu.op = ALU_OP1_FRACT;
4784
4785 alu.dst.chan = 0;
4786 alu.dst.sel = ctx->temp_reg;
4787 alu.dst.write = 1;
4788
4789 alu.src[0].sel = ctx->temp_reg;
4790 alu.src[0].chan = 0;
4791 alu.last = 1;
4792 r = r600_bytecode_add_alu(ctx->bc, &alu);
4793 if (r)
4794 return r;
4795
4796 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4797 alu.op = ALU_OP3_MULADD;
4798 alu.is_op3 = 1;
4799
4800 alu.dst.chan = 0;
4801 alu.dst.sel = ctx->temp_reg;
4802 alu.dst.write = 1;
4803
4804 alu.src[0].sel = ctx->temp_reg;
4805 alu.src[0].chan = 0;
4806
4807 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4808 alu.src[1].chan = 0;
4809 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4810 alu.src[2].chan = 0;
4811
4812 if (ctx->bc->chip_class == R600) {
4813 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4814 alu.src[2].value = u_bitcast_f2u(-M_PI);
4815 } else {
4816 alu.src[1].sel = V_SQ_ALU_SRC_1;
4817 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4818 alu.src[2].neg = 1;
4819 }
4820
4821 alu.last = 1;
4822 r = r600_bytecode_add_alu(ctx->bc, &alu);
4823 if (r)
4824 return r;
4825 return 0;
4826 }
4827
4828 static int cayman_trig(struct r600_shader_ctx *ctx)
4829 {
4830 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4831 struct r600_bytecode_alu alu;
4832 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4833 int i, r;
4834
4835 r = tgsi_setup_trig(ctx);
4836 if (r)
4837 return r;
4838
4839
4840 for (i = 0; i < last_slot; i++) {
4841 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4842 alu.op = ctx->inst_info->op;
4843 alu.dst.chan = i;
4844
4845 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4846 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4847
4848 alu.src[0].sel = ctx->temp_reg;
4849 alu.src[0].chan = 0;
4850 if (i == last_slot - 1)
4851 alu.last = 1;
4852 r = r600_bytecode_add_alu(ctx->bc, &alu);
4853 if (r)
4854 return r;
4855 }
4856 return 0;
4857 }
4858
4859 static int tgsi_trig(struct r600_shader_ctx *ctx)
4860 {
4861 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4862 struct r600_bytecode_alu alu;
4863 int i, r;
4864 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4865
4866 r = tgsi_setup_trig(ctx);
4867 if (r)
4868 return r;
4869
4870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4871 alu.op = ctx->inst_info->op;
4872 alu.dst.chan = 0;
4873 alu.dst.sel = ctx->temp_reg;
4874 alu.dst.write = 1;
4875
4876 alu.src[0].sel = ctx->temp_reg;
4877 alu.src[0].chan = 0;
4878 alu.last = 1;
4879 r = r600_bytecode_add_alu(ctx->bc, &alu);
4880 if (r)
4881 return r;
4882
4883 /* replicate result */
4884 for (i = 0; i < lasti + 1; i++) {
4885 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4886 continue;
4887
4888 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4889 alu.op = ALU_OP1_MOV;
4890
4891 alu.src[0].sel = ctx->temp_reg;
4892 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4893 if (i == lasti)
4894 alu.last = 1;
4895 r = r600_bytecode_add_alu(ctx->bc, &alu);
4896 if (r)
4897 return r;
4898 }
4899 return 0;
4900 }
4901
4902 static int tgsi_kill(struct r600_shader_ctx *ctx)
4903 {
4904 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4905 struct r600_bytecode_alu alu;
4906 int i, r;
4907
4908 for (i = 0; i < 4; i++) {
4909 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4910 alu.op = ctx->inst_info->op;
4911
4912 alu.dst.chan = i;
4913
4914 alu.src[0].sel = V_SQ_ALU_SRC_0;
4915
4916 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4917 alu.src[1].sel = V_SQ_ALU_SRC_1;
4918 alu.src[1].neg = 1;
4919 } else {
4920 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4921 }
4922 if (i == 3) {
4923 alu.last = 1;
4924 }
4925 r = r600_bytecode_add_alu(ctx->bc, &alu);
4926 if (r)
4927 return r;
4928 }
4929
4930 /* kill must be last in ALU */
4931 ctx->bc->force_add_cf = 1;
4932 ctx->shader->uses_kill = TRUE;
4933 return 0;
4934 }
4935
4936 static int tgsi_lit(struct r600_shader_ctx *ctx)
4937 {
4938 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4939 struct r600_bytecode_alu alu;
4940 int r;
4941
4942 /* tmp.x = max(src.y, 0.0) */
4943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4944 alu.op = ALU_OP2_MAX;
4945 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4946 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4947 alu.src[1].chan = 1;
4948
4949 alu.dst.sel = ctx->temp_reg;
4950 alu.dst.chan = 0;
4951 alu.dst.write = 1;
4952
4953 alu.last = 1;
4954 r = r600_bytecode_add_alu(ctx->bc, &alu);
4955 if (r)
4956 return r;
4957
4958 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4959 {
4960 int chan;
4961 int sel;
4962 unsigned i;
4963
4964 if (ctx->bc->chip_class == CAYMAN) {
4965 for (i = 0; i < 3; i++) {
4966 /* tmp.z = log(tmp.x) */
4967 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4968 alu.op = ALU_OP1_LOG_CLAMPED;
4969 alu.src[0].sel = ctx->temp_reg;
4970 alu.src[0].chan = 0;
4971 alu.dst.sel = ctx->temp_reg;
4972 alu.dst.chan = i;
4973 if (i == 2) {
4974 alu.dst.write = 1;
4975 alu.last = 1;
4976 } else
4977 alu.dst.write = 0;
4978
4979 r = r600_bytecode_add_alu(ctx->bc, &alu);
4980 if (r)
4981 return r;
4982 }
4983 } else {
4984 /* tmp.z = log(tmp.x) */
4985 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4986 alu.op = ALU_OP1_LOG_CLAMPED;
4987 alu.src[0].sel = ctx->temp_reg;
4988 alu.src[0].chan = 0;
4989 alu.dst.sel = ctx->temp_reg;
4990 alu.dst.chan = 2;
4991 alu.dst.write = 1;
4992 alu.last = 1;
4993 r = r600_bytecode_add_alu(ctx->bc, &alu);
4994 if (r)
4995 return r;
4996 }
4997
4998 chan = alu.dst.chan;
4999 sel = alu.dst.sel;
5000
5001 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
5002 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5003 alu.op = ALU_OP3_MUL_LIT;
5004 alu.src[0].sel = sel;
5005 alu.src[0].chan = chan;
5006 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
5007 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
5008 alu.dst.sel = ctx->temp_reg;
5009 alu.dst.chan = 0;
5010 alu.dst.write = 1;
5011 alu.is_op3 = 1;
5012 alu.last = 1;
5013 r = r600_bytecode_add_alu(ctx->bc, &alu);
5014 if (r)
5015 return r;
5016
5017 if (ctx->bc->chip_class == CAYMAN) {
5018 for (i = 0; i < 3; i++) {
5019 /* dst.z = exp(tmp.x) */
5020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5021 alu.op = ALU_OP1_EXP_IEEE;
5022 alu.src[0].sel = ctx->temp_reg;
5023 alu.src[0].chan = 0;
5024 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5025 if (i == 2) {
5026 alu.dst.write = 1;
5027 alu.last = 1;
5028 } else
5029 alu.dst.write = 0;
5030 r = r600_bytecode_add_alu(ctx->bc, &alu);
5031 if (r)
5032 return r;
5033 }
5034 } else {
5035 /* dst.z = exp(tmp.x) */
5036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5037 alu.op = ALU_OP1_EXP_IEEE;
5038 alu.src[0].sel = ctx->temp_reg;
5039 alu.src[0].chan = 0;
5040 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5041 alu.last = 1;
5042 r = r600_bytecode_add_alu(ctx->bc, &alu);
5043 if (r)
5044 return r;
5045 }
5046 }
5047
5048 /* dst.x, <- 1.0 */
5049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5050 alu.op = ALU_OP1_MOV;
5051 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
5052 alu.src[0].chan = 0;
5053 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5054 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
5055 r = r600_bytecode_add_alu(ctx->bc, &alu);
5056 if (r)
5057 return r;
5058
5059 /* dst.y = max(src.x, 0.0) */
5060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5061 alu.op = ALU_OP2_MAX;
5062 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5063 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5064 alu.src[1].chan = 0;
5065 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
5066 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
5067 r = r600_bytecode_add_alu(ctx->bc, &alu);
5068 if (r)
5069 return r;
5070
5071 /* dst.w, <- 1.0 */
5072 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5073 alu.op = ALU_OP1_MOV;
5074 alu.src[0].sel = V_SQ_ALU_SRC_1;
5075 alu.src[0].chan = 0;
5076 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
5077 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
5078 alu.last = 1;
5079 r = r600_bytecode_add_alu(ctx->bc, &alu);
5080 if (r)
5081 return r;
5082
5083 return 0;
5084 }
5085
5086 static int tgsi_rsq(struct r600_shader_ctx *ctx)
5087 {
5088 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5089 struct r600_bytecode_alu alu;
5090 int i, r;
5091
5092 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5093
5094 alu.op = ALU_OP1_RECIPSQRT_IEEE;
5095
5096 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5097 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5098 r600_bytecode_src_set_abs(&alu.src[i]);
5099 }
5100 alu.dst.sel = ctx->temp_reg;
5101 alu.dst.write = 1;
5102 alu.last = 1;
5103 r = r600_bytecode_add_alu(ctx->bc, &alu);
5104 if (r)
5105 return r;
5106 /* replicate result */
5107 return tgsi_helper_tempx_replicate(ctx);
5108 }
5109
5110 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
5111 {
5112 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5113 struct r600_bytecode_alu alu;
5114 int i, r;
5115
5116 for (i = 0; i < 4; i++) {
5117 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5118 alu.src[0].sel = ctx->temp_reg;
5119 alu.op = ALU_OP1_MOV;
5120 alu.dst.chan = i;
5121 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5122 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5123 if (i == 3)
5124 alu.last = 1;
5125 r = r600_bytecode_add_alu(ctx->bc, &alu);
5126 if (r)
5127 return r;
5128 }
5129 return 0;
5130 }
5131
5132 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
5133 {
5134 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5135 struct r600_bytecode_alu alu;
5136 int i, r;
5137
5138 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5139 alu.op = ctx->inst_info->op;
5140 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5141 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5142 }
5143 alu.dst.sel = ctx->temp_reg;
5144 alu.dst.write = 1;
5145 alu.last = 1;
5146 r = r600_bytecode_add_alu(ctx->bc, &alu);
5147 if (r)
5148 return r;
5149 /* replicate result */
5150 return tgsi_helper_tempx_replicate(ctx);
5151 }
5152
5153 static int cayman_pow(struct r600_shader_ctx *ctx)
5154 {
5155 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5156 int i, r;
5157 struct r600_bytecode_alu alu;
5158 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5159
5160 for (i = 0; i < 3; i++) {
5161 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5162 alu.op = ALU_OP1_LOG_IEEE;
5163 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5164 alu.dst.sel = ctx->temp_reg;
5165 alu.dst.chan = i;
5166 alu.dst.write = 1;
5167 if (i == 2)
5168 alu.last = 1;
5169 r = r600_bytecode_add_alu(ctx->bc, &alu);
5170 if (r)
5171 return r;
5172 }
5173
5174 /* b * LOG2(a) */
5175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5176 alu.op = ALU_OP2_MUL;
5177 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5178 alu.src[1].sel = ctx->temp_reg;
5179 alu.dst.sel = ctx->temp_reg;
5180 alu.dst.write = 1;
5181 alu.last = 1;
5182 r = r600_bytecode_add_alu(ctx->bc, &alu);
5183 if (r)
5184 return r;
5185
5186 for (i = 0; i < last_slot; i++) {
5187 /* POW(a,b) = EXP2(b * LOG2(a))*/
5188 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5189 alu.op = ALU_OP1_EXP_IEEE;
5190 alu.src[0].sel = ctx->temp_reg;
5191
5192 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5193 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5194 if (i == last_slot - 1)
5195 alu.last = 1;
5196 r = r600_bytecode_add_alu(ctx->bc, &alu);
5197 if (r)
5198 return r;
5199 }
5200 return 0;
5201 }
5202
5203 static int tgsi_pow(struct r600_shader_ctx *ctx)
5204 {
5205 struct r600_bytecode_alu alu;
5206 int r;
5207
5208 /* LOG2(a) */
5209 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5210 alu.op = ALU_OP1_LOG_IEEE;
5211 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5212 alu.dst.sel = ctx->temp_reg;
5213 alu.dst.write = 1;
5214 alu.last = 1;
5215 r = r600_bytecode_add_alu(ctx->bc, &alu);
5216 if (r)
5217 return r;
5218 /* b * LOG2(a) */
5219 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5220 alu.op = ALU_OP2_MUL;
5221 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5222 alu.src[1].sel = ctx->temp_reg;
5223 alu.dst.sel = ctx->temp_reg;
5224 alu.dst.write = 1;
5225 alu.last = 1;
5226 r = r600_bytecode_add_alu(ctx->bc, &alu);
5227 if (r)
5228 return r;
5229 /* POW(a,b) = EXP2(b * LOG2(a))*/
5230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5231 alu.op = ALU_OP1_EXP_IEEE;
5232 alu.src[0].sel = ctx->temp_reg;
5233 alu.dst.sel = ctx->temp_reg;
5234 alu.dst.write = 1;
5235 alu.last = 1;
5236 r = r600_bytecode_add_alu(ctx->bc, &alu);
5237 if (r)
5238 return r;
5239 return tgsi_helper_tempx_replicate(ctx);
5240 }
5241
5242 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5243 {
5244 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5245 struct r600_bytecode_alu alu;
5246 int i, r, j;
5247 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5248 int tmp0 = ctx->temp_reg;
5249 int tmp1 = r600_get_temp(ctx);
5250 int tmp2 = r600_get_temp(ctx);
5251 int tmp3 = r600_get_temp(ctx);
5252 /* Unsigned path:
5253 *
5254 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5255 *
5256 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5257 * 2. tmp0.z = lo (tmp0.x * src2)
5258 * 3. tmp0.w = -tmp0.z
5259 * 4. tmp0.y = hi (tmp0.x * src2)
5260 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5261 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5262 * 7. tmp1.x = tmp0.x - tmp0.w
5263 * 8. tmp1.y = tmp0.x + tmp0.w
5264 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5265 * 10. tmp0.z = hi(tmp0.x * src1) = q
5266 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5267 *
5268 * 12. tmp0.w = src1 - tmp0.y = r
5269 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5270 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5271 *
5272 * if DIV
5273 *
5274 * 15. tmp1.z = tmp0.z + 1 = q + 1
5275 * 16. tmp1.w = tmp0.z - 1 = q - 1
5276 *
5277 * else MOD
5278 *
5279 * 15. tmp1.z = tmp0.w - src2 = r - src2
5280 * 16. tmp1.w = tmp0.w + src2 = r + src2
5281 *
5282 * endif
5283 *
5284 * 17. tmp1.x = tmp1.x & tmp1.y
5285 *
5286 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5287 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5288 *
5289 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5290 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5291 *
5292 * Signed path:
5293 *
5294 * Same as unsigned, using abs values of the operands,
5295 * and fixing the sign of the result in the end.
5296 */
5297
5298 for (i = 0; i < 4; i++) {
5299 if (!(write_mask & (1<<i)))
5300 continue;
5301
5302 if (signed_op) {
5303
5304 /* tmp2.x = -src0 */
5305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5306 alu.op = ALU_OP2_SUB_INT;
5307
5308 alu.dst.sel = tmp2;
5309 alu.dst.chan = 0;
5310 alu.dst.write = 1;
5311
5312 alu.src[0].sel = V_SQ_ALU_SRC_0;
5313
5314 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5315
5316 alu.last = 1;
5317 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5318 return r;
5319
5320 /* tmp2.y = -src1 */
5321 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5322 alu.op = ALU_OP2_SUB_INT;
5323
5324 alu.dst.sel = tmp2;
5325 alu.dst.chan = 1;
5326 alu.dst.write = 1;
5327
5328 alu.src[0].sel = V_SQ_ALU_SRC_0;
5329
5330 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5331
5332 alu.last = 1;
5333 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5334 return r;
5335
5336 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5337 /* it will be a sign of the quotient */
5338 if (!mod) {
5339
5340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5341 alu.op = ALU_OP2_XOR_INT;
5342
5343 alu.dst.sel = tmp2;
5344 alu.dst.chan = 2;
5345 alu.dst.write = 1;
5346
5347 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5348 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5349
5350 alu.last = 1;
5351 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5352 return r;
5353 }
5354
5355 /* tmp2.x = |src0| */
5356 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5357 alu.op = ALU_OP3_CNDGE_INT;
5358 alu.is_op3 = 1;
5359
5360 alu.dst.sel = tmp2;
5361 alu.dst.chan = 0;
5362 alu.dst.write = 1;
5363
5364 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5365 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5366 alu.src[2].sel = tmp2;
5367 alu.src[2].chan = 0;
5368
5369 alu.last = 1;
5370 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5371 return r;
5372
5373 /* tmp2.y = |src1| */
5374 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5375 alu.op = ALU_OP3_CNDGE_INT;
5376 alu.is_op3 = 1;
5377
5378 alu.dst.sel = tmp2;
5379 alu.dst.chan = 1;
5380 alu.dst.write = 1;
5381
5382 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5383 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5384 alu.src[2].sel = tmp2;
5385 alu.src[2].chan = 1;
5386
5387 alu.last = 1;
5388 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5389 return r;
5390
5391 }
5392
5393 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5394 if (ctx->bc->chip_class == CAYMAN) {
5395 /* tmp3.x = u2f(src2) */
5396 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5397 alu.op = ALU_OP1_UINT_TO_FLT;
5398
5399 alu.dst.sel = tmp3;
5400 alu.dst.chan = 0;
5401 alu.dst.write = 1;
5402
5403 if (signed_op) {
5404 alu.src[0].sel = tmp2;
5405 alu.src[0].chan = 1;
5406 } else {
5407 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5408 }
5409
5410 alu.last = 1;
5411 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5412 return r;
5413
5414 /* tmp0.x = recip(tmp3.x) */
5415 for (j = 0 ; j < 3; j++) {
5416 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5417 alu.op = ALU_OP1_RECIP_IEEE;
5418
5419 alu.dst.sel = tmp0;
5420 alu.dst.chan = j;
5421 alu.dst.write = (j == 0);
5422
5423 alu.src[0].sel = tmp3;
5424 alu.src[0].chan = 0;
5425
5426 if (j == 2)
5427 alu.last = 1;
5428 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5429 return r;
5430 }
5431
5432 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5433 alu.op = ALU_OP2_MUL;
5434
5435 alu.src[0].sel = tmp0;
5436 alu.src[0].chan = 0;
5437
5438 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5439 alu.src[1].value = 0x4f800000;
5440
5441 alu.dst.sel = tmp3;
5442 alu.dst.write = 1;
5443 alu.last = 1;
5444 r = r600_bytecode_add_alu(ctx->bc, &alu);
5445 if (r)
5446 return r;
5447
5448 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5449 alu.op = ALU_OP1_FLT_TO_UINT;
5450
5451 alu.dst.sel = tmp0;
5452 alu.dst.chan = 0;
5453 alu.dst.write = 1;
5454
5455 alu.src[0].sel = tmp3;
5456 alu.src[0].chan = 0;
5457
5458 alu.last = 1;
5459 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5460 return r;
5461
5462 } else {
5463 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5464 alu.op = ALU_OP1_RECIP_UINT;
5465
5466 alu.dst.sel = tmp0;
5467 alu.dst.chan = 0;
5468 alu.dst.write = 1;
5469
5470 if (signed_op) {
5471 alu.src[0].sel = tmp2;
5472 alu.src[0].chan = 1;
5473 } else {
5474 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5475 }
5476
5477 alu.last = 1;
5478 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5479 return r;
5480 }
5481
5482 /* 2. tmp0.z = lo (tmp0.x * src2) */
5483 if (ctx->bc->chip_class == CAYMAN) {
5484 for (j = 0 ; j < 4; j++) {
5485 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5486 alu.op = ALU_OP2_MULLO_UINT;
5487
5488 alu.dst.sel = tmp0;
5489 alu.dst.chan = j;
5490 alu.dst.write = (j == 2);
5491
5492 alu.src[0].sel = tmp0;
5493 alu.src[0].chan = 0;
5494 if (signed_op) {
5495 alu.src[1].sel = tmp2;
5496 alu.src[1].chan = 1;
5497 } else {
5498 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5499 }
5500
5501 alu.last = (j == 3);
5502 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5503 return r;
5504 }
5505 } else {
5506 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5507 alu.op = ALU_OP2_MULLO_UINT;
5508
5509 alu.dst.sel = tmp0;
5510 alu.dst.chan = 2;
5511 alu.dst.write = 1;
5512
5513 alu.src[0].sel = tmp0;
5514 alu.src[0].chan = 0;
5515 if (signed_op) {
5516 alu.src[1].sel = tmp2;
5517 alu.src[1].chan = 1;
5518 } else {
5519 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5520 }
5521
5522 alu.last = 1;
5523 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5524 return r;
5525 }
5526
5527 /* 3. tmp0.w = -tmp0.z */
5528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5529 alu.op = ALU_OP2_SUB_INT;
5530
5531 alu.dst.sel = tmp0;
5532 alu.dst.chan = 3;
5533 alu.dst.write = 1;
5534
5535 alu.src[0].sel = V_SQ_ALU_SRC_0;
5536 alu.src[1].sel = tmp0;
5537 alu.src[1].chan = 2;
5538
5539 alu.last = 1;
5540 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5541 return r;
5542
5543 /* 4. tmp0.y = hi (tmp0.x * src2) */
5544 if (ctx->bc->chip_class == CAYMAN) {
5545 for (j = 0 ; j < 4; j++) {
5546 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5547 alu.op = ALU_OP2_MULHI_UINT;
5548
5549 alu.dst.sel = tmp0;
5550 alu.dst.chan = j;
5551 alu.dst.write = (j == 1);
5552
5553 alu.src[0].sel = tmp0;
5554 alu.src[0].chan = 0;
5555
5556 if (signed_op) {
5557 alu.src[1].sel = tmp2;
5558 alu.src[1].chan = 1;
5559 } else {
5560 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5561 }
5562 alu.last = (j == 3);
5563 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5564 return r;
5565 }
5566 } else {
5567 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5568 alu.op = ALU_OP2_MULHI_UINT;
5569
5570 alu.dst.sel = tmp0;
5571 alu.dst.chan = 1;
5572 alu.dst.write = 1;
5573
5574 alu.src[0].sel = tmp0;
5575 alu.src[0].chan = 0;
5576
5577 if (signed_op) {
5578 alu.src[1].sel = tmp2;
5579 alu.src[1].chan = 1;
5580 } else {
5581 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5582 }
5583
5584 alu.last = 1;
5585 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5586 return r;
5587 }
5588
5589 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5590 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5591 alu.op = ALU_OP3_CNDE_INT;
5592 alu.is_op3 = 1;
5593
5594 alu.dst.sel = tmp0;
5595 alu.dst.chan = 2;
5596 alu.dst.write = 1;
5597
5598 alu.src[0].sel = tmp0;
5599 alu.src[0].chan = 1;
5600 alu.src[1].sel = tmp0;
5601 alu.src[1].chan = 3;
5602 alu.src[2].sel = tmp0;
5603 alu.src[2].chan = 2;
5604
5605 alu.last = 1;
5606 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5607 return r;
5608
5609 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5610 if (ctx->bc->chip_class == CAYMAN) {
5611 for (j = 0 ; j < 4; j++) {
5612 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5613 alu.op = ALU_OP2_MULHI_UINT;
5614
5615 alu.dst.sel = tmp0;
5616 alu.dst.chan = j;
5617 alu.dst.write = (j == 3);
5618
5619 alu.src[0].sel = tmp0;
5620 alu.src[0].chan = 2;
5621
5622 alu.src[1].sel = tmp0;
5623 alu.src[1].chan = 0;
5624
5625 alu.last = (j == 3);
5626 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5627 return r;
5628 }
5629 } else {
5630 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5631 alu.op = ALU_OP2_MULHI_UINT;
5632
5633 alu.dst.sel = tmp0;
5634 alu.dst.chan = 3;
5635 alu.dst.write = 1;
5636
5637 alu.src[0].sel = tmp0;
5638 alu.src[0].chan = 2;
5639
5640 alu.src[1].sel = tmp0;
5641 alu.src[1].chan = 0;
5642
5643 alu.last = 1;
5644 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5645 return r;
5646 }
5647
5648 /* 7. tmp1.x = tmp0.x - tmp0.w */
5649 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5650 alu.op = ALU_OP2_SUB_INT;
5651
5652 alu.dst.sel = tmp1;
5653 alu.dst.chan = 0;
5654 alu.dst.write = 1;
5655
5656 alu.src[0].sel = tmp0;
5657 alu.src[0].chan = 0;
5658 alu.src[1].sel = tmp0;
5659 alu.src[1].chan = 3;
5660
5661 alu.last = 1;
5662 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5663 return r;
5664
5665 /* 8. tmp1.y = tmp0.x + tmp0.w */
5666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5667 alu.op = ALU_OP2_ADD_INT;
5668
5669 alu.dst.sel = tmp1;
5670 alu.dst.chan = 1;
5671 alu.dst.write = 1;
5672
5673 alu.src[0].sel = tmp0;
5674 alu.src[0].chan = 0;
5675 alu.src[1].sel = tmp0;
5676 alu.src[1].chan = 3;
5677
5678 alu.last = 1;
5679 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5680 return r;
5681
5682 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5683 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5684 alu.op = ALU_OP3_CNDE_INT;
5685 alu.is_op3 = 1;
5686
5687 alu.dst.sel = tmp0;
5688 alu.dst.chan = 0;
5689 alu.dst.write = 1;
5690
5691 alu.src[0].sel = tmp0;
5692 alu.src[0].chan = 1;
5693 alu.src[1].sel = tmp1;
5694 alu.src[1].chan = 1;
5695 alu.src[2].sel = tmp1;
5696 alu.src[2].chan = 0;
5697
5698 alu.last = 1;
5699 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5700 return r;
5701
5702 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5703 if (ctx->bc->chip_class == CAYMAN) {
5704 for (j = 0 ; j < 4; j++) {
5705 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5706 alu.op = ALU_OP2_MULHI_UINT;
5707
5708 alu.dst.sel = tmp0;
5709 alu.dst.chan = j;
5710 alu.dst.write = (j == 2);
5711
5712 alu.src[0].sel = tmp0;
5713 alu.src[0].chan = 0;
5714
5715 if (signed_op) {
5716 alu.src[1].sel = tmp2;
5717 alu.src[1].chan = 0;
5718 } else {
5719 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5720 }
5721
5722 alu.last = (j == 3);
5723 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5724 return r;
5725 }
5726 } else {
5727 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5728 alu.op = ALU_OP2_MULHI_UINT;
5729
5730 alu.dst.sel = tmp0;
5731 alu.dst.chan = 2;
5732 alu.dst.write = 1;
5733
5734 alu.src[0].sel = tmp0;
5735 alu.src[0].chan = 0;
5736
5737 if (signed_op) {
5738 alu.src[1].sel = tmp2;
5739 alu.src[1].chan = 0;
5740 } else {
5741 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5742 }
5743
5744 alu.last = 1;
5745 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5746 return r;
5747 }
5748
5749 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5750 if (ctx->bc->chip_class == CAYMAN) {
5751 for (j = 0 ; j < 4; j++) {
5752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5753 alu.op = ALU_OP2_MULLO_UINT;
5754
5755 alu.dst.sel = tmp0;
5756 alu.dst.chan = j;
5757 alu.dst.write = (j == 1);
5758
5759 if (signed_op) {
5760 alu.src[0].sel = tmp2;
5761 alu.src[0].chan = 1;
5762 } else {
5763 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5764 }
5765
5766 alu.src[1].sel = tmp0;
5767 alu.src[1].chan = 2;
5768
5769 alu.last = (j == 3);
5770 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5771 return r;
5772 }
5773 } else {
5774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5775 alu.op = ALU_OP2_MULLO_UINT;
5776
5777 alu.dst.sel = tmp0;
5778 alu.dst.chan = 1;
5779 alu.dst.write = 1;
5780
5781 if (signed_op) {
5782 alu.src[0].sel = tmp2;
5783 alu.src[0].chan = 1;
5784 } else {
5785 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5786 }
5787
5788 alu.src[1].sel = tmp0;
5789 alu.src[1].chan = 2;
5790
5791 alu.last = 1;
5792 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5793 return r;
5794 }
5795
5796 /* 12. tmp0.w = src1 - tmp0.y = r */
5797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5798 alu.op = ALU_OP2_SUB_INT;
5799
5800 alu.dst.sel = tmp0;
5801 alu.dst.chan = 3;
5802 alu.dst.write = 1;
5803
5804 if (signed_op) {
5805 alu.src[0].sel = tmp2;
5806 alu.src[0].chan = 0;
5807 } else {
5808 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5809 }
5810
5811 alu.src[1].sel = tmp0;
5812 alu.src[1].chan = 1;
5813
5814 alu.last = 1;
5815 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5816 return r;
5817
5818 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5819 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5820 alu.op = ALU_OP2_SETGE_UINT;
5821
5822 alu.dst.sel = tmp1;
5823 alu.dst.chan = 0;
5824 alu.dst.write = 1;
5825
5826 alu.src[0].sel = tmp0;
5827 alu.src[0].chan = 3;
5828 if (signed_op) {
5829 alu.src[1].sel = tmp2;
5830 alu.src[1].chan = 1;
5831 } else {
5832 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5833 }
5834
5835 alu.last = 1;
5836 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5837 return r;
5838
5839 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5840 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5841 alu.op = ALU_OP2_SETGE_UINT;
5842
5843 alu.dst.sel = tmp1;
5844 alu.dst.chan = 1;
5845 alu.dst.write = 1;
5846
5847 if (signed_op) {
5848 alu.src[0].sel = tmp2;
5849 alu.src[0].chan = 0;
5850 } else {
5851 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5852 }
5853
5854 alu.src[1].sel = tmp0;
5855 alu.src[1].chan = 1;
5856
5857 alu.last = 1;
5858 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5859 return r;
5860
5861 if (mod) { /* UMOD */
5862
5863 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5865 alu.op = ALU_OP2_SUB_INT;
5866
5867 alu.dst.sel = tmp1;
5868 alu.dst.chan = 2;
5869 alu.dst.write = 1;
5870
5871 alu.src[0].sel = tmp0;
5872 alu.src[0].chan = 3;
5873
5874 if (signed_op) {
5875 alu.src[1].sel = tmp2;
5876 alu.src[1].chan = 1;
5877 } else {
5878 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5879 }
5880
5881 alu.last = 1;
5882 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5883 return r;
5884
5885 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5886 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5887 alu.op = ALU_OP2_ADD_INT;
5888
5889 alu.dst.sel = tmp1;
5890 alu.dst.chan = 3;
5891 alu.dst.write = 1;
5892
5893 alu.src[0].sel = tmp0;
5894 alu.src[0].chan = 3;
5895 if (signed_op) {
5896 alu.src[1].sel = tmp2;
5897 alu.src[1].chan = 1;
5898 } else {
5899 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5900 }
5901
5902 alu.last = 1;
5903 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5904 return r;
5905
5906 } else { /* UDIV */
5907
5908 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5909 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5910 alu.op = ALU_OP2_ADD_INT;
5911
5912 alu.dst.sel = tmp1;
5913 alu.dst.chan = 2;
5914 alu.dst.write = 1;
5915
5916 alu.src[0].sel = tmp0;
5917 alu.src[0].chan = 2;
5918 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5919
5920 alu.last = 1;
5921 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5922 return r;
5923
5924 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5926 alu.op = ALU_OP2_ADD_INT;
5927
5928 alu.dst.sel = tmp1;
5929 alu.dst.chan = 3;
5930 alu.dst.write = 1;
5931
5932 alu.src[0].sel = tmp0;
5933 alu.src[0].chan = 2;
5934 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5935
5936 alu.last = 1;
5937 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5938 return r;
5939
5940 }
5941
5942 /* 17. tmp1.x = tmp1.x & tmp1.y */
5943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5944 alu.op = ALU_OP2_AND_INT;
5945
5946 alu.dst.sel = tmp1;
5947 alu.dst.chan = 0;
5948 alu.dst.write = 1;
5949
5950 alu.src[0].sel = tmp1;
5951 alu.src[0].chan = 0;
5952 alu.src[1].sel = tmp1;
5953 alu.src[1].chan = 1;
5954
5955 alu.last = 1;
5956 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5957 return r;
5958
5959 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5960 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5961 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5962 alu.op = ALU_OP3_CNDE_INT;
5963 alu.is_op3 = 1;
5964
5965 alu.dst.sel = tmp0;
5966 alu.dst.chan = 2;
5967 alu.dst.write = 1;
5968
5969 alu.src[0].sel = tmp1;
5970 alu.src[0].chan = 0;
5971 alu.src[1].sel = tmp0;
5972 alu.src[1].chan = mod ? 3 : 2;
5973 alu.src[2].sel = tmp1;
5974 alu.src[2].chan = 2;
5975
5976 alu.last = 1;
5977 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5978 return r;
5979
5980 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5981 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5982 alu.op = ALU_OP3_CNDE_INT;
5983 alu.is_op3 = 1;
5984
5985 if (signed_op) {
5986 alu.dst.sel = tmp0;
5987 alu.dst.chan = 2;
5988 alu.dst.write = 1;
5989 } else {
5990 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5991 }
5992
5993 alu.src[0].sel = tmp1;
5994 alu.src[0].chan = 1;
5995 alu.src[1].sel = tmp1;
5996 alu.src[1].chan = 3;
5997 alu.src[2].sel = tmp0;
5998 alu.src[2].chan = 2;
5999
6000 alu.last = 1;
6001 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6002 return r;
6003
6004 if (signed_op) {
6005
6006 /* fix the sign of the result */
6007
6008 if (mod) {
6009
6010 /* tmp0.x = -tmp0.z */
6011 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6012 alu.op = ALU_OP2_SUB_INT;
6013
6014 alu.dst.sel = tmp0;
6015 alu.dst.chan = 0;
6016 alu.dst.write = 1;
6017
6018 alu.src[0].sel = V_SQ_ALU_SRC_0;
6019 alu.src[1].sel = tmp0;
6020 alu.src[1].chan = 2;
6021
6022 alu.last = 1;
6023 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6024 return r;
6025
6026 /* sign of the remainder is the same as the sign of src0 */
6027 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
6028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6029 alu.op = ALU_OP3_CNDGE_INT;
6030 alu.is_op3 = 1;
6031
6032 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6033
6034 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6035 alu.src[1].sel = tmp0;
6036 alu.src[1].chan = 2;
6037 alu.src[2].sel = tmp0;
6038 alu.src[2].chan = 0;
6039
6040 alu.last = 1;
6041 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6042 return r;
6043
6044 } else {
6045
6046 /* tmp0.x = -tmp0.z */
6047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6048 alu.op = ALU_OP2_SUB_INT;
6049
6050 alu.dst.sel = tmp0;
6051 alu.dst.chan = 0;
6052 alu.dst.write = 1;
6053
6054 alu.src[0].sel = V_SQ_ALU_SRC_0;
6055 alu.src[1].sel = tmp0;
6056 alu.src[1].chan = 2;
6057
6058 alu.last = 1;
6059 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6060 return r;
6061
6062 /* fix the quotient sign (same as the sign of src0*src1) */
6063 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
6064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6065 alu.op = ALU_OP3_CNDGE_INT;
6066 alu.is_op3 = 1;
6067
6068 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6069
6070 alu.src[0].sel = tmp2;
6071 alu.src[0].chan = 2;
6072 alu.src[1].sel = tmp0;
6073 alu.src[1].chan = 2;
6074 alu.src[2].sel = tmp0;
6075 alu.src[2].chan = 0;
6076
6077 alu.last = 1;
6078 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6079 return r;
6080 }
6081 }
6082 }
6083 return 0;
6084 }
6085
6086 static int tgsi_udiv(struct r600_shader_ctx *ctx)
6087 {
6088 return tgsi_divmod(ctx, 0, 0);
6089 }
6090
6091 static int tgsi_umod(struct r600_shader_ctx *ctx)
6092 {
6093 return tgsi_divmod(ctx, 1, 0);
6094 }
6095
6096 static int tgsi_idiv(struct r600_shader_ctx *ctx)
6097 {
6098 return tgsi_divmod(ctx, 0, 1);
6099 }
6100
6101 static int tgsi_imod(struct r600_shader_ctx *ctx)
6102 {
6103 return tgsi_divmod(ctx, 1, 1);
6104 }
6105
6106
6107 static int tgsi_f2i(struct r600_shader_ctx *ctx)
6108 {
6109 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6110 struct r600_bytecode_alu alu;
6111 int i, r;
6112 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6113 int last_inst = tgsi_last_instruction(write_mask);
6114
6115 for (i = 0; i < 4; i++) {
6116 if (!(write_mask & (1<<i)))
6117 continue;
6118
6119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6120 alu.op = ALU_OP1_TRUNC;
6121
6122 alu.dst.sel = ctx->temp_reg;
6123 alu.dst.chan = i;
6124 alu.dst.write = 1;
6125
6126 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6127 if (i == last_inst)
6128 alu.last = 1;
6129 r = r600_bytecode_add_alu(ctx->bc, &alu);
6130 if (r)
6131 return r;
6132 }
6133
6134 for (i = 0; i < 4; i++) {
6135 if (!(write_mask & (1<<i)))
6136 continue;
6137
6138 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6139 alu.op = ctx->inst_info->op;
6140
6141 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6142
6143 alu.src[0].sel = ctx->temp_reg;
6144 alu.src[0].chan = i;
6145
6146 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6147 alu.last = 1;
6148 r = r600_bytecode_add_alu(ctx->bc, &alu);
6149 if (r)
6150 return r;
6151 }
6152
6153 return 0;
6154 }
6155
6156 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6157 {
6158 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6159 struct r600_bytecode_alu alu;
6160 int i, r;
6161 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6162 int last_inst = tgsi_last_instruction(write_mask);
6163
6164 /* tmp = -src */
6165 for (i = 0; i < 4; i++) {
6166 if (!(write_mask & (1<<i)))
6167 continue;
6168
6169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6170 alu.op = ALU_OP2_SUB_INT;
6171
6172 alu.dst.sel = ctx->temp_reg;
6173 alu.dst.chan = i;
6174 alu.dst.write = 1;
6175
6176 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6177 alu.src[0].sel = V_SQ_ALU_SRC_0;
6178
6179 if (i == last_inst)
6180 alu.last = 1;
6181 r = r600_bytecode_add_alu(ctx->bc, &alu);
6182 if (r)
6183 return r;
6184 }
6185
6186 /* dst = (src >= 0 ? src : tmp) */
6187 for (i = 0; i < 4; i++) {
6188 if (!(write_mask & (1<<i)))
6189 continue;
6190
6191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6192 alu.op = ALU_OP3_CNDGE_INT;
6193 alu.is_op3 = 1;
6194 alu.dst.write = 1;
6195
6196 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6197
6198 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6199 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6200 alu.src[2].sel = ctx->temp_reg;
6201 alu.src[2].chan = i;
6202
6203 if (i == last_inst)
6204 alu.last = 1;
6205 r = r600_bytecode_add_alu(ctx->bc, &alu);
6206 if (r)
6207 return r;
6208 }
6209 return 0;
6210 }
6211
6212 static int tgsi_issg(struct r600_shader_ctx *ctx)
6213 {
6214 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6215 struct r600_bytecode_alu alu;
6216 int i, r;
6217 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6218 int last_inst = tgsi_last_instruction(write_mask);
6219
6220 /* tmp = (src >= 0 ? src : -1) */
6221 for (i = 0; i < 4; i++) {
6222 if (!(write_mask & (1<<i)))
6223 continue;
6224
6225 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6226 alu.op = ALU_OP3_CNDGE_INT;
6227 alu.is_op3 = 1;
6228
6229 alu.dst.sel = ctx->temp_reg;
6230 alu.dst.chan = i;
6231 alu.dst.write = 1;
6232
6233 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6234 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6235 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6236
6237 if (i == last_inst)
6238 alu.last = 1;
6239 r = r600_bytecode_add_alu(ctx->bc, &alu);
6240 if (r)
6241 return r;
6242 }
6243
6244 /* dst = (tmp > 0 ? 1 : tmp) */
6245 for (i = 0; i < 4; i++) {
6246 if (!(write_mask & (1<<i)))
6247 continue;
6248
6249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6250 alu.op = ALU_OP3_CNDGT_INT;
6251 alu.is_op3 = 1;
6252 alu.dst.write = 1;
6253
6254 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6255
6256 alu.src[0].sel = ctx->temp_reg;
6257 alu.src[0].chan = i;
6258
6259 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6260
6261 alu.src[2].sel = ctx->temp_reg;
6262 alu.src[2].chan = i;
6263
6264 if (i == last_inst)
6265 alu.last = 1;
6266 r = r600_bytecode_add_alu(ctx->bc, &alu);
6267 if (r)
6268 return r;
6269 }
6270 return 0;
6271 }
6272
6273
6274
6275 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6276 {
6277 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6278 struct r600_bytecode_alu alu;
6279 int i, r;
6280
6281 /* tmp = (src > 0 ? 1 : src) */
6282 for (i = 0; i < 4; i++) {
6283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6284 alu.op = ALU_OP3_CNDGT;
6285 alu.is_op3 = 1;
6286
6287 alu.dst.sel = ctx->temp_reg;
6288 alu.dst.chan = i;
6289
6290 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6291 alu.src[1].sel = V_SQ_ALU_SRC_1;
6292 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6293
6294 if (i == 3)
6295 alu.last = 1;
6296 r = r600_bytecode_add_alu(ctx->bc, &alu);
6297 if (r)
6298 return r;
6299 }
6300
6301 /* dst = (-tmp > 0 ? -1 : tmp) */
6302 for (i = 0; i < 4; i++) {
6303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6304 alu.op = ALU_OP3_CNDGT;
6305 alu.is_op3 = 1;
6306 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6307
6308 alu.src[0].sel = ctx->temp_reg;
6309 alu.src[0].chan = i;
6310 alu.src[0].neg = 1;
6311
6312 alu.src[1].sel = V_SQ_ALU_SRC_1;
6313 alu.src[1].neg = 1;
6314
6315 alu.src[2].sel = ctx->temp_reg;
6316 alu.src[2].chan = i;
6317
6318 if (i == 3)
6319 alu.last = 1;
6320 r = r600_bytecode_add_alu(ctx->bc, &alu);
6321 if (r)
6322 return r;
6323 }
6324 return 0;
6325 }
6326
6327 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6328 {
6329 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6330 struct r600_bytecode_alu alu;
6331 int i, r, t1, t2;
6332
6333 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6334 int last_inst = tgsi_last_instruction(write_mask);
6335
6336 t1 = r600_get_temp(ctx);
6337
6338 for (i = 0; i < 4; i++) {
6339 if (!(write_mask & (1<<i)))
6340 continue;
6341
6342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6343 alu.op = ALU_OP2_SETGE_INT;
6344 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6345 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6346 alu.src[1].value = 32;
6347 alu.dst.sel = ctx->temp_reg;
6348 alu.dst.chan = i;
6349 alu.dst.write = 1;
6350 alu.last = i == last_inst;
6351 r = r600_bytecode_add_alu(ctx->bc, &alu);
6352 if (r)
6353 return r;
6354 }
6355
6356 for (i = 0; i < 4; i++) {
6357 if (!(write_mask & (1<<i)))
6358 continue;
6359
6360 /* create mask tmp */
6361 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6362 alu.op = ALU_OP2_BFM_INT;
6363 alu.dst.sel = t1;
6364 alu.dst.chan = i;
6365 alu.dst.write = 1;
6366 alu.last = i == last_inst;
6367
6368 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6369 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6370
6371 r = r600_bytecode_add_alu(ctx->bc, &alu);
6372 if (r)
6373 return r;
6374 }
6375
6376 t2 = r600_get_temp(ctx);
6377
6378 for (i = 0; i < 4; i++) {
6379 if (!(write_mask & (1<<i)))
6380 continue;
6381
6382 /* shift insert left */
6383 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6384 alu.op = ALU_OP2_LSHL_INT;
6385 alu.dst.sel = t2;
6386 alu.dst.chan = i;
6387 alu.dst.write = 1;
6388 alu.last = i == last_inst;
6389
6390 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6391 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6392
6393 r = r600_bytecode_add_alu(ctx->bc, &alu);
6394 if (r)
6395 return r;
6396 }
6397
6398 for (i = 0; i < 4; i++) {
6399 if (!(write_mask & (1<<i)))
6400 continue;
6401
6402 /* actual bitfield insert */
6403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6404 alu.op = ALU_OP3_BFI_INT;
6405 alu.is_op3 = 1;
6406 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6407 alu.dst.chan = i;
6408 alu.dst.write = 1;
6409 alu.last = i == last_inst;
6410
6411 alu.src[0].sel = t1;
6412 alu.src[0].chan = i;
6413 alu.src[1].sel = t2;
6414 alu.src[1].chan = i;
6415 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6416
6417 r = r600_bytecode_add_alu(ctx->bc, &alu);
6418 if (r)
6419 return r;
6420 }
6421
6422 for (i = 0; i < 4; i++) {
6423 if (!(write_mask & (1<<i)))
6424 continue;
6425 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6426 alu.op = ALU_OP3_CNDE_INT;
6427 alu.is_op3 = 1;
6428 alu.src[0].sel = ctx->temp_reg;
6429 alu.src[0].chan = i;
6430 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6431
6432 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6433
6434 alu.src[1].sel = alu.dst.sel;
6435 alu.src[1].chan = i;
6436
6437 alu.last = i == last_inst;
6438 r = r600_bytecode_add_alu(ctx->bc, &alu);
6439 if (r)
6440 return r;
6441 }
6442 return 0;
6443 }
6444
6445 static int tgsi_msb(struct r600_shader_ctx *ctx)
6446 {
6447 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6448 struct r600_bytecode_alu alu;
6449 int i, r, t1, t2;
6450
6451 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6452 int last_inst = tgsi_last_instruction(write_mask);
6453
6454 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6455 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6456
6457 t1 = ctx->temp_reg;
6458
6459 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6460 for (i = 0; i < 4; i++) {
6461 if (!(write_mask & (1<<i)))
6462 continue;
6463
6464 /* t1 = FFBH_INT / FFBH_UINT */
6465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6466 alu.op = ctx->inst_info->op;
6467 alu.dst.sel = t1;
6468 alu.dst.chan = i;
6469 alu.dst.write = 1;
6470 alu.last = i == last_inst;
6471
6472 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6473
6474 r = r600_bytecode_add_alu(ctx->bc, &alu);
6475 if (r)
6476 return r;
6477 }
6478
6479 t2 = r600_get_temp(ctx);
6480
6481 for (i = 0; i < 4; i++) {
6482 if (!(write_mask & (1<<i)))
6483 continue;
6484
6485 /* t2 = 31 - t1 */
6486 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6487 alu.op = ALU_OP2_SUB_INT;
6488 alu.dst.sel = t2;
6489 alu.dst.chan = i;
6490 alu.dst.write = 1;
6491 alu.last = i == last_inst;
6492
6493 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6494 alu.src[0].value = 31;
6495 alu.src[1].sel = t1;
6496 alu.src[1].chan = i;
6497
6498 r = r600_bytecode_add_alu(ctx->bc, &alu);
6499 if (r)
6500 return r;
6501 }
6502
6503 for (i = 0; i < 4; i++) {
6504 if (!(write_mask & (1<<i)))
6505 continue;
6506
6507 /* result = t1 >= 0 ? t2 : t1 */
6508 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6509 alu.op = ALU_OP3_CNDGE_INT;
6510 alu.is_op3 = 1;
6511 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6512 alu.dst.chan = i;
6513 alu.dst.write = 1;
6514 alu.last = i == last_inst;
6515
6516 alu.src[0].sel = t1;
6517 alu.src[0].chan = i;
6518 alu.src[1].sel = t2;
6519 alu.src[1].chan = i;
6520 alu.src[2].sel = t1;
6521 alu.src[2].chan = i;
6522
6523 r = r600_bytecode_add_alu(ctx->bc, &alu);
6524 if (r)
6525 return r;
6526 }
6527
6528 return 0;
6529 }
6530
6531 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6532 {
6533 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6534 struct r600_bytecode_alu alu;
6535 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6536 unsigned location;
6537 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6538
6539 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6540
6541 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6542 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6543 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6544 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6545 }
6546 else {
6547 location = TGSI_INTERPOLATE_LOC_CENTROID;
6548 }
6549
6550 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6551 if (k < 0)
6552 k = 0;
6553 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6554 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6555
6556 /* NOTE: currently offset is not perspective correct */
6557 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6558 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6559 int sample_gpr = -1;
6560 int gradientsH, gradientsV;
6561 struct r600_bytecode_tex tex;
6562
6563 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6564 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6565 }
6566
6567 gradientsH = r600_get_temp(ctx);
6568 gradientsV = r600_get_temp(ctx);
6569 for (i = 0; i < 2; i++) {
6570 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6571 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6572 tex.src_gpr = interp_gpr;
6573 tex.src_sel_x = interp_base_chan + 0;
6574 tex.src_sel_y = interp_base_chan + 1;
6575 tex.src_sel_z = 0;
6576 tex.src_sel_w = 0;
6577 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6578 tex.dst_sel_x = 0;
6579 tex.dst_sel_y = 1;
6580 tex.dst_sel_z = 7;
6581 tex.dst_sel_w = 7;
6582 tex.inst_mod = 1; // Use per pixel gradient calculation
6583 tex.sampler_id = 0;
6584 tex.resource_id = tex.sampler_id;
6585 r = r600_bytecode_add_tex(ctx->bc, &tex);
6586 if (r)
6587 return r;
6588 }
6589
6590 for (i = 0; i < 2; i++) {
6591 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6592 alu.op = ALU_OP3_MULADD;
6593 alu.is_op3 = 1;
6594 alu.src[0].sel = gradientsH;
6595 alu.src[0].chan = i;
6596 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6597 alu.src[1].sel = sample_gpr;
6598 alu.src[1].chan = 2;
6599 }
6600 else {
6601 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6602 }
6603 alu.src[2].sel = interp_gpr;
6604 alu.src[2].chan = interp_base_chan + i;
6605 alu.dst.sel = ctx->temp_reg;
6606 alu.dst.chan = i;
6607 alu.last = i == 1;
6608
6609 r = r600_bytecode_add_alu(ctx->bc, &alu);
6610 if (r)
6611 return r;
6612 }
6613
6614 for (i = 0; i < 2; i++) {
6615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6616 alu.op = ALU_OP3_MULADD;
6617 alu.is_op3 = 1;
6618 alu.src[0].sel = gradientsV;
6619 alu.src[0].chan = i;
6620 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6621 alu.src[1].sel = sample_gpr;
6622 alu.src[1].chan = 3;
6623 }
6624 else {
6625 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6626 }
6627 alu.src[2].sel = ctx->temp_reg;
6628 alu.src[2].chan = i;
6629 alu.dst.sel = ctx->temp_reg;
6630 alu.dst.chan = i;
6631 alu.last = i == 1;
6632
6633 r = r600_bytecode_add_alu(ctx->bc, &alu);
6634 if (r)
6635 return r;
6636 }
6637 }
6638
6639 tmp = r600_get_temp(ctx);
6640 for (i = 0; i < 8; i++) {
6641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6642 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6643
6644 alu.dst.sel = tmp;
6645 if ((i > 1 && i < 6)) {
6646 alu.dst.write = 1;
6647 }
6648 else {
6649 alu.dst.write = 0;
6650 }
6651 alu.dst.chan = i % 4;
6652
6653 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6654 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6655 alu.src[0].sel = ctx->temp_reg;
6656 alu.src[0].chan = 1 - (i % 2);
6657 } else {
6658 alu.src[0].sel = interp_gpr;
6659 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6660 }
6661 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6662 alu.src[1].chan = 0;
6663
6664 alu.last = i % 4 == 3;
6665 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6666
6667 r = r600_bytecode_add_alu(ctx->bc, &alu);
6668 if (r)
6669 return r;
6670 }
6671
6672 // INTERP can't swizzle dst
6673 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6674 for (i = 0; i <= lasti; i++) {
6675 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6676 continue;
6677
6678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6679 alu.op = ALU_OP1_MOV;
6680 alu.src[0].sel = tmp;
6681 alu.src[0].chan = ctx->src[0].swizzle[i];
6682 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6683 alu.dst.write = 1;
6684 alu.last = i == lasti;
6685 r = r600_bytecode_add_alu(ctx->bc, &alu);
6686 if (r)
6687 return r;
6688 }
6689
6690 return 0;
6691 }
6692
6693
6694 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6695 {
6696 struct r600_bytecode_alu alu;
6697 int i, r;
6698
6699 for (i = 0; i < 4; i++) {
6700 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6701 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6702 alu.op = ALU_OP0_NOP;
6703 alu.dst.chan = i;
6704 } else {
6705 alu.op = ALU_OP1_MOV;
6706 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6707 alu.src[0].sel = ctx->temp_reg;
6708 alu.src[0].chan = i;
6709 }
6710 if (i == 3) {
6711 alu.last = 1;
6712 }
6713 r = r600_bytecode_add_alu(ctx->bc, &alu);
6714 if (r)
6715 return r;
6716 }
6717 return 0;
6718 }
6719
6720 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6721 unsigned temp, int chan,
6722 struct r600_bytecode_alu_src *bc_src,
6723 const struct r600_shader_src *shader_src)
6724 {
6725 struct r600_bytecode_alu alu;
6726 int r;
6727
6728 r600_bytecode_src(bc_src, shader_src, chan);
6729
6730 /* op3 operands don't support abs modifier */
6731 if (bc_src->abs) {
6732 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6734 alu.op = ALU_OP1_MOV;
6735 alu.dst.sel = temp;
6736 alu.dst.chan = chan;
6737 alu.dst.write = 1;
6738
6739 alu.src[0] = *bc_src;
6740 alu.last = true; // sufficient?
6741 r = r600_bytecode_add_alu(ctx->bc, &alu);
6742 if (r)
6743 return r;
6744
6745 memset(bc_src, 0, sizeof(*bc_src));
6746 bc_src->sel = temp;
6747 bc_src->chan = chan;
6748 }
6749 return 0;
6750 }
6751
6752 static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
6753 {
6754 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6755 struct r600_bytecode_alu alu;
6756 int i, j, r;
6757 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6758 int temp_regs[4];
6759 unsigned op = ctx->inst_info->op;
6760
6761 if (op == ALU_OP3_MULADD_IEEE &&
6762 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6763 op = ALU_OP3_MULADD;
6764
6765 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6766 temp_regs[j] = 0;
6767 if (ctx->src[j].abs)
6768 temp_regs[j] = r600_get_temp(ctx);
6769 }
6770 for (i = 0; i < lasti + 1; i++) {
6771 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6772 continue;
6773
6774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6775 alu.op = op;
6776 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6777 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6778 if (r)
6779 return r;
6780 }
6781
6782 if (dst == -1) {
6783 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6784 } else {
6785 alu.dst.sel = dst;
6786 }
6787 alu.dst.chan = i;
6788 alu.dst.write = 1;
6789 alu.is_op3 = 1;
6790 if (i == lasti) {
6791 alu.last = 1;
6792 }
6793 r = r600_bytecode_add_alu(ctx->bc, &alu);
6794 if (r)
6795 return r;
6796 }
6797 return 0;
6798 }
6799
6800 static int tgsi_op3(struct r600_shader_ctx *ctx)
6801 {
6802 return tgsi_op3_dst(ctx, -1);
6803 }
6804
6805 static int tgsi_dp(struct r600_shader_ctx *ctx)
6806 {
6807 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6808 struct r600_bytecode_alu alu;
6809 int i, j, r;
6810 unsigned op = ctx->inst_info->op;
6811 if (op == ALU_OP2_DOT4_IEEE &&
6812 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6813 op = ALU_OP2_DOT4;
6814
6815 for (i = 0; i < 4; i++) {
6816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6817 alu.op = op;
6818 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6819 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6820 }
6821
6822 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6823 alu.dst.chan = i;
6824 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6825 /* handle some special cases */
6826 switch (inst->Instruction.Opcode) {
6827 case TGSI_OPCODE_DP2:
6828 if (i > 1) {
6829 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6830 alu.src[0].chan = alu.src[1].chan = 0;
6831 }
6832 break;
6833 case TGSI_OPCODE_DP3:
6834 if (i > 2) {
6835 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6836 alu.src[0].chan = alu.src[1].chan = 0;
6837 }
6838 break;
6839 default:
6840 break;
6841 }
6842 if (i == 3) {
6843 alu.last = 1;
6844 }
6845 r = r600_bytecode_add_alu(ctx->bc, &alu);
6846 if (r)
6847 return r;
6848 }
6849 return 0;
6850 }
6851
6852 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6853 unsigned index)
6854 {
6855 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6856 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6857 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6858 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6859 ctx->src[index].neg || ctx->src[index].abs ||
6860 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6861 }
6862
6863 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6864 unsigned index)
6865 {
6866 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6867 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6868 }
6869
6870 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6871 {
6872 struct r600_bytecode_vtx vtx;
6873 struct r600_bytecode_alu alu;
6874 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6875 int src_gpr, r, i;
6876 int id = tgsi_tex_get_src_gpr(ctx, 1);
6877
6878 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6879 if (src_requires_loading) {
6880 for (i = 0; i < 4; i++) {
6881 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6882 alu.op = ALU_OP1_MOV;
6883 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6884 alu.dst.sel = ctx->temp_reg;
6885 alu.dst.chan = i;
6886 if (i == 3)
6887 alu.last = 1;
6888 alu.dst.write = 1;
6889 r = r600_bytecode_add_alu(ctx->bc, &alu);
6890 if (r)
6891 return r;
6892 }
6893 src_gpr = ctx->temp_reg;
6894 }
6895
6896 memset(&vtx, 0, sizeof(vtx));
6897 vtx.op = FETCH_OP_VFETCH;
6898 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6899 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6900 vtx.src_gpr = src_gpr;
6901 vtx.mega_fetch_count = 16;
6902 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6903 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6904 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6905 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6906 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6907 vtx.use_const_fields = 1;
6908
6909 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6910 return r;
6911
6912 if (ctx->bc->chip_class >= EVERGREEN)
6913 return 0;
6914
6915 for (i = 0; i < 4; i++) {
6916 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6917 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6918 continue;
6919
6920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6921 alu.op = ALU_OP2_AND_INT;
6922
6923 alu.dst.chan = i;
6924 alu.dst.sel = vtx.dst_gpr;
6925 alu.dst.write = 1;
6926
6927 alu.src[0].sel = vtx.dst_gpr;
6928 alu.src[0].chan = i;
6929
6930 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6931 alu.src[1].sel += (id * 2);
6932 alu.src[1].chan = i % 4;
6933 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6934
6935 if (i == lasti)
6936 alu.last = 1;
6937 r = r600_bytecode_add_alu(ctx->bc, &alu);
6938 if (r)
6939 return r;
6940 }
6941
6942 if (inst->Dst[0].Register.WriteMask & 3) {
6943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6944 alu.op = ALU_OP2_OR_INT;
6945
6946 alu.dst.chan = 3;
6947 alu.dst.sel = vtx.dst_gpr;
6948 alu.dst.write = 1;
6949
6950 alu.src[0].sel = vtx.dst_gpr;
6951 alu.src[0].chan = 3;
6952
6953 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6954 alu.src[1].chan = 0;
6955 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6956
6957 alu.last = 1;
6958 r = r600_bytecode_add_alu(ctx->bc, &alu);
6959 if (r)
6960 return r;
6961 }
6962 return 0;
6963 }
6964
6965 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset)
6966 {
6967 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6968 struct r600_bytecode_alu alu;
6969 int r;
6970 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
6971
6972 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6973 alu.op = ALU_OP1_MOV;
6974 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6975 if (ctx->bc->chip_class >= EVERGREEN) {
6976 /* channel 0 or 2 of each word */
6977 alu.src[0].sel += (id / 2);
6978 alu.src[0].chan = (id % 2) * 2;
6979 } else {
6980 /* r600 we have them at channel 2 of the second dword */
6981 alu.src[0].sel += (id * 2) + 1;
6982 alu.src[0].chan = 1;
6983 }
6984 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6985 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6986 alu.last = 1;
6987 r = r600_bytecode_add_alu(ctx->bc, &alu);
6988 if (r)
6989 return r;
6990 return 0;
6991 }
6992
6993 static int tgsi_tex(struct r600_shader_ctx *ctx)
6994 {
6995 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6996 struct r600_bytecode_tex tex;
6997 struct r600_bytecode_alu alu;
6998 unsigned src_gpr;
6999 int r, i, j;
7000 int opcode;
7001 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
7002 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7003 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
7004 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
7005
7006 bool txf_add_offsets = inst->Texture.NumOffsets &&
7007 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7008 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
7009
7010 /* Texture fetch instructions can only use gprs as source.
7011 * Also they cannot negate the source or take the absolute value */
7012 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
7013 tgsi_tex_src_requires_loading(ctx, 0)) ||
7014 read_compressed_msaa || txf_add_offsets;
7015
7016 boolean src_loaded = FALSE;
7017 unsigned sampler_src_reg = 1;
7018 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
7019 boolean has_txq_cube_array_z = false;
7020 unsigned sampler_index_mode;
7021
7022 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
7023 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7024 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
7025 if (inst->Dst[0].Register.WriteMask & 4) {
7026 ctx->shader->has_txq_cube_array_z_comp = true;
7027 has_txq_cube_array_z = true;
7028 }
7029
7030 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
7031 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7032 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
7033 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
7034 sampler_src_reg = 2;
7035
7036 /* TGSI moves the sampler to src reg 3 for TXD */
7037 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
7038 sampler_src_reg = 3;
7039
7040 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7041
7042 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7043
7044 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
7045 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
7046 ctx->shader->uses_tex_buffers = true;
7047 return r600_do_buffer_txq(ctx, 1, 0);
7048 }
7049 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
7050 if (ctx->bc->chip_class < EVERGREEN)
7051 ctx->shader->uses_tex_buffers = true;
7052 return do_vtx_fetch_inst(ctx, src_requires_loading);
7053 }
7054 }
7055
7056 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
7057 int out_chan;
7058 /* Add perspective divide */
7059 if (ctx->bc->chip_class == CAYMAN) {
7060 out_chan = 2;
7061 for (i = 0; i < 3; i++) {
7062 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7063 alu.op = ALU_OP1_RECIP_IEEE;
7064 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7065
7066 alu.dst.sel = ctx->temp_reg;
7067 alu.dst.chan = i;
7068 if (i == 2)
7069 alu.last = 1;
7070 if (out_chan == i)
7071 alu.dst.write = 1;
7072 r = r600_bytecode_add_alu(ctx->bc, &alu);
7073 if (r)
7074 return r;
7075 }
7076
7077 } else {
7078 out_chan = 3;
7079 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7080 alu.op = ALU_OP1_RECIP_IEEE;
7081 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7082
7083 alu.dst.sel = ctx->temp_reg;
7084 alu.dst.chan = out_chan;
7085 alu.last = 1;
7086 alu.dst.write = 1;
7087 r = r600_bytecode_add_alu(ctx->bc, &alu);
7088 if (r)
7089 return r;
7090 }
7091
7092 for (i = 0; i < 3; i++) {
7093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7094 alu.op = ALU_OP2_MUL;
7095 alu.src[0].sel = ctx->temp_reg;
7096 alu.src[0].chan = out_chan;
7097 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7098 alu.dst.sel = ctx->temp_reg;
7099 alu.dst.chan = i;
7100 alu.dst.write = 1;
7101 r = r600_bytecode_add_alu(ctx->bc, &alu);
7102 if (r)
7103 return r;
7104 }
7105 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7106 alu.op = ALU_OP1_MOV;
7107 alu.src[0].sel = V_SQ_ALU_SRC_1;
7108 alu.src[0].chan = 0;
7109 alu.dst.sel = ctx->temp_reg;
7110 alu.dst.chan = 3;
7111 alu.last = 1;
7112 alu.dst.write = 1;
7113 r = r600_bytecode_add_alu(ctx->bc, &alu);
7114 if (r)
7115 return r;
7116 src_loaded = TRUE;
7117 src_gpr = ctx->temp_reg;
7118 }
7119
7120
7121 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7122 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7123 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7124 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7125 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
7126
7127 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
7128 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
7129
7130 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7131 for (i = 0; i < 4; i++) {
7132 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7133 alu.op = ALU_OP2_CUBE;
7134 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7135 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
7136 alu.dst.sel = ctx->temp_reg;
7137 alu.dst.chan = i;
7138 if (i == 3)
7139 alu.last = 1;
7140 alu.dst.write = 1;
7141 r = r600_bytecode_add_alu(ctx->bc, &alu);
7142 if (r)
7143 return r;
7144 }
7145
7146 /* tmp1.z = RCP_e(|tmp1.z|) */
7147 if (ctx->bc->chip_class == CAYMAN) {
7148 for (i = 0; i < 3; i++) {
7149 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7150 alu.op = ALU_OP1_RECIP_IEEE;
7151 alu.src[0].sel = ctx->temp_reg;
7152 alu.src[0].chan = 2;
7153 alu.src[0].abs = 1;
7154 alu.dst.sel = ctx->temp_reg;
7155 alu.dst.chan = i;
7156 if (i == 2)
7157 alu.dst.write = 1;
7158 if (i == 2)
7159 alu.last = 1;
7160 r = r600_bytecode_add_alu(ctx->bc, &alu);
7161 if (r)
7162 return r;
7163 }
7164 } else {
7165 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7166 alu.op = ALU_OP1_RECIP_IEEE;
7167 alu.src[0].sel = ctx->temp_reg;
7168 alu.src[0].chan = 2;
7169 alu.src[0].abs = 1;
7170 alu.dst.sel = ctx->temp_reg;
7171 alu.dst.chan = 2;
7172 alu.dst.write = 1;
7173 alu.last = 1;
7174 r = r600_bytecode_add_alu(ctx->bc, &alu);
7175 if (r)
7176 return r;
7177 }
7178
7179 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7180 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7181 * muladd has no writemask, have to use another temp
7182 */
7183 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7184 alu.op = ALU_OP3_MULADD;
7185 alu.is_op3 = 1;
7186
7187 alu.src[0].sel = ctx->temp_reg;
7188 alu.src[0].chan = 0;
7189 alu.src[1].sel = ctx->temp_reg;
7190 alu.src[1].chan = 2;
7191
7192 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7193 alu.src[2].chan = 0;
7194 alu.src[2].value = u_bitcast_f2u(1.5f);
7195
7196 alu.dst.sel = ctx->temp_reg;
7197 alu.dst.chan = 0;
7198 alu.dst.write = 1;
7199
7200 r = r600_bytecode_add_alu(ctx->bc, &alu);
7201 if (r)
7202 return r;
7203
7204 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7205 alu.op = ALU_OP3_MULADD;
7206 alu.is_op3 = 1;
7207
7208 alu.src[0].sel = ctx->temp_reg;
7209 alu.src[0].chan = 1;
7210 alu.src[1].sel = ctx->temp_reg;
7211 alu.src[1].chan = 2;
7212
7213 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7214 alu.src[2].chan = 0;
7215 alu.src[2].value = u_bitcast_f2u(1.5f);
7216
7217 alu.dst.sel = ctx->temp_reg;
7218 alu.dst.chan = 1;
7219 alu.dst.write = 1;
7220
7221 alu.last = 1;
7222 r = r600_bytecode_add_alu(ctx->bc, &alu);
7223 if (r)
7224 return r;
7225 /* write initial compare value into Z component
7226 - W src 0 for shadow cube
7227 - X src 1 for shadow cube array */
7228 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7229 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7231 alu.op = ALU_OP1_MOV;
7232 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7233 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7234 else
7235 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7236 alu.dst.sel = ctx->temp_reg;
7237 alu.dst.chan = 2;
7238 alu.dst.write = 1;
7239 alu.last = 1;
7240 r = r600_bytecode_add_alu(ctx->bc, &alu);
7241 if (r)
7242 return r;
7243 }
7244
7245 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7246 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7247 if (ctx->bc->chip_class >= EVERGREEN) {
7248 int mytmp = r600_get_temp(ctx);
7249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7250 alu.op = ALU_OP1_MOV;
7251 alu.src[0].sel = ctx->temp_reg;
7252 alu.src[0].chan = 3;
7253 alu.dst.sel = mytmp;
7254 alu.dst.chan = 0;
7255 alu.dst.write = 1;
7256 alu.last = 1;
7257 r = r600_bytecode_add_alu(ctx->bc, &alu);
7258 if (r)
7259 return r;
7260
7261 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7262 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7263 alu.op = ALU_OP3_MULADD;
7264 alu.is_op3 = 1;
7265 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7266 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7267 alu.src[1].chan = 0;
7268 alu.src[1].value = u_bitcast_f2u(8.0f);
7269 alu.src[2].sel = mytmp;
7270 alu.src[2].chan = 0;
7271 alu.dst.sel = ctx->temp_reg;
7272 alu.dst.chan = 3;
7273 alu.dst.write = 1;
7274 alu.last = 1;
7275 r = r600_bytecode_add_alu(ctx->bc, &alu);
7276 if (r)
7277 return r;
7278 } else if (ctx->bc->chip_class < EVERGREEN) {
7279 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7280 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7281 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7282 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7283 tex.src_gpr = r600_get_temp(ctx);
7284 tex.src_sel_x = 0;
7285 tex.src_sel_y = 0;
7286 tex.src_sel_z = 0;
7287 tex.src_sel_w = 0;
7288 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7289 tex.coord_type_x = 1;
7290 tex.coord_type_y = 1;
7291 tex.coord_type_z = 1;
7292 tex.coord_type_w = 1;
7293 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7294 alu.op = ALU_OP1_MOV;
7295 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7296 alu.dst.sel = tex.src_gpr;
7297 alu.dst.chan = 0;
7298 alu.last = 1;
7299 alu.dst.write = 1;
7300 r = r600_bytecode_add_alu(ctx->bc, &alu);
7301 if (r)
7302 return r;
7303
7304 r = r600_bytecode_add_tex(ctx->bc, &tex);
7305 if (r)
7306 return r;
7307 }
7308
7309 }
7310
7311 /* for cube forms of lod and bias we need to route things */
7312 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7313 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7314 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7315 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7316 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7317 alu.op = ALU_OP1_MOV;
7318 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7319 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7320 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7321 else
7322 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7323 alu.dst.sel = ctx->temp_reg;
7324 alu.dst.chan = 2;
7325 alu.last = 1;
7326 alu.dst.write = 1;
7327 r = r600_bytecode_add_alu(ctx->bc, &alu);
7328 if (r)
7329 return r;
7330 }
7331
7332 src_loaded = TRUE;
7333 src_gpr = ctx->temp_reg;
7334 }
7335
7336 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7337 int temp_h = 0, temp_v = 0;
7338 int start_val = 0;
7339
7340 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7341 if (src_loaded == TRUE)
7342 start_val = 1;
7343 else
7344 src_loaded = TRUE;
7345 for (i = start_val; i < 3; i++) {
7346 int treg = r600_get_temp(ctx);
7347
7348 if (i == 0)
7349 src_gpr = treg;
7350 else if (i == 1)
7351 temp_h = treg;
7352 else
7353 temp_v = treg;
7354
7355 for (j = 0; j < 4; j++) {
7356 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7357 alu.op = ALU_OP1_MOV;
7358 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7359 alu.dst.sel = treg;
7360 alu.dst.chan = j;
7361 if (j == 3)
7362 alu.last = 1;
7363 alu.dst.write = 1;
7364 r = r600_bytecode_add_alu(ctx->bc, &alu);
7365 if (r)
7366 return r;
7367 }
7368 }
7369 for (i = 1; i < 3; i++) {
7370 /* set gradients h/v */
7371 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7372 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7373 FETCH_OP_SET_GRADIENTS_V;
7374 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7375 tex.sampler_index_mode = sampler_index_mode;
7376 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7377 tex.resource_index_mode = sampler_index_mode;
7378
7379 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7380 tex.src_sel_x = 0;
7381 tex.src_sel_y = 1;
7382 tex.src_sel_z = 2;
7383 tex.src_sel_w = 3;
7384
7385 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7386 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7387 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7388 tex.coord_type_x = 1;
7389 tex.coord_type_y = 1;
7390 tex.coord_type_z = 1;
7391 tex.coord_type_w = 1;
7392 }
7393 r = r600_bytecode_add_tex(ctx->bc, &tex);
7394 if (r)
7395 return r;
7396 }
7397 }
7398
7399 if (src_requires_loading && !src_loaded) {
7400 for (i = 0; i < 4; i++) {
7401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7402 alu.op = ALU_OP1_MOV;
7403 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7404 alu.dst.sel = ctx->temp_reg;
7405 alu.dst.chan = i;
7406 if (i == 3)
7407 alu.last = 1;
7408 alu.dst.write = 1;
7409 r = r600_bytecode_add_alu(ctx->bc, &alu);
7410 if (r)
7411 return r;
7412 }
7413 src_loaded = TRUE;
7414 src_gpr = ctx->temp_reg;
7415 }
7416
7417 /* get offset values */
7418 if (inst->Texture.NumOffsets) {
7419 assert(inst->Texture.NumOffsets == 1);
7420
7421 /* The texture offset feature doesn't work with the TXF instruction
7422 * and must be emulated by adding the offset to the texture coordinates. */
7423 if (txf_add_offsets) {
7424 const struct tgsi_texture_offset *off = inst->TexOffsets;
7425
7426 switch (inst->Texture.Texture) {
7427 case TGSI_TEXTURE_3D:
7428 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7429 alu.op = ALU_OP2_ADD_INT;
7430 alu.src[0].sel = src_gpr;
7431 alu.src[0].chan = 2;
7432 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7433 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7434 alu.dst.sel = src_gpr;
7435 alu.dst.chan = 2;
7436 alu.dst.write = 1;
7437 alu.last = 1;
7438 r = r600_bytecode_add_alu(ctx->bc, &alu);
7439 if (r)
7440 return r;
7441 /* fall through */
7442
7443 case TGSI_TEXTURE_2D:
7444 case TGSI_TEXTURE_SHADOW2D:
7445 case TGSI_TEXTURE_RECT:
7446 case TGSI_TEXTURE_SHADOWRECT:
7447 case TGSI_TEXTURE_2D_ARRAY:
7448 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7449 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7450 alu.op = ALU_OP2_ADD_INT;
7451 alu.src[0].sel = src_gpr;
7452 alu.src[0].chan = 1;
7453 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7454 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7455 alu.dst.sel = src_gpr;
7456 alu.dst.chan = 1;
7457 alu.dst.write = 1;
7458 alu.last = 1;
7459 r = r600_bytecode_add_alu(ctx->bc, &alu);
7460 if (r)
7461 return r;
7462 /* fall through */
7463
7464 case TGSI_TEXTURE_1D:
7465 case TGSI_TEXTURE_SHADOW1D:
7466 case TGSI_TEXTURE_1D_ARRAY:
7467 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7469 alu.op = ALU_OP2_ADD_INT;
7470 alu.src[0].sel = src_gpr;
7471 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7472 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7473 alu.dst.sel = src_gpr;
7474 alu.dst.write = 1;
7475 alu.last = 1;
7476 r = r600_bytecode_add_alu(ctx->bc, &alu);
7477 if (r)
7478 return r;
7479 break;
7480 /* texture offsets do not apply to other texture targets */
7481 }
7482 } else {
7483 switch (inst->Texture.Texture) {
7484 case TGSI_TEXTURE_3D:
7485 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7486 /* fallthrough */
7487 case TGSI_TEXTURE_2D:
7488 case TGSI_TEXTURE_SHADOW2D:
7489 case TGSI_TEXTURE_RECT:
7490 case TGSI_TEXTURE_SHADOWRECT:
7491 case TGSI_TEXTURE_2D_ARRAY:
7492 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7493 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7494 /* fallthrough */
7495 case TGSI_TEXTURE_1D:
7496 case TGSI_TEXTURE_SHADOW1D:
7497 case TGSI_TEXTURE_1D_ARRAY:
7498 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7499 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7500 }
7501 }
7502 }
7503
7504 /* Obtain the sample index for reading a compressed MSAA color texture.
7505 * To read the FMASK, we use the ldfptr instruction, which tells us
7506 * where the samples are stored.
7507 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7508 * which is the identity mapping. Each nibble says which physical sample
7509 * should be fetched to get that sample.
7510 *
7511 * Assume src.z contains the sample index. It should be modified like this:
7512 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7513 * Then fetch the texel with src.
7514 */
7515 if (read_compressed_msaa) {
7516 unsigned sample_chan = 3;
7517 unsigned temp = r600_get_temp(ctx);
7518 assert(src_loaded);
7519
7520 /* temp.w = ldfptr() */
7521 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7522 tex.op = FETCH_OP_LD;
7523 tex.inst_mod = 1; /* to indicate this is ldfptr */
7524 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7525 tex.sampler_index_mode = sampler_index_mode;
7526 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7527 tex.resource_index_mode = sampler_index_mode;
7528 tex.src_gpr = src_gpr;
7529 tex.dst_gpr = temp;
7530 tex.dst_sel_x = 7; /* mask out these components */
7531 tex.dst_sel_y = 7;
7532 tex.dst_sel_z = 7;
7533 tex.dst_sel_w = 0; /* store X */
7534 tex.src_sel_x = 0;
7535 tex.src_sel_y = 1;
7536 tex.src_sel_z = 2;
7537 tex.src_sel_w = 3;
7538 tex.offset_x = offset_x;
7539 tex.offset_y = offset_y;
7540 tex.offset_z = offset_z;
7541 r = r600_bytecode_add_tex(ctx->bc, &tex);
7542 if (r)
7543 return r;
7544
7545 /* temp.x = sample_index*4 */
7546 if (ctx->bc->chip_class == CAYMAN) {
7547 for (i = 0 ; i < 4; i++) {
7548 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7549 alu.op = ALU_OP2_MULLO_INT;
7550 alu.src[0].sel = src_gpr;
7551 alu.src[0].chan = sample_chan;
7552 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7553 alu.src[1].value = 4;
7554 alu.dst.sel = temp;
7555 alu.dst.chan = i;
7556 alu.dst.write = i == 0;
7557 if (i == 3)
7558 alu.last = 1;
7559 r = r600_bytecode_add_alu(ctx->bc, &alu);
7560 if (r)
7561 return r;
7562 }
7563 } else {
7564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7565 alu.op = ALU_OP2_MULLO_INT;
7566 alu.src[0].sel = src_gpr;
7567 alu.src[0].chan = sample_chan;
7568 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7569 alu.src[1].value = 4;
7570 alu.dst.sel = temp;
7571 alu.dst.chan = 0;
7572 alu.dst.write = 1;
7573 alu.last = 1;
7574 r = r600_bytecode_add_alu(ctx->bc, &alu);
7575 if (r)
7576 return r;
7577 }
7578
7579 /* sample_index = temp.w >> temp.x */
7580 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7581 alu.op = ALU_OP2_LSHR_INT;
7582 alu.src[0].sel = temp;
7583 alu.src[0].chan = 3;
7584 alu.src[1].sel = temp;
7585 alu.src[1].chan = 0;
7586 alu.dst.sel = src_gpr;
7587 alu.dst.chan = sample_chan;
7588 alu.dst.write = 1;
7589 alu.last = 1;
7590 r = r600_bytecode_add_alu(ctx->bc, &alu);
7591 if (r)
7592 return r;
7593
7594 /* sample_index & 0xF */
7595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7596 alu.op = ALU_OP2_AND_INT;
7597 alu.src[0].sel = src_gpr;
7598 alu.src[0].chan = sample_chan;
7599 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7600 alu.src[1].value = 0xF;
7601 alu.dst.sel = src_gpr;
7602 alu.dst.chan = sample_chan;
7603 alu.dst.write = 1;
7604 alu.last = 1;
7605 r = r600_bytecode_add_alu(ctx->bc, &alu);
7606 if (r)
7607 return r;
7608 #if 0
7609 /* visualize the FMASK */
7610 for (i = 0; i < 4; i++) {
7611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7612 alu.op = ALU_OP1_INT_TO_FLT;
7613 alu.src[0].sel = src_gpr;
7614 alu.src[0].chan = sample_chan;
7615 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7616 alu.dst.chan = i;
7617 alu.dst.write = 1;
7618 alu.last = 1;
7619 r = r600_bytecode_add_alu(ctx->bc, &alu);
7620 if (r)
7621 return r;
7622 }
7623 return 0;
7624 #endif
7625 }
7626
7627 /* does this shader want a num layers from TXQ for a cube array? */
7628 if (has_txq_cube_array_z) {
7629 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7630
7631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7632 alu.op = ALU_OP1_MOV;
7633
7634 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7635 if (ctx->bc->chip_class >= EVERGREEN) {
7636 /* channel 1 or 3 of each word */
7637 alu.src[0].sel += (id / 2);
7638 alu.src[0].chan = ((id % 2) * 2) + 1;
7639 } else {
7640 /* r600 we have them at channel 2 of the second dword */
7641 alu.src[0].sel += (id * 2) + 1;
7642 alu.src[0].chan = 2;
7643 }
7644 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7645 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7646 alu.last = 1;
7647 r = r600_bytecode_add_alu(ctx->bc, &alu);
7648 if (r)
7649 return r;
7650 /* disable writemask from texture instruction */
7651 inst->Dst[0].Register.WriteMask &= ~4;
7652 }
7653
7654 opcode = ctx->inst_info->op;
7655 if (opcode == FETCH_OP_GATHER4 &&
7656 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7657 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7658 opcode = FETCH_OP_GATHER4_O;
7659
7660 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7661 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7662 encoded in the instruction are ignored. */
7663 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7664 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7665 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7666 tex.sampler_index_mode = sampler_index_mode;
7667 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7668 tex.resource_index_mode = sampler_index_mode;
7669
7670 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7671 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7672 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7673 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7674 tex.src_sel_w = 4;
7675
7676 tex.dst_sel_x = 7;
7677 tex.dst_sel_y = 7;
7678 tex.dst_sel_z = 7;
7679 tex.dst_sel_w = 7;
7680
7681 r = r600_bytecode_add_tex(ctx->bc, &tex);
7682 if (r)
7683 return r;
7684 }
7685
7686 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7687 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7688 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7689 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7690 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7691 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7692 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7693 switch (opcode) {
7694 case FETCH_OP_SAMPLE:
7695 opcode = FETCH_OP_SAMPLE_C;
7696 break;
7697 case FETCH_OP_SAMPLE_L:
7698 opcode = FETCH_OP_SAMPLE_C_L;
7699 break;
7700 case FETCH_OP_SAMPLE_LB:
7701 opcode = FETCH_OP_SAMPLE_C_LB;
7702 break;
7703 case FETCH_OP_SAMPLE_G:
7704 opcode = FETCH_OP_SAMPLE_C_G;
7705 break;
7706 /* Texture gather variants */
7707 case FETCH_OP_GATHER4:
7708 opcode = FETCH_OP_GATHER4_C;
7709 break;
7710 case FETCH_OP_GATHER4_O:
7711 opcode = FETCH_OP_GATHER4_C_O;
7712 break;
7713 }
7714 }
7715
7716 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7717 tex.op = opcode;
7718
7719 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7720 tex.sampler_index_mode = sampler_index_mode;
7721 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7722 tex.resource_index_mode = sampler_index_mode;
7723 tex.src_gpr = src_gpr;
7724 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7725
7726 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7727 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7728 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7729 }
7730
7731 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7732 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7733 tex.inst_mod = texture_component_select;
7734
7735 if (ctx->bc->chip_class == CAYMAN) {
7736 /* GATHER4 result order is different from TGSI TG4 */
7737 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7738 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7739 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7740 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7741 } else {
7742 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7743 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7744 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7745 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7746 }
7747 }
7748 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7749 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7750 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7751 tex.dst_sel_z = 7;
7752 tex.dst_sel_w = 7;
7753 }
7754 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7755 tex.dst_sel_x = 3;
7756 tex.dst_sel_y = 7;
7757 tex.dst_sel_z = 7;
7758 tex.dst_sel_w = 7;
7759 }
7760 else {
7761 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7762 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7763 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7764 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7765 }
7766
7767
7768 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7769 tex.src_sel_x = 4;
7770 tex.src_sel_y = 4;
7771 tex.src_sel_z = 4;
7772 tex.src_sel_w = 4;
7773 } else if (src_loaded) {
7774 tex.src_sel_x = 0;
7775 tex.src_sel_y = 1;
7776 tex.src_sel_z = 2;
7777 tex.src_sel_w = 3;
7778 } else {
7779 tex.src_sel_x = ctx->src[0].swizzle[0];
7780 tex.src_sel_y = ctx->src[0].swizzle[1];
7781 tex.src_sel_z = ctx->src[0].swizzle[2];
7782 tex.src_sel_w = ctx->src[0].swizzle[3];
7783 tex.src_rel = ctx->src[0].rel;
7784 }
7785
7786 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7787 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7788 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7789 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7790 tex.src_sel_x = 1;
7791 tex.src_sel_y = 0;
7792 tex.src_sel_z = 3;
7793 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7794 }
7795
7796 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7797 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7798 tex.coord_type_x = 1;
7799 tex.coord_type_y = 1;
7800 }
7801 tex.coord_type_z = 1;
7802 tex.coord_type_w = 1;
7803
7804 tex.offset_x = offset_x;
7805 tex.offset_y = offset_y;
7806 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7807 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7808 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7809 tex.offset_z = 0;
7810 }
7811 else {
7812 tex.offset_z = offset_z;
7813 }
7814
7815 /* Put the depth for comparison in W.
7816 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7817 * Some instructions expect the depth in Z. */
7818 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7819 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7820 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7821 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7822 opcode != FETCH_OP_SAMPLE_C_L &&
7823 opcode != FETCH_OP_SAMPLE_C_LB) {
7824 tex.src_sel_w = tex.src_sel_z;
7825 }
7826
7827 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7828 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7829 if (opcode == FETCH_OP_SAMPLE_C_L ||
7830 opcode == FETCH_OP_SAMPLE_C_LB) {
7831 /* the array index is read from Y */
7832 tex.coord_type_y = 0;
7833 } else {
7834 /* the array index is read from Z */
7835 tex.coord_type_z = 0;
7836 tex.src_sel_z = tex.src_sel_y;
7837 }
7838 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7839 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7840 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7841 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7842 (ctx->bc->chip_class >= EVERGREEN)))
7843 /* the array index is read from Z */
7844 tex.coord_type_z = 0;
7845
7846 /* mask unused source components */
7847 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7848 switch (inst->Texture.Texture) {
7849 case TGSI_TEXTURE_2D:
7850 case TGSI_TEXTURE_RECT:
7851 tex.src_sel_z = 7;
7852 tex.src_sel_w = 7;
7853 break;
7854 case TGSI_TEXTURE_1D_ARRAY:
7855 tex.src_sel_y = 7;
7856 tex.src_sel_w = 7;
7857 break;
7858 case TGSI_TEXTURE_1D:
7859 tex.src_sel_y = 7;
7860 tex.src_sel_z = 7;
7861 tex.src_sel_w = 7;
7862 break;
7863 }
7864 }
7865
7866 r = r600_bytecode_add_tex(ctx->bc, &tex);
7867 if (r)
7868 return r;
7869
7870 /* add shadow ambient support - gallium doesn't do it yet */
7871 return 0;
7872 }
7873
7874 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7875 struct tgsi_full_src_register *src)
7876 {
7877 unsigned i;
7878
7879 if (src->Register.Indirect) {
7880 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7881 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7882 return ctx->shader->atomics[i].hw_idx;
7883 }
7884 } else {
7885 uint32_t index = src->Register.Index;
7886 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7887 if (ctx->shader->atomics[i].buffer_id != (unsigned)src->Dimension.Index)
7888 continue;
7889 if (index > ctx->shader->atomics[i].end)
7890 continue;
7891 if (index < ctx->shader->atomics[i].start)
7892 continue;
7893 uint32_t offset = (index - ctx->shader->atomics[i].start);
7894 return ctx->shader->atomics[i].hw_idx + offset;
7895 }
7896 }
7897 assert(0);
7898 return -1;
7899 }
7900
7901 static int tgsi_set_gds_temp(struct r600_shader_ctx *ctx,
7902 int *uav_id_p, int *uav_index_mode_p)
7903 {
7904 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7905 int uav_id, uav_index_mode = 0;
7906 int r;
7907 bool is_cm = (ctx->bc->chip_class == CAYMAN);
7908
7909 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7910
7911 if (inst->Src[0].Register.Indirect) {
7912 if (is_cm) {
7913 struct r600_bytecode_alu alu;
7914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7915 alu.op = ALU_OP2_LSHL_INT;
7916 alu.src[0].sel = get_address_file_reg(ctx, inst->Src[0].Indirect.Index);
7917 alu.src[0].chan = 0;
7918 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7919 alu.src[1].value = 2;
7920 alu.dst.sel = ctx->temp_reg;
7921 alu.dst.chan = 0;
7922 alu.dst.write = 1;
7923 alu.last = 1;
7924 r = r600_bytecode_add_alu(ctx->bc, &alu);
7925 if (r)
7926 return r;
7927
7928 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
7929 ctx->temp_reg, 0,
7930 ctx->temp_reg, 0,
7931 V_SQ_ALU_SRC_LITERAL, uav_id * 4);
7932 if (r)
7933 return r;
7934 } else
7935 uav_index_mode = 2;
7936 } else if (is_cm) {
7937 r = single_alu_op2(ctx, ALU_OP1_MOV,
7938 ctx->temp_reg, 0,
7939 V_SQ_ALU_SRC_LITERAL, uav_id * 4,
7940 0, 0);
7941 if (r)
7942 return r;
7943 }
7944 *uav_id_p = uav_id;
7945 *uav_index_mode_p = uav_index_mode;
7946 return 0;
7947 }
7948
7949 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7950 {
7951 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7952 int r;
7953 struct r600_bytecode_gds gds;
7954 int uav_id = 0;
7955 int uav_index_mode = 0;
7956 bool is_cm = (ctx->bc->chip_class == CAYMAN);
7957
7958 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
7959 if (r)
7960 return r;
7961
7962 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7963 gds.op = FETCH_OP_GDS_READ_RET;
7964 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7965 gds.uav_id = is_cm ? 0 : uav_id;
7966 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
7967 gds.src_gpr = ctx->temp_reg;
7968 gds.src_sel_x = (is_cm) ? 0 : 4;
7969 gds.src_sel_y = 4;
7970 gds.src_sel_z = 4;
7971 gds.dst_sel_x = 0;
7972 gds.dst_sel_y = 7;
7973 gds.dst_sel_z = 7;
7974 gds.dst_sel_w = 7;
7975 gds.src_gpr2 = 0;
7976 gds.alloc_consume = !is_cm;
7977 r = r600_bytecode_add_gds(ctx->bc, &gds);
7978 if (r)
7979 return r;
7980
7981 ctx->bc->cf_last->vpm = 1;
7982 return 0;
7983 }
7984
7985 /* this fixes up 1D arrays properly */
7986 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
7987 {
7988 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7989 int r, i;
7990 struct r600_bytecode_alu alu;
7991 int temp_reg = r600_get_temp(ctx);
7992
7993 for (i = 0; i < 4; i++) {
7994 bool def_val = true, write_zero = false;
7995 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7996 alu.op = ALU_OP1_MOV;
7997 alu.dst.sel = temp_reg;
7998 alu.dst.chan = i;
7999
8000 switch (inst->Memory.Texture) {
8001 case TGSI_TEXTURE_BUFFER:
8002 case TGSI_TEXTURE_1D:
8003 if (i == 1 || i == 2 || i == 3) {
8004 write_zero = true;
8005 }
8006 break;
8007 case TGSI_TEXTURE_1D_ARRAY:
8008 if (i == 1 || i == 3)
8009 write_zero = true;
8010 else if (i == 2) {
8011 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
8012 def_val = false;
8013 }
8014 break;
8015 case TGSI_TEXTURE_2D:
8016 if (i == 2 || i == 3)
8017 write_zero = true;
8018 break;
8019 default:
8020 if (i == 3)
8021 write_zero = true;
8022 break;
8023 }
8024
8025 if (write_zero) {
8026 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8027 alu.src[0].value = 0;
8028 } else if (def_val) {
8029 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
8030 }
8031
8032 if (i == 3)
8033 alu.last = 1;
8034 alu.dst.write = 1;
8035 r = r600_bytecode_add_alu(ctx->bc, &alu);
8036 if (r)
8037 return r;
8038 }
8039 *idx_gpr = temp_reg;
8040 return 0;
8041 }
8042
8043 static int load_buffer_coord(struct r600_shader_ctx *ctx, int src_idx,
8044 int temp_reg)
8045 {
8046 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8047 int r;
8048 if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
8049 int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
8050 r = single_alu_op2(ctx, ALU_OP1_MOV,
8051 temp_reg, 0,
8052 V_SQ_ALU_SRC_LITERAL, value >> 2,
8053 0, 0);
8054 if (r)
8055 return r;
8056 } else {
8057 struct r600_bytecode_alu alu;
8058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8059 alu.op = ALU_OP2_LSHR_INT;
8060 r600_bytecode_src(&alu.src[0], &ctx->src[src_idx], 0);
8061 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8062 alu.src[1].value = 2;
8063 alu.dst.sel = temp_reg;
8064 alu.dst.write = 1;
8065 alu.last = 1;
8066 r = r600_bytecode_add_alu(ctx->bc, &alu);
8067 if (r)
8068 return r;
8069 }
8070 return 0;
8071 }
8072
8073 static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
8074 {
8075 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8076 /* have to work out the offset into the RAT immediate return buffer */
8077 struct r600_bytecode_vtx vtx;
8078 struct r600_bytecode_cf *cf;
8079 int r;
8080 int temp_reg = r600_get_temp(ctx);
8081 unsigned rat_index_mode;
8082 unsigned base;
8083
8084 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8085 base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
8086
8087 r = load_buffer_coord(ctx, 1, temp_reg);
8088 if (r)
8089 return r;
8090 ctx->bc->cf_last->barrier = 1;
8091 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8092 vtx.op = FETCH_OP_VFETCH;
8093 vtx.buffer_id = inst->Src[0].Register.Index + base;
8094 vtx.buffer_index_mode = rat_index_mode;
8095 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8096 vtx.src_gpr = temp_reg;
8097 vtx.src_sel_x = 0;
8098 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8099 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
8100 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
8101 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
8102 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
8103 vtx.num_format_all = 1;
8104 vtx.format_comp_all = 1;
8105 vtx.srf_mode_all = 0;
8106
8107 if (inst->Dst[0].Register.WriteMask & 8) {
8108 vtx.data_format = FMT_32_32_32_32;
8109 vtx.use_const_fields = 0;
8110 } else if (inst->Dst[0].Register.WriteMask & 4) {
8111 vtx.data_format = FMT_32_32_32;
8112 vtx.use_const_fields = 0;
8113 } else if (inst->Dst[0].Register.WriteMask & 2) {
8114 vtx.data_format = FMT_32_32;
8115 vtx.use_const_fields = 0;
8116 } else {
8117 vtx.data_format = FMT_32;
8118 vtx.use_const_fields = 0;
8119 }
8120
8121 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8122 if (r)
8123 return r;
8124 cf = ctx->bc->cf_last;
8125 cf->barrier = 1;
8126 return 0;
8127 }
8128
8129 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
8130 {
8131 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8132 /* have to work out the offset into the RAT immediate return buffer */
8133 struct r600_bytecode_vtx vtx;
8134 struct r600_bytecode_cf *cf;
8135 int r;
8136 int idx_gpr;
8137 unsigned format, num_format, format_comp, endian;
8138 const struct util_format_description *desc;
8139 unsigned rat_index_mode;
8140 unsigned immed_base;
8141
8142 r = load_thread_id_gpr(ctx);
8143 if (r)
8144 return r;
8145
8146 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8147
8148 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8149 r = load_index_src(ctx, 1, &idx_gpr);
8150 if (r)
8151 return r;
8152
8153 if (rat_index_mode)
8154 egcm_load_index_reg(ctx->bc, 1, false);
8155
8156 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8157 cf = ctx->bc->cf_last;
8158
8159 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8160 cf->rat.inst = V_RAT_INST_NOP_RTN;
8161 cf->rat.index_mode = rat_index_mode;
8162 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8163 cf->output.gpr = ctx->thread_id_gpr;
8164 cf->output.index_gpr = idx_gpr;
8165 cf->output.comp_mask = 0xf;
8166 cf->output.burst_count = 1;
8167 cf->vpm = 1;
8168 cf->barrier = 1;
8169 cf->mark = 1;
8170 cf->output.elem_size = 0;
8171
8172 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8173 cf = ctx->bc->cf_last;
8174 cf->barrier = 1;
8175
8176 desc = util_format_description(inst->Memory.Format);
8177 r600_vertex_data_type(inst->Memory.Format,
8178 &format, &num_format, &format_comp, &endian);
8179 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8180 vtx.op = FETCH_OP_VFETCH;
8181 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8182 vtx.buffer_index_mode = rat_index_mode;
8183 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8184 vtx.src_gpr = ctx->thread_id_gpr;
8185 vtx.src_sel_x = 1;
8186 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8187 vtx.dst_sel_x = desc->swizzle[0];
8188 vtx.dst_sel_y = desc->swizzle[1];
8189 vtx.dst_sel_z = desc->swizzle[2];
8190 vtx.dst_sel_w = desc->swizzle[3];
8191 vtx.srf_mode_all = 1;
8192 vtx.data_format = format;
8193 vtx.num_format_all = num_format;
8194 vtx.format_comp_all = format_comp;
8195 vtx.endian = endian;
8196 vtx.offset = 0;
8197 vtx.mega_fetch_count = 3;
8198 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8199 if (r)
8200 return r;
8201 cf = ctx->bc->cf_last;
8202 cf->barrier = 1;
8203 return 0;
8204 }
8205
8206 static int tgsi_load_lds(struct r600_shader_ctx *ctx)
8207 {
8208 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8209 struct r600_bytecode_alu alu;
8210 int r;
8211 int temp_reg = r600_get_temp(ctx);
8212
8213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8214 alu.op = ALU_OP1_MOV;
8215 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8216 alu.dst.sel = temp_reg;
8217 alu.dst.write = 1;
8218 alu.last = 1;
8219 r = r600_bytecode_add_alu(ctx->bc, &alu);
8220 if (r)
8221 return r;
8222
8223 r = do_lds_fetch_values(ctx, temp_reg,
8224 ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
8225 if (r)
8226 return r;
8227 return 0;
8228 }
8229
8230 static int tgsi_load(struct r600_shader_ctx *ctx)
8231 {
8232 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8233 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8234 return tgsi_load_rat(ctx);
8235 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8236 return tgsi_load_gds(ctx);
8237 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8238 return tgsi_load_buffer(ctx);
8239 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8240 return tgsi_load_lds(ctx);
8241 return 0;
8242 }
8243
8244 static int tgsi_store_buffer_rat(struct r600_shader_ctx *ctx)
8245 {
8246 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8247 struct r600_bytecode_cf *cf;
8248 int r, i;
8249 unsigned rat_index_mode;
8250 int lasti;
8251 int temp_reg = r600_get_temp(ctx), treg2 = r600_get_temp(ctx);
8252
8253 r = load_buffer_coord(ctx, 0, treg2);
8254 if (r)
8255 return r;
8256
8257 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8258 if (rat_index_mode)
8259 egcm_load_index_reg(ctx->bc, 1, false);
8260
8261 for (i = 0; i <= 3; i++) {
8262 struct r600_bytecode_alu alu;
8263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8264 alu.op = ALU_OP1_MOV;
8265 alu.dst.sel = temp_reg;
8266 alu.dst.chan = i;
8267 alu.src[0].sel = V_SQ_ALU_SRC_0;
8268 alu.last = (i == 3);
8269 alu.dst.write = 1;
8270 r = r600_bytecode_add_alu(ctx->bc, &alu);
8271 if (r)
8272 return r;
8273 }
8274
8275 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8276 for (i = 0; i <= lasti; i++) {
8277 struct r600_bytecode_alu alu;
8278 if (!((1 << i) & inst->Dst[0].Register.WriteMask))
8279 continue;
8280
8281 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8282 temp_reg, 0,
8283 treg2, 0,
8284 V_SQ_ALU_SRC_LITERAL, i);
8285 if (r)
8286 return r;
8287
8288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8289 alu.op = ALU_OP1_MOV;
8290 alu.dst.sel = ctx->temp_reg;
8291 alu.dst.chan = 0;
8292
8293 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8294 alu.last = 1;
8295 alu.dst.write = 1;
8296 r = r600_bytecode_add_alu(ctx->bc, &alu);
8297 if (r)
8298 return r;
8299
8300 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8301 cf = ctx->bc->cf_last;
8302
8303 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index + ctx->info.file_count[TGSI_FILE_IMAGE];
8304 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8305 cf->rat.index_mode = rat_index_mode;
8306 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8307 cf->output.gpr = ctx->temp_reg;
8308 cf->output.index_gpr = temp_reg;
8309 cf->output.comp_mask = 1;
8310 cf->output.burst_count = 1;
8311 cf->vpm = 1;
8312 cf->barrier = 1;
8313 cf->output.elem_size = 0;
8314 }
8315 return 0;
8316 }
8317
8318 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
8319 {
8320 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8321 struct r600_bytecode_cf *cf;
8322 bool src_requires_loading = false;
8323 int val_gpr, idx_gpr;
8324 int r, i;
8325 unsigned rat_index_mode;
8326
8327 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8328
8329 r = load_index_src(ctx, 0, &idx_gpr);
8330 if (r)
8331 return r;
8332
8333 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
8334 src_requires_loading = true;
8335
8336 if (src_requires_loading) {
8337 struct r600_bytecode_alu alu;
8338 for (i = 0; i < 4; i++) {
8339 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8340 alu.op = ALU_OP1_MOV;
8341 alu.dst.sel = ctx->temp_reg;
8342 alu.dst.chan = i;
8343
8344 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8345 if (i == 3)
8346 alu.last = 1;
8347 alu.dst.write = 1;
8348 r = r600_bytecode_add_alu(ctx->bc, &alu);
8349 if (r)
8350 return r;
8351 }
8352 val_gpr = ctx->temp_reg;
8353 } else
8354 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
8355 if (rat_index_mode)
8356 egcm_load_index_reg(ctx->bc, 1, false);
8357
8358 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8359 cf = ctx->bc->cf_last;
8360
8361 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
8362 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8363 cf->rat.index_mode = rat_index_mode;
8364 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8365 cf->output.gpr = val_gpr;
8366 cf->output.index_gpr = idx_gpr;
8367 cf->output.comp_mask = 0xf;
8368 cf->output.burst_count = 1;
8369 cf->vpm = 1;
8370 cf->barrier = 1;
8371 cf->output.elem_size = 0;
8372 return 0;
8373 }
8374
8375 static int tgsi_store_lds(struct r600_shader_ctx *ctx)
8376 {
8377 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8378 struct r600_bytecode_alu alu;
8379 int r, i, lasti;
8380 int write_mask = inst->Dst[0].Register.WriteMask;
8381 int temp_reg = r600_get_temp(ctx);
8382
8383 /* LDS write */
8384 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8385 alu.op = ALU_OP1_MOV;
8386 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8387 alu.dst.sel = temp_reg;
8388 alu.dst.write = 1;
8389 alu.last = 1;
8390 r = r600_bytecode_add_alu(ctx->bc, &alu);
8391 if (r)
8392 return r;
8393
8394 lasti = tgsi_last_instruction(write_mask);
8395 for (i = 1; i <= lasti; i++) {
8396 if (!(write_mask & (1 << i)))
8397 continue;
8398 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8399 temp_reg, i,
8400 temp_reg, 0,
8401 V_SQ_ALU_SRC_LITERAL, 4 * i);
8402 if (r)
8403 return r;
8404 }
8405 for (i = 0; i <= lasti; i++) {
8406 if (!(write_mask & (1 << i)))
8407 continue;
8408
8409 if ((i == 0 && ((write_mask & 3) == 3)) ||
8410 (i == 2 && ((write_mask & 0xc) == 0xc))) {
8411 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8412 alu.op = LDS_OP3_LDS_WRITE_REL;
8413
8414 alu.src[0].sel = temp_reg;
8415 alu.src[0].chan = i;
8416 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8417 r600_bytecode_src(&alu.src[2], &ctx->src[1], i + 1);
8418 alu.last = 1;
8419 alu.is_lds_idx_op = true;
8420 alu.lds_idx = 1;
8421 r = r600_bytecode_add_alu(ctx->bc, &alu);
8422 if (r)
8423 return r;
8424 i += 1;
8425 continue;
8426 }
8427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8428 alu.op = LDS_OP2_LDS_WRITE;
8429
8430 alu.src[0].sel = temp_reg;
8431 alu.src[0].chan = i;
8432 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8433
8434 alu.last = 1;
8435 alu.is_lds_idx_op = true;
8436
8437 r = r600_bytecode_add_alu(ctx->bc, &alu);
8438 if (r)
8439 return r;
8440 }
8441 return 0;
8442 }
8443
8444 static int tgsi_store(struct r600_shader_ctx *ctx)
8445 {
8446 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8447 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
8448 return tgsi_store_buffer_rat(ctx);
8449 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
8450 return tgsi_store_lds(ctx);
8451 else
8452 return tgsi_store_rat(ctx);
8453 }
8454
8455 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
8456 {
8457 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8458 /* have to work out the offset into the RAT immediate return buffer */
8459 struct r600_bytecode_alu alu;
8460 struct r600_bytecode_vtx vtx;
8461 struct r600_bytecode_cf *cf;
8462 int r;
8463 int idx_gpr;
8464 unsigned format, num_format, format_comp, endian;
8465 const struct util_format_description *desc;
8466 unsigned rat_index_mode;
8467 unsigned immed_base;
8468 unsigned rat_base;
8469
8470 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8471 rat_base = ctx->shader->rat_base;
8472
8473 r = load_thread_id_gpr(ctx);
8474 if (r)
8475 return r;
8476
8477 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
8478 immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8479 rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8480
8481 r = load_buffer_coord(ctx, 1, ctx->temp_reg);
8482 if (r)
8483 return r;
8484 idx_gpr = ctx->temp_reg;
8485 } else {
8486 r = load_index_src(ctx, 1, &idx_gpr);
8487 if (r)
8488 return r;
8489 }
8490
8491 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8492
8493 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
8494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8495 alu.op = ALU_OP1_MOV;
8496 alu.dst.sel = ctx->thread_id_gpr;
8497 alu.dst.chan = 0;
8498 alu.dst.write = 1;
8499 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8500 alu.last = 1;
8501 r = r600_bytecode_add_alu(ctx->bc, &alu);
8502 if (r)
8503 return r;
8504
8505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8506 alu.op = ALU_OP1_MOV;
8507 alu.dst.sel = ctx->thread_id_gpr;
8508 if (ctx->bc->chip_class == CAYMAN)
8509 alu.dst.chan = 2;
8510 else
8511 alu.dst.chan = 3;
8512 alu.dst.write = 1;
8513 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8514 alu.last = 1;
8515 r = r600_bytecode_add_alu(ctx->bc, &alu);
8516 if (r)
8517 return r;
8518 } else {
8519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8520 alu.op = ALU_OP1_MOV;
8521 alu.dst.sel = ctx->thread_id_gpr;
8522 alu.dst.chan = 0;
8523 alu.dst.write = 1;
8524 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8525 alu.last = 1;
8526 r = r600_bytecode_add_alu(ctx->bc, &alu);
8527 if (r)
8528 return r;
8529 }
8530
8531 if (rat_index_mode)
8532 egcm_load_index_reg(ctx->bc, 1, false);
8533 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8534 cf = ctx->bc->cf_last;
8535
8536 cf->rat.id = rat_base + inst->Src[0].Register.Index;
8537 cf->rat.inst = ctx->inst_info->op;
8538 cf->rat.index_mode = rat_index_mode;
8539 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8540 cf->output.gpr = ctx->thread_id_gpr;
8541 cf->output.index_gpr = idx_gpr;
8542 cf->output.comp_mask = 0xf;
8543 cf->output.burst_count = 1;
8544 cf->vpm = 1;
8545 cf->barrier = 1;
8546 cf->mark = 1;
8547 cf->output.elem_size = 0;
8548 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8549 cf = ctx->bc->cf_last;
8550 cf->barrier = 1;
8551 cf->cf_addr = 1;
8552
8553 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8554 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
8555 desc = util_format_description(inst->Memory.Format);
8556 r600_vertex_data_type(inst->Memory.Format,
8557 &format, &num_format, &format_comp, &endian);
8558 vtx.dst_sel_x = desc->swizzle[0];
8559 } else {
8560 format = FMT_32;
8561 num_format = 1;
8562 format_comp = 0;
8563 endian = 0;
8564 vtx.dst_sel_x = 0;
8565 }
8566 vtx.op = FETCH_OP_VFETCH;
8567 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8568 vtx.buffer_index_mode = rat_index_mode;
8569 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8570 vtx.src_gpr = ctx->thread_id_gpr;
8571 vtx.src_sel_x = 1;
8572 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8573 vtx.dst_sel_y = 7;
8574 vtx.dst_sel_z = 7;
8575 vtx.dst_sel_w = 7;
8576 vtx.use_const_fields = 0;
8577 vtx.srf_mode_all = 1;
8578 vtx.data_format = format;
8579 vtx.num_format_all = num_format;
8580 vtx.format_comp_all = format_comp;
8581 vtx.endian = endian;
8582 vtx.offset = 0;
8583 vtx.mega_fetch_count = 0xf;
8584 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8585 if (r)
8586 return r;
8587 cf = ctx->bc->cf_last;
8588 cf->vpm = 1;
8589 cf->barrier = 1;
8590 return 0;
8591 }
8592
8593 static int get_gds_op(int opcode)
8594 {
8595 switch (opcode) {
8596 case TGSI_OPCODE_ATOMUADD:
8597 return FETCH_OP_GDS_ADD_RET;
8598 case TGSI_OPCODE_ATOMAND:
8599 return FETCH_OP_GDS_AND_RET;
8600 case TGSI_OPCODE_ATOMOR:
8601 return FETCH_OP_GDS_OR_RET;
8602 case TGSI_OPCODE_ATOMXOR:
8603 return FETCH_OP_GDS_XOR_RET;
8604 case TGSI_OPCODE_ATOMUMIN:
8605 return FETCH_OP_GDS_MIN_UINT_RET;
8606 case TGSI_OPCODE_ATOMUMAX:
8607 return FETCH_OP_GDS_MAX_UINT_RET;
8608 case TGSI_OPCODE_ATOMXCHG:
8609 return FETCH_OP_GDS_XCHG_RET;
8610 case TGSI_OPCODE_ATOMCAS:
8611 return FETCH_OP_GDS_CMP_XCHG_RET;
8612 default:
8613 return -1;
8614 }
8615 }
8616
8617 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
8618 {
8619 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8620 struct r600_bytecode_gds gds;
8621 struct r600_bytecode_alu alu;
8622 int gds_op = get_gds_op(inst->Instruction.Opcode);
8623 int r;
8624 int uav_id = 0;
8625 int uav_index_mode = 0;
8626 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8627
8628 if (gds_op == -1) {
8629 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
8630 return -1;
8631 }
8632
8633 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8634 if (r)
8635 return r;
8636
8637 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
8638 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
8639 int abs_value = abs(value);
8640 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
8641 gds_op = FETCH_OP_GDS_SUB_RET;
8642 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8643 alu.op = ALU_OP1_MOV;
8644 alu.dst.sel = ctx->temp_reg;
8645 alu.dst.chan = is_cm ? 1 : 0;
8646 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8647 alu.src[0].value = abs_value;
8648 alu.last = 1;
8649 alu.dst.write = 1;
8650 r = r600_bytecode_add_alu(ctx->bc, &alu);
8651 if (r)
8652 return r;
8653 } else {
8654 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8655 alu.op = ALU_OP1_MOV;
8656 alu.dst.sel = ctx->temp_reg;
8657 alu.dst.chan = is_cm ? 1 : 0;
8658 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8659 alu.last = 1;
8660 alu.dst.write = 1;
8661 r = r600_bytecode_add_alu(ctx->bc, &alu);
8662 if (r)
8663 return r;
8664 }
8665
8666
8667 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8668 gds.op = gds_op;
8669 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8670 gds.uav_id = is_cm ? 0 : uav_id;
8671 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8672 gds.src_gpr = ctx->temp_reg;
8673 gds.src_gpr2 = 0;
8674 gds.src_sel_x = is_cm ? 0 : 4;
8675 gds.src_sel_y = is_cm ? 1 : 0;
8676 gds.src_sel_z = 7;
8677 gds.dst_sel_x = 0;
8678 gds.dst_sel_y = 7;
8679 gds.dst_sel_z = 7;
8680 gds.dst_sel_w = 7;
8681 gds.alloc_consume = !is_cm;
8682
8683 r = r600_bytecode_add_gds(ctx->bc, &gds);
8684 if (r)
8685 return r;
8686 ctx->bc->cf_last->vpm = 1;
8687 return 0;
8688 }
8689
8690 static int get_lds_op(int opcode)
8691 {
8692 switch (opcode) {
8693 case TGSI_OPCODE_ATOMUADD:
8694 return LDS_OP2_LDS_ADD_RET;
8695 case TGSI_OPCODE_ATOMAND:
8696 return LDS_OP2_LDS_AND_RET;
8697 case TGSI_OPCODE_ATOMOR:
8698 return LDS_OP2_LDS_OR_RET;
8699 case TGSI_OPCODE_ATOMXOR:
8700 return LDS_OP2_LDS_XOR_RET;
8701 case TGSI_OPCODE_ATOMUMIN:
8702 return LDS_OP2_LDS_MIN_UINT_RET;
8703 case TGSI_OPCODE_ATOMUMAX:
8704 return LDS_OP2_LDS_MAX_UINT_RET;
8705 case TGSI_OPCODE_ATOMIMIN:
8706 return LDS_OP2_LDS_MIN_INT_RET;
8707 case TGSI_OPCODE_ATOMIMAX:
8708 return LDS_OP2_LDS_MAX_INT_RET;
8709 case TGSI_OPCODE_ATOMXCHG:
8710 return LDS_OP2_LDS_XCHG_RET;
8711 case TGSI_OPCODE_ATOMCAS:
8712 return LDS_OP3_LDS_CMP_XCHG_RET;
8713 default:
8714 return -1;
8715 }
8716 }
8717
8718 static int tgsi_atomic_op_lds(struct r600_shader_ctx *ctx)
8719 {
8720 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8721 int lds_op = get_lds_op(inst->Instruction.Opcode);
8722 int r;
8723
8724 struct r600_bytecode_alu alu;
8725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8726 alu.op = lds_op;
8727 alu.is_lds_idx_op = true;
8728 alu.last = 1;
8729 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8730 r600_bytecode_src(&alu.src[1], &ctx->src[2], 0);
8731 if (lds_op == LDS_OP3_LDS_CMP_XCHG_RET)
8732 r600_bytecode_src(&alu.src[2], &ctx->src[3], 0);
8733 else
8734 alu.src[2].sel = V_SQ_ALU_SRC_0;
8735 r = r600_bytecode_add_alu(ctx->bc, &alu);
8736 if (r)
8737 return r;
8738
8739 /* then read from LDS_OQ_A_POP */
8740 memset(&alu, 0, sizeof(alu));
8741
8742 alu.op = ALU_OP1_MOV;
8743 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
8744 alu.src[0].chan = 0;
8745 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
8746 alu.dst.write = 1;
8747 alu.last = 1;
8748 r = r600_bytecode_add_alu(ctx->bc, &alu);
8749 if (r)
8750 return r;
8751
8752 return 0;
8753 }
8754
8755 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
8756 {
8757 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8758 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8759 return tgsi_atomic_op_rat(ctx);
8760 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8761 return tgsi_atomic_op_gds(ctx);
8762 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8763 return tgsi_atomic_op_rat(ctx);
8764 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8765 return tgsi_atomic_op_lds(ctx);
8766 return 0;
8767 }
8768
8769 static int tgsi_resq(struct r600_shader_ctx *ctx)
8770 {
8771 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8772 unsigned sampler_index_mode;
8773 struct r600_bytecode_tex tex;
8774 int r;
8775 boolean has_txq_cube_array_z = false;
8776
8777 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
8778 (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
8779 ctx->shader->uses_tex_buffers = true;
8780 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset);
8781 }
8782
8783 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
8784 inst->Dst[0].Register.WriteMask & 4) {
8785 ctx->shader->has_txq_cube_array_z_comp = true;
8786 has_txq_cube_array_z = true;
8787 }
8788
8789 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8790 if (sampler_index_mode)
8791 egcm_load_index_reg(ctx->bc, 1, false);
8792
8793
8794 /* does this shader want a num layers from TXQ for a cube array? */
8795 if (has_txq_cube_array_z) {
8796 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
8797 struct r600_bytecode_alu alu;
8798
8799 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8800 alu.op = ALU_OP1_MOV;
8801
8802 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8803 /* channel 1 or 3 of each word */
8804 alu.src[0].sel += (id / 2);
8805 alu.src[0].chan = ((id % 2) * 2) + 1;
8806 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8807 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8808 alu.last = 1;
8809 r = r600_bytecode_add_alu(ctx->bc, &alu);
8810 if (r)
8811 return r;
8812 /* disable writemask from texture instruction */
8813 inst->Dst[0].Register.WriteMask &= ~4;
8814 }
8815 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8816 tex.op = ctx->inst_info->op;
8817 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
8818 tex.sampler_index_mode = sampler_index_mode;
8819 tex.resource_id = tex.sampler_id;
8820 tex.resource_index_mode = sampler_index_mode;
8821 tex.src_sel_x = 4;
8822 tex.src_sel_y = 4;
8823 tex.src_sel_z = 4;
8824 tex.src_sel_w = 4;
8825 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8826 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8827 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8828 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8829 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8830 r = r600_bytecode_add_tex(ctx->bc, &tex);
8831 if (r)
8832 return r;
8833
8834 return 0;
8835 }
8836
8837 static int tgsi_lrp(struct r600_shader_ctx *ctx)
8838 {
8839 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8840 struct r600_bytecode_alu alu;
8841 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8842 unsigned i, temp_regs[2];
8843 int r;
8844
8845 /* optimize if it's just an equal balance */
8846 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
8847 for (i = 0; i < lasti + 1; i++) {
8848 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8849 continue;
8850
8851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8852 alu.op = ALU_OP2_ADD;
8853 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8854 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8855 alu.omod = 3;
8856 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8857 alu.dst.chan = i;
8858 if (i == lasti) {
8859 alu.last = 1;
8860 }
8861 r = r600_bytecode_add_alu(ctx->bc, &alu);
8862 if (r)
8863 return r;
8864 }
8865 return 0;
8866 }
8867
8868 /* 1 - src0 */
8869 for (i = 0; i < lasti + 1; i++) {
8870 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8871 continue;
8872
8873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8874 alu.op = ALU_OP2_ADD;
8875 alu.src[0].sel = V_SQ_ALU_SRC_1;
8876 alu.src[0].chan = 0;
8877 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
8878 r600_bytecode_src_toggle_neg(&alu.src[1]);
8879 alu.dst.sel = ctx->temp_reg;
8880 alu.dst.chan = i;
8881 if (i == lasti) {
8882 alu.last = 1;
8883 }
8884 alu.dst.write = 1;
8885 r = r600_bytecode_add_alu(ctx->bc, &alu);
8886 if (r)
8887 return r;
8888 }
8889
8890 /* (1 - src0) * src2 */
8891 for (i = 0; i < lasti + 1; i++) {
8892 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8893 continue;
8894
8895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8896 alu.op = ALU_OP2_MUL;
8897 alu.src[0].sel = ctx->temp_reg;
8898 alu.src[0].chan = i;
8899 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8900 alu.dst.sel = ctx->temp_reg;
8901 alu.dst.chan = i;
8902 if (i == lasti) {
8903 alu.last = 1;
8904 }
8905 alu.dst.write = 1;
8906 r = r600_bytecode_add_alu(ctx->bc, &alu);
8907 if (r)
8908 return r;
8909 }
8910
8911 /* src0 * src1 + (1 - src0) * src2 */
8912 if (ctx->src[0].abs)
8913 temp_regs[0] = r600_get_temp(ctx);
8914 else
8915 temp_regs[0] = 0;
8916 if (ctx->src[1].abs)
8917 temp_regs[1] = r600_get_temp(ctx);
8918 else
8919 temp_regs[1] = 0;
8920
8921 for (i = 0; i < lasti + 1; i++) {
8922 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8923 continue;
8924
8925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8926 alu.op = ALU_OP3_MULADD;
8927 alu.is_op3 = 1;
8928 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8929 if (r)
8930 return r;
8931 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
8932 if (r)
8933 return r;
8934 alu.src[2].sel = ctx->temp_reg;
8935 alu.src[2].chan = i;
8936
8937 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8938 alu.dst.chan = i;
8939 if (i == lasti) {
8940 alu.last = 1;
8941 }
8942 r = r600_bytecode_add_alu(ctx->bc, &alu);
8943 if (r)
8944 return r;
8945 }
8946 return 0;
8947 }
8948
8949 static int tgsi_cmp(struct r600_shader_ctx *ctx)
8950 {
8951 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8952 struct r600_bytecode_alu alu;
8953 int i, r, j;
8954 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8955 int temp_regs[3];
8956 unsigned op;
8957
8958 if (ctx->src[0].abs && ctx->src[0].neg) {
8959 op = ALU_OP3_CNDE;
8960 ctx->src[0].abs = 0;
8961 ctx->src[0].neg = 0;
8962 } else {
8963 op = ALU_OP3_CNDGE;
8964 }
8965
8966 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
8967 temp_regs[j] = 0;
8968 if (ctx->src[j].abs)
8969 temp_regs[j] = r600_get_temp(ctx);
8970 }
8971
8972 for (i = 0; i < lasti + 1; i++) {
8973 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8974 continue;
8975
8976 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8977 alu.op = op;
8978 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8979 if (r)
8980 return r;
8981 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
8982 if (r)
8983 return r;
8984 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
8985 if (r)
8986 return r;
8987 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8988 alu.dst.chan = i;
8989 alu.dst.write = 1;
8990 alu.is_op3 = 1;
8991 if (i == lasti)
8992 alu.last = 1;
8993 r = r600_bytecode_add_alu(ctx->bc, &alu);
8994 if (r)
8995 return r;
8996 }
8997 return 0;
8998 }
8999
9000 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
9001 {
9002 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9003 struct r600_bytecode_alu alu;
9004 int i, r;
9005 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9006
9007 for (i = 0; i < lasti + 1; i++) {
9008 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9009 continue;
9010
9011 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9012 alu.op = ALU_OP3_CNDE_INT;
9013 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9014 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9015 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
9016 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9017 alu.dst.chan = i;
9018 alu.dst.write = 1;
9019 alu.is_op3 = 1;
9020 if (i == lasti)
9021 alu.last = 1;
9022 r = r600_bytecode_add_alu(ctx->bc, &alu);
9023 if (r)
9024 return r;
9025 }
9026 return 0;
9027 }
9028
9029 static int tgsi_exp(struct r600_shader_ctx *ctx)
9030 {
9031 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9032 struct r600_bytecode_alu alu;
9033 int r;
9034 unsigned i;
9035
9036 /* result.x = 2^floor(src); */
9037 if (inst->Dst[0].Register.WriteMask & 1) {
9038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9039
9040 alu.op = ALU_OP1_FLOOR;
9041 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9042
9043 alu.dst.sel = ctx->temp_reg;
9044 alu.dst.chan = 0;
9045 alu.dst.write = 1;
9046 alu.last = 1;
9047 r = r600_bytecode_add_alu(ctx->bc, &alu);
9048 if (r)
9049 return r;
9050
9051 if (ctx->bc->chip_class == CAYMAN) {
9052 for (i = 0; i < 3; i++) {
9053 alu.op = ALU_OP1_EXP_IEEE;
9054 alu.src[0].sel = ctx->temp_reg;
9055 alu.src[0].chan = 0;
9056
9057 alu.dst.sel = ctx->temp_reg;
9058 alu.dst.chan = i;
9059 alu.dst.write = i == 0;
9060 alu.last = i == 2;
9061 r = r600_bytecode_add_alu(ctx->bc, &alu);
9062 if (r)
9063 return r;
9064 }
9065 } else {
9066 alu.op = ALU_OP1_EXP_IEEE;
9067 alu.src[0].sel = ctx->temp_reg;
9068 alu.src[0].chan = 0;
9069
9070 alu.dst.sel = ctx->temp_reg;
9071 alu.dst.chan = 0;
9072 alu.dst.write = 1;
9073 alu.last = 1;
9074 r = r600_bytecode_add_alu(ctx->bc, &alu);
9075 if (r)
9076 return r;
9077 }
9078 }
9079
9080 /* result.y = tmp - floor(tmp); */
9081 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9083
9084 alu.op = ALU_OP1_FRACT;
9085 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9086
9087 alu.dst.sel = ctx->temp_reg;
9088 #if 0
9089 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9090 if (r)
9091 return r;
9092 #endif
9093 alu.dst.write = 1;
9094 alu.dst.chan = 1;
9095
9096 alu.last = 1;
9097
9098 r = r600_bytecode_add_alu(ctx->bc, &alu);
9099 if (r)
9100 return r;
9101 }
9102
9103 /* result.z = RoughApprox2ToX(tmp);*/
9104 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
9105 if (ctx->bc->chip_class == CAYMAN) {
9106 for (i = 0; i < 3; i++) {
9107 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9108 alu.op = ALU_OP1_EXP_IEEE;
9109 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9110
9111 alu.dst.sel = ctx->temp_reg;
9112 alu.dst.chan = i;
9113 if (i == 2) {
9114 alu.dst.write = 1;
9115 alu.last = 1;
9116 }
9117
9118 r = r600_bytecode_add_alu(ctx->bc, &alu);
9119 if (r)
9120 return r;
9121 }
9122 } else {
9123 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9124 alu.op = ALU_OP1_EXP_IEEE;
9125 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9126
9127 alu.dst.sel = ctx->temp_reg;
9128 alu.dst.write = 1;
9129 alu.dst.chan = 2;
9130
9131 alu.last = 1;
9132
9133 r = r600_bytecode_add_alu(ctx->bc, &alu);
9134 if (r)
9135 return r;
9136 }
9137 }
9138
9139 /* result.w = 1.0;*/
9140 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
9141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9142
9143 alu.op = ALU_OP1_MOV;
9144 alu.src[0].sel = V_SQ_ALU_SRC_1;
9145 alu.src[0].chan = 0;
9146
9147 alu.dst.sel = ctx->temp_reg;
9148 alu.dst.chan = 3;
9149 alu.dst.write = 1;
9150 alu.last = 1;
9151 r = r600_bytecode_add_alu(ctx->bc, &alu);
9152 if (r)
9153 return r;
9154 }
9155 return tgsi_helper_copy(ctx, inst);
9156 }
9157
9158 static int tgsi_log(struct r600_shader_ctx *ctx)
9159 {
9160 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9161 struct r600_bytecode_alu alu;
9162 int r;
9163 unsigned i;
9164
9165 /* result.x = floor(log2(|src|)); */
9166 if (inst->Dst[0].Register.WriteMask & 1) {
9167 if (ctx->bc->chip_class == CAYMAN) {
9168 for (i = 0; i < 3; i++) {
9169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9170
9171 alu.op = ALU_OP1_LOG_IEEE;
9172 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9173 r600_bytecode_src_set_abs(&alu.src[0]);
9174
9175 alu.dst.sel = ctx->temp_reg;
9176 alu.dst.chan = i;
9177 if (i == 0)
9178 alu.dst.write = 1;
9179 if (i == 2)
9180 alu.last = 1;
9181 r = r600_bytecode_add_alu(ctx->bc, &alu);
9182 if (r)
9183 return r;
9184 }
9185
9186 } else {
9187 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9188
9189 alu.op = ALU_OP1_LOG_IEEE;
9190 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9191 r600_bytecode_src_set_abs(&alu.src[0]);
9192
9193 alu.dst.sel = ctx->temp_reg;
9194 alu.dst.chan = 0;
9195 alu.dst.write = 1;
9196 alu.last = 1;
9197 r = r600_bytecode_add_alu(ctx->bc, &alu);
9198 if (r)
9199 return r;
9200 }
9201
9202 alu.op = ALU_OP1_FLOOR;
9203 alu.src[0].sel = ctx->temp_reg;
9204 alu.src[0].chan = 0;
9205
9206 alu.dst.sel = ctx->temp_reg;
9207 alu.dst.chan = 0;
9208 alu.dst.write = 1;
9209 alu.last = 1;
9210
9211 r = r600_bytecode_add_alu(ctx->bc, &alu);
9212 if (r)
9213 return r;
9214 }
9215
9216 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
9217 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9218
9219 if (ctx->bc->chip_class == CAYMAN) {
9220 for (i = 0; i < 3; i++) {
9221 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9222
9223 alu.op = ALU_OP1_LOG_IEEE;
9224 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9225 r600_bytecode_src_set_abs(&alu.src[0]);
9226
9227 alu.dst.sel = ctx->temp_reg;
9228 alu.dst.chan = i;
9229 if (i == 1)
9230 alu.dst.write = 1;
9231 if (i == 2)
9232 alu.last = 1;
9233
9234 r = r600_bytecode_add_alu(ctx->bc, &alu);
9235 if (r)
9236 return r;
9237 }
9238 } else {
9239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9240
9241 alu.op = ALU_OP1_LOG_IEEE;
9242 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9243 r600_bytecode_src_set_abs(&alu.src[0]);
9244
9245 alu.dst.sel = ctx->temp_reg;
9246 alu.dst.chan = 1;
9247 alu.dst.write = 1;
9248 alu.last = 1;
9249
9250 r = r600_bytecode_add_alu(ctx->bc, &alu);
9251 if (r)
9252 return r;
9253 }
9254
9255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9256
9257 alu.op = ALU_OP1_FLOOR;
9258 alu.src[0].sel = ctx->temp_reg;
9259 alu.src[0].chan = 1;
9260
9261 alu.dst.sel = ctx->temp_reg;
9262 alu.dst.chan = 1;
9263 alu.dst.write = 1;
9264 alu.last = 1;
9265
9266 r = r600_bytecode_add_alu(ctx->bc, &alu);
9267 if (r)
9268 return r;
9269
9270 if (ctx->bc->chip_class == CAYMAN) {
9271 for (i = 0; i < 3; i++) {
9272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9273 alu.op = ALU_OP1_EXP_IEEE;
9274 alu.src[0].sel = ctx->temp_reg;
9275 alu.src[0].chan = 1;
9276
9277 alu.dst.sel = ctx->temp_reg;
9278 alu.dst.chan = i;
9279 if (i == 1)
9280 alu.dst.write = 1;
9281 if (i == 2)
9282 alu.last = 1;
9283
9284 r = r600_bytecode_add_alu(ctx->bc, &alu);
9285 if (r)
9286 return r;
9287 }
9288 } else {
9289 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9290 alu.op = ALU_OP1_EXP_IEEE;
9291 alu.src[0].sel = ctx->temp_reg;
9292 alu.src[0].chan = 1;
9293
9294 alu.dst.sel = ctx->temp_reg;
9295 alu.dst.chan = 1;
9296 alu.dst.write = 1;
9297 alu.last = 1;
9298
9299 r = r600_bytecode_add_alu(ctx->bc, &alu);
9300 if (r)
9301 return r;
9302 }
9303
9304 if (ctx->bc->chip_class == CAYMAN) {
9305 for (i = 0; i < 3; i++) {
9306 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9307 alu.op = ALU_OP1_RECIP_IEEE;
9308 alu.src[0].sel = ctx->temp_reg;
9309 alu.src[0].chan = 1;
9310
9311 alu.dst.sel = ctx->temp_reg;
9312 alu.dst.chan = i;
9313 if (i == 1)
9314 alu.dst.write = 1;
9315 if (i == 2)
9316 alu.last = 1;
9317
9318 r = r600_bytecode_add_alu(ctx->bc, &alu);
9319 if (r)
9320 return r;
9321 }
9322 } else {
9323 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9324 alu.op = ALU_OP1_RECIP_IEEE;
9325 alu.src[0].sel = ctx->temp_reg;
9326 alu.src[0].chan = 1;
9327
9328 alu.dst.sel = ctx->temp_reg;
9329 alu.dst.chan = 1;
9330 alu.dst.write = 1;
9331 alu.last = 1;
9332
9333 r = r600_bytecode_add_alu(ctx->bc, &alu);
9334 if (r)
9335 return r;
9336 }
9337
9338 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9339
9340 alu.op = ALU_OP2_MUL;
9341
9342 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9343 r600_bytecode_src_set_abs(&alu.src[0]);
9344
9345 alu.src[1].sel = ctx->temp_reg;
9346 alu.src[1].chan = 1;
9347
9348 alu.dst.sel = ctx->temp_reg;
9349 alu.dst.chan = 1;
9350 alu.dst.write = 1;
9351 alu.last = 1;
9352
9353 r = r600_bytecode_add_alu(ctx->bc, &alu);
9354 if (r)
9355 return r;
9356 }
9357
9358 /* result.z = log2(|src|);*/
9359 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
9360 if (ctx->bc->chip_class == CAYMAN) {
9361 for (i = 0; i < 3; i++) {
9362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9363
9364 alu.op = ALU_OP1_LOG_IEEE;
9365 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9366 r600_bytecode_src_set_abs(&alu.src[0]);
9367
9368 alu.dst.sel = ctx->temp_reg;
9369 if (i == 2)
9370 alu.dst.write = 1;
9371 alu.dst.chan = i;
9372 if (i == 2)
9373 alu.last = 1;
9374
9375 r = r600_bytecode_add_alu(ctx->bc, &alu);
9376 if (r)
9377 return r;
9378 }
9379 } else {
9380 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9381
9382 alu.op = ALU_OP1_LOG_IEEE;
9383 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9384 r600_bytecode_src_set_abs(&alu.src[0]);
9385
9386 alu.dst.sel = ctx->temp_reg;
9387 alu.dst.write = 1;
9388 alu.dst.chan = 2;
9389 alu.last = 1;
9390
9391 r = r600_bytecode_add_alu(ctx->bc, &alu);
9392 if (r)
9393 return r;
9394 }
9395 }
9396
9397 /* result.w = 1.0; */
9398 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
9399 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9400
9401 alu.op = ALU_OP1_MOV;
9402 alu.src[0].sel = V_SQ_ALU_SRC_1;
9403 alu.src[0].chan = 0;
9404
9405 alu.dst.sel = ctx->temp_reg;
9406 alu.dst.chan = 3;
9407 alu.dst.write = 1;
9408 alu.last = 1;
9409
9410 r = r600_bytecode_add_alu(ctx->bc, &alu);
9411 if (r)
9412 return r;
9413 }
9414
9415 return tgsi_helper_copy(ctx, inst);
9416 }
9417
9418 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
9419 {
9420 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9421 struct r600_bytecode_alu alu;
9422 int r;
9423 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9424 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
9425
9426 assert(inst->Dst[0].Register.Index < 3);
9427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9428
9429 switch (inst->Instruction.Opcode) {
9430 case TGSI_OPCODE_ARL:
9431 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
9432 break;
9433 case TGSI_OPCODE_ARR:
9434 alu.op = ALU_OP1_FLT_TO_INT;
9435 break;
9436 case TGSI_OPCODE_UARL:
9437 alu.op = ALU_OP1_MOV;
9438 break;
9439 default:
9440 assert(0);
9441 return -1;
9442 }
9443
9444 for (i = 0; i <= lasti; ++i) {
9445 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9446 continue;
9447 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9448 alu.last = i == lasti;
9449 alu.dst.sel = reg;
9450 alu.dst.chan = i;
9451 alu.dst.write = 1;
9452 r = r600_bytecode_add_alu(ctx->bc, &alu);
9453 if (r)
9454 return r;
9455 }
9456
9457 if (inst->Dst[0].Register.Index > 0)
9458 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
9459 else
9460 ctx->bc->ar_loaded = 0;
9461
9462 return 0;
9463 }
9464 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
9465 {
9466 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9467 struct r600_bytecode_alu alu;
9468 int r;
9469 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9470
9471 switch (inst->Instruction.Opcode) {
9472 case TGSI_OPCODE_ARL:
9473 memset(&alu, 0, sizeof(alu));
9474 alu.op = ALU_OP1_FLOOR;
9475 alu.dst.sel = ctx->bc->ar_reg;
9476 alu.dst.write = 1;
9477 for (i = 0; i <= lasti; ++i) {
9478 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9479 alu.dst.chan = i;
9480 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9481 alu.last = i == lasti;
9482 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9483 return r;
9484 }
9485 }
9486
9487 memset(&alu, 0, sizeof(alu));
9488 alu.op = ALU_OP1_FLT_TO_INT;
9489 alu.src[0].sel = ctx->bc->ar_reg;
9490 alu.dst.sel = ctx->bc->ar_reg;
9491 alu.dst.write = 1;
9492 /* FLT_TO_INT is trans-only on r600/r700 */
9493 alu.last = TRUE;
9494 for (i = 0; i <= lasti; ++i) {
9495 alu.dst.chan = i;
9496 alu.src[0].chan = i;
9497 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9498 return r;
9499 }
9500 break;
9501 case TGSI_OPCODE_ARR:
9502 memset(&alu, 0, sizeof(alu));
9503 alu.op = ALU_OP1_FLT_TO_INT;
9504 alu.dst.sel = ctx->bc->ar_reg;
9505 alu.dst.write = 1;
9506 /* FLT_TO_INT is trans-only on r600/r700 */
9507 alu.last = TRUE;
9508 for (i = 0; i <= lasti; ++i) {
9509 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9510 alu.dst.chan = i;
9511 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9512 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9513 return r;
9514 }
9515 }
9516 break;
9517 case TGSI_OPCODE_UARL:
9518 memset(&alu, 0, sizeof(alu));
9519 alu.op = ALU_OP1_MOV;
9520 alu.dst.sel = ctx->bc->ar_reg;
9521 alu.dst.write = 1;
9522 for (i = 0; i <= lasti; ++i) {
9523 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9524 alu.dst.chan = i;
9525 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9526 alu.last = i == lasti;
9527 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9528 return r;
9529 }
9530 }
9531 break;
9532 default:
9533 assert(0);
9534 return -1;
9535 }
9536
9537 ctx->bc->ar_loaded = 0;
9538 return 0;
9539 }
9540
9541 static int tgsi_opdst(struct r600_shader_ctx *ctx)
9542 {
9543 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9544 struct r600_bytecode_alu alu;
9545 int i, r = 0;
9546
9547 for (i = 0; i < 4; i++) {
9548 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9549
9550 alu.op = ALU_OP2_MUL;
9551 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9552
9553 if (i == 0 || i == 3) {
9554 alu.src[0].sel = V_SQ_ALU_SRC_1;
9555 } else {
9556 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9557 }
9558
9559 if (i == 0 || i == 2) {
9560 alu.src[1].sel = V_SQ_ALU_SRC_1;
9561 } else {
9562 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
9563 }
9564 if (i == 3)
9565 alu.last = 1;
9566 r = r600_bytecode_add_alu(ctx->bc, &alu);
9567 if (r)
9568 return r;
9569 }
9570 return 0;
9571 }
9572
9573 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
9574 {
9575 struct r600_bytecode_alu alu;
9576 int r;
9577
9578 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9579 alu.op = opcode;
9580 alu.execute_mask = 1;
9581 alu.update_pred = 1;
9582
9583 alu.dst.sel = ctx->temp_reg;
9584 alu.dst.write = 1;
9585 alu.dst.chan = 0;
9586
9587 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9588 alu.src[1].sel = V_SQ_ALU_SRC_0;
9589 alu.src[1].chan = 0;
9590
9591 alu.last = 1;
9592
9593 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
9594 if (r)
9595 return r;
9596 return 0;
9597 }
9598
9599 static int pops(struct r600_shader_ctx *ctx, int pops)
9600 {
9601 unsigned force_pop = ctx->bc->force_add_cf;
9602
9603 if (!force_pop) {
9604 int alu_pop = 3;
9605 if (ctx->bc->cf_last) {
9606 if (ctx->bc->cf_last->op == CF_OP_ALU)
9607 alu_pop = 0;
9608 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
9609 alu_pop = 1;
9610 }
9611 alu_pop += pops;
9612 if (alu_pop == 1) {
9613 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
9614 ctx->bc->force_add_cf = 1;
9615 } else if (alu_pop == 2) {
9616 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
9617 ctx->bc->force_add_cf = 1;
9618 } else {
9619 force_pop = 1;
9620 }
9621 }
9622
9623 if (force_pop) {
9624 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
9625 ctx->bc->cf_last->pop_count = pops;
9626 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9627 }
9628
9629 return 0;
9630 }
9631
9632 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
9633 unsigned reason)
9634 {
9635 struct r600_stack_info *stack = &ctx->bc->stack;
9636 unsigned elements;
9637 int entries;
9638
9639 unsigned entry_size = stack->entry_size;
9640
9641 elements = (stack->loop + stack->push_wqm ) * entry_size;
9642 elements += stack->push;
9643
9644 switch (ctx->bc->chip_class) {
9645 case R600:
9646 case R700:
9647 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9648 * the stack must be reserved to hold the current active/continue
9649 * masks */
9650 if (reason == FC_PUSH_VPM) {
9651 elements += 2;
9652 }
9653 break;
9654
9655 case CAYMAN:
9656 /* r9xx: any stack operation on empty stack consumes 2 additional
9657 * elements */
9658 elements += 2;
9659
9660 /* fallthrough */
9661 /* FIXME: do the two elements added above cover the cases for the
9662 * r8xx+ below? */
9663
9664 case EVERGREEN:
9665 /* r8xx+: 2 extra elements are not always required, but one extra
9666 * element must be added for each of the following cases:
9667 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9668 * stack usage.
9669 * (Currently we don't use ALU_ELSE_AFTER.)
9670 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9671 * PUSH instruction executed.
9672 *
9673 * NOTE: it seems we also need to reserve additional element in some
9674 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9675 * then STACK_SIZE should be 2 instead of 1 */
9676 if (reason == FC_PUSH_VPM) {
9677 elements += 1;
9678 }
9679 break;
9680
9681 default:
9682 assert(0);
9683 break;
9684 }
9685
9686 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9687 * for all chips, so we use 4 in the final formula, not the real entry_size
9688 * for the chip */
9689 entry_size = 4;
9690
9691 entries = (elements + (entry_size - 1)) / entry_size;
9692
9693 if (entries > stack->max_entries)
9694 stack->max_entries = entries;
9695 }
9696
9697 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
9698 {
9699 switch(reason) {
9700 case FC_PUSH_VPM:
9701 --ctx->bc->stack.push;
9702 assert(ctx->bc->stack.push >= 0);
9703 break;
9704 case FC_PUSH_WQM:
9705 --ctx->bc->stack.push_wqm;
9706 assert(ctx->bc->stack.push_wqm >= 0);
9707 break;
9708 case FC_LOOP:
9709 --ctx->bc->stack.loop;
9710 assert(ctx->bc->stack.loop >= 0);
9711 break;
9712 default:
9713 assert(0);
9714 break;
9715 }
9716 }
9717
9718 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
9719 {
9720 switch (reason) {
9721 case FC_PUSH_VPM:
9722 ++ctx->bc->stack.push;
9723 break;
9724 case FC_PUSH_WQM:
9725 ++ctx->bc->stack.push_wqm;
9726 case FC_LOOP:
9727 ++ctx->bc->stack.loop;
9728 break;
9729 default:
9730 assert(0);
9731 }
9732
9733 callstack_update_max_depth(ctx, reason);
9734 }
9735
9736 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
9737 {
9738 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
9739
9740 sp->mid = realloc((void *)sp->mid,
9741 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
9742 sp->mid[sp->num_mid] = ctx->bc->cf_last;
9743 sp->num_mid++;
9744 }
9745
9746 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
9747 {
9748 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
9749 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
9750 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
9751 ctx->bc->fc_sp++;
9752 }
9753
9754 static void fc_poplevel(struct r600_shader_ctx *ctx)
9755 {
9756 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
9757 free(sp->mid);
9758 sp->mid = NULL;
9759 sp->num_mid = 0;
9760 sp->start = NULL;
9761 sp->type = 0;
9762 ctx->bc->fc_sp--;
9763 }
9764
9765 #if 0
9766 static int emit_return(struct r600_shader_ctx *ctx)
9767 {
9768 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
9769 return 0;
9770 }
9771
9772 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
9773 {
9774
9775 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
9776 ctx->bc->cf_last->pop_count = pops;
9777 /* XXX work out offset */
9778 return 0;
9779 }
9780
9781 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
9782 {
9783 return 0;
9784 }
9785
9786 static void emit_testflag(struct r600_shader_ctx *ctx)
9787 {
9788
9789 }
9790
9791 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
9792 {
9793 emit_testflag(ctx);
9794 emit_jump_to_offset(ctx, 1, 4);
9795 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
9796 pops(ctx, ifidx + 1);
9797 emit_return(ctx);
9798 }
9799
9800 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
9801 {
9802 emit_testflag(ctx);
9803
9804 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9805 ctx->bc->cf_last->pop_count = 1;
9806
9807 fc_set_mid(ctx, fc_sp);
9808
9809 pops(ctx, 1);
9810 }
9811 #endif
9812
9813 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
9814 {
9815 int alu_type = CF_OP_ALU_PUSH_BEFORE;
9816
9817 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9818 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9819 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9820 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9821 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
9822 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
9823 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9824 alu_type = CF_OP_ALU;
9825 }
9826
9827 emit_logic_pred(ctx, opcode, alu_type);
9828
9829 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
9830
9831 fc_pushlevel(ctx, FC_IF);
9832
9833 callstack_push(ctx, FC_PUSH_VPM);
9834 return 0;
9835 }
9836
9837 static int tgsi_if(struct r600_shader_ctx *ctx)
9838 {
9839 return emit_if(ctx, ALU_OP2_PRED_SETNE);
9840 }
9841
9842 static int tgsi_uif(struct r600_shader_ctx *ctx)
9843 {
9844 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
9845 }
9846
9847 static int tgsi_else(struct r600_shader_ctx *ctx)
9848 {
9849 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
9850 ctx->bc->cf_last->pop_count = 1;
9851
9852 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
9853 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
9854 return 0;
9855 }
9856
9857 static int tgsi_endif(struct r600_shader_ctx *ctx)
9858 {
9859 pops(ctx, 1);
9860 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
9861 R600_ERR("if/endif unbalanced in shader\n");
9862 return -1;
9863 }
9864
9865 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
9866 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9867 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
9868 } else {
9869 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
9870 }
9871 fc_poplevel(ctx);
9872
9873 callstack_pop(ctx, FC_PUSH_VPM);
9874 return 0;
9875 }
9876
9877 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
9878 {
9879 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9880 * limited to 4096 iterations, like the other LOOP_* instructions. */
9881 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
9882
9883 fc_pushlevel(ctx, FC_LOOP);
9884
9885 /* check stack depth */
9886 callstack_push(ctx, FC_LOOP);
9887 return 0;
9888 }
9889
9890 static int tgsi_endloop(struct r600_shader_ctx *ctx)
9891 {
9892 int i;
9893
9894 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
9895
9896 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
9897 R600_ERR("loop/endloop in shader code are not paired.\n");
9898 return -EINVAL;
9899 }
9900
9901 /* fixup loop pointers - from r600isa
9902 LOOP END points to CF after LOOP START,
9903 LOOP START point to CF after LOOP END
9904 BRK/CONT point to LOOP END CF
9905 */
9906 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
9907
9908 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9909
9910 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
9911 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
9912 }
9913 /* XXX add LOOPRET support */
9914 fc_poplevel(ctx);
9915 callstack_pop(ctx, FC_LOOP);
9916 return 0;
9917 }
9918
9919 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
9920 {
9921 unsigned int fscp;
9922
9923 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
9924 {
9925 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
9926 break;
9927 }
9928
9929 if (fscp == 0) {
9930 R600_ERR("Break not inside loop/endloop pair\n");
9931 return -EINVAL;
9932 }
9933
9934 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9935
9936 fc_set_mid(ctx, fscp - 1);
9937
9938 return 0;
9939 }
9940
9941 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
9942 {
9943 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9944 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
9945 int r;
9946
9947 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9948 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
9949
9950 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9951 if (!r) {
9952 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
9953 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9954 return emit_inc_ring_offset(ctx, stream, TRUE);
9955 }
9956 return r;
9957 }
9958
9959 static int tgsi_umad(struct r600_shader_ctx *ctx)
9960 {
9961 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9962 struct r600_bytecode_alu alu;
9963 int i, j, k, r;
9964 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9965
9966 /* src0 * src1 */
9967 for (i = 0; i < lasti + 1; i++) {
9968 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9969 continue;
9970
9971 if (ctx->bc->chip_class == CAYMAN) {
9972 for (j = 0 ; j < 4; j++) {
9973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9974
9975 alu.op = ALU_OP2_MULLO_UINT;
9976 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
9977 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
9978 }
9979 alu.dst.chan = j;
9980 alu.dst.sel = ctx->temp_reg;
9981 alu.dst.write = (j == i);
9982 if (j == 3)
9983 alu.last = 1;
9984 r = r600_bytecode_add_alu(ctx->bc, &alu);
9985 if (r)
9986 return r;
9987 }
9988 } else {
9989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9990
9991 alu.dst.chan = i;
9992 alu.dst.sel = ctx->temp_reg;
9993 alu.dst.write = 1;
9994
9995 alu.op = ALU_OP2_MULLO_UINT;
9996 for (j = 0; j < 2; j++) {
9997 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
9998 }
9999
10000 alu.last = 1;
10001 r = r600_bytecode_add_alu(ctx->bc, &alu);
10002 if (r)
10003 return r;
10004 }
10005 }
10006
10007
10008 for (i = 0; i < lasti + 1; i++) {
10009 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10010 continue;
10011
10012 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10013 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10014
10015 alu.op = ALU_OP2_ADD_INT;
10016
10017 alu.src[0].sel = ctx->temp_reg;
10018 alu.src[0].chan = i;
10019
10020 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
10021 if (i == lasti) {
10022 alu.last = 1;
10023 }
10024 r = r600_bytecode_add_alu(ctx->bc, &alu);
10025 if (r)
10026 return r;
10027 }
10028 return 0;
10029 }
10030
10031 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
10032 {
10033 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10034 struct r600_bytecode_alu alu;
10035 int r, i;
10036 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10037
10038 /* temp.xy = f32_to_f16(src) */
10039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10040 alu.op = ALU_OP1_FLT32_TO_FLT16;
10041 alu.dst.chan = 0;
10042 alu.dst.sel = ctx->temp_reg;
10043 alu.dst.write = 1;
10044 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10045 r = r600_bytecode_add_alu(ctx->bc, &alu);
10046 if (r)
10047 return r;
10048 alu.dst.chan = 1;
10049 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10050 alu.last = 1;
10051 r = r600_bytecode_add_alu(ctx->bc, &alu);
10052 if (r)
10053 return r;
10054
10055 /* dst.x = temp.y * 0x10000 + temp.x */
10056 for (i = 0; i < lasti + 1; i++) {
10057 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10058 continue;
10059
10060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10061 alu.op = ALU_OP3_MULADD_UINT24;
10062 alu.is_op3 = 1;
10063 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10064 alu.last = i == lasti;
10065 alu.src[0].sel = ctx->temp_reg;
10066 alu.src[0].chan = 1;
10067 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10068 alu.src[1].value = 0x10000;
10069 alu.src[2].sel = ctx->temp_reg;
10070 alu.src[2].chan = 0;
10071 r = r600_bytecode_add_alu(ctx->bc, &alu);
10072 if (r)
10073 return r;
10074 }
10075
10076 return 0;
10077 }
10078
10079 static int tgsi_up2h(struct r600_shader_ctx *ctx)
10080 {
10081 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10082 struct r600_bytecode_alu alu;
10083 int r, i;
10084 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10085
10086 /* temp.x = src.x */
10087 /* note: no need to mask out the high bits */
10088 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10089 alu.op = ALU_OP1_MOV;
10090 alu.dst.chan = 0;
10091 alu.dst.sel = ctx->temp_reg;
10092 alu.dst.write = 1;
10093 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10094 r = r600_bytecode_add_alu(ctx->bc, &alu);
10095 if (r)
10096 return r;
10097
10098 /* temp.y = src.x >> 16 */
10099 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10100 alu.op = ALU_OP2_LSHR_INT;
10101 alu.dst.chan = 1;
10102 alu.dst.sel = ctx->temp_reg;
10103 alu.dst.write = 1;
10104 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10105 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10106 alu.src[1].value = 16;
10107 alu.last = 1;
10108 r = r600_bytecode_add_alu(ctx->bc, &alu);
10109 if (r)
10110 return r;
10111
10112 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
10113 for (i = 0; i < lasti + 1; i++) {
10114 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10115 continue;
10116 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10117 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10118 alu.op = ALU_OP1_FLT16_TO_FLT32;
10119 alu.src[0].sel = ctx->temp_reg;
10120 alu.src[0].chan = i % 2;
10121 alu.last = i == lasti;
10122 r = r600_bytecode_add_alu(ctx->bc, &alu);
10123 if (r)
10124 return r;
10125 }
10126
10127 return 0;
10128 }
10129
10130 static int tgsi_bfe(struct r600_shader_ctx *ctx)
10131 {
10132 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10133 struct r600_bytecode_alu alu;
10134 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10135 int r, i;
10136 int dst = -1;
10137
10138 if ((inst->Src[0].Register.File == inst->Dst[0].Register.File &&
10139 inst->Src[0].Register.Index == inst->Dst[0].Register.Index) ||
10140 (inst->Src[2].Register.File == inst->Dst[0].Register.File &&
10141 inst->Src[2].Register.Index == inst->Dst[0].Register.Index))
10142 dst = r600_get_temp(ctx);
10143
10144 r = tgsi_op3_dst(ctx, dst);
10145 if (r)
10146 return r;
10147
10148 for (i = 0; i < lasti + 1; i++) {
10149 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10150 alu.op = ALU_OP2_SETGE_INT;
10151 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
10152 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10153 alu.src[1].value = 32;
10154 alu.dst.sel = ctx->temp_reg;
10155 alu.dst.chan = i;
10156 alu.dst.write = 1;
10157 if (i == lasti)
10158 alu.last = 1;
10159 r = r600_bytecode_add_alu(ctx->bc, &alu);
10160 if (r)
10161 return r;
10162 }
10163
10164 for (i = 0; i < lasti + 1; i++) {
10165 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10166 alu.op = ALU_OP3_CNDE_INT;
10167 alu.is_op3 = 1;
10168 alu.src[0].sel = ctx->temp_reg;
10169 alu.src[0].chan = i;
10170
10171 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10172 if (dst != -1)
10173 alu.src[1].sel = dst;
10174 else
10175 alu.src[1].sel = alu.dst.sel;
10176 alu.src[1].chan = i;
10177 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
10178 alu.dst.write = 1;
10179 if (i == lasti)
10180 alu.last = 1;
10181 r = r600_bytecode_add_alu(ctx->bc, &alu);
10182 if (r)
10183 return r;
10184 }
10185
10186 return 0;
10187 }
10188
10189 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
10190 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
10191 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10192 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10193
10194 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
10195
10196 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
10197 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10198 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10199 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10200 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10201 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10202 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10203 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10204 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
10205 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10206 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10207 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10208 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10209 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10210 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10211 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
10212 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
10213 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10214 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10215 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10216 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10217 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10218 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10219 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10220 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
10221 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
10222 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
10223 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10224 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10225 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10226 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10227 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10228 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
10229 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10230 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10231 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10232 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
10233 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10234 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10235 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10236 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10237 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10238 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10239 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10240 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
10241 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10242 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10243 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10244 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10245 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10246 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10247 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
10248 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10249 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10250 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10251 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10252 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10253 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
10254 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10255 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10256 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10257 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10258 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10259 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10260 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10261 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10262 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10263 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10264 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10265 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10266 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10267 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10268 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10269 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10270 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10271 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
10272 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
10273 [81] = { ALU_OP0_NOP, tgsi_unsupported},
10274 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10275 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10276 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
10277 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10278 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10279 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
10280 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10281 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10282 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10283 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10284 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10285 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10286 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10287 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10288 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10289 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10290 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10291 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10292 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10293 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10294 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10295 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10296 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10297 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
10298 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10299 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10300 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10301 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10302 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10303 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10304 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
10305 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10306 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10307 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10308 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10309 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10310 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
10311 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
10312 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10313 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10314 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10315 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10316 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10317 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
10318 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10319 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
10320 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
10321 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10322 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10323 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10324 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10325 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10326 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10327 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
10328 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10329 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10330 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
10331 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10332 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
10333 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10334 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10335 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10336 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10337 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10338 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10339 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10340 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10341 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10342 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10343 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10344 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10345 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10346 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10347 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10348 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10349 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
10350 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10351 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10352 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10353 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
10354 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
10355 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10356 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10357 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10358 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
10359 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
10360 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
10361 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
10362 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
10363 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
10364 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
10365 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
10366 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
10367 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
10368 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
10369 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10370 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10371 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10372 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
10373 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
10374 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
10375 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
10376 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
10377 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
10378 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
10379 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
10380 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
10381 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
10382 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
10383 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
10384 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
10385 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
10386 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
10387 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10388 };
10389
10390 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
10391 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
10392 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10393 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10394 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
10395 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
10396 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10397 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10398 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10399 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10400 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10401 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10402 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10403 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10404 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10405 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10406 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10407 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10408 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10409 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
10410 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
10411 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10412 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10413 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10414 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10415 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10416 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10417 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10418 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
10419 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
10420 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
10421 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10422 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10423 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10424 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10425 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10426 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
10427 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10428 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10429 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10430 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
10431 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10432 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10433 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10434 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10435 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10436 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10437 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10438 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
10439 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10440 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10441 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10442 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10443 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10444 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10445 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
10446 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10447 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10448 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10449 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10450 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10451 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
10452 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10453 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10454 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10455 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10456 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10457 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10458 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10459 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10460 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10461 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10462 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10463 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10464 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10465 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10466 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10467 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10468 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10469 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10470 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10471 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10472 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10473 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
10474 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10475 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10476 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
10477 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10478 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10479 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10480 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10481 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10482 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10483 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10484 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10485 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10486 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10487 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10488 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10489 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10490 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10491 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10492 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10493 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10494 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
10495 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10496 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10497 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10498 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10499 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10500 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10501 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10502 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10503 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10504 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10505 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10506 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10507 /* Refer below for TGSI_OPCODE_DFMA */
10508 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
10509 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10510 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10511 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10512 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10513 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10514 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
10515 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10516 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
10517 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
10518 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10519 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10520 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10521 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10522 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10523 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10524 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
10525 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10526 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10527 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
10528 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10529 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
10530 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10531 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10532 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10533 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10534 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10535 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10536 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10537 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10538 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10539 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10540 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10541 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10542 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10543 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10544 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10545 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10546 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
10547 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10548 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10549 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10550 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
10551 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
10552 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10553 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10554 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10555 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10556 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
10557 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
10558 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
10559 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
10560 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
10561 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10562 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10563 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10564 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10565 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10566 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10567 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10568 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10569 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
10570 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
10571 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10572 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10573 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10574 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10575 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10576 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10577 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10578 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10579 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10580 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10581 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10582 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10583 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10584 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10585 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10586 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10587 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10588 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10589 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10590 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10591 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10592 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10593 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10594 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10595 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10596 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10597 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10598 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10599 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10600 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10601 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10602 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10603 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10604 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10605 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10606 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10607 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10608 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10609 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10610 };
10611
10612 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
10613 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
10614 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10615 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10616 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
10617 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
10618 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10619 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10620 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10621 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10622 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10623 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10624 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10625 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10626 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10627 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10628 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10629 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10630 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10631 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
10632 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
10633 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10634 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10635 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10636 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10637 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10638 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10639 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10640 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
10641 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
10642 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
10643 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10644 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10645 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10646 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10647 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10648 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
10649 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10650 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10651 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10652 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
10653 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10654 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10655 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10656 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10657 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10658 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10659 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10660 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
10661 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10662 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10663 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10664 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10665 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10666 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10667 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
10668 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10669 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10670 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10671 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10672 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10673 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
10674 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10675 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10676 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10677 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10678 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10679 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10680 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10681 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10682 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10683 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10684 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10685 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10686 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10687 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10688 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10689 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10690 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10691 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10692 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10693 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10694 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10695 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
10696 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10697 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10698 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
10699 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10700 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10701 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10702 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10703 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10704 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10705 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10706 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10707 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10708 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10709 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10710 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10711 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10712 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10713 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10714 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10715 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10716 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
10717 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10718 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10719 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10720 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10721 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10722 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10723 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10724 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10725 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10726 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10727 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10728 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10729 /* Refer below for TGSI_OPCODE_DFMA */
10730 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
10731 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10732 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10733 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10734 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10735 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10736 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
10737 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10738 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
10739 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
10740 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10741 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10742 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10743 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10744 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10745 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10746 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
10747 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10748 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10749 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
10750 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10751 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
10752 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10753 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10754 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10755 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10756 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10757 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10758 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10759 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10760 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10761 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10762 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10763 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10764 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10765 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10766 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10767 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10768 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
10769 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10770 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10771 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10772 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
10773 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
10774 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10775 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10776 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10777 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10778 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
10779 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
10780 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
10781 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
10782 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
10783 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10784 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10785 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10786 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10787 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10788 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10789 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10790 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10791 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
10792 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
10793 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10794 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10795 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10796 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10797 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10798 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10799 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10800 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10801 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10802 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10803 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10804 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10805 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10806 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10807 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10808 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10809 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10810 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10811 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10812 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10813 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10814 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10815 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10816 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10817 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10818 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10819 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10820 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10821 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10822 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10823 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10824 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10825 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10826 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10827 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10828 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10829 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10830 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10831 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10832 };