2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
38 struct r600_shader_tgsi_instruction
;
40 struct r600_shader_ctx
{
41 struct tgsi_shader_info info
;
42 struct tgsi_parse_context parse
;
43 const struct tgsi_token
*tokens
;
45 unsigned file_offset
[TGSI_FILE_COUNT
];
47 struct r600_shader_tgsi_instruction
*inst_info
;
49 struct r600_shader
*shader
;
53 struct r600_shader_tgsi_instruction
{
57 int (*process
)(struct r600_shader_ctx
*ctx
);
60 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[];
61 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
63 static int r600_shader_update(struct pipe_context
*ctx
, struct r600_shader
*shader
)
65 struct r600_context
*rctx
= r600_context(ctx
);
66 const struct util_format_description
*desc
;
67 enum pipe_format resource_format
[160];
68 unsigned i
, nresources
= 0;
69 struct r600_bc
*bc
= &shader
->bc
;
70 struct r600_bc_cf
*cf
;
71 struct r600_bc_vtx
*vtx
;
73 if (shader
->processor_type
!= TGSI_PROCESSOR_VERTEX
)
75 for (i
= 0; i
< rctx
->vertex_elements
->count
; i
++) {
76 resource_format
[nresources
++] = rctx
->vertex_elements
->elements
[i
].src_format
;
78 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
80 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
81 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
82 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
83 desc
= util_format_description(resource_format
[vtx
->buffer_id
]);
85 R600_ERR("unknown format %d\n", resource_format
[vtx
->buffer_id
]);
88 vtx
->dst_sel_x
= desc
->swizzle
[0];
89 vtx
->dst_sel_y
= desc
->swizzle
[1];
90 vtx
->dst_sel_z
= desc
->swizzle
[2];
91 vtx
->dst_sel_w
= desc
->swizzle
[3];
98 return r600_bc_build(&shader
->bc
);
101 int r600_pipe_shader_create(struct pipe_context
*ctx
,
102 struct r600_context_state
*rpshader
,
103 const struct tgsi_token
*tokens
)
105 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
108 fprintf(stderr
, "--------------------------------------------------------------\n");
109 tgsi_dump(tokens
, 0);
110 if (rpshader
== NULL
)
112 rpshader
->shader
.family
= radeon_get_family(rscreen
->rw
);
113 r
= r600_shader_from_tgsi(tokens
, &rpshader
->shader
);
115 R600_ERR("translation from TGSI failed !\n");
118 r
= r600_bc_build(&rpshader
->shader
.bc
);
120 R600_ERR("building bytecode failed !\n");
123 fprintf(stderr
, "______________________________________________________________\n");
127 static int r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
129 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
130 struct r600_shader
*rshader
= &rpshader
->shader
;
131 struct radeon_state
*state
;
134 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
135 state
= radeon_state(rscreen
->rw
, R600_VS_SHADER_TYPE
, R600_VS_SHADER
);
138 for (i
= 0; i
< 10; i
++) {
139 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
] = 0;
141 /* so far never got proper semantic id from tgsi */
142 for (i
= 0; i
< 32; i
++) {
143 tmp
= i
<< ((i
& 3) * 8);
144 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
/ 4] |= tmp
;
146 state
->states
[R600_VS_SHADER__SPI_VS_OUT_CONFIG
] = S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2);
147 state
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
148 rpshader
->rstate
= state
;
149 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
150 rpshader
->rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
151 rpshader
->rstate
->nbo
= 2;
152 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
153 return radeon_state_pm4(state
);
156 static int r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
158 const struct pipe_rasterizer_state
*rasterizer
;
159 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
160 struct r600_shader
*rshader
= &rpshader
->shader
;
161 struct r600_context
*rctx
= r600_context(ctx
);
162 struct radeon_state
*state
;
163 unsigned i
, tmp
, exports_ps
, num_cout
;
165 rasterizer
= &rctx
->rasterizer
->state
.rasterizer
;
166 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
167 state
= radeon_state(rscreen
->rw
, R600_PS_SHADER_TYPE
, R600_PS_SHADER
);
170 for (i
= 0; i
< rshader
->ninput
; i
++) {
171 tmp
= S_028644_SEMANTIC(i
);
172 tmp
|= S_028644_SEL_CENTROID(1);
173 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
174 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
) {
175 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
177 if (rasterizer
->sprite_coord_enable
& (1 << i
)) {
178 tmp
|= S_028644_PT_SPRITE_TEX(1);
180 state
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
+ i
] = tmp
;
185 for (i
= 0; i
< rshader
->noutput
; i
++) {
186 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
188 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
189 exports_ps
|= (1 << (num_cout
+1));
193 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] = S_0286CC_NUM_INTERP(rshader
->ninput
) |
194 S_0286CC_PERSP_GRADIENT_ENA(1);
195 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_1
] = 0x00000000;
196 state
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
197 state
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = exports_ps
;
198 rpshader
->rstate
= state
;
199 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
200 rpshader
->rstate
->nbo
= 1;
201 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
202 return radeon_state_pm4(state
);
205 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
207 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
208 struct r600_context
*rctx
= r600_context(ctx
);
209 struct r600_shader
*rshader
= &rpshader
->shader
;
212 /* copy new shader */
213 radeon_bo_decref(rscreen
->rw
, rpshader
->bo
);
215 rpshader
->bo
= radeon_bo(rscreen
->rw
, 0, rshader
->bc
.ndw
* 4,
217 if (rpshader
->bo
== NULL
) {
220 radeon_bo_map(rscreen
->rw
, rpshader
->bo
);
221 memcpy(rpshader
->bo
->data
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
222 radeon_bo_unmap(rscreen
->rw
, rpshader
->bo
);
224 rshader
->flat_shade
= rctx
->flat_shade
;
225 switch (rshader
->processor_type
) {
226 case TGSI_PROCESSOR_VERTEX
:
227 r
= r600_pipe_shader_vs(ctx
, rpshader
);
229 case TGSI_PROCESSOR_FRAGMENT
:
230 r
= r600_pipe_shader_ps(ctx
, rpshader
);
239 int r600_pipe_shader_update(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
241 struct r600_context
*rctx
= r600_context(ctx
);
244 if (rpshader
== NULL
)
246 /* there should be enough input */
247 if (rctx
->vertex_elements
->count
< rpshader
->shader
.bc
.nresource
) {
248 R600_ERR("%d resources provided, expecting %d\n",
249 rctx
->vertex_elements
->count
, rpshader
->shader
.bc
.nresource
);
252 r
= r600_shader_update(ctx
, &rpshader
->shader
);
255 return r600_pipe_shader(ctx
, rpshader
);
258 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
260 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
263 if (i
->Instruction
.NumDstRegs
> 1) {
264 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
267 if (i
->Instruction
.Predicate
) {
268 R600_ERR("predicate unsupported\n");
271 if (i
->Instruction
.Label
) {
272 R600_ERR("label unsupported\n");
275 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
276 if (i
->Src
[j
].Register
.Indirect
||
277 i
->Src
[j
].Register
.Dimension
||
278 i
->Src
[j
].Register
.Absolute
) {
279 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
283 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
284 if (i
->Dst
[j
].Register
.Indirect
|| i
->Dst
[j
].Register
.Dimension
) {
285 R600_ERR("unsupported dst (indirect|dimension)\n");
292 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
294 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
295 struct r600_bc_vtx vtx
;
299 switch (d
->Declaration
.File
) {
300 case TGSI_FILE_INPUT
:
301 i
= ctx
->shader
->ninput
++;
302 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
303 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
304 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
305 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
306 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
307 /* turn input into fetch */
308 memset(&vtx
, 0, sizeof(struct r600_bc_vtx
));
312 /* register containing the index into the buffer */
315 vtx
.mega_fetch_count
= 0x1F;
316 vtx
.dst_gpr
= ctx
->shader
->input
[i
].gpr
;
321 r
= r600_bc_add_vtx(ctx
->bc
, &vtx
);
326 case TGSI_FILE_OUTPUT
:
327 i
= ctx
->shader
->noutput
++;
328 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
329 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
330 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
331 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
333 case TGSI_FILE_CONSTANT
:
334 case TGSI_FILE_TEMPORARY
:
335 case TGSI_FILE_SAMPLER
:
338 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
344 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
346 struct tgsi_full_immediate
*immediate
;
347 struct r600_shader_ctx ctx
;
348 struct r600_bc_output output
[32];
349 unsigned output_done
, noutput
;
353 ctx
.bc
= &shader
->bc
;
355 r
= r600_bc_init(ctx
.bc
, shader
->family
);
359 tgsi_scan_shader(tokens
, &ctx
.info
);
360 tgsi_parse_init(&ctx
.parse
, tokens
);
361 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
362 shader
->processor_type
= ctx
.type
;
364 /* register allocations */
365 /* Values [0,127] correspond to GPR[0..127].
366 * Values [256,511] correspond to cfile constants c[0..255].
367 * Other special values are shown in the list below.
368 * 248 SQ_ALU_SRC_0: special constant 0.0.
369 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
370 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
371 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
372 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
373 * 253 SQ_ALU_SRC_LITERAL: literal constant.
374 * 254 SQ_ALU_SRC_PV: previous vector result.
375 * 255 SQ_ALU_SRC_PS: previous scalar result.
377 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
378 ctx
.file_offset
[i
] = 0;
380 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
381 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
383 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
384 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
385 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
386 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
387 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 256;
388 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = 253;
389 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
390 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
392 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
393 tgsi_parse_token(&ctx
.parse
);
394 switch (ctx
.parse
.FullToken
.Token
.Type
) {
395 case TGSI_TOKEN_TYPE_IMMEDIATE
:
396 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
397 ctx
.value
[0] = immediate
->u
[0].Uint
;
398 ctx
.value
[1] = immediate
->u
[1].Uint
;
399 ctx
.value
[2] = immediate
->u
[2].Uint
;
400 ctx
.value
[3] = immediate
->u
[3].Uint
;
402 case TGSI_TOKEN_TYPE_DECLARATION
:
403 r
= tgsi_declaration(&ctx
);
407 case TGSI_TOKEN_TYPE_INSTRUCTION
:
408 r
= tgsi_is_supported(&ctx
);
411 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
412 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
413 r
= ctx
.inst_info
->process(&ctx
);
416 r
= r600_bc_add_literal(ctx
.bc
, ctx
.value
);
421 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
427 noutput
= shader
->noutput
;
428 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
429 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
430 output
[i
].gpr
= shader
->output
[i
].gpr
;
431 output
[i
].elem_size
= 3;
432 output
[i
].swizzle_x
= 0;
433 output
[i
].swizzle_y
= 1;
434 output
[i
].swizzle_z
= 2;
435 output
[i
].swizzle_w
= 3;
436 output
[i
].barrier
= 1;
437 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
438 output
[i
].array_base
= i
- pos0
;
439 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
441 case TGSI_PROCESSOR_VERTEX
:
442 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
443 output
[i
].array_base
= 60;
444 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
445 /* position doesn't count in array_base */
448 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
449 output
[i
].array_base
= 61;
450 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
451 /* position doesn't count in array_base */
455 case TGSI_PROCESSOR_FRAGMENT
:
456 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
457 output
[i
].array_base
= shader
->output
[i
].sid
;
458 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
459 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
460 output
[i
].array_base
= 61;
461 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
463 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
469 R600_ERR("unsupported processor type %d\n", ctx
.type
);
474 /* add fake param output for vertex shader if no param is exported */
475 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
476 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
477 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
483 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
485 output
[i
].elem_size
= 3;
486 output
[i
].swizzle_x
= 0;
487 output
[i
].swizzle_y
= 1;
488 output
[i
].swizzle_z
= 2;
489 output
[i
].swizzle_w
= 3;
490 output
[i
].barrier
= 1;
491 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
492 output
[i
].array_base
= 0;
493 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
497 /* add fake pixel export */
498 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
499 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
501 output
[0].elem_size
= 3;
502 output
[0].swizzle_x
= 7;
503 output
[0].swizzle_y
= 7;
504 output
[0].swizzle_z
= 7;
505 output
[0].swizzle_w
= 7;
506 output
[0].barrier
= 1;
507 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
508 output
[0].array_base
= 0;
509 output
[0].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT
;
512 /* set export done on last export of each type */
513 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
514 if (i
== (noutput
- 1)) {
515 output
[i
].end_of_program
= 1;
517 if (!(output_done
& (1 << output
[i
].type
))) {
518 output_done
|= (1 << output
[i
].type
);
519 output
[i
].inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
;
522 /* add output to bytecode */
523 for (i
= 0; i
< noutput
; i
++) {
524 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
528 tgsi_parse_free(&ctx
.parse
);
531 tgsi_parse_free(&ctx
.parse
);
535 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
537 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
541 static int tgsi_end(struct r600_shader_ctx
*ctx
)
546 static int tgsi_src(struct r600_shader_ctx
*ctx
,
547 const struct tgsi_full_src_register
*tgsi_src
,
548 struct r600_bc_alu_src
*r600_src
)
550 memset(r600_src
, 0, sizeof(struct r600_bc_alu_src
));
551 r600_src
->sel
= tgsi_src
->Register
.Index
;
552 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
555 r600_src
->neg
= tgsi_src
->Register
.Negate
;
556 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
560 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
561 const struct tgsi_full_dst_register
*tgsi_dst
,
563 struct r600_bc_alu_dst
*r600_dst
)
565 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
567 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
568 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
569 r600_dst
->chan
= swizzle
;
571 if (inst
->Instruction
.Saturate
) {
577 static unsigned tgsi_chan(const struct tgsi_full_src_register
*tgsi_src
, unsigned swizzle
)
581 return tgsi_src
->Register
.SwizzleX
;
583 return tgsi_src
->Register
.SwizzleY
;
585 return tgsi_src
->Register
.SwizzleZ
;
587 return tgsi_src
->Register
.SwizzleW
;
593 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
595 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
596 struct r600_bc_alu alu
;
597 int i
, j
, k
, nconst
, r
;
599 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
600 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
603 r
= tgsi_src(ctx
, &inst
->Src
[i
], &r600_src
[i
]);
608 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
609 if (inst
->Src
[j
].Register
.File
== TGSI_FILE_CONSTANT
&& j
> 0) {
610 for (k
= 0; k
< 4; k
++) {
611 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
612 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
613 alu
.src
[0].sel
= r600_src
[0].sel
;
615 alu
.dst
.sel
= ctx
->temp_reg
+ j
;
620 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
624 r600_src
[0].sel
= ctx
->temp_reg
+ j
;
631 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
633 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
634 struct r600_bc_alu_src r600_src
[3];
635 struct r600_bc_alu alu
;
638 r
= tgsi_split_constant(ctx
, r600_src
);
641 for (i
= 0; i
< 4; i
++) {
642 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
643 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
644 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
647 alu
.inst
= ctx
->inst_info
->r600_opcode
;
648 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
649 alu
.src
[j
] = r600_src
[j
];
650 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
652 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
656 /* handle some special cases */
657 switch (ctx
->inst_info
->tgsi_opcode
) {
658 case TGSI_OPCODE_SUB
:
661 case TGSI_OPCODE_ABS
:
670 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
678 * r600 - trunc to -PI..PI range
679 * r700 - normalize by dividing by 2PI
682 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
684 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
685 struct r600_bc_alu_src r600_src
[3];
686 struct r600_bc_alu alu
;
688 uint32_t lit_vals
[4];
690 memset(lit_vals
, 0, 4*4);
691 r
= tgsi_split_constant(ctx
, r600_src
);
694 lit_vals
[0] = fui(1.0 /(3.1415926535 * 2));
695 lit_vals
[1] = fui(0.5f
);
697 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
698 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
702 alu
.dst
.sel
= ctx
->temp_reg
;
705 alu
.src
[0] = r600_src
[0];
706 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
708 alu
.src
[1].sel
= SQ_ALU_SRC_LITERAL
;
710 alu
.src
[2].sel
= SQ_ALU_SRC_LITERAL
;
713 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
716 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
720 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
721 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
;
724 alu
.dst
.sel
= ctx
->temp_reg
;
727 alu
.src
[0].sel
= ctx
->temp_reg
;
730 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
734 if (ctx
->bc
->chiprev
== 0) {
735 lit_vals
[0] = fui(3.1415926535897f
* 2.0f
);
736 lit_vals
[1] = fui(-3.1415926535897f
);
738 lit_vals
[0] = fui(1.0f
);
739 lit_vals
[1] = fui(-0.5f
);
742 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
743 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
747 alu
.dst
.sel
= ctx
->temp_reg
;
750 alu
.src
[0].sel
= ctx
->temp_reg
;
753 alu
.src
[1].sel
= SQ_ALU_SRC_LITERAL
;
755 alu
.src
[2].sel
= SQ_ALU_SRC_LITERAL
;
758 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
761 r
= r600_bc_add_literal(ctx
->bc
, lit_vals
);
765 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
766 alu
.inst
= ctx
->inst_info
->r600_opcode
;
768 alu
.dst
.sel
= ctx
->temp_reg
;
771 alu
.src
[0].sel
= ctx
->temp_reg
;
774 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
778 /* replicate result */
779 for (i
= 0; i
< 4; i
++) {
780 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
781 alu
.src
[0].sel
= ctx
->temp_reg
;
782 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
784 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
787 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
790 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
797 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
799 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
800 struct r600_bc_alu alu
;
803 for (i
= 0; i
< 4; i
++) {
804 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
805 alu
.inst
= ctx
->inst_info
->r600_opcode
;
807 alu
.src
[0].sel
= SQ_ALU_SRC_0
;
808 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
811 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
815 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
822 static int tgsi_slt(struct r600_shader_ctx
*ctx
)
824 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
825 struct r600_bc_alu_src r600_src
[3];
826 struct r600_bc_alu alu
;
829 r
= tgsi_split_constant(ctx
, r600_src
);
832 for (i
= 0; i
< 4; i
++) {
833 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
834 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
835 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
838 alu
.inst
= ctx
->inst_info
->r600_opcode
;
839 alu
.src
[1] = r600_src
[0];
840 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
841 alu
.src
[0] = r600_src
[1];
842 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
843 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
850 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
857 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
859 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
860 struct r600_bc_alu alu
;
864 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
865 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
866 alu
.src
[0].sel
= SQ_ALU_SRC_1
; /*1.0*/
868 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
871 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
872 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
876 /* dst.y = max(src.x, 0.0) */
877 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
878 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
;
879 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
882 alu
.src
[1].sel
= SQ_ALU_SRC_0
; /*0.0*/
883 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 0);
884 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
887 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
888 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
892 /* dst.z = NOP - fill Z slot */
893 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
894 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
896 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
901 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
902 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
903 alu
.src
[0].sel
= SQ_ALU_SRC_1
;
905 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
908 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
910 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
914 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
919 /* dst.z = log(src.y) */
920 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
921 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
;
922 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
925 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
926 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
930 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
937 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
938 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
939 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
940 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
943 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
944 alu
.src
[1].sel
= sel
;
945 alu
.src
[1].chan
= chan
;
946 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[2]);
949 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], 0);
950 alu
.dst
.sel
= ctx
->temp_reg
;
955 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
959 /* dst.z = exp(tmp.x) */
960 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
961 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
962 alu
.src
[0].sel
= ctx
->temp_reg
;
964 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
968 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
975 static int tgsi_trans(struct r600_shader_ctx
*ctx
)
977 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
978 struct r600_bc_alu alu
;
981 for (i
= 0; i
< 4; i
++) {
982 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
983 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
984 alu
.inst
= ctx
->inst_info
->r600_opcode
;
985 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
986 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
989 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
991 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
995 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1003 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
1005 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1006 struct r600_bc_alu alu
;
1009 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1010 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1011 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1012 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
1015 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], 0);
1017 alu
.dst
.sel
= ctx
->temp_reg
;
1020 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1023 /* replicate result */
1024 for (i
= 0; i
< 4; i
++) {
1025 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1026 alu
.src
[0].sel
= ctx
->temp_reg
;
1027 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1029 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1032 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1035 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1042 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
1044 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1045 struct r600_bc_alu alu
;
1046 struct r600_bc_alu_src r600_src
[3];
1049 r
= tgsi_split_constant(ctx
, r600_src
);
1053 /* tmp = (src > 0 ? 1 : src) */
1054 for (i
= 0; i
< 4; i
++) {
1055 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1056 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
;
1058 alu
.dst
.sel
= ctx
->temp_reg
;
1061 alu
.src
[0] = r600_src
[0];
1062 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1064 alu
.src
[1].sel
= SQ_ALU_SRC_1
;
1066 alu
.src
[2] = r600_src
[0];
1067 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], i
);
1070 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1075 /* dst = (-tmp > 0 ? -1 : tmp) */
1076 for (i
= 0; i
< 4; i
++) {
1077 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1078 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
;
1080 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1084 alu
.src
[0].sel
= ctx
->temp_reg
;
1087 alu
.src
[1].sel
= SQ_ALU_SRC_1
;
1090 alu
.src
[2].sel
= ctx
->temp_reg
;
1095 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1102 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
1104 struct r600_bc_alu alu
;
1107 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1110 for (i
= 0; i
< 4; i
++) {
1111 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1112 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
1113 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
1116 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1117 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1120 alu
.src
[0].sel
= ctx
->temp_reg
;
1121 alu
.src
[0].chan
= i
;
1126 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1133 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
1135 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1136 struct r600_bc_alu_src r600_src
[3];
1137 struct r600_bc_alu alu
;
1140 r
= tgsi_split_constant(ctx
, r600_src
);
1143 /* do it in 2 step as op3 doesn't support writemask */
1144 for (i
= 0; i
< 4; i
++) {
1145 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1146 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1147 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1148 alu
.src
[j
] = r600_src
[j
];
1149 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1151 alu
.dst
.sel
= ctx
->temp_reg
;
1158 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1162 return tgsi_helper_copy(ctx
, inst
);
1165 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
1167 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1168 struct r600_bc_alu_src r600_src
[3];
1169 struct r600_bc_alu alu
;
1172 r
= tgsi_split_constant(ctx
, r600_src
);
1175 for (i
= 0; i
< 4; i
++) {
1176 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1177 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1178 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1179 alu
.src
[j
] = r600_src
[j
];
1180 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1182 alu
.dst
.sel
= ctx
->temp_reg
;
1185 /* handle some special cases */
1186 switch (ctx
->inst_info
->tgsi_opcode
) {
1187 case TGSI_OPCODE_DP2
:
1189 alu
.src
[0].sel
= alu
.src
[1].sel
= SQ_ALU_SRC_0
;
1190 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1193 case TGSI_OPCODE_DP3
:
1195 alu
.src
[0].sel
= alu
.src
[1].sel
= SQ_ALU_SRC_0
;
1196 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1205 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1209 return tgsi_helper_copy(ctx
, inst
);
1212 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1214 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1215 struct r600_bc_tex tex
;
1216 struct r600_bc_alu alu
;
1220 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1222 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1223 /* Add perspective divide */
1224 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1225 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
1226 alu
.src
[0].sel
= src_gpr
;
1227 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1228 alu
.dst
.sel
= ctx
->temp_reg
;
1232 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1236 for (i
= 0; i
< 3; i
++) {
1237 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1238 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1239 alu
.src
[0].sel
= ctx
->temp_reg
;
1240 alu
.src
[0].chan
= 3;
1241 alu
.src
[1].sel
= src_gpr
;
1242 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1243 alu
.dst
.sel
= ctx
->temp_reg
;
1246 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1250 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1251 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1252 alu
.src
[0].sel
= SQ_ALU_SRC_1
;
1253 alu
.src
[0].chan
= 0;
1254 alu
.dst
.sel
= ctx
->temp_reg
;
1258 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1261 src_gpr
= ctx
->temp_reg
;
1262 } else if (inst
->Src
[0].Register
.File
!= TGSI_FILE_TEMPORARY
) {
1263 for (i
= 0; i
< 4; i
++) {
1264 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1265 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1266 alu
.src
[0].sel
= src_gpr
;
1267 alu
.src
[0].chan
= i
;
1268 alu
.dst
.sel
= ctx
->temp_reg
;
1273 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1277 src_gpr
= ctx
->temp_reg
;
1280 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1281 tex
.inst
= ctx
->inst_info
->r600_opcode
;
1282 tex
.resource_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1283 tex
.sampler_id
= tex
.resource_id
;
1284 tex
.src_gpr
= src_gpr
;
1285 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1295 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1296 tex
.coord_type_x
= 1;
1297 tex
.coord_type_y
= 1;
1298 tex
.coord_type_z
= 1;
1299 tex
.coord_type_w
= 1;
1301 return r600_bc_add_tex(ctx
->bc
, &tex
);
1304 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1306 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1307 struct r600_bc_alu_src r600_src
[3];
1308 struct r600_bc_alu alu
;
1312 r
= tgsi_split_constant(ctx
, r600_src
);
1316 for (i
= 0; i
< 4; i
++) {
1317 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1318 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
;
1319 alu
.src
[0].sel
= SQ_ALU_SRC_1
;
1320 alu
.src
[0].chan
= 0;
1321 alu
.src
[1] = r600_src
[0];
1322 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1324 alu
.dst
.sel
= ctx
->temp_reg
;
1330 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1334 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1338 /* (1 - src0) * src2 */
1339 for (i
= 0; i
< 4; i
++) {
1340 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1341 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1342 alu
.src
[0].sel
= ctx
->temp_reg
;
1343 alu
.src
[0].chan
= i
;
1344 alu
.src
[1] = r600_src
[2];
1345 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1346 alu
.dst
.sel
= ctx
->temp_reg
;
1352 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1356 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1360 /* src0 * src1 + (1 - src0) * src2 */
1361 for (i
= 0; i
< 4; i
++) {
1362 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1363 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1365 alu
.src
[0] = r600_src
[0];
1366 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1367 alu
.src
[1] = r600_src
[1];
1368 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
1369 alu
.src
[2].sel
= ctx
->temp_reg
;
1370 alu
.src
[2].chan
= i
;
1371 alu
.dst
.sel
= ctx
->temp_reg
;
1376 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1380 return tgsi_helper_copy(ctx
, inst
);
1383 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
1384 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1385 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1386 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
1387 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
1388 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
1389 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1390 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1391 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
1392 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1393 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1394 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1395 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1396 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
1397 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
1398 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_slt
},
1399 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
1400 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
1401 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1402 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
1403 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1405 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1406 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1408 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1409 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1410 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
1411 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1412 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
1413 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1414 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
1415 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
1416 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1417 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1419 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1420 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1421 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1422 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1423 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
1424 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
1425 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
1426 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
}, /* predicated kill */
1427 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1428 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1429 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1430 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1431 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1432 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
1433 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1434 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
1435 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
1436 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_slt
},
1437 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
1438 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1439 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
1440 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1441 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
1442 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1443 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1444 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1445 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1446 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1447 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1448 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1449 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1450 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1451 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1452 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
1453 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1454 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1455 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
1456 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1457 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1458 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1459 {TGSI_OPCODE_TXL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1460 {TGSI_OPCODE_BRK
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1461 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1463 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1464 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1465 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1466 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1468 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1469 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1470 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1471 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1472 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1473 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1474 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1475 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
1476 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1478 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1479 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1480 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1481 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1482 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1483 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1484 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1485 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1486 {TGSI_OPCODE_CONT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1487 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1488 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1489 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1490 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1491 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1492 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1494 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1495 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1496 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1497 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1498 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1500 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1501 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1502 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1503 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1504 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1505 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1506 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1507 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1508 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
1509 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
1511 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1512 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1513 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1514 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1515 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1516 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1517 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1518 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1519 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1520 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1521 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1522 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1523 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1524 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1525 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1526 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1527 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1528 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1529 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1530 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1531 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1532 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1533 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1534 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1535 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1536 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1537 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1538 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},